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ac/nir: Add float cast before shadow comparator clamp.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct nir_to_llvm_context;
51
52 struct ac_nir_context {
53 struct ac_llvm_context ac;
54 struct ac_shader_abi *abi;
55
56 gl_shader_stage stage;
57
58 struct hash_table *defs;
59 struct hash_table *phis;
60 struct hash_table *vars;
61
62 LLVMValueRef main_function;
63 LLVMBasicBlockRef continue_block;
64 LLVMBasicBlockRef break_block;
65
66 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
67
68 int num_locals;
69 LLVMValueRef *locals;
70
71 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
72 };
73
74 struct nir_to_llvm_context {
75 struct ac_llvm_context ac;
76 const struct ac_nir_compiler_options *options;
77 struct ac_shader_variant_info *shader_info;
78 struct ac_shader_abi abi;
79 struct ac_nir_context *nir;
80
81 unsigned max_workgroup_size;
82 LLVMContextRef context;
83 LLVMModuleRef module;
84 LLVMBuilderRef builder;
85 LLVMValueRef main_function;
86
87 struct hash_table *defs;
88 struct hash_table *phis;
89
90 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
91 LLVMValueRef ring_offsets;
92 LLVMValueRef push_constants;
93 LLVMValueRef num_work_groups;
94 LLVMValueRef workgroup_ids;
95 LLVMValueRef local_invocation_ids;
96 LLVMValueRef tg_size;
97
98 LLVMValueRef vertex_buffers;
99 LLVMValueRef rel_auto_id;
100 LLVMValueRef vs_prim_id;
101 LLVMValueRef ls_out_layout;
102 LLVMValueRef es2gs_offset;
103
104 LLVMValueRef tcs_offchip_layout;
105 LLVMValueRef tcs_out_offsets;
106 LLVMValueRef tcs_out_layout;
107 LLVMValueRef tcs_in_layout;
108 LLVMValueRef oc_lds;
109 LLVMValueRef tess_factor_offset;
110 LLVMValueRef tcs_patch_id;
111 LLVMValueRef tcs_rel_ids;
112 LLVMValueRef tes_rel_patch_id;
113 LLVMValueRef tes_patch_id;
114 LLVMValueRef tes_u;
115 LLVMValueRef tes_v;
116
117 LLVMValueRef gsvs_ring_stride;
118 LLVMValueRef gsvs_num_entries;
119 LLVMValueRef gs2vs_offset;
120 LLVMValueRef gs_wave_id;
121 LLVMValueRef gs_vtx_offset[6];
122 LLVMValueRef gs_prim_id, gs_invocation_id;
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 LLVMTypeRef i1;
135 LLVMTypeRef i8;
136 LLVMTypeRef i16;
137 LLVMTypeRef i32;
138 LLVMTypeRef i64;
139 LLVMTypeRef v2i32;
140 LLVMTypeRef v3i32;
141 LLVMTypeRef v4i32;
142 LLVMTypeRef v8i32;
143 LLVMTypeRef f64;
144 LLVMTypeRef f32;
145 LLVMTypeRef f16;
146 LLVMTypeRef v2f32;
147 LLVMTypeRef v4f32;
148 LLVMTypeRef voidt;
149
150 LLVMValueRef i1true;
151 LLVMValueRef i1false;
152 LLVMValueRef i32zero;
153 LLVMValueRef i32one;
154 LLVMValueRef f32zero;
155 LLVMValueRef f32one;
156 LLVMValueRef v4f32empty;
157
158 unsigned uniform_md_kind;
159 LLVMValueRef empty_md;
160 gl_shader_stage stage;
161
162 LLVMValueRef lds;
163 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
164
165 uint64_t input_mask;
166 uint64_t output_mask;
167 uint8_t num_output_clips;
168 uint8_t num_output_culls;
169
170 bool is_gs_copy_shader;
171 LLVMValueRef gs_next_vertex;
172 unsigned gs_max_out_vertices;
173
174 unsigned tes_primitive_mode;
175 uint64_t tess_outputs_written;
176 uint64_t tess_patch_outputs_written;
177 };
178
179 static inline struct nir_to_llvm_context *
180 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
181 {
182 struct nir_to_llvm_context *ctx = NULL;
183 return container_of(abi, ctx, abi);
184 }
185
186 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
187 const nir_deref_var *deref,
188 enum ac_descriptor_type desc_type,
189 bool image, bool write);
190
191 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
192 {
193 return (index * 4) + chan;
194 }
195
196 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
197 {
198 /* handle patch indices separate */
199 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
200 return 0;
201 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
202 return 1;
203 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
204 return 2 + (slot - VARYING_SLOT_PATCH0);
205
206 if (slot == VARYING_SLOT_POS)
207 return 0;
208 if (slot == VARYING_SLOT_PSIZ)
209 return 1;
210 if (slot == VARYING_SLOT_CLIP_DIST0)
211 return 2;
212 /* 3 is reserved for clip dist as well */
213 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
214 return 4 + (slot - VARYING_SLOT_VAR0);
215 unreachable("illegal slot in get unique index\n");
216 }
217
218 static unsigned llvm_get_type_size(LLVMTypeRef type)
219 {
220 LLVMTypeKind kind = LLVMGetTypeKind(type);
221
222 switch (kind) {
223 case LLVMIntegerTypeKind:
224 return LLVMGetIntTypeWidth(type) / 8;
225 case LLVMFloatTypeKind:
226 return 4;
227 case LLVMPointerTypeKind:
228 return 8;
229 case LLVMVectorTypeKind:
230 return LLVMGetVectorSize(type) *
231 llvm_get_type_size(LLVMGetElementType(type));
232 default:
233 assert(0);
234 return 0;
235 }
236 }
237
238 static void set_llvm_calling_convention(LLVMValueRef func,
239 gl_shader_stage stage)
240 {
241 enum radeon_llvm_calling_convention calling_conv;
242
243 switch (stage) {
244 case MESA_SHADER_VERTEX:
245 case MESA_SHADER_TESS_CTRL:
246 case MESA_SHADER_TESS_EVAL:
247 calling_conv = RADEON_LLVM_AMDGPU_VS;
248 break;
249 case MESA_SHADER_GEOMETRY:
250 calling_conv = RADEON_LLVM_AMDGPU_GS;
251 break;
252 case MESA_SHADER_FRAGMENT:
253 calling_conv = RADEON_LLVM_AMDGPU_PS;
254 break;
255 case MESA_SHADER_COMPUTE:
256 calling_conv = RADEON_LLVM_AMDGPU_CS;
257 break;
258 default:
259 unreachable("Unhandle shader type");
260 }
261
262 LLVMSetFunctionCallConv(func, calling_conv);
263 }
264
265 #define MAX_ARGS 23
266 struct arg_info {
267 LLVMTypeRef types[MAX_ARGS];
268 LLVMValueRef *assign[MAX_ARGS];
269 unsigned array_params_mask;
270 uint8_t count;
271 uint8_t user_sgpr_count;
272 uint8_t sgpr_count;
273 uint8_t num_user_sgprs_used;
274 uint8_t num_sgprs_used;
275 uint8_t num_vgprs_used;
276 };
277
278 static inline void
279 add_argument(struct arg_info *info,
280 LLVMTypeRef type, LLVMValueRef *param_ptr)
281 {
282 assert(info->count < MAX_ARGS);
283 info->assign[info->count] = param_ptr;
284 info->types[info->count] = type;
285 info->count++;
286 }
287
288 static inline void
289 add_sgpr_argument(struct arg_info *info,
290 LLVMTypeRef type, LLVMValueRef *param_ptr)
291 {
292 add_argument(info, type, param_ptr);
293 info->num_sgprs_used += llvm_get_type_size(type) / 4;
294 info->sgpr_count++;
295 }
296
297 static inline void
298 add_user_sgpr_argument(struct arg_info *info,
299 LLVMTypeRef type,
300 LLVMValueRef *param_ptr)
301 {
302 add_sgpr_argument(info, type, param_ptr);
303 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
304 info->user_sgpr_count++;
305 }
306
307 static inline void
308 add_vgpr_argument(struct arg_info *info,
309 LLVMTypeRef type,
310 LLVMValueRef *param_ptr)
311 {
312 add_argument(info, type, param_ptr);
313 info->num_vgprs_used += llvm_get_type_size(type) / 4;
314 }
315
316 static inline void
317 add_user_sgpr_array_argument(struct arg_info *info,
318 LLVMTypeRef type,
319 LLVMValueRef *param_ptr)
320 {
321 info->array_params_mask |= (1 << info->count);
322 add_user_sgpr_argument(info, type, param_ptr);
323 }
324
325 static void assign_arguments(LLVMValueRef main_function,
326 struct arg_info *info)
327 {
328 unsigned i;
329 for (i = 0; i < info->count; i++) {
330 if (info->assign[i])
331 *info->assign[i] = LLVMGetParam(main_function, i);
332 }
333 }
334
335 static LLVMValueRef
336 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
337 LLVMBuilderRef builder, LLVMTypeRef *return_types,
338 unsigned num_return_elems,
339 struct arg_info *args,
340 unsigned max_workgroup_size,
341 bool unsafe_math)
342 {
343 LLVMTypeRef main_function_type, ret_type;
344 LLVMBasicBlockRef main_function_body;
345
346 if (num_return_elems)
347 ret_type = LLVMStructTypeInContext(ctx, return_types,
348 num_return_elems, true);
349 else
350 ret_type = LLVMVoidTypeInContext(ctx);
351
352 /* Setup the function */
353 main_function_type =
354 LLVMFunctionType(ret_type, args->types, args->count, 0);
355 LLVMValueRef main_function =
356 LLVMAddFunction(module, "main", main_function_type);
357 main_function_body =
358 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
359 LLVMPositionBuilderAtEnd(builder, main_function_body);
360
361 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
362 for (unsigned i = 0; i < args->sgpr_count; ++i) {
363 if (args->array_params_mask & (1 << i)) {
364 LLVMValueRef P = LLVMGetParam(main_function, i);
365 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
366 ac_add_attr_dereferenceable(P, UINT64_MAX);
367 }
368 else {
369 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
370 }
371 }
372
373 if (max_workgroup_size) {
374 ac_llvm_add_target_dep_function_attr(main_function,
375 "amdgpu-max-work-group-size",
376 max_workgroup_size);
377 }
378 if (unsafe_math) {
379 /* These were copied from some LLVM test. */
380 LLVMAddTargetDependentFunctionAttr(main_function,
381 "less-precise-fpmad",
382 "true");
383 LLVMAddTargetDependentFunctionAttr(main_function,
384 "no-infs-fp-math",
385 "true");
386 LLVMAddTargetDependentFunctionAttr(main_function,
387 "no-nans-fp-math",
388 "true");
389 LLVMAddTargetDependentFunctionAttr(main_function,
390 "unsafe-fp-math",
391 "true");
392 }
393 return main_function;
394 }
395
396 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
397 {
398 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
399 CONST_ADDR_SPACE);
400 }
401
402 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
403 {
404 if (t == ctx->f16 || t == ctx->i16)
405 return ctx->i16;
406 else if (t == ctx->f32 || t == ctx->i32)
407 return ctx->i32;
408 else if (t == ctx->f64 || t == ctx->i64)
409 return ctx->i64;
410 else
411 unreachable("Unhandled integer size");
412 }
413
414 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
415 {
416 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
417 LLVMTypeRef elem_type = LLVMGetElementType(t);
418 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
419 LLVMGetVectorSize(t));
420 }
421 return to_integer_type_scalar(ctx, t);
422 }
423
424 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
425 {
426 LLVMTypeRef type = LLVMTypeOf(v);
427 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
428 }
429
430 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
431 {
432 if (t == ctx->i16 || t == ctx->f16)
433 return ctx->f16;
434 else if (t == ctx->i32 || t == ctx->f32)
435 return ctx->f32;
436 else if (t == ctx->i64 || t == ctx->f64)
437 return ctx->f64;
438 else
439 unreachable("Unhandled float size");
440 }
441
442 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
443 {
444 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
445 LLVMTypeRef elem_type = LLVMGetElementType(t);
446 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
447 LLVMGetVectorSize(t));
448 }
449 return to_float_type_scalar(ctx, t);
450 }
451
452 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
453 {
454 LLVMTypeRef type = LLVMTypeOf(v);
455 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
456 }
457
458 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
459 {
460 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
461 type = LLVMGetElementType(type);
462
463 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
464 return LLVMGetIntTypeWidth(type);
465
466 if (type == ctx->f16)
467 return 16;
468 if (type == ctx->f32)
469 return 32;
470 if (type == ctx->f64)
471 return 64;
472
473 unreachable("Unhandled type kind in get_elem_bits");
474 }
475
476 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
477 LLVMValueRef param, unsigned rshift,
478 unsigned bitwidth)
479 {
480 LLVMValueRef value = param;
481 if (rshift)
482 value = LLVMBuildLShr(ctx->builder, value,
483 LLVMConstInt(ctx->i32, rshift, false), "");
484
485 if (rshift + bitwidth < 32) {
486 unsigned mask = (1 << bitwidth) - 1;
487 value = LLVMBuildAnd(ctx->builder, value,
488 LLVMConstInt(ctx->i32, mask, false), "");
489 }
490 return value;
491 }
492
493 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
494 {
495 switch (ctx->stage) {
496 case MESA_SHADER_TESS_CTRL:
497 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
498 case MESA_SHADER_TESS_EVAL:
499 return ctx->tes_rel_patch_id;
500 break;
501 default:
502 unreachable("Illegal stage");
503 }
504 }
505
506 /* Tessellation shaders pass outputs to the next shader using LDS.
507 *
508 * LS outputs = TCS inputs
509 * TCS outputs = TES inputs
510 *
511 * The LDS layout is:
512 * - TCS inputs for patch 0
513 * - TCS inputs for patch 1
514 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
515 * - ...
516 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
517 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
518 * - TCS outputs for patch 1
519 * - Per-patch TCS outputs for patch 1
520 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
521 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
522 * - ...
523 *
524 * All three shaders VS(LS), TCS, TES share the same LDS space.
525 */
526 static LLVMValueRef
527 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
528 {
529 if (ctx->stage == MESA_SHADER_VERTEX)
530 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
531 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
532 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
533 else {
534 assert(0);
535 return NULL;
536 }
537 }
538
539 static LLVMValueRef
540 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
541 {
542 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
543 }
544
545 static LLVMValueRef
546 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
547 {
548 return LLVMBuildMul(ctx->builder,
549 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
550 LLVMConstInt(ctx->i32, 4, false), "");
551 }
552
553 static LLVMValueRef
554 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
555 {
556 return LLVMBuildMul(ctx->builder,
557 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
558 LLVMConstInt(ctx->i32, 4, false), "");
559 }
560
561 static LLVMValueRef
562 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
563 {
564 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
565 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
566
567 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
568 }
569
570 static LLVMValueRef
571 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
572 {
573 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
574 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
575 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
576
577 return LLVMBuildAdd(ctx->builder, patch0_offset,
578 LLVMBuildMul(ctx->builder, patch_stride,
579 rel_patch_id, ""),
580 "");
581 }
582
583 static LLVMValueRef
584 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
585 {
586 LLVMValueRef patch0_patch_data_offset =
587 get_tcs_out_patch0_patch_data_offset(ctx);
588 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
589 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
590
591 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
592 LLVMBuildMul(ctx->builder, patch_stride,
593 rel_patch_id, ""),
594 "");
595 }
596
597 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
598 {
599 ud_info->sgpr_idx = *sgpr_idx;
600 ud_info->num_sgprs = num_sgprs;
601 ud_info->indirect = false;
602 ud_info->indirect_offset = 0;
603 *sgpr_idx += num_sgprs;
604 }
605
606 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
607 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
608 {
609 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
610 }
611
612
613 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
614 uint32_t indirect_offset)
615 {
616 ud_info->sgpr_idx = sgpr_idx;
617 ud_info->num_sgprs = num_sgprs;
618 ud_info->indirect = true;
619 ud_info->indirect_offset = indirect_offset;
620 }
621
622 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
623 {
624 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
625 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
626 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
627 "tess_lds");
628 }
629
630 struct user_sgpr_info {
631 bool need_ring_offsets;
632 uint8_t sgpr_count;
633 bool indirect_all_descriptor_sets;
634 };
635
636 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
637 struct user_sgpr_info *user_sgpr_info)
638 {
639 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
640
641 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
642 if (ctx->stage == MESA_SHADER_GEOMETRY ||
643 ctx->stage == MESA_SHADER_VERTEX ||
644 ctx->stage == MESA_SHADER_TESS_CTRL ||
645 ctx->stage == MESA_SHADER_TESS_EVAL ||
646 ctx->is_gs_copy_shader)
647 user_sgpr_info->need_ring_offsets = true;
648
649 if (ctx->stage == MESA_SHADER_FRAGMENT &&
650 ctx->shader_info->info.ps.needs_sample_positions)
651 user_sgpr_info->need_ring_offsets = true;
652
653 /* 2 user sgprs will nearly always be allocated for scratch/rings */
654 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
655 user_sgpr_info->sgpr_count += 2;
656 }
657
658 switch (ctx->stage) {
659 case MESA_SHADER_COMPUTE:
660 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
661 break;
662 case MESA_SHADER_FRAGMENT:
663 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
664 break;
665 case MESA_SHADER_VERTEX:
666 if (!ctx->is_gs_copy_shader) {
667 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
668 if (ctx->shader_info->info.vs.needs_draw_id) {
669 user_sgpr_info->sgpr_count += 3;
670 } else {
671 user_sgpr_info->sgpr_count += 2;
672 }
673 }
674 if (ctx->options->key.vs.as_ls)
675 user_sgpr_info->sgpr_count++;
676 break;
677 case MESA_SHADER_TESS_CTRL:
678 user_sgpr_info->sgpr_count += 4;
679 break;
680 case MESA_SHADER_TESS_EVAL:
681 user_sgpr_info->sgpr_count += 1;
682 break;
683 case MESA_SHADER_GEOMETRY:
684 user_sgpr_info->sgpr_count += 2;
685 break;
686 default:
687 break;
688 }
689
690 if (ctx->shader_info->info.needs_push_constants)
691 user_sgpr_info->sgpr_count += 2;
692
693 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
694 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
695 user_sgpr_info->sgpr_count += 2;
696 user_sgpr_info->indirect_all_descriptor_sets = true;
697 } else {
698 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
699 }
700 }
701
702 static void create_function(struct nir_to_llvm_context *ctx)
703 {
704 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
705 uint8_t user_sgpr_idx;
706 struct user_sgpr_info user_sgpr_info;
707 struct arg_info args = {};
708 LLVMValueRef desc_sets;
709
710 allocate_user_sgprs(ctx, &user_sgpr_info);
711 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
712 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
713 }
714
715 /* 1 for each descriptor set */
716 if (!user_sgpr_info.indirect_all_descriptor_sets) {
717 for (unsigned i = 0; i < num_sets; ++i) {
718 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
719 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
720 }
721 }
722 } else
723 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
724
725 if (ctx->shader_info->info.needs_push_constants) {
726 /* 1 for push constants and dynamic descriptors */
727 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
728 }
729
730 switch (ctx->stage) {
731 case MESA_SHADER_COMPUTE:
732 if (ctx->shader_info->info.cs.grid_components_used)
733 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
734 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
735 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
736 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
737 break;
738 case MESA_SHADER_VERTEX:
739 if (!ctx->is_gs_copy_shader) {
740 if (ctx->shader_info->info.vs.has_vertex_buffers)
741 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
742 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
743 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
744 if (ctx->shader_info->info.vs.needs_draw_id)
745 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
746 }
747 if (ctx->options->key.vs.as_es)
748 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
749 else if (ctx->options->key.vs.as_ls)
750 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
751 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
752 if (!ctx->is_gs_copy_shader) {
753 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
754 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
755 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
756 }
757 break;
758 case MESA_SHADER_TESS_CTRL:
759 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
760 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
761 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
762 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
763 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
764 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
765 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
766 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
767 break;
768 case MESA_SHADER_TESS_EVAL:
769 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
770 if (ctx->options->key.tes.as_es) {
771 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
772 add_sgpr_argument(&args, ctx->i32, NULL); //
773 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
774 } else {
775 add_sgpr_argument(&args, ctx->i32, NULL); //
776 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
777 }
778 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
779 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
780 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
781 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
782 break;
783 case MESA_SHADER_GEOMETRY:
784 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
785 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
786 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
787 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
788 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
789 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
790 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
791 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
792 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
793 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
796 break;
797 case MESA_SHADER_FRAGMENT:
798 if (ctx->shader_info->info.ps.needs_sample_positions)
799 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
800 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
801 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
802 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
803 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
804 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
805 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
806 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
807 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
808 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
809 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */
810 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */
811 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */
812 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */
813 add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /* front face */
814 add_vgpr_argument(&args, ctx->i32, &ctx->abi.ancillary); /* ancillary */
815 add_vgpr_argument(&args, ctx->i32, &ctx->abi.sample_coverage); /* sample coverage */
816 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
817 break;
818 default:
819 unreachable("Shader stage not implemented");
820 }
821
822 ctx->main_function = create_llvm_function(
823 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
824 ctx->max_workgroup_size,
825 ctx->options->unsafe_math);
826 set_llvm_calling_convention(ctx->main_function, ctx->stage);
827
828
829 ctx->shader_info->num_input_vgprs = 0;
830 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
831 ctx->options->supports_spill ? 2 : 0;
832
833 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
834 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
835
836 if (ctx->stage != MESA_SHADER_FRAGMENT)
837 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
838
839 assign_arguments(ctx->main_function, &args);
840
841 user_sgpr_idx = 0;
842
843 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
844 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
845 if (ctx->options->supports_spill) {
846 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
847 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
848 NULL, 0, AC_FUNC_ATTR_READNONE);
849 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
850 const_array(ctx->v4i32, 16), "");
851 }
852 }
853
854 if (!user_sgpr_info.indirect_all_descriptor_sets) {
855 for (unsigned i = 0; i < num_sets; ++i) {
856 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
857 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
858 } else
859 ctx->descriptor_sets[i] = NULL;
860 }
861 } else {
862 uint32_t desc_sgpr_idx = user_sgpr_idx;
863 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
864
865 for (unsigned i = 0; i < num_sets; ++i) {
866 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
867 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
868 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
869
870 } else
871 ctx->descriptor_sets[i] = NULL;
872 }
873 ctx->shader_info->need_indirect_descriptor_sets = true;
874 }
875
876 if (ctx->shader_info->info.needs_push_constants) {
877 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
878 }
879
880 switch (ctx->stage) {
881 case MESA_SHADER_COMPUTE:
882 if (ctx->shader_info->info.cs.grid_components_used) {
883 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
884 }
885 break;
886 case MESA_SHADER_VERTEX:
887 if (!ctx->is_gs_copy_shader) {
888 if (ctx->shader_info->info.vs.has_vertex_buffers) {
889 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
890 }
891 unsigned vs_num = 2;
892 if (ctx->shader_info->info.vs.needs_draw_id)
893 vs_num++;
894
895 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
896 }
897 if (ctx->options->key.vs.as_ls) {
898 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
899 }
900 if (ctx->options->key.vs.as_ls)
901 declare_tess_lds(ctx);
902 break;
903 case MESA_SHADER_TESS_CTRL:
904 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
905 declare_tess_lds(ctx);
906 break;
907 case MESA_SHADER_TESS_EVAL:
908 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
909 break;
910 case MESA_SHADER_GEOMETRY:
911 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
912 break;
913 case MESA_SHADER_FRAGMENT:
914 if (ctx->shader_info->info.ps.needs_sample_positions) {
915 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
916 }
917 break;
918 default:
919 unreachable("Shader stage not implemented");
920 }
921 }
922
923 static void setup_types(struct nir_to_llvm_context *ctx)
924 {
925 LLVMValueRef args[4];
926
927 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
928 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
929 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
930 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
931 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
932 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
933 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
934 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
935 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
936 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
937 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
938 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
939 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
940 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
941 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
942
943 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
944 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
945 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
946 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
947 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
948 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
949
950 args[0] = ctx->f32zero;
951 args[1] = ctx->f32zero;
952 args[2] = ctx->f32zero;
953 args[3] = ctx->f32one;
954 ctx->v4f32empty = LLVMConstVector(args, 4);
955
956 ctx->uniform_md_kind =
957 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
958 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
959
960 args[0] = LLVMConstReal(ctx->f32, 2.5);
961 }
962
963 static int get_llvm_num_components(LLVMValueRef value)
964 {
965 LLVMTypeRef type = LLVMTypeOf(value);
966 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
967 ? LLVMGetVectorSize(type)
968 : 1;
969 return num_components;
970 }
971
972 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
973 LLVMValueRef value,
974 int index)
975 {
976 int count = get_llvm_num_components(value);
977
978 assert(index < count);
979 if (count == 1)
980 return value;
981
982 return LLVMBuildExtractElement(ac->builder, value,
983 LLVMConstInt(ac->i32, index, false), "");
984 }
985
986 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
987 LLVMValueRef value, unsigned count)
988 {
989 unsigned num_components = get_llvm_num_components(value);
990 if (count == num_components)
991 return value;
992
993 LLVMValueRef masks[] = {
994 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
995 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
996
997 if (count == 1)
998 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
999 "");
1000
1001 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1002 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1003 }
1004
1005 static void
1006 build_store_values_extended(struct ac_llvm_context *ac,
1007 LLVMValueRef *values,
1008 unsigned value_count,
1009 unsigned value_stride,
1010 LLVMValueRef vec)
1011 {
1012 LLVMBuilderRef builder = ac->builder;
1013 unsigned i;
1014
1015 for (i = 0; i < value_count; i++) {
1016 LLVMValueRef ptr = values[i * value_stride];
1017 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1018 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1019 LLVMBuildStore(builder, value, ptr);
1020 }
1021 }
1022
1023 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1024 const nir_ssa_def *def)
1025 {
1026 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1027 if (def->num_components > 1) {
1028 type = LLVMVectorType(type, def->num_components);
1029 }
1030 return type;
1031 }
1032
1033 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1034 {
1035 assert(src.is_ssa);
1036 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1037 return (LLVMValueRef)entry->data;
1038 }
1039
1040
1041 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1042 const struct nir_block *b)
1043 {
1044 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1045 return (LLVMBasicBlockRef)entry->data;
1046 }
1047
1048 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1049 nir_alu_src src,
1050 unsigned num_components)
1051 {
1052 LLVMValueRef value = get_src(ctx, src.src);
1053 bool need_swizzle = false;
1054
1055 assert(value);
1056 LLVMTypeRef type = LLVMTypeOf(value);
1057 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1058 ? LLVMGetVectorSize(type)
1059 : 1;
1060
1061 for (unsigned i = 0; i < num_components; ++i) {
1062 assert(src.swizzle[i] < src_components);
1063 if (src.swizzle[i] != i)
1064 need_swizzle = true;
1065 }
1066
1067 if (need_swizzle || num_components != src_components) {
1068 LLVMValueRef masks[] = {
1069 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1070 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1071 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1072 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1073
1074 if (src_components > 1 && num_components == 1) {
1075 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1076 masks[0], "");
1077 } else if (src_components == 1 && num_components > 1) {
1078 LLVMValueRef values[] = {value, value, value, value};
1079 value = ac_build_gather_values(&ctx->ac, values, num_components);
1080 } else {
1081 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1082 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1083 swizzle, "");
1084 }
1085 }
1086 assert(!src.negate);
1087 assert(!src.abs);
1088 return value;
1089 }
1090
1091 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1092 LLVMIntPredicate pred, LLVMValueRef src0,
1093 LLVMValueRef src1)
1094 {
1095 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1096 return LLVMBuildSelect(ctx->builder, result,
1097 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1098 LLVMConstInt(ctx->i32, 0, false), "");
1099 }
1100
1101 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1102 LLVMRealPredicate pred, LLVMValueRef src0,
1103 LLVMValueRef src1)
1104 {
1105 LLVMValueRef result;
1106 src0 = to_float(ctx, src0);
1107 src1 = to_float(ctx, src1);
1108 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1109 return LLVMBuildSelect(ctx->builder, result,
1110 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1111 LLVMConstInt(ctx->i32, 0, false), "");
1112 }
1113
1114 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1115 const char *intrin,
1116 LLVMTypeRef result_type,
1117 LLVMValueRef src0)
1118 {
1119 char name[64];
1120 LLVMValueRef params[] = {
1121 to_float(ctx, src0),
1122 };
1123
1124 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1125 get_elem_bits(ctx, result_type));
1126 assert(length < sizeof(name));
1127 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1128 }
1129
1130 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1131 const char *intrin,
1132 LLVMTypeRef result_type,
1133 LLVMValueRef src0, LLVMValueRef src1)
1134 {
1135 char name[64];
1136 LLVMValueRef params[] = {
1137 to_float(ctx, src0),
1138 to_float(ctx, src1),
1139 };
1140
1141 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1142 get_elem_bits(ctx, result_type));
1143 assert(length < sizeof(name));
1144 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1145 }
1146
1147 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1148 const char *intrin,
1149 LLVMTypeRef result_type,
1150 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1151 {
1152 char name[64];
1153 LLVMValueRef params[] = {
1154 to_float(ctx, src0),
1155 to_float(ctx, src1),
1156 to_float(ctx, src2),
1157 };
1158
1159 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1160 get_elem_bits(ctx, result_type));
1161 assert(length < sizeof(name));
1162 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1163 }
1164
1165 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1166 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1167 {
1168 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1169 ctx->i32_0, "");
1170 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1171 }
1172
1173 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1174 LLVMValueRef src0)
1175 {
1176 LLVMValueRef params[2] = {
1177 src0,
1178
1179 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1180 * add special code to check for x=0. The reason is that
1181 * the LLVM behavior for x=0 is different from what we
1182 * need here.
1183 *
1184 * The hardware already implements the correct behavior.
1185 */
1186 LLVMConstInt(ctx->i1, 1, false),
1187 };
1188
1189 LLVMValueRef lsb = ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32,
1190 params, 2,
1191 AC_FUNC_ATTR_READNONE);
1192
1193 /* TODO: We need an intrinsic to skip this conditional. */
1194 /* Check for zero: */
1195 return LLVMBuildSelect(ctx->builder, LLVMBuildICmp(ctx->builder,
1196 LLVMIntEQ, src0,
1197 ctx->i32_0, ""),
1198 LLVMConstInt(ctx->i32, -1, 0), lsb, "");
1199 }
1200
1201 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1202 LLVMValueRef src0)
1203 {
1204 return ac_build_imsb(ctx, src0, ctx->i32);
1205 }
1206
1207 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1208 LLVMValueRef src0)
1209 {
1210 return ac_build_umsb(ctx, src0, ctx->i32);
1211 }
1212
1213 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1214 LLVMIntPredicate pred,
1215 LLVMValueRef src0, LLVMValueRef src1)
1216 {
1217 return LLVMBuildSelect(ctx->builder,
1218 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1219 src0,
1220 src1, "");
1221
1222 }
1223 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1224 LLVMValueRef src0)
1225 {
1226 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1227 LLVMBuildNeg(ctx->builder, src0, ""));
1228 }
1229
1230 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1231 LLVMValueRef src0)
1232 {
1233 LLVMValueRef cmp, val;
1234
1235 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1236 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1237 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1238 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1239 return val;
1240 }
1241
1242 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1243 LLVMValueRef src0)
1244 {
1245 LLVMValueRef cmp, val;
1246
1247 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1248 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1249 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1250 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1251 return val;
1252 }
1253
1254 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1255 LLVMValueRef src0)
1256 {
1257 const char *intr = "llvm.floor.f32";
1258 LLVMValueRef fsrc0 = to_float(ctx, src0);
1259 LLVMValueRef params[] = {
1260 fsrc0,
1261 };
1262 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1263 ctx->f32, params, 1,
1264 AC_FUNC_ATTR_READNONE);
1265 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1266 }
1267
1268 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1269 const char *intrin,
1270 LLVMValueRef src0, LLVMValueRef src1)
1271 {
1272 LLVMTypeRef ret_type;
1273 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1274 LLVMValueRef res;
1275 LLVMValueRef params[] = { src0, src1 };
1276 ret_type = LLVMStructTypeInContext(ctx->context, types,
1277 2, true);
1278
1279 res = ac_build_intrinsic(ctx, intrin, ret_type,
1280 params, 2, AC_FUNC_ATTR_READNONE);
1281
1282 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1283 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1284 return res;
1285 }
1286
1287 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1288 LLVMValueRef src0)
1289 {
1290 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1291 }
1292
1293 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1294 LLVMValueRef src0)
1295 {
1296 src0 = to_float(ctx, src0);
1297 return LLVMBuildSExt(ctx->builder,
1298 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1299 ctx->i32, "");
1300 }
1301
1302 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1303 LLVMValueRef src0)
1304 {
1305 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1306 }
1307
1308 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1309 LLVMValueRef src0)
1310 {
1311 return LLVMBuildSExt(ctx->builder,
1312 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1313 ctx->i32, "");
1314 }
1315
1316 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1317 LLVMValueRef src0)
1318 {
1319 LLVMValueRef result;
1320 LLVMValueRef cond;
1321
1322 src0 = to_float(&ctx->ac, src0);
1323 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1324
1325 /* TODO SI/CIK options here */
1326 if (ctx->options->chip_class >= VI) {
1327 LLVMValueRef args[2];
1328 /* Check if the result is a denormal - and flush to 0 if so. */
1329 args[0] = result;
1330 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1331 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1332 }
1333
1334 /* need to convert back up to f32 */
1335 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1336
1337 if (ctx->options->chip_class >= VI)
1338 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1339
1340 return result;
1341 }
1342
1343 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1344 LLVMValueRef src0, LLVMValueRef src1)
1345 {
1346 LLVMValueRef dst64, result;
1347 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1348 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1349
1350 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1351 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1352 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1353 return result;
1354 }
1355
1356 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0, LLVMValueRef src1)
1358 {
1359 LLVMValueRef dst64, result;
1360 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1361 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1362
1363 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1364 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1365 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1366 return result;
1367 }
1368
1369 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1370 bool is_signed,
1371 const LLVMValueRef srcs[3])
1372 {
1373 LLVMValueRef result;
1374 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1375
1376 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1377 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1378 return result;
1379 }
1380
1381 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1382 LLVMValueRef src0, LLVMValueRef src1,
1383 LLVMValueRef src2, LLVMValueRef src3)
1384 {
1385 LLVMValueRef bfi_args[3], result;
1386
1387 bfi_args[0] = LLVMBuildShl(ctx->builder,
1388 LLVMBuildSub(ctx->builder,
1389 LLVMBuildShl(ctx->builder,
1390 ctx->i32_1,
1391 src3, ""),
1392 ctx->i32_1, ""),
1393 src2, "");
1394 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1395 bfi_args[2] = src0;
1396
1397 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1398
1399 /* Calculate:
1400 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1401 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1402 */
1403 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1404 LLVMBuildAnd(ctx->builder, bfi_args[0],
1405 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1406
1407 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1408 return result;
1409 }
1410
1411 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1412 LLVMValueRef src0)
1413 {
1414 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1415 int i;
1416 LLVMValueRef comp[2];
1417
1418 src0 = to_float(ctx, src0);
1419 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1420 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1421 for (i = 0; i < 2; i++) {
1422 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1423 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1424 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1425 }
1426
1427 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1428 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1429
1430 return comp[0];
1431 }
1432
1433 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1434 LLVMValueRef src0)
1435 {
1436 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1437 LLVMValueRef temps[2], result, val;
1438 int i;
1439
1440 for (i = 0; i < 2; i++) {
1441 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1442 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1443 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1444 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1445 }
1446
1447 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1448 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1449 ctx->i32_0, "");
1450 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1451 ctx->i32_1, "");
1452 return result;
1453 }
1454
1455 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1456 nir_op op,
1457 LLVMValueRef src0)
1458 {
1459 unsigned mask;
1460 int idx;
1461 LLVMValueRef result;
1462 bool has_ds_bpermute = ctx->abi->chip_class >= VI;
1463
1464 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1465 mask = AC_TID_MASK_LEFT;
1466 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1467 mask = AC_TID_MASK_TOP;
1468 else
1469 mask = AC_TID_MASK_TOP_LEFT;
1470
1471 /* for DDX we want to next X pixel, DDY next Y pixel. */
1472 if (op == nir_op_fddx_fine ||
1473 op == nir_op_fddx_coarse ||
1474 op == nir_op_fddx)
1475 idx = 1;
1476 else
1477 idx = 2;
1478
1479 result = ac_build_ddxy(&ctx->ac, has_ds_bpermute,
1480 mask, idx,
1481 src0);
1482 return result;
1483 }
1484
1485 /*
1486 * this takes an I,J coordinate pair,
1487 * and works out the X and Y derivatives.
1488 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1489 */
1490 static LLVMValueRef emit_ddxy_interp(
1491 struct ac_nir_context *ctx,
1492 LLVMValueRef interp_ij)
1493 {
1494 LLVMValueRef result[4], a;
1495 unsigned i;
1496
1497 for (i = 0; i < 2; i++) {
1498 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1499 LLVMConstInt(ctx->ac.i32, i, false), "");
1500 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1501 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1502 }
1503 return ac_build_gather_values(&ctx->ac, result, 4);
1504 }
1505
1506 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1507 {
1508 LLVMValueRef src[4], result = NULL;
1509 unsigned num_components = instr->dest.dest.ssa.num_components;
1510 unsigned src_components;
1511 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1512
1513 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1514 switch (instr->op) {
1515 case nir_op_vec2:
1516 case nir_op_vec3:
1517 case nir_op_vec4:
1518 src_components = 1;
1519 break;
1520 case nir_op_pack_half_2x16:
1521 src_components = 2;
1522 break;
1523 case nir_op_unpack_half_2x16:
1524 src_components = 1;
1525 break;
1526 default:
1527 src_components = num_components;
1528 break;
1529 }
1530 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1531 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1532
1533 switch (instr->op) {
1534 case nir_op_fmov:
1535 case nir_op_imov:
1536 result = src[0];
1537 break;
1538 case nir_op_fneg:
1539 src[0] = to_float(&ctx->ac, src[0]);
1540 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1541 break;
1542 case nir_op_ineg:
1543 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1544 break;
1545 case nir_op_inot:
1546 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1547 break;
1548 case nir_op_iadd:
1549 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1550 break;
1551 case nir_op_fadd:
1552 src[0] = to_float(&ctx->ac, src[0]);
1553 src[1] = to_float(&ctx->ac, src[1]);
1554 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1555 break;
1556 case nir_op_fsub:
1557 src[0] = to_float(&ctx->ac, src[0]);
1558 src[1] = to_float(&ctx->ac, src[1]);
1559 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1560 break;
1561 case nir_op_isub:
1562 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1563 break;
1564 case nir_op_imul:
1565 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1566 break;
1567 case nir_op_imod:
1568 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1569 break;
1570 case nir_op_umod:
1571 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1572 break;
1573 case nir_op_fmod:
1574 src[0] = to_float(&ctx->ac, src[0]);
1575 src[1] = to_float(&ctx->ac, src[1]);
1576 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1577 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1578 to_float_type(&ctx->ac, def_type), result);
1579 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1580 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1581 break;
1582 case nir_op_frem:
1583 src[0] = to_float(&ctx->ac, src[0]);
1584 src[1] = to_float(&ctx->ac, src[1]);
1585 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1586 break;
1587 case nir_op_irem:
1588 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1589 break;
1590 case nir_op_idiv:
1591 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1592 break;
1593 case nir_op_udiv:
1594 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1595 break;
1596 case nir_op_fmul:
1597 src[0] = to_float(&ctx->ac, src[0]);
1598 src[1] = to_float(&ctx->ac, src[1]);
1599 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1600 break;
1601 case nir_op_fdiv:
1602 src[0] = to_float(&ctx->ac, src[0]);
1603 src[1] = to_float(&ctx->ac, src[1]);
1604 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1605 break;
1606 case nir_op_frcp:
1607 src[0] = to_float(&ctx->ac, src[0]);
1608 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1609 break;
1610 case nir_op_iand:
1611 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1612 break;
1613 case nir_op_ior:
1614 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1615 break;
1616 case nir_op_ixor:
1617 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1618 break;
1619 case nir_op_ishl:
1620 result = LLVMBuildShl(ctx->ac.builder, src[0],
1621 LLVMBuildZExt(ctx->ac.builder, src[1],
1622 LLVMTypeOf(src[0]), ""),
1623 "");
1624 break;
1625 case nir_op_ishr:
1626 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1627 LLVMBuildZExt(ctx->ac.builder, src[1],
1628 LLVMTypeOf(src[0]), ""),
1629 "");
1630 break;
1631 case nir_op_ushr:
1632 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1633 LLVMBuildZExt(ctx->ac.builder, src[1],
1634 LLVMTypeOf(src[0]), ""),
1635 "");
1636 break;
1637 case nir_op_ilt:
1638 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1639 break;
1640 case nir_op_ine:
1641 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1642 break;
1643 case nir_op_ieq:
1644 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1645 break;
1646 case nir_op_ige:
1647 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1648 break;
1649 case nir_op_ult:
1650 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1651 break;
1652 case nir_op_uge:
1653 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1654 break;
1655 case nir_op_feq:
1656 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1657 break;
1658 case nir_op_fne:
1659 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1660 break;
1661 case nir_op_flt:
1662 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1663 break;
1664 case nir_op_fge:
1665 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1666 break;
1667 case nir_op_fabs:
1668 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1669 to_float_type(&ctx->ac, def_type), src[0]);
1670 break;
1671 case nir_op_iabs:
1672 result = emit_iabs(&ctx->ac, src[0]);
1673 break;
1674 case nir_op_imax:
1675 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1676 break;
1677 case nir_op_imin:
1678 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1679 break;
1680 case nir_op_umax:
1681 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1682 break;
1683 case nir_op_umin:
1684 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1685 break;
1686 case nir_op_isign:
1687 result = emit_isign(&ctx->ac, src[0]);
1688 break;
1689 case nir_op_fsign:
1690 src[0] = to_float(&ctx->ac, src[0]);
1691 result = emit_fsign(&ctx->ac, src[0]);
1692 break;
1693 case nir_op_ffloor:
1694 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1695 to_float_type(&ctx->ac, def_type), src[0]);
1696 break;
1697 case nir_op_ftrunc:
1698 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1699 to_float_type(&ctx->ac, def_type), src[0]);
1700 break;
1701 case nir_op_fceil:
1702 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1703 to_float_type(&ctx->ac, def_type), src[0]);
1704 break;
1705 case nir_op_fround_even:
1706 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1707 to_float_type(&ctx->ac, def_type),src[0]);
1708 break;
1709 case nir_op_ffract:
1710 result = emit_ffract(&ctx->ac, src[0]);
1711 break;
1712 case nir_op_fsin:
1713 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1714 to_float_type(&ctx->ac, def_type), src[0]);
1715 break;
1716 case nir_op_fcos:
1717 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1718 to_float_type(&ctx->ac, def_type), src[0]);
1719 break;
1720 case nir_op_fsqrt:
1721 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1722 to_float_type(&ctx->ac, def_type), src[0]);
1723 break;
1724 case nir_op_fexp2:
1725 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1726 to_float_type(&ctx->ac, def_type), src[0]);
1727 break;
1728 case nir_op_flog2:
1729 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1730 to_float_type(&ctx->ac, def_type), src[0]);
1731 break;
1732 case nir_op_frsq:
1733 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1734 to_float_type(&ctx->ac, def_type), src[0]);
1735 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1736 break;
1737 case nir_op_fpow:
1738 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1739 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1740 break;
1741 case nir_op_fmax:
1742 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1743 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1744 if (instr->dest.dest.ssa.bit_size == 32)
1745 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1746 to_float_type(&ctx->ac, def_type),
1747 result);
1748 break;
1749 case nir_op_fmin:
1750 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1751 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1752 if (instr->dest.dest.ssa.bit_size == 32)
1753 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1754 to_float_type(&ctx->ac, def_type),
1755 result);
1756 break;
1757 case nir_op_ffma:
1758 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1759 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1760 break;
1761 case nir_op_ibitfield_extract:
1762 result = emit_bitfield_extract(&ctx->ac, true, src);
1763 break;
1764 case nir_op_ubitfield_extract:
1765 result = emit_bitfield_extract(&ctx->ac, false, src);
1766 break;
1767 case nir_op_bitfield_insert:
1768 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1769 break;
1770 case nir_op_bitfield_reverse:
1771 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1772 break;
1773 case nir_op_bit_count:
1774 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1775 break;
1776 case nir_op_vec2:
1777 case nir_op_vec3:
1778 case nir_op_vec4:
1779 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1780 src[i] = to_integer(&ctx->ac, src[i]);
1781 result = ac_build_gather_values(&ctx->ac, src, num_components);
1782 break;
1783 case nir_op_f2i32:
1784 case nir_op_f2i64:
1785 src[0] = to_float(&ctx->ac, src[0]);
1786 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1787 break;
1788 case nir_op_f2u32:
1789 case nir_op_f2u64:
1790 src[0] = to_float(&ctx->ac, src[0]);
1791 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1792 break;
1793 case nir_op_i2f32:
1794 case nir_op_i2f64:
1795 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1796 break;
1797 case nir_op_u2f32:
1798 case nir_op_u2f64:
1799 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1800 break;
1801 case nir_op_f2f64:
1802 result = LLVMBuildFPExt(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1803 break;
1804 case nir_op_f2f32:
1805 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1806 break;
1807 case nir_op_u2u32:
1808 case nir_op_u2u64:
1809 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1810 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1811 else
1812 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1813 break;
1814 case nir_op_i2i32:
1815 case nir_op_i2i64:
1816 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1817 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1818 else
1819 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1820 break;
1821 case nir_op_bcsel:
1822 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1823 break;
1824 case nir_op_find_lsb:
1825 result = emit_find_lsb(&ctx->ac, src[0]);
1826 break;
1827 case nir_op_ufind_msb:
1828 result = emit_ufind_msb(&ctx->ac, src[0]);
1829 break;
1830 case nir_op_ifind_msb:
1831 result = emit_ifind_msb(&ctx->ac, src[0]);
1832 break;
1833 case nir_op_uadd_carry:
1834 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1835 break;
1836 case nir_op_usub_borrow:
1837 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1838 break;
1839 case nir_op_b2f:
1840 result = emit_b2f(&ctx->ac, src[0]);
1841 break;
1842 case nir_op_f2b:
1843 result = emit_f2b(&ctx->ac, src[0]);
1844 break;
1845 case nir_op_b2i:
1846 result = emit_b2i(&ctx->ac, src[0]);
1847 break;
1848 case nir_op_i2b:
1849 result = emit_i2b(&ctx->ac, src[0]);
1850 break;
1851 case nir_op_fquantize2f16:
1852 result = emit_f2f16(ctx->nctx, src[0]);
1853 break;
1854 case nir_op_umul_high:
1855 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1856 break;
1857 case nir_op_imul_high:
1858 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1859 break;
1860 case nir_op_pack_half_2x16:
1861 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1862 break;
1863 case nir_op_unpack_half_2x16:
1864 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1865 break;
1866 case nir_op_fddx:
1867 case nir_op_fddy:
1868 case nir_op_fddx_fine:
1869 case nir_op_fddy_fine:
1870 case nir_op_fddx_coarse:
1871 case nir_op_fddy_coarse:
1872 result = emit_ddxy(ctx, instr->op, src[0]);
1873 break;
1874
1875 case nir_op_unpack_64_2x32_split_x: {
1876 assert(instr->src[0].src.ssa->num_components == 1);
1877 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1878 LLVMVectorType(ctx->ac.i32, 2),
1879 "");
1880 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1881 ctx->ac.i32_0, "");
1882 break;
1883 }
1884
1885 case nir_op_unpack_64_2x32_split_y: {
1886 assert(instr->src[0].src.ssa->num_components == 1);
1887 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1888 LLVMVectorType(ctx->ac.i32, 2),
1889 "");
1890 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1891 ctx->ac.i32_1, "");
1892 break;
1893 }
1894
1895 case nir_op_pack_64_2x32_split: {
1896 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1897 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1898 src[0], ctx->ac.i32_0, "");
1899 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1900 src[1], ctx->ac.i32_1, "");
1901 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1902 break;
1903 }
1904
1905 default:
1906 fprintf(stderr, "Unknown NIR alu instr: ");
1907 nir_print_instr(&instr->instr, stderr);
1908 fprintf(stderr, "\n");
1909 abort();
1910 }
1911
1912 if (result) {
1913 assert(instr->dest.dest.is_ssa);
1914 result = to_integer(&ctx->ac, result);
1915 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1916 result);
1917 }
1918 }
1919
1920 static void visit_load_const(struct ac_nir_context *ctx,
1921 const nir_load_const_instr *instr)
1922 {
1923 LLVMValueRef values[4], value = NULL;
1924 LLVMTypeRef element_type =
1925 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1926
1927 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1928 switch (instr->def.bit_size) {
1929 case 32:
1930 values[i] = LLVMConstInt(element_type,
1931 instr->value.u32[i], false);
1932 break;
1933 case 64:
1934 values[i] = LLVMConstInt(element_type,
1935 instr->value.u64[i], false);
1936 break;
1937 default:
1938 fprintf(stderr,
1939 "unsupported nir load_const bit_size: %d\n",
1940 instr->def.bit_size);
1941 abort();
1942 }
1943 }
1944 if (instr->def.num_components > 1) {
1945 value = LLVMConstVector(values, instr->def.num_components);
1946 } else
1947 value = values[0];
1948
1949 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1950 }
1951
1952 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1953 LLVMTypeRef type)
1954 {
1955 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1956 return LLVMBuildBitCast(ctx->builder, ptr,
1957 LLVMPointerType(type, addr_space), "");
1958 }
1959
1960 static LLVMValueRef
1961 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1962 {
1963 LLVMValueRef size =
1964 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1965 LLVMConstInt(ctx->ac.i32, 2, false), "");
1966
1967 /* VI only */
1968 if (ctx->abi->chip_class >= VI && in_elements) {
1969 /* On VI, the descriptor contains the size in bytes,
1970 * but TXQ must return the size in elements.
1971 * The stride is always non-zero for resources using TXQ.
1972 */
1973 LLVMValueRef stride =
1974 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1975 LLVMConstInt(ctx->ac.i32, 1, false), "");
1976 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1977 LLVMConstInt(ctx->ac.i32, 16, false), "");
1978 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1979 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1980
1981 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1982 }
1983 return size;
1984 }
1985
1986 /**
1987 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1988 * intrinsic names).
1989 */
1990 static void build_int_type_name(
1991 LLVMTypeRef type,
1992 char *buf, unsigned bufsize)
1993 {
1994 assert(bufsize >= 6);
1995
1996 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1997 snprintf(buf, bufsize, "v%ui32",
1998 LLVMGetVectorSize(type));
1999 else
2000 strcpy(buf, "i32");
2001 }
2002
2003 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2004 struct ac_image_args *args,
2005 const nir_tex_instr *instr)
2006 {
2007 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2008 LLVMValueRef coord = args->addr;
2009 LLVMValueRef half_texel[2];
2010 LLVMValueRef compare_cube_wa;
2011 LLVMValueRef result;
2012 int c;
2013 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2014
2015 //TODO Rect
2016 {
2017 struct ac_image_args txq_args = { 0 };
2018
2019 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2020 txq_args.opcode = ac_image_get_resinfo;
2021 txq_args.dmask = 0xf;
2022 txq_args.addr = ctx->i32_0;
2023 txq_args.resource = args->resource;
2024 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2025
2026 for (c = 0; c < 2; c++) {
2027 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2028 LLVMConstInt(ctx->i32, c, false), "");
2029 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2030 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2031 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2032 LLVMConstReal(ctx->f32, -0.5), "");
2033 }
2034 }
2035
2036 LLVMValueRef orig_coords = args->addr;
2037
2038 for (c = 0; c < 2; c++) {
2039 LLVMValueRef tmp;
2040 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2041 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2042 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2043 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2044 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2045 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2046 }
2047
2048
2049 /*
2050 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2051 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2052 * workaround by sampling using a scaled type and converting.
2053 * This is taken from amdgpu-pro shaders.
2054 */
2055 /* NOTE this produces some ugly code compared to amdgpu-pro,
2056 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2057 * and then reads them back. -pro generates two selects,
2058 * one s_cmp for the descriptor rewriting
2059 * one v_cmp for the coordinate and result changes.
2060 */
2061 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2062 LLVMValueRef tmp, tmp2;
2063
2064 /* workaround 8/8/8/8 uint/sint cube gather bug */
2065 /* first detect it then change to a scaled read and f2i */
2066 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2067 tmp2 = tmp;
2068
2069 /* extract the DATA_FORMAT */
2070 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2071 LLVMConstInt(ctx->i32, 6, false), false);
2072
2073 /* is the DATA_FORMAT == 8_8_8_8 */
2074 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2075
2076 if (stype == GLSL_TYPE_UINT)
2077 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2078 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2079 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2080 else
2081 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2082 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2083 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2084
2085 /* replace the NUM FORMAT in the descriptor */
2086 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2087 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2088
2089 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2090
2091 /* don't modify the coordinates for this case */
2092 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2093 }
2094 args->addr = coord;
2095 result = ac_build_image_opcode(ctx, args);
2096
2097 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2098 LLVMValueRef tmp, tmp2;
2099
2100 /* if the cube workaround is in place, f2i the result. */
2101 for (c = 0; c < 4; c++) {
2102 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2103 if (stype == GLSL_TYPE_UINT)
2104 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2105 else
2106 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2107 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2108 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2109 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2110 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2111 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2112 }
2113 }
2114 return result;
2115 }
2116
2117 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2118 const nir_tex_instr *instr,
2119 bool lod_is_zero,
2120 struct ac_image_args *args)
2121 {
2122 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2123 return ac_build_buffer_load_format(&ctx->ac,
2124 args->resource,
2125 args->addr,
2126 LLVMConstInt(ctx->ac.i32, 0, false),
2127 true);
2128 }
2129
2130 args->opcode = ac_image_sample;
2131 args->compare = instr->is_shadow;
2132
2133 switch (instr->op) {
2134 case nir_texop_txf:
2135 case nir_texop_txf_ms:
2136 case nir_texop_samples_identical:
2137 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2138 args->compare = false;
2139 args->offset = false;
2140 break;
2141 case nir_texop_txb:
2142 args->bias = true;
2143 break;
2144 case nir_texop_txl:
2145 if (lod_is_zero)
2146 args->level_zero = true;
2147 else
2148 args->lod = true;
2149 break;
2150 case nir_texop_txs:
2151 case nir_texop_query_levels:
2152 args->opcode = ac_image_get_resinfo;
2153 break;
2154 case nir_texop_tex:
2155 if (ctx->stage != MESA_SHADER_FRAGMENT)
2156 args->level_zero = true;
2157 break;
2158 case nir_texop_txd:
2159 args->deriv = true;
2160 break;
2161 case nir_texop_tg4:
2162 args->opcode = ac_image_gather4;
2163 args->level_zero = true;
2164 break;
2165 case nir_texop_lod:
2166 args->opcode = ac_image_get_lod;
2167 args->compare = false;
2168 args->offset = false;
2169 break;
2170 default:
2171 break;
2172 }
2173
2174 if (instr->op == nir_texop_tg4) {
2175 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2176 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2177 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2178 }
2179 }
2180 return ac_build_image_opcode(&ctx->ac, args);
2181 }
2182
2183 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2184 nir_intrinsic_instr *instr)
2185 {
2186 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2187 unsigned desc_set = nir_intrinsic_desc_set(instr);
2188 unsigned binding = nir_intrinsic_binding(instr);
2189 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2190 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2191 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2192 unsigned base_offset = layout->binding[binding].offset;
2193 LLVMValueRef offset, stride;
2194
2195 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2196 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2197 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2198 layout->binding[binding].dynamic_offset_offset;
2199 desc_ptr = ctx->push_constants;
2200 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2201 stride = LLVMConstInt(ctx->i32, 16, false);
2202 } else
2203 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2204
2205 offset = LLVMConstInt(ctx->i32, base_offset, false);
2206 index = LLVMBuildMul(ctx->builder, index, stride, "");
2207 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2208
2209 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2210 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2211 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2212
2213 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2214 }
2215
2216 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2217 nir_intrinsic_instr *instr)
2218 {
2219 LLVMValueRef ptr, addr;
2220
2221 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2222 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2223
2224 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2225 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2226
2227 return LLVMBuildLoad(ctx->builder, ptr, "");
2228 }
2229
2230 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2231 const nir_intrinsic_instr *instr)
2232 {
2233 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2234
2235 return get_buffer_size(ctx, desc, false);
2236 }
2237 static void visit_store_ssbo(struct ac_nir_context *ctx,
2238 nir_intrinsic_instr *instr)
2239 {
2240 const char *store_name;
2241 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2242 LLVMTypeRef data_type = ctx->ac.f32;
2243 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2244 int components_32bit = elem_size_mult * instr->num_components;
2245 unsigned writemask = nir_intrinsic_write_mask(instr);
2246 LLVMValueRef base_data, base_offset;
2247 LLVMValueRef params[6];
2248 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2249
2250 params[1] = ctx->abi->load_ssbo(ctx->abi,
2251 get_src(ctx, instr->src[1]), true);
2252 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2253 params[4] = i1false; /* glc */
2254 params[5] = i1false; /* slc */
2255
2256 if (components_32bit > 1)
2257 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2258
2259 base_data = to_float(&ctx->ac, src_data);
2260 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2261 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2262 data_type, "");
2263 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2264 while (writemask) {
2265 int start, count;
2266 LLVMValueRef data;
2267 LLVMValueRef offset;
2268 LLVMValueRef tmp;
2269 u_bit_scan_consecutive_range(&writemask, &start, &count);
2270
2271 /* Due to an LLVM limitation, split 3-element writes
2272 * into a 2-element and a 1-element write. */
2273 if (count == 3) {
2274 writemask |= 1 << (start + 2);
2275 count = 2;
2276 }
2277
2278 start *= elem_size_mult;
2279 count *= elem_size_mult;
2280
2281 if (count > 4) {
2282 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2283 count = 4;
2284 }
2285
2286 if (count == 4) {
2287 store_name = "llvm.amdgcn.buffer.store.v4f32";
2288 data = base_data;
2289 } else if (count == 2) {
2290 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2291
2292 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2293 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2294 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2295 ctx->ac.i32_0, "");
2296
2297 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2298 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2299 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2300 ctx->ac.i32_1, "");
2301 store_name = "llvm.amdgcn.buffer.store.v2f32";
2302
2303 } else {
2304 assert(count == 1);
2305 if (get_llvm_num_components(base_data) > 1)
2306 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2307 LLVMConstInt(ctx->ac.i32, start, false), "");
2308 else
2309 data = base_data;
2310 store_name = "llvm.amdgcn.buffer.store.f32";
2311 }
2312
2313 offset = base_offset;
2314 if (start != 0) {
2315 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2316 }
2317 params[0] = data;
2318 params[3] = offset;
2319 ac_build_intrinsic(&ctx->ac, store_name,
2320 ctx->ac.voidt, params, 6, 0);
2321 }
2322 }
2323
2324 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2325 const nir_intrinsic_instr *instr)
2326 {
2327 const char *name;
2328 LLVMValueRef params[6];
2329 int arg_count = 0;
2330
2331 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2332 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2333 }
2334 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2335 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2336 get_src(ctx, instr->src[0]),
2337 true);
2338 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2339 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2340 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2341
2342 switch (instr->intrinsic) {
2343 case nir_intrinsic_ssbo_atomic_add:
2344 name = "llvm.amdgcn.buffer.atomic.add";
2345 break;
2346 case nir_intrinsic_ssbo_atomic_imin:
2347 name = "llvm.amdgcn.buffer.atomic.smin";
2348 break;
2349 case nir_intrinsic_ssbo_atomic_umin:
2350 name = "llvm.amdgcn.buffer.atomic.umin";
2351 break;
2352 case nir_intrinsic_ssbo_atomic_imax:
2353 name = "llvm.amdgcn.buffer.atomic.smax";
2354 break;
2355 case nir_intrinsic_ssbo_atomic_umax:
2356 name = "llvm.amdgcn.buffer.atomic.umax";
2357 break;
2358 case nir_intrinsic_ssbo_atomic_and:
2359 name = "llvm.amdgcn.buffer.atomic.and";
2360 break;
2361 case nir_intrinsic_ssbo_atomic_or:
2362 name = "llvm.amdgcn.buffer.atomic.or";
2363 break;
2364 case nir_intrinsic_ssbo_atomic_xor:
2365 name = "llvm.amdgcn.buffer.atomic.xor";
2366 break;
2367 case nir_intrinsic_ssbo_atomic_exchange:
2368 name = "llvm.amdgcn.buffer.atomic.swap";
2369 break;
2370 case nir_intrinsic_ssbo_atomic_comp_swap:
2371 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2372 break;
2373 default:
2374 abort();
2375 }
2376
2377 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2378 }
2379
2380 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2381 const nir_intrinsic_instr *instr)
2382 {
2383 LLVMValueRef results[2];
2384 int load_components;
2385 int num_components = instr->num_components;
2386 if (instr->dest.ssa.bit_size == 64)
2387 num_components *= 2;
2388
2389 for (int i = 0; i < num_components; i += load_components) {
2390 load_components = MIN2(num_components - i, 4);
2391 const char *load_name;
2392 LLVMTypeRef data_type = ctx->ac.f32;
2393 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2394 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2395
2396 if (load_components == 3)
2397 data_type = LLVMVectorType(ctx->ac.f32, 4);
2398 else if (load_components > 1)
2399 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2400
2401 if (load_components >= 3)
2402 load_name = "llvm.amdgcn.buffer.load.v4f32";
2403 else if (load_components == 2)
2404 load_name = "llvm.amdgcn.buffer.load.v2f32";
2405 else if (load_components == 1)
2406 load_name = "llvm.amdgcn.buffer.load.f32";
2407 else
2408 unreachable("unhandled number of components");
2409
2410 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2411 LLVMValueRef params[] = {
2412 ctx->abi->load_ssbo(ctx->abi,
2413 get_src(ctx, instr->src[0]),
2414 false),
2415 LLVMConstInt(ctx->ac.i32, 0, false),
2416 offset,
2417 i1false,
2418 i1false,
2419 };
2420
2421 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2422
2423 }
2424
2425 LLVMValueRef ret = results[0];
2426 if (num_components > 4 || num_components == 3) {
2427 LLVMValueRef masks[] = {
2428 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2429 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2430 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2431 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2432 };
2433
2434 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2435 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2436 results[num_components > 4 ? 1 : 0], swizzle, "");
2437 }
2438
2439 return LLVMBuildBitCast(ctx->ac.builder, ret,
2440 get_def_type(ctx, &instr->dest.ssa), "");
2441 }
2442
2443 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2444 const nir_intrinsic_instr *instr)
2445 {
2446 LLVMValueRef results[8], ret;
2447 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2448 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2449 int num_components = instr->num_components;
2450
2451 if (ctx->abi->load_ubo)
2452 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2453
2454 if (instr->dest.ssa.bit_size == 64)
2455 num_components *= 2;
2456
2457 for (unsigned i = 0; i < num_components; ++i) {
2458 LLVMValueRef params[] = {
2459 rsrc,
2460 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2461 offset, "")
2462 };
2463 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2464 params, 2,
2465 AC_FUNC_ATTR_READNONE |
2466 AC_FUNC_ATTR_LEGACY);
2467 }
2468
2469
2470 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2471 return LLVMBuildBitCast(ctx->ac.builder, ret,
2472 get_def_type(ctx, &instr->dest.ssa), "");
2473 }
2474
2475 static void
2476 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2477 bool vs_in, unsigned *vertex_index_out,
2478 LLVMValueRef *vertex_index_ref,
2479 unsigned *const_out, LLVMValueRef *indir_out)
2480 {
2481 unsigned const_offset = 0;
2482 nir_deref *tail = &deref->deref;
2483 LLVMValueRef offset = NULL;
2484
2485 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2486 tail = tail->child;
2487 nir_deref_array *deref_array = nir_deref_as_array(tail);
2488 if (vertex_index_out)
2489 *vertex_index_out = deref_array->base_offset;
2490
2491 if (vertex_index_ref) {
2492 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2493 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2494 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2495 }
2496 *vertex_index_ref = vtx;
2497 }
2498 }
2499
2500 if (deref->var->data.compact) {
2501 assert(tail->child->deref_type == nir_deref_type_array);
2502 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2503 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2504 /* We always lower indirect dereferences for "compact" array vars. */
2505 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2506
2507 const_offset = deref_array->base_offset;
2508 goto out;
2509 }
2510
2511 while (tail->child != NULL) {
2512 const struct glsl_type *parent_type = tail->type;
2513 tail = tail->child;
2514
2515 if (tail->deref_type == nir_deref_type_array) {
2516 nir_deref_array *deref_array = nir_deref_as_array(tail);
2517 LLVMValueRef index, stride, local_offset;
2518 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2519
2520 const_offset += size * deref_array->base_offset;
2521 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2522 continue;
2523
2524 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2525 index = get_src(ctx, deref_array->indirect);
2526 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2527 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2528
2529 if (offset)
2530 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2531 else
2532 offset = local_offset;
2533 } else if (tail->deref_type == nir_deref_type_struct) {
2534 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2535
2536 for (unsigned i = 0; i < deref_struct->index; i++) {
2537 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2538 const_offset += glsl_count_attribute_slots(ft, vs_in);
2539 }
2540 } else
2541 unreachable("unsupported deref type");
2542
2543 }
2544 out:
2545 if (const_offset && offset)
2546 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2547 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2548 "");
2549
2550 *const_out = const_offset;
2551 *indir_out = offset;
2552 }
2553
2554 static LLVMValueRef
2555 lds_load(struct nir_to_llvm_context *ctx,
2556 LLVMValueRef dw_addr)
2557 {
2558 LLVMValueRef value;
2559 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2560 return value;
2561 }
2562
2563 static void
2564 lds_store(struct nir_to_llvm_context *ctx,
2565 LLVMValueRef dw_addr, LLVMValueRef value)
2566 {
2567 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2568 ac_build_indexed_store(&ctx->ac, ctx->lds,
2569 dw_addr, value);
2570 }
2571
2572 /* The offchip buffer layout for TCS->TES is
2573 *
2574 * - attribute 0 of patch 0 vertex 0
2575 * - attribute 0 of patch 0 vertex 1
2576 * - attribute 0 of patch 0 vertex 2
2577 * ...
2578 * - attribute 0 of patch 1 vertex 0
2579 * - attribute 0 of patch 1 vertex 1
2580 * ...
2581 * - attribute 1 of patch 0 vertex 0
2582 * - attribute 1 of patch 0 vertex 1
2583 * ...
2584 * - per patch attribute 0 of patch 0
2585 * - per patch attribute 0 of patch 1
2586 * ...
2587 *
2588 * Note that every attribute has 4 components.
2589 */
2590 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2591 LLVMValueRef vertex_index,
2592 LLVMValueRef param_index)
2593 {
2594 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2595 LLVMValueRef param_stride, constant16;
2596 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2597
2598 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2599 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2600 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2601 num_patches, "");
2602
2603 constant16 = LLVMConstInt(ctx->i32, 16, false);
2604 if (vertex_index) {
2605 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2606 vertices_per_patch, "");
2607
2608 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2609 vertex_index, "");
2610
2611 param_stride = total_vertices;
2612 } else {
2613 base_addr = rel_patch_id;
2614 param_stride = num_patches;
2615 }
2616
2617 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2618 LLVMBuildMul(ctx->builder, param_index,
2619 param_stride, ""), "");
2620
2621 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2622
2623 if (!vertex_index) {
2624 LLVMValueRef patch_data_offset =
2625 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2626
2627 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2628 patch_data_offset, "");
2629 }
2630 return base_addr;
2631 }
2632
2633 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2634 unsigned param,
2635 unsigned const_index,
2636 bool is_compact,
2637 LLVMValueRef vertex_index,
2638 LLVMValueRef indir_index)
2639 {
2640 LLVMValueRef param_index;
2641
2642 if (indir_index)
2643 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2644 indir_index, "");
2645 else {
2646 if (const_index && !is_compact)
2647 param += const_index;
2648 param_index = LLVMConstInt(ctx->i32, param, false);
2649 }
2650 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2651 }
2652
2653 static void
2654 mark_tess_output(struct nir_to_llvm_context *ctx,
2655 bool is_patch, uint32_t param)
2656
2657 {
2658 if (is_patch) {
2659 ctx->tess_patch_outputs_written |= (1ull << param);
2660 } else
2661 ctx->tess_outputs_written |= (1ull << param);
2662 }
2663
2664 static LLVMValueRef
2665 get_dw_address(struct nir_to_llvm_context *ctx,
2666 LLVMValueRef dw_addr,
2667 unsigned param,
2668 unsigned const_index,
2669 bool compact_const_index,
2670 LLVMValueRef vertex_index,
2671 LLVMValueRef stride,
2672 LLVMValueRef indir_index)
2673
2674 {
2675
2676 if (vertex_index) {
2677 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2678 LLVMBuildMul(ctx->builder,
2679 vertex_index,
2680 stride, ""), "");
2681 }
2682
2683 if (indir_index)
2684 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2685 LLVMBuildMul(ctx->builder, indir_index,
2686 LLVMConstInt(ctx->i32, 4, false), ""), "");
2687 else if (const_index && !compact_const_index)
2688 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2689 LLVMConstInt(ctx->i32, const_index, false), "");
2690
2691 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2692 LLVMConstInt(ctx->i32, param * 4, false), "");
2693
2694 if (const_index && compact_const_index)
2695 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2696 LLVMConstInt(ctx->i32, const_index, false), "");
2697 return dw_addr;
2698 }
2699
2700 static LLVMValueRef
2701 load_tcs_input(struct nir_to_llvm_context *ctx,
2702 nir_intrinsic_instr *instr)
2703 {
2704 LLVMValueRef dw_addr, stride;
2705 unsigned const_index;
2706 LLVMValueRef vertex_index;
2707 LLVMValueRef indir_index;
2708 unsigned param;
2709 LLVMValueRef value[4], result;
2710 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2711 const bool is_compact = instr->variables[0]->var->data.compact;
2712 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2713 get_deref_offset(ctx->nir, instr->variables[0],
2714 false, NULL, per_vertex ? &vertex_index : NULL,
2715 &const_index, &indir_index);
2716
2717 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2718 dw_addr = get_tcs_in_current_patch_offset(ctx);
2719 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2720 indir_index);
2721
2722 for (unsigned i = 0; i < instr->num_components; i++) {
2723 value[i] = lds_load(ctx, dw_addr);
2724 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2725 ctx->i32one, "");
2726 }
2727 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2728 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2729 return result;
2730 }
2731
2732 static LLVMValueRef
2733 load_tcs_output(struct nir_to_llvm_context *ctx,
2734 nir_intrinsic_instr *instr)
2735 {
2736 LLVMValueRef dw_addr, stride;
2737 LLVMValueRef value[4], result;
2738 LLVMValueRef vertex_index = NULL;
2739 LLVMValueRef indir_index = NULL;
2740 unsigned const_index = 0;
2741 unsigned param;
2742 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2743 const bool is_compact = instr->variables[0]->var->data.compact;
2744 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2745 get_deref_offset(ctx->nir, instr->variables[0],
2746 false, NULL, per_vertex ? &vertex_index : NULL,
2747 &const_index, &indir_index);
2748
2749 if (!instr->variables[0]->var->data.patch) {
2750 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2751 dw_addr = get_tcs_out_current_patch_offset(ctx);
2752 } else {
2753 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2754 }
2755
2756 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2757 indir_index);
2758
2759 for (unsigned i = 0; i < instr->num_components; i++) {
2760 value[i] = lds_load(ctx, dw_addr);
2761 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2762 ctx->i32one, "");
2763 }
2764 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2765 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2766 return result;
2767 }
2768
2769 static void
2770 store_tcs_output(struct nir_to_llvm_context *ctx,
2771 nir_intrinsic_instr *instr,
2772 LLVMValueRef src,
2773 unsigned writemask)
2774 {
2775 LLVMValueRef stride, dw_addr;
2776 LLVMValueRef buf_addr = NULL;
2777 LLVMValueRef vertex_index = NULL;
2778 LLVMValueRef indir_index = NULL;
2779 unsigned const_index = 0;
2780 unsigned param;
2781 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2782 const bool is_compact = instr->variables[0]->var->data.compact;
2783
2784 get_deref_offset(ctx->nir, instr->variables[0],
2785 false, NULL, per_vertex ? &vertex_index : NULL,
2786 &const_index, &indir_index);
2787
2788 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2789 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2790 is_compact && const_index > 3) {
2791 const_index -= 3;
2792 param++;
2793 }
2794
2795 if (!instr->variables[0]->var->data.patch) {
2796 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2797 dw_addr = get_tcs_out_current_patch_offset(ctx);
2798 } else {
2799 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2800 }
2801
2802 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2803
2804 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2805 indir_index);
2806 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2807 vertex_index, indir_index);
2808
2809 unsigned base = is_compact ? const_index : 0;
2810 for (unsigned chan = 0; chan < 8; chan++) {
2811 bool is_tess_factor = false;
2812 if (!(writemask & (1 << chan)))
2813 continue;
2814 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2815
2816 lds_store(ctx, dw_addr, value);
2817
2818 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2819 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2820 is_tess_factor = true;
2821
2822 if (!is_tess_factor && writemask != 0xF)
2823 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2824 buf_addr, ctx->oc_lds,
2825 4 * (base + chan), 1, 0, true, false);
2826
2827 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2828 ctx->i32one, "");
2829 }
2830
2831 if (writemask == 0xF) {
2832 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2833 buf_addr, ctx->oc_lds,
2834 (base * 4), 1, 0, true, false);
2835 }
2836 }
2837
2838 static LLVMValueRef
2839 load_tes_input(struct nir_to_llvm_context *ctx,
2840 const nir_intrinsic_instr *instr)
2841 {
2842 LLVMValueRef buf_addr;
2843 LLVMValueRef result;
2844 LLVMValueRef vertex_index = NULL;
2845 LLVMValueRef indir_index = NULL;
2846 unsigned const_index = 0;
2847 unsigned param;
2848 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2849 const bool is_compact = instr->variables[0]->var->data.compact;
2850
2851 get_deref_offset(ctx->nir, instr->variables[0],
2852 false, NULL, per_vertex ? &vertex_index : NULL,
2853 &const_index, &indir_index);
2854 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2855 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2856 is_compact && const_index > 3) {
2857 const_index -= 3;
2858 param++;
2859 }
2860 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2861 is_compact, vertex_index, indir_index);
2862
2863 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2864 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2865 result = trim_vector(&ctx->ac, result, instr->num_components);
2866 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2867 return result;
2868 }
2869
2870 static LLVMValueRef
2871 load_gs_input(struct nir_to_llvm_context *ctx,
2872 nir_intrinsic_instr *instr)
2873 {
2874 LLVMValueRef indir_index, vtx_offset;
2875 unsigned const_index;
2876 LLVMValueRef args[9];
2877 unsigned param, vtx_offset_param;
2878 LLVMValueRef value[4], result;
2879 unsigned vertex_index;
2880 get_deref_offset(ctx->nir, instr->variables[0],
2881 false, &vertex_index, NULL,
2882 &const_index, &indir_index);
2883 vtx_offset_param = vertex_index;
2884 assert(vtx_offset_param < 6);
2885 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2886 LLVMConstInt(ctx->i32, 4, false), "");
2887
2888 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2889 for (unsigned i = 0; i < instr->num_components; i++) {
2890
2891 args[0] = ctx->esgs_ring;
2892 args[1] = vtx_offset;
2893 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2894 args[3] = ctx->i32zero;
2895 args[4] = ctx->i32one; /* OFFEN */
2896 args[5] = ctx->i32zero; /* IDXEN */
2897 args[6] = ctx->i32one; /* GLC */
2898 args[7] = ctx->i32zero; /* SLC */
2899 args[8] = ctx->i32zero; /* TFE */
2900
2901 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2902 ctx->i32, args, 9,
2903 AC_FUNC_ATTR_READONLY |
2904 AC_FUNC_ATTR_LEGACY);
2905 }
2906 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2907
2908 return result;
2909 }
2910
2911 static LLVMValueRef
2912 build_gep_for_deref(struct ac_nir_context *ctx,
2913 nir_deref_var *deref)
2914 {
2915 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2916 assert(entry->data);
2917 LLVMValueRef val = entry->data;
2918 nir_deref *tail = deref->deref.child;
2919 while (tail != NULL) {
2920 LLVMValueRef offset;
2921 switch (tail->deref_type) {
2922 case nir_deref_type_array: {
2923 nir_deref_array *array = nir_deref_as_array(tail);
2924 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2925 if (array->deref_array_type ==
2926 nir_deref_array_type_indirect) {
2927 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2928 get_src(ctx,
2929 array->indirect),
2930 "");
2931 }
2932 break;
2933 }
2934 case nir_deref_type_struct: {
2935 nir_deref_struct *deref_struct =
2936 nir_deref_as_struct(tail);
2937 offset = LLVMConstInt(ctx->ac.i32,
2938 deref_struct->index, 0);
2939 break;
2940 }
2941 default:
2942 unreachable("bad deref type");
2943 }
2944 val = ac_build_gep0(&ctx->ac, val, offset);
2945 tail = tail->child;
2946 }
2947 return val;
2948 }
2949
2950 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2951 nir_intrinsic_instr *instr)
2952 {
2953 LLVMValueRef values[8];
2954 int idx = instr->variables[0]->var->data.driver_location;
2955 int ve = instr->dest.ssa.num_components;
2956 LLVMValueRef indir_index;
2957 LLVMValueRef ret;
2958 unsigned const_index;
2959 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2960 instr->variables[0]->var->data.mode == nir_var_shader_in;
2961 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2962 &const_index, &indir_index);
2963
2964 if (instr->dest.ssa.bit_size == 64)
2965 ve *= 2;
2966
2967 switch (instr->variables[0]->var->data.mode) {
2968 case nir_var_shader_in:
2969 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2970 return load_tcs_input(ctx->nctx, instr);
2971 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2972 return load_tes_input(ctx->nctx, instr);
2973 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2974 return load_gs_input(ctx->nctx, instr);
2975 }
2976 for (unsigned chan = 0; chan < ve; chan++) {
2977 if (indir_index) {
2978 unsigned count = glsl_count_attribute_slots(
2979 instr->variables[0]->var->type,
2980 ctx->stage == MESA_SHADER_VERTEX);
2981 count -= chan / 4;
2982 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2983 &ctx->ac, ctx->abi->inputs + idx + chan, count,
2984 4, false, true);
2985
2986 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2987 tmp_vec,
2988 indir_index, "");
2989 } else
2990 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
2991 }
2992 break;
2993 case nir_var_local:
2994 for (unsigned chan = 0; chan < ve; chan++) {
2995 if (indir_index) {
2996 unsigned count = glsl_count_attribute_slots(
2997 instr->variables[0]->var->type, false);
2998 count -= chan / 4;
2999 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3000 &ctx->ac, ctx->locals + idx + chan, count,
3001 4, true, true);
3002
3003 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3004 tmp_vec,
3005 indir_index, "");
3006 } else {
3007 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3008 }
3009 }
3010 break;
3011 case nir_var_shared: {
3012 LLVMValueRef address = build_gep_for_deref(ctx,
3013 instr->variables[0]);
3014 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3015 return LLVMBuildBitCast(ctx->ac.builder, val,
3016 get_def_type(ctx, &instr->dest.ssa),
3017 "");
3018 }
3019 case nir_var_shader_out:
3020 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3021 return load_tcs_output(ctx->nctx, instr);
3022 for (unsigned chan = 0; chan < ve; chan++) {
3023 if (indir_index) {
3024 unsigned count = glsl_count_attribute_slots(
3025 instr->variables[0]->var->type, false);
3026 count -= chan / 4;
3027 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3028 &ctx->ac, ctx->outputs + idx + chan, count,
3029 4, true, true);
3030
3031 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3032 tmp_vec,
3033 indir_index, "");
3034 } else {
3035 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3036 ctx->outputs[idx + chan + const_index * 4],
3037 "");
3038 }
3039 }
3040 break;
3041 default:
3042 unreachable("unhandle variable mode");
3043 }
3044 ret = ac_build_gather_values(&ctx->ac, values, ve);
3045 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3046 }
3047
3048 static void
3049 visit_store_var(struct ac_nir_context *ctx,
3050 nir_intrinsic_instr *instr)
3051 {
3052 LLVMValueRef temp_ptr, value;
3053 int idx = instr->variables[0]->var->data.driver_location;
3054 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3055 int writemask = instr->const_index[0];
3056 LLVMValueRef indir_index;
3057 unsigned const_index;
3058 get_deref_offset(ctx, instr->variables[0], false,
3059 NULL, NULL, &const_index, &indir_index);
3060
3061 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3062 int old_writemask = writemask;
3063
3064 src = LLVMBuildBitCast(ctx->ac.builder, src,
3065 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3066 "");
3067
3068 writemask = 0;
3069 for (unsigned chan = 0; chan < 4; chan++) {
3070 if (old_writemask & (1 << chan))
3071 writemask |= 3u << (2 * chan);
3072 }
3073 }
3074
3075 switch (instr->variables[0]->var->data.mode) {
3076 case nir_var_shader_out:
3077
3078 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3079 store_tcs_output(ctx->nctx, instr, src, writemask);
3080 return;
3081 }
3082
3083 for (unsigned chan = 0; chan < 8; chan++) {
3084 int stride = 4;
3085 if (!(writemask & (1 << chan)))
3086 continue;
3087
3088 value = llvm_extract_elem(&ctx->ac, src, chan);
3089
3090 if (instr->variables[0]->var->data.compact)
3091 stride = 1;
3092 if (indir_index) {
3093 unsigned count = glsl_count_attribute_slots(
3094 instr->variables[0]->var->type, false);
3095 count -= chan / 4;
3096 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3097 &ctx->ac, ctx->outputs + idx + chan, count,
3098 stride, true, true);
3099
3100 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3101 value, indir_index, "");
3102 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3103 count, stride, tmp_vec);
3104
3105 } else {
3106 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3107
3108 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3109 }
3110 }
3111 break;
3112 case nir_var_local:
3113 for (unsigned chan = 0; chan < 8; chan++) {
3114 if (!(writemask & (1 << chan)))
3115 continue;
3116
3117 value = llvm_extract_elem(&ctx->ac, src, chan);
3118 if (indir_index) {
3119 unsigned count = glsl_count_attribute_slots(
3120 instr->variables[0]->var->type, false);
3121 count -= chan / 4;
3122 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3123 &ctx->ac, ctx->locals + idx + chan, count,
3124 4, true, true);
3125
3126 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3127 value, indir_index, "");
3128 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3129 count, 4, tmp_vec);
3130 } else {
3131 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3132
3133 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3134 }
3135 }
3136 break;
3137 case nir_var_shared: {
3138 int writemask = instr->const_index[0];
3139 LLVMValueRef address = build_gep_for_deref(ctx,
3140 instr->variables[0]);
3141 LLVMValueRef val = get_src(ctx, instr->src[0]);
3142 unsigned components =
3143 glsl_get_vector_elements(
3144 nir_deref_tail(&instr->variables[0]->deref)->type);
3145 if (writemask == (1 << components) - 1) {
3146 val = LLVMBuildBitCast(
3147 ctx->ac.builder, val,
3148 LLVMGetElementType(LLVMTypeOf(address)), "");
3149 LLVMBuildStore(ctx->ac.builder, val, address);
3150 } else {
3151 for (unsigned chan = 0; chan < 4; chan++) {
3152 if (!(writemask & (1 << chan)))
3153 continue;
3154 LLVMValueRef ptr =
3155 LLVMBuildStructGEP(ctx->ac.builder,
3156 address, chan, "");
3157 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3158 chan);
3159 src = LLVMBuildBitCast(
3160 ctx->ac.builder, src,
3161 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3162 LLVMBuildStore(ctx->ac.builder, src, ptr);
3163 }
3164 }
3165 break;
3166 }
3167 default:
3168 break;
3169 }
3170 }
3171
3172 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3173 {
3174 switch (dim) {
3175 case GLSL_SAMPLER_DIM_BUF:
3176 return 1;
3177 case GLSL_SAMPLER_DIM_1D:
3178 return array ? 2 : 1;
3179 case GLSL_SAMPLER_DIM_2D:
3180 return array ? 3 : 2;
3181 case GLSL_SAMPLER_DIM_MS:
3182 return array ? 4 : 3;
3183 case GLSL_SAMPLER_DIM_3D:
3184 case GLSL_SAMPLER_DIM_CUBE:
3185 return 3;
3186 case GLSL_SAMPLER_DIM_RECT:
3187 case GLSL_SAMPLER_DIM_SUBPASS:
3188 return 2;
3189 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3190 return 3;
3191 default:
3192 break;
3193 }
3194 return 0;
3195 }
3196
3197
3198
3199 /* Adjust the sample index according to FMASK.
3200 *
3201 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3202 * which is the identity mapping. Each nibble says which physical sample
3203 * should be fetched to get that sample.
3204 *
3205 * For example, 0x11111100 means there are only 2 samples stored and
3206 * the second sample covers 3/4 of the pixel. When reading samples 0
3207 * and 1, return physical sample 0 (determined by the first two 0s
3208 * in FMASK), otherwise return physical sample 1.
3209 *
3210 * The sample index should be adjusted as follows:
3211 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3212 */
3213 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3214 LLVMValueRef coord_x, LLVMValueRef coord_y,
3215 LLVMValueRef coord_z,
3216 LLVMValueRef sample_index,
3217 LLVMValueRef fmask_desc_ptr)
3218 {
3219 LLVMValueRef fmask_load_address[4];
3220 LLVMValueRef res;
3221
3222 fmask_load_address[0] = coord_x;
3223 fmask_load_address[1] = coord_y;
3224 if (coord_z) {
3225 fmask_load_address[2] = coord_z;
3226 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3227 }
3228
3229 struct ac_image_args args = {0};
3230
3231 args.opcode = ac_image_load;
3232 args.da = coord_z ? true : false;
3233 args.resource = fmask_desc_ptr;
3234 args.dmask = 0xf;
3235 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3236
3237 res = ac_build_image_opcode(ctx, &args);
3238
3239 res = to_integer(ctx, res);
3240 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3241 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3242
3243 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3244 res,
3245 ctx->i32_0, "");
3246
3247 LLVMValueRef sample_index4 =
3248 LLVMBuildMul(ctx->builder, sample_index, four, "");
3249 LLVMValueRef shifted_fmask =
3250 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3251 LLVMValueRef final_sample =
3252 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3253
3254 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3255 * resource descriptor is 0 (invalid),
3256 */
3257 LLVMValueRef fmask_desc =
3258 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3259 ctx->v8i32, "");
3260
3261 LLVMValueRef fmask_word1 =
3262 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3263 ctx->i32_1, "");
3264
3265 LLVMValueRef word1_is_nonzero =
3266 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3267 fmask_word1, ctx->i32_0, "");
3268
3269 /* Replace the MSAA sample index. */
3270 sample_index =
3271 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3272 final_sample, sample_index, "");
3273 return sample_index;
3274 }
3275
3276 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3277 const nir_intrinsic_instr *instr)
3278 {
3279 const struct glsl_type *type = instr->variables[0]->var->type;
3280 if(instr->variables[0]->deref.child)
3281 type = instr->variables[0]->deref.child->type;
3282
3283 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3284 LLVMValueRef coords[4];
3285 LLVMValueRef masks[] = {
3286 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3287 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3288 };
3289 LLVMValueRef res;
3290 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3291
3292 int count;
3293 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3294 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3295 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3296 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3297 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3298
3299 count = image_type_to_components_count(dim,
3300 glsl_sampler_type_is_array(type));
3301
3302 if (is_ms) {
3303 LLVMValueRef fmask_load_address[3];
3304 int chan;
3305
3306 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3307 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3308 if (glsl_sampler_type_is_array(type))
3309 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3310 else
3311 fmask_load_address[2] = NULL;
3312 if (add_frag_pos) {
3313 for (chan = 0; chan < 2; ++chan)
3314 fmask_load_address[chan] =
3315 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3316 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3317 ctx->ac.i32, ""), "");
3318 }
3319 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3320 fmask_load_address[0],
3321 fmask_load_address[1],
3322 fmask_load_address[2],
3323 sample_index,
3324 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3325 }
3326 if (count == 1) {
3327 if (instr->src[0].ssa->num_components)
3328 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3329 else
3330 res = src0;
3331 } else {
3332 int chan;
3333 if (is_ms)
3334 count--;
3335 for (chan = 0; chan < count; ++chan) {
3336 coords[chan] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[chan], "");
3337 }
3338
3339 if (add_frag_pos) {
3340 for (chan = 0; chan < count; ++chan)
3341 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3342 ctx->ac.i32, ""), "");
3343 }
3344 if (is_ms) {
3345 coords[count] = sample_index;
3346 count++;
3347 }
3348
3349 if (count == 3) {
3350 coords[3] = LLVMGetUndef(ctx->ac.i32);
3351 count = 4;
3352 }
3353 res = ac_build_gather_values(&ctx->ac, coords, count);
3354 }
3355 return res;
3356 }
3357
3358 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3359 const nir_intrinsic_instr *instr)
3360 {
3361 LLVMValueRef params[7];
3362 LLVMValueRef res;
3363 char intrinsic_name[64];
3364 const nir_variable *var = instr->variables[0]->var;
3365 const struct glsl_type *type = var->type;
3366 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3367 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3368
3369 if(instr->variables[0]->deref.child)
3370 type = instr->variables[0]->deref.child->type;
3371
3372 type = glsl_without_array(type);
3373 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3374 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3375 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3376 ctx->ac.i32_0, ""); /* vindex */
3377 params[2] = ctx->ac.i32_0; /* voffset */
3378 params[3] = i1false; /* glc */
3379 params[4] = i1false; /* slc */
3380 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3381 params, 5, 0);
3382
3383 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3384 res = to_integer(&ctx->ac, res);
3385 } else {
3386 bool is_da = glsl_sampler_type_is_array(type) ||
3387 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3388 LLVMValueRef da = is_da ? i1true : i1false;
3389 LLVMValueRef glc = i1false;
3390 LLVMValueRef slc = i1false;
3391
3392 params[0] = get_image_coords(ctx, instr);
3393 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3394 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3395 if (HAVE_LLVM <= 0x0309) {
3396 params[3] = i1false; /* r128 */
3397 params[4] = da;
3398 params[5] = glc;
3399 params[6] = slc;
3400 } else {
3401 LLVMValueRef lwe = i1false;
3402 params[3] = glc;
3403 params[4] = slc;
3404 params[5] = lwe;
3405 params[6] = da;
3406 }
3407
3408 ac_get_image_intr_name("llvm.amdgcn.image.load",
3409 ctx->ac.v4f32, /* vdata */
3410 LLVMTypeOf(params[0]), /* coords */
3411 LLVMTypeOf(params[1]), /* rsrc */
3412 intrinsic_name, sizeof(intrinsic_name));
3413
3414 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3415 params, 7, AC_FUNC_ATTR_READONLY);
3416 }
3417 return to_integer(&ctx->ac, res);
3418 }
3419
3420 static void visit_image_store(struct ac_nir_context *ctx,
3421 nir_intrinsic_instr *instr)
3422 {
3423 LLVMValueRef params[8];
3424 char intrinsic_name[64];
3425 const nir_variable *var = instr->variables[0]->var;
3426 const struct glsl_type *type = glsl_without_array(var->type);
3427 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3428 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3429 LLVMValueRef glc = i1false;
3430 bool force_glc = ctx->abi->chip_class == SI;
3431 if (force_glc)
3432 glc = i1true;
3433
3434 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3435 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3436 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3437 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3438 ctx->ac.i32_0, ""); /* vindex */
3439 params[3] = ctx->ac.i32_0; /* voffset */
3440 params[4] = glc; /* glc */
3441 params[5] = i1false; /* slc */
3442 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3443 params, 6, 0);
3444 } else {
3445 bool is_da = glsl_sampler_type_is_array(type) ||
3446 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3447 LLVMValueRef da = is_da ? i1true : i1false;
3448 LLVMValueRef slc = i1false;
3449
3450 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3451 params[1] = get_image_coords(ctx, instr); /* coords */
3452 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3453 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3454 if (HAVE_LLVM <= 0x0309) {
3455 params[4] = i1false; /* r128 */
3456 params[5] = da;
3457 params[6] = glc;
3458 params[7] = slc;
3459 } else {
3460 LLVMValueRef lwe = i1false;
3461 params[4] = glc;
3462 params[5] = slc;
3463 params[6] = lwe;
3464 params[7] = da;
3465 }
3466
3467 ac_get_image_intr_name("llvm.amdgcn.image.store",
3468 LLVMTypeOf(params[0]), /* vdata */
3469 LLVMTypeOf(params[1]), /* coords */
3470 LLVMTypeOf(params[2]), /* rsrc */
3471 intrinsic_name, sizeof(intrinsic_name));
3472
3473 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3474 params, 8, 0);
3475 }
3476
3477 }
3478
3479 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3480 const nir_intrinsic_instr *instr)
3481 {
3482 LLVMValueRef params[6];
3483 int param_count = 0;
3484 const nir_variable *var = instr->variables[0]->var;
3485
3486 const char *atomic_name;
3487 char intrinsic_name[41];
3488 const struct glsl_type *type = glsl_without_array(var->type);
3489 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3490 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3491 MAYBE_UNUSED int length;
3492
3493 switch (instr->intrinsic) {
3494 case nir_intrinsic_image_atomic_add:
3495 atomic_name = "add";
3496 break;
3497 case nir_intrinsic_image_atomic_min:
3498 atomic_name = "smin";
3499 break;
3500 case nir_intrinsic_image_atomic_max:
3501 atomic_name = "smax";
3502 break;
3503 case nir_intrinsic_image_atomic_and:
3504 atomic_name = "and";
3505 break;
3506 case nir_intrinsic_image_atomic_or:
3507 atomic_name = "or";
3508 break;
3509 case nir_intrinsic_image_atomic_xor:
3510 atomic_name = "xor";
3511 break;
3512 case nir_intrinsic_image_atomic_exchange:
3513 atomic_name = "swap";
3514 break;
3515 case nir_intrinsic_image_atomic_comp_swap:
3516 atomic_name = "cmpswap";
3517 break;
3518 default:
3519 abort();
3520 }
3521
3522 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3523 params[param_count++] = get_src(ctx, instr->src[3]);
3524 params[param_count++] = get_src(ctx, instr->src[2]);
3525
3526 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3527 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3528 true, true);
3529 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3530 ctx->ac.i32_0, ""); /* vindex */
3531 params[param_count++] = ctx->ac.i32_0; /* voffset */
3532 params[param_count++] = i1false; /* slc */
3533
3534 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3535 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3536 } else {
3537 char coords_type[8];
3538
3539 bool da = glsl_sampler_type_is_array(type) ||
3540 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3541
3542 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3543 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3544 true, true);
3545 params[param_count++] = i1false; /* r128 */
3546 params[param_count++] = da ? i1true : i1false; /* da */
3547 params[param_count++] = i1false; /* slc */
3548
3549 build_int_type_name(LLVMTypeOf(coords),
3550 coords_type, sizeof(coords_type));
3551
3552 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3553 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3554 }
3555
3556 assert(length < sizeof(intrinsic_name));
3557 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3558 }
3559
3560 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3561 const nir_intrinsic_instr *instr)
3562 {
3563 LLVMValueRef res;
3564 const nir_variable *var = instr->variables[0]->var;
3565 const struct glsl_type *type = instr->variables[0]->var->type;
3566 bool da = glsl_sampler_type_is_array(var->type) ||
3567 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3568 if(instr->variables[0]->deref.child)
3569 type = instr->variables[0]->deref.child->type;
3570
3571 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3572 return get_buffer_size(ctx,
3573 get_sampler_desc(ctx, instr->variables[0],
3574 AC_DESC_BUFFER, true, false), true);
3575
3576 struct ac_image_args args = { 0 };
3577
3578 args.da = da;
3579 args.dmask = 0xf;
3580 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3581 args.opcode = ac_image_get_resinfo;
3582 args.addr = ctx->ac.i32_0;
3583
3584 res = ac_build_image_opcode(&ctx->ac, &args);
3585
3586 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3587 glsl_sampler_type_is_array(type)) {
3588 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3589 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3590 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3591 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3592 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3593 }
3594 return res;
3595 }
3596
3597 #define NOOP_WAITCNT 0xf7f
3598 #define LGKM_CNT 0x07f
3599 #define VM_CNT 0xf70
3600
3601 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3602 unsigned simm16)
3603 {
3604 LLVMValueRef args[1] = {
3605 LLVMConstInt(ctx->i32, simm16, false),
3606 };
3607 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3608 ctx->voidt, args, 1, 0);
3609 }
3610
3611 static void emit_barrier(struct nir_to_llvm_context *ctx)
3612 {
3613 /* SI only (thanks to a hw bug workaround):
3614 * The real barrier instruction isn’t needed, because an entire patch
3615 * always fits into a single wave.
3616 */
3617 if (ctx->options->chip_class == SI &&
3618 ctx->stage == MESA_SHADER_TESS_CTRL) {
3619 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3620 return;
3621 }
3622 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3623 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3624 }
3625
3626 static void emit_discard_if(struct ac_nir_context *ctx,
3627 const nir_intrinsic_instr *instr)
3628 {
3629 LLVMValueRef cond;
3630
3631 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
3632 get_src(ctx, instr->src[0]),
3633 ctx->ac.i32_0, "");
3634
3635 cond = LLVMBuildSelect(ctx->ac.builder, cond,
3636 LLVMConstReal(ctx->ac.f32, -1.0f),
3637 ctx->ac.f32_0, "");
3638 ac_build_kill(&ctx->ac, cond);
3639 }
3640
3641 static LLVMValueRef
3642 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3643 {
3644 LLVMValueRef result;
3645 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3646 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3647 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3648
3649 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3650 }
3651
3652 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3653 const nir_intrinsic_instr *instr)
3654 {
3655 LLVMValueRef ptr, result;
3656 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3657 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3658
3659 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3660 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3661 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3662 ptr, src, src1,
3663 LLVMAtomicOrderingSequentiallyConsistent,
3664 LLVMAtomicOrderingSequentiallyConsistent,
3665 false);
3666 } else {
3667 LLVMAtomicRMWBinOp op;
3668 switch (instr->intrinsic) {
3669 case nir_intrinsic_var_atomic_add:
3670 op = LLVMAtomicRMWBinOpAdd;
3671 break;
3672 case nir_intrinsic_var_atomic_umin:
3673 op = LLVMAtomicRMWBinOpUMin;
3674 break;
3675 case nir_intrinsic_var_atomic_umax:
3676 op = LLVMAtomicRMWBinOpUMax;
3677 break;
3678 case nir_intrinsic_var_atomic_imin:
3679 op = LLVMAtomicRMWBinOpMin;
3680 break;
3681 case nir_intrinsic_var_atomic_imax:
3682 op = LLVMAtomicRMWBinOpMax;
3683 break;
3684 case nir_intrinsic_var_atomic_and:
3685 op = LLVMAtomicRMWBinOpAnd;
3686 break;
3687 case nir_intrinsic_var_atomic_or:
3688 op = LLVMAtomicRMWBinOpOr;
3689 break;
3690 case nir_intrinsic_var_atomic_xor:
3691 op = LLVMAtomicRMWBinOpXor;
3692 break;
3693 case nir_intrinsic_var_atomic_exchange:
3694 op = LLVMAtomicRMWBinOpXchg;
3695 break;
3696 default:
3697 return NULL;
3698 }
3699
3700 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3701 LLVMAtomicOrderingSequentiallyConsistent,
3702 false);
3703 }
3704 return result;
3705 }
3706
3707 #define INTERP_CENTER 0
3708 #define INTERP_CENTROID 1
3709 #define INTERP_SAMPLE 2
3710
3711 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3712 enum glsl_interp_mode interp, unsigned location)
3713 {
3714 switch (interp) {
3715 case INTERP_MODE_FLAT:
3716 default:
3717 return NULL;
3718 case INTERP_MODE_SMOOTH:
3719 case INTERP_MODE_NONE:
3720 if (location == INTERP_CENTER)
3721 return ctx->persp_center;
3722 else if (location == INTERP_CENTROID)
3723 return ctx->persp_centroid;
3724 else if (location == INTERP_SAMPLE)
3725 return ctx->persp_sample;
3726 break;
3727 case INTERP_MODE_NOPERSPECTIVE:
3728 if (location == INTERP_CENTER)
3729 return ctx->linear_center;
3730 else if (location == INTERP_CENTROID)
3731 return ctx->linear_centroid;
3732 else if (location == INTERP_SAMPLE)
3733 return ctx->linear_sample;
3734 break;
3735 }
3736 return NULL;
3737 }
3738
3739 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3740 LLVMValueRef sample_id)
3741 {
3742 LLVMValueRef result;
3743 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3744
3745 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3746 const_array(ctx->v2f32, 64), "");
3747
3748 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3749 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3750
3751 return result;
3752 }
3753
3754 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3755 {
3756 LLVMValueRef values[2];
3757
3758 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3759 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3760 return ac_build_gather_values(&ctx->ac, values, 2);
3761 }
3762
3763 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3764 const nir_intrinsic_instr *instr)
3765 {
3766 LLVMValueRef result[2];
3767 LLVMValueRef interp_param, attr_number;
3768 unsigned location;
3769 unsigned chan;
3770 LLVMValueRef src_c0, src_c1;
3771 LLVMValueRef src0;
3772 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3773 switch (instr->intrinsic) {
3774 case nir_intrinsic_interp_var_at_centroid:
3775 location = INTERP_CENTROID;
3776 break;
3777 case nir_intrinsic_interp_var_at_sample:
3778 case nir_intrinsic_interp_var_at_offset:
3779 location = INTERP_CENTER;
3780 src0 = get_src(ctx->nir, instr->src[0]);
3781 break;
3782 default:
3783 break;
3784 }
3785
3786 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3787 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3788 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3789 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3790 LLVMValueRef sample_position;
3791 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3792
3793 /* fetch sample ID */
3794 sample_position = load_sample_position(ctx, src0);
3795
3796 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3797 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3798 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3799 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3800 }
3801 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3802 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3803
3804 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3805 LLVMValueRef ij_out[2];
3806 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3807
3808 /*
3809 * take the I then J parameters, and the DDX/Y for it, and
3810 * calculate the IJ inputs for the interpolator.
3811 * temp1 = ddx * offset/sample.x + I;
3812 * interp_param.I = ddy * offset/sample.y + temp1;
3813 * temp1 = ddx * offset/sample.x + J;
3814 * interp_param.J = ddy * offset/sample.y + temp1;
3815 */
3816 for (unsigned i = 0; i < 2; i++) {
3817 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3818 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3819 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3820 ddxy_out, ix_ll, "");
3821 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3822 ddxy_out, iy_ll, "");
3823 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3824 interp_param, ix_ll, "");
3825 LLVMValueRef temp1, temp2;
3826
3827 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3828 ctx->f32, "");
3829
3830 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3831 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3832
3833 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3834 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3835
3836 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3837 temp2, ctx->i32, "");
3838 }
3839 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3840
3841 }
3842
3843 for (chan = 0; chan < 2; chan++) {
3844 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3845
3846 if (interp_param) {
3847 interp_param = LLVMBuildBitCast(ctx->builder,
3848 interp_param, LLVMVectorType(ctx->f32, 2), "");
3849 LLVMValueRef i = LLVMBuildExtractElement(
3850 ctx->builder, interp_param, ctx->i32zero, "");
3851 LLVMValueRef j = LLVMBuildExtractElement(
3852 ctx->builder, interp_param, ctx->i32one, "");
3853
3854 result[chan] = ac_build_fs_interp(&ctx->ac,
3855 llvm_chan, attr_number,
3856 ctx->prim_mask, i, j);
3857 } else {
3858 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3859 LLVMConstInt(ctx->i32, 2, false),
3860 llvm_chan, attr_number,
3861 ctx->prim_mask);
3862 }
3863 }
3864 return ac_build_gather_values(&ctx->ac, result, 2);
3865 }
3866
3867 static void
3868 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3869 const nir_intrinsic_instr *instr)
3870 {
3871 LLVMValueRef gs_next_vertex;
3872 LLVMValueRef can_emit, kill;
3873 int idx;
3874
3875 assert(instr->const_index[0] == 0);
3876 /* Write vertex attribute values to GSVS ring */
3877 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3878 ctx->gs_next_vertex,
3879 "");
3880
3881 /* If this thread has already emitted the declared maximum number of
3882 * vertices, kill it: excessive vertex emissions are not supposed to
3883 * have any effect, and GS threads have no externally observable
3884 * effects other than emitting vertices.
3885 */
3886 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3887 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3888
3889 kill = LLVMBuildSelect(ctx->builder, can_emit,
3890 LLVMConstReal(ctx->f32, 1.0f),
3891 LLVMConstReal(ctx->f32, -1.0f), "");
3892 ac_build_kill(&ctx->ac, kill);
3893
3894 /* loop num outputs */
3895 idx = 0;
3896 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3897 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3898 int length = 4;
3899 int slot = idx;
3900 int slot_inc = 1;
3901
3902 if (!(ctx->output_mask & (1ull << i)))
3903 continue;
3904
3905 if (i == VARYING_SLOT_CLIP_DIST0) {
3906 /* pack clip and cull into a single set of slots */
3907 length = ctx->num_output_clips + ctx->num_output_culls;
3908 if (length > 4)
3909 slot_inc = 2;
3910 }
3911 for (unsigned j = 0; j < length; j++) {
3912 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3913 out_ptr[j], "");
3914 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3915 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3916 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3917
3918 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3919
3920 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3921 out_val, 1,
3922 voffset, ctx->gs2vs_offset, 0,
3923 1, 1, true, true);
3924 }
3925 idx += slot_inc;
3926 }
3927
3928 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3929 ctx->i32one, "");
3930 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3931
3932 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3933 }
3934
3935 static void
3936 visit_end_primitive(struct nir_to_llvm_context *ctx,
3937 const nir_intrinsic_instr *instr)
3938 {
3939 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3940 }
3941
3942 static LLVMValueRef
3943 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3944 const nir_intrinsic_instr *instr)
3945 {
3946 LLVMValueRef coord[4] = {
3947 ctx->tes_u,
3948 ctx->tes_v,
3949 ctx->f32zero,
3950 ctx->f32zero,
3951 };
3952
3953 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3954 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3955 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3956
3957 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3958 return LLVMBuildBitCast(ctx->builder, result,
3959 get_def_type(ctx->nir, &instr->dest.ssa), "");
3960 }
3961
3962 static void visit_intrinsic(struct ac_nir_context *ctx,
3963 nir_intrinsic_instr *instr)
3964 {
3965 LLVMValueRef result = NULL;
3966
3967 switch (instr->intrinsic) {
3968 case nir_intrinsic_load_work_group_id: {
3969 result = ctx->nctx->workgroup_ids;
3970 break;
3971 }
3972 case nir_intrinsic_load_base_vertex: {
3973 result = ctx->abi->base_vertex;
3974 break;
3975 }
3976 case nir_intrinsic_load_vertex_id_zero_base: {
3977 result = ctx->abi->vertex_id;
3978 break;
3979 }
3980 case nir_intrinsic_load_local_invocation_id: {
3981 result = ctx->nctx->local_invocation_ids;
3982 break;
3983 }
3984 case nir_intrinsic_load_base_instance:
3985 result = ctx->abi->start_instance;
3986 break;
3987 case nir_intrinsic_load_draw_id:
3988 result = ctx->abi->draw_id;
3989 break;
3990 case nir_intrinsic_load_invocation_id:
3991 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3992 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
3993 else
3994 result = ctx->nctx->gs_invocation_id;
3995 break;
3996 case nir_intrinsic_load_primitive_id:
3997 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3998 ctx->nctx->shader_info->gs.uses_prim_id = true;
3999 result = ctx->nctx->gs_prim_id;
4000 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4001 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4002 result = ctx->nctx->tcs_patch_id;
4003 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4004 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4005 result = ctx->nctx->tes_patch_id;
4006 } else
4007 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4008 break;
4009 case nir_intrinsic_load_sample_id:
4010 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4011 break;
4012 case nir_intrinsic_load_sample_pos:
4013 result = load_sample_pos(ctx);
4014 break;
4015 case nir_intrinsic_load_sample_mask_in:
4016 result = ctx->abi->sample_coverage;
4017 break;
4018 case nir_intrinsic_load_frag_coord: {
4019 LLVMValueRef values[4] = {
4020 ctx->abi->frag_pos[0],
4021 ctx->abi->frag_pos[1],
4022 ctx->abi->frag_pos[2],
4023 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4024 };
4025 result = ac_build_gather_values(&ctx->ac, values, 4);
4026 break;
4027 }
4028 case nir_intrinsic_load_front_face:
4029 result = ctx->abi->front_face;
4030 break;
4031 case nir_intrinsic_load_instance_id:
4032 result = ctx->abi->instance_id;
4033 break;
4034 case nir_intrinsic_load_num_work_groups:
4035 result = ctx->nctx->num_work_groups;
4036 break;
4037 case nir_intrinsic_load_local_invocation_index:
4038 result = visit_load_local_invocation_index(ctx->nctx);
4039 break;
4040 case nir_intrinsic_load_push_constant:
4041 result = visit_load_push_constant(ctx->nctx, instr);
4042 break;
4043 case nir_intrinsic_vulkan_resource_index:
4044 result = visit_vulkan_resource_index(ctx->nctx, instr);
4045 break;
4046 case nir_intrinsic_store_ssbo:
4047 visit_store_ssbo(ctx, instr);
4048 break;
4049 case nir_intrinsic_load_ssbo:
4050 result = visit_load_buffer(ctx, instr);
4051 break;
4052 case nir_intrinsic_ssbo_atomic_add:
4053 case nir_intrinsic_ssbo_atomic_imin:
4054 case nir_intrinsic_ssbo_atomic_umin:
4055 case nir_intrinsic_ssbo_atomic_imax:
4056 case nir_intrinsic_ssbo_atomic_umax:
4057 case nir_intrinsic_ssbo_atomic_and:
4058 case nir_intrinsic_ssbo_atomic_or:
4059 case nir_intrinsic_ssbo_atomic_xor:
4060 case nir_intrinsic_ssbo_atomic_exchange:
4061 case nir_intrinsic_ssbo_atomic_comp_swap:
4062 result = visit_atomic_ssbo(ctx, instr);
4063 break;
4064 case nir_intrinsic_load_ubo:
4065 result = visit_load_ubo_buffer(ctx, instr);
4066 break;
4067 case nir_intrinsic_get_buffer_size:
4068 result = visit_get_buffer_size(ctx, instr);
4069 break;
4070 case nir_intrinsic_load_var:
4071 result = visit_load_var(ctx, instr);
4072 break;
4073 case nir_intrinsic_store_var:
4074 visit_store_var(ctx, instr);
4075 break;
4076 case nir_intrinsic_image_load:
4077 result = visit_image_load(ctx, instr);
4078 break;
4079 case nir_intrinsic_image_store:
4080 visit_image_store(ctx, instr);
4081 break;
4082 case nir_intrinsic_image_atomic_add:
4083 case nir_intrinsic_image_atomic_min:
4084 case nir_intrinsic_image_atomic_max:
4085 case nir_intrinsic_image_atomic_and:
4086 case nir_intrinsic_image_atomic_or:
4087 case nir_intrinsic_image_atomic_xor:
4088 case nir_intrinsic_image_atomic_exchange:
4089 case nir_intrinsic_image_atomic_comp_swap:
4090 result = visit_image_atomic(ctx, instr);
4091 break;
4092 case nir_intrinsic_image_size:
4093 result = visit_image_size(ctx, instr);
4094 break;
4095 case nir_intrinsic_discard:
4096 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4097 LLVMVoidTypeInContext(ctx->ac.context),
4098 NULL, 0, AC_FUNC_ATTR_LEGACY);
4099 break;
4100 case nir_intrinsic_discard_if:
4101 emit_discard_if(ctx, instr);
4102 break;
4103 case nir_intrinsic_memory_barrier:
4104 emit_waitcnt(ctx->nctx, VM_CNT);
4105 break;
4106 case nir_intrinsic_barrier:
4107 emit_barrier(ctx->nctx);
4108 break;
4109 case nir_intrinsic_var_atomic_add:
4110 case nir_intrinsic_var_atomic_imin:
4111 case nir_intrinsic_var_atomic_umin:
4112 case nir_intrinsic_var_atomic_imax:
4113 case nir_intrinsic_var_atomic_umax:
4114 case nir_intrinsic_var_atomic_and:
4115 case nir_intrinsic_var_atomic_or:
4116 case nir_intrinsic_var_atomic_xor:
4117 case nir_intrinsic_var_atomic_exchange:
4118 case nir_intrinsic_var_atomic_comp_swap:
4119 result = visit_var_atomic(ctx->nctx, instr);
4120 break;
4121 case nir_intrinsic_interp_var_at_centroid:
4122 case nir_intrinsic_interp_var_at_sample:
4123 case nir_intrinsic_interp_var_at_offset:
4124 result = visit_interp(ctx->nctx, instr);
4125 break;
4126 case nir_intrinsic_emit_vertex:
4127 visit_emit_vertex(ctx->nctx, instr);
4128 break;
4129 case nir_intrinsic_end_primitive:
4130 visit_end_primitive(ctx->nctx, instr);
4131 break;
4132 case nir_intrinsic_load_tess_coord:
4133 result = visit_load_tess_coord(ctx->nctx, instr);
4134 break;
4135 case nir_intrinsic_load_patch_vertices_in:
4136 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4137 break;
4138 default:
4139 fprintf(stderr, "Unknown intrinsic: ");
4140 nir_print_instr(&instr->instr, stderr);
4141 fprintf(stderr, "\n");
4142 break;
4143 }
4144 if (result) {
4145 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4146 }
4147 }
4148
4149 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4150 LLVMValueRef buffer, bool write)
4151 {
4152 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4153
4154 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4155 ctx->shader_info->fs.writes_memory = true;
4156
4157 return buffer;
4158 }
4159
4160 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4161 unsigned descriptor_set,
4162 unsigned base_index,
4163 unsigned constant_index,
4164 LLVMValueRef index,
4165 enum ac_descriptor_type desc_type,
4166 bool image, bool write)
4167 {
4168 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4169 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4170 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4171 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4172 unsigned offset = binding->offset;
4173 unsigned stride = binding->size;
4174 unsigned type_size;
4175 LLVMBuilderRef builder = ctx->builder;
4176 LLVMTypeRef type;
4177
4178 assert(base_index < layout->binding_count);
4179
4180 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4181 ctx->shader_info->fs.writes_memory = true;
4182
4183 switch (desc_type) {
4184 case AC_DESC_IMAGE:
4185 type = ctx->v8i32;
4186 type_size = 32;
4187 break;
4188 case AC_DESC_FMASK:
4189 type = ctx->v8i32;
4190 offset += 32;
4191 type_size = 32;
4192 break;
4193 case AC_DESC_SAMPLER:
4194 type = ctx->v4i32;
4195 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4196 offset += 64;
4197
4198 type_size = 16;
4199 break;
4200 case AC_DESC_BUFFER:
4201 type = ctx->v4i32;
4202 type_size = 16;
4203 break;
4204 default:
4205 unreachable("invalid desc_type\n");
4206 }
4207
4208 offset += constant_index * stride;
4209
4210 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4211 (!index || binding->immutable_samplers_equal)) {
4212 if (binding->immutable_samplers_equal)
4213 constant_index = 0;
4214
4215 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4216
4217 LLVMValueRef constants[] = {
4218 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4219 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4220 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4221 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4222 };
4223 return ac_build_gather_values(&ctx->ac, constants, 4);
4224 }
4225
4226 assert(stride % type_size == 0);
4227
4228 if (!index)
4229 index = ctx->i32zero;
4230
4231 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4232
4233 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4234 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4235
4236 return ac_build_indexed_load_const(&ctx->ac, list, index);
4237 }
4238
4239 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4240 const nir_deref_var *deref,
4241 enum ac_descriptor_type desc_type,
4242 bool image, bool write)
4243 {
4244 LLVMValueRef index = NULL;
4245 unsigned constant_index = 0;
4246 const nir_deref *tail = &deref->deref;
4247
4248 while (tail->child) {
4249 const nir_deref_array *child = nir_deref_as_array(tail->child);
4250 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4251
4252 if (!array_size)
4253 array_size = 1;
4254
4255 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4256
4257 if (child->deref_array_type == nir_deref_array_type_indirect) {
4258 LLVMValueRef indirect = get_src(ctx, child->indirect);
4259
4260 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4261 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4262
4263 if (!index)
4264 index = indirect;
4265 else
4266 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4267 }
4268
4269 constant_index += child->base_offset * array_size;
4270
4271 tail = &child->deref;
4272 }
4273
4274 return ctx->abi->load_sampler_desc(ctx->abi,
4275 deref->var->data.descriptor_set,
4276 deref->var->data.binding,
4277 constant_index, index,
4278 desc_type, image, write);
4279 }
4280
4281 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4282 struct ac_image_args *args,
4283 const nir_tex_instr *instr,
4284 nir_texop op,
4285 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4286 LLVMValueRef *param, unsigned count,
4287 unsigned dmask)
4288 {
4289 unsigned is_rect = 0;
4290 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4291
4292 if (op == nir_texop_lod)
4293 da = false;
4294 /* Pad to power of two vector */
4295 while (count < util_next_power_of_two(count))
4296 param[count++] = LLVMGetUndef(ctx->i32);
4297
4298 if (count > 1)
4299 args->addr = ac_build_gather_values(ctx, param, count);
4300 else
4301 args->addr = param[0];
4302
4303 args->resource = res_ptr;
4304 args->sampler = samp_ptr;
4305
4306 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4307 args->addr = param[0];
4308 return;
4309 }
4310
4311 args->dmask = dmask;
4312 args->unorm = is_rect;
4313 args->da = da;
4314 }
4315
4316 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4317 *
4318 * SI-CI:
4319 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4320 * filtering manually. The driver sets img7 to a mask clearing
4321 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4322 * s_and_b32 samp0, samp0, img7
4323 *
4324 * VI:
4325 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4326 */
4327 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4328 LLVMValueRef res, LLVMValueRef samp)
4329 {
4330 LLVMBuilderRef builder = ctx->ac.builder;
4331 LLVMValueRef img7, samp0;
4332
4333 if (ctx->abi->chip_class >= VI)
4334 return samp;
4335
4336 img7 = LLVMBuildExtractElement(builder, res,
4337 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4338 samp0 = LLVMBuildExtractElement(builder, samp,
4339 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4340 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4341 return LLVMBuildInsertElement(builder, samp, samp0,
4342 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4343 }
4344
4345 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4346 nir_tex_instr *instr,
4347 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4348 LLVMValueRef *fmask_ptr)
4349 {
4350 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4351 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4352 else
4353 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4354 if (samp_ptr) {
4355 if (instr->sampler)
4356 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4357 else
4358 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4359 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4360 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4361 }
4362 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4363 instr->op == nir_texop_samples_identical))
4364 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4365 }
4366
4367 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4368 LLVMValueRef coord)
4369 {
4370 coord = to_float(ctx, coord);
4371 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4372 coord = to_integer(ctx, coord);
4373 return coord;
4374 }
4375
4376 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4377 {
4378 LLVMValueRef result = NULL;
4379 struct ac_image_args args = { 0 };
4380 unsigned dmask = 0xf;
4381 LLVMValueRef address[16];
4382 LLVMValueRef coords[5];
4383 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4384 LLVMValueRef bias = NULL, offsets = NULL;
4385 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4386 LLVMValueRef ddx = NULL, ddy = NULL;
4387 LLVMValueRef derivs[6];
4388 unsigned chan, count = 0;
4389 unsigned const_src = 0, num_deriv_comp = 0;
4390 bool lod_is_zero = false;
4391
4392 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4393
4394 for (unsigned i = 0; i < instr->num_srcs; i++) {
4395 switch (instr->src[i].src_type) {
4396 case nir_tex_src_coord:
4397 coord = get_src(ctx, instr->src[i].src);
4398 break;
4399 case nir_tex_src_projector:
4400 break;
4401 case nir_tex_src_comparator:
4402 comparator = get_src(ctx, instr->src[i].src);
4403 break;
4404 case nir_tex_src_offset:
4405 offsets = get_src(ctx, instr->src[i].src);
4406 const_src = i;
4407 break;
4408 case nir_tex_src_bias:
4409 bias = get_src(ctx, instr->src[i].src);
4410 break;
4411 case nir_tex_src_lod: {
4412 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4413
4414 if (val && val->i32[0] == 0)
4415 lod_is_zero = true;
4416 lod = get_src(ctx, instr->src[i].src);
4417 break;
4418 }
4419 case nir_tex_src_ms_index:
4420 sample_index = get_src(ctx, instr->src[i].src);
4421 break;
4422 case nir_tex_src_ms_mcs:
4423 break;
4424 case nir_tex_src_ddx:
4425 ddx = get_src(ctx, instr->src[i].src);
4426 num_deriv_comp = instr->src[i].src.ssa->num_components;
4427 break;
4428 case nir_tex_src_ddy:
4429 ddy = get_src(ctx, instr->src[i].src);
4430 break;
4431 case nir_tex_src_texture_offset:
4432 case nir_tex_src_sampler_offset:
4433 case nir_tex_src_plane:
4434 default:
4435 break;
4436 }
4437 }
4438
4439 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4440 result = get_buffer_size(ctx, res_ptr, true);
4441 goto write_result;
4442 }
4443
4444 if (instr->op == nir_texop_texture_samples) {
4445 LLVMValueRef res, samples, is_msaa;
4446 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4447 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4448 LLVMConstInt(ctx->ac.i32, 3, false), "");
4449 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4450 LLVMConstInt(ctx->ac.i32, 28, false), "");
4451 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4452 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4453 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4454 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4455
4456 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4457 LLVMConstInt(ctx->ac.i32, 16, false), "");
4458 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4459 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4460 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4461 samples, "");
4462 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4463 ctx->ac.i32_1, "");
4464 result = samples;
4465 goto write_result;
4466 }
4467
4468 if (coord)
4469 for (chan = 0; chan < instr->coord_components; chan++)
4470 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4471
4472 if (offsets && instr->op != nir_texop_txf) {
4473 LLVMValueRef offset[3], pack;
4474 for (chan = 0; chan < 3; ++chan)
4475 offset[chan] = ctx->ac.i32_0;
4476
4477 args.offset = true;
4478 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4479 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4480 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4481 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4482 if (chan)
4483 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4484 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4485 }
4486 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4487 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4488 address[count++] = pack;
4489
4490 }
4491 /* pack LOD bias value */
4492 if (instr->op == nir_texop_txb && bias) {
4493 address[count++] = bias;
4494 }
4495
4496 /* Pack depth comparison value */
4497 if (instr->is_shadow && comparator) {
4498 LLVMValueRef z = to_float(&ctx->ac,
4499 llvm_extract_elem(&ctx->ac, comparator, 0));
4500
4501 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4502 * so the depth comparison value isn't clamped for Z16 and
4503 * Z24 anymore. Do it manually here.
4504 *
4505 * It's unnecessary if the original texture format was
4506 * Z32_FLOAT, but we don't know that here.
4507 */
4508 if (ctx->abi->chip_class == VI)
4509 z = ac_build_clamp(&ctx->ac, z);
4510
4511 address[count++] = z;
4512 }
4513
4514 /* pack derivatives */
4515 if (ddx || ddy) {
4516 switch (instr->sampler_dim) {
4517 case GLSL_SAMPLER_DIM_3D:
4518 case GLSL_SAMPLER_DIM_CUBE:
4519 num_deriv_comp = 3;
4520 break;
4521 case GLSL_SAMPLER_DIM_2D:
4522 default:
4523 num_deriv_comp = 2;
4524 break;
4525 case GLSL_SAMPLER_DIM_1D:
4526 num_deriv_comp = 1;
4527 break;
4528 }
4529
4530 for (unsigned i = 0; i < num_deriv_comp; i++) {
4531 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4532 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4533 }
4534 }
4535
4536 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4537 if (instr->is_array && instr->op != nir_texop_lod)
4538 coords[3] = apply_round_slice(&ctx->ac, coords[3]);
4539 for (chan = 0; chan < instr->coord_components; chan++)
4540 coords[chan] = to_float(&ctx->ac, coords[chan]);
4541 if (instr->coord_components == 3)
4542 coords[3] = LLVMGetUndef(ctx->ac.f32);
4543 ac_prepare_cube_coords(&ctx->ac,
4544 instr->op == nir_texop_txd, instr->is_array,
4545 coords, derivs);
4546 if (num_deriv_comp)
4547 num_deriv_comp--;
4548 }
4549
4550 if (ddx || ddy) {
4551 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4552 address[count++] = derivs[i];
4553 }
4554
4555 /* Pack texture coordinates */
4556 if (coord) {
4557 address[count++] = coords[0];
4558 if (instr->coord_components > 1) {
4559 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4560 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4561 }
4562 address[count++] = coords[1];
4563 }
4564 if (instr->coord_components > 2) {
4565 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4566 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4567 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4568 instr->op != nir_texop_txf) {
4569 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4570 }
4571 address[count++] = coords[2];
4572 }
4573 }
4574
4575 /* Pack LOD */
4576 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4577 instr->op == nir_texop_txf)) {
4578 address[count++] = lod;
4579 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4580 address[count++] = sample_index;
4581 } else if(instr->op == nir_texop_txs) {
4582 count = 0;
4583 if (lod)
4584 address[count++] = lod;
4585 else
4586 address[count++] = ctx->ac.i32_0;
4587 }
4588
4589 for (chan = 0; chan < count; chan++) {
4590 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4591 address[chan], ctx->ac.i32, "");
4592 }
4593
4594 if (instr->op == nir_texop_samples_identical) {
4595 LLVMValueRef txf_address[4];
4596 struct ac_image_args txf_args = { 0 };
4597 unsigned txf_count = count;
4598 memcpy(txf_address, address, sizeof(txf_address));
4599
4600 if (!instr->is_array)
4601 txf_address[2] = ctx->ac.i32_0;
4602 txf_address[3] = ctx->ac.i32_0;
4603
4604 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4605 fmask_ptr, NULL,
4606 txf_address, txf_count, 0xf);
4607
4608 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4609
4610 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4611 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4612 goto write_result;
4613 }
4614
4615 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4616 instr->op != nir_texop_txs) {
4617 unsigned sample_chan = instr->is_array ? 3 : 2;
4618 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4619 address[0],
4620 address[1],
4621 instr->is_array ? address[2] : NULL,
4622 address[sample_chan],
4623 fmask_ptr);
4624 }
4625
4626 if (offsets && instr->op == nir_texop_txf) {
4627 nir_const_value *const_offset =
4628 nir_src_as_const_value(instr->src[const_src].src);
4629 int num_offsets = instr->src[const_src].src.ssa->num_components;
4630 assert(const_offset);
4631 num_offsets = MIN2(num_offsets, instr->coord_components);
4632 if (num_offsets > 2)
4633 address[2] = LLVMBuildAdd(ctx->ac.builder,
4634 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4635 if (num_offsets > 1)
4636 address[1] = LLVMBuildAdd(ctx->ac.builder,
4637 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4638 address[0] = LLVMBuildAdd(ctx->ac.builder,
4639 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4640
4641 }
4642
4643 /* TODO TG4 support */
4644 if (instr->op == nir_texop_tg4) {
4645 if (instr->is_shadow)
4646 dmask = 1;
4647 else
4648 dmask = 1 << instr->component;
4649 }
4650 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4651 res_ptr, samp_ptr, address, count, dmask);
4652
4653 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4654
4655 if (instr->op == nir_texop_query_levels)
4656 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4657 else if (instr->is_shadow && instr->is_new_style_shadow &&
4658 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4659 instr->op != nir_texop_tg4)
4660 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4661 else if (instr->op == nir_texop_txs &&
4662 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4663 instr->is_array) {
4664 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4665 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4666 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4667 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4668 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4669 } else if (instr->dest.ssa.num_components != 4)
4670 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4671
4672 write_result:
4673 if (result) {
4674 assert(instr->dest.is_ssa);
4675 result = to_integer(&ctx->ac, result);
4676 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4677 }
4678 }
4679
4680
4681 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4682 {
4683 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4684 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4685
4686 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4687 _mesa_hash_table_insert(ctx->phis, instr, result);
4688 }
4689
4690 static void visit_post_phi(struct ac_nir_context *ctx,
4691 nir_phi_instr *instr,
4692 LLVMValueRef llvm_phi)
4693 {
4694 nir_foreach_phi_src(src, instr) {
4695 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4696 LLVMValueRef llvm_src = get_src(ctx, src->src);
4697
4698 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4699 }
4700 }
4701
4702 static void phi_post_pass(struct ac_nir_context *ctx)
4703 {
4704 struct hash_entry *entry;
4705 hash_table_foreach(ctx->phis, entry) {
4706 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4707 (LLVMValueRef)entry->data);
4708 }
4709 }
4710
4711
4712 static void visit_ssa_undef(struct ac_nir_context *ctx,
4713 const nir_ssa_undef_instr *instr)
4714 {
4715 unsigned num_components = instr->def.num_components;
4716 LLVMValueRef undef;
4717
4718 if (num_components == 1)
4719 undef = LLVMGetUndef(ctx->ac.i32);
4720 else {
4721 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4722 }
4723 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4724 }
4725
4726 static void visit_jump(struct ac_nir_context *ctx,
4727 const nir_jump_instr *instr)
4728 {
4729 switch (instr->type) {
4730 case nir_jump_break:
4731 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4732 LLVMClearInsertionPosition(ctx->ac.builder);
4733 break;
4734 case nir_jump_continue:
4735 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4736 LLVMClearInsertionPosition(ctx->ac.builder);
4737 break;
4738 default:
4739 fprintf(stderr, "Unknown NIR jump instr: ");
4740 nir_print_instr(&instr->instr, stderr);
4741 fprintf(stderr, "\n");
4742 abort();
4743 }
4744 }
4745
4746 static void visit_cf_list(struct ac_nir_context *ctx,
4747 struct exec_list *list);
4748
4749 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4750 {
4751 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4752 nir_foreach_instr(instr, block)
4753 {
4754 switch (instr->type) {
4755 case nir_instr_type_alu:
4756 visit_alu(ctx, nir_instr_as_alu(instr));
4757 break;
4758 case nir_instr_type_load_const:
4759 visit_load_const(ctx, nir_instr_as_load_const(instr));
4760 break;
4761 case nir_instr_type_intrinsic:
4762 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4763 break;
4764 case nir_instr_type_tex:
4765 visit_tex(ctx, nir_instr_as_tex(instr));
4766 break;
4767 case nir_instr_type_phi:
4768 visit_phi(ctx, nir_instr_as_phi(instr));
4769 break;
4770 case nir_instr_type_ssa_undef:
4771 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4772 break;
4773 case nir_instr_type_jump:
4774 visit_jump(ctx, nir_instr_as_jump(instr));
4775 break;
4776 default:
4777 fprintf(stderr, "Unknown NIR instr type: ");
4778 nir_print_instr(instr, stderr);
4779 fprintf(stderr, "\n");
4780 abort();
4781 }
4782 }
4783
4784 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4785 }
4786
4787 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4788 {
4789 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4790
4791 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4792 LLVMBasicBlockRef merge_block =
4793 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4794 LLVMBasicBlockRef if_block =
4795 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4796 LLVMBasicBlockRef else_block = merge_block;
4797 if (!exec_list_is_empty(&if_stmt->else_list))
4798 else_block = LLVMAppendBasicBlockInContext(
4799 ctx->ac.context, fn, "");
4800
4801 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4802 LLVMConstInt(ctx->ac.i32, 0, false), "");
4803 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4804
4805 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4806 visit_cf_list(ctx, &if_stmt->then_list);
4807 if (LLVMGetInsertBlock(ctx->ac.builder))
4808 LLVMBuildBr(ctx->ac.builder, merge_block);
4809
4810 if (!exec_list_is_empty(&if_stmt->else_list)) {
4811 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4812 visit_cf_list(ctx, &if_stmt->else_list);
4813 if (LLVMGetInsertBlock(ctx->ac.builder))
4814 LLVMBuildBr(ctx->ac.builder, merge_block);
4815 }
4816
4817 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4818 }
4819
4820 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4821 {
4822 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4823 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4824 LLVMBasicBlockRef break_parent = ctx->break_block;
4825
4826 ctx->continue_block =
4827 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4828 ctx->break_block =
4829 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4830
4831 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4832 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4833 visit_cf_list(ctx, &loop->body);
4834
4835 if (LLVMGetInsertBlock(ctx->ac.builder))
4836 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4837 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4838
4839 ctx->continue_block = continue_parent;
4840 ctx->break_block = break_parent;
4841 }
4842
4843 static void visit_cf_list(struct ac_nir_context *ctx,
4844 struct exec_list *list)
4845 {
4846 foreach_list_typed(nir_cf_node, node, node, list)
4847 {
4848 switch (node->type) {
4849 case nir_cf_node_block:
4850 visit_block(ctx, nir_cf_node_as_block(node));
4851 break;
4852
4853 case nir_cf_node_if:
4854 visit_if(ctx, nir_cf_node_as_if(node));
4855 break;
4856
4857 case nir_cf_node_loop:
4858 visit_loop(ctx, nir_cf_node_as_loop(node));
4859 break;
4860
4861 default:
4862 assert(0);
4863 }
4864 }
4865 }
4866
4867 static void
4868 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4869 struct nir_variable *variable)
4870 {
4871 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4872 LLVMValueRef t_offset;
4873 LLVMValueRef t_list;
4874 LLVMValueRef input;
4875 LLVMValueRef buffer_index;
4876 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4877 int idx = variable->data.location;
4878 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4879
4880 variable->data.driver_location = idx * 4;
4881
4882 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4883 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4884 ctx->abi.start_instance, "");
4885 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4886 ctx->shader_info->vs.vgpr_comp_cnt);
4887 } else
4888 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4889 ctx->abi.base_vertex, "");
4890
4891 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4892 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4893
4894 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4895
4896 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4897 buffer_index,
4898 LLVMConstInt(ctx->i32, 0, false),
4899 true);
4900
4901 for (unsigned chan = 0; chan < 4; chan++) {
4902 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4903 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4904 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4905 input, llvm_chan, ""));
4906 }
4907 }
4908 }
4909
4910 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4911 unsigned attr,
4912 LLVMValueRef interp_param,
4913 LLVMValueRef prim_mask,
4914 LLVMValueRef result[4])
4915 {
4916 LLVMValueRef attr_number;
4917 unsigned chan;
4918 LLVMValueRef i, j;
4919 bool interp = interp_param != NULL;
4920
4921 attr_number = LLVMConstInt(ctx->i32, attr, false);
4922
4923 /* fs.constant returns the param from the middle vertex, so it's not
4924 * really useful for flat shading. It's meant to be used for custom
4925 * interpolation (but the intrinsic can't fetch from the other two
4926 * vertices).
4927 *
4928 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4929 * to do the right thing. The only reason we use fs.constant is that
4930 * fs.interp cannot be used on integers, because they can be equal
4931 * to NaN.
4932 */
4933 if (interp) {
4934 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4935 LLVMVectorType(ctx->f32, 2), "");
4936
4937 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4938 ctx->i32zero, "");
4939 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4940 ctx->i32one, "");
4941 }
4942
4943 for (chan = 0; chan < 4; chan++) {
4944 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4945
4946 if (interp) {
4947 result[chan] = ac_build_fs_interp(&ctx->ac,
4948 llvm_chan,
4949 attr_number,
4950 prim_mask, i, j);
4951 } else {
4952 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4953 LLVMConstInt(ctx->i32, 2, false),
4954 llvm_chan,
4955 attr_number,
4956 prim_mask);
4957 }
4958 }
4959 }
4960
4961 static void
4962 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4963 struct nir_variable *variable)
4964 {
4965 int idx = variable->data.location;
4966 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4967 LLVMValueRef interp;
4968
4969 variable->data.driver_location = idx * 4;
4970 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4971
4972 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4973 unsigned interp_type;
4974 if (variable->data.sample) {
4975 interp_type = INTERP_SAMPLE;
4976 ctx->shader_info->info.ps.force_persample = true;
4977 } else if (variable->data.centroid)
4978 interp_type = INTERP_CENTROID;
4979 else
4980 interp_type = INTERP_CENTER;
4981
4982 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4983 } else
4984 interp = NULL;
4985
4986 for (unsigned i = 0; i < attrib_count; ++i)
4987 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4988
4989 }
4990
4991 static void
4992 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4993 struct nir_variable *variable)
4994 {
4995 switch (ctx->stage) {
4996 case MESA_SHADER_VERTEX:
4997 handle_vs_input_decl(ctx, variable);
4998 break;
4999 case MESA_SHADER_FRAGMENT:
5000 handle_fs_input_decl(ctx, variable);
5001 break;
5002 default:
5003 break;
5004 }
5005
5006 }
5007
5008 static void
5009 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
5010 struct nir_shader *nir)
5011 {
5012 unsigned index = 0;
5013 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5014 LLVMValueRef interp_param;
5015 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5016
5017 if (!(ctx->input_mask & (1ull << i)))
5018 continue;
5019
5020 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5021 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5022 interp_param = *inputs;
5023 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5024 inputs);
5025
5026 if (!interp_param)
5027 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5028 ++index;
5029 } else if (i == VARYING_SLOT_POS) {
5030 for(int i = 0; i < 3; ++i)
5031 inputs[i] = ctx->abi.frag_pos[i];
5032
5033 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one,
5034 ctx->abi.frag_pos[3]);
5035 }
5036 }
5037 ctx->shader_info->fs.num_interp = index;
5038 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5039 ctx->shader_info->fs.has_pcoord = true;
5040 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5041 ctx->shader_info->fs.prim_id_input = true;
5042 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5043 ctx->shader_info->fs.layer_input = true;
5044 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5045 }
5046
5047 static LLVMValueRef
5048 ac_build_alloca(struct ac_llvm_context *ac,
5049 LLVMTypeRef type,
5050 const char *name)
5051 {
5052 LLVMBuilderRef builder = ac->builder;
5053 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5054 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5055 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5056 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5057 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5058 LLVMValueRef res;
5059
5060 if (first_instr) {
5061 LLVMPositionBuilderBefore(first_builder, first_instr);
5062 } else {
5063 LLVMPositionBuilderAtEnd(first_builder, first_block);
5064 }
5065
5066 res = LLVMBuildAlloca(first_builder, type, name);
5067 LLVMBuildStore(builder, LLVMConstNull(type), res);
5068
5069 LLVMDisposeBuilder(first_builder);
5070
5071 return res;
5072 }
5073
5074 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5075 LLVMTypeRef type,
5076 const char *name)
5077 {
5078 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5079 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5080 return ptr;
5081 }
5082
5083 static void
5084 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5085 struct nir_variable *variable)
5086 {
5087 int idx = variable->data.location + variable->data.index;
5088 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5089 uint64_t mask_attribs;
5090
5091 variable->data.driver_location = idx * 4;
5092
5093 /* tess ctrl has it's own load/store paths for outputs */
5094 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5095 return;
5096
5097 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5098 if (ctx->stage == MESA_SHADER_VERTEX ||
5099 ctx->stage == MESA_SHADER_TESS_EVAL ||
5100 ctx->stage == MESA_SHADER_GEOMETRY) {
5101 if (idx == VARYING_SLOT_CLIP_DIST0) {
5102 int length = ctx->num_output_clips + ctx->num_output_culls;
5103 if (ctx->stage == MESA_SHADER_VERTEX) {
5104 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5105 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5106 }
5107 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5108 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5109 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5110 }
5111
5112 if (length > 4)
5113 attrib_count = 2;
5114 else
5115 attrib_count = 1;
5116 mask_attribs = 1ull << idx;
5117 }
5118 }
5119
5120 ctx->output_mask |= mask_attribs;
5121 }
5122
5123 static void
5124 handle_shader_output_decl(struct ac_nir_context *ctx,
5125 struct nir_shader *nir,
5126 struct nir_variable *variable)
5127 {
5128 unsigned output_loc = variable->data.driver_location / 4;
5129 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5130
5131 /* tess ctrl has it's own load/store paths for outputs */
5132 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5133 return;
5134
5135 if (ctx->stage == MESA_SHADER_VERTEX ||
5136 ctx->stage == MESA_SHADER_TESS_EVAL ||
5137 ctx->stage == MESA_SHADER_GEOMETRY) {
5138 int idx = variable->data.location + variable->data.index;
5139 if (idx == VARYING_SLOT_CLIP_DIST0) {
5140 int length = nir->info.clip_distance_array_size +
5141 nir->info.cull_distance_array_size;
5142
5143 if (length > 4)
5144 attrib_count = 2;
5145 else
5146 attrib_count = 1;
5147 }
5148 }
5149
5150 for (unsigned i = 0; i < attrib_count; ++i) {
5151 for (unsigned chan = 0; chan < 4; chan++) {
5152 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5153 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5154 }
5155 }
5156 }
5157
5158 static LLVMTypeRef
5159 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5160 enum glsl_base_type type)
5161 {
5162 switch (type) {
5163 case GLSL_TYPE_INT:
5164 case GLSL_TYPE_UINT:
5165 case GLSL_TYPE_BOOL:
5166 case GLSL_TYPE_SUBROUTINE:
5167 return ctx->i32;
5168 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5169 return ctx->f32;
5170 case GLSL_TYPE_INT64:
5171 case GLSL_TYPE_UINT64:
5172 return ctx->i64;
5173 case GLSL_TYPE_DOUBLE:
5174 return ctx->f64;
5175 default:
5176 unreachable("unknown GLSL type");
5177 }
5178 }
5179
5180 static LLVMTypeRef
5181 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5182 const struct glsl_type *type)
5183 {
5184 if (glsl_type_is_scalar(type)) {
5185 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5186 }
5187
5188 if (glsl_type_is_vector(type)) {
5189 return LLVMVectorType(
5190 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5191 glsl_get_vector_elements(type));
5192 }
5193
5194 if (glsl_type_is_matrix(type)) {
5195 return LLVMArrayType(
5196 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5197 glsl_get_matrix_columns(type));
5198 }
5199
5200 if (glsl_type_is_array(type)) {
5201 return LLVMArrayType(
5202 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5203 glsl_get_length(type));
5204 }
5205
5206 assert(glsl_type_is_struct(type));
5207
5208 LLVMTypeRef member_types[glsl_get_length(type)];
5209
5210 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5211 member_types[i] =
5212 glsl_to_llvm_type(ctx,
5213 glsl_get_struct_field(type, i));
5214 }
5215
5216 return LLVMStructTypeInContext(ctx->context, member_types,
5217 glsl_get_length(type), false);
5218 }
5219
5220 static void
5221 setup_locals(struct ac_nir_context *ctx,
5222 struct nir_function *func)
5223 {
5224 int i, j;
5225 ctx->num_locals = 0;
5226 nir_foreach_variable(variable, &func->impl->locals) {
5227 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5228 variable->data.driver_location = ctx->num_locals * 4;
5229 ctx->num_locals += attrib_count;
5230 }
5231 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5232 if (!ctx->locals)
5233 return;
5234
5235 for (i = 0; i < ctx->num_locals; i++) {
5236 for (j = 0; j < 4; j++) {
5237 ctx->locals[i * 4 + j] =
5238 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5239 }
5240 }
5241 }
5242
5243 static void
5244 setup_shared(struct ac_nir_context *ctx,
5245 struct nir_shader *nir)
5246 {
5247 nir_foreach_variable(variable, &nir->shared) {
5248 LLVMValueRef shared =
5249 LLVMAddGlobalInAddressSpace(
5250 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5251 variable->name ? variable->name : "",
5252 LOCAL_ADDR_SPACE);
5253 _mesa_hash_table_insert(ctx->vars, variable, shared);
5254 }
5255 }
5256
5257 static LLVMValueRef
5258 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5259 {
5260 v = to_float(ctx, v);
5261 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5262 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5263 }
5264
5265
5266 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5267 LLVMValueRef src0, LLVMValueRef src1)
5268 {
5269 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5270 LLVMValueRef comp[2];
5271
5272 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5273 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5274 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5275 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5276 }
5277
5278 /* Initialize arguments for the shader export intrinsic */
5279 static void
5280 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5281 LLVMValueRef *values,
5282 unsigned target,
5283 struct ac_export_args *args)
5284 {
5285 /* Default is 0xf. Adjusted below depending on the format. */
5286 args->enabled_channels = 0xf;
5287
5288 /* Specify whether the EXEC mask represents the valid mask */
5289 args->valid_mask = 0;
5290
5291 /* Specify whether this is the last export */
5292 args->done = 0;
5293
5294 /* Specify the target we are exporting */
5295 args->target = target;
5296
5297 args->compr = false;
5298 args->out[0] = LLVMGetUndef(ctx->f32);
5299 args->out[1] = LLVMGetUndef(ctx->f32);
5300 args->out[2] = LLVMGetUndef(ctx->f32);
5301 args->out[3] = LLVMGetUndef(ctx->f32);
5302
5303 if (!values)
5304 return;
5305
5306 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5307 LLVMValueRef val[4];
5308 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5309 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5310 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5311 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5312
5313 switch(col_format) {
5314 case V_028714_SPI_SHADER_ZERO:
5315 args->enabled_channels = 0; /* writemask */
5316 args->target = V_008DFC_SQ_EXP_NULL;
5317 break;
5318
5319 case V_028714_SPI_SHADER_32_R:
5320 args->enabled_channels = 1;
5321 args->out[0] = values[0];
5322 break;
5323
5324 case V_028714_SPI_SHADER_32_GR:
5325 args->enabled_channels = 0x3;
5326 args->out[0] = values[0];
5327 args->out[1] = values[1];
5328 break;
5329
5330 case V_028714_SPI_SHADER_32_AR:
5331 args->enabled_channels = 0x9;
5332 args->out[0] = values[0];
5333 args->out[3] = values[3];
5334 break;
5335
5336 case V_028714_SPI_SHADER_FP16_ABGR:
5337 args->compr = 1;
5338
5339 for (unsigned chan = 0; chan < 2; chan++) {
5340 LLVMValueRef pack_args[2] = {
5341 values[2 * chan],
5342 values[2 * chan + 1]
5343 };
5344 LLVMValueRef packed;
5345
5346 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5347 args->out[chan] = packed;
5348 }
5349 break;
5350
5351 case V_028714_SPI_SHADER_UNORM16_ABGR:
5352 for (unsigned chan = 0; chan < 4; chan++) {
5353 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5354 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5355 LLVMConstReal(ctx->f32, 65535), "");
5356 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5357 LLVMConstReal(ctx->f32, 0.5), "");
5358 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5359 ctx->i32, "");
5360 }
5361
5362 args->compr = 1;
5363 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5364 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5365 break;
5366
5367 case V_028714_SPI_SHADER_SNORM16_ABGR:
5368 for (unsigned chan = 0; chan < 4; chan++) {
5369 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5370 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5371 LLVMConstReal(ctx->f32, 32767), "");
5372
5373 /* If positive, add 0.5, else add -0.5. */
5374 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5375 LLVMBuildSelect(ctx->builder,
5376 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5377 val[chan], ctx->f32zero, ""),
5378 LLVMConstReal(ctx->f32, 0.5),
5379 LLVMConstReal(ctx->f32, -0.5), ""), "");
5380 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5381 }
5382
5383 args->compr = 1;
5384 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5385 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5386 break;
5387
5388 case V_028714_SPI_SHADER_UINT16_ABGR: {
5389 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5390 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5391 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
5392
5393 for (unsigned chan = 0; chan < 4; chan++) {
5394 val[chan] = to_integer(&ctx->ac, values[chan]);
5395 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5396 }
5397
5398 args->compr = 1;
5399 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5400 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5401 break;
5402 }
5403
5404 case V_028714_SPI_SHADER_SINT16_ABGR: {
5405 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5406 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5407 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
5408 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5409 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->i32one;
5410 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
5411
5412 /* Clamp. */
5413 for (unsigned chan = 0; chan < 4; chan++) {
5414 val[chan] = to_integer(&ctx->ac, values[chan]);
5415 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5416 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5417 }
5418
5419 args->compr = 1;
5420 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5421 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5422 break;
5423 }
5424
5425 default:
5426 case V_028714_SPI_SHADER_32_ABGR:
5427 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5428 break;
5429 }
5430 } else
5431 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5432
5433 for (unsigned i = 0; i < 4; ++i)
5434 args->out[i] = to_float(&ctx->ac, args->out[i]);
5435 }
5436
5437 static void
5438 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5439 bool export_prim_id,
5440 struct ac_vs_output_info *outinfo)
5441 {
5442 uint32_t param_count = 0;
5443 unsigned target;
5444 unsigned pos_idx, num_pos_exports = 0;
5445 struct ac_export_args args, pos_args[4] = {};
5446 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5447 int i;
5448
5449 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5450 sizeof(outinfo->vs_output_param_offset));
5451
5452 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5453 LLVMValueRef slots[8];
5454 unsigned j;
5455
5456 if (outinfo->cull_dist_mask)
5457 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5458
5459 i = VARYING_SLOT_CLIP_DIST0;
5460 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5461 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5462 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5463
5464 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5465 slots[i] = LLVMGetUndef(ctx->f32);
5466
5467 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5468 target = V_008DFC_SQ_EXP_POS + 3;
5469 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5470 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5471 &args, sizeof(args));
5472 }
5473
5474 target = V_008DFC_SQ_EXP_POS + 2;
5475 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5476 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5477 &args, sizeof(args));
5478
5479 }
5480
5481 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5482 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5483 for (unsigned j = 0; j < 4; j++)
5484 pos_values[j] = LLVMBuildLoad(ctx->builder,
5485 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5486 }
5487 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5488
5489 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5490 outinfo->writes_pointsize = true;
5491 psize_value = LLVMBuildLoad(ctx->builder,
5492 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5493 }
5494
5495 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5496 outinfo->writes_layer = true;
5497 layer_value = LLVMBuildLoad(ctx->builder,
5498 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5499 }
5500
5501 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5502 outinfo->writes_viewport_index = true;
5503 viewport_index_value = LLVMBuildLoad(ctx->builder,
5504 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5505 }
5506
5507 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5508 (outinfo->writes_layer == true ? 4 : 0) |
5509 (outinfo->writes_viewport_index == true ? 8 : 0));
5510 if (mask) {
5511 pos_args[1].enabled_channels = mask;
5512 pos_args[1].valid_mask = 0;
5513 pos_args[1].done = 0;
5514 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5515 pos_args[1].compr = 0;
5516 pos_args[1].out[0] = ctx->f32zero; /* X */
5517 pos_args[1].out[1] = ctx->f32zero; /* Y */
5518 pos_args[1].out[2] = ctx->f32zero; /* Z */
5519 pos_args[1].out[3] = ctx->f32zero; /* W */
5520
5521 if (outinfo->writes_pointsize == true)
5522 pos_args[1].out[0] = psize_value;
5523 if (outinfo->writes_layer == true)
5524 pos_args[1].out[2] = layer_value;
5525 if (outinfo->writes_viewport_index == true)
5526 pos_args[1].out[3] = viewport_index_value;
5527 }
5528 for (i = 0; i < 4; i++) {
5529 if (pos_args[i].out[0])
5530 num_pos_exports++;
5531 }
5532
5533 pos_idx = 0;
5534 for (i = 0; i < 4; i++) {
5535 if (!pos_args[i].out[0])
5536 continue;
5537
5538 /* Specify the target we are exporting */
5539 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5540 if (pos_idx == num_pos_exports)
5541 pos_args[i].done = 1;
5542 ac_build_export(&ctx->ac, &pos_args[i]);
5543 }
5544
5545 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5546 LLVMValueRef values[4];
5547 if (!(ctx->output_mask & (1ull << i)))
5548 continue;
5549
5550 for (unsigned j = 0; j < 4; j++)
5551 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5552 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5553
5554 if (i == VARYING_SLOT_LAYER) {
5555 target = V_008DFC_SQ_EXP_PARAM + param_count;
5556 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5557 param_count++;
5558 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5559 target = V_008DFC_SQ_EXP_PARAM + param_count;
5560 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5561 param_count++;
5562 } else if (i >= VARYING_SLOT_VAR0) {
5563 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5564 target = V_008DFC_SQ_EXP_PARAM + param_count;
5565 outinfo->vs_output_param_offset[i] = param_count;
5566 param_count++;
5567 } else
5568 continue;
5569
5570 si_llvm_init_export_args(ctx, values, target, &args);
5571
5572 if (target >= V_008DFC_SQ_EXP_POS &&
5573 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5574 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5575 &args, sizeof(args));
5576 } else {
5577 ac_build_export(&ctx->ac, &args);
5578 }
5579 }
5580
5581 if (export_prim_id) {
5582 LLVMValueRef values[4];
5583 target = V_008DFC_SQ_EXP_PARAM + param_count;
5584 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5585 param_count++;
5586
5587 values[0] = ctx->vs_prim_id;
5588 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5589 ctx->shader_info->vs.vgpr_comp_cnt);
5590 for (unsigned j = 1; j < 4; j++)
5591 values[j] = ctx->f32zero;
5592 si_llvm_init_export_args(ctx, values, target, &args);
5593 ac_build_export(&ctx->ac, &args);
5594 outinfo->export_prim_id = true;
5595 }
5596
5597 outinfo->pos_exports = num_pos_exports;
5598 outinfo->param_exports = param_count;
5599 }
5600
5601 static void
5602 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5603 struct ac_es_output_info *outinfo)
5604 {
5605 int j;
5606 uint64_t max_output_written = 0;
5607 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5608 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5609 int param_index;
5610 int length = 4;
5611
5612 if (!(ctx->output_mask & (1ull << i)))
5613 continue;
5614
5615 if (i == VARYING_SLOT_CLIP_DIST0)
5616 length = ctx->num_output_clips + ctx->num_output_culls;
5617
5618 param_index = shader_io_get_unique_index(i);
5619
5620 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5621
5622 for (j = 0; j < length; j++) {
5623 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5624 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5625
5626 ac_build_buffer_store_dword(&ctx->ac,
5627 ctx->esgs_ring,
5628 out_val, 1,
5629 NULL, ctx->es2gs_offset,
5630 (4 * param_index + j) * 4,
5631 1, 1, true, true);
5632 }
5633 }
5634 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5635 }
5636
5637 static void
5638 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5639 {
5640 LLVMValueRef vertex_id = ctx->rel_auto_id;
5641 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5642 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5643 vertex_dw_stride, "");
5644
5645 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5646 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5647 int length = 4;
5648
5649 if (!(ctx->output_mask & (1ull << i)))
5650 continue;
5651
5652 if (i == VARYING_SLOT_CLIP_DIST0)
5653 length = ctx->num_output_clips + ctx->num_output_culls;
5654 int param = shader_io_get_unique_index(i);
5655 mark_tess_output(ctx, false, param);
5656 if (length > 4)
5657 mark_tess_output(ctx, false, param + 1);
5658 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5659 LLVMConstInt(ctx->i32, param * 4, false),
5660 "");
5661 for (unsigned j = 0; j < length; j++) {
5662 lds_store(ctx, dw_addr,
5663 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5664 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5665 }
5666 }
5667 }
5668
5669 struct ac_build_if_state
5670 {
5671 struct nir_to_llvm_context *ctx;
5672 LLVMValueRef condition;
5673 LLVMBasicBlockRef entry_block;
5674 LLVMBasicBlockRef true_block;
5675 LLVMBasicBlockRef false_block;
5676 LLVMBasicBlockRef merge_block;
5677 };
5678
5679 static LLVMBasicBlockRef
5680 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5681 {
5682 LLVMBasicBlockRef current_block;
5683 LLVMBasicBlockRef next_block;
5684 LLVMBasicBlockRef new_block;
5685
5686 /* get current basic block */
5687 current_block = LLVMGetInsertBlock(ctx->builder);
5688
5689 /* chqeck if there's another block after this one */
5690 next_block = LLVMGetNextBasicBlock(current_block);
5691 if (next_block) {
5692 /* insert the new block before the next block */
5693 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5694 }
5695 else {
5696 /* append new block after current block */
5697 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5698 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5699 }
5700 return new_block;
5701 }
5702
5703 static void
5704 ac_nir_build_if(struct ac_build_if_state *ifthen,
5705 struct nir_to_llvm_context *ctx,
5706 LLVMValueRef condition)
5707 {
5708 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5709
5710 memset(ifthen, 0, sizeof *ifthen);
5711 ifthen->ctx = ctx;
5712 ifthen->condition = condition;
5713 ifthen->entry_block = block;
5714
5715 /* create endif/merge basic block for the phi functions */
5716 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5717
5718 /* create/insert true_block before merge_block */
5719 ifthen->true_block =
5720 LLVMInsertBasicBlockInContext(ctx->context,
5721 ifthen->merge_block,
5722 "if-true-block");
5723
5724 /* successive code goes into the true block */
5725 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5726 }
5727
5728 /**
5729 * End a conditional.
5730 */
5731 static void
5732 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5733 {
5734 LLVMBuilderRef builder = ifthen->ctx->builder;
5735
5736 /* Insert branch to the merge block from current block */
5737 LLVMBuildBr(builder, ifthen->merge_block);
5738
5739 /*
5740 * Now patch in the various branch instructions.
5741 */
5742
5743 /* Insert the conditional branch instruction at the end of entry_block */
5744 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5745 if (ifthen->false_block) {
5746 /* we have an else clause */
5747 LLVMBuildCondBr(builder, ifthen->condition,
5748 ifthen->true_block, ifthen->false_block);
5749 }
5750 else {
5751 /* no else clause */
5752 LLVMBuildCondBr(builder, ifthen->condition,
5753 ifthen->true_block, ifthen->merge_block);
5754 }
5755
5756 /* Resume building code at end of the ifthen->merge_block */
5757 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5758 }
5759
5760 static void
5761 write_tess_factors(struct nir_to_llvm_context *ctx)
5762 {
5763 unsigned stride, outer_comps, inner_comps;
5764 struct ac_build_if_state if_ctx, inner_if_ctx;
5765 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
5766 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
5767 unsigned tess_inner_index, tess_outer_index;
5768 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5769 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5770 int i;
5771 emit_barrier(ctx);
5772
5773 switch (ctx->options->key.tcs.primitive_mode) {
5774 case GL_ISOLINES:
5775 stride = 2;
5776 outer_comps = 2;
5777 inner_comps = 0;
5778 break;
5779 case GL_TRIANGLES:
5780 stride = 4;
5781 outer_comps = 3;
5782 inner_comps = 1;
5783 break;
5784 case GL_QUADS:
5785 stride = 6;
5786 outer_comps = 4;
5787 inner_comps = 2;
5788 break;
5789 default:
5790 return;
5791 }
5792
5793 ac_nir_build_if(&if_ctx, ctx,
5794 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5795 invocation_id, ctx->i32zero, ""));
5796
5797 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5798 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5799
5800 mark_tess_output(ctx, true, tess_inner_index);
5801 mark_tess_output(ctx, true, tess_outer_index);
5802 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5803 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5804 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5805 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5806 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5807
5808 for (i = 0; i < 4; i++) {
5809 inner[i] = LLVMGetUndef(ctx->i32);
5810 outer[i] = LLVMGetUndef(ctx->i32);
5811 }
5812
5813 // LINES reverseal
5814 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5815 outer[0] = out[1] = lds_load(ctx, lds_outer);
5816 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5817 LLVMConstInt(ctx->i32, 1, false), "");
5818 outer[1] = out[0] = lds_load(ctx, lds_outer);
5819 } else {
5820 for (i = 0; i < outer_comps; i++) {
5821 outer[i] = out[i] =
5822 lds_load(ctx, lds_outer);
5823 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5824 LLVMConstInt(ctx->i32, 1, false), "");
5825 }
5826 for (i = 0; i < inner_comps; i++) {
5827 inner[i] = out[outer_comps+i] =
5828 lds_load(ctx, lds_inner);
5829 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5830 LLVMConstInt(ctx->i32, 1, false), "");
5831 }
5832 }
5833
5834 /* Convert the outputs to vectors for stores. */
5835 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5836 vec1 = NULL;
5837
5838 if (stride > 4)
5839 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5840
5841
5842 buffer = ctx->hs_ring_tess_factor;
5843 tf_base = ctx->tess_factor_offset;
5844 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5845 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5846
5847 ac_nir_build_if(&inner_if_ctx, ctx,
5848 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5849 rel_patch_id, ctx->i32zero, ""));
5850
5851 /* Store the dynamic HS control word. */
5852 ac_build_buffer_store_dword(&ctx->ac, buffer,
5853 LLVMConstInt(ctx->i32, 0x80000000, false),
5854 1, ctx->i32zero, tf_base,
5855 0, 1, 0, true, false);
5856 ac_nir_build_endif(&inner_if_ctx);
5857
5858 /* Store the tessellation factors. */
5859 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5860 MIN2(stride, 4), byteoffset, tf_base,
5861 4, 1, 0, true, false);
5862 if (vec1)
5863 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5864 stride - 4, byteoffset, tf_base,
5865 20, 1, 0, true, false);
5866
5867 //TODO store to offchip for TES to read - only if TES reads them
5868 if (1) {
5869 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5870 LLVMValueRef tf_inner_offset;
5871 unsigned param_outer, param_inner;
5872
5873 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5874 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5875 LLVMConstInt(ctx->i32, param_outer, 0));
5876
5877 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5878 util_next_power_of_two(outer_comps));
5879
5880 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5881 outer_comps, tf_outer_offset,
5882 ctx->oc_lds, 0, 1, 0, true, false);
5883 if (inner_comps) {
5884 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5885 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5886 LLVMConstInt(ctx->i32, param_inner, 0));
5887
5888 inner_vec = inner_comps == 1 ? inner[0] :
5889 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5890 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5891 inner_comps, tf_inner_offset,
5892 ctx->oc_lds, 0, 1, 0, true, false);
5893 }
5894 }
5895 ac_nir_build_endif(&if_ctx);
5896 }
5897
5898 static void
5899 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5900 {
5901 write_tess_factors(ctx);
5902 }
5903
5904 static bool
5905 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5906 LLVMValueRef *color, unsigned param, bool is_last,
5907 struct ac_export_args *args)
5908 {
5909 /* Export */
5910 si_llvm_init_export_args(ctx, color, param,
5911 args);
5912
5913 if (is_last) {
5914 args->valid_mask = 1; /* whether the EXEC mask is valid */
5915 args->done = 1; /* DONE bit */
5916 } else if (!args->enabled_channels)
5917 return false; /* unnecessary NULL export */
5918
5919 return true;
5920 }
5921
5922 static void
5923 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5924 LLVMValueRef depth, LLVMValueRef stencil,
5925 LLVMValueRef samplemask)
5926 {
5927 struct ac_export_args args;
5928
5929 args.enabled_channels = 0;
5930 args.valid_mask = 1;
5931 args.done = 1;
5932 args.target = V_008DFC_SQ_EXP_MRTZ;
5933 args.compr = false;
5934
5935 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5936 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5937 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5938 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5939
5940 if (depth) {
5941 args.out[0] = depth;
5942 args.enabled_channels |= 0x1;
5943 }
5944
5945 if (stencil) {
5946 args.out[1] = stencil;
5947 args.enabled_channels |= 0x2;
5948 }
5949
5950 if (samplemask) {
5951 args.out[2] = samplemask;
5952 args.enabled_channels |= 0x4;
5953 }
5954
5955 /* SI (except OLAND and HAINAN) has a bug that it only looks
5956 * at the X writemask component. */
5957 if (ctx->options->chip_class == SI &&
5958 ctx->options->family != CHIP_OLAND &&
5959 ctx->options->family != CHIP_HAINAN)
5960 args.enabled_channels |= 0x1;
5961
5962 ac_build_export(&ctx->ac, &args);
5963 }
5964
5965 static void
5966 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5967 {
5968 unsigned index = 0;
5969 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5970 struct ac_export_args color_args[8];
5971
5972 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5973 LLVMValueRef values[4];
5974
5975 if (!(ctx->output_mask & (1ull << i)))
5976 continue;
5977
5978 if (i == FRAG_RESULT_DEPTH) {
5979 ctx->shader_info->fs.writes_z = true;
5980 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5981 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5982 } else if (i == FRAG_RESULT_STENCIL) {
5983 ctx->shader_info->fs.writes_stencil = true;
5984 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5985 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5986 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5987 ctx->shader_info->fs.writes_sample_mask = true;
5988 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5989 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5990 } else {
5991 bool last = false;
5992 for (unsigned j = 0; j < 4; j++)
5993 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5994 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5995
5996 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5997 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5998
5999 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6000 if (ret)
6001 index++;
6002 }
6003 }
6004
6005 for (unsigned i = 0; i < index; i++)
6006 ac_build_export(&ctx->ac, &color_args[i]);
6007 if (depth || stencil || samplemask)
6008 si_export_mrt_z(ctx, depth, stencil, samplemask);
6009 else if (!index) {
6010 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6011 ac_build_export(&ctx->ac, &color_args[0]);
6012 }
6013
6014 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6015 }
6016
6017 static void
6018 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6019 {
6020 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6021 }
6022
6023 static void
6024 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6025 LLVMValueRef *addrs)
6026 {
6027 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6028
6029 switch (ctx->stage) {
6030 case MESA_SHADER_VERTEX:
6031 if (ctx->options->key.vs.as_ls)
6032 handle_ls_outputs_post(ctx);
6033 else if (ctx->options->key.vs.as_es)
6034 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6035 else
6036 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6037 &ctx->shader_info->vs.outinfo);
6038 break;
6039 case MESA_SHADER_FRAGMENT:
6040 handle_fs_outputs_post(ctx);
6041 break;
6042 case MESA_SHADER_GEOMETRY:
6043 emit_gs_epilogue(ctx);
6044 break;
6045 case MESA_SHADER_TESS_CTRL:
6046 handle_tcs_outputs_post(ctx);
6047 break;
6048 case MESA_SHADER_TESS_EVAL:
6049 if (ctx->options->key.tes.as_es)
6050 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6051 else
6052 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6053 &ctx->shader_info->tes.outinfo);
6054 break;
6055 default:
6056 break;
6057 }
6058 }
6059
6060 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6061 {
6062 LLVMPassManagerRef passmgr;
6063 /* Create the pass manager */
6064 passmgr = LLVMCreateFunctionPassManagerForModule(
6065 ctx->module);
6066
6067 /* This pass should eliminate all the load and store instructions */
6068 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6069
6070 /* Add some optimization passes */
6071 LLVMAddScalarReplAggregatesPass(passmgr);
6072 LLVMAddLICMPass(passmgr);
6073 LLVMAddAggressiveDCEPass(passmgr);
6074 LLVMAddCFGSimplificationPass(passmgr);
6075 LLVMAddInstructionCombiningPass(passmgr);
6076
6077 /* Run the pass */
6078 LLVMInitializeFunctionPassManager(passmgr);
6079 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6080 LLVMFinalizeFunctionPassManager(passmgr);
6081
6082 LLVMDisposeBuilder(ctx->builder);
6083 LLVMDisposePassManager(passmgr);
6084 }
6085
6086 static void
6087 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6088 {
6089 struct ac_vs_output_info *outinfo;
6090
6091 switch (ctx->stage) {
6092 case MESA_SHADER_FRAGMENT:
6093 case MESA_SHADER_COMPUTE:
6094 case MESA_SHADER_TESS_CTRL:
6095 case MESA_SHADER_GEOMETRY:
6096 return;
6097 case MESA_SHADER_VERTEX:
6098 if (ctx->options->key.vs.as_ls ||
6099 ctx->options->key.vs.as_es)
6100 return;
6101 outinfo = &ctx->shader_info->vs.outinfo;
6102 break;
6103 case MESA_SHADER_TESS_EVAL:
6104 if (ctx->options->key.vs.as_es)
6105 return;
6106 outinfo = &ctx->shader_info->tes.outinfo;
6107 break;
6108 default:
6109 unreachable("Unhandled shader type");
6110 }
6111
6112 ac_optimize_vs_outputs(&ctx->ac,
6113 ctx->main_function,
6114 outinfo->vs_output_param_offset,
6115 VARYING_SLOT_MAX,
6116 &outinfo->param_exports);
6117 }
6118
6119 static void
6120 ac_setup_rings(struct nir_to_llvm_context *ctx)
6121 {
6122 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6123 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6124 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6125 }
6126
6127 if (ctx->is_gs_copy_shader) {
6128 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6129 }
6130 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6131 LLVMValueRef tmp;
6132 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6133 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6134
6135 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6136
6137 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6138 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6139 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6140 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6141 }
6142
6143 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6144 ctx->stage == MESA_SHADER_TESS_EVAL) {
6145 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6146 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6147 }
6148 }
6149
6150 static unsigned
6151 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6152 const struct nir_shader *nir)
6153 {
6154 switch (nir->stage) {
6155 case MESA_SHADER_TESS_CTRL:
6156 return chip_class >= CIK ? 128 : 64;
6157 case MESA_SHADER_GEOMETRY:
6158 return 64;
6159 case MESA_SHADER_COMPUTE:
6160 break;
6161 default:
6162 return 0;
6163 }
6164
6165 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6166 nir->info.cs.local_size[1] *
6167 nir->info.cs.local_size[2];
6168 return max_workgroup_size;
6169 }
6170
6171 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6172 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6173 {
6174 struct ac_nir_context ctx = {};
6175 struct nir_function *func;
6176
6177 ctx.ac = *ac;
6178 ctx.abi = abi;
6179
6180 ctx.nctx = nctx;
6181 if (nctx)
6182 nctx->nir = &ctx;
6183
6184 ctx.stage = nir->stage;
6185
6186 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6187
6188 nir_foreach_variable(variable, &nir->outputs)
6189 handle_shader_output_decl(&ctx, nir, variable);
6190
6191 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6192 _mesa_key_pointer_equal);
6193 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6194 _mesa_key_pointer_equal);
6195 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6196 _mesa_key_pointer_equal);
6197
6198 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6199
6200 setup_locals(&ctx, func);
6201
6202 if (nir->stage == MESA_SHADER_COMPUTE)
6203 setup_shared(&ctx, nir);
6204
6205 visit_cf_list(&ctx, &func->impl->body);
6206 phi_post_pass(&ctx);
6207
6208 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6209 ctx.outputs);
6210
6211 free(ctx.locals);
6212 ralloc_free(ctx.defs);
6213 ralloc_free(ctx.phis);
6214 ralloc_free(ctx.vars);
6215
6216 if (nctx)
6217 nctx->nir = NULL;
6218 }
6219
6220 static
6221 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6222 struct nir_shader *nir,
6223 struct ac_shader_variant_info *shader_info,
6224 const struct ac_nir_compiler_options *options)
6225 {
6226 struct nir_to_llvm_context ctx = {0};
6227 unsigned i;
6228 ctx.options = options;
6229 ctx.shader_info = shader_info;
6230 ctx.context = LLVMContextCreate();
6231 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6232
6233 ac_llvm_context_init(&ctx.ac, ctx.context);
6234 ctx.ac.module = ctx.module;
6235
6236 memset(shader_info, 0, sizeof(*shader_info));
6237
6238 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6239
6240 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6241
6242 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6243 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6244 LLVMSetDataLayout(ctx.module, data_layout_str);
6245 LLVMDisposeTargetData(data_layout);
6246 LLVMDisposeMessage(data_layout_str);
6247
6248 setup_types(&ctx);
6249
6250 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6251 ctx.ac.builder = ctx.builder;
6252 ctx.stage = nir->stage;
6253 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6254
6255 for (i = 0; i < AC_UD_MAX_SETS; i++)
6256 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6257 for (i = 0; i < AC_UD_MAX_UD; i++)
6258 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6259
6260 create_function(&ctx);
6261
6262 if (nir->stage == MESA_SHADER_GEOMETRY) {
6263 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6264
6265 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6266 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6267 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6268 } else if (nir->stage == MESA_SHADER_VERTEX) {
6269 if (shader_info->info.vs.needs_instance_id) {
6270 ctx.shader_info->vs.vgpr_comp_cnt =
6271 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6272 }
6273 } else if (nir->stage == MESA_SHADER_FRAGMENT) {
6274 shader_info->fs.can_discard = nir->info.fs.uses_discard;
6275 }
6276
6277 ac_setup_rings(&ctx);
6278
6279 ctx.num_output_clips = nir->info.clip_distance_array_size;
6280 ctx.num_output_culls = nir->info.cull_distance_array_size;
6281
6282 nir_foreach_variable(variable, &nir->inputs)
6283 handle_shader_input_decl(&ctx, variable);
6284
6285 if (nir->stage == MESA_SHADER_FRAGMENT)
6286 handle_fs_inputs_pre(&ctx, nir);
6287
6288 ctx.abi.chip_class = options->chip_class;
6289 ctx.abi.inputs = &ctx.inputs[0];
6290 ctx.abi.emit_outputs = handle_shader_outputs_post;
6291 ctx.abi.load_ssbo = radv_load_ssbo;
6292 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6293
6294 nir_foreach_variable(variable, &nir->outputs)
6295 scan_shader_output_decl(&ctx, variable);
6296
6297 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6298
6299 LLVMBuildRetVoid(ctx.builder);
6300
6301 ac_llvm_finalize_module(&ctx);
6302
6303 ac_nir_eliminate_const_vs_outputs(&ctx);
6304
6305 if (nir->stage == MESA_SHADER_GEOMETRY) {
6306 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6307 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6308 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6309 nir->info.gs.vertices_out;
6310 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6311 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6312 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6313 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6314 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6315 }
6316
6317 return ctx.module;
6318 }
6319
6320 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6321 {
6322 unsigned *retval = (unsigned *)context;
6323 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6324 char *description = LLVMGetDiagInfoDescription(di);
6325
6326 if (severity == LLVMDSError) {
6327 *retval = 1;
6328 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6329 description);
6330 }
6331
6332 LLVMDisposeMessage(description);
6333 }
6334
6335 static unsigned ac_llvm_compile(LLVMModuleRef M,
6336 struct ac_shader_binary *binary,
6337 LLVMTargetMachineRef tm)
6338 {
6339 unsigned retval = 0;
6340 char *err;
6341 LLVMContextRef llvm_ctx;
6342 LLVMMemoryBufferRef out_buffer;
6343 unsigned buffer_size;
6344 const char *buffer_data;
6345 LLVMBool mem_err;
6346
6347 /* Setup Diagnostic Handler*/
6348 llvm_ctx = LLVMGetModuleContext(M);
6349
6350 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6351 &retval);
6352
6353 /* Compile IR*/
6354 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6355 &err, &out_buffer);
6356
6357 /* Process Errors/Warnings */
6358 if (mem_err) {
6359 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6360 free(err);
6361 retval = 1;
6362 goto out;
6363 }
6364
6365 /* Extract Shader Code*/
6366 buffer_size = LLVMGetBufferSize(out_buffer);
6367 buffer_data = LLVMGetBufferStart(out_buffer);
6368
6369 ac_elf_read(buffer_data, buffer_size, binary);
6370
6371 /* Clean up */
6372 LLVMDisposeMemoryBuffer(out_buffer);
6373
6374 out:
6375 return retval;
6376 }
6377
6378 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6379 LLVMModuleRef llvm_module,
6380 struct ac_shader_binary *binary,
6381 struct ac_shader_config *config,
6382 struct ac_shader_variant_info *shader_info,
6383 gl_shader_stage stage,
6384 bool dump_shader, bool supports_spill)
6385 {
6386 if (dump_shader)
6387 ac_dump_module(llvm_module);
6388
6389 memset(binary, 0, sizeof(*binary));
6390 int v = ac_llvm_compile(llvm_module, binary, tm);
6391 if (v) {
6392 fprintf(stderr, "compile failed\n");
6393 }
6394
6395 if (dump_shader)
6396 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6397
6398 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6399
6400 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6401 LLVMDisposeModule(llvm_module);
6402 LLVMContextDispose(ctx);
6403
6404 if (stage == MESA_SHADER_FRAGMENT) {
6405 shader_info->num_input_vgprs = 0;
6406 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6407 shader_info->num_input_vgprs += 2;
6408 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6409 shader_info->num_input_vgprs += 2;
6410 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6411 shader_info->num_input_vgprs += 2;
6412 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6413 shader_info->num_input_vgprs += 3;
6414 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6415 shader_info->num_input_vgprs += 2;
6416 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6417 shader_info->num_input_vgprs += 2;
6418 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6419 shader_info->num_input_vgprs += 2;
6420 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6421 shader_info->num_input_vgprs += 1;
6422 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6423 shader_info->num_input_vgprs += 1;
6424 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6425 shader_info->num_input_vgprs += 1;
6426 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6427 shader_info->num_input_vgprs += 1;
6428 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6429 shader_info->num_input_vgprs += 1;
6430 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6431 shader_info->num_input_vgprs += 1;
6432 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6433 shader_info->num_input_vgprs += 1;
6434 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6435 shader_info->num_input_vgprs += 1;
6436 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6437 shader_info->num_input_vgprs += 1;
6438 }
6439 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6440
6441 /* +3 for scratch wave offset and VCC */
6442 config->num_sgprs = MAX2(config->num_sgprs,
6443 shader_info->num_input_sgprs + 3);
6444 }
6445
6446 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6447 struct ac_shader_binary *binary,
6448 struct ac_shader_config *config,
6449 struct ac_shader_variant_info *shader_info,
6450 struct nir_shader *nir,
6451 const struct ac_nir_compiler_options *options,
6452 bool dump_shader)
6453 {
6454
6455 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6456 options);
6457
6458 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6459 switch (nir->stage) {
6460 case MESA_SHADER_COMPUTE:
6461 for (int i = 0; i < 3; ++i)
6462 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6463 break;
6464 case MESA_SHADER_FRAGMENT:
6465 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6466 break;
6467 case MESA_SHADER_GEOMETRY:
6468 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6469 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6470 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6471 shader_info->gs.invocations = nir->info.gs.invocations;
6472 break;
6473 case MESA_SHADER_TESS_EVAL:
6474 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6475 shader_info->tes.spacing = nir->info.tess.spacing;
6476 shader_info->tes.ccw = nir->info.tess.ccw;
6477 shader_info->tes.point_mode = nir->info.tess.point_mode;
6478 shader_info->tes.as_es = options->key.tes.as_es;
6479 break;
6480 case MESA_SHADER_TESS_CTRL:
6481 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6482 break;
6483 case MESA_SHADER_VERTEX:
6484 shader_info->vs.as_es = options->key.vs.as_es;
6485 shader_info->vs.as_ls = options->key.vs.as_ls;
6486 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6487 if (options->key.vs.as_ls)
6488 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6489 break;
6490 default:
6491 break;
6492 }
6493 }
6494
6495 static void
6496 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6497 {
6498 LLVMValueRef args[9];
6499 args[0] = ctx->gsvs_ring;
6500 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6501 args[3] = ctx->i32zero;
6502 args[4] = ctx->i32one; /* OFFEN */
6503 args[5] = ctx->i32zero; /* IDXEN */
6504 args[6] = ctx->i32one; /* GLC */
6505 args[7] = ctx->i32one; /* SLC */
6506 args[8] = ctx->i32zero; /* TFE */
6507
6508 int idx = 0;
6509
6510 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6511 int length = 4;
6512 int slot = idx;
6513 int slot_inc = 1;
6514 if (!(ctx->output_mask & (1ull << i)))
6515 continue;
6516
6517 if (i == VARYING_SLOT_CLIP_DIST0) {
6518 /* unpack clip and cull from a single set of slots */
6519 length = ctx->num_output_clips + ctx->num_output_culls;
6520 if (length > 4)
6521 slot_inc = 2;
6522 }
6523
6524 for (unsigned j = 0; j < length; j++) {
6525 LLVMValueRef value;
6526 args[2] = LLVMConstInt(ctx->i32,
6527 (slot * 4 + j) *
6528 ctx->gs_max_out_vertices * 16 * 4, false);
6529
6530 value = ac_build_intrinsic(&ctx->ac,
6531 "llvm.SI.buffer.load.dword.i32.i32",
6532 ctx->i32, args, 9,
6533 AC_FUNC_ATTR_READONLY |
6534 AC_FUNC_ATTR_LEGACY);
6535
6536 LLVMBuildStore(ctx->builder,
6537 to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6538 }
6539 idx += slot_inc;
6540 }
6541 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6542 }
6543
6544 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6545 struct nir_shader *geom_shader,
6546 struct ac_shader_binary *binary,
6547 struct ac_shader_config *config,
6548 struct ac_shader_variant_info *shader_info,
6549 const struct ac_nir_compiler_options *options,
6550 bool dump_shader)
6551 {
6552 struct nir_to_llvm_context ctx = {0};
6553 ctx.context = LLVMContextCreate();
6554 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6555 ctx.options = options;
6556 ctx.shader_info = shader_info;
6557
6558 ac_llvm_context_init(&ctx.ac, ctx.context);
6559 ctx.ac.module = ctx.module;
6560
6561 ctx.is_gs_copy_shader = true;
6562 LLVMSetTarget(ctx.module, "amdgcn--");
6563 setup_types(&ctx);
6564
6565 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6566 ctx.ac.builder = ctx.builder;
6567 ctx.stage = MESA_SHADER_VERTEX;
6568
6569 create_function(&ctx);
6570
6571 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6572 ac_setup_rings(&ctx);
6573
6574 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6575 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6576
6577 struct ac_nir_context nir_ctx = {};
6578 nir_ctx.ac = ctx.ac;
6579 nir_ctx.abi = &ctx.abi;
6580
6581 nir_ctx.nctx = &ctx;
6582 ctx.nir = &nir_ctx;
6583
6584 nir_foreach_variable(variable, &geom_shader->outputs) {
6585 scan_shader_output_decl(&ctx, variable);
6586 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6587 }
6588
6589 ac_gs_copy_shader_emit(&ctx);
6590
6591 ctx.nir = NULL;
6592
6593 LLVMBuildRetVoid(ctx.builder);
6594
6595 ac_llvm_finalize_module(&ctx);
6596
6597 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6598 MESA_SHADER_VERTEX,
6599 dump_shader, options->supports_spill);
6600 }