2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
38 enum radeon_llvm_calling_convention
{
39 RADEON_LLVM_AMDGPU_VS
= 87,
40 RADEON_LLVM_AMDGPU_GS
= 88,
41 RADEON_LLVM_AMDGPU_PS
= 89,
42 RADEON_LLVM_AMDGPU_CS
= 90,
43 RADEON_LLVM_AMDGPU_HS
= 93,
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 struct ac_nir_context
{
49 struct ac_llvm_context ac
;
50 struct ac_shader_abi
*abi
;
52 gl_shader_stage stage
;
54 struct hash_table
*defs
;
55 struct hash_table
*phis
;
56 struct hash_table
*vars
;
58 LLVMValueRef main_function
;
59 LLVMBasicBlockRef continue_block
;
60 LLVMBasicBlockRef break_block
;
66 struct radv_shader_context
{
67 struct ac_llvm_context ac
;
68 const struct ac_nir_compiler_options
*options
;
69 struct ac_shader_variant_info
*shader_info
;
70 struct ac_shader_abi abi
;
72 unsigned max_workgroup_size
;
73 LLVMContextRef context
;
74 LLVMValueRef main_function
;
76 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
77 LLVMValueRef ring_offsets
;
79 LLVMValueRef vertex_buffers
;
80 LLVMValueRef rel_auto_id
;
81 LLVMValueRef vs_prim_id
;
82 LLVMValueRef ls_out_layout
;
83 LLVMValueRef es2gs_offset
;
85 LLVMValueRef tcs_offchip_layout
;
86 LLVMValueRef tcs_out_offsets
;
87 LLVMValueRef tcs_out_layout
;
88 LLVMValueRef tcs_in_layout
;
90 LLVMValueRef merged_wave_info
;
91 LLVMValueRef tess_factor_offset
;
92 LLVMValueRef tes_rel_patch_id
;
96 LLVMValueRef gsvs_ring_stride
;
97 LLVMValueRef gsvs_num_entries
;
98 LLVMValueRef gs2vs_offset
;
99 LLVMValueRef gs_wave_id
;
100 LLVMValueRef gs_vtx_offset
[6];
102 LLVMValueRef esgs_ring
;
103 LLVMValueRef gsvs_ring
;
104 LLVMValueRef hs_ring_tess_offchip
;
105 LLVMValueRef hs_ring_tess_factor
;
107 LLVMValueRef sample_pos_offset
;
108 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
109 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
111 gl_shader_stage stage
;
113 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
116 uint64_t output_mask
;
117 uint8_t num_output_clips
;
118 uint8_t num_output_culls
;
120 bool is_gs_copy_shader
;
121 LLVMValueRef gs_next_vertex
;
122 unsigned gs_max_out_vertices
;
124 unsigned tes_primitive_mode
;
125 uint64_t tess_outputs_written
;
126 uint64_t tess_patch_outputs_written
;
128 uint32_t tcs_patch_outputs_read
;
129 uint64_t tcs_outputs_read
;
130 uint32_t tcs_vertices_per_patch
;
133 static inline struct radv_shader_context
*
134 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
136 struct radv_shader_context
*ctx
= NULL
;
137 return container_of(abi
, ctx
, abi
);
140 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
141 const nir_deref_var
*deref
,
142 enum ac_descriptor_type desc_type
,
143 const nir_tex_instr
*instr
,
144 bool image
, bool write
);
146 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
148 return (index
* 4) + chan
;
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
153 /* handle patch indices separate */
154 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
156 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
158 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
159 return 2 + (slot
- VARYING_SLOT_PATCH0
);
161 if (slot
== VARYING_SLOT_POS
)
163 if (slot
== VARYING_SLOT_PSIZ
)
165 if (slot
== VARYING_SLOT_CLIP_DIST0
)
167 /* 3 is reserved for clip dist as well */
168 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
169 return 4 + (slot
- VARYING_SLOT_VAR0
);
170 unreachable("illegal slot in get unique index\n");
173 static void set_llvm_calling_convention(LLVMValueRef func
,
174 gl_shader_stage stage
)
176 enum radeon_llvm_calling_convention calling_conv
;
179 case MESA_SHADER_VERTEX
:
180 case MESA_SHADER_TESS_EVAL
:
181 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
183 case MESA_SHADER_GEOMETRY
:
184 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
186 case MESA_SHADER_TESS_CTRL
:
187 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
189 case MESA_SHADER_FRAGMENT
:
190 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
192 case MESA_SHADER_COMPUTE
:
193 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
196 unreachable("Unhandle shader type");
199 LLVMSetFunctionCallConv(func
, calling_conv
);
204 LLVMTypeRef types
[MAX_ARGS
];
205 LLVMValueRef
*assign
[MAX_ARGS
];
206 unsigned array_params_mask
;
209 uint8_t num_sgprs_used
;
210 uint8_t num_vgprs_used
;
213 enum ac_arg_regfile
{
219 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
220 LLVMValueRef
*param_ptr
)
222 assert(info
->count
< MAX_ARGS
);
224 info
->assign
[info
->count
] = param_ptr
;
225 info
->types
[info
->count
] = type
;
228 if (regfile
== ARG_SGPR
) {
229 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
232 assert(regfile
== ARG_VGPR
);
233 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
238 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
240 info
->array_params_mask
|= (1 << info
->count
);
241 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
244 static void assign_arguments(LLVMValueRef main_function
,
245 struct arg_info
*info
)
248 for (i
= 0; i
< info
->count
; i
++) {
250 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
255 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
256 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
257 unsigned num_return_elems
,
258 struct arg_info
*args
,
259 unsigned max_workgroup_size
,
262 LLVMTypeRef main_function_type
, ret_type
;
263 LLVMBasicBlockRef main_function_body
;
265 if (num_return_elems
)
266 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
267 num_return_elems
, true);
269 ret_type
= LLVMVoidTypeInContext(ctx
);
271 /* Setup the function */
273 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
274 LLVMValueRef main_function
=
275 LLVMAddFunction(module
, "main", main_function_type
);
277 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
278 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
280 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
281 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
282 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
284 if (args
->array_params_mask
& (1 << i
)) {
285 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
286 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
287 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
291 if (max_workgroup_size
) {
292 ac_llvm_add_target_dep_function_attr(main_function
,
293 "amdgpu-max-work-group-size",
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function
,
299 "less-precise-fpmad",
301 LLVMAddTargetDependentFunctionAttr(main_function
,
304 LLVMAddTargetDependentFunctionAttr(main_function
,
307 LLVMAddTargetDependentFunctionAttr(main_function
,
310 LLVMAddTargetDependentFunctionAttr(main_function
,
311 "no-signed-zeros-fp-math",
314 return main_function
;
317 static LLVMValueRef
unpack_param(struct ac_llvm_context
*ctx
,
318 LLVMValueRef param
, unsigned rshift
,
321 LLVMValueRef value
= param
;
323 value
= LLVMBuildLShr(ctx
->builder
, value
,
324 LLVMConstInt(ctx
->i32
, rshift
, false), "");
326 if (rshift
+ bitwidth
< 32) {
327 unsigned mask
= (1 << bitwidth
) - 1;
328 value
= LLVMBuildAnd(ctx
->builder
, value
,
329 LLVMConstInt(ctx
->i32
, mask
, false), "");
334 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
336 switch (ctx
->stage
) {
337 case MESA_SHADER_TESS_CTRL
:
338 return unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
339 case MESA_SHADER_TESS_EVAL
:
340 return ctx
->tes_rel_patch_id
;
343 unreachable("Illegal stage");
347 /* Tessellation shaders pass outputs to the next shader using LDS.
349 * LS outputs = TCS inputs
350 * TCS outputs = TES inputs
353 * - TCS inputs for patch 0
354 * - TCS inputs for patch 1
355 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
357 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
358 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
359 * - TCS outputs for patch 1
360 * - Per-patch TCS outputs for patch 1
361 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
362 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
365 * All three shaders VS(LS), TCS, TES share the same LDS space.
368 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
370 if (ctx
->stage
== MESA_SHADER_VERTEX
)
371 return unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
372 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
373 return unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
381 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
383 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
387 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
389 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
393 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
395 return LLVMBuildMul(ctx
->ac
.builder
,
396 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
397 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
401 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
403 return LLVMBuildMul(ctx
->ac
.builder
,
404 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
405 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
409 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
411 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
412 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
414 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
418 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
420 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
421 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
422 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
424 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_offset
,
425 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
431 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
433 LLVMValueRef patch0_patch_data_offset
=
434 get_tcs_out_patch0_patch_data_offset(ctx
);
435 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
436 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
438 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_patch_data_offset
,
439 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
445 set_loc(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
,
446 uint32_t indirect_offset
)
448 ud_info
->sgpr_idx
= *sgpr_idx
;
449 ud_info
->num_sgprs
= num_sgprs
;
450 ud_info
->indirect
= indirect_offset
> 0;
451 ud_info
->indirect_offset
= indirect_offset
;
452 *sgpr_idx
+= num_sgprs
;
456 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
459 struct ac_userdata_info
*ud_info
=
460 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
463 set_loc(ud_info
, sgpr_idx
, num_sgprs
, 0);
467 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
468 uint32_t indirect_offset
)
470 struct ac_userdata_info
*ud_info
=
471 &ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[idx
];
474 set_loc(ud_info
, sgpr_idx
, 2, indirect_offset
);
477 struct user_sgpr_info
{
478 bool need_ring_offsets
;
480 bool indirect_all_descriptor_sets
;
483 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
484 gl_shader_stage stage
)
487 case MESA_SHADER_VERTEX
:
488 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
489 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
492 case MESA_SHADER_TESS_EVAL
:
493 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
496 case MESA_SHADER_GEOMETRY
:
497 case MESA_SHADER_TESS_CTRL
:
498 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
508 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
512 count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
513 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
518 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
519 gl_shader_stage stage
,
520 bool has_previous_stage
,
521 gl_shader_stage previous_stage
,
522 bool needs_view_index
,
523 struct user_sgpr_info
*user_sgpr_info
)
525 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
527 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
528 if (stage
== MESA_SHADER_GEOMETRY
||
529 stage
== MESA_SHADER_VERTEX
||
530 stage
== MESA_SHADER_TESS_CTRL
||
531 stage
== MESA_SHADER_TESS_EVAL
||
532 ctx
->is_gs_copy_shader
)
533 user_sgpr_info
->need_ring_offsets
= true;
535 if (stage
== MESA_SHADER_FRAGMENT
&&
536 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
537 user_sgpr_info
->need_ring_offsets
= true;
539 /* 2 user sgprs will nearly always be allocated for scratch/rings */
540 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
541 user_sgpr_info
->sgpr_count
+= 2;
545 case MESA_SHADER_COMPUTE
:
546 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
547 user_sgpr_info
->sgpr_count
+= 3;
549 case MESA_SHADER_FRAGMENT
:
550 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
552 case MESA_SHADER_VERTEX
:
553 if (!ctx
->is_gs_copy_shader
)
554 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
555 if (ctx
->options
->key
.vs
.as_ls
)
556 user_sgpr_info
->sgpr_count
++;
558 case MESA_SHADER_TESS_CTRL
:
559 if (has_previous_stage
) {
560 if (previous_stage
== MESA_SHADER_VERTEX
)
561 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
562 user_sgpr_info
->sgpr_count
++;
564 user_sgpr_info
->sgpr_count
+= 4;
566 case MESA_SHADER_TESS_EVAL
:
567 user_sgpr_info
->sgpr_count
+= 1;
569 case MESA_SHADER_GEOMETRY
:
570 if (has_previous_stage
) {
571 if (previous_stage
== MESA_SHADER_VERTEX
) {
572 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
574 user_sgpr_info
->sgpr_count
++;
577 user_sgpr_info
->sgpr_count
+= 2;
583 if (needs_view_index
)
584 user_sgpr_info
->sgpr_count
++;
586 if (ctx
->shader_info
->info
.loads_push_constants
)
587 user_sgpr_info
->sgpr_count
+= 2;
589 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
? 32 : 16;
590 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_info
->sgpr_count
;
592 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
593 user_sgpr_info
->sgpr_count
+= 2;
594 user_sgpr_info
->indirect_all_descriptor_sets
= true;
596 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
601 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
602 gl_shader_stage stage
,
603 bool has_previous_stage
,
604 gl_shader_stage previous_stage
,
605 const struct user_sgpr_info
*user_sgpr_info
,
606 struct arg_info
*args
,
607 LLVMValueRef
*desc_sets
)
609 LLVMTypeRef type
= ac_array_in_const_addr_space(ctx
->ac
.i8
);
610 unsigned num_sets
= ctx
->options
->layout
?
611 ctx
->options
->layout
->num_sets
: 0;
612 unsigned stage_mask
= 1 << stage
;
614 if (has_previous_stage
)
615 stage_mask
|= 1 << previous_stage
;
617 /* 1 for each descriptor set */
618 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
619 for (unsigned i
= 0; i
< num_sets
; ++i
) {
620 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
621 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
622 add_array_arg(args
, type
,
623 &ctx
->descriptor_sets
[i
]);
627 add_array_arg(args
, ac_array_in_const_addr_space(type
), desc_sets
);
630 if (ctx
->shader_info
->info
.loads_push_constants
) {
631 /* 1 for push constants and dynamic descriptors */
632 add_array_arg(args
, type
, &ctx
->abi
.push_constants
);
637 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
638 gl_shader_stage stage
,
639 bool has_previous_stage
,
640 gl_shader_stage previous_stage
,
641 struct arg_info
*args
)
643 if (!ctx
->is_gs_copy_shader
&&
644 (stage
== MESA_SHADER_VERTEX
||
645 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
646 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
647 add_arg(args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
648 &ctx
->vertex_buffers
);
650 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
651 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
652 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
653 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
659 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
661 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
662 if (!ctx
->is_gs_copy_shader
) {
663 if (ctx
->options
->key
.vs
.as_ls
) {
664 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
665 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
667 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
668 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
670 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
675 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
677 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
678 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
679 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
680 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
684 set_global_input_locs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
685 bool has_previous_stage
, gl_shader_stage previous_stage
,
686 const struct user_sgpr_info
*user_sgpr_info
,
687 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
689 unsigned num_sets
= ctx
->options
->layout
?
690 ctx
->options
->layout
->num_sets
: 0;
691 unsigned stage_mask
= 1 << stage
;
693 if (has_previous_stage
)
694 stage_mask
|= 1 << previous_stage
;
696 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
697 for (unsigned i
= 0; i
< num_sets
; ++i
) {
698 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
699 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
700 set_loc_desc(ctx
, i
, user_sgpr_idx
, 0);
702 ctx
->descriptor_sets
[i
] = NULL
;
705 set_loc_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
708 for (unsigned i
= 0; i
< num_sets
; ++i
) {
709 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
710 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
711 set_loc_desc(ctx
, i
, user_sgpr_idx
, i
* 8);
712 ctx
->descriptor_sets
[i
] =
713 ac_build_load_to_sgpr(&ctx
->ac
,
715 LLVMConstInt(ctx
->ac
.i32
, i
, false));
718 ctx
->descriptor_sets
[i
] = NULL
;
720 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
723 if (ctx
->shader_info
->info
.loads_push_constants
) {
724 set_loc_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
729 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
730 gl_shader_stage stage
, bool has_previous_stage
,
731 gl_shader_stage previous_stage
,
732 uint8_t *user_sgpr_idx
)
734 if (!ctx
->is_gs_copy_shader
&&
735 (stage
== MESA_SHADER_VERTEX
||
736 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
737 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
738 set_loc_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
743 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
746 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
747 user_sgpr_idx
, vs_num
);
751 static void create_function(struct radv_shader_context
*ctx
,
752 gl_shader_stage stage
,
753 bool has_previous_stage
,
754 gl_shader_stage previous_stage
)
756 uint8_t user_sgpr_idx
;
757 struct user_sgpr_info user_sgpr_info
;
758 struct arg_info args
= {};
759 LLVMValueRef desc_sets
;
760 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
761 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
762 previous_stage
, needs_view_index
, &user_sgpr_info
);
764 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
765 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
770 case MESA_SHADER_COMPUTE
:
771 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
772 previous_stage
, &user_sgpr_info
,
775 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
776 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
777 &ctx
->abi
.num_work_groups
);
780 for (int i
= 0; i
< 3; i
++) {
781 ctx
->abi
.workgroup_ids
[i
] = NULL
;
782 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
783 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
784 &ctx
->abi
.workgroup_ids
[i
]);
788 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
789 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
790 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
791 &ctx
->abi
.local_invocation_ids
);
793 case MESA_SHADER_VERTEX
:
794 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
795 previous_stage
, &user_sgpr_info
,
797 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
798 previous_stage
, &args
);
800 if (needs_view_index
)
801 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
802 &ctx
->abi
.view_index
);
803 if (ctx
->options
->key
.vs
.as_es
)
804 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
806 else if (ctx
->options
->key
.vs
.as_ls
)
807 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
808 &ctx
->ls_out_layout
);
810 declare_vs_input_vgprs(ctx
, &args
);
812 case MESA_SHADER_TESS_CTRL
:
813 if (has_previous_stage
) {
814 // First 6 system regs
815 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
816 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
817 &ctx
->merged_wave_info
);
818 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
819 &ctx
->tess_factor_offset
);
821 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
822 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
823 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
825 declare_global_input_sgprs(ctx
, stage
,
828 &user_sgpr_info
, &args
,
830 declare_vs_specific_input_sgprs(ctx
, stage
,
832 previous_stage
, &args
);
834 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
835 &ctx
->ls_out_layout
);
837 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
838 &ctx
->tcs_offchip_layout
);
839 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
840 &ctx
->tcs_out_offsets
);
841 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
842 &ctx
->tcs_out_layout
);
843 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
844 &ctx
->tcs_in_layout
);
845 if (needs_view_index
)
846 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
847 &ctx
->abi
.view_index
);
849 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
850 &ctx
->abi
.tcs_patch_id
);
851 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
852 &ctx
->abi
.tcs_rel_ids
);
854 declare_vs_input_vgprs(ctx
, &args
);
856 declare_global_input_sgprs(ctx
, stage
,
859 &user_sgpr_info
, &args
,
862 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
863 &ctx
->tcs_offchip_layout
);
864 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
865 &ctx
->tcs_out_offsets
);
866 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
867 &ctx
->tcs_out_layout
);
868 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
869 &ctx
->tcs_in_layout
);
870 if (needs_view_index
)
871 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
872 &ctx
->abi
.view_index
);
874 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
875 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
876 &ctx
->tess_factor_offset
);
877 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
878 &ctx
->abi
.tcs_patch_id
);
879 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
880 &ctx
->abi
.tcs_rel_ids
);
883 case MESA_SHADER_TESS_EVAL
:
884 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
885 previous_stage
, &user_sgpr_info
,
888 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
);
889 if (needs_view_index
)
890 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
891 &ctx
->abi
.view_index
);
893 if (ctx
->options
->key
.tes
.as_es
) {
894 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
895 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
896 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
899 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
900 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
902 declare_tes_input_vgprs(ctx
, &args
);
904 case MESA_SHADER_GEOMETRY
:
905 if (has_previous_stage
) {
906 // First 6 system regs
907 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
909 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
910 &ctx
->merged_wave_info
);
911 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
913 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
914 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
915 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
917 declare_global_input_sgprs(ctx
, stage
,
920 &user_sgpr_info
, &args
,
923 if (previous_stage
== MESA_SHADER_TESS_EVAL
) {
924 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
925 &ctx
->tcs_offchip_layout
);
927 declare_vs_specific_input_sgprs(ctx
, stage
,
933 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
934 &ctx
->gsvs_ring_stride
);
935 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
936 &ctx
->gsvs_num_entries
);
937 if (needs_view_index
)
938 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
939 &ctx
->abi
.view_index
);
941 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
942 &ctx
->gs_vtx_offset
[0]);
943 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
944 &ctx
->gs_vtx_offset
[2]);
945 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
946 &ctx
->abi
.gs_prim_id
);
947 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
948 &ctx
->abi
.gs_invocation_id
);
949 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
950 &ctx
->gs_vtx_offset
[4]);
952 if (previous_stage
== MESA_SHADER_VERTEX
) {
953 declare_vs_input_vgprs(ctx
, &args
);
955 declare_tes_input_vgprs(ctx
, &args
);
958 declare_global_input_sgprs(ctx
, stage
,
961 &user_sgpr_info
, &args
,
964 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
965 &ctx
->gsvs_ring_stride
);
966 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
967 &ctx
->gsvs_num_entries
);
968 if (needs_view_index
)
969 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
970 &ctx
->abi
.view_index
);
972 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
973 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
974 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
975 &ctx
->gs_vtx_offset
[0]);
976 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
977 &ctx
->gs_vtx_offset
[1]);
978 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
979 &ctx
->abi
.gs_prim_id
);
980 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
981 &ctx
->gs_vtx_offset
[2]);
982 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
983 &ctx
->gs_vtx_offset
[3]);
984 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
985 &ctx
->gs_vtx_offset
[4]);
986 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
987 &ctx
->gs_vtx_offset
[5]);
988 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
989 &ctx
->abi
.gs_invocation_id
);
992 case MESA_SHADER_FRAGMENT
:
993 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
994 previous_stage
, &user_sgpr_info
,
997 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
998 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
999 &ctx
->sample_pos_offset
);
1001 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1002 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1003 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1004 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1005 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1006 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1007 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1008 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1009 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1010 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1011 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1012 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1013 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1014 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1015 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1016 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1017 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1020 unreachable("Shader stage not implemented");
1023 ctx
->main_function
= create_llvm_function(
1024 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1025 ctx
->max_workgroup_size
,
1026 ctx
->options
->unsafe_math
);
1027 set_llvm_calling_convention(ctx
->main_function
, stage
);
1030 ctx
->shader_info
->num_input_vgprs
= 0;
1031 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1033 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1035 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1036 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1038 assign_arguments(ctx
->main_function
, &args
);
1042 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1043 set_loc_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1045 if (ctx
->options
->supports_spill
) {
1046 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx
->ac
.i8
, AC_CONST_ADDR_SPACE
),
1048 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1049 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1050 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage
)
1059 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1060 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1063 case MESA_SHADER_COMPUTE
:
1064 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1065 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1069 case MESA_SHADER_VERTEX
:
1070 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1071 previous_stage
, &user_sgpr_idx
);
1072 if (ctx
->abi
.view_index
)
1073 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1074 if (ctx
->options
->key
.vs
.as_ls
) {
1075 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1079 case MESA_SHADER_TESS_CTRL
:
1080 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1081 previous_stage
, &user_sgpr_idx
);
1082 if (has_previous_stage
)
1083 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1085 set_loc_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
1086 if (ctx
->abi
.view_index
)
1087 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1089 case MESA_SHADER_TESS_EVAL
:
1090 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
1091 if (ctx
->abi
.view_index
)
1092 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1094 case MESA_SHADER_GEOMETRY
:
1095 if (has_previous_stage
) {
1096 if (previous_stage
== MESA_SHADER_VERTEX
)
1097 set_vs_specific_input_locs(ctx
, stage
,
1102 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
,
1105 set_loc_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
,
1107 if (ctx
->abi
.view_index
)
1108 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1110 case MESA_SHADER_FRAGMENT
:
1111 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1112 set_loc_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
,
1117 unreachable("Shader stage not implemented");
1120 if (stage
== MESA_SHADER_TESS_CTRL
||
1121 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_ls
) ||
1122 /* GFX9 has the ESGS ring buffer in LDS. */
1123 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1124 ac_declare_lds_as_pointer(&ctx
->ac
);
1127 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1130 static LLVMValueRef
trim_vector(struct ac_llvm_context
*ctx
,
1131 LLVMValueRef value
, unsigned count
)
1133 unsigned num_components
= ac_get_llvm_num_components(value
);
1134 if (count
== num_components
)
1137 LLVMValueRef masks
[] = {
1138 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1139 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1142 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1145 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1146 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1150 build_store_values_extended(struct ac_llvm_context
*ac
,
1151 LLVMValueRef
*values
,
1152 unsigned value_count
,
1153 unsigned value_stride
,
1156 LLVMBuilderRef builder
= ac
->builder
;
1159 for (i
= 0; i
< value_count
; i
++) {
1160 LLVMValueRef ptr
= values
[i
* value_stride
];
1161 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1162 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1163 LLVMBuildStore(builder
, value
, ptr
);
1167 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1168 const nir_ssa_def
*def
)
1170 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1171 if (def
->num_components
> 1) {
1172 type
= LLVMVectorType(type
, def
->num_components
);
1177 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1180 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1181 return (LLVMValueRef
)entry
->data
;
1185 get_memory_ptr(struct ac_nir_context
*ctx
, nir_src src
)
1187 LLVMValueRef ptr
= get_src(ctx
, src
);
1188 ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ac
.lds
, &ptr
, 1, "");
1189 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
1191 return LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1192 LLVMPointerType(ctx
->ac
.i32
, addr_space
), "");
1195 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1196 const struct nir_block
*b
)
1198 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1199 return (LLVMBasicBlockRef
)entry
->data
;
1202 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1204 unsigned num_components
)
1206 LLVMValueRef value
= get_src(ctx
, src
.src
);
1207 bool need_swizzle
= false;
1210 unsigned src_components
= ac_get_llvm_num_components(value
);
1211 for (unsigned i
= 0; i
< num_components
; ++i
) {
1212 assert(src
.swizzle
[i
] < src_components
);
1213 if (src
.swizzle
[i
] != i
)
1214 need_swizzle
= true;
1217 if (need_swizzle
|| num_components
!= src_components
) {
1218 LLVMValueRef masks
[] = {
1219 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1220 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1221 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1222 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1224 if (src_components
> 1 && num_components
== 1) {
1225 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1227 } else if (src_components
== 1 && num_components
> 1) {
1228 LLVMValueRef values
[] = {value
, value
, value
, value
};
1229 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1231 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1232 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1236 assert(!src
.negate
);
1241 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1242 LLVMIntPredicate pred
, LLVMValueRef src0
,
1245 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1246 return LLVMBuildSelect(ctx
->builder
, result
,
1247 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1251 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1252 LLVMRealPredicate pred
, LLVMValueRef src0
,
1255 LLVMValueRef result
;
1256 src0
= ac_to_float(ctx
, src0
);
1257 src1
= ac_to_float(ctx
, src1
);
1258 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1259 return LLVMBuildSelect(ctx
->builder
, result
,
1260 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1264 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1266 LLVMTypeRef result_type
,
1270 LLVMValueRef params
[] = {
1271 ac_to_float(ctx
, src0
),
1274 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1275 ac_get_elem_bits(ctx
, result_type
));
1276 assert(length
< sizeof(name
));
1277 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1280 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1282 LLVMTypeRef result_type
,
1283 LLVMValueRef src0
, LLVMValueRef src1
)
1286 LLVMValueRef params
[] = {
1287 ac_to_float(ctx
, src0
),
1288 ac_to_float(ctx
, src1
),
1291 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1292 ac_get_elem_bits(ctx
, result_type
));
1293 assert(length
< sizeof(name
));
1294 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1297 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1299 LLVMTypeRef result_type
,
1300 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1303 LLVMValueRef params
[] = {
1304 ac_to_float(ctx
, src0
),
1305 ac_to_float(ctx
, src1
),
1306 ac_to_float(ctx
, src2
),
1309 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1310 ac_get_elem_bits(ctx
, result_type
));
1311 assert(length
< sizeof(name
));
1312 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1315 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1316 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1318 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1320 return LLVMBuildSelect(ctx
->builder
, v
, ac_to_integer(ctx
, src1
),
1321 ac_to_integer(ctx
, src2
), "");
1324 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1325 LLVMIntPredicate pred
,
1326 LLVMValueRef src0
, LLVMValueRef src1
)
1328 return LLVMBuildSelect(ctx
->builder
,
1329 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1334 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1337 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1338 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1341 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1343 LLVMValueRef src0
, LLVMValueRef src1
)
1345 LLVMTypeRef ret_type
;
1346 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1348 LLVMValueRef params
[] = { src0
, src1
};
1349 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1352 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1353 params
, 2, AC_FUNC_ATTR_READNONE
);
1355 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1356 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1360 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1363 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1366 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1369 src0
= ac_to_float(ctx
, src0
);
1370 LLVMValueRef zero
= LLVMConstNull(LLVMTypeOf(src0
));
1371 return LLVMBuildSExt(ctx
->builder
,
1372 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, zero
, ""),
1376 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1380 LLVMValueRef result
= LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1385 return LLVMBuildZExt(ctx
->builder
, result
, ctx
->i64
, "");
1388 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1391 LLVMValueRef zero
= LLVMConstNull(LLVMTypeOf(src0
));
1392 return LLVMBuildSExt(ctx
->builder
,
1393 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, zero
, ""),
1397 static LLVMValueRef
emit_f2f16(struct ac_llvm_context
*ctx
,
1400 LLVMValueRef result
;
1401 LLVMValueRef cond
= NULL
;
1403 src0
= ac_to_float(ctx
, src0
);
1404 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->f16
, "");
1406 if (ctx
->chip_class
>= VI
) {
1407 LLVMValueRef args
[2];
1408 /* Check if the result is a denormal - and flush to 0 if so. */
1410 args
[1] = LLVMConstInt(ctx
->i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1411 cond
= ac_build_intrinsic(ctx
, "llvm.amdgcn.class.f16", ctx
->i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1414 /* need to convert back up to f32 */
1415 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->f32
, "");
1417 if (ctx
->chip_class
>= VI
)
1418 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->f32_0
, result
, "");
1421 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1422 * so compare the result and flush to 0 if it's smaller.
1424 LLVMValueRef temp
, cond2
;
1425 temp
= emit_intrin_1f_param(ctx
, "llvm.fabs", ctx
->f32
, result
);
1426 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1427 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->i32
, 0x38800000, false), ctx
->f32
, ""),
1429 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1430 temp
, ctx
->f32_0
, "");
1431 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1432 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->f32_0
, result
, "");
1437 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1438 LLVMValueRef src0
, LLVMValueRef src1
)
1440 LLVMValueRef dst64
, result
;
1441 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1442 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1444 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1445 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1446 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1450 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1451 LLVMValueRef src0
, LLVMValueRef src1
)
1453 LLVMValueRef dst64
, result
;
1454 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1455 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1457 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1458 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1459 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1463 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1465 const LLVMValueRef srcs
[3])
1467 LLVMValueRef result
;
1468 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1470 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1471 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1475 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1476 LLVMValueRef src0
, LLVMValueRef src1
,
1477 LLVMValueRef src2
, LLVMValueRef src3
)
1479 LLVMValueRef bfi_args
[3], result
;
1481 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1482 LLVMBuildSub(ctx
->builder
,
1483 LLVMBuildShl(ctx
->builder
,
1488 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1491 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1494 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1495 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1497 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1498 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1499 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1501 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1505 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1508 LLVMValueRef comp
[2];
1510 src0
= ac_to_float(ctx
, src0
);
1511 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1512 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1514 return ac_build_cvt_pkrtz_f16(ctx
, comp
);
1517 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1520 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1521 LLVMValueRef temps
[2], result
, val
;
1524 for (i
= 0; i
< 2; i
++) {
1525 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1526 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1527 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1528 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1531 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), temps
[0],
1533 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1538 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1544 LLVMValueRef result
;
1546 if (op
== nir_op_fddx_fine
)
1547 mask
= AC_TID_MASK_LEFT
;
1548 else if (op
== nir_op_fddy_fine
)
1549 mask
= AC_TID_MASK_TOP
;
1551 mask
= AC_TID_MASK_TOP_LEFT
;
1553 /* for DDX we want to next X pixel, DDY next Y pixel. */
1554 if (op
== nir_op_fddx_fine
||
1555 op
== nir_op_fddx_coarse
||
1561 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1566 * this takes an I,J coordinate pair,
1567 * and works out the X and Y derivatives.
1568 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1570 static LLVMValueRef
emit_ddxy_interp(
1571 struct ac_nir_context
*ctx
,
1572 LLVMValueRef interp_ij
)
1574 LLVMValueRef result
[4], a
;
1577 for (i
= 0; i
< 2; i
++) {
1578 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1579 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1580 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1581 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1583 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1586 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1588 LLVMValueRef src
[4], result
= NULL
;
1589 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1590 unsigned src_components
;
1591 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1593 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1594 switch (instr
->op
) {
1600 case nir_op_pack_half_2x16
:
1603 case nir_op_unpack_half_2x16
:
1606 case nir_op_cube_face_coord
:
1607 case nir_op_cube_face_index
:
1611 src_components
= num_components
;
1614 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1615 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1617 switch (instr
->op
) {
1623 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1624 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1627 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1630 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1633 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1636 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1637 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1638 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1641 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1642 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1643 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1646 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1649 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1652 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1655 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1658 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1659 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1660 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1661 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1662 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1663 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1664 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1667 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1668 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1669 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1672 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1675 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1678 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1681 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1682 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1683 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1686 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1687 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1691 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1694 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1697 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1700 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1701 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1702 LLVMTypeOf(src
[0]), ""),
1706 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1707 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1708 LLVMTypeOf(src
[0]), ""),
1712 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1713 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1714 LLVMTypeOf(src
[0]), ""),
1718 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1721 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1724 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1727 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1730 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1733 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1736 result
= emit_float_cmp(&ctx
->ac
, LLVMRealOEQ
, src
[0], src
[1]);
1739 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1742 result
= emit_float_cmp(&ctx
->ac
, LLVMRealOLT
, src
[0], src
[1]);
1745 result
= emit_float_cmp(&ctx
->ac
, LLVMRealOGE
, src
[0], src
[1]);
1748 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1749 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1752 result
= emit_iabs(&ctx
->ac
, src
[0]);
1755 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1758 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1761 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1764 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1767 result
= ac_build_isign(&ctx
->ac
, src
[0],
1768 instr
->dest
.dest
.ssa
.bit_size
);
1771 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1772 result
= ac_build_fsign(&ctx
->ac
, src
[0],
1773 instr
->dest
.dest
.ssa
.bit_size
);
1776 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1777 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1780 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1781 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1784 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1785 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1787 case nir_op_fround_even
:
1788 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1789 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1792 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1793 result
= ac_build_fract(&ctx
->ac
, src
[0],
1794 instr
->dest
.dest
.ssa
.bit_size
);
1797 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1798 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1801 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1802 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1805 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1806 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1809 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1810 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1813 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1814 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1817 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1818 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1819 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1823 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1824 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1825 if (ctx
->ac
.chip_class
< GFX9
&&
1826 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1827 /* Only pre-GFX9 chips do not flush denorms. */
1828 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1829 ac_to_float_type(&ctx
->ac
, def_type
),
1834 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1835 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1836 if (ctx
->ac
.chip_class
< GFX9
&&
1837 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1838 /* Only pre-GFX9 chips do not flush denorms. */
1839 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1840 ac_to_float_type(&ctx
->ac
, def_type
),
1845 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1846 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1849 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1850 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) == 32)
1851 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ldexp.f32", ctx
->ac
.f32
, src
, 2, AC_FUNC_ATTR_READNONE
);
1853 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ldexp.f64", ctx
->ac
.f64
, src
, 2, AC_FUNC_ATTR_READNONE
);
1855 case nir_op_ibitfield_extract
:
1856 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1858 case nir_op_ubitfield_extract
:
1859 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1861 case nir_op_bitfield_insert
:
1862 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1864 case nir_op_bitfield_reverse
:
1865 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1867 case nir_op_bit_count
:
1868 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) == 32)
1869 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1871 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i64", ctx
->ac
.i64
, src
, 1, AC_FUNC_ATTR_READNONE
);
1872 result
= LLVMBuildTrunc(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
1878 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1879 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1880 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1884 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1885 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1889 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1890 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1894 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1895 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1899 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1900 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1903 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1904 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1907 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1908 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1912 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1913 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < ac_get_elem_bits(&ctx
->ac
, def_type
))
1914 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1916 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1920 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1921 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < ac_get_elem_bits(&ctx
->ac
, def_type
))
1922 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1924 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1927 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1929 case nir_op_find_lsb
:
1930 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1931 result
= ac_find_lsb(&ctx
->ac
, ctx
->ac
.i32
, src
[0]);
1933 case nir_op_ufind_msb
:
1934 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1935 result
= ac_build_umsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1937 case nir_op_ifind_msb
:
1938 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1939 result
= ac_build_imsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1941 case nir_op_uadd_carry
:
1942 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1943 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1944 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
1946 case nir_op_usub_borrow
:
1947 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1948 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1949 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
1952 result
= emit_b2f(&ctx
->ac
, src
[0]);
1955 result
= emit_f2b(&ctx
->ac
, src
[0]);
1958 result
= emit_b2i(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1961 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1962 result
= emit_i2b(&ctx
->ac
, src
[0]);
1964 case nir_op_fquantize2f16
:
1965 result
= emit_f2f16(&ctx
->ac
, src
[0]);
1967 case nir_op_umul_high
:
1968 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1969 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1970 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
1972 case nir_op_imul_high
:
1973 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1974 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1975 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
1977 case nir_op_pack_half_2x16
:
1978 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
1980 case nir_op_unpack_half_2x16
:
1981 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
1985 case nir_op_fddx_fine
:
1986 case nir_op_fddy_fine
:
1987 case nir_op_fddx_coarse
:
1988 case nir_op_fddy_coarse
:
1989 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
1992 case nir_op_unpack_64_2x32_split_x
: {
1993 assert(ac_get_llvm_num_components(src
[0]) == 1);
1994 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
1997 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2002 case nir_op_unpack_64_2x32_split_y
: {
2003 assert(ac_get_llvm_num_components(src
[0]) == 1);
2004 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2007 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2012 case nir_op_pack_64_2x32_split
: {
2013 LLVMValueRef tmp
= LLVMGetUndef(ctx
->ac
.v2i32
);
2014 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2015 src
[0], ctx
->ac
.i32_0
, "");
2016 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2017 src
[1], ctx
->ac
.i32_1
, "");
2018 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
2022 case nir_op_cube_face_coord
: {
2023 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
2024 LLVMValueRef results
[2];
2026 for (unsigned chan
= 0; chan
< 3; chan
++)
2027 in
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src
[0], chan
);
2028 results
[0] = ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.cubetc",
2029 ctx
->ac
.f32
, in
, 3, AC_FUNC_ATTR_READNONE
);
2030 results
[1] = ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.cubesc",
2031 ctx
->ac
.f32
, in
, 3, AC_FUNC_ATTR_READNONE
);
2032 result
= ac_build_gather_values(&ctx
->ac
, results
, 2);
2036 case nir_op_cube_face_index
: {
2037 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
2039 for (unsigned chan
= 0; chan
< 3; chan
++)
2040 in
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src
[0], chan
);
2041 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.cubeid",
2042 ctx
->ac
.f32
, in
, 3, AC_FUNC_ATTR_READNONE
);
2047 fprintf(stderr
, "Unknown NIR alu instr: ");
2048 nir_print_instr(&instr
->instr
, stderr
);
2049 fprintf(stderr
, "\n");
2054 assert(instr
->dest
.dest
.is_ssa
);
2055 result
= ac_to_integer(&ctx
->ac
, result
);
2056 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
2061 static void visit_load_const(struct ac_nir_context
*ctx
,
2062 const nir_load_const_instr
*instr
)
2064 LLVMValueRef values
[4], value
= NULL
;
2065 LLVMTypeRef element_type
=
2066 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
2068 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
2069 switch (instr
->def
.bit_size
) {
2071 values
[i
] = LLVMConstInt(element_type
,
2072 instr
->value
.u32
[i
], false);
2075 values
[i
] = LLVMConstInt(element_type
,
2076 instr
->value
.u64
[i
], false);
2080 "unsupported nir load_const bit_size: %d\n",
2081 instr
->def
.bit_size
);
2085 if (instr
->def
.num_components
> 1) {
2086 value
= LLVMConstVector(values
, instr
->def
.num_components
);
2090 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
2093 static LLVMValueRef
cast_ptr(struct ac_llvm_context
*ctx
, LLVMValueRef ptr
,
2096 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
2097 return LLVMBuildBitCast(ctx
->builder
, ptr
,
2098 LLVMPointerType(type
, addr_space
), "");
2102 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
2105 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2106 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2109 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
2110 /* On VI, the descriptor contains the size in bytes,
2111 * but TXQ must return the size in elements.
2112 * The stride is always non-zero for resources using TXQ.
2114 LLVMValueRef stride
=
2115 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2117 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2118 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2119 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2120 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2122 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2128 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2131 static void build_int_type_name(
2133 char *buf
, unsigned bufsize
)
2135 assert(bufsize
>= 6);
2137 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2138 snprintf(buf
, bufsize
, "v%ui32",
2139 LLVMGetVectorSize(type
));
2144 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2145 struct ac_image_args
*args
,
2146 const nir_tex_instr
*instr
)
2148 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2149 LLVMValueRef coord
= args
->addr
;
2150 LLVMValueRef half_texel
[2];
2151 LLVMValueRef compare_cube_wa
= NULL
;
2152 LLVMValueRef result
;
2154 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2158 struct ac_image_args txq_args
= { 0 };
2160 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2161 txq_args
.opcode
= ac_image_get_resinfo
;
2162 txq_args
.dmask
= 0xf;
2163 txq_args
.addr
= ctx
->i32_0
;
2164 txq_args
.resource
= args
->resource
;
2165 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2167 for (c
= 0; c
< 2; c
++) {
2168 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2169 LLVMConstInt(ctx
->i32
, c
, false), "");
2170 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2171 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2172 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2173 LLVMConstReal(ctx
->f32
, -0.5), "");
2177 LLVMValueRef orig_coords
= args
->addr
;
2179 for (c
= 0; c
< 2; c
++) {
2181 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2182 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2183 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2184 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2185 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2186 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2191 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2192 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2193 * workaround by sampling using a scaled type and converting.
2194 * This is taken from amdgpu-pro shaders.
2196 /* NOTE this produces some ugly code compared to amdgpu-pro,
2197 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2198 * and then reads them back. -pro generates two selects,
2199 * one s_cmp for the descriptor rewriting
2200 * one v_cmp for the coordinate and result changes.
2202 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2203 LLVMValueRef tmp
, tmp2
;
2205 /* workaround 8/8/8/8 uint/sint cube gather bug */
2206 /* first detect it then change to a scaled read and f2i */
2207 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2210 /* extract the DATA_FORMAT */
2211 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2212 LLVMConstInt(ctx
->i32
, 6, false), false);
2214 /* is the DATA_FORMAT == 8_8_8_8 */
2215 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2217 if (stype
== GLSL_TYPE_UINT
)
2218 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2219 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2220 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2222 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2223 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2224 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2226 /* replace the NUM FORMAT in the descriptor */
2227 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2228 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2230 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2232 /* don't modify the coordinates for this case */
2233 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2236 result
= ac_build_image_opcode(ctx
, args
);
2238 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2239 LLVMValueRef tmp
, tmp2
;
2241 /* if the cube workaround is in place, f2i the result. */
2242 for (c
= 0; c
< 4; c
++) {
2243 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2244 if (stype
== GLSL_TYPE_UINT
)
2245 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2247 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2248 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2249 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2250 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2251 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2252 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2258 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2259 const nir_tex_instr
*instr
,
2261 struct ac_image_args
*args
)
2263 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2264 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
2266 return ac_build_buffer_load_format(&ctx
->ac
,
2270 util_last_bit(mask
),
2274 args
->opcode
= ac_image_sample
;
2275 args
->compare
= instr
->is_shadow
;
2277 switch (instr
->op
) {
2279 case nir_texop_txf_ms
:
2280 case nir_texop_samples_identical
:
2281 args
->opcode
= lod_is_zero
||
2282 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
?
2283 ac_image_load
: ac_image_load_mip
;
2284 args
->compare
= false;
2285 args
->offset
= false;
2292 args
->level_zero
= true;
2297 case nir_texop_query_levels
:
2298 args
->opcode
= ac_image_get_resinfo
;
2301 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2302 args
->level_zero
= true;
2308 args
->opcode
= ac_image_gather4
;
2309 args
->level_zero
= true;
2312 args
->opcode
= ac_image_get_lod
;
2313 args
->compare
= false;
2314 args
->offset
= false;
2320 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2321 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2322 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2323 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2326 return ac_build_image_opcode(&ctx
->ac
, args
);
2330 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
2331 unsigned desc_set
, unsigned binding
)
2333 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2334 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2335 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2336 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2337 unsigned base_offset
= layout
->binding
[binding
].offset
;
2338 LLVMValueRef offset
, stride
;
2340 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2341 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2342 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2343 layout
->binding
[binding
].dynamic_offset_offset
;
2344 desc_ptr
= ctx
->abi
.push_constants
;
2345 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2346 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2348 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
2350 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
2351 index
= LLVMBuildMul(ctx
->ac
.builder
, index
, stride
, "");
2352 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, index
, "");
2354 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2355 desc_ptr
= cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
2356 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2361 static LLVMValueRef
visit_vulkan_resource_reindex(struct ac_nir_context
*ctx
,
2362 nir_intrinsic_instr
*instr
)
2364 LLVMValueRef ptr
= get_src(ctx
, instr
->src
[0]);
2365 LLVMValueRef index
= get_src(ctx
, instr
->src
[1]);
2367 LLVMValueRef result
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
2368 LLVMSetMetadata(result
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2372 static LLVMValueRef
visit_load_push_constant(struct ac_nir_context
*ctx
,
2373 nir_intrinsic_instr
*instr
)
2375 LLVMValueRef ptr
, addr
;
2377 addr
= LLVMConstInt(ctx
->ac
.i32
, nir_intrinsic_base(instr
), 0);
2378 addr
= LLVMBuildAdd(ctx
->ac
.builder
, addr
,
2379 get_src(ctx
, instr
->src
[0]), "");
2381 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->abi
->push_constants
, addr
);
2382 ptr
= cast_ptr(&ctx
->ac
, ptr
, get_def_type(ctx
, &instr
->dest
.ssa
));
2384 return LLVMBuildLoad(ctx
->ac
.builder
, ptr
, "");
2387 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2388 const nir_intrinsic_instr
*instr
)
2390 LLVMValueRef index
= get_src(ctx
, instr
->src
[0]);
2392 return get_buffer_size(ctx
, ctx
->abi
->load_ssbo(ctx
->abi
, index
, false), false);
2395 static uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2397 uint32_t new_mask
= 0;
2398 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2399 if (mask
& (1u << i
))
2400 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2404 static LLVMValueRef
extract_vector_range(struct ac_llvm_context
*ctx
, LLVMValueRef src
,
2405 unsigned start
, unsigned count
)
2407 LLVMTypeRef type
= LLVMTypeOf(src
);
2409 if (LLVMGetTypeKind(type
) != LLVMVectorTypeKind
) {
2415 unsigned src_elements
= LLVMGetVectorSize(type
);
2416 assert(start
< src_elements
);
2417 assert(start
+ count
<= src_elements
);
2419 if (start
== 0 && count
== src_elements
)
2423 return LLVMBuildExtractElement(ctx
->builder
, src
, LLVMConstInt(ctx
->i32
, start
, false), "");
2426 LLVMValueRef indices
[8];
2427 for (unsigned i
= 0; i
< count
; ++i
)
2428 indices
[i
] = LLVMConstInt(ctx
->i32
, start
+ i
, false);
2430 LLVMValueRef swizzle
= LLVMConstVector(indices
, count
);
2431 return LLVMBuildShuffleVector(ctx
->builder
, src
, src
, swizzle
, "");
2434 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2435 nir_intrinsic_instr
*instr
)
2437 const char *store_name
;
2438 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2439 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2440 int elem_size_mult
= ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2441 int components_32bit
= elem_size_mult
* instr
->num_components
;
2442 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2443 LLVMValueRef base_data
, base_offset
;
2444 LLVMValueRef params
[6];
2446 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2447 get_src(ctx
, instr
->src
[1]), true);
2448 params
[2] = ctx
->ac
.i32_0
; /* vindex */
2449 params
[4] = ctx
->ac
.i1false
; /* glc */
2450 params
[5] = ctx
->ac
.i1false
; /* slc */
2452 if (components_32bit
> 1)
2453 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2455 writemask
= widen_mask(writemask
, elem_size_mult
);
2457 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2458 base_data
= trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2459 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2461 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2465 LLVMValueRef offset
;
2467 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2469 /* Due to an LLVM limitation, split 3-element writes
2470 * into a 2-element and a 1-element write. */
2472 writemask
|= 1 << (start
+ 2);
2477 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2482 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2483 } else if (count
== 2) {
2484 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2488 store_name
= "llvm.amdgcn.buffer.store.f32";
2490 data
= extract_vector_range(&ctx
->ac
, base_data
, start
, count
);
2492 offset
= base_offset
;
2494 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2498 ac_build_intrinsic(&ctx
->ac
, store_name
,
2499 ctx
->ac
.voidt
, params
, 6, 0);
2503 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2504 const nir_intrinsic_instr
*instr
)
2507 LLVMValueRef params
[6];
2510 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2511 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2513 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2514 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2515 get_src(ctx
, instr
->src
[0]),
2517 params
[arg_count
++] = ctx
->ac
.i32_0
; /* vindex */
2518 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2519 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2521 switch (instr
->intrinsic
) {
2522 case nir_intrinsic_ssbo_atomic_add
:
2523 name
= "llvm.amdgcn.buffer.atomic.add";
2525 case nir_intrinsic_ssbo_atomic_imin
:
2526 name
= "llvm.amdgcn.buffer.atomic.smin";
2528 case nir_intrinsic_ssbo_atomic_umin
:
2529 name
= "llvm.amdgcn.buffer.atomic.umin";
2531 case nir_intrinsic_ssbo_atomic_imax
:
2532 name
= "llvm.amdgcn.buffer.atomic.smax";
2534 case nir_intrinsic_ssbo_atomic_umax
:
2535 name
= "llvm.amdgcn.buffer.atomic.umax";
2537 case nir_intrinsic_ssbo_atomic_and
:
2538 name
= "llvm.amdgcn.buffer.atomic.and";
2540 case nir_intrinsic_ssbo_atomic_or
:
2541 name
= "llvm.amdgcn.buffer.atomic.or";
2543 case nir_intrinsic_ssbo_atomic_xor
:
2544 name
= "llvm.amdgcn.buffer.atomic.xor";
2546 case nir_intrinsic_ssbo_atomic_exchange
:
2547 name
= "llvm.amdgcn.buffer.atomic.swap";
2549 case nir_intrinsic_ssbo_atomic_comp_swap
:
2550 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2556 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2559 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2560 const nir_intrinsic_instr
*instr
)
2562 LLVMValueRef results
[2];
2563 int load_components
;
2564 int num_components
= instr
->num_components
;
2565 if (instr
->dest
.ssa
.bit_size
== 64)
2566 num_components
*= 2;
2568 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2569 load_components
= MIN2(num_components
- i
, 4);
2570 const char *load_name
;
2571 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2572 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2573 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2575 if (load_components
== 3)
2576 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2577 else if (load_components
> 1)
2578 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2580 if (load_components
>= 3)
2581 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2582 else if (load_components
== 2)
2583 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2584 else if (load_components
== 1)
2585 load_name
= "llvm.amdgcn.buffer.load.f32";
2587 unreachable("unhandled number of components");
2589 LLVMValueRef params
[] = {
2590 ctx
->abi
->load_ssbo(ctx
->abi
,
2591 get_src(ctx
, instr
->src
[0]),
2599 results
[i
> 0 ? 1 : 0] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2603 LLVMValueRef ret
= results
[0];
2604 if (num_components
> 4 || num_components
== 3) {
2605 LLVMValueRef masks
[] = {
2606 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2607 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2608 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2609 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2612 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2613 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2614 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2617 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2618 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2621 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2622 const nir_intrinsic_instr
*instr
)
2625 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2626 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2627 int num_components
= instr
->num_components
;
2629 if (ctx
->abi
->load_ubo
)
2630 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2632 if (instr
->dest
.ssa
.bit_size
== 64)
2633 num_components
*= 2;
2635 ret
= ac_build_buffer_load(&ctx
->ac
, rsrc
, num_components
, NULL
, offset
,
2636 NULL
, 0, false, false, true, true);
2637 ret
= trim_vector(&ctx
->ac
, ret
, num_components
);
2638 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2639 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2643 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2644 bool vs_in
, unsigned *vertex_index_out
,
2645 LLVMValueRef
*vertex_index_ref
,
2646 unsigned *const_out
, LLVMValueRef
*indir_out
)
2648 unsigned const_offset
= 0;
2649 nir_deref
*tail
= &deref
->deref
;
2650 LLVMValueRef offset
= NULL
;
2652 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2654 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2655 if (vertex_index_out
)
2656 *vertex_index_out
= deref_array
->base_offset
;
2658 if (vertex_index_ref
) {
2659 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2660 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2661 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2663 *vertex_index_ref
= vtx
;
2667 if (deref
->var
->data
.compact
) {
2668 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2669 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2670 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2671 /* We always lower indirect dereferences for "compact" array vars. */
2672 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2674 const_offset
= deref_array
->base_offset
;
2678 while (tail
->child
!= NULL
) {
2679 const struct glsl_type
*parent_type
= tail
->type
;
2682 if (tail
->deref_type
== nir_deref_type_array
) {
2683 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2684 LLVMValueRef index
, stride
, local_offset
;
2685 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2687 const_offset
+= size
* deref_array
->base_offset
;
2688 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2691 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2692 index
= get_src(ctx
, deref_array
->indirect
);
2693 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2694 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2697 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2699 offset
= local_offset
;
2700 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2701 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2703 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2704 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2705 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2708 unreachable("unsupported deref type");
2712 if (const_offset
&& offset
)
2713 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2714 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2717 *const_out
= const_offset
;
2718 *indir_out
= offset
;
2722 /* The offchip buffer layout for TCS->TES is
2724 * - attribute 0 of patch 0 vertex 0
2725 * - attribute 0 of patch 0 vertex 1
2726 * - attribute 0 of patch 0 vertex 2
2728 * - attribute 0 of patch 1 vertex 0
2729 * - attribute 0 of patch 1 vertex 1
2731 * - attribute 1 of patch 0 vertex 0
2732 * - attribute 1 of patch 0 vertex 1
2734 * - per patch attribute 0 of patch 0
2735 * - per patch attribute 0 of patch 1
2738 * Note that every attribute has 4 components.
2740 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
2741 LLVMValueRef vertex_index
,
2742 LLVMValueRef param_index
)
2744 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
;
2745 LLVMValueRef param_stride
, constant16
;
2746 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2748 vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
2749 num_patches
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2751 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2753 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
2754 vertices_per_patch
, "");
2756 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
2759 param_stride
= LLVMBuildMul(ctx
->ac
.builder
, vertices_per_patch
,
2762 base_addr
= rel_patch_id
;
2763 param_stride
= num_patches
;
2766 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
2767 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
2768 param_stride
, ""), "");
2770 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
2772 if (!vertex_index
) {
2773 LLVMValueRef patch_data_offset
=
2774 unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2776 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
2777 patch_data_offset
, "");
2782 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
2784 unsigned const_index
,
2786 LLVMValueRef vertex_index
,
2787 LLVMValueRef indir_index
)
2789 LLVMValueRef param_index
;
2792 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
2795 if (const_index
&& !is_compact
)
2796 param
+= const_index
;
2797 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
2799 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2803 mark_tess_output(struct radv_shader_context
*ctx
,
2804 bool is_patch
, uint32_t param
)
2808 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2810 ctx
->tess_outputs_written
|= (1ull << param
);
2814 get_dw_address(struct radv_shader_context
*ctx
,
2815 LLVMValueRef dw_addr
,
2817 unsigned const_index
,
2818 bool compact_const_index
,
2819 LLVMValueRef vertex_index
,
2820 LLVMValueRef stride
,
2821 LLVMValueRef indir_index
)
2826 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2827 LLVMBuildMul(ctx
->ac
.builder
,
2833 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2834 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
2835 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
2836 else if (const_index
&& !compact_const_index
)
2837 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2838 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2840 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2841 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
2843 if (const_index
&& compact_const_index
)
2844 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2845 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2850 load_tcs_varyings(struct ac_shader_abi
*abi
,
2852 LLVMValueRef vertex_index
,
2853 LLVMValueRef indir_index
,
2854 unsigned const_index
,
2856 unsigned driver_location
,
2858 unsigned num_components
,
2863 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2864 LLVMValueRef dw_addr
, stride
;
2865 LLVMValueRef value
[4], result
;
2866 unsigned param
= shader_io_get_unique_index(location
);
2869 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2870 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2873 stride
= get_tcs_out_vertex_stride(ctx
);
2874 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2876 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2881 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2884 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
2885 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2886 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2889 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
2894 store_tcs_output(struct ac_shader_abi
*abi
,
2895 LLVMValueRef vertex_index
,
2896 LLVMValueRef param_index
,
2897 unsigned const_index
,
2899 unsigned driver_location
,
2906 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2907 LLVMValueRef dw_addr
;
2908 LLVMValueRef stride
= NULL
;
2909 LLVMValueRef buf_addr
= NULL
;
2911 bool store_lds
= true;
2914 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
2917 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
2921 param
= shader_io_get_unique_index(location
);
2922 if (location
== VARYING_SLOT_CLIP_DIST0
&&
2923 is_compact
&& const_index
> 3) {
2929 stride
= get_tcs_out_vertex_stride(ctx
);
2930 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2932 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2935 mark_tess_output(ctx
, is_patch
, param
);
2937 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2939 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2940 vertex_index
, param_index
);
2942 bool is_tess_factor
= false;
2943 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2944 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2945 is_tess_factor
= true;
2947 unsigned base
= is_compact
? const_index
: 0;
2948 for (unsigned chan
= 0; chan
< 8; chan
++) {
2949 if (!(writemask
& (1 << chan
)))
2951 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
2953 if (store_lds
|| is_tess_factor
) {
2954 LLVMValueRef dw_addr_chan
=
2955 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2956 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
2957 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
2960 if (!is_tess_factor
&& writemask
!= 0xF)
2961 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
2962 buf_addr
, ctx
->oc_lds
,
2963 4 * (base
+ chan
), 1, 0, true, false);
2966 if (writemask
== 0xF) {
2967 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
2968 buf_addr
, ctx
->oc_lds
,
2969 (base
* 4), 1, 0, true, false);
2974 load_tes_input(struct ac_shader_abi
*abi
,
2976 LLVMValueRef vertex_index
,
2977 LLVMValueRef param_index
,
2978 unsigned const_index
,
2980 unsigned driver_location
,
2982 unsigned num_components
,
2987 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2988 LLVMValueRef buf_addr
;
2989 LLVMValueRef result
;
2990 unsigned param
= shader_io_get_unique_index(location
);
2992 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
2997 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
2998 is_compact
, vertex_index
, param_index
);
3000 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
3001 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
3003 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
3004 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
3005 result
= trim_vector(&ctx
->ac
, result
, num_components
);
3010 load_gs_input(struct ac_shader_abi
*abi
,
3012 unsigned driver_location
,
3014 unsigned num_components
,
3015 unsigned vertex_index
,
3016 unsigned const_index
,
3019 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3020 LLVMValueRef vtx_offset
;
3021 unsigned param
, vtx_offset_param
;
3022 LLVMValueRef value
[4], result
;
3024 vtx_offset_param
= vertex_index
;
3025 assert(vtx_offset_param
< 6);
3026 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
3027 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3029 param
= shader_io_get_unique_index(location
);
3031 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
3032 if (ctx
->ac
.chip_class
>= GFX9
) {
3033 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
3034 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3035 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
3036 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
3038 LLVMValueRef soffset
=
3039 LLVMConstInt(ctx
->ac
.i32
,
3040 (param
* 4 + i
+ const_index
) * 256,
3043 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
3046 vtx_offset
, soffset
,
3047 0, 1, 0, true, false);
3049 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
],
3053 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
3054 result
= ac_to_integer(&ctx
->ac
, result
);
3059 build_gep_for_deref(struct ac_nir_context
*ctx
,
3060 nir_deref_var
*deref
)
3062 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
3063 assert(entry
->data
);
3064 LLVMValueRef val
= entry
->data
;
3065 nir_deref
*tail
= deref
->deref
.child
;
3066 while (tail
!= NULL
) {
3067 LLVMValueRef offset
;
3068 switch (tail
->deref_type
) {
3069 case nir_deref_type_array
: {
3070 nir_deref_array
*array
= nir_deref_as_array(tail
);
3071 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
3072 if (array
->deref_array_type
==
3073 nir_deref_array_type_indirect
) {
3074 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
3081 case nir_deref_type_struct
: {
3082 nir_deref_struct
*deref_struct
=
3083 nir_deref_as_struct(tail
);
3084 offset
= LLVMConstInt(ctx
->ac
.i32
,
3085 deref_struct
->index
, 0);
3089 unreachable("bad deref type");
3091 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
3097 static LLVMValueRef
load_tess_varyings(struct ac_nir_context
*ctx
,
3098 nir_intrinsic_instr
*instr
,
3101 LLVMValueRef result
;
3102 LLVMValueRef vertex_index
= NULL
;
3103 LLVMValueRef indir_index
= NULL
;
3104 unsigned const_index
= 0;
3105 unsigned location
= instr
->variables
[0]->var
->data
.location
;
3106 unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3107 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3108 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3110 get_deref_offset(ctx
, instr
->variables
[0],
3111 false, NULL
, is_patch
? NULL
: &vertex_index
,
3112 &const_index
, &indir_index
);
3114 LLVMTypeRef dest_type
= get_def_type(ctx
, &instr
->dest
.ssa
);
3116 LLVMTypeRef src_component_type
;
3117 if (LLVMGetTypeKind(dest_type
) == LLVMVectorTypeKind
)
3118 src_component_type
= LLVMGetElementType(dest_type
);
3120 src_component_type
= dest_type
;
3122 result
= ctx
->abi
->load_tess_varyings(ctx
->abi
, src_component_type
,
3123 vertex_index
, indir_index
,
3124 const_index
, location
, driver_location
,
3125 instr
->variables
[0]->var
->data
.location_frac
,
3126 instr
->num_components
,
3127 is_patch
, is_compact
, load_inputs
);
3128 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, dest_type
, "");
3131 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
3132 nir_intrinsic_instr
*instr
)
3134 LLVMValueRef values
[8];
3135 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3136 int ve
= instr
->dest
.ssa
.num_components
;
3137 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3138 LLVMValueRef indir_index
;
3140 unsigned const_index
;
3141 unsigned stride
= instr
->variables
[0]->var
->data
.compact
? 1 : 4;
3142 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3143 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3144 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3145 &const_index
, &indir_index
);
3147 if (instr
->dest
.ssa
.bit_size
== 64)
3150 switch (instr
->variables
[0]->var
->data
.mode
) {
3151 case nir_var_shader_in
:
3152 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3153 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3154 return load_tess_varyings(ctx
, instr
, true);
3157 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3158 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->dest
.ssa
.bit_size
);
3159 LLVMValueRef indir_index
;
3160 unsigned const_index
, vertex_index
;
3161 get_deref_offset(ctx
, instr
->variables
[0],
3162 false, &vertex_index
, NULL
,
3163 &const_index
, &indir_index
);
3165 return ctx
->abi
->load_inputs(ctx
->abi
, instr
->variables
[0]->var
->data
.location
,
3166 instr
->variables
[0]->var
->data
.driver_location
,
3167 instr
->variables
[0]->var
->data
.location_frac
,
3168 instr
->num_components
, vertex_index
, const_index
, type
);
3171 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3173 unsigned count
= glsl_count_attribute_slots(
3174 instr
->variables
[0]->var
->type
,
3175 ctx
->stage
== MESA_SHADER_VERTEX
);
3177 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3178 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3179 stride
, false, true);
3181 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3185 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* stride
];
3189 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3191 unsigned count
= glsl_count_attribute_slots(
3192 instr
->variables
[0]->var
->type
, false);
3194 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3195 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3196 stride
, true, true);
3198 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3202 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* stride
], "");
3206 case nir_var_shared
: {
3207 LLVMValueRef address
= build_gep_for_deref(ctx
,
3208 instr
->variables
[0]);
3209 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3210 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3211 get_def_type(ctx
, &instr
->dest
.ssa
),
3214 case nir_var_shader_out
:
3215 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3216 return load_tess_varyings(ctx
, instr
, false);
3219 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3221 unsigned count
= glsl_count_attribute_slots(
3222 instr
->variables
[0]->var
->type
, false);
3224 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3225 &ctx
->ac
, ctx
->abi
->outputs
+ idx
+ chan
, count
,
3226 stride
, true, true);
3228 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3232 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3233 ctx
->abi
->outputs
[idx
+ chan
+ const_index
* stride
],
3239 unreachable("unhandle variable mode");
3241 ret
= ac_build_varying_gather_values(&ctx
->ac
, values
, ve
, comp
);
3242 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3246 visit_store_var(struct ac_nir_context
*ctx
,
3247 nir_intrinsic_instr
*instr
)
3249 LLVMValueRef temp_ptr
, value
;
3250 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3251 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3252 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3253 int writemask
= instr
->const_index
[0] << comp
;
3254 LLVMValueRef indir_index
;
3255 unsigned const_index
;
3256 get_deref_offset(ctx
, instr
->variables
[0], false,
3257 NULL
, NULL
, &const_index
, &indir_index
);
3259 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3261 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3262 LLVMVectorType(ctx
->ac
.f32
, ac_get_llvm_num_components(src
) * 2),
3265 writemask
= widen_mask(writemask
, 2);
3268 switch (instr
->variables
[0]->var
->data
.mode
) {
3269 case nir_var_shader_out
:
3271 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3272 LLVMValueRef vertex_index
= NULL
;
3273 LLVMValueRef indir_index
= NULL
;
3274 unsigned const_index
= 0;
3275 const unsigned location
= instr
->variables
[0]->var
->data
.location
;
3276 const unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3277 const unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3278 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3279 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3281 get_deref_offset(ctx
, instr
->variables
[0],
3282 false, NULL
, is_patch
? NULL
: &vertex_index
,
3283 &const_index
, &indir_index
);
3285 ctx
->abi
->store_tcs_outputs(ctx
->abi
, vertex_index
, indir_index
,
3286 const_index
, location
, driver_location
,
3287 src
, comp
, is_patch
, is_compact
, writemask
);
3291 for (unsigned chan
= 0; chan
< 8; chan
++) {
3293 if (!(writemask
& (1 << chan
)))
3296 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
3298 if (instr
->variables
[0]->var
->data
.compact
)
3301 unsigned count
= glsl_count_attribute_slots(
3302 instr
->variables
[0]->var
->type
, false);
3304 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3305 &ctx
->ac
, ctx
->abi
->outputs
+ idx
+ chan
, count
,
3306 stride
, true, true);
3308 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3309 value
, indir_index
, "");
3310 build_store_values_extended(&ctx
->ac
, ctx
->abi
->outputs
+ idx
+ chan
,
3311 count
, stride
, tmp_vec
);
3314 temp_ptr
= ctx
->abi
->outputs
[idx
+ chan
+ const_index
* stride
];
3316 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3321 for (unsigned chan
= 0; chan
< 8; chan
++) {
3322 if (!(writemask
& (1 << chan
)))
3325 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3327 unsigned count
= glsl_count_attribute_slots(
3328 instr
->variables
[0]->var
->type
, false);
3330 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3331 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3334 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3335 value
, indir_index
, "");
3336 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3339 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3341 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3345 case nir_var_shared
: {
3346 int writemask
= instr
->const_index
[0];
3347 LLVMValueRef address
= build_gep_for_deref(ctx
,
3348 instr
->variables
[0]);
3349 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3350 unsigned components
=
3351 glsl_get_vector_elements(
3352 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3353 if (writemask
== (1 << components
) - 1) {
3354 val
= LLVMBuildBitCast(
3355 ctx
->ac
.builder
, val
,
3356 LLVMGetElementType(LLVMTypeOf(address
)), "");
3357 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3359 for (unsigned chan
= 0; chan
< 4; chan
++) {
3360 if (!(writemask
& (1 << chan
)))
3363 LLVMBuildStructGEP(ctx
->ac
.builder
,
3365 LLVMValueRef src
= ac_llvm_extract_elem(&ctx
->ac
, val
,
3367 src
= LLVMBuildBitCast(
3368 ctx
->ac
.builder
, src
,
3369 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3370 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3380 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3383 case GLSL_SAMPLER_DIM_BUF
:
3385 case GLSL_SAMPLER_DIM_1D
:
3386 return array
? 2 : 1;
3387 case GLSL_SAMPLER_DIM_2D
:
3388 return array
? 3 : 2;
3389 case GLSL_SAMPLER_DIM_MS
:
3390 return array
? 4 : 3;
3391 case GLSL_SAMPLER_DIM_3D
:
3392 case GLSL_SAMPLER_DIM_CUBE
:
3394 case GLSL_SAMPLER_DIM_RECT
:
3395 case GLSL_SAMPLER_DIM_SUBPASS
:
3397 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3406 glsl_is_array_image(const struct glsl_type
*type
)
3408 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3410 if (glsl_sampler_type_is_array(type
))
3413 return dim
== GLSL_SAMPLER_DIM_CUBE
||
3414 dim
== GLSL_SAMPLER_DIM_3D
||
3415 dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3416 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
;
3420 /* Adjust the sample index according to FMASK.
3422 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3423 * which is the identity mapping. Each nibble says which physical sample
3424 * should be fetched to get that sample.
3426 * For example, 0x11111100 means there are only 2 samples stored and
3427 * the second sample covers 3/4 of the pixel. When reading samples 0
3428 * and 1, return physical sample 0 (determined by the first two 0s
3429 * in FMASK), otherwise return physical sample 1.
3431 * The sample index should be adjusted as follows:
3432 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3434 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3435 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3436 LLVMValueRef coord_z
,
3437 LLVMValueRef sample_index
,
3438 LLVMValueRef fmask_desc_ptr
)
3440 LLVMValueRef fmask_load_address
[4];
3443 fmask_load_address
[0] = coord_x
;
3444 fmask_load_address
[1] = coord_y
;
3446 fmask_load_address
[2] = coord_z
;
3447 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3450 struct ac_image_args args
= {0};
3452 args
.opcode
= ac_image_load
;
3453 args
.da
= coord_z
? true : false;
3454 args
.resource
= fmask_desc_ptr
;
3456 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3458 res
= ac_build_image_opcode(ctx
, &args
);
3460 res
= ac_to_integer(ctx
, res
);
3461 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3462 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3464 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3468 LLVMValueRef sample_index4
=
3469 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3470 LLVMValueRef shifted_fmask
=
3471 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3472 LLVMValueRef final_sample
=
3473 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3475 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3476 * resource descriptor is 0 (invalid),
3478 LLVMValueRef fmask_desc
=
3479 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3482 LLVMValueRef fmask_word1
=
3483 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3486 LLVMValueRef word1_is_nonzero
=
3487 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3488 fmask_word1
, ctx
->i32_0
, "");
3490 /* Replace the MSAA sample index. */
3492 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3493 final_sample
, sample_index
, "");
3494 return sample_index
;
3497 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3498 const nir_intrinsic_instr
*instr
)
3500 const struct glsl_type
*type
= glsl_without_array(instr
->variables
[0]->var
->type
);
3502 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3503 LLVMValueRef coords
[4];
3504 LLVMValueRef masks
[] = {
3505 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3506 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3509 LLVMValueRef sample_index
= ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3512 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3513 bool is_array
= glsl_sampler_type_is_array(type
);
3514 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3515 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3516 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3517 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3518 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3519 count
= image_type_to_components_count(dim
, is_array
);
3522 LLVMValueRef fmask_load_address
[3];
3525 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3526 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3528 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3530 fmask_load_address
[2] = NULL
;
3532 for (chan
= 0; chan
< 2; ++chan
)
3533 fmask_load_address
[chan
] =
3534 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3535 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3536 ctx
->ac
.i32
, ""), "");
3537 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3539 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3540 fmask_load_address
[0],
3541 fmask_load_address
[1],
3542 fmask_load_address
[2],
3544 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, NULL
, true, false));
3546 if (count
== 1 && !gfx9_1d
) {
3547 if (instr
->src
[0].ssa
->num_components
)
3548 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3555 for (chan
= 0; chan
< count
; ++chan
) {
3556 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3559 for (chan
= 0; chan
< 2; ++chan
)
3560 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3561 ctx
->ac
.i32
, ""), "");
3562 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3568 coords
[2] = coords
[1];
3569 coords
[1] = ctx
->ac
.i32_0
;
3571 coords
[1] = ctx
->ac
.i32_0
;
3576 coords
[count
] = sample_index
;
3581 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3584 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3589 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3590 const nir_intrinsic_instr
*instr
)
3592 LLVMValueRef params
[7];
3594 char intrinsic_name
[64];
3595 const nir_variable
*var
= instr
->variables
[0]->var
;
3596 const struct glsl_type
*type
= var
->type
;
3598 if(instr
->variables
[0]->deref
.child
)
3599 type
= instr
->variables
[0]->deref
.child
->type
;
3601 type
= glsl_without_array(type
);
3603 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3604 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3605 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
3606 unsigned num_channels
= util_last_bit(mask
);
3607 LLVMValueRef rsrc
, vindex
;
3609 rsrc
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, false);
3610 vindex
= LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3613 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3614 res
= ac_build_buffer_load_format(&ctx
->ac
, rsrc
, vindex
,
3615 ctx
->ac
.i32_0
, num_channels
,
3617 res
= ac_build_expand_to_vec4(&ctx
->ac
, res
, num_channels
);
3619 res
= trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3620 res
= ac_to_integer(&ctx
->ac
, res
);
3622 LLVMValueRef da
= glsl_is_array_image(type
) ? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3623 LLVMValueRef slc
= ctx
->ac
.i1false
;
3625 params
[0] = get_image_coords(ctx
, instr
);
3626 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3627 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3628 params
[3] = (var
->data
.image
._volatile
|| var
->data
.image
.coherent
) ?
3629 ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3631 params
[5] = ctx
->ac
.i1false
;
3634 ac_get_image_intr_name("llvm.amdgcn.image.load",
3635 ctx
->ac
.v4f32
, /* vdata */
3636 LLVMTypeOf(params
[0]), /* coords */
3637 LLVMTypeOf(params
[1]), /* rsrc */
3638 intrinsic_name
, sizeof(intrinsic_name
));
3640 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3641 params
, 7, AC_FUNC_ATTR_READONLY
);
3643 return ac_to_integer(&ctx
->ac
, res
);
3646 static void visit_image_store(struct ac_nir_context
*ctx
,
3647 nir_intrinsic_instr
*instr
)
3649 LLVMValueRef params
[8];
3650 char intrinsic_name
[64];
3651 const nir_variable
*var
= instr
->variables
[0]->var
;
3652 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3653 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3654 LLVMValueRef glc
= ctx
->ac
.i1false
;
3655 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3657 glc
= ctx
->ac
.i1true
;
3659 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3660 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3661 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, true);
3662 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3663 ctx
->ac
.i32_0
, ""); /* vindex */
3664 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3665 params
[4] = glc
; /* glc */
3666 params
[5] = ctx
->ac
.i1false
; /* slc */
3667 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3670 LLVMValueRef da
= glsl_is_array_image(type
) ? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3671 LLVMValueRef slc
= ctx
->ac
.i1false
;
3673 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3674 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3675 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, true);
3676 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3677 params
[4] = (force_glc
|| var
->data
.image
._volatile
|| var
->data
.image
.coherent
) ?
3678 ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3680 params
[6] = ctx
->ac
.i1false
;
3683 ac_get_image_intr_name("llvm.amdgcn.image.store",
3684 LLVMTypeOf(params
[0]), /* vdata */
3685 LLVMTypeOf(params
[1]), /* coords */
3686 LLVMTypeOf(params
[2]), /* rsrc */
3687 intrinsic_name
, sizeof(intrinsic_name
));
3689 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3695 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3696 const nir_intrinsic_instr
*instr
)
3698 LLVMValueRef params
[7];
3699 int param_count
= 0;
3700 const nir_variable
*var
= instr
->variables
[0]->var
;
3702 const char *atomic_name
;
3703 char intrinsic_name
[41];
3704 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3705 MAYBE_UNUSED
int length
;
3707 bool is_unsigned
= glsl_get_sampler_result_type(type
) == GLSL_TYPE_UINT
;
3709 switch (instr
->intrinsic
) {
3710 case nir_intrinsic_image_atomic_add
:
3711 atomic_name
= "add";
3713 case nir_intrinsic_image_atomic_min
:
3714 atomic_name
= is_unsigned
? "umin" : "smin";
3716 case nir_intrinsic_image_atomic_max
:
3717 atomic_name
= is_unsigned
? "umax" : "smax";
3719 case nir_intrinsic_image_atomic_and
:
3720 atomic_name
= "and";
3722 case nir_intrinsic_image_atomic_or
:
3725 case nir_intrinsic_image_atomic_xor
:
3726 atomic_name
= "xor";
3728 case nir_intrinsic_image_atomic_exchange
:
3729 atomic_name
= "swap";
3731 case nir_intrinsic_image_atomic_comp_swap
:
3732 atomic_name
= "cmpswap";
3738 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3739 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3740 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3742 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3743 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3745 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3746 ctx
->ac
.i32_0
, ""); /* vindex */
3747 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3748 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3750 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3751 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3753 char coords_type
[8];
3755 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3756 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3758 params
[param_count
++] = ctx
->ac
.i1false
; /* r128 */
3759 params
[param_count
++] = glsl_is_array_image(type
) ? ctx
->ac
.i1true
: ctx
->ac
.i1false
; /* da */
3760 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3762 build_int_type_name(LLVMTypeOf(coords
),
3763 coords_type
, sizeof(coords_type
));
3765 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3766 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3769 assert(length
< sizeof(intrinsic_name
));
3770 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3773 static LLVMValueRef
visit_image_samples(struct ac_nir_context
*ctx
,
3774 const nir_intrinsic_instr
*instr
)
3776 const nir_variable
*var
= instr
->variables
[0]->var
;
3777 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3779 struct ac_image_args args
= { 0 };
3780 args
.da
= glsl_is_array_image(type
);
3782 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0],
3783 AC_DESC_IMAGE
, NULL
, true, false);
3784 args
.opcode
= ac_image_get_resinfo
;
3785 args
.addr
= ctx
->ac
.i32_0
;
3787 return ac_build_image_opcode(&ctx
->ac
, &args
);
3790 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3791 const nir_intrinsic_instr
*instr
)
3794 const nir_variable
*var
= instr
->variables
[0]->var
;
3795 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3797 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3798 return get_buffer_size(ctx
,
3799 get_sampler_desc(ctx
, instr
->variables
[0],
3800 AC_DESC_BUFFER
, NULL
, true, false), true);
3802 struct ac_image_args args
= { 0 };
3804 args
.da
= glsl_is_array_image(type
);
3806 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3807 args
.opcode
= ac_image_get_resinfo
;
3808 args
.addr
= ctx
->ac
.i32_0
;
3810 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3812 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3814 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3815 glsl_sampler_type_is_array(type
)) {
3816 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3817 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3818 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3819 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3821 if (ctx
->ac
.chip_class
>= GFX9
&&
3822 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3823 glsl_sampler_type_is_array(type
)) {
3824 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3825 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3832 #define NOOP_WAITCNT 0xf7f
3833 #define LGKM_CNT 0x07f
3834 #define VM_CNT 0xf70
3836 static void emit_membar(struct ac_llvm_context
*ac
,
3837 const nir_intrinsic_instr
*instr
)
3839 unsigned waitcnt
= NOOP_WAITCNT
;
3841 switch (instr
->intrinsic
) {
3842 case nir_intrinsic_memory_barrier
:
3843 case nir_intrinsic_group_memory_barrier
:
3844 waitcnt
&= VM_CNT
& LGKM_CNT
;
3846 case nir_intrinsic_memory_barrier_atomic_counter
:
3847 case nir_intrinsic_memory_barrier_buffer
:
3848 case nir_intrinsic_memory_barrier_image
:
3851 case nir_intrinsic_memory_barrier_shared
:
3852 waitcnt
&= LGKM_CNT
;
3857 if (waitcnt
!= NOOP_WAITCNT
)
3858 ac_build_waitcnt(ac
, waitcnt
);
3861 static void emit_barrier(struct ac_llvm_context
*ac
, gl_shader_stage stage
)
3863 /* SI only (thanks to a hw bug workaround):
3864 * The real barrier instruction isn’t needed, because an entire patch
3865 * always fits into a single wave.
3867 if (ac
->chip_class
== SI
&& stage
== MESA_SHADER_TESS_CTRL
) {
3868 ac_build_waitcnt(ac
, LGKM_CNT
& VM_CNT
);
3871 ac_build_intrinsic(ac
, "llvm.amdgcn.s.barrier",
3872 ac
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3875 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
3877 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3878 ac_build_kill_if_false(&ctx
->ac
, visible
);
3881 static void emit_discard(struct ac_nir_context
*ctx
,
3882 const nir_intrinsic_instr
*instr
)
3886 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3887 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3888 get_src(ctx
, instr
->src
[0]),
3891 assert(instr
->intrinsic
== nir_intrinsic_discard
);
3892 cond
= LLVMConstInt(ctx
->ac
.i1
, false, 0);
3895 ctx
->abi
->emit_kill(ctx
->abi
, cond
);
3899 visit_load_helper_invocation(struct ac_nir_context
*ctx
)
3901 LLVMValueRef result
= ac_build_intrinsic(&ctx
->ac
,
3902 "llvm.amdgcn.ps.live",
3903 ctx
->ac
.i1
, NULL
, 0,
3904 AC_FUNC_ATTR_READNONE
);
3905 result
= LLVMBuildNot(ctx
->ac
.builder
, result
, "");
3906 return LLVMBuildSExt(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
3910 visit_load_local_invocation_index(struct ac_nir_context
*ctx
)
3912 LLVMValueRef result
;
3913 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3914 result
= LLVMBuildAnd(ctx
->ac
.builder
, ctx
->abi
->tg_size
,
3915 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3917 return LLVMBuildAdd(ctx
->ac
.builder
, result
, thread_id
, "");
3921 visit_load_subgroup_id(struct ac_nir_context
*ctx
)
3923 if (ctx
->stage
== MESA_SHADER_COMPUTE
) {
3924 LLVMValueRef result
;
3925 result
= LLVMBuildAnd(ctx
->ac
.builder
, ctx
->abi
->tg_size
,
3926 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3927 return LLVMBuildLShr(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 6, false), "");
3929 return LLVMConstInt(ctx
->ac
.i32
, 0, false);
3934 visit_load_num_subgroups(struct ac_nir_context
*ctx
)
3936 if (ctx
->stage
== MESA_SHADER_COMPUTE
) {
3937 return LLVMBuildAnd(ctx
->ac
.builder
, ctx
->abi
->tg_size
,
3938 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
3940 return LLVMConstInt(ctx
->ac
.i32
, 1, false);
3945 visit_first_invocation(struct ac_nir_context
*ctx
)
3947 LLVMValueRef active_set
= ac_build_ballot(&ctx
->ac
, ctx
->ac
.i32_1
);
3949 /* The second argument is whether cttz(0) should be defined, but we do not care. */
3950 LLVMValueRef args
[] = {active_set
, LLVMConstInt(ctx
->ac
.i1
, 0, false)};
3951 LLVMValueRef result
= ac_build_intrinsic(&ctx
->ac
,
3953 ctx
->ac
.i64
, args
, 2,
3954 AC_FUNC_ATTR_NOUNWIND
|
3955 AC_FUNC_ATTR_READNONE
);
3957 return LLVMBuildTrunc(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
3961 visit_load_shared(struct ac_nir_context
*ctx
,
3962 const nir_intrinsic_instr
*instr
)
3964 LLVMValueRef values
[4], derived_ptr
, index
, ret
;
3966 LLVMValueRef ptr
= get_memory_ptr(ctx
, instr
->src
[0]);
3968 for (int chan
= 0; chan
< instr
->num_components
; chan
++) {
3969 index
= LLVMConstInt(ctx
->ac
.i32
, chan
, 0);
3970 derived_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
3971 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, derived_ptr
, "");
3974 ret
= ac_build_gather_values(&ctx
->ac
, values
, instr
->num_components
);
3975 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3979 visit_store_shared(struct ac_nir_context
*ctx
,
3980 const nir_intrinsic_instr
*instr
)
3982 LLVMValueRef derived_ptr
, data
,index
;
3983 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3985 LLVMValueRef ptr
= get_memory_ptr(ctx
, instr
->src
[1]);
3986 LLVMValueRef src
= get_src(ctx
, instr
->src
[0]);
3988 int writemask
= nir_intrinsic_write_mask(instr
);
3989 for (int chan
= 0; chan
< 4; chan
++) {
3990 if (!(writemask
& (1 << chan
))) {
3993 data
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3994 index
= LLVMConstInt(ctx
->ac
.i32
, chan
, 0);
3995 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
3996 LLVMBuildStore(builder
, data
, derived_ptr
);
4000 static LLVMValueRef
visit_var_atomic(struct ac_nir_context
*ctx
,
4001 const nir_intrinsic_instr
*instr
,
4002 LLVMValueRef ptr
, int src_idx
)
4004 LLVMValueRef result
;
4005 LLVMValueRef src
= get_src(ctx
, instr
->src
[src_idx
]);
4007 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
||
4008 instr
->intrinsic
== nir_intrinsic_shared_atomic_comp_swap
) {
4009 LLVMValueRef src1
= get_src(ctx
, instr
->src
[src_idx
+ 1]);
4010 result
= LLVMBuildAtomicCmpXchg(ctx
->ac
.builder
,
4012 LLVMAtomicOrderingSequentiallyConsistent
,
4013 LLVMAtomicOrderingSequentiallyConsistent
,
4016 LLVMAtomicRMWBinOp op
;
4017 switch (instr
->intrinsic
) {
4018 case nir_intrinsic_var_atomic_add
:
4019 case nir_intrinsic_shared_atomic_add
:
4020 op
= LLVMAtomicRMWBinOpAdd
;
4022 case nir_intrinsic_var_atomic_umin
:
4023 case nir_intrinsic_shared_atomic_umin
:
4024 op
= LLVMAtomicRMWBinOpUMin
;
4026 case nir_intrinsic_var_atomic_umax
:
4027 case nir_intrinsic_shared_atomic_umax
:
4028 op
= LLVMAtomicRMWBinOpUMax
;
4030 case nir_intrinsic_var_atomic_imin
:
4031 case nir_intrinsic_shared_atomic_imin
:
4032 op
= LLVMAtomicRMWBinOpMin
;
4034 case nir_intrinsic_var_atomic_imax
:
4035 case nir_intrinsic_shared_atomic_imax
:
4036 op
= LLVMAtomicRMWBinOpMax
;
4038 case nir_intrinsic_var_atomic_and
:
4039 case nir_intrinsic_shared_atomic_and
:
4040 op
= LLVMAtomicRMWBinOpAnd
;
4042 case nir_intrinsic_var_atomic_or
:
4043 case nir_intrinsic_shared_atomic_or
:
4044 op
= LLVMAtomicRMWBinOpOr
;
4046 case nir_intrinsic_var_atomic_xor
:
4047 case nir_intrinsic_shared_atomic_xor
:
4048 op
= LLVMAtomicRMWBinOpXor
;
4050 case nir_intrinsic_var_atomic_exchange
:
4051 case nir_intrinsic_shared_atomic_exchange
:
4052 op
= LLVMAtomicRMWBinOpXchg
;
4058 result
= LLVMBuildAtomicRMW(ctx
->ac
.builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
4059 LLVMAtomicOrderingSequentiallyConsistent
,
4065 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
4066 enum glsl_interp_mode interp
, unsigned location
)
4068 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4071 case INTERP_MODE_FLAT
:
4074 case INTERP_MODE_SMOOTH
:
4075 case INTERP_MODE_NONE
:
4076 if (location
== INTERP_CENTER
)
4077 return ctx
->persp_center
;
4078 else if (location
== INTERP_CENTROID
)
4079 return ctx
->persp_centroid
;
4080 else if (location
== INTERP_SAMPLE
)
4081 return ctx
->persp_sample
;
4083 case INTERP_MODE_NOPERSPECTIVE
:
4084 if (location
== INTERP_CENTER
)
4085 return ctx
->linear_center
;
4086 else if (location
== INTERP_CENTROID
)
4087 return ctx
->linear_centroid
;
4088 else if (location
== INTERP_SAMPLE
)
4089 return ctx
->linear_sample
;
4095 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
4096 LLVMValueRef sample_id
)
4098 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4100 LLVMValueRef result
;
4101 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
4103 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
4104 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
4106 sample_id
= LLVMBuildAdd(ctx
->ac
.builder
, sample_id
, ctx
->sample_pos_offset
, "");
4107 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
4112 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
4114 LLVMValueRef values
[2];
4115 LLVMValueRef pos
[2];
4117 pos
[0] = ac_to_float(&ctx
->ac
, ctx
->abi
->frag_pos
[0]);
4118 pos
[1] = ac_to_float(&ctx
->ac
, ctx
->abi
->frag_pos
[1]);
4120 values
[0] = ac_build_fract(&ctx
->ac
, pos
[0], 32);
4121 values
[1] = ac_build_fract(&ctx
->ac
, pos
[1], 32);
4122 return ac_build_gather_values(&ctx
->ac
, values
, 2);
4125 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
4127 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4128 uint8_t log2_ps_iter_samples
= ctx
->shader_info
->info
.ps
.force_persample
?
4129 ctx
->options
->key
.fs
.log2_num_samples
:
4130 ctx
->options
->key
.fs
.log2_ps_iter_samples
;
4132 /* The bit pattern matches that used by fixed function fragment
4134 static const uint16_t ps_iter_masks
[] = {
4135 0xffff, /* not used */
4141 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
4143 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
4145 LLVMValueRef result
, sample_id
;
4146 sample_id
= unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
4147 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
4148 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
4152 static LLVMValueRef
visit_interp(struct ac_nir_context
*ctx
,
4153 const nir_intrinsic_instr
*instr
)
4155 LLVMValueRef result
[4];
4156 LLVMValueRef interp_param
, attr_number
;
4159 LLVMValueRef src_c0
= NULL
;
4160 LLVMValueRef src_c1
= NULL
;
4161 LLVMValueRef src0
= NULL
;
4162 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
4163 switch (instr
->intrinsic
) {
4164 case nir_intrinsic_interp_var_at_centroid
:
4165 location
= INTERP_CENTROID
;
4167 case nir_intrinsic_interp_var_at_sample
:
4168 case nir_intrinsic_interp_var_at_offset
:
4169 location
= INTERP_CENTER
;
4170 src0
= get_src(ctx
, instr
->src
[0]);
4176 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
4177 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, ctx
->ac
.i32_0
, ""));
4178 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, ctx
->ac
.i32_1
, ""));
4179 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
4180 LLVMValueRef sample_position
;
4181 LLVMValueRef halfval
= LLVMConstReal(ctx
->ac
.f32
, 0.5f
);
4183 /* fetch sample ID */
4184 sample_position
= ctx
->abi
->load_sample_position(ctx
->abi
, src0
);
4186 src_c0
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
, ctx
->ac
.i32_0
, "");
4187 src_c0
= LLVMBuildFSub(ctx
->ac
.builder
, src_c0
, halfval
, "");
4188 src_c1
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
, ctx
->ac
.i32_1
, "");
4189 src_c1
= LLVMBuildFSub(ctx
->ac
.builder
, src_c1
, halfval
, "");
4191 interp_param
= ctx
->abi
->lookup_interp_param(ctx
->abi
, instr
->variables
[0]->var
->data
.interpolation
, location
);
4192 attr_number
= LLVMConstInt(ctx
->ac
.i32
, input_index
, false);
4194 if (location
== INTERP_CENTER
) {
4195 LLVMValueRef ij_out
[2];
4196 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
, interp_param
);
4199 * take the I then J parameters, and the DDX/Y for it, and
4200 * calculate the IJ inputs for the interpolator.
4201 * temp1 = ddx * offset/sample.x + I;
4202 * interp_param.I = ddy * offset/sample.y + temp1;
4203 * temp1 = ddx * offset/sample.x + J;
4204 * interp_param.J = ddy * offset/sample.y + temp1;
4206 for (unsigned i
= 0; i
< 2; i
++) {
4207 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->ac
.i32
, i
, false);
4208 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->ac
.i32
, i
+ 2, false);
4209 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4210 ddxy_out
, ix_ll
, "");
4211 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4212 ddxy_out
, iy_ll
, "");
4213 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4214 interp_param
, ix_ll
, "");
4215 LLVMValueRef temp1
, temp2
;
4217 interp_el
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_el
,
4220 temp1
= LLVMBuildFMul(ctx
->ac
.builder
, ddx_el
, src_c0
, "");
4221 temp1
= LLVMBuildFAdd(ctx
->ac
.builder
, temp1
, interp_el
, "");
4223 temp2
= LLVMBuildFMul(ctx
->ac
.builder
, ddy_el
, src_c1
, "");
4224 temp2
= LLVMBuildFAdd(ctx
->ac
.builder
, temp2
, temp1
, "");
4226 ij_out
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
,
4227 temp2
, ctx
->ac
.i32
, "");
4229 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4233 for (chan
= 0; chan
< 4; chan
++) {
4234 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
4237 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
,
4238 interp_param
, ctx
->ac
.v2f32
, "");
4239 LLVMValueRef i
= LLVMBuildExtractElement(
4240 ctx
->ac
.builder
, interp_param
, ctx
->ac
.i32_0
, "");
4241 LLVMValueRef j
= LLVMBuildExtractElement(
4242 ctx
->ac
.builder
, interp_param
, ctx
->ac
.i32_1
, "");
4244 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
4245 llvm_chan
, attr_number
,
4246 ctx
->abi
->prim_mask
, i
, j
);
4248 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
4249 LLVMConstInt(ctx
->ac
.i32
, 2, false),
4250 llvm_chan
, attr_number
,
4251 ctx
->abi
->prim_mask
);
4254 return ac_build_varying_gather_values(&ctx
->ac
, result
, instr
->num_components
,
4255 instr
->variables
[0]->var
->data
.location_frac
);
4259 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
4261 LLVMValueRef gs_next_vertex
;
4262 LLVMValueRef can_emit
;
4264 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4266 assert(stream
== 0);
4268 /* Write vertex attribute values to GSVS ring */
4269 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
4270 ctx
->gs_next_vertex
,
4273 /* If this thread has already emitted the declared maximum number of
4274 * vertices, kill it: excessive vertex emissions are not supposed to
4275 * have any effect, and GS threads have no externally observable
4276 * effects other than emitting vertices.
4278 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
4279 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
4280 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4282 /* loop num outputs */
4284 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4285 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
4290 if (!(ctx
->output_mask
& (1ull << i
)))
4293 if (i
== VARYING_SLOT_CLIP_DIST0
) {
4294 /* pack clip and cull into a single set of slots */
4295 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4299 for (unsigned j
= 0; j
< length
; j
++) {
4300 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
4302 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4303 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
4304 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4306 out_val
= LLVMBuildBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
4308 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4310 voffset
, ctx
->gs2vs_offset
, 0,
4316 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
4318 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4320 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4324 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
4326 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4327 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
4331 load_tess_coord(struct ac_shader_abi
*abi
)
4333 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4335 LLVMValueRef coord
[4] = {
4342 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4343 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
4344 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
4346 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
4350 load_patch_vertices_in(struct ac_shader_abi
*abi
)
4352 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4353 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
4356 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4357 nir_intrinsic_instr
*instr
)
4359 LLVMValueRef result
= NULL
;
4361 switch (instr
->intrinsic
) {
4362 case nir_intrinsic_ballot
:
4363 result
= ac_build_ballot(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4365 case nir_intrinsic_read_invocation
:
4366 case nir_intrinsic_read_first_invocation
: {
4367 LLVMValueRef args
[2];
4370 args
[0] = get_src(ctx
, instr
->src
[0]);
4373 const char *intr_name
;
4374 if (instr
->intrinsic
== nir_intrinsic_read_invocation
) {
4376 intr_name
= "llvm.amdgcn.readlane";
4379 args
[1] = get_src(ctx
, instr
->src
[1]);
4382 intr_name
= "llvm.amdgcn.readfirstlane";
4385 /* We currently have no other way to prevent LLVM from lifting the icmp
4386 * calls to a dominating basic block.
4388 ac_build_optimization_barrier(&ctx
->ac
, &args
[0]);
4390 result
= ac_build_intrinsic(&ctx
->ac
, intr_name
,
4391 ctx
->ac
.i32
, args
, num_args
,
4392 AC_FUNC_ATTR_READNONE
|
4393 AC_FUNC_ATTR_CONVERGENT
);
4396 case nir_intrinsic_load_subgroup_invocation
:
4397 result
= ac_get_thread_id(&ctx
->ac
);
4399 case nir_intrinsic_load_work_group_id
: {
4400 LLVMValueRef values
[3];
4402 for (int i
= 0; i
< 3; i
++) {
4403 values
[i
] = ctx
->abi
->workgroup_ids
[i
] ?
4404 ctx
->abi
->workgroup_ids
[i
] : ctx
->ac
.i32_0
;
4407 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
4410 case nir_intrinsic_load_base_vertex
: {
4411 result
= ctx
->abi
->load_base_vertex(ctx
->abi
);
4414 case nir_intrinsic_load_local_group_size
:
4415 result
= ctx
->abi
->load_local_group_size(ctx
->abi
);
4417 case nir_intrinsic_load_vertex_id
:
4418 result
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
->vertex_id
,
4419 ctx
->abi
->base_vertex
, "");
4421 case nir_intrinsic_load_vertex_id_zero_base
: {
4422 result
= ctx
->abi
->vertex_id
;
4425 case nir_intrinsic_load_local_invocation_id
: {
4426 result
= ctx
->abi
->local_invocation_ids
;
4429 case nir_intrinsic_load_base_instance
:
4430 result
= ctx
->abi
->start_instance
;
4432 case nir_intrinsic_load_draw_id
:
4433 result
= ctx
->abi
->draw_id
;
4435 case nir_intrinsic_load_view_index
:
4436 result
= ctx
->abi
->view_index
;
4438 case nir_intrinsic_load_invocation_id
:
4439 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4440 result
= unpack_param(&ctx
->ac
, ctx
->abi
->tcs_rel_ids
, 8, 5);
4442 result
= ctx
->abi
->gs_invocation_id
;
4444 case nir_intrinsic_load_primitive_id
:
4445 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4446 result
= ctx
->abi
->gs_prim_id
;
4447 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4448 result
= ctx
->abi
->tcs_patch_id
;
4449 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4450 result
= ctx
->abi
->tes_patch_id
;
4452 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4454 case nir_intrinsic_load_sample_id
:
4455 result
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4457 case nir_intrinsic_load_sample_pos
:
4458 result
= load_sample_pos(ctx
);
4460 case nir_intrinsic_load_sample_mask_in
:
4461 result
= ctx
->abi
->load_sample_mask_in(ctx
->abi
);
4463 case nir_intrinsic_load_frag_coord
: {
4464 LLVMValueRef values
[4] = {
4465 ctx
->abi
->frag_pos
[0],
4466 ctx
->abi
->frag_pos
[1],
4467 ctx
->abi
->frag_pos
[2],
4468 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4470 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4473 case nir_intrinsic_load_front_face
:
4474 result
= ctx
->abi
->front_face
;
4476 case nir_intrinsic_load_helper_invocation
:
4477 result
= visit_load_helper_invocation(ctx
);
4479 case nir_intrinsic_load_instance_id
:
4480 result
= ctx
->abi
->instance_id
;
4482 case nir_intrinsic_load_num_work_groups
:
4483 result
= ctx
->abi
->num_work_groups
;
4485 case nir_intrinsic_load_local_invocation_index
:
4486 result
= visit_load_local_invocation_index(ctx
);
4488 case nir_intrinsic_load_subgroup_id
:
4489 result
= visit_load_subgroup_id(ctx
);
4491 case nir_intrinsic_load_num_subgroups
:
4492 result
= visit_load_num_subgroups(ctx
);
4494 case nir_intrinsic_first_invocation
:
4495 result
= visit_first_invocation(ctx
);
4497 case nir_intrinsic_load_push_constant
:
4498 result
= visit_load_push_constant(ctx
, instr
);
4500 case nir_intrinsic_vulkan_resource_index
: {
4501 LLVMValueRef index
= get_src(ctx
, instr
->src
[0]);
4502 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4503 unsigned binding
= nir_intrinsic_binding(instr
);
4505 result
= ctx
->abi
->load_resource(ctx
->abi
, index
, desc_set
,
4509 case nir_intrinsic_vulkan_resource_reindex
:
4510 result
= visit_vulkan_resource_reindex(ctx
, instr
);
4512 case nir_intrinsic_store_ssbo
:
4513 visit_store_ssbo(ctx
, instr
);
4515 case nir_intrinsic_load_ssbo
:
4516 result
= visit_load_buffer(ctx
, instr
);
4518 case nir_intrinsic_ssbo_atomic_add
:
4519 case nir_intrinsic_ssbo_atomic_imin
:
4520 case nir_intrinsic_ssbo_atomic_umin
:
4521 case nir_intrinsic_ssbo_atomic_imax
:
4522 case nir_intrinsic_ssbo_atomic_umax
:
4523 case nir_intrinsic_ssbo_atomic_and
:
4524 case nir_intrinsic_ssbo_atomic_or
:
4525 case nir_intrinsic_ssbo_atomic_xor
:
4526 case nir_intrinsic_ssbo_atomic_exchange
:
4527 case nir_intrinsic_ssbo_atomic_comp_swap
:
4528 result
= visit_atomic_ssbo(ctx
, instr
);
4530 case nir_intrinsic_load_ubo
:
4531 result
= visit_load_ubo_buffer(ctx
, instr
);
4533 case nir_intrinsic_get_buffer_size
:
4534 result
= visit_get_buffer_size(ctx
, instr
);
4536 case nir_intrinsic_load_var
:
4537 result
= visit_load_var(ctx
, instr
);
4539 case nir_intrinsic_store_var
:
4540 visit_store_var(ctx
, instr
);
4542 case nir_intrinsic_load_shared
:
4543 result
= visit_load_shared(ctx
, instr
);
4545 case nir_intrinsic_store_shared
:
4546 visit_store_shared(ctx
, instr
);
4548 case nir_intrinsic_image_samples
:
4549 result
= visit_image_samples(ctx
, instr
);
4551 case nir_intrinsic_image_load
:
4552 result
= visit_image_load(ctx
, instr
);
4554 case nir_intrinsic_image_store
:
4555 visit_image_store(ctx
, instr
);
4557 case nir_intrinsic_image_atomic_add
:
4558 case nir_intrinsic_image_atomic_min
:
4559 case nir_intrinsic_image_atomic_max
:
4560 case nir_intrinsic_image_atomic_and
:
4561 case nir_intrinsic_image_atomic_or
:
4562 case nir_intrinsic_image_atomic_xor
:
4563 case nir_intrinsic_image_atomic_exchange
:
4564 case nir_intrinsic_image_atomic_comp_swap
:
4565 result
= visit_image_atomic(ctx
, instr
);
4567 case nir_intrinsic_image_size
:
4568 result
= visit_image_size(ctx
, instr
);
4570 case nir_intrinsic_shader_clock
:
4571 result
= ac_build_shader_clock(&ctx
->ac
);
4573 case nir_intrinsic_discard
:
4574 case nir_intrinsic_discard_if
:
4575 emit_discard(ctx
, instr
);
4577 case nir_intrinsic_memory_barrier
:
4578 case nir_intrinsic_group_memory_barrier
:
4579 case nir_intrinsic_memory_barrier_atomic_counter
:
4580 case nir_intrinsic_memory_barrier_buffer
:
4581 case nir_intrinsic_memory_barrier_image
:
4582 case nir_intrinsic_memory_barrier_shared
:
4583 emit_membar(&ctx
->ac
, instr
);
4585 case nir_intrinsic_barrier
:
4586 emit_barrier(&ctx
->ac
, ctx
->stage
);
4588 case nir_intrinsic_shared_atomic_add
:
4589 case nir_intrinsic_shared_atomic_imin
:
4590 case nir_intrinsic_shared_atomic_umin
:
4591 case nir_intrinsic_shared_atomic_imax
:
4592 case nir_intrinsic_shared_atomic_umax
:
4593 case nir_intrinsic_shared_atomic_and
:
4594 case nir_intrinsic_shared_atomic_or
:
4595 case nir_intrinsic_shared_atomic_xor
:
4596 case nir_intrinsic_shared_atomic_exchange
:
4597 case nir_intrinsic_shared_atomic_comp_swap
: {
4598 LLVMValueRef ptr
= get_memory_ptr(ctx
, instr
->src
[0]);
4599 result
= visit_var_atomic(ctx
, instr
, ptr
, 1);
4602 case nir_intrinsic_var_atomic_add
:
4603 case nir_intrinsic_var_atomic_imin
:
4604 case nir_intrinsic_var_atomic_umin
:
4605 case nir_intrinsic_var_atomic_imax
:
4606 case nir_intrinsic_var_atomic_umax
:
4607 case nir_intrinsic_var_atomic_and
:
4608 case nir_intrinsic_var_atomic_or
:
4609 case nir_intrinsic_var_atomic_xor
:
4610 case nir_intrinsic_var_atomic_exchange
:
4611 case nir_intrinsic_var_atomic_comp_swap
: {
4612 LLVMValueRef ptr
= build_gep_for_deref(ctx
, instr
->variables
[0]);
4613 result
= visit_var_atomic(ctx
, instr
, ptr
, 0);
4616 case nir_intrinsic_interp_var_at_centroid
:
4617 case nir_intrinsic_interp_var_at_sample
:
4618 case nir_intrinsic_interp_var_at_offset
:
4619 result
= visit_interp(ctx
, instr
);
4621 case nir_intrinsic_emit_vertex
:
4622 ctx
->abi
->emit_vertex(ctx
->abi
, nir_intrinsic_stream_id(instr
), ctx
->abi
->outputs
);
4624 case nir_intrinsic_end_primitive
:
4625 ctx
->abi
->emit_primitive(ctx
->abi
, nir_intrinsic_stream_id(instr
));
4627 case nir_intrinsic_load_tess_coord
:
4628 result
= ctx
->abi
->load_tess_coord(ctx
->abi
);
4630 case nir_intrinsic_load_tess_level_outer
:
4631 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_OUTER
);
4633 case nir_intrinsic_load_tess_level_inner
:
4634 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_INNER
);
4636 case nir_intrinsic_load_patch_vertices_in
:
4637 result
= ctx
->abi
->load_patch_vertices_in(ctx
->abi
);
4639 case nir_intrinsic_vote_all
: {
4640 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4641 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4644 case nir_intrinsic_vote_any
: {
4645 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4646 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4650 fprintf(stderr
, "Unknown intrinsic: ");
4651 nir_print_instr(&instr
->instr
, stderr
);
4652 fprintf(stderr
, "\n");
4656 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4660 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
4662 return abi
->base_vertex
;
4665 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4666 LLVMValueRef buffer_ptr
, bool write
)
4668 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4669 LLVMValueRef result
;
4671 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4673 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
4674 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4679 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
4681 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4682 LLVMValueRef result
;
4684 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4686 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
4687 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4692 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4693 unsigned descriptor_set
,
4694 unsigned base_index
,
4695 unsigned constant_index
,
4697 enum ac_descriptor_type desc_type
,
4698 bool image
, bool write
)
4700 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4701 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4702 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4703 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4704 unsigned offset
= binding
->offset
;
4705 unsigned stride
= binding
->size
;
4707 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4710 assert(base_index
< layout
->binding_count
);
4712 switch (desc_type
) {
4714 type
= ctx
->ac
.v8i32
;
4718 type
= ctx
->ac
.v8i32
;
4722 case AC_DESC_SAMPLER
:
4723 type
= ctx
->ac
.v4i32
;
4724 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4729 case AC_DESC_BUFFER
:
4730 type
= ctx
->ac
.v4i32
;
4734 unreachable("invalid desc_type\n");
4737 offset
+= constant_index
* stride
;
4739 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4740 (!index
|| binding
->immutable_samplers_equal
)) {
4741 if (binding
->immutable_samplers_equal
)
4744 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4746 LLVMValueRef constants
[] = {
4747 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
4748 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
4749 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
4750 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
4752 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4755 assert(stride
% type_size
== 0);
4758 index
= ctx
->ac
.i32_0
;
4760 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
4762 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
4763 list
= LLVMBuildPointerCast(builder
, list
, ac_array_in_const_addr_space(type
), "");
4765 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4768 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4769 const nir_deref_var
*deref
,
4770 enum ac_descriptor_type desc_type
,
4771 const nir_tex_instr
*tex_instr
,
4772 bool image
, bool write
)
4774 LLVMValueRef index
= NULL
;
4775 unsigned constant_index
= 0;
4776 unsigned descriptor_set
;
4777 unsigned base_index
;
4780 assert(tex_instr
&& !image
);
4782 base_index
= tex_instr
->sampler_index
;
4784 const nir_deref
*tail
= &deref
->deref
;
4785 while (tail
->child
) {
4786 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4787 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4792 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4794 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4795 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4797 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4798 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4803 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4806 constant_index
+= child
->base_offset
* array_size
;
4808 tail
= &child
->deref
;
4810 descriptor_set
= deref
->var
->data
.descriptor_set
;
4811 base_index
= deref
->var
->data
.binding
;
4814 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4817 constant_index
, index
,
4818 desc_type
, image
, write
);
4821 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4822 struct ac_image_args
*args
,
4823 const nir_tex_instr
*instr
,
4825 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4826 LLVMValueRef
*param
, unsigned count
,
4829 unsigned is_rect
= 0;
4830 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4832 if (op
== nir_texop_lod
)
4834 /* Pad to power of two vector */
4835 while (count
< util_next_power_of_two(count
))
4836 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4839 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4841 args
->addr
= param
[0];
4843 args
->resource
= res_ptr
;
4844 args
->sampler
= samp_ptr
;
4846 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4847 args
->addr
= param
[0];
4851 args
->dmask
= dmask
;
4852 args
->unorm
= is_rect
;
4856 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4859 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4860 * filtering manually. The driver sets img7 to a mask clearing
4861 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4862 * s_and_b32 samp0, samp0, img7
4865 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4867 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4868 LLVMValueRef res
, LLVMValueRef samp
)
4870 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4871 LLVMValueRef img7
, samp0
;
4873 if (ctx
->ac
.chip_class
>= VI
)
4876 img7
= LLVMBuildExtractElement(builder
, res
,
4877 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4878 samp0
= LLVMBuildExtractElement(builder
, samp
,
4879 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4880 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4881 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4882 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4885 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4886 nir_tex_instr
*instr
,
4887 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4888 LLVMValueRef
*fmask_ptr
)
4890 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4891 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, instr
, false, false);
4893 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, instr
, false, false);
4896 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, instr
, false, false);
4898 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, instr
, false, false);
4899 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4900 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4902 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4903 instr
->op
== nir_texop_samples_identical
))
4904 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, instr
, false, false);
4907 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4910 coord
= ac_to_float(ctx
, coord
);
4911 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4912 coord
= ac_to_integer(ctx
, coord
);
4916 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4918 LLVMValueRef result
= NULL
;
4919 struct ac_image_args args
= { 0 };
4920 unsigned dmask
= 0xf;
4921 LLVMValueRef address
[16];
4922 LLVMValueRef coords
[5];
4923 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4924 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4925 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4926 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4927 LLVMValueRef derivs
[6];
4928 unsigned chan
, count
= 0;
4929 unsigned const_src
= 0, num_deriv_comp
= 0;
4930 bool lod_is_zero
= false;
4932 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4934 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4935 switch (instr
->src
[i
].src_type
) {
4936 case nir_tex_src_coord
:
4937 coord
= get_src(ctx
, instr
->src
[i
].src
);
4939 case nir_tex_src_projector
:
4941 case nir_tex_src_comparator
:
4942 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4944 case nir_tex_src_offset
:
4945 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4948 case nir_tex_src_bias
:
4949 bias
= get_src(ctx
, instr
->src
[i
].src
);
4951 case nir_tex_src_lod
: {
4952 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4954 if (val
&& val
->i32
[0] == 0)
4956 lod
= get_src(ctx
, instr
->src
[i
].src
);
4959 case nir_tex_src_ms_index
:
4960 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4962 case nir_tex_src_ms_mcs
:
4964 case nir_tex_src_ddx
:
4965 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4966 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4968 case nir_tex_src_ddy
:
4969 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4971 case nir_tex_src_texture_offset
:
4972 case nir_tex_src_sampler_offset
:
4973 case nir_tex_src_plane
:
4979 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4980 result
= get_buffer_size(ctx
, res_ptr
, true);
4984 if (instr
->op
== nir_texop_texture_samples
) {
4985 LLVMValueRef res
, samples
, is_msaa
;
4986 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4987 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4988 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4989 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4990 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4991 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4992 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4993 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4994 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4996 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4997 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4998 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4999 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
5000 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
5002 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
5009 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
5010 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, coord
, chan
);
5012 if (offsets
&& instr
->op
!= nir_texop_txf
) {
5013 LLVMValueRef offset
[3], pack
;
5014 for (chan
= 0; chan
< 3; ++chan
)
5015 offset
[chan
] = ctx
->ac
.i32_0
;
5018 for (chan
= 0; chan
< ac_get_llvm_num_components(offsets
); chan
++) {
5019 offset
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
5020 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
5021 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
5023 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
5024 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
5026 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
5027 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
5028 address
[count
++] = pack
;
5031 /* pack LOD bias value */
5032 if (instr
->op
== nir_texop_txb
&& bias
) {
5033 address
[count
++] = bias
;
5036 /* Pack depth comparison value */
5037 if (instr
->is_shadow
&& comparator
) {
5038 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
5039 ac_llvm_extract_elem(&ctx
->ac
, comparator
, 0));
5041 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
5042 * so the depth comparison value isn't clamped for Z16 and
5043 * Z24 anymore. Do it manually here.
5045 * It's unnecessary if the original texture format was
5046 * Z32_FLOAT, but we don't know that here.
5048 if (ctx
->ac
.chip_class
== VI
&& ctx
->abi
->clamp_shadow_reference
)
5049 z
= ac_build_clamp(&ctx
->ac
, z
);
5051 address
[count
++] = z
;
5054 /* pack derivatives */
5056 int num_src_deriv_channels
, num_dest_deriv_channels
;
5057 switch (instr
->sampler_dim
) {
5058 case GLSL_SAMPLER_DIM_3D
:
5059 case GLSL_SAMPLER_DIM_CUBE
:
5061 num_src_deriv_channels
= 3;
5062 num_dest_deriv_channels
= 3;
5064 case GLSL_SAMPLER_DIM_2D
:
5066 num_src_deriv_channels
= 2;
5067 num_dest_deriv_channels
= 2;
5070 case GLSL_SAMPLER_DIM_1D
:
5071 num_src_deriv_channels
= 1;
5072 if (ctx
->ac
.chip_class
>= GFX9
) {
5073 num_dest_deriv_channels
= 2;
5076 num_dest_deriv_channels
= 1;
5082 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
5083 derivs
[i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddx
, i
));
5084 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddy
, i
));
5086 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
5087 derivs
[i
] = ctx
->ac
.f32_0
;
5088 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
5092 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
5093 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
5094 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
5095 if (instr
->coord_components
== 3)
5096 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5097 ac_prepare_cube_coords(&ctx
->ac
,
5098 instr
->op
== nir_texop_txd
, instr
->is_array
,
5099 instr
->op
== nir_texop_lod
, coords
, derivs
);
5105 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
5106 address
[count
++] = derivs
[i
];
5109 /* Pack texture coordinates */
5111 address
[count
++] = coords
[0];
5112 if (instr
->coord_components
> 1) {
5113 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
5114 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
5116 address
[count
++] = coords
[1];
5118 if (instr
->coord_components
> 2) {
5119 if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
5120 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
5121 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
5122 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
5124 instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
5125 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
5127 address
[count
++] = coords
[2];
5130 if (ctx
->ac
.chip_class
>= GFX9
) {
5131 LLVMValueRef filler
;
5132 if (instr
->op
== nir_texop_txf
)
5133 filler
= ctx
->ac
.i32_0
;
5135 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
5137 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
5138 /* No nir_texop_lod, because it does not take a slice
5139 * even with array textures. */
5140 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
5141 address
[count
] = address
[count
- 1];
5142 address
[count
- 1] = filler
;
5145 address
[count
++] = filler
;
5151 if (lod
&& ((instr
->op
== nir_texop_txl
|| instr
->op
== nir_texop_txf
) && !lod_is_zero
)) {
5152 address
[count
++] = lod
;
5153 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
5154 address
[count
++] = sample_index
;
5155 } else if(instr
->op
== nir_texop_txs
) {
5158 address
[count
++] = lod
;
5160 address
[count
++] = ctx
->ac
.i32_0
;
5163 for (chan
= 0; chan
< count
; chan
++) {
5164 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
5165 address
[chan
], ctx
->ac
.i32
, "");
5168 if (instr
->op
== nir_texop_samples_identical
) {
5169 LLVMValueRef txf_address
[4];
5170 struct ac_image_args txf_args
= { 0 };
5171 unsigned txf_count
= count
;
5172 memcpy(txf_address
, address
, sizeof(txf_address
));
5174 if (!instr
->is_array
)
5175 txf_address
[2] = ctx
->ac
.i32_0
;
5176 txf_address
[3] = ctx
->ac
.i32_0
;
5178 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
5180 txf_address
, txf_count
, 0xf);
5182 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
5184 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5185 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
5189 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
5190 instr
->op
!= nir_texop_txs
) {
5191 unsigned sample_chan
= instr
->is_array
? 3 : 2;
5192 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
5195 instr
->is_array
? address
[2] : NULL
,
5196 address
[sample_chan
],
5200 if (offsets
&& instr
->op
== nir_texop_txf
) {
5201 nir_const_value
*const_offset
=
5202 nir_src_as_const_value(instr
->src
[const_src
].src
);
5203 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
5204 assert(const_offset
);
5205 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
5206 if (num_offsets
> 2)
5207 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
5208 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
5209 if (num_offsets
> 1)
5210 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
5211 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
5212 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
5213 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
5217 /* TODO TG4 support */
5218 if (instr
->op
== nir_texop_tg4
) {
5219 if (instr
->is_shadow
)
5222 dmask
= 1 << instr
->component
;
5224 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
5225 res_ptr
, samp_ptr
, address
, count
, dmask
);
5227 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
5229 if (instr
->op
== nir_texop_query_levels
)
5230 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
5231 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
5232 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
5233 instr
->op
!= nir_texop_tg4
)
5234 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5235 else if (instr
->op
== nir_texop_txs
&&
5236 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
5238 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5239 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
5240 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5241 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
5242 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
5243 } else if (ctx
->ac
.chip_class
>= GFX9
&&
5244 instr
->op
== nir_texop_txs
&&
5245 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
5247 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5248 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5249 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
5251 } else if (instr
->dest
.ssa
.num_components
!= 4)
5252 result
= trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
5256 assert(instr
->dest
.is_ssa
);
5257 result
= ac_to_integer(&ctx
->ac
, result
);
5258 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5263 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
5265 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
5266 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
5268 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5269 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
5272 static void visit_post_phi(struct ac_nir_context
*ctx
,
5273 nir_phi_instr
*instr
,
5274 LLVMValueRef llvm_phi
)
5276 nir_foreach_phi_src(src
, instr
) {
5277 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
5278 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
5280 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
5284 static void phi_post_pass(struct ac_nir_context
*ctx
)
5286 struct hash_entry
*entry
;
5287 hash_table_foreach(ctx
->phis
, entry
) {
5288 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
5289 (LLVMValueRef
)entry
->data
);
5294 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
5295 const nir_ssa_undef_instr
*instr
)
5297 unsigned num_components
= instr
->def
.num_components
;
5298 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
5301 if (num_components
== 1)
5302 undef
= LLVMGetUndef(type
);
5304 undef
= LLVMGetUndef(LLVMVectorType(type
, num_components
));
5306 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
5309 static void visit_jump(struct ac_llvm_context
*ctx
,
5310 const nir_jump_instr
*instr
)
5312 switch (instr
->type
) {
5313 case nir_jump_break
:
5314 ac_build_break(ctx
);
5316 case nir_jump_continue
:
5317 ac_build_continue(ctx
);
5320 fprintf(stderr
, "Unknown NIR jump instr: ");
5321 nir_print_instr(&instr
->instr
, stderr
);
5322 fprintf(stderr
, "\n");
5327 static void visit_cf_list(struct ac_nir_context
*ctx
,
5328 struct exec_list
*list
);
5330 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
5332 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
5333 nir_foreach_instr(instr
, block
)
5335 switch (instr
->type
) {
5336 case nir_instr_type_alu
:
5337 visit_alu(ctx
, nir_instr_as_alu(instr
));
5339 case nir_instr_type_load_const
:
5340 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
5342 case nir_instr_type_intrinsic
:
5343 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
5345 case nir_instr_type_tex
:
5346 visit_tex(ctx
, nir_instr_as_tex(instr
));
5348 case nir_instr_type_phi
:
5349 visit_phi(ctx
, nir_instr_as_phi(instr
));
5351 case nir_instr_type_ssa_undef
:
5352 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
5354 case nir_instr_type_jump
:
5355 visit_jump(&ctx
->ac
, nir_instr_as_jump(instr
));
5358 fprintf(stderr
, "Unknown NIR instr type: ");
5359 nir_print_instr(instr
, stderr
);
5360 fprintf(stderr
, "\n");
5365 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
5368 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
5370 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
5372 nir_block
*then_block
=
5373 (nir_block
*) exec_list_get_head(&if_stmt
->then_list
);
5375 ac_build_uif(&ctx
->ac
, value
, then_block
->index
);
5377 visit_cf_list(ctx
, &if_stmt
->then_list
);
5379 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
5380 nir_block
*else_block
=
5381 (nir_block
*) exec_list_get_head(&if_stmt
->else_list
);
5383 ac_build_else(&ctx
->ac
, else_block
->index
);
5384 visit_cf_list(ctx
, &if_stmt
->else_list
);
5387 ac_build_endif(&ctx
->ac
, then_block
->index
);
5390 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
5392 nir_block
*first_loop_block
=
5393 (nir_block
*) exec_list_get_head(&loop
->body
);
5395 ac_build_bgnloop(&ctx
->ac
, first_loop_block
->index
);
5397 visit_cf_list(ctx
, &loop
->body
);
5399 ac_build_endloop(&ctx
->ac
, first_loop_block
->index
);
5402 static void visit_cf_list(struct ac_nir_context
*ctx
,
5403 struct exec_list
*list
)
5405 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5407 switch (node
->type
) {
5408 case nir_cf_node_block
:
5409 visit_block(ctx
, nir_cf_node_as_block(node
));
5412 case nir_cf_node_if
:
5413 visit_if(ctx
, nir_cf_node_as_if(node
));
5416 case nir_cf_node_loop
:
5417 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5427 handle_vs_input_decl(struct radv_shader_context
*ctx
,
5428 struct nir_variable
*variable
)
5430 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5431 LLVMValueRef t_offset
;
5432 LLVMValueRef t_list
;
5434 LLVMValueRef buffer_index
;
5435 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5436 int idx
= variable
->data
.location
;
5437 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5438 uint8_t input_usage_mask
=
5439 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
5440 unsigned num_channels
= util_last_bit(input_usage_mask
);
5442 variable
->data
.driver_location
= idx
* 4;
5444 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5445 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << (index
+ i
))) {
5446 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.instance_id
,
5447 ctx
->abi
.start_instance
, "");
5448 if (ctx
->options
->key
.vs
.as_ls
) {
5449 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5450 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5452 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5453 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5456 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
5457 ctx
->abi
.base_vertex
, "");
5458 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
5460 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5462 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5465 num_channels
, false, true);
5467 input
= ac_build_expand_to_vec4(&ctx
->ac
, input
, num_channels
);
5469 for (unsigned chan
= 0; chan
< 4; chan
++) {
5470 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5471 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5472 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
,
5473 input
, llvm_chan
, ""));
5478 static void interp_fs_input(struct radv_shader_context
*ctx
,
5480 LLVMValueRef interp_param
,
5481 LLVMValueRef prim_mask
,
5482 LLVMValueRef result
[4])
5484 LLVMValueRef attr_number
;
5487 bool interp
= interp_param
!= NULL
;
5489 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
5491 /* fs.constant returns the param from the middle vertex, so it's not
5492 * really useful for flat shading. It's meant to be used for custom
5493 * interpolation (but the intrinsic can't fetch from the other two
5496 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5497 * to do the right thing. The only reason we use fs.constant is that
5498 * fs.interp cannot be used on integers, because they can be equal
5502 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
5505 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
5507 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
5511 for (chan
= 0; chan
< 4; chan
++) {
5512 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5515 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5520 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5521 LLVMConstInt(ctx
->ac
.i32
, 2, false),
5530 handle_fs_input_decl(struct radv_shader_context
*ctx
,
5531 struct nir_variable
*variable
)
5533 int idx
= variable
->data
.location
;
5534 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5535 LLVMValueRef interp
;
5537 variable
->data
.driver_location
= idx
* 4;
5538 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5540 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5541 unsigned interp_type
;
5542 if (variable
->data
.sample
)
5543 interp_type
= INTERP_SAMPLE
;
5544 else if (variable
->data
.centroid
)
5545 interp_type
= INTERP_CENTROID
;
5547 interp_type
= INTERP_CENTER
;
5549 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
5553 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5554 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5559 handle_vs_inputs(struct radv_shader_context
*ctx
,
5560 struct nir_shader
*nir
) {
5561 nir_foreach_variable(variable
, &nir
->inputs
)
5562 handle_vs_input_decl(ctx
, variable
);
5566 prepare_interp_optimize(struct radv_shader_context
*ctx
,
5567 struct nir_shader
*nir
)
5569 if (!ctx
->options
->key
.fs
.multisample
)
5572 bool uses_center
= false;
5573 bool uses_centroid
= false;
5574 nir_foreach_variable(variable
, &nir
->inputs
) {
5575 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5576 variable
->data
.sample
)
5579 if (variable
->data
.centroid
)
5580 uses_centroid
= true;
5585 if (uses_center
&& uses_centroid
) {
5586 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
5587 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5588 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5593 handle_fs_inputs(struct radv_shader_context
*ctx
,
5594 struct nir_shader
*nir
)
5596 prepare_interp_optimize(ctx
, nir
);
5598 nir_foreach_variable(variable
, &nir
->inputs
)
5599 handle_fs_input_decl(ctx
, variable
);
5603 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5604 ctx
->shader_info
->info
.needs_multiview_view_index
)
5605 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5607 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5608 LLVMValueRef interp_param
;
5609 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5611 if (!(ctx
->input_mask
& (1ull << i
)))
5614 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5615 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5616 interp_param
= *inputs
;
5617 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
,
5621 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5623 } else if (i
== VARYING_SLOT_POS
) {
5624 for(int i
= 0; i
< 3; ++i
)
5625 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5627 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
5628 ctx
->abi
.frag_pos
[3]);
5631 ctx
->shader_info
->fs
.num_interp
= index
;
5632 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5634 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5635 ctx
->abi
.view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5639 ac_build_alloca(struct ac_llvm_context
*ac
,
5643 LLVMBuilderRef builder
= ac
->builder
;
5644 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
5645 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5646 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
5647 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
5648 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
5652 LLVMPositionBuilderBefore(first_builder
, first_instr
);
5654 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
5657 res
= LLVMBuildAlloca(first_builder
, type
, name
);
5658 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
5660 LLVMDisposeBuilder(first_builder
);
5665 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5669 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5670 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5675 scan_shader_output_decl(struct radv_shader_context
*ctx
,
5676 struct nir_variable
*variable
,
5677 struct nir_shader
*shader
,
5678 gl_shader_stage stage
)
5680 int idx
= variable
->data
.location
+ variable
->data
.index
;
5681 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5682 uint64_t mask_attribs
;
5684 variable
->data
.driver_location
= idx
* 4;
5686 /* tess ctrl has it's own load/store paths for outputs */
5687 if (stage
== MESA_SHADER_TESS_CTRL
)
5690 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5691 if (stage
== MESA_SHADER_VERTEX
||
5692 stage
== MESA_SHADER_TESS_EVAL
||
5693 stage
== MESA_SHADER_GEOMETRY
) {
5694 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5695 int length
= shader
->info
.clip_distance_array_size
+
5696 shader
->info
.cull_distance_array_size
;
5697 if (stage
== MESA_SHADER_VERTEX
) {
5698 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5699 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5701 if (stage
== MESA_SHADER_TESS_EVAL
) {
5702 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5703 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5710 mask_attribs
= 1ull << idx
;
5714 ctx
->output_mask
|= mask_attribs
;
5718 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5719 struct nir_shader
*nir
,
5720 struct nir_variable
*variable
)
5722 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5723 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5725 /* tess ctrl has it's own load/store paths for outputs */
5726 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5729 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5730 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5731 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5732 int idx
= variable
->data
.location
+ variable
->data
.index
;
5733 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5734 int length
= nir
->info
.clip_distance_array_size
+
5735 nir
->info
.cull_distance_array_size
;
5744 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5745 for (unsigned chan
= 0; chan
< 4; chan
++) {
5746 ctx
->abi
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5747 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5753 glsl_base_to_llvm_type(struct ac_llvm_context
*ac
,
5754 enum glsl_base_type type
)
5758 case GLSL_TYPE_UINT
:
5759 case GLSL_TYPE_BOOL
:
5760 case GLSL_TYPE_SUBROUTINE
:
5762 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5764 case GLSL_TYPE_INT64
:
5765 case GLSL_TYPE_UINT64
:
5767 case GLSL_TYPE_DOUBLE
:
5770 unreachable("unknown GLSL type");
5775 glsl_to_llvm_type(struct ac_llvm_context
*ac
,
5776 const struct glsl_type
*type
)
5778 if (glsl_type_is_scalar(type
)) {
5779 return glsl_base_to_llvm_type(ac
, glsl_get_base_type(type
));
5782 if (glsl_type_is_vector(type
)) {
5783 return LLVMVectorType(
5784 glsl_base_to_llvm_type(ac
, glsl_get_base_type(type
)),
5785 glsl_get_vector_elements(type
));
5788 if (glsl_type_is_matrix(type
)) {
5789 return LLVMArrayType(
5790 glsl_to_llvm_type(ac
, glsl_get_column_type(type
)),
5791 glsl_get_matrix_columns(type
));
5794 if (glsl_type_is_array(type
)) {
5795 return LLVMArrayType(
5796 glsl_to_llvm_type(ac
, glsl_get_array_element(type
)),
5797 glsl_get_length(type
));
5800 assert(glsl_type_is_struct(type
));
5802 LLVMTypeRef member_types
[glsl_get_length(type
)];
5804 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5806 glsl_to_llvm_type(ac
,
5807 glsl_get_struct_field(type
, i
));
5810 return LLVMStructTypeInContext(ac
->context
, member_types
,
5811 glsl_get_length(type
), false);
5815 setup_locals(struct ac_nir_context
*ctx
,
5816 struct nir_function
*func
)
5819 ctx
->num_locals
= 0;
5820 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5821 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5822 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5823 variable
->data
.location_frac
= 0;
5824 ctx
->num_locals
+= attrib_count
;
5826 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5830 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5831 for (j
= 0; j
< 4; j
++) {
5832 ctx
->locals
[i
* 4 + j
] =
5833 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5839 setup_shared(struct ac_nir_context
*ctx
,
5840 struct nir_shader
*nir
)
5842 nir_foreach_variable(variable
, &nir
->shared
) {
5843 LLVMValueRef shared
=
5844 LLVMAddGlobalInAddressSpace(
5845 ctx
->ac
.module
, glsl_to_llvm_type(&ctx
->ac
, variable
->type
),
5846 variable
->name
? variable
->name
: "",
5847 AC_LOCAL_ADDR_SPACE
);
5848 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5852 /* Initialize arguments for the shader export intrinsic */
5854 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
5855 LLVMValueRef
*values
,
5856 unsigned enabled_channels
,
5858 struct ac_export_args
*args
)
5860 /* Specify the channels that are enabled. */
5861 args
->enabled_channels
= enabled_channels
;
5863 /* Specify whether the EXEC mask represents the valid mask */
5864 args
->valid_mask
= 0;
5866 /* Specify whether this is the last export */
5869 /* Specify the target we are exporting */
5870 args
->target
= target
;
5872 args
->compr
= false;
5873 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
5874 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
5875 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
5876 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5878 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5879 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5880 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5881 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5882 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5885 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
5886 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
5887 unsigned bits
, bool hi
) = NULL
;
5889 switch(col_format
) {
5890 case V_028714_SPI_SHADER_ZERO
:
5891 args
->enabled_channels
= 0; /* writemask */
5892 args
->target
= V_008DFC_SQ_EXP_NULL
;
5895 case V_028714_SPI_SHADER_32_R
:
5896 args
->enabled_channels
= 1;
5897 args
->out
[0] = values
[0];
5900 case V_028714_SPI_SHADER_32_GR
:
5901 args
->enabled_channels
= 0x3;
5902 args
->out
[0] = values
[0];
5903 args
->out
[1] = values
[1];
5906 case V_028714_SPI_SHADER_32_AR
:
5907 args
->enabled_channels
= 0x9;
5908 args
->out
[0] = values
[0];
5909 args
->out
[3] = values
[3];
5912 case V_028714_SPI_SHADER_FP16_ABGR
:
5913 args
->enabled_channels
= 0x5;
5914 packf
= ac_build_cvt_pkrtz_f16
;
5917 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5918 args
->enabled_channels
= 0x5;
5919 packf
= ac_build_cvt_pknorm_u16
;
5922 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5923 args
->enabled_channels
= 0x5;
5924 packf
= ac_build_cvt_pknorm_i16
;
5927 case V_028714_SPI_SHADER_UINT16_ABGR
:
5928 args
->enabled_channels
= 0x5;
5929 packi
= ac_build_cvt_pk_u16
;
5932 case V_028714_SPI_SHADER_SINT16_ABGR
:
5933 args
->enabled_channels
= 0x5;
5934 packi
= ac_build_cvt_pk_i16
;
5938 case V_028714_SPI_SHADER_32_ABGR
:
5939 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5943 /* Pack f16 or norm_i16/u16. */
5945 for (chan
= 0; chan
< 2; chan
++) {
5946 LLVMValueRef pack_args
[2] = {
5948 values
[2 * chan
+ 1]
5950 LLVMValueRef packed
;
5952 packed
= packf(&ctx
->ac
, pack_args
);
5953 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
5955 args
->compr
= 1; /* COMPR flag */
5960 for (chan
= 0; chan
< 2; chan
++) {
5961 LLVMValueRef pack_args
[2] = {
5962 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
5963 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
5965 LLVMValueRef packed
;
5967 packed
= packi(&ctx
->ac
, pack_args
,
5968 is_int8
? 8 : is_int10
? 10 : 16,
5970 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
5972 args
->compr
= 1; /* COMPR flag */
5977 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5979 for (unsigned i
= 0; i
< 4; ++i
) {
5980 if (!(args
->enabled_channels
& (1 << i
)))
5983 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5988 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
5989 LLVMValueRef
*values
, unsigned enabled_channels
)
5991 struct ac_export_args args
;
5993 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
5994 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
5995 ac_build_export(&ctx
->ac
, &args
);
5999 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
6001 LLVMValueRef output
=
6002 ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(index
, chan
)];
6004 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
6008 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
6009 bool export_prim_id
,
6010 struct ac_vs_output_info
*outinfo
)
6012 uint32_t param_count
= 0;
6014 unsigned pos_idx
, num_pos_exports
= 0;
6015 struct ac_export_args args
, pos_args
[4] = {};
6016 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
6019 if (ctx
->options
->key
.has_multiview_view_index
) {
6020 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
6022 for(unsigned i
= 0; i
< 4; ++i
)
6023 ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
6024 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
6027 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
6028 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
6031 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
6032 sizeof(outinfo
->vs_output_param_offset
));
6034 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
6035 LLVMValueRef slots
[8];
6038 if (outinfo
->cull_dist_mask
)
6039 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
6041 i
= VARYING_SLOT_CLIP_DIST0
;
6042 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
6043 slots
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
6045 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
6046 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
6048 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
6049 target
= V_008DFC_SQ_EXP_POS
+ 3;
6050 si_llvm_init_export_args(ctx
, &slots
[4], 0xf, target
, &args
);
6051 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
6052 &args
, sizeof(args
));
6055 target
= V_008DFC_SQ_EXP_POS
+ 2;
6056 si_llvm_init_export_args(ctx
, &slots
[0], 0xf, target
, &args
);
6057 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
6058 &args
, sizeof(args
));
6062 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
6063 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
6064 for (unsigned j
= 0; j
< 4; j
++)
6065 pos_values
[j
] = radv_load_output(ctx
, VARYING_SLOT_POS
, j
);
6067 si_llvm_init_export_args(ctx
, pos_values
, 0xf, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
6069 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
6070 outinfo
->writes_pointsize
= true;
6071 psize_value
= radv_load_output(ctx
, VARYING_SLOT_PSIZ
, 0);
6074 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
6075 outinfo
->writes_layer
= true;
6076 layer_value
= radv_load_output(ctx
, VARYING_SLOT_LAYER
, 0);
6079 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
6080 outinfo
->writes_viewport_index
= true;
6081 viewport_index_value
= radv_load_output(ctx
, VARYING_SLOT_VIEWPORT
, 0);
6084 if (outinfo
->writes_pointsize
||
6085 outinfo
->writes_layer
||
6086 outinfo
->writes_viewport_index
) {
6087 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
6088 (outinfo
->writes_layer
== true ? 4 : 0));
6089 pos_args
[1].valid_mask
= 0;
6090 pos_args
[1].done
= 0;
6091 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
6092 pos_args
[1].compr
= 0;
6093 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
6094 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
6095 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
6096 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
6098 if (outinfo
->writes_pointsize
== true)
6099 pos_args
[1].out
[0] = psize_value
;
6100 if (outinfo
->writes_layer
== true)
6101 pos_args
[1].out
[2] = layer_value
;
6102 if (outinfo
->writes_viewport_index
== true) {
6103 if (ctx
->options
->chip_class
>= GFX9
) {
6104 /* GFX9 has the layer in out.z[10:0] and the viewport
6105 * index in out.z[19:16].
6107 LLVMValueRef v
= viewport_index_value
;
6108 v
= ac_to_integer(&ctx
->ac
, v
);
6109 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
6110 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6112 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
6113 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
6115 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
6116 pos_args
[1].enabled_channels
|= 1 << 2;
6118 pos_args
[1].out
[3] = viewport_index_value
;
6119 pos_args
[1].enabled_channels
|= 1 << 3;
6123 for (i
= 0; i
< 4; i
++) {
6124 if (pos_args
[i
].out
[0])
6129 for (i
= 0; i
< 4; i
++) {
6130 if (!pos_args
[i
].out
[0])
6133 /* Specify the target we are exporting */
6134 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
6135 if (pos_idx
== num_pos_exports
)
6136 pos_args
[i
].done
= 1;
6137 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
6140 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6141 LLVMValueRef values
[4];
6142 if (!(ctx
->output_mask
& (1ull << i
)))
6145 if (i
!= VARYING_SLOT_LAYER
&&
6146 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
6147 i
< VARYING_SLOT_VAR0
)
6150 for (unsigned j
= 0; j
< 4; j
++)
6151 values
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
6153 unsigned output_usage_mask
;
6155 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
6156 !ctx
->is_gs_copy_shader
) {
6158 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
6159 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6161 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
6163 /* Enable all channels for the GS copy shader because
6164 * we don't know the output usage mask currently.
6166 output_usage_mask
= 0xf;
6169 radv_export_param(ctx
, param_count
, values
, output_usage_mask
);
6171 outinfo
->vs_output_param_offset
[i
] = param_count
++;
6174 if (export_prim_id
) {
6175 LLVMValueRef values
[4];
6177 values
[0] = ctx
->vs_prim_id
;
6178 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
6179 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
6180 for (unsigned j
= 1; j
< 4; j
++)
6181 values
[j
] = ctx
->ac
.f32_0
;
6183 radv_export_param(ctx
, param_count
, values
, 0xf);
6185 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
6186 outinfo
->export_prim_id
= true;
6189 outinfo
->pos_exports
= num_pos_exports
;
6190 outinfo
->param_exports
= param_count
;
6194 handle_es_outputs_post(struct radv_shader_context
*ctx
,
6195 struct ac_es_output_info
*outinfo
)
6198 uint64_t max_output_written
= 0;
6199 LLVMValueRef lds_base
= NULL
;
6201 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6205 if (!(ctx
->output_mask
& (1ull << i
)))
6208 if (i
== VARYING_SLOT_CLIP_DIST0
)
6209 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6211 param_index
= shader_io_get_unique_index(i
);
6213 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
6216 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
6218 if (ctx
->ac
.chip_class
>= GFX9
) {
6219 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
6220 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
6221 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6222 LLVMConstInt(ctx
->ac
.i32
, 24, false),
6223 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
6224 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
6225 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
6226 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
6227 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
6228 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
6231 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6232 LLVMValueRef dw_addr
= NULL
;
6233 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
6237 if (!(ctx
->output_mask
& (1ull << i
)))
6240 if (i
== VARYING_SLOT_CLIP_DIST0
)
6241 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6243 param_index
= shader_io_get_unique_index(i
);
6246 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
6247 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
6250 for (j
= 0; j
< length
; j
++) {
6251 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
6252 out_val
= LLVMBuildBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
6254 if (ctx
->ac
.chip_class
>= GFX9
) {
6255 ac_lds_store(&ctx
->ac
, dw_addr
,
6256 LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], ""));
6257 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6259 ac_build_buffer_store_dword(&ctx
->ac
,
6262 NULL
, ctx
->es2gs_offset
,
6263 (4 * param_index
+ j
) * 4,
6271 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
6273 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
6274 LLVMValueRef vertex_dw_stride
= unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
6275 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
6276 vertex_dw_stride
, "");
6278 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6279 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
6282 if (!(ctx
->output_mask
& (1ull << i
)))
6285 if (i
== VARYING_SLOT_CLIP_DIST0
)
6286 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6287 int param
= shader_io_get_unique_index(i
);
6288 mark_tess_output(ctx
, false, param
);
6290 mark_tess_output(ctx
, false, param
+ 1);
6291 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
6292 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
6294 for (unsigned j
= 0; j
< length
; j
++) {
6295 ac_lds_store(&ctx
->ac
, dw_addr
,
6296 LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], ""));
6297 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6302 struct ac_build_if_state
6304 struct radv_shader_context
*ctx
;
6305 LLVMValueRef condition
;
6306 LLVMBasicBlockRef entry_block
;
6307 LLVMBasicBlockRef true_block
;
6308 LLVMBasicBlockRef false_block
;
6309 LLVMBasicBlockRef merge_block
;
6312 static LLVMBasicBlockRef
6313 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
6315 LLVMBasicBlockRef current_block
;
6316 LLVMBasicBlockRef next_block
;
6317 LLVMBasicBlockRef new_block
;
6319 /* get current basic block */
6320 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
6322 /* chqeck if there's another block after this one */
6323 next_block
= LLVMGetNextBasicBlock(current_block
);
6325 /* insert the new block before the next block */
6326 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
6329 /* append new block after current block */
6330 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
6331 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
6337 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
6338 struct radv_shader_context
*ctx
,
6339 LLVMValueRef condition
)
6341 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
6343 memset(ifthen
, 0, sizeof *ifthen
);
6345 ifthen
->condition
= condition
;
6346 ifthen
->entry_block
= block
;
6348 /* create endif/merge basic block for the phi functions */
6349 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
6351 /* create/insert true_block before merge_block */
6352 ifthen
->true_block
=
6353 LLVMInsertBasicBlockInContext(ctx
->context
,
6354 ifthen
->merge_block
,
6357 /* successive code goes into the true block */
6358 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
6362 * End a conditional.
6365 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6367 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
6369 /* Insert branch to the merge block from current block */
6370 LLVMBuildBr(builder
, ifthen
->merge_block
);
6373 * Now patch in the various branch instructions.
6376 /* Insert the conditional branch instruction at the end of entry_block */
6377 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6378 if (ifthen
->false_block
) {
6379 /* we have an else clause */
6380 LLVMBuildCondBr(builder
, ifthen
->condition
,
6381 ifthen
->true_block
, ifthen
->false_block
);
6384 /* no else clause */
6385 LLVMBuildCondBr(builder
, ifthen
->condition
,
6386 ifthen
->true_block
, ifthen
->merge_block
);
6389 /* Resume building code at end of the ifthen->merge_block */
6390 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6394 write_tess_factors(struct radv_shader_context
*ctx
)
6396 unsigned stride
, outer_comps
, inner_comps
;
6397 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6398 LLVMValueRef invocation_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
6399 LLVMValueRef rel_patch_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
6400 unsigned tess_inner_index
= 0, tess_outer_index
;
6401 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
6402 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6404 emit_barrier(&ctx
->ac
, ctx
->stage
);
6406 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6426 ac_nir_build_if(&if_ctx
, ctx
,
6427 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
6428 invocation_id
, ctx
->ac
.i32_0
, ""));
6430 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6433 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6434 mark_tess_output(ctx
, true, tess_inner_index
);
6435 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
6436 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
6439 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6440 mark_tess_output(ctx
, true, tess_outer_index
);
6441 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
6442 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
6444 for (i
= 0; i
< 4; i
++) {
6445 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6446 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6450 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6451 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
6452 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
6454 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
6456 for (i
= 0; i
< outer_comps
; i
++) {
6458 ac_lds_load(&ctx
->ac
, lds_outer
);
6459 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
6462 for (i
= 0; i
< inner_comps
; i
++) {
6463 inner
[i
] = out
[outer_comps
+i
] =
6464 ac_lds_load(&ctx
->ac
, lds_inner
);
6465 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
6470 /* Convert the outputs to vectors for stores. */
6471 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6475 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6478 buffer
= ctx
->hs_ring_tess_factor
;
6479 tf_base
= ctx
->tess_factor_offset
;
6480 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
6481 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
6482 unsigned tf_offset
= 0;
6484 if (ctx
->options
->chip_class
<= VI
) {
6485 ac_nir_build_if(&inner_if_ctx
, ctx
,
6486 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
6487 rel_patch_id
, ctx
->ac
.i32_0
, ""));
6489 /* Store the dynamic HS control word. */
6490 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6491 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
6492 1, ctx
->ac
.i32_0
, tf_base
,
6493 0, 1, 0, true, false);
6496 ac_nir_build_endif(&inner_if_ctx
);
6499 /* Store the tessellation factors. */
6500 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6501 MIN2(stride
, 4), byteoffset
, tf_base
,
6502 tf_offset
, 1, 0, true, false);
6504 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6505 stride
- 4, byteoffset
, tf_base
,
6506 16 + tf_offset
, 1, 0, true, false);
6508 //store to offchip for TES to read - only if TES reads them
6509 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6510 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6511 LLVMValueRef tf_inner_offset
;
6512 unsigned param_outer
, param_inner
;
6514 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6515 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6516 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
6518 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6519 util_next_power_of_two(outer_comps
));
6521 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6522 outer_comps
, tf_outer_offset
,
6523 ctx
->oc_lds
, 0, 1, 0, true, false);
6525 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6526 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6527 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
6529 inner_vec
= inner_comps
== 1 ? inner
[0] :
6530 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6531 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6532 inner_comps
, tf_inner_offset
,
6533 ctx
->oc_lds
, 0, 1, 0, true, false);
6536 ac_nir_build_endif(&if_ctx
);
6540 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
6542 write_tess_factors(ctx
);
6546 si_export_mrt_color(struct radv_shader_context
*ctx
,
6547 LLVMValueRef
*color
, unsigned index
,
6548 struct ac_export_args
*args
)
6551 si_llvm_init_export_args(ctx
, color
, 0xf,
6552 V_008DFC_SQ_EXP_MRT
+ index
, args
);
6553 if (!args
->enabled_channels
)
6554 return false; /* unnecessary NULL export */
6560 radv_export_mrt_z(struct radv_shader_context
*ctx
,
6561 LLVMValueRef depth
, LLVMValueRef stencil
,
6562 LLVMValueRef samplemask
)
6564 struct ac_export_args args
;
6566 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
6568 ac_build_export(&ctx
->ac
, &args
);
6572 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
6575 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6576 struct ac_export_args color_args
[8];
6578 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6579 LLVMValueRef values
[4];
6581 if (!(ctx
->output_mask
& (1ull << i
)))
6584 if (i
< FRAG_RESULT_DATA0
)
6587 for (unsigned j
= 0; j
< 4; j
++)
6588 values
[j
] = ac_to_float(&ctx
->ac
,
6589 radv_load_output(ctx
, i
, j
));
6591 bool ret
= si_export_mrt_color(ctx
, values
,
6592 i
- FRAG_RESULT_DATA0
,
6593 &color_args
[index
]);
6598 /* Process depth, stencil, samplemask. */
6599 if (ctx
->shader_info
->info
.ps
.writes_z
) {
6600 depth
= ac_to_float(&ctx
->ac
,
6601 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
6603 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
6604 stencil
= ac_to_float(&ctx
->ac
,
6605 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
6607 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
6608 samplemask
= ac_to_float(&ctx
->ac
,
6609 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
6612 /* Set the DONE bit on last non-null color export only if Z isn't
6616 !ctx
->shader_info
->info
.ps
.writes_z
&&
6617 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
6618 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
6619 unsigned last
= index
- 1;
6621 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
6622 color_args
[last
].done
= 1; /* DONE bit */
6625 /* Export PS outputs. */
6626 for (unsigned i
= 0; i
< index
; i
++)
6627 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6629 if (depth
|| stencil
|| samplemask
)
6630 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6632 ac_build_export_null(&ctx
->ac
);
6636 emit_gs_epilogue(struct radv_shader_context
*ctx
)
6638 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6642 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6643 LLVMValueRef
*addrs
)
6645 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
6647 switch (ctx
->stage
) {
6648 case MESA_SHADER_VERTEX
:
6649 if (ctx
->options
->key
.vs
.as_ls
)
6650 handle_ls_outputs_post(ctx
);
6651 else if (ctx
->options
->key
.vs
.as_es
)
6652 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6654 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6655 &ctx
->shader_info
->vs
.outinfo
);
6657 case MESA_SHADER_FRAGMENT
:
6658 handle_fs_outputs_post(ctx
);
6660 case MESA_SHADER_GEOMETRY
:
6661 emit_gs_epilogue(ctx
);
6663 case MESA_SHADER_TESS_CTRL
:
6664 handle_tcs_outputs_post(ctx
);
6666 case MESA_SHADER_TESS_EVAL
:
6667 if (ctx
->options
->key
.tes
.as_es
)
6668 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6670 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6671 &ctx
->shader_info
->tes
.outinfo
);
6678 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
)
6680 LLVMPassManagerRef passmgr
;
6681 /* Create the pass manager */
6682 passmgr
= LLVMCreateFunctionPassManagerForModule(
6685 /* This pass should eliminate all the load and store instructions */
6686 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6688 /* Add some optimization passes */
6689 LLVMAddScalarReplAggregatesPass(passmgr
);
6690 LLVMAddLICMPass(passmgr
);
6691 LLVMAddAggressiveDCEPass(passmgr
);
6692 LLVMAddCFGSimplificationPass(passmgr
);
6693 LLVMAddInstructionCombiningPass(passmgr
);
6696 LLVMInitializeFunctionPassManager(passmgr
);
6697 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6698 LLVMFinalizeFunctionPassManager(passmgr
);
6700 LLVMDisposeBuilder(ctx
->ac
.builder
);
6701 LLVMDisposePassManager(passmgr
);
6703 ac_llvm_context_dispose(&ctx
->ac
);
6707 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
6709 struct ac_vs_output_info
*outinfo
;
6711 switch (ctx
->stage
) {
6712 case MESA_SHADER_FRAGMENT
:
6713 case MESA_SHADER_COMPUTE
:
6714 case MESA_SHADER_TESS_CTRL
:
6715 case MESA_SHADER_GEOMETRY
:
6717 case MESA_SHADER_VERTEX
:
6718 if (ctx
->options
->key
.vs
.as_ls
||
6719 ctx
->options
->key
.vs
.as_es
)
6721 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6723 case MESA_SHADER_TESS_EVAL
:
6724 if (ctx
->options
->key
.vs
.as_es
)
6726 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6729 unreachable("Unhandled shader type");
6732 ac_optimize_vs_outputs(&ctx
->ac
,
6734 outinfo
->vs_output_param_offset
,
6736 &outinfo
->param_exports
);
6740 ac_setup_rings(struct radv_shader_context
*ctx
)
6742 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6743 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6744 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
6747 if (ctx
->is_gs_copy_shader
) {
6748 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
6750 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6752 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
6753 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
6755 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
6757 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
6758 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
6759 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6760 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
6763 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6764 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6765 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
6766 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
6771 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6772 const struct nir_shader
*nir
)
6774 switch (nir
->info
.stage
) {
6775 case MESA_SHADER_TESS_CTRL
:
6776 return chip_class
>= CIK
? 128 : 64;
6777 case MESA_SHADER_GEOMETRY
:
6778 return chip_class
>= GFX9
? 128 : 64;
6779 case MESA_SHADER_COMPUTE
:
6785 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6786 nir
->info
.cs
.local_size
[1] *
6787 nir
->info
.cs
.local_size
[2];
6788 return max_workgroup_size
;
6791 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6792 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
6794 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6795 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6796 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6797 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6799 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6800 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6801 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
6802 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6805 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
6807 for(int i
= 5; i
>= 0; --i
) {
6808 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6809 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6810 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6813 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6814 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6815 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6818 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6819 struct nir_shader
*nir
)
6821 struct ac_nir_context ctx
= {};
6822 struct nir_function
*func
;
6824 /* Last minute passes for both radv & radeonsi */
6825 ac_lower_subgroups(nir
);
6830 ctx
.stage
= nir
->info
.stage
;
6832 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6834 nir_foreach_variable(variable
, &nir
->outputs
)
6835 handle_shader_output_decl(&ctx
, nir
, variable
);
6837 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6838 _mesa_key_pointer_equal
);
6839 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6840 _mesa_key_pointer_equal
);
6841 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6842 _mesa_key_pointer_equal
);
6844 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6846 setup_locals(&ctx
, func
);
6848 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6849 setup_shared(&ctx
, nir
);
6851 visit_cf_list(&ctx
, &func
->impl
->body
);
6852 phi_post_pass(&ctx
);
6854 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
6855 ctx
.abi
->emit_outputs(ctx
.abi
, AC_LLVM_MAX_OUTPUTS
,
6859 ralloc_free(ctx
.defs
);
6860 ralloc_free(ctx
.phis
);
6861 ralloc_free(ctx
.vars
);
6865 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6866 struct nir_shader
*const *shaders
,
6868 struct ac_shader_variant_info
*shader_info
,
6869 const struct ac_nir_compiler_options
*options
,
6872 struct radv_shader_context ctx
= {0};
6874 ctx
.options
= options
;
6875 ctx
.shader_info
= shader_info
;
6876 ctx
.context
= LLVMContextCreate();
6878 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
6880 ctx
.ac
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6881 LLVMSetTarget(ctx
.ac
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6883 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6884 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6885 LLVMSetDataLayout(ctx
.ac
.module
, data_layout_str
);
6886 LLVMDisposeTargetData(data_layout
);
6887 LLVMDisposeMessage(data_layout_str
);
6889 enum ac_float_mode float_mode
=
6890 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
6891 AC_FLOAT_MODE_DEFAULT
;
6893 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
6895 memset(shader_info
, 0, sizeof(*shader_info
));
6897 for(int i
= 0; i
< shader_count
; ++i
)
6898 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6900 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6901 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6902 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6903 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6905 ctx
.max_workgroup_size
= 0;
6906 for (int i
= 0; i
< shader_count
; ++i
) {
6907 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6908 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6912 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6913 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6915 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6916 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6917 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
6918 ctx
.abi
.load_ubo
= radv_load_ubo
;
6919 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6920 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6921 ctx
.abi
.load_resource
= radv_load_resource
;
6922 ctx
.abi
.clamp_shadow_reference
= false;
6924 if (shader_count
>= 2)
6925 ac_init_exec_full_mask(&ctx
.ac
);
6927 if (ctx
.ac
.chip_class
== GFX9
&&
6928 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6929 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6931 for(int i
= 0; i
< shader_count
; ++i
) {
6932 ctx
.stage
= shaders
[i
]->info
.stage
;
6933 ctx
.output_mask
= 0;
6934 ctx
.tess_outputs_written
= 0;
6935 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6936 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6938 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6939 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
6940 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6941 ctx
.abi
.load_inputs
= load_gs_input
;
6942 ctx
.abi
.emit_primitive
= visit_end_primitive
;
6943 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6944 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
6945 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
6946 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
6947 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6948 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
6949 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
6950 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6951 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6952 ctx
.abi
.load_tess_varyings
= load_tes_input
;
6953 ctx
.abi
.load_tess_coord
= load_tess_coord
;
6954 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6955 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
6956 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6957 if (shader_info
->info
.vs
.needs_instance_id
) {
6958 if (ctx
.options
->key
.vs
.as_ls
) {
6959 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6960 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6962 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6963 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6966 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
6967 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6968 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6969 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
6970 ctx
.abi
.load_sample_position
= load_sample_position
;
6971 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
6972 ctx
.abi
.emit_kill
= radv_emit_kill
;
6976 emit_barrier(&ctx
.ac
, ctx
.stage
);
6978 ac_setup_rings(&ctx
);
6980 LLVMBasicBlockRef merge_block
;
6981 if (shader_count
>= 2) {
6982 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6983 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6984 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6986 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6987 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6988 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6989 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6990 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6991 thread_id
, count
, "");
6992 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6994 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6997 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6998 handle_fs_inputs(&ctx
, shaders
[i
]);
6999 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
7000 handle_vs_inputs(&ctx
, shaders
[i
]);
7001 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
7002 prepare_gs_input_vgprs(&ctx
);
7004 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
7005 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
7007 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
7009 if (shader_count
>= 2) {
7010 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
7011 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
7014 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
7015 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
7016 shaders
[i
]->info
.cull_distance_array_size
> 4;
7017 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
7018 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
7019 shaders
[i
]->info
.gs
.vertices_out
;
7020 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7021 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
7022 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
7023 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
7024 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
7028 LLVMBuildRetVoid(ctx
.ac
.builder
);
7030 if (options
->dump_preoptir
)
7031 ac_dump_module(ctx
.ac
.module
);
7033 ac_llvm_finalize_module(&ctx
);
7035 if (shader_count
== 1)
7036 ac_nir_eliminate_const_vs_outputs(&ctx
);
7039 ctx
.shader_info
->private_mem_vgprs
=
7040 ac_count_scratch_private_memory(ctx
.main_function
);
7043 return ctx
.ac
.module
;
7046 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
7048 unsigned *retval
= (unsigned *)context
;
7049 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
7050 char *description
= LLVMGetDiagInfoDescription(di
);
7052 if (severity
== LLVMDSError
) {
7054 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
7058 LLVMDisposeMessage(description
);
7061 static unsigned ac_llvm_compile(LLVMModuleRef M
,
7062 struct ac_shader_binary
*binary
,
7063 LLVMTargetMachineRef tm
)
7065 unsigned retval
= 0;
7067 LLVMContextRef llvm_ctx
;
7068 LLVMMemoryBufferRef out_buffer
;
7069 unsigned buffer_size
;
7070 const char *buffer_data
;
7073 /* Setup Diagnostic Handler*/
7074 llvm_ctx
= LLVMGetModuleContext(M
);
7076 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
7080 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
7083 /* Process Errors/Warnings */
7085 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
7091 /* Extract Shader Code*/
7092 buffer_size
= LLVMGetBufferSize(out_buffer
);
7093 buffer_data
= LLVMGetBufferStart(out_buffer
);
7095 ac_elf_read(buffer_data
, buffer_size
, binary
);
7098 LLVMDisposeMemoryBuffer(out_buffer
);
7104 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
7105 LLVMModuleRef llvm_module
,
7106 struct ac_shader_binary
*binary
,
7107 struct ac_shader_config
*config
,
7108 struct ac_shader_variant_info
*shader_info
,
7109 gl_shader_stage stage
,
7110 bool dump_shader
, bool supports_spill
)
7113 ac_dump_module(llvm_module
);
7115 memset(binary
, 0, sizeof(*binary
));
7116 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
7118 fprintf(stderr
, "compile failed\n");
7122 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
7124 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
7126 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
7127 LLVMDisposeModule(llvm_module
);
7128 LLVMContextDispose(ctx
);
7130 if (stage
== MESA_SHADER_FRAGMENT
) {
7131 shader_info
->num_input_vgprs
= 0;
7132 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
7133 shader_info
->num_input_vgprs
+= 2;
7134 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
7135 shader_info
->num_input_vgprs
+= 2;
7136 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
7137 shader_info
->num_input_vgprs
+= 2;
7138 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
7139 shader_info
->num_input_vgprs
+= 3;
7140 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
7141 shader_info
->num_input_vgprs
+= 2;
7142 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
7143 shader_info
->num_input_vgprs
+= 2;
7144 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
7145 shader_info
->num_input_vgprs
+= 2;
7146 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
7147 shader_info
->num_input_vgprs
+= 1;
7148 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
7149 shader_info
->num_input_vgprs
+= 1;
7150 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
7151 shader_info
->num_input_vgprs
+= 1;
7152 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
7153 shader_info
->num_input_vgprs
+= 1;
7154 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
7155 shader_info
->num_input_vgprs
+= 1;
7156 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
7157 shader_info
->num_input_vgprs
+= 1;
7158 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
7159 shader_info
->num_input_vgprs
+= 1;
7160 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
7161 shader_info
->num_input_vgprs
+= 1;
7162 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
7163 shader_info
->num_input_vgprs
+= 1;
7165 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
7167 /* +3 for scratch wave offset and VCC */
7168 config
->num_sgprs
= MAX2(config
->num_sgprs
,
7169 shader_info
->num_input_sgprs
+ 3);
7171 /* Enable 64-bit and 16-bit denormals, because there is no performance
7174 * If denormals are enabled, all floating-point output modifiers are
7177 * Don't enable denormals for 32-bit floats, because:
7178 * - Floating-point output modifiers would be ignored by the hw.
7179 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7180 * have to stop using those.
7181 * - SI & CI would be very slow.
7183 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
7187 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
7189 switch (nir
->info
.stage
) {
7190 case MESA_SHADER_COMPUTE
:
7191 for (int i
= 0; i
< 3; ++i
)
7192 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
7194 case MESA_SHADER_FRAGMENT
:
7195 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
7197 case MESA_SHADER_GEOMETRY
:
7198 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
7199 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
7200 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
7201 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
7203 case MESA_SHADER_TESS_EVAL
:
7204 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
7205 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
7206 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
7207 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
7208 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
7210 case MESA_SHADER_TESS_CTRL
:
7211 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
7213 case MESA_SHADER_VERTEX
:
7214 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
7215 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
7216 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7217 if (options
->key
.vs
.as_ls
)
7218 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
7225 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
7226 struct ac_shader_binary
*binary
,
7227 struct ac_shader_config
*config
,
7228 struct ac_shader_variant_info
*shader_info
,
7229 struct nir_shader
*const *nir
,
7231 const struct ac_nir_compiler_options
*options
,
7235 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
7236 options
, dump_shader
);
7238 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
7239 for (int i
= 0; i
< nir_count
; ++i
)
7240 ac_fill_shader_info(shader_info
, nir
[i
], options
);
7242 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7243 if (options
->chip_class
== GFX9
) {
7244 if (nir_count
== 2 &&
7245 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
7246 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
7252 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
7254 LLVMValueRef vtx_offset
=
7255 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
7256 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
7259 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
7263 if (!(ctx
->output_mask
& (1ull << i
)))
7266 if (i
== VARYING_SLOT_CLIP_DIST0
) {
7267 /* unpack clip and cull from a single set of slots */
7268 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
7273 for (unsigned j
= 0; j
< length
; j
++) {
7274 LLVMValueRef value
, soffset
;
7276 soffset
= LLVMConstInt(ctx
->ac
.i32
,
7278 ctx
->gs_max_out_vertices
* 16 * 4, false);
7280 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->gsvs_ring
,
7282 vtx_offset
, soffset
,
7283 0, 1, 1, true, false);
7285 LLVMBuildStore(ctx
->ac
.builder
,
7286 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
7290 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
7293 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
7294 struct nir_shader
*geom_shader
,
7295 struct ac_shader_binary
*binary
,
7296 struct ac_shader_config
*config
,
7297 struct ac_shader_variant_info
*shader_info
,
7298 const struct ac_nir_compiler_options
*options
,
7301 struct radv_shader_context ctx
= {0};
7302 ctx
.context
= LLVMContextCreate();
7303 ctx
.options
= options
;
7304 ctx
.shader_info
= shader_info
;
7306 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
7308 ctx
.ac
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
7310 ctx
.is_gs_copy_shader
= true;
7311 LLVMSetTarget(ctx
.ac
.module
, "amdgcn--");
7313 enum ac_float_mode float_mode
=
7314 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
7315 AC_FLOAT_MODE_DEFAULT
;
7317 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
7318 ctx
.stage
= MESA_SHADER_VERTEX
;
7320 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
7322 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
7323 ac_setup_rings(&ctx
);
7325 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
7326 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
7328 struct ac_nir_context nir_ctx
= {};
7329 nir_ctx
.ac
= ctx
.ac
;
7330 nir_ctx
.abi
= &ctx
.abi
;
7332 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
7333 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
7334 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
7337 ac_gs_copy_shader_emit(&ctx
);
7339 LLVMBuildRetVoid(ctx
.ac
.builder
);
7341 ac_llvm_finalize_module(&ctx
);
7343 ac_compile_llvm_module(tm
, ctx
.ac
.module
, binary
, config
, shader_info
,
7345 dump_shader
, options
->supports_spill
);
7349 ac_lower_indirect_derefs(struct nir_shader
*nir
, enum chip_class chip_class
)
7351 /* While it would be nice not to have this flag, we are constrained
7352 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
7355 bool llvm_has_working_vgpr_indexing
= chip_class
<= VI
;
7357 /* TODO: Indirect indexing of GS inputs is unimplemented.
7359 * TCS and TES load inputs directly from LDS or offchip memory, so
7360 * indirect indexing is trivial.
7362 nir_variable_mode indirect_mask
= 0;
7363 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
||
7364 (nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
&&
7365 nir
->info
.stage
!= MESA_SHADER_TESS_EVAL
&&
7366 !llvm_has_working_vgpr_indexing
)) {
7367 indirect_mask
|= nir_var_shader_in
;
7369 if (!llvm_has_working_vgpr_indexing
&&
7370 nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
)
7371 indirect_mask
|= nir_var_shader_out
;
7373 /* TODO: We shouldn't need to do this, however LLVM isn't currently
7374 * smart enough to handle indirects without causing excess spilling
7375 * causing the gpu to hang.
7377 * See the following thread for more details of the problem:
7378 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
7380 indirect_mask
|= nir_var_local
;
7382 nir_lower_indirect_derefs(nir
, indirect_mask
);