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ac/nir: Don't load the descriptor in vulkan_resource_index.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef merged_wave_info;
112 LLVMValueRef tess_factor_offset;
113 LLVMValueRef tcs_patch_id;
114 LLVMValueRef tcs_rel_ids;
115 LLVMValueRef tes_rel_patch_id;
116 LLVMValueRef tes_patch_id;
117 LLVMValueRef tes_u;
118 LLVMValueRef tes_v;
119
120 LLVMValueRef gsvs_ring_stride;
121 LLVMValueRef gsvs_num_entries;
122 LLVMValueRef gs2vs_offset;
123 LLVMValueRef gs_wave_id;
124 LLVMValueRef gs_vtx_offset[6];
125
126 LLVMValueRef esgs_ring;
127 LLVMValueRef gsvs_ring;
128 LLVMValueRef hs_ring_tess_offchip;
129 LLVMValueRef hs_ring_tess_factor;
130
131 LLVMValueRef prim_mask;
132 LLVMValueRef sample_pos_offset;
133 LLVMValueRef persp_sample, persp_center, persp_centroid;
134 LLVMValueRef linear_sample, linear_center, linear_centroid;
135
136 gl_shader_stage stage;
137
138 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
139
140 uint64_t input_mask;
141 uint64_t output_mask;
142 uint8_t num_output_clips;
143 uint8_t num_output_culls;
144
145 bool is_gs_copy_shader;
146 LLVMValueRef gs_next_vertex;
147 unsigned gs_max_out_vertices;
148
149 unsigned tes_primitive_mode;
150 uint64_t tess_outputs_written;
151 uint64_t tess_patch_outputs_written;
152
153 uint32_t tcs_patch_outputs_read;
154 uint64_t tcs_outputs_read;
155 };
156
157 static inline struct nir_to_llvm_context *
158 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
159 {
160 struct nir_to_llvm_context *ctx = NULL;
161 return container_of(abi, ctx, abi);
162 }
163
164 static LLVMTypeRef
165 nir2llvmtype(struct ac_nir_context *ctx,
166 const struct glsl_type *type)
167 {
168 switch (glsl_get_base_type(glsl_without_array(type))) {
169 case GLSL_TYPE_UINT:
170 case GLSL_TYPE_INT:
171 return ctx->ac.i32;
172 case GLSL_TYPE_UINT64:
173 case GLSL_TYPE_INT64:
174 return ctx->ac.i64;
175 case GLSL_TYPE_DOUBLE:
176 return ctx->ac.f64;
177 case GLSL_TYPE_FLOAT:
178 return ctx->ac.f32;
179 default:
180 assert(!"Unsupported type in nir2llvmtype()");
181 break;
182 }
183 return 0;
184 }
185
186 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
187 const nir_deref_var *deref,
188 enum ac_descriptor_type desc_type,
189 const nir_tex_instr *instr,
190 bool image, bool write);
191
192 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
193 {
194 return (index * 4) + chan;
195 }
196
197 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
198 {
199 /* handle patch indices separate */
200 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
201 return 0;
202 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
203 return 1;
204 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
205 return 2 + (slot - VARYING_SLOT_PATCH0);
206
207 if (slot == VARYING_SLOT_POS)
208 return 0;
209 if (slot == VARYING_SLOT_PSIZ)
210 return 1;
211 if (slot == VARYING_SLOT_CLIP_DIST0)
212 return 2;
213 /* 3 is reserved for clip dist as well */
214 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
215 return 4 + (slot - VARYING_SLOT_VAR0);
216 unreachable("illegal slot in get unique index\n");
217 }
218
219 static void set_llvm_calling_convention(LLVMValueRef func,
220 gl_shader_stage stage)
221 {
222 enum radeon_llvm_calling_convention calling_conv;
223
224 switch (stage) {
225 case MESA_SHADER_VERTEX:
226 case MESA_SHADER_TESS_EVAL:
227 calling_conv = RADEON_LLVM_AMDGPU_VS;
228 break;
229 case MESA_SHADER_GEOMETRY:
230 calling_conv = RADEON_LLVM_AMDGPU_GS;
231 break;
232 case MESA_SHADER_TESS_CTRL:
233 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
234 break;
235 case MESA_SHADER_FRAGMENT:
236 calling_conv = RADEON_LLVM_AMDGPU_PS;
237 break;
238 case MESA_SHADER_COMPUTE:
239 calling_conv = RADEON_LLVM_AMDGPU_CS;
240 break;
241 default:
242 unreachable("Unhandle shader type");
243 }
244
245 LLVMSetFunctionCallConv(func, calling_conv);
246 }
247
248 #define MAX_ARGS 23
249 struct arg_info {
250 LLVMTypeRef types[MAX_ARGS];
251 LLVMValueRef *assign[MAX_ARGS];
252 unsigned array_params_mask;
253 uint8_t count;
254 uint8_t user_sgpr_count;
255 uint8_t sgpr_count;
256 uint8_t num_user_sgprs_used;
257 uint8_t num_sgprs_used;
258 uint8_t num_vgprs_used;
259 };
260
261 static inline void
262 add_argument(struct arg_info *info,
263 LLVMTypeRef type, LLVMValueRef *param_ptr)
264 {
265 assert(info->count < MAX_ARGS);
266 info->assign[info->count] = param_ptr;
267 info->types[info->count] = type;
268 info->count++;
269 }
270
271 static inline void
272 add_sgpr_argument(struct arg_info *info,
273 LLVMTypeRef type, LLVMValueRef *param_ptr)
274 {
275 add_argument(info, type, param_ptr);
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 }
279
280 static inline void
281 add_user_sgpr_argument(struct arg_info *info,
282 LLVMTypeRef type,
283 LLVMValueRef *param_ptr)
284 {
285 add_sgpr_argument(info, type, param_ptr);
286 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
287 info->user_sgpr_count++;
288 }
289
290 static inline void
291 add_vgpr_argument(struct arg_info *info,
292 LLVMTypeRef type,
293 LLVMValueRef *param_ptr)
294 {
295 add_argument(info, type, param_ptr);
296 info->num_vgprs_used += ac_get_type_size(type) / 4;
297 }
298
299 static inline void
300 add_user_sgpr_array_argument(struct arg_info *info,
301 LLVMTypeRef type,
302 LLVMValueRef *param_ptr)
303 {
304 info->array_params_mask |= (1 << info->count);
305 add_user_sgpr_argument(info, type, param_ptr);
306 }
307
308 static void assign_arguments(LLVMValueRef main_function,
309 struct arg_info *info)
310 {
311 unsigned i;
312 for (i = 0; i < info->count; i++) {
313 if (info->assign[i])
314 *info->assign[i] = LLVMGetParam(main_function, i);
315 }
316 }
317
318 static LLVMValueRef
319 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
320 LLVMBuilderRef builder, LLVMTypeRef *return_types,
321 unsigned num_return_elems,
322 struct arg_info *args,
323 unsigned max_workgroup_size,
324 bool unsafe_math)
325 {
326 LLVMTypeRef main_function_type, ret_type;
327 LLVMBasicBlockRef main_function_body;
328
329 if (num_return_elems)
330 ret_type = LLVMStructTypeInContext(ctx, return_types,
331 num_return_elems, true);
332 else
333 ret_type = LLVMVoidTypeInContext(ctx);
334
335 /* Setup the function */
336 main_function_type =
337 LLVMFunctionType(ret_type, args->types, args->count, 0);
338 LLVMValueRef main_function =
339 LLVMAddFunction(module, "main", main_function_type);
340 main_function_body =
341 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
342 LLVMPositionBuilderAtEnd(builder, main_function_body);
343
344 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
345 for (unsigned i = 0; i < args->sgpr_count; ++i) {
346 if (args->array_params_mask & (1 << i)) {
347 LLVMValueRef P = LLVMGetParam(main_function, i);
348 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
349 ac_add_attr_dereferenceable(P, UINT64_MAX);
350 }
351 else {
352 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
353 }
354 }
355
356 if (max_workgroup_size) {
357 ac_llvm_add_target_dep_function_attr(main_function,
358 "amdgpu-max-work-group-size",
359 max_workgroup_size);
360 }
361 if (unsafe_math) {
362 /* These were copied from some LLVM test. */
363 LLVMAddTargetDependentFunctionAttr(main_function,
364 "less-precise-fpmad",
365 "true");
366 LLVMAddTargetDependentFunctionAttr(main_function,
367 "no-infs-fp-math",
368 "true");
369 LLVMAddTargetDependentFunctionAttr(main_function,
370 "no-nans-fp-math",
371 "true");
372 LLVMAddTargetDependentFunctionAttr(main_function,
373 "unsafe-fp-math",
374 "true");
375 }
376 return main_function;
377 }
378
379 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
380 {
381 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
382 CONST_ADDR_SPACE);
383 }
384
385 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
386 {
387 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
388 type = LLVMGetElementType(type);
389
390 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
391 return LLVMGetIntTypeWidth(type);
392
393 if (type == ctx->f16)
394 return 16;
395 if (type == ctx->f32)
396 return 32;
397 if (type == ctx->f64)
398 return 64;
399
400 unreachable("Unhandled type kind in get_elem_bits");
401 }
402
403 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
404 LLVMValueRef param, unsigned rshift,
405 unsigned bitwidth)
406 {
407 LLVMValueRef value = param;
408 if (rshift)
409 value = LLVMBuildLShr(ctx->builder, value,
410 LLVMConstInt(ctx->i32, rshift, false), "");
411
412 if (rshift + bitwidth < 32) {
413 unsigned mask = (1 << bitwidth) - 1;
414 value = LLVMBuildAnd(ctx->builder, value,
415 LLVMConstInt(ctx->i32, mask, false), "");
416 }
417 return value;
418 }
419
420 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
421 {
422 switch (ctx->stage) {
423 case MESA_SHADER_TESS_CTRL:
424 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
425 case MESA_SHADER_TESS_EVAL:
426 return ctx->tes_rel_patch_id;
427 break;
428 default:
429 unreachable("Illegal stage");
430 }
431 }
432
433 /* Tessellation shaders pass outputs to the next shader using LDS.
434 *
435 * LS outputs = TCS inputs
436 * TCS outputs = TES inputs
437 *
438 * The LDS layout is:
439 * - TCS inputs for patch 0
440 * - TCS inputs for patch 1
441 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
442 * - ...
443 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
444 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
445 * - TCS outputs for patch 1
446 * - Per-patch TCS outputs for patch 1
447 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
448 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
449 * - ...
450 *
451 * All three shaders VS(LS), TCS, TES share the same LDS space.
452 */
453 static LLVMValueRef
454 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
455 {
456 if (ctx->stage == MESA_SHADER_VERTEX)
457 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
458 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
459 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
460 else {
461 assert(0);
462 return NULL;
463 }
464 }
465
466 static LLVMValueRef
467 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
468 {
469 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
470 }
471
472 static LLVMValueRef
473 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
474 {
475 return LLVMBuildMul(ctx->builder,
476 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
477 LLVMConstInt(ctx->ac.i32, 4, false), "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
482 {
483 return LLVMBuildMul(ctx->builder,
484 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
485 LLVMConstInt(ctx->ac.i32, 4, false), "");
486 }
487
488 static LLVMValueRef
489 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
490 {
491 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
492 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
493
494 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
495 }
496
497 static LLVMValueRef
498 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
499 {
500 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
501 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
502 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
503
504 return LLVMBuildAdd(ctx->builder, patch0_offset,
505 LLVMBuildMul(ctx->builder, patch_stride,
506 rel_patch_id, ""),
507 "");
508 }
509
510 static LLVMValueRef
511 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
512 {
513 LLVMValueRef patch0_patch_data_offset =
514 get_tcs_out_patch0_patch_data_offset(ctx);
515 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
516 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
517
518 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
519 LLVMBuildMul(ctx->builder, patch_stride,
520 rel_patch_id, ""),
521 "");
522 }
523
524 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
525 {
526 ud_info->sgpr_idx = *sgpr_idx;
527 ud_info->num_sgprs = num_sgprs;
528 ud_info->indirect = false;
529 ud_info->indirect_offset = 0;
530 *sgpr_idx += num_sgprs;
531 }
532
533 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
534 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
535 {
536 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
537 }
538
539
540 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
541 uint32_t indirect_offset)
542 {
543 ud_info->sgpr_idx = sgpr_idx;
544 ud_info->num_sgprs = num_sgprs;
545 ud_info->indirect = true;
546 ud_info->indirect_offset = indirect_offset;
547 }
548
549 struct user_sgpr_info {
550 bool need_ring_offsets;
551 uint8_t sgpr_count;
552 bool indirect_all_descriptor_sets;
553 };
554
555 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
556 struct user_sgpr_info *user_sgpr_info)
557 {
558 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
559
560 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
561 if (ctx->stage == MESA_SHADER_GEOMETRY ||
562 ctx->stage == MESA_SHADER_VERTEX ||
563 ctx->stage == MESA_SHADER_TESS_CTRL ||
564 ctx->stage == MESA_SHADER_TESS_EVAL ||
565 ctx->is_gs_copy_shader)
566 user_sgpr_info->need_ring_offsets = true;
567
568 if (ctx->stage == MESA_SHADER_FRAGMENT &&
569 ctx->shader_info->info.ps.needs_sample_positions)
570 user_sgpr_info->need_ring_offsets = true;
571
572 /* 2 user sgprs will nearly always be allocated for scratch/rings */
573 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
574 user_sgpr_info->sgpr_count += 2;
575 }
576
577 switch (ctx->stage) {
578 case MESA_SHADER_COMPUTE:
579 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
580 break;
581 case MESA_SHADER_FRAGMENT:
582 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
583 break;
584 case MESA_SHADER_VERTEX:
585 if (!ctx->is_gs_copy_shader) {
586 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
587 if (ctx->shader_info->info.vs.needs_draw_id) {
588 user_sgpr_info->sgpr_count += 3;
589 } else {
590 user_sgpr_info->sgpr_count += 2;
591 }
592 }
593 if (ctx->options->key.vs.as_ls)
594 user_sgpr_info->sgpr_count++;
595 break;
596 case MESA_SHADER_TESS_CTRL:
597 user_sgpr_info->sgpr_count += 4;
598 break;
599 case MESA_SHADER_TESS_EVAL:
600 user_sgpr_info->sgpr_count += 1;
601 break;
602 case MESA_SHADER_GEOMETRY:
603 user_sgpr_info->sgpr_count += 2;
604 break;
605 default:
606 break;
607 }
608
609 if (ctx->shader_info->info.needs_push_constants)
610 user_sgpr_info->sgpr_count += 2;
611
612 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
613 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
614 user_sgpr_info->sgpr_count += 2;
615 user_sgpr_info->indirect_all_descriptor_sets = true;
616 } else {
617 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
618 }
619 }
620
621 static void
622 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
623 gl_shader_stage stage,
624 bool has_previous_stage,
625 gl_shader_stage previous_stage,
626 const struct user_sgpr_info *user_sgpr_info,
627 struct arg_info *args,
628 LLVMValueRef *desc_sets)
629 {
630 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
631 unsigned stage_mask = 1 << stage;
632 if (has_previous_stage)
633 stage_mask |= 1 << previous_stage;
634
635 /* 1 for each descriptor set */
636 if (!user_sgpr_info->indirect_all_descriptor_sets) {
637 for (unsigned i = 0; i < num_sets; ++i) {
638 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
639 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->descriptor_sets[i]);
640 }
641 }
642 } else
643 add_user_sgpr_array_argument(args, const_array(const_array(ctx->ac.i8, 1024 * 1024), 32), desc_sets);
644
645 if (ctx->shader_info->info.needs_push_constants) {
646 /* 1 for push constants and dynamic descriptors */
647 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->push_constants);
648 }
649 }
650
651 static void
652 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
653 gl_shader_stage stage,
654 bool has_previous_stage,
655 gl_shader_stage previous_stage,
656 const struct user_sgpr_info *user_sgpr_info,
657 LLVMValueRef desc_sets,
658 uint8_t *user_sgpr_idx)
659 {
660 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
661 unsigned stage_mask = 1 << stage;
662 if (has_previous_stage)
663 stage_mask |= 1 << previous_stage;
664
665 if (!user_sgpr_info->indirect_all_descriptor_sets) {
666 for (unsigned i = 0; i < num_sets; ++i) {
667 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
668 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
669 } else
670 ctx->descriptor_sets[i] = NULL;
671 }
672 } else {
673 uint32_t desc_sgpr_idx = *user_sgpr_idx;
674 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
675
676 for (unsigned i = 0; i < num_sets; ++i) {
677 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
678 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
679 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
680
681 } else
682 ctx->descriptor_sets[i] = NULL;
683 }
684 ctx->shader_info->need_indirect_descriptor_sets = true;
685 }
686
687 if (ctx->shader_info->info.needs_push_constants) {
688 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
689 }
690 }
691
692 static void
693 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
694 gl_shader_stage stage,
695 bool has_previous_stage,
696 gl_shader_stage previous_stage,
697 struct arg_info *args)
698 {
699 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
700 if (ctx->shader_info->info.vs.has_vertex_buffers)
701 add_user_sgpr_argument(args, const_array(ctx->ac.v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
702 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.base_vertex); // base vertex
703 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.start_instance);// start instance
704 if (ctx->shader_info->info.vs.needs_draw_id)
705 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.draw_id); // draw id
706 }
707 }
708
709 static void
710 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
711 gl_shader_stage stage,
712 bool has_previous_stage,
713 gl_shader_stage previous_stage,
714 uint8_t *user_sgpr_idx)
715 {
716 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
717 if (ctx->shader_info->info.vs.has_vertex_buffers) {
718 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
719 }
720 unsigned vs_num = 2;
721 if (ctx->shader_info->info.vs.needs_draw_id)
722 vs_num++;
723
724 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
725 }
726 }
727
728
729 static void create_function(struct nir_to_llvm_context *ctx,
730 gl_shader_stage stage,
731 bool has_previous_stage,
732 gl_shader_stage previous_stage)
733 {
734 uint8_t user_sgpr_idx;
735 struct user_sgpr_info user_sgpr_info;
736 struct arg_info args = {};
737 LLVMValueRef desc_sets;
738
739 allocate_user_sgprs(ctx, &user_sgpr_info);
740
741 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
742 add_user_sgpr_argument(&args, const_array(ctx->ac.v4i32, 16), &ctx->ring_offsets); /* address of rings */
743 }
744
745 switch (stage) {
746 case MESA_SHADER_COMPUTE:
747 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
748 if (ctx->shader_info->info.cs.grid_components_used)
749 add_user_sgpr_argument(&args, LLVMVectorType(ctx->ac.i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
750 add_sgpr_argument(&args, ctx->ac.v3i32, &ctx->workgroup_ids);
751 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
752 add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
753 break;
754 case MESA_SHADER_VERTEX:
755 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
756 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
757 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
758 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
759 if (ctx->options->key.vs.as_es)
760 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
761 else if (ctx->options->key.vs.as_ls)
762 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
763 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
764 if (!ctx->is_gs_copy_shader) {
765 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
766 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
767 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
768 }
769 break;
770 case MESA_SHADER_TESS_CTRL:
771 if (has_previous_stage) {
772 // First 6 system regs
773 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
774 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
775 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
776
777 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
778 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
779 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
780
781 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
782 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
783 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
784
785 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
786 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
787 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
788 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
789 if (ctx->shader_info->info.needs_multiview_view_index)
790 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
791
792 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
793 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
794 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
795 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
796 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
797 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
798 } else {
799 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
800 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
801 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
802 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
803 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
804 if (ctx->shader_info->info.needs_multiview_view_index)
805 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
806 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
807 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
808 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
809 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
810 }
811 break;
812 case MESA_SHADER_TESS_EVAL:
813 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
814 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
815 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
816 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
817 if (ctx->options->key.tes.as_es) {
818 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
819 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
820 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
821 } else {
822 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
823 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
824 }
825 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
826 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
827 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
828 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
829 break;
830 case MESA_SHADER_GEOMETRY:
831 if (has_previous_stage) {
832 // First 6 system regs
833 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
834 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
835 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
836
837 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
838 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
839 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
840
841 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
842 if (previous_stage == MESA_SHADER_TESS_EVAL)
843 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
844 else
845 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
846 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
847 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
848 if (ctx->shader_info->info.needs_multiview_view_index)
849 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
850
851 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx01
852 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]); // vtx23
853 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
854 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
855 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
856
857 if (previous_stage == MESA_SHADER_VERTEX) {
858 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
859 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
860 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
861 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
862 } else {
863 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
864 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
865 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
866 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
867 }
868 } else {
869 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
870 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
871 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
872 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
873 if (ctx->shader_info->info.needs_multiview_view_index)
874 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
875 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
876 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
877 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx0
878 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[1]); // vtx1
879 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
880 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]);
881 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[3]);
882 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
883 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[5]);
884 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
885 }
886 break;
887 case MESA_SHADER_FRAGMENT:
888 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
889 if (ctx->shader_info->info.ps.needs_sample_positions)
890 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */
891 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
892 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /* persp sample */
893 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /* persp center */
894 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid); /* persp centroid */
895 add_vgpr_argument(&args, ctx->ac.v3i32, NULL); /* persp pull model */
896 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_sample); /* linear sample */
897 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_center); /* linear center */
898 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_centroid); /* linear centroid */
899 add_vgpr_argument(&args, ctx->ac.f32, NULL); /* line stipple tex */
900 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[0]); /* pos x float */
901 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[1]); /* pos y float */
902 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[2]); /* pos z float */
903 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[3]); /* pos w float */
904 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */
905 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */
906 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.sample_coverage); /* sample coverage */
907 add_vgpr_argument(&args, ctx->ac.i32, NULL); /* fixed pt */
908 break;
909 default:
910 unreachable("Shader stage not implemented");
911 }
912
913 ctx->main_function = create_llvm_function(
914 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
915 ctx->max_workgroup_size,
916 ctx->options->unsafe_math);
917 set_llvm_calling_convention(ctx->main_function, stage);
918
919
920 ctx->shader_info->num_input_vgprs = 0;
921 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
922
923 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
924
925 if (ctx->stage != MESA_SHADER_FRAGMENT)
926 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
927
928 assign_arguments(ctx->main_function, &args);
929
930 user_sgpr_idx = 0;
931
932 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
933 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
934 if (ctx->options->supports_spill) {
935 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
936 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
937 NULL, 0, AC_FUNC_ATTR_READNONE);
938 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
939 const_array(ctx->ac.v4i32, 16), "");
940 }
941 }
942
943 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
944 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
945 if (has_previous_stage)
946 user_sgpr_idx = 0;
947
948 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
949
950 switch (stage) {
951 case MESA_SHADER_COMPUTE:
952 if (ctx->shader_info->info.cs.grid_components_used) {
953 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
954 }
955 break;
956 case MESA_SHADER_VERTEX:
957 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
958 if (ctx->view_index)
959 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
960 if (ctx->options->key.vs.as_ls) {
961 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
962 }
963 if (ctx->options->key.vs.as_ls)
964 ac_declare_lds_as_pointer(&ctx->ac);
965 break;
966 case MESA_SHADER_TESS_CTRL:
967 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
968 if (has_previous_stage)
969 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
970 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
971 if (ctx->view_index)
972 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
973 ac_declare_lds_as_pointer(&ctx->ac);
974 break;
975 case MESA_SHADER_TESS_EVAL:
976 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
977 if (ctx->view_index)
978 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
979 break;
980 case MESA_SHADER_GEOMETRY:
981 if (has_previous_stage) {
982 if (previous_stage == MESA_SHADER_VERTEX)
983 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
984 else
985 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
986 }
987 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
988 if (ctx->view_index)
989 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
990 if (has_previous_stage)
991 ac_declare_lds_as_pointer(&ctx->ac);
992 break;
993 case MESA_SHADER_FRAGMENT:
994 if (ctx->shader_info->info.ps.needs_sample_positions) {
995 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
996 }
997 break;
998 default:
999 unreachable("Shader stage not implemented");
1000 }
1001
1002 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1003 }
1004
1005 static int get_llvm_num_components(LLVMValueRef value)
1006 {
1007 LLVMTypeRef type = LLVMTypeOf(value);
1008 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1009 ? LLVMGetVectorSize(type)
1010 : 1;
1011 return num_components;
1012 }
1013
1014 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1015 LLVMValueRef value,
1016 int index)
1017 {
1018 int count = get_llvm_num_components(value);
1019
1020 if (count == 1)
1021 return value;
1022
1023 return LLVMBuildExtractElement(ac->builder, value,
1024 LLVMConstInt(ac->i32, index, false), "");
1025 }
1026
1027 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1028 LLVMValueRef value, unsigned count)
1029 {
1030 unsigned num_components = get_llvm_num_components(value);
1031 if (count == num_components)
1032 return value;
1033
1034 LLVMValueRef masks[] = {
1035 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1036 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1037
1038 if (count == 1)
1039 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1040 "");
1041
1042 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1043 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1044 }
1045
1046 static void
1047 build_store_values_extended(struct ac_llvm_context *ac,
1048 LLVMValueRef *values,
1049 unsigned value_count,
1050 unsigned value_stride,
1051 LLVMValueRef vec)
1052 {
1053 LLVMBuilderRef builder = ac->builder;
1054 unsigned i;
1055
1056 for (i = 0; i < value_count; i++) {
1057 LLVMValueRef ptr = values[i * value_stride];
1058 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1059 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1060 LLVMBuildStore(builder, value, ptr);
1061 }
1062 }
1063
1064 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1065 const nir_ssa_def *def)
1066 {
1067 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1068 if (def->num_components > 1) {
1069 type = LLVMVectorType(type, def->num_components);
1070 }
1071 return type;
1072 }
1073
1074 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1075 {
1076 assert(src.is_ssa);
1077 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1078 return (LLVMValueRef)entry->data;
1079 }
1080
1081
1082 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1083 const struct nir_block *b)
1084 {
1085 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1086 return (LLVMBasicBlockRef)entry->data;
1087 }
1088
1089 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1090 nir_alu_src src,
1091 unsigned num_components)
1092 {
1093 LLVMValueRef value = get_src(ctx, src.src);
1094 bool need_swizzle = false;
1095
1096 assert(value);
1097 LLVMTypeRef type = LLVMTypeOf(value);
1098 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1099 ? LLVMGetVectorSize(type)
1100 : 1;
1101
1102 for (unsigned i = 0; i < num_components; ++i) {
1103 assert(src.swizzle[i] < src_components);
1104 if (src.swizzle[i] != i)
1105 need_swizzle = true;
1106 }
1107
1108 if (need_swizzle || num_components != src_components) {
1109 LLVMValueRef masks[] = {
1110 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1111 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1112 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1113 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1114
1115 if (src_components > 1 && num_components == 1) {
1116 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1117 masks[0], "");
1118 } else if (src_components == 1 && num_components > 1) {
1119 LLVMValueRef values[] = {value, value, value, value};
1120 value = ac_build_gather_values(&ctx->ac, values, num_components);
1121 } else {
1122 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1123 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1124 swizzle, "");
1125 }
1126 }
1127 assert(!src.negate);
1128 assert(!src.abs);
1129 return value;
1130 }
1131
1132 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1133 LLVMIntPredicate pred, LLVMValueRef src0,
1134 LLVMValueRef src1)
1135 {
1136 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1137 return LLVMBuildSelect(ctx->builder, result,
1138 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1139 LLVMConstInt(ctx->i32, 0, false), "");
1140 }
1141
1142 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1143 LLVMRealPredicate pred, LLVMValueRef src0,
1144 LLVMValueRef src1)
1145 {
1146 LLVMValueRef result;
1147 src0 = ac_to_float(ctx, src0);
1148 src1 = ac_to_float(ctx, src1);
1149 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1150 return LLVMBuildSelect(ctx->builder, result,
1151 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1152 LLVMConstInt(ctx->i32, 0, false), "");
1153 }
1154
1155 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1156 const char *intrin,
1157 LLVMTypeRef result_type,
1158 LLVMValueRef src0)
1159 {
1160 char name[64];
1161 LLVMValueRef params[] = {
1162 ac_to_float(ctx, src0),
1163 };
1164
1165 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1166 get_elem_bits(ctx, result_type));
1167 assert(length < sizeof(name));
1168 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1169 }
1170
1171 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1172 const char *intrin,
1173 LLVMTypeRef result_type,
1174 LLVMValueRef src0, LLVMValueRef src1)
1175 {
1176 char name[64];
1177 LLVMValueRef params[] = {
1178 ac_to_float(ctx, src0),
1179 ac_to_float(ctx, src1),
1180 };
1181
1182 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1183 get_elem_bits(ctx, result_type));
1184 assert(length < sizeof(name));
1185 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1186 }
1187
1188 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1189 const char *intrin,
1190 LLVMTypeRef result_type,
1191 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1192 {
1193 char name[64];
1194 LLVMValueRef params[] = {
1195 ac_to_float(ctx, src0),
1196 ac_to_float(ctx, src1),
1197 ac_to_float(ctx, src2),
1198 };
1199
1200 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1201 get_elem_bits(ctx, result_type));
1202 assert(length < sizeof(name));
1203 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1204 }
1205
1206 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1207 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1208 {
1209 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1210 ctx->i32_0, "");
1211 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1212 }
1213
1214 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1215 LLVMIntPredicate pred,
1216 LLVMValueRef src0, LLVMValueRef src1)
1217 {
1218 return LLVMBuildSelect(ctx->builder,
1219 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1220 src0,
1221 src1, "");
1222
1223 }
1224 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1225 LLVMValueRef src0)
1226 {
1227 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1228 LLVMBuildNeg(ctx->builder, src0, ""));
1229 }
1230
1231 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1232 LLVMValueRef src0)
1233 {
1234 LLVMValueRef cmp, val;
1235
1236 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1237 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1238 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1239 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1240 return val;
1241 }
1242
1243 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1244 LLVMValueRef src0)
1245 {
1246 LLVMValueRef cmp, val;
1247
1248 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1249 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1250 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1251 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1252 return val;
1253 }
1254
1255 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1256 LLVMValueRef src0)
1257 {
1258 const char *intr = "llvm.floor.f32";
1259 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1260 LLVMValueRef params[] = {
1261 fsrc0,
1262 };
1263 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1264 ctx->f32, params, 1,
1265 AC_FUNC_ATTR_READNONE);
1266 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1267 }
1268
1269 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1270 const char *intrin,
1271 LLVMValueRef src0, LLVMValueRef src1)
1272 {
1273 LLVMTypeRef ret_type;
1274 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1275 LLVMValueRef res;
1276 LLVMValueRef params[] = { src0, src1 };
1277 ret_type = LLVMStructTypeInContext(ctx->context, types,
1278 2, true);
1279
1280 res = ac_build_intrinsic(ctx, intrin, ret_type,
1281 params, 2, AC_FUNC_ATTR_READNONE);
1282
1283 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1284 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1285 return res;
1286 }
1287
1288 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1289 LLVMValueRef src0)
1290 {
1291 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1292 }
1293
1294 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1295 LLVMValueRef src0)
1296 {
1297 src0 = ac_to_float(ctx, src0);
1298 return LLVMBuildSExt(ctx->builder,
1299 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1300 ctx->i32, "");
1301 }
1302
1303 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1304 LLVMValueRef src0)
1305 {
1306 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1307 }
1308
1309 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1310 LLVMValueRef src0)
1311 {
1312 return LLVMBuildSExt(ctx->builder,
1313 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1314 ctx->i32, "");
1315 }
1316
1317 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1318 LLVMValueRef src0)
1319 {
1320 LLVMValueRef result;
1321 LLVMValueRef cond = NULL;
1322
1323 src0 = ac_to_float(&ctx->ac, src0);
1324 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1325
1326 if (ctx->options->chip_class >= VI) {
1327 LLVMValueRef args[2];
1328 /* Check if the result is a denormal - and flush to 0 if so. */
1329 args[0] = result;
1330 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1331 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1332 }
1333
1334 /* need to convert back up to f32 */
1335 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1336
1337 if (ctx->options->chip_class >= VI)
1338 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1339 else {
1340 /* for SI/CIK */
1341 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1342 * so compare the result and flush to 0 if it's smaller.
1343 */
1344 LLVMValueRef temp, cond2;
1345 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1346 ctx->ac.f32, result);
1347 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1348 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1349 temp, "");
1350 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1351 temp, ctx->ac.f32_0, "");
1352 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1353 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1354 }
1355 return result;
1356 }
1357
1358 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1359 LLVMValueRef src0, LLVMValueRef src1)
1360 {
1361 LLVMValueRef dst64, result;
1362 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1363 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1364
1365 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1366 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1367 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1368 return result;
1369 }
1370
1371 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1372 LLVMValueRef src0, LLVMValueRef src1)
1373 {
1374 LLVMValueRef dst64, result;
1375 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1376 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1377
1378 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1379 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1380 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1381 return result;
1382 }
1383
1384 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1385 bool is_signed,
1386 const LLVMValueRef srcs[3])
1387 {
1388 LLVMValueRef result;
1389 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1390
1391 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1392 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1393 return result;
1394 }
1395
1396 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1397 LLVMValueRef src0, LLVMValueRef src1,
1398 LLVMValueRef src2, LLVMValueRef src3)
1399 {
1400 LLVMValueRef bfi_args[3], result;
1401
1402 bfi_args[0] = LLVMBuildShl(ctx->builder,
1403 LLVMBuildSub(ctx->builder,
1404 LLVMBuildShl(ctx->builder,
1405 ctx->i32_1,
1406 src3, ""),
1407 ctx->i32_1, ""),
1408 src2, "");
1409 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1410 bfi_args[2] = src0;
1411
1412 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1413
1414 /* Calculate:
1415 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1416 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1417 */
1418 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1419 LLVMBuildAnd(ctx->builder, bfi_args[0],
1420 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1421
1422 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1423 return result;
1424 }
1425
1426 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1427 LLVMValueRef src0)
1428 {
1429 LLVMValueRef comp[2];
1430
1431 src0 = ac_to_float(ctx, src0);
1432 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1433 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1434
1435 return ac_build_cvt_pkrtz_f16(ctx, comp);
1436 }
1437
1438 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1439 LLVMValueRef src0)
1440 {
1441 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1442 LLVMValueRef temps[2], result, val;
1443 int i;
1444
1445 for (i = 0; i < 2; i++) {
1446 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1447 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1448 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1449 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1450 }
1451
1452 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1453 ctx->i32_0, "");
1454 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1455 ctx->i32_1, "");
1456 return result;
1457 }
1458
1459 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1460 nir_op op,
1461 LLVMValueRef src0)
1462 {
1463 unsigned mask;
1464 int idx;
1465 LLVMValueRef result;
1466
1467 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1468 mask = AC_TID_MASK_LEFT;
1469 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1470 mask = AC_TID_MASK_TOP;
1471 else
1472 mask = AC_TID_MASK_TOP_LEFT;
1473
1474 /* for DDX we want to next X pixel, DDY next Y pixel. */
1475 if (op == nir_op_fddx_fine ||
1476 op == nir_op_fddx_coarse ||
1477 op == nir_op_fddx)
1478 idx = 1;
1479 else
1480 idx = 2;
1481
1482 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1483 return result;
1484 }
1485
1486 /*
1487 * this takes an I,J coordinate pair,
1488 * and works out the X and Y derivatives.
1489 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1490 */
1491 static LLVMValueRef emit_ddxy_interp(
1492 struct ac_nir_context *ctx,
1493 LLVMValueRef interp_ij)
1494 {
1495 LLVMValueRef result[4], a;
1496 unsigned i;
1497
1498 for (i = 0; i < 2; i++) {
1499 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1500 LLVMConstInt(ctx->ac.i32, i, false), "");
1501 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1502 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1503 }
1504 return ac_build_gather_values(&ctx->ac, result, 4);
1505 }
1506
1507 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1508 {
1509 LLVMValueRef src[4], result = NULL;
1510 unsigned num_components = instr->dest.dest.ssa.num_components;
1511 unsigned src_components;
1512 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1513
1514 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1515 switch (instr->op) {
1516 case nir_op_vec2:
1517 case nir_op_vec3:
1518 case nir_op_vec4:
1519 src_components = 1;
1520 break;
1521 case nir_op_pack_half_2x16:
1522 src_components = 2;
1523 break;
1524 case nir_op_unpack_half_2x16:
1525 src_components = 1;
1526 break;
1527 default:
1528 src_components = num_components;
1529 break;
1530 }
1531 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1532 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1533
1534 switch (instr->op) {
1535 case nir_op_fmov:
1536 case nir_op_imov:
1537 result = src[0];
1538 break;
1539 case nir_op_fneg:
1540 src[0] = ac_to_float(&ctx->ac, src[0]);
1541 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1542 break;
1543 case nir_op_ineg:
1544 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1545 break;
1546 case nir_op_inot:
1547 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1548 break;
1549 case nir_op_iadd:
1550 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1551 break;
1552 case nir_op_fadd:
1553 src[0] = ac_to_float(&ctx->ac, src[0]);
1554 src[1] = ac_to_float(&ctx->ac, src[1]);
1555 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1556 break;
1557 case nir_op_fsub:
1558 src[0] = ac_to_float(&ctx->ac, src[0]);
1559 src[1] = ac_to_float(&ctx->ac, src[1]);
1560 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1561 break;
1562 case nir_op_isub:
1563 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1564 break;
1565 case nir_op_imul:
1566 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1567 break;
1568 case nir_op_imod:
1569 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1570 break;
1571 case nir_op_umod:
1572 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1573 break;
1574 case nir_op_fmod:
1575 src[0] = ac_to_float(&ctx->ac, src[0]);
1576 src[1] = ac_to_float(&ctx->ac, src[1]);
1577 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1578 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1579 ac_to_float_type(&ctx->ac, def_type), result);
1580 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1581 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1582 break;
1583 case nir_op_frem:
1584 src[0] = ac_to_float(&ctx->ac, src[0]);
1585 src[1] = ac_to_float(&ctx->ac, src[1]);
1586 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1587 break;
1588 case nir_op_irem:
1589 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1590 break;
1591 case nir_op_idiv:
1592 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1593 break;
1594 case nir_op_udiv:
1595 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1596 break;
1597 case nir_op_fmul:
1598 src[0] = ac_to_float(&ctx->ac, src[0]);
1599 src[1] = ac_to_float(&ctx->ac, src[1]);
1600 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1601 break;
1602 case nir_op_fdiv:
1603 src[0] = ac_to_float(&ctx->ac, src[0]);
1604 src[1] = ac_to_float(&ctx->ac, src[1]);
1605 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1606 break;
1607 case nir_op_frcp:
1608 src[0] = ac_to_float(&ctx->ac, src[0]);
1609 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1610 break;
1611 case nir_op_iand:
1612 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1613 break;
1614 case nir_op_ior:
1615 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1616 break;
1617 case nir_op_ixor:
1618 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1619 break;
1620 case nir_op_ishl:
1621 result = LLVMBuildShl(ctx->ac.builder, src[0],
1622 LLVMBuildZExt(ctx->ac.builder, src[1],
1623 LLVMTypeOf(src[0]), ""),
1624 "");
1625 break;
1626 case nir_op_ishr:
1627 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1628 LLVMBuildZExt(ctx->ac.builder, src[1],
1629 LLVMTypeOf(src[0]), ""),
1630 "");
1631 break;
1632 case nir_op_ushr:
1633 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1634 LLVMBuildZExt(ctx->ac.builder, src[1],
1635 LLVMTypeOf(src[0]), ""),
1636 "");
1637 break;
1638 case nir_op_ilt:
1639 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1640 break;
1641 case nir_op_ine:
1642 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1643 break;
1644 case nir_op_ieq:
1645 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1646 break;
1647 case nir_op_ige:
1648 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1649 break;
1650 case nir_op_ult:
1651 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1652 break;
1653 case nir_op_uge:
1654 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1655 break;
1656 case nir_op_feq:
1657 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1658 break;
1659 case nir_op_fne:
1660 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1661 break;
1662 case nir_op_flt:
1663 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1664 break;
1665 case nir_op_fge:
1666 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1667 break;
1668 case nir_op_fabs:
1669 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1670 ac_to_float_type(&ctx->ac, def_type), src[0]);
1671 break;
1672 case nir_op_iabs:
1673 result = emit_iabs(&ctx->ac, src[0]);
1674 break;
1675 case nir_op_imax:
1676 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1677 break;
1678 case nir_op_imin:
1679 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1680 break;
1681 case nir_op_umax:
1682 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1683 break;
1684 case nir_op_umin:
1685 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1686 break;
1687 case nir_op_isign:
1688 result = emit_isign(&ctx->ac, src[0]);
1689 break;
1690 case nir_op_fsign:
1691 src[0] = ac_to_float(&ctx->ac, src[0]);
1692 result = emit_fsign(&ctx->ac, src[0]);
1693 break;
1694 case nir_op_ffloor:
1695 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1696 ac_to_float_type(&ctx->ac, def_type), src[0]);
1697 break;
1698 case nir_op_ftrunc:
1699 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1700 ac_to_float_type(&ctx->ac, def_type), src[0]);
1701 break;
1702 case nir_op_fceil:
1703 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1704 ac_to_float_type(&ctx->ac, def_type), src[0]);
1705 break;
1706 case nir_op_fround_even:
1707 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1708 ac_to_float_type(&ctx->ac, def_type),src[0]);
1709 break;
1710 case nir_op_ffract:
1711 result = emit_ffract(&ctx->ac, src[0]);
1712 break;
1713 case nir_op_fsin:
1714 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1715 ac_to_float_type(&ctx->ac, def_type), src[0]);
1716 break;
1717 case nir_op_fcos:
1718 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1719 ac_to_float_type(&ctx->ac, def_type), src[0]);
1720 break;
1721 case nir_op_fsqrt:
1722 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1723 ac_to_float_type(&ctx->ac, def_type), src[0]);
1724 break;
1725 case nir_op_fexp2:
1726 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1727 ac_to_float_type(&ctx->ac, def_type), src[0]);
1728 break;
1729 case nir_op_flog2:
1730 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1731 ac_to_float_type(&ctx->ac, def_type), src[0]);
1732 break;
1733 case nir_op_frsq:
1734 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1735 ac_to_float_type(&ctx->ac, def_type), src[0]);
1736 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1737 break;
1738 case nir_op_fpow:
1739 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1740 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1741 break;
1742 case nir_op_fmax:
1743 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1744 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1745 if (instr->dest.dest.ssa.bit_size == 32)
1746 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1747 ac_to_float_type(&ctx->ac, def_type),
1748 result);
1749 break;
1750 case nir_op_fmin:
1751 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1752 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1753 if (instr->dest.dest.ssa.bit_size == 32)
1754 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1755 ac_to_float_type(&ctx->ac, def_type),
1756 result);
1757 break;
1758 case nir_op_ffma:
1759 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1760 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1761 break;
1762 case nir_op_ibitfield_extract:
1763 result = emit_bitfield_extract(&ctx->ac, true, src);
1764 break;
1765 case nir_op_ubitfield_extract:
1766 result = emit_bitfield_extract(&ctx->ac, false, src);
1767 break;
1768 case nir_op_bitfield_insert:
1769 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1770 break;
1771 case nir_op_bitfield_reverse:
1772 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1773 break;
1774 case nir_op_bit_count:
1775 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1776 break;
1777 case nir_op_vec2:
1778 case nir_op_vec3:
1779 case nir_op_vec4:
1780 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1781 src[i] = ac_to_integer(&ctx->ac, src[i]);
1782 result = ac_build_gather_values(&ctx->ac, src, num_components);
1783 break;
1784 case nir_op_f2i32:
1785 case nir_op_f2i64:
1786 src[0] = ac_to_float(&ctx->ac, src[0]);
1787 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1788 break;
1789 case nir_op_f2u32:
1790 case nir_op_f2u64:
1791 src[0] = ac_to_float(&ctx->ac, src[0]);
1792 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1793 break;
1794 case nir_op_i2f32:
1795 case nir_op_i2f64:
1796 src[0] = ac_to_integer(&ctx->ac, src[0]);
1797 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1798 break;
1799 case nir_op_u2f32:
1800 case nir_op_u2f64:
1801 src[0] = ac_to_integer(&ctx->ac, src[0]);
1802 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1803 break;
1804 case nir_op_f2f64:
1805 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1806 break;
1807 case nir_op_f2f32:
1808 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1809 break;
1810 case nir_op_u2u32:
1811 case nir_op_u2u64:
1812 src[0] = ac_to_integer(&ctx->ac, src[0]);
1813 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1814 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1815 else
1816 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1817 break;
1818 case nir_op_i2i32:
1819 case nir_op_i2i64:
1820 src[0] = ac_to_integer(&ctx->ac, src[0]);
1821 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1822 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1823 else
1824 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1825 break;
1826 case nir_op_bcsel:
1827 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1828 break;
1829 case nir_op_find_lsb:
1830 src[0] = ac_to_integer(&ctx->ac, src[0]);
1831 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1832 break;
1833 case nir_op_ufind_msb:
1834 src[0] = ac_to_integer(&ctx->ac, src[0]);
1835 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1836 break;
1837 case nir_op_ifind_msb:
1838 src[0] = ac_to_integer(&ctx->ac, src[0]);
1839 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1840 break;
1841 case nir_op_uadd_carry:
1842 src[0] = ac_to_integer(&ctx->ac, src[0]);
1843 src[1] = ac_to_integer(&ctx->ac, src[1]);
1844 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1845 break;
1846 case nir_op_usub_borrow:
1847 src[0] = ac_to_integer(&ctx->ac, src[0]);
1848 src[1] = ac_to_integer(&ctx->ac, src[1]);
1849 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1850 break;
1851 case nir_op_b2f:
1852 result = emit_b2f(&ctx->ac, src[0]);
1853 break;
1854 case nir_op_f2b:
1855 result = emit_f2b(&ctx->ac, src[0]);
1856 break;
1857 case nir_op_b2i:
1858 result = emit_b2i(&ctx->ac, src[0]);
1859 break;
1860 case nir_op_i2b:
1861 src[0] = ac_to_integer(&ctx->ac, src[0]);
1862 result = emit_i2b(&ctx->ac, src[0]);
1863 break;
1864 case nir_op_fquantize2f16:
1865 result = emit_f2f16(ctx->nctx, src[0]);
1866 break;
1867 case nir_op_umul_high:
1868 src[0] = ac_to_integer(&ctx->ac, src[0]);
1869 src[1] = ac_to_integer(&ctx->ac, src[1]);
1870 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1871 break;
1872 case nir_op_imul_high:
1873 src[0] = ac_to_integer(&ctx->ac, src[0]);
1874 src[1] = ac_to_integer(&ctx->ac, src[1]);
1875 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1876 break;
1877 case nir_op_pack_half_2x16:
1878 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1879 break;
1880 case nir_op_unpack_half_2x16:
1881 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1882 break;
1883 case nir_op_fddx:
1884 case nir_op_fddy:
1885 case nir_op_fddx_fine:
1886 case nir_op_fddy_fine:
1887 case nir_op_fddx_coarse:
1888 case nir_op_fddy_coarse:
1889 result = emit_ddxy(ctx, instr->op, src[0]);
1890 break;
1891
1892 case nir_op_unpack_64_2x32_split_x: {
1893 assert(instr->src[0].src.ssa->num_components == 1);
1894 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1895 ctx->ac.v2i32,
1896 "");
1897 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1898 ctx->ac.i32_0, "");
1899 break;
1900 }
1901
1902 case nir_op_unpack_64_2x32_split_y: {
1903 assert(instr->src[0].src.ssa->num_components == 1);
1904 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1905 ctx->ac.v2i32,
1906 "");
1907 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1908 ctx->ac.i32_1, "");
1909 break;
1910 }
1911
1912 case nir_op_pack_64_2x32_split: {
1913 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1914 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1915 src[0], ctx->ac.i32_0, "");
1916 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1917 src[1], ctx->ac.i32_1, "");
1918 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1919 break;
1920 }
1921
1922 default:
1923 fprintf(stderr, "Unknown NIR alu instr: ");
1924 nir_print_instr(&instr->instr, stderr);
1925 fprintf(stderr, "\n");
1926 abort();
1927 }
1928
1929 if (result) {
1930 assert(instr->dest.dest.is_ssa);
1931 result = ac_to_integer(&ctx->ac, result);
1932 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1933 result);
1934 }
1935 }
1936
1937 static void visit_load_const(struct ac_nir_context *ctx,
1938 const nir_load_const_instr *instr)
1939 {
1940 LLVMValueRef values[4], value = NULL;
1941 LLVMTypeRef element_type =
1942 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1943
1944 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1945 switch (instr->def.bit_size) {
1946 case 32:
1947 values[i] = LLVMConstInt(element_type,
1948 instr->value.u32[i], false);
1949 break;
1950 case 64:
1951 values[i] = LLVMConstInt(element_type,
1952 instr->value.u64[i], false);
1953 break;
1954 default:
1955 fprintf(stderr,
1956 "unsupported nir load_const bit_size: %d\n",
1957 instr->def.bit_size);
1958 abort();
1959 }
1960 }
1961 if (instr->def.num_components > 1) {
1962 value = LLVMConstVector(values, instr->def.num_components);
1963 } else
1964 value = values[0];
1965
1966 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1967 }
1968
1969 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1970 LLVMTypeRef type)
1971 {
1972 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1973 return LLVMBuildBitCast(ctx->builder, ptr,
1974 LLVMPointerType(type, addr_space), "");
1975 }
1976
1977 static LLVMValueRef
1978 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1979 {
1980 LLVMValueRef size =
1981 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1982 LLVMConstInt(ctx->ac.i32, 2, false), "");
1983
1984 /* VI only */
1985 if (ctx->ac.chip_class == VI && in_elements) {
1986 /* On VI, the descriptor contains the size in bytes,
1987 * but TXQ must return the size in elements.
1988 * The stride is always non-zero for resources using TXQ.
1989 */
1990 LLVMValueRef stride =
1991 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1992 LLVMConstInt(ctx->ac.i32, 1, false), "");
1993 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1994 LLVMConstInt(ctx->ac.i32, 16, false), "");
1995 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1996 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1997
1998 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1999 }
2000 return size;
2001 }
2002
2003 /**
2004 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2005 * intrinsic names).
2006 */
2007 static void build_int_type_name(
2008 LLVMTypeRef type,
2009 char *buf, unsigned bufsize)
2010 {
2011 assert(bufsize >= 6);
2012
2013 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2014 snprintf(buf, bufsize, "v%ui32",
2015 LLVMGetVectorSize(type));
2016 else
2017 strcpy(buf, "i32");
2018 }
2019
2020 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2021 struct ac_image_args *args,
2022 const nir_tex_instr *instr)
2023 {
2024 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2025 LLVMValueRef coord = args->addr;
2026 LLVMValueRef half_texel[2];
2027 LLVMValueRef compare_cube_wa = NULL;
2028 LLVMValueRef result;
2029 int c;
2030 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2031
2032 //TODO Rect
2033 {
2034 struct ac_image_args txq_args = { 0 };
2035
2036 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2037 txq_args.opcode = ac_image_get_resinfo;
2038 txq_args.dmask = 0xf;
2039 txq_args.addr = ctx->i32_0;
2040 txq_args.resource = args->resource;
2041 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2042
2043 for (c = 0; c < 2; c++) {
2044 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2045 LLVMConstInt(ctx->i32, c, false), "");
2046 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2047 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2048 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2049 LLVMConstReal(ctx->f32, -0.5), "");
2050 }
2051 }
2052
2053 LLVMValueRef orig_coords = args->addr;
2054
2055 for (c = 0; c < 2; c++) {
2056 LLVMValueRef tmp;
2057 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2058 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2059 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2060 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2061 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2062 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2063 }
2064
2065
2066 /*
2067 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2068 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2069 * workaround by sampling using a scaled type and converting.
2070 * This is taken from amdgpu-pro shaders.
2071 */
2072 /* NOTE this produces some ugly code compared to amdgpu-pro,
2073 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2074 * and then reads them back. -pro generates two selects,
2075 * one s_cmp for the descriptor rewriting
2076 * one v_cmp for the coordinate and result changes.
2077 */
2078 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2079 LLVMValueRef tmp, tmp2;
2080
2081 /* workaround 8/8/8/8 uint/sint cube gather bug */
2082 /* first detect it then change to a scaled read and f2i */
2083 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2084 tmp2 = tmp;
2085
2086 /* extract the DATA_FORMAT */
2087 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2088 LLVMConstInt(ctx->i32, 6, false), false);
2089
2090 /* is the DATA_FORMAT == 8_8_8_8 */
2091 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2092
2093 if (stype == GLSL_TYPE_UINT)
2094 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2095 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2096 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2097 else
2098 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2099 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2100 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2101
2102 /* replace the NUM FORMAT in the descriptor */
2103 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2104 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2105
2106 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2107
2108 /* don't modify the coordinates for this case */
2109 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2110 }
2111 args->addr = coord;
2112 result = ac_build_image_opcode(ctx, args);
2113
2114 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2115 LLVMValueRef tmp, tmp2;
2116
2117 /* if the cube workaround is in place, f2i the result. */
2118 for (c = 0; c < 4; c++) {
2119 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2120 if (stype == GLSL_TYPE_UINT)
2121 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2122 else
2123 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2124 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2125 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2126 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2127 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2128 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2129 }
2130 }
2131 return result;
2132 }
2133
2134 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2135 const nir_tex_instr *instr,
2136 bool lod_is_zero,
2137 struct ac_image_args *args)
2138 {
2139 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2140 return ac_build_buffer_load_format(&ctx->ac,
2141 args->resource,
2142 args->addr,
2143 LLVMConstInt(ctx->ac.i32, 0, false),
2144 true);
2145 }
2146
2147 args->opcode = ac_image_sample;
2148 args->compare = instr->is_shadow;
2149
2150 switch (instr->op) {
2151 case nir_texop_txf:
2152 case nir_texop_txf_ms:
2153 case nir_texop_samples_identical:
2154 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2155 args->compare = false;
2156 args->offset = false;
2157 break;
2158 case nir_texop_txb:
2159 args->bias = true;
2160 break;
2161 case nir_texop_txl:
2162 if (lod_is_zero)
2163 args->level_zero = true;
2164 else
2165 args->lod = true;
2166 break;
2167 case nir_texop_txs:
2168 case nir_texop_query_levels:
2169 args->opcode = ac_image_get_resinfo;
2170 break;
2171 case nir_texop_tex:
2172 if (ctx->stage != MESA_SHADER_FRAGMENT)
2173 args->level_zero = true;
2174 break;
2175 case nir_texop_txd:
2176 args->deriv = true;
2177 break;
2178 case nir_texop_tg4:
2179 args->opcode = ac_image_gather4;
2180 args->level_zero = true;
2181 break;
2182 case nir_texop_lod:
2183 args->opcode = ac_image_get_lod;
2184 args->compare = false;
2185 args->offset = false;
2186 break;
2187 default:
2188 break;
2189 }
2190
2191 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2192 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2193 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2194 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2195 }
2196 }
2197 return ac_build_image_opcode(&ctx->ac, args);
2198 }
2199
2200 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2201 nir_intrinsic_instr *instr)
2202 {
2203 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2204 unsigned desc_set = nir_intrinsic_desc_set(instr);
2205 unsigned binding = nir_intrinsic_binding(instr);
2206 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2207 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2208 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2209 unsigned base_offset = layout->binding[binding].offset;
2210 LLVMValueRef offset, stride;
2211
2212 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2213 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2214 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2215 layout->binding[binding].dynamic_offset_offset;
2216 desc_ptr = ctx->push_constants;
2217 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2218 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2219 } else
2220 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2221
2222 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2223 index = LLVMBuildMul(ctx->builder, index, stride, "");
2224 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2225
2226 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2227 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2228 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2229
2230 return desc_ptr;
2231 }
2232
2233 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2234 nir_intrinsic_instr *instr)
2235 {
2236 LLVMValueRef ptr, addr;
2237
2238 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2239 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2240
2241 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2242 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2243
2244 return LLVMBuildLoad(ctx->builder, ptr, "");
2245 }
2246
2247 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2248 const nir_intrinsic_instr *instr)
2249 {
2250 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2251
2252 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2253 }
2254 static void visit_store_ssbo(struct ac_nir_context *ctx,
2255 nir_intrinsic_instr *instr)
2256 {
2257 const char *store_name;
2258 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2259 LLVMTypeRef data_type = ctx->ac.f32;
2260 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2261 int components_32bit = elem_size_mult * instr->num_components;
2262 unsigned writemask = nir_intrinsic_write_mask(instr);
2263 LLVMValueRef base_data, base_offset;
2264 LLVMValueRef params[6];
2265
2266 params[1] = ctx->abi->load_ssbo(ctx->abi,
2267 get_src(ctx, instr->src[1]), true);
2268 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2269 params[4] = ctx->ac.i1false; /* glc */
2270 params[5] = ctx->ac.i1false; /* slc */
2271
2272 if (components_32bit > 1)
2273 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2274
2275 base_data = ac_to_float(&ctx->ac, src_data);
2276 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2277 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2278 data_type, "");
2279 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2280 while (writemask) {
2281 int start, count;
2282 LLVMValueRef data;
2283 LLVMValueRef offset;
2284 LLVMValueRef tmp;
2285 u_bit_scan_consecutive_range(&writemask, &start, &count);
2286
2287 /* Due to an LLVM limitation, split 3-element writes
2288 * into a 2-element and a 1-element write. */
2289 if (count == 3) {
2290 writemask |= 1 << (start + 2);
2291 count = 2;
2292 }
2293
2294 start *= elem_size_mult;
2295 count *= elem_size_mult;
2296
2297 if (count > 4) {
2298 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2299 count = 4;
2300 }
2301
2302 if (count == 4) {
2303 store_name = "llvm.amdgcn.buffer.store.v4f32";
2304 data = base_data;
2305 } else if (count == 2) {
2306 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2307 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2308 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2309 ctx->ac.i32_0, "");
2310
2311 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2312 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2313 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2314 ctx->ac.i32_1, "");
2315 store_name = "llvm.amdgcn.buffer.store.v2f32";
2316
2317 } else {
2318 assert(count == 1);
2319 if (get_llvm_num_components(base_data) > 1)
2320 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2321 LLVMConstInt(ctx->ac.i32, start, false), "");
2322 else
2323 data = base_data;
2324 store_name = "llvm.amdgcn.buffer.store.f32";
2325 }
2326
2327 offset = base_offset;
2328 if (start != 0) {
2329 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2330 }
2331 params[0] = data;
2332 params[3] = offset;
2333 ac_build_intrinsic(&ctx->ac, store_name,
2334 ctx->ac.voidt, params, 6, 0);
2335 }
2336 }
2337
2338 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2339 const nir_intrinsic_instr *instr)
2340 {
2341 const char *name;
2342 LLVMValueRef params[6];
2343 int arg_count = 0;
2344
2345 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2346 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2347 }
2348 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2349 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2350 get_src(ctx, instr->src[0]),
2351 true);
2352 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2353 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2354 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2355
2356 switch (instr->intrinsic) {
2357 case nir_intrinsic_ssbo_atomic_add:
2358 name = "llvm.amdgcn.buffer.atomic.add";
2359 break;
2360 case nir_intrinsic_ssbo_atomic_imin:
2361 name = "llvm.amdgcn.buffer.atomic.smin";
2362 break;
2363 case nir_intrinsic_ssbo_atomic_umin:
2364 name = "llvm.amdgcn.buffer.atomic.umin";
2365 break;
2366 case nir_intrinsic_ssbo_atomic_imax:
2367 name = "llvm.amdgcn.buffer.atomic.smax";
2368 break;
2369 case nir_intrinsic_ssbo_atomic_umax:
2370 name = "llvm.amdgcn.buffer.atomic.umax";
2371 break;
2372 case nir_intrinsic_ssbo_atomic_and:
2373 name = "llvm.amdgcn.buffer.atomic.and";
2374 break;
2375 case nir_intrinsic_ssbo_atomic_or:
2376 name = "llvm.amdgcn.buffer.atomic.or";
2377 break;
2378 case nir_intrinsic_ssbo_atomic_xor:
2379 name = "llvm.amdgcn.buffer.atomic.xor";
2380 break;
2381 case nir_intrinsic_ssbo_atomic_exchange:
2382 name = "llvm.amdgcn.buffer.atomic.swap";
2383 break;
2384 case nir_intrinsic_ssbo_atomic_comp_swap:
2385 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2386 break;
2387 default:
2388 abort();
2389 }
2390
2391 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2392 }
2393
2394 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2395 const nir_intrinsic_instr *instr)
2396 {
2397 LLVMValueRef results[2];
2398 int load_components;
2399 int num_components = instr->num_components;
2400 if (instr->dest.ssa.bit_size == 64)
2401 num_components *= 2;
2402
2403 for (int i = 0; i < num_components; i += load_components) {
2404 load_components = MIN2(num_components - i, 4);
2405 const char *load_name;
2406 LLVMTypeRef data_type = ctx->ac.f32;
2407 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2408 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2409
2410 if (load_components == 3)
2411 data_type = LLVMVectorType(ctx->ac.f32, 4);
2412 else if (load_components > 1)
2413 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2414
2415 if (load_components >= 3)
2416 load_name = "llvm.amdgcn.buffer.load.v4f32";
2417 else if (load_components == 2)
2418 load_name = "llvm.amdgcn.buffer.load.v2f32";
2419 else if (load_components == 1)
2420 load_name = "llvm.amdgcn.buffer.load.f32";
2421 else
2422 unreachable("unhandled number of components");
2423
2424 LLVMValueRef params[] = {
2425 ctx->abi->load_ssbo(ctx->abi,
2426 get_src(ctx, instr->src[0]),
2427 false),
2428 LLVMConstInt(ctx->ac.i32, 0, false),
2429 offset,
2430 ctx->ac.i1false,
2431 ctx->ac.i1false,
2432 };
2433
2434 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2435
2436 }
2437
2438 assume(results[0]);
2439 LLVMValueRef ret = results[0];
2440 if (num_components > 4 || num_components == 3) {
2441 LLVMValueRef masks[] = {
2442 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2443 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2444 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2445 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2446 };
2447
2448 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2449 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2450 results[num_components > 4 ? 1 : 0], swizzle, "");
2451 }
2452
2453 return LLVMBuildBitCast(ctx->ac.builder, ret,
2454 get_def_type(ctx, &instr->dest.ssa), "");
2455 }
2456
2457 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2458 const nir_intrinsic_instr *instr)
2459 {
2460 LLVMValueRef results[8], ret;
2461 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2462 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2463 int num_components = instr->num_components;
2464
2465 if (ctx->abi->load_ubo)
2466 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2467
2468 if (instr->dest.ssa.bit_size == 64)
2469 num_components *= 2;
2470
2471 for (unsigned i = 0; i < num_components; ++i) {
2472 LLVMValueRef params[] = {
2473 rsrc,
2474 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2475 offset, "")
2476 };
2477 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2478 params, 2,
2479 AC_FUNC_ATTR_READNONE |
2480 AC_FUNC_ATTR_LEGACY);
2481 }
2482
2483
2484 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2485 return LLVMBuildBitCast(ctx->ac.builder, ret,
2486 get_def_type(ctx, &instr->dest.ssa), "");
2487 }
2488
2489 static void
2490 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2491 bool vs_in, unsigned *vertex_index_out,
2492 LLVMValueRef *vertex_index_ref,
2493 unsigned *const_out, LLVMValueRef *indir_out)
2494 {
2495 unsigned const_offset = 0;
2496 nir_deref *tail = &deref->deref;
2497 LLVMValueRef offset = NULL;
2498
2499 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2500 tail = tail->child;
2501 nir_deref_array *deref_array = nir_deref_as_array(tail);
2502 if (vertex_index_out)
2503 *vertex_index_out = deref_array->base_offset;
2504
2505 if (vertex_index_ref) {
2506 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2507 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2508 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2509 }
2510 *vertex_index_ref = vtx;
2511 }
2512 }
2513
2514 if (deref->var->data.compact) {
2515 assert(tail->child->deref_type == nir_deref_type_array);
2516 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2517 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2518 /* We always lower indirect dereferences for "compact" array vars. */
2519 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2520
2521 const_offset = deref_array->base_offset;
2522 goto out;
2523 }
2524
2525 while (tail->child != NULL) {
2526 const struct glsl_type *parent_type = tail->type;
2527 tail = tail->child;
2528
2529 if (tail->deref_type == nir_deref_type_array) {
2530 nir_deref_array *deref_array = nir_deref_as_array(tail);
2531 LLVMValueRef index, stride, local_offset;
2532 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2533
2534 const_offset += size * deref_array->base_offset;
2535 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2536 continue;
2537
2538 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2539 index = get_src(ctx, deref_array->indirect);
2540 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2541 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2542
2543 if (offset)
2544 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2545 else
2546 offset = local_offset;
2547 } else if (tail->deref_type == nir_deref_type_struct) {
2548 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2549
2550 for (unsigned i = 0; i < deref_struct->index; i++) {
2551 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2552 const_offset += glsl_count_attribute_slots(ft, vs_in);
2553 }
2554 } else
2555 unreachable("unsupported deref type");
2556
2557 }
2558 out:
2559 if (const_offset && offset)
2560 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2561 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2562 "");
2563
2564 *const_out = const_offset;
2565 *indir_out = offset;
2566 }
2567
2568
2569 /* The offchip buffer layout for TCS->TES is
2570 *
2571 * - attribute 0 of patch 0 vertex 0
2572 * - attribute 0 of patch 0 vertex 1
2573 * - attribute 0 of patch 0 vertex 2
2574 * ...
2575 * - attribute 0 of patch 1 vertex 0
2576 * - attribute 0 of patch 1 vertex 1
2577 * ...
2578 * - attribute 1 of patch 0 vertex 0
2579 * - attribute 1 of patch 0 vertex 1
2580 * ...
2581 * - per patch attribute 0 of patch 0
2582 * - per patch attribute 0 of patch 1
2583 * ...
2584 *
2585 * Note that every attribute has 4 components.
2586 */
2587 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2588 LLVMValueRef vertex_index,
2589 LLVMValueRef param_index)
2590 {
2591 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2592 LLVMValueRef param_stride, constant16;
2593 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2594
2595 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2596 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2597 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2598 num_patches, "");
2599
2600 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2601 if (vertex_index) {
2602 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2603 vertices_per_patch, "");
2604
2605 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2606 vertex_index, "");
2607
2608 param_stride = total_vertices;
2609 } else {
2610 base_addr = rel_patch_id;
2611 param_stride = num_patches;
2612 }
2613
2614 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2615 LLVMBuildMul(ctx->builder, param_index,
2616 param_stride, ""), "");
2617
2618 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2619
2620 if (!vertex_index) {
2621 LLVMValueRef patch_data_offset =
2622 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2623
2624 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2625 patch_data_offset, "");
2626 }
2627 return base_addr;
2628 }
2629
2630 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2631 unsigned param,
2632 unsigned const_index,
2633 bool is_compact,
2634 LLVMValueRef vertex_index,
2635 LLVMValueRef indir_index)
2636 {
2637 LLVMValueRef param_index;
2638
2639 if (indir_index)
2640 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2641 indir_index, "");
2642 else {
2643 if (const_index && !is_compact)
2644 param += const_index;
2645 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2646 }
2647 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2648 }
2649
2650 static void
2651 mark_tess_output(struct nir_to_llvm_context *ctx,
2652 bool is_patch, uint32_t param)
2653
2654 {
2655 if (is_patch) {
2656 ctx->tess_patch_outputs_written |= (1ull << param);
2657 } else
2658 ctx->tess_outputs_written |= (1ull << param);
2659 }
2660
2661 static LLVMValueRef
2662 get_dw_address(struct nir_to_llvm_context *ctx,
2663 LLVMValueRef dw_addr,
2664 unsigned param,
2665 unsigned const_index,
2666 bool compact_const_index,
2667 LLVMValueRef vertex_index,
2668 LLVMValueRef stride,
2669 LLVMValueRef indir_index)
2670
2671 {
2672
2673 if (vertex_index) {
2674 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2675 LLVMBuildMul(ctx->builder,
2676 vertex_index,
2677 stride, ""), "");
2678 }
2679
2680 if (indir_index)
2681 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2682 LLVMBuildMul(ctx->builder, indir_index,
2683 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2684 else if (const_index && !compact_const_index)
2685 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2686 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2687
2688 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2689 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2690
2691 if (const_index && compact_const_index)
2692 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2693 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2694 return dw_addr;
2695 }
2696
2697 static LLVMValueRef
2698 load_tcs_input(struct nir_to_llvm_context *ctx,
2699 nir_intrinsic_instr *instr)
2700 {
2701 LLVMValueRef dw_addr, stride;
2702 unsigned const_index;
2703 LLVMValueRef vertex_index;
2704 LLVMValueRef indir_index;
2705 unsigned param;
2706 LLVMValueRef value[4], result;
2707 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2708 const bool is_compact = instr->variables[0]->var->data.compact;
2709 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2710 get_deref_offset(ctx->nir, instr->variables[0],
2711 false, NULL, per_vertex ? &vertex_index : NULL,
2712 &const_index, &indir_index);
2713
2714 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2715 dw_addr = get_tcs_in_current_patch_offset(ctx);
2716 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2717 indir_index);
2718
2719 unsigned comp = instr->variables[0]->var->data.location_frac;
2720 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2721 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2722 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2723 ctx->ac.i32_1, "");
2724 }
2725 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2726 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2727 return result;
2728 }
2729
2730 static LLVMValueRef
2731 load_tcs_output(struct nir_to_llvm_context *ctx,
2732 nir_intrinsic_instr *instr)
2733 {
2734 LLVMValueRef dw_addr;
2735 LLVMValueRef stride = NULL;
2736 LLVMValueRef value[4], result;
2737 LLVMValueRef vertex_index = NULL;
2738 LLVMValueRef indir_index = NULL;
2739 unsigned const_index = 0;
2740 unsigned param;
2741 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2742 const bool is_compact = instr->variables[0]->var->data.compact;
2743 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2744 get_deref_offset(ctx->nir, instr->variables[0],
2745 false, NULL, per_vertex ? &vertex_index : NULL,
2746 &const_index, &indir_index);
2747
2748 if (!instr->variables[0]->var->data.patch) {
2749 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2750 dw_addr = get_tcs_out_current_patch_offset(ctx);
2751 } else {
2752 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2753 }
2754
2755 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2756 indir_index);
2757
2758 unsigned comp = instr->variables[0]->var->data.location_frac;
2759 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2760 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2761 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2762 ctx->ac.i32_1, "");
2763 }
2764 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2765 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2766 return result;
2767 }
2768
2769 static void
2770 store_tcs_output(struct nir_to_llvm_context *ctx,
2771 nir_intrinsic_instr *instr,
2772 LLVMValueRef src,
2773 unsigned writemask)
2774 {
2775 LLVMValueRef dw_addr;
2776 LLVMValueRef stride = NULL;
2777 LLVMValueRef buf_addr = NULL;
2778 LLVMValueRef vertex_index = NULL;
2779 LLVMValueRef indir_index = NULL;
2780 unsigned const_index = 0;
2781 unsigned param;
2782 const unsigned comp = instr->variables[0]->var->data.location_frac;
2783 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2784 const bool is_compact = instr->variables[0]->var->data.compact;
2785 bool store_lds = true;
2786
2787 if (instr->variables[0]->var->data.patch) {
2788 if (!(ctx->tcs_patch_outputs_read & (1U << instr->variables[0]->var->data.location)))
2789 store_lds = false;
2790 } else {
2791 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2792 store_lds = false;
2793 }
2794 get_deref_offset(ctx->nir, instr->variables[0],
2795 false, NULL, per_vertex ? &vertex_index : NULL,
2796 &const_index, &indir_index);
2797
2798 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2799 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2800 is_compact && const_index > 3) {
2801 const_index -= 3;
2802 param++;
2803 }
2804
2805 if (!instr->variables[0]->var->data.patch) {
2806 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2807 dw_addr = get_tcs_out_current_patch_offset(ctx);
2808 } else {
2809 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2810 }
2811
2812 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2813
2814 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2815 indir_index);
2816 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2817 vertex_index, indir_index);
2818
2819 bool is_tess_factor = false;
2820 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2821 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2822 is_tess_factor = true;
2823
2824 unsigned base = is_compact ? const_index : 0;
2825 for (unsigned chan = 0; chan < 8; chan++) {
2826 if (!(writemask & (1 << chan)))
2827 continue;
2828 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2829
2830 if (store_lds || is_tess_factor)
2831 ac_lds_store(&ctx->ac, dw_addr, value);
2832
2833 if (!is_tess_factor && writemask != 0xF)
2834 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2835 buf_addr, ctx->oc_lds,
2836 4 * (base + chan), 1, 0, true, false);
2837
2838 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2839 ctx->ac.i32_1, "");
2840 }
2841
2842 if (writemask == 0xF) {
2843 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2844 buf_addr, ctx->oc_lds,
2845 (base * 4), 1, 0, true, false);
2846 }
2847 }
2848
2849 static LLVMValueRef
2850 load_tes_input(struct nir_to_llvm_context *ctx,
2851 const nir_intrinsic_instr *instr)
2852 {
2853 LLVMValueRef buf_addr;
2854 LLVMValueRef result;
2855 LLVMValueRef vertex_index = NULL;
2856 LLVMValueRef indir_index = NULL;
2857 unsigned const_index = 0;
2858 unsigned param;
2859 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2860 const bool is_compact = instr->variables[0]->var->data.compact;
2861
2862 get_deref_offset(ctx->nir, instr->variables[0],
2863 false, NULL, per_vertex ? &vertex_index : NULL,
2864 &const_index, &indir_index);
2865 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2866 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2867 is_compact && const_index > 3) {
2868 const_index -= 3;
2869 param++;
2870 }
2871
2872 unsigned comp = instr->variables[0]->var->data.location_frac;
2873 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2874 is_compact, vertex_index, indir_index);
2875
2876 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2877 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2878
2879 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2880 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2881 result = trim_vector(&ctx->ac, result, instr->num_components);
2882 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2883 return result;
2884 }
2885
2886 static LLVMValueRef
2887 load_gs_input(struct ac_shader_abi *abi,
2888 unsigned location,
2889 unsigned driver_location,
2890 unsigned component,
2891 unsigned num_components,
2892 unsigned vertex_index,
2893 unsigned const_index,
2894 LLVMTypeRef type)
2895 {
2896 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2897 LLVMValueRef vtx_offset;
2898 LLVMValueRef args[9];
2899 unsigned param, vtx_offset_param;
2900 LLVMValueRef value[4], result;
2901
2902 vtx_offset_param = vertex_index;
2903 assert(vtx_offset_param < 6);
2904 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2905 LLVMConstInt(ctx->ac.i32, 4, false), "");
2906
2907 param = shader_io_get_unique_index(location);
2908
2909 for (unsigned i = component; i < num_components + component; i++) {
2910 if (ctx->ac.chip_class >= GFX9) {
2911 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2912 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2913 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2914 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2915 } else {
2916 args[0] = ctx->esgs_ring;
2917 args[1] = vtx_offset;
2918 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
2919 args[3] = ctx->ac.i32_0;
2920 args[4] = ctx->ac.i32_1; /* OFFEN */
2921 args[5] = ctx->ac.i32_0; /* IDXEN */
2922 args[6] = ctx->ac.i32_1; /* GLC */
2923 args[7] = ctx->ac.i32_0; /* SLC */
2924 args[8] = ctx->ac.i32_0; /* TFE */
2925
2926 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2927 ctx->ac.i32, args, 9,
2928 AC_FUNC_ATTR_READONLY |
2929 AC_FUNC_ATTR_LEGACY);
2930 }
2931 }
2932 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2933
2934 return result;
2935 }
2936
2937 static LLVMValueRef
2938 build_gep_for_deref(struct ac_nir_context *ctx,
2939 nir_deref_var *deref)
2940 {
2941 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2942 assert(entry->data);
2943 LLVMValueRef val = entry->data;
2944 nir_deref *tail = deref->deref.child;
2945 while (tail != NULL) {
2946 LLVMValueRef offset;
2947 switch (tail->deref_type) {
2948 case nir_deref_type_array: {
2949 nir_deref_array *array = nir_deref_as_array(tail);
2950 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2951 if (array->deref_array_type ==
2952 nir_deref_array_type_indirect) {
2953 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2954 get_src(ctx,
2955 array->indirect),
2956 "");
2957 }
2958 break;
2959 }
2960 case nir_deref_type_struct: {
2961 nir_deref_struct *deref_struct =
2962 nir_deref_as_struct(tail);
2963 offset = LLVMConstInt(ctx->ac.i32,
2964 deref_struct->index, 0);
2965 break;
2966 }
2967 default:
2968 unreachable("bad deref type");
2969 }
2970 val = ac_build_gep0(&ctx->ac, val, offset);
2971 tail = tail->child;
2972 }
2973 return val;
2974 }
2975
2976 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2977 nir_intrinsic_instr *instr)
2978 {
2979 LLVMValueRef values[8];
2980 int idx = instr->variables[0]->var->data.driver_location;
2981 int ve = instr->dest.ssa.num_components;
2982 unsigned comp = instr->variables[0]->var->data.location_frac;
2983 LLVMValueRef indir_index;
2984 LLVMValueRef ret;
2985 unsigned const_index;
2986 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2987 instr->variables[0]->var->data.mode == nir_var_shader_in;
2988 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2989 &const_index, &indir_index);
2990
2991 if (instr->dest.ssa.bit_size == 64)
2992 ve *= 2;
2993
2994 switch (instr->variables[0]->var->data.mode) {
2995 case nir_var_shader_in:
2996 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2997 return load_tcs_input(ctx->nctx, instr);
2998 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2999 return load_tes_input(ctx->nctx, instr);
3000 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3001 LLVMValueRef indir_index;
3002 unsigned const_index, vertex_index;
3003 get_deref_offset(ctx, instr->variables[0],
3004 false, &vertex_index, NULL,
3005 &const_index, &indir_index);
3006 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3007 instr->variables[0]->var->data.driver_location,
3008 instr->variables[0]->var->data.location_frac, ve,
3009 vertex_index, const_index,
3010 nir2llvmtype(ctx, instr->variables[0]->var->type));
3011 }
3012
3013 for (unsigned chan = comp; chan < ve + comp; chan++) {
3014 if (indir_index) {
3015 unsigned count = glsl_count_attribute_slots(
3016 instr->variables[0]->var->type,
3017 ctx->stage == MESA_SHADER_VERTEX);
3018 count -= chan / 4;
3019 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3020 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3021 4, false, true);
3022
3023 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3024 tmp_vec,
3025 indir_index, "");
3026 } else
3027 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3028 }
3029 break;
3030 case nir_var_local:
3031 for (unsigned chan = 0; chan < ve; chan++) {
3032 if (indir_index) {
3033 unsigned count = glsl_count_attribute_slots(
3034 instr->variables[0]->var->type, false);
3035 count -= chan / 4;
3036 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3037 &ctx->ac, ctx->locals + idx + chan, count,
3038 4, true, true);
3039
3040 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3041 tmp_vec,
3042 indir_index, "");
3043 } else {
3044 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3045 }
3046 }
3047 break;
3048 case nir_var_shared: {
3049 LLVMValueRef address = build_gep_for_deref(ctx,
3050 instr->variables[0]);
3051 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3052 return LLVMBuildBitCast(ctx->ac.builder, val,
3053 get_def_type(ctx, &instr->dest.ssa),
3054 "");
3055 }
3056 case nir_var_shader_out:
3057 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3058 return load_tcs_output(ctx->nctx, instr);
3059
3060 for (unsigned chan = comp; chan < ve + comp; chan++) {
3061 if (indir_index) {
3062 unsigned count = glsl_count_attribute_slots(
3063 instr->variables[0]->var->type, false);
3064 count -= chan / 4;
3065 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3066 &ctx->ac, ctx->outputs + idx + chan, count,
3067 4, true, true);
3068
3069 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3070 tmp_vec,
3071 indir_index, "");
3072 } else {
3073 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3074 ctx->outputs[idx + chan + const_index * 4],
3075 "");
3076 }
3077 }
3078 break;
3079 default:
3080 unreachable("unhandle variable mode");
3081 }
3082 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3083 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3084 }
3085
3086 static void
3087 visit_store_var(struct ac_nir_context *ctx,
3088 nir_intrinsic_instr *instr)
3089 {
3090 LLVMValueRef temp_ptr, value;
3091 int idx = instr->variables[0]->var->data.driver_location;
3092 unsigned comp = instr->variables[0]->var->data.location_frac;
3093 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3094 int writemask = instr->const_index[0] << comp;
3095 LLVMValueRef indir_index;
3096 unsigned const_index;
3097 get_deref_offset(ctx, instr->variables[0], false,
3098 NULL, NULL, &const_index, &indir_index);
3099
3100 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3101 int old_writemask = writemask;
3102
3103 src = LLVMBuildBitCast(ctx->ac.builder, src,
3104 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3105 "");
3106
3107 writemask = 0;
3108 for (unsigned chan = 0; chan < 4; chan++) {
3109 if (old_writemask & (1 << chan))
3110 writemask |= 3u << (2 * chan);
3111 }
3112 }
3113
3114 switch (instr->variables[0]->var->data.mode) {
3115 case nir_var_shader_out:
3116
3117 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3118 store_tcs_output(ctx->nctx, instr, src, writemask);
3119 return;
3120 }
3121
3122 for (unsigned chan = 0; chan < 8; chan++) {
3123 int stride = 4;
3124 if (!(writemask & (1 << chan)))
3125 continue;
3126
3127 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3128
3129 if (instr->variables[0]->var->data.compact)
3130 stride = 1;
3131 if (indir_index) {
3132 unsigned count = glsl_count_attribute_slots(
3133 instr->variables[0]->var->type, false);
3134 count -= chan / 4;
3135 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3136 &ctx->ac, ctx->outputs + idx + chan, count,
3137 stride, true, true);
3138
3139 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3140 value, indir_index, "");
3141 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3142 count, stride, tmp_vec);
3143
3144 } else {
3145 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3146
3147 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3148 }
3149 }
3150 break;
3151 case nir_var_local:
3152 for (unsigned chan = 0; chan < 8; chan++) {
3153 if (!(writemask & (1 << chan)))
3154 continue;
3155
3156 value = llvm_extract_elem(&ctx->ac, src, chan);
3157 if (indir_index) {
3158 unsigned count = glsl_count_attribute_slots(
3159 instr->variables[0]->var->type, false);
3160 count -= chan / 4;
3161 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3162 &ctx->ac, ctx->locals + idx + chan, count,
3163 4, true, true);
3164
3165 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3166 value, indir_index, "");
3167 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3168 count, 4, tmp_vec);
3169 } else {
3170 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3171
3172 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3173 }
3174 }
3175 break;
3176 case nir_var_shared: {
3177 int writemask = instr->const_index[0];
3178 LLVMValueRef address = build_gep_for_deref(ctx,
3179 instr->variables[0]);
3180 LLVMValueRef val = get_src(ctx, instr->src[0]);
3181 unsigned components =
3182 glsl_get_vector_elements(
3183 nir_deref_tail(&instr->variables[0]->deref)->type);
3184 if (writemask == (1 << components) - 1) {
3185 val = LLVMBuildBitCast(
3186 ctx->ac.builder, val,
3187 LLVMGetElementType(LLVMTypeOf(address)), "");
3188 LLVMBuildStore(ctx->ac.builder, val, address);
3189 } else {
3190 for (unsigned chan = 0; chan < 4; chan++) {
3191 if (!(writemask & (1 << chan)))
3192 continue;
3193 LLVMValueRef ptr =
3194 LLVMBuildStructGEP(ctx->ac.builder,
3195 address, chan, "");
3196 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3197 chan);
3198 src = LLVMBuildBitCast(
3199 ctx->ac.builder, src,
3200 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3201 LLVMBuildStore(ctx->ac.builder, src, ptr);
3202 }
3203 }
3204 break;
3205 }
3206 default:
3207 break;
3208 }
3209 }
3210
3211 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3212 {
3213 switch (dim) {
3214 case GLSL_SAMPLER_DIM_BUF:
3215 return 1;
3216 case GLSL_SAMPLER_DIM_1D:
3217 return array ? 2 : 1;
3218 case GLSL_SAMPLER_DIM_2D:
3219 return array ? 3 : 2;
3220 case GLSL_SAMPLER_DIM_MS:
3221 return array ? 4 : 3;
3222 case GLSL_SAMPLER_DIM_3D:
3223 case GLSL_SAMPLER_DIM_CUBE:
3224 return 3;
3225 case GLSL_SAMPLER_DIM_RECT:
3226 case GLSL_SAMPLER_DIM_SUBPASS:
3227 return 2;
3228 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3229 return 3;
3230 default:
3231 break;
3232 }
3233 return 0;
3234 }
3235
3236
3237
3238 /* Adjust the sample index according to FMASK.
3239 *
3240 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3241 * which is the identity mapping. Each nibble says which physical sample
3242 * should be fetched to get that sample.
3243 *
3244 * For example, 0x11111100 means there are only 2 samples stored and
3245 * the second sample covers 3/4 of the pixel. When reading samples 0
3246 * and 1, return physical sample 0 (determined by the first two 0s
3247 * in FMASK), otherwise return physical sample 1.
3248 *
3249 * The sample index should be adjusted as follows:
3250 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3251 */
3252 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3253 LLVMValueRef coord_x, LLVMValueRef coord_y,
3254 LLVMValueRef coord_z,
3255 LLVMValueRef sample_index,
3256 LLVMValueRef fmask_desc_ptr)
3257 {
3258 LLVMValueRef fmask_load_address[4];
3259 LLVMValueRef res;
3260
3261 fmask_load_address[0] = coord_x;
3262 fmask_load_address[1] = coord_y;
3263 if (coord_z) {
3264 fmask_load_address[2] = coord_z;
3265 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3266 }
3267
3268 struct ac_image_args args = {0};
3269
3270 args.opcode = ac_image_load;
3271 args.da = coord_z ? true : false;
3272 args.resource = fmask_desc_ptr;
3273 args.dmask = 0xf;
3274 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3275
3276 res = ac_build_image_opcode(ctx, &args);
3277
3278 res = ac_to_integer(ctx, res);
3279 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3280 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3281
3282 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3283 res,
3284 ctx->i32_0, "");
3285
3286 LLVMValueRef sample_index4 =
3287 LLVMBuildMul(ctx->builder, sample_index, four, "");
3288 LLVMValueRef shifted_fmask =
3289 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3290 LLVMValueRef final_sample =
3291 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3292
3293 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3294 * resource descriptor is 0 (invalid),
3295 */
3296 LLVMValueRef fmask_desc =
3297 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3298 ctx->v8i32, "");
3299
3300 LLVMValueRef fmask_word1 =
3301 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3302 ctx->i32_1, "");
3303
3304 LLVMValueRef word1_is_nonzero =
3305 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3306 fmask_word1, ctx->i32_0, "");
3307
3308 /* Replace the MSAA sample index. */
3309 sample_index =
3310 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3311 final_sample, sample_index, "");
3312 return sample_index;
3313 }
3314
3315 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3316 const nir_intrinsic_instr *instr)
3317 {
3318 const struct glsl_type *type = instr->variables[0]->var->type;
3319 if(instr->variables[0]->deref.child)
3320 type = instr->variables[0]->deref.child->type;
3321
3322 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3323 LLVMValueRef coords[4];
3324 LLVMValueRef masks[] = {
3325 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3326 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3327 };
3328 LLVMValueRef res;
3329 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3330
3331 int count;
3332 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3333 bool is_array = glsl_sampler_type_is_array(type);
3334 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3335 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3336 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3337 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3338 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3339 count = image_type_to_components_count(dim, is_array);
3340
3341 if (is_ms) {
3342 LLVMValueRef fmask_load_address[3];
3343 int chan;
3344
3345 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3346 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3347 if (is_array)
3348 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3349 else
3350 fmask_load_address[2] = NULL;
3351 if (add_frag_pos) {
3352 for (chan = 0; chan < 2; ++chan)
3353 fmask_load_address[chan] =
3354 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3355 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3356 ctx->ac.i32, ""), "");
3357 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3358 }
3359 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3360 fmask_load_address[0],
3361 fmask_load_address[1],
3362 fmask_load_address[2],
3363 sample_index,
3364 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3365 }
3366 if (count == 1 && !gfx9_1d) {
3367 if (instr->src[0].ssa->num_components)
3368 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3369 else
3370 res = src0;
3371 } else {
3372 int chan;
3373 if (is_ms)
3374 count--;
3375 for (chan = 0; chan < count; ++chan) {
3376 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3377 }
3378 if (add_frag_pos) {
3379 for (chan = 0; chan < 2; ++chan)
3380 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3381 ctx->ac.i32, ""), "");
3382 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3383 count++;
3384 }
3385
3386 if (gfx9_1d) {
3387 if (is_array) {
3388 coords[2] = coords[1];
3389 coords[1] = ctx->ac.i32_0;
3390 } else
3391 coords[1] = ctx->ac.i32_0;
3392 count++;
3393 }
3394
3395 if (is_ms) {
3396 coords[count] = sample_index;
3397 count++;
3398 }
3399
3400 if (count == 3) {
3401 coords[3] = LLVMGetUndef(ctx->ac.i32);
3402 count = 4;
3403 }
3404 res = ac_build_gather_values(&ctx->ac, coords, count);
3405 }
3406 return res;
3407 }
3408
3409 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3410 const nir_intrinsic_instr *instr)
3411 {
3412 LLVMValueRef params[7];
3413 LLVMValueRef res;
3414 char intrinsic_name[64];
3415 const nir_variable *var = instr->variables[0]->var;
3416 const struct glsl_type *type = var->type;
3417
3418 if(instr->variables[0]->deref.child)
3419 type = instr->variables[0]->deref.child->type;
3420
3421 type = glsl_without_array(type);
3422 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3423 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3424 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3425 ctx->ac.i32_0, ""); /* vindex */
3426 params[2] = ctx->ac.i32_0; /* voffset */
3427 params[3] = ctx->ac.i1false; /* glc */
3428 params[4] = ctx->ac.i1false; /* slc */
3429 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3430 params, 5, 0);
3431
3432 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3433 res = ac_to_integer(&ctx->ac, res);
3434 } else {
3435 bool is_da = glsl_sampler_type_is_array(type) ||
3436 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3437 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3438 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3439 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3440 LLVMValueRef glc = ctx->ac.i1false;
3441 LLVMValueRef slc = ctx->ac.i1false;
3442
3443 params[0] = get_image_coords(ctx, instr);
3444 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3445 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3446 if (HAVE_LLVM <= 0x0309) {
3447 params[3] = ctx->ac.i1false; /* r128 */
3448 params[4] = da;
3449 params[5] = glc;
3450 params[6] = slc;
3451 } else {
3452 LLVMValueRef lwe = ctx->ac.i1false;
3453 params[3] = glc;
3454 params[4] = slc;
3455 params[5] = lwe;
3456 params[6] = da;
3457 }
3458
3459 ac_get_image_intr_name("llvm.amdgcn.image.load",
3460 ctx->ac.v4f32, /* vdata */
3461 LLVMTypeOf(params[0]), /* coords */
3462 LLVMTypeOf(params[1]), /* rsrc */
3463 intrinsic_name, sizeof(intrinsic_name));
3464
3465 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3466 params, 7, AC_FUNC_ATTR_READONLY);
3467 }
3468 return ac_to_integer(&ctx->ac, res);
3469 }
3470
3471 static void visit_image_store(struct ac_nir_context *ctx,
3472 nir_intrinsic_instr *instr)
3473 {
3474 LLVMValueRef params[8];
3475 char intrinsic_name[64];
3476 const nir_variable *var = instr->variables[0]->var;
3477 const struct glsl_type *type = glsl_without_array(var->type);
3478 LLVMValueRef glc = ctx->ac.i1false;
3479 bool force_glc = ctx->ac.chip_class == SI;
3480 if (force_glc)
3481 glc = ctx->ac.i1true;
3482
3483 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3484 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3485 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3486 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3487 ctx->ac.i32_0, ""); /* vindex */
3488 params[3] = ctx->ac.i32_0; /* voffset */
3489 params[4] = glc; /* glc */
3490 params[5] = ctx->ac.i1false; /* slc */
3491 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3492 params, 6, 0);
3493 } else {
3494 bool is_da = glsl_sampler_type_is_array(type) ||
3495 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3496 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3497 LLVMValueRef slc = ctx->ac.i1false;
3498
3499 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3500 params[1] = get_image_coords(ctx, instr); /* coords */
3501 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3502 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3503 if (HAVE_LLVM <= 0x0309) {
3504 params[4] = ctx->ac.i1false; /* r128 */
3505 params[5] = da;
3506 params[6] = glc;
3507 params[7] = slc;
3508 } else {
3509 LLVMValueRef lwe = ctx->ac.i1false;
3510 params[4] = glc;
3511 params[5] = slc;
3512 params[6] = lwe;
3513 params[7] = da;
3514 }
3515
3516 ac_get_image_intr_name("llvm.amdgcn.image.store",
3517 LLVMTypeOf(params[0]), /* vdata */
3518 LLVMTypeOf(params[1]), /* coords */
3519 LLVMTypeOf(params[2]), /* rsrc */
3520 intrinsic_name, sizeof(intrinsic_name));
3521
3522 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3523 params, 8, 0);
3524 }
3525
3526 }
3527
3528 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3529 const nir_intrinsic_instr *instr)
3530 {
3531 LLVMValueRef params[7];
3532 int param_count = 0;
3533 const nir_variable *var = instr->variables[0]->var;
3534
3535 const char *atomic_name;
3536 char intrinsic_name[41];
3537 const struct glsl_type *type = glsl_without_array(var->type);
3538 MAYBE_UNUSED int length;
3539
3540 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3541
3542 switch (instr->intrinsic) {
3543 case nir_intrinsic_image_atomic_add:
3544 atomic_name = "add";
3545 break;
3546 case nir_intrinsic_image_atomic_min:
3547 atomic_name = is_unsigned ? "umin" : "smin";
3548 break;
3549 case nir_intrinsic_image_atomic_max:
3550 atomic_name = is_unsigned ? "umax" : "smax";
3551 break;
3552 case nir_intrinsic_image_atomic_and:
3553 atomic_name = "and";
3554 break;
3555 case nir_intrinsic_image_atomic_or:
3556 atomic_name = "or";
3557 break;
3558 case nir_intrinsic_image_atomic_xor:
3559 atomic_name = "xor";
3560 break;
3561 case nir_intrinsic_image_atomic_exchange:
3562 atomic_name = "swap";
3563 break;
3564 case nir_intrinsic_image_atomic_comp_swap:
3565 atomic_name = "cmpswap";
3566 break;
3567 default:
3568 abort();
3569 }
3570
3571 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3572 params[param_count++] = get_src(ctx, instr->src[3]);
3573 params[param_count++] = get_src(ctx, instr->src[2]);
3574
3575 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3576 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3577 NULL, true, true);
3578 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3579 ctx->ac.i32_0, ""); /* vindex */
3580 params[param_count++] = ctx->ac.i32_0; /* voffset */
3581 params[param_count++] = ctx->ac.i1false; /* slc */
3582
3583 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3584 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3585 } else {
3586 char coords_type[8];
3587
3588 bool da = glsl_sampler_type_is_array(type) ||
3589 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3590
3591 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3592 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3593 NULL, true, true);
3594 params[param_count++] = ctx->ac.i1false; /* r128 */
3595 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3596 params[param_count++] = ctx->ac.i1false; /* slc */
3597
3598 build_int_type_name(LLVMTypeOf(coords),
3599 coords_type, sizeof(coords_type));
3600
3601 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3602 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3603 }
3604
3605 assert(length < sizeof(intrinsic_name));
3606 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3607 }
3608
3609 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3610 const nir_intrinsic_instr *instr)
3611 {
3612 LLVMValueRef res;
3613 const nir_variable *var = instr->variables[0]->var;
3614 const struct glsl_type *type = instr->variables[0]->var->type;
3615 bool da = glsl_sampler_type_is_array(var->type) ||
3616 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3617 if(instr->variables[0]->deref.child)
3618 type = instr->variables[0]->deref.child->type;
3619
3620 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3621 return get_buffer_size(ctx,
3622 get_sampler_desc(ctx, instr->variables[0],
3623 AC_DESC_BUFFER, NULL, true, false), true);
3624
3625 struct ac_image_args args = { 0 };
3626
3627 args.da = da;
3628 args.dmask = 0xf;
3629 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3630 args.opcode = ac_image_get_resinfo;
3631 args.addr = ctx->ac.i32_0;
3632
3633 res = ac_build_image_opcode(&ctx->ac, &args);
3634
3635 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3636
3637 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3638 glsl_sampler_type_is_array(type)) {
3639 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3640 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3641 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3642 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3643 }
3644 if (ctx->ac.chip_class >= GFX9 &&
3645 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3646 glsl_sampler_type_is_array(type)) {
3647 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3648 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3649 ctx->ac.i32_1, "");
3650
3651 }
3652 return res;
3653 }
3654
3655 #define NOOP_WAITCNT 0xf7f
3656 #define LGKM_CNT 0x07f
3657 #define VM_CNT 0xf70
3658
3659 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3660 unsigned simm16)
3661 {
3662 LLVMValueRef args[1] = {
3663 LLVMConstInt(ctx->ac.i32, simm16, false),
3664 };
3665 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3666 ctx->ac.voidt, args, 1, 0);
3667 }
3668
3669 static void emit_membar(struct nir_to_llvm_context *ctx,
3670 const nir_intrinsic_instr *instr)
3671 {
3672 unsigned waitcnt = NOOP_WAITCNT;
3673
3674 switch (instr->intrinsic) {
3675 case nir_intrinsic_memory_barrier:
3676 case nir_intrinsic_group_memory_barrier:
3677 waitcnt &= VM_CNT & LGKM_CNT;
3678 break;
3679 case nir_intrinsic_memory_barrier_atomic_counter:
3680 case nir_intrinsic_memory_barrier_buffer:
3681 case nir_intrinsic_memory_barrier_image:
3682 waitcnt &= VM_CNT;
3683 break;
3684 case nir_intrinsic_memory_barrier_shared:
3685 waitcnt &= LGKM_CNT;
3686 break;
3687 default:
3688 break;
3689 }
3690 if (waitcnt != NOOP_WAITCNT)
3691 emit_waitcnt(ctx, waitcnt);
3692 }
3693
3694 static void emit_barrier(struct nir_to_llvm_context *ctx)
3695 {
3696 /* SI only (thanks to a hw bug workaround):
3697 * The real barrier instruction isn’t needed, because an entire patch
3698 * always fits into a single wave.
3699 */
3700 if (ctx->options->chip_class == SI &&
3701 ctx->stage == MESA_SHADER_TESS_CTRL) {
3702 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3703 return;
3704 }
3705 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3706 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3707 }
3708
3709 static void emit_discard_if(struct ac_nir_context *ctx,
3710 const nir_intrinsic_instr *instr)
3711 {
3712 LLVMValueRef cond;
3713
3714 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3715 get_src(ctx, instr->src[0]),
3716 ctx->ac.i32_0, "");
3717 ac_build_kill_if_false(&ctx->ac, cond);
3718 }
3719
3720 static LLVMValueRef
3721 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3722 {
3723 LLVMValueRef result;
3724 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3725 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3726 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3727
3728 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3729 }
3730
3731 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3732 const nir_intrinsic_instr *instr)
3733 {
3734 LLVMValueRef ptr, result;
3735 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3736 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3737
3738 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3739 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3740 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3741 ptr, src, src1,
3742 LLVMAtomicOrderingSequentiallyConsistent,
3743 LLVMAtomicOrderingSequentiallyConsistent,
3744 false);
3745 } else {
3746 LLVMAtomicRMWBinOp op;
3747 switch (instr->intrinsic) {
3748 case nir_intrinsic_var_atomic_add:
3749 op = LLVMAtomicRMWBinOpAdd;
3750 break;
3751 case nir_intrinsic_var_atomic_umin:
3752 op = LLVMAtomicRMWBinOpUMin;
3753 break;
3754 case nir_intrinsic_var_atomic_umax:
3755 op = LLVMAtomicRMWBinOpUMax;
3756 break;
3757 case nir_intrinsic_var_atomic_imin:
3758 op = LLVMAtomicRMWBinOpMin;
3759 break;
3760 case nir_intrinsic_var_atomic_imax:
3761 op = LLVMAtomicRMWBinOpMax;
3762 break;
3763 case nir_intrinsic_var_atomic_and:
3764 op = LLVMAtomicRMWBinOpAnd;
3765 break;
3766 case nir_intrinsic_var_atomic_or:
3767 op = LLVMAtomicRMWBinOpOr;
3768 break;
3769 case nir_intrinsic_var_atomic_xor:
3770 op = LLVMAtomicRMWBinOpXor;
3771 break;
3772 case nir_intrinsic_var_atomic_exchange:
3773 op = LLVMAtomicRMWBinOpXchg;
3774 break;
3775 default:
3776 return NULL;
3777 }
3778
3779 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3780 LLVMAtomicOrderingSequentiallyConsistent,
3781 false);
3782 }
3783 return result;
3784 }
3785
3786 #define INTERP_CENTER 0
3787 #define INTERP_CENTROID 1
3788 #define INTERP_SAMPLE 2
3789
3790 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3791 enum glsl_interp_mode interp, unsigned location)
3792 {
3793 switch (interp) {
3794 case INTERP_MODE_FLAT:
3795 default:
3796 return NULL;
3797 case INTERP_MODE_SMOOTH:
3798 case INTERP_MODE_NONE:
3799 if (location == INTERP_CENTER)
3800 return ctx->persp_center;
3801 else if (location == INTERP_CENTROID)
3802 return ctx->persp_centroid;
3803 else if (location == INTERP_SAMPLE)
3804 return ctx->persp_sample;
3805 break;
3806 case INTERP_MODE_NOPERSPECTIVE:
3807 if (location == INTERP_CENTER)
3808 return ctx->linear_center;
3809 else if (location == INTERP_CENTROID)
3810 return ctx->linear_centroid;
3811 else if (location == INTERP_SAMPLE)
3812 return ctx->linear_sample;
3813 break;
3814 }
3815 return NULL;
3816 }
3817
3818 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3819 LLVMValueRef sample_id)
3820 {
3821 LLVMValueRef result;
3822 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3823
3824 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3825 const_array(ctx->ac.v2f32, 64), "");
3826
3827 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3828 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3829
3830 return result;
3831 }
3832
3833 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3834 {
3835 LLVMValueRef values[2];
3836
3837 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3838 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3839 return ac_build_gather_values(&ctx->ac, values, 2);
3840 }
3841
3842 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3843 const nir_intrinsic_instr *instr)
3844 {
3845 LLVMValueRef result[4];
3846 LLVMValueRef interp_param, attr_number;
3847 unsigned location;
3848 unsigned chan;
3849 LLVMValueRef src_c0 = NULL;
3850 LLVMValueRef src_c1 = NULL;
3851 LLVMValueRef src0 = NULL;
3852 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3853 switch (instr->intrinsic) {
3854 case nir_intrinsic_interp_var_at_centroid:
3855 location = INTERP_CENTROID;
3856 break;
3857 case nir_intrinsic_interp_var_at_sample:
3858 case nir_intrinsic_interp_var_at_offset:
3859 location = INTERP_CENTER;
3860 src0 = get_src(ctx->nir, instr->src[0]);
3861 break;
3862 default:
3863 break;
3864 }
3865
3866 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3867 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3868 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3869 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3870 LLVMValueRef sample_position;
3871 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3872
3873 /* fetch sample ID */
3874 sample_position = load_sample_position(ctx, src0);
3875
3876 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3877 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3878 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3879 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3880 }
3881 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3882 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3883
3884 if (location == INTERP_CENTER) {
3885 LLVMValueRef ij_out[2];
3886 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3887
3888 /*
3889 * take the I then J parameters, and the DDX/Y for it, and
3890 * calculate the IJ inputs for the interpolator.
3891 * temp1 = ddx * offset/sample.x + I;
3892 * interp_param.I = ddy * offset/sample.y + temp1;
3893 * temp1 = ddx * offset/sample.x + J;
3894 * interp_param.J = ddy * offset/sample.y + temp1;
3895 */
3896 for (unsigned i = 0; i < 2; i++) {
3897 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
3898 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
3899 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3900 ddxy_out, ix_ll, "");
3901 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3902 ddxy_out, iy_ll, "");
3903 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3904 interp_param, ix_ll, "");
3905 LLVMValueRef temp1, temp2;
3906
3907 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3908 ctx->ac.f32, "");
3909
3910 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3911 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3912
3913 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3914 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3915
3916 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3917 temp2, ctx->ac.i32, "");
3918 }
3919 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3920
3921 }
3922
3923 for (chan = 0; chan < 4; chan++) {
3924 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
3925
3926 if (interp_param) {
3927 interp_param = LLVMBuildBitCast(ctx->builder,
3928 interp_param, ctx->ac.v2f32, "");
3929 LLVMValueRef i = LLVMBuildExtractElement(
3930 ctx->builder, interp_param, ctx->ac.i32_0, "");
3931 LLVMValueRef j = LLVMBuildExtractElement(
3932 ctx->builder, interp_param, ctx->ac.i32_1, "");
3933
3934 result[chan] = ac_build_fs_interp(&ctx->ac,
3935 llvm_chan, attr_number,
3936 ctx->prim_mask, i, j);
3937 } else {
3938 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3939 LLVMConstInt(ctx->ac.i32, 2, false),
3940 llvm_chan, attr_number,
3941 ctx->prim_mask);
3942 }
3943 }
3944 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
3945 instr->variables[0]->var->data.location_frac);
3946 }
3947
3948 static void
3949 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
3950 {
3951 LLVMValueRef gs_next_vertex;
3952 LLVMValueRef can_emit;
3953 int idx;
3954 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3955
3956 /* Write vertex attribute values to GSVS ring */
3957 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3958 ctx->gs_next_vertex,
3959 "");
3960
3961 /* If this thread has already emitted the declared maximum number of
3962 * vertices, kill it: excessive vertex emissions are not supposed to
3963 * have any effect, and GS threads have no externally observable
3964 * effects other than emitting vertices.
3965 */
3966 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3967 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
3968 ac_build_kill_if_false(&ctx->ac, can_emit);
3969
3970 /* loop num outputs */
3971 idx = 0;
3972 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3973 LLVMValueRef *out_ptr = &addrs[i * 4];
3974 int length = 4;
3975 int slot = idx;
3976 int slot_inc = 1;
3977
3978 if (!(ctx->output_mask & (1ull << i)))
3979 continue;
3980
3981 if (i == VARYING_SLOT_CLIP_DIST0) {
3982 /* pack clip and cull into a single set of slots */
3983 length = ctx->num_output_clips + ctx->num_output_culls;
3984 if (length > 4)
3985 slot_inc = 2;
3986 }
3987 for (unsigned j = 0; j < length; j++) {
3988 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3989 out_ptr[j], "");
3990 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3991 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3992 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
3993
3994 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
3995
3996 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3997 out_val, 1,
3998 voffset, ctx->gs2vs_offset, 0,
3999 1, 1, true, true);
4000 }
4001 idx += slot_inc;
4002 }
4003
4004 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4005 ctx->ac.i32_1, "");
4006 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4007
4008 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4009 }
4010
4011 static void
4012 visit_end_primitive(struct nir_to_llvm_context *ctx,
4013 const nir_intrinsic_instr *instr)
4014 {
4015 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4016 }
4017
4018 static LLVMValueRef
4019 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4020 const nir_intrinsic_instr *instr)
4021 {
4022 LLVMValueRef coord[4] = {
4023 ctx->tes_u,
4024 ctx->tes_v,
4025 ctx->ac.f32_0,
4026 ctx->ac.f32_0,
4027 };
4028
4029 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4030 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4031 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4032
4033 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4034 return LLVMBuildBitCast(ctx->builder, result,
4035 get_def_type(ctx->nir, &instr->dest.ssa), "");
4036 }
4037
4038 static void visit_intrinsic(struct ac_nir_context *ctx,
4039 nir_intrinsic_instr *instr)
4040 {
4041 LLVMValueRef result = NULL;
4042
4043 switch (instr->intrinsic) {
4044 case nir_intrinsic_load_work_group_id: {
4045 result = ctx->nctx->workgroup_ids;
4046 break;
4047 }
4048 case nir_intrinsic_load_base_vertex: {
4049 result = ctx->abi->base_vertex;
4050 break;
4051 }
4052 case nir_intrinsic_load_vertex_id_zero_base: {
4053 result = ctx->abi->vertex_id;
4054 break;
4055 }
4056 case nir_intrinsic_load_local_invocation_id: {
4057 result = ctx->nctx->local_invocation_ids;
4058 break;
4059 }
4060 case nir_intrinsic_load_base_instance:
4061 result = ctx->abi->start_instance;
4062 break;
4063 case nir_intrinsic_load_draw_id:
4064 result = ctx->abi->draw_id;
4065 break;
4066 case nir_intrinsic_load_view_index:
4067 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4068 break;
4069 case nir_intrinsic_load_invocation_id:
4070 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4071 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4072 else
4073 result = ctx->abi->gs_invocation_id;
4074 break;
4075 case nir_intrinsic_load_primitive_id:
4076 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4077 if (ctx->nctx)
4078 ctx->nctx->shader_info->gs.uses_prim_id = true;
4079 result = ctx->abi->gs_prim_id;
4080 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4081 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4082 result = ctx->nctx->tcs_patch_id;
4083 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4084 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4085 result = ctx->nctx->tes_patch_id;
4086 } else
4087 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4088 break;
4089 case nir_intrinsic_load_sample_id:
4090 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4091 break;
4092 case nir_intrinsic_load_sample_pos:
4093 result = load_sample_pos(ctx);
4094 break;
4095 case nir_intrinsic_load_sample_mask_in:
4096 result = ctx->abi->sample_coverage;
4097 break;
4098 case nir_intrinsic_load_frag_coord: {
4099 LLVMValueRef values[4] = {
4100 ctx->abi->frag_pos[0],
4101 ctx->abi->frag_pos[1],
4102 ctx->abi->frag_pos[2],
4103 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4104 };
4105 result = ac_build_gather_values(&ctx->ac, values, 4);
4106 break;
4107 }
4108 case nir_intrinsic_load_front_face:
4109 result = ctx->abi->front_face;
4110 break;
4111 case nir_intrinsic_load_instance_id:
4112 result = ctx->abi->instance_id;
4113 break;
4114 case nir_intrinsic_load_num_work_groups:
4115 result = ctx->nctx->num_work_groups;
4116 break;
4117 case nir_intrinsic_load_local_invocation_index:
4118 result = visit_load_local_invocation_index(ctx->nctx);
4119 break;
4120 case nir_intrinsic_load_push_constant:
4121 result = visit_load_push_constant(ctx->nctx, instr);
4122 break;
4123 case nir_intrinsic_vulkan_resource_index:
4124 result = visit_vulkan_resource_index(ctx->nctx, instr);
4125 break;
4126 case nir_intrinsic_store_ssbo:
4127 visit_store_ssbo(ctx, instr);
4128 break;
4129 case nir_intrinsic_load_ssbo:
4130 result = visit_load_buffer(ctx, instr);
4131 break;
4132 case nir_intrinsic_ssbo_atomic_add:
4133 case nir_intrinsic_ssbo_atomic_imin:
4134 case nir_intrinsic_ssbo_atomic_umin:
4135 case nir_intrinsic_ssbo_atomic_imax:
4136 case nir_intrinsic_ssbo_atomic_umax:
4137 case nir_intrinsic_ssbo_atomic_and:
4138 case nir_intrinsic_ssbo_atomic_or:
4139 case nir_intrinsic_ssbo_atomic_xor:
4140 case nir_intrinsic_ssbo_atomic_exchange:
4141 case nir_intrinsic_ssbo_atomic_comp_swap:
4142 result = visit_atomic_ssbo(ctx, instr);
4143 break;
4144 case nir_intrinsic_load_ubo:
4145 result = visit_load_ubo_buffer(ctx, instr);
4146 break;
4147 case nir_intrinsic_get_buffer_size:
4148 result = visit_get_buffer_size(ctx, instr);
4149 break;
4150 case nir_intrinsic_load_var:
4151 result = visit_load_var(ctx, instr);
4152 break;
4153 case nir_intrinsic_store_var:
4154 visit_store_var(ctx, instr);
4155 break;
4156 case nir_intrinsic_image_load:
4157 result = visit_image_load(ctx, instr);
4158 break;
4159 case nir_intrinsic_image_store:
4160 visit_image_store(ctx, instr);
4161 break;
4162 case nir_intrinsic_image_atomic_add:
4163 case nir_intrinsic_image_atomic_min:
4164 case nir_intrinsic_image_atomic_max:
4165 case nir_intrinsic_image_atomic_and:
4166 case nir_intrinsic_image_atomic_or:
4167 case nir_intrinsic_image_atomic_xor:
4168 case nir_intrinsic_image_atomic_exchange:
4169 case nir_intrinsic_image_atomic_comp_swap:
4170 result = visit_image_atomic(ctx, instr);
4171 break;
4172 case nir_intrinsic_image_size:
4173 result = visit_image_size(ctx, instr);
4174 break;
4175 case nir_intrinsic_discard:
4176 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4177 LLVMVoidTypeInContext(ctx->ac.context),
4178 NULL, 0, AC_FUNC_ATTR_LEGACY);
4179 break;
4180 case nir_intrinsic_discard_if:
4181 emit_discard_if(ctx, instr);
4182 break;
4183 case nir_intrinsic_memory_barrier:
4184 case nir_intrinsic_group_memory_barrier:
4185 case nir_intrinsic_memory_barrier_atomic_counter:
4186 case nir_intrinsic_memory_barrier_buffer:
4187 case nir_intrinsic_memory_barrier_image:
4188 case nir_intrinsic_memory_barrier_shared:
4189 emit_membar(ctx->nctx, instr);
4190 break;
4191 case nir_intrinsic_barrier:
4192 emit_barrier(ctx->nctx);
4193 break;
4194 case nir_intrinsic_var_atomic_add:
4195 case nir_intrinsic_var_atomic_imin:
4196 case nir_intrinsic_var_atomic_umin:
4197 case nir_intrinsic_var_atomic_imax:
4198 case nir_intrinsic_var_atomic_umax:
4199 case nir_intrinsic_var_atomic_and:
4200 case nir_intrinsic_var_atomic_or:
4201 case nir_intrinsic_var_atomic_xor:
4202 case nir_intrinsic_var_atomic_exchange:
4203 case nir_intrinsic_var_atomic_comp_swap:
4204 result = visit_var_atomic(ctx->nctx, instr);
4205 break;
4206 case nir_intrinsic_interp_var_at_centroid:
4207 case nir_intrinsic_interp_var_at_sample:
4208 case nir_intrinsic_interp_var_at_offset:
4209 result = visit_interp(ctx->nctx, instr);
4210 break;
4211 case nir_intrinsic_emit_vertex:
4212 assert(instr->const_index[0] == 0);
4213 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4214 break;
4215 case nir_intrinsic_end_primitive:
4216 visit_end_primitive(ctx->nctx, instr);
4217 break;
4218 case nir_intrinsic_load_tess_coord:
4219 result = visit_load_tess_coord(ctx->nctx, instr);
4220 break;
4221 case nir_intrinsic_load_patch_vertices_in:
4222 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4223 break;
4224 default:
4225 fprintf(stderr, "Unknown intrinsic: ");
4226 nir_print_instr(&instr->instr, stderr);
4227 fprintf(stderr, "\n");
4228 break;
4229 }
4230 if (result) {
4231 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4232 }
4233 }
4234
4235 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4236 LLVMValueRef buffer_ptr, bool write)
4237 {
4238 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4239
4240 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4241 ctx->shader_info->fs.writes_memory = true;
4242
4243 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4244 }
4245
4246 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4247 {
4248 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4249
4250 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4251 }
4252
4253 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4254 unsigned descriptor_set,
4255 unsigned base_index,
4256 unsigned constant_index,
4257 LLVMValueRef index,
4258 enum ac_descriptor_type desc_type,
4259 bool image, bool write)
4260 {
4261 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4262 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4263 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4264 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4265 unsigned offset = binding->offset;
4266 unsigned stride = binding->size;
4267 unsigned type_size;
4268 LLVMBuilderRef builder = ctx->builder;
4269 LLVMTypeRef type;
4270
4271 assert(base_index < layout->binding_count);
4272
4273 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4274 ctx->shader_info->fs.writes_memory = true;
4275
4276 switch (desc_type) {
4277 case AC_DESC_IMAGE:
4278 type = ctx->ac.v8i32;
4279 type_size = 32;
4280 break;
4281 case AC_DESC_FMASK:
4282 type = ctx->ac.v8i32;
4283 offset += 32;
4284 type_size = 32;
4285 break;
4286 case AC_DESC_SAMPLER:
4287 type = ctx->ac.v4i32;
4288 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4289 offset += 64;
4290
4291 type_size = 16;
4292 break;
4293 case AC_DESC_BUFFER:
4294 type = ctx->ac.v4i32;
4295 type_size = 16;
4296 break;
4297 default:
4298 unreachable("invalid desc_type\n");
4299 }
4300
4301 offset += constant_index * stride;
4302
4303 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4304 (!index || binding->immutable_samplers_equal)) {
4305 if (binding->immutable_samplers_equal)
4306 constant_index = 0;
4307
4308 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4309
4310 LLVMValueRef constants[] = {
4311 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4312 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4313 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4314 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4315 };
4316 return ac_build_gather_values(&ctx->ac, constants, 4);
4317 }
4318
4319 assert(stride % type_size == 0);
4320
4321 if (!index)
4322 index = ctx->ac.i32_0;
4323
4324 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4325
4326 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4327 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4328
4329 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4330 }
4331
4332 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4333 const nir_deref_var *deref,
4334 enum ac_descriptor_type desc_type,
4335 const nir_tex_instr *tex_instr,
4336 bool image, bool write)
4337 {
4338 LLVMValueRef index = NULL;
4339 unsigned constant_index = 0;
4340 unsigned descriptor_set;
4341 unsigned base_index;
4342
4343 if (!deref) {
4344 assert(tex_instr && !image);
4345 descriptor_set = 0;
4346 base_index = tex_instr->sampler_index;
4347 } else {
4348 const nir_deref *tail = &deref->deref;
4349 while (tail->child) {
4350 const nir_deref_array *child = nir_deref_as_array(tail->child);
4351 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4352
4353 if (!array_size)
4354 array_size = 1;
4355
4356 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4357
4358 if (child->deref_array_type == nir_deref_array_type_indirect) {
4359 LLVMValueRef indirect = get_src(ctx, child->indirect);
4360
4361 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4362 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4363
4364 if (!index)
4365 index = indirect;
4366 else
4367 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4368 }
4369
4370 constant_index += child->base_offset * array_size;
4371
4372 tail = &child->deref;
4373 }
4374 descriptor_set = deref->var->data.descriptor_set;
4375 base_index = deref->var->data.binding;
4376 }
4377
4378 return ctx->abi->load_sampler_desc(ctx->abi,
4379 descriptor_set,
4380 base_index,
4381 constant_index, index,
4382 desc_type, image, write);
4383 }
4384
4385 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4386 struct ac_image_args *args,
4387 const nir_tex_instr *instr,
4388 nir_texop op,
4389 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4390 LLVMValueRef *param, unsigned count,
4391 unsigned dmask)
4392 {
4393 unsigned is_rect = 0;
4394 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4395
4396 if (op == nir_texop_lod)
4397 da = false;
4398 /* Pad to power of two vector */
4399 while (count < util_next_power_of_two(count))
4400 param[count++] = LLVMGetUndef(ctx->i32);
4401
4402 if (count > 1)
4403 args->addr = ac_build_gather_values(ctx, param, count);
4404 else
4405 args->addr = param[0];
4406
4407 args->resource = res_ptr;
4408 args->sampler = samp_ptr;
4409
4410 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4411 args->addr = param[0];
4412 return;
4413 }
4414
4415 args->dmask = dmask;
4416 args->unorm = is_rect;
4417 args->da = da;
4418 }
4419
4420 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4421 *
4422 * SI-CI:
4423 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4424 * filtering manually. The driver sets img7 to a mask clearing
4425 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4426 * s_and_b32 samp0, samp0, img7
4427 *
4428 * VI:
4429 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4430 */
4431 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4432 LLVMValueRef res, LLVMValueRef samp)
4433 {
4434 LLVMBuilderRef builder = ctx->ac.builder;
4435 LLVMValueRef img7, samp0;
4436
4437 if (ctx->ac.chip_class >= VI)
4438 return samp;
4439
4440 img7 = LLVMBuildExtractElement(builder, res,
4441 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4442 samp0 = LLVMBuildExtractElement(builder, samp,
4443 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4444 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4445 return LLVMBuildInsertElement(builder, samp, samp0,
4446 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4447 }
4448
4449 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4450 nir_tex_instr *instr,
4451 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4452 LLVMValueRef *fmask_ptr)
4453 {
4454 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4455 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4456 else
4457 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4458 if (samp_ptr) {
4459 if (instr->sampler)
4460 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4461 else
4462 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4463 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4464 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4465 }
4466 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4467 instr->op == nir_texop_samples_identical))
4468 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4469 }
4470
4471 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4472 LLVMValueRef coord)
4473 {
4474 coord = ac_to_float(ctx, coord);
4475 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4476 coord = ac_to_integer(ctx, coord);
4477 return coord;
4478 }
4479
4480 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4481 {
4482 LLVMValueRef result = NULL;
4483 struct ac_image_args args = { 0 };
4484 unsigned dmask = 0xf;
4485 LLVMValueRef address[16];
4486 LLVMValueRef coords[5];
4487 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4488 LLVMValueRef bias = NULL, offsets = NULL;
4489 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4490 LLVMValueRef ddx = NULL, ddy = NULL;
4491 LLVMValueRef derivs[6];
4492 unsigned chan, count = 0;
4493 unsigned const_src = 0, num_deriv_comp = 0;
4494 bool lod_is_zero = false;
4495
4496 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4497
4498 for (unsigned i = 0; i < instr->num_srcs; i++) {
4499 switch (instr->src[i].src_type) {
4500 case nir_tex_src_coord:
4501 coord = get_src(ctx, instr->src[i].src);
4502 break;
4503 case nir_tex_src_projector:
4504 break;
4505 case nir_tex_src_comparator:
4506 comparator = get_src(ctx, instr->src[i].src);
4507 break;
4508 case nir_tex_src_offset:
4509 offsets = get_src(ctx, instr->src[i].src);
4510 const_src = i;
4511 break;
4512 case nir_tex_src_bias:
4513 bias = get_src(ctx, instr->src[i].src);
4514 break;
4515 case nir_tex_src_lod: {
4516 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4517
4518 if (val && val->i32[0] == 0)
4519 lod_is_zero = true;
4520 lod = get_src(ctx, instr->src[i].src);
4521 break;
4522 }
4523 case nir_tex_src_ms_index:
4524 sample_index = get_src(ctx, instr->src[i].src);
4525 break;
4526 case nir_tex_src_ms_mcs:
4527 break;
4528 case nir_tex_src_ddx:
4529 ddx = get_src(ctx, instr->src[i].src);
4530 num_deriv_comp = instr->src[i].src.ssa->num_components;
4531 break;
4532 case nir_tex_src_ddy:
4533 ddy = get_src(ctx, instr->src[i].src);
4534 break;
4535 case nir_tex_src_texture_offset:
4536 case nir_tex_src_sampler_offset:
4537 case nir_tex_src_plane:
4538 default:
4539 break;
4540 }
4541 }
4542
4543 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4544 result = get_buffer_size(ctx, res_ptr, true);
4545 goto write_result;
4546 }
4547
4548 if (instr->op == nir_texop_texture_samples) {
4549 LLVMValueRef res, samples, is_msaa;
4550 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4551 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4552 LLVMConstInt(ctx->ac.i32, 3, false), "");
4553 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4554 LLVMConstInt(ctx->ac.i32, 28, false), "");
4555 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4556 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4557 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4558 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4559
4560 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4561 LLVMConstInt(ctx->ac.i32, 16, false), "");
4562 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4563 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4564 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4565 samples, "");
4566 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4567 ctx->ac.i32_1, "");
4568 result = samples;
4569 goto write_result;
4570 }
4571
4572 if (coord)
4573 for (chan = 0; chan < instr->coord_components; chan++)
4574 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4575
4576 if (offsets && instr->op != nir_texop_txf) {
4577 LLVMValueRef offset[3], pack;
4578 for (chan = 0; chan < 3; ++chan)
4579 offset[chan] = ctx->ac.i32_0;
4580
4581 args.offset = true;
4582 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4583 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4584 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4585 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4586 if (chan)
4587 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4588 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4589 }
4590 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4591 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4592 address[count++] = pack;
4593
4594 }
4595 /* pack LOD bias value */
4596 if (instr->op == nir_texop_txb && bias) {
4597 address[count++] = bias;
4598 }
4599
4600 /* Pack depth comparison value */
4601 if (instr->is_shadow && comparator) {
4602 LLVMValueRef z = ac_to_float(&ctx->ac,
4603 llvm_extract_elem(&ctx->ac, comparator, 0));
4604
4605 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4606 * so the depth comparison value isn't clamped for Z16 and
4607 * Z24 anymore. Do it manually here.
4608 *
4609 * It's unnecessary if the original texture format was
4610 * Z32_FLOAT, but we don't know that here.
4611 */
4612 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4613 z = ac_build_clamp(&ctx->ac, z);
4614
4615 address[count++] = z;
4616 }
4617
4618 /* pack derivatives */
4619 if (ddx || ddy) {
4620 int num_src_deriv_channels, num_dest_deriv_channels;
4621 switch (instr->sampler_dim) {
4622 case GLSL_SAMPLER_DIM_3D:
4623 case GLSL_SAMPLER_DIM_CUBE:
4624 num_deriv_comp = 3;
4625 num_src_deriv_channels = 3;
4626 num_dest_deriv_channels = 3;
4627 break;
4628 case GLSL_SAMPLER_DIM_2D:
4629 default:
4630 num_src_deriv_channels = 2;
4631 num_dest_deriv_channels = 2;
4632 num_deriv_comp = 2;
4633 break;
4634 case GLSL_SAMPLER_DIM_1D:
4635 num_src_deriv_channels = 1;
4636 if (ctx->ac.chip_class >= GFX9) {
4637 num_dest_deriv_channels = 2;
4638 num_deriv_comp = 2;
4639 } else {
4640 num_dest_deriv_channels = 1;
4641 num_deriv_comp = 1;
4642 }
4643 break;
4644 }
4645
4646 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4647 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4648 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4649 }
4650 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4651 derivs[i] = ctx->ac.f32_0;
4652 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4653 }
4654 }
4655
4656 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4657 for (chan = 0; chan < instr->coord_components; chan++)
4658 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4659 if (instr->coord_components == 3)
4660 coords[3] = LLVMGetUndef(ctx->ac.f32);
4661 ac_prepare_cube_coords(&ctx->ac,
4662 instr->op == nir_texop_txd, instr->is_array,
4663 instr->op == nir_texop_lod, coords, derivs);
4664 if (num_deriv_comp)
4665 num_deriv_comp--;
4666 }
4667
4668 if (ddx || ddy) {
4669 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4670 address[count++] = derivs[i];
4671 }
4672
4673 /* Pack texture coordinates */
4674 if (coord) {
4675 address[count++] = coords[0];
4676 if (instr->coord_components > 1) {
4677 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4678 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4679 }
4680 address[count++] = coords[1];
4681 }
4682 if (instr->coord_components > 2) {
4683 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4684 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4685 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4686 instr->op != nir_texop_txf) {
4687 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4688 }
4689 address[count++] = coords[2];
4690 }
4691
4692 if (ctx->ac.chip_class >= GFX9) {
4693 LLVMValueRef filler;
4694 if (instr->op == nir_texop_txf)
4695 filler = ctx->ac.i32_0;
4696 else
4697 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4698
4699 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4700 /* No nir_texop_lod, because it does not take a slice
4701 * even with array textures. */
4702 if (instr->is_array && instr->op != nir_texop_lod ) {
4703 address[count] = address[count - 1];
4704 address[count - 1] = filler;
4705 count++;
4706 } else
4707 address[count++] = filler;
4708 }
4709 }
4710 }
4711
4712 /* Pack LOD */
4713 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4714 instr->op == nir_texop_txf)) {
4715 address[count++] = lod;
4716 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4717 address[count++] = sample_index;
4718 } else if(instr->op == nir_texop_txs) {
4719 count = 0;
4720 if (lod)
4721 address[count++] = lod;
4722 else
4723 address[count++] = ctx->ac.i32_0;
4724 }
4725
4726 for (chan = 0; chan < count; chan++) {
4727 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4728 address[chan], ctx->ac.i32, "");
4729 }
4730
4731 if (instr->op == nir_texop_samples_identical) {
4732 LLVMValueRef txf_address[4];
4733 struct ac_image_args txf_args = { 0 };
4734 unsigned txf_count = count;
4735 memcpy(txf_address, address, sizeof(txf_address));
4736
4737 if (!instr->is_array)
4738 txf_address[2] = ctx->ac.i32_0;
4739 txf_address[3] = ctx->ac.i32_0;
4740
4741 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4742 fmask_ptr, NULL,
4743 txf_address, txf_count, 0xf);
4744
4745 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4746
4747 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4748 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4749 goto write_result;
4750 }
4751
4752 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4753 instr->op != nir_texop_txs) {
4754 unsigned sample_chan = instr->is_array ? 3 : 2;
4755 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4756 address[0],
4757 address[1],
4758 instr->is_array ? address[2] : NULL,
4759 address[sample_chan],
4760 fmask_ptr);
4761 }
4762
4763 if (offsets && instr->op == nir_texop_txf) {
4764 nir_const_value *const_offset =
4765 nir_src_as_const_value(instr->src[const_src].src);
4766 int num_offsets = instr->src[const_src].src.ssa->num_components;
4767 assert(const_offset);
4768 num_offsets = MIN2(num_offsets, instr->coord_components);
4769 if (num_offsets > 2)
4770 address[2] = LLVMBuildAdd(ctx->ac.builder,
4771 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4772 if (num_offsets > 1)
4773 address[1] = LLVMBuildAdd(ctx->ac.builder,
4774 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4775 address[0] = LLVMBuildAdd(ctx->ac.builder,
4776 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4777
4778 }
4779
4780 /* TODO TG4 support */
4781 if (instr->op == nir_texop_tg4) {
4782 if (instr->is_shadow)
4783 dmask = 1;
4784 else
4785 dmask = 1 << instr->component;
4786 }
4787 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4788 res_ptr, samp_ptr, address, count, dmask);
4789
4790 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4791
4792 if (instr->op == nir_texop_query_levels)
4793 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4794 else if (instr->is_shadow && instr->is_new_style_shadow &&
4795 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4796 instr->op != nir_texop_tg4)
4797 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4798 else if (instr->op == nir_texop_txs &&
4799 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4800 instr->is_array) {
4801 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4802 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4803 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4804 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4805 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4806 } else if (ctx->ac.chip_class >= GFX9 &&
4807 instr->op == nir_texop_txs &&
4808 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4809 instr->is_array) {
4810 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4811 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4812 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4813 ctx->ac.i32_1, "");
4814 } else if (instr->dest.ssa.num_components != 4)
4815 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4816
4817 write_result:
4818 if (result) {
4819 assert(instr->dest.is_ssa);
4820 result = ac_to_integer(&ctx->ac, result);
4821 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4822 }
4823 }
4824
4825
4826 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4827 {
4828 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4829 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4830
4831 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4832 _mesa_hash_table_insert(ctx->phis, instr, result);
4833 }
4834
4835 static void visit_post_phi(struct ac_nir_context *ctx,
4836 nir_phi_instr *instr,
4837 LLVMValueRef llvm_phi)
4838 {
4839 nir_foreach_phi_src(src, instr) {
4840 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4841 LLVMValueRef llvm_src = get_src(ctx, src->src);
4842
4843 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4844 }
4845 }
4846
4847 static void phi_post_pass(struct ac_nir_context *ctx)
4848 {
4849 struct hash_entry *entry;
4850 hash_table_foreach(ctx->phis, entry) {
4851 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4852 (LLVMValueRef)entry->data);
4853 }
4854 }
4855
4856
4857 static void visit_ssa_undef(struct ac_nir_context *ctx,
4858 const nir_ssa_undef_instr *instr)
4859 {
4860 unsigned num_components = instr->def.num_components;
4861 LLVMValueRef undef;
4862
4863 if (num_components == 1)
4864 undef = LLVMGetUndef(ctx->ac.i32);
4865 else {
4866 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4867 }
4868 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4869 }
4870
4871 static void visit_jump(struct ac_nir_context *ctx,
4872 const nir_jump_instr *instr)
4873 {
4874 switch (instr->type) {
4875 case nir_jump_break:
4876 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4877 LLVMClearInsertionPosition(ctx->ac.builder);
4878 break;
4879 case nir_jump_continue:
4880 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4881 LLVMClearInsertionPosition(ctx->ac.builder);
4882 break;
4883 default:
4884 fprintf(stderr, "Unknown NIR jump instr: ");
4885 nir_print_instr(&instr->instr, stderr);
4886 fprintf(stderr, "\n");
4887 abort();
4888 }
4889 }
4890
4891 static void visit_cf_list(struct ac_nir_context *ctx,
4892 struct exec_list *list);
4893
4894 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4895 {
4896 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4897 nir_foreach_instr(instr, block)
4898 {
4899 switch (instr->type) {
4900 case nir_instr_type_alu:
4901 visit_alu(ctx, nir_instr_as_alu(instr));
4902 break;
4903 case nir_instr_type_load_const:
4904 visit_load_const(ctx, nir_instr_as_load_const(instr));
4905 break;
4906 case nir_instr_type_intrinsic:
4907 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4908 break;
4909 case nir_instr_type_tex:
4910 visit_tex(ctx, nir_instr_as_tex(instr));
4911 break;
4912 case nir_instr_type_phi:
4913 visit_phi(ctx, nir_instr_as_phi(instr));
4914 break;
4915 case nir_instr_type_ssa_undef:
4916 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4917 break;
4918 case nir_instr_type_jump:
4919 visit_jump(ctx, nir_instr_as_jump(instr));
4920 break;
4921 default:
4922 fprintf(stderr, "Unknown NIR instr type: ");
4923 nir_print_instr(instr, stderr);
4924 fprintf(stderr, "\n");
4925 abort();
4926 }
4927 }
4928
4929 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4930 }
4931
4932 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4933 {
4934 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4935
4936 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4937 LLVMBasicBlockRef merge_block =
4938 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4939 LLVMBasicBlockRef if_block =
4940 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4941 LLVMBasicBlockRef else_block = merge_block;
4942 if (!exec_list_is_empty(&if_stmt->else_list))
4943 else_block = LLVMAppendBasicBlockInContext(
4944 ctx->ac.context, fn, "");
4945
4946 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4947 LLVMConstInt(ctx->ac.i32, 0, false), "");
4948 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4949
4950 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4951 visit_cf_list(ctx, &if_stmt->then_list);
4952 if (LLVMGetInsertBlock(ctx->ac.builder))
4953 LLVMBuildBr(ctx->ac.builder, merge_block);
4954
4955 if (!exec_list_is_empty(&if_stmt->else_list)) {
4956 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4957 visit_cf_list(ctx, &if_stmt->else_list);
4958 if (LLVMGetInsertBlock(ctx->ac.builder))
4959 LLVMBuildBr(ctx->ac.builder, merge_block);
4960 }
4961
4962 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4963 }
4964
4965 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4966 {
4967 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4968 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4969 LLVMBasicBlockRef break_parent = ctx->break_block;
4970
4971 ctx->continue_block =
4972 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4973 ctx->break_block =
4974 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4975
4976 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4977 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4978 visit_cf_list(ctx, &loop->body);
4979
4980 if (LLVMGetInsertBlock(ctx->ac.builder))
4981 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4982 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4983
4984 ctx->continue_block = continue_parent;
4985 ctx->break_block = break_parent;
4986 }
4987
4988 static void visit_cf_list(struct ac_nir_context *ctx,
4989 struct exec_list *list)
4990 {
4991 foreach_list_typed(nir_cf_node, node, node, list)
4992 {
4993 switch (node->type) {
4994 case nir_cf_node_block:
4995 visit_block(ctx, nir_cf_node_as_block(node));
4996 break;
4997
4998 case nir_cf_node_if:
4999 visit_if(ctx, nir_cf_node_as_if(node));
5000 break;
5001
5002 case nir_cf_node_loop:
5003 visit_loop(ctx, nir_cf_node_as_loop(node));
5004 break;
5005
5006 default:
5007 assert(0);
5008 }
5009 }
5010 }
5011
5012 static void
5013 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5014 struct nir_variable *variable)
5015 {
5016 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5017 LLVMValueRef t_offset;
5018 LLVMValueRef t_list;
5019 LLVMValueRef input;
5020 LLVMValueRef buffer_index;
5021 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5022 int idx = variable->data.location;
5023 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5024
5025 variable->data.driver_location = idx * 4;
5026
5027 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5028 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5029 ctx->abi.start_instance, "");
5030 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5031 ctx->shader_info->vs.vgpr_comp_cnt);
5032 } else
5033 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5034 ctx->abi.base_vertex, "");
5035
5036 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5037 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5038
5039 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5040
5041 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5042 buffer_index,
5043 LLVMConstInt(ctx->ac.i32, 0, false),
5044 true);
5045
5046 for (unsigned chan = 0; chan < 4; chan++) {
5047 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5048 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5049 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5050 input, llvm_chan, ""));
5051 }
5052 }
5053 }
5054
5055 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5056 unsigned attr,
5057 LLVMValueRef interp_param,
5058 LLVMValueRef prim_mask,
5059 LLVMValueRef result[4])
5060 {
5061 LLVMValueRef attr_number;
5062 unsigned chan;
5063 LLVMValueRef i, j;
5064 bool interp = interp_param != NULL;
5065
5066 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5067
5068 /* fs.constant returns the param from the middle vertex, so it's not
5069 * really useful for flat shading. It's meant to be used for custom
5070 * interpolation (but the intrinsic can't fetch from the other two
5071 * vertices).
5072 *
5073 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5074 * to do the right thing. The only reason we use fs.constant is that
5075 * fs.interp cannot be used on integers, because they can be equal
5076 * to NaN.
5077 */
5078 if (interp) {
5079 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5080 ctx->ac.v2f32, "");
5081
5082 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5083 ctx->ac.i32_0, "");
5084 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5085 ctx->ac.i32_1, "");
5086 }
5087
5088 for (chan = 0; chan < 4; chan++) {
5089 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5090
5091 if (interp) {
5092 result[chan] = ac_build_fs_interp(&ctx->ac,
5093 llvm_chan,
5094 attr_number,
5095 prim_mask, i, j);
5096 } else {
5097 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5098 LLVMConstInt(ctx->ac.i32, 2, false),
5099 llvm_chan,
5100 attr_number,
5101 prim_mask);
5102 }
5103 }
5104 }
5105
5106 static void
5107 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5108 struct nir_variable *variable)
5109 {
5110 int idx = variable->data.location;
5111 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5112 LLVMValueRef interp;
5113
5114 variable->data.driver_location = idx * 4;
5115 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5116
5117 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5118 unsigned interp_type;
5119 if (variable->data.sample) {
5120 interp_type = INTERP_SAMPLE;
5121 ctx->shader_info->info.ps.force_persample = true;
5122 } else if (variable->data.centroid)
5123 interp_type = INTERP_CENTROID;
5124 else
5125 interp_type = INTERP_CENTER;
5126
5127 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5128 } else
5129 interp = NULL;
5130
5131 for (unsigned i = 0; i < attrib_count; ++i)
5132 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5133
5134 }
5135
5136 static void
5137 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5138 struct nir_shader *nir) {
5139 nir_foreach_variable(variable, &nir->inputs)
5140 handle_vs_input_decl(ctx, variable);
5141 }
5142
5143 static void
5144 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5145 struct nir_shader *nir)
5146 {
5147 if (!ctx->options->key.fs.multisample)
5148 return;
5149
5150 bool uses_center = false;
5151 bool uses_centroid = false;
5152 nir_foreach_variable(variable, &nir->inputs) {
5153 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5154 variable->data.sample)
5155 continue;
5156
5157 if (variable->data.centroid)
5158 uses_centroid = true;
5159 else
5160 uses_center = true;
5161 }
5162
5163 if (uses_center && uses_centroid) {
5164 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5165 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5166 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5167 }
5168 }
5169
5170 static void
5171 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5172 struct nir_shader *nir)
5173 {
5174 prepare_interp_optimize(ctx, nir);
5175
5176 nir_foreach_variable(variable, &nir->inputs)
5177 handle_fs_input_decl(ctx, variable);
5178
5179 unsigned index = 0;
5180
5181 if (ctx->shader_info->info.ps.uses_input_attachments ||
5182 ctx->shader_info->info.needs_multiview_view_index)
5183 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5184
5185 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5186 LLVMValueRef interp_param;
5187 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5188
5189 if (!(ctx->input_mask & (1ull << i)))
5190 continue;
5191
5192 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5193 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5194 interp_param = *inputs;
5195 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5196 inputs);
5197
5198 if (!interp_param)
5199 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5200 ++index;
5201 } else if (i == VARYING_SLOT_POS) {
5202 for(int i = 0; i < 3; ++i)
5203 inputs[i] = ctx->abi.frag_pos[i];
5204
5205 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5206 ctx->abi.frag_pos[3]);
5207 }
5208 }
5209 ctx->shader_info->fs.num_interp = index;
5210 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5211 ctx->shader_info->fs.has_pcoord = true;
5212 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5213 ctx->shader_info->fs.prim_id_input = true;
5214 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5215 ctx->shader_info->fs.layer_input = true;
5216 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5217
5218 if (ctx->shader_info->info.needs_multiview_view_index)
5219 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5220 }
5221
5222 static LLVMValueRef
5223 ac_build_alloca(struct ac_llvm_context *ac,
5224 LLVMTypeRef type,
5225 const char *name)
5226 {
5227 LLVMBuilderRef builder = ac->builder;
5228 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5229 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5230 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5231 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5232 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5233 LLVMValueRef res;
5234
5235 if (first_instr) {
5236 LLVMPositionBuilderBefore(first_builder, first_instr);
5237 } else {
5238 LLVMPositionBuilderAtEnd(first_builder, first_block);
5239 }
5240
5241 res = LLVMBuildAlloca(first_builder, type, name);
5242 LLVMBuildStore(builder, LLVMConstNull(type), res);
5243
5244 LLVMDisposeBuilder(first_builder);
5245
5246 return res;
5247 }
5248
5249 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5250 LLVMTypeRef type,
5251 const char *name)
5252 {
5253 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5254 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5255 return ptr;
5256 }
5257
5258 static void
5259 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5260 struct nir_variable *variable,
5261 struct nir_shader *shader,
5262 gl_shader_stage stage)
5263 {
5264 int idx = variable->data.location + variable->data.index;
5265 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5266 uint64_t mask_attribs;
5267
5268 variable->data.driver_location = idx * 4;
5269
5270 /* tess ctrl has it's own load/store paths for outputs */
5271 if (stage == MESA_SHADER_TESS_CTRL)
5272 return;
5273
5274 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5275 if (stage == MESA_SHADER_VERTEX ||
5276 stage == MESA_SHADER_TESS_EVAL ||
5277 stage == MESA_SHADER_GEOMETRY) {
5278 if (idx == VARYING_SLOT_CLIP_DIST0) {
5279 int length = shader->info.clip_distance_array_size +
5280 shader->info.cull_distance_array_size;
5281 if (stage == MESA_SHADER_VERTEX) {
5282 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5283 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5284 }
5285 if (stage == MESA_SHADER_TESS_EVAL) {
5286 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5287 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5288 }
5289
5290 if (length > 4)
5291 attrib_count = 2;
5292 else
5293 attrib_count = 1;
5294 mask_attribs = 1ull << idx;
5295 }
5296 }
5297
5298 ctx->output_mask |= mask_attribs;
5299 }
5300
5301 static void
5302 handle_shader_output_decl(struct ac_nir_context *ctx,
5303 struct nir_shader *nir,
5304 struct nir_variable *variable)
5305 {
5306 unsigned output_loc = variable->data.driver_location / 4;
5307 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5308
5309 /* tess ctrl has it's own load/store paths for outputs */
5310 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5311 return;
5312
5313 if (ctx->stage == MESA_SHADER_VERTEX ||
5314 ctx->stage == MESA_SHADER_TESS_EVAL ||
5315 ctx->stage == MESA_SHADER_GEOMETRY) {
5316 int idx = variable->data.location + variable->data.index;
5317 if (idx == VARYING_SLOT_CLIP_DIST0) {
5318 int length = nir->info.clip_distance_array_size +
5319 nir->info.cull_distance_array_size;
5320
5321 if (length > 4)
5322 attrib_count = 2;
5323 else
5324 attrib_count = 1;
5325 }
5326 }
5327
5328 for (unsigned i = 0; i < attrib_count; ++i) {
5329 for (unsigned chan = 0; chan < 4; chan++) {
5330 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5331 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5332 }
5333 }
5334 }
5335
5336 static LLVMTypeRef
5337 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5338 enum glsl_base_type type)
5339 {
5340 switch (type) {
5341 case GLSL_TYPE_INT:
5342 case GLSL_TYPE_UINT:
5343 case GLSL_TYPE_BOOL:
5344 case GLSL_TYPE_SUBROUTINE:
5345 return ctx->ac.i32;
5346 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5347 return ctx->ac.f32;
5348 case GLSL_TYPE_INT64:
5349 case GLSL_TYPE_UINT64:
5350 return ctx->ac.i64;
5351 case GLSL_TYPE_DOUBLE:
5352 return ctx->ac.f64;
5353 default:
5354 unreachable("unknown GLSL type");
5355 }
5356 }
5357
5358 static LLVMTypeRef
5359 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5360 const struct glsl_type *type)
5361 {
5362 if (glsl_type_is_scalar(type)) {
5363 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5364 }
5365
5366 if (glsl_type_is_vector(type)) {
5367 return LLVMVectorType(
5368 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5369 glsl_get_vector_elements(type));
5370 }
5371
5372 if (glsl_type_is_matrix(type)) {
5373 return LLVMArrayType(
5374 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5375 glsl_get_matrix_columns(type));
5376 }
5377
5378 if (glsl_type_is_array(type)) {
5379 return LLVMArrayType(
5380 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5381 glsl_get_length(type));
5382 }
5383
5384 assert(glsl_type_is_struct(type));
5385
5386 LLVMTypeRef member_types[glsl_get_length(type)];
5387
5388 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5389 member_types[i] =
5390 glsl_to_llvm_type(ctx,
5391 glsl_get_struct_field(type, i));
5392 }
5393
5394 return LLVMStructTypeInContext(ctx->context, member_types,
5395 glsl_get_length(type), false);
5396 }
5397
5398 static void
5399 setup_locals(struct ac_nir_context *ctx,
5400 struct nir_function *func)
5401 {
5402 int i, j;
5403 ctx->num_locals = 0;
5404 nir_foreach_variable(variable, &func->impl->locals) {
5405 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5406 variable->data.driver_location = ctx->num_locals * 4;
5407 ctx->num_locals += attrib_count;
5408 }
5409 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5410 if (!ctx->locals)
5411 return;
5412
5413 for (i = 0; i < ctx->num_locals; i++) {
5414 for (j = 0; j < 4; j++) {
5415 ctx->locals[i * 4 + j] =
5416 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5417 }
5418 }
5419 }
5420
5421 static void
5422 setup_shared(struct ac_nir_context *ctx,
5423 struct nir_shader *nir)
5424 {
5425 nir_foreach_variable(variable, &nir->shared) {
5426 LLVMValueRef shared =
5427 LLVMAddGlobalInAddressSpace(
5428 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5429 variable->name ? variable->name : "",
5430 LOCAL_ADDR_SPACE);
5431 _mesa_hash_table_insert(ctx->vars, variable, shared);
5432 }
5433 }
5434
5435 static LLVMValueRef
5436 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5437 {
5438 v = ac_to_float(ctx, v);
5439 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5440 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5441 }
5442
5443
5444 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5445 LLVMValueRef src0, LLVMValueRef src1)
5446 {
5447 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5448 LLVMValueRef comp[2];
5449
5450 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5451 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5452 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5453 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5454 }
5455
5456 /* Initialize arguments for the shader export intrinsic */
5457 static void
5458 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5459 LLVMValueRef *values,
5460 unsigned target,
5461 struct ac_export_args *args)
5462 {
5463 /* Default is 0xf. Adjusted below depending on the format. */
5464 args->enabled_channels = 0xf;
5465
5466 /* Specify whether the EXEC mask represents the valid mask */
5467 args->valid_mask = 0;
5468
5469 /* Specify whether this is the last export */
5470 args->done = 0;
5471
5472 /* Specify the target we are exporting */
5473 args->target = target;
5474
5475 args->compr = false;
5476 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5477 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5478 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5479 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5480
5481 if (!values)
5482 return;
5483
5484 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5485 LLVMValueRef val[4];
5486 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5487 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5488 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5489 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5490
5491 switch(col_format) {
5492 case V_028714_SPI_SHADER_ZERO:
5493 args->enabled_channels = 0; /* writemask */
5494 args->target = V_008DFC_SQ_EXP_NULL;
5495 break;
5496
5497 case V_028714_SPI_SHADER_32_R:
5498 args->enabled_channels = 1;
5499 args->out[0] = values[0];
5500 break;
5501
5502 case V_028714_SPI_SHADER_32_GR:
5503 args->enabled_channels = 0x3;
5504 args->out[0] = values[0];
5505 args->out[1] = values[1];
5506 break;
5507
5508 case V_028714_SPI_SHADER_32_AR:
5509 args->enabled_channels = 0x9;
5510 args->out[0] = values[0];
5511 args->out[3] = values[3];
5512 break;
5513
5514 case V_028714_SPI_SHADER_FP16_ABGR:
5515 args->compr = 1;
5516
5517 for (unsigned chan = 0; chan < 2; chan++) {
5518 LLVMValueRef pack_args[2] = {
5519 values[2 * chan],
5520 values[2 * chan + 1]
5521 };
5522 LLVMValueRef packed;
5523
5524 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5525 args->out[chan] = packed;
5526 }
5527 break;
5528
5529 case V_028714_SPI_SHADER_UNORM16_ABGR:
5530 for (unsigned chan = 0; chan < 4; chan++) {
5531 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5532 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5533 LLVMConstReal(ctx->ac.f32, 65535), "");
5534 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5535 LLVMConstReal(ctx->ac.f32, 0.5), "");
5536 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5537 ctx->ac.i32, "");
5538 }
5539
5540 args->compr = 1;
5541 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5542 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5543 break;
5544
5545 case V_028714_SPI_SHADER_SNORM16_ABGR:
5546 for (unsigned chan = 0; chan < 4; chan++) {
5547 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5548 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5549 LLVMConstReal(ctx->ac.f32, 32767), "");
5550
5551 /* If positive, add 0.5, else add -0.5. */
5552 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5553 LLVMBuildSelect(ctx->builder,
5554 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5555 val[chan], ctx->ac.f32_0, ""),
5556 LLVMConstReal(ctx->ac.f32, 0.5),
5557 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5558 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5559 }
5560
5561 args->compr = 1;
5562 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5563 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5564 break;
5565
5566 case V_028714_SPI_SHADER_UINT16_ABGR: {
5567 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5568 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5569 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5570
5571 for (unsigned chan = 0; chan < 4; chan++) {
5572 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5573 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5574 }
5575
5576 args->compr = 1;
5577 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5578 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5579 break;
5580 }
5581
5582 case V_028714_SPI_SHADER_SINT16_ABGR: {
5583 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5584 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5585 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5586 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5587 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5588 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5589
5590 /* Clamp. */
5591 for (unsigned chan = 0; chan < 4; chan++) {
5592 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5593 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5594 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5595 }
5596
5597 args->compr = 1;
5598 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5599 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5600 break;
5601 }
5602
5603 default:
5604 case V_028714_SPI_SHADER_32_ABGR:
5605 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5606 break;
5607 }
5608 } else
5609 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5610
5611 for (unsigned i = 0; i < 4; ++i)
5612 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5613 }
5614
5615 static void
5616 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5617 bool export_prim_id,
5618 struct ac_vs_output_info *outinfo)
5619 {
5620 uint32_t param_count = 0;
5621 unsigned target;
5622 unsigned pos_idx, num_pos_exports = 0;
5623 struct ac_export_args args, pos_args[4] = {};
5624 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5625 int i;
5626
5627 if (ctx->options->key.has_multiview_view_index) {
5628 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5629 if(!*tmp_out) {
5630 for(unsigned i = 0; i < 4; ++i)
5631 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5632 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5633 }
5634
5635 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5636 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5637 }
5638
5639 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5640 sizeof(outinfo->vs_output_param_offset));
5641
5642 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5643 LLVMValueRef slots[8];
5644 unsigned j;
5645
5646 if (outinfo->cull_dist_mask)
5647 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5648
5649 i = VARYING_SLOT_CLIP_DIST0;
5650 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5651 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5652 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5653
5654 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5655 slots[i] = LLVMGetUndef(ctx->ac.f32);
5656
5657 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5658 target = V_008DFC_SQ_EXP_POS + 3;
5659 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5660 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5661 &args, sizeof(args));
5662 }
5663
5664 target = V_008DFC_SQ_EXP_POS + 2;
5665 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5666 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5667 &args, sizeof(args));
5668
5669 }
5670
5671 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5672 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5673 for (unsigned j = 0; j < 4; j++)
5674 pos_values[j] = LLVMBuildLoad(ctx->builder,
5675 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5676 }
5677 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5678
5679 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5680 outinfo->writes_pointsize = true;
5681 psize_value = LLVMBuildLoad(ctx->builder,
5682 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5683 }
5684
5685 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5686 outinfo->writes_layer = true;
5687 layer_value = LLVMBuildLoad(ctx->builder,
5688 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5689 }
5690
5691 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5692 outinfo->writes_viewport_index = true;
5693 viewport_index_value = LLVMBuildLoad(ctx->builder,
5694 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5695 }
5696
5697 if (outinfo->writes_pointsize ||
5698 outinfo->writes_layer ||
5699 outinfo->writes_viewport_index) {
5700 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5701 (outinfo->writes_layer == true ? 4 : 0));
5702 pos_args[1].valid_mask = 0;
5703 pos_args[1].done = 0;
5704 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5705 pos_args[1].compr = 0;
5706 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5707 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5708 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5709 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5710
5711 if (outinfo->writes_pointsize == true)
5712 pos_args[1].out[0] = psize_value;
5713 if (outinfo->writes_layer == true)
5714 pos_args[1].out[2] = layer_value;
5715 if (outinfo->writes_viewport_index == true) {
5716 if (ctx->options->chip_class >= GFX9) {
5717 /* GFX9 has the layer in out.z[10:0] and the viewport
5718 * index in out.z[19:16].
5719 */
5720 LLVMValueRef v = viewport_index_value;
5721 v = ac_to_integer(&ctx->ac, v);
5722 v = LLVMBuildShl(ctx->builder, v,
5723 LLVMConstInt(ctx->ac.i32, 16, false),
5724 "");
5725 v = LLVMBuildOr(ctx->builder, v,
5726 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5727
5728 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5729 pos_args[1].enabled_channels |= 1 << 2;
5730 } else {
5731 pos_args[1].out[3] = viewport_index_value;
5732 pos_args[1].enabled_channels |= 1 << 3;
5733 }
5734 }
5735 }
5736 for (i = 0; i < 4; i++) {
5737 if (pos_args[i].out[0])
5738 num_pos_exports++;
5739 }
5740
5741 pos_idx = 0;
5742 for (i = 0; i < 4; i++) {
5743 if (!pos_args[i].out[0])
5744 continue;
5745
5746 /* Specify the target we are exporting */
5747 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5748 if (pos_idx == num_pos_exports)
5749 pos_args[i].done = 1;
5750 ac_build_export(&ctx->ac, &pos_args[i]);
5751 }
5752
5753 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5754 LLVMValueRef values[4];
5755 if (!(ctx->output_mask & (1ull << i)))
5756 continue;
5757
5758 for (unsigned j = 0; j < 4; j++)
5759 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5760 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5761
5762 if (i == VARYING_SLOT_LAYER) {
5763 target = V_008DFC_SQ_EXP_PARAM + param_count;
5764 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5765 param_count++;
5766 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5767 target = V_008DFC_SQ_EXP_PARAM + param_count;
5768 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5769 param_count++;
5770 } else if (i >= VARYING_SLOT_VAR0) {
5771 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5772 target = V_008DFC_SQ_EXP_PARAM + param_count;
5773 outinfo->vs_output_param_offset[i] = param_count;
5774 param_count++;
5775 } else
5776 continue;
5777
5778 si_llvm_init_export_args(ctx, values, target, &args);
5779
5780 if (target >= V_008DFC_SQ_EXP_POS &&
5781 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5782 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5783 &args, sizeof(args));
5784 } else {
5785 ac_build_export(&ctx->ac, &args);
5786 }
5787 }
5788
5789 if (export_prim_id) {
5790 LLVMValueRef values[4];
5791 target = V_008DFC_SQ_EXP_PARAM + param_count;
5792 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5793 param_count++;
5794
5795 values[0] = ctx->vs_prim_id;
5796 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5797 ctx->shader_info->vs.vgpr_comp_cnt);
5798 for (unsigned j = 1; j < 4; j++)
5799 values[j] = ctx->ac.f32_0;
5800 si_llvm_init_export_args(ctx, values, target, &args);
5801 ac_build_export(&ctx->ac, &args);
5802 outinfo->export_prim_id = true;
5803 }
5804
5805 outinfo->pos_exports = num_pos_exports;
5806 outinfo->param_exports = param_count;
5807 }
5808
5809 static void
5810 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5811 struct ac_es_output_info *outinfo)
5812 {
5813 int j;
5814 uint64_t max_output_written = 0;
5815 LLVMValueRef lds_base = NULL;
5816
5817 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5818 int param_index;
5819 int length = 4;
5820
5821 if (!(ctx->output_mask & (1ull << i)))
5822 continue;
5823
5824 if (i == VARYING_SLOT_CLIP_DIST0)
5825 length = ctx->num_output_clips + ctx->num_output_culls;
5826
5827 param_index = shader_io_get_unique_index(i);
5828
5829 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5830 }
5831
5832 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5833
5834 if (ctx->ac.chip_class >= GFX9) {
5835 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5836 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5837 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5838 LLVMConstInt(ctx->ac.i32, 24, false),
5839 LLVMConstInt(ctx->ac.i32, 4, false), false);
5840 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5841 LLVMBuildMul(ctx->ac.builder, wave_idx,
5842 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5843 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5844 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5845 }
5846
5847 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5848 LLVMValueRef dw_addr;
5849 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5850 int param_index;
5851 int length = 4;
5852
5853 if (!(ctx->output_mask & (1ull << i)))
5854 continue;
5855
5856 if (i == VARYING_SLOT_CLIP_DIST0)
5857 length = ctx->num_output_clips + ctx->num_output_culls;
5858
5859 param_index = shader_io_get_unique_index(i);
5860
5861 if (lds_base) {
5862 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5863 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5864 "");
5865 }
5866 for (j = 0; j < length; j++) {
5867 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5868 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5869
5870 if (ctx->ac.chip_class >= GFX9) {
5871 ac_lds_store(&ctx->ac, dw_addr,
5872 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5873 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5874 } else {
5875 ac_build_buffer_store_dword(&ctx->ac,
5876 ctx->esgs_ring,
5877 out_val, 1,
5878 NULL, ctx->es2gs_offset,
5879 (4 * param_index + j) * 4,
5880 1, 1, true, true);
5881 }
5882 }
5883 }
5884 }
5885
5886 static void
5887 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5888 {
5889 LLVMValueRef vertex_id = ctx->rel_auto_id;
5890 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5891 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5892 vertex_dw_stride, "");
5893
5894 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5895 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5896 int length = 4;
5897
5898 if (!(ctx->output_mask & (1ull << i)))
5899 continue;
5900
5901 if (i == VARYING_SLOT_CLIP_DIST0)
5902 length = ctx->num_output_clips + ctx->num_output_culls;
5903 int param = shader_io_get_unique_index(i);
5904 mark_tess_output(ctx, false, param);
5905 if (length > 4)
5906 mark_tess_output(ctx, false, param + 1);
5907 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5908 LLVMConstInt(ctx->ac.i32, param * 4, false),
5909 "");
5910 for (unsigned j = 0; j < length; j++) {
5911 ac_lds_store(&ctx->ac, dw_addr,
5912 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5913 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5914 }
5915 }
5916 }
5917
5918 struct ac_build_if_state
5919 {
5920 struct nir_to_llvm_context *ctx;
5921 LLVMValueRef condition;
5922 LLVMBasicBlockRef entry_block;
5923 LLVMBasicBlockRef true_block;
5924 LLVMBasicBlockRef false_block;
5925 LLVMBasicBlockRef merge_block;
5926 };
5927
5928 static LLVMBasicBlockRef
5929 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5930 {
5931 LLVMBasicBlockRef current_block;
5932 LLVMBasicBlockRef next_block;
5933 LLVMBasicBlockRef new_block;
5934
5935 /* get current basic block */
5936 current_block = LLVMGetInsertBlock(ctx->builder);
5937
5938 /* chqeck if there's another block after this one */
5939 next_block = LLVMGetNextBasicBlock(current_block);
5940 if (next_block) {
5941 /* insert the new block before the next block */
5942 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5943 }
5944 else {
5945 /* append new block after current block */
5946 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5947 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5948 }
5949 return new_block;
5950 }
5951
5952 static void
5953 ac_nir_build_if(struct ac_build_if_state *ifthen,
5954 struct nir_to_llvm_context *ctx,
5955 LLVMValueRef condition)
5956 {
5957 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5958
5959 memset(ifthen, 0, sizeof *ifthen);
5960 ifthen->ctx = ctx;
5961 ifthen->condition = condition;
5962 ifthen->entry_block = block;
5963
5964 /* create endif/merge basic block for the phi functions */
5965 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5966
5967 /* create/insert true_block before merge_block */
5968 ifthen->true_block =
5969 LLVMInsertBasicBlockInContext(ctx->context,
5970 ifthen->merge_block,
5971 "if-true-block");
5972
5973 /* successive code goes into the true block */
5974 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5975 }
5976
5977 /**
5978 * End a conditional.
5979 */
5980 static void
5981 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5982 {
5983 LLVMBuilderRef builder = ifthen->ctx->builder;
5984
5985 /* Insert branch to the merge block from current block */
5986 LLVMBuildBr(builder, ifthen->merge_block);
5987
5988 /*
5989 * Now patch in the various branch instructions.
5990 */
5991
5992 /* Insert the conditional branch instruction at the end of entry_block */
5993 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5994 if (ifthen->false_block) {
5995 /* we have an else clause */
5996 LLVMBuildCondBr(builder, ifthen->condition,
5997 ifthen->true_block, ifthen->false_block);
5998 }
5999 else {
6000 /* no else clause */
6001 LLVMBuildCondBr(builder, ifthen->condition,
6002 ifthen->true_block, ifthen->merge_block);
6003 }
6004
6005 /* Resume building code at end of the ifthen->merge_block */
6006 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6007 }
6008
6009 static void
6010 write_tess_factors(struct nir_to_llvm_context *ctx)
6011 {
6012 unsigned stride, outer_comps, inner_comps;
6013 struct ac_build_if_state if_ctx, inner_if_ctx;
6014 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6015 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6016 unsigned tess_inner_index, tess_outer_index;
6017 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6018 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6019 int i;
6020 emit_barrier(ctx);
6021
6022 switch (ctx->options->key.tcs.primitive_mode) {
6023 case GL_ISOLINES:
6024 stride = 2;
6025 outer_comps = 2;
6026 inner_comps = 0;
6027 break;
6028 case GL_TRIANGLES:
6029 stride = 4;
6030 outer_comps = 3;
6031 inner_comps = 1;
6032 break;
6033 case GL_QUADS:
6034 stride = 6;
6035 outer_comps = 4;
6036 inner_comps = 2;
6037 break;
6038 default:
6039 return;
6040 }
6041
6042 ac_nir_build_if(&if_ctx, ctx,
6043 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6044 invocation_id, ctx->ac.i32_0, ""));
6045
6046 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6047 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6048
6049 mark_tess_output(ctx, true, tess_inner_index);
6050 mark_tess_output(ctx, true, tess_outer_index);
6051 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6052 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6053 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6054 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6055 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6056
6057 for (i = 0; i < 4; i++) {
6058 inner[i] = LLVMGetUndef(ctx->ac.i32);
6059 outer[i] = LLVMGetUndef(ctx->ac.i32);
6060 }
6061
6062 // LINES reverseal
6063 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6064 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6065 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6066 LLVMConstInt(ctx->ac.i32, 1, false), "");
6067 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6068 } else {
6069 for (i = 0; i < outer_comps; i++) {
6070 outer[i] = out[i] =
6071 ac_lds_load(&ctx->ac, lds_outer);
6072 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6073 LLVMConstInt(ctx->ac.i32, 1, false), "");
6074 }
6075 for (i = 0; i < inner_comps; i++) {
6076 inner[i] = out[outer_comps+i] =
6077 ac_lds_load(&ctx->ac, lds_inner);
6078 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6079 LLVMConstInt(ctx->ac.i32, 1, false), "");
6080 }
6081 }
6082
6083 /* Convert the outputs to vectors for stores. */
6084 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6085 vec1 = NULL;
6086
6087 if (stride > 4)
6088 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6089
6090
6091 buffer = ctx->hs_ring_tess_factor;
6092 tf_base = ctx->tess_factor_offset;
6093 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6094 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6095 unsigned tf_offset = 0;
6096
6097 if (ctx->options->chip_class <= VI) {
6098 ac_nir_build_if(&inner_if_ctx, ctx,
6099 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6100 rel_patch_id, ctx->ac.i32_0, ""));
6101
6102 /* Store the dynamic HS control word. */
6103 ac_build_buffer_store_dword(&ctx->ac, buffer,
6104 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6105 1, ctx->ac.i32_0, tf_base,
6106 0, 1, 0, true, false);
6107 tf_offset += 4;
6108
6109 ac_nir_build_endif(&inner_if_ctx);
6110 }
6111
6112 /* Store the tessellation factors. */
6113 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6114 MIN2(stride, 4), byteoffset, tf_base,
6115 tf_offset, 1, 0, true, false);
6116 if (vec1)
6117 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6118 stride - 4, byteoffset, tf_base,
6119 16 + tf_offset, 1, 0, true, false);
6120
6121 //store to offchip for TES to read - only if TES reads them
6122 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6123 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6124 LLVMValueRef tf_inner_offset;
6125 unsigned param_outer, param_inner;
6126
6127 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6128 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6129 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6130
6131 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6132 util_next_power_of_two(outer_comps));
6133
6134 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6135 outer_comps, tf_outer_offset,
6136 ctx->oc_lds, 0, 1, 0, true, false);
6137 if (inner_comps) {
6138 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6139 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6140 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6141
6142 inner_vec = inner_comps == 1 ? inner[0] :
6143 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6144 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6145 inner_comps, tf_inner_offset,
6146 ctx->oc_lds, 0, 1, 0, true, false);
6147 }
6148 }
6149 ac_nir_build_endif(&if_ctx);
6150 }
6151
6152 static void
6153 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6154 {
6155 write_tess_factors(ctx);
6156 }
6157
6158 static bool
6159 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6160 LLVMValueRef *color, unsigned param, bool is_last,
6161 struct ac_export_args *args)
6162 {
6163 /* Export */
6164 si_llvm_init_export_args(ctx, color, param,
6165 args);
6166
6167 if (is_last) {
6168 args->valid_mask = 1; /* whether the EXEC mask is valid */
6169 args->done = 1; /* DONE bit */
6170 } else if (!args->enabled_channels)
6171 return false; /* unnecessary NULL export */
6172
6173 return true;
6174 }
6175
6176 static void
6177 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6178 LLVMValueRef depth, LLVMValueRef stencil,
6179 LLVMValueRef samplemask)
6180 {
6181 struct ac_export_args args;
6182
6183 args.enabled_channels = 0;
6184 args.valid_mask = 1;
6185 args.done = 1;
6186 args.target = V_008DFC_SQ_EXP_MRTZ;
6187 args.compr = false;
6188
6189 args.out[0] = LLVMGetUndef(ctx->ac.f32); /* R, depth */
6190 args.out[1] = LLVMGetUndef(ctx->ac.f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6191 args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */
6192 args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */
6193
6194 if (depth) {
6195 args.out[0] = depth;
6196 args.enabled_channels |= 0x1;
6197 }
6198
6199 if (stencil) {
6200 args.out[1] = stencil;
6201 args.enabled_channels |= 0x2;
6202 }
6203
6204 if (samplemask) {
6205 args.out[2] = samplemask;
6206 args.enabled_channels |= 0x4;
6207 }
6208
6209 /* SI (except OLAND and HAINAN) has a bug that it only looks
6210 * at the X writemask component. */
6211 if (ctx->options->chip_class == SI &&
6212 ctx->options->family != CHIP_OLAND &&
6213 ctx->options->family != CHIP_HAINAN)
6214 args.enabled_channels |= 0x1;
6215
6216 ac_build_export(&ctx->ac, &args);
6217 }
6218
6219 static void
6220 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6221 {
6222 unsigned index = 0;
6223 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6224 struct ac_export_args color_args[8];
6225
6226 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6227 LLVMValueRef values[4];
6228
6229 if (!(ctx->output_mask & (1ull << i)))
6230 continue;
6231
6232 if (i == FRAG_RESULT_DEPTH) {
6233 ctx->shader_info->fs.writes_z = true;
6234 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6235 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6236 } else if (i == FRAG_RESULT_STENCIL) {
6237 ctx->shader_info->fs.writes_stencil = true;
6238 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6239 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6240 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6241 ctx->shader_info->fs.writes_sample_mask = true;
6242 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6243 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6244 } else {
6245 bool last = false;
6246 for (unsigned j = 0; j < 4; j++)
6247 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6248 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6249
6250 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6251 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6252
6253 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6254 if (ret)
6255 index++;
6256 }
6257 }
6258
6259 for (unsigned i = 0; i < index; i++)
6260 ac_build_export(&ctx->ac, &color_args[i]);
6261 if (depth || stencil || samplemask)
6262 si_export_mrt_z(ctx, depth, stencil, samplemask);
6263 else if (!index) {
6264 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6265 ac_build_export(&ctx->ac, &color_args[0]);
6266 }
6267
6268 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6269 }
6270
6271 static void
6272 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6273 {
6274 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6275 }
6276
6277 static void
6278 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6279 LLVMValueRef *addrs)
6280 {
6281 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6282
6283 switch (ctx->stage) {
6284 case MESA_SHADER_VERTEX:
6285 if (ctx->options->key.vs.as_ls)
6286 handle_ls_outputs_post(ctx);
6287 else if (ctx->options->key.vs.as_es)
6288 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6289 else
6290 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6291 &ctx->shader_info->vs.outinfo);
6292 break;
6293 case MESA_SHADER_FRAGMENT:
6294 handle_fs_outputs_post(ctx);
6295 break;
6296 case MESA_SHADER_GEOMETRY:
6297 emit_gs_epilogue(ctx);
6298 break;
6299 case MESA_SHADER_TESS_CTRL:
6300 handle_tcs_outputs_post(ctx);
6301 break;
6302 case MESA_SHADER_TESS_EVAL:
6303 if (ctx->options->key.tes.as_es)
6304 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6305 else
6306 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6307 &ctx->shader_info->tes.outinfo);
6308 break;
6309 default:
6310 break;
6311 }
6312 }
6313
6314 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6315 {
6316 LLVMPassManagerRef passmgr;
6317 /* Create the pass manager */
6318 passmgr = LLVMCreateFunctionPassManagerForModule(
6319 ctx->module);
6320
6321 /* This pass should eliminate all the load and store instructions */
6322 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6323
6324 /* Add some optimization passes */
6325 LLVMAddScalarReplAggregatesPass(passmgr);
6326 LLVMAddLICMPass(passmgr);
6327 LLVMAddAggressiveDCEPass(passmgr);
6328 LLVMAddCFGSimplificationPass(passmgr);
6329 LLVMAddInstructionCombiningPass(passmgr);
6330
6331 /* Run the pass */
6332 LLVMInitializeFunctionPassManager(passmgr);
6333 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6334 LLVMFinalizeFunctionPassManager(passmgr);
6335
6336 LLVMDisposeBuilder(ctx->builder);
6337 LLVMDisposePassManager(passmgr);
6338 }
6339
6340 static void
6341 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6342 {
6343 struct ac_vs_output_info *outinfo;
6344
6345 switch (ctx->stage) {
6346 case MESA_SHADER_FRAGMENT:
6347 case MESA_SHADER_COMPUTE:
6348 case MESA_SHADER_TESS_CTRL:
6349 case MESA_SHADER_GEOMETRY:
6350 return;
6351 case MESA_SHADER_VERTEX:
6352 if (ctx->options->key.vs.as_ls ||
6353 ctx->options->key.vs.as_es)
6354 return;
6355 outinfo = &ctx->shader_info->vs.outinfo;
6356 break;
6357 case MESA_SHADER_TESS_EVAL:
6358 if (ctx->options->key.vs.as_es)
6359 return;
6360 outinfo = &ctx->shader_info->tes.outinfo;
6361 break;
6362 default:
6363 unreachable("Unhandled shader type");
6364 }
6365
6366 ac_optimize_vs_outputs(&ctx->ac,
6367 ctx->main_function,
6368 outinfo->vs_output_param_offset,
6369 VARYING_SLOT_MAX,
6370 &outinfo->param_exports);
6371 }
6372
6373 static void
6374 ac_setup_rings(struct nir_to_llvm_context *ctx)
6375 {
6376 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6377 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6378 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6379 }
6380
6381 if (ctx->is_gs_copy_shader) {
6382 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6383 }
6384 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6385 LLVMValueRef tmp;
6386 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6387 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6388
6389 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6390
6391 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6392 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6393 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6394 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6395 }
6396
6397 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6398 ctx->stage == MESA_SHADER_TESS_EVAL) {
6399 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6400 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6401 }
6402 }
6403
6404 static unsigned
6405 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6406 const struct nir_shader *nir)
6407 {
6408 switch (nir->info.stage) {
6409 case MESA_SHADER_TESS_CTRL:
6410 return chip_class >= CIK ? 128 : 64;
6411 case MESA_SHADER_GEOMETRY:
6412 return chip_class >= GFX9 ? 128 : 64;
6413 case MESA_SHADER_COMPUTE:
6414 break;
6415 default:
6416 return 0;
6417 }
6418
6419 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6420 nir->info.cs.local_size[1] *
6421 nir->info.cs.local_size[2];
6422 return max_workgroup_size;
6423 }
6424
6425 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6426 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6427 {
6428 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6429 LLVMConstInt(ctx->ac.i32, 8, false),
6430 LLVMConstInt(ctx->ac.i32, 8, false), false);
6431 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6432 LLVMConstInt(ctx->ac.i32, 0, false), "");
6433 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6434 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6435 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6436 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6437 }
6438
6439 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6440 {
6441 for(int i = 5; i >= 0; --i) {
6442 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6443 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6444 LLVMConstInt(ctx->ac.i32, 16, false), false);
6445 }
6446
6447 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6448 LLVMConstInt(ctx->ac.i32, 16, false),
6449 LLVMConstInt(ctx->ac.i32, 8, false), false);
6450 }
6451
6452 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6453 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6454 {
6455 struct ac_nir_context ctx = {};
6456 struct nir_function *func;
6457
6458 ctx.ac = *ac;
6459 ctx.abi = abi;
6460
6461 ctx.nctx = nctx;
6462 if (nctx)
6463 nctx->nir = &ctx;
6464
6465 ctx.stage = nir->info.stage;
6466
6467 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6468
6469 nir_foreach_variable(variable, &nir->outputs)
6470 handle_shader_output_decl(&ctx, nir, variable);
6471
6472 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6473 _mesa_key_pointer_equal);
6474 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6475 _mesa_key_pointer_equal);
6476 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6477 _mesa_key_pointer_equal);
6478
6479 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6480
6481 setup_locals(&ctx, func);
6482
6483 if (nir->info.stage == MESA_SHADER_COMPUTE)
6484 setup_shared(&ctx, nir);
6485
6486 visit_cf_list(&ctx, &func->impl->body);
6487 phi_post_pass(&ctx);
6488
6489 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6490 ctx.outputs);
6491
6492 free(ctx.locals);
6493 ralloc_free(ctx.defs);
6494 ralloc_free(ctx.phis);
6495 ralloc_free(ctx.vars);
6496
6497 if (nctx)
6498 nctx->nir = NULL;
6499 }
6500
6501 static
6502 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6503 struct nir_shader *const *shaders,
6504 int shader_count,
6505 struct ac_shader_variant_info *shader_info,
6506 const struct ac_nir_compiler_options *options)
6507 {
6508 struct nir_to_llvm_context ctx = {0};
6509 unsigned i;
6510 ctx.options = options;
6511 ctx.shader_info = shader_info;
6512 ctx.context = LLVMContextCreate();
6513 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6514
6515 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6516 ctx.ac.module = ctx.module;
6517 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6518
6519 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6520 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6521 LLVMSetDataLayout(ctx.module, data_layout_str);
6522 LLVMDisposeTargetData(data_layout);
6523 LLVMDisposeMessage(data_layout_str);
6524
6525 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6526 ctx.ac.builder = ctx.builder;
6527
6528 memset(shader_info, 0, sizeof(*shader_info));
6529
6530 for(int i = 0; i < shader_count; ++i)
6531 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6532
6533 for (i = 0; i < AC_UD_MAX_SETS; i++)
6534 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6535 for (i = 0; i < AC_UD_MAX_UD; i++)
6536 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6537
6538 ctx.max_workgroup_size = 0;
6539 for (int i = 0; i < shader_count; ++i) {
6540 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6541 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6542 shaders[i]));
6543 }
6544
6545 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6546 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6547
6548 ctx.abi.inputs = &ctx.inputs[0];
6549 ctx.abi.emit_outputs = handle_shader_outputs_post;
6550 ctx.abi.emit_vertex = visit_emit_vertex;
6551 ctx.abi.load_ubo = radv_load_ubo;
6552 ctx.abi.load_ssbo = radv_load_ssbo;
6553 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6554 ctx.abi.clamp_shadow_reference = false;
6555
6556 if (shader_count >= 2)
6557 ac_init_exec_full_mask(&ctx.ac);
6558
6559 if (ctx.ac.chip_class == GFX9 &&
6560 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6561 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6562
6563 for(int i = 0; i < shader_count; ++i) {
6564 ctx.stage = shaders[i]->info.stage;
6565 ctx.output_mask = 0;
6566 ctx.tess_outputs_written = 0;
6567 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6568 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6569
6570 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6571 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6572 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6573 ctx.abi.load_inputs = load_gs_input;
6574 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6575 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6576 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6577 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6578 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6579 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6580 if (shader_info->info.vs.needs_instance_id) {
6581 ctx.shader_info->vs.vgpr_comp_cnt =
6582 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6583 }
6584 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6585 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6586 }
6587
6588 if (i)
6589 emit_barrier(&ctx);
6590
6591 ac_setup_rings(&ctx);
6592
6593 LLVMBasicBlockRef merge_block;
6594 if (shader_count >= 2) {
6595 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6596 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6597 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6598
6599 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6600 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6601 LLVMConstInt(ctx.ac.i32, 8, false), false);
6602 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6603 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6604 thread_id, count, "");
6605 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6606
6607 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6608 }
6609
6610 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6611 handle_fs_inputs(&ctx, shaders[i]);
6612 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6613 handle_vs_inputs(&ctx, shaders[i]);
6614 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6615 prepare_gs_input_vgprs(&ctx);
6616
6617 nir_foreach_variable(variable, &shaders[i]->outputs)
6618 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6619
6620 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6621
6622 if (shader_count >= 2) {
6623 LLVMBuildBr(ctx.ac.builder, merge_block);
6624 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6625 }
6626
6627 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6628 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6629 shaders[i]->info.cull_distance_array_size > 4;
6630 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6631 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6632 shaders[i]->info.gs.vertices_out;
6633 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6634 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6635 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6636 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6637 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6638 }
6639 }
6640
6641 LLVMBuildRetVoid(ctx.builder);
6642
6643 ac_llvm_finalize_module(&ctx);
6644
6645 if (shader_count == 1)
6646 ac_nir_eliminate_const_vs_outputs(&ctx);
6647
6648 return ctx.module;
6649 }
6650
6651 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6652 {
6653 unsigned *retval = (unsigned *)context;
6654 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6655 char *description = LLVMGetDiagInfoDescription(di);
6656
6657 if (severity == LLVMDSError) {
6658 *retval = 1;
6659 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6660 description);
6661 }
6662
6663 LLVMDisposeMessage(description);
6664 }
6665
6666 static unsigned ac_llvm_compile(LLVMModuleRef M,
6667 struct ac_shader_binary *binary,
6668 LLVMTargetMachineRef tm)
6669 {
6670 unsigned retval = 0;
6671 char *err;
6672 LLVMContextRef llvm_ctx;
6673 LLVMMemoryBufferRef out_buffer;
6674 unsigned buffer_size;
6675 const char *buffer_data;
6676 LLVMBool mem_err;
6677
6678 /* Setup Diagnostic Handler*/
6679 llvm_ctx = LLVMGetModuleContext(M);
6680
6681 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6682 &retval);
6683
6684 /* Compile IR*/
6685 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6686 &err, &out_buffer);
6687
6688 /* Process Errors/Warnings */
6689 if (mem_err) {
6690 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6691 free(err);
6692 retval = 1;
6693 goto out;
6694 }
6695
6696 /* Extract Shader Code*/
6697 buffer_size = LLVMGetBufferSize(out_buffer);
6698 buffer_data = LLVMGetBufferStart(out_buffer);
6699
6700 ac_elf_read(buffer_data, buffer_size, binary);
6701
6702 /* Clean up */
6703 LLVMDisposeMemoryBuffer(out_buffer);
6704
6705 out:
6706 return retval;
6707 }
6708
6709 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6710 LLVMModuleRef llvm_module,
6711 struct ac_shader_binary *binary,
6712 struct ac_shader_config *config,
6713 struct ac_shader_variant_info *shader_info,
6714 gl_shader_stage stage,
6715 bool dump_shader, bool supports_spill)
6716 {
6717 if (dump_shader)
6718 ac_dump_module(llvm_module);
6719
6720 memset(binary, 0, sizeof(*binary));
6721 int v = ac_llvm_compile(llvm_module, binary, tm);
6722 if (v) {
6723 fprintf(stderr, "compile failed\n");
6724 }
6725
6726 if (dump_shader)
6727 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6728
6729 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6730
6731 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6732 LLVMDisposeModule(llvm_module);
6733 LLVMContextDispose(ctx);
6734
6735 if (stage == MESA_SHADER_FRAGMENT) {
6736 shader_info->num_input_vgprs = 0;
6737 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6738 shader_info->num_input_vgprs += 2;
6739 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6740 shader_info->num_input_vgprs += 2;
6741 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6742 shader_info->num_input_vgprs += 2;
6743 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6744 shader_info->num_input_vgprs += 3;
6745 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6746 shader_info->num_input_vgprs += 2;
6747 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6748 shader_info->num_input_vgprs += 2;
6749 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6750 shader_info->num_input_vgprs += 2;
6751 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6752 shader_info->num_input_vgprs += 1;
6753 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6754 shader_info->num_input_vgprs += 1;
6755 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6756 shader_info->num_input_vgprs += 1;
6757 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6758 shader_info->num_input_vgprs += 1;
6759 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6760 shader_info->num_input_vgprs += 1;
6761 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6762 shader_info->num_input_vgprs += 1;
6763 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6764 shader_info->num_input_vgprs += 1;
6765 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6766 shader_info->num_input_vgprs += 1;
6767 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6768 shader_info->num_input_vgprs += 1;
6769 }
6770 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6771
6772 /* +3 for scratch wave offset and VCC */
6773 config->num_sgprs = MAX2(config->num_sgprs,
6774 shader_info->num_input_sgprs + 3);
6775 }
6776
6777 static void
6778 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6779 {
6780 switch (nir->info.stage) {
6781 case MESA_SHADER_COMPUTE:
6782 for (int i = 0; i < 3; ++i)
6783 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6784 break;
6785 case MESA_SHADER_FRAGMENT:
6786 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6787 break;
6788 case MESA_SHADER_GEOMETRY:
6789 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6790 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6791 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6792 shader_info->gs.invocations = nir->info.gs.invocations;
6793 break;
6794 case MESA_SHADER_TESS_EVAL:
6795 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6796 shader_info->tes.spacing = nir->info.tess.spacing;
6797 shader_info->tes.ccw = nir->info.tess.ccw;
6798 shader_info->tes.point_mode = nir->info.tess.point_mode;
6799 shader_info->tes.as_es = options->key.tes.as_es;
6800 break;
6801 case MESA_SHADER_TESS_CTRL:
6802 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6803 break;
6804 case MESA_SHADER_VERTEX:
6805 shader_info->vs.as_es = options->key.vs.as_es;
6806 shader_info->vs.as_ls = options->key.vs.as_ls;
6807 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6808 if (options->key.vs.as_ls)
6809 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6810 break;
6811 default:
6812 break;
6813 }
6814 }
6815
6816 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6817 struct ac_shader_binary *binary,
6818 struct ac_shader_config *config,
6819 struct ac_shader_variant_info *shader_info,
6820 struct nir_shader *const *nir,
6821 int nir_count,
6822 const struct ac_nir_compiler_options *options,
6823 bool dump_shader)
6824 {
6825
6826 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6827 options);
6828
6829 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6830 for (int i = 0; i < nir_count; ++i)
6831 ac_fill_shader_info(shader_info, nir[i], options);
6832 }
6833
6834 static void
6835 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6836 {
6837 LLVMValueRef args[9];
6838 args[0] = ctx->gsvs_ring;
6839 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6840 args[3] = ctx->ac.i32_0;
6841 args[4] = ctx->ac.i32_1; /* OFFEN */
6842 args[5] = ctx->ac.i32_0; /* IDXEN */
6843 args[6] = ctx->ac.i32_1; /* GLC */
6844 args[7] = ctx->ac.i32_1; /* SLC */
6845 args[8] = ctx->ac.i32_0; /* TFE */
6846
6847 int idx = 0;
6848
6849 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6850 int length = 4;
6851 int slot = idx;
6852 int slot_inc = 1;
6853 if (!(ctx->output_mask & (1ull << i)))
6854 continue;
6855
6856 if (i == VARYING_SLOT_CLIP_DIST0) {
6857 /* unpack clip and cull from a single set of slots */
6858 length = ctx->num_output_clips + ctx->num_output_culls;
6859 if (length > 4)
6860 slot_inc = 2;
6861 }
6862
6863 for (unsigned j = 0; j < length; j++) {
6864 LLVMValueRef value;
6865 args[2] = LLVMConstInt(ctx->ac.i32,
6866 (slot * 4 + j) *
6867 ctx->gs_max_out_vertices * 16 * 4, false);
6868
6869 value = ac_build_intrinsic(&ctx->ac,
6870 "llvm.SI.buffer.load.dword.i32.i32",
6871 ctx->ac.i32, args, 9,
6872 AC_FUNC_ATTR_READONLY |
6873 AC_FUNC_ATTR_LEGACY);
6874
6875 LLVMBuildStore(ctx->builder,
6876 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6877 }
6878 idx += slot_inc;
6879 }
6880 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6881 }
6882
6883 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6884 struct nir_shader *geom_shader,
6885 struct ac_shader_binary *binary,
6886 struct ac_shader_config *config,
6887 struct ac_shader_variant_info *shader_info,
6888 const struct ac_nir_compiler_options *options,
6889 bool dump_shader)
6890 {
6891 struct nir_to_llvm_context ctx = {0};
6892 ctx.context = LLVMContextCreate();
6893 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6894 ctx.options = options;
6895 ctx.shader_info = shader_info;
6896
6897 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6898 ctx.ac.module = ctx.module;
6899
6900 ctx.is_gs_copy_shader = true;
6901 LLVMSetTarget(ctx.module, "amdgcn--");
6902
6903 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6904 ctx.ac.builder = ctx.builder;
6905 ctx.stage = MESA_SHADER_VERTEX;
6906
6907 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6908
6909 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6910 ac_setup_rings(&ctx);
6911
6912 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6913 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6914
6915 struct ac_nir_context nir_ctx = {};
6916 nir_ctx.ac = ctx.ac;
6917 nir_ctx.abi = &ctx.abi;
6918
6919 nir_ctx.nctx = &ctx;
6920 ctx.nir = &nir_ctx;
6921
6922 nir_foreach_variable(variable, &geom_shader->outputs) {
6923 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6924 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6925 }
6926
6927 ac_gs_copy_shader_emit(&ctx);
6928
6929 ctx.nir = NULL;
6930
6931 LLVMBuildRetVoid(ctx.builder);
6932
6933 ac_llvm_finalize_module(&ctx);
6934
6935 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6936 MESA_SHADER_VERTEX,
6937 dump_shader, options->supports_spill);
6938 }