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radv/ac: add support for patch inputs to unique index code.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83 LLVMValueRef ls_out_layout;
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef tcs_offchip_layout;
87 LLVMValueRef tcs_out_offsets;
88 LLVMValueRef tcs_out_layout;
89 LLVMValueRef tcs_in_layout;
90 LLVMValueRef oc_lds;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tcs_patch_id;
93 LLVMValueRef tcs_rel_ids;
94 LLVMValueRef tes_rel_patch_id;
95 LLVMValueRef tes_patch_id;
96 LLVMValueRef tes_u;
97 LLVMValueRef tes_v;
98
99 LLVMValueRef gsvs_ring_stride;
100 LLVMValueRef gsvs_num_entries;
101 LLVMValueRef gs2vs_offset;
102 LLVMValueRef gs_wave_id;
103 LLVMValueRef gs_vtx_offset[6];
104 LLVMValueRef gs_prim_id, gs_invocation_id;
105
106 LLVMValueRef esgs_ring;
107 LLVMValueRef gsvs_ring;
108 LLVMValueRef hs_ring_tess_offchip;
109 LLVMValueRef hs_ring_tess_factor;
110
111 LLVMValueRef prim_mask;
112 LLVMValueRef sample_positions;
113 LLVMValueRef persp_sample, persp_center, persp_centroid;
114 LLVMValueRef linear_sample, linear_center, linear_centroid;
115 LLVMValueRef front_face;
116 LLVMValueRef ancillary;
117 LLVMValueRef sample_coverage;
118 LLVMValueRef frag_pos[4];
119
120 LLVMBasicBlockRef continue_block;
121 LLVMBasicBlockRef break_block;
122
123 LLVMTypeRef i1;
124 LLVMTypeRef i8;
125 LLVMTypeRef i16;
126 LLVMTypeRef i32;
127 LLVMTypeRef i64;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v3i32;
130 LLVMTypeRef v4i32;
131 LLVMTypeRef v8i32;
132 LLVMTypeRef f64;
133 LLVMTypeRef f32;
134 LLVMTypeRef f16;
135 LLVMTypeRef v2f32;
136 LLVMTypeRef v4f32;
137 LLVMTypeRef v16i8;
138 LLVMTypeRef voidt;
139
140 LLVMValueRef i1true;
141 LLVMValueRef i1false;
142 LLVMValueRef i32zero;
143 LLVMValueRef i32one;
144 LLVMValueRef f32zero;
145 LLVMValueRef f32one;
146 LLVMValueRef v4f32empty;
147
148 unsigned uniform_md_kind;
149 LLVMValueRef empty_md;
150 gl_shader_stage stage;
151
152 LLVMValueRef lds;
153 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
154 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
155
156 LLVMValueRef shared_memory;
157 uint64_t input_mask;
158 uint64_t output_mask;
159 int num_locals;
160 LLVMValueRef *locals;
161 bool has_ddxy;
162 uint8_t num_output_clips;
163 uint8_t num_output_culls;
164
165 bool has_ds_bpermute;
166
167 bool is_gs_copy_shader;
168 LLVMValueRef gs_next_vertex;
169 unsigned gs_max_out_vertices;
170 };
171
172 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
173 nir_deref_var *deref,
174 enum desc_type desc_type);
175 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
176 {
177 return (index * 4) + chan;
178 }
179
180 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
181 {
182 /* handle patch indices separate */
183 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
184 return 0;
185 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
186 return 1;
187 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
188 return 2 + (slot - VARYING_SLOT_PATCH0);
189
190 if (slot == VARYING_SLOT_POS)
191 return 0;
192 if (slot == VARYING_SLOT_PSIZ)
193 return 1;
194 if (slot == VARYING_SLOT_CLIP_DIST0)
195 return 2;
196 /* 3 is reserved for clip dist as well */
197 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
198 return 4 + (slot - VARYING_SLOT_VAR0);
199 unreachable("illegal slot in get unique index\n");
200 }
201
202 static unsigned llvm_get_type_size(LLVMTypeRef type)
203 {
204 LLVMTypeKind kind = LLVMGetTypeKind(type);
205
206 switch (kind) {
207 case LLVMIntegerTypeKind:
208 return LLVMGetIntTypeWidth(type) / 8;
209 case LLVMFloatTypeKind:
210 return 4;
211 case LLVMPointerTypeKind:
212 return 8;
213 case LLVMVectorTypeKind:
214 return LLVMGetVectorSize(type) *
215 llvm_get_type_size(LLVMGetElementType(type));
216 default:
217 assert(0);
218 return 0;
219 }
220 }
221
222 static void set_llvm_calling_convention(LLVMValueRef func,
223 gl_shader_stage stage)
224 {
225 enum radeon_llvm_calling_convention calling_conv;
226
227 switch (stage) {
228 case MESA_SHADER_VERTEX:
229 case MESA_SHADER_TESS_CTRL:
230 case MESA_SHADER_TESS_EVAL:
231 calling_conv = RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_GEOMETRY:
234 calling_conv = RADEON_LLVM_AMDGPU_GS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 static LLVMValueRef
250 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
251 LLVMBuilderRef builder, LLVMTypeRef *return_types,
252 unsigned num_return_elems, LLVMTypeRef *param_types,
253 unsigned param_count, unsigned array_params_mask,
254 unsigned sgpr_params, bool unsafe_math)
255 {
256 LLVMTypeRef main_function_type, ret_type;
257 LLVMBasicBlockRef main_function_body;
258
259 if (num_return_elems)
260 ret_type = LLVMStructTypeInContext(ctx, return_types,
261 num_return_elems, true);
262 else
263 ret_type = LLVMVoidTypeInContext(ctx);
264
265 /* Setup the function */
266 main_function_type =
267 LLVMFunctionType(ret_type, param_types, param_count, 0);
268 LLVMValueRef main_function =
269 LLVMAddFunction(module, "main", main_function_type);
270 main_function_body =
271 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
272 LLVMPositionBuilderAtEnd(builder, main_function_body);
273
274 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
275 for (unsigned i = 0; i < sgpr_params; ++i) {
276 if (array_params_mask & (1 << i)) {
277 LLVMValueRef P = LLVMGetParam(main_function, i);
278 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
279 ac_add_attr_dereferenceable(P, UINT64_MAX);
280 }
281 else {
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
283 }
284 }
285
286 if (unsafe_math) {
287 /* These were copied from some LLVM test. */
288 LLVMAddTargetDependentFunctionAttr(main_function,
289 "less-precise-fpmad",
290 "true");
291 LLVMAddTargetDependentFunctionAttr(main_function,
292 "no-infs-fp-math",
293 "true");
294 LLVMAddTargetDependentFunctionAttr(main_function,
295 "no-nans-fp-math",
296 "true");
297 LLVMAddTargetDependentFunctionAttr(main_function,
298 "unsafe-fp-math",
299 "true");
300 }
301 return main_function;
302 }
303
304 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
305 {
306 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
307 CONST_ADDR_SPACE);
308 }
309
310 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
311 int idx,
312 LLVMTypeRef type)
313 {
314 LLVMValueRef offset;
315 LLVMValueRef ptr;
316 int addr_space;
317
318 offset = LLVMConstInt(ctx->i32, idx * 16, false);
319
320 ptr = ctx->shared_memory;
321 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
322 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
323 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
324 return ptr;
325 }
326
327 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
328 {
329 if (t == ctx->f16 || t == ctx->i16)
330 return ctx->i16;
331 else if (t == ctx->f32 || t == ctx->i32)
332 return ctx->i32;
333 else if (t == ctx->f64 || t == ctx->i64)
334 return ctx->i64;
335 else
336 unreachable("Unhandled integer size");
337 }
338
339 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
340 {
341 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
342 LLVMTypeRef elem_type = LLVMGetElementType(t);
343 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
344 LLVMGetVectorSize(t));
345 }
346 return to_integer_type_scalar(ctx, t);
347 }
348
349 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
350 {
351 LLVMTypeRef type = LLVMTypeOf(v);
352 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
353 }
354
355 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
356 {
357 if (t == ctx->i16 || t == ctx->f16)
358 return ctx->f16;
359 else if (t == ctx->i32 || t == ctx->f32)
360 return ctx->f32;
361 else if (t == ctx->i64 || t == ctx->f64)
362 return ctx->f64;
363 else
364 unreachable("Unhandled float size");
365 }
366
367 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
368 {
369 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
370 LLVMTypeRef elem_type = LLVMGetElementType(t);
371 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
372 LLVMGetVectorSize(t));
373 }
374 return to_float_type_scalar(ctx, t);
375 }
376
377 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
378 {
379 LLVMTypeRef type = LLVMTypeOf(v);
380 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
381 }
382
383 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
384 {
385 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
386 type = LLVMGetElementType(type);
387
388 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
389 return LLVMGetIntTypeWidth(type);
390
391 if (type == ctx->f16)
392 return 16;
393 if (type == ctx->f32)
394 return 32;
395 if (type == ctx->f64)
396 return 64;
397
398 unreachable("Unhandled type kind in get_elem_bits");
399 }
400
401 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
402 LLVMValueRef param, unsigned rshift,
403 unsigned bitwidth)
404 {
405 LLVMValueRef value = param;
406 if (rshift)
407 value = LLVMBuildLShr(ctx->builder, value,
408 LLVMConstInt(ctx->i32, rshift, false), "");
409
410 if (rshift + bitwidth < 32) {
411 unsigned mask = (1 << bitwidth) - 1;
412 value = LLVMBuildAnd(ctx->builder, value,
413 LLVMConstInt(ctx->i32, mask, false), "");
414 }
415 return value;
416 }
417
418 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
419 {
420 ud_info->sgpr_idx = sgpr_idx;
421 ud_info->num_sgprs = num_sgprs;
422 ud_info->indirect = false;
423 ud_info->indirect_offset = 0;
424 }
425
426 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
427 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
428 {
429 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
430 }
431
432 #if 0
433 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
434 uint32_t indirect_offset)
435 {
436 ud_info->sgpr_idx = sgpr_idx;
437 ud_info->num_sgprs = num_sgprs;
438 ud_info->indirect = true;
439 ud_info->indirect_offset = indirect_offset;
440 }
441 #endif
442
443 static void create_function(struct nir_to_llvm_context *ctx)
444 {
445 LLVMTypeRef arg_types[23];
446 unsigned arg_idx = 0;
447 unsigned array_params_mask = 0;
448 unsigned sgpr_count = 0, user_sgpr_count;
449 unsigned i;
450 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
451 unsigned user_sgpr_idx;
452 bool need_push_constants;
453 bool need_ring_offsets = false;
454
455 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
456 if (ctx->stage == MESA_SHADER_GEOMETRY ||
457 ctx->stage == MESA_SHADER_VERTEX ||
458 ctx->stage == MESA_SHADER_TESS_CTRL ||
459 ctx->stage == MESA_SHADER_TESS_EVAL ||
460 ctx->is_gs_copy_shader)
461 need_ring_offsets = true;
462
463 need_push_constants = true;
464 if (!ctx->options->layout)
465 need_push_constants = false;
466 else if (!ctx->options->layout->push_constant_size &&
467 !ctx->options->layout->dynamic_offset_count)
468 need_push_constants = false;
469
470 if (need_ring_offsets && !ctx->options->supports_spill) {
471 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
472 }
473
474 /* 1 for each descriptor set */
475 for (unsigned i = 0; i < num_sets; ++i) {
476 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
477 array_params_mask |= (1 << arg_idx);
478 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
479 }
480 }
481
482 if (need_push_constants) {
483 /* 1 for push constants and dynamic descriptors */
484 array_params_mask |= (1 << arg_idx);
485 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
486 }
487
488 switch (ctx->stage) {
489 case MESA_SHADER_COMPUTE:
490 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
491 user_sgpr_count = arg_idx;
492 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
493 arg_types[arg_idx++] = ctx->i32;
494 sgpr_count = arg_idx;
495
496 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
497 break;
498 case MESA_SHADER_VERTEX:
499 if (!ctx->is_gs_copy_shader) {
500 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
501 arg_types[arg_idx++] = ctx->i32; // base vertex
502 arg_types[arg_idx++] = ctx->i32; // start instance
503 arg_types[arg_idx++] = ctx->i32; // draw index
504 }
505 user_sgpr_count = arg_idx;
506 if (ctx->options->key.vs.as_es)
507 arg_types[arg_idx++] = ctx->i32; //es2gs offset
508 else if (ctx->options->key.vs.as_ls) {
509 arg_types[arg_idx++] = ctx->i32; //ls out layout
510 user_sgpr_count++;
511 }
512 sgpr_count = arg_idx;
513 arg_types[arg_idx++] = ctx->i32; // vertex id
514 if (!ctx->is_gs_copy_shader) {
515 arg_types[arg_idx++] = ctx->i32; // rel auto id
516 arg_types[arg_idx++] = ctx->i32; // vs prim id
517 arg_types[arg_idx++] = ctx->i32; // instance id
518 }
519 break;
520 case MESA_SHADER_TESS_CTRL:
521 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
522 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
523 arg_types[arg_idx++] = ctx->i32; // tcs out layout
524 arg_types[arg_idx++] = ctx->i32; // tcs in layout
525 user_sgpr_count = arg_idx;
526 arg_types[arg_idx++] = ctx->i32; // param oc lds
527 arg_types[arg_idx++] = ctx->i32; // tess factor offset
528 sgpr_count = arg_idx;
529 arg_types[arg_idx++] = ctx->i32; // patch id
530 arg_types[arg_idx++] = ctx->i32; // rel ids;
531 break;
532 case MESA_SHADER_TESS_EVAL:
533 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
534 user_sgpr_count = arg_idx;
535 if (ctx->options->key.tes.as_es) {
536 arg_types[arg_idx++] = ctx->i32; // OC LDS
537 arg_types[arg_idx++] = ctx->i32; //
538 arg_types[arg_idx++] = ctx->i32; // es2gs offset
539 } else {
540 arg_types[arg_idx++] = ctx->i32; //
541 arg_types[arg_idx++] = ctx->i32; // OC LDS
542 }
543 sgpr_count = arg_idx;
544 arg_types[arg_idx++] = ctx->f32; // tes_u
545 arg_types[arg_idx++] = ctx->f32; // tes_v
546 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
547 arg_types[arg_idx++] = ctx->i32; // tes patch id
548 break;
549 case MESA_SHADER_GEOMETRY:
550 arg_types[arg_idx++] = ctx->i32; // gsvs stride
551 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
552 user_sgpr_count = arg_idx;
553 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
554 arg_types[arg_idx++] = ctx->i32; // wave id
555 sgpr_count = arg_idx;
556 arg_types[arg_idx++] = ctx->i32; // vtx0
557 arg_types[arg_idx++] = ctx->i32; // vtx1
558 arg_types[arg_idx++] = ctx->i32; // prim id
559 arg_types[arg_idx++] = ctx->i32; // vtx2
560 arg_types[arg_idx++] = ctx->i32; // vtx3
561 arg_types[arg_idx++] = ctx->i32; // vtx4
562 arg_types[arg_idx++] = ctx->i32; // vtx5
563 arg_types[arg_idx++] = ctx->i32; // GS instance id
564 break;
565 case MESA_SHADER_FRAGMENT:
566 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
567 user_sgpr_count = arg_idx;
568 arg_types[arg_idx++] = ctx->i32; /* prim mask */
569 sgpr_count = arg_idx;
570 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
571 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
572 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
573 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
574 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
575 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
576 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
577 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
578 arg_types[arg_idx++] = ctx->f32; /* pos x float */
579 arg_types[arg_idx++] = ctx->f32; /* pos y float */
580 arg_types[arg_idx++] = ctx->f32; /* pos z float */
581 arg_types[arg_idx++] = ctx->f32; /* pos w float */
582 arg_types[arg_idx++] = ctx->i32; /* front face */
583 arg_types[arg_idx++] = ctx->i32; /* ancillary */
584 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
585 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
586 break;
587 default:
588 unreachable("Shader stage not implemented");
589 }
590
591 ctx->main_function = create_llvm_function(
592 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
593 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
594 set_llvm_calling_convention(ctx->main_function, ctx->stage);
595
596 ctx->shader_info->num_input_sgprs = 0;
597 ctx->shader_info->num_input_vgprs = 0;
598
599 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
600 for (i = 0; i < user_sgpr_count; i++)
601 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
602
603 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
604 for (; i < sgpr_count; i++)
605 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
606
607 if (ctx->stage != MESA_SHADER_FRAGMENT)
608 for (; i < arg_idx; ++i)
609 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
610
611 arg_idx = 0;
612 user_sgpr_idx = 0;
613
614 if (ctx->options->supports_spill || need_ring_offsets) {
615 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
616 user_sgpr_idx += 2;
617 if (ctx->options->supports_spill) {
618 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
619 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
620 NULL, 0, AC_FUNC_ATTR_READNONE);
621 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
622 const_array(ctx->v16i8, 8), "");
623 } else
624 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
625 }
626
627 for (unsigned i = 0; i < num_sets; ++i) {
628 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
629 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
630 user_sgpr_idx += 2;
631 ctx->descriptor_sets[i] =
632 LLVMGetParam(ctx->main_function, arg_idx++);
633 } else
634 ctx->descriptor_sets[i] = NULL;
635 }
636
637 if (need_push_constants) {
638 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
639 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
640 user_sgpr_idx += 2;
641 }
642
643 switch (ctx->stage) {
644 case MESA_SHADER_COMPUTE:
645 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
646 user_sgpr_idx += 3;
647 ctx->num_work_groups =
648 LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->workgroup_ids =
650 LLVMGetParam(ctx->main_function, arg_idx++);
651 ctx->tg_size =
652 LLVMGetParam(ctx->main_function, arg_idx++);
653 ctx->local_invocation_ids =
654 LLVMGetParam(ctx->main_function, arg_idx++);
655 break;
656 case MESA_SHADER_VERTEX:
657 if (!ctx->is_gs_copy_shader) {
658 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
659 user_sgpr_idx += 2;
660 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
661 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
662 user_sgpr_idx += 3;
663 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
664 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
665 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
666 }
667 if (ctx->options->key.vs.as_es)
668 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
669 else if (ctx->options->key.vs.as_ls) {
670 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, user_sgpr_idx, 1);
671 user_sgpr_idx += 1;
672 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
673 }
674 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
675 if (!ctx->is_gs_copy_shader) {
676 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
677 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
678 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
679 }
680 break;
681 case MESA_SHADER_TESS_CTRL:
682 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
683 user_sgpr_idx += 4;
684 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
685 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
686 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
687 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
688 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
689 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
690 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
691 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
692 break;
693 case MESA_SHADER_TESS_EVAL:
694 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
695 user_sgpr_idx += 1;
696 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
697 if (ctx->options->key.tes.as_es) {
698 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
699 arg_idx++;
700 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
701 } else {
702 arg_idx++;
703 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
704 }
705 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
706 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
707 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
708 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
709 break;
710 case MESA_SHADER_GEOMETRY:
711 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
712 user_sgpr_idx += 2;
713 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
714 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
715 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
716 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
717 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
718 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
719 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
720 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
721 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
722 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
723 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
724 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
725 break;
726 case MESA_SHADER_FRAGMENT:
727 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
728 user_sgpr_idx += 2;
729 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
730 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
731 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
732 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
733 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
734 arg_idx++;
735 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
736 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
737 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
738 arg_idx++; /* line stipple */
739 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
740 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
741 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
742 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
743 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
744 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
745 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
746 break;
747 default:
748 unreachable("Shader stage not implemented");
749 }
750 }
751
752 static void setup_types(struct nir_to_llvm_context *ctx)
753 {
754 LLVMValueRef args[4];
755
756 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
757 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
758 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
759 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
760 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
761 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
762 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
763 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
764 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
765 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
766 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
767 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
768 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
769 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
770 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
771 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
772
773 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
774 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
775 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
776 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
777 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
778 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
779
780 args[0] = ctx->f32zero;
781 args[1] = ctx->f32zero;
782 args[2] = ctx->f32zero;
783 args[3] = ctx->f32one;
784 ctx->v4f32empty = LLVMConstVector(args, 4);
785
786 ctx->uniform_md_kind =
787 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
788 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
789
790 args[0] = LLVMConstReal(ctx->f32, 2.5);
791 }
792
793 static int get_llvm_num_components(LLVMValueRef value)
794 {
795 LLVMTypeRef type = LLVMTypeOf(value);
796 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
797 ? LLVMGetVectorSize(type)
798 : 1;
799 return num_components;
800 }
801
802 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
803 LLVMValueRef value,
804 int index)
805 {
806 int count = get_llvm_num_components(value);
807
808 assert(index < count);
809 if (count == 1)
810 return value;
811
812 return LLVMBuildExtractElement(ctx->builder, value,
813 LLVMConstInt(ctx->i32, index, false), "");
814 }
815
816 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
817 LLVMValueRef value, unsigned count)
818 {
819 unsigned num_components = get_llvm_num_components(value);
820 if (count == num_components)
821 return value;
822
823 LLVMValueRef masks[] = {
824 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
825 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
826
827 if (count == 1)
828 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
829 "");
830
831 LLVMValueRef swizzle = LLVMConstVector(masks, count);
832 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
833 }
834
835 static void
836 build_store_values_extended(struct nir_to_llvm_context *ctx,
837 LLVMValueRef *values,
838 unsigned value_count,
839 unsigned value_stride,
840 LLVMValueRef vec)
841 {
842 LLVMBuilderRef builder = ctx->builder;
843 unsigned i;
844
845 if (value_count == 1) {
846 LLVMBuildStore(builder, vec, values[0]);
847 return;
848 }
849
850 for (i = 0; i < value_count; i++) {
851 LLVMValueRef ptr = values[i * value_stride];
852 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
853 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
854 LLVMBuildStore(builder, value, ptr);
855 }
856 }
857
858 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
859 nir_ssa_def *def)
860 {
861 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
862 if (def->num_components > 1) {
863 type = LLVMVectorType(type, def->num_components);
864 }
865 return type;
866 }
867
868 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
869 {
870 assert(src.is_ssa);
871 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
872 return (LLVMValueRef)entry->data;
873 }
874
875
876 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
877 struct nir_block *b)
878 {
879 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
880 return (LLVMBasicBlockRef)entry->data;
881 }
882
883 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
884 nir_alu_src src,
885 unsigned num_components)
886 {
887 LLVMValueRef value = get_src(ctx, src.src);
888 bool need_swizzle = false;
889
890 assert(value);
891 LLVMTypeRef type = LLVMTypeOf(value);
892 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
893 ? LLVMGetVectorSize(type)
894 : 1;
895
896 for (unsigned i = 0; i < num_components; ++i) {
897 assert(src.swizzle[i] < src_components);
898 if (src.swizzle[i] != i)
899 need_swizzle = true;
900 }
901
902 if (need_swizzle || num_components != src_components) {
903 LLVMValueRef masks[] = {
904 LLVMConstInt(ctx->i32, src.swizzle[0], false),
905 LLVMConstInt(ctx->i32, src.swizzle[1], false),
906 LLVMConstInt(ctx->i32, src.swizzle[2], false),
907 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
908
909 if (src_components > 1 && num_components == 1) {
910 value = LLVMBuildExtractElement(ctx->builder, value,
911 masks[0], "");
912 } else if (src_components == 1 && num_components > 1) {
913 LLVMValueRef values[] = {value, value, value, value};
914 value = ac_build_gather_values(&ctx->ac, values, num_components);
915 } else {
916 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
917 value = LLVMBuildShuffleVector(ctx->builder, value, value,
918 swizzle, "");
919 }
920 }
921 assert(!src.negate);
922 assert(!src.abs);
923 return value;
924 }
925
926 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
927 LLVMIntPredicate pred, LLVMValueRef src0,
928 LLVMValueRef src1)
929 {
930 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
931 return LLVMBuildSelect(ctx->builder, result,
932 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
933 LLVMConstInt(ctx->i32, 0, false), "");
934 }
935
936 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
937 LLVMRealPredicate pred, LLVMValueRef src0,
938 LLVMValueRef src1)
939 {
940 LLVMValueRef result;
941 src0 = to_float(ctx, src0);
942 src1 = to_float(ctx, src1);
943 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
944 return LLVMBuildSelect(ctx->builder, result,
945 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
946 LLVMConstInt(ctx->i32, 0, false), "");
947 }
948
949 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
950 const char *intrin,
951 LLVMTypeRef result_type,
952 LLVMValueRef src0)
953 {
954 char name[64];
955 LLVMValueRef params[] = {
956 to_float(ctx, src0),
957 };
958
959 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
960 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
961 }
962
963 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
964 const char *intrin,
965 LLVMTypeRef result_type,
966 LLVMValueRef src0, LLVMValueRef src1)
967 {
968 char name[64];
969 LLVMValueRef params[] = {
970 to_float(ctx, src0),
971 to_float(ctx, src1),
972 };
973
974 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
975 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
976 }
977
978 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
979 const char *intrin,
980 LLVMTypeRef result_type,
981 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
982 {
983 char name[64];
984 LLVMValueRef params[] = {
985 to_float(ctx, src0),
986 to_float(ctx, src1),
987 to_float(ctx, src2),
988 };
989
990 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
991 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
992 }
993
994 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
995 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
996 {
997 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
998 ctx->i32zero, "");
999 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1000 }
1001
1002 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1003 LLVMValueRef src0)
1004 {
1005 LLVMValueRef params[2] = {
1006 src0,
1007
1008 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1009 * add special code to check for x=0. The reason is that
1010 * the LLVM behavior for x=0 is different from what we
1011 * need here.
1012 *
1013 * The hardware already implements the correct behavior.
1014 */
1015 LLVMConstInt(ctx->i32, 1, false),
1016 };
1017 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1018 }
1019
1020 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1021 LLVMValueRef src0)
1022 {
1023 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1024 }
1025
1026 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1027 LLVMValueRef src0)
1028 {
1029 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1030 }
1031
1032 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1033 LLVMIntPredicate pred,
1034 LLVMValueRef src0, LLVMValueRef src1)
1035 {
1036 return LLVMBuildSelect(ctx->builder,
1037 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1038 src0,
1039 src1, "");
1040
1041 }
1042 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1043 LLVMValueRef src0)
1044 {
1045 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1046 LLVMBuildNeg(ctx->builder, src0, ""));
1047 }
1048
1049 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1050 LLVMValueRef src0)
1051 {
1052 LLVMValueRef cmp, val;
1053
1054 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1055 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1056 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1057 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1058 return val;
1059 }
1060
1061 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1062 LLVMValueRef src0)
1063 {
1064 LLVMValueRef cmp, val;
1065
1066 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1067 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1068 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1069 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1070 return val;
1071 }
1072
1073 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1074 LLVMValueRef src0)
1075 {
1076 const char *intr = "llvm.floor.f32";
1077 LLVMValueRef fsrc0 = to_float(ctx, src0);
1078 LLVMValueRef params[] = {
1079 fsrc0,
1080 };
1081 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1082 ctx->f32, params, 1,
1083 AC_FUNC_ATTR_READNONE);
1084 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1085 }
1086
1087 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1088 const char *intrin,
1089 LLVMValueRef src0, LLVMValueRef src1)
1090 {
1091 LLVMTypeRef ret_type;
1092 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1093 LLVMValueRef res;
1094 LLVMValueRef params[] = { src0, src1 };
1095 ret_type = LLVMStructTypeInContext(ctx->context, types,
1096 2, true);
1097
1098 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1099 params, 2, AC_FUNC_ATTR_READNONE);
1100
1101 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1102 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1103 return res;
1104 }
1105
1106 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1107 LLVMValueRef src0)
1108 {
1109 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1110 }
1111
1112 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1113 LLVMValueRef src0, LLVMValueRef src1)
1114 {
1115 LLVMValueRef dst64, result;
1116 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1117 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1118
1119 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1120 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1121 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1122 return result;
1123 }
1124
1125 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1126 LLVMValueRef src0, LLVMValueRef src1)
1127 {
1128 LLVMValueRef dst64, result;
1129 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1130 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1131
1132 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1133 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1134 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1135 return result;
1136 }
1137
1138 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1139 bool is_signed,
1140 LLVMValueRef srcs[3])
1141 {
1142 LLVMValueRef result;
1143 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1144
1145 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1146 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1147 return result;
1148 }
1149
1150 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1151 LLVMValueRef src0, LLVMValueRef src1,
1152 LLVMValueRef src2, LLVMValueRef src3)
1153 {
1154 LLVMValueRef bfi_args[3], result;
1155
1156 bfi_args[0] = LLVMBuildShl(ctx->builder,
1157 LLVMBuildSub(ctx->builder,
1158 LLVMBuildShl(ctx->builder,
1159 ctx->i32one,
1160 src3, ""),
1161 ctx->i32one, ""),
1162 src2, "");
1163 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1164 bfi_args[2] = src0;
1165
1166 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1167
1168 /* Calculate:
1169 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1170 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1171 */
1172 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1173 LLVMBuildAnd(ctx->builder, bfi_args[0],
1174 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1175
1176 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1177 return result;
1178 }
1179
1180 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1181 LLVMValueRef src0)
1182 {
1183 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1184 int i;
1185 LLVMValueRef comp[2];
1186
1187 src0 = to_float(ctx, src0);
1188 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1189 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1190 for (i = 0; i < 2; i++) {
1191 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1192 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1193 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1194 }
1195
1196 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1197 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1198
1199 return comp[0];
1200 }
1201
1202 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1203 LLVMValueRef src0)
1204 {
1205 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1206 LLVMValueRef temps[2], result, val;
1207 int i;
1208
1209 for (i = 0; i < 2; i++) {
1210 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1211 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1212 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1213 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1214 }
1215
1216 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1217 ctx->i32zero, "");
1218 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1219 ctx->i32one, "");
1220 return result;
1221 }
1222
1223 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1224 nir_op op,
1225 LLVMValueRef src0)
1226 {
1227 unsigned mask;
1228 int idx;
1229 LLVMValueRef result;
1230 ctx->has_ddxy = true;
1231
1232 if (!ctx->lds && !ctx->has_ds_bpermute)
1233 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1234 LLVMArrayType(ctx->i32, 64),
1235 "ddxy_lds", LOCAL_ADDR_SPACE);
1236
1237 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1238 mask = AC_TID_MASK_LEFT;
1239 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1240 mask = AC_TID_MASK_TOP;
1241 else
1242 mask = AC_TID_MASK_TOP_LEFT;
1243
1244 /* for DDX we want to next X pixel, DDY next Y pixel. */
1245 if (op == nir_op_fddx_fine ||
1246 op == nir_op_fddx_coarse ||
1247 op == nir_op_fddx)
1248 idx = 1;
1249 else
1250 idx = 2;
1251
1252 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1253 mask, idx, ctx->lds,
1254 src0);
1255 return result;
1256 }
1257
1258 /*
1259 * this takes an I,J coordinate pair,
1260 * and works out the X and Y derivatives.
1261 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1262 */
1263 static LLVMValueRef emit_ddxy_interp(
1264 struct nir_to_llvm_context *ctx,
1265 LLVMValueRef interp_ij)
1266 {
1267 LLVMValueRef result[4], a;
1268 unsigned i;
1269
1270 for (i = 0; i < 2; i++) {
1271 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1272 LLVMConstInt(ctx->i32, i, false), "");
1273 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1274 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1275 }
1276 return ac_build_gather_values(&ctx->ac, result, 4);
1277 }
1278
1279 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1280 {
1281 LLVMValueRef src[4], result = NULL;
1282 unsigned num_components = instr->dest.dest.ssa.num_components;
1283 unsigned src_components;
1284 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1285
1286 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1287 switch (instr->op) {
1288 case nir_op_vec2:
1289 case nir_op_vec3:
1290 case nir_op_vec4:
1291 src_components = 1;
1292 break;
1293 case nir_op_pack_half_2x16:
1294 src_components = 2;
1295 break;
1296 case nir_op_unpack_half_2x16:
1297 src_components = 1;
1298 break;
1299 default:
1300 src_components = num_components;
1301 break;
1302 }
1303 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1304 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1305
1306 switch (instr->op) {
1307 case nir_op_fmov:
1308 case nir_op_imov:
1309 result = src[0];
1310 break;
1311 case nir_op_fneg:
1312 src[0] = to_float(ctx, src[0]);
1313 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1314 break;
1315 case nir_op_ineg:
1316 result = LLVMBuildNeg(ctx->builder, src[0], "");
1317 break;
1318 case nir_op_inot:
1319 result = LLVMBuildNot(ctx->builder, src[0], "");
1320 break;
1321 case nir_op_iadd:
1322 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1323 break;
1324 case nir_op_fadd:
1325 src[0] = to_float(ctx, src[0]);
1326 src[1] = to_float(ctx, src[1]);
1327 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1328 break;
1329 case nir_op_fsub:
1330 src[0] = to_float(ctx, src[0]);
1331 src[1] = to_float(ctx, src[1]);
1332 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1333 break;
1334 case nir_op_isub:
1335 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1336 break;
1337 case nir_op_imul:
1338 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1339 break;
1340 case nir_op_imod:
1341 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1342 break;
1343 case nir_op_umod:
1344 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1345 break;
1346 case nir_op_fmod:
1347 src[0] = to_float(ctx, src[0]);
1348 src[1] = to_float(ctx, src[1]);
1349 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1350 result = emit_intrin_1f_param(ctx, "llvm.floor",
1351 to_float_type(ctx, def_type), result);
1352 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1353 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1354 break;
1355 case nir_op_frem:
1356 src[0] = to_float(ctx, src[0]);
1357 src[1] = to_float(ctx, src[1]);
1358 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1359 break;
1360 case nir_op_irem:
1361 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1362 break;
1363 case nir_op_idiv:
1364 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1365 break;
1366 case nir_op_udiv:
1367 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1368 break;
1369 case nir_op_fmul:
1370 src[0] = to_float(ctx, src[0]);
1371 src[1] = to_float(ctx, src[1]);
1372 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1373 break;
1374 case nir_op_fdiv:
1375 src[0] = to_float(ctx, src[0]);
1376 src[1] = to_float(ctx, src[1]);
1377 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1378 break;
1379 case nir_op_frcp:
1380 src[0] = to_float(ctx, src[0]);
1381 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1382 break;
1383 case nir_op_iand:
1384 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1385 break;
1386 case nir_op_ior:
1387 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1388 break;
1389 case nir_op_ixor:
1390 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1391 break;
1392 case nir_op_ishl:
1393 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1394 break;
1395 case nir_op_ishr:
1396 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1397 break;
1398 case nir_op_ushr:
1399 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1400 break;
1401 case nir_op_ilt:
1402 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1403 break;
1404 case nir_op_ine:
1405 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1406 break;
1407 case nir_op_ieq:
1408 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1409 break;
1410 case nir_op_ige:
1411 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1412 break;
1413 case nir_op_ult:
1414 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1415 break;
1416 case nir_op_uge:
1417 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1418 break;
1419 case nir_op_feq:
1420 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1421 break;
1422 case nir_op_fne:
1423 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1424 break;
1425 case nir_op_flt:
1426 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1427 break;
1428 case nir_op_fge:
1429 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1430 break;
1431 case nir_op_fabs:
1432 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1433 to_float_type(ctx, def_type), src[0]);
1434 break;
1435 case nir_op_iabs:
1436 result = emit_iabs(ctx, src[0]);
1437 break;
1438 case nir_op_imax:
1439 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1440 break;
1441 case nir_op_imin:
1442 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1443 break;
1444 case nir_op_umax:
1445 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1446 break;
1447 case nir_op_umin:
1448 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1449 break;
1450 case nir_op_isign:
1451 result = emit_isign(ctx, src[0]);
1452 break;
1453 case nir_op_fsign:
1454 src[0] = to_float(ctx, src[0]);
1455 result = emit_fsign(ctx, src[0]);
1456 break;
1457 case nir_op_ffloor:
1458 result = emit_intrin_1f_param(ctx, "llvm.floor",
1459 to_float_type(ctx, def_type), src[0]);
1460 break;
1461 case nir_op_ftrunc:
1462 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1463 to_float_type(ctx, def_type), src[0]);
1464 break;
1465 case nir_op_fceil:
1466 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1467 to_float_type(ctx, def_type), src[0]);
1468 break;
1469 case nir_op_fround_even:
1470 result = emit_intrin_1f_param(ctx, "llvm.rint",
1471 to_float_type(ctx, def_type),src[0]);
1472 break;
1473 case nir_op_ffract:
1474 result = emit_ffract(ctx, src[0]);
1475 break;
1476 case nir_op_fsin:
1477 result = emit_intrin_1f_param(ctx, "llvm.sin",
1478 to_float_type(ctx, def_type), src[0]);
1479 break;
1480 case nir_op_fcos:
1481 result = emit_intrin_1f_param(ctx, "llvm.cos",
1482 to_float_type(ctx, def_type), src[0]);
1483 break;
1484 case nir_op_fsqrt:
1485 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1486 to_float_type(ctx, def_type), src[0]);
1487 break;
1488 case nir_op_fexp2:
1489 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1490 to_float_type(ctx, def_type), src[0]);
1491 break;
1492 case nir_op_flog2:
1493 result = emit_intrin_1f_param(ctx, "llvm.log2",
1494 to_float_type(ctx, def_type), src[0]);
1495 break;
1496 case nir_op_frsq:
1497 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1498 to_float_type(ctx, def_type), src[0]);
1499 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1500 break;
1501 case nir_op_fpow:
1502 result = emit_intrin_2f_param(ctx, "llvm.pow",
1503 to_float_type(ctx, def_type), src[0], src[1]);
1504 break;
1505 case nir_op_fmax:
1506 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1507 to_float_type(ctx, def_type), src[0], src[1]);
1508 break;
1509 case nir_op_fmin:
1510 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1511 to_float_type(ctx, def_type), src[0], src[1]);
1512 break;
1513 case nir_op_ffma:
1514 result = emit_intrin_3f_param(ctx, "llvm.fma",
1515 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1516 break;
1517 case nir_op_ibitfield_extract:
1518 result = emit_bitfield_extract(ctx, true, src);
1519 break;
1520 case nir_op_ubitfield_extract:
1521 result = emit_bitfield_extract(ctx, false, src);
1522 break;
1523 case nir_op_bitfield_insert:
1524 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1525 break;
1526 case nir_op_bitfield_reverse:
1527 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1528 break;
1529 case nir_op_bit_count:
1530 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1531 break;
1532 case nir_op_vec2:
1533 case nir_op_vec3:
1534 case nir_op_vec4:
1535 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1536 src[i] = to_integer(ctx, src[i]);
1537 result = ac_build_gather_values(&ctx->ac, src, num_components);
1538 break;
1539 case nir_op_f2i32:
1540 case nir_op_f2i64:
1541 src[0] = to_float(ctx, src[0]);
1542 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1543 break;
1544 case nir_op_f2u32:
1545 case nir_op_f2u64:
1546 src[0] = to_float(ctx, src[0]);
1547 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1548 break;
1549 case nir_op_i2f32:
1550 case nir_op_i2f64:
1551 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1552 break;
1553 case nir_op_u2f32:
1554 case nir_op_u2f64:
1555 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1556 break;
1557 case nir_op_f2f64:
1558 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1559 break;
1560 case nir_op_f2f32:
1561 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1562 break;
1563 case nir_op_u2u32:
1564 case nir_op_u2u64:
1565 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1566 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1567 else
1568 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1569 break;
1570 case nir_op_i2i32:
1571 case nir_op_i2i64:
1572 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1573 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1574 else
1575 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1576 break;
1577 case nir_op_bcsel:
1578 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1579 break;
1580 case nir_op_find_lsb:
1581 result = emit_find_lsb(ctx, src[0]);
1582 break;
1583 case nir_op_ufind_msb:
1584 result = emit_ufind_msb(ctx, src[0]);
1585 break;
1586 case nir_op_ifind_msb:
1587 result = emit_ifind_msb(ctx, src[0]);
1588 break;
1589 case nir_op_uadd_carry:
1590 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1591 break;
1592 case nir_op_usub_borrow:
1593 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1594 break;
1595 case nir_op_b2f:
1596 result = emit_b2f(ctx, src[0]);
1597 break;
1598 case nir_op_fquantize2f16:
1599 src[0] = to_float(ctx, src[0]);
1600 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1601 /* need to convert back up to f32 */
1602 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1603 break;
1604 case nir_op_umul_high:
1605 result = emit_umul_high(ctx, src[0], src[1]);
1606 break;
1607 case nir_op_imul_high:
1608 result = emit_imul_high(ctx, src[0], src[1]);
1609 break;
1610 case nir_op_pack_half_2x16:
1611 result = emit_pack_half_2x16(ctx, src[0]);
1612 break;
1613 case nir_op_unpack_half_2x16:
1614 result = emit_unpack_half_2x16(ctx, src[0]);
1615 break;
1616 case nir_op_fddx:
1617 case nir_op_fddy:
1618 case nir_op_fddx_fine:
1619 case nir_op_fddy_fine:
1620 case nir_op_fddx_coarse:
1621 case nir_op_fddy_coarse:
1622 result = emit_ddxy(ctx, instr->op, src[0]);
1623 break;
1624 default:
1625 fprintf(stderr, "Unknown NIR alu instr: ");
1626 nir_print_instr(&instr->instr, stderr);
1627 fprintf(stderr, "\n");
1628 abort();
1629 }
1630
1631 if (result) {
1632 assert(instr->dest.dest.is_ssa);
1633 result = to_integer(ctx, result);
1634 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1635 result);
1636 }
1637 }
1638
1639 static void visit_load_const(struct nir_to_llvm_context *ctx,
1640 nir_load_const_instr *instr)
1641 {
1642 LLVMValueRef values[4], value = NULL;
1643 LLVMTypeRef element_type =
1644 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1645
1646 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1647 switch (instr->def.bit_size) {
1648 case 32:
1649 values[i] = LLVMConstInt(element_type,
1650 instr->value.u32[i], false);
1651 break;
1652 case 64:
1653 values[i] = LLVMConstInt(element_type,
1654 instr->value.u64[i], false);
1655 break;
1656 default:
1657 fprintf(stderr,
1658 "unsupported nir load_const bit_size: %d\n",
1659 instr->def.bit_size);
1660 abort();
1661 }
1662 }
1663 if (instr->def.num_components > 1) {
1664 value = LLVMConstVector(values, instr->def.num_components);
1665 } else
1666 value = values[0];
1667
1668 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1669 }
1670
1671 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1672 LLVMTypeRef type)
1673 {
1674 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1675 return LLVMBuildBitCast(ctx->builder, ptr,
1676 LLVMPointerType(type, addr_space), "");
1677 }
1678
1679 static LLVMValueRef
1680 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1681 {
1682 LLVMValueRef size =
1683 LLVMBuildExtractElement(ctx->builder, descriptor,
1684 LLVMConstInt(ctx->i32, 2, false), "");
1685
1686 /* VI only */
1687 if (ctx->options->chip_class >= VI && in_elements) {
1688 /* On VI, the descriptor contains the size in bytes,
1689 * but TXQ must return the size in elements.
1690 * The stride is always non-zero for resources using TXQ.
1691 */
1692 LLVMValueRef stride =
1693 LLVMBuildExtractElement(ctx->builder, descriptor,
1694 LLVMConstInt(ctx->i32, 1, false), "");
1695 stride = LLVMBuildLShr(ctx->builder, stride,
1696 LLVMConstInt(ctx->i32, 16, false), "");
1697 stride = LLVMBuildAnd(ctx->builder, stride,
1698 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1699
1700 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1701 }
1702 return size;
1703 }
1704
1705 /**
1706 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1707 * intrinsic names).
1708 */
1709 static void build_int_type_name(
1710 LLVMTypeRef type,
1711 char *buf, unsigned bufsize)
1712 {
1713 assert(bufsize >= 6);
1714
1715 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1716 snprintf(buf, bufsize, "v%ui32",
1717 LLVMGetVectorSize(type));
1718 else
1719 strcpy(buf, "i32");
1720 }
1721
1722 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1723 struct ac_image_args *args,
1724 nir_tex_instr *instr)
1725 {
1726 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1727 LLVMValueRef coord = args->addr;
1728 LLVMValueRef half_texel[2];
1729 LLVMValueRef compare_cube_wa;
1730 LLVMValueRef result;
1731 int c;
1732 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1733
1734 //TODO Rect
1735 {
1736 struct ac_image_args txq_args = { 0 };
1737
1738 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1739 txq_args.opcode = ac_image_get_resinfo;
1740 txq_args.dmask = 0xf;
1741 txq_args.addr = ctx->i32zero;
1742 txq_args.resource = args->resource;
1743 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1744
1745 for (c = 0; c < 2; c++) {
1746 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1747 LLVMConstInt(ctx->i32, c, false), "");
1748 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1749 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1750 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1751 LLVMConstReal(ctx->f32, -0.5), "");
1752 }
1753 }
1754
1755 LLVMValueRef orig_coords = args->addr;
1756
1757 for (c = 0; c < 2; c++) {
1758 LLVMValueRef tmp;
1759 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1760 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1761 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1762 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1763 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1764 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1765 }
1766
1767
1768 /*
1769 * Apparantly cube has issue with integer types that the workaround doesn't solve,
1770 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
1771 * workaround by sampling using a scaled type and converting.
1772 * This is taken from amdgpu-pro shaders.
1773 */
1774 /* NOTE this produces some ugly code compared to amdgpu-pro,
1775 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
1776 * and then reads them back. -pro generates two selects,
1777 * one s_cmp for the descriptor rewriting
1778 * one v_cmp for the coordinate and result changes.
1779 */
1780 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1781 LLVMValueRef tmp, tmp2;
1782
1783 /* workaround 8/8/8/8 uint/sint cube gather bug */
1784 /* first detect it then change to a scaled read and f2i */
1785 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
1786 tmp2 = tmp;
1787
1788 /* extract the DATA_FORMAT */
1789 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
1790 LLVMConstInt(ctx->i32, 6, false), false);
1791
1792 /* is the DATA_FORMAT == 8_8_8_8 */
1793 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
1794
1795 if (stype == GLSL_TYPE_UINT)
1796 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
1797 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
1798 LLVMConstInt(ctx->i32, 0x10000000, false), "");
1799 else
1800 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
1801 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
1802 LLVMConstInt(ctx->i32, 0x14000000, false), "");
1803
1804 /* replace the NUM FORMAT in the descriptor */
1805 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
1806 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
1807
1808 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
1809
1810 /* don't modify the coordinates for this case */
1811 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
1812 }
1813 args->addr = coord;
1814 result = ac_build_image_opcode(&ctx->ac, args);
1815
1816 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1817 LLVMValueRef tmp, tmp2;
1818
1819 /* if the cube workaround is in place, f2i the result. */
1820 for (c = 0; c < 4; c++) {
1821 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
1822 if (stype == GLSL_TYPE_UINT)
1823 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
1824 else
1825 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
1826 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1827 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
1828 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
1829 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1830 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
1831 }
1832 }
1833 return result;
1834 }
1835
1836 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1837 nir_tex_instr *instr,
1838 struct ac_image_args *args)
1839 {
1840 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
1841 return ac_build_buffer_load_format(&ctx->ac,
1842 args->resource,
1843 args->addr,
1844 LLVMConstInt(ctx->i32, 0, false),
1845 true);
1846 }
1847
1848 args->opcode = ac_image_sample;
1849 args->compare = instr->is_shadow;
1850
1851 switch (instr->op) {
1852 case nir_texop_txf:
1853 case nir_texop_txf_ms:
1854 case nir_texop_samples_identical:
1855 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
1856 args->compare = false;
1857 args->offset = false;
1858 break;
1859 case nir_texop_txb:
1860 args->bias = true;
1861 break;
1862 case nir_texop_txl:
1863 args->lod = true;
1864 break;
1865 case nir_texop_txs:
1866 case nir_texop_query_levels:
1867 args->opcode = ac_image_get_resinfo;
1868 break;
1869 case nir_texop_tex:
1870 if (ctx->stage != MESA_SHADER_FRAGMENT)
1871 args->level_zero = true;
1872 break;
1873 case nir_texop_txd:
1874 args->deriv = true;
1875 break;
1876 case nir_texop_tg4:
1877 args->opcode = ac_image_gather4;
1878 args->level_zero = true;
1879 break;
1880 case nir_texop_lod:
1881 args->opcode = ac_image_get_lod;
1882 args->compare = false;
1883 args->offset = false;
1884 break;
1885 default:
1886 break;
1887 }
1888
1889 if (instr->op == nir_texop_tg4) {
1890 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1891 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1892 return radv_lower_gather4_integer(ctx, args, instr);
1893 }
1894 }
1895 return ac_build_image_opcode(&ctx->ac, args);
1896 }
1897
1898 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1899 nir_intrinsic_instr *instr)
1900 {
1901 LLVMValueRef index = get_src(ctx, instr->src[0]);
1902 unsigned desc_set = nir_intrinsic_desc_set(instr);
1903 unsigned binding = nir_intrinsic_binding(instr);
1904 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1905 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1906 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1907 unsigned base_offset = layout->binding[binding].offset;
1908 LLVMValueRef offset, stride;
1909
1910 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1911 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1912 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1913 layout->binding[binding].dynamic_offset_offset;
1914 desc_ptr = ctx->push_constants;
1915 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1916 stride = LLVMConstInt(ctx->i32, 16, false);
1917 } else
1918 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1919
1920 offset = LLVMConstInt(ctx->i32, base_offset, false);
1921 index = LLVMBuildMul(ctx->builder, index, stride, "");
1922 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1923
1924 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1925 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1926 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1927
1928 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1929 }
1930
1931 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1932 nir_intrinsic_instr *instr)
1933 {
1934 LLVMValueRef ptr, addr;
1935
1936 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1937 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1938
1939 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1940 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1941
1942 return LLVMBuildLoad(ctx->builder, ptr, "");
1943 }
1944
1945 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1946 nir_intrinsic_instr *instr)
1947 {
1948 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1949
1950 return get_buffer_size(ctx, desc, false);
1951 }
1952 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1953 nir_intrinsic_instr *instr)
1954 {
1955 const char *store_name;
1956 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1957 LLVMTypeRef data_type = ctx->f32;
1958 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1959 int components_32bit = elem_size_mult * instr->num_components;
1960 unsigned writemask = nir_intrinsic_write_mask(instr);
1961 LLVMValueRef base_data, base_offset;
1962 LLVMValueRef params[6];
1963
1964 if (ctx->stage == MESA_SHADER_FRAGMENT)
1965 ctx->shader_info->fs.writes_memory = true;
1966
1967 params[1] = get_src(ctx, instr->src[1]);
1968 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1969 params[4] = ctx->i1false; /* glc */
1970 params[5] = ctx->i1false; /* slc */
1971
1972 if (components_32bit > 1)
1973 data_type = LLVMVectorType(ctx->f32, components_32bit);
1974
1975 base_data = to_float(ctx, src_data);
1976 base_data = trim_vector(ctx, base_data, instr->num_components);
1977 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1978 data_type, "");
1979 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1980 while (writemask) {
1981 int start, count;
1982 LLVMValueRef data;
1983 LLVMValueRef offset;
1984 LLVMValueRef tmp;
1985 u_bit_scan_consecutive_range(&writemask, &start, &count);
1986
1987 /* Due to an LLVM limitation, split 3-element writes
1988 * into a 2-element and a 1-element write. */
1989 if (count == 3) {
1990 writemask |= 1 << (start + 2);
1991 count = 2;
1992 }
1993
1994 start *= elem_size_mult;
1995 count *= elem_size_mult;
1996
1997 if (count > 4) {
1998 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1999 count = 4;
2000 }
2001
2002 if (count == 4) {
2003 store_name = "llvm.amdgcn.buffer.store.v4f32";
2004 data = base_data;
2005 } else if (count == 2) {
2006 tmp = LLVMBuildExtractElement(ctx->builder,
2007 base_data, LLVMConstInt(ctx->i32, start, false), "");
2008 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2009 ctx->i32zero, "");
2010
2011 tmp = LLVMBuildExtractElement(ctx->builder,
2012 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2013 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2014 ctx->i32one, "");
2015 store_name = "llvm.amdgcn.buffer.store.v2f32";
2016
2017 } else {
2018 assert(count == 1);
2019 if (get_llvm_num_components(base_data) > 1)
2020 data = LLVMBuildExtractElement(ctx->builder, base_data,
2021 LLVMConstInt(ctx->i32, start, false), "");
2022 else
2023 data = base_data;
2024 store_name = "llvm.amdgcn.buffer.store.f32";
2025 }
2026
2027 offset = base_offset;
2028 if (start != 0) {
2029 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2030 }
2031 params[0] = data;
2032 params[3] = offset;
2033 ac_build_intrinsic(&ctx->ac, store_name,
2034 ctx->voidt, params, 6, 0);
2035 }
2036 }
2037
2038 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2039 nir_intrinsic_instr *instr)
2040 {
2041 const char *name;
2042 LLVMValueRef params[6];
2043 int arg_count = 0;
2044 if (ctx->stage == MESA_SHADER_FRAGMENT)
2045 ctx->shader_info->fs.writes_memory = true;
2046
2047 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2048 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2049 }
2050 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2051 params[arg_count++] = get_src(ctx, instr->src[0]);
2052 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2053 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2054 params[arg_count++] = ctx->i1false; /* slc */
2055
2056 switch (instr->intrinsic) {
2057 case nir_intrinsic_ssbo_atomic_add:
2058 name = "llvm.amdgcn.buffer.atomic.add";
2059 break;
2060 case nir_intrinsic_ssbo_atomic_imin:
2061 name = "llvm.amdgcn.buffer.atomic.smin";
2062 break;
2063 case nir_intrinsic_ssbo_atomic_umin:
2064 name = "llvm.amdgcn.buffer.atomic.umin";
2065 break;
2066 case nir_intrinsic_ssbo_atomic_imax:
2067 name = "llvm.amdgcn.buffer.atomic.smax";
2068 break;
2069 case nir_intrinsic_ssbo_atomic_umax:
2070 name = "llvm.amdgcn.buffer.atomic.umax";
2071 break;
2072 case nir_intrinsic_ssbo_atomic_and:
2073 name = "llvm.amdgcn.buffer.atomic.and";
2074 break;
2075 case nir_intrinsic_ssbo_atomic_or:
2076 name = "llvm.amdgcn.buffer.atomic.or";
2077 break;
2078 case nir_intrinsic_ssbo_atomic_xor:
2079 name = "llvm.amdgcn.buffer.atomic.xor";
2080 break;
2081 case nir_intrinsic_ssbo_atomic_exchange:
2082 name = "llvm.amdgcn.buffer.atomic.swap";
2083 break;
2084 case nir_intrinsic_ssbo_atomic_comp_swap:
2085 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2086 break;
2087 default:
2088 abort();
2089 }
2090
2091 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2092 }
2093
2094 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2095 nir_intrinsic_instr *instr)
2096 {
2097 LLVMValueRef results[2];
2098 int load_components;
2099 int num_components = instr->num_components;
2100 if (instr->dest.ssa.bit_size == 64)
2101 num_components *= 2;
2102
2103 for (int i = 0; i < num_components; i += load_components) {
2104 load_components = MIN2(num_components - i, 4);
2105 const char *load_name;
2106 LLVMTypeRef data_type = ctx->f32;
2107 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2108 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2109
2110 if (load_components == 3)
2111 data_type = LLVMVectorType(ctx->f32, 4);
2112 else if (load_components > 1)
2113 data_type = LLVMVectorType(ctx->f32, load_components);
2114
2115 if (load_components >= 3)
2116 load_name = "llvm.amdgcn.buffer.load.v4f32";
2117 else if (load_components == 2)
2118 load_name = "llvm.amdgcn.buffer.load.v2f32";
2119 else if (load_components == 1)
2120 load_name = "llvm.amdgcn.buffer.load.f32";
2121 else
2122 unreachable("unhandled number of components");
2123
2124 LLVMValueRef params[] = {
2125 get_src(ctx, instr->src[0]),
2126 LLVMConstInt(ctx->i32, 0, false),
2127 offset,
2128 ctx->i1false,
2129 ctx->i1false,
2130 };
2131
2132 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2133
2134 }
2135
2136 LLVMValueRef ret = results[0];
2137 if (num_components > 4 || num_components == 3) {
2138 LLVMValueRef masks[] = {
2139 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2140 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2141 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2142 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2143 };
2144
2145 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2146 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2147 results[num_components > 4 ? 1 : 0], swizzle, "");
2148 }
2149
2150 return LLVMBuildBitCast(ctx->builder, ret,
2151 get_def_type(ctx, &instr->dest.ssa), "");
2152 }
2153
2154 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2155 nir_intrinsic_instr *instr)
2156 {
2157 LLVMValueRef results[8], ret;
2158 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2159 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2160 int num_components = instr->num_components;
2161
2162 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2163
2164 if (instr->dest.ssa.bit_size == 64)
2165 num_components *= 2;
2166
2167 for (unsigned i = 0; i < num_components; ++i) {
2168 LLVMValueRef params[] = {
2169 rsrc,
2170 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2171 offset, "")
2172 };
2173 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2174 params, 2,
2175 AC_FUNC_ATTR_READNONE |
2176 AC_FUNC_ATTR_LEGACY);
2177 }
2178
2179
2180 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2181 return LLVMBuildBitCast(ctx->builder, ret,
2182 get_def_type(ctx, &instr->dest.ssa), "");
2183 }
2184
2185 static void
2186 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2187 bool vs_in, unsigned *vertex_index_out,
2188 unsigned *const_out, LLVMValueRef *indir_out)
2189 {
2190 unsigned const_offset = 0;
2191 LLVMValueRef offset = NULL;
2192
2193 if (vertex_index_out != NULL) {
2194 tail = tail->child;
2195 nir_deref_array *deref_array = nir_deref_as_array(tail);
2196 *vertex_index_out = deref_array->base_offset;
2197 }
2198
2199 while (tail->child != NULL) {
2200 const struct glsl_type *parent_type = tail->type;
2201 tail = tail->child;
2202
2203 if (tail->deref_type == nir_deref_type_array) {
2204 nir_deref_array *deref_array = nir_deref_as_array(tail);
2205 LLVMValueRef index, stride, local_offset;
2206 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2207
2208 const_offset += size * deref_array->base_offset;
2209 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2210 continue;
2211
2212 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2213 index = get_src(ctx, deref_array->indirect);
2214 stride = LLVMConstInt(ctx->i32, size, 0);
2215 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2216
2217 if (offset)
2218 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2219 else
2220 offset = local_offset;
2221 } else if (tail->deref_type == nir_deref_type_struct) {
2222 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2223
2224 for (unsigned i = 0; i < deref_struct->index; i++) {
2225 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2226 const_offset += glsl_count_attribute_slots(ft, vs_in);
2227 }
2228 } else
2229 unreachable("unsupported deref type");
2230
2231 }
2232
2233 if (const_offset && offset)
2234 offset = LLVMBuildAdd(ctx->builder, offset,
2235 LLVMConstInt(ctx->i32, const_offset, 0),
2236 "");
2237
2238 *const_out = const_offset;
2239 *indir_out = offset;
2240 }
2241
2242 static LLVMValueRef
2243 load_gs_input(struct nir_to_llvm_context *ctx,
2244 nir_intrinsic_instr *instr)
2245 {
2246 LLVMValueRef indir_index, vtx_offset;
2247 unsigned const_index;
2248 LLVMValueRef args[9];
2249 unsigned param, vtx_offset_param;
2250 LLVMValueRef value[4], result;
2251 unsigned vertex_index;
2252 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2253 false, &vertex_index,
2254 &const_index, &indir_index);
2255 vtx_offset_param = vertex_index;
2256 assert(vtx_offset_param < 6);
2257 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2258 LLVMConstInt(ctx->i32, 4, false), "");
2259
2260 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2261 for (unsigned i = 0; i < instr->num_components; i++) {
2262
2263 args[0] = ctx->esgs_ring;
2264 args[1] = vtx_offset;
2265 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2266 args[3] = ctx->i32zero;
2267 args[4] = ctx->i32one; /* OFFEN */
2268 args[5] = ctx->i32zero; /* IDXEN */
2269 args[6] = ctx->i32one; /* GLC */
2270 args[7] = ctx->i32zero; /* SLC */
2271 args[8] = ctx->i32zero; /* TFE */
2272
2273 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2274 ctx->i32, args, 9,
2275 AC_FUNC_ATTR_READONLY |
2276 AC_FUNC_ATTR_LEGACY);
2277 }
2278 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2279
2280 return result;
2281 }
2282
2283 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2284 nir_intrinsic_instr *instr)
2285 {
2286 LLVMValueRef values[8];
2287 int idx = instr->variables[0]->var->data.driver_location;
2288 int ve = instr->dest.ssa.num_components;
2289 LLVMValueRef indir_index;
2290 LLVMValueRef ret;
2291 unsigned const_index;
2292 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2293 instr->variables[0]->var->data.mode == nir_var_shader_in;
2294 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2295 &const_index, &indir_index);
2296
2297 if (instr->dest.ssa.bit_size == 64)
2298 ve *= 2;
2299
2300 switch (instr->variables[0]->var->data.mode) {
2301 case nir_var_shader_in:
2302 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2303 return load_gs_input(ctx, instr);
2304 }
2305 for (unsigned chan = 0; chan < ve; chan++) {
2306 if (indir_index) {
2307 unsigned count = glsl_count_attribute_slots(
2308 instr->variables[0]->var->type,
2309 ctx->stage == MESA_SHADER_VERTEX);
2310 count -= chan / 4;
2311 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2312 &ctx->ac, ctx->inputs + idx + chan, count,
2313 4, false);
2314
2315 values[chan] = LLVMBuildExtractElement(ctx->builder,
2316 tmp_vec,
2317 indir_index, "");
2318 } else
2319 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2320 }
2321 break;
2322 case nir_var_local:
2323 for (unsigned chan = 0; chan < ve; chan++) {
2324 if (indir_index) {
2325 unsigned count = glsl_count_attribute_slots(
2326 instr->variables[0]->var->type, false);
2327 count -= chan / 4;
2328 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2329 &ctx->ac, ctx->locals + idx + chan, count,
2330 4, true);
2331
2332 values[chan] = LLVMBuildExtractElement(ctx->builder,
2333 tmp_vec,
2334 indir_index, "");
2335 } else {
2336 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2337 }
2338 }
2339 break;
2340 case nir_var_shader_out:
2341 for (unsigned chan = 0; chan < ve; chan++) {
2342 if (indir_index) {
2343 unsigned count = glsl_count_attribute_slots(
2344 instr->variables[0]->var->type, false);
2345 count -= chan / 4;
2346 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2347 &ctx->ac, ctx->outputs + idx + chan, count,
2348 4, true);
2349
2350 values[chan] = LLVMBuildExtractElement(ctx->builder,
2351 tmp_vec,
2352 indir_index, "");
2353 } else {
2354 values[chan] = LLVMBuildLoad(ctx->builder,
2355 ctx->outputs[idx + chan + const_index * 4],
2356 "");
2357 }
2358 }
2359 break;
2360 case nir_var_shared: {
2361 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2362 LLVMValueRef derived_ptr;
2363
2364 if (indir_index)
2365 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2366
2367 for (unsigned chan = 0; chan < ve; chan++) {
2368 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2369 if (indir_index)
2370 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2371 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2372
2373 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2374 }
2375 break;
2376 }
2377 default:
2378 unreachable("unhandle variable mode");
2379 }
2380 ret = ac_build_gather_values(&ctx->ac, values, ve);
2381 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2382 }
2383
2384 static void
2385 visit_store_var(struct nir_to_llvm_context *ctx,
2386 nir_intrinsic_instr *instr)
2387 {
2388 LLVMValueRef temp_ptr, value;
2389 int idx = instr->variables[0]->var->data.driver_location;
2390 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2391 int writemask = instr->const_index[0];
2392 LLVMValueRef indir_index;
2393 unsigned const_index;
2394 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2395 NULL, &const_index, &indir_index);
2396
2397 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2398 int old_writemask = writemask;
2399
2400 src = LLVMBuildBitCast(ctx->builder, src,
2401 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2402 "");
2403
2404 writemask = 0;
2405 for (unsigned chan = 0; chan < 4; chan++) {
2406 if (old_writemask & (1 << chan))
2407 writemask |= 3u << (2 * chan);
2408 }
2409 }
2410
2411 switch (instr->variables[0]->var->data.mode) {
2412 case nir_var_shader_out:
2413 for (unsigned chan = 0; chan < 8; chan++) {
2414 int stride = 4;
2415 if (!(writemask & (1 << chan)))
2416 continue;
2417
2418 value = llvm_extract_elem(ctx, src, chan);
2419
2420 if (instr->variables[0]->var->data.compact)
2421 stride = 1;
2422 if (indir_index) {
2423 unsigned count = glsl_count_attribute_slots(
2424 instr->variables[0]->var->type, false);
2425 count -= chan / 4;
2426 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2427 &ctx->ac, ctx->outputs + idx + chan, count,
2428 stride, true);
2429
2430 if (get_llvm_num_components(tmp_vec) > 1) {
2431 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2432 value, indir_index, "");
2433 } else
2434 tmp_vec = value;
2435 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2436 count, stride, tmp_vec);
2437
2438 } else {
2439 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2440
2441 LLVMBuildStore(ctx->builder, value, temp_ptr);
2442 }
2443 }
2444 break;
2445 case nir_var_local:
2446 for (unsigned chan = 0; chan < 8; chan++) {
2447 if (!(writemask & (1 << chan)))
2448 continue;
2449
2450 value = llvm_extract_elem(ctx, src, chan);
2451 if (indir_index) {
2452 unsigned count = glsl_count_attribute_slots(
2453 instr->variables[0]->var->type, false);
2454 count -= chan / 4;
2455 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2456 &ctx->ac, ctx->locals + idx + chan, count,
2457 4, true);
2458
2459 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2460 value, indir_index, "");
2461 build_store_values_extended(ctx, ctx->locals + idx + chan,
2462 count, 4, tmp_vec);
2463 } else {
2464 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2465
2466 LLVMBuildStore(ctx->builder, value, temp_ptr);
2467 }
2468 }
2469 break;
2470 case nir_var_shared: {
2471 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2472
2473 if (indir_index)
2474 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2475
2476 for (unsigned chan = 0; chan < 8; chan++) {
2477 if (!(writemask & (1 << chan)))
2478 continue;
2479 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2480 LLVMValueRef derived_ptr;
2481
2482 if (indir_index)
2483 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2484
2485 value = llvm_extract_elem(ctx, src, chan);
2486 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2487 LLVMBuildStore(ctx->builder,
2488 to_integer(ctx, value), derived_ptr);
2489 }
2490 break;
2491 }
2492 default:
2493 break;
2494 }
2495 }
2496
2497 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2498 {
2499 switch (dim) {
2500 case GLSL_SAMPLER_DIM_BUF:
2501 return 1;
2502 case GLSL_SAMPLER_DIM_1D:
2503 return array ? 2 : 1;
2504 case GLSL_SAMPLER_DIM_2D:
2505 return array ? 3 : 2;
2506 case GLSL_SAMPLER_DIM_MS:
2507 return array ? 4 : 3;
2508 case GLSL_SAMPLER_DIM_3D:
2509 case GLSL_SAMPLER_DIM_CUBE:
2510 return 3;
2511 case GLSL_SAMPLER_DIM_RECT:
2512 case GLSL_SAMPLER_DIM_SUBPASS:
2513 return 2;
2514 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2515 return 3;
2516 default:
2517 break;
2518 }
2519 return 0;
2520 }
2521
2522
2523
2524 /* Adjust the sample index according to FMASK.
2525 *
2526 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2527 * which is the identity mapping. Each nibble says which physical sample
2528 * should be fetched to get that sample.
2529 *
2530 * For example, 0x11111100 means there are only 2 samples stored and
2531 * the second sample covers 3/4 of the pixel. When reading samples 0
2532 * and 1, return physical sample 0 (determined by the first two 0s
2533 * in FMASK), otherwise return physical sample 1.
2534 *
2535 * The sample index should be adjusted as follows:
2536 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2537 */
2538 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
2539 LLVMValueRef coord_x, LLVMValueRef coord_y,
2540 LLVMValueRef coord_z,
2541 LLVMValueRef sample_index,
2542 LLVMValueRef fmask_desc_ptr)
2543 {
2544 LLVMValueRef fmask_load_address[4];
2545 LLVMValueRef res;
2546
2547 fmask_load_address[0] = coord_x;
2548 fmask_load_address[1] = coord_y;
2549 if (coord_z) {
2550 fmask_load_address[2] = coord_z;
2551 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
2552 }
2553
2554 struct ac_image_args args = {0};
2555
2556 args.opcode = ac_image_load;
2557 args.da = coord_z ? true : false;
2558 args.resource = fmask_desc_ptr;
2559 args.dmask = 0xf;
2560 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
2561
2562 res = ac_build_image_opcode(&ctx->ac, &args);
2563
2564 res = to_integer(ctx, res);
2565 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
2566 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
2567
2568 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
2569 res,
2570 ctx->i32zero, "");
2571
2572 LLVMValueRef sample_index4 =
2573 LLVMBuildMul(ctx->builder, sample_index, four, "");
2574 LLVMValueRef shifted_fmask =
2575 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
2576 LLVMValueRef final_sample =
2577 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
2578
2579 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2580 * resource descriptor is 0 (invalid),
2581 */
2582 LLVMValueRef fmask_desc =
2583 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
2584 ctx->v8i32, "");
2585
2586 LLVMValueRef fmask_word1 =
2587 LLVMBuildExtractElement(ctx->builder, fmask_desc,
2588 ctx->i32one, "");
2589
2590 LLVMValueRef word1_is_nonzero =
2591 LLVMBuildICmp(ctx->builder, LLVMIntNE,
2592 fmask_word1, ctx->i32zero, "");
2593
2594 /* Replace the MSAA sample index. */
2595 sample_index =
2596 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
2597 final_sample, sample_index, "");
2598 return sample_index;
2599 }
2600
2601 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2602 nir_intrinsic_instr *instr)
2603 {
2604 const struct glsl_type *type = instr->variables[0]->var->type;
2605 if(instr->variables[0]->deref.child)
2606 type = instr->variables[0]->deref.child->type;
2607
2608 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2609 LLVMValueRef coords[4];
2610 LLVMValueRef masks[] = {
2611 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2612 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2613 };
2614 LLVMValueRef res;
2615 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2616
2617 int count;
2618 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2619 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2620 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2621 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2622 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2623
2624 count = image_type_to_components_count(dim,
2625 glsl_sampler_type_is_array(type));
2626
2627 if (is_ms) {
2628 LLVMValueRef fmask_load_address[3];
2629 int chan;
2630
2631 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2632 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
2633 if (glsl_sampler_type_is_array(type))
2634 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
2635 else
2636 fmask_load_address[2] = NULL;
2637 if (add_frag_pos) {
2638 for (chan = 0; chan < 2; ++chan)
2639 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2640 }
2641 sample_index = adjust_sample_index_using_fmask(ctx,
2642 fmask_load_address[0],
2643 fmask_load_address[1],
2644 fmask_load_address[2],
2645 sample_index,
2646 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
2647 }
2648 if (count == 1) {
2649 if (instr->src[0].ssa->num_components)
2650 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2651 else
2652 res = src0;
2653 } else {
2654 int chan;
2655 if (is_ms)
2656 count--;
2657 for (chan = 0; chan < count; ++chan) {
2658 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2659 }
2660
2661 if (add_frag_pos) {
2662 for (chan = 0; chan < count; ++chan)
2663 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2664 }
2665 if (is_ms) {
2666 coords[count] = sample_index;
2667 count++;
2668 }
2669
2670 if (count == 3) {
2671 coords[3] = LLVMGetUndef(ctx->i32);
2672 count = 4;
2673 }
2674 res = ac_build_gather_values(&ctx->ac, coords, count);
2675 }
2676 return res;
2677 }
2678
2679 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2680 nir_intrinsic_instr *instr)
2681 {
2682 LLVMValueRef params[7];
2683 LLVMValueRef res;
2684 char intrinsic_name[64];
2685 const nir_variable *var = instr->variables[0]->var;
2686 const struct glsl_type *type = var->type;
2687 if(instr->variables[0]->deref.child)
2688 type = instr->variables[0]->deref.child->type;
2689
2690 type = glsl_without_array(type);
2691 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2692 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2693 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2694 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2695 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2696 params[3] = ctx->i1false; /* glc */
2697 params[4] = ctx->i1false; /* slc */
2698 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2699 params, 5, 0);
2700
2701 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2702 res = to_integer(ctx, res);
2703 } else {
2704 bool is_da = glsl_sampler_type_is_array(type) ||
2705 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2706 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
2707 LLVMValueRef glc = ctx->i1false;
2708 LLVMValueRef slc = ctx->i1false;
2709
2710 params[0] = get_image_coords(ctx, instr);
2711 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2712 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2713 if (HAVE_LLVM <= 0x0309) {
2714 params[3] = ctx->i1false; /* r128 */
2715 params[4] = da;
2716 params[5] = glc;
2717 params[6] = slc;
2718 } else {
2719 LLVMValueRef lwe = ctx->i1false;
2720 params[3] = glc;
2721 params[4] = slc;
2722 params[5] = lwe;
2723 params[6] = da;
2724 }
2725
2726 ac_get_image_intr_name("llvm.amdgcn.image.load",
2727 ctx->v4f32, /* vdata */
2728 LLVMTypeOf(params[0]), /* coords */
2729 LLVMTypeOf(params[1]), /* rsrc */
2730 intrinsic_name, sizeof(intrinsic_name));
2731
2732 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2733 params, 7, AC_FUNC_ATTR_READONLY);
2734 }
2735 return to_integer(ctx, res);
2736 }
2737
2738 static void visit_image_store(struct nir_to_llvm_context *ctx,
2739 nir_intrinsic_instr *instr)
2740 {
2741 LLVMValueRef params[8];
2742 char intrinsic_name[64];
2743 const nir_variable *var = instr->variables[0]->var;
2744 const struct glsl_type *type = glsl_without_array(var->type);
2745
2746 if (ctx->stage == MESA_SHADER_FRAGMENT)
2747 ctx->shader_info->fs.writes_memory = true;
2748
2749 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2750 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2751 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2752 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2753 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2754 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2755 params[4] = ctx->i1false; /* glc */
2756 params[5] = ctx->i1false; /* slc */
2757 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2758 params, 6, 0);
2759 } else {
2760 bool is_da = glsl_sampler_type_is_array(type) ||
2761 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2762 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
2763 LLVMValueRef glc = ctx->i1false;
2764 LLVMValueRef slc = ctx->i1false;
2765
2766 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2767 params[1] = get_image_coords(ctx, instr); /* coords */
2768 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2769 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2770 if (HAVE_LLVM <= 0x0309) {
2771 params[4] = ctx->i1false; /* r128 */
2772 params[5] = da;
2773 params[6] = glc;
2774 params[7] = slc;
2775 } else {
2776 LLVMValueRef lwe = ctx->i1false;
2777 params[4] = glc;
2778 params[5] = slc;
2779 params[6] = lwe;
2780 params[7] = da;
2781 }
2782
2783 ac_get_image_intr_name("llvm.amdgcn.image.store",
2784 LLVMTypeOf(params[0]), /* vdata */
2785 LLVMTypeOf(params[1]), /* coords */
2786 LLVMTypeOf(params[2]), /* rsrc */
2787 intrinsic_name, sizeof(intrinsic_name));
2788
2789 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2790 params, 8, 0);
2791 }
2792
2793 }
2794
2795 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2796 nir_intrinsic_instr *instr)
2797 {
2798 LLVMValueRef params[6];
2799 int param_count = 0;
2800 const nir_variable *var = instr->variables[0]->var;
2801
2802 const char *base_name = "llvm.amdgcn.image.atomic";
2803 const char *atomic_name;
2804 LLVMValueRef coords;
2805 char intrinsic_name[32], coords_type[8];
2806 const struct glsl_type *type = glsl_without_array(var->type);
2807
2808 if (ctx->stage == MESA_SHADER_FRAGMENT)
2809 ctx->shader_info->fs.writes_memory = true;
2810
2811 params[param_count++] = get_src(ctx, instr->src[2]);
2812 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2813 params[param_count++] = get_src(ctx, instr->src[3]);
2814
2815 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2816 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2817 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2818 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2819 params[param_count++] = ctx->i32zero; /* voffset */
2820 params[param_count++] = ctx->i1false; /* glc */
2821 params[param_count++] = ctx->i1false; /* slc */
2822 } else {
2823 bool da = glsl_sampler_type_is_array(type) ||
2824 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2825
2826 coords = params[param_count++] = get_image_coords(ctx, instr);
2827 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2828 params[param_count++] = ctx->i1false; /* r128 */
2829 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
2830 params[param_count++] = ctx->i1false; /* slc */
2831 }
2832
2833 switch (instr->intrinsic) {
2834 case nir_intrinsic_image_atomic_add:
2835 atomic_name = "add";
2836 break;
2837 case nir_intrinsic_image_atomic_min:
2838 atomic_name = "smin";
2839 break;
2840 case nir_intrinsic_image_atomic_max:
2841 atomic_name = "smax";
2842 break;
2843 case nir_intrinsic_image_atomic_and:
2844 atomic_name = "and";
2845 break;
2846 case nir_intrinsic_image_atomic_or:
2847 atomic_name = "or";
2848 break;
2849 case nir_intrinsic_image_atomic_xor:
2850 atomic_name = "xor";
2851 break;
2852 case nir_intrinsic_image_atomic_exchange:
2853 atomic_name = "swap";
2854 break;
2855 case nir_intrinsic_image_atomic_comp_swap:
2856 atomic_name = "cmpswap";
2857 break;
2858 default:
2859 abort();
2860 }
2861 build_int_type_name(LLVMTypeOf(coords),
2862 coords_type, sizeof(coords_type));
2863
2864 snprintf(intrinsic_name, sizeof(intrinsic_name),
2865 "%s.%s.%s", base_name, atomic_name, coords_type);
2866 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2867 }
2868
2869 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2870 nir_intrinsic_instr *instr)
2871 {
2872 LLVMValueRef res;
2873 const nir_variable *var = instr->variables[0]->var;
2874 const struct glsl_type *type = instr->variables[0]->var->type;
2875 bool da = glsl_sampler_type_is_array(var->type) ||
2876 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2877 if(instr->variables[0]->deref.child)
2878 type = instr->variables[0]->deref.child->type;
2879
2880 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2881 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2882
2883 struct ac_image_args args = { 0 };
2884
2885 args.da = da;
2886 args.dmask = 0xf;
2887 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2888 args.opcode = ac_image_get_resinfo;
2889 args.addr = ctx->i32zero;
2890
2891 res = ac_build_image_opcode(&ctx->ac, &args);
2892
2893 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2894 glsl_sampler_type_is_array(type)) {
2895 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2896 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2897 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2898 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2899 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2900 }
2901 return res;
2902 }
2903
2904 #define NOOP_WAITCNT 0xf7f
2905 #define LGKM_CNT 0x07f
2906 #define VM_CNT 0xf70
2907
2908 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
2909 unsigned simm16)
2910 {
2911 LLVMValueRef args[1] = {
2912 LLVMConstInt(ctx->i32, simm16, false),
2913 };
2914 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2915 ctx->voidt, args, 1, 0);
2916 }
2917
2918 static void emit_barrier(struct nir_to_llvm_context *ctx)
2919 {
2920 // TODO tess
2921 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2922 ctx->voidt, NULL, 0, 0);
2923 }
2924
2925 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2926 nir_intrinsic_instr *instr)
2927 {
2928 LLVMValueRef cond;
2929 ctx->shader_info->fs.can_discard = true;
2930
2931 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2932 get_src(ctx, instr->src[0]),
2933 ctx->i32zero, "");
2934
2935 cond = LLVMBuildSelect(ctx->builder, cond,
2936 LLVMConstReal(ctx->f32, -1.0f),
2937 ctx->f32zero, "");
2938 ac_build_kill(&ctx->ac, cond);
2939 }
2940
2941 static LLVMValueRef
2942 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2943 {
2944 LLVMValueRef result;
2945 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2946 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2947 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2948
2949 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2950 }
2951
2952 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2953 nir_intrinsic_instr *instr)
2954 {
2955 LLVMValueRef ptr, result;
2956 int idx = instr->variables[0]->var->data.driver_location;
2957 LLVMValueRef src = get_src(ctx, instr->src[0]);
2958 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2959
2960 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2961 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2962 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2963 ptr, src, src1,
2964 LLVMAtomicOrderingSequentiallyConsistent,
2965 LLVMAtomicOrderingSequentiallyConsistent,
2966 false);
2967 } else {
2968 LLVMAtomicRMWBinOp op;
2969 switch (instr->intrinsic) {
2970 case nir_intrinsic_var_atomic_add:
2971 op = LLVMAtomicRMWBinOpAdd;
2972 break;
2973 case nir_intrinsic_var_atomic_umin:
2974 op = LLVMAtomicRMWBinOpUMin;
2975 break;
2976 case nir_intrinsic_var_atomic_umax:
2977 op = LLVMAtomicRMWBinOpUMax;
2978 break;
2979 case nir_intrinsic_var_atomic_imin:
2980 op = LLVMAtomicRMWBinOpMin;
2981 break;
2982 case nir_intrinsic_var_atomic_imax:
2983 op = LLVMAtomicRMWBinOpMax;
2984 break;
2985 case nir_intrinsic_var_atomic_and:
2986 op = LLVMAtomicRMWBinOpAnd;
2987 break;
2988 case nir_intrinsic_var_atomic_or:
2989 op = LLVMAtomicRMWBinOpOr;
2990 break;
2991 case nir_intrinsic_var_atomic_xor:
2992 op = LLVMAtomicRMWBinOpXor;
2993 break;
2994 case nir_intrinsic_var_atomic_exchange:
2995 op = LLVMAtomicRMWBinOpXchg;
2996 break;
2997 default:
2998 return NULL;
2999 }
3000
3001 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3002 LLVMAtomicOrderingSequentiallyConsistent,
3003 false);
3004 }
3005 return result;
3006 }
3007
3008 #define INTERP_CENTER 0
3009 #define INTERP_CENTROID 1
3010 #define INTERP_SAMPLE 2
3011
3012 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3013 enum glsl_interp_mode interp, unsigned location)
3014 {
3015 switch (interp) {
3016 case INTERP_MODE_FLAT:
3017 default:
3018 return NULL;
3019 case INTERP_MODE_SMOOTH:
3020 case INTERP_MODE_NONE:
3021 if (location == INTERP_CENTER)
3022 return ctx->persp_center;
3023 else if (location == INTERP_CENTROID)
3024 return ctx->persp_centroid;
3025 else if (location == INTERP_SAMPLE)
3026 return ctx->persp_sample;
3027 break;
3028 case INTERP_MODE_NOPERSPECTIVE:
3029 if (location == INTERP_CENTER)
3030 return ctx->linear_center;
3031 else if (location == INTERP_CENTROID)
3032 return ctx->linear_centroid;
3033 else if (location == INTERP_SAMPLE)
3034 return ctx->linear_sample;
3035 break;
3036 }
3037 return NULL;
3038 }
3039
3040 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3041 LLVMValueRef sample_id)
3042 {
3043 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
3044 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
3045 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
3046 LLVMValueRef result[2];
3047
3048 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
3049 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
3050
3051 return ac_build_gather_values(&ctx->ac, result, 2);
3052 }
3053
3054 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3055 {
3056 LLVMValueRef values[2];
3057
3058 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3059 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3060 return ac_build_gather_values(&ctx->ac, values, 2);
3061 }
3062
3063 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3064 nir_intrinsic_instr *instr)
3065 {
3066 LLVMValueRef result[2];
3067 LLVMValueRef interp_param, attr_number;
3068 unsigned location;
3069 unsigned chan;
3070 LLVMValueRef src_c0, src_c1;
3071 LLVMValueRef src0;
3072 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3073 switch (instr->intrinsic) {
3074 case nir_intrinsic_interp_var_at_centroid:
3075 location = INTERP_CENTROID;
3076 break;
3077 case nir_intrinsic_interp_var_at_sample:
3078 location = INTERP_SAMPLE;
3079 src0 = get_src(ctx, instr->src[0]);
3080 break;
3081 case nir_intrinsic_interp_var_at_offset:
3082 location = INTERP_CENTER;
3083 src0 = get_src(ctx, instr->src[0]);
3084 default:
3085 break;
3086 }
3087
3088 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3089 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3090 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3091 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3092 LLVMValueRef sample_position;
3093 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3094
3095 /* fetch sample ID */
3096 sample_position = load_sample_position(ctx, src0);
3097
3098 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3099 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3100 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3101 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3102 }
3103 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3104 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3105
3106 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3107 LLVMValueRef ij_out[2];
3108 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3109
3110 /*
3111 * take the I then J parameters, and the DDX/Y for it, and
3112 * calculate the IJ inputs for the interpolator.
3113 * temp1 = ddx * offset/sample.x + I;
3114 * interp_param.I = ddy * offset/sample.y + temp1;
3115 * temp1 = ddx * offset/sample.x + J;
3116 * interp_param.J = ddy * offset/sample.y + temp1;
3117 */
3118 for (unsigned i = 0; i < 2; i++) {
3119 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3120 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3121 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3122 ddxy_out, ix_ll, "");
3123 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3124 ddxy_out, iy_ll, "");
3125 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3126 interp_param, ix_ll, "");
3127 LLVMValueRef temp1, temp2;
3128
3129 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3130 ctx->f32, "");
3131
3132 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3133 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3134
3135 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3136 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3137
3138 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3139 temp2, ctx->i32, "");
3140 }
3141 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3142
3143 }
3144
3145 for (chan = 0; chan < 2; chan++) {
3146 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3147
3148 if (interp_param) {
3149 interp_param = LLVMBuildBitCast(ctx->builder,
3150 interp_param, LLVMVectorType(ctx->f32, 2), "");
3151 LLVMValueRef i = LLVMBuildExtractElement(
3152 ctx->builder, interp_param, ctx->i32zero, "");
3153 LLVMValueRef j = LLVMBuildExtractElement(
3154 ctx->builder, interp_param, ctx->i32one, "");
3155
3156 result[chan] = ac_build_fs_interp(&ctx->ac,
3157 llvm_chan, attr_number,
3158 ctx->prim_mask, i, j);
3159 } else {
3160 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3161 LLVMConstInt(ctx->i32, 2, false),
3162 llvm_chan, attr_number,
3163 ctx->prim_mask);
3164 }
3165 }
3166 return ac_build_gather_values(&ctx->ac, result, 2);
3167 }
3168
3169 static void
3170 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3171 nir_intrinsic_instr *instr)
3172 {
3173 LLVMValueRef gs_next_vertex;
3174 LLVMValueRef can_emit, kill;
3175 int idx;
3176
3177 assert(instr->const_index[0] == 0);
3178 /* Write vertex attribute values to GSVS ring */
3179 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3180 ctx->gs_next_vertex,
3181 "");
3182
3183 /* If this thread has already emitted the declared maximum number of
3184 * vertices, kill it: excessive vertex emissions are not supposed to
3185 * have any effect, and GS threads have no externally observable
3186 * effects other than emitting vertices.
3187 */
3188 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3189 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3190
3191 kill = LLVMBuildSelect(ctx->builder, can_emit,
3192 LLVMConstReal(ctx->f32, 1.0f),
3193 LLVMConstReal(ctx->f32, -1.0f), "");
3194 ac_build_kill(&ctx->ac, kill);
3195
3196 /* loop num outputs */
3197 idx = 0;
3198 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3199 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3200 int length = 4;
3201 int slot = idx;
3202 int slot_inc = 1;
3203
3204 if (!(ctx->output_mask & (1ull << i)))
3205 continue;
3206
3207 if (i == VARYING_SLOT_CLIP_DIST0) {
3208 /* pack clip and cull into a single set of slots */
3209 length = ctx->num_output_clips + ctx->num_output_culls;
3210 if (length > 4)
3211 slot_inc = 2;
3212 }
3213 for (unsigned j = 0; j < length; j++) {
3214 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3215 out_ptr[j], "");
3216 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3217 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3218 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3219
3220 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3221
3222 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3223 out_val, 1,
3224 voffset, ctx->gs2vs_offset, 0,
3225 1, 1, true, true);
3226 }
3227 idx += slot_inc;
3228 }
3229
3230 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3231 ctx->i32one, "");
3232 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3233
3234 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3235 }
3236
3237 static void
3238 visit_end_primitive(struct nir_to_llvm_context *ctx,
3239 nir_intrinsic_instr *instr)
3240 {
3241 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3242 }
3243
3244 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3245 nir_intrinsic_instr *instr)
3246 {
3247 LLVMValueRef result = NULL;
3248
3249 switch (instr->intrinsic) {
3250 case nir_intrinsic_load_work_group_id: {
3251 result = ctx->workgroup_ids;
3252 break;
3253 }
3254 case nir_intrinsic_load_base_vertex: {
3255 result = ctx->base_vertex;
3256 break;
3257 }
3258 case nir_intrinsic_load_vertex_id_zero_base: {
3259 result = ctx->vertex_id;
3260 break;
3261 }
3262 case nir_intrinsic_load_local_invocation_id: {
3263 result = ctx->local_invocation_ids;
3264 break;
3265 }
3266 case nir_intrinsic_load_base_instance:
3267 result = ctx->start_instance;
3268 break;
3269 case nir_intrinsic_load_draw_id:
3270 result = ctx->draw_index;
3271 break;
3272 case nir_intrinsic_load_invocation_id:
3273 result = ctx->gs_invocation_id;
3274 break;
3275 case nir_intrinsic_load_primitive_id:
3276 if (ctx->stage == MESA_SHADER_GEOMETRY)
3277 result = ctx->gs_prim_id;
3278 else
3279 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3280 break;
3281 case nir_intrinsic_load_sample_id:
3282 ctx->shader_info->fs.force_persample = true;
3283 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3284 break;
3285 case nir_intrinsic_load_sample_pos:
3286 ctx->shader_info->fs.force_persample = true;
3287 result = load_sample_pos(ctx);
3288 break;
3289 case nir_intrinsic_load_sample_mask_in:
3290 result = ctx->sample_coverage;
3291 break;
3292 case nir_intrinsic_load_front_face:
3293 result = ctx->front_face;
3294 break;
3295 case nir_intrinsic_load_instance_id:
3296 result = ctx->instance_id;
3297 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3298 ctx->shader_info->vs.vgpr_comp_cnt);
3299 break;
3300 case nir_intrinsic_load_num_work_groups:
3301 result = ctx->num_work_groups;
3302 break;
3303 case nir_intrinsic_load_local_invocation_index:
3304 result = visit_load_local_invocation_index(ctx);
3305 break;
3306 case nir_intrinsic_load_push_constant:
3307 result = visit_load_push_constant(ctx, instr);
3308 break;
3309 case nir_intrinsic_vulkan_resource_index:
3310 result = visit_vulkan_resource_index(ctx, instr);
3311 break;
3312 case nir_intrinsic_store_ssbo:
3313 visit_store_ssbo(ctx, instr);
3314 break;
3315 case nir_intrinsic_load_ssbo:
3316 result = visit_load_buffer(ctx, instr);
3317 break;
3318 case nir_intrinsic_ssbo_atomic_add:
3319 case nir_intrinsic_ssbo_atomic_imin:
3320 case nir_intrinsic_ssbo_atomic_umin:
3321 case nir_intrinsic_ssbo_atomic_imax:
3322 case nir_intrinsic_ssbo_atomic_umax:
3323 case nir_intrinsic_ssbo_atomic_and:
3324 case nir_intrinsic_ssbo_atomic_or:
3325 case nir_intrinsic_ssbo_atomic_xor:
3326 case nir_intrinsic_ssbo_atomic_exchange:
3327 case nir_intrinsic_ssbo_atomic_comp_swap:
3328 result = visit_atomic_ssbo(ctx, instr);
3329 break;
3330 case nir_intrinsic_load_ubo:
3331 result = visit_load_ubo_buffer(ctx, instr);
3332 break;
3333 case nir_intrinsic_get_buffer_size:
3334 result = visit_get_buffer_size(ctx, instr);
3335 break;
3336 case nir_intrinsic_load_var:
3337 result = visit_load_var(ctx, instr);
3338 break;
3339 case nir_intrinsic_store_var:
3340 visit_store_var(ctx, instr);
3341 break;
3342 case nir_intrinsic_image_load:
3343 result = visit_image_load(ctx, instr);
3344 break;
3345 case nir_intrinsic_image_store:
3346 visit_image_store(ctx, instr);
3347 break;
3348 case nir_intrinsic_image_atomic_add:
3349 case nir_intrinsic_image_atomic_min:
3350 case nir_intrinsic_image_atomic_max:
3351 case nir_intrinsic_image_atomic_and:
3352 case nir_intrinsic_image_atomic_or:
3353 case nir_intrinsic_image_atomic_xor:
3354 case nir_intrinsic_image_atomic_exchange:
3355 case nir_intrinsic_image_atomic_comp_swap:
3356 result = visit_image_atomic(ctx, instr);
3357 break;
3358 case nir_intrinsic_image_size:
3359 result = visit_image_size(ctx, instr);
3360 break;
3361 case nir_intrinsic_discard:
3362 ctx->shader_info->fs.can_discard = true;
3363 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3364 ctx->voidt,
3365 NULL, 0, AC_FUNC_ATTR_LEGACY);
3366 break;
3367 case nir_intrinsic_discard_if:
3368 emit_discard_if(ctx, instr);
3369 break;
3370 case nir_intrinsic_memory_barrier:
3371 emit_waitcnt(ctx, VM_CNT);
3372 break;
3373 case nir_intrinsic_barrier:
3374 emit_barrier(ctx);
3375 break;
3376 case nir_intrinsic_var_atomic_add:
3377 case nir_intrinsic_var_atomic_imin:
3378 case nir_intrinsic_var_atomic_umin:
3379 case nir_intrinsic_var_atomic_imax:
3380 case nir_intrinsic_var_atomic_umax:
3381 case nir_intrinsic_var_atomic_and:
3382 case nir_intrinsic_var_atomic_or:
3383 case nir_intrinsic_var_atomic_xor:
3384 case nir_intrinsic_var_atomic_exchange:
3385 case nir_intrinsic_var_atomic_comp_swap:
3386 result = visit_var_atomic(ctx, instr);
3387 break;
3388 case nir_intrinsic_interp_var_at_centroid:
3389 case nir_intrinsic_interp_var_at_sample:
3390 case nir_intrinsic_interp_var_at_offset:
3391 result = visit_interp(ctx, instr);
3392 break;
3393 case nir_intrinsic_emit_vertex:
3394 visit_emit_vertex(ctx, instr);
3395 break;
3396 case nir_intrinsic_end_primitive:
3397 visit_end_primitive(ctx, instr);
3398 break;
3399 default:
3400 fprintf(stderr, "Unknown intrinsic: ");
3401 nir_print_instr(&instr->instr, stderr);
3402 fprintf(stderr, "\n");
3403 break;
3404 }
3405 if (result) {
3406 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3407 }
3408 }
3409
3410 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3411 nir_deref_var *deref,
3412 enum desc_type desc_type)
3413 {
3414 unsigned desc_set = deref->var->data.descriptor_set;
3415 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3416 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3417 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3418 unsigned offset = binding->offset;
3419 unsigned stride = binding->size;
3420 unsigned type_size;
3421 LLVMBuilderRef builder = ctx->builder;
3422 LLVMTypeRef type;
3423 LLVMValueRef index = NULL;
3424 unsigned constant_index = 0;
3425
3426 assert(deref->var->data.binding < layout->binding_count);
3427
3428 switch (desc_type) {
3429 case DESC_IMAGE:
3430 type = ctx->v8i32;
3431 type_size = 32;
3432 break;
3433 case DESC_FMASK:
3434 type = ctx->v8i32;
3435 offset += 32;
3436 type_size = 32;
3437 break;
3438 case DESC_SAMPLER:
3439 type = ctx->v4i32;
3440 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3441 offset += 64;
3442
3443 type_size = 16;
3444 break;
3445 case DESC_BUFFER:
3446 type = ctx->v4i32;
3447 type_size = 16;
3448 break;
3449 default:
3450 unreachable("invalid desc_type\n");
3451 }
3452
3453 if (deref->deref.child) {
3454 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3455
3456 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3457 offset += child->base_offset * stride;
3458 if (child->deref_array_type == nir_deref_array_type_indirect) {
3459 index = get_src(ctx, child->indirect);
3460 }
3461
3462 constant_index = child->base_offset;
3463 }
3464 if (desc_type == DESC_SAMPLER && binding->immutable_samplers &&
3465 (!index || binding->immutable_samplers_equal)) {
3466 if (binding->immutable_samplers_equal)
3467 constant_index = 0;
3468
3469 LLVMValueRef constants[] = {
3470 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 0], 0),
3471 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 1], 0),
3472 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 2], 0),
3473 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 3], 0),
3474 };
3475 return ac_build_gather_values(&ctx->ac, constants, 4);
3476 }
3477
3478 assert(stride % type_size == 0);
3479
3480 if (!index)
3481 index = ctx->i32zero;
3482
3483 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3484
3485 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3486 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3487
3488 return ac_build_indexed_load_const(&ctx->ac, list, index);
3489 }
3490
3491 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3492 struct ac_image_args *args,
3493 nir_tex_instr *instr,
3494 nir_texop op,
3495 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3496 LLVMValueRef *param, unsigned count,
3497 unsigned dmask)
3498 {
3499 unsigned is_rect = 0;
3500 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3501
3502 if (op == nir_texop_lod)
3503 da = false;
3504 /* Pad to power of two vector */
3505 while (count < util_next_power_of_two(count))
3506 param[count++] = LLVMGetUndef(ctx->i32);
3507
3508 if (count > 1)
3509 args->addr = ac_build_gather_values(&ctx->ac, param, count);
3510 else
3511 args->addr = param[0];
3512
3513 args->resource = res_ptr;
3514 args->sampler = samp_ptr;
3515
3516 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3517 args->addr = param[0];
3518 return;
3519 }
3520
3521 args->dmask = dmask;
3522 args->unorm = is_rect;
3523 args->da = da;
3524 }
3525
3526 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3527 *
3528 * SI-CI:
3529 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3530 * filtering manually. The driver sets img7 to a mask clearing
3531 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3532 * s_and_b32 samp0, samp0, img7
3533 *
3534 * VI:
3535 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3536 */
3537 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3538 LLVMValueRef res, LLVMValueRef samp)
3539 {
3540 LLVMBuilderRef builder = ctx->builder;
3541 LLVMValueRef img7, samp0;
3542
3543 if (ctx->options->chip_class >= VI)
3544 return samp;
3545
3546 img7 = LLVMBuildExtractElement(builder, res,
3547 LLVMConstInt(ctx->i32, 7, 0), "");
3548 samp0 = LLVMBuildExtractElement(builder, samp,
3549 LLVMConstInt(ctx->i32, 0, 0), "");
3550 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3551 return LLVMBuildInsertElement(builder, samp, samp0,
3552 LLVMConstInt(ctx->i32, 0, 0), "");
3553 }
3554
3555 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3556 nir_tex_instr *instr,
3557 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3558 LLVMValueRef *fmask_ptr)
3559 {
3560 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3561 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3562 else
3563 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3564 if (samp_ptr) {
3565 if (instr->sampler)
3566 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3567 else
3568 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3569 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3570 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3571 }
3572 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3573 instr->op == nir_texop_samples_identical))
3574 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3575 }
3576
3577 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3578 LLVMValueRef coord)
3579 {
3580 coord = to_float(ctx, coord);
3581 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3582 coord = to_integer(ctx, coord);
3583 return coord;
3584 }
3585
3586 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3587 {
3588 LLVMValueRef result = NULL;
3589 struct ac_image_args args = { 0 };
3590 unsigned dmask = 0xf;
3591 LLVMValueRef address[16];
3592 LLVMValueRef coords[5];
3593 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3594 LLVMValueRef bias = NULL, offsets = NULL;
3595 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3596 LLVMValueRef ddx = NULL, ddy = NULL;
3597 LLVMValueRef derivs[6];
3598 unsigned chan, count = 0;
3599 unsigned const_src = 0, num_deriv_comp = 0;
3600
3601 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3602
3603 for (unsigned i = 0; i < instr->num_srcs; i++) {
3604 switch (instr->src[i].src_type) {
3605 case nir_tex_src_coord:
3606 coord = get_src(ctx, instr->src[i].src);
3607 break;
3608 case nir_tex_src_projector:
3609 break;
3610 case nir_tex_src_comparator:
3611 comparator = get_src(ctx, instr->src[i].src);
3612 break;
3613 case nir_tex_src_offset:
3614 offsets = get_src(ctx, instr->src[i].src);
3615 const_src = i;
3616 break;
3617 case nir_tex_src_bias:
3618 bias = get_src(ctx, instr->src[i].src);
3619 break;
3620 case nir_tex_src_lod:
3621 lod = get_src(ctx, instr->src[i].src);
3622 break;
3623 case nir_tex_src_ms_index:
3624 sample_index = get_src(ctx, instr->src[i].src);
3625 break;
3626 case nir_tex_src_ms_mcs:
3627 break;
3628 case nir_tex_src_ddx:
3629 ddx = get_src(ctx, instr->src[i].src);
3630 num_deriv_comp = instr->src[i].src.ssa->num_components;
3631 break;
3632 case nir_tex_src_ddy:
3633 ddy = get_src(ctx, instr->src[i].src);
3634 break;
3635 case nir_tex_src_texture_offset:
3636 case nir_tex_src_sampler_offset:
3637 case nir_tex_src_plane:
3638 default:
3639 break;
3640 }
3641 }
3642
3643 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3644 result = get_buffer_size(ctx, res_ptr, true);
3645 goto write_result;
3646 }
3647
3648 if (instr->op == nir_texop_texture_samples) {
3649 LLVMValueRef res, samples, is_msaa;
3650 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3651 samples = LLVMBuildExtractElement(ctx->builder, res,
3652 LLVMConstInt(ctx->i32, 3, false), "");
3653 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3654 LLVMConstInt(ctx->i32, 28, false), "");
3655 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3656 LLVMConstInt(ctx->i32, 0xe, false), "");
3657 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3658 LLVMConstInt(ctx->i32, 0xe, false), "");
3659
3660 samples = LLVMBuildLShr(ctx->builder, samples,
3661 LLVMConstInt(ctx->i32, 16, false), "");
3662 samples = LLVMBuildAnd(ctx->builder, samples,
3663 LLVMConstInt(ctx->i32, 0xf, false), "");
3664 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3665 samples, "");
3666 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3667 ctx->i32one, "");
3668 result = samples;
3669 goto write_result;
3670 }
3671
3672 if (coord)
3673 for (chan = 0; chan < instr->coord_components; chan++)
3674 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3675
3676 if (offsets && instr->op != nir_texop_txf) {
3677 LLVMValueRef offset[3], pack;
3678 for (chan = 0; chan < 3; ++chan)
3679 offset[chan] = ctx->i32zero;
3680
3681 args.offset = true;
3682 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3683 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3684 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3685 LLVMConstInt(ctx->i32, 0x3f, false), "");
3686 if (chan)
3687 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3688 LLVMConstInt(ctx->i32, chan * 8, false), "");
3689 }
3690 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3691 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3692 address[count++] = pack;
3693
3694 }
3695 /* pack LOD bias value */
3696 if (instr->op == nir_texop_txb && bias) {
3697 address[count++] = bias;
3698 }
3699
3700 /* Pack depth comparison value */
3701 if (instr->is_shadow && comparator) {
3702 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3703 }
3704
3705 /* pack derivatives */
3706 if (ddx || ddy) {
3707 switch (instr->sampler_dim) {
3708 case GLSL_SAMPLER_DIM_3D:
3709 case GLSL_SAMPLER_DIM_CUBE:
3710 num_deriv_comp = 3;
3711 break;
3712 case GLSL_SAMPLER_DIM_2D:
3713 default:
3714 num_deriv_comp = 2;
3715 break;
3716 case GLSL_SAMPLER_DIM_1D:
3717 num_deriv_comp = 1;
3718 break;
3719 }
3720
3721 for (unsigned i = 0; i < num_deriv_comp; i++) {
3722 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3723 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3724 }
3725 }
3726
3727 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3728 for (chan = 0; chan < instr->coord_components; chan++)
3729 coords[chan] = to_float(ctx, coords[chan]);
3730 if (instr->coord_components == 3)
3731 coords[3] = LLVMGetUndef(ctx->f32);
3732 ac_prepare_cube_coords(&ctx->ac,
3733 instr->op == nir_texop_txd, instr->is_array,
3734 coords, derivs);
3735 if (num_deriv_comp)
3736 num_deriv_comp--;
3737 }
3738
3739 if (ddx || ddy) {
3740 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3741 address[count++] = derivs[i];
3742 }
3743
3744 /* Pack texture coordinates */
3745 if (coord) {
3746 address[count++] = coords[0];
3747 if (instr->coord_components > 1) {
3748 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3749 coords[1] = apply_round_slice(ctx, coords[1]);
3750 }
3751 address[count++] = coords[1];
3752 }
3753 if (instr->coord_components > 2) {
3754 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3755 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3756 coords[2] = apply_round_slice(ctx, coords[2]);
3757 }
3758 address[count++] = coords[2];
3759 }
3760 }
3761
3762 /* Pack LOD */
3763 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3764 address[count++] = lod;
3765 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3766 address[count++] = sample_index;
3767 } else if(instr->op == nir_texop_txs) {
3768 count = 0;
3769 if (lod)
3770 address[count++] = lod;
3771 else
3772 address[count++] = ctx->i32zero;
3773 }
3774
3775 for (chan = 0; chan < count; chan++) {
3776 address[chan] = LLVMBuildBitCast(ctx->builder,
3777 address[chan], ctx->i32, "");
3778 }
3779
3780 if (instr->op == nir_texop_samples_identical) {
3781 LLVMValueRef txf_address[4];
3782 struct ac_image_args txf_args = { 0 };
3783 unsigned txf_count = count;
3784 memcpy(txf_address, address, sizeof(txf_address));
3785
3786 if (!instr->is_array)
3787 txf_address[2] = ctx->i32zero;
3788 txf_address[3] = ctx->i32zero;
3789
3790 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
3791 fmask_ptr, NULL,
3792 txf_address, txf_count, 0xf);
3793
3794 result = build_tex_intrinsic(ctx, instr, &txf_args);
3795
3796 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3797 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3798 goto write_result;
3799 }
3800
3801 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3802 instr->op != nir_texop_txs) {
3803 unsigned sample_chan = instr->is_array ? 3 : 2;
3804 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
3805 address[0],
3806 address[1],
3807 instr->is_array ? address[2] : NULL,
3808 address[sample_chan],
3809 fmask_ptr);
3810 }
3811
3812 if (offsets && instr->op == nir_texop_txf) {
3813 nir_const_value *const_offset =
3814 nir_src_as_const_value(instr->src[const_src].src);
3815 int num_offsets = instr->src[const_src].src.ssa->num_components;
3816 assert(const_offset);
3817 num_offsets = MIN2(num_offsets, instr->coord_components);
3818 if (num_offsets > 2)
3819 address[2] = LLVMBuildAdd(ctx->builder,
3820 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3821 if (num_offsets > 1)
3822 address[1] = LLVMBuildAdd(ctx->builder,
3823 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3824 address[0] = LLVMBuildAdd(ctx->builder,
3825 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3826
3827 }
3828
3829 /* TODO TG4 support */
3830 if (instr->op == nir_texop_tg4) {
3831 if (instr->is_shadow)
3832 dmask = 1;
3833 else
3834 dmask = 1 << instr->component;
3835 }
3836 set_tex_fetch_args(ctx, &args, instr, instr->op,
3837 res_ptr, samp_ptr, address, count, dmask);
3838
3839 result = build_tex_intrinsic(ctx, instr, &args);
3840
3841 if (instr->op == nir_texop_query_levels)
3842 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3843 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3844 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3845 else if (instr->op == nir_texop_txs &&
3846 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3847 instr->is_array) {
3848 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3849 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3850 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3851 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3852 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3853 } else if (instr->dest.ssa.num_components != 4)
3854 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3855
3856 write_result:
3857 if (result) {
3858 assert(instr->dest.is_ssa);
3859 result = to_integer(ctx, result);
3860 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3861 }
3862 }
3863
3864
3865 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3866 {
3867 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3868 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3869
3870 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3871 _mesa_hash_table_insert(ctx->phis, instr, result);
3872 }
3873
3874 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3875 nir_phi_instr *instr,
3876 LLVMValueRef llvm_phi)
3877 {
3878 nir_foreach_phi_src(src, instr) {
3879 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3880 LLVMValueRef llvm_src = get_src(ctx, src->src);
3881
3882 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3883 }
3884 }
3885
3886 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3887 {
3888 struct hash_entry *entry;
3889 hash_table_foreach(ctx->phis, entry) {
3890 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3891 (LLVMValueRef)entry->data);
3892 }
3893 }
3894
3895
3896 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3897 nir_ssa_undef_instr *instr)
3898 {
3899 unsigned num_components = instr->def.num_components;
3900 LLVMValueRef undef;
3901
3902 if (num_components == 1)
3903 undef = LLVMGetUndef(ctx->i32);
3904 else {
3905 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3906 }
3907 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3908 }
3909
3910 static void visit_jump(struct nir_to_llvm_context *ctx,
3911 nir_jump_instr *instr)
3912 {
3913 switch (instr->type) {
3914 case nir_jump_break:
3915 LLVMBuildBr(ctx->builder, ctx->break_block);
3916 LLVMClearInsertionPosition(ctx->builder);
3917 break;
3918 case nir_jump_continue:
3919 LLVMBuildBr(ctx->builder, ctx->continue_block);
3920 LLVMClearInsertionPosition(ctx->builder);
3921 break;
3922 default:
3923 fprintf(stderr, "Unknown NIR jump instr: ");
3924 nir_print_instr(&instr->instr, stderr);
3925 fprintf(stderr, "\n");
3926 abort();
3927 }
3928 }
3929
3930 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3931 struct exec_list *list);
3932
3933 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3934 {
3935 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3936 nir_foreach_instr(instr, block)
3937 {
3938 switch (instr->type) {
3939 case nir_instr_type_alu:
3940 visit_alu(ctx, nir_instr_as_alu(instr));
3941 break;
3942 case nir_instr_type_load_const:
3943 visit_load_const(ctx, nir_instr_as_load_const(instr));
3944 break;
3945 case nir_instr_type_intrinsic:
3946 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3947 break;
3948 case nir_instr_type_tex:
3949 visit_tex(ctx, nir_instr_as_tex(instr));
3950 break;
3951 case nir_instr_type_phi:
3952 visit_phi(ctx, nir_instr_as_phi(instr));
3953 break;
3954 case nir_instr_type_ssa_undef:
3955 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3956 break;
3957 case nir_instr_type_jump:
3958 visit_jump(ctx, nir_instr_as_jump(instr));
3959 break;
3960 default:
3961 fprintf(stderr, "Unknown NIR instr type: ");
3962 nir_print_instr(instr, stderr);
3963 fprintf(stderr, "\n");
3964 abort();
3965 }
3966 }
3967
3968 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3969 }
3970
3971 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3972 {
3973 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3974
3975 LLVMBasicBlockRef merge_block =
3976 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3977 LLVMBasicBlockRef if_block =
3978 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3979 LLVMBasicBlockRef else_block = merge_block;
3980 if (!exec_list_is_empty(&if_stmt->else_list))
3981 else_block = LLVMAppendBasicBlockInContext(
3982 ctx->context, ctx->main_function, "");
3983
3984 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3985 LLVMConstInt(ctx->i32, 0, false), "");
3986 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3987
3988 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3989 visit_cf_list(ctx, &if_stmt->then_list);
3990 if (LLVMGetInsertBlock(ctx->builder))
3991 LLVMBuildBr(ctx->builder, merge_block);
3992
3993 if (!exec_list_is_empty(&if_stmt->else_list)) {
3994 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3995 visit_cf_list(ctx, &if_stmt->else_list);
3996 if (LLVMGetInsertBlock(ctx->builder))
3997 LLVMBuildBr(ctx->builder, merge_block);
3998 }
3999
4000 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4001 }
4002
4003 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4004 {
4005 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4006 LLVMBasicBlockRef break_parent = ctx->break_block;
4007
4008 ctx->continue_block =
4009 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4010 ctx->break_block =
4011 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4012
4013 LLVMBuildBr(ctx->builder, ctx->continue_block);
4014 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4015 visit_cf_list(ctx, &loop->body);
4016
4017 if (LLVMGetInsertBlock(ctx->builder))
4018 LLVMBuildBr(ctx->builder, ctx->continue_block);
4019 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4020
4021 ctx->continue_block = continue_parent;
4022 ctx->break_block = break_parent;
4023 }
4024
4025 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4026 struct exec_list *list)
4027 {
4028 foreach_list_typed(nir_cf_node, node, node, list)
4029 {
4030 switch (node->type) {
4031 case nir_cf_node_block:
4032 visit_block(ctx, nir_cf_node_as_block(node));
4033 break;
4034
4035 case nir_cf_node_if:
4036 visit_if(ctx, nir_cf_node_as_if(node));
4037 break;
4038
4039 case nir_cf_node_loop:
4040 visit_loop(ctx, nir_cf_node_as_loop(node));
4041 break;
4042
4043 default:
4044 assert(0);
4045 }
4046 }
4047 }
4048
4049 static void
4050 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4051 struct nir_variable *variable)
4052 {
4053 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4054 LLVMValueRef t_offset;
4055 LLVMValueRef t_list;
4056 LLVMValueRef args[3];
4057 LLVMValueRef input;
4058 LLVMValueRef buffer_index;
4059 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4060 int idx = variable->data.location;
4061 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4062
4063 variable->data.driver_location = idx * 4;
4064
4065 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4066 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4067 ctx->start_instance, "");
4068 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4069 ctx->shader_info->vs.vgpr_comp_cnt);
4070 } else
4071 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4072 ctx->base_vertex, "");
4073
4074 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4075 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4076
4077 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4078 args[0] = t_list;
4079 args[1] = LLVMConstInt(ctx->i32, 0, false);
4080 args[2] = buffer_index;
4081 input = ac_build_intrinsic(&ctx->ac,
4082 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
4083 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND |
4084 AC_FUNC_ATTR_LEGACY);
4085
4086 for (unsigned chan = 0; chan < 4; chan++) {
4087 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4088 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4089 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4090 input, llvm_chan, ""));
4091 }
4092 }
4093 }
4094
4095 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4096 unsigned attr,
4097 LLVMValueRef interp_param,
4098 LLVMValueRef prim_mask,
4099 LLVMValueRef result[4])
4100 {
4101 LLVMValueRef attr_number;
4102 unsigned chan;
4103 LLVMValueRef i, j;
4104 bool interp = interp_param != NULL;
4105
4106 attr_number = LLVMConstInt(ctx->i32, attr, false);
4107
4108 /* fs.constant returns the param from the middle vertex, so it's not
4109 * really useful for flat shading. It's meant to be used for custom
4110 * interpolation (but the intrinsic can't fetch from the other two
4111 * vertices).
4112 *
4113 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4114 * to do the right thing. The only reason we use fs.constant is that
4115 * fs.interp cannot be used on integers, because they can be equal
4116 * to NaN.
4117 */
4118 if (interp) {
4119 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4120 LLVMVectorType(ctx->f32, 2), "");
4121
4122 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4123 ctx->i32zero, "");
4124 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4125 ctx->i32one, "");
4126 }
4127
4128 for (chan = 0; chan < 4; chan++) {
4129 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4130
4131 if (interp) {
4132 result[chan] = ac_build_fs_interp(&ctx->ac,
4133 llvm_chan,
4134 attr_number,
4135 prim_mask, i, j);
4136 } else {
4137 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4138 LLVMConstInt(ctx->i32, 2, false),
4139 llvm_chan,
4140 attr_number,
4141 prim_mask);
4142 }
4143 }
4144 }
4145
4146 static void
4147 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4148 struct nir_variable *variable)
4149 {
4150 int idx = variable->data.location;
4151 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4152 LLVMValueRef interp;
4153
4154 variable->data.driver_location = idx * 4;
4155 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4156
4157 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4158 unsigned interp_type;
4159 if (variable->data.sample) {
4160 interp_type = INTERP_SAMPLE;
4161 ctx->shader_info->fs.force_persample = true;
4162 } else if (variable->data.centroid)
4163 interp_type = INTERP_CENTROID;
4164 else
4165 interp_type = INTERP_CENTER;
4166
4167 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4168 } else
4169 interp = NULL;
4170
4171 for (unsigned i = 0; i < attrib_count; ++i)
4172 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4173
4174 }
4175
4176 static void
4177 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4178 struct nir_variable *variable)
4179 {
4180 switch (ctx->stage) {
4181 case MESA_SHADER_VERTEX:
4182 handle_vs_input_decl(ctx, variable);
4183 break;
4184 case MESA_SHADER_FRAGMENT:
4185 handle_fs_input_decl(ctx, variable);
4186 break;
4187 default:
4188 break;
4189 }
4190
4191 }
4192
4193 static void
4194 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4195 struct nir_shader *nir)
4196 {
4197 unsigned index = 0;
4198 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4199 LLVMValueRef interp_param;
4200 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4201
4202 if (!(ctx->input_mask & (1ull << i)))
4203 continue;
4204
4205 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4206 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4207 interp_param = *inputs;
4208 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4209 inputs);
4210
4211 if (!interp_param)
4212 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4213 ++index;
4214 } else if (i == VARYING_SLOT_POS) {
4215 for(int i = 0; i < 3; ++i)
4216 inputs[i] = ctx->frag_pos[i];
4217
4218 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4219 }
4220 }
4221 ctx->shader_info->fs.num_interp = index;
4222 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4223 ctx->shader_info->fs.has_pcoord = true;
4224 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4225 ctx->shader_info->fs.prim_id_input = true;
4226 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4227 ctx->shader_info->fs.layer_input = true;
4228 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4229 }
4230
4231 static LLVMValueRef
4232 ac_build_alloca(struct nir_to_llvm_context *ctx,
4233 LLVMTypeRef type,
4234 const char *name)
4235 {
4236 LLVMBuilderRef builder = ctx->builder;
4237 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4238 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4239 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4240 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4241 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4242 LLVMValueRef res;
4243
4244 if (first_instr) {
4245 LLVMPositionBuilderBefore(first_builder, first_instr);
4246 } else {
4247 LLVMPositionBuilderAtEnd(first_builder, first_block);
4248 }
4249
4250 res = LLVMBuildAlloca(first_builder, type, name);
4251 LLVMBuildStore(builder, LLVMConstNull(type), res);
4252
4253 LLVMDisposeBuilder(first_builder);
4254
4255 return res;
4256 }
4257
4258 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4259 LLVMTypeRef type,
4260 const char *name)
4261 {
4262 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4263 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4264 return ptr;
4265 }
4266
4267 static void
4268 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4269 struct nir_variable *variable)
4270 {
4271 int idx = variable->data.location + variable->data.index;
4272 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4273 uint64_t mask_attribs;
4274 variable->data.driver_location = idx * 4;
4275
4276 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4277 if (ctx->stage == MESA_SHADER_VERTEX ||
4278 ctx->stage == MESA_SHADER_GEOMETRY) {
4279 if (idx == VARYING_SLOT_CLIP_DIST0) {
4280 int length = ctx->num_output_clips + ctx->num_output_culls;
4281 if (ctx->stage == MESA_SHADER_VERTEX) {
4282 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4283 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4284 }
4285
4286 if (length > 4)
4287 attrib_count = 2;
4288 else
4289 attrib_count = 1;
4290 mask_attribs = 1ull << idx;
4291 }
4292 }
4293
4294 for (unsigned i = 0; i < attrib_count; ++i) {
4295 for (unsigned chan = 0; chan < 4; chan++) {
4296 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4297 si_build_alloca_undef(ctx, ctx->f32, "");
4298 }
4299 }
4300 ctx->output_mask |= mask_attribs;
4301 }
4302
4303 static void
4304 setup_locals(struct nir_to_llvm_context *ctx,
4305 struct nir_function *func)
4306 {
4307 int i, j;
4308 ctx->num_locals = 0;
4309 nir_foreach_variable(variable, &func->impl->locals) {
4310 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4311 variable->data.driver_location = ctx->num_locals * 4;
4312 ctx->num_locals += attrib_count;
4313 }
4314 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4315 if (!ctx->locals)
4316 return;
4317
4318 for (i = 0; i < ctx->num_locals; i++) {
4319 for (j = 0; j < 4; j++) {
4320 ctx->locals[i * 4 + j] =
4321 si_build_alloca_undef(ctx, ctx->f32, "temp");
4322 }
4323 }
4324 }
4325
4326 static LLVMValueRef
4327 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4328 {
4329 v = to_float(ctx, v);
4330 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4331 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4332 }
4333
4334
4335 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4336 LLVMValueRef src0, LLVMValueRef src1)
4337 {
4338 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4339 LLVMValueRef comp[2];
4340
4341 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4342 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4343 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4344 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4345 }
4346
4347 /* Initialize arguments for the shader export intrinsic */
4348 static void
4349 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4350 LLVMValueRef *values,
4351 unsigned target,
4352 struct ac_export_args *args)
4353 {
4354 /* Default is 0xf. Adjusted below depending on the format. */
4355 args->enabled_channels = 0xf;
4356
4357 /* Specify whether the EXEC mask represents the valid mask */
4358 args->valid_mask = 0;
4359
4360 /* Specify whether this is the last export */
4361 args->done = 0;
4362
4363 /* Specify the target we are exporting */
4364 args->target = target;
4365
4366 args->compr = false;
4367 args->out[0] = LLVMGetUndef(ctx->f32);
4368 args->out[1] = LLVMGetUndef(ctx->f32);
4369 args->out[2] = LLVMGetUndef(ctx->f32);
4370 args->out[3] = LLVMGetUndef(ctx->f32);
4371
4372 if (!values)
4373 return;
4374
4375 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4376 LLVMValueRef val[4];
4377 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4378 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4379 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4380
4381 switch(col_format) {
4382 case V_028714_SPI_SHADER_ZERO:
4383 args->enabled_channels = 0; /* writemask */
4384 args->target = V_008DFC_SQ_EXP_NULL;
4385 break;
4386
4387 case V_028714_SPI_SHADER_32_R:
4388 args->enabled_channels = 1;
4389 args->out[0] = values[0];
4390 break;
4391
4392 case V_028714_SPI_SHADER_32_GR:
4393 args->enabled_channels = 0x3;
4394 args->out[0] = values[0];
4395 args->out[1] = values[1];
4396 break;
4397
4398 case V_028714_SPI_SHADER_32_AR:
4399 args->enabled_channels = 0x9;
4400 args->out[0] = values[0];
4401 args->out[3] = values[3];
4402 break;
4403
4404 case V_028714_SPI_SHADER_FP16_ABGR:
4405 args->compr = 1;
4406
4407 for (unsigned chan = 0; chan < 2; chan++) {
4408 LLVMValueRef pack_args[2] = {
4409 values[2 * chan],
4410 values[2 * chan + 1]
4411 };
4412 LLVMValueRef packed;
4413
4414 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
4415 args->out[chan] = packed;
4416 }
4417 break;
4418
4419 case V_028714_SPI_SHADER_UNORM16_ABGR:
4420 for (unsigned chan = 0; chan < 4; chan++) {
4421 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
4422 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4423 LLVMConstReal(ctx->f32, 65535), "");
4424 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4425 LLVMConstReal(ctx->f32, 0.5), "");
4426 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4427 ctx->i32, "");
4428 }
4429
4430 args->compr = 1;
4431 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4432 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4433 break;
4434
4435 case V_028714_SPI_SHADER_SNORM16_ABGR:
4436 for (unsigned chan = 0; chan < 4; chan++) {
4437 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4438 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4439 LLVMConstReal(ctx->f32, 32767), "");
4440
4441 /* If positive, add 0.5, else add -0.5. */
4442 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4443 LLVMBuildSelect(ctx->builder,
4444 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4445 val[chan], ctx->f32zero, ""),
4446 LLVMConstReal(ctx->f32, 0.5),
4447 LLVMConstReal(ctx->f32, -0.5), ""), "");
4448 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4449 }
4450
4451 args->compr = 1;
4452 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4453 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4454 break;
4455
4456 case V_028714_SPI_SHADER_UINT16_ABGR: {
4457 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4458
4459 for (unsigned chan = 0; chan < 4; chan++) {
4460 val[chan] = to_integer(ctx, values[chan]);
4461 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4462 }
4463
4464 args->compr = 1;
4465 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4466 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4467 break;
4468 }
4469
4470 case V_028714_SPI_SHADER_SINT16_ABGR: {
4471 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4472 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4473
4474 /* Clamp. */
4475 for (unsigned chan = 0; chan < 4; chan++) {
4476 val[chan] = to_integer(ctx, values[chan]);
4477 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4478 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4479 }
4480
4481 args->compr = 1;
4482 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4483 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4484 break;
4485 }
4486
4487 default:
4488 case V_028714_SPI_SHADER_32_ABGR:
4489 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
4490 break;
4491 }
4492 } else
4493 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
4494
4495 for (unsigned i = 0; i < 4; ++i)
4496 args->out[i] = to_float(ctx, args->out[i]);
4497 }
4498
4499 static void
4500 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
4501 struct ac_vs_output_info *outinfo)
4502 {
4503 uint32_t param_count = 0;
4504 unsigned target;
4505 unsigned pos_idx, num_pos_exports = 0;
4506 struct ac_export_args args, pos_args[4] = {};
4507 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4508 int i;
4509
4510 outinfo->prim_id_output = 0xffffffff;
4511 outinfo->layer_output = 0xffffffff;
4512 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
4513 LLVMValueRef slots[8];
4514 unsigned j;
4515
4516 if (outinfo->cull_dist_mask)
4517 outinfo->cull_dist_mask <<= ctx->num_output_clips;
4518
4519 i = VARYING_SLOT_CLIP_DIST0;
4520 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
4521 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4522 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4523
4524 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
4525 slots[i] = LLVMGetUndef(ctx->f32);
4526
4527 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
4528 target = V_008DFC_SQ_EXP_POS + 3;
4529 si_llvm_init_export_args(ctx, &slots[4], target, &args);
4530 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4531 &args, sizeof(args));
4532 }
4533
4534 target = V_008DFC_SQ_EXP_POS + 2;
4535 si_llvm_init_export_args(ctx, &slots[0], target, &args);
4536 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4537 &args, sizeof(args));
4538
4539 }
4540
4541 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4542 LLVMValueRef values[4];
4543 if (!(ctx->output_mask & (1ull << i)))
4544 continue;
4545
4546 for (unsigned j = 0; j < 4; j++)
4547 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4548 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4549
4550 if (i == VARYING_SLOT_POS) {
4551 target = V_008DFC_SQ_EXP_POS;
4552 } else if (i == VARYING_SLOT_CLIP_DIST0) {
4553 continue;
4554 } else if (i == VARYING_SLOT_PSIZ) {
4555 outinfo->writes_pointsize = true;
4556 psize_value = values[0];
4557 continue;
4558 } else if (i == VARYING_SLOT_LAYER) {
4559 outinfo->writes_layer = true;
4560 layer_value = values[0];
4561 outinfo->layer_output = param_count;
4562 target = V_008DFC_SQ_EXP_PARAM + param_count;
4563 param_count++;
4564 } else if (i == VARYING_SLOT_VIEWPORT) {
4565 outinfo->writes_viewport_index = true;
4566 viewport_index_value = values[0];
4567 continue;
4568 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4569 outinfo->prim_id_output = param_count;
4570 target = V_008DFC_SQ_EXP_PARAM + param_count;
4571 param_count++;
4572 } else if (i >= VARYING_SLOT_VAR0) {
4573 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4574 target = V_008DFC_SQ_EXP_PARAM + param_count;
4575 param_count++;
4576 }
4577
4578 si_llvm_init_export_args(ctx, values, target, &args);
4579
4580 if (target >= V_008DFC_SQ_EXP_POS &&
4581 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4582 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4583 &args, sizeof(args));
4584 } else {
4585 ac_build_export(&ctx->ac, &args);
4586 }
4587 }
4588
4589 /* We need to add the position output manually if it's missing. */
4590 if (!pos_args[0].out[0]) {
4591 pos_args[0].enabled_channels = 0xf;
4592 pos_args[0].valid_mask = 0;
4593 pos_args[0].done = 0;
4594 pos_args[0].target = V_008DFC_SQ_EXP_POS;
4595 pos_args[0].compr = 0;
4596 pos_args[0].out[0] = ctx->f32zero; /* X */
4597 pos_args[0].out[1] = ctx->f32zero; /* Y */
4598 pos_args[0].out[2] = ctx->f32zero; /* Z */
4599 pos_args[0].out[3] = ctx->f32one; /* W */
4600 }
4601
4602 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
4603 (outinfo->writes_layer == true ? 4 : 0) |
4604 (outinfo->writes_viewport_index == true ? 8 : 0));
4605 if (mask) {
4606 pos_args[1].enabled_channels = mask;
4607 pos_args[1].valid_mask = 0;
4608 pos_args[1].done = 0;
4609 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
4610 pos_args[1].compr = 0;
4611 pos_args[1].out[0] = ctx->f32zero; /* X */
4612 pos_args[1].out[1] = ctx->f32zero; /* Y */
4613 pos_args[1].out[2] = ctx->f32zero; /* Z */
4614 pos_args[1].out[3] = ctx->f32zero; /* W */
4615
4616 if (outinfo->writes_pointsize == true)
4617 pos_args[1].out[0] = psize_value;
4618 if (outinfo->writes_layer == true)
4619 pos_args[1].out[2] = layer_value;
4620 if (outinfo->writes_viewport_index == true)
4621 pos_args[1].out[3] = viewport_index_value;
4622 }
4623 for (i = 0; i < 4; i++) {
4624 if (pos_args[i].out[0])
4625 num_pos_exports++;
4626 }
4627
4628 pos_idx = 0;
4629 for (i = 0; i < 4; i++) {
4630 if (!pos_args[i].out[0])
4631 continue;
4632
4633 /* Specify the target we are exporting */
4634 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
4635 if (pos_idx == num_pos_exports)
4636 pos_args[i].done = 1;
4637 ac_build_export(&ctx->ac, &pos_args[i]);
4638 }
4639
4640 outinfo->pos_exports = num_pos_exports;
4641 outinfo->param_exports = param_count;
4642 }
4643
4644 static void
4645 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
4646 struct ac_es_output_info *outinfo)
4647 {
4648 int j;
4649 uint64_t max_output_written = 0;
4650 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4651 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4652 int param_index;
4653 int length = 4;
4654
4655 if (!(ctx->output_mask & (1ull << i)))
4656 continue;
4657
4658 if (i == VARYING_SLOT_CLIP_DIST0)
4659 length = ctx->num_output_clips + ctx->num_output_culls;
4660
4661 param_index = shader_io_get_unique_index(i);
4662
4663 max_output_written = MAX2(param_index + (length > 4), max_output_written);
4664
4665 for (j = 0; j < length; j++) {
4666 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4667 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4668
4669 ac_build_buffer_store_dword(&ctx->ac,
4670 ctx->esgs_ring,
4671 out_val, 1,
4672 NULL, ctx->es2gs_offset,
4673 (4 * param_index + j) * 4,
4674 1, 1, true, true);
4675 }
4676 }
4677 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
4678 }
4679
4680 static void
4681 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4682 LLVMValueRef *color, unsigned param, bool is_last)
4683 {
4684
4685 struct ac_export_args args;
4686
4687 /* Export */
4688 si_llvm_init_export_args(ctx, color, param,
4689 &args);
4690
4691 if (is_last) {
4692 args.valid_mask = 1; /* whether the EXEC mask is valid */
4693 args.done = 1; /* DONE bit */
4694 } else if (!args.enabled_channels)
4695 return; /* unnecessary NULL export */
4696
4697 ac_build_export(&ctx->ac, &args);
4698 }
4699
4700 static void
4701 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4702 LLVMValueRef depth, LLVMValueRef stencil,
4703 LLVMValueRef samplemask)
4704 {
4705 struct ac_export_args args;
4706
4707 args.enabled_channels = 0;
4708 args.valid_mask = 1;
4709 args.done = 1;
4710 args.target = V_008DFC_SQ_EXP_MRTZ;
4711 args.compr = false;
4712
4713 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
4714 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4715 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4716 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4717
4718 if (depth) {
4719 args.out[0] = depth;
4720 args.enabled_channels |= 0x1;
4721 }
4722
4723 if (stencil) {
4724 args.out[1] = stencil;
4725 args.enabled_channels |= 0x2;
4726 }
4727
4728 if (samplemask) {
4729 args.out[2] = samplemask;
4730 args.enabled_channels |= 0x4;
4731 }
4732
4733 /* SI (except OLAND) has a bug that it only looks
4734 * at the X writemask component. */
4735 if (ctx->options->chip_class == SI &&
4736 ctx->options->family != CHIP_OLAND)
4737 args.enabled_channels |= 0x1;
4738
4739 ac_build_export(&ctx->ac, &args);
4740 }
4741
4742 static void
4743 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4744 {
4745 unsigned index = 0;
4746 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4747
4748 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4749 LLVMValueRef values[4];
4750
4751 if (!(ctx->output_mask & (1ull << i)))
4752 continue;
4753
4754 if (i == FRAG_RESULT_DEPTH) {
4755 ctx->shader_info->fs.writes_z = true;
4756 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4757 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4758 } else if (i == FRAG_RESULT_STENCIL) {
4759 ctx->shader_info->fs.writes_stencil = true;
4760 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4761 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4762 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
4763 ctx->shader_info->fs.writes_sample_mask = true;
4764 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
4765 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4766 } else {
4767 bool last = false;
4768 for (unsigned j = 0; j < 4; j++)
4769 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4770 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4771
4772 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
4773 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4774
4775 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4776 index++;
4777 }
4778 }
4779
4780 if (depth || stencil || samplemask)
4781 si_export_mrt_z(ctx, depth, stencil, samplemask);
4782 else if (!index)
4783 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4784
4785 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4786 }
4787
4788 static void
4789 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4790 {
4791 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4792 }
4793
4794 static void
4795 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4796 {
4797 switch (ctx->stage) {
4798 case MESA_SHADER_VERTEX:
4799 if (ctx->options->key.vs.as_es)
4800 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
4801 else
4802 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
4803 break;
4804 case MESA_SHADER_FRAGMENT:
4805 handle_fs_outputs_post(ctx);
4806 break;
4807 case MESA_SHADER_GEOMETRY:
4808 emit_gs_epilogue(ctx);
4809 break;
4810 default:
4811 break;
4812 }
4813 }
4814
4815 static void
4816 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4817 struct nir_variable *variable, uint32_t *offset, int idx)
4818 {
4819 unsigned size = glsl_count_attribute_slots(variable->type, false);
4820 variable->data.driver_location = *offset;
4821 *offset += size;
4822 }
4823
4824 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4825 {
4826 LLVMPassManagerRef passmgr;
4827 /* Create the pass manager */
4828 passmgr = LLVMCreateFunctionPassManagerForModule(
4829 ctx->module);
4830
4831 /* This pass should eliminate all the load and store instructions */
4832 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4833
4834 /* Add some optimization passes */
4835 LLVMAddScalarReplAggregatesPass(passmgr);
4836 LLVMAddLICMPass(passmgr);
4837 LLVMAddAggressiveDCEPass(passmgr);
4838 LLVMAddCFGSimplificationPass(passmgr);
4839 LLVMAddInstructionCombiningPass(passmgr);
4840
4841 /* Run the pass */
4842 LLVMInitializeFunctionPassManager(passmgr);
4843 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4844 LLVMFinalizeFunctionPassManager(passmgr);
4845
4846 LLVMDisposeBuilder(ctx->builder);
4847 LLVMDisposePassManager(passmgr);
4848 }
4849
4850 static void
4851 ac_setup_rings(struct nir_to_llvm_context *ctx)
4852 {
4853 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
4854 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
4855 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
4856 }
4857
4858 if (ctx->is_gs_copy_shader) {
4859 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
4860 }
4861 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4862 LLVMValueRef tmp;
4863 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
4864 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
4865
4866 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4867
4868 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4869 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4870 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4871 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4872
4873 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4874 }
4875
4876 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
4877 ctx->stage == MESA_SHADER_TESS_EVAL) {
4878 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
4879 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
4880 }
4881 }
4882
4883 static
4884 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4885 struct nir_shader *nir,
4886 struct ac_shader_variant_info *shader_info,
4887 const struct ac_nir_compiler_options *options)
4888 {
4889 struct nir_to_llvm_context ctx = {0};
4890 struct nir_function *func;
4891 unsigned i;
4892 ctx.options = options;
4893 ctx.shader_info = shader_info;
4894 ctx.context = LLVMContextCreate();
4895 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4896
4897 ac_llvm_context_init(&ctx.ac, ctx.context);
4898 ctx.ac.module = ctx.module;
4899
4900 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4901
4902 memset(shader_info, 0, sizeof(*shader_info));
4903
4904 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4905
4906 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
4907 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
4908 LLVMSetDataLayout(ctx.module, data_layout_str);
4909 LLVMDisposeTargetData(data_layout);
4910 LLVMDisposeMessage(data_layout_str);
4911
4912 setup_types(&ctx);
4913
4914 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4915 ctx.ac.builder = ctx.builder;
4916 ctx.stage = nir->stage;
4917
4918 for (i = 0; i < AC_UD_MAX_SETS; i++)
4919 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4920 for (i = 0; i < AC_UD_MAX_UD; i++)
4921 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4922
4923 create_function(&ctx);
4924
4925 if (nir->stage == MESA_SHADER_COMPUTE) {
4926 int num_shared = 0;
4927 nir_foreach_variable(variable, &nir->shared)
4928 num_shared++;
4929 if (num_shared) {
4930 int idx = 0;
4931 uint32_t shared_size = 0;
4932 LLVMValueRef var;
4933 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4934 nir_foreach_variable(variable, &nir->shared) {
4935 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4936 idx++;
4937 }
4938
4939 shared_size *= 16;
4940 var = LLVMAddGlobalInAddressSpace(ctx.module,
4941 LLVMArrayType(ctx.i8, shared_size),
4942 "compute_lds",
4943 LOCAL_ADDR_SPACE);
4944 LLVMSetAlignment(var, 4);
4945 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4946 }
4947 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4948 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4949
4950 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4951 }
4952
4953 ac_setup_rings(&ctx);
4954
4955 nir_foreach_variable(variable, &nir->inputs)
4956 handle_shader_input_decl(&ctx, variable);
4957
4958 if (nir->stage == MESA_SHADER_FRAGMENT)
4959 handle_fs_inputs_pre(&ctx, nir);
4960
4961 ctx.num_output_clips = nir->info->clip_distance_array_size;
4962 ctx.num_output_culls = nir->info->cull_distance_array_size;
4963
4964 nir_foreach_variable(variable, &nir->outputs)
4965 handle_shader_output_decl(&ctx, variable);
4966
4967 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4968 _mesa_key_pointer_equal);
4969 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4970 _mesa_key_pointer_equal);
4971
4972 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4973
4974 setup_locals(&ctx, func);
4975
4976 visit_cf_list(&ctx, &func->impl->body);
4977 phi_post_pass(&ctx);
4978
4979 handle_shader_outputs_post(&ctx);
4980 LLVMBuildRetVoid(ctx.builder);
4981
4982 ac_llvm_finalize_module(&ctx);
4983 free(ctx.locals);
4984 ralloc_free(ctx.defs);
4985 ralloc_free(ctx.phis);
4986
4987 if (nir->stage == MESA_SHADER_GEOMETRY) {
4988 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
4989 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
4990 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4991 nir->info->gs.vertices_out;
4992 }
4993 return ctx.module;
4994 }
4995
4996 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4997 {
4998 unsigned *retval = (unsigned *)context;
4999 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5000 char *description = LLVMGetDiagInfoDescription(di);
5001
5002 if (severity == LLVMDSError) {
5003 *retval = 1;
5004 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5005 description);
5006 }
5007
5008 LLVMDisposeMessage(description);
5009 }
5010
5011 static unsigned ac_llvm_compile(LLVMModuleRef M,
5012 struct ac_shader_binary *binary,
5013 LLVMTargetMachineRef tm)
5014 {
5015 unsigned retval = 0;
5016 char *err;
5017 LLVMContextRef llvm_ctx;
5018 LLVMMemoryBufferRef out_buffer;
5019 unsigned buffer_size;
5020 const char *buffer_data;
5021 LLVMBool mem_err;
5022
5023 /* Setup Diagnostic Handler*/
5024 llvm_ctx = LLVMGetModuleContext(M);
5025
5026 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5027 &retval);
5028
5029 /* Compile IR*/
5030 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5031 &err, &out_buffer);
5032
5033 /* Process Errors/Warnings */
5034 if (mem_err) {
5035 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5036 free(err);
5037 retval = 1;
5038 goto out;
5039 }
5040
5041 /* Extract Shader Code*/
5042 buffer_size = LLVMGetBufferSize(out_buffer);
5043 buffer_data = LLVMGetBufferStart(out_buffer);
5044
5045 ac_elf_read(buffer_data, buffer_size, binary);
5046
5047 /* Clean up */
5048 LLVMDisposeMemoryBuffer(out_buffer);
5049
5050 out:
5051 return retval;
5052 }
5053
5054 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5055 LLVMModuleRef llvm_module,
5056 struct ac_shader_binary *binary,
5057 struct ac_shader_config *config,
5058 struct ac_shader_variant_info *shader_info,
5059 gl_shader_stage stage,
5060 bool dump_shader, bool supports_spill)
5061 {
5062 if (dump_shader)
5063 ac_dump_module(llvm_module);
5064
5065 memset(binary, 0, sizeof(*binary));
5066 int v = ac_llvm_compile(llvm_module, binary, tm);
5067 if (v) {
5068 fprintf(stderr, "compile failed\n");
5069 }
5070
5071 if (dump_shader)
5072 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5073
5074 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5075
5076 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5077 LLVMDisposeModule(llvm_module);
5078 LLVMContextDispose(ctx);
5079
5080 if (stage == MESA_SHADER_FRAGMENT) {
5081 shader_info->num_input_vgprs = 0;
5082 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5083 shader_info->num_input_vgprs += 2;
5084 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5085 shader_info->num_input_vgprs += 2;
5086 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5087 shader_info->num_input_vgprs += 2;
5088 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5089 shader_info->num_input_vgprs += 3;
5090 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5091 shader_info->num_input_vgprs += 2;
5092 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5093 shader_info->num_input_vgprs += 2;
5094 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5095 shader_info->num_input_vgprs += 2;
5096 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5097 shader_info->num_input_vgprs += 1;
5098 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5099 shader_info->num_input_vgprs += 1;
5100 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5101 shader_info->num_input_vgprs += 1;
5102 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5103 shader_info->num_input_vgprs += 1;
5104 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5105 shader_info->num_input_vgprs += 1;
5106 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5107 shader_info->num_input_vgprs += 1;
5108 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5109 shader_info->num_input_vgprs += 1;
5110 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5111 shader_info->num_input_vgprs += 1;
5112 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5113 shader_info->num_input_vgprs += 1;
5114 }
5115 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5116
5117 /* +3 for scratch wave offset and VCC */
5118 config->num_sgprs = MAX2(config->num_sgprs,
5119 shader_info->num_input_sgprs + 3);
5120 }
5121
5122 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5123 struct ac_shader_binary *binary,
5124 struct ac_shader_config *config,
5125 struct ac_shader_variant_info *shader_info,
5126 struct nir_shader *nir,
5127 const struct ac_nir_compiler_options *options,
5128 bool dump_shader)
5129 {
5130
5131 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5132 options);
5133
5134 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5135 switch (nir->stage) {
5136 case MESA_SHADER_COMPUTE:
5137 for (int i = 0; i < 3; ++i)
5138 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5139 break;
5140 case MESA_SHADER_FRAGMENT:
5141 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5142 break;
5143 case MESA_SHADER_GEOMETRY:
5144 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5145 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5146 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5147 shader_info->gs.invocations = nir->info->gs.invocations;
5148 break;
5149 case MESA_SHADER_VERTEX:
5150 shader_info->vs.as_es = options->key.vs.as_es;
5151 break;
5152 default:
5153 break;
5154 }
5155 }
5156
5157 static void
5158 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5159 {
5160 LLVMValueRef args[9];
5161 args[0] = ctx->gsvs_ring;
5162 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5163 args[3] = ctx->i32zero;
5164 args[4] = ctx->i32one; /* OFFEN */
5165 args[5] = ctx->i32zero; /* IDXEN */
5166 args[6] = ctx->i32one; /* GLC */
5167 args[7] = ctx->i32one; /* SLC */
5168 args[8] = ctx->i32zero; /* TFE */
5169
5170 int idx = 0;
5171
5172 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5173 int length = 4;
5174 int slot = idx;
5175 int slot_inc = 1;
5176 if (!(ctx->output_mask & (1ull << i)))
5177 continue;
5178
5179 if (i == VARYING_SLOT_CLIP_DIST0) {
5180 /* unpack clip and cull from a single set of slots */
5181 length = ctx->num_output_clips + ctx->num_output_culls;
5182 if (length > 4)
5183 slot_inc = 2;
5184 }
5185
5186 for (unsigned j = 0; j < length; j++) {
5187 LLVMValueRef value;
5188 args[2] = LLVMConstInt(ctx->i32,
5189 (slot * 4 + j) *
5190 ctx->gs_max_out_vertices * 16 * 4, false);
5191
5192 value = ac_build_intrinsic(&ctx->ac,
5193 "llvm.SI.buffer.load.dword.i32.i32",
5194 ctx->i32, args, 9,
5195 AC_FUNC_ATTR_READONLY |
5196 AC_FUNC_ATTR_LEGACY);
5197
5198 LLVMBuildStore(ctx->builder,
5199 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5200 }
5201 idx += slot_inc;
5202 }
5203 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5204 }
5205
5206 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5207 struct nir_shader *geom_shader,
5208 struct ac_shader_binary *binary,
5209 struct ac_shader_config *config,
5210 struct ac_shader_variant_info *shader_info,
5211 const struct ac_nir_compiler_options *options,
5212 bool dump_shader)
5213 {
5214 struct nir_to_llvm_context ctx = {0};
5215 ctx.context = LLVMContextCreate();
5216 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5217 ctx.options = options;
5218 ctx.shader_info = shader_info;
5219
5220 ac_llvm_context_init(&ctx.ac, ctx.context);
5221 ctx.ac.module = ctx.module;
5222
5223 ctx.is_gs_copy_shader = true;
5224 LLVMSetTarget(ctx.module, "amdgcn--");
5225 setup_types(&ctx);
5226
5227 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5228 ctx.ac.builder = ctx.builder;
5229 ctx.stage = MESA_SHADER_VERTEX;
5230
5231 create_function(&ctx);
5232
5233 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5234 ac_setup_rings(&ctx);
5235
5236 ctx.num_output_clips = geom_shader->info->clip_distance_array_size;
5237 ctx.num_output_culls = geom_shader->info->cull_distance_array_size;
5238
5239 nir_foreach_variable(variable, &geom_shader->outputs)
5240 handle_shader_output_decl(&ctx, variable);
5241
5242 ac_gs_copy_shader_emit(&ctx);
5243
5244 LLVMBuildRetVoid(ctx.builder);
5245
5246 ac_llvm_finalize_module(&ctx);
5247
5248 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5249 MESA_SHADER_VERTEX,
5250 dump_shader, options->supports_spill);
5251 }