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ac/nir: Implement input attachments with layered rendering.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct nir_to_llvm_context;
51
52 struct ac_nir_context {
53 struct ac_llvm_context ac;
54 struct ac_shader_abi *abi;
55
56 gl_shader_stage stage;
57
58 struct hash_table *defs;
59 struct hash_table *phis;
60 struct hash_table *vars;
61
62 LLVMValueRef main_function;
63 LLVMBasicBlockRef continue_block;
64 LLVMBasicBlockRef break_block;
65
66 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
67
68 int num_locals;
69 LLVMValueRef *locals;
70
71 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
72 };
73
74 struct nir_to_llvm_context {
75 struct ac_llvm_context ac;
76 const struct ac_nir_compiler_options *options;
77 struct ac_shader_variant_info *shader_info;
78 struct ac_shader_abi abi;
79 struct ac_nir_context *nir;
80
81 unsigned max_workgroup_size;
82 LLVMContextRef context;
83 LLVMModuleRef module;
84 LLVMBuilderRef builder;
85 LLVMValueRef main_function;
86
87 struct hash_table *defs;
88 struct hash_table *phis;
89
90 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
91 LLVMValueRef ring_offsets;
92 LLVMValueRef push_constants;
93 LLVMValueRef num_work_groups;
94 LLVMValueRef workgroup_ids;
95 LLVMValueRef local_invocation_ids;
96 LLVMValueRef tg_size;
97
98 LLVMValueRef vertex_buffers;
99 LLVMValueRef rel_auto_id;
100 LLVMValueRef vs_prim_id;
101 LLVMValueRef ls_out_layout;
102 LLVMValueRef es2gs_offset;
103
104 LLVMValueRef tcs_offchip_layout;
105 LLVMValueRef tcs_out_offsets;
106 LLVMValueRef tcs_out_layout;
107 LLVMValueRef tcs_in_layout;
108 LLVMValueRef oc_lds;
109 LLVMValueRef tess_factor_offset;
110 LLVMValueRef tcs_patch_id;
111 LLVMValueRef tcs_rel_ids;
112 LLVMValueRef tes_rel_patch_id;
113 LLVMValueRef tes_patch_id;
114 LLVMValueRef tes_u;
115 LLVMValueRef tes_v;
116
117 LLVMValueRef gsvs_ring_stride;
118 LLVMValueRef gsvs_num_entries;
119 LLVMValueRef gs2vs_offset;
120 LLVMValueRef gs_wave_id;
121 LLVMValueRef gs_vtx_offset[6];
122 LLVMValueRef gs_prim_id, gs_invocation_id;
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 LLVMTypeRef i1;
135 LLVMTypeRef i8;
136 LLVMTypeRef i16;
137 LLVMTypeRef i32;
138 LLVMTypeRef i64;
139 LLVMTypeRef v2i32;
140 LLVMTypeRef v3i32;
141 LLVMTypeRef v4i32;
142 LLVMTypeRef v8i32;
143 LLVMTypeRef f64;
144 LLVMTypeRef f32;
145 LLVMTypeRef f16;
146 LLVMTypeRef v2f32;
147 LLVMTypeRef v4f32;
148 LLVMTypeRef voidt;
149
150 LLVMValueRef i1true;
151 LLVMValueRef i1false;
152 LLVMValueRef i32zero;
153 LLVMValueRef i32one;
154 LLVMValueRef f32zero;
155 LLVMValueRef f32one;
156 LLVMValueRef v4f32empty;
157
158 unsigned uniform_md_kind;
159 LLVMValueRef empty_md;
160 gl_shader_stage stage;
161
162 LLVMValueRef lds;
163 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
164
165 uint64_t input_mask;
166 uint64_t output_mask;
167 uint8_t num_output_clips;
168 uint8_t num_output_culls;
169
170 bool is_gs_copy_shader;
171 LLVMValueRef gs_next_vertex;
172 unsigned gs_max_out_vertices;
173
174 unsigned tes_primitive_mode;
175 uint64_t tess_outputs_written;
176 uint64_t tess_patch_outputs_written;
177 };
178
179 static inline struct nir_to_llvm_context *
180 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
181 {
182 struct nir_to_llvm_context *ctx = NULL;
183 return container_of(abi, ctx, abi);
184 }
185
186 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
187 const nir_deref_var *deref,
188 enum ac_descriptor_type desc_type,
189 bool image, bool write);
190
191 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
192 {
193 return (index * 4) + chan;
194 }
195
196 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
197 {
198 /* handle patch indices separate */
199 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
200 return 0;
201 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
202 return 1;
203 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
204 return 2 + (slot - VARYING_SLOT_PATCH0);
205
206 if (slot == VARYING_SLOT_POS)
207 return 0;
208 if (slot == VARYING_SLOT_PSIZ)
209 return 1;
210 if (slot == VARYING_SLOT_CLIP_DIST0)
211 return 2;
212 /* 3 is reserved for clip dist as well */
213 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
214 return 4 + (slot - VARYING_SLOT_VAR0);
215 unreachable("illegal slot in get unique index\n");
216 }
217
218 static unsigned llvm_get_type_size(LLVMTypeRef type)
219 {
220 LLVMTypeKind kind = LLVMGetTypeKind(type);
221
222 switch (kind) {
223 case LLVMIntegerTypeKind:
224 return LLVMGetIntTypeWidth(type) / 8;
225 case LLVMFloatTypeKind:
226 return 4;
227 case LLVMPointerTypeKind:
228 return 8;
229 case LLVMVectorTypeKind:
230 return LLVMGetVectorSize(type) *
231 llvm_get_type_size(LLVMGetElementType(type));
232 default:
233 assert(0);
234 return 0;
235 }
236 }
237
238 static void set_llvm_calling_convention(LLVMValueRef func,
239 gl_shader_stage stage)
240 {
241 enum radeon_llvm_calling_convention calling_conv;
242
243 switch (stage) {
244 case MESA_SHADER_VERTEX:
245 case MESA_SHADER_TESS_CTRL:
246 case MESA_SHADER_TESS_EVAL:
247 calling_conv = RADEON_LLVM_AMDGPU_VS;
248 break;
249 case MESA_SHADER_GEOMETRY:
250 calling_conv = RADEON_LLVM_AMDGPU_GS;
251 break;
252 case MESA_SHADER_FRAGMENT:
253 calling_conv = RADEON_LLVM_AMDGPU_PS;
254 break;
255 case MESA_SHADER_COMPUTE:
256 calling_conv = RADEON_LLVM_AMDGPU_CS;
257 break;
258 default:
259 unreachable("Unhandle shader type");
260 }
261
262 LLVMSetFunctionCallConv(func, calling_conv);
263 }
264
265 #define MAX_ARGS 23
266 struct arg_info {
267 LLVMTypeRef types[MAX_ARGS];
268 LLVMValueRef *assign[MAX_ARGS];
269 unsigned array_params_mask;
270 uint8_t count;
271 uint8_t user_sgpr_count;
272 uint8_t sgpr_count;
273 uint8_t num_user_sgprs_used;
274 uint8_t num_sgprs_used;
275 uint8_t num_vgprs_used;
276 };
277
278 static inline void
279 add_argument(struct arg_info *info,
280 LLVMTypeRef type, LLVMValueRef *param_ptr)
281 {
282 assert(info->count < MAX_ARGS);
283 info->assign[info->count] = param_ptr;
284 info->types[info->count] = type;
285 info->count++;
286 }
287
288 static inline void
289 add_sgpr_argument(struct arg_info *info,
290 LLVMTypeRef type, LLVMValueRef *param_ptr)
291 {
292 add_argument(info, type, param_ptr);
293 info->num_sgprs_used += llvm_get_type_size(type) / 4;
294 info->sgpr_count++;
295 }
296
297 static inline void
298 add_user_sgpr_argument(struct arg_info *info,
299 LLVMTypeRef type,
300 LLVMValueRef *param_ptr)
301 {
302 add_sgpr_argument(info, type, param_ptr);
303 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
304 info->user_sgpr_count++;
305 }
306
307 static inline void
308 add_vgpr_argument(struct arg_info *info,
309 LLVMTypeRef type,
310 LLVMValueRef *param_ptr)
311 {
312 add_argument(info, type, param_ptr);
313 info->num_vgprs_used += llvm_get_type_size(type) / 4;
314 }
315
316 static inline void
317 add_user_sgpr_array_argument(struct arg_info *info,
318 LLVMTypeRef type,
319 LLVMValueRef *param_ptr)
320 {
321 info->array_params_mask |= (1 << info->count);
322 add_user_sgpr_argument(info, type, param_ptr);
323 }
324
325 static void assign_arguments(LLVMValueRef main_function,
326 struct arg_info *info)
327 {
328 unsigned i;
329 for (i = 0; i < info->count; i++) {
330 if (info->assign[i])
331 *info->assign[i] = LLVMGetParam(main_function, i);
332 }
333 }
334
335 static LLVMValueRef
336 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
337 LLVMBuilderRef builder, LLVMTypeRef *return_types,
338 unsigned num_return_elems,
339 struct arg_info *args,
340 unsigned max_workgroup_size,
341 bool unsafe_math)
342 {
343 LLVMTypeRef main_function_type, ret_type;
344 LLVMBasicBlockRef main_function_body;
345
346 if (num_return_elems)
347 ret_type = LLVMStructTypeInContext(ctx, return_types,
348 num_return_elems, true);
349 else
350 ret_type = LLVMVoidTypeInContext(ctx);
351
352 /* Setup the function */
353 main_function_type =
354 LLVMFunctionType(ret_type, args->types, args->count, 0);
355 LLVMValueRef main_function =
356 LLVMAddFunction(module, "main", main_function_type);
357 main_function_body =
358 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
359 LLVMPositionBuilderAtEnd(builder, main_function_body);
360
361 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
362 for (unsigned i = 0; i < args->sgpr_count; ++i) {
363 if (args->array_params_mask & (1 << i)) {
364 LLVMValueRef P = LLVMGetParam(main_function, i);
365 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
366 ac_add_attr_dereferenceable(P, UINT64_MAX);
367 }
368 else {
369 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
370 }
371 }
372
373 if (max_workgroup_size) {
374 ac_llvm_add_target_dep_function_attr(main_function,
375 "amdgpu-max-work-group-size",
376 max_workgroup_size);
377 }
378 if (unsafe_math) {
379 /* These were copied from some LLVM test. */
380 LLVMAddTargetDependentFunctionAttr(main_function,
381 "less-precise-fpmad",
382 "true");
383 LLVMAddTargetDependentFunctionAttr(main_function,
384 "no-infs-fp-math",
385 "true");
386 LLVMAddTargetDependentFunctionAttr(main_function,
387 "no-nans-fp-math",
388 "true");
389 LLVMAddTargetDependentFunctionAttr(main_function,
390 "unsafe-fp-math",
391 "true");
392 }
393 return main_function;
394 }
395
396 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
397 {
398 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
399 CONST_ADDR_SPACE);
400 }
401
402 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
403 {
404 if (t == ctx->f16 || t == ctx->i16)
405 return ctx->i16;
406 else if (t == ctx->f32 || t == ctx->i32)
407 return ctx->i32;
408 else if (t == ctx->f64 || t == ctx->i64)
409 return ctx->i64;
410 else
411 unreachable("Unhandled integer size");
412 }
413
414 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
415 {
416 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
417 LLVMTypeRef elem_type = LLVMGetElementType(t);
418 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
419 LLVMGetVectorSize(t));
420 }
421 return to_integer_type_scalar(ctx, t);
422 }
423
424 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
425 {
426 LLVMTypeRef type = LLVMTypeOf(v);
427 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
428 }
429
430 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
431 {
432 if (t == ctx->i16 || t == ctx->f16)
433 return ctx->f16;
434 else if (t == ctx->i32 || t == ctx->f32)
435 return ctx->f32;
436 else if (t == ctx->i64 || t == ctx->f64)
437 return ctx->f64;
438 else
439 unreachable("Unhandled float size");
440 }
441
442 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
443 {
444 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
445 LLVMTypeRef elem_type = LLVMGetElementType(t);
446 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
447 LLVMGetVectorSize(t));
448 }
449 return to_float_type_scalar(ctx, t);
450 }
451
452 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
453 {
454 LLVMTypeRef type = LLVMTypeOf(v);
455 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
456 }
457
458 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
459 {
460 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
461 type = LLVMGetElementType(type);
462
463 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
464 return LLVMGetIntTypeWidth(type);
465
466 if (type == ctx->f16)
467 return 16;
468 if (type == ctx->f32)
469 return 32;
470 if (type == ctx->f64)
471 return 64;
472
473 unreachable("Unhandled type kind in get_elem_bits");
474 }
475
476 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
477 LLVMValueRef param, unsigned rshift,
478 unsigned bitwidth)
479 {
480 LLVMValueRef value = param;
481 if (rshift)
482 value = LLVMBuildLShr(ctx->builder, value,
483 LLVMConstInt(ctx->i32, rshift, false), "");
484
485 if (rshift + bitwidth < 32) {
486 unsigned mask = (1 << bitwidth) - 1;
487 value = LLVMBuildAnd(ctx->builder, value,
488 LLVMConstInt(ctx->i32, mask, false), "");
489 }
490 return value;
491 }
492
493 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
494 {
495 switch (ctx->stage) {
496 case MESA_SHADER_TESS_CTRL:
497 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
498 case MESA_SHADER_TESS_EVAL:
499 return ctx->tes_rel_patch_id;
500 break;
501 default:
502 unreachable("Illegal stage");
503 }
504 }
505
506 /* Tessellation shaders pass outputs to the next shader using LDS.
507 *
508 * LS outputs = TCS inputs
509 * TCS outputs = TES inputs
510 *
511 * The LDS layout is:
512 * - TCS inputs for patch 0
513 * - TCS inputs for patch 1
514 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
515 * - ...
516 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
517 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
518 * - TCS outputs for patch 1
519 * - Per-patch TCS outputs for patch 1
520 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
521 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
522 * - ...
523 *
524 * All three shaders VS(LS), TCS, TES share the same LDS space.
525 */
526 static LLVMValueRef
527 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
528 {
529 if (ctx->stage == MESA_SHADER_VERTEX)
530 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
531 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
532 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
533 else {
534 assert(0);
535 return NULL;
536 }
537 }
538
539 static LLVMValueRef
540 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
541 {
542 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
543 }
544
545 static LLVMValueRef
546 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
547 {
548 return LLVMBuildMul(ctx->builder,
549 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
550 LLVMConstInt(ctx->i32, 4, false), "");
551 }
552
553 static LLVMValueRef
554 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
555 {
556 return LLVMBuildMul(ctx->builder,
557 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
558 LLVMConstInt(ctx->i32, 4, false), "");
559 }
560
561 static LLVMValueRef
562 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
563 {
564 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
565 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
566
567 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
568 }
569
570 static LLVMValueRef
571 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
572 {
573 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
574 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
575 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
576
577 return LLVMBuildAdd(ctx->builder, patch0_offset,
578 LLVMBuildMul(ctx->builder, patch_stride,
579 rel_patch_id, ""),
580 "");
581 }
582
583 static LLVMValueRef
584 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
585 {
586 LLVMValueRef patch0_patch_data_offset =
587 get_tcs_out_patch0_patch_data_offset(ctx);
588 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
589 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
590
591 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
592 LLVMBuildMul(ctx->builder, patch_stride,
593 rel_patch_id, ""),
594 "");
595 }
596
597 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
598 {
599 ud_info->sgpr_idx = *sgpr_idx;
600 ud_info->num_sgprs = num_sgprs;
601 ud_info->indirect = false;
602 ud_info->indirect_offset = 0;
603 *sgpr_idx += num_sgprs;
604 }
605
606 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
607 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
608 {
609 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
610 }
611
612
613 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
614 uint32_t indirect_offset)
615 {
616 ud_info->sgpr_idx = sgpr_idx;
617 ud_info->num_sgprs = num_sgprs;
618 ud_info->indirect = true;
619 ud_info->indirect_offset = indirect_offset;
620 }
621
622 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
623 {
624 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
625 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
626 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
627 "tess_lds");
628 }
629
630 struct user_sgpr_info {
631 bool need_ring_offsets;
632 uint8_t sgpr_count;
633 bool indirect_all_descriptor_sets;
634 };
635
636 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
637 struct user_sgpr_info *user_sgpr_info)
638 {
639 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
640
641 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
642 if (ctx->stage == MESA_SHADER_GEOMETRY ||
643 ctx->stage == MESA_SHADER_VERTEX ||
644 ctx->stage == MESA_SHADER_TESS_CTRL ||
645 ctx->stage == MESA_SHADER_TESS_EVAL ||
646 ctx->is_gs_copy_shader)
647 user_sgpr_info->need_ring_offsets = true;
648
649 if (ctx->stage == MESA_SHADER_FRAGMENT &&
650 ctx->shader_info->info.ps.needs_sample_positions)
651 user_sgpr_info->need_ring_offsets = true;
652
653 /* 2 user sgprs will nearly always be allocated for scratch/rings */
654 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
655 user_sgpr_info->sgpr_count += 2;
656 }
657
658 switch (ctx->stage) {
659 case MESA_SHADER_COMPUTE:
660 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
661 break;
662 case MESA_SHADER_FRAGMENT:
663 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
664 break;
665 case MESA_SHADER_VERTEX:
666 if (!ctx->is_gs_copy_shader) {
667 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
668 if (ctx->shader_info->info.vs.needs_draw_id) {
669 user_sgpr_info->sgpr_count += 3;
670 } else {
671 user_sgpr_info->sgpr_count += 2;
672 }
673 }
674 if (ctx->options->key.vs.as_ls)
675 user_sgpr_info->sgpr_count++;
676 break;
677 case MESA_SHADER_TESS_CTRL:
678 user_sgpr_info->sgpr_count += 4;
679 break;
680 case MESA_SHADER_TESS_EVAL:
681 user_sgpr_info->sgpr_count += 1;
682 break;
683 case MESA_SHADER_GEOMETRY:
684 user_sgpr_info->sgpr_count += 2;
685 break;
686 default:
687 break;
688 }
689
690 if (ctx->shader_info->info.needs_push_constants)
691 user_sgpr_info->sgpr_count += 2;
692
693 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
694 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
695 user_sgpr_info->sgpr_count += 2;
696 user_sgpr_info->indirect_all_descriptor_sets = true;
697 } else {
698 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
699 }
700 }
701
702 static void create_function(struct nir_to_llvm_context *ctx)
703 {
704 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
705 uint8_t user_sgpr_idx;
706 struct user_sgpr_info user_sgpr_info;
707 struct arg_info args = {};
708 LLVMValueRef desc_sets;
709
710 allocate_user_sgprs(ctx, &user_sgpr_info);
711 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
712 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
713 }
714
715 /* 1 for each descriptor set */
716 if (!user_sgpr_info.indirect_all_descriptor_sets) {
717 for (unsigned i = 0; i < num_sets; ++i) {
718 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
719 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
720 }
721 }
722 } else
723 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
724
725 if (ctx->shader_info->info.needs_push_constants) {
726 /* 1 for push constants and dynamic descriptors */
727 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
728 }
729
730 switch (ctx->stage) {
731 case MESA_SHADER_COMPUTE:
732 if (ctx->shader_info->info.cs.grid_components_used)
733 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
734 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
735 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
736 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
737 break;
738 case MESA_SHADER_VERTEX:
739 if (!ctx->is_gs_copy_shader) {
740 if (ctx->shader_info->info.vs.has_vertex_buffers)
741 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
742 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
743 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
744 if (ctx->shader_info->info.vs.needs_draw_id)
745 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
746 }
747 if (ctx->options->key.vs.as_es)
748 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
749 else if (ctx->options->key.vs.as_ls)
750 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
751 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
752 if (!ctx->is_gs_copy_shader) {
753 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
754 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
755 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
756 }
757 break;
758 case MESA_SHADER_TESS_CTRL:
759 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
760 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
761 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
762 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
763 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
764 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
765 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
766 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
767 break;
768 case MESA_SHADER_TESS_EVAL:
769 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
770 if (ctx->options->key.tes.as_es) {
771 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
772 add_sgpr_argument(&args, ctx->i32, NULL); //
773 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
774 } else {
775 add_sgpr_argument(&args, ctx->i32, NULL); //
776 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
777 }
778 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
779 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
780 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
781 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
782 break;
783 case MESA_SHADER_GEOMETRY:
784 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
785 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
786 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
787 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
788 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
789 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
790 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
791 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
792 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
793 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
796 break;
797 case MESA_SHADER_FRAGMENT:
798 if (ctx->shader_info->info.ps.needs_sample_positions)
799 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
800 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
801 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
802 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
803 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
804 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
805 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
806 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
807 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
808 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
809 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */
810 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */
811 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */
812 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */
813 add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /* front face */
814 add_vgpr_argument(&args, ctx->i32, &ctx->abi.ancillary); /* ancillary */
815 add_vgpr_argument(&args, ctx->i32, &ctx->abi.sample_coverage); /* sample coverage */
816 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
817 break;
818 default:
819 unreachable("Shader stage not implemented");
820 }
821
822 ctx->main_function = create_llvm_function(
823 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
824 ctx->max_workgroup_size,
825 ctx->options->unsafe_math);
826 set_llvm_calling_convention(ctx->main_function, ctx->stage);
827
828
829 ctx->shader_info->num_input_vgprs = 0;
830 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
831 ctx->options->supports_spill ? 2 : 0;
832
833 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
834 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
835
836 if (ctx->stage != MESA_SHADER_FRAGMENT)
837 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
838
839 assign_arguments(ctx->main_function, &args);
840
841 user_sgpr_idx = 0;
842
843 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
844 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
845 if (ctx->options->supports_spill) {
846 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
847 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
848 NULL, 0, AC_FUNC_ATTR_READNONE);
849 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
850 const_array(ctx->v4i32, 16), "");
851 }
852 }
853
854 if (!user_sgpr_info.indirect_all_descriptor_sets) {
855 for (unsigned i = 0; i < num_sets; ++i) {
856 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
857 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
858 } else
859 ctx->descriptor_sets[i] = NULL;
860 }
861 } else {
862 uint32_t desc_sgpr_idx = user_sgpr_idx;
863 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
864
865 for (unsigned i = 0; i < num_sets; ++i) {
866 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
867 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
868 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
869
870 } else
871 ctx->descriptor_sets[i] = NULL;
872 }
873 ctx->shader_info->need_indirect_descriptor_sets = true;
874 }
875
876 if (ctx->shader_info->info.needs_push_constants) {
877 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
878 }
879
880 switch (ctx->stage) {
881 case MESA_SHADER_COMPUTE:
882 if (ctx->shader_info->info.cs.grid_components_used) {
883 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
884 }
885 break;
886 case MESA_SHADER_VERTEX:
887 if (!ctx->is_gs_copy_shader) {
888 if (ctx->shader_info->info.vs.has_vertex_buffers) {
889 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
890 }
891 unsigned vs_num = 2;
892 if (ctx->shader_info->info.vs.needs_draw_id)
893 vs_num++;
894
895 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
896 }
897 if (ctx->options->key.vs.as_ls) {
898 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
899 }
900 if (ctx->options->key.vs.as_ls)
901 declare_tess_lds(ctx);
902 break;
903 case MESA_SHADER_TESS_CTRL:
904 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
905 declare_tess_lds(ctx);
906 break;
907 case MESA_SHADER_TESS_EVAL:
908 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
909 break;
910 case MESA_SHADER_GEOMETRY:
911 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
912 break;
913 case MESA_SHADER_FRAGMENT:
914 if (ctx->shader_info->info.ps.needs_sample_positions) {
915 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
916 }
917 break;
918 default:
919 unreachable("Shader stage not implemented");
920 }
921 }
922
923 static void setup_types(struct nir_to_llvm_context *ctx)
924 {
925 LLVMValueRef args[4];
926
927 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
928 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
929 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
930 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
931 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
932 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
933 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
934 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
935 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
936 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
937 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
938 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
939 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
940 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
941 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
942
943 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
944 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
945 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
946 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
947 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
948 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
949
950 args[0] = ctx->f32zero;
951 args[1] = ctx->f32zero;
952 args[2] = ctx->f32zero;
953 args[3] = ctx->f32one;
954 ctx->v4f32empty = LLVMConstVector(args, 4);
955
956 ctx->uniform_md_kind =
957 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
958 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
959
960 args[0] = LLVMConstReal(ctx->f32, 2.5);
961 }
962
963 static int get_llvm_num_components(LLVMValueRef value)
964 {
965 LLVMTypeRef type = LLVMTypeOf(value);
966 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
967 ? LLVMGetVectorSize(type)
968 : 1;
969 return num_components;
970 }
971
972 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
973 LLVMValueRef value,
974 int index)
975 {
976 int count = get_llvm_num_components(value);
977
978 assert(index < count);
979 if (count == 1)
980 return value;
981
982 return LLVMBuildExtractElement(ac->builder, value,
983 LLVMConstInt(ac->i32, index, false), "");
984 }
985
986 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
987 LLVMValueRef value, unsigned count)
988 {
989 unsigned num_components = get_llvm_num_components(value);
990 if (count == num_components)
991 return value;
992
993 LLVMValueRef masks[] = {
994 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
995 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
996
997 if (count == 1)
998 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
999 "");
1000
1001 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1002 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1003 }
1004
1005 static void
1006 build_store_values_extended(struct ac_llvm_context *ac,
1007 LLVMValueRef *values,
1008 unsigned value_count,
1009 unsigned value_stride,
1010 LLVMValueRef vec)
1011 {
1012 LLVMBuilderRef builder = ac->builder;
1013 unsigned i;
1014
1015 for (i = 0; i < value_count; i++) {
1016 LLVMValueRef ptr = values[i * value_stride];
1017 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1018 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1019 LLVMBuildStore(builder, value, ptr);
1020 }
1021 }
1022
1023 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1024 const nir_ssa_def *def)
1025 {
1026 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1027 if (def->num_components > 1) {
1028 type = LLVMVectorType(type, def->num_components);
1029 }
1030 return type;
1031 }
1032
1033 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1034 {
1035 assert(src.is_ssa);
1036 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1037 return (LLVMValueRef)entry->data;
1038 }
1039
1040
1041 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1042 const struct nir_block *b)
1043 {
1044 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1045 return (LLVMBasicBlockRef)entry->data;
1046 }
1047
1048 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1049 nir_alu_src src,
1050 unsigned num_components)
1051 {
1052 LLVMValueRef value = get_src(ctx, src.src);
1053 bool need_swizzle = false;
1054
1055 assert(value);
1056 LLVMTypeRef type = LLVMTypeOf(value);
1057 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1058 ? LLVMGetVectorSize(type)
1059 : 1;
1060
1061 for (unsigned i = 0; i < num_components; ++i) {
1062 assert(src.swizzle[i] < src_components);
1063 if (src.swizzle[i] != i)
1064 need_swizzle = true;
1065 }
1066
1067 if (need_swizzle || num_components != src_components) {
1068 LLVMValueRef masks[] = {
1069 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1070 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1071 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1072 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1073
1074 if (src_components > 1 && num_components == 1) {
1075 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1076 masks[0], "");
1077 } else if (src_components == 1 && num_components > 1) {
1078 LLVMValueRef values[] = {value, value, value, value};
1079 value = ac_build_gather_values(&ctx->ac, values, num_components);
1080 } else {
1081 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1082 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1083 swizzle, "");
1084 }
1085 }
1086 assert(!src.negate);
1087 assert(!src.abs);
1088 return value;
1089 }
1090
1091 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1092 LLVMIntPredicate pred, LLVMValueRef src0,
1093 LLVMValueRef src1)
1094 {
1095 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1096 return LLVMBuildSelect(ctx->builder, result,
1097 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1098 LLVMConstInt(ctx->i32, 0, false), "");
1099 }
1100
1101 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1102 LLVMRealPredicate pred, LLVMValueRef src0,
1103 LLVMValueRef src1)
1104 {
1105 LLVMValueRef result;
1106 src0 = to_float(ctx, src0);
1107 src1 = to_float(ctx, src1);
1108 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1109 return LLVMBuildSelect(ctx->builder, result,
1110 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1111 LLVMConstInt(ctx->i32, 0, false), "");
1112 }
1113
1114 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1115 const char *intrin,
1116 LLVMTypeRef result_type,
1117 LLVMValueRef src0)
1118 {
1119 char name[64];
1120 LLVMValueRef params[] = {
1121 to_float(ctx, src0),
1122 };
1123
1124 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1125 get_elem_bits(ctx, result_type));
1126 assert(length < sizeof(name));
1127 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1128 }
1129
1130 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1131 const char *intrin,
1132 LLVMTypeRef result_type,
1133 LLVMValueRef src0, LLVMValueRef src1)
1134 {
1135 char name[64];
1136 LLVMValueRef params[] = {
1137 to_float(ctx, src0),
1138 to_float(ctx, src1),
1139 };
1140
1141 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1142 get_elem_bits(ctx, result_type));
1143 assert(length < sizeof(name));
1144 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1145 }
1146
1147 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1148 const char *intrin,
1149 LLVMTypeRef result_type,
1150 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1151 {
1152 char name[64];
1153 LLVMValueRef params[] = {
1154 to_float(ctx, src0),
1155 to_float(ctx, src1),
1156 to_float(ctx, src2),
1157 };
1158
1159 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1160 get_elem_bits(ctx, result_type));
1161 assert(length < sizeof(name));
1162 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1163 }
1164
1165 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1166 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1167 {
1168 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1169 ctx->i32_0, "");
1170 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1171 }
1172
1173 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1174 LLVMValueRef src0)
1175 {
1176 LLVMValueRef params[2] = {
1177 src0,
1178
1179 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1180 * add special code to check for x=0. The reason is that
1181 * the LLVM behavior for x=0 is different from what we
1182 * need here.
1183 *
1184 * The hardware already implements the correct behavior.
1185 */
1186 LLVMConstInt(ctx->i1, 1, false),
1187 };
1188
1189 LLVMValueRef lsb = ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32,
1190 params, 2,
1191 AC_FUNC_ATTR_READNONE);
1192
1193 /* TODO: We need an intrinsic to skip this conditional. */
1194 /* Check for zero: */
1195 return LLVMBuildSelect(ctx->builder, LLVMBuildICmp(ctx->builder,
1196 LLVMIntEQ, src0,
1197 ctx->i32_0, ""),
1198 LLVMConstInt(ctx->i32, -1, 0), lsb, "");
1199 }
1200
1201 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1202 LLVMValueRef src0)
1203 {
1204 return ac_build_imsb(ctx, src0, ctx->i32);
1205 }
1206
1207 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1208 LLVMValueRef src0)
1209 {
1210 return ac_build_umsb(ctx, src0, ctx->i32);
1211 }
1212
1213 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1214 LLVMIntPredicate pred,
1215 LLVMValueRef src0, LLVMValueRef src1)
1216 {
1217 return LLVMBuildSelect(ctx->builder,
1218 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1219 src0,
1220 src1, "");
1221
1222 }
1223 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1224 LLVMValueRef src0)
1225 {
1226 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1227 LLVMBuildNeg(ctx->builder, src0, ""));
1228 }
1229
1230 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1231 LLVMValueRef src0)
1232 {
1233 LLVMValueRef cmp, val;
1234
1235 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1236 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1237 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1238 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1239 return val;
1240 }
1241
1242 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1243 LLVMValueRef src0)
1244 {
1245 LLVMValueRef cmp, val;
1246
1247 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1248 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1249 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1250 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1251 return val;
1252 }
1253
1254 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1255 LLVMValueRef src0)
1256 {
1257 const char *intr = "llvm.floor.f32";
1258 LLVMValueRef fsrc0 = to_float(ctx, src0);
1259 LLVMValueRef params[] = {
1260 fsrc0,
1261 };
1262 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1263 ctx->f32, params, 1,
1264 AC_FUNC_ATTR_READNONE);
1265 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1266 }
1267
1268 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1269 const char *intrin,
1270 LLVMValueRef src0, LLVMValueRef src1)
1271 {
1272 LLVMTypeRef ret_type;
1273 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1274 LLVMValueRef res;
1275 LLVMValueRef params[] = { src0, src1 };
1276 ret_type = LLVMStructTypeInContext(ctx->context, types,
1277 2, true);
1278
1279 res = ac_build_intrinsic(ctx, intrin, ret_type,
1280 params, 2, AC_FUNC_ATTR_READNONE);
1281
1282 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1283 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1284 return res;
1285 }
1286
1287 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1288 LLVMValueRef src0)
1289 {
1290 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1291 }
1292
1293 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1294 LLVMValueRef src0)
1295 {
1296 src0 = to_float(ctx, src0);
1297 return LLVMBuildSExt(ctx->builder,
1298 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1299 ctx->i32, "");
1300 }
1301
1302 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1303 LLVMValueRef src0)
1304 {
1305 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1306 }
1307
1308 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1309 LLVMValueRef src0)
1310 {
1311 return LLVMBuildSExt(ctx->builder,
1312 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1313 ctx->i32, "");
1314 }
1315
1316 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1317 LLVMValueRef src0)
1318 {
1319 LLVMValueRef result;
1320 LLVMValueRef cond;
1321
1322 src0 = to_float(&ctx->ac, src0);
1323 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1324
1325 if (ctx->options->chip_class >= VI) {
1326 LLVMValueRef args[2];
1327 /* Check if the result is a denormal - and flush to 0 if so. */
1328 args[0] = result;
1329 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1330 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1331 }
1332
1333 /* need to convert back up to f32 */
1334 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1335
1336 if (ctx->options->chip_class >= VI)
1337 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1338 else {
1339 /* for SI/CIK */
1340 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1341 * so compare the result and flush to 0 if it's smaller.
1342 */
1343 LLVMValueRef temp, cond2;
1344 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1345 ctx->f32, result);
1346 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1347 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1348 temp, "");
1349 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1350 temp, ctx->f32zero, "");
1351 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1352 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1353 }
1354 return result;
1355 }
1356
1357 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1358 LLVMValueRef src0, LLVMValueRef src1)
1359 {
1360 LLVMValueRef dst64, result;
1361 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1362 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1363
1364 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1365 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1366 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1367 return result;
1368 }
1369
1370 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1371 LLVMValueRef src0, LLVMValueRef src1)
1372 {
1373 LLVMValueRef dst64, result;
1374 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1375 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1376
1377 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1378 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1379 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1380 return result;
1381 }
1382
1383 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1384 bool is_signed,
1385 const LLVMValueRef srcs[3])
1386 {
1387 LLVMValueRef result;
1388 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1389
1390 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1391 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1392 return result;
1393 }
1394
1395 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1396 LLVMValueRef src0, LLVMValueRef src1,
1397 LLVMValueRef src2, LLVMValueRef src3)
1398 {
1399 LLVMValueRef bfi_args[3], result;
1400
1401 bfi_args[0] = LLVMBuildShl(ctx->builder,
1402 LLVMBuildSub(ctx->builder,
1403 LLVMBuildShl(ctx->builder,
1404 ctx->i32_1,
1405 src3, ""),
1406 ctx->i32_1, ""),
1407 src2, "");
1408 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1409 bfi_args[2] = src0;
1410
1411 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1412
1413 /* Calculate:
1414 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1415 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1416 */
1417 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1418 LLVMBuildAnd(ctx->builder, bfi_args[0],
1419 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1420
1421 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1422 return result;
1423 }
1424
1425 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1426 LLVMValueRef src0)
1427 {
1428 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1429 int i;
1430 LLVMValueRef comp[2];
1431
1432 src0 = to_float(ctx, src0);
1433 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1434 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1435 for (i = 0; i < 2; i++) {
1436 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1437 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1438 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1439 }
1440
1441 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1442 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1443
1444 return comp[0];
1445 }
1446
1447 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1448 LLVMValueRef src0)
1449 {
1450 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1451 LLVMValueRef temps[2], result, val;
1452 int i;
1453
1454 for (i = 0; i < 2; i++) {
1455 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1456 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1457 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1458 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1459 }
1460
1461 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1462 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1463 ctx->i32_0, "");
1464 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1465 ctx->i32_1, "");
1466 return result;
1467 }
1468
1469 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1470 nir_op op,
1471 LLVMValueRef src0)
1472 {
1473 unsigned mask;
1474 int idx;
1475 LLVMValueRef result;
1476 bool has_ds_bpermute = ctx->abi->chip_class >= VI;
1477
1478 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1479 mask = AC_TID_MASK_LEFT;
1480 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1481 mask = AC_TID_MASK_TOP;
1482 else
1483 mask = AC_TID_MASK_TOP_LEFT;
1484
1485 /* for DDX we want to next X pixel, DDY next Y pixel. */
1486 if (op == nir_op_fddx_fine ||
1487 op == nir_op_fddx_coarse ||
1488 op == nir_op_fddx)
1489 idx = 1;
1490 else
1491 idx = 2;
1492
1493 result = ac_build_ddxy(&ctx->ac, has_ds_bpermute,
1494 mask, idx,
1495 src0);
1496 return result;
1497 }
1498
1499 /*
1500 * this takes an I,J coordinate pair,
1501 * and works out the X and Y derivatives.
1502 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1503 */
1504 static LLVMValueRef emit_ddxy_interp(
1505 struct ac_nir_context *ctx,
1506 LLVMValueRef interp_ij)
1507 {
1508 LLVMValueRef result[4], a;
1509 unsigned i;
1510
1511 for (i = 0; i < 2; i++) {
1512 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1513 LLVMConstInt(ctx->ac.i32, i, false), "");
1514 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1515 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1516 }
1517 return ac_build_gather_values(&ctx->ac, result, 4);
1518 }
1519
1520 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1521 {
1522 LLVMValueRef src[4], result = NULL;
1523 unsigned num_components = instr->dest.dest.ssa.num_components;
1524 unsigned src_components;
1525 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1526
1527 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1528 switch (instr->op) {
1529 case nir_op_vec2:
1530 case nir_op_vec3:
1531 case nir_op_vec4:
1532 src_components = 1;
1533 break;
1534 case nir_op_pack_half_2x16:
1535 src_components = 2;
1536 break;
1537 case nir_op_unpack_half_2x16:
1538 src_components = 1;
1539 break;
1540 default:
1541 src_components = num_components;
1542 break;
1543 }
1544 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1545 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1546
1547 switch (instr->op) {
1548 case nir_op_fmov:
1549 case nir_op_imov:
1550 result = src[0];
1551 break;
1552 case nir_op_fneg:
1553 src[0] = to_float(&ctx->ac, src[0]);
1554 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1555 break;
1556 case nir_op_ineg:
1557 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1558 break;
1559 case nir_op_inot:
1560 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1561 break;
1562 case nir_op_iadd:
1563 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1564 break;
1565 case nir_op_fadd:
1566 src[0] = to_float(&ctx->ac, src[0]);
1567 src[1] = to_float(&ctx->ac, src[1]);
1568 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1569 break;
1570 case nir_op_fsub:
1571 src[0] = to_float(&ctx->ac, src[0]);
1572 src[1] = to_float(&ctx->ac, src[1]);
1573 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1574 break;
1575 case nir_op_isub:
1576 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1577 break;
1578 case nir_op_imul:
1579 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1580 break;
1581 case nir_op_imod:
1582 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1583 break;
1584 case nir_op_umod:
1585 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1586 break;
1587 case nir_op_fmod:
1588 src[0] = to_float(&ctx->ac, src[0]);
1589 src[1] = to_float(&ctx->ac, src[1]);
1590 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1591 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1592 to_float_type(&ctx->ac, def_type), result);
1593 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1594 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1595 break;
1596 case nir_op_frem:
1597 src[0] = to_float(&ctx->ac, src[0]);
1598 src[1] = to_float(&ctx->ac, src[1]);
1599 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1600 break;
1601 case nir_op_irem:
1602 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1603 break;
1604 case nir_op_idiv:
1605 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1606 break;
1607 case nir_op_udiv:
1608 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1609 break;
1610 case nir_op_fmul:
1611 src[0] = to_float(&ctx->ac, src[0]);
1612 src[1] = to_float(&ctx->ac, src[1]);
1613 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1614 break;
1615 case nir_op_fdiv:
1616 src[0] = to_float(&ctx->ac, src[0]);
1617 src[1] = to_float(&ctx->ac, src[1]);
1618 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1619 break;
1620 case nir_op_frcp:
1621 src[0] = to_float(&ctx->ac, src[0]);
1622 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1623 break;
1624 case nir_op_iand:
1625 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1626 break;
1627 case nir_op_ior:
1628 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1629 break;
1630 case nir_op_ixor:
1631 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1632 break;
1633 case nir_op_ishl:
1634 result = LLVMBuildShl(ctx->ac.builder, src[0],
1635 LLVMBuildZExt(ctx->ac.builder, src[1],
1636 LLVMTypeOf(src[0]), ""),
1637 "");
1638 break;
1639 case nir_op_ishr:
1640 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1641 LLVMBuildZExt(ctx->ac.builder, src[1],
1642 LLVMTypeOf(src[0]), ""),
1643 "");
1644 break;
1645 case nir_op_ushr:
1646 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1647 LLVMBuildZExt(ctx->ac.builder, src[1],
1648 LLVMTypeOf(src[0]), ""),
1649 "");
1650 break;
1651 case nir_op_ilt:
1652 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1653 break;
1654 case nir_op_ine:
1655 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1656 break;
1657 case nir_op_ieq:
1658 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1659 break;
1660 case nir_op_ige:
1661 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1662 break;
1663 case nir_op_ult:
1664 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1665 break;
1666 case nir_op_uge:
1667 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1668 break;
1669 case nir_op_feq:
1670 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1671 break;
1672 case nir_op_fne:
1673 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1674 break;
1675 case nir_op_flt:
1676 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1677 break;
1678 case nir_op_fge:
1679 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1680 break;
1681 case nir_op_fabs:
1682 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1683 to_float_type(&ctx->ac, def_type), src[0]);
1684 break;
1685 case nir_op_iabs:
1686 result = emit_iabs(&ctx->ac, src[0]);
1687 break;
1688 case nir_op_imax:
1689 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1690 break;
1691 case nir_op_imin:
1692 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1693 break;
1694 case nir_op_umax:
1695 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1696 break;
1697 case nir_op_umin:
1698 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1699 break;
1700 case nir_op_isign:
1701 result = emit_isign(&ctx->ac, src[0]);
1702 break;
1703 case nir_op_fsign:
1704 src[0] = to_float(&ctx->ac, src[0]);
1705 result = emit_fsign(&ctx->ac, src[0]);
1706 break;
1707 case nir_op_ffloor:
1708 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1709 to_float_type(&ctx->ac, def_type), src[0]);
1710 break;
1711 case nir_op_ftrunc:
1712 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1713 to_float_type(&ctx->ac, def_type), src[0]);
1714 break;
1715 case nir_op_fceil:
1716 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1717 to_float_type(&ctx->ac, def_type), src[0]);
1718 break;
1719 case nir_op_fround_even:
1720 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1721 to_float_type(&ctx->ac, def_type),src[0]);
1722 break;
1723 case nir_op_ffract:
1724 result = emit_ffract(&ctx->ac, src[0]);
1725 break;
1726 case nir_op_fsin:
1727 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1728 to_float_type(&ctx->ac, def_type), src[0]);
1729 break;
1730 case nir_op_fcos:
1731 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1732 to_float_type(&ctx->ac, def_type), src[0]);
1733 break;
1734 case nir_op_fsqrt:
1735 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1736 to_float_type(&ctx->ac, def_type), src[0]);
1737 break;
1738 case nir_op_fexp2:
1739 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1740 to_float_type(&ctx->ac, def_type), src[0]);
1741 break;
1742 case nir_op_flog2:
1743 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1744 to_float_type(&ctx->ac, def_type), src[0]);
1745 break;
1746 case nir_op_frsq:
1747 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1748 to_float_type(&ctx->ac, def_type), src[0]);
1749 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1750 break;
1751 case nir_op_fpow:
1752 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1753 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1754 break;
1755 case nir_op_fmax:
1756 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1757 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1758 if (instr->dest.dest.ssa.bit_size == 32)
1759 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1760 to_float_type(&ctx->ac, def_type),
1761 result);
1762 break;
1763 case nir_op_fmin:
1764 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1765 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1766 if (instr->dest.dest.ssa.bit_size == 32)
1767 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1768 to_float_type(&ctx->ac, def_type),
1769 result);
1770 break;
1771 case nir_op_ffma:
1772 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1773 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1774 break;
1775 case nir_op_ibitfield_extract:
1776 result = emit_bitfield_extract(&ctx->ac, true, src);
1777 break;
1778 case nir_op_ubitfield_extract:
1779 result = emit_bitfield_extract(&ctx->ac, false, src);
1780 break;
1781 case nir_op_bitfield_insert:
1782 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1783 break;
1784 case nir_op_bitfield_reverse:
1785 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1786 break;
1787 case nir_op_bit_count:
1788 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1789 break;
1790 case nir_op_vec2:
1791 case nir_op_vec3:
1792 case nir_op_vec4:
1793 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1794 src[i] = to_integer(&ctx->ac, src[i]);
1795 result = ac_build_gather_values(&ctx->ac, src, num_components);
1796 break;
1797 case nir_op_f2i32:
1798 case nir_op_f2i64:
1799 src[0] = to_float(&ctx->ac, src[0]);
1800 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1801 break;
1802 case nir_op_f2u32:
1803 case nir_op_f2u64:
1804 src[0] = to_float(&ctx->ac, src[0]);
1805 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1806 break;
1807 case nir_op_i2f32:
1808 case nir_op_i2f64:
1809 src[0] = to_integer(&ctx->ac, src[0]);
1810 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1811 break;
1812 case nir_op_u2f32:
1813 case nir_op_u2f64:
1814 src[0] = to_integer(&ctx->ac, src[0]);
1815 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1816 break;
1817 case nir_op_f2f64:
1818 result = LLVMBuildFPExt(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1819 break;
1820 case nir_op_f2f32:
1821 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1822 break;
1823 case nir_op_u2u32:
1824 case nir_op_u2u64:
1825 src[0] = to_integer(&ctx->ac, src[0]);
1826 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1827 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1828 else
1829 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1830 break;
1831 case nir_op_i2i32:
1832 case nir_op_i2i64:
1833 src[0] = to_integer(&ctx->ac, src[0]);
1834 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1835 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1836 else
1837 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1838 break;
1839 case nir_op_bcsel:
1840 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1841 break;
1842 case nir_op_find_lsb:
1843 src[0] = to_integer(&ctx->ac, src[0]);
1844 result = emit_find_lsb(&ctx->ac, src[0]);
1845 break;
1846 case nir_op_ufind_msb:
1847 src[0] = to_integer(&ctx->ac, src[0]);
1848 result = emit_ufind_msb(&ctx->ac, src[0]);
1849 break;
1850 case nir_op_ifind_msb:
1851 src[0] = to_integer(&ctx->ac, src[0]);
1852 result = emit_ifind_msb(&ctx->ac, src[0]);
1853 break;
1854 case nir_op_uadd_carry:
1855 src[0] = to_integer(&ctx->ac, src[0]);
1856 src[1] = to_integer(&ctx->ac, src[1]);
1857 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1858 break;
1859 case nir_op_usub_borrow:
1860 src[0] = to_integer(&ctx->ac, src[0]);
1861 src[1] = to_integer(&ctx->ac, src[1]);
1862 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1863 break;
1864 case nir_op_b2f:
1865 result = emit_b2f(&ctx->ac, src[0]);
1866 break;
1867 case nir_op_f2b:
1868 result = emit_f2b(&ctx->ac, src[0]);
1869 break;
1870 case nir_op_b2i:
1871 result = emit_b2i(&ctx->ac, src[0]);
1872 break;
1873 case nir_op_i2b:
1874 src[0] = to_integer(&ctx->ac, src[0]);
1875 result = emit_i2b(&ctx->ac, src[0]);
1876 break;
1877 case nir_op_fquantize2f16:
1878 result = emit_f2f16(ctx->nctx, src[0]);
1879 break;
1880 case nir_op_umul_high:
1881 src[0] = to_integer(&ctx->ac, src[0]);
1882 src[1] = to_integer(&ctx->ac, src[1]);
1883 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1884 break;
1885 case nir_op_imul_high:
1886 src[0] = to_integer(&ctx->ac, src[0]);
1887 src[1] = to_integer(&ctx->ac, src[1]);
1888 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1889 break;
1890 case nir_op_pack_half_2x16:
1891 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1892 break;
1893 case nir_op_unpack_half_2x16:
1894 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1895 break;
1896 case nir_op_fddx:
1897 case nir_op_fddy:
1898 case nir_op_fddx_fine:
1899 case nir_op_fddy_fine:
1900 case nir_op_fddx_coarse:
1901 case nir_op_fddy_coarse:
1902 result = emit_ddxy(ctx, instr->op, src[0]);
1903 break;
1904
1905 case nir_op_unpack_64_2x32_split_x: {
1906 assert(instr->src[0].src.ssa->num_components == 1);
1907 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1908 LLVMVectorType(ctx->ac.i32, 2),
1909 "");
1910 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1911 ctx->ac.i32_0, "");
1912 break;
1913 }
1914
1915 case nir_op_unpack_64_2x32_split_y: {
1916 assert(instr->src[0].src.ssa->num_components == 1);
1917 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1918 LLVMVectorType(ctx->ac.i32, 2),
1919 "");
1920 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1921 ctx->ac.i32_1, "");
1922 break;
1923 }
1924
1925 case nir_op_pack_64_2x32_split: {
1926 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1927 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1928 src[0], ctx->ac.i32_0, "");
1929 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1930 src[1], ctx->ac.i32_1, "");
1931 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1932 break;
1933 }
1934
1935 default:
1936 fprintf(stderr, "Unknown NIR alu instr: ");
1937 nir_print_instr(&instr->instr, stderr);
1938 fprintf(stderr, "\n");
1939 abort();
1940 }
1941
1942 if (result) {
1943 assert(instr->dest.dest.is_ssa);
1944 result = to_integer(&ctx->ac, result);
1945 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1946 result);
1947 }
1948 }
1949
1950 static void visit_load_const(struct ac_nir_context *ctx,
1951 const nir_load_const_instr *instr)
1952 {
1953 LLVMValueRef values[4], value = NULL;
1954 LLVMTypeRef element_type =
1955 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1956
1957 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1958 switch (instr->def.bit_size) {
1959 case 32:
1960 values[i] = LLVMConstInt(element_type,
1961 instr->value.u32[i], false);
1962 break;
1963 case 64:
1964 values[i] = LLVMConstInt(element_type,
1965 instr->value.u64[i], false);
1966 break;
1967 default:
1968 fprintf(stderr,
1969 "unsupported nir load_const bit_size: %d\n",
1970 instr->def.bit_size);
1971 abort();
1972 }
1973 }
1974 if (instr->def.num_components > 1) {
1975 value = LLVMConstVector(values, instr->def.num_components);
1976 } else
1977 value = values[0];
1978
1979 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1980 }
1981
1982 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1983 LLVMTypeRef type)
1984 {
1985 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1986 return LLVMBuildBitCast(ctx->builder, ptr,
1987 LLVMPointerType(type, addr_space), "");
1988 }
1989
1990 static LLVMValueRef
1991 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1992 {
1993 LLVMValueRef size =
1994 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1995 LLVMConstInt(ctx->ac.i32, 2, false), "");
1996
1997 /* VI only */
1998 if (ctx->abi->chip_class >= VI && in_elements) {
1999 /* On VI, the descriptor contains the size in bytes,
2000 * but TXQ must return the size in elements.
2001 * The stride is always non-zero for resources using TXQ.
2002 */
2003 LLVMValueRef stride =
2004 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2005 LLVMConstInt(ctx->ac.i32, 1, false), "");
2006 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2007 LLVMConstInt(ctx->ac.i32, 16, false), "");
2008 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2009 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2010
2011 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2012 }
2013 return size;
2014 }
2015
2016 /**
2017 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2018 * intrinsic names).
2019 */
2020 static void build_int_type_name(
2021 LLVMTypeRef type,
2022 char *buf, unsigned bufsize)
2023 {
2024 assert(bufsize >= 6);
2025
2026 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2027 snprintf(buf, bufsize, "v%ui32",
2028 LLVMGetVectorSize(type));
2029 else
2030 strcpy(buf, "i32");
2031 }
2032
2033 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2034 struct ac_image_args *args,
2035 const nir_tex_instr *instr)
2036 {
2037 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2038 LLVMValueRef coord = args->addr;
2039 LLVMValueRef half_texel[2];
2040 LLVMValueRef compare_cube_wa;
2041 LLVMValueRef result;
2042 int c;
2043 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2044
2045 //TODO Rect
2046 {
2047 struct ac_image_args txq_args = { 0 };
2048
2049 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2050 txq_args.opcode = ac_image_get_resinfo;
2051 txq_args.dmask = 0xf;
2052 txq_args.addr = ctx->i32_0;
2053 txq_args.resource = args->resource;
2054 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2055
2056 for (c = 0; c < 2; c++) {
2057 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2058 LLVMConstInt(ctx->i32, c, false), "");
2059 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2060 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2061 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2062 LLVMConstReal(ctx->f32, -0.5), "");
2063 }
2064 }
2065
2066 LLVMValueRef orig_coords = args->addr;
2067
2068 for (c = 0; c < 2; c++) {
2069 LLVMValueRef tmp;
2070 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2071 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2072 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2073 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2074 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2075 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2076 }
2077
2078
2079 /*
2080 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2081 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2082 * workaround by sampling using a scaled type and converting.
2083 * This is taken from amdgpu-pro shaders.
2084 */
2085 /* NOTE this produces some ugly code compared to amdgpu-pro,
2086 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2087 * and then reads them back. -pro generates two selects,
2088 * one s_cmp for the descriptor rewriting
2089 * one v_cmp for the coordinate and result changes.
2090 */
2091 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2092 LLVMValueRef tmp, tmp2;
2093
2094 /* workaround 8/8/8/8 uint/sint cube gather bug */
2095 /* first detect it then change to a scaled read and f2i */
2096 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2097 tmp2 = tmp;
2098
2099 /* extract the DATA_FORMAT */
2100 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2101 LLVMConstInt(ctx->i32, 6, false), false);
2102
2103 /* is the DATA_FORMAT == 8_8_8_8 */
2104 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2105
2106 if (stype == GLSL_TYPE_UINT)
2107 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2108 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2109 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2110 else
2111 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2112 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2113 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2114
2115 /* replace the NUM FORMAT in the descriptor */
2116 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2117 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2118
2119 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2120
2121 /* don't modify the coordinates for this case */
2122 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2123 }
2124 args->addr = coord;
2125 result = ac_build_image_opcode(ctx, args);
2126
2127 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2128 LLVMValueRef tmp, tmp2;
2129
2130 /* if the cube workaround is in place, f2i the result. */
2131 for (c = 0; c < 4; c++) {
2132 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2133 if (stype == GLSL_TYPE_UINT)
2134 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2135 else
2136 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2137 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2138 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2139 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2140 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2141 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2142 }
2143 }
2144 return result;
2145 }
2146
2147 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2148 const nir_tex_instr *instr,
2149 bool lod_is_zero,
2150 struct ac_image_args *args)
2151 {
2152 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2153 return ac_build_buffer_load_format(&ctx->ac,
2154 args->resource,
2155 args->addr,
2156 LLVMConstInt(ctx->ac.i32, 0, false),
2157 true);
2158 }
2159
2160 args->opcode = ac_image_sample;
2161 args->compare = instr->is_shadow;
2162
2163 switch (instr->op) {
2164 case nir_texop_txf:
2165 case nir_texop_txf_ms:
2166 case nir_texop_samples_identical:
2167 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2168 args->compare = false;
2169 args->offset = false;
2170 break;
2171 case nir_texop_txb:
2172 args->bias = true;
2173 break;
2174 case nir_texop_txl:
2175 if (lod_is_zero)
2176 args->level_zero = true;
2177 else
2178 args->lod = true;
2179 break;
2180 case nir_texop_txs:
2181 case nir_texop_query_levels:
2182 args->opcode = ac_image_get_resinfo;
2183 break;
2184 case nir_texop_tex:
2185 if (ctx->stage != MESA_SHADER_FRAGMENT)
2186 args->level_zero = true;
2187 break;
2188 case nir_texop_txd:
2189 args->deriv = true;
2190 break;
2191 case nir_texop_tg4:
2192 args->opcode = ac_image_gather4;
2193 args->level_zero = true;
2194 break;
2195 case nir_texop_lod:
2196 args->opcode = ac_image_get_lod;
2197 args->compare = false;
2198 args->offset = false;
2199 break;
2200 default:
2201 break;
2202 }
2203
2204 if (instr->op == nir_texop_tg4 && ctx->abi->chip_class <= VI) {
2205 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2206 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2207 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2208 }
2209 }
2210 return ac_build_image_opcode(&ctx->ac, args);
2211 }
2212
2213 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2214 nir_intrinsic_instr *instr)
2215 {
2216 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2217 unsigned desc_set = nir_intrinsic_desc_set(instr);
2218 unsigned binding = nir_intrinsic_binding(instr);
2219 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2220 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2221 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2222 unsigned base_offset = layout->binding[binding].offset;
2223 LLVMValueRef offset, stride;
2224
2225 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2226 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2227 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2228 layout->binding[binding].dynamic_offset_offset;
2229 desc_ptr = ctx->push_constants;
2230 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2231 stride = LLVMConstInt(ctx->i32, 16, false);
2232 } else
2233 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2234
2235 offset = LLVMConstInt(ctx->i32, base_offset, false);
2236 index = LLVMBuildMul(ctx->builder, index, stride, "");
2237 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2238
2239 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2240 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2241 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2242
2243 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2244 }
2245
2246 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2247 nir_intrinsic_instr *instr)
2248 {
2249 LLVMValueRef ptr, addr;
2250
2251 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2252 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2253
2254 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2255 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2256
2257 return LLVMBuildLoad(ctx->builder, ptr, "");
2258 }
2259
2260 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2261 const nir_intrinsic_instr *instr)
2262 {
2263 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2264
2265 return get_buffer_size(ctx, desc, false);
2266 }
2267 static void visit_store_ssbo(struct ac_nir_context *ctx,
2268 nir_intrinsic_instr *instr)
2269 {
2270 const char *store_name;
2271 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2272 LLVMTypeRef data_type = ctx->ac.f32;
2273 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2274 int components_32bit = elem_size_mult * instr->num_components;
2275 unsigned writemask = nir_intrinsic_write_mask(instr);
2276 LLVMValueRef base_data, base_offset;
2277 LLVMValueRef params[6];
2278 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2279
2280 params[1] = ctx->abi->load_ssbo(ctx->abi,
2281 get_src(ctx, instr->src[1]), true);
2282 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2283 params[4] = i1false; /* glc */
2284 params[5] = i1false; /* slc */
2285
2286 if (components_32bit > 1)
2287 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2288
2289 base_data = to_float(&ctx->ac, src_data);
2290 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2291 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2292 data_type, "");
2293 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2294 while (writemask) {
2295 int start, count;
2296 LLVMValueRef data;
2297 LLVMValueRef offset;
2298 LLVMValueRef tmp;
2299 u_bit_scan_consecutive_range(&writemask, &start, &count);
2300
2301 /* Due to an LLVM limitation, split 3-element writes
2302 * into a 2-element and a 1-element write. */
2303 if (count == 3) {
2304 writemask |= 1 << (start + 2);
2305 count = 2;
2306 }
2307
2308 start *= elem_size_mult;
2309 count *= elem_size_mult;
2310
2311 if (count > 4) {
2312 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2313 count = 4;
2314 }
2315
2316 if (count == 4) {
2317 store_name = "llvm.amdgcn.buffer.store.v4f32";
2318 data = base_data;
2319 } else if (count == 2) {
2320 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2321
2322 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2323 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2324 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2325 ctx->ac.i32_0, "");
2326
2327 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2328 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2329 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2330 ctx->ac.i32_1, "");
2331 store_name = "llvm.amdgcn.buffer.store.v2f32";
2332
2333 } else {
2334 assert(count == 1);
2335 if (get_llvm_num_components(base_data) > 1)
2336 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2337 LLVMConstInt(ctx->ac.i32, start, false), "");
2338 else
2339 data = base_data;
2340 store_name = "llvm.amdgcn.buffer.store.f32";
2341 }
2342
2343 offset = base_offset;
2344 if (start != 0) {
2345 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2346 }
2347 params[0] = data;
2348 params[3] = offset;
2349 ac_build_intrinsic(&ctx->ac, store_name,
2350 ctx->ac.voidt, params, 6, 0);
2351 }
2352 }
2353
2354 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2355 const nir_intrinsic_instr *instr)
2356 {
2357 const char *name;
2358 LLVMValueRef params[6];
2359 int arg_count = 0;
2360
2361 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2362 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2363 }
2364 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2365 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2366 get_src(ctx, instr->src[0]),
2367 true);
2368 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2369 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2370 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2371
2372 switch (instr->intrinsic) {
2373 case nir_intrinsic_ssbo_atomic_add:
2374 name = "llvm.amdgcn.buffer.atomic.add";
2375 break;
2376 case nir_intrinsic_ssbo_atomic_imin:
2377 name = "llvm.amdgcn.buffer.atomic.smin";
2378 break;
2379 case nir_intrinsic_ssbo_atomic_umin:
2380 name = "llvm.amdgcn.buffer.atomic.umin";
2381 break;
2382 case nir_intrinsic_ssbo_atomic_imax:
2383 name = "llvm.amdgcn.buffer.atomic.smax";
2384 break;
2385 case nir_intrinsic_ssbo_atomic_umax:
2386 name = "llvm.amdgcn.buffer.atomic.umax";
2387 break;
2388 case nir_intrinsic_ssbo_atomic_and:
2389 name = "llvm.amdgcn.buffer.atomic.and";
2390 break;
2391 case nir_intrinsic_ssbo_atomic_or:
2392 name = "llvm.amdgcn.buffer.atomic.or";
2393 break;
2394 case nir_intrinsic_ssbo_atomic_xor:
2395 name = "llvm.amdgcn.buffer.atomic.xor";
2396 break;
2397 case nir_intrinsic_ssbo_atomic_exchange:
2398 name = "llvm.amdgcn.buffer.atomic.swap";
2399 break;
2400 case nir_intrinsic_ssbo_atomic_comp_swap:
2401 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2402 break;
2403 default:
2404 abort();
2405 }
2406
2407 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2408 }
2409
2410 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2411 const nir_intrinsic_instr *instr)
2412 {
2413 LLVMValueRef results[2];
2414 int load_components;
2415 int num_components = instr->num_components;
2416 if (instr->dest.ssa.bit_size == 64)
2417 num_components *= 2;
2418
2419 for (int i = 0; i < num_components; i += load_components) {
2420 load_components = MIN2(num_components - i, 4);
2421 const char *load_name;
2422 LLVMTypeRef data_type = ctx->ac.f32;
2423 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2424 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2425
2426 if (load_components == 3)
2427 data_type = LLVMVectorType(ctx->ac.f32, 4);
2428 else if (load_components > 1)
2429 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2430
2431 if (load_components >= 3)
2432 load_name = "llvm.amdgcn.buffer.load.v4f32";
2433 else if (load_components == 2)
2434 load_name = "llvm.amdgcn.buffer.load.v2f32";
2435 else if (load_components == 1)
2436 load_name = "llvm.amdgcn.buffer.load.f32";
2437 else
2438 unreachable("unhandled number of components");
2439
2440 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2441 LLVMValueRef params[] = {
2442 ctx->abi->load_ssbo(ctx->abi,
2443 get_src(ctx, instr->src[0]),
2444 false),
2445 LLVMConstInt(ctx->ac.i32, 0, false),
2446 offset,
2447 i1false,
2448 i1false,
2449 };
2450
2451 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2452
2453 }
2454
2455 LLVMValueRef ret = results[0];
2456 if (num_components > 4 || num_components == 3) {
2457 LLVMValueRef masks[] = {
2458 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2459 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2460 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2461 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2462 };
2463
2464 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2465 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2466 results[num_components > 4 ? 1 : 0], swizzle, "");
2467 }
2468
2469 return LLVMBuildBitCast(ctx->ac.builder, ret,
2470 get_def_type(ctx, &instr->dest.ssa), "");
2471 }
2472
2473 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2474 const nir_intrinsic_instr *instr)
2475 {
2476 LLVMValueRef results[8], ret;
2477 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2478 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2479 int num_components = instr->num_components;
2480
2481 if (ctx->abi->load_ubo)
2482 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2483
2484 if (instr->dest.ssa.bit_size == 64)
2485 num_components *= 2;
2486
2487 for (unsigned i = 0; i < num_components; ++i) {
2488 LLVMValueRef params[] = {
2489 rsrc,
2490 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2491 offset, "")
2492 };
2493 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2494 params, 2,
2495 AC_FUNC_ATTR_READNONE |
2496 AC_FUNC_ATTR_LEGACY);
2497 }
2498
2499
2500 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2501 return LLVMBuildBitCast(ctx->ac.builder, ret,
2502 get_def_type(ctx, &instr->dest.ssa), "");
2503 }
2504
2505 static void
2506 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2507 bool vs_in, unsigned *vertex_index_out,
2508 LLVMValueRef *vertex_index_ref,
2509 unsigned *const_out, LLVMValueRef *indir_out)
2510 {
2511 unsigned const_offset = 0;
2512 nir_deref *tail = &deref->deref;
2513 LLVMValueRef offset = NULL;
2514
2515 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2516 tail = tail->child;
2517 nir_deref_array *deref_array = nir_deref_as_array(tail);
2518 if (vertex_index_out)
2519 *vertex_index_out = deref_array->base_offset;
2520
2521 if (vertex_index_ref) {
2522 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2523 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2524 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2525 }
2526 *vertex_index_ref = vtx;
2527 }
2528 }
2529
2530 if (deref->var->data.compact) {
2531 assert(tail->child->deref_type == nir_deref_type_array);
2532 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2533 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2534 /* We always lower indirect dereferences for "compact" array vars. */
2535 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2536
2537 const_offset = deref_array->base_offset;
2538 goto out;
2539 }
2540
2541 while (tail->child != NULL) {
2542 const struct glsl_type *parent_type = tail->type;
2543 tail = tail->child;
2544
2545 if (tail->deref_type == nir_deref_type_array) {
2546 nir_deref_array *deref_array = nir_deref_as_array(tail);
2547 LLVMValueRef index, stride, local_offset;
2548 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2549
2550 const_offset += size * deref_array->base_offset;
2551 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2552 continue;
2553
2554 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2555 index = get_src(ctx, deref_array->indirect);
2556 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2557 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2558
2559 if (offset)
2560 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2561 else
2562 offset = local_offset;
2563 } else if (tail->deref_type == nir_deref_type_struct) {
2564 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2565
2566 for (unsigned i = 0; i < deref_struct->index; i++) {
2567 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2568 const_offset += glsl_count_attribute_slots(ft, vs_in);
2569 }
2570 } else
2571 unreachable("unsupported deref type");
2572
2573 }
2574 out:
2575 if (const_offset && offset)
2576 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2577 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2578 "");
2579
2580 *const_out = const_offset;
2581 *indir_out = offset;
2582 }
2583
2584 static LLVMValueRef
2585 lds_load(struct nir_to_llvm_context *ctx,
2586 LLVMValueRef dw_addr)
2587 {
2588 LLVMValueRef value;
2589 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2590 return value;
2591 }
2592
2593 static void
2594 lds_store(struct nir_to_llvm_context *ctx,
2595 LLVMValueRef dw_addr, LLVMValueRef value)
2596 {
2597 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2598 ac_build_indexed_store(&ctx->ac, ctx->lds,
2599 dw_addr, value);
2600 }
2601
2602 /* The offchip buffer layout for TCS->TES is
2603 *
2604 * - attribute 0 of patch 0 vertex 0
2605 * - attribute 0 of patch 0 vertex 1
2606 * - attribute 0 of patch 0 vertex 2
2607 * ...
2608 * - attribute 0 of patch 1 vertex 0
2609 * - attribute 0 of patch 1 vertex 1
2610 * ...
2611 * - attribute 1 of patch 0 vertex 0
2612 * - attribute 1 of patch 0 vertex 1
2613 * ...
2614 * - per patch attribute 0 of patch 0
2615 * - per patch attribute 0 of patch 1
2616 * ...
2617 *
2618 * Note that every attribute has 4 components.
2619 */
2620 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2621 LLVMValueRef vertex_index,
2622 LLVMValueRef param_index)
2623 {
2624 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2625 LLVMValueRef param_stride, constant16;
2626 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2627
2628 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2629 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2630 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2631 num_patches, "");
2632
2633 constant16 = LLVMConstInt(ctx->i32, 16, false);
2634 if (vertex_index) {
2635 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2636 vertices_per_patch, "");
2637
2638 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2639 vertex_index, "");
2640
2641 param_stride = total_vertices;
2642 } else {
2643 base_addr = rel_patch_id;
2644 param_stride = num_patches;
2645 }
2646
2647 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2648 LLVMBuildMul(ctx->builder, param_index,
2649 param_stride, ""), "");
2650
2651 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2652
2653 if (!vertex_index) {
2654 LLVMValueRef patch_data_offset =
2655 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2656
2657 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2658 patch_data_offset, "");
2659 }
2660 return base_addr;
2661 }
2662
2663 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2664 unsigned param,
2665 unsigned const_index,
2666 bool is_compact,
2667 LLVMValueRef vertex_index,
2668 LLVMValueRef indir_index)
2669 {
2670 LLVMValueRef param_index;
2671
2672 if (indir_index)
2673 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2674 indir_index, "");
2675 else {
2676 if (const_index && !is_compact)
2677 param += const_index;
2678 param_index = LLVMConstInt(ctx->i32, param, false);
2679 }
2680 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2681 }
2682
2683 static void
2684 mark_tess_output(struct nir_to_llvm_context *ctx,
2685 bool is_patch, uint32_t param)
2686
2687 {
2688 if (is_patch) {
2689 ctx->tess_patch_outputs_written |= (1ull << param);
2690 } else
2691 ctx->tess_outputs_written |= (1ull << param);
2692 }
2693
2694 static LLVMValueRef
2695 get_dw_address(struct nir_to_llvm_context *ctx,
2696 LLVMValueRef dw_addr,
2697 unsigned param,
2698 unsigned const_index,
2699 bool compact_const_index,
2700 LLVMValueRef vertex_index,
2701 LLVMValueRef stride,
2702 LLVMValueRef indir_index)
2703
2704 {
2705
2706 if (vertex_index) {
2707 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2708 LLVMBuildMul(ctx->builder,
2709 vertex_index,
2710 stride, ""), "");
2711 }
2712
2713 if (indir_index)
2714 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2715 LLVMBuildMul(ctx->builder, indir_index,
2716 LLVMConstInt(ctx->i32, 4, false), ""), "");
2717 else if (const_index && !compact_const_index)
2718 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2719 LLVMConstInt(ctx->i32, const_index, false), "");
2720
2721 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2722 LLVMConstInt(ctx->i32, param * 4, false), "");
2723
2724 if (const_index && compact_const_index)
2725 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2726 LLVMConstInt(ctx->i32, const_index, false), "");
2727 return dw_addr;
2728 }
2729
2730 static LLVMValueRef
2731 load_tcs_input(struct nir_to_llvm_context *ctx,
2732 nir_intrinsic_instr *instr)
2733 {
2734 LLVMValueRef dw_addr, stride;
2735 unsigned const_index;
2736 LLVMValueRef vertex_index;
2737 LLVMValueRef indir_index;
2738 unsigned param;
2739 LLVMValueRef value[4], result;
2740 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2741 const bool is_compact = instr->variables[0]->var->data.compact;
2742 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2743 get_deref_offset(ctx->nir, instr->variables[0],
2744 false, NULL, per_vertex ? &vertex_index : NULL,
2745 &const_index, &indir_index);
2746
2747 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2748 dw_addr = get_tcs_in_current_patch_offset(ctx);
2749 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2750 indir_index);
2751
2752 for (unsigned i = 0; i < instr->num_components; i++) {
2753 value[i] = lds_load(ctx, dw_addr);
2754 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2755 ctx->i32one, "");
2756 }
2757 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2758 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2759 return result;
2760 }
2761
2762 static LLVMValueRef
2763 load_tcs_output(struct nir_to_llvm_context *ctx,
2764 nir_intrinsic_instr *instr)
2765 {
2766 LLVMValueRef dw_addr, stride;
2767 LLVMValueRef value[4], result;
2768 LLVMValueRef vertex_index = NULL;
2769 LLVMValueRef indir_index = NULL;
2770 unsigned const_index = 0;
2771 unsigned param;
2772 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2773 const bool is_compact = instr->variables[0]->var->data.compact;
2774 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2775 get_deref_offset(ctx->nir, instr->variables[0],
2776 false, NULL, per_vertex ? &vertex_index : NULL,
2777 &const_index, &indir_index);
2778
2779 if (!instr->variables[0]->var->data.patch) {
2780 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2781 dw_addr = get_tcs_out_current_patch_offset(ctx);
2782 } else {
2783 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2784 }
2785
2786 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2787 indir_index);
2788
2789 for (unsigned i = 0; i < instr->num_components; i++) {
2790 value[i] = lds_load(ctx, dw_addr);
2791 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2792 ctx->i32one, "");
2793 }
2794 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2795 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2796 return result;
2797 }
2798
2799 static void
2800 store_tcs_output(struct nir_to_llvm_context *ctx,
2801 nir_intrinsic_instr *instr,
2802 LLVMValueRef src,
2803 unsigned writemask)
2804 {
2805 LLVMValueRef stride, dw_addr;
2806 LLVMValueRef buf_addr = NULL;
2807 LLVMValueRef vertex_index = NULL;
2808 LLVMValueRef indir_index = NULL;
2809 unsigned const_index = 0;
2810 unsigned param;
2811 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2812 const bool is_compact = instr->variables[0]->var->data.compact;
2813
2814 get_deref_offset(ctx->nir, instr->variables[0],
2815 false, NULL, per_vertex ? &vertex_index : NULL,
2816 &const_index, &indir_index);
2817
2818 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2819 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2820 is_compact && const_index > 3) {
2821 const_index -= 3;
2822 param++;
2823 }
2824
2825 if (!instr->variables[0]->var->data.patch) {
2826 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2827 dw_addr = get_tcs_out_current_patch_offset(ctx);
2828 } else {
2829 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2830 }
2831
2832 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2833
2834 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2835 indir_index);
2836 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2837 vertex_index, indir_index);
2838
2839 unsigned base = is_compact ? const_index : 0;
2840 for (unsigned chan = 0; chan < 8; chan++) {
2841 bool is_tess_factor = false;
2842 if (!(writemask & (1 << chan)))
2843 continue;
2844 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2845
2846 lds_store(ctx, dw_addr, value);
2847
2848 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2849 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2850 is_tess_factor = true;
2851
2852 if (!is_tess_factor && writemask != 0xF)
2853 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2854 buf_addr, ctx->oc_lds,
2855 4 * (base + chan), 1, 0, true, false);
2856
2857 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2858 ctx->i32one, "");
2859 }
2860
2861 if (writemask == 0xF) {
2862 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2863 buf_addr, ctx->oc_lds,
2864 (base * 4), 1, 0, true, false);
2865 }
2866 }
2867
2868 static LLVMValueRef
2869 load_tes_input(struct nir_to_llvm_context *ctx,
2870 const nir_intrinsic_instr *instr)
2871 {
2872 LLVMValueRef buf_addr;
2873 LLVMValueRef result;
2874 LLVMValueRef vertex_index = NULL;
2875 LLVMValueRef indir_index = NULL;
2876 unsigned const_index = 0;
2877 unsigned param;
2878 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2879 const bool is_compact = instr->variables[0]->var->data.compact;
2880
2881 get_deref_offset(ctx->nir, instr->variables[0],
2882 false, NULL, per_vertex ? &vertex_index : NULL,
2883 &const_index, &indir_index);
2884 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2885 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2886 is_compact && const_index > 3) {
2887 const_index -= 3;
2888 param++;
2889 }
2890 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2891 is_compact, vertex_index, indir_index);
2892
2893 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2894 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2895 result = trim_vector(&ctx->ac, result, instr->num_components);
2896 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2897 return result;
2898 }
2899
2900 static LLVMValueRef
2901 load_gs_input(struct nir_to_llvm_context *ctx,
2902 nir_intrinsic_instr *instr)
2903 {
2904 LLVMValueRef indir_index, vtx_offset;
2905 unsigned const_index;
2906 LLVMValueRef args[9];
2907 unsigned param, vtx_offset_param;
2908 LLVMValueRef value[4], result;
2909 unsigned vertex_index;
2910 get_deref_offset(ctx->nir, instr->variables[0],
2911 false, &vertex_index, NULL,
2912 &const_index, &indir_index);
2913 vtx_offset_param = vertex_index;
2914 assert(vtx_offset_param < 6);
2915 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2916 LLVMConstInt(ctx->i32, 4, false), "");
2917
2918 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2919 for (unsigned i = 0; i < instr->num_components; i++) {
2920
2921 args[0] = ctx->esgs_ring;
2922 args[1] = vtx_offset;
2923 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2924 args[3] = ctx->i32zero;
2925 args[4] = ctx->i32one; /* OFFEN */
2926 args[5] = ctx->i32zero; /* IDXEN */
2927 args[6] = ctx->i32one; /* GLC */
2928 args[7] = ctx->i32zero; /* SLC */
2929 args[8] = ctx->i32zero; /* TFE */
2930
2931 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2932 ctx->i32, args, 9,
2933 AC_FUNC_ATTR_READONLY |
2934 AC_FUNC_ATTR_LEGACY);
2935 }
2936 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2937
2938 return result;
2939 }
2940
2941 static LLVMValueRef
2942 build_gep_for_deref(struct ac_nir_context *ctx,
2943 nir_deref_var *deref)
2944 {
2945 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2946 assert(entry->data);
2947 LLVMValueRef val = entry->data;
2948 nir_deref *tail = deref->deref.child;
2949 while (tail != NULL) {
2950 LLVMValueRef offset;
2951 switch (tail->deref_type) {
2952 case nir_deref_type_array: {
2953 nir_deref_array *array = nir_deref_as_array(tail);
2954 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2955 if (array->deref_array_type ==
2956 nir_deref_array_type_indirect) {
2957 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2958 get_src(ctx,
2959 array->indirect),
2960 "");
2961 }
2962 break;
2963 }
2964 case nir_deref_type_struct: {
2965 nir_deref_struct *deref_struct =
2966 nir_deref_as_struct(tail);
2967 offset = LLVMConstInt(ctx->ac.i32,
2968 deref_struct->index, 0);
2969 break;
2970 }
2971 default:
2972 unreachable("bad deref type");
2973 }
2974 val = ac_build_gep0(&ctx->ac, val, offset);
2975 tail = tail->child;
2976 }
2977 return val;
2978 }
2979
2980 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2981 nir_intrinsic_instr *instr)
2982 {
2983 LLVMValueRef values[8];
2984 int idx = instr->variables[0]->var->data.driver_location;
2985 int ve = instr->dest.ssa.num_components;
2986 LLVMValueRef indir_index;
2987 LLVMValueRef ret;
2988 unsigned const_index;
2989 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2990 instr->variables[0]->var->data.mode == nir_var_shader_in;
2991 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2992 &const_index, &indir_index);
2993
2994 if (instr->dest.ssa.bit_size == 64)
2995 ve *= 2;
2996
2997 switch (instr->variables[0]->var->data.mode) {
2998 case nir_var_shader_in:
2999 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3000 return load_tcs_input(ctx->nctx, instr);
3001 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3002 return load_tes_input(ctx->nctx, instr);
3003 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3004 return load_gs_input(ctx->nctx, instr);
3005 }
3006 for (unsigned chan = 0; chan < ve; chan++) {
3007 if (indir_index) {
3008 unsigned count = glsl_count_attribute_slots(
3009 instr->variables[0]->var->type,
3010 ctx->stage == MESA_SHADER_VERTEX);
3011 count -= chan / 4;
3012 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3013 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3014 4, false, true);
3015
3016 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3017 tmp_vec,
3018 indir_index, "");
3019 } else
3020 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3021 }
3022 break;
3023 case nir_var_local:
3024 for (unsigned chan = 0; chan < ve; chan++) {
3025 if (indir_index) {
3026 unsigned count = glsl_count_attribute_slots(
3027 instr->variables[0]->var->type, false);
3028 count -= chan / 4;
3029 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3030 &ctx->ac, ctx->locals + idx + chan, count,
3031 4, true, true);
3032
3033 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3034 tmp_vec,
3035 indir_index, "");
3036 } else {
3037 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3038 }
3039 }
3040 break;
3041 case nir_var_shared: {
3042 LLVMValueRef address = build_gep_for_deref(ctx,
3043 instr->variables[0]);
3044 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3045 return LLVMBuildBitCast(ctx->ac.builder, val,
3046 get_def_type(ctx, &instr->dest.ssa),
3047 "");
3048 }
3049 case nir_var_shader_out:
3050 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3051 return load_tcs_output(ctx->nctx, instr);
3052 for (unsigned chan = 0; chan < ve; chan++) {
3053 if (indir_index) {
3054 unsigned count = glsl_count_attribute_slots(
3055 instr->variables[0]->var->type, false);
3056 count -= chan / 4;
3057 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3058 &ctx->ac, ctx->outputs + idx + chan, count,
3059 4, true, true);
3060
3061 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3062 tmp_vec,
3063 indir_index, "");
3064 } else {
3065 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3066 ctx->outputs[idx + chan + const_index * 4],
3067 "");
3068 }
3069 }
3070 break;
3071 default:
3072 unreachable("unhandle variable mode");
3073 }
3074 ret = ac_build_gather_values(&ctx->ac, values, ve);
3075 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3076 }
3077
3078 static void
3079 visit_store_var(struct ac_nir_context *ctx,
3080 nir_intrinsic_instr *instr)
3081 {
3082 LLVMValueRef temp_ptr, value;
3083 int idx = instr->variables[0]->var->data.driver_location;
3084 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3085 int writemask = instr->const_index[0];
3086 LLVMValueRef indir_index;
3087 unsigned const_index;
3088 get_deref_offset(ctx, instr->variables[0], false,
3089 NULL, NULL, &const_index, &indir_index);
3090
3091 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3092 int old_writemask = writemask;
3093
3094 src = LLVMBuildBitCast(ctx->ac.builder, src,
3095 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3096 "");
3097
3098 writemask = 0;
3099 for (unsigned chan = 0; chan < 4; chan++) {
3100 if (old_writemask & (1 << chan))
3101 writemask |= 3u << (2 * chan);
3102 }
3103 }
3104
3105 switch (instr->variables[0]->var->data.mode) {
3106 case nir_var_shader_out:
3107
3108 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3109 store_tcs_output(ctx->nctx, instr, src, writemask);
3110 return;
3111 }
3112
3113 for (unsigned chan = 0; chan < 8; chan++) {
3114 int stride = 4;
3115 if (!(writemask & (1 << chan)))
3116 continue;
3117
3118 value = llvm_extract_elem(&ctx->ac, src, chan);
3119
3120 if (instr->variables[0]->var->data.compact)
3121 stride = 1;
3122 if (indir_index) {
3123 unsigned count = glsl_count_attribute_slots(
3124 instr->variables[0]->var->type, false);
3125 count -= chan / 4;
3126 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3127 &ctx->ac, ctx->outputs + idx + chan, count,
3128 stride, true, true);
3129
3130 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3131 value, indir_index, "");
3132 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3133 count, stride, tmp_vec);
3134
3135 } else {
3136 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3137
3138 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3139 }
3140 }
3141 break;
3142 case nir_var_local:
3143 for (unsigned chan = 0; chan < 8; chan++) {
3144 if (!(writemask & (1 << chan)))
3145 continue;
3146
3147 value = llvm_extract_elem(&ctx->ac, src, chan);
3148 if (indir_index) {
3149 unsigned count = glsl_count_attribute_slots(
3150 instr->variables[0]->var->type, false);
3151 count -= chan / 4;
3152 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3153 &ctx->ac, ctx->locals + idx + chan, count,
3154 4, true, true);
3155
3156 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3157 value, indir_index, "");
3158 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3159 count, 4, tmp_vec);
3160 } else {
3161 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3162
3163 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3164 }
3165 }
3166 break;
3167 case nir_var_shared: {
3168 int writemask = instr->const_index[0];
3169 LLVMValueRef address = build_gep_for_deref(ctx,
3170 instr->variables[0]);
3171 LLVMValueRef val = get_src(ctx, instr->src[0]);
3172 unsigned components =
3173 glsl_get_vector_elements(
3174 nir_deref_tail(&instr->variables[0]->deref)->type);
3175 if (writemask == (1 << components) - 1) {
3176 val = LLVMBuildBitCast(
3177 ctx->ac.builder, val,
3178 LLVMGetElementType(LLVMTypeOf(address)), "");
3179 LLVMBuildStore(ctx->ac.builder, val, address);
3180 } else {
3181 for (unsigned chan = 0; chan < 4; chan++) {
3182 if (!(writemask & (1 << chan)))
3183 continue;
3184 LLVMValueRef ptr =
3185 LLVMBuildStructGEP(ctx->ac.builder,
3186 address, chan, "");
3187 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3188 chan);
3189 src = LLVMBuildBitCast(
3190 ctx->ac.builder, src,
3191 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3192 LLVMBuildStore(ctx->ac.builder, src, ptr);
3193 }
3194 }
3195 break;
3196 }
3197 default:
3198 break;
3199 }
3200 }
3201
3202 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3203 {
3204 switch (dim) {
3205 case GLSL_SAMPLER_DIM_BUF:
3206 return 1;
3207 case GLSL_SAMPLER_DIM_1D:
3208 return array ? 2 : 1;
3209 case GLSL_SAMPLER_DIM_2D:
3210 return array ? 3 : 2;
3211 case GLSL_SAMPLER_DIM_MS:
3212 return array ? 4 : 3;
3213 case GLSL_SAMPLER_DIM_3D:
3214 case GLSL_SAMPLER_DIM_CUBE:
3215 return 3;
3216 case GLSL_SAMPLER_DIM_RECT:
3217 case GLSL_SAMPLER_DIM_SUBPASS:
3218 return 2;
3219 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3220 return 3;
3221 default:
3222 break;
3223 }
3224 return 0;
3225 }
3226
3227
3228
3229 /* Adjust the sample index according to FMASK.
3230 *
3231 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3232 * which is the identity mapping. Each nibble says which physical sample
3233 * should be fetched to get that sample.
3234 *
3235 * For example, 0x11111100 means there are only 2 samples stored and
3236 * the second sample covers 3/4 of the pixel. When reading samples 0
3237 * and 1, return physical sample 0 (determined by the first two 0s
3238 * in FMASK), otherwise return physical sample 1.
3239 *
3240 * The sample index should be adjusted as follows:
3241 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3242 */
3243 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3244 LLVMValueRef coord_x, LLVMValueRef coord_y,
3245 LLVMValueRef coord_z,
3246 LLVMValueRef sample_index,
3247 LLVMValueRef fmask_desc_ptr)
3248 {
3249 LLVMValueRef fmask_load_address[4];
3250 LLVMValueRef res;
3251
3252 fmask_load_address[0] = coord_x;
3253 fmask_load_address[1] = coord_y;
3254 if (coord_z) {
3255 fmask_load_address[2] = coord_z;
3256 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3257 }
3258
3259 struct ac_image_args args = {0};
3260
3261 args.opcode = ac_image_load;
3262 args.da = coord_z ? true : false;
3263 args.resource = fmask_desc_ptr;
3264 args.dmask = 0xf;
3265 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3266
3267 res = ac_build_image_opcode(ctx, &args);
3268
3269 res = to_integer(ctx, res);
3270 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3271 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3272
3273 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3274 res,
3275 ctx->i32_0, "");
3276
3277 LLVMValueRef sample_index4 =
3278 LLVMBuildMul(ctx->builder, sample_index, four, "");
3279 LLVMValueRef shifted_fmask =
3280 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3281 LLVMValueRef final_sample =
3282 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3283
3284 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3285 * resource descriptor is 0 (invalid),
3286 */
3287 LLVMValueRef fmask_desc =
3288 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3289 ctx->v8i32, "");
3290
3291 LLVMValueRef fmask_word1 =
3292 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3293 ctx->i32_1, "");
3294
3295 LLVMValueRef word1_is_nonzero =
3296 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3297 fmask_word1, ctx->i32_0, "");
3298
3299 /* Replace the MSAA sample index. */
3300 sample_index =
3301 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3302 final_sample, sample_index, "");
3303 return sample_index;
3304 }
3305
3306 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3307 const nir_intrinsic_instr *instr)
3308 {
3309 const struct glsl_type *type = instr->variables[0]->var->type;
3310 if(instr->variables[0]->deref.child)
3311 type = instr->variables[0]->deref.child->type;
3312
3313 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3314 LLVMValueRef coords[4];
3315 LLVMValueRef masks[] = {
3316 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3317 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3318 };
3319 LLVMValueRef res;
3320 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3321
3322 int count;
3323 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3324 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3325 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3326 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3327 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3328
3329 count = image_type_to_components_count(dim,
3330 glsl_sampler_type_is_array(type));
3331
3332 if (is_ms) {
3333 LLVMValueRef fmask_load_address[3];
3334 int chan;
3335
3336 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3337 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3338 if (glsl_sampler_type_is_array(type))
3339 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3340 else
3341 fmask_load_address[2] = NULL;
3342 if (add_frag_pos) {
3343 for (chan = 0; chan < 2; ++chan)
3344 fmask_load_address[chan] =
3345 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3346 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3347 ctx->ac.i32, ""), "");
3348 fmask_load_address[2] = to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3349 }
3350 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3351 fmask_load_address[0],
3352 fmask_load_address[1],
3353 fmask_load_address[2],
3354 sample_index,
3355 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3356 }
3357 if (count == 1) {
3358 if (instr->src[0].ssa->num_components)
3359 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3360 else
3361 res = src0;
3362 } else {
3363 int chan;
3364 if (is_ms)
3365 count--;
3366 for (chan = 0; chan < count; ++chan) {
3367 coords[chan] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[chan], "");
3368 }
3369
3370 if (add_frag_pos) {
3371 for (chan = 0; chan < 2; ++chan)
3372 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3373 ctx->ac.i32, ""), "");
3374 coords[2] = to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3375 count++;
3376 }
3377 if (is_ms) {
3378 coords[count] = sample_index;
3379 count++;
3380 }
3381
3382 if (count == 3) {
3383 coords[3] = LLVMGetUndef(ctx->ac.i32);
3384 count = 4;
3385 }
3386 res = ac_build_gather_values(&ctx->ac, coords, count);
3387 }
3388 return res;
3389 }
3390
3391 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3392 const nir_intrinsic_instr *instr)
3393 {
3394 LLVMValueRef params[7];
3395 LLVMValueRef res;
3396 char intrinsic_name[64];
3397 const nir_variable *var = instr->variables[0]->var;
3398 const struct glsl_type *type = var->type;
3399 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3400 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3401
3402 if(instr->variables[0]->deref.child)
3403 type = instr->variables[0]->deref.child->type;
3404
3405 type = glsl_without_array(type);
3406 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3407 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3408 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3409 ctx->ac.i32_0, ""); /* vindex */
3410 params[2] = ctx->ac.i32_0; /* voffset */
3411 params[3] = i1false; /* glc */
3412 params[4] = i1false; /* slc */
3413 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3414 params, 5, 0);
3415
3416 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3417 res = to_integer(&ctx->ac, res);
3418 } else {
3419 bool is_da = glsl_sampler_type_is_array(type) ||
3420 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3421 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3422 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3423 LLVMValueRef da = is_da ? i1true : i1false;
3424 LLVMValueRef glc = i1false;
3425 LLVMValueRef slc = i1false;
3426
3427 params[0] = get_image_coords(ctx, instr);
3428 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3429 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3430 if (HAVE_LLVM <= 0x0309) {
3431 params[3] = i1false; /* r128 */
3432 params[4] = da;
3433 params[5] = glc;
3434 params[6] = slc;
3435 } else {
3436 LLVMValueRef lwe = i1false;
3437 params[3] = glc;
3438 params[4] = slc;
3439 params[5] = lwe;
3440 params[6] = da;
3441 }
3442
3443 ac_get_image_intr_name("llvm.amdgcn.image.load",
3444 ctx->ac.v4f32, /* vdata */
3445 LLVMTypeOf(params[0]), /* coords */
3446 LLVMTypeOf(params[1]), /* rsrc */
3447 intrinsic_name, sizeof(intrinsic_name));
3448
3449 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3450 params, 7, AC_FUNC_ATTR_READONLY);
3451 }
3452 return to_integer(&ctx->ac, res);
3453 }
3454
3455 static void visit_image_store(struct ac_nir_context *ctx,
3456 nir_intrinsic_instr *instr)
3457 {
3458 LLVMValueRef params[8];
3459 char intrinsic_name[64];
3460 const nir_variable *var = instr->variables[0]->var;
3461 const struct glsl_type *type = glsl_without_array(var->type);
3462 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3463 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3464 LLVMValueRef glc = i1false;
3465 bool force_glc = ctx->abi->chip_class == SI;
3466 if (force_glc)
3467 glc = i1true;
3468
3469 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3470 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3471 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3472 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3473 ctx->ac.i32_0, ""); /* vindex */
3474 params[3] = ctx->ac.i32_0; /* voffset */
3475 params[4] = glc; /* glc */
3476 params[5] = i1false; /* slc */
3477 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3478 params, 6, 0);
3479 } else {
3480 bool is_da = glsl_sampler_type_is_array(type) ||
3481 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3482 LLVMValueRef da = is_da ? i1true : i1false;
3483 LLVMValueRef slc = i1false;
3484
3485 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3486 params[1] = get_image_coords(ctx, instr); /* coords */
3487 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3488 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3489 if (HAVE_LLVM <= 0x0309) {
3490 params[4] = i1false; /* r128 */
3491 params[5] = da;
3492 params[6] = glc;
3493 params[7] = slc;
3494 } else {
3495 LLVMValueRef lwe = i1false;
3496 params[4] = glc;
3497 params[5] = slc;
3498 params[6] = lwe;
3499 params[7] = da;
3500 }
3501
3502 ac_get_image_intr_name("llvm.amdgcn.image.store",
3503 LLVMTypeOf(params[0]), /* vdata */
3504 LLVMTypeOf(params[1]), /* coords */
3505 LLVMTypeOf(params[2]), /* rsrc */
3506 intrinsic_name, sizeof(intrinsic_name));
3507
3508 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3509 params, 8, 0);
3510 }
3511
3512 }
3513
3514 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3515 const nir_intrinsic_instr *instr)
3516 {
3517 LLVMValueRef params[6];
3518 int param_count = 0;
3519 const nir_variable *var = instr->variables[0]->var;
3520
3521 const char *atomic_name;
3522 char intrinsic_name[41];
3523 const struct glsl_type *type = glsl_without_array(var->type);
3524 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3525 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3526 MAYBE_UNUSED int length;
3527
3528 switch (instr->intrinsic) {
3529 case nir_intrinsic_image_atomic_add:
3530 atomic_name = "add";
3531 break;
3532 case nir_intrinsic_image_atomic_min:
3533 atomic_name = "smin";
3534 break;
3535 case nir_intrinsic_image_atomic_max:
3536 atomic_name = "smax";
3537 break;
3538 case nir_intrinsic_image_atomic_and:
3539 atomic_name = "and";
3540 break;
3541 case nir_intrinsic_image_atomic_or:
3542 atomic_name = "or";
3543 break;
3544 case nir_intrinsic_image_atomic_xor:
3545 atomic_name = "xor";
3546 break;
3547 case nir_intrinsic_image_atomic_exchange:
3548 atomic_name = "swap";
3549 break;
3550 case nir_intrinsic_image_atomic_comp_swap:
3551 atomic_name = "cmpswap";
3552 break;
3553 default:
3554 abort();
3555 }
3556
3557 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3558 params[param_count++] = get_src(ctx, instr->src[3]);
3559 params[param_count++] = get_src(ctx, instr->src[2]);
3560
3561 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3562 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3563 true, true);
3564 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3565 ctx->ac.i32_0, ""); /* vindex */
3566 params[param_count++] = ctx->ac.i32_0; /* voffset */
3567 params[param_count++] = i1false; /* slc */
3568
3569 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3570 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3571 } else {
3572 char coords_type[8];
3573
3574 bool da = glsl_sampler_type_is_array(type) ||
3575 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3576
3577 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3578 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3579 true, true);
3580 params[param_count++] = i1false; /* r128 */
3581 params[param_count++] = da ? i1true : i1false; /* da */
3582 params[param_count++] = i1false; /* slc */
3583
3584 build_int_type_name(LLVMTypeOf(coords),
3585 coords_type, sizeof(coords_type));
3586
3587 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3588 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3589 }
3590
3591 assert(length < sizeof(intrinsic_name));
3592 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3593 }
3594
3595 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3596 const nir_intrinsic_instr *instr)
3597 {
3598 LLVMValueRef res;
3599 const nir_variable *var = instr->variables[0]->var;
3600 const struct glsl_type *type = instr->variables[0]->var->type;
3601 bool da = glsl_sampler_type_is_array(var->type) ||
3602 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3603 if(instr->variables[0]->deref.child)
3604 type = instr->variables[0]->deref.child->type;
3605
3606 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3607 return get_buffer_size(ctx,
3608 get_sampler_desc(ctx, instr->variables[0],
3609 AC_DESC_BUFFER, true, false), true);
3610
3611 struct ac_image_args args = { 0 };
3612
3613 args.da = da;
3614 args.dmask = 0xf;
3615 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3616 args.opcode = ac_image_get_resinfo;
3617 args.addr = ctx->ac.i32_0;
3618
3619 res = ac_build_image_opcode(&ctx->ac, &args);
3620
3621 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3622 glsl_sampler_type_is_array(type)) {
3623 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3624 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3625 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3626 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3627 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3628 }
3629 return res;
3630 }
3631
3632 #define NOOP_WAITCNT 0xf7f
3633 #define LGKM_CNT 0x07f
3634 #define VM_CNT 0xf70
3635
3636 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3637 unsigned simm16)
3638 {
3639 LLVMValueRef args[1] = {
3640 LLVMConstInt(ctx->i32, simm16, false),
3641 };
3642 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3643 ctx->voidt, args, 1, 0);
3644 }
3645
3646 static void emit_barrier(struct nir_to_llvm_context *ctx)
3647 {
3648 /* SI only (thanks to a hw bug workaround):
3649 * The real barrier instruction isn’t needed, because an entire patch
3650 * always fits into a single wave.
3651 */
3652 if (ctx->options->chip_class == SI &&
3653 ctx->stage == MESA_SHADER_TESS_CTRL) {
3654 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3655 return;
3656 }
3657 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3658 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3659 }
3660
3661 static void emit_discard_if(struct ac_nir_context *ctx,
3662 const nir_intrinsic_instr *instr)
3663 {
3664 LLVMValueRef cond;
3665
3666 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
3667 get_src(ctx, instr->src[0]),
3668 ctx->ac.i32_0, "");
3669
3670 cond = LLVMBuildSelect(ctx->ac.builder, cond,
3671 LLVMConstReal(ctx->ac.f32, -1.0f),
3672 ctx->ac.f32_0, "");
3673 ac_build_kill(&ctx->ac, cond);
3674 }
3675
3676 static LLVMValueRef
3677 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3678 {
3679 LLVMValueRef result;
3680 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3681 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3682 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3683
3684 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3685 }
3686
3687 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3688 const nir_intrinsic_instr *instr)
3689 {
3690 LLVMValueRef ptr, result;
3691 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3692 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3693
3694 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3695 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3696 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3697 ptr, src, src1,
3698 LLVMAtomicOrderingSequentiallyConsistent,
3699 LLVMAtomicOrderingSequentiallyConsistent,
3700 false);
3701 } else {
3702 LLVMAtomicRMWBinOp op;
3703 switch (instr->intrinsic) {
3704 case nir_intrinsic_var_atomic_add:
3705 op = LLVMAtomicRMWBinOpAdd;
3706 break;
3707 case nir_intrinsic_var_atomic_umin:
3708 op = LLVMAtomicRMWBinOpUMin;
3709 break;
3710 case nir_intrinsic_var_atomic_umax:
3711 op = LLVMAtomicRMWBinOpUMax;
3712 break;
3713 case nir_intrinsic_var_atomic_imin:
3714 op = LLVMAtomicRMWBinOpMin;
3715 break;
3716 case nir_intrinsic_var_atomic_imax:
3717 op = LLVMAtomicRMWBinOpMax;
3718 break;
3719 case nir_intrinsic_var_atomic_and:
3720 op = LLVMAtomicRMWBinOpAnd;
3721 break;
3722 case nir_intrinsic_var_atomic_or:
3723 op = LLVMAtomicRMWBinOpOr;
3724 break;
3725 case nir_intrinsic_var_atomic_xor:
3726 op = LLVMAtomicRMWBinOpXor;
3727 break;
3728 case nir_intrinsic_var_atomic_exchange:
3729 op = LLVMAtomicRMWBinOpXchg;
3730 break;
3731 default:
3732 return NULL;
3733 }
3734
3735 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3736 LLVMAtomicOrderingSequentiallyConsistent,
3737 false);
3738 }
3739 return result;
3740 }
3741
3742 #define INTERP_CENTER 0
3743 #define INTERP_CENTROID 1
3744 #define INTERP_SAMPLE 2
3745
3746 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3747 enum glsl_interp_mode interp, unsigned location)
3748 {
3749 switch (interp) {
3750 case INTERP_MODE_FLAT:
3751 default:
3752 return NULL;
3753 case INTERP_MODE_SMOOTH:
3754 case INTERP_MODE_NONE:
3755 if (location == INTERP_CENTER)
3756 return ctx->persp_center;
3757 else if (location == INTERP_CENTROID)
3758 return ctx->persp_centroid;
3759 else if (location == INTERP_SAMPLE)
3760 return ctx->persp_sample;
3761 break;
3762 case INTERP_MODE_NOPERSPECTIVE:
3763 if (location == INTERP_CENTER)
3764 return ctx->linear_center;
3765 else if (location == INTERP_CENTROID)
3766 return ctx->linear_centroid;
3767 else if (location == INTERP_SAMPLE)
3768 return ctx->linear_sample;
3769 break;
3770 }
3771 return NULL;
3772 }
3773
3774 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3775 LLVMValueRef sample_id)
3776 {
3777 LLVMValueRef result;
3778 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3779
3780 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3781 const_array(ctx->v2f32, 64), "");
3782
3783 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3784 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3785
3786 return result;
3787 }
3788
3789 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3790 {
3791 LLVMValueRef values[2];
3792
3793 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3794 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3795 return ac_build_gather_values(&ctx->ac, values, 2);
3796 }
3797
3798 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3799 const nir_intrinsic_instr *instr)
3800 {
3801 LLVMValueRef result[2];
3802 LLVMValueRef interp_param, attr_number;
3803 unsigned location;
3804 unsigned chan;
3805 LLVMValueRef src_c0, src_c1;
3806 LLVMValueRef src0;
3807 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3808 switch (instr->intrinsic) {
3809 case nir_intrinsic_interp_var_at_centroid:
3810 location = INTERP_CENTROID;
3811 break;
3812 case nir_intrinsic_interp_var_at_sample:
3813 case nir_intrinsic_interp_var_at_offset:
3814 location = INTERP_CENTER;
3815 src0 = get_src(ctx->nir, instr->src[0]);
3816 break;
3817 default:
3818 break;
3819 }
3820
3821 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3822 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3823 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3824 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3825 LLVMValueRef sample_position;
3826 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3827
3828 /* fetch sample ID */
3829 sample_position = load_sample_position(ctx, src0);
3830
3831 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3832 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3833 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3834 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3835 }
3836 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3837 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3838
3839 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3840 LLVMValueRef ij_out[2];
3841 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3842
3843 /*
3844 * take the I then J parameters, and the DDX/Y for it, and
3845 * calculate the IJ inputs for the interpolator.
3846 * temp1 = ddx * offset/sample.x + I;
3847 * interp_param.I = ddy * offset/sample.y + temp1;
3848 * temp1 = ddx * offset/sample.x + J;
3849 * interp_param.J = ddy * offset/sample.y + temp1;
3850 */
3851 for (unsigned i = 0; i < 2; i++) {
3852 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3853 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3854 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3855 ddxy_out, ix_ll, "");
3856 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3857 ddxy_out, iy_ll, "");
3858 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3859 interp_param, ix_ll, "");
3860 LLVMValueRef temp1, temp2;
3861
3862 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3863 ctx->f32, "");
3864
3865 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3866 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3867
3868 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3869 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3870
3871 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3872 temp2, ctx->i32, "");
3873 }
3874 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3875
3876 }
3877
3878 for (chan = 0; chan < 2; chan++) {
3879 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3880
3881 if (interp_param) {
3882 interp_param = LLVMBuildBitCast(ctx->builder,
3883 interp_param, LLVMVectorType(ctx->f32, 2), "");
3884 LLVMValueRef i = LLVMBuildExtractElement(
3885 ctx->builder, interp_param, ctx->i32zero, "");
3886 LLVMValueRef j = LLVMBuildExtractElement(
3887 ctx->builder, interp_param, ctx->i32one, "");
3888
3889 result[chan] = ac_build_fs_interp(&ctx->ac,
3890 llvm_chan, attr_number,
3891 ctx->prim_mask, i, j);
3892 } else {
3893 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3894 LLVMConstInt(ctx->i32, 2, false),
3895 llvm_chan, attr_number,
3896 ctx->prim_mask);
3897 }
3898 }
3899 return ac_build_gather_values(&ctx->ac, result, 2);
3900 }
3901
3902 static void
3903 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3904 const nir_intrinsic_instr *instr)
3905 {
3906 LLVMValueRef gs_next_vertex;
3907 LLVMValueRef can_emit, kill;
3908 int idx;
3909
3910 assert(instr->const_index[0] == 0);
3911 /* Write vertex attribute values to GSVS ring */
3912 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3913 ctx->gs_next_vertex,
3914 "");
3915
3916 /* If this thread has already emitted the declared maximum number of
3917 * vertices, kill it: excessive vertex emissions are not supposed to
3918 * have any effect, and GS threads have no externally observable
3919 * effects other than emitting vertices.
3920 */
3921 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3922 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3923
3924 kill = LLVMBuildSelect(ctx->builder, can_emit,
3925 LLVMConstReal(ctx->f32, 1.0f),
3926 LLVMConstReal(ctx->f32, -1.0f), "");
3927 ac_build_kill(&ctx->ac, kill);
3928
3929 /* loop num outputs */
3930 idx = 0;
3931 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3932 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3933 int length = 4;
3934 int slot = idx;
3935 int slot_inc = 1;
3936
3937 if (!(ctx->output_mask & (1ull << i)))
3938 continue;
3939
3940 if (i == VARYING_SLOT_CLIP_DIST0) {
3941 /* pack clip and cull into a single set of slots */
3942 length = ctx->num_output_clips + ctx->num_output_culls;
3943 if (length > 4)
3944 slot_inc = 2;
3945 }
3946 for (unsigned j = 0; j < length; j++) {
3947 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3948 out_ptr[j], "");
3949 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3950 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3951 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3952
3953 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3954
3955 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3956 out_val, 1,
3957 voffset, ctx->gs2vs_offset, 0,
3958 1, 1, true, true);
3959 }
3960 idx += slot_inc;
3961 }
3962
3963 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3964 ctx->i32one, "");
3965 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3966
3967 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3968 }
3969
3970 static void
3971 visit_end_primitive(struct nir_to_llvm_context *ctx,
3972 const nir_intrinsic_instr *instr)
3973 {
3974 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3975 }
3976
3977 static LLVMValueRef
3978 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3979 const nir_intrinsic_instr *instr)
3980 {
3981 LLVMValueRef coord[4] = {
3982 ctx->tes_u,
3983 ctx->tes_v,
3984 ctx->f32zero,
3985 ctx->f32zero,
3986 };
3987
3988 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3989 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3990 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3991
3992 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3993 return LLVMBuildBitCast(ctx->builder, result,
3994 get_def_type(ctx->nir, &instr->dest.ssa), "");
3995 }
3996
3997 static void visit_intrinsic(struct ac_nir_context *ctx,
3998 nir_intrinsic_instr *instr)
3999 {
4000 LLVMValueRef result = NULL;
4001
4002 switch (instr->intrinsic) {
4003 case nir_intrinsic_load_work_group_id: {
4004 result = ctx->nctx->workgroup_ids;
4005 break;
4006 }
4007 case nir_intrinsic_load_base_vertex: {
4008 result = ctx->abi->base_vertex;
4009 break;
4010 }
4011 case nir_intrinsic_load_vertex_id_zero_base: {
4012 result = ctx->abi->vertex_id;
4013 break;
4014 }
4015 case nir_intrinsic_load_local_invocation_id: {
4016 result = ctx->nctx->local_invocation_ids;
4017 break;
4018 }
4019 case nir_intrinsic_load_base_instance:
4020 result = ctx->abi->start_instance;
4021 break;
4022 case nir_intrinsic_load_draw_id:
4023 result = ctx->abi->draw_id;
4024 break;
4025 case nir_intrinsic_load_invocation_id:
4026 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4027 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4028 else
4029 result = ctx->nctx->gs_invocation_id;
4030 break;
4031 case nir_intrinsic_load_primitive_id:
4032 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4033 ctx->nctx->shader_info->gs.uses_prim_id = true;
4034 result = ctx->nctx->gs_prim_id;
4035 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4036 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4037 result = ctx->nctx->tcs_patch_id;
4038 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4039 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4040 result = ctx->nctx->tes_patch_id;
4041 } else
4042 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4043 break;
4044 case nir_intrinsic_load_sample_id:
4045 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4046 break;
4047 case nir_intrinsic_load_sample_pos:
4048 result = load_sample_pos(ctx);
4049 break;
4050 case nir_intrinsic_load_sample_mask_in:
4051 result = ctx->abi->sample_coverage;
4052 break;
4053 case nir_intrinsic_load_frag_coord: {
4054 LLVMValueRef values[4] = {
4055 ctx->abi->frag_pos[0],
4056 ctx->abi->frag_pos[1],
4057 ctx->abi->frag_pos[2],
4058 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4059 };
4060 result = ac_build_gather_values(&ctx->ac, values, 4);
4061 break;
4062 }
4063 case nir_intrinsic_load_front_face:
4064 result = ctx->abi->front_face;
4065 break;
4066 case nir_intrinsic_load_instance_id:
4067 result = ctx->abi->instance_id;
4068 break;
4069 case nir_intrinsic_load_num_work_groups:
4070 result = ctx->nctx->num_work_groups;
4071 break;
4072 case nir_intrinsic_load_local_invocation_index:
4073 result = visit_load_local_invocation_index(ctx->nctx);
4074 break;
4075 case nir_intrinsic_load_push_constant:
4076 result = visit_load_push_constant(ctx->nctx, instr);
4077 break;
4078 case nir_intrinsic_vulkan_resource_index:
4079 result = visit_vulkan_resource_index(ctx->nctx, instr);
4080 break;
4081 case nir_intrinsic_store_ssbo:
4082 visit_store_ssbo(ctx, instr);
4083 break;
4084 case nir_intrinsic_load_ssbo:
4085 result = visit_load_buffer(ctx, instr);
4086 break;
4087 case nir_intrinsic_ssbo_atomic_add:
4088 case nir_intrinsic_ssbo_atomic_imin:
4089 case nir_intrinsic_ssbo_atomic_umin:
4090 case nir_intrinsic_ssbo_atomic_imax:
4091 case nir_intrinsic_ssbo_atomic_umax:
4092 case nir_intrinsic_ssbo_atomic_and:
4093 case nir_intrinsic_ssbo_atomic_or:
4094 case nir_intrinsic_ssbo_atomic_xor:
4095 case nir_intrinsic_ssbo_atomic_exchange:
4096 case nir_intrinsic_ssbo_atomic_comp_swap:
4097 result = visit_atomic_ssbo(ctx, instr);
4098 break;
4099 case nir_intrinsic_load_ubo:
4100 result = visit_load_ubo_buffer(ctx, instr);
4101 break;
4102 case nir_intrinsic_get_buffer_size:
4103 result = visit_get_buffer_size(ctx, instr);
4104 break;
4105 case nir_intrinsic_load_var:
4106 result = visit_load_var(ctx, instr);
4107 break;
4108 case nir_intrinsic_store_var:
4109 visit_store_var(ctx, instr);
4110 break;
4111 case nir_intrinsic_image_load:
4112 result = visit_image_load(ctx, instr);
4113 break;
4114 case nir_intrinsic_image_store:
4115 visit_image_store(ctx, instr);
4116 break;
4117 case nir_intrinsic_image_atomic_add:
4118 case nir_intrinsic_image_atomic_min:
4119 case nir_intrinsic_image_atomic_max:
4120 case nir_intrinsic_image_atomic_and:
4121 case nir_intrinsic_image_atomic_or:
4122 case nir_intrinsic_image_atomic_xor:
4123 case nir_intrinsic_image_atomic_exchange:
4124 case nir_intrinsic_image_atomic_comp_swap:
4125 result = visit_image_atomic(ctx, instr);
4126 break;
4127 case nir_intrinsic_image_size:
4128 result = visit_image_size(ctx, instr);
4129 break;
4130 case nir_intrinsic_discard:
4131 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4132 LLVMVoidTypeInContext(ctx->ac.context),
4133 NULL, 0, AC_FUNC_ATTR_LEGACY);
4134 break;
4135 case nir_intrinsic_discard_if:
4136 emit_discard_if(ctx, instr);
4137 break;
4138 case nir_intrinsic_memory_barrier:
4139 emit_waitcnt(ctx->nctx, VM_CNT);
4140 break;
4141 case nir_intrinsic_barrier:
4142 emit_barrier(ctx->nctx);
4143 break;
4144 case nir_intrinsic_var_atomic_add:
4145 case nir_intrinsic_var_atomic_imin:
4146 case nir_intrinsic_var_atomic_umin:
4147 case nir_intrinsic_var_atomic_imax:
4148 case nir_intrinsic_var_atomic_umax:
4149 case nir_intrinsic_var_atomic_and:
4150 case nir_intrinsic_var_atomic_or:
4151 case nir_intrinsic_var_atomic_xor:
4152 case nir_intrinsic_var_atomic_exchange:
4153 case nir_intrinsic_var_atomic_comp_swap:
4154 result = visit_var_atomic(ctx->nctx, instr);
4155 break;
4156 case nir_intrinsic_interp_var_at_centroid:
4157 case nir_intrinsic_interp_var_at_sample:
4158 case nir_intrinsic_interp_var_at_offset:
4159 result = visit_interp(ctx->nctx, instr);
4160 break;
4161 case nir_intrinsic_emit_vertex:
4162 visit_emit_vertex(ctx->nctx, instr);
4163 break;
4164 case nir_intrinsic_end_primitive:
4165 visit_end_primitive(ctx->nctx, instr);
4166 break;
4167 case nir_intrinsic_load_tess_coord:
4168 result = visit_load_tess_coord(ctx->nctx, instr);
4169 break;
4170 case nir_intrinsic_load_patch_vertices_in:
4171 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4172 break;
4173 default:
4174 fprintf(stderr, "Unknown intrinsic: ");
4175 nir_print_instr(&instr->instr, stderr);
4176 fprintf(stderr, "\n");
4177 break;
4178 }
4179 if (result) {
4180 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4181 }
4182 }
4183
4184 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4185 LLVMValueRef buffer, bool write)
4186 {
4187 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4188
4189 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4190 ctx->shader_info->fs.writes_memory = true;
4191
4192 return buffer;
4193 }
4194
4195 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4196 unsigned descriptor_set,
4197 unsigned base_index,
4198 unsigned constant_index,
4199 LLVMValueRef index,
4200 enum ac_descriptor_type desc_type,
4201 bool image, bool write)
4202 {
4203 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4204 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4205 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4206 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4207 unsigned offset = binding->offset;
4208 unsigned stride = binding->size;
4209 unsigned type_size;
4210 LLVMBuilderRef builder = ctx->builder;
4211 LLVMTypeRef type;
4212
4213 assert(base_index < layout->binding_count);
4214
4215 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4216 ctx->shader_info->fs.writes_memory = true;
4217
4218 switch (desc_type) {
4219 case AC_DESC_IMAGE:
4220 type = ctx->v8i32;
4221 type_size = 32;
4222 break;
4223 case AC_DESC_FMASK:
4224 type = ctx->v8i32;
4225 offset += 32;
4226 type_size = 32;
4227 break;
4228 case AC_DESC_SAMPLER:
4229 type = ctx->v4i32;
4230 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4231 offset += 64;
4232
4233 type_size = 16;
4234 break;
4235 case AC_DESC_BUFFER:
4236 type = ctx->v4i32;
4237 type_size = 16;
4238 break;
4239 default:
4240 unreachable("invalid desc_type\n");
4241 }
4242
4243 offset += constant_index * stride;
4244
4245 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4246 (!index || binding->immutable_samplers_equal)) {
4247 if (binding->immutable_samplers_equal)
4248 constant_index = 0;
4249
4250 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4251
4252 LLVMValueRef constants[] = {
4253 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4254 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4255 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4256 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4257 };
4258 return ac_build_gather_values(&ctx->ac, constants, 4);
4259 }
4260
4261 assert(stride % type_size == 0);
4262
4263 if (!index)
4264 index = ctx->i32zero;
4265
4266 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4267
4268 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4269 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4270
4271 return ac_build_indexed_load_const(&ctx->ac, list, index);
4272 }
4273
4274 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4275 const nir_deref_var *deref,
4276 enum ac_descriptor_type desc_type,
4277 bool image, bool write)
4278 {
4279 LLVMValueRef index = NULL;
4280 unsigned constant_index = 0;
4281 const nir_deref *tail = &deref->deref;
4282
4283 while (tail->child) {
4284 const nir_deref_array *child = nir_deref_as_array(tail->child);
4285 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4286
4287 if (!array_size)
4288 array_size = 1;
4289
4290 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4291
4292 if (child->deref_array_type == nir_deref_array_type_indirect) {
4293 LLVMValueRef indirect = get_src(ctx, child->indirect);
4294
4295 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4296 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4297
4298 if (!index)
4299 index = indirect;
4300 else
4301 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4302 }
4303
4304 constant_index += child->base_offset * array_size;
4305
4306 tail = &child->deref;
4307 }
4308
4309 return ctx->abi->load_sampler_desc(ctx->abi,
4310 deref->var->data.descriptor_set,
4311 deref->var->data.binding,
4312 constant_index, index,
4313 desc_type, image, write);
4314 }
4315
4316 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4317 struct ac_image_args *args,
4318 const nir_tex_instr *instr,
4319 nir_texop op,
4320 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4321 LLVMValueRef *param, unsigned count,
4322 unsigned dmask)
4323 {
4324 unsigned is_rect = 0;
4325 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4326
4327 if (op == nir_texop_lod)
4328 da = false;
4329 /* Pad to power of two vector */
4330 while (count < util_next_power_of_two(count))
4331 param[count++] = LLVMGetUndef(ctx->i32);
4332
4333 if (count > 1)
4334 args->addr = ac_build_gather_values(ctx, param, count);
4335 else
4336 args->addr = param[0];
4337
4338 args->resource = res_ptr;
4339 args->sampler = samp_ptr;
4340
4341 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4342 args->addr = param[0];
4343 return;
4344 }
4345
4346 args->dmask = dmask;
4347 args->unorm = is_rect;
4348 args->da = da;
4349 }
4350
4351 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4352 *
4353 * SI-CI:
4354 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4355 * filtering manually. The driver sets img7 to a mask clearing
4356 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4357 * s_and_b32 samp0, samp0, img7
4358 *
4359 * VI:
4360 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4361 */
4362 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4363 LLVMValueRef res, LLVMValueRef samp)
4364 {
4365 LLVMBuilderRef builder = ctx->ac.builder;
4366 LLVMValueRef img7, samp0;
4367
4368 if (ctx->abi->chip_class >= VI)
4369 return samp;
4370
4371 img7 = LLVMBuildExtractElement(builder, res,
4372 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4373 samp0 = LLVMBuildExtractElement(builder, samp,
4374 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4375 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4376 return LLVMBuildInsertElement(builder, samp, samp0,
4377 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4378 }
4379
4380 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4381 nir_tex_instr *instr,
4382 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4383 LLVMValueRef *fmask_ptr)
4384 {
4385 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4386 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4387 else
4388 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4389 if (samp_ptr) {
4390 if (instr->sampler)
4391 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4392 else
4393 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4394 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4395 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4396 }
4397 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4398 instr->op == nir_texop_samples_identical))
4399 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4400 }
4401
4402 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4403 LLVMValueRef coord)
4404 {
4405 coord = to_float(ctx, coord);
4406 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4407 coord = to_integer(ctx, coord);
4408 return coord;
4409 }
4410
4411 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4412 {
4413 LLVMValueRef result = NULL;
4414 struct ac_image_args args = { 0 };
4415 unsigned dmask = 0xf;
4416 LLVMValueRef address[16];
4417 LLVMValueRef coords[5];
4418 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4419 LLVMValueRef bias = NULL, offsets = NULL;
4420 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4421 LLVMValueRef ddx = NULL, ddy = NULL;
4422 LLVMValueRef derivs[6];
4423 unsigned chan, count = 0;
4424 unsigned const_src = 0, num_deriv_comp = 0;
4425 bool lod_is_zero = false;
4426
4427 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4428
4429 for (unsigned i = 0; i < instr->num_srcs; i++) {
4430 switch (instr->src[i].src_type) {
4431 case nir_tex_src_coord:
4432 coord = get_src(ctx, instr->src[i].src);
4433 break;
4434 case nir_tex_src_projector:
4435 break;
4436 case nir_tex_src_comparator:
4437 comparator = get_src(ctx, instr->src[i].src);
4438 break;
4439 case nir_tex_src_offset:
4440 offsets = get_src(ctx, instr->src[i].src);
4441 const_src = i;
4442 break;
4443 case nir_tex_src_bias:
4444 bias = get_src(ctx, instr->src[i].src);
4445 break;
4446 case nir_tex_src_lod: {
4447 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4448
4449 if (val && val->i32[0] == 0)
4450 lod_is_zero = true;
4451 lod = get_src(ctx, instr->src[i].src);
4452 break;
4453 }
4454 case nir_tex_src_ms_index:
4455 sample_index = get_src(ctx, instr->src[i].src);
4456 break;
4457 case nir_tex_src_ms_mcs:
4458 break;
4459 case nir_tex_src_ddx:
4460 ddx = get_src(ctx, instr->src[i].src);
4461 num_deriv_comp = instr->src[i].src.ssa->num_components;
4462 break;
4463 case nir_tex_src_ddy:
4464 ddy = get_src(ctx, instr->src[i].src);
4465 break;
4466 case nir_tex_src_texture_offset:
4467 case nir_tex_src_sampler_offset:
4468 case nir_tex_src_plane:
4469 default:
4470 break;
4471 }
4472 }
4473
4474 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4475 result = get_buffer_size(ctx, res_ptr, true);
4476 goto write_result;
4477 }
4478
4479 if (instr->op == nir_texop_texture_samples) {
4480 LLVMValueRef res, samples, is_msaa;
4481 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4482 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4483 LLVMConstInt(ctx->ac.i32, 3, false), "");
4484 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4485 LLVMConstInt(ctx->ac.i32, 28, false), "");
4486 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4487 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4488 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4489 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4490
4491 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4492 LLVMConstInt(ctx->ac.i32, 16, false), "");
4493 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4494 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4495 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4496 samples, "");
4497 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4498 ctx->ac.i32_1, "");
4499 result = samples;
4500 goto write_result;
4501 }
4502
4503 if (coord)
4504 for (chan = 0; chan < instr->coord_components; chan++)
4505 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4506
4507 if (offsets && instr->op != nir_texop_txf) {
4508 LLVMValueRef offset[3], pack;
4509 for (chan = 0; chan < 3; ++chan)
4510 offset[chan] = ctx->ac.i32_0;
4511
4512 args.offset = true;
4513 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4514 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4515 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4516 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4517 if (chan)
4518 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4519 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4520 }
4521 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4522 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4523 address[count++] = pack;
4524
4525 }
4526 /* pack LOD bias value */
4527 if (instr->op == nir_texop_txb && bias) {
4528 address[count++] = bias;
4529 }
4530
4531 /* Pack depth comparison value */
4532 if (instr->is_shadow && comparator) {
4533 LLVMValueRef z = to_float(&ctx->ac,
4534 llvm_extract_elem(&ctx->ac, comparator, 0));
4535
4536 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4537 * so the depth comparison value isn't clamped for Z16 and
4538 * Z24 anymore. Do it manually here.
4539 *
4540 * It's unnecessary if the original texture format was
4541 * Z32_FLOAT, but we don't know that here.
4542 */
4543 if (ctx->abi->chip_class == VI)
4544 z = ac_build_clamp(&ctx->ac, z);
4545
4546 address[count++] = z;
4547 }
4548
4549 /* pack derivatives */
4550 if (ddx || ddy) {
4551 switch (instr->sampler_dim) {
4552 case GLSL_SAMPLER_DIM_3D:
4553 case GLSL_SAMPLER_DIM_CUBE:
4554 num_deriv_comp = 3;
4555 break;
4556 case GLSL_SAMPLER_DIM_2D:
4557 default:
4558 num_deriv_comp = 2;
4559 break;
4560 case GLSL_SAMPLER_DIM_1D:
4561 num_deriv_comp = 1;
4562 break;
4563 }
4564
4565 for (unsigned i = 0; i < num_deriv_comp; i++) {
4566 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4567 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4568 }
4569 }
4570
4571 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4572 if (instr->is_array && instr->op != nir_texop_lod)
4573 coords[3] = apply_round_slice(&ctx->ac, coords[3]);
4574 for (chan = 0; chan < instr->coord_components; chan++)
4575 coords[chan] = to_float(&ctx->ac, coords[chan]);
4576 if (instr->coord_components == 3)
4577 coords[3] = LLVMGetUndef(ctx->ac.f32);
4578 ac_prepare_cube_coords(&ctx->ac,
4579 instr->op == nir_texop_txd, instr->is_array,
4580 coords, derivs);
4581 if (num_deriv_comp)
4582 num_deriv_comp--;
4583 }
4584
4585 if (ddx || ddy) {
4586 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4587 address[count++] = derivs[i];
4588 }
4589
4590 /* Pack texture coordinates */
4591 if (coord) {
4592 address[count++] = coords[0];
4593 if (instr->coord_components > 1) {
4594 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4595 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4596 }
4597 address[count++] = coords[1];
4598 }
4599 if (instr->coord_components > 2) {
4600 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4601 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4602 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4603 instr->op != nir_texop_txf) {
4604 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4605 }
4606 address[count++] = coords[2];
4607 }
4608 }
4609
4610 /* Pack LOD */
4611 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4612 instr->op == nir_texop_txf)) {
4613 address[count++] = lod;
4614 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4615 address[count++] = sample_index;
4616 } else if(instr->op == nir_texop_txs) {
4617 count = 0;
4618 if (lod)
4619 address[count++] = lod;
4620 else
4621 address[count++] = ctx->ac.i32_0;
4622 }
4623
4624 for (chan = 0; chan < count; chan++) {
4625 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4626 address[chan], ctx->ac.i32, "");
4627 }
4628
4629 if (instr->op == nir_texop_samples_identical) {
4630 LLVMValueRef txf_address[4];
4631 struct ac_image_args txf_args = { 0 };
4632 unsigned txf_count = count;
4633 memcpy(txf_address, address, sizeof(txf_address));
4634
4635 if (!instr->is_array)
4636 txf_address[2] = ctx->ac.i32_0;
4637 txf_address[3] = ctx->ac.i32_0;
4638
4639 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4640 fmask_ptr, NULL,
4641 txf_address, txf_count, 0xf);
4642
4643 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4644
4645 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4646 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4647 goto write_result;
4648 }
4649
4650 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4651 instr->op != nir_texop_txs) {
4652 unsigned sample_chan = instr->is_array ? 3 : 2;
4653 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4654 address[0],
4655 address[1],
4656 instr->is_array ? address[2] : NULL,
4657 address[sample_chan],
4658 fmask_ptr);
4659 }
4660
4661 if (offsets && instr->op == nir_texop_txf) {
4662 nir_const_value *const_offset =
4663 nir_src_as_const_value(instr->src[const_src].src);
4664 int num_offsets = instr->src[const_src].src.ssa->num_components;
4665 assert(const_offset);
4666 num_offsets = MIN2(num_offsets, instr->coord_components);
4667 if (num_offsets > 2)
4668 address[2] = LLVMBuildAdd(ctx->ac.builder,
4669 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4670 if (num_offsets > 1)
4671 address[1] = LLVMBuildAdd(ctx->ac.builder,
4672 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4673 address[0] = LLVMBuildAdd(ctx->ac.builder,
4674 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4675
4676 }
4677
4678 /* TODO TG4 support */
4679 if (instr->op == nir_texop_tg4) {
4680 if (instr->is_shadow)
4681 dmask = 1;
4682 else
4683 dmask = 1 << instr->component;
4684 }
4685 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4686 res_ptr, samp_ptr, address, count, dmask);
4687
4688 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4689
4690 if (instr->op == nir_texop_query_levels)
4691 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4692 else if (instr->is_shadow && instr->is_new_style_shadow &&
4693 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4694 instr->op != nir_texop_tg4)
4695 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4696 else if (instr->op == nir_texop_txs &&
4697 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4698 instr->is_array) {
4699 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4700 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4701 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4702 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4703 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4704 } else if (instr->dest.ssa.num_components != 4)
4705 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4706
4707 write_result:
4708 if (result) {
4709 assert(instr->dest.is_ssa);
4710 result = to_integer(&ctx->ac, result);
4711 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4712 }
4713 }
4714
4715
4716 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4717 {
4718 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4719 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4720
4721 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4722 _mesa_hash_table_insert(ctx->phis, instr, result);
4723 }
4724
4725 static void visit_post_phi(struct ac_nir_context *ctx,
4726 nir_phi_instr *instr,
4727 LLVMValueRef llvm_phi)
4728 {
4729 nir_foreach_phi_src(src, instr) {
4730 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4731 LLVMValueRef llvm_src = get_src(ctx, src->src);
4732
4733 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4734 }
4735 }
4736
4737 static void phi_post_pass(struct ac_nir_context *ctx)
4738 {
4739 struct hash_entry *entry;
4740 hash_table_foreach(ctx->phis, entry) {
4741 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4742 (LLVMValueRef)entry->data);
4743 }
4744 }
4745
4746
4747 static void visit_ssa_undef(struct ac_nir_context *ctx,
4748 const nir_ssa_undef_instr *instr)
4749 {
4750 unsigned num_components = instr->def.num_components;
4751 LLVMValueRef undef;
4752
4753 if (num_components == 1)
4754 undef = LLVMGetUndef(ctx->ac.i32);
4755 else {
4756 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4757 }
4758 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4759 }
4760
4761 static void visit_jump(struct ac_nir_context *ctx,
4762 const nir_jump_instr *instr)
4763 {
4764 switch (instr->type) {
4765 case nir_jump_break:
4766 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4767 LLVMClearInsertionPosition(ctx->ac.builder);
4768 break;
4769 case nir_jump_continue:
4770 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4771 LLVMClearInsertionPosition(ctx->ac.builder);
4772 break;
4773 default:
4774 fprintf(stderr, "Unknown NIR jump instr: ");
4775 nir_print_instr(&instr->instr, stderr);
4776 fprintf(stderr, "\n");
4777 abort();
4778 }
4779 }
4780
4781 static void visit_cf_list(struct ac_nir_context *ctx,
4782 struct exec_list *list);
4783
4784 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4785 {
4786 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4787 nir_foreach_instr(instr, block)
4788 {
4789 switch (instr->type) {
4790 case nir_instr_type_alu:
4791 visit_alu(ctx, nir_instr_as_alu(instr));
4792 break;
4793 case nir_instr_type_load_const:
4794 visit_load_const(ctx, nir_instr_as_load_const(instr));
4795 break;
4796 case nir_instr_type_intrinsic:
4797 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4798 break;
4799 case nir_instr_type_tex:
4800 visit_tex(ctx, nir_instr_as_tex(instr));
4801 break;
4802 case nir_instr_type_phi:
4803 visit_phi(ctx, nir_instr_as_phi(instr));
4804 break;
4805 case nir_instr_type_ssa_undef:
4806 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4807 break;
4808 case nir_instr_type_jump:
4809 visit_jump(ctx, nir_instr_as_jump(instr));
4810 break;
4811 default:
4812 fprintf(stderr, "Unknown NIR instr type: ");
4813 nir_print_instr(instr, stderr);
4814 fprintf(stderr, "\n");
4815 abort();
4816 }
4817 }
4818
4819 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4820 }
4821
4822 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4823 {
4824 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4825
4826 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4827 LLVMBasicBlockRef merge_block =
4828 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4829 LLVMBasicBlockRef if_block =
4830 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4831 LLVMBasicBlockRef else_block = merge_block;
4832 if (!exec_list_is_empty(&if_stmt->else_list))
4833 else_block = LLVMAppendBasicBlockInContext(
4834 ctx->ac.context, fn, "");
4835
4836 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4837 LLVMConstInt(ctx->ac.i32, 0, false), "");
4838 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4839
4840 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4841 visit_cf_list(ctx, &if_stmt->then_list);
4842 if (LLVMGetInsertBlock(ctx->ac.builder))
4843 LLVMBuildBr(ctx->ac.builder, merge_block);
4844
4845 if (!exec_list_is_empty(&if_stmt->else_list)) {
4846 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4847 visit_cf_list(ctx, &if_stmt->else_list);
4848 if (LLVMGetInsertBlock(ctx->ac.builder))
4849 LLVMBuildBr(ctx->ac.builder, merge_block);
4850 }
4851
4852 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4853 }
4854
4855 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4856 {
4857 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4858 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4859 LLVMBasicBlockRef break_parent = ctx->break_block;
4860
4861 ctx->continue_block =
4862 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4863 ctx->break_block =
4864 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4865
4866 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4867 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4868 visit_cf_list(ctx, &loop->body);
4869
4870 if (LLVMGetInsertBlock(ctx->ac.builder))
4871 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4872 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4873
4874 ctx->continue_block = continue_parent;
4875 ctx->break_block = break_parent;
4876 }
4877
4878 static void visit_cf_list(struct ac_nir_context *ctx,
4879 struct exec_list *list)
4880 {
4881 foreach_list_typed(nir_cf_node, node, node, list)
4882 {
4883 switch (node->type) {
4884 case nir_cf_node_block:
4885 visit_block(ctx, nir_cf_node_as_block(node));
4886 break;
4887
4888 case nir_cf_node_if:
4889 visit_if(ctx, nir_cf_node_as_if(node));
4890 break;
4891
4892 case nir_cf_node_loop:
4893 visit_loop(ctx, nir_cf_node_as_loop(node));
4894 break;
4895
4896 default:
4897 assert(0);
4898 }
4899 }
4900 }
4901
4902 static void
4903 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4904 struct nir_variable *variable)
4905 {
4906 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4907 LLVMValueRef t_offset;
4908 LLVMValueRef t_list;
4909 LLVMValueRef input;
4910 LLVMValueRef buffer_index;
4911 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4912 int idx = variable->data.location;
4913 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4914
4915 variable->data.driver_location = idx * 4;
4916
4917 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4918 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4919 ctx->abi.start_instance, "");
4920 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4921 ctx->shader_info->vs.vgpr_comp_cnt);
4922 } else
4923 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4924 ctx->abi.base_vertex, "");
4925
4926 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4927 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4928
4929 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4930
4931 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4932 buffer_index,
4933 LLVMConstInt(ctx->i32, 0, false),
4934 true);
4935
4936 for (unsigned chan = 0; chan < 4; chan++) {
4937 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4938 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4939 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4940 input, llvm_chan, ""));
4941 }
4942 }
4943 }
4944
4945 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4946 unsigned attr,
4947 LLVMValueRef interp_param,
4948 LLVMValueRef prim_mask,
4949 LLVMValueRef result[4])
4950 {
4951 LLVMValueRef attr_number;
4952 unsigned chan;
4953 LLVMValueRef i, j;
4954 bool interp = interp_param != NULL;
4955
4956 attr_number = LLVMConstInt(ctx->i32, attr, false);
4957
4958 /* fs.constant returns the param from the middle vertex, so it's not
4959 * really useful for flat shading. It's meant to be used for custom
4960 * interpolation (but the intrinsic can't fetch from the other two
4961 * vertices).
4962 *
4963 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4964 * to do the right thing. The only reason we use fs.constant is that
4965 * fs.interp cannot be used on integers, because they can be equal
4966 * to NaN.
4967 */
4968 if (interp) {
4969 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4970 LLVMVectorType(ctx->f32, 2), "");
4971
4972 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4973 ctx->i32zero, "");
4974 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4975 ctx->i32one, "");
4976 }
4977
4978 for (chan = 0; chan < 4; chan++) {
4979 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4980
4981 if (interp) {
4982 result[chan] = ac_build_fs_interp(&ctx->ac,
4983 llvm_chan,
4984 attr_number,
4985 prim_mask, i, j);
4986 } else {
4987 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4988 LLVMConstInt(ctx->i32, 2, false),
4989 llvm_chan,
4990 attr_number,
4991 prim_mask);
4992 }
4993 }
4994 }
4995
4996 static void
4997 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4998 struct nir_variable *variable)
4999 {
5000 int idx = variable->data.location;
5001 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5002 LLVMValueRef interp;
5003
5004 variable->data.driver_location = idx * 4;
5005 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5006
5007 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5008 unsigned interp_type;
5009 if (variable->data.sample) {
5010 interp_type = INTERP_SAMPLE;
5011 ctx->shader_info->info.ps.force_persample = true;
5012 } else if (variable->data.centroid)
5013 interp_type = INTERP_CENTROID;
5014 else
5015 interp_type = INTERP_CENTER;
5016
5017 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5018 } else
5019 interp = NULL;
5020
5021 for (unsigned i = 0; i < attrib_count; ++i)
5022 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5023
5024 }
5025
5026 static void
5027 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5028 struct nir_shader *nir) {
5029 nir_foreach_variable(variable, &nir->inputs)
5030 handle_vs_input_decl(ctx, variable);
5031 }
5032
5033 static void
5034 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5035 struct nir_shader *nir)
5036 {
5037 if (!ctx->options->key.fs.multisample)
5038 return;
5039
5040 bool uses_center = false;
5041 bool uses_centroid = false;
5042 nir_foreach_variable(variable, &nir->inputs) {
5043 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5044 variable->data.sample)
5045 continue;
5046
5047 if (variable->data.centroid)
5048 uses_centroid = true;
5049 else
5050 uses_center = true;
5051 }
5052
5053 if (uses_center && uses_centroid) {
5054 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5055 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5056 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5057 }
5058 }
5059
5060 static void
5061 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5062 struct nir_shader *nir)
5063 {
5064 prepare_interp_optimize(ctx, nir);
5065
5066 nir_foreach_variable(variable, &nir->inputs)
5067 handle_fs_input_decl(ctx, variable);
5068
5069 unsigned index = 0;
5070
5071 if (ctx->shader_info->info.ps.uses_input_attachments)
5072 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5073
5074 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5075 LLVMValueRef interp_param;
5076 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5077
5078 if (!(ctx->input_mask & (1ull << i)))
5079 continue;
5080
5081 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5082 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5083 interp_param = *inputs;
5084 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5085 inputs);
5086
5087 if (!interp_param)
5088 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5089 ++index;
5090 } else if (i == VARYING_SLOT_POS) {
5091 for(int i = 0; i < 3; ++i)
5092 inputs[i] = ctx->abi.frag_pos[i];
5093
5094 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one,
5095 ctx->abi.frag_pos[3]);
5096 }
5097 }
5098 ctx->shader_info->fs.num_interp = index;
5099 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5100 ctx->shader_info->fs.has_pcoord = true;
5101 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5102 ctx->shader_info->fs.prim_id_input = true;
5103 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5104 ctx->shader_info->fs.layer_input = true;
5105 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5106 }
5107
5108 static LLVMValueRef
5109 ac_build_alloca(struct ac_llvm_context *ac,
5110 LLVMTypeRef type,
5111 const char *name)
5112 {
5113 LLVMBuilderRef builder = ac->builder;
5114 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5115 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5116 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5117 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5118 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5119 LLVMValueRef res;
5120
5121 if (first_instr) {
5122 LLVMPositionBuilderBefore(first_builder, first_instr);
5123 } else {
5124 LLVMPositionBuilderAtEnd(first_builder, first_block);
5125 }
5126
5127 res = LLVMBuildAlloca(first_builder, type, name);
5128 LLVMBuildStore(builder, LLVMConstNull(type), res);
5129
5130 LLVMDisposeBuilder(first_builder);
5131
5132 return res;
5133 }
5134
5135 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5136 LLVMTypeRef type,
5137 const char *name)
5138 {
5139 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5140 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5141 return ptr;
5142 }
5143
5144 static void
5145 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5146 struct nir_variable *variable)
5147 {
5148 int idx = variable->data.location + variable->data.index;
5149 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5150 uint64_t mask_attribs;
5151
5152 variable->data.driver_location = idx * 4;
5153
5154 /* tess ctrl has it's own load/store paths for outputs */
5155 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5156 return;
5157
5158 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5159 if (ctx->stage == MESA_SHADER_VERTEX ||
5160 ctx->stage == MESA_SHADER_TESS_EVAL ||
5161 ctx->stage == MESA_SHADER_GEOMETRY) {
5162 if (idx == VARYING_SLOT_CLIP_DIST0) {
5163 int length = ctx->num_output_clips + ctx->num_output_culls;
5164 if (ctx->stage == MESA_SHADER_VERTEX) {
5165 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5166 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5167 }
5168 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5169 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5170 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5171 }
5172
5173 if (length > 4)
5174 attrib_count = 2;
5175 else
5176 attrib_count = 1;
5177 mask_attribs = 1ull << idx;
5178 }
5179 }
5180
5181 ctx->output_mask |= mask_attribs;
5182 }
5183
5184 static void
5185 handle_shader_output_decl(struct ac_nir_context *ctx,
5186 struct nir_shader *nir,
5187 struct nir_variable *variable)
5188 {
5189 unsigned output_loc = variable->data.driver_location / 4;
5190 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5191
5192 /* tess ctrl has it's own load/store paths for outputs */
5193 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5194 return;
5195
5196 if (ctx->stage == MESA_SHADER_VERTEX ||
5197 ctx->stage == MESA_SHADER_TESS_EVAL ||
5198 ctx->stage == MESA_SHADER_GEOMETRY) {
5199 int idx = variable->data.location + variable->data.index;
5200 if (idx == VARYING_SLOT_CLIP_DIST0) {
5201 int length = nir->info.clip_distance_array_size +
5202 nir->info.cull_distance_array_size;
5203
5204 if (length > 4)
5205 attrib_count = 2;
5206 else
5207 attrib_count = 1;
5208 }
5209 }
5210
5211 for (unsigned i = 0; i < attrib_count; ++i) {
5212 for (unsigned chan = 0; chan < 4; chan++) {
5213 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5214 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5215 }
5216 }
5217 }
5218
5219 static LLVMTypeRef
5220 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5221 enum glsl_base_type type)
5222 {
5223 switch (type) {
5224 case GLSL_TYPE_INT:
5225 case GLSL_TYPE_UINT:
5226 case GLSL_TYPE_BOOL:
5227 case GLSL_TYPE_SUBROUTINE:
5228 return ctx->i32;
5229 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5230 return ctx->f32;
5231 case GLSL_TYPE_INT64:
5232 case GLSL_TYPE_UINT64:
5233 return ctx->i64;
5234 case GLSL_TYPE_DOUBLE:
5235 return ctx->f64;
5236 default:
5237 unreachable("unknown GLSL type");
5238 }
5239 }
5240
5241 static LLVMTypeRef
5242 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5243 const struct glsl_type *type)
5244 {
5245 if (glsl_type_is_scalar(type)) {
5246 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5247 }
5248
5249 if (glsl_type_is_vector(type)) {
5250 return LLVMVectorType(
5251 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5252 glsl_get_vector_elements(type));
5253 }
5254
5255 if (glsl_type_is_matrix(type)) {
5256 return LLVMArrayType(
5257 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5258 glsl_get_matrix_columns(type));
5259 }
5260
5261 if (glsl_type_is_array(type)) {
5262 return LLVMArrayType(
5263 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5264 glsl_get_length(type));
5265 }
5266
5267 assert(glsl_type_is_struct(type));
5268
5269 LLVMTypeRef member_types[glsl_get_length(type)];
5270
5271 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5272 member_types[i] =
5273 glsl_to_llvm_type(ctx,
5274 glsl_get_struct_field(type, i));
5275 }
5276
5277 return LLVMStructTypeInContext(ctx->context, member_types,
5278 glsl_get_length(type), false);
5279 }
5280
5281 static void
5282 setup_locals(struct ac_nir_context *ctx,
5283 struct nir_function *func)
5284 {
5285 int i, j;
5286 ctx->num_locals = 0;
5287 nir_foreach_variable(variable, &func->impl->locals) {
5288 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5289 variable->data.driver_location = ctx->num_locals * 4;
5290 ctx->num_locals += attrib_count;
5291 }
5292 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5293 if (!ctx->locals)
5294 return;
5295
5296 for (i = 0; i < ctx->num_locals; i++) {
5297 for (j = 0; j < 4; j++) {
5298 ctx->locals[i * 4 + j] =
5299 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5300 }
5301 }
5302 }
5303
5304 static void
5305 setup_shared(struct ac_nir_context *ctx,
5306 struct nir_shader *nir)
5307 {
5308 nir_foreach_variable(variable, &nir->shared) {
5309 LLVMValueRef shared =
5310 LLVMAddGlobalInAddressSpace(
5311 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5312 variable->name ? variable->name : "",
5313 LOCAL_ADDR_SPACE);
5314 _mesa_hash_table_insert(ctx->vars, variable, shared);
5315 }
5316 }
5317
5318 static LLVMValueRef
5319 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5320 {
5321 v = to_float(ctx, v);
5322 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5323 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5324 }
5325
5326
5327 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5328 LLVMValueRef src0, LLVMValueRef src1)
5329 {
5330 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5331 LLVMValueRef comp[2];
5332
5333 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5334 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5335 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5336 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5337 }
5338
5339 /* Initialize arguments for the shader export intrinsic */
5340 static void
5341 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5342 LLVMValueRef *values,
5343 unsigned target,
5344 struct ac_export_args *args)
5345 {
5346 /* Default is 0xf. Adjusted below depending on the format. */
5347 args->enabled_channels = 0xf;
5348
5349 /* Specify whether the EXEC mask represents the valid mask */
5350 args->valid_mask = 0;
5351
5352 /* Specify whether this is the last export */
5353 args->done = 0;
5354
5355 /* Specify the target we are exporting */
5356 args->target = target;
5357
5358 args->compr = false;
5359 args->out[0] = LLVMGetUndef(ctx->f32);
5360 args->out[1] = LLVMGetUndef(ctx->f32);
5361 args->out[2] = LLVMGetUndef(ctx->f32);
5362 args->out[3] = LLVMGetUndef(ctx->f32);
5363
5364 if (!values)
5365 return;
5366
5367 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5368 LLVMValueRef val[4];
5369 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5370 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5371 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5372 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5373
5374 switch(col_format) {
5375 case V_028714_SPI_SHADER_ZERO:
5376 args->enabled_channels = 0; /* writemask */
5377 args->target = V_008DFC_SQ_EXP_NULL;
5378 break;
5379
5380 case V_028714_SPI_SHADER_32_R:
5381 args->enabled_channels = 1;
5382 args->out[0] = values[0];
5383 break;
5384
5385 case V_028714_SPI_SHADER_32_GR:
5386 args->enabled_channels = 0x3;
5387 args->out[0] = values[0];
5388 args->out[1] = values[1];
5389 break;
5390
5391 case V_028714_SPI_SHADER_32_AR:
5392 args->enabled_channels = 0x9;
5393 args->out[0] = values[0];
5394 args->out[3] = values[3];
5395 break;
5396
5397 case V_028714_SPI_SHADER_FP16_ABGR:
5398 args->compr = 1;
5399
5400 for (unsigned chan = 0; chan < 2; chan++) {
5401 LLVMValueRef pack_args[2] = {
5402 values[2 * chan],
5403 values[2 * chan + 1]
5404 };
5405 LLVMValueRef packed;
5406
5407 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5408 args->out[chan] = packed;
5409 }
5410 break;
5411
5412 case V_028714_SPI_SHADER_UNORM16_ABGR:
5413 for (unsigned chan = 0; chan < 4; chan++) {
5414 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5415 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5416 LLVMConstReal(ctx->f32, 65535), "");
5417 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5418 LLVMConstReal(ctx->f32, 0.5), "");
5419 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5420 ctx->i32, "");
5421 }
5422
5423 args->compr = 1;
5424 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5425 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5426 break;
5427
5428 case V_028714_SPI_SHADER_SNORM16_ABGR:
5429 for (unsigned chan = 0; chan < 4; chan++) {
5430 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5431 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5432 LLVMConstReal(ctx->f32, 32767), "");
5433
5434 /* If positive, add 0.5, else add -0.5. */
5435 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5436 LLVMBuildSelect(ctx->builder,
5437 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5438 val[chan], ctx->f32zero, ""),
5439 LLVMConstReal(ctx->f32, 0.5),
5440 LLVMConstReal(ctx->f32, -0.5), ""), "");
5441 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5442 }
5443
5444 args->compr = 1;
5445 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5446 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5447 break;
5448
5449 case V_028714_SPI_SHADER_UINT16_ABGR: {
5450 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5451 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5452 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
5453
5454 for (unsigned chan = 0; chan < 4; chan++) {
5455 val[chan] = to_integer(&ctx->ac, values[chan]);
5456 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5457 }
5458
5459 args->compr = 1;
5460 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5461 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5462 break;
5463 }
5464
5465 case V_028714_SPI_SHADER_SINT16_ABGR: {
5466 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5467 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5468 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
5469 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5470 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->i32one;
5471 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
5472
5473 /* Clamp. */
5474 for (unsigned chan = 0; chan < 4; chan++) {
5475 val[chan] = to_integer(&ctx->ac, values[chan]);
5476 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5477 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5478 }
5479
5480 args->compr = 1;
5481 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5482 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5483 break;
5484 }
5485
5486 default:
5487 case V_028714_SPI_SHADER_32_ABGR:
5488 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5489 break;
5490 }
5491 } else
5492 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5493
5494 for (unsigned i = 0; i < 4; ++i)
5495 args->out[i] = to_float(&ctx->ac, args->out[i]);
5496 }
5497
5498 static void
5499 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5500 bool export_prim_id,
5501 struct ac_vs_output_info *outinfo)
5502 {
5503 uint32_t param_count = 0;
5504 unsigned target;
5505 unsigned pos_idx, num_pos_exports = 0;
5506 struct ac_export_args args, pos_args[4] = {};
5507 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5508 int i;
5509
5510 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5511 sizeof(outinfo->vs_output_param_offset));
5512
5513 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5514 LLVMValueRef slots[8];
5515 unsigned j;
5516
5517 if (outinfo->cull_dist_mask)
5518 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5519
5520 i = VARYING_SLOT_CLIP_DIST0;
5521 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5522 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5523 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5524
5525 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5526 slots[i] = LLVMGetUndef(ctx->f32);
5527
5528 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5529 target = V_008DFC_SQ_EXP_POS + 3;
5530 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5531 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5532 &args, sizeof(args));
5533 }
5534
5535 target = V_008DFC_SQ_EXP_POS + 2;
5536 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5537 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5538 &args, sizeof(args));
5539
5540 }
5541
5542 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5543 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5544 for (unsigned j = 0; j < 4; j++)
5545 pos_values[j] = LLVMBuildLoad(ctx->builder,
5546 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5547 }
5548 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5549
5550 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5551 outinfo->writes_pointsize = true;
5552 psize_value = LLVMBuildLoad(ctx->builder,
5553 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5554 }
5555
5556 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5557 outinfo->writes_layer = true;
5558 layer_value = LLVMBuildLoad(ctx->builder,
5559 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5560 }
5561
5562 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5563 outinfo->writes_viewport_index = true;
5564 viewport_index_value = LLVMBuildLoad(ctx->builder,
5565 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5566 }
5567
5568 if (outinfo->writes_pointsize ||
5569 outinfo->writes_layer ||
5570 outinfo->writes_viewport_index) {
5571 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5572 (outinfo->writes_layer == true ? 4 : 0));
5573 pos_args[1].valid_mask = 0;
5574 pos_args[1].done = 0;
5575 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5576 pos_args[1].compr = 0;
5577 pos_args[1].out[0] = ctx->f32zero; /* X */
5578 pos_args[1].out[1] = ctx->f32zero; /* Y */
5579 pos_args[1].out[2] = ctx->f32zero; /* Z */
5580 pos_args[1].out[3] = ctx->f32zero; /* W */
5581
5582 if (outinfo->writes_pointsize == true)
5583 pos_args[1].out[0] = psize_value;
5584 if (outinfo->writes_layer == true)
5585 pos_args[1].out[2] = layer_value;
5586 if (outinfo->writes_viewport_index == true) {
5587 if (ctx->options->chip_class >= GFX9) {
5588 /* GFX9 has the layer in out.z[10:0] and the viewport
5589 * index in out.z[19:16].
5590 */
5591 LLVMValueRef v = viewport_index_value;
5592 v = to_integer(&ctx->ac, v);
5593 v = LLVMBuildShl(ctx->builder, v,
5594 LLVMConstInt(ctx->i32, 16, false),
5595 "");
5596 v = LLVMBuildOr(ctx->builder, v,
5597 to_integer(&ctx->ac, pos_args[1].out[2]), "");
5598
5599 pos_args[1].out[2] = to_float(&ctx->ac, v);
5600 pos_args[1].enabled_channels |= 1 << 2;
5601 } else {
5602 pos_args[1].out[3] = viewport_index_value;
5603 pos_args[1].enabled_channels |= 1 << 3;
5604 }
5605 }
5606 }
5607 for (i = 0; i < 4; i++) {
5608 if (pos_args[i].out[0])
5609 num_pos_exports++;
5610 }
5611
5612 pos_idx = 0;
5613 for (i = 0; i < 4; i++) {
5614 if (!pos_args[i].out[0])
5615 continue;
5616
5617 /* Specify the target we are exporting */
5618 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5619 if (pos_idx == num_pos_exports)
5620 pos_args[i].done = 1;
5621 ac_build_export(&ctx->ac, &pos_args[i]);
5622 }
5623
5624 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5625 LLVMValueRef values[4];
5626 if (!(ctx->output_mask & (1ull << i)))
5627 continue;
5628
5629 for (unsigned j = 0; j < 4; j++)
5630 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5631 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5632
5633 if (i == VARYING_SLOT_LAYER) {
5634 target = V_008DFC_SQ_EXP_PARAM + param_count;
5635 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5636 param_count++;
5637 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5638 target = V_008DFC_SQ_EXP_PARAM + param_count;
5639 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5640 param_count++;
5641 } else if (i >= VARYING_SLOT_VAR0) {
5642 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5643 target = V_008DFC_SQ_EXP_PARAM + param_count;
5644 outinfo->vs_output_param_offset[i] = param_count;
5645 param_count++;
5646 } else
5647 continue;
5648
5649 si_llvm_init_export_args(ctx, values, target, &args);
5650
5651 if (target >= V_008DFC_SQ_EXP_POS &&
5652 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5653 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5654 &args, sizeof(args));
5655 } else {
5656 ac_build_export(&ctx->ac, &args);
5657 }
5658 }
5659
5660 if (export_prim_id) {
5661 LLVMValueRef values[4];
5662 target = V_008DFC_SQ_EXP_PARAM + param_count;
5663 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5664 param_count++;
5665
5666 values[0] = ctx->vs_prim_id;
5667 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5668 ctx->shader_info->vs.vgpr_comp_cnt);
5669 for (unsigned j = 1; j < 4; j++)
5670 values[j] = ctx->f32zero;
5671 si_llvm_init_export_args(ctx, values, target, &args);
5672 ac_build_export(&ctx->ac, &args);
5673 outinfo->export_prim_id = true;
5674 }
5675
5676 outinfo->pos_exports = num_pos_exports;
5677 outinfo->param_exports = param_count;
5678 }
5679
5680 static void
5681 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5682 struct ac_es_output_info *outinfo)
5683 {
5684 int j;
5685 uint64_t max_output_written = 0;
5686 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5687 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5688 int param_index;
5689 int length = 4;
5690
5691 if (!(ctx->output_mask & (1ull << i)))
5692 continue;
5693
5694 if (i == VARYING_SLOT_CLIP_DIST0)
5695 length = ctx->num_output_clips + ctx->num_output_culls;
5696
5697 param_index = shader_io_get_unique_index(i);
5698
5699 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5700
5701 for (j = 0; j < length; j++) {
5702 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5703 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5704
5705 ac_build_buffer_store_dword(&ctx->ac,
5706 ctx->esgs_ring,
5707 out_val, 1,
5708 NULL, ctx->es2gs_offset,
5709 (4 * param_index + j) * 4,
5710 1, 1, true, true);
5711 }
5712 }
5713 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5714 }
5715
5716 static void
5717 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5718 {
5719 LLVMValueRef vertex_id = ctx->rel_auto_id;
5720 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5721 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5722 vertex_dw_stride, "");
5723
5724 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5725 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5726 int length = 4;
5727
5728 if (!(ctx->output_mask & (1ull << i)))
5729 continue;
5730
5731 if (i == VARYING_SLOT_CLIP_DIST0)
5732 length = ctx->num_output_clips + ctx->num_output_culls;
5733 int param = shader_io_get_unique_index(i);
5734 mark_tess_output(ctx, false, param);
5735 if (length > 4)
5736 mark_tess_output(ctx, false, param + 1);
5737 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5738 LLVMConstInt(ctx->i32, param * 4, false),
5739 "");
5740 for (unsigned j = 0; j < length; j++) {
5741 lds_store(ctx, dw_addr,
5742 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5743 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5744 }
5745 }
5746 }
5747
5748 struct ac_build_if_state
5749 {
5750 struct nir_to_llvm_context *ctx;
5751 LLVMValueRef condition;
5752 LLVMBasicBlockRef entry_block;
5753 LLVMBasicBlockRef true_block;
5754 LLVMBasicBlockRef false_block;
5755 LLVMBasicBlockRef merge_block;
5756 };
5757
5758 static LLVMBasicBlockRef
5759 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5760 {
5761 LLVMBasicBlockRef current_block;
5762 LLVMBasicBlockRef next_block;
5763 LLVMBasicBlockRef new_block;
5764
5765 /* get current basic block */
5766 current_block = LLVMGetInsertBlock(ctx->builder);
5767
5768 /* chqeck if there's another block after this one */
5769 next_block = LLVMGetNextBasicBlock(current_block);
5770 if (next_block) {
5771 /* insert the new block before the next block */
5772 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5773 }
5774 else {
5775 /* append new block after current block */
5776 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5777 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5778 }
5779 return new_block;
5780 }
5781
5782 static void
5783 ac_nir_build_if(struct ac_build_if_state *ifthen,
5784 struct nir_to_llvm_context *ctx,
5785 LLVMValueRef condition)
5786 {
5787 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5788
5789 memset(ifthen, 0, sizeof *ifthen);
5790 ifthen->ctx = ctx;
5791 ifthen->condition = condition;
5792 ifthen->entry_block = block;
5793
5794 /* create endif/merge basic block for the phi functions */
5795 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5796
5797 /* create/insert true_block before merge_block */
5798 ifthen->true_block =
5799 LLVMInsertBasicBlockInContext(ctx->context,
5800 ifthen->merge_block,
5801 "if-true-block");
5802
5803 /* successive code goes into the true block */
5804 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5805 }
5806
5807 /**
5808 * End a conditional.
5809 */
5810 static void
5811 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5812 {
5813 LLVMBuilderRef builder = ifthen->ctx->builder;
5814
5815 /* Insert branch to the merge block from current block */
5816 LLVMBuildBr(builder, ifthen->merge_block);
5817
5818 /*
5819 * Now patch in the various branch instructions.
5820 */
5821
5822 /* Insert the conditional branch instruction at the end of entry_block */
5823 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5824 if (ifthen->false_block) {
5825 /* we have an else clause */
5826 LLVMBuildCondBr(builder, ifthen->condition,
5827 ifthen->true_block, ifthen->false_block);
5828 }
5829 else {
5830 /* no else clause */
5831 LLVMBuildCondBr(builder, ifthen->condition,
5832 ifthen->true_block, ifthen->merge_block);
5833 }
5834
5835 /* Resume building code at end of the ifthen->merge_block */
5836 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5837 }
5838
5839 static void
5840 write_tess_factors(struct nir_to_llvm_context *ctx)
5841 {
5842 unsigned stride, outer_comps, inner_comps;
5843 struct ac_build_if_state if_ctx, inner_if_ctx;
5844 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
5845 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
5846 unsigned tess_inner_index, tess_outer_index;
5847 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5848 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5849 int i;
5850 emit_barrier(ctx);
5851
5852 switch (ctx->options->key.tcs.primitive_mode) {
5853 case GL_ISOLINES:
5854 stride = 2;
5855 outer_comps = 2;
5856 inner_comps = 0;
5857 break;
5858 case GL_TRIANGLES:
5859 stride = 4;
5860 outer_comps = 3;
5861 inner_comps = 1;
5862 break;
5863 case GL_QUADS:
5864 stride = 6;
5865 outer_comps = 4;
5866 inner_comps = 2;
5867 break;
5868 default:
5869 return;
5870 }
5871
5872 ac_nir_build_if(&if_ctx, ctx,
5873 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5874 invocation_id, ctx->i32zero, ""));
5875
5876 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5877 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5878
5879 mark_tess_output(ctx, true, tess_inner_index);
5880 mark_tess_output(ctx, true, tess_outer_index);
5881 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5882 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5883 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5884 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5885 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5886
5887 for (i = 0; i < 4; i++) {
5888 inner[i] = LLVMGetUndef(ctx->i32);
5889 outer[i] = LLVMGetUndef(ctx->i32);
5890 }
5891
5892 // LINES reverseal
5893 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5894 outer[0] = out[1] = lds_load(ctx, lds_outer);
5895 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5896 LLVMConstInt(ctx->i32, 1, false), "");
5897 outer[1] = out[0] = lds_load(ctx, lds_outer);
5898 } else {
5899 for (i = 0; i < outer_comps; i++) {
5900 outer[i] = out[i] =
5901 lds_load(ctx, lds_outer);
5902 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5903 LLVMConstInt(ctx->i32, 1, false), "");
5904 }
5905 for (i = 0; i < inner_comps; i++) {
5906 inner[i] = out[outer_comps+i] =
5907 lds_load(ctx, lds_inner);
5908 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5909 LLVMConstInt(ctx->i32, 1, false), "");
5910 }
5911 }
5912
5913 /* Convert the outputs to vectors for stores. */
5914 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5915 vec1 = NULL;
5916
5917 if (stride > 4)
5918 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5919
5920
5921 buffer = ctx->hs_ring_tess_factor;
5922 tf_base = ctx->tess_factor_offset;
5923 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5924 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5925
5926 ac_nir_build_if(&inner_if_ctx, ctx,
5927 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5928 rel_patch_id, ctx->i32zero, ""));
5929
5930 /* Store the dynamic HS control word. */
5931 ac_build_buffer_store_dword(&ctx->ac, buffer,
5932 LLVMConstInt(ctx->i32, 0x80000000, false),
5933 1, ctx->i32zero, tf_base,
5934 0, 1, 0, true, false);
5935 ac_nir_build_endif(&inner_if_ctx);
5936
5937 /* Store the tessellation factors. */
5938 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5939 MIN2(stride, 4), byteoffset, tf_base,
5940 4, 1, 0, true, false);
5941 if (vec1)
5942 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5943 stride - 4, byteoffset, tf_base,
5944 20, 1, 0, true, false);
5945
5946 //TODO store to offchip for TES to read - only if TES reads them
5947 if (1) {
5948 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5949 LLVMValueRef tf_inner_offset;
5950 unsigned param_outer, param_inner;
5951
5952 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5953 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5954 LLVMConstInt(ctx->i32, param_outer, 0));
5955
5956 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5957 util_next_power_of_two(outer_comps));
5958
5959 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5960 outer_comps, tf_outer_offset,
5961 ctx->oc_lds, 0, 1, 0, true, false);
5962 if (inner_comps) {
5963 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5964 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5965 LLVMConstInt(ctx->i32, param_inner, 0));
5966
5967 inner_vec = inner_comps == 1 ? inner[0] :
5968 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5969 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5970 inner_comps, tf_inner_offset,
5971 ctx->oc_lds, 0, 1, 0, true, false);
5972 }
5973 }
5974 ac_nir_build_endif(&if_ctx);
5975 }
5976
5977 static void
5978 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5979 {
5980 write_tess_factors(ctx);
5981 }
5982
5983 static bool
5984 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5985 LLVMValueRef *color, unsigned param, bool is_last,
5986 struct ac_export_args *args)
5987 {
5988 /* Export */
5989 si_llvm_init_export_args(ctx, color, param,
5990 args);
5991
5992 if (is_last) {
5993 args->valid_mask = 1; /* whether the EXEC mask is valid */
5994 args->done = 1; /* DONE bit */
5995 } else if (!args->enabled_channels)
5996 return false; /* unnecessary NULL export */
5997
5998 return true;
5999 }
6000
6001 static void
6002 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6003 LLVMValueRef depth, LLVMValueRef stencil,
6004 LLVMValueRef samplemask)
6005 {
6006 struct ac_export_args args;
6007
6008 args.enabled_channels = 0;
6009 args.valid_mask = 1;
6010 args.done = 1;
6011 args.target = V_008DFC_SQ_EXP_MRTZ;
6012 args.compr = false;
6013
6014 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
6015 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6016 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
6017 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
6018
6019 if (depth) {
6020 args.out[0] = depth;
6021 args.enabled_channels |= 0x1;
6022 }
6023
6024 if (stencil) {
6025 args.out[1] = stencil;
6026 args.enabled_channels |= 0x2;
6027 }
6028
6029 if (samplemask) {
6030 args.out[2] = samplemask;
6031 args.enabled_channels |= 0x4;
6032 }
6033
6034 /* SI (except OLAND and HAINAN) has a bug that it only looks
6035 * at the X writemask component. */
6036 if (ctx->options->chip_class == SI &&
6037 ctx->options->family != CHIP_OLAND &&
6038 ctx->options->family != CHIP_HAINAN)
6039 args.enabled_channels |= 0x1;
6040
6041 ac_build_export(&ctx->ac, &args);
6042 }
6043
6044 static void
6045 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6046 {
6047 unsigned index = 0;
6048 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6049 struct ac_export_args color_args[8];
6050
6051 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6052 LLVMValueRef values[4];
6053
6054 if (!(ctx->output_mask & (1ull << i)))
6055 continue;
6056
6057 if (i == FRAG_RESULT_DEPTH) {
6058 ctx->shader_info->fs.writes_z = true;
6059 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6060 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6061 } else if (i == FRAG_RESULT_STENCIL) {
6062 ctx->shader_info->fs.writes_stencil = true;
6063 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6064 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6065 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6066 ctx->shader_info->fs.writes_sample_mask = true;
6067 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6068 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6069 } else {
6070 bool last = false;
6071 for (unsigned j = 0; j < 4; j++)
6072 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6073 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6074
6075 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6076 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6077
6078 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6079 if (ret)
6080 index++;
6081 }
6082 }
6083
6084 for (unsigned i = 0; i < index; i++)
6085 ac_build_export(&ctx->ac, &color_args[i]);
6086 if (depth || stencil || samplemask)
6087 si_export_mrt_z(ctx, depth, stencil, samplemask);
6088 else if (!index) {
6089 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6090 ac_build_export(&ctx->ac, &color_args[0]);
6091 }
6092
6093 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6094 }
6095
6096 static void
6097 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6098 {
6099 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6100 }
6101
6102 static void
6103 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6104 LLVMValueRef *addrs)
6105 {
6106 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6107
6108 switch (ctx->stage) {
6109 case MESA_SHADER_VERTEX:
6110 if (ctx->options->key.vs.as_ls)
6111 handle_ls_outputs_post(ctx);
6112 else if (ctx->options->key.vs.as_es)
6113 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6114 else
6115 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6116 &ctx->shader_info->vs.outinfo);
6117 break;
6118 case MESA_SHADER_FRAGMENT:
6119 handle_fs_outputs_post(ctx);
6120 break;
6121 case MESA_SHADER_GEOMETRY:
6122 emit_gs_epilogue(ctx);
6123 break;
6124 case MESA_SHADER_TESS_CTRL:
6125 handle_tcs_outputs_post(ctx);
6126 break;
6127 case MESA_SHADER_TESS_EVAL:
6128 if (ctx->options->key.tes.as_es)
6129 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6130 else
6131 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6132 &ctx->shader_info->tes.outinfo);
6133 break;
6134 default:
6135 break;
6136 }
6137 }
6138
6139 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6140 {
6141 LLVMPassManagerRef passmgr;
6142 /* Create the pass manager */
6143 passmgr = LLVMCreateFunctionPassManagerForModule(
6144 ctx->module);
6145
6146 /* This pass should eliminate all the load and store instructions */
6147 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6148
6149 /* Add some optimization passes */
6150 LLVMAddScalarReplAggregatesPass(passmgr);
6151 LLVMAddLICMPass(passmgr);
6152 LLVMAddAggressiveDCEPass(passmgr);
6153 LLVMAddCFGSimplificationPass(passmgr);
6154 LLVMAddInstructionCombiningPass(passmgr);
6155
6156 /* Run the pass */
6157 LLVMInitializeFunctionPassManager(passmgr);
6158 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6159 LLVMFinalizeFunctionPassManager(passmgr);
6160
6161 LLVMDisposeBuilder(ctx->builder);
6162 LLVMDisposePassManager(passmgr);
6163 }
6164
6165 static void
6166 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6167 {
6168 struct ac_vs_output_info *outinfo;
6169
6170 switch (ctx->stage) {
6171 case MESA_SHADER_FRAGMENT:
6172 case MESA_SHADER_COMPUTE:
6173 case MESA_SHADER_TESS_CTRL:
6174 case MESA_SHADER_GEOMETRY:
6175 return;
6176 case MESA_SHADER_VERTEX:
6177 if (ctx->options->key.vs.as_ls ||
6178 ctx->options->key.vs.as_es)
6179 return;
6180 outinfo = &ctx->shader_info->vs.outinfo;
6181 break;
6182 case MESA_SHADER_TESS_EVAL:
6183 if (ctx->options->key.vs.as_es)
6184 return;
6185 outinfo = &ctx->shader_info->tes.outinfo;
6186 break;
6187 default:
6188 unreachable("Unhandled shader type");
6189 }
6190
6191 ac_optimize_vs_outputs(&ctx->ac,
6192 ctx->main_function,
6193 outinfo->vs_output_param_offset,
6194 VARYING_SLOT_MAX,
6195 &outinfo->param_exports);
6196 }
6197
6198 static void
6199 ac_setup_rings(struct nir_to_llvm_context *ctx)
6200 {
6201 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6202 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6203 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6204 }
6205
6206 if (ctx->is_gs_copy_shader) {
6207 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6208 }
6209 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6210 LLVMValueRef tmp;
6211 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6212 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6213
6214 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6215
6216 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6217 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6218 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6219 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6220 }
6221
6222 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6223 ctx->stage == MESA_SHADER_TESS_EVAL) {
6224 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6225 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6226 }
6227 }
6228
6229 static unsigned
6230 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6231 const struct nir_shader *nir)
6232 {
6233 switch (nir->stage) {
6234 case MESA_SHADER_TESS_CTRL:
6235 return chip_class >= CIK ? 128 : 64;
6236 case MESA_SHADER_GEOMETRY:
6237 return 64;
6238 case MESA_SHADER_COMPUTE:
6239 break;
6240 default:
6241 return 0;
6242 }
6243
6244 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6245 nir->info.cs.local_size[1] *
6246 nir->info.cs.local_size[2];
6247 return max_workgroup_size;
6248 }
6249
6250 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6251 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6252 {
6253 struct ac_nir_context ctx = {};
6254 struct nir_function *func;
6255
6256 ctx.ac = *ac;
6257 ctx.abi = abi;
6258
6259 ctx.nctx = nctx;
6260 if (nctx)
6261 nctx->nir = &ctx;
6262
6263 ctx.stage = nir->stage;
6264
6265 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6266
6267 nir_foreach_variable(variable, &nir->outputs)
6268 handle_shader_output_decl(&ctx, nir, variable);
6269
6270 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6271 _mesa_key_pointer_equal);
6272 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6273 _mesa_key_pointer_equal);
6274 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6275 _mesa_key_pointer_equal);
6276
6277 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6278
6279 setup_locals(&ctx, func);
6280
6281 if (nir->stage == MESA_SHADER_COMPUTE)
6282 setup_shared(&ctx, nir);
6283
6284 visit_cf_list(&ctx, &func->impl->body);
6285 phi_post_pass(&ctx);
6286
6287 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6288 ctx.outputs);
6289
6290 free(ctx.locals);
6291 ralloc_free(ctx.defs);
6292 ralloc_free(ctx.phis);
6293 ralloc_free(ctx.vars);
6294
6295 if (nctx)
6296 nctx->nir = NULL;
6297 }
6298
6299 static
6300 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6301 struct nir_shader *nir,
6302 struct ac_shader_variant_info *shader_info,
6303 const struct ac_nir_compiler_options *options)
6304 {
6305 struct nir_to_llvm_context ctx = {0};
6306 unsigned i;
6307 ctx.options = options;
6308 ctx.shader_info = shader_info;
6309 ctx.context = LLVMContextCreate();
6310 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6311
6312 ac_llvm_context_init(&ctx.ac, ctx.context);
6313 ctx.ac.module = ctx.module;
6314
6315 memset(shader_info, 0, sizeof(*shader_info));
6316
6317 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6318
6319 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6320
6321 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6322 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6323 LLVMSetDataLayout(ctx.module, data_layout_str);
6324 LLVMDisposeTargetData(data_layout);
6325 LLVMDisposeMessage(data_layout_str);
6326
6327 setup_types(&ctx);
6328
6329 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6330 ctx.ac.builder = ctx.builder;
6331 ctx.stage = nir->stage;
6332 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6333
6334 for (i = 0; i < AC_UD_MAX_SETS; i++)
6335 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6336 for (i = 0; i < AC_UD_MAX_UD; i++)
6337 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6338
6339 create_function(&ctx);
6340
6341 if (nir->stage == MESA_SHADER_GEOMETRY) {
6342 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6343
6344 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6345 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6346 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6347 } else if (nir->stage == MESA_SHADER_VERTEX) {
6348 if (shader_info->info.vs.needs_instance_id) {
6349 ctx.shader_info->vs.vgpr_comp_cnt =
6350 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6351 }
6352 } else if (nir->stage == MESA_SHADER_FRAGMENT) {
6353 shader_info->fs.can_discard = nir->info.fs.uses_discard;
6354 }
6355
6356 ac_setup_rings(&ctx);
6357
6358 ctx.num_output_clips = nir->info.clip_distance_array_size;
6359 ctx.num_output_culls = nir->info.cull_distance_array_size;
6360
6361 if (nir->stage == MESA_SHADER_FRAGMENT)
6362 handle_fs_inputs(&ctx, nir);
6363 else if(nir->stage == MESA_SHADER_VERTEX)
6364 handle_vs_inputs(&ctx, nir);
6365
6366 ctx.abi.chip_class = options->chip_class;
6367 ctx.abi.inputs = &ctx.inputs[0];
6368 ctx.abi.emit_outputs = handle_shader_outputs_post;
6369 ctx.abi.load_ssbo = radv_load_ssbo;
6370 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6371
6372 nir_foreach_variable(variable, &nir->outputs)
6373 scan_shader_output_decl(&ctx, variable);
6374
6375 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6376
6377 LLVMBuildRetVoid(ctx.builder);
6378
6379 ac_llvm_finalize_module(&ctx);
6380
6381 ac_nir_eliminate_const_vs_outputs(&ctx);
6382
6383 if (nir->stage == MESA_SHADER_GEOMETRY) {
6384 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6385 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6386 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6387 nir->info.gs.vertices_out;
6388 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6389 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6390 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6391 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6392 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6393 }
6394
6395 return ctx.module;
6396 }
6397
6398 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6399 {
6400 unsigned *retval = (unsigned *)context;
6401 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6402 char *description = LLVMGetDiagInfoDescription(di);
6403
6404 if (severity == LLVMDSError) {
6405 *retval = 1;
6406 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6407 description);
6408 }
6409
6410 LLVMDisposeMessage(description);
6411 }
6412
6413 static unsigned ac_llvm_compile(LLVMModuleRef M,
6414 struct ac_shader_binary *binary,
6415 LLVMTargetMachineRef tm)
6416 {
6417 unsigned retval = 0;
6418 char *err;
6419 LLVMContextRef llvm_ctx;
6420 LLVMMemoryBufferRef out_buffer;
6421 unsigned buffer_size;
6422 const char *buffer_data;
6423 LLVMBool mem_err;
6424
6425 /* Setup Diagnostic Handler*/
6426 llvm_ctx = LLVMGetModuleContext(M);
6427
6428 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6429 &retval);
6430
6431 /* Compile IR*/
6432 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6433 &err, &out_buffer);
6434
6435 /* Process Errors/Warnings */
6436 if (mem_err) {
6437 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6438 free(err);
6439 retval = 1;
6440 goto out;
6441 }
6442
6443 /* Extract Shader Code*/
6444 buffer_size = LLVMGetBufferSize(out_buffer);
6445 buffer_data = LLVMGetBufferStart(out_buffer);
6446
6447 ac_elf_read(buffer_data, buffer_size, binary);
6448
6449 /* Clean up */
6450 LLVMDisposeMemoryBuffer(out_buffer);
6451
6452 out:
6453 return retval;
6454 }
6455
6456 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6457 LLVMModuleRef llvm_module,
6458 struct ac_shader_binary *binary,
6459 struct ac_shader_config *config,
6460 struct ac_shader_variant_info *shader_info,
6461 gl_shader_stage stage,
6462 bool dump_shader, bool supports_spill)
6463 {
6464 if (dump_shader)
6465 ac_dump_module(llvm_module);
6466
6467 memset(binary, 0, sizeof(*binary));
6468 int v = ac_llvm_compile(llvm_module, binary, tm);
6469 if (v) {
6470 fprintf(stderr, "compile failed\n");
6471 }
6472
6473 if (dump_shader)
6474 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6475
6476 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6477
6478 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6479 LLVMDisposeModule(llvm_module);
6480 LLVMContextDispose(ctx);
6481
6482 if (stage == MESA_SHADER_FRAGMENT) {
6483 shader_info->num_input_vgprs = 0;
6484 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6485 shader_info->num_input_vgprs += 2;
6486 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6487 shader_info->num_input_vgprs += 2;
6488 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6489 shader_info->num_input_vgprs += 2;
6490 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6491 shader_info->num_input_vgprs += 3;
6492 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6493 shader_info->num_input_vgprs += 2;
6494 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6495 shader_info->num_input_vgprs += 2;
6496 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6497 shader_info->num_input_vgprs += 2;
6498 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6499 shader_info->num_input_vgprs += 1;
6500 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6501 shader_info->num_input_vgprs += 1;
6502 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6503 shader_info->num_input_vgprs += 1;
6504 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6505 shader_info->num_input_vgprs += 1;
6506 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6507 shader_info->num_input_vgprs += 1;
6508 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6509 shader_info->num_input_vgprs += 1;
6510 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6511 shader_info->num_input_vgprs += 1;
6512 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6513 shader_info->num_input_vgprs += 1;
6514 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6515 shader_info->num_input_vgprs += 1;
6516 }
6517 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6518
6519 /* +3 for scratch wave offset and VCC */
6520 config->num_sgprs = MAX2(config->num_sgprs,
6521 shader_info->num_input_sgprs + 3);
6522 }
6523
6524 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6525 struct ac_shader_binary *binary,
6526 struct ac_shader_config *config,
6527 struct ac_shader_variant_info *shader_info,
6528 struct nir_shader *nir,
6529 const struct ac_nir_compiler_options *options,
6530 bool dump_shader)
6531 {
6532
6533 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6534 options);
6535
6536 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6537 switch (nir->stage) {
6538 case MESA_SHADER_COMPUTE:
6539 for (int i = 0; i < 3; ++i)
6540 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6541 break;
6542 case MESA_SHADER_FRAGMENT:
6543 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6544 break;
6545 case MESA_SHADER_GEOMETRY:
6546 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6547 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6548 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6549 shader_info->gs.invocations = nir->info.gs.invocations;
6550 break;
6551 case MESA_SHADER_TESS_EVAL:
6552 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6553 shader_info->tes.spacing = nir->info.tess.spacing;
6554 shader_info->tes.ccw = nir->info.tess.ccw;
6555 shader_info->tes.point_mode = nir->info.tess.point_mode;
6556 shader_info->tes.as_es = options->key.tes.as_es;
6557 break;
6558 case MESA_SHADER_TESS_CTRL:
6559 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6560 break;
6561 case MESA_SHADER_VERTEX:
6562 shader_info->vs.as_es = options->key.vs.as_es;
6563 shader_info->vs.as_ls = options->key.vs.as_ls;
6564 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6565 if (options->key.vs.as_ls)
6566 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6567 break;
6568 default:
6569 break;
6570 }
6571 }
6572
6573 static void
6574 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6575 {
6576 LLVMValueRef args[9];
6577 args[0] = ctx->gsvs_ring;
6578 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6579 args[3] = ctx->i32zero;
6580 args[4] = ctx->i32one; /* OFFEN */
6581 args[5] = ctx->i32zero; /* IDXEN */
6582 args[6] = ctx->i32one; /* GLC */
6583 args[7] = ctx->i32one; /* SLC */
6584 args[8] = ctx->i32zero; /* TFE */
6585
6586 int idx = 0;
6587
6588 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6589 int length = 4;
6590 int slot = idx;
6591 int slot_inc = 1;
6592 if (!(ctx->output_mask & (1ull << i)))
6593 continue;
6594
6595 if (i == VARYING_SLOT_CLIP_DIST0) {
6596 /* unpack clip and cull from a single set of slots */
6597 length = ctx->num_output_clips + ctx->num_output_culls;
6598 if (length > 4)
6599 slot_inc = 2;
6600 }
6601
6602 for (unsigned j = 0; j < length; j++) {
6603 LLVMValueRef value;
6604 args[2] = LLVMConstInt(ctx->i32,
6605 (slot * 4 + j) *
6606 ctx->gs_max_out_vertices * 16 * 4, false);
6607
6608 value = ac_build_intrinsic(&ctx->ac,
6609 "llvm.SI.buffer.load.dword.i32.i32",
6610 ctx->i32, args, 9,
6611 AC_FUNC_ATTR_READONLY |
6612 AC_FUNC_ATTR_LEGACY);
6613
6614 LLVMBuildStore(ctx->builder,
6615 to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6616 }
6617 idx += slot_inc;
6618 }
6619 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6620 }
6621
6622 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6623 struct nir_shader *geom_shader,
6624 struct ac_shader_binary *binary,
6625 struct ac_shader_config *config,
6626 struct ac_shader_variant_info *shader_info,
6627 const struct ac_nir_compiler_options *options,
6628 bool dump_shader)
6629 {
6630 struct nir_to_llvm_context ctx = {0};
6631 ctx.context = LLVMContextCreate();
6632 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6633 ctx.options = options;
6634 ctx.shader_info = shader_info;
6635
6636 ac_llvm_context_init(&ctx.ac, ctx.context);
6637 ctx.ac.module = ctx.module;
6638
6639 ctx.is_gs_copy_shader = true;
6640 LLVMSetTarget(ctx.module, "amdgcn--");
6641 setup_types(&ctx);
6642
6643 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6644 ctx.ac.builder = ctx.builder;
6645 ctx.stage = MESA_SHADER_VERTEX;
6646
6647 create_function(&ctx);
6648
6649 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6650 ac_setup_rings(&ctx);
6651
6652 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6653 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6654
6655 struct ac_nir_context nir_ctx = {};
6656 nir_ctx.ac = ctx.ac;
6657 nir_ctx.abi = &ctx.abi;
6658
6659 nir_ctx.nctx = &ctx;
6660 ctx.nir = &nir_ctx;
6661
6662 nir_foreach_variable(variable, &geom_shader->outputs) {
6663 scan_shader_output_decl(&ctx, variable);
6664 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6665 }
6666
6667 ac_gs_copy_shader_emit(&ctx);
6668
6669 ctx.nir = NULL;
6670
6671 LLVMBuildRetVoid(ctx.builder);
6672
6673 ac_llvm_finalize_module(&ctx);
6674
6675 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6676 MESA_SHADER_VERTEX,
6677 dump_shader, options->supports_spill);
6678 }