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radv: properly load unused gl_LocalInvocationID/gl_WorkGroupID components
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tcs_patch_id;
115 LLVMValueRef tcs_rel_ids;
116 LLVMValueRef tes_rel_patch_id;
117 LLVMValueRef tes_patch_id;
118 LLVMValueRef tes_u;
119 LLVMValueRef tes_v;
120
121 LLVMValueRef gsvs_ring_stride;
122 LLVMValueRef gsvs_num_entries;
123 LLVMValueRef gs2vs_offset;
124 LLVMValueRef gs_wave_id;
125 LLVMValueRef gs_vtx_offset[6];
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153
154 uint32_t tcs_patch_outputs_read;
155 uint64_t tcs_outputs_read;
156 };
157
158 static inline struct nir_to_llvm_context *
159 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
160 {
161 struct nir_to_llvm_context *ctx = NULL;
162 return container_of(abi, ctx, abi);
163 }
164
165 static LLVMTypeRef
166 nir2llvmtype(struct ac_nir_context *ctx,
167 const struct glsl_type *type)
168 {
169 switch (glsl_get_base_type(glsl_without_array(type))) {
170 case GLSL_TYPE_UINT:
171 case GLSL_TYPE_INT:
172 return ctx->ac.i32;
173 case GLSL_TYPE_UINT64:
174 case GLSL_TYPE_INT64:
175 return ctx->ac.i64;
176 case GLSL_TYPE_DOUBLE:
177 return ctx->ac.f64;
178 case GLSL_TYPE_FLOAT:
179 return ctx->ac.f32;
180 default:
181 assert(!"Unsupported type in nir2llvmtype()");
182 break;
183 }
184 return 0;
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 const nir_tex_instr *instr,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t user_sgpr_count;
256 uint8_t sgpr_count;
257 uint8_t num_user_sgprs_used;
258 uint8_t num_sgprs_used;
259 uint8_t num_vgprs_used;
260 };
261
262 static inline void
263 add_argument(struct arg_info *info,
264 LLVMTypeRef type, LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267 info->assign[info->count] = param_ptr;
268 info->types[info->count] = type;
269 info->count++;
270 }
271
272 static inline void
273 add_sgpr_argument(struct arg_info *info,
274 LLVMTypeRef type, LLVMValueRef *param_ptr)
275 {
276 add_argument(info, type, param_ptr);
277 info->num_sgprs_used += ac_get_type_size(type) / 4;
278 info->sgpr_count++;
279 }
280
281 static inline void
282 add_user_sgpr_argument(struct arg_info *info,
283 LLVMTypeRef type,
284 LLVMValueRef *param_ptr)
285 {
286 add_sgpr_argument(info, type, param_ptr);
287 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
288 info->user_sgpr_count++;
289 }
290
291 static inline void
292 add_vgpr_argument(struct arg_info *info,
293 LLVMTypeRef type,
294 LLVMValueRef *param_ptr)
295 {
296 add_argument(info, type, param_ptr);
297 info->num_vgprs_used += ac_get_type_size(type) / 4;
298 }
299
300 static inline void
301 add_user_sgpr_array_argument(struct arg_info *info,
302 LLVMTypeRef type,
303 LLVMValueRef *param_ptr)
304 {
305 info->array_params_mask |= (1 << info->count);
306 add_user_sgpr_argument(info, type, param_ptr);
307 }
308
309 static void assign_arguments(LLVMValueRef main_function,
310 struct arg_info *info)
311 {
312 unsigned i;
313 for (i = 0; i < info->count; i++) {
314 if (info->assign[i])
315 *info->assign[i] = LLVMGetParam(main_function, i);
316 }
317 }
318
319 static LLVMValueRef
320 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
321 LLVMBuilderRef builder, LLVMTypeRef *return_types,
322 unsigned num_return_elems,
323 struct arg_info *args,
324 unsigned max_workgroup_size,
325 bool unsafe_math)
326 {
327 LLVMTypeRef main_function_type, ret_type;
328 LLVMBasicBlockRef main_function_body;
329
330 if (num_return_elems)
331 ret_type = LLVMStructTypeInContext(ctx, return_types,
332 num_return_elems, true);
333 else
334 ret_type = LLVMVoidTypeInContext(ctx);
335
336 /* Setup the function */
337 main_function_type =
338 LLVMFunctionType(ret_type, args->types, args->count, 0);
339 LLVMValueRef main_function =
340 LLVMAddFunction(module, "main", main_function_type);
341 main_function_body =
342 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
343 LLVMPositionBuilderAtEnd(builder, main_function_body);
344
345 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
346 for (unsigned i = 0; i < args->sgpr_count; ++i) {
347 if (args->array_params_mask & (1 << i)) {
348 LLVMValueRef P = LLVMGetParam(main_function, i);
349 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
350 ac_add_attr_dereferenceable(P, UINT64_MAX);
351 }
352 else {
353 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
354 }
355 }
356
357 if (max_workgroup_size) {
358 ac_llvm_add_target_dep_function_attr(main_function,
359 "amdgpu-max-work-group-size",
360 max_workgroup_size);
361 }
362 if (unsafe_math) {
363 /* These were copied from some LLVM test. */
364 LLVMAddTargetDependentFunctionAttr(main_function,
365 "less-precise-fpmad",
366 "true");
367 LLVMAddTargetDependentFunctionAttr(main_function,
368 "no-infs-fp-math",
369 "true");
370 LLVMAddTargetDependentFunctionAttr(main_function,
371 "no-nans-fp-math",
372 "true");
373 LLVMAddTargetDependentFunctionAttr(main_function,
374 "unsafe-fp-math",
375 "true");
376 }
377 return main_function;
378 }
379
380 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
381 {
382 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
383 CONST_ADDR_SPACE);
384 }
385
386 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
387 {
388 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
389 type = LLVMGetElementType(type);
390
391 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
392 return LLVMGetIntTypeWidth(type);
393
394 if (type == ctx->f16)
395 return 16;
396 if (type == ctx->f32)
397 return 32;
398 if (type == ctx->f64)
399 return 64;
400
401 unreachable("Unhandled type kind in get_elem_bits");
402 }
403
404 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
405 LLVMValueRef param, unsigned rshift,
406 unsigned bitwidth)
407 {
408 LLVMValueRef value = param;
409 if (rshift)
410 value = LLVMBuildLShr(ctx->builder, value,
411 LLVMConstInt(ctx->i32, rshift, false), "");
412
413 if (rshift + bitwidth < 32) {
414 unsigned mask = (1 << bitwidth) - 1;
415 value = LLVMBuildAnd(ctx->builder, value,
416 LLVMConstInt(ctx->i32, mask, false), "");
417 }
418 return value;
419 }
420
421 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
422 {
423 switch (ctx->stage) {
424 case MESA_SHADER_TESS_CTRL:
425 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
426 case MESA_SHADER_TESS_EVAL:
427 return ctx->tes_rel_patch_id;
428 break;
429 default:
430 unreachable("Illegal stage");
431 }
432 }
433
434 /* Tessellation shaders pass outputs to the next shader using LDS.
435 *
436 * LS outputs = TCS inputs
437 * TCS outputs = TES inputs
438 *
439 * The LDS layout is:
440 * - TCS inputs for patch 0
441 * - TCS inputs for patch 1
442 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
443 * - ...
444 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
445 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
446 * - TCS outputs for patch 1
447 * - Per-patch TCS outputs for patch 1
448 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
449 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
450 * - ...
451 *
452 * All three shaders VS(LS), TCS, TES share the same LDS space.
453 */
454 static LLVMValueRef
455 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
456 {
457 if (ctx->stage == MESA_SHADER_VERTEX)
458 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
459 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
460 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
461 else {
462 assert(0);
463 return NULL;
464 }
465 }
466
467 static LLVMValueRef
468 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
469 {
470 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
471 }
472
473 static LLVMValueRef
474 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
475 {
476 return LLVMBuildMul(ctx->builder,
477 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
478 LLVMConstInt(ctx->ac.i32, 4, false), "");
479 }
480
481 static LLVMValueRef
482 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
483 {
484 return LLVMBuildMul(ctx->builder,
485 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
486 LLVMConstInt(ctx->ac.i32, 4, false), "");
487 }
488
489 static LLVMValueRef
490 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
491 {
492 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
493 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
494
495 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
496 }
497
498 static LLVMValueRef
499 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
500 {
501 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
502 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
503 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
504
505 return LLVMBuildAdd(ctx->builder, patch0_offset,
506 LLVMBuildMul(ctx->builder, patch_stride,
507 rel_patch_id, ""),
508 "");
509 }
510
511 static LLVMValueRef
512 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
513 {
514 LLVMValueRef patch0_patch_data_offset =
515 get_tcs_out_patch0_patch_data_offset(ctx);
516 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
517 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
518
519 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
520 LLVMBuildMul(ctx->builder, patch_stride,
521 rel_patch_id, ""),
522 "");
523 }
524
525 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
526 {
527 ud_info->sgpr_idx = *sgpr_idx;
528 ud_info->num_sgprs = num_sgprs;
529 ud_info->indirect = false;
530 ud_info->indirect_offset = 0;
531 *sgpr_idx += num_sgprs;
532 }
533
534 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
535 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
536 {
537 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
538 }
539
540
541 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
542 uint32_t indirect_offset)
543 {
544 ud_info->sgpr_idx = sgpr_idx;
545 ud_info->num_sgprs = num_sgprs;
546 ud_info->indirect = true;
547 ud_info->indirect_offset = indirect_offset;
548 }
549
550 struct user_sgpr_info {
551 bool need_ring_offsets;
552 uint8_t sgpr_count;
553 bool indirect_all_descriptor_sets;
554 };
555
556 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
557 struct user_sgpr_info *user_sgpr_info)
558 {
559 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
560
561 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
562 if (ctx->stage == MESA_SHADER_GEOMETRY ||
563 ctx->stage == MESA_SHADER_VERTEX ||
564 ctx->stage == MESA_SHADER_TESS_CTRL ||
565 ctx->stage == MESA_SHADER_TESS_EVAL ||
566 ctx->is_gs_copy_shader)
567 user_sgpr_info->need_ring_offsets = true;
568
569 if (ctx->stage == MESA_SHADER_FRAGMENT &&
570 ctx->shader_info->info.ps.needs_sample_positions)
571 user_sgpr_info->need_ring_offsets = true;
572
573 /* 2 user sgprs will nearly always be allocated for scratch/rings */
574 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
575 user_sgpr_info->sgpr_count += 2;
576 }
577
578 switch (ctx->stage) {
579 case MESA_SHADER_COMPUTE:
580 if (ctx->shader_info->info.cs.uses_grid_size)
581 user_sgpr_info->sgpr_count += 3;
582 break;
583 case MESA_SHADER_FRAGMENT:
584 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
585 break;
586 case MESA_SHADER_VERTEX:
587 if (!ctx->is_gs_copy_shader) {
588 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
589 if (ctx->shader_info->info.vs.needs_draw_id) {
590 user_sgpr_info->sgpr_count += 3;
591 } else {
592 user_sgpr_info->sgpr_count += 2;
593 }
594 }
595 if (ctx->options->key.vs.as_ls)
596 user_sgpr_info->sgpr_count++;
597 break;
598 case MESA_SHADER_TESS_CTRL:
599 user_sgpr_info->sgpr_count += 4;
600 break;
601 case MESA_SHADER_TESS_EVAL:
602 user_sgpr_info->sgpr_count += 1;
603 break;
604 case MESA_SHADER_GEOMETRY:
605 user_sgpr_info->sgpr_count += 2;
606 break;
607 default:
608 break;
609 }
610
611 if (ctx->shader_info->info.needs_push_constants)
612 user_sgpr_info->sgpr_count += 2;
613
614 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
615 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
616 user_sgpr_info->sgpr_count += 2;
617 user_sgpr_info->indirect_all_descriptor_sets = true;
618 } else {
619 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
620 }
621 }
622
623 static void
624 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
625 gl_shader_stage stage,
626 bool has_previous_stage,
627 gl_shader_stage previous_stage,
628 const struct user_sgpr_info *user_sgpr_info,
629 struct arg_info *args,
630 LLVMValueRef *desc_sets)
631 {
632 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
633 unsigned stage_mask = 1 << stage;
634 if (has_previous_stage)
635 stage_mask |= 1 << previous_stage;
636
637 /* 1 for each descriptor set */
638 if (!user_sgpr_info->indirect_all_descriptor_sets) {
639 for (unsigned i = 0; i < num_sets; ++i) {
640 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
641 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->descriptor_sets[i]);
642 }
643 }
644 } else
645 add_user_sgpr_array_argument(args, const_array(const_array(ctx->ac.i8, 1024 * 1024), 32), desc_sets);
646
647 if (ctx->shader_info->info.needs_push_constants) {
648 /* 1 for push constants and dynamic descriptors */
649 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->push_constants);
650 }
651 }
652
653 static void
654 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
655 gl_shader_stage stage,
656 bool has_previous_stage,
657 gl_shader_stage previous_stage,
658 const struct user_sgpr_info *user_sgpr_info,
659 LLVMValueRef desc_sets,
660 uint8_t *user_sgpr_idx)
661 {
662 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
663 unsigned stage_mask = 1 << stage;
664 if (has_previous_stage)
665 stage_mask |= 1 << previous_stage;
666
667 if (!user_sgpr_info->indirect_all_descriptor_sets) {
668 for (unsigned i = 0; i < num_sets; ++i) {
669 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
670 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
671 } else
672 ctx->descriptor_sets[i] = NULL;
673 }
674 } else {
675 uint32_t desc_sgpr_idx = *user_sgpr_idx;
676 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
677
678 for (unsigned i = 0; i < num_sets; ++i) {
679 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
680 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
681 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
682
683 } else
684 ctx->descriptor_sets[i] = NULL;
685 }
686 ctx->shader_info->need_indirect_descriptor_sets = true;
687 }
688
689 if (ctx->shader_info->info.needs_push_constants) {
690 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
691 }
692 }
693
694 static void
695 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
696 gl_shader_stage stage,
697 bool has_previous_stage,
698 gl_shader_stage previous_stage,
699 struct arg_info *args)
700 {
701 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
702 if (ctx->shader_info->info.vs.has_vertex_buffers)
703 add_user_sgpr_argument(args, const_array(ctx->ac.v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
704 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.base_vertex); // base vertex
705 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.start_instance);// start instance
706 if (ctx->shader_info->info.vs.needs_draw_id)
707 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.draw_id); // draw id
708 }
709 }
710
711 static void
712 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
713 gl_shader_stage stage,
714 bool has_previous_stage,
715 gl_shader_stage previous_stage,
716 uint8_t *user_sgpr_idx)
717 {
718 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
719 if (ctx->shader_info->info.vs.has_vertex_buffers) {
720 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
721 }
722 unsigned vs_num = 2;
723 if (ctx->shader_info->info.vs.needs_draw_id)
724 vs_num++;
725
726 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
727 }
728 }
729
730
731 static void create_function(struct nir_to_llvm_context *ctx,
732 gl_shader_stage stage,
733 bool has_previous_stage,
734 gl_shader_stage previous_stage)
735 {
736 uint8_t user_sgpr_idx;
737 struct user_sgpr_info user_sgpr_info;
738 struct arg_info args = {};
739 LLVMValueRef desc_sets;
740
741 allocate_user_sgprs(ctx, &user_sgpr_info);
742
743 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
744 add_user_sgpr_argument(&args, const_array(ctx->ac.v4i32, 16), &ctx->ring_offsets); /* address of rings */
745 }
746
747 switch (stage) {
748 case MESA_SHADER_COMPUTE:
749 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
750 if (ctx->shader_info->info.cs.uses_grid_size) {
751 add_user_sgpr_argument(&args, ctx->ac.v3i32,
752 &ctx->num_work_groups);
753 }
754
755 for (int i = 0; i < 3; i++) {
756 ctx->workgroup_ids[i] = NULL;
757 if (ctx->shader_info->info.cs.uses_block_id[i]) {
758 add_sgpr_argument(&args, ctx->ac.i32,
759 &ctx->workgroup_ids[i]);
760 }
761 }
762
763 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
764 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
765 add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
766 break;
767 case MESA_SHADER_VERTEX:
768 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
769 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
770 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
771 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
772 if (ctx->options->key.vs.as_es)
773 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
774 else if (ctx->options->key.vs.as_ls)
775 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
776 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
777 if (!ctx->is_gs_copy_shader) {
778 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
779 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
780 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
781 }
782 break;
783 case MESA_SHADER_TESS_CTRL:
784 if (has_previous_stage) {
785 // First 6 system regs
786 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
787 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
788 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
789
790 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
791 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
792 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
793
794 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
795 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
796 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
797
798 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
799 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
800 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
801 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
802 if (ctx->shader_info->info.needs_multiview_view_index)
803 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
804
805 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
806 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
807 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
808 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
809 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
810 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
811 } else {
812 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
813 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
814 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
815 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
816 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
817 if (ctx->shader_info->info.needs_multiview_view_index)
818 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
819 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
820 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
821 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
822 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
823 }
824 break;
825 case MESA_SHADER_TESS_EVAL:
826 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
827 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
828 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
829 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
830 if (ctx->options->key.tes.as_es) {
831 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
832 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
833 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
834 } else {
835 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
836 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
837 }
838 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
839 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
840 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
841 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
842 break;
843 case MESA_SHADER_GEOMETRY:
844 if (has_previous_stage) {
845 // First 6 system regs
846 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
847 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
848 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
849
850 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
851 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
852 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
853
854 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
855 if (previous_stage == MESA_SHADER_TESS_EVAL)
856 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
857 else
858 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
859 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
860 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
861 if (ctx->shader_info->info.needs_multiview_view_index)
862 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
863
864 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx01
865 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]); // vtx23
866 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
867 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
868 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
869
870 if (previous_stage == MESA_SHADER_VERTEX) {
871 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
872 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
873 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
874 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
875 } else {
876 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
877 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
878 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
879 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
880 }
881 } else {
882 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
883 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
884 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
885 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
886 if (ctx->shader_info->info.needs_multiview_view_index)
887 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
888 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
889 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
890 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx0
891 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[1]); // vtx1
892 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
893 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]);
894 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[3]);
895 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
896 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[5]);
897 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
898 }
899 break;
900 case MESA_SHADER_FRAGMENT:
901 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
902 if (ctx->shader_info->info.ps.needs_sample_positions)
903 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */
904 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
905 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /* persp sample */
906 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /* persp center */
907 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid); /* persp centroid */
908 add_vgpr_argument(&args, ctx->ac.v3i32, NULL); /* persp pull model */
909 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_sample); /* linear sample */
910 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_center); /* linear center */
911 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_centroid); /* linear centroid */
912 add_vgpr_argument(&args, ctx->ac.f32, NULL); /* line stipple tex */
913 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[0]); /* pos x float */
914 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[1]); /* pos y float */
915 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[2]); /* pos z float */
916 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[3]); /* pos w float */
917 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */
918 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */
919 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.sample_coverage); /* sample coverage */
920 add_vgpr_argument(&args, ctx->ac.i32, NULL); /* fixed pt */
921 break;
922 default:
923 unreachable("Shader stage not implemented");
924 }
925
926 ctx->main_function = create_llvm_function(
927 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
928 ctx->max_workgroup_size,
929 ctx->options->unsafe_math);
930 set_llvm_calling_convention(ctx->main_function, stage);
931
932
933 ctx->shader_info->num_input_vgprs = 0;
934 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
935
936 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
937
938 if (ctx->stage != MESA_SHADER_FRAGMENT)
939 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
940
941 assign_arguments(ctx->main_function, &args);
942
943 user_sgpr_idx = 0;
944
945 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
946 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
947 if (ctx->options->supports_spill) {
948 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
949 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
950 NULL, 0, AC_FUNC_ATTR_READNONE);
951 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
952 const_array(ctx->ac.v4i32, 16), "");
953 }
954 }
955
956 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
957 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
958 if (has_previous_stage)
959 user_sgpr_idx = 0;
960
961 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
962
963 switch (stage) {
964 case MESA_SHADER_COMPUTE:
965 if (ctx->shader_info->info.cs.uses_grid_size) {
966 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE,
967 &user_sgpr_idx, 3);
968 }
969 break;
970 case MESA_SHADER_VERTEX:
971 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
972 if (ctx->view_index)
973 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
974 if (ctx->options->key.vs.as_ls) {
975 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
976 }
977 if (ctx->options->key.vs.as_ls)
978 ac_declare_lds_as_pointer(&ctx->ac);
979 break;
980 case MESA_SHADER_TESS_CTRL:
981 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
982 if (has_previous_stage)
983 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
984 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
985 if (ctx->view_index)
986 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
987 ac_declare_lds_as_pointer(&ctx->ac);
988 break;
989 case MESA_SHADER_TESS_EVAL:
990 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
991 if (ctx->view_index)
992 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
993 break;
994 case MESA_SHADER_GEOMETRY:
995 if (has_previous_stage) {
996 if (previous_stage == MESA_SHADER_VERTEX)
997 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
998 else
999 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1000 }
1001 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
1002 if (ctx->view_index)
1003 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1004 if (has_previous_stage)
1005 ac_declare_lds_as_pointer(&ctx->ac);
1006 break;
1007 case MESA_SHADER_FRAGMENT:
1008 if (ctx->shader_info->info.ps.needs_sample_positions) {
1009 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
1010 }
1011 break;
1012 default:
1013 unreachable("Shader stage not implemented");
1014 }
1015
1016 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1017 }
1018
1019 static int get_llvm_num_components(LLVMValueRef value)
1020 {
1021 LLVMTypeRef type = LLVMTypeOf(value);
1022 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1023 ? LLVMGetVectorSize(type)
1024 : 1;
1025 return num_components;
1026 }
1027
1028 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1029 LLVMValueRef value,
1030 int index)
1031 {
1032 int count = get_llvm_num_components(value);
1033
1034 if (count == 1)
1035 return value;
1036
1037 return LLVMBuildExtractElement(ac->builder, value,
1038 LLVMConstInt(ac->i32, index, false), "");
1039 }
1040
1041 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1042 LLVMValueRef value, unsigned count)
1043 {
1044 unsigned num_components = get_llvm_num_components(value);
1045 if (count == num_components)
1046 return value;
1047
1048 LLVMValueRef masks[] = {
1049 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1050 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1051
1052 if (count == 1)
1053 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1054 "");
1055
1056 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1057 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1058 }
1059
1060 static void
1061 build_store_values_extended(struct ac_llvm_context *ac,
1062 LLVMValueRef *values,
1063 unsigned value_count,
1064 unsigned value_stride,
1065 LLVMValueRef vec)
1066 {
1067 LLVMBuilderRef builder = ac->builder;
1068 unsigned i;
1069
1070 for (i = 0; i < value_count; i++) {
1071 LLVMValueRef ptr = values[i * value_stride];
1072 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1073 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1074 LLVMBuildStore(builder, value, ptr);
1075 }
1076 }
1077
1078 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1079 const nir_ssa_def *def)
1080 {
1081 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1082 if (def->num_components > 1) {
1083 type = LLVMVectorType(type, def->num_components);
1084 }
1085 return type;
1086 }
1087
1088 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1089 {
1090 assert(src.is_ssa);
1091 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1092 return (LLVMValueRef)entry->data;
1093 }
1094
1095
1096 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1097 const struct nir_block *b)
1098 {
1099 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1100 return (LLVMBasicBlockRef)entry->data;
1101 }
1102
1103 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1104 nir_alu_src src,
1105 unsigned num_components)
1106 {
1107 LLVMValueRef value = get_src(ctx, src.src);
1108 bool need_swizzle = false;
1109
1110 assert(value);
1111 LLVMTypeRef type = LLVMTypeOf(value);
1112 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1113 ? LLVMGetVectorSize(type)
1114 : 1;
1115
1116 for (unsigned i = 0; i < num_components; ++i) {
1117 assert(src.swizzle[i] < src_components);
1118 if (src.swizzle[i] != i)
1119 need_swizzle = true;
1120 }
1121
1122 if (need_swizzle || num_components != src_components) {
1123 LLVMValueRef masks[] = {
1124 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1125 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1126 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1127 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1128
1129 if (src_components > 1 && num_components == 1) {
1130 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1131 masks[0], "");
1132 } else if (src_components == 1 && num_components > 1) {
1133 LLVMValueRef values[] = {value, value, value, value};
1134 value = ac_build_gather_values(&ctx->ac, values, num_components);
1135 } else {
1136 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1137 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1138 swizzle, "");
1139 }
1140 }
1141 assert(!src.negate);
1142 assert(!src.abs);
1143 return value;
1144 }
1145
1146 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1147 LLVMIntPredicate pred, LLVMValueRef src0,
1148 LLVMValueRef src1)
1149 {
1150 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1151 return LLVMBuildSelect(ctx->builder, result,
1152 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1153 ctx->i32_0, "");
1154 }
1155
1156 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1157 LLVMRealPredicate pred, LLVMValueRef src0,
1158 LLVMValueRef src1)
1159 {
1160 LLVMValueRef result;
1161 src0 = ac_to_float(ctx, src0);
1162 src1 = ac_to_float(ctx, src1);
1163 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1164 return LLVMBuildSelect(ctx->builder, result,
1165 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1166 ctx->i32_0, "");
1167 }
1168
1169 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1170 const char *intrin,
1171 LLVMTypeRef result_type,
1172 LLVMValueRef src0)
1173 {
1174 char name[64];
1175 LLVMValueRef params[] = {
1176 ac_to_float(ctx, src0),
1177 };
1178
1179 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1180 get_elem_bits(ctx, result_type));
1181 assert(length < sizeof(name));
1182 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1183 }
1184
1185 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1186 const char *intrin,
1187 LLVMTypeRef result_type,
1188 LLVMValueRef src0, LLVMValueRef src1)
1189 {
1190 char name[64];
1191 LLVMValueRef params[] = {
1192 ac_to_float(ctx, src0),
1193 ac_to_float(ctx, src1),
1194 };
1195
1196 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1197 get_elem_bits(ctx, result_type));
1198 assert(length < sizeof(name));
1199 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1200 }
1201
1202 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1203 const char *intrin,
1204 LLVMTypeRef result_type,
1205 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1206 {
1207 char name[64];
1208 LLVMValueRef params[] = {
1209 ac_to_float(ctx, src0),
1210 ac_to_float(ctx, src1),
1211 ac_to_float(ctx, src2),
1212 };
1213
1214 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1215 get_elem_bits(ctx, result_type));
1216 assert(length < sizeof(name));
1217 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1218 }
1219
1220 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1221 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1222 {
1223 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1224 ctx->i32_0, "");
1225 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1226 }
1227
1228 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1229 LLVMIntPredicate pred,
1230 LLVMValueRef src0, LLVMValueRef src1)
1231 {
1232 return LLVMBuildSelect(ctx->builder,
1233 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1234 src0,
1235 src1, "");
1236
1237 }
1238 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1239 LLVMValueRef src0)
1240 {
1241 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1242 LLVMBuildNeg(ctx->builder, src0, ""));
1243 }
1244
1245 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1246 LLVMValueRef src0)
1247 {
1248 LLVMValueRef cmp, val;
1249
1250 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1251 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1252 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1253 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1254 return val;
1255 }
1256
1257 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1258 LLVMValueRef src0)
1259 {
1260 LLVMValueRef cmp, val;
1261
1262 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1263 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1264 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1265 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1266 return val;
1267 }
1268
1269 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1270 LLVMValueRef src0)
1271 {
1272 const char *intr = "llvm.floor.f32";
1273 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1274 LLVMValueRef params[] = {
1275 fsrc0,
1276 };
1277 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1278 ctx->f32, params, 1,
1279 AC_FUNC_ATTR_READNONE);
1280 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1281 }
1282
1283 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1284 const char *intrin,
1285 LLVMValueRef src0, LLVMValueRef src1)
1286 {
1287 LLVMTypeRef ret_type;
1288 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1289 LLVMValueRef res;
1290 LLVMValueRef params[] = { src0, src1 };
1291 ret_type = LLVMStructTypeInContext(ctx->context, types,
1292 2, true);
1293
1294 res = ac_build_intrinsic(ctx, intrin, ret_type,
1295 params, 2, AC_FUNC_ATTR_READNONE);
1296
1297 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1298 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1299 return res;
1300 }
1301
1302 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1303 LLVMValueRef src0)
1304 {
1305 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1306 }
1307
1308 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1309 LLVMValueRef src0)
1310 {
1311 src0 = ac_to_float(ctx, src0);
1312 return LLVMBuildSExt(ctx->builder,
1313 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1314 ctx->i32, "");
1315 }
1316
1317 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1318 LLVMValueRef src0)
1319 {
1320 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1321 }
1322
1323 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1324 LLVMValueRef src0)
1325 {
1326 return LLVMBuildSExt(ctx->builder,
1327 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1328 ctx->i32, "");
1329 }
1330
1331 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1332 LLVMValueRef src0)
1333 {
1334 LLVMValueRef result;
1335 LLVMValueRef cond = NULL;
1336
1337 src0 = ac_to_float(&ctx->ac, src0);
1338 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1339
1340 if (ctx->options->chip_class >= VI) {
1341 LLVMValueRef args[2];
1342 /* Check if the result is a denormal - and flush to 0 if so. */
1343 args[0] = result;
1344 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1345 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1346 }
1347
1348 /* need to convert back up to f32 */
1349 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1350
1351 if (ctx->options->chip_class >= VI)
1352 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1353 else {
1354 /* for SI/CIK */
1355 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1356 * so compare the result and flush to 0 if it's smaller.
1357 */
1358 LLVMValueRef temp, cond2;
1359 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1360 ctx->ac.f32, result);
1361 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1362 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1363 temp, "");
1364 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1365 temp, ctx->ac.f32_0, "");
1366 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1367 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1368 }
1369 return result;
1370 }
1371
1372 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1373 LLVMValueRef src0, LLVMValueRef src1)
1374 {
1375 LLVMValueRef dst64, result;
1376 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1377 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1378
1379 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1380 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1381 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1382 return result;
1383 }
1384
1385 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1386 LLVMValueRef src0, LLVMValueRef src1)
1387 {
1388 LLVMValueRef dst64, result;
1389 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1390 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1391
1392 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1393 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1394 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1395 return result;
1396 }
1397
1398 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1399 bool is_signed,
1400 const LLVMValueRef srcs[3])
1401 {
1402 LLVMValueRef result;
1403 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1404
1405 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1406 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1407 return result;
1408 }
1409
1410 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1411 LLVMValueRef src0, LLVMValueRef src1,
1412 LLVMValueRef src2, LLVMValueRef src3)
1413 {
1414 LLVMValueRef bfi_args[3], result;
1415
1416 bfi_args[0] = LLVMBuildShl(ctx->builder,
1417 LLVMBuildSub(ctx->builder,
1418 LLVMBuildShl(ctx->builder,
1419 ctx->i32_1,
1420 src3, ""),
1421 ctx->i32_1, ""),
1422 src2, "");
1423 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1424 bfi_args[2] = src0;
1425
1426 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1427
1428 /* Calculate:
1429 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1430 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1431 */
1432 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1433 LLVMBuildAnd(ctx->builder, bfi_args[0],
1434 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1435
1436 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1437 return result;
1438 }
1439
1440 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1441 LLVMValueRef src0)
1442 {
1443 LLVMValueRef comp[2];
1444
1445 src0 = ac_to_float(ctx, src0);
1446 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1447 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1448
1449 return ac_build_cvt_pkrtz_f16(ctx, comp);
1450 }
1451
1452 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1453 LLVMValueRef src0)
1454 {
1455 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1456 LLVMValueRef temps[2], result, val;
1457 int i;
1458
1459 for (i = 0; i < 2; i++) {
1460 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1461 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1462 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1463 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1464 }
1465
1466 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1467 ctx->i32_0, "");
1468 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1469 ctx->i32_1, "");
1470 return result;
1471 }
1472
1473 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1474 nir_op op,
1475 LLVMValueRef src0)
1476 {
1477 unsigned mask;
1478 int idx;
1479 LLVMValueRef result;
1480
1481 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1482 mask = AC_TID_MASK_LEFT;
1483 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1484 mask = AC_TID_MASK_TOP;
1485 else
1486 mask = AC_TID_MASK_TOP_LEFT;
1487
1488 /* for DDX we want to next X pixel, DDY next Y pixel. */
1489 if (op == nir_op_fddx_fine ||
1490 op == nir_op_fddx_coarse ||
1491 op == nir_op_fddx)
1492 idx = 1;
1493 else
1494 idx = 2;
1495
1496 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1497 return result;
1498 }
1499
1500 /*
1501 * this takes an I,J coordinate pair,
1502 * and works out the X and Y derivatives.
1503 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1504 */
1505 static LLVMValueRef emit_ddxy_interp(
1506 struct ac_nir_context *ctx,
1507 LLVMValueRef interp_ij)
1508 {
1509 LLVMValueRef result[4], a;
1510 unsigned i;
1511
1512 for (i = 0; i < 2; i++) {
1513 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1514 LLVMConstInt(ctx->ac.i32, i, false), "");
1515 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1516 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1517 }
1518 return ac_build_gather_values(&ctx->ac, result, 4);
1519 }
1520
1521 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1522 {
1523 LLVMValueRef src[4], result = NULL;
1524 unsigned num_components = instr->dest.dest.ssa.num_components;
1525 unsigned src_components;
1526 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1527
1528 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1529 switch (instr->op) {
1530 case nir_op_vec2:
1531 case nir_op_vec3:
1532 case nir_op_vec4:
1533 src_components = 1;
1534 break;
1535 case nir_op_pack_half_2x16:
1536 src_components = 2;
1537 break;
1538 case nir_op_unpack_half_2x16:
1539 src_components = 1;
1540 break;
1541 default:
1542 src_components = num_components;
1543 break;
1544 }
1545 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1546 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1547
1548 switch (instr->op) {
1549 case nir_op_fmov:
1550 case nir_op_imov:
1551 result = src[0];
1552 break;
1553 case nir_op_fneg:
1554 src[0] = ac_to_float(&ctx->ac, src[0]);
1555 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1556 break;
1557 case nir_op_ineg:
1558 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1559 break;
1560 case nir_op_inot:
1561 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1562 break;
1563 case nir_op_iadd:
1564 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1565 break;
1566 case nir_op_fadd:
1567 src[0] = ac_to_float(&ctx->ac, src[0]);
1568 src[1] = ac_to_float(&ctx->ac, src[1]);
1569 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1570 break;
1571 case nir_op_fsub:
1572 src[0] = ac_to_float(&ctx->ac, src[0]);
1573 src[1] = ac_to_float(&ctx->ac, src[1]);
1574 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1575 break;
1576 case nir_op_isub:
1577 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1578 break;
1579 case nir_op_imul:
1580 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1581 break;
1582 case nir_op_imod:
1583 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1584 break;
1585 case nir_op_umod:
1586 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1587 break;
1588 case nir_op_fmod:
1589 src[0] = ac_to_float(&ctx->ac, src[0]);
1590 src[1] = ac_to_float(&ctx->ac, src[1]);
1591 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1592 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1593 ac_to_float_type(&ctx->ac, def_type), result);
1594 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1595 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1596 break;
1597 case nir_op_frem:
1598 src[0] = ac_to_float(&ctx->ac, src[0]);
1599 src[1] = ac_to_float(&ctx->ac, src[1]);
1600 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1601 break;
1602 case nir_op_irem:
1603 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1604 break;
1605 case nir_op_idiv:
1606 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1607 break;
1608 case nir_op_udiv:
1609 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1610 break;
1611 case nir_op_fmul:
1612 src[0] = ac_to_float(&ctx->ac, src[0]);
1613 src[1] = ac_to_float(&ctx->ac, src[1]);
1614 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1615 break;
1616 case nir_op_fdiv:
1617 src[0] = ac_to_float(&ctx->ac, src[0]);
1618 src[1] = ac_to_float(&ctx->ac, src[1]);
1619 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1620 break;
1621 case nir_op_frcp:
1622 src[0] = ac_to_float(&ctx->ac, src[0]);
1623 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1624 break;
1625 case nir_op_iand:
1626 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1627 break;
1628 case nir_op_ior:
1629 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1630 break;
1631 case nir_op_ixor:
1632 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1633 break;
1634 case nir_op_ishl:
1635 result = LLVMBuildShl(ctx->ac.builder, src[0],
1636 LLVMBuildZExt(ctx->ac.builder, src[1],
1637 LLVMTypeOf(src[0]), ""),
1638 "");
1639 break;
1640 case nir_op_ishr:
1641 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1642 LLVMBuildZExt(ctx->ac.builder, src[1],
1643 LLVMTypeOf(src[0]), ""),
1644 "");
1645 break;
1646 case nir_op_ushr:
1647 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1648 LLVMBuildZExt(ctx->ac.builder, src[1],
1649 LLVMTypeOf(src[0]), ""),
1650 "");
1651 break;
1652 case nir_op_ilt:
1653 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1654 break;
1655 case nir_op_ine:
1656 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1657 break;
1658 case nir_op_ieq:
1659 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1660 break;
1661 case nir_op_ige:
1662 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1663 break;
1664 case nir_op_ult:
1665 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1666 break;
1667 case nir_op_uge:
1668 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1669 break;
1670 case nir_op_feq:
1671 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1672 break;
1673 case nir_op_fne:
1674 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1675 break;
1676 case nir_op_flt:
1677 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1678 break;
1679 case nir_op_fge:
1680 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1681 break;
1682 case nir_op_fabs:
1683 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1684 ac_to_float_type(&ctx->ac, def_type), src[0]);
1685 break;
1686 case nir_op_iabs:
1687 result = emit_iabs(&ctx->ac, src[0]);
1688 break;
1689 case nir_op_imax:
1690 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1691 break;
1692 case nir_op_imin:
1693 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1694 break;
1695 case nir_op_umax:
1696 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1697 break;
1698 case nir_op_umin:
1699 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1700 break;
1701 case nir_op_isign:
1702 result = emit_isign(&ctx->ac, src[0]);
1703 break;
1704 case nir_op_fsign:
1705 src[0] = ac_to_float(&ctx->ac, src[0]);
1706 result = emit_fsign(&ctx->ac, src[0]);
1707 break;
1708 case nir_op_ffloor:
1709 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1710 ac_to_float_type(&ctx->ac, def_type), src[0]);
1711 break;
1712 case nir_op_ftrunc:
1713 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1714 ac_to_float_type(&ctx->ac, def_type), src[0]);
1715 break;
1716 case nir_op_fceil:
1717 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1718 ac_to_float_type(&ctx->ac, def_type), src[0]);
1719 break;
1720 case nir_op_fround_even:
1721 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1722 ac_to_float_type(&ctx->ac, def_type),src[0]);
1723 break;
1724 case nir_op_ffract:
1725 result = emit_ffract(&ctx->ac, src[0]);
1726 break;
1727 case nir_op_fsin:
1728 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1729 ac_to_float_type(&ctx->ac, def_type), src[0]);
1730 break;
1731 case nir_op_fcos:
1732 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1733 ac_to_float_type(&ctx->ac, def_type), src[0]);
1734 break;
1735 case nir_op_fsqrt:
1736 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1737 ac_to_float_type(&ctx->ac, def_type), src[0]);
1738 break;
1739 case nir_op_fexp2:
1740 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1741 ac_to_float_type(&ctx->ac, def_type), src[0]);
1742 break;
1743 case nir_op_flog2:
1744 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1745 ac_to_float_type(&ctx->ac, def_type), src[0]);
1746 break;
1747 case nir_op_frsq:
1748 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1749 ac_to_float_type(&ctx->ac, def_type), src[0]);
1750 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1751 break;
1752 case nir_op_fpow:
1753 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1754 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1755 break;
1756 case nir_op_fmax:
1757 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1758 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1759 if (instr->dest.dest.ssa.bit_size == 32)
1760 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1761 ac_to_float_type(&ctx->ac, def_type),
1762 result);
1763 break;
1764 case nir_op_fmin:
1765 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1766 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1767 if (instr->dest.dest.ssa.bit_size == 32)
1768 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1769 ac_to_float_type(&ctx->ac, def_type),
1770 result);
1771 break;
1772 case nir_op_ffma:
1773 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1774 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1775 break;
1776 case nir_op_ibitfield_extract:
1777 result = emit_bitfield_extract(&ctx->ac, true, src);
1778 break;
1779 case nir_op_ubitfield_extract:
1780 result = emit_bitfield_extract(&ctx->ac, false, src);
1781 break;
1782 case nir_op_bitfield_insert:
1783 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1784 break;
1785 case nir_op_bitfield_reverse:
1786 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1787 break;
1788 case nir_op_bit_count:
1789 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1790 break;
1791 case nir_op_vec2:
1792 case nir_op_vec3:
1793 case nir_op_vec4:
1794 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1795 src[i] = ac_to_integer(&ctx->ac, src[i]);
1796 result = ac_build_gather_values(&ctx->ac, src, num_components);
1797 break;
1798 case nir_op_f2i32:
1799 case nir_op_f2i64:
1800 src[0] = ac_to_float(&ctx->ac, src[0]);
1801 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1802 break;
1803 case nir_op_f2u32:
1804 case nir_op_f2u64:
1805 src[0] = ac_to_float(&ctx->ac, src[0]);
1806 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1807 break;
1808 case nir_op_i2f32:
1809 case nir_op_i2f64:
1810 src[0] = ac_to_integer(&ctx->ac, src[0]);
1811 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1812 break;
1813 case nir_op_u2f32:
1814 case nir_op_u2f64:
1815 src[0] = ac_to_integer(&ctx->ac, src[0]);
1816 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1817 break;
1818 case nir_op_f2f64:
1819 src[0] = ac_to_float(&ctx->ac, src[0]);
1820 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1821 break;
1822 case nir_op_f2f32:
1823 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1824 break;
1825 case nir_op_u2u32:
1826 case nir_op_u2u64:
1827 src[0] = ac_to_integer(&ctx->ac, src[0]);
1828 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1829 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1830 else
1831 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1832 break;
1833 case nir_op_i2i32:
1834 case nir_op_i2i64:
1835 src[0] = ac_to_integer(&ctx->ac, src[0]);
1836 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1837 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1838 else
1839 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1840 break;
1841 case nir_op_bcsel:
1842 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1843 break;
1844 case nir_op_find_lsb:
1845 src[0] = ac_to_integer(&ctx->ac, src[0]);
1846 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1847 break;
1848 case nir_op_ufind_msb:
1849 src[0] = ac_to_integer(&ctx->ac, src[0]);
1850 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1851 break;
1852 case nir_op_ifind_msb:
1853 src[0] = ac_to_integer(&ctx->ac, src[0]);
1854 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1855 break;
1856 case nir_op_uadd_carry:
1857 src[0] = ac_to_integer(&ctx->ac, src[0]);
1858 src[1] = ac_to_integer(&ctx->ac, src[1]);
1859 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1860 break;
1861 case nir_op_usub_borrow:
1862 src[0] = ac_to_integer(&ctx->ac, src[0]);
1863 src[1] = ac_to_integer(&ctx->ac, src[1]);
1864 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1865 break;
1866 case nir_op_b2f:
1867 result = emit_b2f(&ctx->ac, src[0]);
1868 break;
1869 case nir_op_f2b:
1870 result = emit_f2b(&ctx->ac, src[0]);
1871 break;
1872 case nir_op_b2i:
1873 result = emit_b2i(&ctx->ac, src[0]);
1874 break;
1875 case nir_op_i2b:
1876 src[0] = ac_to_integer(&ctx->ac, src[0]);
1877 result = emit_i2b(&ctx->ac, src[0]);
1878 break;
1879 case nir_op_fquantize2f16:
1880 result = emit_f2f16(ctx->nctx, src[0]);
1881 break;
1882 case nir_op_umul_high:
1883 src[0] = ac_to_integer(&ctx->ac, src[0]);
1884 src[1] = ac_to_integer(&ctx->ac, src[1]);
1885 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1886 break;
1887 case nir_op_imul_high:
1888 src[0] = ac_to_integer(&ctx->ac, src[0]);
1889 src[1] = ac_to_integer(&ctx->ac, src[1]);
1890 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1891 break;
1892 case nir_op_pack_half_2x16:
1893 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1894 break;
1895 case nir_op_unpack_half_2x16:
1896 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1897 break;
1898 case nir_op_fddx:
1899 case nir_op_fddy:
1900 case nir_op_fddx_fine:
1901 case nir_op_fddy_fine:
1902 case nir_op_fddx_coarse:
1903 case nir_op_fddy_coarse:
1904 result = emit_ddxy(ctx, instr->op, src[0]);
1905 break;
1906
1907 case nir_op_unpack_64_2x32_split_x: {
1908 assert(instr->src[0].src.ssa->num_components == 1);
1909 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1910 ctx->ac.v2i32,
1911 "");
1912 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1913 ctx->ac.i32_0, "");
1914 break;
1915 }
1916
1917 case nir_op_unpack_64_2x32_split_y: {
1918 assert(instr->src[0].src.ssa->num_components == 1);
1919 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1920 ctx->ac.v2i32,
1921 "");
1922 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1923 ctx->ac.i32_1, "");
1924 break;
1925 }
1926
1927 case nir_op_pack_64_2x32_split: {
1928 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1929 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1930 src[0], ctx->ac.i32_0, "");
1931 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1932 src[1], ctx->ac.i32_1, "");
1933 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1934 break;
1935 }
1936
1937 default:
1938 fprintf(stderr, "Unknown NIR alu instr: ");
1939 nir_print_instr(&instr->instr, stderr);
1940 fprintf(stderr, "\n");
1941 abort();
1942 }
1943
1944 if (result) {
1945 assert(instr->dest.dest.is_ssa);
1946 result = ac_to_integer(&ctx->ac, result);
1947 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1948 result);
1949 }
1950 }
1951
1952 static void visit_load_const(struct ac_nir_context *ctx,
1953 const nir_load_const_instr *instr)
1954 {
1955 LLVMValueRef values[4], value = NULL;
1956 LLVMTypeRef element_type =
1957 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1958
1959 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1960 switch (instr->def.bit_size) {
1961 case 32:
1962 values[i] = LLVMConstInt(element_type,
1963 instr->value.u32[i], false);
1964 break;
1965 case 64:
1966 values[i] = LLVMConstInt(element_type,
1967 instr->value.u64[i], false);
1968 break;
1969 default:
1970 fprintf(stderr,
1971 "unsupported nir load_const bit_size: %d\n",
1972 instr->def.bit_size);
1973 abort();
1974 }
1975 }
1976 if (instr->def.num_components > 1) {
1977 value = LLVMConstVector(values, instr->def.num_components);
1978 } else
1979 value = values[0];
1980
1981 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1982 }
1983
1984 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1985 LLVMTypeRef type)
1986 {
1987 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1988 return LLVMBuildBitCast(ctx->builder, ptr,
1989 LLVMPointerType(type, addr_space), "");
1990 }
1991
1992 static LLVMValueRef
1993 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1994 {
1995 LLVMValueRef size =
1996 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1997 LLVMConstInt(ctx->ac.i32, 2, false), "");
1998
1999 /* VI only */
2000 if (ctx->ac.chip_class == VI && in_elements) {
2001 /* On VI, the descriptor contains the size in bytes,
2002 * but TXQ must return the size in elements.
2003 * The stride is always non-zero for resources using TXQ.
2004 */
2005 LLVMValueRef stride =
2006 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2007 ctx->ac.i32_1, "");
2008 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2009 LLVMConstInt(ctx->ac.i32, 16, false), "");
2010 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2011 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2012
2013 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2014 }
2015 return size;
2016 }
2017
2018 /**
2019 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2020 * intrinsic names).
2021 */
2022 static void build_int_type_name(
2023 LLVMTypeRef type,
2024 char *buf, unsigned bufsize)
2025 {
2026 assert(bufsize >= 6);
2027
2028 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2029 snprintf(buf, bufsize, "v%ui32",
2030 LLVMGetVectorSize(type));
2031 else
2032 strcpy(buf, "i32");
2033 }
2034
2035 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2036 struct ac_image_args *args,
2037 const nir_tex_instr *instr)
2038 {
2039 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2040 LLVMValueRef coord = args->addr;
2041 LLVMValueRef half_texel[2];
2042 LLVMValueRef compare_cube_wa = NULL;
2043 LLVMValueRef result;
2044 int c;
2045 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2046
2047 //TODO Rect
2048 {
2049 struct ac_image_args txq_args = { 0 };
2050
2051 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2052 txq_args.opcode = ac_image_get_resinfo;
2053 txq_args.dmask = 0xf;
2054 txq_args.addr = ctx->i32_0;
2055 txq_args.resource = args->resource;
2056 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2057
2058 for (c = 0; c < 2; c++) {
2059 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2060 LLVMConstInt(ctx->i32, c, false), "");
2061 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2062 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2063 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2064 LLVMConstReal(ctx->f32, -0.5), "");
2065 }
2066 }
2067
2068 LLVMValueRef orig_coords = args->addr;
2069
2070 for (c = 0; c < 2; c++) {
2071 LLVMValueRef tmp;
2072 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2073 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2074 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2075 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2076 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2077 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2078 }
2079
2080
2081 /*
2082 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2083 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2084 * workaround by sampling using a scaled type and converting.
2085 * This is taken from amdgpu-pro shaders.
2086 */
2087 /* NOTE this produces some ugly code compared to amdgpu-pro,
2088 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2089 * and then reads them back. -pro generates two selects,
2090 * one s_cmp for the descriptor rewriting
2091 * one v_cmp for the coordinate and result changes.
2092 */
2093 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2094 LLVMValueRef tmp, tmp2;
2095
2096 /* workaround 8/8/8/8 uint/sint cube gather bug */
2097 /* first detect it then change to a scaled read and f2i */
2098 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2099 tmp2 = tmp;
2100
2101 /* extract the DATA_FORMAT */
2102 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2103 LLVMConstInt(ctx->i32, 6, false), false);
2104
2105 /* is the DATA_FORMAT == 8_8_8_8 */
2106 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2107
2108 if (stype == GLSL_TYPE_UINT)
2109 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2110 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2111 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2112 else
2113 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2114 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2115 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2116
2117 /* replace the NUM FORMAT in the descriptor */
2118 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2119 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2120
2121 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2122
2123 /* don't modify the coordinates for this case */
2124 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2125 }
2126 args->addr = coord;
2127 result = ac_build_image_opcode(ctx, args);
2128
2129 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2130 LLVMValueRef tmp, tmp2;
2131
2132 /* if the cube workaround is in place, f2i the result. */
2133 for (c = 0; c < 4; c++) {
2134 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2135 if (stype == GLSL_TYPE_UINT)
2136 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2137 else
2138 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2139 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2140 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2141 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2142 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2143 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2144 }
2145 }
2146 return result;
2147 }
2148
2149 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2150 const nir_tex_instr *instr,
2151 bool lod_is_zero,
2152 struct ac_image_args *args)
2153 {
2154 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2155 return ac_build_buffer_load_format(&ctx->ac,
2156 args->resource,
2157 args->addr,
2158 ctx->ac.i32_0,
2159 true);
2160 }
2161
2162 args->opcode = ac_image_sample;
2163 args->compare = instr->is_shadow;
2164
2165 switch (instr->op) {
2166 case nir_texop_txf:
2167 case nir_texop_txf_ms:
2168 case nir_texop_samples_identical:
2169 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2170 args->compare = false;
2171 args->offset = false;
2172 break;
2173 case nir_texop_txb:
2174 args->bias = true;
2175 break;
2176 case nir_texop_txl:
2177 if (lod_is_zero)
2178 args->level_zero = true;
2179 else
2180 args->lod = true;
2181 break;
2182 case nir_texop_txs:
2183 case nir_texop_query_levels:
2184 args->opcode = ac_image_get_resinfo;
2185 break;
2186 case nir_texop_tex:
2187 if (ctx->stage != MESA_SHADER_FRAGMENT)
2188 args->level_zero = true;
2189 break;
2190 case nir_texop_txd:
2191 args->deriv = true;
2192 break;
2193 case nir_texop_tg4:
2194 args->opcode = ac_image_gather4;
2195 args->level_zero = true;
2196 break;
2197 case nir_texop_lod:
2198 args->opcode = ac_image_get_lod;
2199 args->compare = false;
2200 args->offset = false;
2201 break;
2202 default:
2203 break;
2204 }
2205
2206 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2207 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2208 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2209 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2210 }
2211 }
2212 return ac_build_image_opcode(&ctx->ac, args);
2213 }
2214
2215 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2216 nir_intrinsic_instr *instr)
2217 {
2218 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2219 unsigned desc_set = nir_intrinsic_desc_set(instr);
2220 unsigned binding = nir_intrinsic_binding(instr);
2221 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2222 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2223 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2224 unsigned base_offset = layout->binding[binding].offset;
2225 LLVMValueRef offset, stride;
2226
2227 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2228 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2229 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2230 layout->binding[binding].dynamic_offset_offset;
2231 desc_ptr = ctx->push_constants;
2232 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2233 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2234 } else
2235 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2236
2237 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2238 index = LLVMBuildMul(ctx->builder, index, stride, "");
2239 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2240
2241 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2242 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2243 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2244
2245 return desc_ptr;
2246 }
2247
2248 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2249 nir_intrinsic_instr *instr)
2250 {
2251 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2252 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2253
2254 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2255 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2256 return result;
2257 }
2258
2259 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2260 nir_intrinsic_instr *instr)
2261 {
2262 LLVMValueRef ptr, addr;
2263
2264 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2265 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2266
2267 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2268 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2269
2270 return LLVMBuildLoad(ctx->builder, ptr, "");
2271 }
2272
2273 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2274 const nir_intrinsic_instr *instr)
2275 {
2276 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2277
2278 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2279 }
2280 static void visit_store_ssbo(struct ac_nir_context *ctx,
2281 nir_intrinsic_instr *instr)
2282 {
2283 const char *store_name;
2284 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2285 LLVMTypeRef data_type = ctx->ac.f32;
2286 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2287 int components_32bit = elem_size_mult * instr->num_components;
2288 unsigned writemask = nir_intrinsic_write_mask(instr);
2289 LLVMValueRef base_data, base_offset;
2290 LLVMValueRef params[6];
2291
2292 params[1] = ctx->abi->load_ssbo(ctx->abi,
2293 get_src(ctx, instr->src[1]), true);
2294 params[2] = ctx->ac.i32_0; /* vindex */
2295 params[4] = ctx->ac.i1false; /* glc */
2296 params[5] = ctx->ac.i1false; /* slc */
2297
2298 if (components_32bit > 1)
2299 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2300
2301 base_data = ac_to_float(&ctx->ac, src_data);
2302 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2303 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2304 data_type, "");
2305 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2306 while (writemask) {
2307 int start, count;
2308 LLVMValueRef data;
2309 LLVMValueRef offset;
2310 LLVMValueRef tmp;
2311 u_bit_scan_consecutive_range(&writemask, &start, &count);
2312
2313 /* Due to an LLVM limitation, split 3-element writes
2314 * into a 2-element and a 1-element write. */
2315 if (count == 3) {
2316 writemask |= 1 << (start + 2);
2317 count = 2;
2318 }
2319
2320 start *= elem_size_mult;
2321 count *= elem_size_mult;
2322
2323 if (count > 4) {
2324 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2325 count = 4;
2326 }
2327
2328 if (count == 4) {
2329 store_name = "llvm.amdgcn.buffer.store.v4f32";
2330 data = base_data;
2331 } else if (count == 2) {
2332 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2333 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2334 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2335 ctx->ac.i32_0, "");
2336
2337 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2338 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2339 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2340 ctx->ac.i32_1, "");
2341 store_name = "llvm.amdgcn.buffer.store.v2f32";
2342
2343 } else {
2344 assert(count == 1);
2345 if (get_llvm_num_components(base_data) > 1)
2346 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2347 LLVMConstInt(ctx->ac.i32, start, false), "");
2348 else
2349 data = base_data;
2350 store_name = "llvm.amdgcn.buffer.store.f32";
2351 }
2352
2353 offset = base_offset;
2354 if (start != 0) {
2355 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2356 }
2357 params[0] = data;
2358 params[3] = offset;
2359 ac_build_intrinsic(&ctx->ac, store_name,
2360 ctx->ac.voidt, params, 6, 0);
2361 }
2362 }
2363
2364 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2365 const nir_intrinsic_instr *instr)
2366 {
2367 const char *name;
2368 LLVMValueRef params[6];
2369 int arg_count = 0;
2370
2371 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2372 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2373 }
2374 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2375 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2376 get_src(ctx, instr->src[0]),
2377 true);
2378 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2379 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2380 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2381
2382 switch (instr->intrinsic) {
2383 case nir_intrinsic_ssbo_atomic_add:
2384 name = "llvm.amdgcn.buffer.atomic.add";
2385 break;
2386 case nir_intrinsic_ssbo_atomic_imin:
2387 name = "llvm.amdgcn.buffer.atomic.smin";
2388 break;
2389 case nir_intrinsic_ssbo_atomic_umin:
2390 name = "llvm.amdgcn.buffer.atomic.umin";
2391 break;
2392 case nir_intrinsic_ssbo_atomic_imax:
2393 name = "llvm.amdgcn.buffer.atomic.smax";
2394 break;
2395 case nir_intrinsic_ssbo_atomic_umax:
2396 name = "llvm.amdgcn.buffer.atomic.umax";
2397 break;
2398 case nir_intrinsic_ssbo_atomic_and:
2399 name = "llvm.amdgcn.buffer.atomic.and";
2400 break;
2401 case nir_intrinsic_ssbo_atomic_or:
2402 name = "llvm.amdgcn.buffer.atomic.or";
2403 break;
2404 case nir_intrinsic_ssbo_atomic_xor:
2405 name = "llvm.amdgcn.buffer.atomic.xor";
2406 break;
2407 case nir_intrinsic_ssbo_atomic_exchange:
2408 name = "llvm.amdgcn.buffer.atomic.swap";
2409 break;
2410 case nir_intrinsic_ssbo_atomic_comp_swap:
2411 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2412 break;
2413 default:
2414 abort();
2415 }
2416
2417 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2418 }
2419
2420 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2421 const nir_intrinsic_instr *instr)
2422 {
2423 LLVMValueRef results[2];
2424 int load_components;
2425 int num_components = instr->num_components;
2426 if (instr->dest.ssa.bit_size == 64)
2427 num_components *= 2;
2428
2429 for (int i = 0; i < num_components; i += load_components) {
2430 load_components = MIN2(num_components - i, 4);
2431 const char *load_name;
2432 LLVMTypeRef data_type = ctx->ac.f32;
2433 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2434 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2435
2436 if (load_components == 3)
2437 data_type = LLVMVectorType(ctx->ac.f32, 4);
2438 else if (load_components > 1)
2439 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2440
2441 if (load_components >= 3)
2442 load_name = "llvm.amdgcn.buffer.load.v4f32";
2443 else if (load_components == 2)
2444 load_name = "llvm.amdgcn.buffer.load.v2f32";
2445 else if (load_components == 1)
2446 load_name = "llvm.amdgcn.buffer.load.f32";
2447 else
2448 unreachable("unhandled number of components");
2449
2450 LLVMValueRef params[] = {
2451 ctx->abi->load_ssbo(ctx->abi,
2452 get_src(ctx, instr->src[0]),
2453 false),
2454 ctx->ac.i32_0,
2455 offset,
2456 ctx->ac.i1false,
2457 ctx->ac.i1false,
2458 };
2459
2460 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2461
2462 }
2463
2464 assume(results[0]);
2465 LLVMValueRef ret = results[0];
2466 if (num_components > 4 || num_components == 3) {
2467 LLVMValueRef masks[] = {
2468 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2469 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2470 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2471 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2472 };
2473
2474 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2475 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2476 results[num_components > 4 ? 1 : 0], swizzle, "");
2477 }
2478
2479 return LLVMBuildBitCast(ctx->ac.builder, ret,
2480 get_def_type(ctx, &instr->dest.ssa), "");
2481 }
2482
2483 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2484 const nir_intrinsic_instr *instr)
2485 {
2486 LLVMValueRef results[8], ret;
2487 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2488 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2489 int num_components = instr->num_components;
2490
2491 if (ctx->abi->load_ubo)
2492 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2493
2494 if (instr->dest.ssa.bit_size == 64)
2495 num_components *= 2;
2496
2497 for (unsigned i = 0; i < num_components; ++i) {
2498 LLVMValueRef params[] = {
2499 rsrc,
2500 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2501 offset, "")
2502 };
2503 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2504 params, 2,
2505 AC_FUNC_ATTR_READNONE |
2506 AC_FUNC_ATTR_LEGACY);
2507 }
2508
2509
2510 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2511 return LLVMBuildBitCast(ctx->ac.builder, ret,
2512 get_def_type(ctx, &instr->dest.ssa), "");
2513 }
2514
2515 static void
2516 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2517 bool vs_in, unsigned *vertex_index_out,
2518 LLVMValueRef *vertex_index_ref,
2519 unsigned *const_out, LLVMValueRef *indir_out)
2520 {
2521 unsigned const_offset = 0;
2522 nir_deref *tail = &deref->deref;
2523 LLVMValueRef offset = NULL;
2524
2525 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2526 tail = tail->child;
2527 nir_deref_array *deref_array = nir_deref_as_array(tail);
2528 if (vertex_index_out)
2529 *vertex_index_out = deref_array->base_offset;
2530
2531 if (vertex_index_ref) {
2532 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2533 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2534 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2535 }
2536 *vertex_index_ref = vtx;
2537 }
2538 }
2539
2540 if (deref->var->data.compact) {
2541 assert(tail->child->deref_type == nir_deref_type_array);
2542 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2543 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2544 /* We always lower indirect dereferences for "compact" array vars. */
2545 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2546
2547 const_offset = deref_array->base_offset;
2548 goto out;
2549 }
2550
2551 while (tail->child != NULL) {
2552 const struct glsl_type *parent_type = tail->type;
2553 tail = tail->child;
2554
2555 if (tail->deref_type == nir_deref_type_array) {
2556 nir_deref_array *deref_array = nir_deref_as_array(tail);
2557 LLVMValueRef index, stride, local_offset;
2558 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2559
2560 const_offset += size * deref_array->base_offset;
2561 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2562 continue;
2563
2564 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2565 index = get_src(ctx, deref_array->indirect);
2566 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2567 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2568
2569 if (offset)
2570 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2571 else
2572 offset = local_offset;
2573 } else if (tail->deref_type == nir_deref_type_struct) {
2574 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2575
2576 for (unsigned i = 0; i < deref_struct->index; i++) {
2577 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2578 const_offset += glsl_count_attribute_slots(ft, vs_in);
2579 }
2580 } else
2581 unreachable("unsupported deref type");
2582
2583 }
2584 out:
2585 if (const_offset && offset)
2586 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2587 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2588 "");
2589
2590 *const_out = const_offset;
2591 *indir_out = offset;
2592 }
2593
2594
2595 /* The offchip buffer layout for TCS->TES is
2596 *
2597 * - attribute 0 of patch 0 vertex 0
2598 * - attribute 0 of patch 0 vertex 1
2599 * - attribute 0 of patch 0 vertex 2
2600 * ...
2601 * - attribute 0 of patch 1 vertex 0
2602 * - attribute 0 of patch 1 vertex 1
2603 * ...
2604 * - attribute 1 of patch 0 vertex 0
2605 * - attribute 1 of patch 0 vertex 1
2606 * ...
2607 * - per patch attribute 0 of patch 0
2608 * - per patch attribute 0 of patch 1
2609 * ...
2610 *
2611 * Note that every attribute has 4 components.
2612 */
2613 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2614 LLVMValueRef vertex_index,
2615 LLVMValueRef param_index)
2616 {
2617 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2618 LLVMValueRef param_stride, constant16;
2619 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2620
2621 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2622 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2623 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2624 num_patches, "");
2625
2626 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2627 if (vertex_index) {
2628 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2629 vertices_per_patch, "");
2630
2631 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2632 vertex_index, "");
2633
2634 param_stride = total_vertices;
2635 } else {
2636 base_addr = rel_patch_id;
2637 param_stride = num_patches;
2638 }
2639
2640 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2641 LLVMBuildMul(ctx->builder, param_index,
2642 param_stride, ""), "");
2643
2644 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2645
2646 if (!vertex_index) {
2647 LLVMValueRef patch_data_offset =
2648 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2649
2650 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2651 patch_data_offset, "");
2652 }
2653 return base_addr;
2654 }
2655
2656 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2657 unsigned param,
2658 unsigned const_index,
2659 bool is_compact,
2660 LLVMValueRef vertex_index,
2661 LLVMValueRef indir_index)
2662 {
2663 LLVMValueRef param_index;
2664
2665 if (indir_index)
2666 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2667 indir_index, "");
2668 else {
2669 if (const_index && !is_compact)
2670 param += const_index;
2671 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2672 }
2673 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2674 }
2675
2676 static void
2677 mark_tess_output(struct nir_to_llvm_context *ctx,
2678 bool is_patch, uint32_t param)
2679
2680 {
2681 if (is_patch) {
2682 ctx->tess_patch_outputs_written |= (1ull << param);
2683 } else
2684 ctx->tess_outputs_written |= (1ull << param);
2685 }
2686
2687 static LLVMValueRef
2688 get_dw_address(struct nir_to_llvm_context *ctx,
2689 LLVMValueRef dw_addr,
2690 unsigned param,
2691 unsigned const_index,
2692 bool compact_const_index,
2693 LLVMValueRef vertex_index,
2694 LLVMValueRef stride,
2695 LLVMValueRef indir_index)
2696
2697 {
2698
2699 if (vertex_index) {
2700 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2701 LLVMBuildMul(ctx->builder,
2702 vertex_index,
2703 stride, ""), "");
2704 }
2705
2706 if (indir_index)
2707 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2708 LLVMBuildMul(ctx->builder, indir_index,
2709 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2710 else if (const_index && !compact_const_index)
2711 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2712 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2713
2714 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2715 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2716
2717 if (const_index && compact_const_index)
2718 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2719 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2720 return dw_addr;
2721 }
2722
2723 static LLVMValueRef
2724 load_tcs_input(struct nir_to_llvm_context *ctx,
2725 nir_intrinsic_instr *instr)
2726 {
2727 LLVMValueRef dw_addr, stride;
2728 unsigned const_index;
2729 LLVMValueRef vertex_index;
2730 LLVMValueRef indir_index;
2731 unsigned param;
2732 LLVMValueRef value[4], result;
2733 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2734 const bool is_compact = instr->variables[0]->var->data.compact;
2735 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2736 get_deref_offset(ctx->nir, instr->variables[0],
2737 false, NULL, per_vertex ? &vertex_index : NULL,
2738 &const_index, &indir_index);
2739
2740 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2741 dw_addr = get_tcs_in_current_patch_offset(ctx);
2742 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2743 indir_index);
2744
2745 unsigned comp = instr->variables[0]->var->data.location_frac;
2746 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2747 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2748 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2749 ctx->ac.i32_1, "");
2750 }
2751 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2752 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2753 return result;
2754 }
2755
2756 static LLVMValueRef
2757 load_tcs_output(struct nir_to_llvm_context *ctx,
2758 nir_intrinsic_instr *instr)
2759 {
2760 LLVMValueRef dw_addr;
2761 LLVMValueRef stride = NULL;
2762 LLVMValueRef value[4], result;
2763 LLVMValueRef vertex_index = NULL;
2764 LLVMValueRef indir_index = NULL;
2765 unsigned const_index = 0;
2766 unsigned param;
2767 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2768 const bool is_compact = instr->variables[0]->var->data.compact;
2769 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2770 get_deref_offset(ctx->nir, instr->variables[0],
2771 false, NULL, per_vertex ? &vertex_index : NULL,
2772 &const_index, &indir_index);
2773
2774 if (!instr->variables[0]->var->data.patch) {
2775 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2776 dw_addr = get_tcs_out_current_patch_offset(ctx);
2777 } else {
2778 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2779 }
2780
2781 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2782 indir_index);
2783
2784 unsigned comp = instr->variables[0]->var->data.location_frac;
2785 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2786 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2787 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2788 ctx->ac.i32_1, "");
2789 }
2790 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2791 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2792 return result;
2793 }
2794
2795 static void
2796 store_tcs_output(struct nir_to_llvm_context *ctx,
2797 nir_intrinsic_instr *instr,
2798 LLVMValueRef src,
2799 unsigned writemask)
2800 {
2801 LLVMValueRef dw_addr;
2802 LLVMValueRef stride = NULL;
2803 LLVMValueRef buf_addr = NULL;
2804 LLVMValueRef vertex_index = NULL;
2805 LLVMValueRef indir_index = NULL;
2806 unsigned const_index = 0;
2807 unsigned param;
2808 const unsigned comp = instr->variables[0]->var->data.location_frac;
2809 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2810 const bool is_compact = instr->variables[0]->var->data.compact;
2811 bool store_lds = true;
2812
2813 if (instr->variables[0]->var->data.patch) {
2814 if (!(ctx->tcs_patch_outputs_read & (1U << (instr->variables[0]->var->data.location - VARYING_SLOT_PATCH0))))
2815 store_lds = false;
2816 } else {
2817 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2818 store_lds = false;
2819 }
2820 get_deref_offset(ctx->nir, instr->variables[0],
2821 false, NULL, per_vertex ? &vertex_index : NULL,
2822 &const_index, &indir_index);
2823
2824 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2825 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2826 is_compact && const_index > 3) {
2827 const_index -= 3;
2828 param++;
2829 }
2830
2831 if (!instr->variables[0]->var->data.patch) {
2832 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2833 dw_addr = get_tcs_out_current_patch_offset(ctx);
2834 } else {
2835 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2836 }
2837
2838 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2839
2840 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2841 indir_index);
2842 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2843 vertex_index, indir_index);
2844
2845 bool is_tess_factor = false;
2846 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2847 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2848 is_tess_factor = true;
2849
2850 unsigned base = is_compact ? const_index : 0;
2851 for (unsigned chan = 0; chan < 8; chan++) {
2852 if (!(writemask & (1 << chan)))
2853 continue;
2854 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2855
2856 if (store_lds || is_tess_factor)
2857 ac_lds_store(&ctx->ac, dw_addr, value);
2858
2859 if (!is_tess_factor && writemask != 0xF)
2860 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2861 buf_addr, ctx->oc_lds,
2862 4 * (base + chan), 1, 0, true, false);
2863
2864 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2865 ctx->ac.i32_1, "");
2866 }
2867
2868 if (writemask == 0xF) {
2869 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2870 buf_addr, ctx->oc_lds,
2871 (base * 4), 1, 0, true, false);
2872 }
2873 }
2874
2875 static LLVMValueRef
2876 load_tes_input(struct nir_to_llvm_context *ctx,
2877 const nir_intrinsic_instr *instr)
2878 {
2879 LLVMValueRef buf_addr;
2880 LLVMValueRef result;
2881 LLVMValueRef vertex_index = NULL;
2882 LLVMValueRef indir_index = NULL;
2883 unsigned const_index = 0;
2884 unsigned param;
2885 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2886 const bool is_compact = instr->variables[0]->var->data.compact;
2887
2888 get_deref_offset(ctx->nir, instr->variables[0],
2889 false, NULL, per_vertex ? &vertex_index : NULL,
2890 &const_index, &indir_index);
2891 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2892 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2893 is_compact && const_index > 3) {
2894 const_index -= 3;
2895 param++;
2896 }
2897
2898 unsigned comp = instr->variables[0]->var->data.location_frac;
2899 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2900 is_compact, vertex_index, indir_index);
2901
2902 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2903 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2904
2905 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2906 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2907 result = trim_vector(&ctx->ac, result, instr->num_components);
2908 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2909 return result;
2910 }
2911
2912 static LLVMValueRef
2913 load_gs_input(struct ac_shader_abi *abi,
2914 unsigned location,
2915 unsigned driver_location,
2916 unsigned component,
2917 unsigned num_components,
2918 unsigned vertex_index,
2919 unsigned const_index,
2920 LLVMTypeRef type)
2921 {
2922 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2923 LLVMValueRef vtx_offset;
2924 LLVMValueRef args[9];
2925 unsigned param, vtx_offset_param;
2926 LLVMValueRef value[4], result;
2927
2928 vtx_offset_param = vertex_index;
2929 assert(vtx_offset_param < 6);
2930 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2931 LLVMConstInt(ctx->ac.i32, 4, false), "");
2932
2933 param = shader_io_get_unique_index(location);
2934
2935 for (unsigned i = component; i < num_components + component; i++) {
2936 if (ctx->ac.chip_class >= GFX9) {
2937 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2938 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2939 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2940 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2941 } else {
2942 args[0] = ctx->esgs_ring;
2943 args[1] = vtx_offset;
2944 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
2945 args[3] = ctx->ac.i32_0;
2946 args[4] = ctx->ac.i32_1; /* OFFEN */
2947 args[5] = ctx->ac.i32_0; /* IDXEN */
2948 args[6] = ctx->ac.i32_1; /* GLC */
2949 args[7] = ctx->ac.i32_0; /* SLC */
2950 args[8] = ctx->ac.i32_0; /* TFE */
2951
2952 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2953 ctx->ac.i32, args, 9,
2954 AC_FUNC_ATTR_READONLY |
2955 AC_FUNC_ATTR_LEGACY);
2956 }
2957 }
2958 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2959
2960 return result;
2961 }
2962
2963 static LLVMValueRef
2964 build_gep_for_deref(struct ac_nir_context *ctx,
2965 nir_deref_var *deref)
2966 {
2967 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2968 assert(entry->data);
2969 LLVMValueRef val = entry->data;
2970 nir_deref *tail = deref->deref.child;
2971 while (tail != NULL) {
2972 LLVMValueRef offset;
2973 switch (tail->deref_type) {
2974 case nir_deref_type_array: {
2975 nir_deref_array *array = nir_deref_as_array(tail);
2976 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2977 if (array->deref_array_type ==
2978 nir_deref_array_type_indirect) {
2979 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2980 get_src(ctx,
2981 array->indirect),
2982 "");
2983 }
2984 break;
2985 }
2986 case nir_deref_type_struct: {
2987 nir_deref_struct *deref_struct =
2988 nir_deref_as_struct(tail);
2989 offset = LLVMConstInt(ctx->ac.i32,
2990 deref_struct->index, 0);
2991 break;
2992 }
2993 default:
2994 unreachable("bad deref type");
2995 }
2996 val = ac_build_gep0(&ctx->ac, val, offset);
2997 tail = tail->child;
2998 }
2999 return val;
3000 }
3001
3002 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3003 nir_intrinsic_instr *instr)
3004 {
3005 LLVMValueRef values[8];
3006 int idx = instr->variables[0]->var->data.driver_location;
3007 int ve = instr->dest.ssa.num_components;
3008 unsigned comp = instr->variables[0]->var->data.location_frac;
3009 LLVMValueRef indir_index;
3010 LLVMValueRef ret;
3011 unsigned const_index;
3012 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3013 instr->variables[0]->var->data.mode == nir_var_shader_in;
3014 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3015 &const_index, &indir_index);
3016
3017 if (instr->dest.ssa.bit_size == 64)
3018 ve *= 2;
3019
3020 switch (instr->variables[0]->var->data.mode) {
3021 case nir_var_shader_in:
3022 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3023 return load_tcs_input(ctx->nctx, instr);
3024 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3025 return load_tes_input(ctx->nctx, instr);
3026 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3027 LLVMValueRef indir_index;
3028 unsigned const_index, vertex_index;
3029 get_deref_offset(ctx, instr->variables[0],
3030 false, &vertex_index, NULL,
3031 &const_index, &indir_index);
3032 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3033 instr->variables[0]->var->data.driver_location,
3034 instr->variables[0]->var->data.location_frac, ve,
3035 vertex_index, const_index,
3036 nir2llvmtype(ctx, instr->variables[0]->var->type));
3037 }
3038
3039 for (unsigned chan = comp; chan < ve + comp; chan++) {
3040 if (indir_index) {
3041 unsigned count = glsl_count_attribute_slots(
3042 instr->variables[0]->var->type,
3043 ctx->stage == MESA_SHADER_VERTEX);
3044 count -= chan / 4;
3045 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3046 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3047 4, false, true);
3048
3049 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3050 tmp_vec,
3051 indir_index, "");
3052 } else
3053 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3054 }
3055 break;
3056 case nir_var_local:
3057 for (unsigned chan = 0; chan < ve; chan++) {
3058 if (indir_index) {
3059 unsigned count = glsl_count_attribute_slots(
3060 instr->variables[0]->var->type, false);
3061 count -= chan / 4;
3062 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3063 &ctx->ac, ctx->locals + idx + chan, count,
3064 4, true, true);
3065
3066 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3067 tmp_vec,
3068 indir_index, "");
3069 } else {
3070 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3071 }
3072 }
3073 break;
3074 case nir_var_shared: {
3075 LLVMValueRef address = build_gep_for_deref(ctx,
3076 instr->variables[0]);
3077 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3078 return LLVMBuildBitCast(ctx->ac.builder, val,
3079 get_def_type(ctx, &instr->dest.ssa),
3080 "");
3081 }
3082 case nir_var_shader_out:
3083 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3084 return load_tcs_output(ctx->nctx, instr);
3085
3086 for (unsigned chan = comp; chan < ve + comp; chan++) {
3087 if (indir_index) {
3088 unsigned count = glsl_count_attribute_slots(
3089 instr->variables[0]->var->type, false);
3090 count -= chan / 4;
3091 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3092 &ctx->ac, ctx->outputs + idx + chan, count,
3093 4, true, true);
3094
3095 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3096 tmp_vec,
3097 indir_index, "");
3098 } else {
3099 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3100 ctx->outputs[idx + chan + const_index * 4],
3101 "");
3102 }
3103 }
3104 break;
3105 default:
3106 unreachable("unhandle variable mode");
3107 }
3108 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3109 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3110 }
3111
3112 static void
3113 visit_store_var(struct ac_nir_context *ctx,
3114 nir_intrinsic_instr *instr)
3115 {
3116 LLVMValueRef temp_ptr, value;
3117 int idx = instr->variables[0]->var->data.driver_location;
3118 unsigned comp = instr->variables[0]->var->data.location_frac;
3119 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3120 int writemask = instr->const_index[0] << comp;
3121 LLVMValueRef indir_index;
3122 unsigned const_index;
3123 get_deref_offset(ctx, instr->variables[0], false,
3124 NULL, NULL, &const_index, &indir_index);
3125
3126 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3127 int old_writemask = writemask;
3128
3129 src = LLVMBuildBitCast(ctx->ac.builder, src,
3130 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3131 "");
3132
3133 writemask = 0;
3134 for (unsigned chan = 0; chan < 4; chan++) {
3135 if (old_writemask & (1 << chan))
3136 writemask |= 3u << (2 * chan);
3137 }
3138 }
3139
3140 switch (instr->variables[0]->var->data.mode) {
3141 case nir_var_shader_out:
3142
3143 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3144 store_tcs_output(ctx->nctx, instr, src, writemask);
3145 return;
3146 }
3147
3148 for (unsigned chan = 0; chan < 8; chan++) {
3149 int stride = 4;
3150 if (!(writemask & (1 << chan)))
3151 continue;
3152
3153 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3154
3155 if (instr->variables[0]->var->data.compact)
3156 stride = 1;
3157 if (indir_index) {
3158 unsigned count = glsl_count_attribute_slots(
3159 instr->variables[0]->var->type, false);
3160 count -= chan / 4;
3161 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3162 &ctx->ac, ctx->outputs + idx + chan, count,
3163 stride, true, true);
3164
3165 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3166 value, indir_index, "");
3167 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3168 count, stride, tmp_vec);
3169
3170 } else {
3171 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3172
3173 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3174 }
3175 }
3176 break;
3177 case nir_var_local:
3178 for (unsigned chan = 0; chan < 8; chan++) {
3179 if (!(writemask & (1 << chan)))
3180 continue;
3181
3182 value = llvm_extract_elem(&ctx->ac, src, chan);
3183 if (indir_index) {
3184 unsigned count = glsl_count_attribute_slots(
3185 instr->variables[0]->var->type, false);
3186 count -= chan / 4;
3187 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3188 &ctx->ac, ctx->locals + idx + chan, count,
3189 4, true, true);
3190
3191 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3192 value, indir_index, "");
3193 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3194 count, 4, tmp_vec);
3195 } else {
3196 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3197
3198 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3199 }
3200 }
3201 break;
3202 case nir_var_shared: {
3203 int writemask = instr->const_index[0];
3204 LLVMValueRef address = build_gep_for_deref(ctx,
3205 instr->variables[0]);
3206 LLVMValueRef val = get_src(ctx, instr->src[0]);
3207 unsigned components =
3208 glsl_get_vector_elements(
3209 nir_deref_tail(&instr->variables[0]->deref)->type);
3210 if (writemask == (1 << components) - 1) {
3211 val = LLVMBuildBitCast(
3212 ctx->ac.builder, val,
3213 LLVMGetElementType(LLVMTypeOf(address)), "");
3214 LLVMBuildStore(ctx->ac.builder, val, address);
3215 } else {
3216 for (unsigned chan = 0; chan < 4; chan++) {
3217 if (!(writemask & (1 << chan)))
3218 continue;
3219 LLVMValueRef ptr =
3220 LLVMBuildStructGEP(ctx->ac.builder,
3221 address, chan, "");
3222 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3223 chan);
3224 src = LLVMBuildBitCast(
3225 ctx->ac.builder, src,
3226 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3227 LLVMBuildStore(ctx->ac.builder, src, ptr);
3228 }
3229 }
3230 break;
3231 }
3232 default:
3233 break;
3234 }
3235 }
3236
3237 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3238 {
3239 switch (dim) {
3240 case GLSL_SAMPLER_DIM_BUF:
3241 return 1;
3242 case GLSL_SAMPLER_DIM_1D:
3243 return array ? 2 : 1;
3244 case GLSL_SAMPLER_DIM_2D:
3245 return array ? 3 : 2;
3246 case GLSL_SAMPLER_DIM_MS:
3247 return array ? 4 : 3;
3248 case GLSL_SAMPLER_DIM_3D:
3249 case GLSL_SAMPLER_DIM_CUBE:
3250 return 3;
3251 case GLSL_SAMPLER_DIM_RECT:
3252 case GLSL_SAMPLER_DIM_SUBPASS:
3253 return 2;
3254 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3255 return 3;
3256 default:
3257 break;
3258 }
3259 return 0;
3260 }
3261
3262
3263
3264 /* Adjust the sample index according to FMASK.
3265 *
3266 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3267 * which is the identity mapping. Each nibble says which physical sample
3268 * should be fetched to get that sample.
3269 *
3270 * For example, 0x11111100 means there are only 2 samples stored and
3271 * the second sample covers 3/4 of the pixel. When reading samples 0
3272 * and 1, return physical sample 0 (determined by the first two 0s
3273 * in FMASK), otherwise return physical sample 1.
3274 *
3275 * The sample index should be adjusted as follows:
3276 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3277 */
3278 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3279 LLVMValueRef coord_x, LLVMValueRef coord_y,
3280 LLVMValueRef coord_z,
3281 LLVMValueRef sample_index,
3282 LLVMValueRef fmask_desc_ptr)
3283 {
3284 LLVMValueRef fmask_load_address[4];
3285 LLVMValueRef res;
3286
3287 fmask_load_address[0] = coord_x;
3288 fmask_load_address[1] = coord_y;
3289 if (coord_z) {
3290 fmask_load_address[2] = coord_z;
3291 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3292 }
3293
3294 struct ac_image_args args = {0};
3295
3296 args.opcode = ac_image_load;
3297 args.da = coord_z ? true : false;
3298 args.resource = fmask_desc_ptr;
3299 args.dmask = 0xf;
3300 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3301
3302 res = ac_build_image_opcode(ctx, &args);
3303
3304 res = ac_to_integer(ctx, res);
3305 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3306 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3307
3308 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3309 res,
3310 ctx->i32_0, "");
3311
3312 LLVMValueRef sample_index4 =
3313 LLVMBuildMul(ctx->builder, sample_index, four, "");
3314 LLVMValueRef shifted_fmask =
3315 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3316 LLVMValueRef final_sample =
3317 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3318
3319 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3320 * resource descriptor is 0 (invalid),
3321 */
3322 LLVMValueRef fmask_desc =
3323 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3324 ctx->v8i32, "");
3325
3326 LLVMValueRef fmask_word1 =
3327 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3328 ctx->i32_1, "");
3329
3330 LLVMValueRef word1_is_nonzero =
3331 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3332 fmask_word1, ctx->i32_0, "");
3333
3334 /* Replace the MSAA sample index. */
3335 sample_index =
3336 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3337 final_sample, sample_index, "");
3338 return sample_index;
3339 }
3340
3341 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3342 const nir_intrinsic_instr *instr)
3343 {
3344 const struct glsl_type *type = instr->variables[0]->var->type;
3345 if(instr->variables[0]->deref.child)
3346 type = instr->variables[0]->deref.child->type;
3347
3348 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3349 LLVMValueRef coords[4];
3350 LLVMValueRef masks[] = {
3351 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3352 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3353 };
3354 LLVMValueRef res;
3355 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3356
3357 int count;
3358 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3359 bool is_array = glsl_sampler_type_is_array(type);
3360 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3361 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3362 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3363 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3364 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3365 count = image_type_to_components_count(dim, is_array);
3366
3367 if (is_ms) {
3368 LLVMValueRef fmask_load_address[3];
3369 int chan;
3370
3371 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3372 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3373 if (is_array)
3374 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3375 else
3376 fmask_load_address[2] = NULL;
3377 if (add_frag_pos) {
3378 for (chan = 0; chan < 2; ++chan)
3379 fmask_load_address[chan] =
3380 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3381 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3382 ctx->ac.i32, ""), "");
3383 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3384 }
3385 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3386 fmask_load_address[0],
3387 fmask_load_address[1],
3388 fmask_load_address[2],
3389 sample_index,
3390 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3391 }
3392 if (count == 1 && !gfx9_1d) {
3393 if (instr->src[0].ssa->num_components)
3394 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3395 else
3396 res = src0;
3397 } else {
3398 int chan;
3399 if (is_ms)
3400 count--;
3401 for (chan = 0; chan < count; ++chan) {
3402 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3403 }
3404 if (add_frag_pos) {
3405 for (chan = 0; chan < 2; ++chan)
3406 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3407 ctx->ac.i32, ""), "");
3408 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3409 count++;
3410 }
3411
3412 if (gfx9_1d) {
3413 if (is_array) {
3414 coords[2] = coords[1];
3415 coords[1] = ctx->ac.i32_0;
3416 } else
3417 coords[1] = ctx->ac.i32_0;
3418 count++;
3419 }
3420
3421 if (is_ms) {
3422 coords[count] = sample_index;
3423 count++;
3424 }
3425
3426 if (count == 3) {
3427 coords[3] = LLVMGetUndef(ctx->ac.i32);
3428 count = 4;
3429 }
3430 res = ac_build_gather_values(&ctx->ac, coords, count);
3431 }
3432 return res;
3433 }
3434
3435 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3436 const nir_intrinsic_instr *instr)
3437 {
3438 LLVMValueRef params[7];
3439 LLVMValueRef res;
3440 char intrinsic_name[64];
3441 const nir_variable *var = instr->variables[0]->var;
3442 const struct glsl_type *type = var->type;
3443
3444 if(instr->variables[0]->deref.child)
3445 type = instr->variables[0]->deref.child->type;
3446
3447 type = glsl_without_array(type);
3448 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3449 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3450 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3451 ctx->ac.i32_0, ""); /* vindex */
3452 params[2] = ctx->ac.i32_0; /* voffset */
3453 params[3] = ctx->ac.i1false; /* glc */
3454 params[4] = ctx->ac.i1false; /* slc */
3455 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3456 params, 5, 0);
3457
3458 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3459 res = ac_to_integer(&ctx->ac, res);
3460 } else {
3461 bool is_da = glsl_sampler_type_is_array(type) ||
3462 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3463 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3464 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3465 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3466 LLVMValueRef glc = ctx->ac.i1false;
3467 LLVMValueRef slc = ctx->ac.i1false;
3468
3469 params[0] = get_image_coords(ctx, instr);
3470 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3471 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3472 if (HAVE_LLVM <= 0x0309) {
3473 params[3] = ctx->ac.i1false; /* r128 */
3474 params[4] = da;
3475 params[5] = glc;
3476 params[6] = slc;
3477 } else {
3478 LLVMValueRef lwe = ctx->ac.i1false;
3479 params[3] = glc;
3480 params[4] = slc;
3481 params[5] = lwe;
3482 params[6] = da;
3483 }
3484
3485 ac_get_image_intr_name("llvm.amdgcn.image.load",
3486 ctx->ac.v4f32, /* vdata */
3487 LLVMTypeOf(params[0]), /* coords */
3488 LLVMTypeOf(params[1]), /* rsrc */
3489 intrinsic_name, sizeof(intrinsic_name));
3490
3491 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3492 params, 7, AC_FUNC_ATTR_READONLY);
3493 }
3494 return ac_to_integer(&ctx->ac, res);
3495 }
3496
3497 static void visit_image_store(struct ac_nir_context *ctx,
3498 nir_intrinsic_instr *instr)
3499 {
3500 LLVMValueRef params[8];
3501 char intrinsic_name[64];
3502 const nir_variable *var = instr->variables[0]->var;
3503 const struct glsl_type *type = glsl_without_array(var->type);
3504 LLVMValueRef glc = ctx->ac.i1false;
3505 bool force_glc = ctx->ac.chip_class == SI;
3506 if (force_glc)
3507 glc = ctx->ac.i1true;
3508
3509 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3510 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3511 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3512 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3513 ctx->ac.i32_0, ""); /* vindex */
3514 params[3] = ctx->ac.i32_0; /* voffset */
3515 params[4] = glc; /* glc */
3516 params[5] = ctx->ac.i1false; /* slc */
3517 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3518 params, 6, 0);
3519 } else {
3520 bool is_da = glsl_sampler_type_is_array(type) ||
3521 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3522 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3523 LLVMValueRef slc = ctx->ac.i1false;
3524
3525 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3526 params[1] = get_image_coords(ctx, instr); /* coords */
3527 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3528 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3529 if (HAVE_LLVM <= 0x0309) {
3530 params[4] = ctx->ac.i1false; /* r128 */
3531 params[5] = da;
3532 params[6] = glc;
3533 params[7] = slc;
3534 } else {
3535 LLVMValueRef lwe = ctx->ac.i1false;
3536 params[4] = glc;
3537 params[5] = slc;
3538 params[6] = lwe;
3539 params[7] = da;
3540 }
3541
3542 ac_get_image_intr_name("llvm.amdgcn.image.store",
3543 LLVMTypeOf(params[0]), /* vdata */
3544 LLVMTypeOf(params[1]), /* coords */
3545 LLVMTypeOf(params[2]), /* rsrc */
3546 intrinsic_name, sizeof(intrinsic_name));
3547
3548 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3549 params, 8, 0);
3550 }
3551
3552 }
3553
3554 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3555 const nir_intrinsic_instr *instr)
3556 {
3557 LLVMValueRef params[7];
3558 int param_count = 0;
3559 const nir_variable *var = instr->variables[0]->var;
3560
3561 const char *atomic_name;
3562 char intrinsic_name[41];
3563 const struct glsl_type *type = glsl_without_array(var->type);
3564 MAYBE_UNUSED int length;
3565
3566 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3567
3568 switch (instr->intrinsic) {
3569 case nir_intrinsic_image_atomic_add:
3570 atomic_name = "add";
3571 break;
3572 case nir_intrinsic_image_atomic_min:
3573 atomic_name = is_unsigned ? "umin" : "smin";
3574 break;
3575 case nir_intrinsic_image_atomic_max:
3576 atomic_name = is_unsigned ? "umax" : "smax";
3577 break;
3578 case nir_intrinsic_image_atomic_and:
3579 atomic_name = "and";
3580 break;
3581 case nir_intrinsic_image_atomic_or:
3582 atomic_name = "or";
3583 break;
3584 case nir_intrinsic_image_atomic_xor:
3585 atomic_name = "xor";
3586 break;
3587 case nir_intrinsic_image_atomic_exchange:
3588 atomic_name = "swap";
3589 break;
3590 case nir_intrinsic_image_atomic_comp_swap:
3591 atomic_name = "cmpswap";
3592 break;
3593 default:
3594 abort();
3595 }
3596
3597 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3598 params[param_count++] = get_src(ctx, instr->src[3]);
3599 params[param_count++] = get_src(ctx, instr->src[2]);
3600
3601 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3602 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3603 NULL, true, true);
3604 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3605 ctx->ac.i32_0, ""); /* vindex */
3606 params[param_count++] = ctx->ac.i32_0; /* voffset */
3607 params[param_count++] = ctx->ac.i1false; /* slc */
3608
3609 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3610 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3611 } else {
3612 char coords_type[8];
3613
3614 bool da = glsl_sampler_type_is_array(type) ||
3615 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3616
3617 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3618 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3619 NULL, true, true);
3620 params[param_count++] = ctx->ac.i1false; /* r128 */
3621 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3622 params[param_count++] = ctx->ac.i1false; /* slc */
3623
3624 build_int_type_name(LLVMTypeOf(coords),
3625 coords_type, sizeof(coords_type));
3626
3627 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3628 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3629 }
3630
3631 assert(length < sizeof(intrinsic_name));
3632 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3633 }
3634
3635 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3636 const nir_intrinsic_instr *instr)
3637 {
3638 LLVMValueRef res;
3639 const nir_variable *var = instr->variables[0]->var;
3640 const struct glsl_type *type = instr->variables[0]->var->type;
3641 bool da = glsl_sampler_type_is_array(var->type) ||
3642 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3643 if(instr->variables[0]->deref.child)
3644 type = instr->variables[0]->deref.child->type;
3645
3646 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3647 return get_buffer_size(ctx,
3648 get_sampler_desc(ctx, instr->variables[0],
3649 AC_DESC_BUFFER, NULL, true, false), true);
3650
3651 struct ac_image_args args = { 0 };
3652
3653 args.da = da;
3654 args.dmask = 0xf;
3655 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3656 args.opcode = ac_image_get_resinfo;
3657 args.addr = ctx->ac.i32_0;
3658
3659 res = ac_build_image_opcode(&ctx->ac, &args);
3660
3661 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3662
3663 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3664 glsl_sampler_type_is_array(type)) {
3665 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3666 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3667 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3668 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3669 }
3670 if (ctx->ac.chip_class >= GFX9 &&
3671 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3672 glsl_sampler_type_is_array(type)) {
3673 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3674 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3675 ctx->ac.i32_1, "");
3676
3677 }
3678 return res;
3679 }
3680
3681 #define NOOP_WAITCNT 0xf7f
3682 #define LGKM_CNT 0x07f
3683 #define VM_CNT 0xf70
3684
3685 static void emit_membar(struct nir_to_llvm_context *ctx,
3686 const nir_intrinsic_instr *instr)
3687 {
3688 unsigned waitcnt = NOOP_WAITCNT;
3689
3690 switch (instr->intrinsic) {
3691 case nir_intrinsic_memory_barrier:
3692 case nir_intrinsic_group_memory_barrier:
3693 waitcnt &= VM_CNT & LGKM_CNT;
3694 break;
3695 case nir_intrinsic_memory_barrier_atomic_counter:
3696 case nir_intrinsic_memory_barrier_buffer:
3697 case nir_intrinsic_memory_barrier_image:
3698 waitcnt &= VM_CNT;
3699 break;
3700 case nir_intrinsic_memory_barrier_shared:
3701 waitcnt &= LGKM_CNT;
3702 break;
3703 default:
3704 break;
3705 }
3706 if (waitcnt != NOOP_WAITCNT)
3707 ac_build_waitcnt(&ctx->ac, waitcnt);
3708 }
3709
3710 static void emit_barrier(struct nir_to_llvm_context *ctx)
3711 {
3712 /* SI only (thanks to a hw bug workaround):
3713 * The real barrier instruction isn’t needed, because an entire patch
3714 * always fits into a single wave.
3715 */
3716 if (ctx->options->chip_class == SI &&
3717 ctx->stage == MESA_SHADER_TESS_CTRL) {
3718 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3719 return;
3720 }
3721 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3722 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3723 }
3724
3725 static void emit_discard_if(struct ac_nir_context *ctx,
3726 const nir_intrinsic_instr *instr)
3727 {
3728 LLVMValueRef cond;
3729
3730 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3731 get_src(ctx, instr->src[0]),
3732 ctx->ac.i32_0, "");
3733 ac_build_kill_if_false(&ctx->ac, cond);
3734 }
3735
3736 static LLVMValueRef
3737 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3738 {
3739 LLVMValueRef result;
3740 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3741 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3742 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3743
3744 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3745 }
3746
3747 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3748 const nir_intrinsic_instr *instr)
3749 {
3750 LLVMValueRef ptr, result;
3751 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3752 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3753
3754 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3755 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3756 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3757 ptr, src, src1,
3758 LLVMAtomicOrderingSequentiallyConsistent,
3759 LLVMAtomicOrderingSequentiallyConsistent,
3760 false);
3761 } else {
3762 LLVMAtomicRMWBinOp op;
3763 switch (instr->intrinsic) {
3764 case nir_intrinsic_var_atomic_add:
3765 op = LLVMAtomicRMWBinOpAdd;
3766 break;
3767 case nir_intrinsic_var_atomic_umin:
3768 op = LLVMAtomicRMWBinOpUMin;
3769 break;
3770 case nir_intrinsic_var_atomic_umax:
3771 op = LLVMAtomicRMWBinOpUMax;
3772 break;
3773 case nir_intrinsic_var_atomic_imin:
3774 op = LLVMAtomicRMWBinOpMin;
3775 break;
3776 case nir_intrinsic_var_atomic_imax:
3777 op = LLVMAtomicRMWBinOpMax;
3778 break;
3779 case nir_intrinsic_var_atomic_and:
3780 op = LLVMAtomicRMWBinOpAnd;
3781 break;
3782 case nir_intrinsic_var_atomic_or:
3783 op = LLVMAtomicRMWBinOpOr;
3784 break;
3785 case nir_intrinsic_var_atomic_xor:
3786 op = LLVMAtomicRMWBinOpXor;
3787 break;
3788 case nir_intrinsic_var_atomic_exchange:
3789 op = LLVMAtomicRMWBinOpXchg;
3790 break;
3791 default:
3792 return NULL;
3793 }
3794
3795 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3796 LLVMAtomicOrderingSequentiallyConsistent,
3797 false);
3798 }
3799 return result;
3800 }
3801
3802 #define INTERP_CENTER 0
3803 #define INTERP_CENTROID 1
3804 #define INTERP_SAMPLE 2
3805
3806 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3807 enum glsl_interp_mode interp, unsigned location)
3808 {
3809 switch (interp) {
3810 case INTERP_MODE_FLAT:
3811 default:
3812 return NULL;
3813 case INTERP_MODE_SMOOTH:
3814 case INTERP_MODE_NONE:
3815 if (location == INTERP_CENTER)
3816 return ctx->persp_center;
3817 else if (location == INTERP_CENTROID)
3818 return ctx->persp_centroid;
3819 else if (location == INTERP_SAMPLE)
3820 return ctx->persp_sample;
3821 break;
3822 case INTERP_MODE_NOPERSPECTIVE:
3823 if (location == INTERP_CENTER)
3824 return ctx->linear_center;
3825 else if (location == INTERP_CENTROID)
3826 return ctx->linear_centroid;
3827 else if (location == INTERP_SAMPLE)
3828 return ctx->linear_sample;
3829 break;
3830 }
3831 return NULL;
3832 }
3833
3834 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3835 LLVMValueRef sample_id)
3836 {
3837 LLVMValueRef result;
3838 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3839
3840 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3841 const_array(ctx->ac.v2f32, 64), "");
3842
3843 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3844 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3845
3846 return result;
3847 }
3848
3849 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3850 {
3851 LLVMValueRef values[2];
3852
3853 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3854 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3855 return ac_build_gather_values(&ctx->ac, values, 2);
3856 }
3857
3858 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3859 const nir_intrinsic_instr *instr)
3860 {
3861 LLVMValueRef result[4];
3862 LLVMValueRef interp_param, attr_number;
3863 unsigned location;
3864 unsigned chan;
3865 LLVMValueRef src_c0 = NULL;
3866 LLVMValueRef src_c1 = NULL;
3867 LLVMValueRef src0 = NULL;
3868 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3869 switch (instr->intrinsic) {
3870 case nir_intrinsic_interp_var_at_centroid:
3871 location = INTERP_CENTROID;
3872 break;
3873 case nir_intrinsic_interp_var_at_sample:
3874 case nir_intrinsic_interp_var_at_offset:
3875 location = INTERP_CENTER;
3876 src0 = get_src(ctx->nir, instr->src[0]);
3877 break;
3878 default:
3879 break;
3880 }
3881
3882 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3883 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3884 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3885 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3886 LLVMValueRef sample_position;
3887 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3888
3889 /* fetch sample ID */
3890 sample_position = load_sample_position(ctx, src0);
3891
3892 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3893 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3894 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3895 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3896 }
3897 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3898 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3899
3900 if (location == INTERP_CENTER) {
3901 LLVMValueRef ij_out[2];
3902 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3903
3904 /*
3905 * take the I then J parameters, and the DDX/Y for it, and
3906 * calculate the IJ inputs for the interpolator.
3907 * temp1 = ddx * offset/sample.x + I;
3908 * interp_param.I = ddy * offset/sample.y + temp1;
3909 * temp1 = ddx * offset/sample.x + J;
3910 * interp_param.J = ddy * offset/sample.y + temp1;
3911 */
3912 for (unsigned i = 0; i < 2; i++) {
3913 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
3914 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
3915 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3916 ddxy_out, ix_ll, "");
3917 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3918 ddxy_out, iy_ll, "");
3919 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3920 interp_param, ix_ll, "");
3921 LLVMValueRef temp1, temp2;
3922
3923 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3924 ctx->ac.f32, "");
3925
3926 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3927 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3928
3929 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3930 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3931
3932 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3933 temp2, ctx->ac.i32, "");
3934 }
3935 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3936
3937 }
3938
3939 for (chan = 0; chan < 4; chan++) {
3940 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
3941
3942 if (interp_param) {
3943 interp_param = LLVMBuildBitCast(ctx->builder,
3944 interp_param, ctx->ac.v2f32, "");
3945 LLVMValueRef i = LLVMBuildExtractElement(
3946 ctx->builder, interp_param, ctx->ac.i32_0, "");
3947 LLVMValueRef j = LLVMBuildExtractElement(
3948 ctx->builder, interp_param, ctx->ac.i32_1, "");
3949
3950 result[chan] = ac_build_fs_interp(&ctx->ac,
3951 llvm_chan, attr_number,
3952 ctx->prim_mask, i, j);
3953 } else {
3954 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3955 LLVMConstInt(ctx->ac.i32, 2, false),
3956 llvm_chan, attr_number,
3957 ctx->prim_mask);
3958 }
3959 }
3960 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
3961 instr->variables[0]->var->data.location_frac);
3962 }
3963
3964 static void
3965 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
3966 {
3967 LLVMValueRef gs_next_vertex;
3968 LLVMValueRef can_emit;
3969 int idx;
3970 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3971
3972 /* Write vertex attribute values to GSVS ring */
3973 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3974 ctx->gs_next_vertex,
3975 "");
3976
3977 /* If this thread has already emitted the declared maximum number of
3978 * vertices, kill it: excessive vertex emissions are not supposed to
3979 * have any effect, and GS threads have no externally observable
3980 * effects other than emitting vertices.
3981 */
3982 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3983 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
3984 ac_build_kill_if_false(&ctx->ac, can_emit);
3985
3986 /* loop num outputs */
3987 idx = 0;
3988 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3989 LLVMValueRef *out_ptr = &addrs[i * 4];
3990 int length = 4;
3991 int slot = idx;
3992 int slot_inc = 1;
3993
3994 if (!(ctx->output_mask & (1ull << i)))
3995 continue;
3996
3997 if (i == VARYING_SLOT_CLIP_DIST0) {
3998 /* pack clip and cull into a single set of slots */
3999 length = ctx->num_output_clips + ctx->num_output_culls;
4000 if (length > 4)
4001 slot_inc = 2;
4002 }
4003 for (unsigned j = 0; j < length; j++) {
4004 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4005 out_ptr[j], "");
4006 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4007 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4008 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4009
4010 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4011
4012 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4013 out_val, 1,
4014 voffset, ctx->gs2vs_offset, 0,
4015 1, 1, true, true);
4016 }
4017 idx += slot_inc;
4018 }
4019
4020 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4021 ctx->ac.i32_1, "");
4022 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4023
4024 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4025 }
4026
4027 static void
4028 visit_end_primitive(struct nir_to_llvm_context *ctx,
4029 const nir_intrinsic_instr *instr)
4030 {
4031 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4032 }
4033
4034 static LLVMValueRef
4035 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4036 const nir_intrinsic_instr *instr)
4037 {
4038 LLVMValueRef coord[4] = {
4039 ctx->tes_u,
4040 ctx->tes_v,
4041 ctx->ac.f32_0,
4042 ctx->ac.f32_0,
4043 };
4044
4045 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4046 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4047 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4048
4049 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4050 return LLVMBuildBitCast(ctx->builder, result,
4051 get_def_type(ctx->nir, &instr->dest.ssa), "");
4052 }
4053
4054 static void visit_intrinsic(struct ac_nir_context *ctx,
4055 nir_intrinsic_instr *instr)
4056 {
4057 LLVMValueRef result = NULL;
4058
4059 switch (instr->intrinsic) {
4060 case nir_intrinsic_load_work_group_id: {
4061 LLVMValueRef values[3];
4062
4063 for (int i = 0; i < 3; i++) {
4064 values[i] = ctx->nctx->workgroup_ids[i] ?
4065 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4066 }
4067
4068 result = ac_build_gather_values(&ctx->ac, values, 3);
4069 break;
4070 }
4071 case nir_intrinsic_load_base_vertex: {
4072 result = ctx->abi->base_vertex;
4073 break;
4074 }
4075 case nir_intrinsic_load_vertex_id_zero_base: {
4076 result = ctx->abi->vertex_id;
4077 break;
4078 }
4079 case nir_intrinsic_load_local_invocation_id: {
4080 result = ctx->nctx->local_invocation_ids;
4081 break;
4082 }
4083 case nir_intrinsic_load_base_instance:
4084 result = ctx->abi->start_instance;
4085 break;
4086 case nir_intrinsic_load_draw_id:
4087 result = ctx->abi->draw_id;
4088 break;
4089 case nir_intrinsic_load_view_index:
4090 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4091 break;
4092 case nir_intrinsic_load_invocation_id:
4093 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4094 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4095 else
4096 result = ctx->abi->gs_invocation_id;
4097 break;
4098 case nir_intrinsic_load_primitive_id:
4099 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4100 if (ctx->nctx)
4101 ctx->nctx->shader_info->gs.uses_prim_id = true;
4102 result = ctx->abi->gs_prim_id;
4103 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4104 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4105 result = ctx->nctx->tcs_patch_id;
4106 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4107 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4108 result = ctx->nctx->tes_patch_id;
4109 } else
4110 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4111 break;
4112 case nir_intrinsic_load_sample_id:
4113 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4114 break;
4115 case nir_intrinsic_load_sample_pos:
4116 result = load_sample_pos(ctx);
4117 break;
4118 case nir_intrinsic_load_sample_mask_in:
4119 result = ctx->abi->sample_coverage;
4120 break;
4121 case nir_intrinsic_load_frag_coord: {
4122 LLVMValueRef values[4] = {
4123 ctx->abi->frag_pos[0],
4124 ctx->abi->frag_pos[1],
4125 ctx->abi->frag_pos[2],
4126 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4127 };
4128 result = ac_build_gather_values(&ctx->ac, values, 4);
4129 break;
4130 }
4131 case nir_intrinsic_load_front_face:
4132 result = ctx->abi->front_face;
4133 break;
4134 case nir_intrinsic_load_instance_id:
4135 result = ctx->abi->instance_id;
4136 break;
4137 case nir_intrinsic_load_num_work_groups:
4138 result = ctx->nctx->num_work_groups;
4139 break;
4140 case nir_intrinsic_load_local_invocation_index:
4141 result = visit_load_local_invocation_index(ctx->nctx);
4142 break;
4143 case nir_intrinsic_load_push_constant:
4144 result = visit_load_push_constant(ctx->nctx, instr);
4145 break;
4146 case nir_intrinsic_vulkan_resource_index:
4147 result = visit_vulkan_resource_index(ctx->nctx, instr);
4148 break;
4149 case nir_intrinsic_vulkan_resource_reindex:
4150 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4151 break;
4152 case nir_intrinsic_store_ssbo:
4153 visit_store_ssbo(ctx, instr);
4154 break;
4155 case nir_intrinsic_load_ssbo:
4156 result = visit_load_buffer(ctx, instr);
4157 break;
4158 case nir_intrinsic_ssbo_atomic_add:
4159 case nir_intrinsic_ssbo_atomic_imin:
4160 case nir_intrinsic_ssbo_atomic_umin:
4161 case nir_intrinsic_ssbo_atomic_imax:
4162 case nir_intrinsic_ssbo_atomic_umax:
4163 case nir_intrinsic_ssbo_atomic_and:
4164 case nir_intrinsic_ssbo_atomic_or:
4165 case nir_intrinsic_ssbo_atomic_xor:
4166 case nir_intrinsic_ssbo_atomic_exchange:
4167 case nir_intrinsic_ssbo_atomic_comp_swap:
4168 result = visit_atomic_ssbo(ctx, instr);
4169 break;
4170 case nir_intrinsic_load_ubo:
4171 result = visit_load_ubo_buffer(ctx, instr);
4172 break;
4173 case nir_intrinsic_get_buffer_size:
4174 result = visit_get_buffer_size(ctx, instr);
4175 break;
4176 case nir_intrinsic_load_var:
4177 result = visit_load_var(ctx, instr);
4178 break;
4179 case nir_intrinsic_store_var:
4180 visit_store_var(ctx, instr);
4181 break;
4182 case nir_intrinsic_image_load:
4183 result = visit_image_load(ctx, instr);
4184 break;
4185 case nir_intrinsic_image_store:
4186 visit_image_store(ctx, instr);
4187 break;
4188 case nir_intrinsic_image_atomic_add:
4189 case nir_intrinsic_image_atomic_min:
4190 case nir_intrinsic_image_atomic_max:
4191 case nir_intrinsic_image_atomic_and:
4192 case nir_intrinsic_image_atomic_or:
4193 case nir_intrinsic_image_atomic_xor:
4194 case nir_intrinsic_image_atomic_exchange:
4195 case nir_intrinsic_image_atomic_comp_swap:
4196 result = visit_image_atomic(ctx, instr);
4197 break;
4198 case nir_intrinsic_image_size:
4199 result = visit_image_size(ctx, instr);
4200 break;
4201 case nir_intrinsic_discard:
4202 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4203 LLVMVoidTypeInContext(ctx->ac.context),
4204 NULL, 0, AC_FUNC_ATTR_LEGACY);
4205 break;
4206 case nir_intrinsic_discard_if:
4207 emit_discard_if(ctx, instr);
4208 break;
4209 case nir_intrinsic_memory_barrier:
4210 case nir_intrinsic_group_memory_barrier:
4211 case nir_intrinsic_memory_barrier_atomic_counter:
4212 case nir_intrinsic_memory_barrier_buffer:
4213 case nir_intrinsic_memory_barrier_image:
4214 case nir_intrinsic_memory_barrier_shared:
4215 emit_membar(ctx->nctx, instr);
4216 break;
4217 case nir_intrinsic_barrier:
4218 emit_barrier(ctx->nctx);
4219 break;
4220 case nir_intrinsic_var_atomic_add:
4221 case nir_intrinsic_var_atomic_imin:
4222 case nir_intrinsic_var_atomic_umin:
4223 case nir_intrinsic_var_atomic_imax:
4224 case nir_intrinsic_var_atomic_umax:
4225 case nir_intrinsic_var_atomic_and:
4226 case nir_intrinsic_var_atomic_or:
4227 case nir_intrinsic_var_atomic_xor:
4228 case nir_intrinsic_var_atomic_exchange:
4229 case nir_intrinsic_var_atomic_comp_swap:
4230 result = visit_var_atomic(ctx->nctx, instr);
4231 break;
4232 case nir_intrinsic_interp_var_at_centroid:
4233 case nir_intrinsic_interp_var_at_sample:
4234 case nir_intrinsic_interp_var_at_offset:
4235 result = visit_interp(ctx->nctx, instr);
4236 break;
4237 case nir_intrinsic_emit_vertex:
4238 assert(instr->const_index[0] == 0);
4239 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4240 break;
4241 case nir_intrinsic_end_primitive:
4242 visit_end_primitive(ctx->nctx, instr);
4243 break;
4244 case nir_intrinsic_load_tess_coord:
4245 result = visit_load_tess_coord(ctx->nctx, instr);
4246 break;
4247 case nir_intrinsic_load_patch_vertices_in:
4248 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4249 break;
4250 default:
4251 fprintf(stderr, "Unknown intrinsic: ");
4252 nir_print_instr(&instr->instr, stderr);
4253 fprintf(stderr, "\n");
4254 break;
4255 }
4256 if (result) {
4257 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4258 }
4259 }
4260
4261 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4262 LLVMValueRef buffer_ptr, bool write)
4263 {
4264 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4265
4266 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4267 ctx->shader_info->fs.writes_memory = true;
4268
4269 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4270 }
4271
4272 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4273 {
4274 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4275
4276 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4277 }
4278
4279 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4280 unsigned descriptor_set,
4281 unsigned base_index,
4282 unsigned constant_index,
4283 LLVMValueRef index,
4284 enum ac_descriptor_type desc_type,
4285 bool image, bool write)
4286 {
4287 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4288 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4289 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4290 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4291 unsigned offset = binding->offset;
4292 unsigned stride = binding->size;
4293 unsigned type_size;
4294 LLVMBuilderRef builder = ctx->builder;
4295 LLVMTypeRef type;
4296
4297 assert(base_index < layout->binding_count);
4298
4299 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4300 ctx->shader_info->fs.writes_memory = true;
4301
4302 switch (desc_type) {
4303 case AC_DESC_IMAGE:
4304 type = ctx->ac.v8i32;
4305 type_size = 32;
4306 break;
4307 case AC_DESC_FMASK:
4308 type = ctx->ac.v8i32;
4309 offset += 32;
4310 type_size = 32;
4311 break;
4312 case AC_DESC_SAMPLER:
4313 type = ctx->ac.v4i32;
4314 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4315 offset += 64;
4316
4317 type_size = 16;
4318 break;
4319 case AC_DESC_BUFFER:
4320 type = ctx->ac.v4i32;
4321 type_size = 16;
4322 break;
4323 default:
4324 unreachable("invalid desc_type\n");
4325 }
4326
4327 offset += constant_index * stride;
4328
4329 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4330 (!index || binding->immutable_samplers_equal)) {
4331 if (binding->immutable_samplers_equal)
4332 constant_index = 0;
4333
4334 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4335
4336 LLVMValueRef constants[] = {
4337 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4338 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4339 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4340 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4341 };
4342 return ac_build_gather_values(&ctx->ac, constants, 4);
4343 }
4344
4345 assert(stride % type_size == 0);
4346
4347 if (!index)
4348 index = ctx->ac.i32_0;
4349
4350 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4351
4352 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4353 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4354
4355 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4356 }
4357
4358 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4359 const nir_deref_var *deref,
4360 enum ac_descriptor_type desc_type,
4361 const nir_tex_instr *tex_instr,
4362 bool image, bool write)
4363 {
4364 LLVMValueRef index = NULL;
4365 unsigned constant_index = 0;
4366 unsigned descriptor_set;
4367 unsigned base_index;
4368
4369 if (!deref) {
4370 assert(tex_instr && !image);
4371 descriptor_set = 0;
4372 base_index = tex_instr->sampler_index;
4373 } else {
4374 const nir_deref *tail = &deref->deref;
4375 while (tail->child) {
4376 const nir_deref_array *child = nir_deref_as_array(tail->child);
4377 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4378
4379 if (!array_size)
4380 array_size = 1;
4381
4382 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4383
4384 if (child->deref_array_type == nir_deref_array_type_indirect) {
4385 LLVMValueRef indirect = get_src(ctx, child->indirect);
4386
4387 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4388 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4389
4390 if (!index)
4391 index = indirect;
4392 else
4393 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4394 }
4395
4396 constant_index += child->base_offset * array_size;
4397
4398 tail = &child->deref;
4399 }
4400 descriptor_set = deref->var->data.descriptor_set;
4401 base_index = deref->var->data.binding;
4402 }
4403
4404 return ctx->abi->load_sampler_desc(ctx->abi,
4405 descriptor_set,
4406 base_index,
4407 constant_index, index,
4408 desc_type, image, write);
4409 }
4410
4411 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4412 struct ac_image_args *args,
4413 const nir_tex_instr *instr,
4414 nir_texop op,
4415 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4416 LLVMValueRef *param, unsigned count,
4417 unsigned dmask)
4418 {
4419 unsigned is_rect = 0;
4420 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4421
4422 if (op == nir_texop_lod)
4423 da = false;
4424 /* Pad to power of two vector */
4425 while (count < util_next_power_of_two(count))
4426 param[count++] = LLVMGetUndef(ctx->i32);
4427
4428 if (count > 1)
4429 args->addr = ac_build_gather_values(ctx, param, count);
4430 else
4431 args->addr = param[0];
4432
4433 args->resource = res_ptr;
4434 args->sampler = samp_ptr;
4435
4436 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4437 args->addr = param[0];
4438 return;
4439 }
4440
4441 args->dmask = dmask;
4442 args->unorm = is_rect;
4443 args->da = da;
4444 }
4445
4446 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4447 *
4448 * SI-CI:
4449 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4450 * filtering manually. The driver sets img7 to a mask clearing
4451 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4452 * s_and_b32 samp0, samp0, img7
4453 *
4454 * VI:
4455 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4456 */
4457 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4458 LLVMValueRef res, LLVMValueRef samp)
4459 {
4460 LLVMBuilderRef builder = ctx->ac.builder;
4461 LLVMValueRef img7, samp0;
4462
4463 if (ctx->ac.chip_class >= VI)
4464 return samp;
4465
4466 img7 = LLVMBuildExtractElement(builder, res,
4467 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4468 samp0 = LLVMBuildExtractElement(builder, samp,
4469 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4470 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4471 return LLVMBuildInsertElement(builder, samp, samp0,
4472 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4473 }
4474
4475 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4476 nir_tex_instr *instr,
4477 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4478 LLVMValueRef *fmask_ptr)
4479 {
4480 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4481 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4482 else
4483 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4484 if (samp_ptr) {
4485 if (instr->sampler)
4486 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4487 else
4488 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4489 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4490 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4491 }
4492 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4493 instr->op == nir_texop_samples_identical))
4494 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4495 }
4496
4497 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4498 LLVMValueRef coord)
4499 {
4500 coord = ac_to_float(ctx, coord);
4501 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4502 coord = ac_to_integer(ctx, coord);
4503 return coord;
4504 }
4505
4506 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4507 {
4508 LLVMValueRef result = NULL;
4509 struct ac_image_args args = { 0 };
4510 unsigned dmask = 0xf;
4511 LLVMValueRef address[16];
4512 LLVMValueRef coords[5];
4513 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4514 LLVMValueRef bias = NULL, offsets = NULL;
4515 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4516 LLVMValueRef ddx = NULL, ddy = NULL;
4517 LLVMValueRef derivs[6];
4518 unsigned chan, count = 0;
4519 unsigned const_src = 0, num_deriv_comp = 0;
4520 bool lod_is_zero = false;
4521
4522 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4523
4524 for (unsigned i = 0; i < instr->num_srcs; i++) {
4525 switch (instr->src[i].src_type) {
4526 case nir_tex_src_coord:
4527 coord = get_src(ctx, instr->src[i].src);
4528 break;
4529 case nir_tex_src_projector:
4530 break;
4531 case nir_tex_src_comparator:
4532 comparator = get_src(ctx, instr->src[i].src);
4533 break;
4534 case nir_tex_src_offset:
4535 offsets = get_src(ctx, instr->src[i].src);
4536 const_src = i;
4537 break;
4538 case nir_tex_src_bias:
4539 bias = get_src(ctx, instr->src[i].src);
4540 break;
4541 case nir_tex_src_lod: {
4542 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4543
4544 if (val && val->i32[0] == 0)
4545 lod_is_zero = true;
4546 lod = get_src(ctx, instr->src[i].src);
4547 break;
4548 }
4549 case nir_tex_src_ms_index:
4550 sample_index = get_src(ctx, instr->src[i].src);
4551 break;
4552 case nir_tex_src_ms_mcs:
4553 break;
4554 case nir_tex_src_ddx:
4555 ddx = get_src(ctx, instr->src[i].src);
4556 num_deriv_comp = instr->src[i].src.ssa->num_components;
4557 break;
4558 case nir_tex_src_ddy:
4559 ddy = get_src(ctx, instr->src[i].src);
4560 break;
4561 case nir_tex_src_texture_offset:
4562 case nir_tex_src_sampler_offset:
4563 case nir_tex_src_plane:
4564 default:
4565 break;
4566 }
4567 }
4568
4569 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4570 result = get_buffer_size(ctx, res_ptr, true);
4571 goto write_result;
4572 }
4573
4574 if (instr->op == nir_texop_texture_samples) {
4575 LLVMValueRef res, samples, is_msaa;
4576 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4577 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4578 LLVMConstInt(ctx->ac.i32, 3, false), "");
4579 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4580 LLVMConstInt(ctx->ac.i32, 28, false), "");
4581 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4582 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4583 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4584 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4585
4586 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4587 LLVMConstInt(ctx->ac.i32, 16, false), "");
4588 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4589 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4590 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4591 samples, "");
4592 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4593 ctx->ac.i32_1, "");
4594 result = samples;
4595 goto write_result;
4596 }
4597
4598 if (coord)
4599 for (chan = 0; chan < instr->coord_components; chan++)
4600 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4601
4602 if (offsets && instr->op != nir_texop_txf) {
4603 LLVMValueRef offset[3], pack;
4604 for (chan = 0; chan < 3; ++chan)
4605 offset[chan] = ctx->ac.i32_0;
4606
4607 args.offset = true;
4608 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4609 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4610 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4611 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4612 if (chan)
4613 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4614 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4615 }
4616 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4617 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4618 address[count++] = pack;
4619
4620 }
4621 /* pack LOD bias value */
4622 if (instr->op == nir_texop_txb && bias) {
4623 address[count++] = bias;
4624 }
4625
4626 /* Pack depth comparison value */
4627 if (instr->is_shadow && comparator) {
4628 LLVMValueRef z = ac_to_float(&ctx->ac,
4629 llvm_extract_elem(&ctx->ac, comparator, 0));
4630
4631 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4632 * so the depth comparison value isn't clamped for Z16 and
4633 * Z24 anymore. Do it manually here.
4634 *
4635 * It's unnecessary if the original texture format was
4636 * Z32_FLOAT, but we don't know that here.
4637 */
4638 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4639 z = ac_build_clamp(&ctx->ac, z);
4640
4641 address[count++] = z;
4642 }
4643
4644 /* pack derivatives */
4645 if (ddx || ddy) {
4646 int num_src_deriv_channels, num_dest_deriv_channels;
4647 switch (instr->sampler_dim) {
4648 case GLSL_SAMPLER_DIM_3D:
4649 case GLSL_SAMPLER_DIM_CUBE:
4650 num_deriv_comp = 3;
4651 num_src_deriv_channels = 3;
4652 num_dest_deriv_channels = 3;
4653 break;
4654 case GLSL_SAMPLER_DIM_2D:
4655 default:
4656 num_src_deriv_channels = 2;
4657 num_dest_deriv_channels = 2;
4658 num_deriv_comp = 2;
4659 break;
4660 case GLSL_SAMPLER_DIM_1D:
4661 num_src_deriv_channels = 1;
4662 if (ctx->ac.chip_class >= GFX9) {
4663 num_dest_deriv_channels = 2;
4664 num_deriv_comp = 2;
4665 } else {
4666 num_dest_deriv_channels = 1;
4667 num_deriv_comp = 1;
4668 }
4669 break;
4670 }
4671
4672 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4673 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4674 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4675 }
4676 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4677 derivs[i] = ctx->ac.f32_0;
4678 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4679 }
4680 }
4681
4682 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4683 for (chan = 0; chan < instr->coord_components; chan++)
4684 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4685 if (instr->coord_components == 3)
4686 coords[3] = LLVMGetUndef(ctx->ac.f32);
4687 ac_prepare_cube_coords(&ctx->ac,
4688 instr->op == nir_texop_txd, instr->is_array,
4689 instr->op == nir_texop_lod, coords, derivs);
4690 if (num_deriv_comp)
4691 num_deriv_comp--;
4692 }
4693
4694 if (ddx || ddy) {
4695 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4696 address[count++] = derivs[i];
4697 }
4698
4699 /* Pack texture coordinates */
4700 if (coord) {
4701 address[count++] = coords[0];
4702 if (instr->coord_components > 1) {
4703 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4704 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4705 }
4706 address[count++] = coords[1];
4707 }
4708 if (instr->coord_components > 2) {
4709 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4710 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4711 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4712 instr->op != nir_texop_txf) {
4713 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4714 }
4715 address[count++] = coords[2];
4716 }
4717
4718 if (ctx->ac.chip_class >= GFX9) {
4719 LLVMValueRef filler;
4720 if (instr->op == nir_texop_txf)
4721 filler = ctx->ac.i32_0;
4722 else
4723 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4724
4725 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4726 /* No nir_texop_lod, because it does not take a slice
4727 * even with array textures. */
4728 if (instr->is_array && instr->op != nir_texop_lod ) {
4729 address[count] = address[count - 1];
4730 address[count - 1] = filler;
4731 count++;
4732 } else
4733 address[count++] = filler;
4734 }
4735 }
4736 }
4737
4738 /* Pack LOD */
4739 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4740 instr->op == nir_texop_txf)) {
4741 address[count++] = lod;
4742 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4743 address[count++] = sample_index;
4744 } else if(instr->op == nir_texop_txs) {
4745 count = 0;
4746 if (lod)
4747 address[count++] = lod;
4748 else
4749 address[count++] = ctx->ac.i32_0;
4750 }
4751
4752 for (chan = 0; chan < count; chan++) {
4753 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4754 address[chan], ctx->ac.i32, "");
4755 }
4756
4757 if (instr->op == nir_texop_samples_identical) {
4758 LLVMValueRef txf_address[4];
4759 struct ac_image_args txf_args = { 0 };
4760 unsigned txf_count = count;
4761 memcpy(txf_address, address, sizeof(txf_address));
4762
4763 if (!instr->is_array)
4764 txf_address[2] = ctx->ac.i32_0;
4765 txf_address[3] = ctx->ac.i32_0;
4766
4767 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4768 fmask_ptr, NULL,
4769 txf_address, txf_count, 0xf);
4770
4771 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4772
4773 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4774 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4775 goto write_result;
4776 }
4777
4778 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4779 instr->op != nir_texop_txs) {
4780 unsigned sample_chan = instr->is_array ? 3 : 2;
4781 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4782 address[0],
4783 address[1],
4784 instr->is_array ? address[2] : NULL,
4785 address[sample_chan],
4786 fmask_ptr);
4787 }
4788
4789 if (offsets && instr->op == nir_texop_txf) {
4790 nir_const_value *const_offset =
4791 nir_src_as_const_value(instr->src[const_src].src);
4792 int num_offsets = instr->src[const_src].src.ssa->num_components;
4793 assert(const_offset);
4794 num_offsets = MIN2(num_offsets, instr->coord_components);
4795 if (num_offsets > 2)
4796 address[2] = LLVMBuildAdd(ctx->ac.builder,
4797 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4798 if (num_offsets > 1)
4799 address[1] = LLVMBuildAdd(ctx->ac.builder,
4800 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4801 address[0] = LLVMBuildAdd(ctx->ac.builder,
4802 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4803
4804 }
4805
4806 /* TODO TG4 support */
4807 if (instr->op == nir_texop_tg4) {
4808 if (instr->is_shadow)
4809 dmask = 1;
4810 else
4811 dmask = 1 << instr->component;
4812 }
4813 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4814 res_ptr, samp_ptr, address, count, dmask);
4815
4816 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4817
4818 if (instr->op == nir_texop_query_levels)
4819 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4820 else if (instr->is_shadow && instr->is_new_style_shadow &&
4821 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4822 instr->op != nir_texop_tg4)
4823 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4824 else if (instr->op == nir_texop_txs &&
4825 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4826 instr->is_array) {
4827 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4828 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4829 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4830 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4831 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4832 } else if (ctx->ac.chip_class >= GFX9 &&
4833 instr->op == nir_texop_txs &&
4834 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4835 instr->is_array) {
4836 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4837 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4838 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4839 ctx->ac.i32_1, "");
4840 } else if (instr->dest.ssa.num_components != 4)
4841 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4842
4843 write_result:
4844 if (result) {
4845 assert(instr->dest.is_ssa);
4846 result = ac_to_integer(&ctx->ac, result);
4847 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4848 }
4849 }
4850
4851
4852 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4853 {
4854 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4855 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4856
4857 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4858 _mesa_hash_table_insert(ctx->phis, instr, result);
4859 }
4860
4861 static void visit_post_phi(struct ac_nir_context *ctx,
4862 nir_phi_instr *instr,
4863 LLVMValueRef llvm_phi)
4864 {
4865 nir_foreach_phi_src(src, instr) {
4866 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4867 LLVMValueRef llvm_src = get_src(ctx, src->src);
4868
4869 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4870 }
4871 }
4872
4873 static void phi_post_pass(struct ac_nir_context *ctx)
4874 {
4875 struct hash_entry *entry;
4876 hash_table_foreach(ctx->phis, entry) {
4877 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4878 (LLVMValueRef)entry->data);
4879 }
4880 }
4881
4882
4883 static void visit_ssa_undef(struct ac_nir_context *ctx,
4884 const nir_ssa_undef_instr *instr)
4885 {
4886 unsigned num_components = instr->def.num_components;
4887 LLVMValueRef undef;
4888
4889 if (num_components == 1)
4890 undef = LLVMGetUndef(ctx->ac.i32);
4891 else {
4892 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4893 }
4894 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4895 }
4896
4897 static void visit_jump(struct ac_nir_context *ctx,
4898 const nir_jump_instr *instr)
4899 {
4900 switch (instr->type) {
4901 case nir_jump_break:
4902 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4903 LLVMClearInsertionPosition(ctx->ac.builder);
4904 break;
4905 case nir_jump_continue:
4906 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4907 LLVMClearInsertionPosition(ctx->ac.builder);
4908 break;
4909 default:
4910 fprintf(stderr, "Unknown NIR jump instr: ");
4911 nir_print_instr(&instr->instr, stderr);
4912 fprintf(stderr, "\n");
4913 abort();
4914 }
4915 }
4916
4917 static void visit_cf_list(struct ac_nir_context *ctx,
4918 struct exec_list *list);
4919
4920 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4921 {
4922 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4923 nir_foreach_instr(instr, block)
4924 {
4925 switch (instr->type) {
4926 case nir_instr_type_alu:
4927 visit_alu(ctx, nir_instr_as_alu(instr));
4928 break;
4929 case nir_instr_type_load_const:
4930 visit_load_const(ctx, nir_instr_as_load_const(instr));
4931 break;
4932 case nir_instr_type_intrinsic:
4933 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4934 break;
4935 case nir_instr_type_tex:
4936 visit_tex(ctx, nir_instr_as_tex(instr));
4937 break;
4938 case nir_instr_type_phi:
4939 visit_phi(ctx, nir_instr_as_phi(instr));
4940 break;
4941 case nir_instr_type_ssa_undef:
4942 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4943 break;
4944 case nir_instr_type_jump:
4945 visit_jump(ctx, nir_instr_as_jump(instr));
4946 break;
4947 default:
4948 fprintf(stderr, "Unknown NIR instr type: ");
4949 nir_print_instr(instr, stderr);
4950 fprintf(stderr, "\n");
4951 abort();
4952 }
4953 }
4954
4955 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4956 }
4957
4958 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4959 {
4960 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4961
4962 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4963 LLVMBasicBlockRef merge_block =
4964 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4965 LLVMBasicBlockRef if_block =
4966 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4967 LLVMBasicBlockRef else_block = merge_block;
4968 if (!exec_list_is_empty(&if_stmt->else_list))
4969 else_block = LLVMAppendBasicBlockInContext(
4970 ctx->ac.context, fn, "");
4971
4972 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4973 ctx->ac.i32_0, "");
4974 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4975
4976 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4977 visit_cf_list(ctx, &if_stmt->then_list);
4978 if (LLVMGetInsertBlock(ctx->ac.builder))
4979 LLVMBuildBr(ctx->ac.builder, merge_block);
4980
4981 if (!exec_list_is_empty(&if_stmt->else_list)) {
4982 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4983 visit_cf_list(ctx, &if_stmt->else_list);
4984 if (LLVMGetInsertBlock(ctx->ac.builder))
4985 LLVMBuildBr(ctx->ac.builder, merge_block);
4986 }
4987
4988 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4989 }
4990
4991 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4992 {
4993 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4994 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4995 LLVMBasicBlockRef break_parent = ctx->break_block;
4996
4997 ctx->continue_block =
4998 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4999 ctx->break_block =
5000 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5001
5002 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5003 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5004 visit_cf_list(ctx, &loop->body);
5005
5006 if (LLVMGetInsertBlock(ctx->ac.builder))
5007 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5008 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5009
5010 ctx->continue_block = continue_parent;
5011 ctx->break_block = break_parent;
5012 }
5013
5014 static void visit_cf_list(struct ac_nir_context *ctx,
5015 struct exec_list *list)
5016 {
5017 foreach_list_typed(nir_cf_node, node, node, list)
5018 {
5019 switch (node->type) {
5020 case nir_cf_node_block:
5021 visit_block(ctx, nir_cf_node_as_block(node));
5022 break;
5023
5024 case nir_cf_node_if:
5025 visit_if(ctx, nir_cf_node_as_if(node));
5026 break;
5027
5028 case nir_cf_node_loop:
5029 visit_loop(ctx, nir_cf_node_as_loop(node));
5030 break;
5031
5032 default:
5033 assert(0);
5034 }
5035 }
5036 }
5037
5038 static void
5039 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5040 struct nir_variable *variable)
5041 {
5042 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5043 LLVMValueRef t_offset;
5044 LLVMValueRef t_list;
5045 LLVMValueRef input;
5046 LLVMValueRef buffer_index;
5047 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5048 int idx = variable->data.location;
5049 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5050
5051 variable->data.driver_location = idx * 4;
5052
5053 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5054 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5055 ctx->abi.start_instance, "");
5056 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5057 ctx->shader_info->vs.vgpr_comp_cnt);
5058 } else
5059 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5060 ctx->abi.base_vertex, "");
5061
5062 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5063 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5064
5065 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5066
5067 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5068 buffer_index,
5069 ctx->ac.i32_0,
5070 true);
5071
5072 for (unsigned chan = 0; chan < 4; chan++) {
5073 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5074 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5075 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5076 input, llvm_chan, ""));
5077 }
5078 }
5079 }
5080
5081 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5082 unsigned attr,
5083 LLVMValueRef interp_param,
5084 LLVMValueRef prim_mask,
5085 LLVMValueRef result[4])
5086 {
5087 LLVMValueRef attr_number;
5088 unsigned chan;
5089 LLVMValueRef i, j;
5090 bool interp = interp_param != NULL;
5091
5092 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5093
5094 /* fs.constant returns the param from the middle vertex, so it's not
5095 * really useful for flat shading. It's meant to be used for custom
5096 * interpolation (but the intrinsic can't fetch from the other two
5097 * vertices).
5098 *
5099 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5100 * to do the right thing. The only reason we use fs.constant is that
5101 * fs.interp cannot be used on integers, because they can be equal
5102 * to NaN.
5103 */
5104 if (interp) {
5105 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5106 ctx->ac.v2f32, "");
5107
5108 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5109 ctx->ac.i32_0, "");
5110 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5111 ctx->ac.i32_1, "");
5112 }
5113
5114 for (chan = 0; chan < 4; chan++) {
5115 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5116
5117 if (interp) {
5118 result[chan] = ac_build_fs_interp(&ctx->ac,
5119 llvm_chan,
5120 attr_number,
5121 prim_mask, i, j);
5122 } else {
5123 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5124 LLVMConstInt(ctx->ac.i32, 2, false),
5125 llvm_chan,
5126 attr_number,
5127 prim_mask);
5128 }
5129 }
5130 }
5131
5132 static void
5133 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5134 struct nir_variable *variable)
5135 {
5136 int idx = variable->data.location;
5137 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5138 LLVMValueRef interp;
5139
5140 variable->data.driver_location = idx * 4;
5141 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5142
5143 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5144 unsigned interp_type;
5145 if (variable->data.sample) {
5146 interp_type = INTERP_SAMPLE;
5147 ctx->shader_info->info.ps.force_persample = true;
5148 } else if (variable->data.centroid)
5149 interp_type = INTERP_CENTROID;
5150 else
5151 interp_type = INTERP_CENTER;
5152
5153 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5154 } else
5155 interp = NULL;
5156
5157 for (unsigned i = 0; i < attrib_count; ++i)
5158 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5159
5160 }
5161
5162 static void
5163 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5164 struct nir_shader *nir) {
5165 nir_foreach_variable(variable, &nir->inputs)
5166 handle_vs_input_decl(ctx, variable);
5167 }
5168
5169 static void
5170 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5171 struct nir_shader *nir)
5172 {
5173 if (!ctx->options->key.fs.multisample)
5174 return;
5175
5176 bool uses_center = false;
5177 bool uses_centroid = false;
5178 nir_foreach_variable(variable, &nir->inputs) {
5179 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5180 variable->data.sample)
5181 continue;
5182
5183 if (variable->data.centroid)
5184 uses_centroid = true;
5185 else
5186 uses_center = true;
5187 }
5188
5189 if (uses_center && uses_centroid) {
5190 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5191 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5192 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5193 }
5194 }
5195
5196 static void
5197 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5198 struct nir_shader *nir)
5199 {
5200 prepare_interp_optimize(ctx, nir);
5201
5202 nir_foreach_variable(variable, &nir->inputs)
5203 handle_fs_input_decl(ctx, variable);
5204
5205 unsigned index = 0;
5206
5207 if (ctx->shader_info->info.ps.uses_input_attachments ||
5208 ctx->shader_info->info.needs_multiview_view_index)
5209 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5210
5211 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5212 LLVMValueRef interp_param;
5213 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5214
5215 if (!(ctx->input_mask & (1ull << i)))
5216 continue;
5217
5218 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5219 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5220 interp_param = *inputs;
5221 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5222 inputs);
5223
5224 if (!interp_param)
5225 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5226 ++index;
5227 } else if (i == VARYING_SLOT_POS) {
5228 for(int i = 0; i < 3; ++i)
5229 inputs[i] = ctx->abi.frag_pos[i];
5230
5231 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5232 ctx->abi.frag_pos[3]);
5233 }
5234 }
5235 ctx->shader_info->fs.num_interp = index;
5236 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5237 ctx->shader_info->fs.has_pcoord = true;
5238 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5239 ctx->shader_info->fs.prim_id_input = true;
5240 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5241 ctx->shader_info->fs.layer_input = true;
5242 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5243
5244 if (ctx->shader_info->info.needs_multiview_view_index)
5245 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5246 }
5247
5248 static LLVMValueRef
5249 ac_build_alloca(struct ac_llvm_context *ac,
5250 LLVMTypeRef type,
5251 const char *name)
5252 {
5253 LLVMBuilderRef builder = ac->builder;
5254 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5255 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5256 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5257 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5258 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5259 LLVMValueRef res;
5260
5261 if (first_instr) {
5262 LLVMPositionBuilderBefore(first_builder, first_instr);
5263 } else {
5264 LLVMPositionBuilderAtEnd(first_builder, first_block);
5265 }
5266
5267 res = LLVMBuildAlloca(first_builder, type, name);
5268 LLVMBuildStore(builder, LLVMConstNull(type), res);
5269
5270 LLVMDisposeBuilder(first_builder);
5271
5272 return res;
5273 }
5274
5275 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5276 LLVMTypeRef type,
5277 const char *name)
5278 {
5279 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5280 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5281 return ptr;
5282 }
5283
5284 static void
5285 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5286 struct nir_variable *variable,
5287 struct nir_shader *shader,
5288 gl_shader_stage stage)
5289 {
5290 int idx = variable->data.location + variable->data.index;
5291 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5292 uint64_t mask_attribs;
5293
5294 variable->data.driver_location = idx * 4;
5295
5296 /* tess ctrl has it's own load/store paths for outputs */
5297 if (stage == MESA_SHADER_TESS_CTRL)
5298 return;
5299
5300 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5301 if (stage == MESA_SHADER_VERTEX ||
5302 stage == MESA_SHADER_TESS_EVAL ||
5303 stage == MESA_SHADER_GEOMETRY) {
5304 if (idx == VARYING_SLOT_CLIP_DIST0) {
5305 int length = shader->info.clip_distance_array_size +
5306 shader->info.cull_distance_array_size;
5307 if (stage == MESA_SHADER_VERTEX) {
5308 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5309 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5310 }
5311 if (stage == MESA_SHADER_TESS_EVAL) {
5312 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5313 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5314 }
5315
5316 if (length > 4)
5317 attrib_count = 2;
5318 else
5319 attrib_count = 1;
5320 mask_attribs = 1ull << idx;
5321 }
5322 }
5323
5324 ctx->output_mask |= mask_attribs;
5325 }
5326
5327 static void
5328 handle_shader_output_decl(struct ac_nir_context *ctx,
5329 struct nir_shader *nir,
5330 struct nir_variable *variable)
5331 {
5332 unsigned output_loc = variable->data.driver_location / 4;
5333 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5334
5335 /* tess ctrl has it's own load/store paths for outputs */
5336 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5337 return;
5338
5339 if (ctx->stage == MESA_SHADER_VERTEX ||
5340 ctx->stage == MESA_SHADER_TESS_EVAL ||
5341 ctx->stage == MESA_SHADER_GEOMETRY) {
5342 int idx = variable->data.location + variable->data.index;
5343 if (idx == VARYING_SLOT_CLIP_DIST0) {
5344 int length = nir->info.clip_distance_array_size +
5345 nir->info.cull_distance_array_size;
5346
5347 if (length > 4)
5348 attrib_count = 2;
5349 else
5350 attrib_count = 1;
5351 }
5352 }
5353
5354 for (unsigned i = 0; i < attrib_count; ++i) {
5355 for (unsigned chan = 0; chan < 4; chan++) {
5356 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5357 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5358 }
5359 }
5360 }
5361
5362 static LLVMTypeRef
5363 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5364 enum glsl_base_type type)
5365 {
5366 switch (type) {
5367 case GLSL_TYPE_INT:
5368 case GLSL_TYPE_UINT:
5369 case GLSL_TYPE_BOOL:
5370 case GLSL_TYPE_SUBROUTINE:
5371 return ctx->ac.i32;
5372 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5373 return ctx->ac.f32;
5374 case GLSL_TYPE_INT64:
5375 case GLSL_TYPE_UINT64:
5376 return ctx->ac.i64;
5377 case GLSL_TYPE_DOUBLE:
5378 return ctx->ac.f64;
5379 default:
5380 unreachable("unknown GLSL type");
5381 }
5382 }
5383
5384 static LLVMTypeRef
5385 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5386 const struct glsl_type *type)
5387 {
5388 if (glsl_type_is_scalar(type)) {
5389 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5390 }
5391
5392 if (glsl_type_is_vector(type)) {
5393 return LLVMVectorType(
5394 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5395 glsl_get_vector_elements(type));
5396 }
5397
5398 if (glsl_type_is_matrix(type)) {
5399 return LLVMArrayType(
5400 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5401 glsl_get_matrix_columns(type));
5402 }
5403
5404 if (glsl_type_is_array(type)) {
5405 return LLVMArrayType(
5406 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5407 glsl_get_length(type));
5408 }
5409
5410 assert(glsl_type_is_struct(type));
5411
5412 LLVMTypeRef member_types[glsl_get_length(type)];
5413
5414 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5415 member_types[i] =
5416 glsl_to_llvm_type(ctx,
5417 glsl_get_struct_field(type, i));
5418 }
5419
5420 return LLVMStructTypeInContext(ctx->context, member_types,
5421 glsl_get_length(type), false);
5422 }
5423
5424 static void
5425 setup_locals(struct ac_nir_context *ctx,
5426 struct nir_function *func)
5427 {
5428 int i, j;
5429 ctx->num_locals = 0;
5430 nir_foreach_variable(variable, &func->impl->locals) {
5431 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5432 variable->data.driver_location = ctx->num_locals * 4;
5433 ctx->num_locals += attrib_count;
5434 }
5435 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5436 if (!ctx->locals)
5437 return;
5438
5439 for (i = 0; i < ctx->num_locals; i++) {
5440 for (j = 0; j < 4; j++) {
5441 ctx->locals[i * 4 + j] =
5442 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5443 }
5444 }
5445 }
5446
5447 static void
5448 setup_shared(struct ac_nir_context *ctx,
5449 struct nir_shader *nir)
5450 {
5451 nir_foreach_variable(variable, &nir->shared) {
5452 LLVMValueRef shared =
5453 LLVMAddGlobalInAddressSpace(
5454 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5455 variable->name ? variable->name : "",
5456 LOCAL_ADDR_SPACE);
5457 _mesa_hash_table_insert(ctx->vars, variable, shared);
5458 }
5459 }
5460
5461 static LLVMValueRef
5462 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5463 {
5464 v = ac_to_float(ctx, v);
5465 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5466 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5467 }
5468
5469
5470 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5471 LLVMValueRef src0, LLVMValueRef src1)
5472 {
5473 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5474 LLVMValueRef comp[2];
5475
5476 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5477 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5478 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5479 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5480 }
5481
5482 /* Initialize arguments for the shader export intrinsic */
5483 static void
5484 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5485 LLVMValueRef *values,
5486 unsigned target,
5487 struct ac_export_args *args)
5488 {
5489 /* Default is 0xf. Adjusted below depending on the format. */
5490 args->enabled_channels = 0xf;
5491
5492 /* Specify whether the EXEC mask represents the valid mask */
5493 args->valid_mask = 0;
5494
5495 /* Specify whether this is the last export */
5496 args->done = 0;
5497
5498 /* Specify the target we are exporting */
5499 args->target = target;
5500
5501 args->compr = false;
5502 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5503 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5504 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5505 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5506
5507 if (!values)
5508 return;
5509
5510 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5511 LLVMValueRef val[4];
5512 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5513 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5514 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5515 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5516
5517 switch(col_format) {
5518 case V_028714_SPI_SHADER_ZERO:
5519 args->enabled_channels = 0; /* writemask */
5520 args->target = V_008DFC_SQ_EXP_NULL;
5521 break;
5522
5523 case V_028714_SPI_SHADER_32_R:
5524 args->enabled_channels = 1;
5525 args->out[0] = values[0];
5526 break;
5527
5528 case V_028714_SPI_SHADER_32_GR:
5529 args->enabled_channels = 0x3;
5530 args->out[0] = values[0];
5531 args->out[1] = values[1];
5532 break;
5533
5534 case V_028714_SPI_SHADER_32_AR:
5535 args->enabled_channels = 0x9;
5536 args->out[0] = values[0];
5537 args->out[3] = values[3];
5538 break;
5539
5540 case V_028714_SPI_SHADER_FP16_ABGR:
5541 args->compr = 1;
5542
5543 for (unsigned chan = 0; chan < 2; chan++) {
5544 LLVMValueRef pack_args[2] = {
5545 values[2 * chan],
5546 values[2 * chan + 1]
5547 };
5548 LLVMValueRef packed;
5549
5550 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5551 args->out[chan] = packed;
5552 }
5553 break;
5554
5555 case V_028714_SPI_SHADER_UNORM16_ABGR:
5556 for (unsigned chan = 0; chan < 4; chan++) {
5557 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5558 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5559 LLVMConstReal(ctx->ac.f32, 65535), "");
5560 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5561 LLVMConstReal(ctx->ac.f32, 0.5), "");
5562 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5563 ctx->ac.i32, "");
5564 }
5565
5566 args->compr = 1;
5567 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5568 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5569 break;
5570
5571 case V_028714_SPI_SHADER_SNORM16_ABGR:
5572 for (unsigned chan = 0; chan < 4; chan++) {
5573 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5574 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5575 LLVMConstReal(ctx->ac.f32, 32767), "");
5576
5577 /* If positive, add 0.5, else add -0.5. */
5578 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5579 LLVMBuildSelect(ctx->builder,
5580 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5581 val[chan], ctx->ac.f32_0, ""),
5582 LLVMConstReal(ctx->ac.f32, 0.5),
5583 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5584 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5585 }
5586
5587 args->compr = 1;
5588 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5589 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5590 break;
5591
5592 case V_028714_SPI_SHADER_UINT16_ABGR: {
5593 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5594 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5595 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5596
5597 for (unsigned chan = 0; chan < 4; chan++) {
5598 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5599 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5600 }
5601
5602 args->compr = 1;
5603 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5604 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5605 break;
5606 }
5607
5608 case V_028714_SPI_SHADER_SINT16_ABGR: {
5609 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5610 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5611 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5612 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5613 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5614 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5615
5616 /* Clamp. */
5617 for (unsigned chan = 0; chan < 4; chan++) {
5618 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5619 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5620 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5621 }
5622
5623 args->compr = 1;
5624 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5625 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5626 break;
5627 }
5628
5629 default:
5630 case V_028714_SPI_SHADER_32_ABGR:
5631 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5632 break;
5633 }
5634 } else
5635 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5636
5637 for (unsigned i = 0; i < 4; ++i)
5638 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5639 }
5640
5641 static void
5642 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5643 bool export_prim_id,
5644 struct ac_vs_output_info *outinfo)
5645 {
5646 uint32_t param_count = 0;
5647 unsigned target;
5648 unsigned pos_idx, num_pos_exports = 0;
5649 struct ac_export_args args, pos_args[4] = {};
5650 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5651 int i;
5652
5653 if (ctx->options->key.has_multiview_view_index) {
5654 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5655 if(!*tmp_out) {
5656 for(unsigned i = 0; i < 4; ++i)
5657 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5658 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5659 }
5660
5661 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5662 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5663 }
5664
5665 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5666 sizeof(outinfo->vs_output_param_offset));
5667
5668 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5669 LLVMValueRef slots[8];
5670 unsigned j;
5671
5672 if (outinfo->cull_dist_mask)
5673 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5674
5675 i = VARYING_SLOT_CLIP_DIST0;
5676 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5677 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5678 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5679
5680 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5681 slots[i] = LLVMGetUndef(ctx->ac.f32);
5682
5683 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5684 target = V_008DFC_SQ_EXP_POS + 3;
5685 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5686 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5687 &args, sizeof(args));
5688 }
5689
5690 target = V_008DFC_SQ_EXP_POS + 2;
5691 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5692 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5693 &args, sizeof(args));
5694
5695 }
5696
5697 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5698 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5699 for (unsigned j = 0; j < 4; j++)
5700 pos_values[j] = LLVMBuildLoad(ctx->builder,
5701 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5702 }
5703 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5704
5705 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5706 outinfo->writes_pointsize = true;
5707 psize_value = LLVMBuildLoad(ctx->builder,
5708 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5709 }
5710
5711 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5712 outinfo->writes_layer = true;
5713 layer_value = LLVMBuildLoad(ctx->builder,
5714 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5715 }
5716
5717 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5718 outinfo->writes_viewport_index = true;
5719 viewport_index_value = LLVMBuildLoad(ctx->builder,
5720 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5721 }
5722
5723 if (outinfo->writes_pointsize ||
5724 outinfo->writes_layer ||
5725 outinfo->writes_viewport_index) {
5726 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5727 (outinfo->writes_layer == true ? 4 : 0));
5728 pos_args[1].valid_mask = 0;
5729 pos_args[1].done = 0;
5730 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5731 pos_args[1].compr = 0;
5732 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5733 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5734 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5735 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5736
5737 if (outinfo->writes_pointsize == true)
5738 pos_args[1].out[0] = psize_value;
5739 if (outinfo->writes_layer == true)
5740 pos_args[1].out[2] = layer_value;
5741 if (outinfo->writes_viewport_index == true) {
5742 if (ctx->options->chip_class >= GFX9) {
5743 /* GFX9 has the layer in out.z[10:0] and the viewport
5744 * index in out.z[19:16].
5745 */
5746 LLVMValueRef v = viewport_index_value;
5747 v = ac_to_integer(&ctx->ac, v);
5748 v = LLVMBuildShl(ctx->builder, v,
5749 LLVMConstInt(ctx->ac.i32, 16, false),
5750 "");
5751 v = LLVMBuildOr(ctx->builder, v,
5752 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5753
5754 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5755 pos_args[1].enabled_channels |= 1 << 2;
5756 } else {
5757 pos_args[1].out[3] = viewport_index_value;
5758 pos_args[1].enabled_channels |= 1 << 3;
5759 }
5760 }
5761 }
5762 for (i = 0; i < 4; i++) {
5763 if (pos_args[i].out[0])
5764 num_pos_exports++;
5765 }
5766
5767 pos_idx = 0;
5768 for (i = 0; i < 4; i++) {
5769 if (!pos_args[i].out[0])
5770 continue;
5771
5772 /* Specify the target we are exporting */
5773 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5774 if (pos_idx == num_pos_exports)
5775 pos_args[i].done = 1;
5776 ac_build_export(&ctx->ac, &pos_args[i]);
5777 }
5778
5779 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5780 LLVMValueRef values[4];
5781 if (!(ctx->output_mask & (1ull << i)))
5782 continue;
5783
5784 for (unsigned j = 0; j < 4; j++)
5785 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5786 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5787
5788 if (i == VARYING_SLOT_LAYER) {
5789 target = V_008DFC_SQ_EXP_PARAM + param_count;
5790 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5791 param_count++;
5792 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5793 target = V_008DFC_SQ_EXP_PARAM + param_count;
5794 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5795 param_count++;
5796 } else if (i >= VARYING_SLOT_VAR0) {
5797 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5798 target = V_008DFC_SQ_EXP_PARAM + param_count;
5799 outinfo->vs_output_param_offset[i] = param_count;
5800 param_count++;
5801 } else
5802 continue;
5803
5804 si_llvm_init_export_args(ctx, values, target, &args);
5805
5806 if (target >= V_008DFC_SQ_EXP_POS &&
5807 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5808 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5809 &args, sizeof(args));
5810 } else {
5811 ac_build_export(&ctx->ac, &args);
5812 }
5813 }
5814
5815 if (export_prim_id) {
5816 LLVMValueRef values[4];
5817 target = V_008DFC_SQ_EXP_PARAM + param_count;
5818 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5819 param_count++;
5820
5821 values[0] = ctx->vs_prim_id;
5822 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5823 ctx->shader_info->vs.vgpr_comp_cnt);
5824 for (unsigned j = 1; j < 4; j++)
5825 values[j] = ctx->ac.f32_0;
5826 si_llvm_init_export_args(ctx, values, target, &args);
5827 ac_build_export(&ctx->ac, &args);
5828 outinfo->export_prim_id = true;
5829 }
5830
5831 outinfo->pos_exports = num_pos_exports;
5832 outinfo->param_exports = param_count;
5833 }
5834
5835 static void
5836 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5837 struct ac_es_output_info *outinfo)
5838 {
5839 int j;
5840 uint64_t max_output_written = 0;
5841 LLVMValueRef lds_base = NULL;
5842
5843 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5844 int param_index;
5845 int length = 4;
5846
5847 if (!(ctx->output_mask & (1ull << i)))
5848 continue;
5849
5850 if (i == VARYING_SLOT_CLIP_DIST0)
5851 length = ctx->num_output_clips + ctx->num_output_culls;
5852
5853 param_index = shader_io_get_unique_index(i);
5854
5855 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5856 }
5857
5858 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5859
5860 if (ctx->ac.chip_class >= GFX9) {
5861 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5862 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5863 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5864 LLVMConstInt(ctx->ac.i32, 24, false),
5865 LLVMConstInt(ctx->ac.i32, 4, false), false);
5866 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5867 LLVMBuildMul(ctx->ac.builder, wave_idx,
5868 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5869 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5870 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5871 }
5872
5873 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5874 LLVMValueRef dw_addr;
5875 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5876 int param_index;
5877 int length = 4;
5878
5879 if (!(ctx->output_mask & (1ull << i)))
5880 continue;
5881
5882 if (i == VARYING_SLOT_CLIP_DIST0)
5883 length = ctx->num_output_clips + ctx->num_output_culls;
5884
5885 param_index = shader_io_get_unique_index(i);
5886
5887 if (lds_base) {
5888 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5889 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5890 "");
5891 }
5892 for (j = 0; j < length; j++) {
5893 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5894 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5895
5896 if (ctx->ac.chip_class >= GFX9) {
5897 ac_lds_store(&ctx->ac, dw_addr,
5898 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5899 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5900 } else {
5901 ac_build_buffer_store_dword(&ctx->ac,
5902 ctx->esgs_ring,
5903 out_val, 1,
5904 NULL, ctx->es2gs_offset,
5905 (4 * param_index + j) * 4,
5906 1, 1, true, true);
5907 }
5908 }
5909 }
5910 }
5911
5912 static void
5913 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5914 {
5915 LLVMValueRef vertex_id = ctx->rel_auto_id;
5916 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5917 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5918 vertex_dw_stride, "");
5919
5920 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5921 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5922 int length = 4;
5923
5924 if (!(ctx->output_mask & (1ull << i)))
5925 continue;
5926
5927 if (i == VARYING_SLOT_CLIP_DIST0)
5928 length = ctx->num_output_clips + ctx->num_output_culls;
5929 int param = shader_io_get_unique_index(i);
5930 mark_tess_output(ctx, false, param);
5931 if (length > 4)
5932 mark_tess_output(ctx, false, param + 1);
5933 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5934 LLVMConstInt(ctx->ac.i32, param * 4, false),
5935 "");
5936 for (unsigned j = 0; j < length; j++) {
5937 ac_lds_store(&ctx->ac, dw_addr,
5938 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5939 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5940 }
5941 }
5942 }
5943
5944 struct ac_build_if_state
5945 {
5946 struct nir_to_llvm_context *ctx;
5947 LLVMValueRef condition;
5948 LLVMBasicBlockRef entry_block;
5949 LLVMBasicBlockRef true_block;
5950 LLVMBasicBlockRef false_block;
5951 LLVMBasicBlockRef merge_block;
5952 };
5953
5954 static LLVMBasicBlockRef
5955 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5956 {
5957 LLVMBasicBlockRef current_block;
5958 LLVMBasicBlockRef next_block;
5959 LLVMBasicBlockRef new_block;
5960
5961 /* get current basic block */
5962 current_block = LLVMGetInsertBlock(ctx->builder);
5963
5964 /* chqeck if there's another block after this one */
5965 next_block = LLVMGetNextBasicBlock(current_block);
5966 if (next_block) {
5967 /* insert the new block before the next block */
5968 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5969 }
5970 else {
5971 /* append new block after current block */
5972 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5973 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5974 }
5975 return new_block;
5976 }
5977
5978 static void
5979 ac_nir_build_if(struct ac_build_if_state *ifthen,
5980 struct nir_to_llvm_context *ctx,
5981 LLVMValueRef condition)
5982 {
5983 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5984
5985 memset(ifthen, 0, sizeof *ifthen);
5986 ifthen->ctx = ctx;
5987 ifthen->condition = condition;
5988 ifthen->entry_block = block;
5989
5990 /* create endif/merge basic block for the phi functions */
5991 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5992
5993 /* create/insert true_block before merge_block */
5994 ifthen->true_block =
5995 LLVMInsertBasicBlockInContext(ctx->context,
5996 ifthen->merge_block,
5997 "if-true-block");
5998
5999 /* successive code goes into the true block */
6000 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6001 }
6002
6003 /**
6004 * End a conditional.
6005 */
6006 static void
6007 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6008 {
6009 LLVMBuilderRef builder = ifthen->ctx->builder;
6010
6011 /* Insert branch to the merge block from current block */
6012 LLVMBuildBr(builder, ifthen->merge_block);
6013
6014 /*
6015 * Now patch in the various branch instructions.
6016 */
6017
6018 /* Insert the conditional branch instruction at the end of entry_block */
6019 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6020 if (ifthen->false_block) {
6021 /* we have an else clause */
6022 LLVMBuildCondBr(builder, ifthen->condition,
6023 ifthen->true_block, ifthen->false_block);
6024 }
6025 else {
6026 /* no else clause */
6027 LLVMBuildCondBr(builder, ifthen->condition,
6028 ifthen->true_block, ifthen->merge_block);
6029 }
6030
6031 /* Resume building code at end of the ifthen->merge_block */
6032 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6033 }
6034
6035 static void
6036 write_tess_factors(struct nir_to_llvm_context *ctx)
6037 {
6038 unsigned stride, outer_comps, inner_comps;
6039 struct ac_build_if_state if_ctx, inner_if_ctx;
6040 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6041 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6042 unsigned tess_inner_index, tess_outer_index;
6043 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6044 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6045 int i;
6046 emit_barrier(ctx);
6047
6048 switch (ctx->options->key.tcs.primitive_mode) {
6049 case GL_ISOLINES:
6050 stride = 2;
6051 outer_comps = 2;
6052 inner_comps = 0;
6053 break;
6054 case GL_TRIANGLES:
6055 stride = 4;
6056 outer_comps = 3;
6057 inner_comps = 1;
6058 break;
6059 case GL_QUADS:
6060 stride = 6;
6061 outer_comps = 4;
6062 inner_comps = 2;
6063 break;
6064 default:
6065 return;
6066 }
6067
6068 ac_nir_build_if(&if_ctx, ctx,
6069 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6070 invocation_id, ctx->ac.i32_0, ""));
6071
6072 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6073 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6074
6075 mark_tess_output(ctx, true, tess_inner_index);
6076 mark_tess_output(ctx, true, tess_outer_index);
6077 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6078 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6079 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6080 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6081 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6082
6083 for (i = 0; i < 4; i++) {
6084 inner[i] = LLVMGetUndef(ctx->ac.i32);
6085 outer[i] = LLVMGetUndef(ctx->ac.i32);
6086 }
6087
6088 // LINES reverseal
6089 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6090 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6091 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6092 ctx->ac.i32_1, "");
6093 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6094 } else {
6095 for (i = 0; i < outer_comps; i++) {
6096 outer[i] = out[i] =
6097 ac_lds_load(&ctx->ac, lds_outer);
6098 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6099 ctx->ac.i32_1, "");
6100 }
6101 for (i = 0; i < inner_comps; i++) {
6102 inner[i] = out[outer_comps+i] =
6103 ac_lds_load(&ctx->ac, lds_inner);
6104 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6105 ctx->ac.i32_1, "");
6106 }
6107 }
6108
6109 /* Convert the outputs to vectors for stores. */
6110 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6111 vec1 = NULL;
6112
6113 if (stride > 4)
6114 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6115
6116
6117 buffer = ctx->hs_ring_tess_factor;
6118 tf_base = ctx->tess_factor_offset;
6119 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6120 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6121 unsigned tf_offset = 0;
6122
6123 if (ctx->options->chip_class <= VI) {
6124 ac_nir_build_if(&inner_if_ctx, ctx,
6125 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6126 rel_patch_id, ctx->ac.i32_0, ""));
6127
6128 /* Store the dynamic HS control word. */
6129 ac_build_buffer_store_dword(&ctx->ac, buffer,
6130 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6131 1, ctx->ac.i32_0, tf_base,
6132 0, 1, 0, true, false);
6133 tf_offset += 4;
6134
6135 ac_nir_build_endif(&inner_if_ctx);
6136 }
6137
6138 /* Store the tessellation factors. */
6139 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6140 MIN2(stride, 4), byteoffset, tf_base,
6141 tf_offset, 1, 0, true, false);
6142 if (vec1)
6143 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6144 stride - 4, byteoffset, tf_base,
6145 16 + tf_offset, 1, 0, true, false);
6146
6147 //store to offchip for TES to read - only if TES reads them
6148 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6149 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6150 LLVMValueRef tf_inner_offset;
6151 unsigned param_outer, param_inner;
6152
6153 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6154 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6155 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6156
6157 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6158 util_next_power_of_two(outer_comps));
6159
6160 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6161 outer_comps, tf_outer_offset,
6162 ctx->oc_lds, 0, 1, 0, true, false);
6163 if (inner_comps) {
6164 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6165 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6166 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6167
6168 inner_vec = inner_comps == 1 ? inner[0] :
6169 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6170 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6171 inner_comps, tf_inner_offset,
6172 ctx->oc_lds, 0, 1, 0, true, false);
6173 }
6174 }
6175 ac_nir_build_endif(&if_ctx);
6176 }
6177
6178 static void
6179 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6180 {
6181 write_tess_factors(ctx);
6182 }
6183
6184 static bool
6185 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6186 LLVMValueRef *color, unsigned param, bool is_last,
6187 struct ac_export_args *args)
6188 {
6189 /* Export */
6190 si_llvm_init_export_args(ctx, color, param,
6191 args);
6192
6193 if (is_last) {
6194 args->valid_mask = 1; /* whether the EXEC mask is valid */
6195 args->done = 1; /* DONE bit */
6196 } else if (!args->enabled_channels)
6197 return false; /* unnecessary NULL export */
6198
6199 return true;
6200 }
6201
6202 static void
6203 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6204 LLVMValueRef depth, LLVMValueRef stencil,
6205 LLVMValueRef samplemask)
6206 {
6207 struct ac_export_args args;
6208
6209 args.enabled_channels = 0;
6210 args.valid_mask = 1;
6211 args.done = 1;
6212 args.target = V_008DFC_SQ_EXP_MRTZ;
6213 args.compr = false;
6214
6215 args.out[0] = LLVMGetUndef(ctx->ac.f32); /* R, depth */
6216 args.out[1] = LLVMGetUndef(ctx->ac.f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6217 args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */
6218 args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */
6219
6220 unsigned format = ac_get_spi_shader_z_format(depth != NULL,
6221 stencil != NULL,
6222 samplemask != NULL);
6223
6224 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
6225 assert(!depth);
6226 args.compr = 1; /* COMPR flag */
6227
6228 if (stencil) {
6229 /* Stencil should be in X[23:16]. */
6230 stencil = ac_to_integer(&ctx->ac, stencil);
6231 stencil = LLVMBuildShl(ctx->builder, stencil,
6232 LLVMConstInt(ctx->ac.i32, 16, 0), "");
6233 args.out[0] = ac_to_float(&ctx->ac, stencil);
6234 args.enabled_channels |= 0x3;
6235 }
6236 if (samplemask) {
6237 /* SampleMask should be in Y[15:0]. */
6238 args.out[1] = samplemask;
6239 args.enabled_channels |= 0xc;
6240 }
6241 } else {
6242 if (depth) {
6243 args.out[0] = depth;
6244 args.enabled_channels |= 0x1;
6245 }
6246
6247 if (stencil) {
6248 args.out[1] = stencil;
6249 args.enabled_channels |= 0x2;
6250 }
6251
6252 if (samplemask) {
6253 args.out[2] = samplemask;
6254 args.enabled_channels |= 0x4;
6255 }
6256 }
6257
6258 /* SI (except OLAND and HAINAN) has a bug that it only looks
6259 * at the X writemask component. */
6260 if (ctx->options->chip_class == SI &&
6261 ctx->options->family != CHIP_OLAND &&
6262 ctx->options->family != CHIP_HAINAN)
6263 args.enabled_channels |= 0x1;
6264
6265 ac_build_export(&ctx->ac, &args);
6266 }
6267
6268 static void
6269 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6270 {
6271 unsigned index = 0;
6272 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6273 struct ac_export_args color_args[8];
6274
6275 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6276 LLVMValueRef values[4];
6277
6278 if (!(ctx->output_mask & (1ull << i)))
6279 continue;
6280
6281 if (i == FRAG_RESULT_DEPTH) {
6282 ctx->shader_info->fs.writes_z = true;
6283 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6284 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6285 } else if (i == FRAG_RESULT_STENCIL) {
6286 ctx->shader_info->fs.writes_stencil = true;
6287 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6288 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6289 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6290 ctx->shader_info->fs.writes_sample_mask = true;
6291 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6292 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6293 } else {
6294 bool last = false;
6295 for (unsigned j = 0; j < 4; j++)
6296 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6297 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6298
6299 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6300 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6301
6302 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6303 if (ret)
6304 index++;
6305 }
6306 }
6307
6308 for (unsigned i = 0; i < index; i++)
6309 ac_build_export(&ctx->ac, &color_args[i]);
6310 if (depth || stencil || samplemask)
6311 si_export_mrt_z(ctx, depth, stencil, samplemask);
6312 else if (!index) {
6313 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6314 ac_build_export(&ctx->ac, &color_args[0]);
6315 }
6316
6317 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6318 }
6319
6320 static void
6321 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6322 {
6323 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6324 }
6325
6326 static void
6327 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6328 LLVMValueRef *addrs)
6329 {
6330 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6331
6332 switch (ctx->stage) {
6333 case MESA_SHADER_VERTEX:
6334 if (ctx->options->key.vs.as_ls)
6335 handle_ls_outputs_post(ctx);
6336 else if (ctx->options->key.vs.as_es)
6337 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6338 else
6339 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6340 &ctx->shader_info->vs.outinfo);
6341 break;
6342 case MESA_SHADER_FRAGMENT:
6343 handle_fs_outputs_post(ctx);
6344 break;
6345 case MESA_SHADER_GEOMETRY:
6346 emit_gs_epilogue(ctx);
6347 break;
6348 case MESA_SHADER_TESS_CTRL:
6349 handle_tcs_outputs_post(ctx);
6350 break;
6351 case MESA_SHADER_TESS_EVAL:
6352 if (ctx->options->key.tes.as_es)
6353 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6354 else
6355 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6356 &ctx->shader_info->tes.outinfo);
6357 break;
6358 default:
6359 break;
6360 }
6361 }
6362
6363 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6364 {
6365 LLVMPassManagerRef passmgr;
6366 /* Create the pass manager */
6367 passmgr = LLVMCreateFunctionPassManagerForModule(
6368 ctx->module);
6369
6370 /* This pass should eliminate all the load and store instructions */
6371 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6372
6373 /* Add some optimization passes */
6374 LLVMAddScalarReplAggregatesPass(passmgr);
6375 LLVMAddLICMPass(passmgr);
6376 LLVMAddAggressiveDCEPass(passmgr);
6377 LLVMAddCFGSimplificationPass(passmgr);
6378 LLVMAddInstructionCombiningPass(passmgr);
6379
6380 /* Run the pass */
6381 LLVMInitializeFunctionPassManager(passmgr);
6382 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6383 LLVMFinalizeFunctionPassManager(passmgr);
6384
6385 LLVMDisposeBuilder(ctx->builder);
6386 LLVMDisposePassManager(passmgr);
6387 }
6388
6389 static void
6390 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6391 {
6392 struct ac_vs_output_info *outinfo;
6393
6394 switch (ctx->stage) {
6395 case MESA_SHADER_FRAGMENT:
6396 case MESA_SHADER_COMPUTE:
6397 case MESA_SHADER_TESS_CTRL:
6398 case MESA_SHADER_GEOMETRY:
6399 return;
6400 case MESA_SHADER_VERTEX:
6401 if (ctx->options->key.vs.as_ls ||
6402 ctx->options->key.vs.as_es)
6403 return;
6404 outinfo = &ctx->shader_info->vs.outinfo;
6405 break;
6406 case MESA_SHADER_TESS_EVAL:
6407 if (ctx->options->key.vs.as_es)
6408 return;
6409 outinfo = &ctx->shader_info->tes.outinfo;
6410 break;
6411 default:
6412 unreachable("Unhandled shader type");
6413 }
6414
6415 ac_optimize_vs_outputs(&ctx->ac,
6416 ctx->main_function,
6417 outinfo->vs_output_param_offset,
6418 VARYING_SLOT_MAX,
6419 &outinfo->param_exports);
6420 }
6421
6422 static void
6423 ac_setup_rings(struct nir_to_llvm_context *ctx)
6424 {
6425 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6426 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6427 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6428 }
6429
6430 if (ctx->is_gs_copy_shader) {
6431 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6432 }
6433 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6434 LLVMValueRef tmp;
6435 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6436 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6437
6438 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6439
6440 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6441 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6442 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6443 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6444 }
6445
6446 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6447 ctx->stage == MESA_SHADER_TESS_EVAL) {
6448 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6449 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6450 }
6451 }
6452
6453 static unsigned
6454 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6455 const struct nir_shader *nir)
6456 {
6457 switch (nir->info.stage) {
6458 case MESA_SHADER_TESS_CTRL:
6459 return chip_class >= CIK ? 128 : 64;
6460 case MESA_SHADER_GEOMETRY:
6461 return chip_class >= GFX9 ? 128 : 64;
6462 case MESA_SHADER_COMPUTE:
6463 break;
6464 default:
6465 return 0;
6466 }
6467
6468 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6469 nir->info.cs.local_size[1] *
6470 nir->info.cs.local_size[2];
6471 return max_workgroup_size;
6472 }
6473
6474 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6475 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6476 {
6477 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6478 LLVMConstInt(ctx->ac.i32, 8, false),
6479 LLVMConstInt(ctx->ac.i32, 8, false), false);
6480 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6481 ctx->ac.i32_0, "");
6482 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6483 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6484 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6485 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6486 }
6487
6488 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6489 {
6490 for(int i = 5; i >= 0; --i) {
6491 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6492 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6493 LLVMConstInt(ctx->ac.i32, 16, false), false);
6494 }
6495
6496 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6497 LLVMConstInt(ctx->ac.i32, 16, false),
6498 LLVMConstInt(ctx->ac.i32, 8, false), false);
6499 }
6500
6501 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6502 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6503 {
6504 struct ac_nir_context ctx = {};
6505 struct nir_function *func;
6506
6507 ctx.ac = *ac;
6508 ctx.abi = abi;
6509
6510 ctx.nctx = nctx;
6511 if (nctx)
6512 nctx->nir = &ctx;
6513
6514 ctx.stage = nir->info.stage;
6515
6516 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6517
6518 nir_foreach_variable(variable, &nir->outputs)
6519 handle_shader_output_decl(&ctx, nir, variable);
6520
6521 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6522 _mesa_key_pointer_equal);
6523 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6524 _mesa_key_pointer_equal);
6525 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6526 _mesa_key_pointer_equal);
6527
6528 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6529
6530 setup_locals(&ctx, func);
6531
6532 if (nir->info.stage == MESA_SHADER_COMPUTE)
6533 setup_shared(&ctx, nir);
6534
6535 visit_cf_list(&ctx, &func->impl->body);
6536 phi_post_pass(&ctx);
6537
6538 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6539 ctx.outputs);
6540
6541 free(ctx.locals);
6542 ralloc_free(ctx.defs);
6543 ralloc_free(ctx.phis);
6544 ralloc_free(ctx.vars);
6545
6546 if (nctx)
6547 nctx->nir = NULL;
6548 }
6549
6550 static
6551 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6552 struct nir_shader *const *shaders,
6553 int shader_count,
6554 struct ac_shader_variant_info *shader_info,
6555 const struct ac_nir_compiler_options *options)
6556 {
6557 struct nir_to_llvm_context ctx = {0};
6558 unsigned i;
6559 ctx.options = options;
6560 ctx.shader_info = shader_info;
6561 ctx.context = LLVMContextCreate();
6562 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6563
6564 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6565 ctx.ac.module = ctx.module;
6566 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6567
6568 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6569 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6570 LLVMSetDataLayout(ctx.module, data_layout_str);
6571 LLVMDisposeTargetData(data_layout);
6572 LLVMDisposeMessage(data_layout_str);
6573
6574 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6575 ctx.ac.builder = ctx.builder;
6576
6577 memset(shader_info, 0, sizeof(*shader_info));
6578
6579 for(int i = 0; i < shader_count; ++i)
6580 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6581
6582 for (i = 0; i < AC_UD_MAX_SETS; i++)
6583 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6584 for (i = 0; i < AC_UD_MAX_UD; i++)
6585 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6586
6587 ctx.max_workgroup_size = 0;
6588 for (int i = 0; i < shader_count; ++i) {
6589 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6590 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6591 shaders[i]));
6592 }
6593
6594 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6595 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6596
6597 ctx.abi.inputs = &ctx.inputs[0];
6598 ctx.abi.emit_outputs = handle_shader_outputs_post;
6599 ctx.abi.emit_vertex = visit_emit_vertex;
6600 ctx.abi.load_ubo = radv_load_ubo;
6601 ctx.abi.load_ssbo = radv_load_ssbo;
6602 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6603 ctx.abi.clamp_shadow_reference = false;
6604
6605 if (shader_count >= 2)
6606 ac_init_exec_full_mask(&ctx.ac);
6607
6608 if (ctx.ac.chip_class == GFX9 &&
6609 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6610 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6611
6612 for(int i = 0; i < shader_count; ++i) {
6613 ctx.stage = shaders[i]->info.stage;
6614 ctx.output_mask = 0;
6615 ctx.tess_outputs_written = 0;
6616 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6617 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6618
6619 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6620 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6621 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6622 ctx.abi.load_inputs = load_gs_input;
6623 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6624 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6625 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6626 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6627 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6628 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6629 if (shader_info->info.vs.needs_instance_id) {
6630 ctx.shader_info->vs.vgpr_comp_cnt =
6631 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6632 }
6633 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6634 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6635 }
6636
6637 if (i)
6638 emit_barrier(&ctx);
6639
6640 ac_setup_rings(&ctx);
6641
6642 LLVMBasicBlockRef merge_block;
6643 if (shader_count >= 2) {
6644 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6645 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6646 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6647
6648 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6649 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6650 LLVMConstInt(ctx.ac.i32, 8, false), false);
6651 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6652 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6653 thread_id, count, "");
6654 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6655
6656 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6657 }
6658
6659 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6660 handle_fs_inputs(&ctx, shaders[i]);
6661 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6662 handle_vs_inputs(&ctx, shaders[i]);
6663 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6664 prepare_gs_input_vgprs(&ctx);
6665
6666 nir_foreach_variable(variable, &shaders[i]->outputs)
6667 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6668
6669 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6670
6671 if (shader_count >= 2) {
6672 LLVMBuildBr(ctx.ac.builder, merge_block);
6673 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6674 }
6675
6676 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6677 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6678 shaders[i]->info.cull_distance_array_size > 4;
6679 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6680 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6681 shaders[i]->info.gs.vertices_out;
6682 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6683 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6684 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6685 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6686 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6687 }
6688 }
6689
6690 LLVMBuildRetVoid(ctx.builder);
6691
6692 ac_llvm_finalize_module(&ctx);
6693
6694 if (shader_count == 1)
6695 ac_nir_eliminate_const_vs_outputs(&ctx);
6696
6697 return ctx.module;
6698 }
6699
6700 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6701 {
6702 unsigned *retval = (unsigned *)context;
6703 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6704 char *description = LLVMGetDiagInfoDescription(di);
6705
6706 if (severity == LLVMDSError) {
6707 *retval = 1;
6708 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6709 description);
6710 }
6711
6712 LLVMDisposeMessage(description);
6713 }
6714
6715 static unsigned ac_llvm_compile(LLVMModuleRef M,
6716 struct ac_shader_binary *binary,
6717 LLVMTargetMachineRef tm)
6718 {
6719 unsigned retval = 0;
6720 char *err;
6721 LLVMContextRef llvm_ctx;
6722 LLVMMemoryBufferRef out_buffer;
6723 unsigned buffer_size;
6724 const char *buffer_data;
6725 LLVMBool mem_err;
6726
6727 /* Setup Diagnostic Handler*/
6728 llvm_ctx = LLVMGetModuleContext(M);
6729
6730 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6731 &retval);
6732
6733 /* Compile IR*/
6734 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6735 &err, &out_buffer);
6736
6737 /* Process Errors/Warnings */
6738 if (mem_err) {
6739 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6740 free(err);
6741 retval = 1;
6742 goto out;
6743 }
6744
6745 /* Extract Shader Code*/
6746 buffer_size = LLVMGetBufferSize(out_buffer);
6747 buffer_data = LLVMGetBufferStart(out_buffer);
6748
6749 ac_elf_read(buffer_data, buffer_size, binary);
6750
6751 /* Clean up */
6752 LLVMDisposeMemoryBuffer(out_buffer);
6753
6754 out:
6755 return retval;
6756 }
6757
6758 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6759 LLVMModuleRef llvm_module,
6760 struct ac_shader_binary *binary,
6761 struct ac_shader_config *config,
6762 struct ac_shader_variant_info *shader_info,
6763 gl_shader_stage stage,
6764 bool dump_shader, bool supports_spill)
6765 {
6766 if (dump_shader)
6767 ac_dump_module(llvm_module);
6768
6769 memset(binary, 0, sizeof(*binary));
6770 int v = ac_llvm_compile(llvm_module, binary, tm);
6771 if (v) {
6772 fprintf(stderr, "compile failed\n");
6773 }
6774
6775 if (dump_shader)
6776 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6777
6778 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6779
6780 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6781 LLVMDisposeModule(llvm_module);
6782 LLVMContextDispose(ctx);
6783
6784 if (stage == MESA_SHADER_FRAGMENT) {
6785 shader_info->num_input_vgprs = 0;
6786 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6787 shader_info->num_input_vgprs += 2;
6788 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6789 shader_info->num_input_vgprs += 2;
6790 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6791 shader_info->num_input_vgprs += 2;
6792 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6793 shader_info->num_input_vgprs += 3;
6794 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6795 shader_info->num_input_vgprs += 2;
6796 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6797 shader_info->num_input_vgprs += 2;
6798 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6799 shader_info->num_input_vgprs += 2;
6800 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6801 shader_info->num_input_vgprs += 1;
6802 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6803 shader_info->num_input_vgprs += 1;
6804 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6805 shader_info->num_input_vgprs += 1;
6806 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6807 shader_info->num_input_vgprs += 1;
6808 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6809 shader_info->num_input_vgprs += 1;
6810 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6811 shader_info->num_input_vgprs += 1;
6812 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6813 shader_info->num_input_vgprs += 1;
6814 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6815 shader_info->num_input_vgprs += 1;
6816 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6817 shader_info->num_input_vgprs += 1;
6818 }
6819 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6820
6821 /* +3 for scratch wave offset and VCC */
6822 config->num_sgprs = MAX2(config->num_sgprs,
6823 shader_info->num_input_sgprs + 3);
6824 }
6825
6826 static void
6827 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6828 {
6829 switch (nir->info.stage) {
6830 case MESA_SHADER_COMPUTE:
6831 for (int i = 0; i < 3; ++i)
6832 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6833 break;
6834 case MESA_SHADER_FRAGMENT:
6835 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6836 break;
6837 case MESA_SHADER_GEOMETRY:
6838 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6839 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6840 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6841 shader_info->gs.invocations = nir->info.gs.invocations;
6842 break;
6843 case MESA_SHADER_TESS_EVAL:
6844 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6845 shader_info->tes.spacing = nir->info.tess.spacing;
6846 shader_info->tes.ccw = nir->info.tess.ccw;
6847 shader_info->tes.point_mode = nir->info.tess.point_mode;
6848 shader_info->tes.as_es = options->key.tes.as_es;
6849 break;
6850 case MESA_SHADER_TESS_CTRL:
6851 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6852 break;
6853 case MESA_SHADER_VERTEX:
6854 shader_info->vs.as_es = options->key.vs.as_es;
6855 shader_info->vs.as_ls = options->key.vs.as_ls;
6856 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6857 if (options->key.vs.as_ls)
6858 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6859 break;
6860 default:
6861 break;
6862 }
6863 }
6864
6865 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6866 struct ac_shader_binary *binary,
6867 struct ac_shader_config *config,
6868 struct ac_shader_variant_info *shader_info,
6869 struct nir_shader *const *nir,
6870 int nir_count,
6871 const struct ac_nir_compiler_options *options,
6872 bool dump_shader)
6873 {
6874
6875 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6876 options);
6877
6878 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6879 for (int i = 0; i < nir_count; ++i)
6880 ac_fill_shader_info(shader_info, nir[i], options);
6881 }
6882
6883 static void
6884 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6885 {
6886 LLVMValueRef args[9];
6887 args[0] = ctx->gsvs_ring;
6888 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6889 args[3] = ctx->ac.i32_0;
6890 args[4] = ctx->ac.i32_1; /* OFFEN */
6891 args[5] = ctx->ac.i32_0; /* IDXEN */
6892 args[6] = ctx->ac.i32_1; /* GLC */
6893 args[7] = ctx->ac.i32_1; /* SLC */
6894 args[8] = ctx->ac.i32_0; /* TFE */
6895
6896 int idx = 0;
6897
6898 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6899 int length = 4;
6900 int slot = idx;
6901 int slot_inc = 1;
6902 if (!(ctx->output_mask & (1ull << i)))
6903 continue;
6904
6905 if (i == VARYING_SLOT_CLIP_DIST0) {
6906 /* unpack clip and cull from a single set of slots */
6907 length = ctx->num_output_clips + ctx->num_output_culls;
6908 if (length > 4)
6909 slot_inc = 2;
6910 }
6911
6912 for (unsigned j = 0; j < length; j++) {
6913 LLVMValueRef value;
6914 args[2] = LLVMConstInt(ctx->ac.i32,
6915 (slot * 4 + j) *
6916 ctx->gs_max_out_vertices * 16 * 4, false);
6917
6918 value = ac_build_intrinsic(&ctx->ac,
6919 "llvm.SI.buffer.load.dword.i32.i32",
6920 ctx->ac.i32, args, 9,
6921 AC_FUNC_ATTR_READONLY |
6922 AC_FUNC_ATTR_LEGACY);
6923
6924 LLVMBuildStore(ctx->builder,
6925 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6926 }
6927 idx += slot_inc;
6928 }
6929 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6930 }
6931
6932 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6933 struct nir_shader *geom_shader,
6934 struct ac_shader_binary *binary,
6935 struct ac_shader_config *config,
6936 struct ac_shader_variant_info *shader_info,
6937 const struct ac_nir_compiler_options *options,
6938 bool dump_shader)
6939 {
6940 struct nir_to_llvm_context ctx = {0};
6941 ctx.context = LLVMContextCreate();
6942 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6943 ctx.options = options;
6944 ctx.shader_info = shader_info;
6945
6946 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6947 ctx.ac.module = ctx.module;
6948
6949 ctx.is_gs_copy_shader = true;
6950 LLVMSetTarget(ctx.module, "amdgcn--");
6951
6952 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6953 ctx.ac.builder = ctx.builder;
6954 ctx.stage = MESA_SHADER_VERTEX;
6955
6956 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6957
6958 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6959 ac_setup_rings(&ctx);
6960
6961 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6962 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6963
6964 struct ac_nir_context nir_ctx = {};
6965 nir_ctx.ac = ctx.ac;
6966 nir_ctx.abi = &ctx.abi;
6967
6968 nir_ctx.nctx = &ctx;
6969 ctx.nir = &nir_ctx;
6970
6971 nir_foreach_variable(variable, &geom_shader->outputs) {
6972 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6973 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6974 }
6975
6976 ac_gs_copy_shader_emit(&ctx);
6977
6978 ctx.nir = NULL;
6979
6980 LLVMBuildRetVoid(ctx.builder);
6981
6982 ac_llvm_finalize_module(&ctx);
6983
6984 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6985 MESA_SHADER_VERTEX,
6986 dump_shader, options->supports_spill);
6987 }