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ac/nir: fix shared atomic operations.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 uint32_t tcs_vertices_per_patch;
131 };
132
133 static inline struct radv_shader_context *
134 radv_shader_context_from_abi(struct ac_shader_abi *abi)
135 {
136 struct radv_shader_context *ctx = NULL;
137 return container_of(abi, ctx, abi);
138 }
139
140 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
141 const nir_deref_var *deref,
142 enum ac_descriptor_type desc_type,
143 const nir_tex_instr *instr,
144 bool image, bool write);
145
146 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
147 {
148 return (index * 4) + chan;
149 }
150
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
152 {
153 /* handle patch indices separate */
154 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
155 return 0;
156 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
157 return 1;
158 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
159 return 2 + (slot - VARYING_SLOT_PATCH0);
160
161 if (slot == VARYING_SLOT_POS)
162 return 0;
163 if (slot == VARYING_SLOT_PSIZ)
164 return 1;
165 if (slot == VARYING_SLOT_CLIP_DIST0)
166 return 2;
167 /* 3 is reserved for clip dist as well */
168 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
169 return 4 + (slot - VARYING_SLOT_VAR0);
170 unreachable("illegal slot in get unique index\n");
171 }
172
173 static void set_llvm_calling_convention(LLVMValueRef func,
174 gl_shader_stage stage)
175 {
176 enum radeon_llvm_calling_convention calling_conv;
177
178 switch (stage) {
179 case MESA_SHADER_VERTEX:
180 case MESA_SHADER_TESS_EVAL:
181 calling_conv = RADEON_LLVM_AMDGPU_VS;
182 break;
183 case MESA_SHADER_GEOMETRY:
184 calling_conv = RADEON_LLVM_AMDGPU_GS;
185 break;
186 case MESA_SHADER_TESS_CTRL:
187 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
188 break;
189 case MESA_SHADER_FRAGMENT:
190 calling_conv = RADEON_LLVM_AMDGPU_PS;
191 break;
192 case MESA_SHADER_COMPUTE:
193 calling_conv = RADEON_LLVM_AMDGPU_CS;
194 break;
195 default:
196 unreachable("Unhandle shader type");
197 }
198
199 LLVMSetFunctionCallConv(func, calling_conv);
200 }
201
202 #define MAX_ARGS 23
203 struct arg_info {
204 LLVMTypeRef types[MAX_ARGS];
205 LLVMValueRef *assign[MAX_ARGS];
206 unsigned array_params_mask;
207 uint8_t count;
208 uint8_t sgpr_count;
209 uint8_t num_sgprs_used;
210 uint8_t num_vgprs_used;
211 };
212
213 enum ac_arg_regfile {
214 ARG_SGPR,
215 ARG_VGPR,
216 };
217
218 static void
219 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
220 LLVMValueRef *param_ptr)
221 {
222 assert(info->count < MAX_ARGS);
223
224 info->assign[info->count] = param_ptr;
225 info->types[info->count] = type;
226 info->count++;
227
228 if (regfile == ARG_SGPR) {
229 info->num_sgprs_used += ac_get_type_size(type) / 4;
230 info->sgpr_count++;
231 } else {
232 assert(regfile == ARG_VGPR);
233 info->num_vgprs_used += ac_get_type_size(type) / 4;
234 }
235 }
236
237 static inline void
238 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
239 {
240 info->array_params_mask |= (1 << info->count);
241 add_arg(info, ARG_SGPR, type, param_ptr);
242 }
243
244 static void assign_arguments(LLVMValueRef main_function,
245 struct arg_info *info)
246 {
247 unsigned i;
248 for (i = 0; i < info->count; i++) {
249 if (info->assign[i])
250 *info->assign[i] = LLVMGetParam(main_function, i);
251 }
252 }
253
254 static LLVMValueRef
255 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
256 LLVMBuilderRef builder, LLVMTypeRef *return_types,
257 unsigned num_return_elems,
258 struct arg_info *args,
259 unsigned max_workgroup_size,
260 bool unsafe_math)
261 {
262 LLVMTypeRef main_function_type, ret_type;
263 LLVMBasicBlockRef main_function_body;
264
265 if (num_return_elems)
266 ret_type = LLVMStructTypeInContext(ctx, return_types,
267 num_return_elems, true);
268 else
269 ret_type = LLVMVoidTypeInContext(ctx);
270
271 /* Setup the function */
272 main_function_type =
273 LLVMFunctionType(ret_type, args->types, args->count, 0);
274 LLVMValueRef main_function =
275 LLVMAddFunction(module, "main", main_function_type);
276 main_function_body =
277 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
278 LLVMPositionBuilderAtEnd(builder, main_function_body);
279
280 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
281 for (unsigned i = 0; i < args->sgpr_count; ++i) {
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
283
284 if (args->array_params_mask & (1 << i)) {
285 LLVMValueRef P = LLVMGetParam(main_function, i);
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
287 ac_add_attr_dereferenceable(P, UINT64_MAX);
288 }
289 }
290
291 if (max_workgroup_size) {
292 ac_llvm_add_target_dep_function_attr(main_function,
293 "amdgpu-max-work-group-size",
294 max_workgroup_size);
295 }
296 if (unsafe_math) {
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "less-precise-fpmad",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "no-infs-fp-math",
303 "true");
304 LLVMAddTargetDependentFunctionAttr(main_function,
305 "no-nans-fp-math",
306 "true");
307 LLVMAddTargetDependentFunctionAttr(main_function,
308 "unsafe-fp-math",
309 "true");
310 LLVMAddTargetDependentFunctionAttr(main_function,
311 "no-signed-zeros-fp-math",
312 "true");
313 }
314 return main_function;
315 }
316
317 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
318 LLVMValueRef param, unsigned rshift,
319 unsigned bitwidth)
320 {
321 LLVMValueRef value = param;
322 if (rshift)
323 value = LLVMBuildLShr(ctx->builder, value,
324 LLVMConstInt(ctx->i32, rshift, false), "");
325
326 if (rshift + bitwidth < 32) {
327 unsigned mask = (1 << bitwidth) - 1;
328 value = LLVMBuildAnd(ctx->builder, value,
329 LLVMConstInt(ctx->i32, mask, false), "");
330 }
331 return value;
332 }
333
334 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
335 {
336 switch (ctx->stage) {
337 case MESA_SHADER_TESS_CTRL:
338 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
339 case MESA_SHADER_TESS_EVAL:
340 return ctx->tes_rel_patch_id;
341 break;
342 default:
343 unreachable("Illegal stage");
344 }
345 }
346
347 /* Tessellation shaders pass outputs to the next shader using LDS.
348 *
349 * LS outputs = TCS inputs
350 * TCS outputs = TES inputs
351 *
352 * The LDS layout is:
353 * - TCS inputs for patch 0
354 * - TCS inputs for patch 1
355 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
356 * - ...
357 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
358 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
359 * - TCS outputs for patch 1
360 * - Per-patch TCS outputs for patch 1
361 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
362 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
363 * - ...
364 *
365 * All three shaders VS(LS), TCS, TES share the same LDS space.
366 */
367 static LLVMValueRef
368 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
369 {
370 if (ctx->stage == MESA_SHADER_VERTEX)
371 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
372 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
373 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
374 else {
375 assert(0);
376 return NULL;
377 }
378 }
379
380 static LLVMValueRef
381 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
382 {
383 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
384 }
385
386 static LLVMValueRef
387 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
388 {
389 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
390 }
391
392 static LLVMValueRef
393 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
394 {
395 return LLVMBuildMul(ctx->ac.builder,
396 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
397 LLVMConstInt(ctx->ac.i32, 4, false), "");
398 }
399
400 static LLVMValueRef
401 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
402 {
403 return LLVMBuildMul(ctx->ac.builder,
404 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
405 LLVMConstInt(ctx->ac.i32, 4, false), "");
406 }
407
408 static LLVMValueRef
409 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
410 {
411 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
412 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
413
414 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
415 }
416
417 static LLVMValueRef
418 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
419 {
420 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
421 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
422 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
423
424 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
425 LLVMBuildMul(ctx->ac.builder, patch_stride,
426 rel_patch_id, ""),
427 "");
428 }
429
430 static LLVMValueRef
431 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
432 {
433 LLVMValueRef patch0_patch_data_offset =
434 get_tcs_out_patch0_patch_data_offset(ctx);
435 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
436 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
437
438 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
439 LLVMBuildMul(ctx->ac.builder, patch_stride,
440 rel_patch_id, ""),
441 "");
442 }
443
444 static void
445 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
446 uint32_t indirect_offset)
447 {
448 ud_info->sgpr_idx = *sgpr_idx;
449 ud_info->num_sgprs = num_sgprs;
450 ud_info->indirect = indirect_offset > 0;
451 ud_info->indirect_offset = indirect_offset;
452 *sgpr_idx += num_sgprs;
453 }
454
455 static void
456 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
457 uint8_t num_sgprs)
458 {
459 struct ac_userdata_info *ud_info =
460 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
461 assert(ud_info);
462
463 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
464 }
465
466 static void
467 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
468 uint32_t indirect_offset)
469 {
470 struct ac_userdata_info *ud_info =
471 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
472 assert(ud_info);
473
474 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
475 }
476
477 struct user_sgpr_info {
478 bool need_ring_offsets;
479 uint8_t sgpr_count;
480 bool indirect_all_descriptor_sets;
481 };
482
483 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
484 gl_shader_stage stage)
485 {
486 switch (stage) {
487 case MESA_SHADER_VERTEX:
488 if (ctx->shader_info->info.needs_multiview_view_index ||
489 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
490 return true;
491 break;
492 case MESA_SHADER_TESS_EVAL:
493 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
494 return true;
495 break;
496 case MESA_SHADER_GEOMETRY:
497 case MESA_SHADER_TESS_CTRL:
498 if (ctx->shader_info->info.needs_multiview_view_index)
499 return true;
500 break;
501 default:
502 break;
503 }
504 return false;
505 }
506
507 static uint8_t
508 count_vs_user_sgprs(struct radv_shader_context *ctx)
509 {
510 uint8_t count = 0;
511
512 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
513 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
514
515 return count;
516 }
517
518 static void allocate_user_sgprs(struct radv_shader_context *ctx,
519 gl_shader_stage stage,
520 bool has_previous_stage,
521 gl_shader_stage previous_stage,
522 bool needs_view_index,
523 struct user_sgpr_info *user_sgpr_info)
524 {
525 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
526
527 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
528 if (stage == MESA_SHADER_GEOMETRY ||
529 stage == MESA_SHADER_VERTEX ||
530 stage == MESA_SHADER_TESS_CTRL ||
531 stage == MESA_SHADER_TESS_EVAL ||
532 ctx->is_gs_copy_shader)
533 user_sgpr_info->need_ring_offsets = true;
534
535 if (stage == MESA_SHADER_FRAGMENT &&
536 ctx->shader_info->info.ps.needs_sample_positions)
537 user_sgpr_info->need_ring_offsets = true;
538
539 /* 2 user sgprs will nearly always be allocated for scratch/rings */
540 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
541 user_sgpr_info->sgpr_count += 2;
542 }
543
544 switch (stage) {
545 case MESA_SHADER_COMPUTE:
546 if (ctx->shader_info->info.cs.uses_grid_size)
547 user_sgpr_info->sgpr_count += 3;
548 break;
549 case MESA_SHADER_FRAGMENT:
550 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
551 break;
552 case MESA_SHADER_VERTEX:
553 if (!ctx->is_gs_copy_shader)
554 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
555 if (ctx->options->key.vs.as_ls)
556 user_sgpr_info->sgpr_count++;
557 break;
558 case MESA_SHADER_TESS_CTRL:
559 if (has_previous_stage) {
560 if (previous_stage == MESA_SHADER_VERTEX)
561 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
562 user_sgpr_info->sgpr_count++;
563 }
564 user_sgpr_info->sgpr_count += 4;
565 break;
566 case MESA_SHADER_TESS_EVAL:
567 user_sgpr_info->sgpr_count += 1;
568 break;
569 case MESA_SHADER_GEOMETRY:
570 if (has_previous_stage) {
571 if (previous_stage == MESA_SHADER_VERTEX) {
572 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
573 } else {
574 user_sgpr_info->sgpr_count++;
575 }
576 }
577 user_sgpr_info->sgpr_count += 2;
578 break;
579 default:
580 break;
581 }
582
583 if (needs_view_index)
584 user_sgpr_info->sgpr_count++;
585
586 if (ctx->shader_info->info.loads_push_constants)
587 user_sgpr_info->sgpr_count += 2;
588
589 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
590 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
591
592 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
593 user_sgpr_info->sgpr_count += 2;
594 user_sgpr_info->indirect_all_descriptor_sets = true;
595 } else {
596 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
597 }
598 }
599
600 static void
601 declare_global_input_sgprs(struct radv_shader_context *ctx,
602 gl_shader_stage stage,
603 bool has_previous_stage,
604 gl_shader_stage previous_stage,
605 const struct user_sgpr_info *user_sgpr_info,
606 struct arg_info *args,
607 LLVMValueRef *desc_sets)
608 {
609 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
610 unsigned num_sets = ctx->options->layout ?
611 ctx->options->layout->num_sets : 0;
612 unsigned stage_mask = 1 << stage;
613
614 if (has_previous_stage)
615 stage_mask |= 1 << previous_stage;
616
617 /* 1 for each descriptor set */
618 if (!user_sgpr_info->indirect_all_descriptor_sets) {
619 for (unsigned i = 0; i < num_sets; ++i) {
620 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
621 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
622 add_array_arg(args, type,
623 &ctx->descriptor_sets[i]);
624 }
625 }
626 } else {
627 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
628 }
629
630 if (ctx->shader_info->info.loads_push_constants) {
631 /* 1 for push constants and dynamic descriptors */
632 add_array_arg(args, type, &ctx->abi.push_constants);
633 }
634 }
635
636 static void
637 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
638 gl_shader_stage stage,
639 bool has_previous_stage,
640 gl_shader_stage previous_stage,
641 struct arg_info *args)
642 {
643 if (!ctx->is_gs_copy_shader &&
644 (stage == MESA_SHADER_VERTEX ||
645 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
646 if (ctx->shader_info->info.vs.has_vertex_buffers) {
647 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
648 &ctx->vertex_buffers);
649 }
650 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
651 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
652 if (ctx->shader_info->info.vs.needs_draw_id) {
653 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
654 }
655 }
656 }
657
658 static void
659 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
660 {
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
662 if (!ctx->is_gs_copy_shader) {
663 if (ctx->options->key.vs.as_ls) {
664 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
665 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
666 } else {
667 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
668 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
669 }
670 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
671 }
672 }
673
674 static void
675 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
676 {
677 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
678 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
679 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
681 }
682
683 static void
684 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
685 bool has_previous_stage, gl_shader_stage previous_stage,
686 const struct user_sgpr_info *user_sgpr_info,
687 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
688 {
689 unsigned num_sets = ctx->options->layout ?
690 ctx->options->layout->num_sets : 0;
691 unsigned stage_mask = 1 << stage;
692
693 if (has_previous_stage)
694 stage_mask |= 1 << previous_stage;
695
696 if (!user_sgpr_info->indirect_all_descriptor_sets) {
697 for (unsigned i = 0; i < num_sets; ++i) {
698 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
699 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
700 set_loc_desc(ctx, i, user_sgpr_idx, 0);
701 } else
702 ctx->descriptor_sets[i] = NULL;
703 }
704 } else {
705 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
706 user_sgpr_idx, 2);
707
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
710 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
712 ctx->descriptor_sets[i] =
713 ac_build_load_to_sgpr(&ctx->ac,
714 desc_sets,
715 LLVMConstInt(ctx->ac.i32, i, false));
716
717 } else
718 ctx->descriptor_sets[i] = NULL;
719 }
720 ctx->shader_info->need_indirect_descriptor_sets = true;
721 }
722
723 if (ctx->shader_info->info.loads_push_constants) {
724 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
725 }
726 }
727
728 static void
729 set_vs_specific_input_locs(struct radv_shader_context *ctx,
730 gl_shader_stage stage, bool has_previous_stage,
731 gl_shader_stage previous_stage,
732 uint8_t *user_sgpr_idx)
733 {
734 if (!ctx->is_gs_copy_shader &&
735 (stage == MESA_SHADER_VERTEX ||
736 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
737 if (ctx->shader_info->info.vs.has_vertex_buffers) {
738 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
739 user_sgpr_idx, 2);
740 }
741
742 unsigned vs_num = 2;
743 if (ctx->shader_info->info.vs.needs_draw_id)
744 vs_num++;
745
746 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
747 user_sgpr_idx, vs_num);
748 }
749 }
750
751 static void create_function(struct radv_shader_context *ctx,
752 gl_shader_stage stage,
753 bool has_previous_stage,
754 gl_shader_stage previous_stage)
755 {
756 uint8_t user_sgpr_idx;
757 struct user_sgpr_info user_sgpr_info;
758 struct arg_info args = {};
759 LLVMValueRef desc_sets;
760 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
761 allocate_user_sgprs(ctx, stage, has_previous_stage,
762 previous_stage, needs_view_index, &user_sgpr_info);
763
764 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
765 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
766 &ctx->ring_offsets);
767 }
768
769 switch (stage) {
770 case MESA_SHADER_COMPUTE:
771 declare_global_input_sgprs(ctx, stage, has_previous_stage,
772 previous_stage, &user_sgpr_info,
773 &args, &desc_sets);
774
775 if (ctx->shader_info->info.cs.uses_grid_size) {
776 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
777 &ctx->abi.num_work_groups);
778 }
779
780 for (int i = 0; i < 3; i++) {
781 ctx->abi.workgroup_ids[i] = NULL;
782 if (ctx->shader_info->info.cs.uses_block_id[i]) {
783 add_arg(&args, ARG_SGPR, ctx->ac.i32,
784 &ctx->abi.workgroup_ids[i]);
785 }
786 }
787
788 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
789 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
790 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
791 &ctx->abi.local_invocation_ids);
792 break;
793 case MESA_SHADER_VERTEX:
794 declare_global_input_sgprs(ctx, stage, has_previous_stage,
795 previous_stage, &user_sgpr_info,
796 &args, &desc_sets);
797 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &args);
799
800 if (needs_view_index)
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->abi.view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (needs_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->abi.view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->abi.tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (needs_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->abi.view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->abi.tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (needs_view_index)
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->abi.view_index);
892
893 if (ctx->options->key.tes.as_es) {
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->es2gs_offset);
898 } else {
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 }
902 declare_tes_input_vgprs(ctx, &args);
903 break;
904 case MESA_SHADER_GEOMETRY:
905 if (has_previous_stage) {
906 // First 6 system regs
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->gs2vs_offset);
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->merged_wave_info);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
912
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
916
917 declare_global_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &user_sgpr_info, &args,
921 &desc_sets);
922
923 if (previous_stage == MESA_SHADER_TESS_EVAL) {
924 add_arg(&args, ARG_SGPR, ctx->ac.i32,
925 &ctx->tcs_offchip_layout);
926 } else {
927 declare_vs_specific_input_sgprs(ctx, stage,
928 has_previous_stage,
929 previous_stage,
930 &args);
931 }
932
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->gsvs_ring_stride);
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_num_entries);
937 if (needs_view_index)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->abi.view_index);
940
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->gs_vtx_offset[0]);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[2]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->abi.gs_prim_id);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_invocation_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[4]);
951
952 if (previous_stage == MESA_SHADER_VERTEX) {
953 declare_vs_input_vgprs(ctx, &args);
954 } else {
955 declare_tes_input_vgprs(ctx, &args);
956 }
957 } else {
958 declare_global_input_sgprs(ctx, stage,
959 has_previous_stage,
960 previous_stage,
961 &user_sgpr_info, &args,
962 &desc_sets);
963
964 add_arg(&args, ARG_SGPR, ctx->ac.i32,
965 &ctx->gsvs_ring_stride);
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_num_entries);
968 if (needs_view_index)
969 add_arg(&args, ARG_SGPR, ctx->ac.i32,
970 &ctx->abi.view_index);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
973 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[0]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[1]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->abi.gs_prim_id);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[2]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[3]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[4]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[5]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->abi.gs_invocation_id);
990 }
991 break;
992 case MESA_SHADER_FRAGMENT:
993 declare_global_input_sgprs(ctx, stage, has_previous_stage,
994 previous_stage, &user_sgpr_info,
995 &args, &desc_sets);
996
997 if (ctx->shader_info->info.ps.needs_sample_positions)
998 add_arg(&args, ARG_SGPR, ctx->ac.i32,
999 &ctx->sample_pos_offset);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1018 break;
1019 default:
1020 unreachable("Shader stage not implemented");
1021 }
1022
1023 ctx->main_function = create_llvm_function(
1024 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1025 ctx->max_workgroup_size,
1026 ctx->options->unsafe_math);
1027 set_llvm_calling_convention(ctx->main_function, stage);
1028
1029
1030 ctx->shader_info->num_input_vgprs = 0;
1031 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1032
1033 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1034
1035 if (ctx->stage != MESA_SHADER_FRAGMENT)
1036 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1037
1038 assign_arguments(ctx->main_function, &args);
1039
1040 user_sgpr_idx = 0;
1041
1042 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1043 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1044 &user_sgpr_idx, 2);
1045 if (ctx->options->supports_spill) {
1046 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1048 NULL, 0, AC_FUNC_ATTR_READNONE);
1049 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1050 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1051 }
1052 }
1053
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage)
1057 user_sgpr_idx = 0;
1058
1059 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1060 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1061
1062 switch (stage) {
1063 case MESA_SHADER_COMPUTE:
1064 if (ctx->shader_info->info.cs.uses_grid_size) {
1065 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1066 &user_sgpr_idx, 3);
1067 }
1068 break;
1069 case MESA_SHADER_VERTEX:
1070 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1071 previous_stage, &user_sgpr_idx);
1072 if (ctx->abi.view_index)
1073 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1074 if (ctx->options->key.vs.as_ls) {
1075 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1076 &user_sgpr_idx, 1);
1077 }
1078 break;
1079 case MESA_SHADER_TESS_CTRL:
1080 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1081 previous_stage, &user_sgpr_idx);
1082 if (has_previous_stage)
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1086 if (ctx->abi.view_index)
1087 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1088 break;
1089 case MESA_SHADER_TESS_EVAL:
1090 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1091 if (ctx->abi.view_index)
1092 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1093 break;
1094 case MESA_SHADER_GEOMETRY:
1095 if (has_previous_stage) {
1096 if (previous_stage == MESA_SHADER_VERTEX)
1097 set_vs_specific_input_locs(ctx, stage,
1098 has_previous_stage,
1099 previous_stage,
1100 &user_sgpr_idx);
1101 else
1102 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1103 &user_sgpr_idx, 1);
1104 }
1105 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1106 &user_sgpr_idx, 2);
1107 if (ctx->abi.view_index)
1108 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1109 break;
1110 case MESA_SHADER_FRAGMENT:
1111 if (ctx->shader_info->info.ps.needs_sample_positions) {
1112 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1113 &user_sgpr_idx, 1);
1114 }
1115 break;
1116 default:
1117 unreachable("Shader stage not implemented");
1118 }
1119
1120 if (stage == MESA_SHADER_TESS_CTRL ||
1121 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1122 /* GFX9 has the ESGS ring buffer in LDS. */
1123 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1124 ac_declare_lds_as_pointer(&ctx->ac);
1125 }
1126
1127 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1128 }
1129
1130 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1131 LLVMValueRef value, unsigned count)
1132 {
1133 unsigned num_components = ac_get_llvm_num_components(value);
1134 if (count == num_components)
1135 return value;
1136
1137 LLVMValueRef masks[] = {
1138 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1139 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1140
1141 if (count == 1)
1142 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1143 "");
1144
1145 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1146 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1147 }
1148
1149 static void
1150 build_store_values_extended(struct ac_llvm_context *ac,
1151 LLVMValueRef *values,
1152 unsigned value_count,
1153 unsigned value_stride,
1154 LLVMValueRef vec)
1155 {
1156 LLVMBuilderRef builder = ac->builder;
1157 unsigned i;
1158
1159 for (i = 0; i < value_count; i++) {
1160 LLVMValueRef ptr = values[i * value_stride];
1161 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1162 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1163 LLVMBuildStore(builder, value, ptr);
1164 }
1165 }
1166
1167 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1168 const nir_ssa_def *def)
1169 {
1170 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1171 if (def->num_components > 1) {
1172 type = LLVMVectorType(type, def->num_components);
1173 }
1174 return type;
1175 }
1176
1177 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1178 {
1179 assert(src.is_ssa);
1180 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1181 return (LLVMValueRef)entry->data;
1182 }
1183
1184 static LLVMValueRef
1185 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1186 {
1187 LLVMValueRef ptr = get_src(ctx, src);
1188 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1189 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1190
1191 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1192 LLVMPointerType(ctx->ac.i32, addr_space), "");
1193 }
1194
1195 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1196 const struct nir_block *b)
1197 {
1198 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1199 return (LLVMBasicBlockRef)entry->data;
1200 }
1201
1202 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1203 nir_alu_src src,
1204 unsigned num_components)
1205 {
1206 LLVMValueRef value = get_src(ctx, src.src);
1207 bool need_swizzle = false;
1208
1209 assert(value);
1210 unsigned src_components = ac_get_llvm_num_components(value);
1211 for (unsigned i = 0; i < num_components; ++i) {
1212 assert(src.swizzle[i] < src_components);
1213 if (src.swizzle[i] != i)
1214 need_swizzle = true;
1215 }
1216
1217 if (need_swizzle || num_components != src_components) {
1218 LLVMValueRef masks[] = {
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1220 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1221 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1222 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1223
1224 if (src_components > 1 && num_components == 1) {
1225 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1226 masks[0], "");
1227 } else if (src_components == 1 && num_components > 1) {
1228 LLVMValueRef values[] = {value, value, value, value};
1229 value = ac_build_gather_values(&ctx->ac, values, num_components);
1230 } else {
1231 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1232 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1233 swizzle, "");
1234 }
1235 }
1236 assert(!src.negate);
1237 assert(!src.abs);
1238 return value;
1239 }
1240
1241 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1242 LLVMIntPredicate pred, LLVMValueRef src0,
1243 LLVMValueRef src1)
1244 {
1245 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1246 return LLVMBuildSelect(ctx->builder, result,
1247 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1248 ctx->i32_0, "");
1249 }
1250
1251 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1252 LLVMRealPredicate pred, LLVMValueRef src0,
1253 LLVMValueRef src1)
1254 {
1255 LLVMValueRef result;
1256 src0 = ac_to_float(ctx, src0);
1257 src1 = ac_to_float(ctx, src1);
1258 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1259 return LLVMBuildSelect(ctx->builder, result,
1260 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1261 ctx->i32_0, "");
1262 }
1263
1264 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1265 const char *intrin,
1266 LLVMTypeRef result_type,
1267 LLVMValueRef src0)
1268 {
1269 char name[64];
1270 LLVMValueRef params[] = {
1271 ac_to_float(ctx, src0),
1272 };
1273
1274 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1275 ac_get_elem_bits(ctx, result_type));
1276 assert(length < sizeof(name));
1277 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1278 }
1279
1280 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0, LLVMValueRef src1)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 ac_to_float(ctx, src1),
1289 };
1290
1291 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1292 ac_get_elem_bits(ctx, result_type));
1293 assert(length < sizeof(name));
1294 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1295 }
1296
1297 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1298 const char *intrin,
1299 LLVMTypeRef result_type,
1300 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1301 {
1302 char name[64];
1303 LLVMValueRef params[] = {
1304 ac_to_float(ctx, src0),
1305 ac_to_float(ctx, src1),
1306 ac_to_float(ctx, src2),
1307 };
1308
1309 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1310 ac_get_elem_bits(ctx, result_type));
1311 assert(length < sizeof(name));
1312 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1313 }
1314
1315 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1319 ctx->i32_0, "");
1320 return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
1321 ac_to_integer(ctx, src2), "");
1322 }
1323
1324 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1325 LLVMIntPredicate pred,
1326 LLVMValueRef src0, LLVMValueRef src1)
1327 {
1328 return LLVMBuildSelect(ctx->builder,
1329 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1330 src0,
1331 src1, "");
1332
1333 }
1334 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1335 LLVMValueRef src0)
1336 {
1337 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1338 LLVMBuildNeg(ctx->builder, src0, ""));
1339 }
1340
1341 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1342 LLVMValueRef src0,
1343 unsigned bitsize)
1344 {
1345 LLVMValueRef cmp, val, zero, one;
1346 LLVMTypeRef type;
1347
1348 if (bitsize == 32) {
1349 type = ctx->f32;
1350 zero = ctx->f32_0;
1351 one = ctx->f32_1;
1352 } else {
1353 type = ctx->f64;
1354 zero = ctx->f64_0;
1355 one = ctx->f64_1;
1356 }
1357
1358 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1359 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1360 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1361 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1362 return val;
1363 }
1364
1365 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1366 LLVMValueRef src0, unsigned bitsize)
1367 {
1368 LLVMValueRef cmp, val, zero, one;
1369 LLVMTypeRef type;
1370
1371 if (bitsize == 32) {
1372 type = ctx->i32;
1373 zero = ctx->i32_0;
1374 one = ctx->i32_1;
1375 } else {
1376 type = ctx->i64;
1377 zero = ctx->i64_0;
1378 one = ctx->i64_1;
1379 }
1380
1381 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1382 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1383 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1384 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1385 return val;
1386 }
1387
1388 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1389 LLVMValueRef src0, unsigned bitsize)
1390 {
1391 LLVMTypeRef type;
1392 char *intr;
1393
1394 if (bitsize == 32) {
1395 intr = "llvm.floor.f32";
1396 type = ctx->f32;
1397 } else {
1398 intr = "llvm.floor.f64";
1399 type = ctx->f64;
1400 }
1401
1402 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1403 LLVMValueRef params[] = {
1404 fsrc0,
1405 };
1406 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1407 AC_FUNC_ATTR_READNONE);
1408 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1409 }
1410
1411 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1412 const char *intrin,
1413 LLVMValueRef src0, LLVMValueRef src1)
1414 {
1415 LLVMTypeRef ret_type;
1416 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1417 LLVMValueRef res;
1418 LLVMValueRef params[] = { src0, src1 };
1419 ret_type = LLVMStructTypeInContext(ctx->context, types,
1420 2, true);
1421
1422 res = ac_build_intrinsic(ctx, intrin, ret_type,
1423 params, 2, AC_FUNC_ATTR_READNONE);
1424
1425 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1426 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1427 return res;
1428 }
1429
1430 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1431 LLVMValueRef src0)
1432 {
1433 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1434 }
1435
1436 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1437 LLVMValueRef src0)
1438 {
1439 src0 = ac_to_float(ctx, src0);
1440 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
1441 return LLVMBuildSExt(ctx->builder,
1442 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, zero, ""),
1443 ctx->i32, "");
1444 }
1445
1446 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1447 LLVMValueRef src0,
1448 unsigned bitsize)
1449 {
1450 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1451
1452 if (bitsize == 32)
1453 return result;
1454
1455 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1456 }
1457
1458 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1459 LLVMValueRef src0)
1460 {
1461 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
1462 return LLVMBuildSExt(ctx->builder,
1463 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, zero, ""),
1464 ctx->i32, "");
1465 }
1466
1467 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1468 LLVMValueRef src0)
1469 {
1470 LLVMValueRef result;
1471 LLVMValueRef cond = NULL;
1472
1473 src0 = ac_to_float(ctx, src0);
1474 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1475
1476 if (ctx->chip_class >= VI) {
1477 LLVMValueRef args[2];
1478 /* Check if the result is a denormal - and flush to 0 if so. */
1479 args[0] = result;
1480 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1481 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1482 }
1483
1484 /* need to convert back up to f32 */
1485 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1486
1487 if (ctx->chip_class >= VI)
1488 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1489 else {
1490 /* for SI/CIK */
1491 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1492 * so compare the result and flush to 0 if it's smaller.
1493 */
1494 LLVMValueRef temp, cond2;
1495 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1496 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1497 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1498 temp, "");
1499 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1500 temp, ctx->f32_0, "");
1501 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1502 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1503 }
1504 return result;
1505 }
1506
1507 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1508 LLVMValueRef src0, LLVMValueRef src1)
1509 {
1510 LLVMValueRef dst64, result;
1511 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1512 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1513
1514 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1515 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1516 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1517 return result;
1518 }
1519
1520 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1521 LLVMValueRef src0, LLVMValueRef src1)
1522 {
1523 LLVMValueRef dst64, result;
1524 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1525 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1526
1527 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1528 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1529 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1530 return result;
1531 }
1532
1533 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1534 bool is_signed,
1535 const LLVMValueRef srcs[3])
1536 {
1537 LLVMValueRef result;
1538 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1539
1540 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1541 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1542 return result;
1543 }
1544
1545 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1546 LLVMValueRef src0, LLVMValueRef src1,
1547 LLVMValueRef src2, LLVMValueRef src3)
1548 {
1549 LLVMValueRef bfi_args[3], result;
1550
1551 bfi_args[0] = LLVMBuildShl(ctx->builder,
1552 LLVMBuildSub(ctx->builder,
1553 LLVMBuildShl(ctx->builder,
1554 ctx->i32_1,
1555 src3, ""),
1556 ctx->i32_1, ""),
1557 src2, "");
1558 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1559 bfi_args[2] = src0;
1560
1561 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1562
1563 /* Calculate:
1564 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1565 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1566 */
1567 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1568 LLVMBuildAnd(ctx->builder, bfi_args[0],
1569 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1570
1571 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1572 return result;
1573 }
1574
1575 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1576 LLVMValueRef src0)
1577 {
1578 LLVMValueRef comp[2];
1579
1580 src0 = ac_to_float(ctx, src0);
1581 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1582 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1583
1584 return ac_build_cvt_pkrtz_f16(ctx, comp);
1585 }
1586
1587 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1588 LLVMValueRef src0)
1589 {
1590 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1591 LLVMValueRef temps[2], result, val;
1592 int i;
1593
1594 for (i = 0; i < 2; i++) {
1595 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1596 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1597 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1598 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1599 }
1600
1601 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1602 ctx->i32_0, "");
1603 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1604 ctx->i32_1, "");
1605 return result;
1606 }
1607
1608 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1609 nir_op op,
1610 LLVMValueRef src0)
1611 {
1612 unsigned mask;
1613 int idx;
1614 LLVMValueRef result;
1615
1616 if (op == nir_op_fddx_fine)
1617 mask = AC_TID_MASK_LEFT;
1618 else if (op == nir_op_fddy_fine)
1619 mask = AC_TID_MASK_TOP;
1620 else
1621 mask = AC_TID_MASK_TOP_LEFT;
1622
1623 /* for DDX we want to next X pixel, DDY next Y pixel. */
1624 if (op == nir_op_fddx_fine ||
1625 op == nir_op_fddx_coarse ||
1626 op == nir_op_fddx)
1627 idx = 1;
1628 else
1629 idx = 2;
1630
1631 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1632 return result;
1633 }
1634
1635 /*
1636 * this takes an I,J coordinate pair,
1637 * and works out the X and Y derivatives.
1638 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1639 */
1640 static LLVMValueRef emit_ddxy_interp(
1641 struct ac_nir_context *ctx,
1642 LLVMValueRef interp_ij)
1643 {
1644 LLVMValueRef result[4], a;
1645 unsigned i;
1646
1647 for (i = 0; i < 2; i++) {
1648 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1649 LLVMConstInt(ctx->ac.i32, i, false), "");
1650 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1651 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1652 }
1653 return ac_build_gather_values(&ctx->ac, result, 4);
1654 }
1655
1656 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1657 {
1658 LLVMValueRef src[4], result = NULL;
1659 unsigned num_components = instr->dest.dest.ssa.num_components;
1660 unsigned src_components;
1661 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1662
1663 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1664 switch (instr->op) {
1665 case nir_op_vec2:
1666 case nir_op_vec3:
1667 case nir_op_vec4:
1668 src_components = 1;
1669 break;
1670 case nir_op_pack_half_2x16:
1671 src_components = 2;
1672 break;
1673 case nir_op_unpack_half_2x16:
1674 src_components = 1;
1675 break;
1676 default:
1677 src_components = num_components;
1678 break;
1679 }
1680 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1681 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1682
1683 switch (instr->op) {
1684 case nir_op_fmov:
1685 case nir_op_imov:
1686 result = src[0];
1687 break;
1688 case nir_op_fneg:
1689 src[0] = ac_to_float(&ctx->ac, src[0]);
1690 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1691 break;
1692 case nir_op_ineg:
1693 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1694 break;
1695 case nir_op_inot:
1696 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1697 break;
1698 case nir_op_iadd:
1699 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1700 break;
1701 case nir_op_fadd:
1702 src[0] = ac_to_float(&ctx->ac, src[0]);
1703 src[1] = ac_to_float(&ctx->ac, src[1]);
1704 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1705 break;
1706 case nir_op_fsub:
1707 src[0] = ac_to_float(&ctx->ac, src[0]);
1708 src[1] = ac_to_float(&ctx->ac, src[1]);
1709 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1710 break;
1711 case nir_op_isub:
1712 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1713 break;
1714 case nir_op_imul:
1715 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1716 break;
1717 case nir_op_imod:
1718 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1719 break;
1720 case nir_op_umod:
1721 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1722 break;
1723 case nir_op_fmod:
1724 src[0] = ac_to_float(&ctx->ac, src[0]);
1725 src[1] = ac_to_float(&ctx->ac, src[1]);
1726 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1727 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1728 ac_to_float_type(&ctx->ac, def_type), result);
1729 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1730 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1731 break;
1732 case nir_op_frem:
1733 src[0] = ac_to_float(&ctx->ac, src[0]);
1734 src[1] = ac_to_float(&ctx->ac, src[1]);
1735 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1736 break;
1737 case nir_op_irem:
1738 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1739 break;
1740 case nir_op_idiv:
1741 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1742 break;
1743 case nir_op_udiv:
1744 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1745 break;
1746 case nir_op_fmul:
1747 src[0] = ac_to_float(&ctx->ac, src[0]);
1748 src[1] = ac_to_float(&ctx->ac, src[1]);
1749 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1750 break;
1751 case nir_op_frcp:
1752 src[0] = ac_to_float(&ctx->ac, src[0]);
1753 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1754 src[0]);
1755 break;
1756 case nir_op_iand:
1757 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1758 break;
1759 case nir_op_ior:
1760 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1761 break;
1762 case nir_op_ixor:
1763 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1764 break;
1765 case nir_op_ishl:
1766 result = LLVMBuildShl(ctx->ac.builder, src[0],
1767 LLVMBuildZExt(ctx->ac.builder, src[1],
1768 LLVMTypeOf(src[0]), ""),
1769 "");
1770 break;
1771 case nir_op_ishr:
1772 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1773 LLVMBuildZExt(ctx->ac.builder, src[1],
1774 LLVMTypeOf(src[0]), ""),
1775 "");
1776 break;
1777 case nir_op_ushr:
1778 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1779 LLVMBuildZExt(ctx->ac.builder, src[1],
1780 LLVMTypeOf(src[0]), ""),
1781 "");
1782 break;
1783 case nir_op_ilt:
1784 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1785 break;
1786 case nir_op_ine:
1787 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1788 break;
1789 case nir_op_ieq:
1790 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1791 break;
1792 case nir_op_ige:
1793 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1794 break;
1795 case nir_op_ult:
1796 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1797 break;
1798 case nir_op_uge:
1799 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1800 break;
1801 case nir_op_feq:
1802 result = emit_float_cmp(&ctx->ac, LLVMRealOEQ, src[0], src[1]);
1803 break;
1804 case nir_op_fne:
1805 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1806 break;
1807 case nir_op_flt:
1808 result = emit_float_cmp(&ctx->ac, LLVMRealOLT, src[0], src[1]);
1809 break;
1810 case nir_op_fge:
1811 result = emit_float_cmp(&ctx->ac, LLVMRealOGE, src[0], src[1]);
1812 break;
1813 case nir_op_fabs:
1814 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1815 ac_to_float_type(&ctx->ac, def_type), src[0]);
1816 break;
1817 case nir_op_iabs:
1818 result = emit_iabs(&ctx->ac, src[0]);
1819 break;
1820 case nir_op_imax:
1821 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1822 break;
1823 case nir_op_imin:
1824 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1825 break;
1826 case nir_op_umax:
1827 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1828 break;
1829 case nir_op_umin:
1830 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1831 break;
1832 case nir_op_isign:
1833 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1834 break;
1835 case nir_op_fsign:
1836 src[0] = ac_to_float(&ctx->ac, src[0]);
1837 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1838 break;
1839 case nir_op_ffloor:
1840 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1841 ac_to_float_type(&ctx->ac, def_type), src[0]);
1842 break;
1843 case nir_op_ftrunc:
1844 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1845 ac_to_float_type(&ctx->ac, def_type), src[0]);
1846 break;
1847 case nir_op_fceil:
1848 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1849 ac_to_float_type(&ctx->ac, def_type), src[0]);
1850 break;
1851 case nir_op_fround_even:
1852 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1853 ac_to_float_type(&ctx->ac, def_type),src[0]);
1854 break;
1855 case nir_op_ffract:
1856 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1857 break;
1858 case nir_op_fsin:
1859 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1860 ac_to_float_type(&ctx->ac, def_type), src[0]);
1861 break;
1862 case nir_op_fcos:
1863 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1864 ac_to_float_type(&ctx->ac, def_type), src[0]);
1865 break;
1866 case nir_op_fsqrt:
1867 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1868 ac_to_float_type(&ctx->ac, def_type), src[0]);
1869 break;
1870 case nir_op_fexp2:
1871 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1872 ac_to_float_type(&ctx->ac, def_type), src[0]);
1873 break;
1874 case nir_op_flog2:
1875 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1876 ac_to_float_type(&ctx->ac, def_type), src[0]);
1877 break;
1878 case nir_op_frsq:
1879 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1880 ac_to_float_type(&ctx->ac, def_type), src[0]);
1881 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1882 result);
1883 break;
1884 case nir_op_fmax:
1885 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1886 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1887 if (ctx->ac.chip_class < GFX9 &&
1888 instr->dest.dest.ssa.bit_size == 32) {
1889 /* Only pre-GFX9 chips do not flush denorms. */
1890 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1891 ac_to_float_type(&ctx->ac, def_type),
1892 result);
1893 }
1894 break;
1895 case nir_op_fmin:
1896 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1897 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1898 if (ctx->ac.chip_class < GFX9 &&
1899 instr->dest.dest.ssa.bit_size == 32) {
1900 /* Only pre-GFX9 chips do not flush denorms. */
1901 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1902 ac_to_float_type(&ctx->ac, def_type),
1903 result);
1904 }
1905 break;
1906 case nir_op_ffma:
1907 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1908 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1909 break;
1910 case nir_op_ldexp:
1911 src[0] = ac_to_float(&ctx->ac, src[0]);
1912 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1913 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f32", ctx->ac.f32, src, 2, AC_FUNC_ATTR_READNONE);
1914 else
1915 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f64", ctx->ac.f64, src, 2, AC_FUNC_ATTR_READNONE);
1916 break;
1917 case nir_op_ibitfield_extract:
1918 result = emit_bitfield_extract(&ctx->ac, true, src);
1919 break;
1920 case nir_op_ubitfield_extract:
1921 result = emit_bitfield_extract(&ctx->ac, false, src);
1922 break;
1923 case nir_op_bitfield_insert:
1924 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1925 break;
1926 case nir_op_bitfield_reverse:
1927 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1928 break;
1929 case nir_op_bit_count:
1930 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1931 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1932 else {
1933 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1934 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1935 }
1936 break;
1937 case nir_op_vec2:
1938 case nir_op_vec3:
1939 case nir_op_vec4:
1940 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1941 src[i] = ac_to_integer(&ctx->ac, src[i]);
1942 result = ac_build_gather_values(&ctx->ac, src, num_components);
1943 break;
1944 case nir_op_f2i32:
1945 case nir_op_f2i64:
1946 src[0] = ac_to_float(&ctx->ac, src[0]);
1947 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1948 break;
1949 case nir_op_f2u32:
1950 case nir_op_f2u64:
1951 src[0] = ac_to_float(&ctx->ac, src[0]);
1952 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1953 break;
1954 case nir_op_i2f32:
1955 case nir_op_i2f64:
1956 src[0] = ac_to_integer(&ctx->ac, src[0]);
1957 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1958 break;
1959 case nir_op_u2f32:
1960 case nir_op_u2f64:
1961 src[0] = ac_to_integer(&ctx->ac, src[0]);
1962 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1963 break;
1964 case nir_op_f2f64:
1965 src[0] = ac_to_float(&ctx->ac, src[0]);
1966 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1967 break;
1968 case nir_op_f2f32:
1969 src[0] = ac_to_float(&ctx->ac, src[0]);
1970 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1971 break;
1972 case nir_op_u2u32:
1973 case nir_op_u2u64:
1974 src[0] = ac_to_integer(&ctx->ac, src[0]);
1975 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1976 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1977 else
1978 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1979 break;
1980 case nir_op_i2i32:
1981 case nir_op_i2i64:
1982 src[0] = ac_to_integer(&ctx->ac, src[0]);
1983 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1984 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1985 else
1986 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1987 break;
1988 case nir_op_bcsel:
1989 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1990 break;
1991 case nir_op_find_lsb:
1992 src[0] = ac_to_integer(&ctx->ac, src[0]);
1993 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1994 break;
1995 case nir_op_ufind_msb:
1996 src[0] = ac_to_integer(&ctx->ac, src[0]);
1997 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1998 break;
1999 case nir_op_ifind_msb:
2000 src[0] = ac_to_integer(&ctx->ac, src[0]);
2001 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
2002 break;
2003 case nir_op_uadd_carry:
2004 src[0] = ac_to_integer(&ctx->ac, src[0]);
2005 src[1] = ac_to_integer(&ctx->ac, src[1]);
2006 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
2007 break;
2008 case nir_op_usub_borrow:
2009 src[0] = ac_to_integer(&ctx->ac, src[0]);
2010 src[1] = ac_to_integer(&ctx->ac, src[1]);
2011 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2012 break;
2013 case nir_op_b2f:
2014 result = emit_b2f(&ctx->ac, src[0]);
2015 break;
2016 case nir_op_f2b:
2017 result = emit_f2b(&ctx->ac, src[0]);
2018 break;
2019 case nir_op_b2i:
2020 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2021 break;
2022 case nir_op_i2b:
2023 src[0] = ac_to_integer(&ctx->ac, src[0]);
2024 result = emit_i2b(&ctx->ac, src[0]);
2025 break;
2026 case nir_op_fquantize2f16:
2027 result = emit_f2f16(&ctx->ac, src[0]);
2028 break;
2029 case nir_op_umul_high:
2030 src[0] = ac_to_integer(&ctx->ac, src[0]);
2031 src[1] = ac_to_integer(&ctx->ac, src[1]);
2032 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2033 break;
2034 case nir_op_imul_high:
2035 src[0] = ac_to_integer(&ctx->ac, src[0]);
2036 src[1] = ac_to_integer(&ctx->ac, src[1]);
2037 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2038 break;
2039 case nir_op_pack_half_2x16:
2040 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2041 break;
2042 case nir_op_unpack_half_2x16:
2043 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2044 break;
2045 case nir_op_fddx:
2046 case nir_op_fddy:
2047 case nir_op_fddx_fine:
2048 case nir_op_fddy_fine:
2049 case nir_op_fddx_coarse:
2050 case nir_op_fddy_coarse:
2051 result = emit_ddxy(ctx, instr->op, src[0]);
2052 break;
2053
2054 case nir_op_unpack_64_2x32_split_x: {
2055 assert(ac_get_llvm_num_components(src[0]) == 1);
2056 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2057 ctx->ac.v2i32,
2058 "");
2059 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2060 ctx->ac.i32_0, "");
2061 break;
2062 }
2063
2064 case nir_op_unpack_64_2x32_split_y: {
2065 assert(ac_get_llvm_num_components(src[0]) == 1);
2066 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2067 ctx->ac.v2i32,
2068 "");
2069 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2070 ctx->ac.i32_1, "");
2071 break;
2072 }
2073
2074 case nir_op_pack_64_2x32_split: {
2075 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2076 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2077 src[0], ctx->ac.i32_0, "");
2078 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2079 src[1], ctx->ac.i32_1, "");
2080 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2081 break;
2082 }
2083
2084 default:
2085 fprintf(stderr, "Unknown NIR alu instr: ");
2086 nir_print_instr(&instr->instr, stderr);
2087 fprintf(stderr, "\n");
2088 abort();
2089 }
2090
2091 if (result) {
2092 assert(instr->dest.dest.is_ssa);
2093 result = ac_to_integer(&ctx->ac, result);
2094 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2095 result);
2096 }
2097 }
2098
2099 static void visit_load_const(struct ac_nir_context *ctx,
2100 const nir_load_const_instr *instr)
2101 {
2102 LLVMValueRef values[4], value = NULL;
2103 LLVMTypeRef element_type =
2104 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2105
2106 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2107 switch (instr->def.bit_size) {
2108 case 32:
2109 values[i] = LLVMConstInt(element_type,
2110 instr->value.u32[i], false);
2111 break;
2112 case 64:
2113 values[i] = LLVMConstInt(element_type,
2114 instr->value.u64[i], false);
2115 break;
2116 default:
2117 fprintf(stderr,
2118 "unsupported nir load_const bit_size: %d\n",
2119 instr->def.bit_size);
2120 abort();
2121 }
2122 }
2123 if (instr->def.num_components > 1) {
2124 value = LLVMConstVector(values, instr->def.num_components);
2125 } else
2126 value = values[0];
2127
2128 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2129 }
2130
2131 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2132 LLVMTypeRef type)
2133 {
2134 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2135 return LLVMBuildBitCast(ctx->builder, ptr,
2136 LLVMPointerType(type, addr_space), "");
2137 }
2138
2139 static LLVMValueRef
2140 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2141 {
2142 LLVMValueRef size =
2143 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2144 LLVMConstInt(ctx->ac.i32, 2, false), "");
2145
2146 /* VI only */
2147 if (ctx->ac.chip_class == VI && in_elements) {
2148 /* On VI, the descriptor contains the size in bytes,
2149 * but TXQ must return the size in elements.
2150 * The stride is always non-zero for resources using TXQ.
2151 */
2152 LLVMValueRef stride =
2153 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2154 ctx->ac.i32_1, "");
2155 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2156 LLVMConstInt(ctx->ac.i32, 16, false), "");
2157 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2158 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2159
2160 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2161 }
2162 return size;
2163 }
2164
2165 /**
2166 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2167 * intrinsic names).
2168 */
2169 static void build_int_type_name(
2170 LLVMTypeRef type,
2171 char *buf, unsigned bufsize)
2172 {
2173 assert(bufsize >= 6);
2174
2175 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2176 snprintf(buf, bufsize, "v%ui32",
2177 LLVMGetVectorSize(type));
2178 else
2179 strcpy(buf, "i32");
2180 }
2181
2182 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2183 struct ac_image_args *args,
2184 const nir_tex_instr *instr)
2185 {
2186 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2187 LLVMValueRef coord = args->addr;
2188 LLVMValueRef half_texel[2];
2189 LLVMValueRef compare_cube_wa = NULL;
2190 LLVMValueRef result;
2191 int c;
2192 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2193
2194 //TODO Rect
2195 {
2196 struct ac_image_args txq_args = { 0 };
2197
2198 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2199 txq_args.opcode = ac_image_get_resinfo;
2200 txq_args.dmask = 0xf;
2201 txq_args.addr = ctx->i32_0;
2202 txq_args.resource = args->resource;
2203 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2204
2205 for (c = 0; c < 2; c++) {
2206 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2207 LLVMConstInt(ctx->i32, c, false), "");
2208 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2209 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2210 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2211 LLVMConstReal(ctx->f32, -0.5), "");
2212 }
2213 }
2214
2215 LLVMValueRef orig_coords = args->addr;
2216
2217 for (c = 0; c < 2; c++) {
2218 LLVMValueRef tmp;
2219 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2220 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2221 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2222 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2223 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2224 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2225 }
2226
2227
2228 /*
2229 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2230 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2231 * workaround by sampling using a scaled type and converting.
2232 * This is taken from amdgpu-pro shaders.
2233 */
2234 /* NOTE this produces some ugly code compared to amdgpu-pro,
2235 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2236 * and then reads them back. -pro generates two selects,
2237 * one s_cmp for the descriptor rewriting
2238 * one v_cmp for the coordinate and result changes.
2239 */
2240 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2241 LLVMValueRef tmp, tmp2;
2242
2243 /* workaround 8/8/8/8 uint/sint cube gather bug */
2244 /* first detect it then change to a scaled read and f2i */
2245 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2246 tmp2 = tmp;
2247
2248 /* extract the DATA_FORMAT */
2249 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2250 LLVMConstInt(ctx->i32, 6, false), false);
2251
2252 /* is the DATA_FORMAT == 8_8_8_8 */
2253 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2254
2255 if (stype == GLSL_TYPE_UINT)
2256 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2257 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2258 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2259 else
2260 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2261 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2262 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2263
2264 /* replace the NUM FORMAT in the descriptor */
2265 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2266 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2267
2268 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2269
2270 /* don't modify the coordinates for this case */
2271 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2272 }
2273 args->addr = coord;
2274 result = ac_build_image_opcode(ctx, args);
2275
2276 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2277 LLVMValueRef tmp, tmp2;
2278
2279 /* if the cube workaround is in place, f2i the result. */
2280 for (c = 0; c < 4; c++) {
2281 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2282 if (stype == GLSL_TYPE_UINT)
2283 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2284 else
2285 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2286 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2287 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2288 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2289 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2290 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2291 }
2292 }
2293 return result;
2294 }
2295
2296 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2297 const nir_tex_instr *instr,
2298 bool lod_is_zero,
2299 struct ac_image_args *args)
2300 {
2301 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2302 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2303
2304 return ac_build_buffer_load_format(&ctx->ac,
2305 args->resource,
2306 args->addr,
2307 ctx->ac.i32_0,
2308 util_last_bit(mask),
2309 false, true);
2310 }
2311
2312 args->opcode = ac_image_sample;
2313 args->compare = instr->is_shadow;
2314
2315 switch (instr->op) {
2316 case nir_texop_txf:
2317 case nir_texop_txf_ms:
2318 case nir_texop_samples_identical:
2319 args->opcode = lod_is_zero ||
2320 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2321 ac_image_load : ac_image_load_mip;
2322 args->compare = false;
2323 args->offset = false;
2324 break;
2325 case nir_texop_txb:
2326 args->bias = true;
2327 break;
2328 case nir_texop_txl:
2329 if (lod_is_zero)
2330 args->level_zero = true;
2331 else
2332 args->lod = true;
2333 break;
2334 case nir_texop_txs:
2335 case nir_texop_query_levels:
2336 args->opcode = ac_image_get_resinfo;
2337 break;
2338 case nir_texop_tex:
2339 if (ctx->stage != MESA_SHADER_FRAGMENT)
2340 args->level_zero = true;
2341 break;
2342 case nir_texop_txd:
2343 args->deriv = true;
2344 break;
2345 case nir_texop_tg4:
2346 args->opcode = ac_image_gather4;
2347 args->level_zero = true;
2348 break;
2349 case nir_texop_lod:
2350 args->opcode = ac_image_get_lod;
2351 args->compare = false;
2352 args->offset = false;
2353 break;
2354 default:
2355 break;
2356 }
2357
2358 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2359 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2360 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2361 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2362 }
2363 }
2364 return ac_build_image_opcode(&ctx->ac, args);
2365 }
2366
2367 static LLVMValueRef
2368 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2369 unsigned desc_set, unsigned binding)
2370 {
2371 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2372 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2373 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2374 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2375 unsigned base_offset = layout->binding[binding].offset;
2376 LLVMValueRef offset, stride;
2377
2378 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2379 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2380 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2381 layout->binding[binding].dynamic_offset_offset;
2382 desc_ptr = ctx->abi.push_constants;
2383 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2384 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2385 } else
2386 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2387
2388 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2389 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2390 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2391
2392 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2393 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2394 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2395
2396 return desc_ptr;
2397 }
2398
2399 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2400 nir_intrinsic_instr *instr)
2401 {
2402 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2403 LLVMValueRef index = get_src(ctx, instr->src[1]);
2404
2405 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2406 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2407 return result;
2408 }
2409
2410 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2411 nir_intrinsic_instr *instr)
2412 {
2413 LLVMValueRef ptr, addr;
2414
2415 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2416 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2417 get_src(ctx, instr->src[0]), "");
2418
2419 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2420 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2421
2422 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2423 }
2424
2425 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2426 const nir_intrinsic_instr *instr)
2427 {
2428 LLVMValueRef index = get_src(ctx, instr->src[0]);
2429
2430 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2431 }
2432
2433 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2434 {
2435 uint32_t new_mask = 0;
2436 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2437 if (mask & (1u << i))
2438 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2439 return new_mask;
2440 }
2441
2442 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2443 unsigned start, unsigned count)
2444 {
2445 LLVMTypeRef type = LLVMTypeOf(src);
2446
2447 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2448 assert(start == 0);
2449 assert(count == 1);
2450 return src;
2451 }
2452
2453 unsigned src_elements = LLVMGetVectorSize(type);
2454 assert(start < src_elements);
2455 assert(start + count <= src_elements);
2456
2457 if (start == 0 && count == src_elements)
2458 return src;
2459
2460 if (count == 1)
2461 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2462
2463 assert(count <= 8);
2464 LLVMValueRef indices[8];
2465 for (unsigned i = 0; i < count; ++i)
2466 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2467
2468 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2469 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2470 }
2471
2472 static void visit_store_ssbo(struct ac_nir_context *ctx,
2473 nir_intrinsic_instr *instr)
2474 {
2475 const char *store_name;
2476 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2477 LLVMTypeRef data_type = ctx->ac.f32;
2478 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2479 int components_32bit = elem_size_mult * instr->num_components;
2480 unsigned writemask = nir_intrinsic_write_mask(instr);
2481 LLVMValueRef base_data, base_offset;
2482 LLVMValueRef params[6];
2483
2484 params[1] = ctx->abi->load_ssbo(ctx->abi,
2485 get_src(ctx, instr->src[1]), true);
2486 params[2] = ctx->ac.i32_0; /* vindex */
2487 params[4] = ctx->ac.i1false; /* glc */
2488 params[5] = ctx->ac.i1false; /* slc */
2489
2490 if (components_32bit > 1)
2491 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2492
2493 writemask = widen_mask(writemask, elem_size_mult);
2494
2495 base_data = ac_to_float(&ctx->ac, src_data);
2496 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2497 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2498 data_type, "");
2499 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2500 while (writemask) {
2501 int start, count;
2502 LLVMValueRef data;
2503 LLVMValueRef offset;
2504
2505 u_bit_scan_consecutive_range(&writemask, &start, &count);
2506
2507 /* Due to an LLVM limitation, split 3-element writes
2508 * into a 2-element and a 1-element write. */
2509 if (count == 3) {
2510 writemask |= 1 << (start + 2);
2511 count = 2;
2512 }
2513
2514 if (count > 4) {
2515 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2516 count = 4;
2517 }
2518
2519 if (count == 4) {
2520 store_name = "llvm.amdgcn.buffer.store.v4f32";
2521 } else if (count == 2) {
2522 store_name = "llvm.amdgcn.buffer.store.v2f32";
2523
2524 } else {
2525 assert(count == 1);
2526 store_name = "llvm.amdgcn.buffer.store.f32";
2527 }
2528 data = extract_vector_range(&ctx->ac, base_data, start, count);
2529
2530 offset = base_offset;
2531 if (start != 0) {
2532 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2533 }
2534 params[0] = data;
2535 params[3] = offset;
2536 ac_build_intrinsic(&ctx->ac, store_name,
2537 ctx->ac.voidt, params, 6, 0);
2538 }
2539 }
2540
2541 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2542 const nir_intrinsic_instr *instr)
2543 {
2544 const char *name;
2545 LLVMValueRef params[6];
2546 int arg_count = 0;
2547
2548 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2549 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2550 }
2551 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2552 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2553 get_src(ctx, instr->src[0]),
2554 true);
2555 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2556 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2557 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2558
2559 switch (instr->intrinsic) {
2560 case nir_intrinsic_ssbo_atomic_add:
2561 name = "llvm.amdgcn.buffer.atomic.add";
2562 break;
2563 case nir_intrinsic_ssbo_atomic_imin:
2564 name = "llvm.amdgcn.buffer.atomic.smin";
2565 break;
2566 case nir_intrinsic_ssbo_atomic_umin:
2567 name = "llvm.amdgcn.buffer.atomic.umin";
2568 break;
2569 case nir_intrinsic_ssbo_atomic_imax:
2570 name = "llvm.amdgcn.buffer.atomic.smax";
2571 break;
2572 case nir_intrinsic_ssbo_atomic_umax:
2573 name = "llvm.amdgcn.buffer.atomic.umax";
2574 break;
2575 case nir_intrinsic_ssbo_atomic_and:
2576 name = "llvm.amdgcn.buffer.atomic.and";
2577 break;
2578 case nir_intrinsic_ssbo_atomic_or:
2579 name = "llvm.amdgcn.buffer.atomic.or";
2580 break;
2581 case nir_intrinsic_ssbo_atomic_xor:
2582 name = "llvm.amdgcn.buffer.atomic.xor";
2583 break;
2584 case nir_intrinsic_ssbo_atomic_exchange:
2585 name = "llvm.amdgcn.buffer.atomic.swap";
2586 break;
2587 case nir_intrinsic_ssbo_atomic_comp_swap:
2588 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2589 break;
2590 default:
2591 abort();
2592 }
2593
2594 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2595 }
2596
2597 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2598 const nir_intrinsic_instr *instr)
2599 {
2600 LLVMValueRef results[2];
2601 int load_components;
2602 int num_components = instr->num_components;
2603 if (instr->dest.ssa.bit_size == 64)
2604 num_components *= 2;
2605
2606 for (int i = 0; i < num_components; i += load_components) {
2607 load_components = MIN2(num_components - i, 4);
2608 const char *load_name;
2609 LLVMTypeRef data_type = ctx->ac.f32;
2610 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2611 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2612
2613 if (load_components == 3)
2614 data_type = LLVMVectorType(ctx->ac.f32, 4);
2615 else if (load_components > 1)
2616 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2617
2618 if (load_components >= 3)
2619 load_name = "llvm.amdgcn.buffer.load.v4f32";
2620 else if (load_components == 2)
2621 load_name = "llvm.amdgcn.buffer.load.v2f32";
2622 else if (load_components == 1)
2623 load_name = "llvm.amdgcn.buffer.load.f32";
2624 else
2625 unreachable("unhandled number of components");
2626
2627 LLVMValueRef params[] = {
2628 ctx->abi->load_ssbo(ctx->abi,
2629 get_src(ctx, instr->src[0]),
2630 false),
2631 ctx->ac.i32_0,
2632 offset,
2633 ctx->ac.i1false,
2634 ctx->ac.i1false,
2635 };
2636
2637 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2638 }
2639
2640 assume(results[0]);
2641 LLVMValueRef ret = results[0];
2642 if (num_components > 4 || num_components == 3) {
2643 LLVMValueRef masks[] = {
2644 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2645 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2646 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2647 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2648 };
2649
2650 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2651 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2652 results[num_components > 4 ? 1 : 0], swizzle, "");
2653 }
2654
2655 return LLVMBuildBitCast(ctx->ac.builder, ret,
2656 get_def_type(ctx, &instr->dest.ssa), "");
2657 }
2658
2659 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2660 const nir_intrinsic_instr *instr)
2661 {
2662 LLVMValueRef ret;
2663 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2664 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2665 int num_components = instr->num_components;
2666
2667 if (ctx->abi->load_ubo)
2668 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2669
2670 if (instr->dest.ssa.bit_size == 64)
2671 num_components *= 2;
2672
2673 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2674 NULL, 0, false, false, true, true);
2675 ret = trim_vector(&ctx->ac, ret, num_components);
2676 return LLVMBuildBitCast(ctx->ac.builder, ret,
2677 get_def_type(ctx, &instr->dest.ssa), "");
2678 }
2679
2680 static void
2681 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2682 bool vs_in, unsigned *vertex_index_out,
2683 LLVMValueRef *vertex_index_ref,
2684 unsigned *const_out, LLVMValueRef *indir_out)
2685 {
2686 unsigned const_offset = 0;
2687 nir_deref *tail = &deref->deref;
2688 LLVMValueRef offset = NULL;
2689
2690 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2691 tail = tail->child;
2692 nir_deref_array *deref_array = nir_deref_as_array(tail);
2693 if (vertex_index_out)
2694 *vertex_index_out = deref_array->base_offset;
2695
2696 if (vertex_index_ref) {
2697 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2698 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2699 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2700 }
2701 *vertex_index_ref = vtx;
2702 }
2703 }
2704
2705 if (deref->var->data.compact) {
2706 assert(tail->child->deref_type == nir_deref_type_array);
2707 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2708 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2709 /* We always lower indirect dereferences for "compact" array vars. */
2710 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2711
2712 const_offset = deref_array->base_offset;
2713 goto out;
2714 }
2715
2716 while (tail->child != NULL) {
2717 const struct glsl_type *parent_type = tail->type;
2718 tail = tail->child;
2719
2720 if (tail->deref_type == nir_deref_type_array) {
2721 nir_deref_array *deref_array = nir_deref_as_array(tail);
2722 LLVMValueRef index, stride, local_offset;
2723 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2724
2725 const_offset += size * deref_array->base_offset;
2726 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2727 continue;
2728
2729 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2730 index = get_src(ctx, deref_array->indirect);
2731 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2732 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2733
2734 if (offset)
2735 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2736 else
2737 offset = local_offset;
2738 } else if (tail->deref_type == nir_deref_type_struct) {
2739 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2740
2741 for (unsigned i = 0; i < deref_struct->index; i++) {
2742 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2743 const_offset += glsl_count_attribute_slots(ft, vs_in);
2744 }
2745 } else
2746 unreachable("unsupported deref type");
2747
2748 }
2749 out:
2750 if (const_offset && offset)
2751 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2752 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2753 "");
2754
2755 *const_out = const_offset;
2756 *indir_out = offset;
2757 }
2758
2759
2760 /* The offchip buffer layout for TCS->TES is
2761 *
2762 * - attribute 0 of patch 0 vertex 0
2763 * - attribute 0 of patch 0 vertex 1
2764 * - attribute 0 of patch 0 vertex 2
2765 * ...
2766 * - attribute 0 of patch 1 vertex 0
2767 * - attribute 0 of patch 1 vertex 1
2768 * ...
2769 * - attribute 1 of patch 0 vertex 0
2770 * - attribute 1 of patch 0 vertex 1
2771 * ...
2772 * - per patch attribute 0 of patch 0
2773 * - per patch attribute 0 of patch 1
2774 * ...
2775 *
2776 * Note that every attribute has 4 components.
2777 */
2778 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2779 LLVMValueRef vertex_index,
2780 LLVMValueRef param_index)
2781 {
2782 LLVMValueRef base_addr, vertices_per_patch, num_patches;
2783 LLVMValueRef param_stride, constant16;
2784 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2785
2786 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
2787 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2788
2789 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2790 if (vertex_index) {
2791 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2792 vertices_per_patch, "");
2793
2794 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2795 vertex_index, "");
2796
2797 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2798 num_patches, "");
2799 } else {
2800 base_addr = rel_patch_id;
2801 param_stride = num_patches;
2802 }
2803
2804 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2805 LLVMBuildMul(ctx->ac.builder, param_index,
2806 param_stride, ""), "");
2807
2808 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2809
2810 if (!vertex_index) {
2811 LLVMValueRef patch_data_offset =
2812 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2813
2814 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2815 patch_data_offset, "");
2816 }
2817 return base_addr;
2818 }
2819
2820 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2821 unsigned param,
2822 unsigned const_index,
2823 bool is_compact,
2824 LLVMValueRef vertex_index,
2825 LLVMValueRef indir_index)
2826 {
2827 LLVMValueRef param_index;
2828
2829 if (indir_index)
2830 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2831 indir_index, "");
2832 else {
2833 if (const_index && !is_compact)
2834 param += const_index;
2835 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2836 }
2837 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2838 }
2839
2840 static void
2841 mark_tess_output(struct radv_shader_context *ctx,
2842 bool is_patch, uint32_t param)
2843
2844 {
2845 if (is_patch) {
2846 ctx->tess_patch_outputs_written |= (1ull << param);
2847 } else
2848 ctx->tess_outputs_written |= (1ull << param);
2849 }
2850
2851 static LLVMValueRef
2852 get_dw_address(struct radv_shader_context *ctx,
2853 LLVMValueRef dw_addr,
2854 unsigned param,
2855 unsigned const_index,
2856 bool compact_const_index,
2857 LLVMValueRef vertex_index,
2858 LLVMValueRef stride,
2859 LLVMValueRef indir_index)
2860
2861 {
2862
2863 if (vertex_index) {
2864 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2865 LLVMBuildMul(ctx->ac.builder,
2866 vertex_index,
2867 stride, ""), "");
2868 }
2869
2870 if (indir_index)
2871 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2872 LLVMBuildMul(ctx->ac.builder, indir_index,
2873 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2874 else if (const_index && !compact_const_index)
2875 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2876 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2877
2878 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2879 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2880
2881 if (const_index && compact_const_index)
2882 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2883 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2884 return dw_addr;
2885 }
2886
2887 static LLVMValueRef
2888 load_tcs_varyings(struct ac_shader_abi *abi,
2889 LLVMTypeRef type,
2890 LLVMValueRef vertex_index,
2891 LLVMValueRef indir_index,
2892 unsigned const_index,
2893 unsigned location,
2894 unsigned driver_location,
2895 unsigned component,
2896 unsigned num_components,
2897 bool is_patch,
2898 bool is_compact,
2899 bool load_input)
2900 {
2901 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2902 LLVMValueRef dw_addr, stride;
2903 LLVMValueRef value[4], result;
2904 unsigned param = shader_io_get_unique_index(location);
2905
2906 if (load_input) {
2907 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2908 dw_addr = get_tcs_in_current_patch_offset(ctx);
2909 } else {
2910 if (!is_patch) {
2911 stride = get_tcs_out_vertex_stride(ctx);
2912 dw_addr = get_tcs_out_current_patch_offset(ctx);
2913 } else {
2914 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2915 stride = NULL;
2916 }
2917 }
2918
2919 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2920 indir_index);
2921
2922 for (unsigned i = 0; i < num_components + component; i++) {
2923 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2924 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2925 ctx->ac.i32_1, "");
2926 }
2927 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2928 return result;
2929 }
2930
2931 static void
2932 store_tcs_output(struct ac_shader_abi *abi,
2933 LLVMValueRef vertex_index,
2934 LLVMValueRef param_index,
2935 unsigned const_index,
2936 unsigned location,
2937 unsigned driver_location,
2938 LLVMValueRef src,
2939 unsigned component,
2940 bool is_patch,
2941 bool is_compact,
2942 unsigned writemask)
2943 {
2944 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2945 LLVMValueRef dw_addr;
2946 LLVMValueRef stride = NULL;
2947 LLVMValueRef buf_addr = NULL;
2948 unsigned param;
2949 bool store_lds = true;
2950
2951 if (is_patch) {
2952 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2953 store_lds = false;
2954 } else {
2955 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2956 store_lds = false;
2957 }
2958
2959 param = shader_io_get_unique_index(location);
2960 if (location == VARYING_SLOT_CLIP_DIST0 &&
2961 is_compact && const_index > 3) {
2962 const_index -= 3;
2963 param++;
2964 }
2965
2966 if (!is_patch) {
2967 stride = get_tcs_out_vertex_stride(ctx);
2968 dw_addr = get_tcs_out_current_patch_offset(ctx);
2969 } else {
2970 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2971 }
2972
2973 mark_tess_output(ctx, is_patch, param);
2974
2975 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2976 param_index);
2977 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2978 vertex_index, param_index);
2979
2980 bool is_tess_factor = false;
2981 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2982 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2983 is_tess_factor = true;
2984
2985 unsigned base = is_compact ? const_index : 0;
2986 for (unsigned chan = 0; chan < 8; chan++) {
2987 if (!(writemask & (1 << chan)))
2988 continue;
2989 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2990
2991 if (store_lds || is_tess_factor) {
2992 LLVMValueRef dw_addr_chan =
2993 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2994 LLVMConstInt(ctx->ac.i32, chan, false), "");
2995 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2996 }
2997
2998 if (!is_tess_factor && writemask != 0xF)
2999 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
3000 buf_addr, ctx->oc_lds,
3001 4 * (base + chan), 1, 0, true, false);
3002 }
3003
3004 if (writemask == 0xF) {
3005 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
3006 buf_addr, ctx->oc_lds,
3007 (base * 4), 1, 0, true, false);
3008 }
3009 }
3010
3011 static LLVMValueRef
3012 load_tes_input(struct ac_shader_abi *abi,
3013 LLVMTypeRef type,
3014 LLVMValueRef vertex_index,
3015 LLVMValueRef param_index,
3016 unsigned const_index,
3017 unsigned location,
3018 unsigned driver_location,
3019 unsigned component,
3020 unsigned num_components,
3021 bool is_patch,
3022 bool is_compact,
3023 bool load_input)
3024 {
3025 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3026 LLVMValueRef buf_addr;
3027 LLVMValueRef result;
3028 unsigned param = shader_io_get_unique_index(location);
3029
3030 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3031 const_index -= 3;
3032 param++;
3033 }
3034
3035 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3036 is_compact, vertex_index, param_index);
3037
3038 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3039 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3040
3041 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3042 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3043 result = trim_vector(&ctx->ac, result, num_components);
3044 return result;
3045 }
3046
3047 static LLVMValueRef
3048 load_gs_input(struct ac_shader_abi *abi,
3049 unsigned location,
3050 unsigned driver_location,
3051 unsigned component,
3052 unsigned num_components,
3053 unsigned vertex_index,
3054 unsigned const_index,
3055 LLVMTypeRef type)
3056 {
3057 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3058 LLVMValueRef vtx_offset;
3059 unsigned param, vtx_offset_param;
3060 LLVMValueRef value[4], result;
3061
3062 vtx_offset_param = vertex_index;
3063 assert(vtx_offset_param < 6);
3064 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3065 LLVMConstInt(ctx->ac.i32, 4, false), "");
3066
3067 param = shader_io_get_unique_index(location);
3068
3069 for (unsigned i = component; i < num_components + component; i++) {
3070 if (ctx->ac.chip_class >= GFX9) {
3071 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3072 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3073 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3074 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3075 } else {
3076 LLVMValueRef soffset =
3077 LLVMConstInt(ctx->ac.i32,
3078 (param * 4 + i + const_index) * 256,
3079 false);
3080
3081 value[i] = ac_build_buffer_load(&ctx->ac,
3082 ctx->esgs_ring, 1,
3083 ctx->ac.i32_0,
3084 vtx_offset, soffset,
3085 0, 1, 0, true, false);
3086
3087 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3088 type, "");
3089 }
3090 }
3091 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3092 result = ac_to_integer(&ctx->ac, result);
3093 return result;
3094 }
3095
3096 static LLVMValueRef
3097 build_gep_for_deref(struct ac_nir_context *ctx,
3098 nir_deref_var *deref)
3099 {
3100 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3101 assert(entry->data);
3102 LLVMValueRef val = entry->data;
3103 nir_deref *tail = deref->deref.child;
3104 while (tail != NULL) {
3105 LLVMValueRef offset;
3106 switch (tail->deref_type) {
3107 case nir_deref_type_array: {
3108 nir_deref_array *array = nir_deref_as_array(tail);
3109 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3110 if (array->deref_array_type ==
3111 nir_deref_array_type_indirect) {
3112 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3113 get_src(ctx,
3114 array->indirect),
3115 "");
3116 }
3117 break;
3118 }
3119 case nir_deref_type_struct: {
3120 nir_deref_struct *deref_struct =
3121 nir_deref_as_struct(tail);
3122 offset = LLVMConstInt(ctx->ac.i32,
3123 deref_struct->index, 0);
3124 break;
3125 }
3126 default:
3127 unreachable("bad deref type");
3128 }
3129 val = ac_build_gep0(&ctx->ac, val, offset);
3130 tail = tail->child;
3131 }
3132 return val;
3133 }
3134
3135 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3136 nir_intrinsic_instr *instr,
3137 bool load_inputs)
3138 {
3139 LLVMValueRef result;
3140 LLVMValueRef vertex_index = NULL;
3141 LLVMValueRef indir_index = NULL;
3142 unsigned const_index = 0;
3143 unsigned location = instr->variables[0]->var->data.location;
3144 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3145 const bool is_patch = instr->variables[0]->var->data.patch;
3146 const bool is_compact = instr->variables[0]->var->data.compact;
3147
3148 get_deref_offset(ctx, instr->variables[0],
3149 false, NULL, is_patch ? NULL : &vertex_index,
3150 &const_index, &indir_index);
3151
3152 LLVMTypeRef dest_type = get_def_type(ctx, &instr->dest.ssa);
3153
3154 LLVMTypeRef src_component_type;
3155 if (LLVMGetTypeKind(dest_type) == LLVMVectorTypeKind)
3156 src_component_type = LLVMGetElementType(dest_type);
3157 else
3158 src_component_type = dest_type;
3159
3160 result = ctx->abi->load_tess_varyings(ctx->abi, src_component_type,
3161 vertex_index, indir_index,
3162 const_index, location, driver_location,
3163 instr->variables[0]->var->data.location_frac,
3164 instr->num_components,
3165 is_patch, is_compact, load_inputs);
3166 return LLVMBuildBitCast(ctx->ac.builder, result, dest_type, "");
3167 }
3168
3169 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3170 nir_intrinsic_instr *instr)
3171 {
3172 LLVMValueRef values[8];
3173 int idx = instr->variables[0]->var->data.driver_location;
3174 int ve = instr->dest.ssa.num_components;
3175 unsigned comp = instr->variables[0]->var->data.location_frac;
3176 LLVMValueRef indir_index;
3177 LLVMValueRef ret;
3178 unsigned const_index;
3179 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3180 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3181 instr->variables[0]->var->data.mode == nir_var_shader_in;
3182 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3183 &const_index, &indir_index);
3184
3185 if (instr->dest.ssa.bit_size == 64)
3186 ve *= 2;
3187
3188 switch (instr->variables[0]->var->data.mode) {
3189 case nir_var_shader_in:
3190 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3191 ctx->stage == MESA_SHADER_TESS_EVAL) {
3192 return load_tess_varyings(ctx, instr, true);
3193 }
3194
3195 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3196 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3197 LLVMValueRef indir_index;
3198 unsigned const_index, vertex_index;
3199 get_deref_offset(ctx, instr->variables[0],
3200 false, &vertex_index, NULL,
3201 &const_index, &indir_index);
3202
3203 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3204 instr->variables[0]->var->data.driver_location,
3205 instr->variables[0]->var->data.location_frac, ve,
3206 vertex_index, const_index, type);
3207 }
3208
3209 for (unsigned chan = comp; chan < ve + comp; chan++) {
3210 if (indir_index) {
3211 unsigned count = glsl_count_attribute_slots(
3212 instr->variables[0]->var->type,
3213 ctx->stage == MESA_SHADER_VERTEX);
3214 count -= chan / 4;
3215 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3216 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3217 stride, false, true);
3218
3219 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3220 tmp_vec,
3221 indir_index, "");
3222 } else
3223 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3224 }
3225 break;
3226 case nir_var_local:
3227 for (unsigned chan = 0; chan < ve; chan++) {
3228 if (indir_index) {
3229 unsigned count = glsl_count_attribute_slots(
3230 instr->variables[0]->var->type, false);
3231 count -= chan / 4;
3232 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3233 &ctx->ac, ctx->locals + idx + chan, count,
3234 stride, true, true);
3235
3236 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3237 tmp_vec,
3238 indir_index, "");
3239 } else {
3240 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3241 }
3242 }
3243 break;
3244 case nir_var_shared: {
3245 LLVMValueRef address = build_gep_for_deref(ctx,
3246 instr->variables[0]);
3247 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3248 return LLVMBuildBitCast(ctx->ac.builder, val,
3249 get_def_type(ctx, &instr->dest.ssa),
3250 "");
3251 }
3252 case nir_var_shader_out:
3253 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3254 return load_tess_varyings(ctx, instr, false);
3255 }
3256
3257 for (unsigned chan = comp; chan < ve + comp; chan++) {
3258 if (indir_index) {
3259 unsigned count = glsl_count_attribute_slots(
3260 instr->variables[0]->var->type, false);
3261 count -= chan / 4;
3262 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3263 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3264 stride, true, true);
3265
3266 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3267 tmp_vec,
3268 indir_index, "");
3269 } else {
3270 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3271 ctx->abi->outputs[idx + chan + const_index * stride],
3272 "");
3273 }
3274 }
3275 break;
3276 default:
3277 unreachable("unhandle variable mode");
3278 }
3279 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3280 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3281 }
3282
3283 static void
3284 visit_store_var(struct ac_nir_context *ctx,
3285 nir_intrinsic_instr *instr)
3286 {
3287 LLVMValueRef temp_ptr, value;
3288 int idx = instr->variables[0]->var->data.driver_location;
3289 unsigned comp = instr->variables[0]->var->data.location_frac;
3290 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3291 int writemask = instr->const_index[0] << comp;
3292 LLVMValueRef indir_index;
3293 unsigned const_index;
3294 get_deref_offset(ctx, instr->variables[0], false,
3295 NULL, NULL, &const_index, &indir_index);
3296
3297 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3298
3299 src = LLVMBuildBitCast(ctx->ac.builder, src,
3300 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3301 "");
3302
3303 writemask = widen_mask(writemask, 2);
3304 }
3305
3306 switch (instr->variables[0]->var->data.mode) {
3307 case nir_var_shader_out:
3308
3309 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3310 LLVMValueRef vertex_index = NULL;
3311 LLVMValueRef indir_index = NULL;
3312 unsigned const_index = 0;
3313 const unsigned location = instr->variables[0]->var->data.location;
3314 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3315 const unsigned comp = instr->variables[0]->var->data.location_frac;
3316 const bool is_patch = instr->variables[0]->var->data.patch;
3317 const bool is_compact = instr->variables[0]->var->data.compact;
3318
3319 get_deref_offset(ctx, instr->variables[0],
3320 false, NULL, is_patch ? NULL : &vertex_index,
3321 &const_index, &indir_index);
3322
3323 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3324 const_index, location, driver_location,
3325 src, comp, is_patch, is_compact, writemask);
3326 return;
3327 }
3328
3329 for (unsigned chan = 0; chan < 8; chan++) {
3330 int stride = 4;
3331 if (!(writemask & (1 << chan)))
3332 continue;
3333
3334 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3335
3336 if (instr->variables[0]->var->data.compact)
3337 stride = 1;
3338 if (indir_index) {
3339 unsigned count = glsl_count_attribute_slots(
3340 instr->variables[0]->var->type, false);
3341 count -= chan / 4;
3342 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3343 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3344 stride, true, true);
3345
3346 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3347 value, indir_index, "");
3348 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3349 count, stride, tmp_vec);
3350
3351 } else {
3352 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3353
3354 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3355 }
3356 }
3357 break;
3358 case nir_var_local:
3359 for (unsigned chan = 0; chan < 8; chan++) {
3360 if (!(writemask & (1 << chan)))
3361 continue;
3362
3363 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3364 if (indir_index) {
3365 unsigned count = glsl_count_attribute_slots(
3366 instr->variables[0]->var->type, false);
3367 count -= chan / 4;
3368 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3369 &ctx->ac, ctx->locals + idx + chan, count,
3370 4, true, true);
3371
3372 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3373 value, indir_index, "");
3374 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3375 count, 4, tmp_vec);
3376 } else {
3377 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3378
3379 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3380 }
3381 }
3382 break;
3383 case nir_var_shared: {
3384 int writemask = instr->const_index[0];
3385 LLVMValueRef address = build_gep_for_deref(ctx,
3386 instr->variables[0]);
3387 LLVMValueRef val = get_src(ctx, instr->src[0]);
3388 unsigned components =
3389 glsl_get_vector_elements(
3390 nir_deref_tail(&instr->variables[0]->deref)->type);
3391 if (writemask == (1 << components) - 1) {
3392 val = LLVMBuildBitCast(
3393 ctx->ac.builder, val,
3394 LLVMGetElementType(LLVMTypeOf(address)), "");
3395 LLVMBuildStore(ctx->ac.builder, val, address);
3396 } else {
3397 for (unsigned chan = 0; chan < 4; chan++) {
3398 if (!(writemask & (1 << chan)))
3399 continue;
3400 LLVMValueRef ptr =
3401 LLVMBuildStructGEP(ctx->ac.builder,
3402 address, chan, "");
3403 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3404 chan);
3405 src = LLVMBuildBitCast(
3406 ctx->ac.builder, src,
3407 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3408 LLVMBuildStore(ctx->ac.builder, src, ptr);
3409 }
3410 }
3411 break;
3412 }
3413 default:
3414 break;
3415 }
3416 }
3417
3418 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3419 {
3420 switch (dim) {
3421 case GLSL_SAMPLER_DIM_BUF:
3422 return 1;
3423 case GLSL_SAMPLER_DIM_1D:
3424 return array ? 2 : 1;
3425 case GLSL_SAMPLER_DIM_2D:
3426 return array ? 3 : 2;
3427 case GLSL_SAMPLER_DIM_MS:
3428 return array ? 4 : 3;
3429 case GLSL_SAMPLER_DIM_3D:
3430 case GLSL_SAMPLER_DIM_CUBE:
3431 return 3;
3432 case GLSL_SAMPLER_DIM_RECT:
3433 case GLSL_SAMPLER_DIM_SUBPASS:
3434 return 2;
3435 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3436 return 3;
3437 default:
3438 break;
3439 }
3440 return 0;
3441 }
3442
3443 static bool
3444 glsl_is_array_image(const struct glsl_type *type)
3445 {
3446 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3447
3448 if (glsl_sampler_type_is_array(type))
3449 return true;
3450
3451 return dim == GLSL_SAMPLER_DIM_CUBE ||
3452 dim == GLSL_SAMPLER_DIM_3D ||
3453 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3454 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3455 }
3456
3457
3458 /* Adjust the sample index according to FMASK.
3459 *
3460 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3461 * which is the identity mapping. Each nibble says which physical sample
3462 * should be fetched to get that sample.
3463 *
3464 * For example, 0x11111100 means there are only 2 samples stored and
3465 * the second sample covers 3/4 of the pixel. When reading samples 0
3466 * and 1, return physical sample 0 (determined by the first two 0s
3467 * in FMASK), otherwise return physical sample 1.
3468 *
3469 * The sample index should be adjusted as follows:
3470 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3471 */
3472 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3473 LLVMValueRef coord_x, LLVMValueRef coord_y,
3474 LLVMValueRef coord_z,
3475 LLVMValueRef sample_index,
3476 LLVMValueRef fmask_desc_ptr)
3477 {
3478 LLVMValueRef fmask_load_address[4];
3479 LLVMValueRef res;
3480
3481 fmask_load_address[0] = coord_x;
3482 fmask_load_address[1] = coord_y;
3483 if (coord_z) {
3484 fmask_load_address[2] = coord_z;
3485 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3486 }
3487
3488 struct ac_image_args args = {0};
3489
3490 args.opcode = ac_image_load;
3491 args.da = coord_z ? true : false;
3492 args.resource = fmask_desc_ptr;
3493 args.dmask = 0xf;
3494 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3495
3496 res = ac_build_image_opcode(ctx, &args);
3497
3498 res = ac_to_integer(ctx, res);
3499 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3500 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3501
3502 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3503 res,
3504 ctx->i32_0, "");
3505
3506 LLVMValueRef sample_index4 =
3507 LLVMBuildMul(ctx->builder, sample_index, four, "");
3508 LLVMValueRef shifted_fmask =
3509 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3510 LLVMValueRef final_sample =
3511 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3512
3513 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3514 * resource descriptor is 0 (invalid),
3515 */
3516 LLVMValueRef fmask_desc =
3517 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3518 ctx->v8i32, "");
3519
3520 LLVMValueRef fmask_word1 =
3521 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3522 ctx->i32_1, "");
3523
3524 LLVMValueRef word1_is_nonzero =
3525 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3526 fmask_word1, ctx->i32_0, "");
3527
3528 /* Replace the MSAA sample index. */
3529 sample_index =
3530 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3531 final_sample, sample_index, "");
3532 return sample_index;
3533 }
3534
3535 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3536 const nir_intrinsic_instr *instr)
3537 {
3538 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3539
3540 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3541 LLVMValueRef coords[4];
3542 LLVMValueRef masks[] = {
3543 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3544 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3545 };
3546 LLVMValueRef res;
3547 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3548
3549 int count;
3550 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3551 bool is_array = glsl_sampler_type_is_array(type);
3552 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3553 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3554 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3555 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3556 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3557 count = image_type_to_components_count(dim, is_array);
3558
3559 if (is_ms) {
3560 LLVMValueRef fmask_load_address[3];
3561 int chan;
3562
3563 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3564 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3565 if (is_array)
3566 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3567 else
3568 fmask_load_address[2] = NULL;
3569 if (add_frag_pos) {
3570 for (chan = 0; chan < 2; ++chan)
3571 fmask_load_address[chan] =
3572 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3573 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3574 ctx->ac.i32, ""), "");
3575 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3576 }
3577 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3578 fmask_load_address[0],
3579 fmask_load_address[1],
3580 fmask_load_address[2],
3581 sample_index,
3582 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3583 }
3584 if (count == 1 && !gfx9_1d) {
3585 if (instr->src[0].ssa->num_components)
3586 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3587 else
3588 res = src0;
3589 } else {
3590 int chan;
3591 if (is_ms)
3592 count--;
3593 for (chan = 0; chan < count; ++chan) {
3594 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3595 }
3596 if (add_frag_pos) {
3597 for (chan = 0; chan < 2; ++chan)
3598 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3599 ctx->ac.i32, ""), "");
3600 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3601 count++;
3602 }
3603
3604 if (gfx9_1d) {
3605 if (is_array) {
3606 coords[2] = coords[1];
3607 coords[1] = ctx->ac.i32_0;
3608 } else
3609 coords[1] = ctx->ac.i32_0;
3610 count++;
3611 }
3612
3613 if (is_ms) {
3614 coords[count] = sample_index;
3615 count++;
3616 }
3617
3618 if (count == 3) {
3619 coords[3] = LLVMGetUndef(ctx->ac.i32);
3620 count = 4;
3621 }
3622 res = ac_build_gather_values(&ctx->ac, coords, count);
3623 }
3624 return res;
3625 }
3626
3627 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3628 const nir_intrinsic_instr *instr)
3629 {
3630 LLVMValueRef params[7];
3631 LLVMValueRef res;
3632 char intrinsic_name[64];
3633 const nir_variable *var = instr->variables[0]->var;
3634 const struct glsl_type *type = var->type;
3635
3636 if(instr->variables[0]->deref.child)
3637 type = instr->variables[0]->deref.child->type;
3638
3639 type = glsl_without_array(type);
3640
3641 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3642 if (dim == GLSL_SAMPLER_DIM_BUF) {
3643 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3644 unsigned num_channels = util_last_bit(mask);
3645 LLVMValueRef rsrc, vindex;
3646
3647 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3648 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3649 ctx->ac.i32_0, "");
3650
3651 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3652 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3653 ctx->ac.i32_0, num_channels,
3654 false, false);
3655 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3656
3657 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3658 res = ac_to_integer(&ctx->ac, res);
3659 } else {
3660 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3661 LLVMValueRef slc = ctx->ac.i1false;
3662
3663 params[0] = get_image_coords(ctx, instr);
3664 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3665 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3666 params[3] = (var->data.image._volatile || var->data.image.coherent) ?
3667 ctx->ac.i1true : ctx->ac.i1false;
3668 params[4] = slc;
3669 params[5] = ctx->ac.i1false;
3670 params[6] = da;
3671
3672 ac_get_image_intr_name("llvm.amdgcn.image.load",
3673 ctx->ac.v4f32, /* vdata */
3674 LLVMTypeOf(params[0]), /* coords */
3675 LLVMTypeOf(params[1]), /* rsrc */
3676 intrinsic_name, sizeof(intrinsic_name));
3677
3678 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3679 params, 7, AC_FUNC_ATTR_READONLY);
3680 }
3681 return ac_to_integer(&ctx->ac, res);
3682 }
3683
3684 static void visit_image_store(struct ac_nir_context *ctx,
3685 nir_intrinsic_instr *instr)
3686 {
3687 LLVMValueRef params[8];
3688 char intrinsic_name[64];
3689 const nir_variable *var = instr->variables[0]->var;
3690 const struct glsl_type *type = glsl_without_array(var->type);
3691 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3692 LLVMValueRef glc = ctx->ac.i1false;
3693 bool force_glc = ctx->ac.chip_class == SI;
3694 if (force_glc)
3695 glc = ctx->ac.i1true;
3696
3697 if (dim == GLSL_SAMPLER_DIM_BUF) {
3698 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3699 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3700 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3701 ctx->ac.i32_0, ""); /* vindex */
3702 params[3] = ctx->ac.i32_0; /* voffset */
3703 params[4] = glc; /* glc */
3704 params[5] = ctx->ac.i1false; /* slc */
3705 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3706 params, 6, 0);
3707 } else {
3708 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3709 LLVMValueRef slc = ctx->ac.i1false;
3710
3711 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3712 params[1] = get_image_coords(ctx, instr); /* coords */
3713 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3714 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3715 params[4] = (force_glc || var->data.image._volatile || var->data.image.coherent) ?
3716 ctx->ac.i1true : ctx->ac.i1false;
3717 params[5] = slc;
3718 params[6] = ctx->ac.i1false;
3719 params[7] = da;
3720
3721 ac_get_image_intr_name("llvm.amdgcn.image.store",
3722 LLVMTypeOf(params[0]), /* vdata */
3723 LLVMTypeOf(params[1]), /* coords */
3724 LLVMTypeOf(params[2]), /* rsrc */
3725 intrinsic_name, sizeof(intrinsic_name));
3726
3727 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3728 params, 8, 0);
3729 }
3730
3731 }
3732
3733 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3734 const nir_intrinsic_instr *instr)
3735 {
3736 LLVMValueRef params[7];
3737 int param_count = 0;
3738 const nir_variable *var = instr->variables[0]->var;
3739
3740 const char *atomic_name;
3741 char intrinsic_name[41];
3742 const struct glsl_type *type = glsl_without_array(var->type);
3743 MAYBE_UNUSED int length;
3744
3745 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3746
3747 switch (instr->intrinsic) {
3748 case nir_intrinsic_image_atomic_add:
3749 atomic_name = "add";
3750 break;
3751 case nir_intrinsic_image_atomic_min:
3752 atomic_name = is_unsigned ? "umin" : "smin";
3753 break;
3754 case nir_intrinsic_image_atomic_max:
3755 atomic_name = is_unsigned ? "umax" : "smax";
3756 break;
3757 case nir_intrinsic_image_atomic_and:
3758 atomic_name = "and";
3759 break;
3760 case nir_intrinsic_image_atomic_or:
3761 atomic_name = "or";
3762 break;
3763 case nir_intrinsic_image_atomic_xor:
3764 atomic_name = "xor";
3765 break;
3766 case nir_intrinsic_image_atomic_exchange:
3767 atomic_name = "swap";
3768 break;
3769 case nir_intrinsic_image_atomic_comp_swap:
3770 atomic_name = "cmpswap";
3771 break;
3772 default:
3773 abort();
3774 }
3775
3776 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3777 params[param_count++] = get_src(ctx, instr->src[3]);
3778 params[param_count++] = get_src(ctx, instr->src[2]);
3779
3780 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3781 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3782 NULL, true, true);
3783 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3784 ctx->ac.i32_0, ""); /* vindex */
3785 params[param_count++] = ctx->ac.i32_0; /* voffset */
3786 params[param_count++] = ctx->ac.i1false; /* slc */
3787
3788 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3789 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3790 } else {
3791 char coords_type[8];
3792
3793 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3794 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3795 NULL, true, true);
3796 params[param_count++] = ctx->ac.i1false; /* r128 */
3797 params[param_count++] = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3798 params[param_count++] = ctx->ac.i1false; /* slc */
3799
3800 build_int_type_name(LLVMTypeOf(coords),
3801 coords_type, sizeof(coords_type));
3802
3803 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3804 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3805 }
3806
3807 assert(length < sizeof(intrinsic_name));
3808 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3809 }
3810
3811 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3812 const nir_intrinsic_instr *instr)
3813 {
3814 const nir_variable *var = instr->variables[0]->var;
3815 const struct glsl_type *type = glsl_without_array(var->type);
3816
3817 struct ac_image_args args = { 0 };
3818 args.da = glsl_is_array_image(type);
3819 args.dmask = 0xf;
3820 args.resource = get_sampler_desc(ctx, instr->variables[0],
3821 AC_DESC_IMAGE, NULL, true, false);
3822 args.opcode = ac_image_get_resinfo;
3823 args.addr = ctx->ac.i32_0;
3824
3825 return ac_build_image_opcode(&ctx->ac, &args);
3826 }
3827
3828 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3829 const nir_intrinsic_instr *instr)
3830 {
3831 LLVMValueRef res;
3832 const nir_variable *var = instr->variables[0]->var;
3833 const struct glsl_type *type = glsl_without_array(var->type);
3834
3835 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3836 return get_buffer_size(ctx,
3837 get_sampler_desc(ctx, instr->variables[0],
3838 AC_DESC_BUFFER, NULL, true, false), true);
3839
3840 struct ac_image_args args = { 0 };
3841
3842 args.da = glsl_is_array_image(type);
3843 args.dmask = 0xf;
3844 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3845 args.opcode = ac_image_get_resinfo;
3846 args.addr = ctx->ac.i32_0;
3847
3848 res = ac_build_image_opcode(&ctx->ac, &args);
3849
3850 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3851
3852 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3853 glsl_sampler_type_is_array(type)) {
3854 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3855 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3856 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3857 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3858 }
3859 if (ctx->ac.chip_class >= GFX9 &&
3860 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3861 glsl_sampler_type_is_array(type)) {
3862 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3863 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3864 ctx->ac.i32_1, "");
3865
3866 }
3867 return res;
3868 }
3869
3870 #define NOOP_WAITCNT 0xf7f
3871 #define LGKM_CNT 0x07f
3872 #define VM_CNT 0xf70
3873
3874 static void emit_membar(struct ac_llvm_context *ac,
3875 const nir_intrinsic_instr *instr)
3876 {
3877 unsigned waitcnt = NOOP_WAITCNT;
3878
3879 switch (instr->intrinsic) {
3880 case nir_intrinsic_memory_barrier:
3881 case nir_intrinsic_group_memory_barrier:
3882 waitcnt &= VM_CNT & LGKM_CNT;
3883 break;
3884 case nir_intrinsic_memory_barrier_atomic_counter:
3885 case nir_intrinsic_memory_barrier_buffer:
3886 case nir_intrinsic_memory_barrier_image:
3887 waitcnt &= VM_CNT;
3888 break;
3889 case nir_intrinsic_memory_barrier_shared:
3890 waitcnt &= LGKM_CNT;
3891 break;
3892 default:
3893 break;
3894 }
3895 if (waitcnt != NOOP_WAITCNT)
3896 ac_build_waitcnt(ac, waitcnt);
3897 }
3898
3899 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3900 {
3901 /* SI only (thanks to a hw bug workaround):
3902 * The real barrier instruction isn’t needed, because an entire patch
3903 * always fits into a single wave.
3904 */
3905 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3906 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3907 return;
3908 }
3909 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3910 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3911 }
3912
3913 static void emit_discard(struct ac_nir_context *ctx,
3914 const nir_intrinsic_instr *instr)
3915 {
3916 LLVMValueRef cond;
3917
3918 if (instr->intrinsic == nir_intrinsic_discard_if) {
3919 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3920 get_src(ctx, instr->src[0]),
3921 ctx->ac.i32_0, "");
3922 } else {
3923 assert(instr->intrinsic == nir_intrinsic_discard);
3924 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3925 }
3926
3927 ac_build_kill_if_false(&ctx->ac, cond);
3928 }
3929
3930 static LLVMValueRef
3931 visit_load_helper_invocation(struct ac_nir_context *ctx)
3932 {
3933 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3934 "llvm.amdgcn.ps.live",
3935 ctx->ac.i1, NULL, 0,
3936 AC_FUNC_ATTR_READNONE);
3937 result = LLVMBuildNot(ctx->ac.builder, result, "");
3938 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3939 }
3940
3941 static LLVMValueRef
3942 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3943 {
3944 LLVMValueRef result;
3945 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3946 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3947 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3948
3949 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3950 }
3951
3952 static LLVMValueRef
3953 visit_load_shared(struct ac_nir_context *ctx,
3954 const nir_intrinsic_instr *instr)
3955 {
3956 LLVMValueRef values[4], derived_ptr, index, ret;
3957
3958 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3959
3960 for (int chan = 0; chan < instr->num_components; chan++) {
3961 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3962 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3963 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3964 }
3965
3966 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3967 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3968 }
3969
3970 static void
3971 visit_store_shared(struct ac_nir_context *ctx,
3972 const nir_intrinsic_instr *instr)
3973 {
3974 LLVMValueRef derived_ptr, data,index;
3975 LLVMBuilderRef builder = ctx->ac.builder;
3976
3977 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3978 LLVMValueRef src = get_src(ctx, instr->src[0]);
3979
3980 int writemask = nir_intrinsic_write_mask(instr);
3981 for (int chan = 0; chan < 4; chan++) {
3982 if (!(writemask & (1 << chan))) {
3983 continue;
3984 }
3985 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3986 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3987 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3988 LLVMBuildStore(builder, data, derived_ptr);
3989 }
3990 }
3991
3992 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3993 const nir_intrinsic_instr *instr,
3994 LLVMValueRef ptr, int src_idx)
3995 {
3996 LLVMValueRef result;
3997 LLVMValueRef src = get_src(ctx, instr->src[src_idx]);
3998
3999 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
4000 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
4001 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
4002 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
4003 ptr, src, src1,
4004 LLVMAtomicOrderingSequentiallyConsistent,
4005 LLVMAtomicOrderingSequentiallyConsistent,
4006 false);
4007 } else {
4008 LLVMAtomicRMWBinOp op;
4009 switch (instr->intrinsic) {
4010 case nir_intrinsic_var_atomic_add:
4011 case nir_intrinsic_shared_atomic_add:
4012 op = LLVMAtomicRMWBinOpAdd;
4013 break;
4014 case nir_intrinsic_var_atomic_umin:
4015 case nir_intrinsic_shared_atomic_umin:
4016 op = LLVMAtomicRMWBinOpUMin;
4017 break;
4018 case nir_intrinsic_var_atomic_umax:
4019 case nir_intrinsic_shared_atomic_umax:
4020 op = LLVMAtomicRMWBinOpUMax;
4021 break;
4022 case nir_intrinsic_var_atomic_imin:
4023 case nir_intrinsic_shared_atomic_imin:
4024 op = LLVMAtomicRMWBinOpMin;
4025 break;
4026 case nir_intrinsic_var_atomic_imax:
4027 case nir_intrinsic_shared_atomic_imax:
4028 op = LLVMAtomicRMWBinOpMax;
4029 break;
4030 case nir_intrinsic_var_atomic_and:
4031 case nir_intrinsic_shared_atomic_and:
4032 op = LLVMAtomicRMWBinOpAnd;
4033 break;
4034 case nir_intrinsic_var_atomic_or:
4035 case nir_intrinsic_shared_atomic_or:
4036 op = LLVMAtomicRMWBinOpOr;
4037 break;
4038 case nir_intrinsic_var_atomic_xor:
4039 case nir_intrinsic_shared_atomic_xor:
4040 op = LLVMAtomicRMWBinOpXor;
4041 break;
4042 case nir_intrinsic_var_atomic_exchange:
4043 case nir_intrinsic_shared_atomic_exchange:
4044 op = LLVMAtomicRMWBinOpXchg;
4045 break;
4046 default:
4047 return NULL;
4048 }
4049
4050 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4051 LLVMAtomicOrderingSequentiallyConsistent,
4052 false);
4053 }
4054 return result;
4055 }
4056
4057 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4058 enum glsl_interp_mode interp, unsigned location)
4059 {
4060 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4061
4062 switch (interp) {
4063 case INTERP_MODE_FLAT:
4064 default:
4065 return NULL;
4066 case INTERP_MODE_SMOOTH:
4067 case INTERP_MODE_NONE:
4068 if (location == INTERP_CENTER)
4069 return ctx->persp_center;
4070 else if (location == INTERP_CENTROID)
4071 return ctx->persp_centroid;
4072 else if (location == INTERP_SAMPLE)
4073 return ctx->persp_sample;
4074 break;
4075 case INTERP_MODE_NOPERSPECTIVE:
4076 if (location == INTERP_CENTER)
4077 return ctx->linear_center;
4078 else if (location == INTERP_CENTROID)
4079 return ctx->linear_centroid;
4080 else if (location == INTERP_SAMPLE)
4081 return ctx->linear_sample;
4082 break;
4083 }
4084 return NULL;
4085 }
4086
4087 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4088 LLVMValueRef sample_id)
4089 {
4090 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4091
4092 LLVMValueRef result;
4093 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4094
4095 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4096 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4097
4098 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4099 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4100
4101 return result;
4102 }
4103
4104 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4105 {
4106 LLVMValueRef values[2];
4107
4108 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4109 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4110 return ac_build_gather_values(&ctx->ac, values, 2);
4111 }
4112
4113 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4114 {
4115 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4116 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4117 ctx->options->key.fs.log2_num_samples :
4118 ctx->options->key.fs.log2_ps_iter_samples;
4119
4120 /* The bit pattern matches that used by fixed function fragment
4121 * processing. */
4122 static const uint16_t ps_iter_masks[] = {
4123 0xffff, /* not used */
4124 0x5555,
4125 0x1111,
4126 0x0101,
4127 0x0001,
4128 };
4129 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4130
4131 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4132
4133 LLVMValueRef result, sample_id;
4134 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4135 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4136 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4137 return result;
4138 }
4139
4140 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4141 const nir_intrinsic_instr *instr)
4142 {
4143 LLVMValueRef result[4];
4144 LLVMValueRef interp_param, attr_number;
4145 unsigned location;
4146 unsigned chan;
4147 LLVMValueRef src_c0 = NULL;
4148 LLVMValueRef src_c1 = NULL;
4149 LLVMValueRef src0 = NULL;
4150 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4151 switch (instr->intrinsic) {
4152 case nir_intrinsic_interp_var_at_centroid:
4153 location = INTERP_CENTROID;
4154 break;
4155 case nir_intrinsic_interp_var_at_sample:
4156 case nir_intrinsic_interp_var_at_offset:
4157 location = INTERP_CENTER;
4158 src0 = get_src(ctx, instr->src[0]);
4159 break;
4160 default:
4161 break;
4162 }
4163
4164 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4165 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4166 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4167 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4168 LLVMValueRef sample_position;
4169 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4170
4171 /* fetch sample ID */
4172 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4173
4174 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4175 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4176 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4177 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4178 }
4179 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4180 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4181
4182 if (location == INTERP_CENTER) {
4183 LLVMValueRef ij_out[2];
4184 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4185
4186 /*
4187 * take the I then J parameters, and the DDX/Y for it, and
4188 * calculate the IJ inputs for the interpolator.
4189 * temp1 = ddx * offset/sample.x + I;
4190 * interp_param.I = ddy * offset/sample.y + temp1;
4191 * temp1 = ddx * offset/sample.x + J;
4192 * interp_param.J = ddy * offset/sample.y + temp1;
4193 */
4194 for (unsigned i = 0; i < 2; i++) {
4195 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4196 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4197 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4198 ddxy_out, ix_ll, "");
4199 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4200 ddxy_out, iy_ll, "");
4201 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4202 interp_param, ix_ll, "");
4203 LLVMValueRef temp1, temp2;
4204
4205 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4206 ctx->ac.f32, "");
4207
4208 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4209 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4210
4211 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4212 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4213
4214 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4215 temp2, ctx->ac.i32, "");
4216 }
4217 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4218
4219 }
4220
4221 for (chan = 0; chan < 4; chan++) {
4222 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4223
4224 if (interp_param) {
4225 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4226 interp_param, ctx->ac.v2f32, "");
4227 LLVMValueRef i = LLVMBuildExtractElement(
4228 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4229 LLVMValueRef j = LLVMBuildExtractElement(
4230 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4231
4232 result[chan] = ac_build_fs_interp(&ctx->ac,
4233 llvm_chan, attr_number,
4234 ctx->abi->prim_mask, i, j);
4235 } else {
4236 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4237 LLVMConstInt(ctx->ac.i32, 2, false),
4238 llvm_chan, attr_number,
4239 ctx->abi->prim_mask);
4240 }
4241 }
4242 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4243 instr->variables[0]->var->data.location_frac);
4244 }
4245
4246 static void
4247 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4248 {
4249 LLVMValueRef gs_next_vertex;
4250 LLVMValueRef can_emit;
4251 int idx;
4252 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4253
4254 assert(stream == 0);
4255
4256 /* Write vertex attribute values to GSVS ring */
4257 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4258 ctx->gs_next_vertex,
4259 "");
4260
4261 /* If this thread has already emitted the declared maximum number of
4262 * vertices, kill it: excessive vertex emissions are not supposed to
4263 * have any effect, and GS threads have no externally observable
4264 * effects other than emitting vertices.
4265 */
4266 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4267 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4268 ac_build_kill_if_false(&ctx->ac, can_emit);
4269
4270 /* loop num outputs */
4271 idx = 0;
4272 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4273 LLVMValueRef *out_ptr = &addrs[i * 4];
4274 int length = 4;
4275 int slot = idx;
4276 int slot_inc = 1;
4277
4278 if (!(ctx->output_mask & (1ull << i)))
4279 continue;
4280
4281 if (i == VARYING_SLOT_CLIP_DIST0) {
4282 /* pack clip and cull into a single set of slots */
4283 length = ctx->num_output_clips + ctx->num_output_culls;
4284 if (length > 4)
4285 slot_inc = 2;
4286 }
4287 for (unsigned j = 0; j < length; j++) {
4288 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4289 out_ptr[j], "");
4290 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4291 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4292 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4293
4294 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4295
4296 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4297 out_val, 1,
4298 voffset, ctx->gs2vs_offset, 0,
4299 1, 1, true, true);
4300 }
4301 idx += slot_inc;
4302 }
4303
4304 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4305 ctx->ac.i32_1, "");
4306 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4307
4308 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4309 }
4310
4311 static void
4312 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4313 {
4314 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4315 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4316 }
4317
4318 static LLVMValueRef
4319 load_tess_coord(struct ac_shader_abi *abi)
4320 {
4321 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4322
4323 LLVMValueRef coord[4] = {
4324 ctx->tes_u,
4325 ctx->tes_v,
4326 ctx->ac.f32_0,
4327 ctx->ac.f32_0,
4328 };
4329
4330 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4331 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4332 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4333
4334 return ac_build_gather_values(&ctx->ac, coord, 3);
4335 }
4336
4337 static LLVMValueRef
4338 load_patch_vertices_in(struct ac_shader_abi *abi)
4339 {
4340 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4341 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4342 }
4343
4344 static void visit_intrinsic(struct ac_nir_context *ctx,
4345 nir_intrinsic_instr *instr)
4346 {
4347 LLVMValueRef result = NULL;
4348
4349 switch (instr->intrinsic) {
4350 case nir_intrinsic_ballot:
4351 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4352 break;
4353 case nir_intrinsic_read_invocation:
4354 case nir_intrinsic_read_first_invocation: {
4355 LLVMValueRef args[2];
4356
4357 /* Value */
4358 args[0] = get_src(ctx, instr->src[0]);
4359
4360 unsigned num_args;
4361 const char *intr_name;
4362 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4363 num_args = 2;
4364 intr_name = "llvm.amdgcn.readlane";
4365
4366 /* Invocation */
4367 args[1] = get_src(ctx, instr->src[1]);
4368 } else {
4369 num_args = 1;
4370 intr_name = "llvm.amdgcn.readfirstlane";
4371 }
4372
4373 /* We currently have no other way to prevent LLVM from lifting the icmp
4374 * calls to a dominating basic block.
4375 */
4376 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4377
4378 result = ac_build_intrinsic(&ctx->ac, intr_name,
4379 ctx->ac.i32, args, num_args,
4380 AC_FUNC_ATTR_READNONE |
4381 AC_FUNC_ATTR_CONVERGENT);
4382 break;
4383 }
4384 case nir_intrinsic_load_subgroup_invocation:
4385 result = ac_get_thread_id(&ctx->ac);
4386 break;
4387 case nir_intrinsic_load_work_group_id: {
4388 LLVMValueRef values[3];
4389
4390 for (int i = 0; i < 3; i++) {
4391 values[i] = ctx->abi->workgroup_ids[i] ?
4392 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4393 }
4394
4395 result = ac_build_gather_values(&ctx->ac, values, 3);
4396 break;
4397 }
4398 case nir_intrinsic_load_base_vertex: {
4399 result = ctx->abi->load_base_vertex(ctx->abi);
4400 break;
4401 }
4402 case nir_intrinsic_load_local_group_size:
4403 result = ctx->abi->load_local_group_size(ctx->abi);
4404 break;
4405 case nir_intrinsic_load_vertex_id:
4406 result = LLVMBuildAdd(ctx->ac.builder, ctx->abi->vertex_id,
4407 ctx->abi->base_vertex, "");
4408 break;
4409 case nir_intrinsic_load_vertex_id_zero_base: {
4410 result = ctx->abi->vertex_id;
4411 break;
4412 }
4413 case nir_intrinsic_load_local_invocation_id: {
4414 result = ctx->abi->local_invocation_ids;
4415 break;
4416 }
4417 case nir_intrinsic_load_base_instance:
4418 result = ctx->abi->start_instance;
4419 break;
4420 case nir_intrinsic_load_draw_id:
4421 result = ctx->abi->draw_id;
4422 break;
4423 case nir_intrinsic_load_view_index:
4424 result = ctx->abi->view_index;
4425 break;
4426 case nir_intrinsic_load_invocation_id:
4427 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4428 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4429 else
4430 result = ctx->abi->gs_invocation_id;
4431 break;
4432 case nir_intrinsic_load_primitive_id:
4433 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4434 result = ctx->abi->gs_prim_id;
4435 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4436 result = ctx->abi->tcs_patch_id;
4437 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4438 result = ctx->abi->tes_patch_id;
4439 } else
4440 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4441 break;
4442 case nir_intrinsic_load_sample_id:
4443 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4444 break;
4445 case nir_intrinsic_load_sample_pos:
4446 result = load_sample_pos(ctx);
4447 break;
4448 case nir_intrinsic_load_sample_mask_in:
4449 result = ctx->abi->load_sample_mask_in(ctx->abi);
4450 break;
4451 case nir_intrinsic_load_frag_coord: {
4452 LLVMValueRef values[4] = {
4453 ctx->abi->frag_pos[0],
4454 ctx->abi->frag_pos[1],
4455 ctx->abi->frag_pos[2],
4456 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4457 };
4458 result = ac_build_gather_values(&ctx->ac, values, 4);
4459 break;
4460 }
4461 case nir_intrinsic_load_front_face:
4462 result = ctx->abi->front_face;
4463 break;
4464 case nir_intrinsic_load_helper_invocation:
4465 result = visit_load_helper_invocation(ctx);
4466 break;
4467 case nir_intrinsic_load_instance_id:
4468 result = ctx->abi->instance_id;
4469 break;
4470 case nir_intrinsic_load_num_work_groups:
4471 result = ctx->abi->num_work_groups;
4472 break;
4473 case nir_intrinsic_load_local_invocation_index:
4474 result = visit_load_local_invocation_index(ctx);
4475 break;
4476 case nir_intrinsic_load_push_constant:
4477 result = visit_load_push_constant(ctx, instr);
4478 break;
4479 case nir_intrinsic_vulkan_resource_index: {
4480 LLVMValueRef index = get_src(ctx, instr->src[0]);
4481 unsigned desc_set = nir_intrinsic_desc_set(instr);
4482 unsigned binding = nir_intrinsic_binding(instr);
4483
4484 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4485 binding);
4486 break;
4487 }
4488 case nir_intrinsic_vulkan_resource_reindex:
4489 result = visit_vulkan_resource_reindex(ctx, instr);
4490 break;
4491 case nir_intrinsic_store_ssbo:
4492 visit_store_ssbo(ctx, instr);
4493 break;
4494 case nir_intrinsic_load_ssbo:
4495 result = visit_load_buffer(ctx, instr);
4496 break;
4497 case nir_intrinsic_ssbo_atomic_add:
4498 case nir_intrinsic_ssbo_atomic_imin:
4499 case nir_intrinsic_ssbo_atomic_umin:
4500 case nir_intrinsic_ssbo_atomic_imax:
4501 case nir_intrinsic_ssbo_atomic_umax:
4502 case nir_intrinsic_ssbo_atomic_and:
4503 case nir_intrinsic_ssbo_atomic_or:
4504 case nir_intrinsic_ssbo_atomic_xor:
4505 case nir_intrinsic_ssbo_atomic_exchange:
4506 case nir_intrinsic_ssbo_atomic_comp_swap:
4507 result = visit_atomic_ssbo(ctx, instr);
4508 break;
4509 case nir_intrinsic_load_ubo:
4510 result = visit_load_ubo_buffer(ctx, instr);
4511 break;
4512 case nir_intrinsic_get_buffer_size:
4513 result = visit_get_buffer_size(ctx, instr);
4514 break;
4515 case nir_intrinsic_load_var:
4516 result = visit_load_var(ctx, instr);
4517 break;
4518 case nir_intrinsic_store_var:
4519 visit_store_var(ctx, instr);
4520 break;
4521 case nir_intrinsic_load_shared:
4522 result = visit_load_shared(ctx, instr);
4523 break;
4524 case nir_intrinsic_store_shared:
4525 visit_store_shared(ctx, instr);
4526 break;
4527 case nir_intrinsic_image_samples:
4528 result = visit_image_samples(ctx, instr);
4529 break;
4530 case nir_intrinsic_image_load:
4531 result = visit_image_load(ctx, instr);
4532 break;
4533 case nir_intrinsic_image_store:
4534 visit_image_store(ctx, instr);
4535 break;
4536 case nir_intrinsic_image_atomic_add:
4537 case nir_intrinsic_image_atomic_min:
4538 case nir_intrinsic_image_atomic_max:
4539 case nir_intrinsic_image_atomic_and:
4540 case nir_intrinsic_image_atomic_or:
4541 case nir_intrinsic_image_atomic_xor:
4542 case nir_intrinsic_image_atomic_exchange:
4543 case nir_intrinsic_image_atomic_comp_swap:
4544 result = visit_image_atomic(ctx, instr);
4545 break;
4546 case nir_intrinsic_image_size:
4547 result = visit_image_size(ctx, instr);
4548 break;
4549 case nir_intrinsic_shader_clock:
4550 result = ac_build_shader_clock(&ctx->ac);
4551 break;
4552 case nir_intrinsic_discard:
4553 case nir_intrinsic_discard_if:
4554 emit_discard(ctx, instr);
4555 break;
4556 case nir_intrinsic_memory_barrier:
4557 case nir_intrinsic_group_memory_barrier:
4558 case nir_intrinsic_memory_barrier_atomic_counter:
4559 case nir_intrinsic_memory_barrier_buffer:
4560 case nir_intrinsic_memory_barrier_image:
4561 case nir_intrinsic_memory_barrier_shared:
4562 emit_membar(&ctx->ac, instr);
4563 break;
4564 case nir_intrinsic_barrier:
4565 emit_barrier(&ctx->ac, ctx->stage);
4566 break;
4567 case nir_intrinsic_shared_atomic_add:
4568 case nir_intrinsic_shared_atomic_imin:
4569 case nir_intrinsic_shared_atomic_umin:
4570 case nir_intrinsic_shared_atomic_imax:
4571 case nir_intrinsic_shared_atomic_umax:
4572 case nir_intrinsic_shared_atomic_and:
4573 case nir_intrinsic_shared_atomic_or:
4574 case nir_intrinsic_shared_atomic_xor:
4575 case nir_intrinsic_shared_atomic_exchange:
4576 case nir_intrinsic_shared_atomic_comp_swap: {
4577 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
4578 result = visit_var_atomic(ctx, instr, ptr, 1);
4579 break;
4580 }
4581 case nir_intrinsic_var_atomic_add:
4582 case nir_intrinsic_var_atomic_imin:
4583 case nir_intrinsic_var_atomic_umin:
4584 case nir_intrinsic_var_atomic_imax:
4585 case nir_intrinsic_var_atomic_umax:
4586 case nir_intrinsic_var_atomic_and:
4587 case nir_intrinsic_var_atomic_or:
4588 case nir_intrinsic_var_atomic_xor:
4589 case nir_intrinsic_var_atomic_exchange:
4590 case nir_intrinsic_var_atomic_comp_swap: {
4591 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4592 result = visit_var_atomic(ctx, instr, ptr, 0);
4593 break;
4594 }
4595 case nir_intrinsic_interp_var_at_centroid:
4596 case nir_intrinsic_interp_var_at_sample:
4597 case nir_intrinsic_interp_var_at_offset:
4598 result = visit_interp(ctx, instr);
4599 break;
4600 case nir_intrinsic_emit_vertex:
4601 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4602 break;
4603 case nir_intrinsic_end_primitive:
4604 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4605 break;
4606 case nir_intrinsic_load_tess_coord:
4607 result = ctx->abi->load_tess_coord(ctx->abi);
4608 break;
4609 case nir_intrinsic_load_tess_level_outer:
4610 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4611 break;
4612 case nir_intrinsic_load_tess_level_inner:
4613 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4614 break;
4615 case nir_intrinsic_load_patch_vertices_in:
4616 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4617 break;
4618 case nir_intrinsic_vote_all: {
4619 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4620 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4621 break;
4622 }
4623 case nir_intrinsic_vote_any: {
4624 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4625 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4626 break;
4627 }
4628 case nir_intrinsic_vote_eq: {
4629 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4630 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4631 break;
4632 }
4633 default:
4634 fprintf(stderr, "Unknown intrinsic: ");
4635 nir_print_instr(&instr->instr, stderr);
4636 fprintf(stderr, "\n");
4637 break;
4638 }
4639 if (result) {
4640 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4641 }
4642 }
4643
4644 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
4645 {
4646 return abi->base_vertex;
4647 }
4648
4649 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4650 LLVMValueRef buffer_ptr, bool write)
4651 {
4652 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4653 LLVMValueRef result;
4654
4655 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4656
4657 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4658 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4659
4660 return result;
4661 }
4662
4663 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4664 {
4665 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4666 LLVMValueRef result;
4667
4668 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4669
4670 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4671 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4672
4673 return result;
4674 }
4675
4676 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4677 unsigned descriptor_set,
4678 unsigned base_index,
4679 unsigned constant_index,
4680 LLVMValueRef index,
4681 enum ac_descriptor_type desc_type,
4682 bool image, bool write)
4683 {
4684 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4685 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4686 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4687 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4688 unsigned offset = binding->offset;
4689 unsigned stride = binding->size;
4690 unsigned type_size;
4691 LLVMBuilderRef builder = ctx->ac.builder;
4692 LLVMTypeRef type;
4693
4694 assert(base_index < layout->binding_count);
4695
4696 switch (desc_type) {
4697 case AC_DESC_IMAGE:
4698 type = ctx->ac.v8i32;
4699 type_size = 32;
4700 break;
4701 case AC_DESC_FMASK:
4702 type = ctx->ac.v8i32;
4703 offset += 32;
4704 type_size = 32;
4705 break;
4706 case AC_DESC_SAMPLER:
4707 type = ctx->ac.v4i32;
4708 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4709 offset += 64;
4710
4711 type_size = 16;
4712 break;
4713 case AC_DESC_BUFFER:
4714 type = ctx->ac.v4i32;
4715 type_size = 16;
4716 break;
4717 default:
4718 unreachable("invalid desc_type\n");
4719 }
4720
4721 offset += constant_index * stride;
4722
4723 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4724 (!index || binding->immutable_samplers_equal)) {
4725 if (binding->immutable_samplers_equal)
4726 constant_index = 0;
4727
4728 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4729
4730 LLVMValueRef constants[] = {
4731 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4732 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4733 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4734 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4735 };
4736 return ac_build_gather_values(&ctx->ac, constants, 4);
4737 }
4738
4739 assert(stride % type_size == 0);
4740
4741 if (!index)
4742 index = ctx->ac.i32_0;
4743
4744 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4745
4746 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4747 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4748
4749 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4750 }
4751
4752 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4753 const nir_deref_var *deref,
4754 enum ac_descriptor_type desc_type,
4755 const nir_tex_instr *tex_instr,
4756 bool image, bool write)
4757 {
4758 LLVMValueRef index = NULL;
4759 unsigned constant_index = 0;
4760 unsigned descriptor_set;
4761 unsigned base_index;
4762
4763 if (!deref) {
4764 assert(tex_instr && !image);
4765 descriptor_set = 0;
4766 base_index = tex_instr->sampler_index;
4767 } else {
4768 const nir_deref *tail = &deref->deref;
4769 while (tail->child) {
4770 const nir_deref_array *child = nir_deref_as_array(tail->child);
4771 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4772
4773 if (!array_size)
4774 array_size = 1;
4775
4776 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4777
4778 if (child->deref_array_type == nir_deref_array_type_indirect) {
4779 LLVMValueRef indirect = get_src(ctx, child->indirect);
4780
4781 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4782 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4783
4784 if (!index)
4785 index = indirect;
4786 else
4787 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4788 }
4789
4790 constant_index += child->base_offset * array_size;
4791
4792 tail = &child->deref;
4793 }
4794 descriptor_set = deref->var->data.descriptor_set;
4795 base_index = deref->var->data.binding;
4796 }
4797
4798 return ctx->abi->load_sampler_desc(ctx->abi,
4799 descriptor_set,
4800 base_index,
4801 constant_index, index,
4802 desc_type, image, write);
4803 }
4804
4805 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4806 struct ac_image_args *args,
4807 const nir_tex_instr *instr,
4808 nir_texop op,
4809 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4810 LLVMValueRef *param, unsigned count,
4811 unsigned dmask)
4812 {
4813 unsigned is_rect = 0;
4814 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4815
4816 if (op == nir_texop_lod)
4817 da = false;
4818 /* Pad to power of two vector */
4819 while (count < util_next_power_of_two(count))
4820 param[count++] = LLVMGetUndef(ctx->i32);
4821
4822 if (count > 1)
4823 args->addr = ac_build_gather_values(ctx, param, count);
4824 else
4825 args->addr = param[0];
4826
4827 args->resource = res_ptr;
4828 args->sampler = samp_ptr;
4829
4830 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4831 args->addr = param[0];
4832 return;
4833 }
4834
4835 args->dmask = dmask;
4836 args->unorm = is_rect;
4837 args->da = da;
4838 }
4839
4840 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4841 *
4842 * SI-CI:
4843 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4844 * filtering manually. The driver sets img7 to a mask clearing
4845 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4846 * s_and_b32 samp0, samp0, img7
4847 *
4848 * VI:
4849 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4850 */
4851 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4852 LLVMValueRef res, LLVMValueRef samp)
4853 {
4854 LLVMBuilderRef builder = ctx->ac.builder;
4855 LLVMValueRef img7, samp0;
4856
4857 if (ctx->ac.chip_class >= VI)
4858 return samp;
4859
4860 img7 = LLVMBuildExtractElement(builder, res,
4861 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4862 samp0 = LLVMBuildExtractElement(builder, samp,
4863 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4864 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4865 return LLVMBuildInsertElement(builder, samp, samp0,
4866 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4867 }
4868
4869 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4870 nir_tex_instr *instr,
4871 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4872 LLVMValueRef *fmask_ptr)
4873 {
4874 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4875 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4876 else
4877 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4878 if (samp_ptr) {
4879 if (instr->sampler)
4880 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4881 else
4882 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4883 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4884 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4885 }
4886 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4887 instr->op == nir_texop_samples_identical))
4888 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4889 }
4890
4891 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4892 LLVMValueRef coord)
4893 {
4894 coord = ac_to_float(ctx, coord);
4895 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4896 coord = ac_to_integer(ctx, coord);
4897 return coord;
4898 }
4899
4900 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4901 {
4902 LLVMValueRef result = NULL;
4903 struct ac_image_args args = { 0 };
4904 unsigned dmask = 0xf;
4905 LLVMValueRef address[16];
4906 LLVMValueRef coords[5];
4907 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4908 LLVMValueRef bias = NULL, offsets = NULL;
4909 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4910 LLVMValueRef ddx = NULL, ddy = NULL;
4911 LLVMValueRef derivs[6];
4912 unsigned chan, count = 0;
4913 unsigned const_src = 0, num_deriv_comp = 0;
4914 bool lod_is_zero = false;
4915
4916 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4917
4918 for (unsigned i = 0; i < instr->num_srcs; i++) {
4919 switch (instr->src[i].src_type) {
4920 case nir_tex_src_coord:
4921 coord = get_src(ctx, instr->src[i].src);
4922 break;
4923 case nir_tex_src_projector:
4924 break;
4925 case nir_tex_src_comparator:
4926 comparator = get_src(ctx, instr->src[i].src);
4927 break;
4928 case nir_tex_src_offset:
4929 offsets = get_src(ctx, instr->src[i].src);
4930 const_src = i;
4931 break;
4932 case nir_tex_src_bias:
4933 bias = get_src(ctx, instr->src[i].src);
4934 break;
4935 case nir_tex_src_lod: {
4936 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4937
4938 if (val && val->i32[0] == 0)
4939 lod_is_zero = true;
4940 lod = get_src(ctx, instr->src[i].src);
4941 break;
4942 }
4943 case nir_tex_src_ms_index:
4944 sample_index = get_src(ctx, instr->src[i].src);
4945 break;
4946 case nir_tex_src_ms_mcs:
4947 break;
4948 case nir_tex_src_ddx:
4949 ddx = get_src(ctx, instr->src[i].src);
4950 num_deriv_comp = instr->src[i].src.ssa->num_components;
4951 break;
4952 case nir_tex_src_ddy:
4953 ddy = get_src(ctx, instr->src[i].src);
4954 break;
4955 case nir_tex_src_texture_offset:
4956 case nir_tex_src_sampler_offset:
4957 case nir_tex_src_plane:
4958 default:
4959 break;
4960 }
4961 }
4962
4963 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4964 result = get_buffer_size(ctx, res_ptr, true);
4965 goto write_result;
4966 }
4967
4968 if (instr->op == nir_texop_texture_samples) {
4969 LLVMValueRef res, samples, is_msaa;
4970 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4971 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4972 LLVMConstInt(ctx->ac.i32, 3, false), "");
4973 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4974 LLVMConstInt(ctx->ac.i32, 28, false), "");
4975 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4976 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4977 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4978 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4979
4980 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4981 LLVMConstInt(ctx->ac.i32, 16, false), "");
4982 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4983 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4984 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4985 samples, "");
4986 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4987 ctx->ac.i32_1, "");
4988 result = samples;
4989 goto write_result;
4990 }
4991
4992 if (coord)
4993 for (chan = 0; chan < instr->coord_components; chan++)
4994 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4995
4996 if (offsets && instr->op != nir_texop_txf) {
4997 LLVMValueRef offset[3], pack;
4998 for (chan = 0; chan < 3; ++chan)
4999 offset[chan] = ctx->ac.i32_0;
5000
5001 args.offset = true;
5002 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
5003 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
5004 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
5005 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
5006 if (chan)
5007 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
5008 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
5009 }
5010 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
5011 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
5012 address[count++] = pack;
5013
5014 }
5015 /* pack LOD bias value */
5016 if (instr->op == nir_texop_txb && bias) {
5017 address[count++] = bias;
5018 }
5019
5020 /* Pack depth comparison value */
5021 if (instr->is_shadow && comparator) {
5022 LLVMValueRef z = ac_to_float(&ctx->ac,
5023 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
5024
5025 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
5026 * so the depth comparison value isn't clamped for Z16 and
5027 * Z24 anymore. Do it manually here.
5028 *
5029 * It's unnecessary if the original texture format was
5030 * Z32_FLOAT, but we don't know that here.
5031 */
5032 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5033 z = ac_build_clamp(&ctx->ac, z);
5034
5035 address[count++] = z;
5036 }
5037
5038 /* pack derivatives */
5039 if (ddx || ddy) {
5040 int num_src_deriv_channels, num_dest_deriv_channels;
5041 switch (instr->sampler_dim) {
5042 case GLSL_SAMPLER_DIM_3D:
5043 case GLSL_SAMPLER_DIM_CUBE:
5044 num_deriv_comp = 3;
5045 num_src_deriv_channels = 3;
5046 num_dest_deriv_channels = 3;
5047 break;
5048 case GLSL_SAMPLER_DIM_2D:
5049 default:
5050 num_src_deriv_channels = 2;
5051 num_dest_deriv_channels = 2;
5052 num_deriv_comp = 2;
5053 break;
5054 case GLSL_SAMPLER_DIM_1D:
5055 num_src_deriv_channels = 1;
5056 if (ctx->ac.chip_class >= GFX9) {
5057 num_dest_deriv_channels = 2;
5058 num_deriv_comp = 2;
5059 } else {
5060 num_dest_deriv_channels = 1;
5061 num_deriv_comp = 1;
5062 }
5063 break;
5064 }
5065
5066 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5067 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5068 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5069 }
5070 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5071 derivs[i] = ctx->ac.f32_0;
5072 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5073 }
5074 }
5075
5076 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5077 for (chan = 0; chan < instr->coord_components; chan++)
5078 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5079 if (instr->coord_components == 3)
5080 coords[3] = LLVMGetUndef(ctx->ac.f32);
5081 ac_prepare_cube_coords(&ctx->ac,
5082 instr->op == nir_texop_txd, instr->is_array,
5083 instr->op == nir_texop_lod, coords, derivs);
5084 if (num_deriv_comp)
5085 num_deriv_comp--;
5086 }
5087
5088 if (ddx || ddy) {
5089 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5090 address[count++] = derivs[i];
5091 }
5092
5093 /* Pack texture coordinates */
5094 if (coord) {
5095 address[count++] = coords[0];
5096 if (instr->coord_components > 1) {
5097 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5098 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5099 }
5100 address[count++] = coords[1];
5101 }
5102 if (instr->coord_components > 2) {
5103 if ((instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
5104 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
5105 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
5106 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
5107 instr->is_array &&
5108 instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
5109 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5110 }
5111 address[count++] = coords[2];
5112 }
5113
5114 if (ctx->ac.chip_class >= GFX9) {
5115 LLVMValueRef filler;
5116 if (instr->op == nir_texop_txf)
5117 filler = ctx->ac.i32_0;
5118 else
5119 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5120
5121 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5122 /* No nir_texop_lod, because it does not take a slice
5123 * even with array textures. */
5124 if (instr->is_array && instr->op != nir_texop_lod ) {
5125 address[count] = address[count - 1];
5126 address[count - 1] = filler;
5127 count++;
5128 } else
5129 address[count++] = filler;
5130 }
5131 }
5132 }
5133
5134 /* Pack LOD */
5135 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5136 instr->op == nir_texop_txf)) {
5137 address[count++] = lod;
5138 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5139 address[count++] = sample_index;
5140 } else if(instr->op == nir_texop_txs) {
5141 count = 0;
5142 if (lod)
5143 address[count++] = lod;
5144 else
5145 address[count++] = ctx->ac.i32_0;
5146 }
5147
5148 for (chan = 0; chan < count; chan++) {
5149 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5150 address[chan], ctx->ac.i32, "");
5151 }
5152
5153 if (instr->op == nir_texop_samples_identical) {
5154 LLVMValueRef txf_address[4];
5155 struct ac_image_args txf_args = { 0 };
5156 unsigned txf_count = count;
5157 memcpy(txf_address, address, sizeof(txf_address));
5158
5159 if (!instr->is_array)
5160 txf_address[2] = ctx->ac.i32_0;
5161 txf_address[3] = ctx->ac.i32_0;
5162
5163 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5164 fmask_ptr, NULL,
5165 txf_address, txf_count, 0xf);
5166
5167 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5168
5169 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5170 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5171 goto write_result;
5172 }
5173
5174 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5175 instr->op != nir_texop_txs) {
5176 unsigned sample_chan = instr->is_array ? 3 : 2;
5177 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5178 address[0],
5179 address[1],
5180 instr->is_array ? address[2] : NULL,
5181 address[sample_chan],
5182 fmask_ptr);
5183 }
5184
5185 if (offsets && instr->op == nir_texop_txf) {
5186 nir_const_value *const_offset =
5187 nir_src_as_const_value(instr->src[const_src].src);
5188 int num_offsets = instr->src[const_src].src.ssa->num_components;
5189 assert(const_offset);
5190 num_offsets = MIN2(num_offsets, instr->coord_components);
5191 if (num_offsets > 2)
5192 address[2] = LLVMBuildAdd(ctx->ac.builder,
5193 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5194 if (num_offsets > 1)
5195 address[1] = LLVMBuildAdd(ctx->ac.builder,
5196 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5197 address[0] = LLVMBuildAdd(ctx->ac.builder,
5198 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5199
5200 }
5201
5202 /* TODO TG4 support */
5203 if (instr->op == nir_texop_tg4) {
5204 if (instr->is_shadow)
5205 dmask = 1;
5206 else
5207 dmask = 1 << instr->component;
5208 }
5209 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5210 res_ptr, samp_ptr, address, count, dmask);
5211
5212 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5213
5214 if (instr->op == nir_texop_query_levels)
5215 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5216 else if (instr->is_shadow && instr->is_new_style_shadow &&
5217 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5218 instr->op != nir_texop_tg4)
5219 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5220 else if (instr->op == nir_texop_txs &&
5221 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5222 instr->is_array) {
5223 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5224 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5225 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5226 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5227 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5228 } else if (ctx->ac.chip_class >= GFX9 &&
5229 instr->op == nir_texop_txs &&
5230 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5231 instr->is_array) {
5232 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5233 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5234 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5235 ctx->ac.i32_1, "");
5236 } else if (instr->dest.ssa.num_components != 4)
5237 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5238
5239 write_result:
5240 if (result) {
5241 assert(instr->dest.is_ssa);
5242 result = ac_to_integer(&ctx->ac, result);
5243 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5244 }
5245 }
5246
5247
5248 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5249 {
5250 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5251 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5252
5253 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5254 _mesa_hash_table_insert(ctx->phis, instr, result);
5255 }
5256
5257 static void visit_post_phi(struct ac_nir_context *ctx,
5258 nir_phi_instr *instr,
5259 LLVMValueRef llvm_phi)
5260 {
5261 nir_foreach_phi_src(src, instr) {
5262 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5263 LLVMValueRef llvm_src = get_src(ctx, src->src);
5264
5265 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5266 }
5267 }
5268
5269 static void phi_post_pass(struct ac_nir_context *ctx)
5270 {
5271 struct hash_entry *entry;
5272 hash_table_foreach(ctx->phis, entry) {
5273 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5274 (LLVMValueRef)entry->data);
5275 }
5276 }
5277
5278
5279 static void visit_ssa_undef(struct ac_nir_context *ctx,
5280 const nir_ssa_undef_instr *instr)
5281 {
5282 unsigned num_components = instr->def.num_components;
5283 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5284 LLVMValueRef undef;
5285
5286 if (num_components == 1)
5287 undef = LLVMGetUndef(type);
5288 else {
5289 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5290 }
5291 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5292 }
5293
5294 static void visit_jump(struct ac_nir_context *ctx,
5295 const nir_jump_instr *instr)
5296 {
5297 switch (instr->type) {
5298 case nir_jump_break:
5299 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5300 LLVMClearInsertionPosition(ctx->ac.builder);
5301 break;
5302 case nir_jump_continue:
5303 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5304 LLVMClearInsertionPosition(ctx->ac.builder);
5305 break;
5306 default:
5307 fprintf(stderr, "Unknown NIR jump instr: ");
5308 nir_print_instr(&instr->instr, stderr);
5309 fprintf(stderr, "\n");
5310 abort();
5311 }
5312 }
5313
5314 static void visit_cf_list(struct ac_nir_context *ctx,
5315 struct exec_list *list);
5316
5317 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5318 {
5319 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5320 nir_foreach_instr(instr, block)
5321 {
5322 switch (instr->type) {
5323 case nir_instr_type_alu:
5324 visit_alu(ctx, nir_instr_as_alu(instr));
5325 break;
5326 case nir_instr_type_load_const:
5327 visit_load_const(ctx, nir_instr_as_load_const(instr));
5328 break;
5329 case nir_instr_type_intrinsic:
5330 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5331 break;
5332 case nir_instr_type_tex:
5333 visit_tex(ctx, nir_instr_as_tex(instr));
5334 break;
5335 case nir_instr_type_phi:
5336 visit_phi(ctx, nir_instr_as_phi(instr));
5337 break;
5338 case nir_instr_type_ssa_undef:
5339 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5340 break;
5341 case nir_instr_type_jump:
5342 visit_jump(ctx, nir_instr_as_jump(instr));
5343 break;
5344 default:
5345 fprintf(stderr, "Unknown NIR instr type: ");
5346 nir_print_instr(instr, stderr);
5347 fprintf(stderr, "\n");
5348 abort();
5349 }
5350 }
5351
5352 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5353 }
5354
5355 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5356 {
5357 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5358
5359 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5360 LLVMBasicBlockRef merge_block =
5361 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5362 LLVMBasicBlockRef if_block =
5363 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5364 LLVMBasicBlockRef else_block = merge_block;
5365 if (!exec_list_is_empty(&if_stmt->else_list))
5366 else_block = LLVMAppendBasicBlockInContext(
5367 ctx->ac.context, fn, "");
5368
5369 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5370 ctx->ac.i32_0, "");
5371 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5372
5373 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5374 visit_cf_list(ctx, &if_stmt->then_list);
5375 if (LLVMGetInsertBlock(ctx->ac.builder))
5376 LLVMBuildBr(ctx->ac.builder, merge_block);
5377
5378 if (!exec_list_is_empty(&if_stmt->else_list)) {
5379 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5380 visit_cf_list(ctx, &if_stmt->else_list);
5381 if (LLVMGetInsertBlock(ctx->ac.builder))
5382 LLVMBuildBr(ctx->ac.builder, merge_block);
5383 }
5384
5385 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5386 }
5387
5388 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5389 {
5390 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5391 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5392 LLVMBasicBlockRef break_parent = ctx->break_block;
5393
5394 ctx->continue_block =
5395 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5396 ctx->break_block =
5397 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5398
5399 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5400 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5401 visit_cf_list(ctx, &loop->body);
5402
5403 if (LLVMGetInsertBlock(ctx->ac.builder))
5404 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5405 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5406
5407 ctx->continue_block = continue_parent;
5408 ctx->break_block = break_parent;
5409 }
5410
5411 static void visit_cf_list(struct ac_nir_context *ctx,
5412 struct exec_list *list)
5413 {
5414 foreach_list_typed(nir_cf_node, node, node, list)
5415 {
5416 switch (node->type) {
5417 case nir_cf_node_block:
5418 visit_block(ctx, nir_cf_node_as_block(node));
5419 break;
5420
5421 case nir_cf_node_if:
5422 visit_if(ctx, nir_cf_node_as_if(node));
5423 break;
5424
5425 case nir_cf_node_loop:
5426 visit_loop(ctx, nir_cf_node_as_loop(node));
5427 break;
5428
5429 default:
5430 assert(0);
5431 }
5432 }
5433 }
5434
5435 static void
5436 handle_vs_input_decl(struct radv_shader_context *ctx,
5437 struct nir_variable *variable)
5438 {
5439 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5440 LLVMValueRef t_offset;
5441 LLVMValueRef t_list;
5442 LLVMValueRef input;
5443 LLVMValueRef buffer_index;
5444 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5445 int idx = variable->data.location;
5446 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5447 uint8_t input_usage_mask =
5448 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5449 unsigned num_channels = util_last_bit(input_usage_mask);
5450
5451 variable->data.driver_location = idx * 4;
5452
5453 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5454 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5455 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5456 ctx->abi.start_instance, "");
5457 if (ctx->options->key.vs.as_ls) {
5458 ctx->shader_info->vs.vgpr_comp_cnt =
5459 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5460 } else {
5461 ctx->shader_info->vs.vgpr_comp_cnt =
5462 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5463 }
5464 } else
5465 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5466 ctx->abi.base_vertex, "");
5467 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5468
5469 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5470
5471 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5472 buffer_index,
5473 ctx->ac.i32_0,
5474 num_channels, false, true);
5475
5476 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5477
5478 for (unsigned chan = 0; chan < 4; chan++) {
5479 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5480 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5481 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5482 input, llvm_chan, ""));
5483 }
5484 }
5485 }
5486
5487 static void interp_fs_input(struct radv_shader_context *ctx,
5488 unsigned attr,
5489 LLVMValueRef interp_param,
5490 LLVMValueRef prim_mask,
5491 LLVMValueRef result[4])
5492 {
5493 LLVMValueRef attr_number;
5494 unsigned chan;
5495 LLVMValueRef i, j;
5496 bool interp = interp_param != NULL;
5497
5498 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5499
5500 /* fs.constant returns the param from the middle vertex, so it's not
5501 * really useful for flat shading. It's meant to be used for custom
5502 * interpolation (but the intrinsic can't fetch from the other two
5503 * vertices).
5504 *
5505 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5506 * to do the right thing. The only reason we use fs.constant is that
5507 * fs.interp cannot be used on integers, because they can be equal
5508 * to NaN.
5509 */
5510 if (interp) {
5511 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5512 ctx->ac.v2f32, "");
5513
5514 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5515 ctx->ac.i32_0, "");
5516 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5517 ctx->ac.i32_1, "");
5518 }
5519
5520 for (chan = 0; chan < 4; chan++) {
5521 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5522
5523 if (interp) {
5524 result[chan] = ac_build_fs_interp(&ctx->ac,
5525 llvm_chan,
5526 attr_number,
5527 prim_mask, i, j);
5528 } else {
5529 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5530 LLVMConstInt(ctx->ac.i32, 2, false),
5531 llvm_chan,
5532 attr_number,
5533 prim_mask);
5534 }
5535 }
5536 }
5537
5538 static void
5539 handle_fs_input_decl(struct radv_shader_context *ctx,
5540 struct nir_variable *variable)
5541 {
5542 int idx = variable->data.location;
5543 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5544 LLVMValueRef interp;
5545
5546 variable->data.driver_location = idx * 4;
5547 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5548
5549 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5550 unsigned interp_type;
5551 if (variable->data.sample)
5552 interp_type = INTERP_SAMPLE;
5553 else if (variable->data.centroid)
5554 interp_type = INTERP_CENTROID;
5555 else
5556 interp_type = INTERP_CENTER;
5557
5558 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5559 } else
5560 interp = NULL;
5561
5562 for (unsigned i = 0; i < attrib_count; ++i)
5563 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5564
5565 }
5566
5567 static void
5568 handle_vs_inputs(struct radv_shader_context *ctx,
5569 struct nir_shader *nir) {
5570 nir_foreach_variable(variable, &nir->inputs)
5571 handle_vs_input_decl(ctx, variable);
5572 }
5573
5574 static void
5575 prepare_interp_optimize(struct radv_shader_context *ctx,
5576 struct nir_shader *nir)
5577 {
5578 if (!ctx->options->key.fs.multisample)
5579 return;
5580
5581 bool uses_center = false;
5582 bool uses_centroid = false;
5583 nir_foreach_variable(variable, &nir->inputs) {
5584 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5585 variable->data.sample)
5586 continue;
5587
5588 if (variable->data.centroid)
5589 uses_centroid = true;
5590 else
5591 uses_center = true;
5592 }
5593
5594 if (uses_center && uses_centroid) {
5595 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5596 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5597 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5598 }
5599 }
5600
5601 static void
5602 handle_fs_inputs(struct radv_shader_context *ctx,
5603 struct nir_shader *nir)
5604 {
5605 prepare_interp_optimize(ctx, nir);
5606
5607 nir_foreach_variable(variable, &nir->inputs)
5608 handle_fs_input_decl(ctx, variable);
5609
5610 unsigned index = 0;
5611
5612 if (ctx->shader_info->info.ps.uses_input_attachments ||
5613 ctx->shader_info->info.needs_multiview_view_index)
5614 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5615
5616 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5617 LLVMValueRef interp_param;
5618 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5619
5620 if (!(ctx->input_mask & (1ull << i)))
5621 continue;
5622
5623 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5624 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5625 interp_param = *inputs;
5626 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5627 inputs);
5628
5629 if (!interp_param)
5630 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5631 ++index;
5632 } else if (i == VARYING_SLOT_POS) {
5633 for(int i = 0; i < 3; ++i)
5634 inputs[i] = ctx->abi.frag_pos[i];
5635
5636 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5637 ctx->abi.frag_pos[3]);
5638 }
5639 }
5640 ctx->shader_info->fs.num_interp = index;
5641 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5642
5643 if (ctx->shader_info->info.needs_multiview_view_index)
5644 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5645 }
5646
5647 static LLVMValueRef
5648 ac_build_alloca(struct ac_llvm_context *ac,
5649 LLVMTypeRef type,
5650 const char *name)
5651 {
5652 LLVMBuilderRef builder = ac->builder;
5653 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5654 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5655 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5656 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5657 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5658 LLVMValueRef res;
5659
5660 if (first_instr) {
5661 LLVMPositionBuilderBefore(first_builder, first_instr);
5662 } else {
5663 LLVMPositionBuilderAtEnd(first_builder, first_block);
5664 }
5665
5666 res = LLVMBuildAlloca(first_builder, type, name);
5667 LLVMBuildStore(builder, LLVMConstNull(type), res);
5668
5669 LLVMDisposeBuilder(first_builder);
5670
5671 return res;
5672 }
5673
5674 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5675 LLVMTypeRef type,
5676 const char *name)
5677 {
5678 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5679 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5680 return ptr;
5681 }
5682
5683 static void
5684 scan_shader_output_decl(struct radv_shader_context *ctx,
5685 struct nir_variable *variable,
5686 struct nir_shader *shader,
5687 gl_shader_stage stage)
5688 {
5689 int idx = variable->data.location + variable->data.index;
5690 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5691 uint64_t mask_attribs;
5692
5693 variable->data.driver_location = idx * 4;
5694
5695 /* tess ctrl has it's own load/store paths for outputs */
5696 if (stage == MESA_SHADER_TESS_CTRL)
5697 return;
5698
5699 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5700 if (stage == MESA_SHADER_VERTEX ||
5701 stage == MESA_SHADER_TESS_EVAL ||
5702 stage == MESA_SHADER_GEOMETRY) {
5703 if (idx == VARYING_SLOT_CLIP_DIST0) {
5704 int length = shader->info.clip_distance_array_size +
5705 shader->info.cull_distance_array_size;
5706 if (stage == MESA_SHADER_VERTEX) {
5707 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5708 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5709 }
5710 if (stage == MESA_SHADER_TESS_EVAL) {
5711 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5712 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5713 }
5714
5715 if (length > 4)
5716 attrib_count = 2;
5717 else
5718 attrib_count = 1;
5719 mask_attribs = 1ull << idx;
5720 }
5721 }
5722
5723 ctx->output_mask |= mask_attribs;
5724 }
5725
5726 static void
5727 handle_shader_output_decl(struct ac_nir_context *ctx,
5728 struct nir_shader *nir,
5729 struct nir_variable *variable)
5730 {
5731 unsigned output_loc = variable->data.driver_location / 4;
5732 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5733
5734 /* tess ctrl has it's own load/store paths for outputs */
5735 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5736 return;
5737
5738 if (ctx->stage == MESA_SHADER_VERTEX ||
5739 ctx->stage == MESA_SHADER_TESS_EVAL ||
5740 ctx->stage == MESA_SHADER_GEOMETRY) {
5741 int idx = variable->data.location + variable->data.index;
5742 if (idx == VARYING_SLOT_CLIP_DIST0) {
5743 int length = nir->info.clip_distance_array_size +
5744 nir->info.cull_distance_array_size;
5745
5746 if (length > 4)
5747 attrib_count = 2;
5748 else
5749 attrib_count = 1;
5750 }
5751 }
5752
5753 for (unsigned i = 0; i < attrib_count; ++i) {
5754 for (unsigned chan = 0; chan < 4; chan++) {
5755 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5756 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5757 }
5758 }
5759 }
5760
5761 static LLVMTypeRef
5762 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5763 enum glsl_base_type type)
5764 {
5765 switch (type) {
5766 case GLSL_TYPE_INT:
5767 case GLSL_TYPE_UINT:
5768 case GLSL_TYPE_BOOL:
5769 case GLSL_TYPE_SUBROUTINE:
5770 return ac->i32;
5771 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5772 return ac->f32;
5773 case GLSL_TYPE_INT64:
5774 case GLSL_TYPE_UINT64:
5775 return ac->i64;
5776 case GLSL_TYPE_DOUBLE:
5777 return ac->f64;
5778 default:
5779 unreachable("unknown GLSL type");
5780 }
5781 }
5782
5783 static LLVMTypeRef
5784 glsl_to_llvm_type(struct ac_llvm_context *ac,
5785 const struct glsl_type *type)
5786 {
5787 if (glsl_type_is_scalar(type)) {
5788 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5789 }
5790
5791 if (glsl_type_is_vector(type)) {
5792 return LLVMVectorType(
5793 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5794 glsl_get_vector_elements(type));
5795 }
5796
5797 if (glsl_type_is_matrix(type)) {
5798 return LLVMArrayType(
5799 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5800 glsl_get_matrix_columns(type));
5801 }
5802
5803 if (glsl_type_is_array(type)) {
5804 return LLVMArrayType(
5805 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5806 glsl_get_length(type));
5807 }
5808
5809 assert(glsl_type_is_struct(type));
5810
5811 LLVMTypeRef member_types[glsl_get_length(type)];
5812
5813 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5814 member_types[i] =
5815 glsl_to_llvm_type(ac,
5816 glsl_get_struct_field(type, i));
5817 }
5818
5819 return LLVMStructTypeInContext(ac->context, member_types,
5820 glsl_get_length(type), false);
5821 }
5822
5823 static void
5824 setup_locals(struct ac_nir_context *ctx,
5825 struct nir_function *func)
5826 {
5827 int i, j;
5828 ctx->num_locals = 0;
5829 nir_foreach_variable(variable, &func->impl->locals) {
5830 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5831 variable->data.driver_location = ctx->num_locals * 4;
5832 variable->data.location_frac = 0;
5833 ctx->num_locals += attrib_count;
5834 }
5835 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5836 if (!ctx->locals)
5837 return;
5838
5839 for (i = 0; i < ctx->num_locals; i++) {
5840 for (j = 0; j < 4; j++) {
5841 ctx->locals[i * 4 + j] =
5842 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5843 }
5844 }
5845 }
5846
5847 static void
5848 setup_shared(struct ac_nir_context *ctx,
5849 struct nir_shader *nir)
5850 {
5851 nir_foreach_variable(variable, &nir->shared) {
5852 LLVMValueRef shared =
5853 LLVMAddGlobalInAddressSpace(
5854 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5855 variable->name ? variable->name : "",
5856 AC_LOCAL_ADDR_SPACE);
5857 _mesa_hash_table_insert(ctx->vars, variable, shared);
5858 }
5859 }
5860
5861 /* Initialize arguments for the shader export intrinsic */
5862 static void
5863 si_llvm_init_export_args(struct radv_shader_context *ctx,
5864 LLVMValueRef *values,
5865 unsigned target,
5866 struct ac_export_args *args)
5867 {
5868 /* Default is 0xf. Adjusted below depending on the format. */
5869 args->enabled_channels = 0xf;
5870
5871 /* Specify whether the EXEC mask represents the valid mask */
5872 args->valid_mask = 0;
5873
5874 /* Specify whether this is the last export */
5875 args->done = 0;
5876
5877 /* Specify the target we are exporting */
5878 args->target = target;
5879
5880 args->compr = false;
5881 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5882 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5883 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5884 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5885
5886 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5887 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5888 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5889 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5890 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5891 unsigned chan;
5892
5893 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5894 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5895 unsigned bits, bool hi) = NULL;
5896
5897 switch(col_format) {
5898 case V_028714_SPI_SHADER_ZERO:
5899 args->enabled_channels = 0; /* writemask */
5900 args->target = V_008DFC_SQ_EXP_NULL;
5901 break;
5902
5903 case V_028714_SPI_SHADER_32_R:
5904 args->enabled_channels = 1;
5905 args->out[0] = values[0];
5906 break;
5907
5908 case V_028714_SPI_SHADER_32_GR:
5909 args->enabled_channels = 0x3;
5910 args->out[0] = values[0];
5911 args->out[1] = values[1];
5912 break;
5913
5914 case V_028714_SPI_SHADER_32_AR:
5915 args->enabled_channels = 0x9;
5916 args->out[0] = values[0];
5917 args->out[3] = values[3];
5918 break;
5919
5920 case V_028714_SPI_SHADER_FP16_ABGR:
5921 packf = ac_build_cvt_pkrtz_f16;
5922 break;
5923
5924 case V_028714_SPI_SHADER_UNORM16_ABGR:
5925 packf = ac_build_cvt_pknorm_u16;
5926 break;
5927
5928 case V_028714_SPI_SHADER_SNORM16_ABGR:
5929 packf = ac_build_cvt_pknorm_i16;
5930 break;
5931
5932 case V_028714_SPI_SHADER_UINT16_ABGR:
5933 packi = ac_build_cvt_pk_u16;
5934 break;
5935
5936 case V_028714_SPI_SHADER_SINT16_ABGR:
5937 packi = ac_build_cvt_pk_i16;
5938 break;
5939
5940 default:
5941 case V_028714_SPI_SHADER_32_ABGR:
5942 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5943 break;
5944 }
5945
5946 /* Pack f16 or norm_i16/u16. */
5947 if (packf) {
5948 for (chan = 0; chan < 2; chan++) {
5949 LLVMValueRef pack_args[2] = {
5950 values[2 * chan],
5951 values[2 * chan + 1]
5952 };
5953 LLVMValueRef packed;
5954
5955 packed = packf(&ctx->ac, pack_args);
5956 args->out[chan] = ac_to_float(&ctx->ac, packed);
5957 }
5958 args->compr = 1; /* COMPR flag */
5959 }
5960
5961 /* Pack i16/u16. */
5962 if (packi) {
5963 for (chan = 0; chan < 2; chan++) {
5964 LLVMValueRef pack_args[2] = {
5965 ac_to_integer(&ctx->ac, values[2 * chan]),
5966 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5967 };
5968 LLVMValueRef packed;
5969
5970 packed = packi(&ctx->ac, pack_args,
5971 is_int8 ? 8 : is_int10 ? 10 : 16,
5972 chan == 1);
5973 args->out[chan] = ac_to_float(&ctx->ac, packed);
5974 }
5975 args->compr = 1; /* COMPR flag */
5976 }
5977 return;
5978 }
5979
5980 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5981
5982 for (unsigned i = 0; i < 4; ++i)
5983 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5984 }
5985
5986 static void
5987 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5988 LLVMValueRef *values)
5989 {
5990 struct ac_export_args args;
5991
5992 si_llvm_init_export_args(ctx, values,
5993 V_008DFC_SQ_EXP_PARAM + index, &args);
5994 ac_build_export(&ctx->ac, &args);
5995 }
5996
5997 static LLVMValueRef
5998 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5999 {
6000 LLVMValueRef output =
6001 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
6002
6003 return LLVMBuildLoad(ctx->ac.builder, output, "");
6004 }
6005
6006 static void
6007 handle_vs_outputs_post(struct radv_shader_context *ctx,
6008 bool export_prim_id,
6009 struct ac_vs_output_info *outinfo)
6010 {
6011 uint32_t param_count = 0;
6012 unsigned target;
6013 unsigned pos_idx, num_pos_exports = 0;
6014 struct ac_export_args args, pos_args[4] = {};
6015 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
6016 int i;
6017
6018 if (ctx->options->key.has_multiview_view_index) {
6019 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
6020 if(!*tmp_out) {
6021 for(unsigned i = 0; i < 4; ++i)
6022 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
6023 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
6024 }
6025
6026 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
6027 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
6028 }
6029
6030 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6031 sizeof(outinfo->vs_output_param_offset));
6032
6033 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
6034 LLVMValueRef slots[8];
6035 unsigned j;
6036
6037 if (outinfo->cull_dist_mask)
6038 outinfo->cull_dist_mask <<= ctx->num_output_clips;
6039
6040 i = VARYING_SLOT_CLIP_DIST0;
6041 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
6042 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6043
6044 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
6045 slots[i] = LLVMGetUndef(ctx->ac.f32);
6046
6047 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
6048 target = V_008DFC_SQ_EXP_POS + 3;
6049 si_llvm_init_export_args(ctx, &slots[4], target, &args);
6050 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6051 &args, sizeof(args));
6052 }
6053
6054 target = V_008DFC_SQ_EXP_POS + 2;
6055 si_llvm_init_export_args(ctx, &slots[0], target, &args);
6056 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6057 &args, sizeof(args));
6058
6059 }
6060
6061 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6062 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6063 for (unsigned j = 0; j < 4; j++)
6064 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6065 }
6066 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6067
6068 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6069 outinfo->writes_pointsize = true;
6070 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6071 }
6072
6073 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6074 outinfo->writes_layer = true;
6075 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6076 }
6077
6078 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6079 outinfo->writes_viewport_index = true;
6080 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6081 }
6082
6083 if (outinfo->writes_pointsize ||
6084 outinfo->writes_layer ||
6085 outinfo->writes_viewport_index) {
6086 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6087 (outinfo->writes_layer == true ? 4 : 0));
6088 pos_args[1].valid_mask = 0;
6089 pos_args[1].done = 0;
6090 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6091 pos_args[1].compr = 0;
6092 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6093 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6094 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6095 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6096
6097 if (outinfo->writes_pointsize == true)
6098 pos_args[1].out[0] = psize_value;
6099 if (outinfo->writes_layer == true)
6100 pos_args[1].out[2] = layer_value;
6101 if (outinfo->writes_viewport_index == true) {
6102 if (ctx->options->chip_class >= GFX9) {
6103 /* GFX9 has the layer in out.z[10:0] and the viewport
6104 * index in out.z[19:16].
6105 */
6106 LLVMValueRef v = viewport_index_value;
6107 v = ac_to_integer(&ctx->ac, v);
6108 v = LLVMBuildShl(ctx->ac.builder, v,
6109 LLVMConstInt(ctx->ac.i32, 16, false),
6110 "");
6111 v = LLVMBuildOr(ctx->ac.builder, v,
6112 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6113
6114 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6115 pos_args[1].enabled_channels |= 1 << 2;
6116 } else {
6117 pos_args[1].out[3] = viewport_index_value;
6118 pos_args[1].enabled_channels |= 1 << 3;
6119 }
6120 }
6121 }
6122 for (i = 0; i < 4; i++) {
6123 if (pos_args[i].out[0])
6124 num_pos_exports++;
6125 }
6126
6127 pos_idx = 0;
6128 for (i = 0; i < 4; i++) {
6129 if (!pos_args[i].out[0])
6130 continue;
6131
6132 /* Specify the target we are exporting */
6133 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6134 if (pos_idx == num_pos_exports)
6135 pos_args[i].done = 1;
6136 ac_build_export(&ctx->ac, &pos_args[i]);
6137 }
6138
6139 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6140 LLVMValueRef values[4];
6141 if (!(ctx->output_mask & (1ull << i)))
6142 continue;
6143
6144 if (i != VARYING_SLOT_LAYER &&
6145 i != VARYING_SLOT_PRIMITIVE_ID &&
6146 i < VARYING_SLOT_VAR0)
6147 continue;
6148
6149 for (unsigned j = 0; j < 4; j++)
6150 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6151
6152 radv_export_param(ctx, param_count, values);
6153
6154 outinfo->vs_output_param_offset[i] = param_count++;
6155 }
6156
6157 if (export_prim_id) {
6158 LLVMValueRef values[4];
6159
6160 values[0] = ctx->vs_prim_id;
6161 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6162 ctx->shader_info->vs.vgpr_comp_cnt);
6163 for (unsigned j = 1; j < 4; j++)
6164 values[j] = ctx->ac.f32_0;
6165
6166 radv_export_param(ctx, param_count, values);
6167
6168 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6169 outinfo->export_prim_id = true;
6170 }
6171
6172 outinfo->pos_exports = num_pos_exports;
6173 outinfo->param_exports = param_count;
6174 }
6175
6176 static void
6177 handle_es_outputs_post(struct radv_shader_context *ctx,
6178 struct ac_es_output_info *outinfo)
6179 {
6180 int j;
6181 uint64_t max_output_written = 0;
6182 LLVMValueRef lds_base = NULL;
6183
6184 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6185 int param_index;
6186 int length = 4;
6187
6188 if (!(ctx->output_mask & (1ull << i)))
6189 continue;
6190
6191 if (i == VARYING_SLOT_CLIP_DIST0)
6192 length = ctx->num_output_clips + ctx->num_output_culls;
6193
6194 param_index = shader_io_get_unique_index(i);
6195
6196 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6197 }
6198
6199 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6200
6201 if (ctx->ac.chip_class >= GFX9) {
6202 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6203 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6204 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6205 LLVMConstInt(ctx->ac.i32, 24, false),
6206 LLVMConstInt(ctx->ac.i32, 4, false), false);
6207 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6208 LLVMBuildMul(ctx->ac.builder, wave_idx,
6209 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6210 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6211 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6212 }
6213
6214 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6215 LLVMValueRef dw_addr = NULL;
6216 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6217 int param_index;
6218 int length = 4;
6219
6220 if (!(ctx->output_mask & (1ull << i)))
6221 continue;
6222
6223 if (i == VARYING_SLOT_CLIP_DIST0)
6224 length = ctx->num_output_clips + ctx->num_output_culls;
6225
6226 param_index = shader_io_get_unique_index(i);
6227
6228 if (lds_base) {
6229 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6230 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6231 "");
6232 }
6233 for (j = 0; j < length; j++) {
6234 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6235 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6236
6237 if (ctx->ac.chip_class >= GFX9) {
6238 ac_lds_store(&ctx->ac, dw_addr,
6239 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6240 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6241 } else {
6242 ac_build_buffer_store_dword(&ctx->ac,
6243 ctx->esgs_ring,
6244 out_val, 1,
6245 NULL, ctx->es2gs_offset,
6246 (4 * param_index + j) * 4,
6247 1, 1, true, true);
6248 }
6249 }
6250 }
6251 }
6252
6253 static void
6254 handle_ls_outputs_post(struct radv_shader_context *ctx)
6255 {
6256 LLVMValueRef vertex_id = ctx->rel_auto_id;
6257 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6258 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6259 vertex_dw_stride, "");
6260
6261 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6262 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6263 int length = 4;
6264
6265 if (!(ctx->output_mask & (1ull << i)))
6266 continue;
6267
6268 if (i == VARYING_SLOT_CLIP_DIST0)
6269 length = ctx->num_output_clips + ctx->num_output_culls;
6270 int param = shader_io_get_unique_index(i);
6271 mark_tess_output(ctx, false, param);
6272 if (length > 4)
6273 mark_tess_output(ctx, false, param + 1);
6274 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6275 LLVMConstInt(ctx->ac.i32, param * 4, false),
6276 "");
6277 for (unsigned j = 0; j < length; j++) {
6278 ac_lds_store(&ctx->ac, dw_addr,
6279 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6280 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6281 }
6282 }
6283 }
6284
6285 struct ac_build_if_state
6286 {
6287 struct radv_shader_context *ctx;
6288 LLVMValueRef condition;
6289 LLVMBasicBlockRef entry_block;
6290 LLVMBasicBlockRef true_block;
6291 LLVMBasicBlockRef false_block;
6292 LLVMBasicBlockRef merge_block;
6293 };
6294
6295 static LLVMBasicBlockRef
6296 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6297 {
6298 LLVMBasicBlockRef current_block;
6299 LLVMBasicBlockRef next_block;
6300 LLVMBasicBlockRef new_block;
6301
6302 /* get current basic block */
6303 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6304
6305 /* chqeck if there's another block after this one */
6306 next_block = LLVMGetNextBasicBlock(current_block);
6307 if (next_block) {
6308 /* insert the new block before the next block */
6309 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6310 }
6311 else {
6312 /* append new block after current block */
6313 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6314 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6315 }
6316 return new_block;
6317 }
6318
6319 static void
6320 ac_nir_build_if(struct ac_build_if_state *ifthen,
6321 struct radv_shader_context *ctx,
6322 LLVMValueRef condition)
6323 {
6324 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6325
6326 memset(ifthen, 0, sizeof *ifthen);
6327 ifthen->ctx = ctx;
6328 ifthen->condition = condition;
6329 ifthen->entry_block = block;
6330
6331 /* create endif/merge basic block for the phi functions */
6332 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6333
6334 /* create/insert true_block before merge_block */
6335 ifthen->true_block =
6336 LLVMInsertBasicBlockInContext(ctx->context,
6337 ifthen->merge_block,
6338 "if-true-block");
6339
6340 /* successive code goes into the true block */
6341 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6342 }
6343
6344 /**
6345 * End a conditional.
6346 */
6347 static void
6348 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6349 {
6350 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6351
6352 /* Insert branch to the merge block from current block */
6353 LLVMBuildBr(builder, ifthen->merge_block);
6354
6355 /*
6356 * Now patch in the various branch instructions.
6357 */
6358
6359 /* Insert the conditional branch instruction at the end of entry_block */
6360 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6361 if (ifthen->false_block) {
6362 /* we have an else clause */
6363 LLVMBuildCondBr(builder, ifthen->condition,
6364 ifthen->true_block, ifthen->false_block);
6365 }
6366 else {
6367 /* no else clause */
6368 LLVMBuildCondBr(builder, ifthen->condition,
6369 ifthen->true_block, ifthen->merge_block);
6370 }
6371
6372 /* Resume building code at end of the ifthen->merge_block */
6373 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6374 }
6375
6376 static void
6377 write_tess_factors(struct radv_shader_context *ctx)
6378 {
6379 unsigned stride, outer_comps, inner_comps;
6380 struct ac_build_if_state if_ctx, inner_if_ctx;
6381 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6382 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6383 unsigned tess_inner_index = 0, tess_outer_index;
6384 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
6385 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6386 int i;
6387 emit_barrier(&ctx->ac, ctx->stage);
6388
6389 switch (ctx->options->key.tcs.primitive_mode) {
6390 case GL_ISOLINES:
6391 stride = 2;
6392 outer_comps = 2;
6393 inner_comps = 0;
6394 break;
6395 case GL_TRIANGLES:
6396 stride = 4;
6397 outer_comps = 3;
6398 inner_comps = 1;
6399 break;
6400 case GL_QUADS:
6401 stride = 6;
6402 outer_comps = 4;
6403 inner_comps = 2;
6404 break;
6405 default:
6406 return;
6407 }
6408
6409 ac_nir_build_if(&if_ctx, ctx,
6410 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6411 invocation_id, ctx->ac.i32_0, ""));
6412
6413 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6414
6415 if (inner_comps) {
6416 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6417 mark_tess_output(ctx, true, tess_inner_index);
6418 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6419 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6420 }
6421
6422 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6423 mark_tess_output(ctx, true, tess_outer_index);
6424 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6425 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6426
6427 for (i = 0; i < 4; i++) {
6428 inner[i] = LLVMGetUndef(ctx->ac.i32);
6429 outer[i] = LLVMGetUndef(ctx->ac.i32);
6430 }
6431
6432 // LINES reverseal
6433 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6434 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6435 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6436 ctx->ac.i32_1, "");
6437 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6438 } else {
6439 for (i = 0; i < outer_comps; i++) {
6440 outer[i] = out[i] =
6441 ac_lds_load(&ctx->ac, lds_outer);
6442 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6443 ctx->ac.i32_1, "");
6444 }
6445 for (i = 0; i < inner_comps; i++) {
6446 inner[i] = out[outer_comps+i] =
6447 ac_lds_load(&ctx->ac, lds_inner);
6448 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6449 ctx->ac.i32_1, "");
6450 }
6451 }
6452
6453 /* Convert the outputs to vectors for stores. */
6454 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6455 vec1 = NULL;
6456
6457 if (stride > 4)
6458 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6459
6460
6461 buffer = ctx->hs_ring_tess_factor;
6462 tf_base = ctx->tess_factor_offset;
6463 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6464 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6465 unsigned tf_offset = 0;
6466
6467 if (ctx->options->chip_class <= VI) {
6468 ac_nir_build_if(&inner_if_ctx, ctx,
6469 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6470 rel_patch_id, ctx->ac.i32_0, ""));
6471
6472 /* Store the dynamic HS control word. */
6473 ac_build_buffer_store_dword(&ctx->ac, buffer,
6474 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6475 1, ctx->ac.i32_0, tf_base,
6476 0, 1, 0, true, false);
6477 tf_offset += 4;
6478
6479 ac_nir_build_endif(&inner_if_ctx);
6480 }
6481
6482 /* Store the tessellation factors. */
6483 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6484 MIN2(stride, 4), byteoffset, tf_base,
6485 tf_offset, 1, 0, true, false);
6486 if (vec1)
6487 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6488 stride - 4, byteoffset, tf_base,
6489 16 + tf_offset, 1, 0, true, false);
6490
6491 //store to offchip for TES to read - only if TES reads them
6492 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6493 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6494 LLVMValueRef tf_inner_offset;
6495 unsigned param_outer, param_inner;
6496
6497 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6498 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6499 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6500
6501 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6502 util_next_power_of_two(outer_comps));
6503
6504 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6505 outer_comps, tf_outer_offset,
6506 ctx->oc_lds, 0, 1, 0, true, false);
6507 if (inner_comps) {
6508 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6509 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6510 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6511
6512 inner_vec = inner_comps == 1 ? inner[0] :
6513 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6514 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6515 inner_comps, tf_inner_offset,
6516 ctx->oc_lds, 0, 1, 0, true, false);
6517 }
6518 }
6519 ac_nir_build_endif(&if_ctx);
6520 }
6521
6522 static void
6523 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6524 {
6525 write_tess_factors(ctx);
6526 }
6527
6528 static bool
6529 si_export_mrt_color(struct radv_shader_context *ctx,
6530 LLVMValueRef *color, unsigned index, bool is_last,
6531 struct ac_export_args *args)
6532 {
6533 /* Export */
6534 si_llvm_init_export_args(ctx, color,
6535 V_008DFC_SQ_EXP_MRT + index, args);
6536
6537 if (is_last) {
6538 args->valid_mask = 1; /* whether the EXEC mask is valid */
6539 args->done = 1; /* DONE bit */
6540 } else if (!args->enabled_channels)
6541 return false; /* unnecessary NULL export */
6542
6543 return true;
6544 }
6545
6546 static void
6547 radv_export_mrt_z(struct radv_shader_context *ctx,
6548 LLVMValueRef depth, LLVMValueRef stencil,
6549 LLVMValueRef samplemask)
6550 {
6551 struct ac_export_args args;
6552
6553 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6554
6555 ac_build_export(&ctx->ac, &args);
6556 }
6557
6558 static void
6559 handle_fs_outputs_post(struct radv_shader_context *ctx)
6560 {
6561 unsigned index = 0;
6562 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6563 struct ac_export_args color_args[8];
6564
6565 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6566 LLVMValueRef values[4];
6567 bool last = false;
6568
6569 if (!(ctx->output_mask & (1ull << i)))
6570 continue;
6571
6572 if (i < FRAG_RESULT_DATA0)
6573 continue;
6574
6575 for (unsigned j = 0; j < 4; j++)
6576 values[j] = ac_to_float(&ctx->ac,
6577 radv_load_output(ctx, i, j));
6578
6579 if (!ctx->shader_info->info.ps.writes_z &&
6580 !ctx->shader_info->info.ps.writes_stencil &&
6581 !ctx->shader_info->info.ps.writes_sample_mask)
6582 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6583
6584 bool ret = si_export_mrt_color(ctx, values,
6585 i - FRAG_RESULT_DATA0,
6586 last, &color_args[index]);
6587 if (ret)
6588 index++;
6589 }
6590
6591 /* Process depth, stencil, samplemask. */
6592 if (ctx->shader_info->info.ps.writes_z) {
6593 depth = ac_to_float(&ctx->ac,
6594 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6595 }
6596 if (ctx->shader_info->info.ps.writes_stencil) {
6597 stencil = ac_to_float(&ctx->ac,
6598 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6599 }
6600 if (ctx->shader_info->info.ps.writes_sample_mask) {
6601 samplemask = ac_to_float(&ctx->ac,
6602 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6603 }
6604
6605 /* Export PS outputs. */
6606 for (unsigned i = 0; i < index; i++)
6607 ac_build_export(&ctx->ac, &color_args[i]);
6608
6609 if (depth || stencil || samplemask)
6610 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6611 else if (!index)
6612 ac_build_export_null(&ctx->ac);
6613 }
6614
6615 static void
6616 emit_gs_epilogue(struct radv_shader_context *ctx)
6617 {
6618 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6619 }
6620
6621 static void
6622 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6623 LLVMValueRef *addrs)
6624 {
6625 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6626
6627 switch (ctx->stage) {
6628 case MESA_SHADER_VERTEX:
6629 if (ctx->options->key.vs.as_ls)
6630 handle_ls_outputs_post(ctx);
6631 else if (ctx->options->key.vs.as_es)
6632 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6633 else
6634 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6635 &ctx->shader_info->vs.outinfo);
6636 break;
6637 case MESA_SHADER_FRAGMENT:
6638 handle_fs_outputs_post(ctx);
6639 break;
6640 case MESA_SHADER_GEOMETRY:
6641 emit_gs_epilogue(ctx);
6642 break;
6643 case MESA_SHADER_TESS_CTRL:
6644 handle_tcs_outputs_post(ctx);
6645 break;
6646 case MESA_SHADER_TESS_EVAL:
6647 if (ctx->options->key.tes.as_es)
6648 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6649 else
6650 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6651 &ctx->shader_info->tes.outinfo);
6652 break;
6653 default:
6654 break;
6655 }
6656 }
6657
6658 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6659 {
6660 LLVMPassManagerRef passmgr;
6661 /* Create the pass manager */
6662 passmgr = LLVMCreateFunctionPassManagerForModule(
6663 ctx->ac.module);
6664
6665 /* This pass should eliminate all the load and store instructions */
6666 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6667
6668 /* Add some optimization passes */
6669 LLVMAddScalarReplAggregatesPass(passmgr);
6670 LLVMAddLICMPass(passmgr);
6671 LLVMAddAggressiveDCEPass(passmgr);
6672 LLVMAddCFGSimplificationPass(passmgr);
6673 LLVMAddInstructionCombiningPass(passmgr);
6674
6675 /* Run the pass */
6676 LLVMInitializeFunctionPassManager(passmgr);
6677 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6678 LLVMFinalizeFunctionPassManager(passmgr);
6679
6680 LLVMDisposeBuilder(ctx->ac.builder);
6681 LLVMDisposePassManager(passmgr);
6682 }
6683
6684 static void
6685 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6686 {
6687 struct ac_vs_output_info *outinfo;
6688
6689 switch (ctx->stage) {
6690 case MESA_SHADER_FRAGMENT:
6691 case MESA_SHADER_COMPUTE:
6692 case MESA_SHADER_TESS_CTRL:
6693 case MESA_SHADER_GEOMETRY:
6694 return;
6695 case MESA_SHADER_VERTEX:
6696 if (ctx->options->key.vs.as_ls ||
6697 ctx->options->key.vs.as_es)
6698 return;
6699 outinfo = &ctx->shader_info->vs.outinfo;
6700 break;
6701 case MESA_SHADER_TESS_EVAL:
6702 if (ctx->options->key.vs.as_es)
6703 return;
6704 outinfo = &ctx->shader_info->tes.outinfo;
6705 break;
6706 default:
6707 unreachable("Unhandled shader type");
6708 }
6709
6710 ac_optimize_vs_outputs(&ctx->ac,
6711 ctx->main_function,
6712 outinfo->vs_output_param_offset,
6713 VARYING_SLOT_MAX,
6714 &outinfo->param_exports);
6715 }
6716
6717 static void
6718 ac_setup_rings(struct radv_shader_context *ctx)
6719 {
6720 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6721 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6722 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6723 }
6724
6725 if (ctx->is_gs_copy_shader) {
6726 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6727 }
6728 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6729 LLVMValueRef tmp;
6730 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6731 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6732
6733 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6734
6735 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6736 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6737 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6738 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6739 }
6740
6741 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6742 ctx->stage == MESA_SHADER_TESS_EVAL) {
6743 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6744 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6745 }
6746 }
6747
6748 static unsigned
6749 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6750 const struct nir_shader *nir)
6751 {
6752 switch (nir->info.stage) {
6753 case MESA_SHADER_TESS_CTRL:
6754 return chip_class >= CIK ? 128 : 64;
6755 case MESA_SHADER_GEOMETRY:
6756 return chip_class >= GFX9 ? 128 : 64;
6757 case MESA_SHADER_COMPUTE:
6758 break;
6759 default:
6760 return 0;
6761 }
6762
6763 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6764 nir->info.cs.local_size[1] *
6765 nir->info.cs.local_size[2];
6766 return max_workgroup_size;
6767 }
6768
6769 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6770 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6771 {
6772 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6773 LLVMConstInt(ctx->ac.i32, 8, false),
6774 LLVMConstInt(ctx->ac.i32, 8, false), false);
6775 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6776 ctx->ac.i32_0, "");
6777 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6778 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6779 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6780 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6781 }
6782
6783 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6784 {
6785 for(int i = 5; i >= 0; --i) {
6786 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6787 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6788 LLVMConstInt(ctx->ac.i32, 16, false), false);
6789 }
6790
6791 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6792 LLVMConstInt(ctx->ac.i32, 16, false),
6793 LLVMConstInt(ctx->ac.i32, 8, false), false);
6794 }
6795
6796 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6797 struct nir_shader *nir)
6798 {
6799 struct ac_nir_context ctx = {};
6800 struct nir_function *func;
6801
6802 ctx.ac = *ac;
6803 ctx.abi = abi;
6804
6805 ctx.stage = nir->info.stage;
6806
6807 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6808
6809 nir_foreach_variable(variable, &nir->outputs)
6810 handle_shader_output_decl(&ctx, nir, variable);
6811
6812 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6813 _mesa_key_pointer_equal);
6814 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6815 _mesa_key_pointer_equal);
6816 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6817 _mesa_key_pointer_equal);
6818
6819 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6820
6821 setup_locals(&ctx, func);
6822
6823 if (nir->info.stage == MESA_SHADER_COMPUTE)
6824 setup_shared(&ctx, nir);
6825
6826 visit_cf_list(&ctx, &func->impl->body);
6827 phi_post_pass(&ctx);
6828
6829 if (nir->info.stage != MESA_SHADER_COMPUTE)
6830 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6831 ctx.abi->outputs);
6832
6833 free(ctx.locals);
6834 ralloc_free(ctx.defs);
6835 ralloc_free(ctx.phis);
6836 ralloc_free(ctx.vars);
6837 }
6838
6839 static
6840 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6841 struct nir_shader *const *shaders,
6842 int shader_count,
6843 struct ac_shader_variant_info *shader_info,
6844 const struct ac_nir_compiler_options *options)
6845 {
6846 struct radv_shader_context ctx = {0};
6847 unsigned i;
6848 ctx.options = options;
6849 ctx.shader_info = shader_info;
6850 ctx.context = LLVMContextCreate();
6851
6852 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6853 options->family);
6854 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6855 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6856
6857 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6858 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6859 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6860 LLVMDisposeTargetData(data_layout);
6861 LLVMDisposeMessage(data_layout_str);
6862
6863 enum ac_float_mode float_mode =
6864 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6865 AC_FLOAT_MODE_DEFAULT;
6866
6867 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6868
6869 memset(shader_info, 0, sizeof(*shader_info));
6870
6871 for(int i = 0; i < shader_count; ++i)
6872 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6873
6874 for (i = 0; i < AC_UD_MAX_SETS; i++)
6875 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6876 for (i = 0; i < AC_UD_MAX_UD; i++)
6877 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6878
6879 ctx.max_workgroup_size = 0;
6880 for (int i = 0; i < shader_count; ++i) {
6881 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6882 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6883 shaders[i]));
6884 }
6885
6886 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6887 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6888
6889 ctx.abi.inputs = &ctx.inputs[0];
6890 ctx.abi.emit_outputs = handle_shader_outputs_post;
6891 ctx.abi.emit_vertex = visit_emit_vertex;
6892 ctx.abi.load_ubo = radv_load_ubo;
6893 ctx.abi.load_ssbo = radv_load_ssbo;
6894 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6895 ctx.abi.load_resource = radv_load_resource;
6896 ctx.abi.clamp_shadow_reference = false;
6897
6898 if (shader_count >= 2)
6899 ac_init_exec_full_mask(&ctx.ac);
6900
6901 if (ctx.ac.chip_class == GFX9 &&
6902 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6903 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6904
6905 for(int i = 0; i < shader_count; ++i) {
6906 ctx.stage = shaders[i]->info.stage;
6907 ctx.output_mask = 0;
6908 ctx.tess_outputs_written = 0;
6909 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6910 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6911
6912 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6913 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6914 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6915 ctx.abi.load_inputs = load_gs_input;
6916 ctx.abi.emit_primitive = visit_end_primitive;
6917 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6918 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6919 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6920 ctx.abi.load_tess_varyings = load_tcs_varyings;
6921 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6922 ctx.abi.store_tcs_outputs = store_tcs_output;
6923 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6924 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6925 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6926 ctx.abi.load_tess_varyings = load_tes_input;
6927 ctx.abi.load_tess_coord = load_tess_coord;
6928 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6929 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6930 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6931 if (shader_info->info.vs.needs_instance_id) {
6932 if (ctx.options->key.vs.as_ls) {
6933 ctx.shader_info->vs.vgpr_comp_cnt =
6934 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6935 } else {
6936 ctx.shader_info->vs.vgpr_comp_cnt =
6937 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6938 }
6939 }
6940 ctx.abi.load_base_vertex = radv_load_base_vertex;
6941 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6942 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6943 ctx.abi.lookup_interp_param = lookup_interp_param;
6944 ctx.abi.load_sample_position = load_sample_position;
6945 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6946 }
6947
6948 if (i)
6949 emit_barrier(&ctx.ac, ctx.stage);
6950
6951 ac_setup_rings(&ctx);
6952
6953 LLVMBasicBlockRef merge_block;
6954 if (shader_count >= 2) {
6955 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6956 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6957 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6958
6959 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6960 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6961 LLVMConstInt(ctx.ac.i32, 8, false), false);
6962 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6963 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6964 thread_id, count, "");
6965 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6966
6967 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6968 }
6969
6970 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6971 handle_fs_inputs(&ctx, shaders[i]);
6972 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6973 handle_vs_inputs(&ctx, shaders[i]);
6974 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6975 prepare_gs_input_vgprs(&ctx);
6976
6977 nir_foreach_variable(variable, &shaders[i]->outputs)
6978 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6979
6980 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6981
6982 if (shader_count >= 2) {
6983 LLVMBuildBr(ctx.ac.builder, merge_block);
6984 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6985 }
6986
6987 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6988 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6989 shaders[i]->info.cull_distance_array_size > 4;
6990 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6991 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6992 shaders[i]->info.gs.vertices_out;
6993 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6994 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6995 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6996 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6997 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6998 }
6999 }
7000
7001 LLVMBuildRetVoid(ctx.ac.builder);
7002
7003 if (options->dump_preoptir)
7004 ac_dump_module(ctx.ac.module);
7005
7006 ac_llvm_finalize_module(&ctx);
7007
7008 if (shader_count == 1)
7009 ac_nir_eliminate_const_vs_outputs(&ctx);
7010
7011 return ctx.ac.module;
7012 }
7013
7014 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
7015 {
7016 unsigned *retval = (unsigned *)context;
7017 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
7018 char *description = LLVMGetDiagInfoDescription(di);
7019
7020 if (severity == LLVMDSError) {
7021 *retval = 1;
7022 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
7023 description);
7024 }
7025
7026 LLVMDisposeMessage(description);
7027 }
7028
7029 static unsigned ac_llvm_compile(LLVMModuleRef M,
7030 struct ac_shader_binary *binary,
7031 LLVMTargetMachineRef tm)
7032 {
7033 unsigned retval = 0;
7034 char *err;
7035 LLVMContextRef llvm_ctx;
7036 LLVMMemoryBufferRef out_buffer;
7037 unsigned buffer_size;
7038 const char *buffer_data;
7039 LLVMBool mem_err;
7040
7041 /* Setup Diagnostic Handler*/
7042 llvm_ctx = LLVMGetModuleContext(M);
7043
7044 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
7045 &retval);
7046
7047 /* Compile IR*/
7048 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
7049 &err, &out_buffer);
7050
7051 /* Process Errors/Warnings */
7052 if (mem_err) {
7053 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7054 free(err);
7055 retval = 1;
7056 goto out;
7057 }
7058
7059 /* Extract Shader Code*/
7060 buffer_size = LLVMGetBufferSize(out_buffer);
7061 buffer_data = LLVMGetBufferStart(out_buffer);
7062
7063 ac_elf_read(buffer_data, buffer_size, binary);
7064
7065 /* Clean up */
7066 LLVMDisposeMemoryBuffer(out_buffer);
7067
7068 out:
7069 return retval;
7070 }
7071
7072 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7073 LLVMModuleRef llvm_module,
7074 struct ac_shader_binary *binary,
7075 struct ac_shader_config *config,
7076 struct ac_shader_variant_info *shader_info,
7077 gl_shader_stage stage,
7078 bool dump_shader, bool supports_spill)
7079 {
7080 if (dump_shader)
7081 ac_dump_module(llvm_module);
7082
7083 memset(binary, 0, sizeof(*binary));
7084 int v = ac_llvm_compile(llvm_module, binary, tm);
7085 if (v) {
7086 fprintf(stderr, "compile failed\n");
7087 }
7088
7089 if (dump_shader)
7090 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7091
7092 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7093
7094 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7095 LLVMDisposeModule(llvm_module);
7096 LLVMContextDispose(ctx);
7097
7098 if (stage == MESA_SHADER_FRAGMENT) {
7099 shader_info->num_input_vgprs = 0;
7100 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7101 shader_info->num_input_vgprs += 2;
7102 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7103 shader_info->num_input_vgprs += 2;
7104 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7105 shader_info->num_input_vgprs += 2;
7106 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7107 shader_info->num_input_vgprs += 3;
7108 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7109 shader_info->num_input_vgprs += 2;
7110 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7111 shader_info->num_input_vgprs += 2;
7112 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7113 shader_info->num_input_vgprs += 2;
7114 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7115 shader_info->num_input_vgprs += 1;
7116 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7117 shader_info->num_input_vgprs += 1;
7118 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7119 shader_info->num_input_vgprs += 1;
7120 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7121 shader_info->num_input_vgprs += 1;
7122 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7123 shader_info->num_input_vgprs += 1;
7124 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7125 shader_info->num_input_vgprs += 1;
7126 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7127 shader_info->num_input_vgprs += 1;
7128 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7129 shader_info->num_input_vgprs += 1;
7130 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7131 shader_info->num_input_vgprs += 1;
7132 }
7133 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7134
7135 /* +3 for scratch wave offset and VCC */
7136 config->num_sgprs = MAX2(config->num_sgprs,
7137 shader_info->num_input_sgprs + 3);
7138
7139 /* Enable 64-bit and 16-bit denormals, because there is no performance
7140 * cost.
7141 *
7142 * If denormals are enabled, all floating-point output modifiers are
7143 * ignored.
7144 *
7145 * Don't enable denormals for 32-bit floats, because:
7146 * - Floating-point output modifiers would be ignored by the hw.
7147 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7148 * have to stop using those.
7149 * - SI & CI would be very slow.
7150 */
7151 config->float_mode |= V_00B028_FP_64_DENORMS;
7152 }
7153
7154 static void
7155 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7156 {
7157 switch (nir->info.stage) {
7158 case MESA_SHADER_COMPUTE:
7159 for (int i = 0; i < 3; ++i)
7160 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7161 break;
7162 case MESA_SHADER_FRAGMENT:
7163 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7164 break;
7165 case MESA_SHADER_GEOMETRY:
7166 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7167 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7168 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7169 shader_info->gs.invocations = nir->info.gs.invocations;
7170 break;
7171 case MESA_SHADER_TESS_EVAL:
7172 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7173 shader_info->tes.spacing = nir->info.tess.spacing;
7174 shader_info->tes.ccw = nir->info.tess.ccw;
7175 shader_info->tes.point_mode = nir->info.tess.point_mode;
7176 shader_info->tes.as_es = options->key.tes.as_es;
7177 break;
7178 case MESA_SHADER_TESS_CTRL:
7179 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7180 break;
7181 case MESA_SHADER_VERTEX:
7182 shader_info->vs.as_es = options->key.vs.as_es;
7183 shader_info->vs.as_ls = options->key.vs.as_ls;
7184 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7185 if (options->key.vs.as_ls)
7186 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7187 break;
7188 default:
7189 break;
7190 }
7191 }
7192
7193 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7194 struct ac_shader_binary *binary,
7195 struct ac_shader_config *config,
7196 struct ac_shader_variant_info *shader_info,
7197 struct nir_shader *const *nir,
7198 int nir_count,
7199 const struct ac_nir_compiler_options *options,
7200 bool dump_shader)
7201 {
7202
7203 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7204 options);
7205
7206 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7207 for (int i = 0; i < nir_count; ++i)
7208 ac_fill_shader_info(shader_info, nir[i], options);
7209
7210 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7211 if (options->chip_class == GFX9) {
7212 if (nir_count == 2 &&
7213 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7214 shader_info->gs.es_type = nir[0]->info.stage;
7215 }
7216 }
7217 }
7218
7219 static void
7220 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7221 {
7222 LLVMValueRef vtx_offset =
7223 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7224 LLVMConstInt(ctx->ac.i32, 4, false), "");
7225 int idx = 0;
7226
7227 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7228 int length = 4;
7229 int slot = idx;
7230 int slot_inc = 1;
7231 if (!(ctx->output_mask & (1ull << i)))
7232 continue;
7233
7234 if (i == VARYING_SLOT_CLIP_DIST0) {
7235 /* unpack clip and cull from a single set of slots */
7236 length = ctx->num_output_clips + ctx->num_output_culls;
7237 if (length > 4)
7238 slot_inc = 2;
7239 }
7240
7241 for (unsigned j = 0; j < length; j++) {
7242 LLVMValueRef value, soffset;
7243
7244 soffset = LLVMConstInt(ctx->ac.i32,
7245 (slot * 4 + j) *
7246 ctx->gs_max_out_vertices * 16 * 4, false);
7247
7248 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7249 1, ctx->ac.i32_0,
7250 vtx_offset, soffset,
7251 0, 1, 1, true, false);
7252
7253 LLVMBuildStore(ctx->ac.builder,
7254 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7255 }
7256 idx += slot_inc;
7257 }
7258 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7259 }
7260
7261 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7262 struct nir_shader *geom_shader,
7263 struct ac_shader_binary *binary,
7264 struct ac_shader_config *config,
7265 struct ac_shader_variant_info *shader_info,
7266 const struct ac_nir_compiler_options *options,
7267 bool dump_shader)
7268 {
7269 struct radv_shader_context ctx = {0};
7270 ctx.context = LLVMContextCreate();
7271 ctx.options = options;
7272 ctx.shader_info = shader_info;
7273
7274 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7275 options->family);
7276 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7277
7278 ctx.is_gs_copy_shader = true;
7279 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7280
7281 enum ac_float_mode float_mode =
7282 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7283 AC_FLOAT_MODE_DEFAULT;
7284
7285 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7286 ctx.stage = MESA_SHADER_VERTEX;
7287
7288 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7289
7290 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7291 ac_setup_rings(&ctx);
7292
7293 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7294 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7295
7296 struct ac_nir_context nir_ctx = {};
7297 nir_ctx.ac = ctx.ac;
7298 nir_ctx.abi = &ctx.abi;
7299
7300 nir_foreach_variable(variable, &geom_shader->outputs) {
7301 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7302 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7303 }
7304
7305 ac_gs_copy_shader_emit(&ctx);
7306
7307 LLVMBuildRetVoid(ctx.ac.builder);
7308
7309 ac_llvm_finalize_module(&ctx);
7310
7311 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7312 MESA_SHADER_VERTEX,
7313 dump_shader, options->supports_spill);
7314 }