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ac/nir: move radeon_llvm_reg_index_soa() to ac_nir_to_llvm.h
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 uint32_t tcs_vertices_per_patch;
131 };
132
133 static inline struct radv_shader_context *
134 radv_shader_context_from_abi(struct ac_shader_abi *abi)
135 {
136 struct radv_shader_context *ctx = NULL;
137 return container_of(abi, ctx, abi);
138 }
139
140 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
141 const nir_deref_var *deref,
142 enum ac_descriptor_type desc_type,
143 const nir_tex_instr *instr,
144 bool image, bool write);
145
146 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
147 {
148 /* handle patch indices separate */
149 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
150 return 0;
151 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
152 return 1;
153 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
154 return 2 + (slot - VARYING_SLOT_PATCH0);
155
156 if (slot == VARYING_SLOT_POS)
157 return 0;
158 if (slot == VARYING_SLOT_PSIZ)
159 return 1;
160 if (slot == VARYING_SLOT_CLIP_DIST0)
161 return 2;
162 /* 3 is reserved for clip dist as well */
163 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
164 return 4 + (slot - VARYING_SLOT_VAR0);
165 unreachable("illegal slot in get unique index\n");
166 }
167
168 static void set_llvm_calling_convention(LLVMValueRef func,
169 gl_shader_stage stage)
170 {
171 enum radeon_llvm_calling_convention calling_conv;
172
173 switch (stage) {
174 case MESA_SHADER_VERTEX:
175 case MESA_SHADER_TESS_EVAL:
176 calling_conv = RADEON_LLVM_AMDGPU_VS;
177 break;
178 case MESA_SHADER_GEOMETRY:
179 calling_conv = RADEON_LLVM_AMDGPU_GS;
180 break;
181 case MESA_SHADER_TESS_CTRL:
182 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
183 break;
184 case MESA_SHADER_FRAGMENT:
185 calling_conv = RADEON_LLVM_AMDGPU_PS;
186 break;
187 case MESA_SHADER_COMPUTE:
188 calling_conv = RADEON_LLVM_AMDGPU_CS;
189 break;
190 default:
191 unreachable("Unhandle shader type");
192 }
193
194 LLVMSetFunctionCallConv(func, calling_conv);
195 }
196
197 #define MAX_ARGS 23
198 struct arg_info {
199 LLVMTypeRef types[MAX_ARGS];
200 LLVMValueRef *assign[MAX_ARGS];
201 unsigned array_params_mask;
202 uint8_t count;
203 uint8_t sgpr_count;
204 uint8_t num_sgprs_used;
205 uint8_t num_vgprs_used;
206 };
207
208 enum ac_arg_regfile {
209 ARG_SGPR,
210 ARG_VGPR,
211 };
212
213 static void
214 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
215 LLVMValueRef *param_ptr)
216 {
217 assert(info->count < MAX_ARGS);
218
219 info->assign[info->count] = param_ptr;
220 info->types[info->count] = type;
221 info->count++;
222
223 if (regfile == ARG_SGPR) {
224 info->num_sgprs_used += ac_get_type_size(type) / 4;
225 info->sgpr_count++;
226 } else {
227 assert(regfile == ARG_VGPR);
228 info->num_vgprs_used += ac_get_type_size(type) / 4;
229 }
230 }
231
232 static inline void
233 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
234 {
235 info->array_params_mask |= (1 << info->count);
236 add_arg(info, ARG_SGPR, type, param_ptr);
237 }
238
239 static void assign_arguments(LLVMValueRef main_function,
240 struct arg_info *info)
241 {
242 unsigned i;
243 for (i = 0; i < info->count; i++) {
244 if (info->assign[i])
245 *info->assign[i] = LLVMGetParam(main_function, i);
246 }
247 }
248
249 static LLVMValueRef
250 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
251 LLVMBuilderRef builder, LLVMTypeRef *return_types,
252 unsigned num_return_elems,
253 struct arg_info *args,
254 unsigned max_workgroup_size,
255 bool unsafe_math)
256 {
257 LLVMTypeRef main_function_type, ret_type;
258 LLVMBasicBlockRef main_function_body;
259
260 if (num_return_elems)
261 ret_type = LLVMStructTypeInContext(ctx, return_types,
262 num_return_elems, true);
263 else
264 ret_type = LLVMVoidTypeInContext(ctx);
265
266 /* Setup the function */
267 main_function_type =
268 LLVMFunctionType(ret_type, args->types, args->count, 0);
269 LLVMValueRef main_function =
270 LLVMAddFunction(module, "main", main_function_type);
271 main_function_body =
272 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
273 LLVMPositionBuilderAtEnd(builder, main_function_body);
274
275 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
276 for (unsigned i = 0; i < args->sgpr_count; ++i) {
277 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
278
279 if (args->array_params_mask & (1 << i)) {
280 LLVMValueRef P = LLVMGetParam(main_function, i);
281 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
282 ac_add_attr_dereferenceable(P, UINT64_MAX);
283 }
284 }
285
286 if (max_workgroup_size) {
287 ac_llvm_add_target_dep_function_attr(main_function,
288 "amdgpu-max-work-group-size",
289 max_workgroup_size);
290 }
291 if (unsafe_math) {
292 /* These were copied from some LLVM test. */
293 LLVMAddTargetDependentFunctionAttr(main_function,
294 "less-precise-fpmad",
295 "true");
296 LLVMAddTargetDependentFunctionAttr(main_function,
297 "no-infs-fp-math",
298 "true");
299 LLVMAddTargetDependentFunctionAttr(main_function,
300 "no-nans-fp-math",
301 "true");
302 LLVMAddTargetDependentFunctionAttr(main_function,
303 "unsafe-fp-math",
304 "true");
305 LLVMAddTargetDependentFunctionAttr(main_function,
306 "no-signed-zeros-fp-math",
307 "true");
308 }
309 return main_function;
310 }
311
312 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
313 {
314 switch (ctx->stage) {
315 case MESA_SHADER_TESS_CTRL:
316 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
317 case MESA_SHADER_TESS_EVAL:
318 return ctx->tes_rel_patch_id;
319 break;
320 default:
321 unreachable("Illegal stage");
322 }
323 }
324
325 /* Tessellation shaders pass outputs to the next shader using LDS.
326 *
327 * LS outputs = TCS inputs
328 * TCS outputs = TES inputs
329 *
330 * The LDS layout is:
331 * - TCS inputs for patch 0
332 * - TCS inputs for patch 1
333 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
334 * - ...
335 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
336 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
337 * - TCS outputs for patch 1
338 * - Per-patch TCS outputs for patch 1
339 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
340 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
341 * - ...
342 *
343 * All three shaders VS(LS), TCS, TES share the same LDS space.
344 */
345 static LLVMValueRef
346 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
347 {
348 if (ctx->stage == MESA_SHADER_VERTEX)
349 return ac_unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
350 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
351 return ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
352 else {
353 assert(0);
354 return NULL;
355 }
356 }
357
358 static LLVMValueRef
359 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
360 {
361 return ac_unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
362 }
363
364 static LLVMValueRef
365 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
366 {
367 return ac_unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
368 }
369
370 static LLVMValueRef
371 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
372 {
373 return LLVMBuildMul(ctx->ac.builder,
374 ac_unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
375 LLVMConstInt(ctx->ac.i32, 4, false), "");
376 }
377
378 static LLVMValueRef
379 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
380 {
381 return LLVMBuildMul(ctx->ac.builder,
382 ac_unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
383 LLVMConstInt(ctx->ac.i32, 4, false), "");
384 }
385
386 static LLVMValueRef
387 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
388 {
389 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
390 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
391
392 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
393 }
394
395 static LLVMValueRef
396 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
397 {
398 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
399 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
400 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
401
402 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
403 LLVMBuildMul(ctx->ac.builder, patch_stride,
404 rel_patch_id, ""),
405 "");
406 }
407
408 static LLVMValueRef
409 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
410 {
411 LLVMValueRef patch0_patch_data_offset =
412 get_tcs_out_patch0_patch_data_offset(ctx);
413 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
414 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
415
416 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
417 LLVMBuildMul(ctx->ac.builder, patch_stride,
418 rel_patch_id, ""),
419 "");
420 }
421
422 static void
423 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
424 uint32_t indirect_offset)
425 {
426 ud_info->sgpr_idx = *sgpr_idx;
427 ud_info->num_sgprs = num_sgprs;
428 ud_info->indirect = indirect_offset > 0;
429 ud_info->indirect_offset = indirect_offset;
430 *sgpr_idx += num_sgprs;
431 }
432
433 static void
434 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
435 uint8_t num_sgprs)
436 {
437 struct ac_userdata_info *ud_info =
438 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
439 assert(ud_info);
440
441 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
442 }
443
444 static void
445 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
446 uint32_t indirect_offset)
447 {
448 struct ac_userdata_info *ud_info =
449 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
450 assert(ud_info);
451
452 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
453 }
454
455 struct user_sgpr_info {
456 bool need_ring_offsets;
457 uint8_t sgpr_count;
458 bool indirect_all_descriptor_sets;
459 };
460
461 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
462 gl_shader_stage stage)
463 {
464 switch (stage) {
465 case MESA_SHADER_VERTEX:
466 if (ctx->shader_info->info.needs_multiview_view_index ||
467 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
468 return true;
469 break;
470 case MESA_SHADER_TESS_EVAL:
471 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
472 return true;
473 break;
474 case MESA_SHADER_GEOMETRY:
475 case MESA_SHADER_TESS_CTRL:
476 if (ctx->shader_info->info.needs_multiview_view_index)
477 return true;
478 break;
479 default:
480 break;
481 }
482 return false;
483 }
484
485 static uint8_t
486 count_vs_user_sgprs(struct radv_shader_context *ctx)
487 {
488 uint8_t count = 0;
489
490 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
491 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
492
493 return count;
494 }
495
496 static void allocate_user_sgprs(struct radv_shader_context *ctx,
497 gl_shader_stage stage,
498 bool has_previous_stage,
499 gl_shader_stage previous_stage,
500 bool needs_view_index,
501 struct user_sgpr_info *user_sgpr_info)
502 {
503 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
504
505 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
506 if (stage == MESA_SHADER_GEOMETRY ||
507 stage == MESA_SHADER_VERTEX ||
508 stage == MESA_SHADER_TESS_CTRL ||
509 stage == MESA_SHADER_TESS_EVAL ||
510 ctx->is_gs_copy_shader)
511 user_sgpr_info->need_ring_offsets = true;
512
513 if (stage == MESA_SHADER_FRAGMENT &&
514 ctx->shader_info->info.ps.needs_sample_positions)
515 user_sgpr_info->need_ring_offsets = true;
516
517 /* 2 user sgprs will nearly always be allocated for scratch/rings */
518 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
519 user_sgpr_info->sgpr_count += 2;
520 }
521
522 switch (stage) {
523 case MESA_SHADER_COMPUTE:
524 if (ctx->shader_info->info.cs.uses_grid_size)
525 user_sgpr_info->sgpr_count += 3;
526 break;
527 case MESA_SHADER_FRAGMENT:
528 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
529 break;
530 case MESA_SHADER_VERTEX:
531 if (!ctx->is_gs_copy_shader)
532 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
533 if (ctx->options->key.vs.as_ls)
534 user_sgpr_info->sgpr_count++;
535 break;
536 case MESA_SHADER_TESS_CTRL:
537 if (has_previous_stage) {
538 if (previous_stage == MESA_SHADER_VERTEX)
539 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
540 user_sgpr_info->sgpr_count++;
541 }
542 user_sgpr_info->sgpr_count += 4;
543 break;
544 case MESA_SHADER_TESS_EVAL:
545 user_sgpr_info->sgpr_count += 1;
546 break;
547 case MESA_SHADER_GEOMETRY:
548 if (has_previous_stage) {
549 if (previous_stage == MESA_SHADER_VERTEX) {
550 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
551 } else {
552 user_sgpr_info->sgpr_count++;
553 }
554 }
555 user_sgpr_info->sgpr_count += 2;
556 break;
557 default:
558 break;
559 }
560
561 if (needs_view_index)
562 user_sgpr_info->sgpr_count++;
563
564 if (ctx->shader_info->info.loads_push_constants)
565 user_sgpr_info->sgpr_count += 2;
566
567 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
568 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
569
570 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
571 user_sgpr_info->sgpr_count += 2;
572 user_sgpr_info->indirect_all_descriptor_sets = true;
573 } else {
574 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
575 }
576 }
577
578 static void
579 declare_global_input_sgprs(struct radv_shader_context *ctx,
580 gl_shader_stage stage,
581 bool has_previous_stage,
582 gl_shader_stage previous_stage,
583 const struct user_sgpr_info *user_sgpr_info,
584 struct arg_info *args,
585 LLVMValueRef *desc_sets)
586 {
587 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
588 unsigned num_sets = ctx->options->layout ?
589 ctx->options->layout->num_sets : 0;
590 unsigned stage_mask = 1 << stage;
591
592 if (has_previous_stage)
593 stage_mask |= 1 << previous_stage;
594
595 /* 1 for each descriptor set */
596 if (!user_sgpr_info->indirect_all_descriptor_sets) {
597 for (unsigned i = 0; i < num_sets; ++i) {
598 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
599 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
600 add_array_arg(args, type,
601 &ctx->descriptor_sets[i]);
602 }
603 }
604 } else {
605 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
606 }
607
608 if (ctx->shader_info->info.loads_push_constants) {
609 /* 1 for push constants and dynamic descriptors */
610 add_array_arg(args, type, &ctx->abi.push_constants);
611 }
612 }
613
614 static void
615 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
616 gl_shader_stage stage,
617 bool has_previous_stage,
618 gl_shader_stage previous_stage,
619 struct arg_info *args)
620 {
621 if (!ctx->is_gs_copy_shader &&
622 (stage == MESA_SHADER_VERTEX ||
623 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
624 if (ctx->shader_info->info.vs.has_vertex_buffers) {
625 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
626 &ctx->vertex_buffers);
627 }
628 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
629 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
630 if (ctx->shader_info->info.vs.needs_draw_id) {
631 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
632 }
633 }
634 }
635
636 static void
637 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
638 {
639 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
640 if (!ctx->is_gs_copy_shader) {
641 if (ctx->options->key.vs.as_ls) {
642 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
643 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
644 } else {
645 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
646 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
647 }
648 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
649 }
650 }
651
652 static void
653 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
654 {
655 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
656 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
657 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
658 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
659 }
660
661 static void
662 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
663 bool has_previous_stage, gl_shader_stage previous_stage,
664 const struct user_sgpr_info *user_sgpr_info,
665 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
666 {
667 unsigned num_sets = ctx->options->layout ?
668 ctx->options->layout->num_sets : 0;
669 unsigned stage_mask = 1 << stage;
670
671 if (has_previous_stage)
672 stage_mask |= 1 << previous_stage;
673
674 if (!user_sgpr_info->indirect_all_descriptor_sets) {
675 for (unsigned i = 0; i < num_sets; ++i) {
676 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
677 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
678 set_loc_desc(ctx, i, user_sgpr_idx, 0);
679 } else
680 ctx->descriptor_sets[i] = NULL;
681 }
682 } else {
683 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
684 user_sgpr_idx, 2);
685
686 for (unsigned i = 0; i < num_sets; ++i) {
687 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
688 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
689 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
690 ctx->descriptor_sets[i] =
691 ac_build_load_to_sgpr(&ctx->ac,
692 desc_sets,
693 LLVMConstInt(ctx->ac.i32, i, false));
694
695 } else
696 ctx->descriptor_sets[i] = NULL;
697 }
698 ctx->shader_info->need_indirect_descriptor_sets = true;
699 }
700
701 if (ctx->shader_info->info.loads_push_constants) {
702 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
703 }
704 }
705
706 static void
707 set_vs_specific_input_locs(struct radv_shader_context *ctx,
708 gl_shader_stage stage, bool has_previous_stage,
709 gl_shader_stage previous_stage,
710 uint8_t *user_sgpr_idx)
711 {
712 if (!ctx->is_gs_copy_shader &&
713 (stage == MESA_SHADER_VERTEX ||
714 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
715 if (ctx->shader_info->info.vs.has_vertex_buffers) {
716 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
717 user_sgpr_idx, 2);
718 }
719
720 unsigned vs_num = 2;
721 if (ctx->shader_info->info.vs.needs_draw_id)
722 vs_num++;
723
724 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
725 user_sgpr_idx, vs_num);
726 }
727 }
728
729 static void create_function(struct radv_shader_context *ctx,
730 gl_shader_stage stage,
731 bool has_previous_stage,
732 gl_shader_stage previous_stage)
733 {
734 uint8_t user_sgpr_idx;
735 struct user_sgpr_info user_sgpr_info;
736 struct arg_info args = {};
737 LLVMValueRef desc_sets;
738 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
739 allocate_user_sgprs(ctx, stage, has_previous_stage,
740 previous_stage, needs_view_index, &user_sgpr_info);
741
742 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
743 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
744 &ctx->ring_offsets);
745 }
746
747 switch (stage) {
748 case MESA_SHADER_COMPUTE:
749 declare_global_input_sgprs(ctx, stage, has_previous_stage,
750 previous_stage, &user_sgpr_info,
751 &args, &desc_sets);
752
753 if (ctx->shader_info->info.cs.uses_grid_size) {
754 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
755 &ctx->abi.num_work_groups);
756 }
757
758 for (int i = 0; i < 3; i++) {
759 ctx->abi.workgroup_ids[i] = NULL;
760 if (ctx->shader_info->info.cs.uses_block_id[i]) {
761 add_arg(&args, ARG_SGPR, ctx->ac.i32,
762 &ctx->abi.workgroup_ids[i]);
763 }
764 }
765
766 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
767 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
768 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
769 &ctx->abi.local_invocation_ids);
770 break;
771 case MESA_SHADER_VERTEX:
772 declare_global_input_sgprs(ctx, stage, has_previous_stage,
773 previous_stage, &user_sgpr_info,
774 &args, &desc_sets);
775 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
776 previous_stage, &args);
777
778 if (needs_view_index)
779 add_arg(&args, ARG_SGPR, ctx->ac.i32,
780 &ctx->abi.view_index);
781 if (ctx->options->key.vs.as_es)
782 add_arg(&args, ARG_SGPR, ctx->ac.i32,
783 &ctx->es2gs_offset);
784 else if (ctx->options->key.vs.as_ls)
785 add_arg(&args, ARG_SGPR, ctx->ac.i32,
786 &ctx->ls_out_layout);
787
788 declare_vs_input_vgprs(ctx, &args);
789 break;
790 case MESA_SHADER_TESS_CTRL:
791 if (has_previous_stage) {
792 // First 6 system regs
793 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
794 add_arg(&args, ARG_SGPR, ctx->ac.i32,
795 &ctx->merged_wave_info);
796 add_arg(&args, ARG_SGPR, ctx->ac.i32,
797 &ctx->tess_factor_offset);
798
799 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
800 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
801 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
802
803 declare_global_input_sgprs(ctx, stage,
804 has_previous_stage,
805 previous_stage,
806 &user_sgpr_info, &args,
807 &desc_sets);
808 declare_vs_specific_input_sgprs(ctx, stage,
809 has_previous_stage,
810 previous_stage, &args);
811
812 add_arg(&args, ARG_SGPR, ctx->ac.i32,
813 &ctx->ls_out_layout);
814
815 add_arg(&args, ARG_SGPR, ctx->ac.i32,
816 &ctx->tcs_offchip_layout);
817 add_arg(&args, ARG_SGPR, ctx->ac.i32,
818 &ctx->tcs_out_offsets);
819 add_arg(&args, ARG_SGPR, ctx->ac.i32,
820 &ctx->tcs_out_layout);
821 add_arg(&args, ARG_SGPR, ctx->ac.i32,
822 &ctx->tcs_in_layout);
823 if (needs_view_index)
824 add_arg(&args, ARG_SGPR, ctx->ac.i32,
825 &ctx->abi.view_index);
826
827 add_arg(&args, ARG_VGPR, ctx->ac.i32,
828 &ctx->abi.tcs_patch_id);
829 add_arg(&args, ARG_VGPR, ctx->ac.i32,
830 &ctx->abi.tcs_rel_ids);
831
832 declare_vs_input_vgprs(ctx, &args);
833 } else {
834 declare_global_input_sgprs(ctx, stage,
835 has_previous_stage,
836 previous_stage,
837 &user_sgpr_info, &args,
838 &desc_sets);
839
840 add_arg(&args, ARG_SGPR, ctx->ac.i32,
841 &ctx->tcs_offchip_layout);
842 add_arg(&args, ARG_SGPR, ctx->ac.i32,
843 &ctx->tcs_out_offsets);
844 add_arg(&args, ARG_SGPR, ctx->ac.i32,
845 &ctx->tcs_out_layout);
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_in_layout);
848 if (needs_view_index)
849 add_arg(&args, ARG_SGPR, ctx->ac.i32,
850 &ctx->abi.view_index);
851
852 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
853 add_arg(&args, ARG_SGPR, ctx->ac.i32,
854 &ctx->tess_factor_offset);
855 add_arg(&args, ARG_VGPR, ctx->ac.i32,
856 &ctx->abi.tcs_patch_id);
857 add_arg(&args, ARG_VGPR, ctx->ac.i32,
858 &ctx->abi.tcs_rel_ids);
859 }
860 break;
861 case MESA_SHADER_TESS_EVAL:
862 declare_global_input_sgprs(ctx, stage, has_previous_stage,
863 previous_stage, &user_sgpr_info,
864 &args, &desc_sets);
865
866 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
867 if (needs_view_index)
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->abi.view_index);
870
871 if (ctx->options->key.tes.as_es) {
872 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
873 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
874 add_arg(&args, ARG_SGPR, ctx->ac.i32,
875 &ctx->es2gs_offset);
876 } else {
877 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
878 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
879 }
880 declare_tes_input_vgprs(ctx, &args);
881 break;
882 case MESA_SHADER_GEOMETRY:
883 if (has_previous_stage) {
884 // First 6 system regs
885 add_arg(&args, ARG_SGPR, ctx->ac.i32,
886 &ctx->gs2vs_offset);
887 add_arg(&args, ARG_SGPR, ctx->ac.i32,
888 &ctx->merged_wave_info);
889 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
890
891 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
892 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
894
895 declare_global_input_sgprs(ctx, stage,
896 has_previous_stage,
897 previous_stage,
898 &user_sgpr_info, &args,
899 &desc_sets);
900
901 if (previous_stage == MESA_SHADER_TESS_EVAL) {
902 add_arg(&args, ARG_SGPR, ctx->ac.i32,
903 &ctx->tcs_offchip_layout);
904 } else {
905 declare_vs_specific_input_sgprs(ctx, stage,
906 has_previous_stage,
907 previous_stage,
908 &args);
909 }
910
911 add_arg(&args, ARG_SGPR, ctx->ac.i32,
912 &ctx->gsvs_ring_stride);
913 add_arg(&args, ARG_SGPR, ctx->ac.i32,
914 &ctx->gsvs_num_entries);
915 if (needs_view_index)
916 add_arg(&args, ARG_SGPR, ctx->ac.i32,
917 &ctx->abi.view_index);
918
919 add_arg(&args, ARG_VGPR, ctx->ac.i32,
920 &ctx->gs_vtx_offset[0]);
921 add_arg(&args, ARG_VGPR, ctx->ac.i32,
922 &ctx->gs_vtx_offset[2]);
923 add_arg(&args, ARG_VGPR, ctx->ac.i32,
924 &ctx->abi.gs_prim_id);
925 add_arg(&args, ARG_VGPR, ctx->ac.i32,
926 &ctx->abi.gs_invocation_id);
927 add_arg(&args, ARG_VGPR, ctx->ac.i32,
928 &ctx->gs_vtx_offset[4]);
929
930 if (previous_stage == MESA_SHADER_VERTEX) {
931 declare_vs_input_vgprs(ctx, &args);
932 } else {
933 declare_tes_input_vgprs(ctx, &args);
934 }
935 } else {
936 declare_global_input_sgprs(ctx, stage,
937 has_previous_stage,
938 previous_stage,
939 &user_sgpr_info, &args,
940 &desc_sets);
941
942 add_arg(&args, ARG_SGPR, ctx->ac.i32,
943 &ctx->gsvs_ring_stride);
944 add_arg(&args, ARG_SGPR, ctx->ac.i32,
945 &ctx->gsvs_num_entries);
946 if (needs_view_index)
947 add_arg(&args, ARG_SGPR, ctx->ac.i32,
948 &ctx->abi.view_index);
949
950 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
951 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
952 add_arg(&args, ARG_VGPR, ctx->ac.i32,
953 &ctx->gs_vtx_offset[0]);
954 add_arg(&args, ARG_VGPR, ctx->ac.i32,
955 &ctx->gs_vtx_offset[1]);
956 add_arg(&args, ARG_VGPR, ctx->ac.i32,
957 &ctx->abi.gs_prim_id);
958 add_arg(&args, ARG_VGPR, ctx->ac.i32,
959 &ctx->gs_vtx_offset[2]);
960 add_arg(&args, ARG_VGPR, ctx->ac.i32,
961 &ctx->gs_vtx_offset[3]);
962 add_arg(&args, ARG_VGPR, ctx->ac.i32,
963 &ctx->gs_vtx_offset[4]);
964 add_arg(&args, ARG_VGPR, ctx->ac.i32,
965 &ctx->gs_vtx_offset[5]);
966 add_arg(&args, ARG_VGPR, ctx->ac.i32,
967 &ctx->abi.gs_invocation_id);
968 }
969 break;
970 case MESA_SHADER_FRAGMENT:
971 declare_global_input_sgprs(ctx, stage, has_previous_stage,
972 previous_stage, &user_sgpr_info,
973 &args, &desc_sets);
974
975 if (ctx->shader_info->info.ps.needs_sample_positions)
976 add_arg(&args, ARG_SGPR, ctx->ac.i32,
977 &ctx->sample_pos_offset);
978
979 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
980 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
981 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
982 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
983 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
984 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
985 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
986 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
987 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
988 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
989 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
990 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
991 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
992 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
993 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
994 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
995 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
996 break;
997 default:
998 unreachable("Shader stage not implemented");
999 }
1000
1001 ctx->main_function = create_llvm_function(
1002 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1003 ctx->max_workgroup_size,
1004 ctx->options->unsafe_math);
1005 set_llvm_calling_convention(ctx->main_function, stage);
1006
1007
1008 ctx->shader_info->num_input_vgprs = 0;
1009 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1010
1011 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1012
1013 if (ctx->stage != MESA_SHADER_FRAGMENT)
1014 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1015
1016 assign_arguments(ctx->main_function, &args);
1017
1018 user_sgpr_idx = 0;
1019
1020 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1021 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1022 &user_sgpr_idx, 2);
1023 if (ctx->options->supports_spill) {
1024 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1025 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1026 NULL, 0, AC_FUNC_ATTR_READNONE);
1027 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1028 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1029 }
1030 }
1031
1032 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1033 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1034 if (has_previous_stage)
1035 user_sgpr_idx = 0;
1036
1037 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1038 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1039
1040 switch (stage) {
1041 case MESA_SHADER_COMPUTE:
1042 if (ctx->shader_info->info.cs.uses_grid_size) {
1043 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1044 &user_sgpr_idx, 3);
1045 }
1046 break;
1047 case MESA_SHADER_VERTEX:
1048 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1049 previous_stage, &user_sgpr_idx);
1050 if (ctx->abi.view_index)
1051 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1052 if (ctx->options->key.vs.as_ls) {
1053 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1054 &user_sgpr_idx, 1);
1055 }
1056 break;
1057 case MESA_SHADER_TESS_CTRL:
1058 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1059 previous_stage, &user_sgpr_idx);
1060 if (has_previous_stage)
1061 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1062 &user_sgpr_idx, 1);
1063 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1064 if (ctx->abi.view_index)
1065 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1066 break;
1067 case MESA_SHADER_TESS_EVAL:
1068 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1069 if (ctx->abi.view_index)
1070 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1071 break;
1072 case MESA_SHADER_GEOMETRY:
1073 if (has_previous_stage) {
1074 if (previous_stage == MESA_SHADER_VERTEX)
1075 set_vs_specific_input_locs(ctx, stage,
1076 has_previous_stage,
1077 previous_stage,
1078 &user_sgpr_idx);
1079 else
1080 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1081 &user_sgpr_idx, 1);
1082 }
1083 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1084 &user_sgpr_idx, 2);
1085 if (ctx->abi.view_index)
1086 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1087 break;
1088 case MESA_SHADER_FRAGMENT:
1089 if (ctx->shader_info->info.ps.needs_sample_positions) {
1090 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1091 &user_sgpr_idx, 1);
1092 }
1093 break;
1094 default:
1095 unreachable("Shader stage not implemented");
1096 }
1097
1098 if (stage == MESA_SHADER_TESS_CTRL ||
1099 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1100 /* GFX9 has the ESGS ring buffer in LDS. */
1101 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1102 ac_declare_lds_as_pointer(&ctx->ac);
1103 }
1104
1105 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1106 }
1107
1108 static void
1109 build_store_values_extended(struct ac_llvm_context *ac,
1110 LLVMValueRef *values,
1111 unsigned value_count,
1112 unsigned value_stride,
1113 LLVMValueRef vec)
1114 {
1115 LLVMBuilderRef builder = ac->builder;
1116 unsigned i;
1117
1118 for (i = 0; i < value_count; i++) {
1119 LLVMValueRef ptr = values[i * value_stride];
1120 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1121 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1122 LLVMBuildStore(builder, value, ptr);
1123 }
1124 }
1125
1126 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1127 const nir_ssa_def *def)
1128 {
1129 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1130 if (def->num_components > 1) {
1131 type = LLVMVectorType(type, def->num_components);
1132 }
1133 return type;
1134 }
1135
1136 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1137 {
1138 assert(src.is_ssa);
1139 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1140 return (LLVMValueRef)entry->data;
1141 }
1142
1143 static LLVMValueRef
1144 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1145 {
1146 LLVMValueRef ptr = get_src(ctx, src);
1147 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1148 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1149
1150 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1151 LLVMPointerType(ctx->ac.i32, addr_space), "");
1152 }
1153
1154 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1155 const struct nir_block *b)
1156 {
1157 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1158 return (LLVMBasicBlockRef)entry->data;
1159 }
1160
1161 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1162 nir_alu_src src,
1163 unsigned num_components)
1164 {
1165 LLVMValueRef value = get_src(ctx, src.src);
1166 bool need_swizzle = false;
1167
1168 assert(value);
1169 unsigned src_components = ac_get_llvm_num_components(value);
1170 for (unsigned i = 0; i < num_components; ++i) {
1171 assert(src.swizzle[i] < src_components);
1172 if (src.swizzle[i] != i)
1173 need_swizzle = true;
1174 }
1175
1176 if (need_swizzle || num_components != src_components) {
1177 LLVMValueRef masks[] = {
1178 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1179 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1180 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1181 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1182
1183 if (src_components > 1 && num_components == 1) {
1184 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1185 masks[0], "");
1186 } else if (src_components == 1 && num_components > 1) {
1187 LLVMValueRef values[] = {value, value, value, value};
1188 value = ac_build_gather_values(&ctx->ac, values, num_components);
1189 } else {
1190 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1191 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1192 swizzle, "");
1193 }
1194 }
1195 assert(!src.negate);
1196 assert(!src.abs);
1197 return value;
1198 }
1199
1200 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1201 LLVMIntPredicate pred, LLVMValueRef src0,
1202 LLVMValueRef src1)
1203 {
1204 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1205 return LLVMBuildSelect(ctx->builder, result,
1206 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1207 ctx->i32_0, "");
1208 }
1209
1210 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1211 LLVMRealPredicate pred, LLVMValueRef src0,
1212 LLVMValueRef src1)
1213 {
1214 LLVMValueRef result;
1215 src0 = ac_to_float(ctx, src0);
1216 src1 = ac_to_float(ctx, src1);
1217 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1218 return LLVMBuildSelect(ctx->builder, result,
1219 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1220 ctx->i32_0, "");
1221 }
1222
1223 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1224 const char *intrin,
1225 LLVMTypeRef result_type,
1226 LLVMValueRef src0)
1227 {
1228 char name[64];
1229 LLVMValueRef params[] = {
1230 ac_to_float(ctx, src0),
1231 };
1232
1233 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1234 ac_get_elem_bits(ctx, result_type));
1235 assert(length < sizeof(name));
1236 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1237 }
1238
1239 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1240 const char *intrin,
1241 LLVMTypeRef result_type,
1242 LLVMValueRef src0, LLVMValueRef src1)
1243 {
1244 char name[64];
1245 LLVMValueRef params[] = {
1246 ac_to_float(ctx, src0),
1247 ac_to_float(ctx, src1),
1248 };
1249
1250 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1251 ac_get_elem_bits(ctx, result_type));
1252 assert(length < sizeof(name));
1253 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1254 }
1255
1256 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1257 const char *intrin,
1258 LLVMTypeRef result_type,
1259 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1260 {
1261 char name[64];
1262 LLVMValueRef params[] = {
1263 ac_to_float(ctx, src0),
1264 ac_to_float(ctx, src1),
1265 ac_to_float(ctx, src2),
1266 };
1267
1268 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1269 ac_get_elem_bits(ctx, result_type));
1270 assert(length < sizeof(name));
1271 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1272 }
1273
1274 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1275 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1276 {
1277 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1278 ctx->i32_0, "");
1279 return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
1280 ac_to_integer(ctx, src2), "");
1281 }
1282
1283 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1284 LLVMIntPredicate pred,
1285 LLVMValueRef src0, LLVMValueRef src1)
1286 {
1287 return LLVMBuildSelect(ctx->builder,
1288 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1289 src0,
1290 src1, "");
1291
1292 }
1293 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1294 LLVMValueRef src0)
1295 {
1296 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1297 LLVMBuildNeg(ctx->builder, src0, ""));
1298 }
1299
1300 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1301 const char *intrin,
1302 LLVMValueRef src0, LLVMValueRef src1)
1303 {
1304 LLVMTypeRef ret_type;
1305 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1306 LLVMValueRef res;
1307 LLVMValueRef params[] = { src0, src1 };
1308 ret_type = LLVMStructTypeInContext(ctx->context, types,
1309 2, true);
1310
1311 res = ac_build_intrinsic(ctx, intrin, ret_type,
1312 params, 2, AC_FUNC_ATTR_READNONE);
1313
1314 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1315 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1316 return res;
1317 }
1318
1319 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1320 LLVMValueRef src0)
1321 {
1322 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1323 }
1324
1325 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1326 LLVMValueRef src0)
1327 {
1328 src0 = ac_to_float(ctx, src0);
1329 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
1330 return LLVMBuildSExt(ctx->builder,
1331 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, zero, ""),
1332 ctx->i32, "");
1333 }
1334
1335 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1336 LLVMValueRef src0,
1337 unsigned bitsize)
1338 {
1339 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1340
1341 if (bitsize == 32)
1342 return result;
1343
1344 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1345 }
1346
1347 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1348 LLVMValueRef src0)
1349 {
1350 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
1351 return LLVMBuildSExt(ctx->builder,
1352 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, zero, ""),
1353 ctx->i32, "");
1354 }
1355
1356 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0)
1358 {
1359 LLVMValueRef result;
1360 LLVMValueRef cond = NULL;
1361
1362 src0 = ac_to_float(ctx, src0);
1363 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1364
1365 if (ctx->chip_class >= VI) {
1366 LLVMValueRef args[2];
1367 /* Check if the result is a denormal - and flush to 0 if so. */
1368 args[0] = result;
1369 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1370 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1371 }
1372
1373 /* need to convert back up to f32 */
1374 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1375
1376 if (ctx->chip_class >= VI)
1377 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1378 else {
1379 /* for SI/CIK */
1380 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1381 * so compare the result and flush to 0 if it's smaller.
1382 */
1383 LLVMValueRef temp, cond2;
1384 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1385 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1386 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1387 temp, "");
1388 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1389 temp, ctx->f32_0, "");
1390 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1391 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1392 }
1393 return result;
1394 }
1395
1396 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1397 LLVMValueRef src0, LLVMValueRef src1)
1398 {
1399 LLVMValueRef dst64, result;
1400 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1401 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1402
1403 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1404 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1405 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1406 return result;
1407 }
1408
1409 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1410 LLVMValueRef src0, LLVMValueRef src1)
1411 {
1412 LLVMValueRef dst64, result;
1413 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1414 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1415
1416 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1417 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1418 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1419 return result;
1420 }
1421
1422 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1423 bool is_signed,
1424 const LLVMValueRef srcs[3])
1425 {
1426 LLVMValueRef result;
1427 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1428
1429 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1430 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1431 return result;
1432 }
1433
1434 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0, LLVMValueRef src1,
1436 LLVMValueRef src2, LLVMValueRef src3)
1437 {
1438 LLVMValueRef bfi_args[3], result;
1439
1440 bfi_args[0] = LLVMBuildShl(ctx->builder,
1441 LLVMBuildSub(ctx->builder,
1442 LLVMBuildShl(ctx->builder,
1443 ctx->i32_1,
1444 src3, ""),
1445 ctx->i32_1, ""),
1446 src2, "");
1447 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1448 bfi_args[2] = src0;
1449
1450 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1451
1452 /* Calculate:
1453 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1454 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1455 */
1456 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1457 LLVMBuildAnd(ctx->builder, bfi_args[0],
1458 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1459
1460 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1461 return result;
1462 }
1463
1464 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1465 LLVMValueRef src0)
1466 {
1467 LLVMValueRef comp[2];
1468
1469 src0 = ac_to_float(ctx, src0);
1470 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1471 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1472
1473 return ac_build_cvt_pkrtz_f16(ctx, comp);
1474 }
1475
1476 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1477 LLVMValueRef src0)
1478 {
1479 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1480 LLVMValueRef temps[2], result, val;
1481 int i;
1482
1483 for (i = 0; i < 2; i++) {
1484 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1485 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1486 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1487 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1488 }
1489
1490 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1491 ctx->i32_0, "");
1492 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1493 ctx->i32_1, "");
1494 return result;
1495 }
1496
1497 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1498 nir_op op,
1499 LLVMValueRef src0)
1500 {
1501 unsigned mask;
1502 int idx;
1503 LLVMValueRef result;
1504
1505 if (op == nir_op_fddx_fine)
1506 mask = AC_TID_MASK_LEFT;
1507 else if (op == nir_op_fddy_fine)
1508 mask = AC_TID_MASK_TOP;
1509 else
1510 mask = AC_TID_MASK_TOP_LEFT;
1511
1512 /* for DDX we want to next X pixel, DDY next Y pixel. */
1513 if (op == nir_op_fddx_fine ||
1514 op == nir_op_fddx_coarse ||
1515 op == nir_op_fddx)
1516 idx = 1;
1517 else
1518 idx = 2;
1519
1520 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1521 return result;
1522 }
1523
1524 /*
1525 * this takes an I,J coordinate pair,
1526 * and works out the X and Y derivatives.
1527 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1528 */
1529 static LLVMValueRef emit_ddxy_interp(
1530 struct ac_nir_context *ctx,
1531 LLVMValueRef interp_ij)
1532 {
1533 LLVMValueRef result[4], a;
1534 unsigned i;
1535
1536 for (i = 0; i < 2; i++) {
1537 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1538 LLVMConstInt(ctx->ac.i32, i, false), "");
1539 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1540 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1541 }
1542 return ac_build_gather_values(&ctx->ac, result, 4);
1543 }
1544
1545 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1546 {
1547 LLVMValueRef src[4], result = NULL;
1548 unsigned num_components = instr->dest.dest.ssa.num_components;
1549 unsigned src_components;
1550 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1551
1552 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1553 switch (instr->op) {
1554 case nir_op_vec2:
1555 case nir_op_vec3:
1556 case nir_op_vec4:
1557 src_components = 1;
1558 break;
1559 case nir_op_pack_half_2x16:
1560 src_components = 2;
1561 break;
1562 case nir_op_unpack_half_2x16:
1563 src_components = 1;
1564 break;
1565 case nir_op_cube_face_coord:
1566 case nir_op_cube_face_index:
1567 src_components = 3;
1568 break;
1569 default:
1570 src_components = num_components;
1571 break;
1572 }
1573 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1574 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1575
1576 switch (instr->op) {
1577 case nir_op_fmov:
1578 case nir_op_imov:
1579 result = src[0];
1580 break;
1581 case nir_op_fneg:
1582 src[0] = ac_to_float(&ctx->ac, src[0]);
1583 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1584 break;
1585 case nir_op_ineg:
1586 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1587 break;
1588 case nir_op_inot:
1589 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1590 break;
1591 case nir_op_iadd:
1592 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1593 break;
1594 case nir_op_fadd:
1595 src[0] = ac_to_float(&ctx->ac, src[0]);
1596 src[1] = ac_to_float(&ctx->ac, src[1]);
1597 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1598 break;
1599 case nir_op_fsub:
1600 src[0] = ac_to_float(&ctx->ac, src[0]);
1601 src[1] = ac_to_float(&ctx->ac, src[1]);
1602 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1603 break;
1604 case nir_op_isub:
1605 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1606 break;
1607 case nir_op_imul:
1608 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1609 break;
1610 case nir_op_imod:
1611 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1612 break;
1613 case nir_op_umod:
1614 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1615 break;
1616 case nir_op_fmod:
1617 src[0] = ac_to_float(&ctx->ac, src[0]);
1618 src[1] = ac_to_float(&ctx->ac, src[1]);
1619 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1620 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1621 ac_to_float_type(&ctx->ac, def_type), result);
1622 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1623 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1624 break;
1625 case nir_op_frem:
1626 src[0] = ac_to_float(&ctx->ac, src[0]);
1627 src[1] = ac_to_float(&ctx->ac, src[1]);
1628 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1629 break;
1630 case nir_op_irem:
1631 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1632 break;
1633 case nir_op_idiv:
1634 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1635 break;
1636 case nir_op_udiv:
1637 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1638 break;
1639 case nir_op_fmul:
1640 src[0] = ac_to_float(&ctx->ac, src[0]);
1641 src[1] = ac_to_float(&ctx->ac, src[1]);
1642 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1643 break;
1644 case nir_op_frcp:
1645 src[0] = ac_to_float(&ctx->ac, src[0]);
1646 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1647 src[0]);
1648 break;
1649 case nir_op_iand:
1650 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1651 break;
1652 case nir_op_ior:
1653 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1654 break;
1655 case nir_op_ixor:
1656 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1657 break;
1658 case nir_op_ishl:
1659 result = LLVMBuildShl(ctx->ac.builder, src[0],
1660 LLVMBuildZExt(ctx->ac.builder, src[1],
1661 LLVMTypeOf(src[0]), ""),
1662 "");
1663 break;
1664 case nir_op_ishr:
1665 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1666 LLVMBuildZExt(ctx->ac.builder, src[1],
1667 LLVMTypeOf(src[0]), ""),
1668 "");
1669 break;
1670 case nir_op_ushr:
1671 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1672 LLVMBuildZExt(ctx->ac.builder, src[1],
1673 LLVMTypeOf(src[0]), ""),
1674 "");
1675 break;
1676 case nir_op_ilt:
1677 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1678 break;
1679 case nir_op_ine:
1680 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1681 break;
1682 case nir_op_ieq:
1683 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1684 break;
1685 case nir_op_ige:
1686 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1687 break;
1688 case nir_op_ult:
1689 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1690 break;
1691 case nir_op_uge:
1692 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1693 break;
1694 case nir_op_feq:
1695 result = emit_float_cmp(&ctx->ac, LLVMRealOEQ, src[0], src[1]);
1696 break;
1697 case nir_op_fne:
1698 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1699 break;
1700 case nir_op_flt:
1701 result = emit_float_cmp(&ctx->ac, LLVMRealOLT, src[0], src[1]);
1702 break;
1703 case nir_op_fge:
1704 result = emit_float_cmp(&ctx->ac, LLVMRealOGE, src[0], src[1]);
1705 break;
1706 case nir_op_fabs:
1707 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1708 ac_to_float_type(&ctx->ac, def_type), src[0]);
1709 break;
1710 case nir_op_iabs:
1711 result = emit_iabs(&ctx->ac, src[0]);
1712 break;
1713 case nir_op_imax:
1714 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1715 break;
1716 case nir_op_imin:
1717 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1718 break;
1719 case nir_op_umax:
1720 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1721 break;
1722 case nir_op_umin:
1723 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1724 break;
1725 case nir_op_isign:
1726 result = ac_build_isign(&ctx->ac, src[0],
1727 instr->dest.dest.ssa.bit_size);
1728 break;
1729 case nir_op_fsign:
1730 src[0] = ac_to_float(&ctx->ac, src[0]);
1731 result = ac_build_fsign(&ctx->ac, src[0],
1732 instr->dest.dest.ssa.bit_size);
1733 break;
1734 case nir_op_ffloor:
1735 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1736 ac_to_float_type(&ctx->ac, def_type), src[0]);
1737 break;
1738 case nir_op_ftrunc:
1739 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1740 ac_to_float_type(&ctx->ac, def_type), src[0]);
1741 break;
1742 case nir_op_fceil:
1743 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1744 ac_to_float_type(&ctx->ac, def_type), src[0]);
1745 break;
1746 case nir_op_fround_even:
1747 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1748 ac_to_float_type(&ctx->ac, def_type),src[0]);
1749 break;
1750 case nir_op_ffract:
1751 src[0] = ac_to_float(&ctx->ac, src[0]);
1752 result = ac_build_fract(&ctx->ac, src[0],
1753 instr->dest.dest.ssa.bit_size);
1754 break;
1755 case nir_op_fsin:
1756 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1757 ac_to_float_type(&ctx->ac, def_type), src[0]);
1758 break;
1759 case nir_op_fcos:
1760 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1761 ac_to_float_type(&ctx->ac, def_type), src[0]);
1762 break;
1763 case nir_op_fsqrt:
1764 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1765 ac_to_float_type(&ctx->ac, def_type), src[0]);
1766 break;
1767 case nir_op_fexp2:
1768 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1769 ac_to_float_type(&ctx->ac, def_type), src[0]);
1770 break;
1771 case nir_op_flog2:
1772 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1773 ac_to_float_type(&ctx->ac, def_type), src[0]);
1774 break;
1775 case nir_op_frsq:
1776 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1777 ac_to_float_type(&ctx->ac, def_type), src[0]);
1778 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1779 result);
1780 break;
1781 case nir_op_fmax:
1782 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1783 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1784 if (ctx->ac.chip_class < GFX9 &&
1785 instr->dest.dest.ssa.bit_size == 32) {
1786 /* Only pre-GFX9 chips do not flush denorms. */
1787 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1788 ac_to_float_type(&ctx->ac, def_type),
1789 result);
1790 }
1791 break;
1792 case nir_op_fmin:
1793 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1794 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1795 if (ctx->ac.chip_class < GFX9 &&
1796 instr->dest.dest.ssa.bit_size == 32) {
1797 /* Only pre-GFX9 chips do not flush denorms. */
1798 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1799 ac_to_float_type(&ctx->ac, def_type),
1800 result);
1801 }
1802 break;
1803 case nir_op_ffma:
1804 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1805 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1806 break;
1807 case nir_op_ldexp:
1808 src[0] = ac_to_float(&ctx->ac, src[0]);
1809 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1810 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f32", ctx->ac.f32, src, 2, AC_FUNC_ATTR_READNONE);
1811 else
1812 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f64", ctx->ac.f64, src, 2, AC_FUNC_ATTR_READNONE);
1813 break;
1814 case nir_op_ibitfield_extract:
1815 result = emit_bitfield_extract(&ctx->ac, true, src);
1816 break;
1817 case nir_op_ubitfield_extract:
1818 result = emit_bitfield_extract(&ctx->ac, false, src);
1819 break;
1820 case nir_op_bitfield_insert:
1821 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1822 break;
1823 case nir_op_bitfield_reverse:
1824 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1825 break;
1826 case nir_op_bit_count:
1827 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1828 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1829 else {
1830 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1831 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1832 }
1833 break;
1834 case nir_op_vec2:
1835 case nir_op_vec3:
1836 case nir_op_vec4:
1837 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1838 src[i] = ac_to_integer(&ctx->ac, src[i]);
1839 result = ac_build_gather_values(&ctx->ac, src, num_components);
1840 break;
1841 case nir_op_f2i32:
1842 case nir_op_f2i64:
1843 src[0] = ac_to_float(&ctx->ac, src[0]);
1844 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1845 break;
1846 case nir_op_f2u32:
1847 case nir_op_f2u64:
1848 src[0] = ac_to_float(&ctx->ac, src[0]);
1849 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1850 break;
1851 case nir_op_i2f32:
1852 case nir_op_i2f64:
1853 src[0] = ac_to_integer(&ctx->ac, src[0]);
1854 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1855 break;
1856 case nir_op_u2f32:
1857 case nir_op_u2f64:
1858 src[0] = ac_to_integer(&ctx->ac, src[0]);
1859 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1860 break;
1861 case nir_op_f2f64:
1862 src[0] = ac_to_float(&ctx->ac, src[0]);
1863 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1864 break;
1865 case nir_op_f2f32:
1866 src[0] = ac_to_float(&ctx->ac, src[0]);
1867 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1868 break;
1869 case nir_op_u2u32:
1870 case nir_op_u2u64:
1871 src[0] = ac_to_integer(&ctx->ac, src[0]);
1872 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1873 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1874 else
1875 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1876 break;
1877 case nir_op_i2i32:
1878 case nir_op_i2i64:
1879 src[0] = ac_to_integer(&ctx->ac, src[0]);
1880 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1881 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1882 else
1883 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1884 break;
1885 case nir_op_bcsel:
1886 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1887 break;
1888 case nir_op_find_lsb:
1889 src[0] = ac_to_integer(&ctx->ac, src[0]);
1890 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1891 break;
1892 case nir_op_ufind_msb:
1893 src[0] = ac_to_integer(&ctx->ac, src[0]);
1894 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1895 break;
1896 case nir_op_ifind_msb:
1897 src[0] = ac_to_integer(&ctx->ac, src[0]);
1898 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1899 break;
1900 case nir_op_uadd_carry:
1901 src[0] = ac_to_integer(&ctx->ac, src[0]);
1902 src[1] = ac_to_integer(&ctx->ac, src[1]);
1903 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1904 break;
1905 case nir_op_usub_borrow:
1906 src[0] = ac_to_integer(&ctx->ac, src[0]);
1907 src[1] = ac_to_integer(&ctx->ac, src[1]);
1908 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1909 break;
1910 case nir_op_b2f:
1911 result = emit_b2f(&ctx->ac, src[0]);
1912 break;
1913 case nir_op_f2b:
1914 result = emit_f2b(&ctx->ac, src[0]);
1915 break;
1916 case nir_op_b2i:
1917 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1918 break;
1919 case nir_op_i2b:
1920 src[0] = ac_to_integer(&ctx->ac, src[0]);
1921 result = emit_i2b(&ctx->ac, src[0]);
1922 break;
1923 case nir_op_fquantize2f16:
1924 result = emit_f2f16(&ctx->ac, src[0]);
1925 break;
1926 case nir_op_umul_high:
1927 src[0] = ac_to_integer(&ctx->ac, src[0]);
1928 src[1] = ac_to_integer(&ctx->ac, src[1]);
1929 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1930 break;
1931 case nir_op_imul_high:
1932 src[0] = ac_to_integer(&ctx->ac, src[0]);
1933 src[1] = ac_to_integer(&ctx->ac, src[1]);
1934 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1935 break;
1936 case nir_op_pack_half_2x16:
1937 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1938 break;
1939 case nir_op_unpack_half_2x16:
1940 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1941 break;
1942 case nir_op_fddx:
1943 case nir_op_fddy:
1944 case nir_op_fddx_fine:
1945 case nir_op_fddy_fine:
1946 case nir_op_fddx_coarse:
1947 case nir_op_fddy_coarse:
1948 result = emit_ddxy(ctx, instr->op, src[0]);
1949 break;
1950
1951 case nir_op_unpack_64_2x32_split_x: {
1952 assert(ac_get_llvm_num_components(src[0]) == 1);
1953 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1954 ctx->ac.v2i32,
1955 "");
1956 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1957 ctx->ac.i32_0, "");
1958 break;
1959 }
1960
1961 case nir_op_unpack_64_2x32_split_y: {
1962 assert(ac_get_llvm_num_components(src[0]) == 1);
1963 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1964 ctx->ac.v2i32,
1965 "");
1966 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1967 ctx->ac.i32_1, "");
1968 break;
1969 }
1970
1971 case nir_op_pack_64_2x32_split: {
1972 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1973 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1974 src[0], ctx->ac.i32_0, "");
1975 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1976 src[1], ctx->ac.i32_1, "");
1977 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1978 break;
1979 }
1980
1981 case nir_op_cube_face_coord: {
1982 src[0] = ac_to_float(&ctx->ac, src[0]);
1983 LLVMValueRef results[2];
1984 LLVMValueRef in[3];
1985 for (unsigned chan = 0; chan < 3; chan++)
1986 in[chan] = ac_llvm_extract_elem(&ctx->ac, src[0], chan);
1987 results[0] = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubetc",
1988 ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
1989 results[1] = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubesc",
1990 ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
1991 result = ac_build_gather_values(&ctx->ac, results, 2);
1992 break;
1993 }
1994
1995 case nir_op_cube_face_index: {
1996 src[0] = ac_to_float(&ctx->ac, src[0]);
1997 LLVMValueRef in[3];
1998 for (unsigned chan = 0; chan < 3; chan++)
1999 in[chan] = ac_llvm_extract_elem(&ctx->ac, src[0], chan);
2000 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubeid",
2001 ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
2002 break;
2003 }
2004
2005 default:
2006 fprintf(stderr, "Unknown NIR alu instr: ");
2007 nir_print_instr(&instr->instr, stderr);
2008 fprintf(stderr, "\n");
2009 abort();
2010 }
2011
2012 if (result) {
2013 assert(instr->dest.dest.is_ssa);
2014 result = ac_to_integer(&ctx->ac, result);
2015 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2016 result);
2017 }
2018 }
2019
2020 static void visit_load_const(struct ac_nir_context *ctx,
2021 const nir_load_const_instr *instr)
2022 {
2023 LLVMValueRef values[4], value = NULL;
2024 LLVMTypeRef element_type =
2025 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2026
2027 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2028 switch (instr->def.bit_size) {
2029 case 32:
2030 values[i] = LLVMConstInt(element_type,
2031 instr->value.u32[i], false);
2032 break;
2033 case 64:
2034 values[i] = LLVMConstInt(element_type,
2035 instr->value.u64[i], false);
2036 break;
2037 default:
2038 fprintf(stderr,
2039 "unsupported nir load_const bit_size: %d\n",
2040 instr->def.bit_size);
2041 abort();
2042 }
2043 }
2044 if (instr->def.num_components > 1) {
2045 value = LLVMConstVector(values, instr->def.num_components);
2046 } else
2047 value = values[0];
2048
2049 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2050 }
2051
2052 static LLVMValueRef
2053 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2054 {
2055 LLVMValueRef size =
2056 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2057 LLVMConstInt(ctx->ac.i32, 2, false), "");
2058
2059 /* VI only */
2060 if (ctx->ac.chip_class == VI && in_elements) {
2061 /* On VI, the descriptor contains the size in bytes,
2062 * but TXQ must return the size in elements.
2063 * The stride is always non-zero for resources using TXQ.
2064 */
2065 LLVMValueRef stride =
2066 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2067 ctx->ac.i32_1, "");
2068 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2069 LLVMConstInt(ctx->ac.i32, 16, false), "");
2070 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2071 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2072
2073 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2074 }
2075 return size;
2076 }
2077
2078 /**
2079 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2080 * intrinsic names).
2081 */
2082 static void build_int_type_name(
2083 LLVMTypeRef type,
2084 char *buf, unsigned bufsize)
2085 {
2086 assert(bufsize >= 6);
2087
2088 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2089 snprintf(buf, bufsize, "v%ui32",
2090 LLVMGetVectorSize(type));
2091 else
2092 strcpy(buf, "i32");
2093 }
2094
2095 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2096 struct ac_image_args *args,
2097 const nir_tex_instr *instr)
2098 {
2099 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2100 LLVMValueRef coord = args->addr;
2101 LLVMValueRef half_texel[2];
2102 LLVMValueRef compare_cube_wa = NULL;
2103 LLVMValueRef result;
2104 int c;
2105 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2106
2107 //TODO Rect
2108 {
2109 struct ac_image_args txq_args = { 0 };
2110
2111 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2112 txq_args.opcode = ac_image_get_resinfo;
2113 txq_args.dmask = 0xf;
2114 txq_args.addr = ctx->i32_0;
2115 txq_args.resource = args->resource;
2116 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2117
2118 for (c = 0; c < 2; c++) {
2119 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2120 LLVMConstInt(ctx->i32, c, false), "");
2121 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2122 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2123 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2124 LLVMConstReal(ctx->f32, -0.5), "");
2125 }
2126 }
2127
2128 LLVMValueRef orig_coords = args->addr;
2129
2130 for (c = 0; c < 2; c++) {
2131 LLVMValueRef tmp;
2132 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2133 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2134 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2135 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2136 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2137 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2138 }
2139
2140
2141 /*
2142 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2143 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2144 * workaround by sampling using a scaled type and converting.
2145 * This is taken from amdgpu-pro shaders.
2146 */
2147 /* NOTE this produces some ugly code compared to amdgpu-pro,
2148 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2149 * and then reads them back. -pro generates two selects,
2150 * one s_cmp for the descriptor rewriting
2151 * one v_cmp for the coordinate and result changes.
2152 */
2153 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2154 LLVMValueRef tmp, tmp2;
2155
2156 /* workaround 8/8/8/8 uint/sint cube gather bug */
2157 /* first detect it then change to a scaled read and f2i */
2158 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2159 tmp2 = tmp;
2160
2161 /* extract the DATA_FORMAT */
2162 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2163 LLVMConstInt(ctx->i32, 6, false), false);
2164
2165 /* is the DATA_FORMAT == 8_8_8_8 */
2166 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2167
2168 if (stype == GLSL_TYPE_UINT)
2169 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2170 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2171 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2172 else
2173 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2174 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2175 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2176
2177 /* replace the NUM FORMAT in the descriptor */
2178 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2179 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2180
2181 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2182
2183 /* don't modify the coordinates for this case */
2184 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2185 }
2186 args->addr = coord;
2187 result = ac_build_image_opcode(ctx, args);
2188
2189 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2190 LLVMValueRef tmp, tmp2;
2191
2192 /* if the cube workaround is in place, f2i the result. */
2193 for (c = 0; c < 4; c++) {
2194 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2195 if (stype == GLSL_TYPE_UINT)
2196 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2197 else
2198 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2199 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2200 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2201 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2202 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2203 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2204 }
2205 }
2206 return result;
2207 }
2208
2209 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2210 const nir_tex_instr *instr,
2211 bool lod_is_zero,
2212 struct ac_image_args *args)
2213 {
2214 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2215 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2216
2217 return ac_build_buffer_load_format(&ctx->ac,
2218 args->resource,
2219 args->addr,
2220 ctx->ac.i32_0,
2221 util_last_bit(mask),
2222 false, true);
2223 }
2224
2225 args->opcode = ac_image_sample;
2226 args->compare = instr->is_shadow;
2227
2228 switch (instr->op) {
2229 case nir_texop_txf:
2230 case nir_texop_txf_ms:
2231 case nir_texop_samples_identical:
2232 args->opcode = lod_is_zero ||
2233 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2234 ac_image_load : ac_image_load_mip;
2235 args->compare = false;
2236 args->offset = false;
2237 break;
2238 case nir_texop_txb:
2239 args->bias = true;
2240 break;
2241 case nir_texop_txl:
2242 if (lod_is_zero)
2243 args->level_zero = true;
2244 else
2245 args->lod = true;
2246 break;
2247 case nir_texop_txs:
2248 case nir_texop_query_levels:
2249 args->opcode = ac_image_get_resinfo;
2250 break;
2251 case nir_texop_tex:
2252 if (ctx->stage != MESA_SHADER_FRAGMENT)
2253 args->level_zero = true;
2254 break;
2255 case nir_texop_txd:
2256 args->deriv = true;
2257 break;
2258 case nir_texop_tg4:
2259 args->opcode = ac_image_gather4;
2260 args->level_zero = true;
2261 break;
2262 case nir_texop_lod:
2263 args->opcode = ac_image_get_lod;
2264 args->compare = false;
2265 args->offset = false;
2266 break;
2267 default:
2268 break;
2269 }
2270
2271 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2272 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2273 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2274 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2275 }
2276 }
2277 return ac_build_image_opcode(&ctx->ac, args);
2278 }
2279
2280 static LLVMValueRef
2281 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2282 unsigned desc_set, unsigned binding)
2283 {
2284 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2285 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2286 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2287 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2288 unsigned base_offset = layout->binding[binding].offset;
2289 LLVMValueRef offset, stride;
2290
2291 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2292 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2293 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2294 layout->binding[binding].dynamic_offset_offset;
2295 desc_ptr = ctx->abi.push_constants;
2296 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2297 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2298 } else
2299 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2300
2301 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2302 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2303 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2304
2305 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2306 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2307 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2308
2309 return desc_ptr;
2310 }
2311
2312 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2313 nir_intrinsic_instr *instr)
2314 {
2315 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2316 LLVMValueRef index = get_src(ctx, instr->src[1]);
2317
2318 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2319 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2320 return result;
2321 }
2322
2323 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2324 nir_intrinsic_instr *instr)
2325 {
2326 LLVMValueRef ptr, addr;
2327
2328 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2329 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2330 get_src(ctx, instr->src[0]), "");
2331
2332 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2333 ptr = ac_cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2334
2335 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2336 }
2337
2338 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2339 const nir_intrinsic_instr *instr)
2340 {
2341 LLVMValueRef index = get_src(ctx, instr->src[0]);
2342
2343 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2344 }
2345
2346 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2347 {
2348 uint32_t new_mask = 0;
2349 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2350 if (mask & (1u << i))
2351 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2352 return new_mask;
2353 }
2354
2355 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2356 unsigned start, unsigned count)
2357 {
2358 LLVMTypeRef type = LLVMTypeOf(src);
2359
2360 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2361 assert(start == 0);
2362 assert(count == 1);
2363 return src;
2364 }
2365
2366 unsigned src_elements = LLVMGetVectorSize(type);
2367 assert(start < src_elements);
2368 assert(start + count <= src_elements);
2369
2370 if (start == 0 && count == src_elements)
2371 return src;
2372
2373 if (count == 1)
2374 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2375
2376 assert(count <= 8);
2377 LLVMValueRef indices[8];
2378 for (unsigned i = 0; i < count; ++i)
2379 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2380
2381 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2382 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2383 }
2384
2385 static void visit_store_ssbo(struct ac_nir_context *ctx,
2386 nir_intrinsic_instr *instr)
2387 {
2388 const char *store_name;
2389 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2390 LLVMTypeRef data_type = ctx->ac.f32;
2391 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2392 int components_32bit = elem_size_mult * instr->num_components;
2393 unsigned writemask = nir_intrinsic_write_mask(instr);
2394 LLVMValueRef base_data, base_offset;
2395 LLVMValueRef params[6];
2396
2397 params[1] = ctx->abi->load_ssbo(ctx->abi,
2398 get_src(ctx, instr->src[1]), true);
2399 params[2] = ctx->ac.i32_0; /* vindex */
2400 params[4] = ctx->ac.i1false; /* glc */
2401 params[5] = ctx->ac.i1false; /* slc */
2402
2403 if (components_32bit > 1)
2404 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2405
2406 writemask = widen_mask(writemask, elem_size_mult);
2407
2408 base_data = ac_to_float(&ctx->ac, src_data);
2409 base_data = ac_trim_vector(&ctx->ac, base_data, instr->num_components);
2410 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2411 data_type, "");
2412 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2413 while (writemask) {
2414 int start, count;
2415 LLVMValueRef data;
2416 LLVMValueRef offset;
2417
2418 u_bit_scan_consecutive_range(&writemask, &start, &count);
2419
2420 /* Due to an LLVM limitation, split 3-element writes
2421 * into a 2-element and a 1-element write. */
2422 if (count == 3) {
2423 writemask |= 1 << (start + 2);
2424 count = 2;
2425 }
2426
2427 if (count > 4) {
2428 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2429 count = 4;
2430 }
2431
2432 if (count == 4) {
2433 store_name = "llvm.amdgcn.buffer.store.v4f32";
2434 } else if (count == 2) {
2435 store_name = "llvm.amdgcn.buffer.store.v2f32";
2436
2437 } else {
2438 assert(count == 1);
2439 store_name = "llvm.amdgcn.buffer.store.f32";
2440 }
2441 data = extract_vector_range(&ctx->ac, base_data, start, count);
2442
2443 offset = base_offset;
2444 if (start != 0) {
2445 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2446 }
2447 params[0] = data;
2448 params[3] = offset;
2449 ac_build_intrinsic(&ctx->ac, store_name,
2450 ctx->ac.voidt, params, 6, 0);
2451 }
2452 }
2453
2454 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2455 const nir_intrinsic_instr *instr)
2456 {
2457 const char *name;
2458 LLVMValueRef params[6];
2459 int arg_count = 0;
2460
2461 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2462 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2463 }
2464 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2465 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2466 get_src(ctx, instr->src[0]),
2467 true);
2468 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2469 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2470 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2471
2472 switch (instr->intrinsic) {
2473 case nir_intrinsic_ssbo_atomic_add:
2474 name = "llvm.amdgcn.buffer.atomic.add";
2475 break;
2476 case nir_intrinsic_ssbo_atomic_imin:
2477 name = "llvm.amdgcn.buffer.atomic.smin";
2478 break;
2479 case nir_intrinsic_ssbo_atomic_umin:
2480 name = "llvm.amdgcn.buffer.atomic.umin";
2481 break;
2482 case nir_intrinsic_ssbo_atomic_imax:
2483 name = "llvm.amdgcn.buffer.atomic.smax";
2484 break;
2485 case nir_intrinsic_ssbo_atomic_umax:
2486 name = "llvm.amdgcn.buffer.atomic.umax";
2487 break;
2488 case nir_intrinsic_ssbo_atomic_and:
2489 name = "llvm.amdgcn.buffer.atomic.and";
2490 break;
2491 case nir_intrinsic_ssbo_atomic_or:
2492 name = "llvm.amdgcn.buffer.atomic.or";
2493 break;
2494 case nir_intrinsic_ssbo_atomic_xor:
2495 name = "llvm.amdgcn.buffer.atomic.xor";
2496 break;
2497 case nir_intrinsic_ssbo_atomic_exchange:
2498 name = "llvm.amdgcn.buffer.atomic.swap";
2499 break;
2500 case nir_intrinsic_ssbo_atomic_comp_swap:
2501 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2502 break;
2503 default:
2504 abort();
2505 }
2506
2507 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2508 }
2509
2510 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2511 const nir_intrinsic_instr *instr)
2512 {
2513 LLVMValueRef results[2];
2514 int load_components;
2515 int num_components = instr->num_components;
2516 if (instr->dest.ssa.bit_size == 64)
2517 num_components *= 2;
2518
2519 for (int i = 0; i < num_components; i += load_components) {
2520 load_components = MIN2(num_components - i, 4);
2521 const char *load_name;
2522 LLVMTypeRef data_type = ctx->ac.f32;
2523 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2524 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2525
2526 if (load_components == 3)
2527 data_type = LLVMVectorType(ctx->ac.f32, 4);
2528 else if (load_components > 1)
2529 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2530
2531 if (load_components >= 3)
2532 load_name = "llvm.amdgcn.buffer.load.v4f32";
2533 else if (load_components == 2)
2534 load_name = "llvm.amdgcn.buffer.load.v2f32";
2535 else if (load_components == 1)
2536 load_name = "llvm.amdgcn.buffer.load.f32";
2537 else
2538 unreachable("unhandled number of components");
2539
2540 LLVMValueRef params[] = {
2541 ctx->abi->load_ssbo(ctx->abi,
2542 get_src(ctx, instr->src[0]),
2543 false),
2544 ctx->ac.i32_0,
2545 offset,
2546 ctx->ac.i1false,
2547 ctx->ac.i1false,
2548 };
2549
2550 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2551 }
2552
2553 assume(results[0]);
2554 LLVMValueRef ret = results[0];
2555 if (num_components > 4 || num_components == 3) {
2556 LLVMValueRef masks[] = {
2557 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2558 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2559 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2560 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2561 };
2562
2563 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2564 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2565 results[num_components > 4 ? 1 : 0], swizzle, "");
2566 }
2567
2568 return LLVMBuildBitCast(ctx->ac.builder, ret,
2569 get_def_type(ctx, &instr->dest.ssa), "");
2570 }
2571
2572 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2573 const nir_intrinsic_instr *instr)
2574 {
2575 LLVMValueRef ret;
2576 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2577 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2578 int num_components = instr->num_components;
2579
2580 if (ctx->abi->load_ubo)
2581 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2582
2583 if (instr->dest.ssa.bit_size == 64)
2584 num_components *= 2;
2585
2586 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2587 NULL, 0, false, false, true, true);
2588 ret = ac_trim_vector(&ctx->ac, ret, num_components);
2589 return LLVMBuildBitCast(ctx->ac.builder, ret,
2590 get_def_type(ctx, &instr->dest.ssa), "");
2591 }
2592
2593 static void
2594 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2595 bool vs_in, unsigned *vertex_index_out,
2596 LLVMValueRef *vertex_index_ref,
2597 unsigned *const_out, LLVMValueRef *indir_out)
2598 {
2599 unsigned const_offset = 0;
2600 nir_deref *tail = &deref->deref;
2601 LLVMValueRef offset = NULL;
2602
2603 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2604 tail = tail->child;
2605 nir_deref_array *deref_array = nir_deref_as_array(tail);
2606 if (vertex_index_out)
2607 *vertex_index_out = deref_array->base_offset;
2608
2609 if (vertex_index_ref) {
2610 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2611 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2612 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2613 }
2614 *vertex_index_ref = vtx;
2615 }
2616 }
2617
2618 if (deref->var->data.compact) {
2619 assert(tail->child->deref_type == nir_deref_type_array);
2620 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2621 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2622 /* We always lower indirect dereferences for "compact" array vars. */
2623 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2624
2625 const_offset = deref_array->base_offset;
2626 goto out;
2627 }
2628
2629 while (tail->child != NULL) {
2630 const struct glsl_type *parent_type = tail->type;
2631 tail = tail->child;
2632
2633 if (tail->deref_type == nir_deref_type_array) {
2634 nir_deref_array *deref_array = nir_deref_as_array(tail);
2635 LLVMValueRef index, stride, local_offset;
2636 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2637
2638 const_offset += size * deref_array->base_offset;
2639 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2640 continue;
2641
2642 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2643 index = get_src(ctx, deref_array->indirect);
2644 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2645 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2646
2647 if (offset)
2648 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2649 else
2650 offset = local_offset;
2651 } else if (tail->deref_type == nir_deref_type_struct) {
2652 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2653
2654 for (unsigned i = 0; i < deref_struct->index; i++) {
2655 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2656 const_offset += glsl_count_attribute_slots(ft, vs_in);
2657 }
2658 } else
2659 unreachable("unsupported deref type");
2660
2661 }
2662 out:
2663 if (const_offset && offset)
2664 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2665 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2666 "");
2667
2668 *const_out = const_offset;
2669 *indir_out = offset;
2670 }
2671
2672
2673 /* The offchip buffer layout for TCS->TES is
2674 *
2675 * - attribute 0 of patch 0 vertex 0
2676 * - attribute 0 of patch 0 vertex 1
2677 * - attribute 0 of patch 0 vertex 2
2678 * ...
2679 * - attribute 0 of patch 1 vertex 0
2680 * - attribute 0 of patch 1 vertex 1
2681 * ...
2682 * - attribute 1 of patch 0 vertex 0
2683 * - attribute 1 of patch 0 vertex 1
2684 * ...
2685 * - per patch attribute 0 of patch 0
2686 * - per patch attribute 0 of patch 1
2687 * ...
2688 *
2689 * Note that every attribute has 4 components.
2690 */
2691 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2692 LLVMValueRef vertex_index,
2693 LLVMValueRef param_index)
2694 {
2695 LLVMValueRef base_addr, vertices_per_patch, num_patches;
2696 LLVMValueRef param_stride, constant16;
2697 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2698
2699 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
2700 num_patches = ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2701
2702 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2703 if (vertex_index) {
2704 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2705 vertices_per_patch, "");
2706
2707 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2708 vertex_index, "");
2709
2710 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2711 num_patches, "");
2712 } else {
2713 base_addr = rel_patch_id;
2714 param_stride = num_patches;
2715 }
2716
2717 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2718 LLVMBuildMul(ctx->ac.builder, param_index,
2719 param_stride, ""), "");
2720
2721 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2722
2723 if (!vertex_index) {
2724 LLVMValueRef patch_data_offset =
2725 ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2726
2727 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2728 patch_data_offset, "");
2729 }
2730 return base_addr;
2731 }
2732
2733 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2734 unsigned param,
2735 unsigned const_index,
2736 bool is_compact,
2737 LLVMValueRef vertex_index,
2738 LLVMValueRef indir_index)
2739 {
2740 LLVMValueRef param_index;
2741
2742 if (indir_index)
2743 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2744 indir_index, "");
2745 else {
2746 if (const_index && !is_compact)
2747 param += const_index;
2748 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2749 }
2750 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2751 }
2752
2753 static void
2754 mark_tess_output(struct radv_shader_context *ctx,
2755 bool is_patch, uint32_t param)
2756
2757 {
2758 if (is_patch) {
2759 ctx->tess_patch_outputs_written |= (1ull << param);
2760 } else
2761 ctx->tess_outputs_written |= (1ull << param);
2762 }
2763
2764 static LLVMValueRef
2765 get_dw_address(struct radv_shader_context *ctx,
2766 LLVMValueRef dw_addr,
2767 unsigned param,
2768 unsigned const_index,
2769 bool compact_const_index,
2770 LLVMValueRef vertex_index,
2771 LLVMValueRef stride,
2772 LLVMValueRef indir_index)
2773
2774 {
2775
2776 if (vertex_index) {
2777 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2778 LLVMBuildMul(ctx->ac.builder,
2779 vertex_index,
2780 stride, ""), "");
2781 }
2782
2783 if (indir_index)
2784 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2785 LLVMBuildMul(ctx->ac.builder, indir_index,
2786 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2787 else if (const_index && !compact_const_index)
2788 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2789 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2790
2791 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2792 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2793
2794 if (const_index && compact_const_index)
2795 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2796 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2797 return dw_addr;
2798 }
2799
2800 static LLVMValueRef
2801 load_tcs_varyings(struct ac_shader_abi *abi,
2802 LLVMTypeRef type,
2803 LLVMValueRef vertex_index,
2804 LLVMValueRef indir_index,
2805 unsigned const_index,
2806 unsigned location,
2807 unsigned driver_location,
2808 unsigned component,
2809 unsigned num_components,
2810 bool is_patch,
2811 bool is_compact,
2812 bool load_input)
2813 {
2814 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2815 LLVMValueRef dw_addr, stride;
2816 LLVMValueRef value[4], result;
2817 unsigned param = shader_io_get_unique_index(location);
2818
2819 if (load_input) {
2820 stride = ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2821 dw_addr = get_tcs_in_current_patch_offset(ctx);
2822 } else {
2823 if (!is_patch) {
2824 stride = get_tcs_out_vertex_stride(ctx);
2825 dw_addr = get_tcs_out_current_patch_offset(ctx);
2826 } else {
2827 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2828 stride = NULL;
2829 }
2830 }
2831
2832 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2833 indir_index);
2834
2835 for (unsigned i = 0; i < num_components + component; i++) {
2836 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2837 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2838 ctx->ac.i32_1, "");
2839 }
2840 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2841 return result;
2842 }
2843
2844 static void
2845 store_tcs_output(struct ac_shader_abi *abi,
2846 LLVMValueRef vertex_index,
2847 LLVMValueRef param_index,
2848 unsigned const_index,
2849 unsigned location,
2850 unsigned driver_location,
2851 LLVMValueRef src,
2852 unsigned component,
2853 bool is_patch,
2854 bool is_compact,
2855 unsigned writemask)
2856 {
2857 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2858 LLVMValueRef dw_addr;
2859 LLVMValueRef stride = NULL;
2860 LLVMValueRef buf_addr = NULL;
2861 unsigned param;
2862 bool store_lds = true;
2863
2864 if (is_patch) {
2865 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2866 store_lds = false;
2867 } else {
2868 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2869 store_lds = false;
2870 }
2871
2872 param = shader_io_get_unique_index(location);
2873 if (location == VARYING_SLOT_CLIP_DIST0 &&
2874 is_compact && const_index > 3) {
2875 const_index -= 3;
2876 param++;
2877 }
2878
2879 if (!is_patch) {
2880 stride = get_tcs_out_vertex_stride(ctx);
2881 dw_addr = get_tcs_out_current_patch_offset(ctx);
2882 } else {
2883 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2884 }
2885
2886 mark_tess_output(ctx, is_patch, param);
2887
2888 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2889 param_index);
2890 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2891 vertex_index, param_index);
2892
2893 bool is_tess_factor = false;
2894 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2895 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2896 is_tess_factor = true;
2897
2898 unsigned base = is_compact ? const_index : 0;
2899 for (unsigned chan = 0; chan < 8; chan++) {
2900 if (!(writemask & (1 << chan)))
2901 continue;
2902 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2903
2904 if (store_lds || is_tess_factor) {
2905 LLVMValueRef dw_addr_chan =
2906 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2907 LLVMConstInt(ctx->ac.i32, chan, false), "");
2908 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2909 }
2910
2911 if (!is_tess_factor && writemask != 0xF)
2912 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2913 buf_addr, ctx->oc_lds,
2914 4 * (base + chan), 1, 0, true, false);
2915 }
2916
2917 if (writemask == 0xF) {
2918 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2919 buf_addr, ctx->oc_lds,
2920 (base * 4), 1, 0, true, false);
2921 }
2922 }
2923
2924 static LLVMValueRef
2925 load_tes_input(struct ac_shader_abi *abi,
2926 LLVMTypeRef type,
2927 LLVMValueRef vertex_index,
2928 LLVMValueRef param_index,
2929 unsigned const_index,
2930 unsigned location,
2931 unsigned driver_location,
2932 unsigned component,
2933 unsigned num_components,
2934 bool is_patch,
2935 bool is_compact,
2936 bool load_input)
2937 {
2938 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2939 LLVMValueRef buf_addr;
2940 LLVMValueRef result;
2941 unsigned param = shader_io_get_unique_index(location);
2942
2943 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2944 const_index -= 3;
2945 param++;
2946 }
2947
2948 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2949 is_compact, vertex_index, param_index);
2950
2951 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
2952 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
2953
2954 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
2955 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2956 result = ac_trim_vector(&ctx->ac, result, num_components);
2957 return result;
2958 }
2959
2960 static LLVMValueRef
2961 load_gs_input(struct ac_shader_abi *abi,
2962 unsigned location,
2963 unsigned driver_location,
2964 unsigned component,
2965 unsigned num_components,
2966 unsigned vertex_index,
2967 unsigned const_index,
2968 LLVMTypeRef type)
2969 {
2970 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2971 LLVMValueRef vtx_offset;
2972 unsigned param, vtx_offset_param;
2973 LLVMValueRef value[4], result;
2974
2975 vtx_offset_param = vertex_index;
2976 assert(vtx_offset_param < 6);
2977 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
2978 LLVMConstInt(ctx->ac.i32, 4, false), "");
2979
2980 param = shader_io_get_unique_index(location);
2981
2982 for (unsigned i = component; i < num_components + component; i++) {
2983 if (ctx->ac.chip_class >= GFX9) {
2984 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2985 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2986 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2987 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2988 } else {
2989 LLVMValueRef soffset =
2990 LLVMConstInt(ctx->ac.i32,
2991 (param * 4 + i + const_index) * 256,
2992 false);
2993
2994 value[i] = ac_build_buffer_load(&ctx->ac,
2995 ctx->esgs_ring, 1,
2996 ctx->ac.i32_0,
2997 vtx_offset, soffset,
2998 0, 1, 0, true, false);
2999
3000 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3001 type, "");
3002 }
3003 }
3004 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3005 result = ac_to_integer(&ctx->ac, result);
3006 return result;
3007 }
3008
3009 static LLVMValueRef
3010 build_gep_for_deref(struct ac_nir_context *ctx,
3011 nir_deref_var *deref)
3012 {
3013 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3014 assert(entry->data);
3015 LLVMValueRef val = entry->data;
3016 nir_deref *tail = deref->deref.child;
3017 while (tail != NULL) {
3018 LLVMValueRef offset;
3019 switch (tail->deref_type) {
3020 case nir_deref_type_array: {
3021 nir_deref_array *array = nir_deref_as_array(tail);
3022 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3023 if (array->deref_array_type ==
3024 nir_deref_array_type_indirect) {
3025 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3026 get_src(ctx,
3027 array->indirect),
3028 "");
3029 }
3030 break;
3031 }
3032 case nir_deref_type_struct: {
3033 nir_deref_struct *deref_struct =
3034 nir_deref_as_struct(tail);
3035 offset = LLVMConstInt(ctx->ac.i32,
3036 deref_struct->index, 0);
3037 break;
3038 }
3039 default:
3040 unreachable("bad deref type");
3041 }
3042 val = ac_build_gep0(&ctx->ac, val, offset);
3043 tail = tail->child;
3044 }
3045 return val;
3046 }
3047
3048 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3049 nir_intrinsic_instr *instr,
3050 bool load_inputs)
3051 {
3052 LLVMValueRef result;
3053 LLVMValueRef vertex_index = NULL;
3054 LLVMValueRef indir_index = NULL;
3055 unsigned const_index = 0;
3056 unsigned location = instr->variables[0]->var->data.location;
3057 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3058 const bool is_patch = instr->variables[0]->var->data.patch;
3059 const bool is_compact = instr->variables[0]->var->data.compact;
3060
3061 get_deref_offset(ctx, instr->variables[0],
3062 false, NULL, is_patch ? NULL : &vertex_index,
3063 &const_index, &indir_index);
3064
3065 LLVMTypeRef dest_type = get_def_type(ctx, &instr->dest.ssa);
3066
3067 LLVMTypeRef src_component_type;
3068 if (LLVMGetTypeKind(dest_type) == LLVMVectorTypeKind)
3069 src_component_type = LLVMGetElementType(dest_type);
3070 else
3071 src_component_type = dest_type;
3072
3073 result = ctx->abi->load_tess_varyings(ctx->abi, src_component_type,
3074 vertex_index, indir_index,
3075 const_index, location, driver_location,
3076 instr->variables[0]->var->data.location_frac,
3077 instr->num_components,
3078 is_patch, is_compact, load_inputs);
3079 return LLVMBuildBitCast(ctx->ac.builder, result, dest_type, "");
3080 }
3081
3082 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3083 nir_intrinsic_instr *instr)
3084 {
3085 LLVMValueRef values[8];
3086 int idx = instr->variables[0]->var->data.driver_location;
3087 int ve = instr->dest.ssa.num_components;
3088 unsigned comp = instr->variables[0]->var->data.location_frac;
3089 LLVMValueRef indir_index;
3090 LLVMValueRef ret;
3091 unsigned const_index;
3092 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3093 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3094 instr->variables[0]->var->data.mode == nir_var_shader_in;
3095 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3096 &const_index, &indir_index);
3097
3098 if (instr->dest.ssa.bit_size == 64)
3099 ve *= 2;
3100
3101 switch (instr->variables[0]->var->data.mode) {
3102 case nir_var_shader_in:
3103 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3104 ctx->stage == MESA_SHADER_TESS_EVAL) {
3105 return load_tess_varyings(ctx, instr, true);
3106 }
3107
3108 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3109 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3110 LLVMValueRef indir_index;
3111 unsigned const_index, vertex_index;
3112 get_deref_offset(ctx, instr->variables[0],
3113 false, &vertex_index, NULL,
3114 &const_index, &indir_index);
3115
3116 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3117 instr->variables[0]->var->data.driver_location,
3118 instr->variables[0]->var->data.location_frac,
3119 instr->num_components, vertex_index, const_index, type);
3120 }
3121
3122 for (unsigned chan = comp; chan < ve + comp; chan++) {
3123 if (indir_index) {
3124 unsigned count = glsl_count_attribute_slots(
3125 instr->variables[0]->var->type,
3126 ctx->stage == MESA_SHADER_VERTEX);
3127 count -= chan / 4;
3128 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3129 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3130 stride, false, true);
3131
3132 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3133 tmp_vec,
3134 indir_index, "");
3135 } else
3136 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3137 }
3138 break;
3139 case nir_var_local:
3140 for (unsigned chan = 0; chan < ve; chan++) {
3141 if (indir_index) {
3142 unsigned count = glsl_count_attribute_slots(
3143 instr->variables[0]->var->type, false);
3144 count -= chan / 4;
3145 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3146 &ctx->ac, ctx->locals + idx + chan, count,
3147 stride, true, true);
3148
3149 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3150 tmp_vec,
3151 indir_index, "");
3152 } else {
3153 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3154 }
3155 }
3156 break;
3157 case nir_var_shared: {
3158 LLVMValueRef address = build_gep_for_deref(ctx,
3159 instr->variables[0]);
3160 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3161 return LLVMBuildBitCast(ctx->ac.builder, val,
3162 get_def_type(ctx, &instr->dest.ssa),
3163 "");
3164 }
3165 case nir_var_shader_out:
3166 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3167 return load_tess_varyings(ctx, instr, false);
3168 }
3169
3170 for (unsigned chan = comp; chan < ve + comp; chan++) {
3171 if (indir_index) {
3172 unsigned count = glsl_count_attribute_slots(
3173 instr->variables[0]->var->type, false);
3174 count -= chan / 4;
3175 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3176 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3177 stride, true, true);
3178
3179 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3180 tmp_vec,
3181 indir_index, "");
3182 } else {
3183 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3184 ctx->abi->outputs[idx + chan + const_index * stride],
3185 "");
3186 }
3187 }
3188 break;
3189 default:
3190 unreachable("unhandle variable mode");
3191 }
3192 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3193 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3194 }
3195
3196 static void
3197 visit_store_var(struct ac_nir_context *ctx,
3198 nir_intrinsic_instr *instr)
3199 {
3200 LLVMValueRef temp_ptr, value;
3201 int idx = instr->variables[0]->var->data.driver_location;
3202 unsigned comp = instr->variables[0]->var->data.location_frac;
3203 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3204 int writemask = instr->const_index[0] << comp;
3205 LLVMValueRef indir_index;
3206 unsigned const_index;
3207 get_deref_offset(ctx, instr->variables[0], false,
3208 NULL, NULL, &const_index, &indir_index);
3209
3210 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3211
3212 src = LLVMBuildBitCast(ctx->ac.builder, src,
3213 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3214 "");
3215
3216 writemask = widen_mask(writemask, 2);
3217 }
3218
3219 switch (instr->variables[0]->var->data.mode) {
3220 case nir_var_shader_out:
3221
3222 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3223 LLVMValueRef vertex_index = NULL;
3224 LLVMValueRef indir_index = NULL;
3225 unsigned const_index = 0;
3226 const unsigned location = instr->variables[0]->var->data.location;
3227 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3228 const unsigned comp = instr->variables[0]->var->data.location_frac;
3229 const bool is_patch = instr->variables[0]->var->data.patch;
3230 const bool is_compact = instr->variables[0]->var->data.compact;
3231
3232 get_deref_offset(ctx, instr->variables[0],
3233 false, NULL, is_patch ? NULL : &vertex_index,
3234 &const_index, &indir_index);
3235
3236 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3237 const_index, location, driver_location,
3238 src, comp, is_patch, is_compact, writemask);
3239 return;
3240 }
3241
3242 for (unsigned chan = 0; chan < 8; chan++) {
3243 int stride = 4;
3244 if (!(writemask & (1 << chan)))
3245 continue;
3246
3247 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3248
3249 if (instr->variables[0]->var->data.compact)
3250 stride = 1;
3251 if (indir_index) {
3252 unsigned count = glsl_count_attribute_slots(
3253 instr->variables[0]->var->type, false);
3254 count -= chan / 4;
3255 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3256 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3257 stride, true, true);
3258
3259 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3260 value, indir_index, "");
3261 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3262 count, stride, tmp_vec);
3263
3264 } else {
3265 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3266
3267 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3268 }
3269 }
3270 break;
3271 case nir_var_local:
3272 for (unsigned chan = 0; chan < 8; chan++) {
3273 if (!(writemask & (1 << chan)))
3274 continue;
3275
3276 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3277 if (indir_index) {
3278 unsigned count = glsl_count_attribute_slots(
3279 instr->variables[0]->var->type, false);
3280 count -= chan / 4;
3281 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3282 &ctx->ac, ctx->locals + idx + chan, count,
3283 4, true, true);
3284
3285 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3286 value, indir_index, "");
3287 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3288 count, 4, tmp_vec);
3289 } else {
3290 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3291
3292 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3293 }
3294 }
3295 break;
3296 case nir_var_shared: {
3297 int writemask = instr->const_index[0];
3298 LLVMValueRef address = build_gep_for_deref(ctx,
3299 instr->variables[0]);
3300 LLVMValueRef val = get_src(ctx, instr->src[0]);
3301 unsigned components =
3302 glsl_get_vector_elements(
3303 nir_deref_tail(&instr->variables[0]->deref)->type);
3304 if (writemask == (1 << components) - 1) {
3305 val = LLVMBuildBitCast(
3306 ctx->ac.builder, val,
3307 LLVMGetElementType(LLVMTypeOf(address)), "");
3308 LLVMBuildStore(ctx->ac.builder, val, address);
3309 } else {
3310 for (unsigned chan = 0; chan < 4; chan++) {
3311 if (!(writemask & (1 << chan)))
3312 continue;
3313 LLVMValueRef ptr =
3314 LLVMBuildStructGEP(ctx->ac.builder,
3315 address, chan, "");
3316 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3317 chan);
3318 src = LLVMBuildBitCast(
3319 ctx->ac.builder, src,
3320 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3321 LLVMBuildStore(ctx->ac.builder, src, ptr);
3322 }
3323 }
3324 break;
3325 }
3326 default:
3327 break;
3328 }
3329 }
3330
3331 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3332 {
3333 switch (dim) {
3334 case GLSL_SAMPLER_DIM_BUF:
3335 return 1;
3336 case GLSL_SAMPLER_DIM_1D:
3337 return array ? 2 : 1;
3338 case GLSL_SAMPLER_DIM_2D:
3339 return array ? 3 : 2;
3340 case GLSL_SAMPLER_DIM_MS:
3341 return array ? 4 : 3;
3342 case GLSL_SAMPLER_DIM_3D:
3343 case GLSL_SAMPLER_DIM_CUBE:
3344 return 3;
3345 case GLSL_SAMPLER_DIM_RECT:
3346 case GLSL_SAMPLER_DIM_SUBPASS:
3347 return 2;
3348 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3349 return 3;
3350 default:
3351 break;
3352 }
3353 return 0;
3354 }
3355
3356 static bool
3357 glsl_is_array_image(const struct glsl_type *type)
3358 {
3359 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3360
3361 if (glsl_sampler_type_is_array(type))
3362 return true;
3363
3364 return dim == GLSL_SAMPLER_DIM_CUBE ||
3365 dim == GLSL_SAMPLER_DIM_3D ||
3366 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3367 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3368 }
3369
3370
3371 /* Adjust the sample index according to FMASK.
3372 *
3373 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3374 * which is the identity mapping. Each nibble says which physical sample
3375 * should be fetched to get that sample.
3376 *
3377 * For example, 0x11111100 means there are only 2 samples stored and
3378 * the second sample covers 3/4 of the pixel. When reading samples 0
3379 * and 1, return physical sample 0 (determined by the first two 0s
3380 * in FMASK), otherwise return physical sample 1.
3381 *
3382 * The sample index should be adjusted as follows:
3383 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3384 */
3385 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3386 LLVMValueRef coord_x, LLVMValueRef coord_y,
3387 LLVMValueRef coord_z,
3388 LLVMValueRef sample_index,
3389 LLVMValueRef fmask_desc_ptr)
3390 {
3391 LLVMValueRef fmask_load_address[4];
3392 LLVMValueRef res;
3393
3394 fmask_load_address[0] = coord_x;
3395 fmask_load_address[1] = coord_y;
3396 if (coord_z) {
3397 fmask_load_address[2] = coord_z;
3398 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3399 }
3400
3401 struct ac_image_args args = {0};
3402
3403 args.opcode = ac_image_load;
3404 args.da = coord_z ? true : false;
3405 args.resource = fmask_desc_ptr;
3406 args.dmask = 0xf;
3407 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3408
3409 res = ac_build_image_opcode(ctx, &args);
3410
3411 res = ac_to_integer(ctx, res);
3412 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3413 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3414
3415 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3416 res,
3417 ctx->i32_0, "");
3418
3419 LLVMValueRef sample_index4 =
3420 LLVMBuildMul(ctx->builder, sample_index, four, "");
3421 LLVMValueRef shifted_fmask =
3422 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3423 LLVMValueRef final_sample =
3424 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3425
3426 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3427 * resource descriptor is 0 (invalid),
3428 */
3429 LLVMValueRef fmask_desc =
3430 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3431 ctx->v8i32, "");
3432
3433 LLVMValueRef fmask_word1 =
3434 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3435 ctx->i32_1, "");
3436
3437 LLVMValueRef word1_is_nonzero =
3438 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3439 fmask_word1, ctx->i32_0, "");
3440
3441 /* Replace the MSAA sample index. */
3442 sample_index =
3443 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3444 final_sample, sample_index, "");
3445 return sample_index;
3446 }
3447
3448 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3449 const nir_intrinsic_instr *instr)
3450 {
3451 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3452
3453 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3454 LLVMValueRef coords[4];
3455 LLVMValueRef masks[] = {
3456 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3457 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3458 };
3459 LLVMValueRef res;
3460 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3461
3462 int count;
3463 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3464 bool is_array = glsl_sampler_type_is_array(type);
3465 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3466 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3467 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3468 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3469 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3470 count = image_type_to_components_count(dim, is_array);
3471
3472 if (is_ms) {
3473 LLVMValueRef fmask_load_address[3];
3474 int chan;
3475
3476 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3477 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3478 if (is_array)
3479 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3480 else
3481 fmask_load_address[2] = NULL;
3482 if (add_frag_pos) {
3483 for (chan = 0; chan < 2; ++chan)
3484 fmask_load_address[chan] =
3485 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3486 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3487 ctx->ac.i32, ""), "");
3488 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3489 }
3490 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3491 fmask_load_address[0],
3492 fmask_load_address[1],
3493 fmask_load_address[2],
3494 sample_index,
3495 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3496 }
3497 if (count == 1 && !gfx9_1d) {
3498 if (instr->src[0].ssa->num_components)
3499 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3500 else
3501 res = src0;
3502 } else {
3503 int chan;
3504 if (is_ms)
3505 count--;
3506 for (chan = 0; chan < count; ++chan) {
3507 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3508 }
3509 if (add_frag_pos) {
3510 for (chan = 0; chan < 2; ++chan)
3511 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3512 ctx->ac.i32, ""), "");
3513 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3514 count++;
3515 }
3516
3517 if (gfx9_1d) {
3518 if (is_array) {
3519 coords[2] = coords[1];
3520 coords[1] = ctx->ac.i32_0;
3521 } else
3522 coords[1] = ctx->ac.i32_0;
3523 count++;
3524 }
3525
3526 if (is_ms) {
3527 coords[count] = sample_index;
3528 count++;
3529 }
3530
3531 if (count == 3) {
3532 coords[3] = LLVMGetUndef(ctx->ac.i32);
3533 count = 4;
3534 }
3535 res = ac_build_gather_values(&ctx->ac, coords, count);
3536 }
3537 return res;
3538 }
3539
3540 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3541 const nir_intrinsic_instr *instr)
3542 {
3543 LLVMValueRef params[7];
3544 LLVMValueRef res;
3545 char intrinsic_name[64];
3546 const nir_variable *var = instr->variables[0]->var;
3547 const struct glsl_type *type = var->type;
3548
3549 if(instr->variables[0]->deref.child)
3550 type = instr->variables[0]->deref.child->type;
3551
3552 type = glsl_without_array(type);
3553
3554 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3555 if (dim == GLSL_SAMPLER_DIM_BUF) {
3556 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3557 unsigned num_channels = util_last_bit(mask);
3558 LLVMValueRef rsrc, vindex;
3559
3560 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3561 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3562 ctx->ac.i32_0, "");
3563
3564 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3565 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3566 ctx->ac.i32_0, num_channels,
3567 false, false);
3568 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3569
3570 res = ac_trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3571 res = ac_to_integer(&ctx->ac, res);
3572 } else {
3573 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3574 LLVMValueRef slc = ctx->ac.i1false;
3575
3576 params[0] = get_image_coords(ctx, instr);
3577 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3578 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3579 params[3] = (var->data.image._volatile || var->data.image.coherent) ?
3580 ctx->ac.i1true : ctx->ac.i1false;
3581 params[4] = slc;
3582 params[5] = ctx->ac.i1false;
3583 params[6] = da;
3584
3585 ac_get_image_intr_name("llvm.amdgcn.image.load",
3586 ctx->ac.v4f32, /* vdata */
3587 LLVMTypeOf(params[0]), /* coords */
3588 LLVMTypeOf(params[1]), /* rsrc */
3589 intrinsic_name, sizeof(intrinsic_name));
3590
3591 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3592 params, 7, AC_FUNC_ATTR_READONLY);
3593 }
3594 return ac_to_integer(&ctx->ac, res);
3595 }
3596
3597 static void visit_image_store(struct ac_nir_context *ctx,
3598 nir_intrinsic_instr *instr)
3599 {
3600 LLVMValueRef params[8];
3601 char intrinsic_name[64];
3602 const nir_variable *var = instr->variables[0]->var;
3603 const struct glsl_type *type = glsl_without_array(var->type);
3604 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3605 LLVMValueRef glc = ctx->ac.i1false;
3606 bool force_glc = ctx->ac.chip_class == SI;
3607 if (force_glc)
3608 glc = ctx->ac.i1true;
3609
3610 if (dim == GLSL_SAMPLER_DIM_BUF) {
3611 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3612 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3613 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3614 ctx->ac.i32_0, ""); /* vindex */
3615 params[3] = ctx->ac.i32_0; /* voffset */
3616 params[4] = glc; /* glc */
3617 params[5] = ctx->ac.i1false; /* slc */
3618 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3619 params, 6, 0);
3620 } else {
3621 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3622 LLVMValueRef slc = ctx->ac.i1false;
3623
3624 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3625 params[1] = get_image_coords(ctx, instr); /* coords */
3626 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3627 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3628 params[4] = (force_glc || var->data.image._volatile || var->data.image.coherent) ?
3629 ctx->ac.i1true : ctx->ac.i1false;
3630 params[5] = slc;
3631 params[6] = ctx->ac.i1false;
3632 params[7] = da;
3633
3634 ac_get_image_intr_name("llvm.amdgcn.image.store",
3635 LLVMTypeOf(params[0]), /* vdata */
3636 LLVMTypeOf(params[1]), /* coords */
3637 LLVMTypeOf(params[2]), /* rsrc */
3638 intrinsic_name, sizeof(intrinsic_name));
3639
3640 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3641 params, 8, 0);
3642 }
3643
3644 }
3645
3646 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3647 const nir_intrinsic_instr *instr)
3648 {
3649 LLVMValueRef params[7];
3650 int param_count = 0;
3651 const nir_variable *var = instr->variables[0]->var;
3652
3653 const char *atomic_name;
3654 char intrinsic_name[41];
3655 const struct glsl_type *type = glsl_without_array(var->type);
3656 MAYBE_UNUSED int length;
3657
3658 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3659
3660 switch (instr->intrinsic) {
3661 case nir_intrinsic_image_atomic_add:
3662 atomic_name = "add";
3663 break;
3664 case nir_intrinsic_image_atomic_min:
3665 atomic_name = is_unsigned ? "umin" : "smin";
3666 break;
3667 case nir_intrinsic_image_atomic_max:
3668 atomic_name = is_unsigned ? "umax" : "smax";
3669 break;
3670 case nir_intrinsic_image_atomic_and:
3671 atomic_name = "and";
3672 break;
3673 case nir_intrinsic_image_atomic_or:
3674 atomic_name = "or";
3675 break;
3676 case nir_intrinsic_image_atomic_xor:
3677 atomic_name = "xor";
3678 break;
3679 case nir_intrinsic_image_atomic_exchange:
3680 atomic_name = "swap";
3681 break;
3682 case nir_intrinsic_image_atomic_comp_swap:
3683 atomic_name = "cmpswap";
3684 break;
3685 default:
3686 abort();
3687 }
3688
3689 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3690 params[param_count++] = get_src(ctx, instr->src[3]);
3691 params[param_count++] = get_src(ctx, instr->src[2]);
3692
3693 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3694 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3695 NULL, true, true);
3696 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3697 ctx->ac.i32_0, ""); /* vindex */
3698 params[param_count++] = ctx->ac.i32_0; /* voffset */
3699 params[param_count++] = ctx->ac.i1false; /* slc */
3700
3701 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3702 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3703 } else {
3704 char coords_type[8];
3705
3706 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3707 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3708 NULL, true, true);
3709 params[param_count++] = ctx->ac.i1false; /* r128 */
3710 params[param_count++] = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3711 params[param_count++] = ctx->ac.i1false; /* slc */
3712
3713 build_int_type_name(LLVMTypeOf(coords),
3714 coords_type, sizeof(coords_type));
3715
3716 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3717 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3718 }
3719
3720 assert(length < sizeof(intrinsic_name));
3721 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3722 }
3723
3724 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3725 const nir_intrinsic_instr *instr)
3726 {
3727 const nir_variable *var = instr->variables[0]->var;
3728 const struct glsl_type *type = glsl_without_array(var->type);
3729
3730 struct ac_image_args args = { 0 };
3731 args.da = glsl_is_array_image(type);
3732 args.dmask = 0xf;
3733 args.resource = get_sampler_desc(ctx, instr->variables[0],
3734 AC_DESC_IMAGE, NULL, true, false);
3735 args.opcode = ac_image_get_resinfo;
3736 args.addr = ctx->ac.i32_0;
3737
3738 return ac_build_image_opcode(&ctx->ac, &args);
3739 }
3740
3741 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3742 const nir_intrinsic_instr *instr)
3743 {
3744 LLVMValueRef res;
3745 const nir_variable *var = instr->variables[0]->var;
3746 const struct glsl_type *type = glsl_without_array(var->type);
3747
3748 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3749 return get_buffer_size(ctx,
3750 get_sampler_desc(ctx, instr->variables[0],
3751 AC_DESC_BUFFER, NULL, true, false), true);
3752
3753 struct ac_image_args args = { 0 };
3754
3755 args.da = glsl_is_array_image(type);
3756 args.dmask = 0xf;
3757 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3758 args.opcode = ac_image_get_resinfo;
3759 args.addr = ctx->ac.i32_0;
3760
3761 res = ac_build_image_opcode(&ctx->ac, &args);
3762
3763 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3764
3765 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3766 glsl_sampler_type_is_array(type)) {
3767 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3768 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3769 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3770 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3771 }
3772 if (ctx->ac.chip_class >= GFX9 &&
3773 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3774 glsl_sampler_type_is_array(type)) {
3775 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3776 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3777 ctx->ac.i32_1, "");
3778
3779 }
3780 return res;
3781 }
3782
3783 #define NOOP_WAITCNT 0xf7f
3784 #define LGKM_CNT 0x07f
3785 #define VM_CNT 0xf70
3786
3787 static void emit_membar(struct ac_llvm_context *ac,
3788 const nir_intrinsic_instr *instr)
3789 {
3790 unsigned waitcnt = NOOP_WAITCNT;
3791
3792 switch (instr->intrinsic) {
3793 case nir_intrinsic_memory_barrier:
3794 case nir_intrinsic_group_memory_barrier:
3795 waitcnt &= VM_CNT & LGKM_CNT;
3796 break;
3797 case nir_intrinsic_memory_barrier_atomic_counter:
3798 case nir_intrinsic_memory_barrier_buffer:
3799 case nir_intrinsic_memory_barrier_image:
3800 waitcnt &= VM_CNT;
3801 break;
3802 case nir_intrinsic_memory_barrier_shared:
3803 waitcnt &= LGKM_CNT;
3804 break;
3805 default:
3806 break;
3807 }
3808 if (waitcnt != NOOP_WAITCNT)
3809 ac_build_waitcnt(ac, waitcnt);
3810 }
3811
3812 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3813 {
3814 /* SI only (thanks to a hw bug workaround):
3815 * The real barrier instruction isn’t needed, because an entire patch
3816 * always fits into a single wave.
3817 */
3818 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3819 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3820 return;
3821 }
3822 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3823 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3824 }
3825
3826 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
3827 {
3828 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3829 ac_build_kill_if_false(&ctx->ac, visible);
3830 }
3831
3832 static void emit_discard(struct ac_nir_context *ctx,
3833 const nir_intrinsic_instr *instr)
3834 {
3835 LLVMValueRef cond;
3836
3837 if (instr->intrinsic == nir_intrinsic_discard_if) {
3838 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3839 get_src(ctx, instr->src[0]),
3840 ctx->ac.i32_0, "");
3841 } else {
3842 assert(instr->intrinsic == nir_intrinsic_discard);
3843 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3844 }
3845
3846 ctx->abi->emit_kill(ctx->abi, cond);
3847 }
3848
3849 static LLVMValueRef
3850 visit_load_helper_invocation(struct ac_nir_context *ctx)
3851 {
3852 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3853 "llvm.amdgcn.ps.live",
3854 ctx->ac.i1, NULL, 0,
3855 AC_FUNC_ATTR_READNONE);
3856 result = LLVMBuildNot(ctx->ac.builder, result, "");
3857 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3858 }
3859
3860 static LLVMValueRef
3861 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3862 {
3863 LLVMValueRef result;
3864 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3865 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3866 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3867
3868 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3869 }
3870
3871 static LLVMValueRef
3872 visit_load_subgroup_id(struct ac_nir_context *ctx)
3873 {
3874 if (ctx->stage == MESA_SHADER_COMPUTE) {
3875 LLVMValueRef result;
3876 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3877 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3878 return LLVMBuildLShr(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 6, false), "");
3879 } else {
3880 return LLVMConstInt(ctx->ac.i32, 0, false);
3881 }
3882 }
3883
3884 static LLVMValueRef
3885 visit_load_num_subgroups(struct ac_nir_context *ctx)
3886 {
3887 if (ctx->stage == MESA_SHADER_COMPUTE) {
3888 return LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3889 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
3890 } else {
3891 return LLVMConstInt(ctx->ac.i32, 1, false);
3892 }
3893 }
3894
3895 static LLVMValueRef
3896 visit_first_invocation(struct ac_nir_context *ctx)
3897 {
3898 LLVMValueRef active_set = ac_build_ballot(&ctx->ac, ctx->ac.i32_1);
3899
3900 /* The second argument is whether cttz(0) should be defined, but we do not care. */
3901 LLVMValueRef args[] = {active_set, LLVMConstInt(ctx->ac.i1, 0, false)};
3902 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3903 "llvm.cttz.i64",
3904 ctx->ac.i64, args, 2,
3905 AC_FUNC_ATTR_NOUNWIND |
3906 AC_FUNC_ATTR_READNONE);
3907
3908 return LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
3909 }
3910
3911 static LLVMValueRef
3912 visit_load_shared(struct ac_nir_context *ctx,
3913 const nir_intrinsic_instr *instr)
3914 {
3915 LLVMValueRef values[4], derived_ptr, index, ret;
3916
3917 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3918
3919 for (int chan = 0; chan < instr->num_components; chan++) {
3920 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3921 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3922 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3923 }
3924
3925 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3926 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3927 }
3928
3929 static void
3930 visit_store_shared(struct ac_nir_context *ctx,
3931 const nir_intrinsic_instr *instr)
3932 {
3933 LLVMValueRef derived_ptr, data,index;
3934 LLVMBuilderRef builder = ctx->ac.builder;
3935
3936 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3937 LLVMValueRef src = get_src(ctx, instr->src[0]);
3938
3939 int writemask = nir_intrinsic_write_mask(instr);
3940 for (int chan = 0; chan < 4; chan++) {
3941 if (!(writemask & (1 << chan))) {
3942 continue;
3943 }
3944 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3945 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3946 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3947 LLVMBuildStore(builder, data, derived_ptr);
3948 }
3949 }
3950
3951 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3952 const nir_intrinsic_instr *instr,
3953 LLVMValueRef ptr, int src_idx)
3954 {
3955 LLVMValueRef result;
3956 LLVMValueRef src = get_src(ctx, instr->src[src_idx]);
3957
3958 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3959 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3960 LLVMValueRef src1 = get_src(ctx, instr->src[src_idx + 1]);
3961 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3962 ptr, src, src1,
3963 LLVMAtomicOrderingSequentiallyConsistent,
3964 LLVMAtomicOrderingSequentiallyConsistent,
3965 false);
3966 } else {
3967 LLVMAtomicRMWBinOp op;
3968 switch (instr->intrinsic) {
3969 case nir_intrinsic_var_atomic_add:
3970 case nir_intrinsic_shared_atomic_add:
3971 op = LLVMAtomicRMWBinOpAdd;
3972 break;
3973 case nir_intrinsic_var_atomic_umin:
3974 case nir_intrinsic_shared_atomic_umin:
3975 op = LLVMAtomicRMWBinOpUMin;
3976 break;
3977 case nir_intrinsic_var_atomic_umax:
3978 case nir_intrinsic_shared_atomic_umax:
3979 op = LLVMAtomicRMWBinOpUMax;
3980 break;
3981 case nir_intrinsic_var_atomic_imin:
3982 case nir_intrinsic_shared_atomic_imin:
3983 op = LLVMAtomicRMWBinOpMin;
3984 break;
3985 case nir_intrinsic_var_atomic_imax:
3986 case nir_intrinsic_shared_atomic_imax:
3987 op = LLVMAtomicRMWBinOpMax;
3988 break;
3989 case nir_intrinsic_var_atomic_and:
3990 case nir_intrinsic_shared_atomic_and:
3991 op = LLVMAtomicRMWBinOpAnd;
3992 break;
3993 case nir_intrinsic_var_atomic_or:
3994 case nir_intrinsic_shared_atomic_or:
3995 op = LLVMAtomicRMWBinOpOr;
3996 break;
3997 case nir_intrinsic_var_atomic_xor:
3998 case nir_intrinsic_shared_atomic_xor:
3999 op = LLVMAtomicRMWBinOpXor;
4000 break;
4001 case nir_intrinsic_var_atomic_exchange:
4002 case nir_intrinsic_shared_atomic_exchange:
4003 op = LLVMAtomicRMWBinOpXchg;
4004 break;
4005 default:
4006 return NULL;
4007 }
4008
4009 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4010 LLVMAtomicOrderingSequentiallyConsistent,
4011 false);
4012 }
4013 return result;
4014 }
4015
4016 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4017 enum glsl_interp_mode interp, unsigned location)
4018 {
4019 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4020
4021 switch (interp) {
4022 case INTERP_MODE_FLAT:
4023 default:
4024 return NULL;
4025 case INTERP_MODE_SMOOTH:
4026 case INTERP_MODE_NONE:
4027 if (location == INTERP_CENTER)
4028 return ctx->persp_center;
4029 else if (location == INTERP_CENTROID)
4030 return ctx->persp_centroid;
4031 else if (location == INTERP_SAMPLE)
4032 return ctx->persp_sample;
4033 break;
4034 case INTERP_MODE_NOPERSPECTIVE:
4035 if (location == INTERP_CENTER)
4036 return ctx->linear_center;
4037 else if (location == INTERP_CENTROID)
4038 return ctx->linear_centroid;
4039 else if (location == INTERP_SAMPLE)
4040 return ctx->linear_sample;
4041 break;
4042 }
4043 return NULL;
4044 }
4045
4046 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4047 LLVMValueRef sample_id)
4048 {
4049 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4050
4051 LLVMValueRef result;
4052 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4053
4054 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4055 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4056
4057 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4058 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4059
4060 return result;
4061 }
4062
4063 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4064 {
4065 LLVMValueRef values[2];
4066 LLVMValueRef pos[2];
4067
4068 pos[0] = ac_to_float(&ctx->ac, ctx->abi->frag_pos[0]);
4069 pos[1] = ac_to_float(&ctx->ac, ctx->abi->frag_pos[1]);
4070
4071 values[0] = ac_build_fract(&ctx->ac, pos[0], 32);
4072 values[1] = ac_build_fract(&ctx->ac, pos[1], 32);
4073 return ac_build_gather_values(&ctx->ac, values, 2);
4074 }
4075
4076 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4077 {
4078 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4079 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4080 ctx->options->key.fs.log2_num_samples :
4081 ctx->options->key.fs.log2_ps_iter_samples;
4082
4083 /* The bit pattern matches that used by fixed function fragment
4084 * processing. */
4085 static const uint16_t ps_iter_masks[] = {
4086 0xffff, /* not used */
4087 0x5555,
4088 0x1111,
4089 0x0101,
4090 0x0001,
4091 };
4092 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4093
4094 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4095
4096 LLVMValueRef result, sample_id;
4097 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4098 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4099 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4100 return result;
4101 }
4102
4103 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4104 const nir_intrinsic_instr *instr)
4105 {
4106 LLVMValueRef result[4];
4107 LLVMValueRef interp_param, attr_number;
4108 unsigned location;
4109 unsigned chan;
4110 LLVMValueRef src_c0 = NULL;
4111 LLVMValueRef src_c1 = NULL;
4112 LLVMValueRef src0 = NULL;
4113 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4114 switch (instr->intrinsic) {
4115 case nir_intrinsic_interp_var_at_centroid:
4116 location = INTERP_CENTROID;
4117 break;
4118 case nir_intrinsic_interp_var_at_sample:
4119 case nir_intrinsic_interp_var_at_offset:
4120 location = INTERP_CENTER;
4121 src0 = get_src(ctx, instr->src[0]);
4122 break;
4123 default:
4124 break;
4125 }
4126
4127 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4128 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4129 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4130 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4131 LLVMValueRef sample_position;
4132 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4133
4134 /* fetch sample ID */
4135 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4136
4137 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4138 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4139 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4140 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4141 }
4142 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4143 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4144
4145 if (location == INTERP_CENTER) {
4146 LLVMValueRef ij_out[2];
4147 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4148
4149 /*
4150 * take the I then J parameters, and the DDX/Y for it, and
4151 * calculate the IJ inputs for the interpolator.
4152 * temp1 = ddx * offset/sample.x + I;
4153 * interp_param.I = ddy * offset/sample.y + temp1;
4154 * temp1 = ddx * offset/sample.x + J;
4155 * interp_param.J = ddy * offset/sample.y + temp1;
4156 */
4157 for (unsigned i = 0; i < 2; i++) {
4158 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4159 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4160 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4161 ddxy_out, ix_ll, "");
4162 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4163 ddxy_out, iy_ll, "");
4164 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4165 interp_param, ix_ll, "");
4166 LLVMValueRef temp1, temp2;
4167
4168 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4169 ctx->ac.f32, "");
4170
4171 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4172 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4173
4174 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4175 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4176
4177 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4178 temp2, ctx->ac.i32, "");
4179 }
4180 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4181
4182 }
4183
4184 for (chan = 0; chan < 4; chan++) {
4185 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4186
4187 if (interp_param) {
4188 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4189 interp_param, ctx->ac.v2f32, "");
4190 LLVMValueRef i = LLVMBuildExtractElement(
4191 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4192 LLVMValueRef j = LLVMBuildExtractElement(
4193 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4194
4195 result[chan] = ac_build_fs_interp(&ctx->ac,
4196 llvm_chan, attr_number,
4197 ctx->abi->prim_mask, i, j);
4198 } else {
4199 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4200 LLVMConstInt(ctx->ac.i32, 2, false),
4201 llvm_chan, attr_number,
4202 ctx->abi->prim_mask);
4203 }
4204 }
4205 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4206 instr->variables[0]->var->data.location_frac);
4207 }
4208
4209 static void
4210 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4211 {
4212 LLVMValueRef gs_next_vertex;
4213 LLVMValueRef can_emit;
4214 int idx;
4215 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4216
4217 assert(stream == 0);
4218
4219 /* Write vertex attribute values to GSVS ring */
4220 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4221 ctx->gs_next_vertex,
4222 "");
4223
4224 /* If this thread has already emitted the declared maximum number of
4225 * vertices, kill it: excessive vertex emissions are not supposed to
4226 * have any effect, and GS threads have no externally observable
4227 * effects other than emitting vertices.
4228 */
4229 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4230 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4231 ac_build_kill_if_false(&ctx->ac, can_emit);
4232
4233 /* loop num outputs */
4234 idx = 0;
4235 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4236 LLVMValueRef *out_ptr = &addrs[i * 4];
4237 int length = 4;
4238 int slot = idx;
4239 int slot_inc = 1;
4240
4241 if (!(ctx->output_mask & (1ull << i)))
4242 continue;
4243
4244 if (i == VARYING_SLOT_CLIP_DIST0) {
4245 /* pack clip and cull into a single set of slots */
4246 length = ctx->num_output_clips + ctx->num_output_culls;
4247 if (length > 4)
4248 slot_inc = 2;
4249 }
4250 for (unsigned j = 0; j < length; j++) {
4251 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4252 out_ptr[j], "");
4253 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4254 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4255 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4256
4257 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4258
4259 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4260 out_val, 1,
4261 voffset, ctx->gs2vs_offset, 0,
4262 1, 1, true, true);
4263 }
4264 idx += slot_inc;
4265 }
4266
4267 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4268 ctx->ac.i32_1, "");
4269 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4270
4271 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4272 }
4273
4274 static void
4275 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4276 {
4277 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4278 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4279 }
4280
4281 static LLVMValueRef
4282 load_tess_coord(struct ac_shader_abi *abi)
4283 {
4284 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4285
4286 LLVMValueRef coord[4] = {
4287 ctx->tes_u,
4288 ctx->tes_v,
4289 ctx->ac.f32_0,
4290 ctx->ac.f32_0,
4291 };
4292
4293 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4294 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4295 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4296
4297 return ac_build_gather_values(&ctx->ac, coord, 3);
4298 }
4299
4300 static LLVMValueRef
4301 load_patch_vertices_in(struct ac_shader_abi *abi)
4302 {
4303 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4304 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4305 }
4306
4307 static void visit_intrinsic(struct ac_nir_context *ctx,
4308 nir_intrinsic_instr *instr)
4309 {
4310 LLVMValueRef result = NULL;
4311
4312 switch (instr->intrinsic) {
4313 case nir_intrinsic_ballot:
4314 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4315 break;
4316 case nir_intrinsic_read_invocation:
4317 case nir_intrinsic_read_first_invocation: {
4318 LLVMValueRef args[2];
4319
4320 /* Value */
4321 args[0] = get_src(ctx, instr->src[0]);
4322
4323 unsigned num_args;
4324 const char *intr_name;
4325 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4326 num_args = 2;
4327 intr_name = "llvm.amdgcn.readlane";
4328
4329 /* Invocation */
4330 args[1] = get_src(ctx, instr->src[1]);
4331 } else {
4332 num_args = 1;
4333 intr_name = "llvm.amdgcn.readfirstlane";
4334 }
4335
4336 /* We currently have no other way to prevent LLVM from lifting the icmp
4337 * calls to a dominating basic block.
4338 */
4339 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4340
4341 result = ac_build_intrinsic(&ctx->ac, intr_name,
4342 ctx->ac.i32, args, num_args,
4343 AC_FUNC_ATTR_READNONE |
4344 AC_FUNC_ATTR_CONVERGENT);
4345 break;
4346 }
4347 case nir_intrinsic_load_subgroup_invocation:
4348 result = ac_get_thread_id(&ctx->ac);
4349 break;
4350 case nir_intrinsic_load_work_group_id: {
4351 LLVMValueRef values[3];
4352
4353 for (int i = 0; i < 3; i++) {
4354 values[i] = ctx->abi->workgroup_ids[i] ?
4355 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4356 }
4357
4358 result = ac_build_gather_values(&ctx->ac, values, 3);
4359 break;
4360 }
4361 case nir_intrinsic_load_base_vertex: {
4362 result = ctx->abi->load_base_vertex(ctx->abi);
4363 break;
4364 }
4365 case nir_intrinsic_load_local_group_size:
4366 result = ctx->abi->load_local_group_size(ctx->abi);
4367 break;
4368 case nir_intrinsic_load_vertex_id:
4369 result = LLVMBuildAdd(ctx->ac.builder, ctx->abi->vertex_id,
4370 ctx->abi->base_vertex, "");
4371 break;
4372 case nir_intrinsic_load_vertex_id_zero_base: {
4373 result = ctx->abi->vertex_id;
4374 break;
4375 }
4376 case nir_intrinsic_load_local_invocation_id: {
4377 result = ctx->abi->local_invocation_ids;
4378 break;
4379 }
4380 case nir_intrinsic_load_base_instance:
4381 result = ctx->abi->start_instance;
4382 break;
4383 case nir_intrinsic_load_draw_id:
4384 result = ctx->abi->draw_id;
4385 break;
4386 case nir_intrinsic_load_view_index:
4387 result = ctx->abi->view_index;
4388 break;
4389 case nir_intrinsic_load_invocation_id:
4390 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4391 result = ac_unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4392 else
4393 result = ctx->abi->gs_invocation_id;
4394 break;
4395 case nir_intrinsic_load_primitive_id:
4396 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4397 result = ctx->abi->gs_prim_id;
4398 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4399 result = ctx->abi->tcs_patch_id;
4400 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4401 result = ctx->abi->tes_patch_id;
4402 } else
4403 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4404 break;
4405 case nir_intrinsic_load_sample_id:
4406 result = ac_unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4407 break;
4408 case nir_intrinsic_load_sample_pos:
4409 result = load_sample_pos(ctx);
4410 break;
4411 case nir_intrinsic_load_sample_mask_in:
4412 result = ctx->abi->load_sample_mask_in(ctx->abi);
4413 break;
4414 case nir_intrinsic_load_frag_coord: {
4415 LLVMValueRef values[4] = {
4416 ctx->abi->frag_pos[0],
4417 ctx->abi->frag_pos[1],
4418 ctx->abi->frag_pos[2],
4419 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4420 };
4421 result = ac_build_gather_values(&ctx->ac, values, 4);
4422 break;
4423 }
4424 case nir_intrinsic_load_front_face:
4425 result = ctx->abi->front_face;
4426 break;
4427 case nir_intrinsic_load_helper_invocation:
4428 result = visit_load_helper_invocation(ctx);
4429 break;
4430 case nir_intrinsic_load_instance_id:
4431 result = ctx->abi->instance_id;
4432 break;
4433 case nir_intrinsic_load_num_work_groups:
4434 result = ctx->abi->num_work_groups;
4435 break;
4436 case nir_intrinsic_load_local_invocation_index:
4437 result = visit_load_local_invocation_index(ctx);
4438 break;
4439 case nir_intrinsic_load_subgroup_id:
4440 result = visit_load_subgroup_id(ctx);
4441 break;
4442 case nir_intrinsic_load_num_subgroups:
4443 result = visit_load_num_subgroups(ctx);
4444 break;
4445 case nir_intrinsic_first_invocation:
4446 result = visit_first_invocation(ctx);
4447 break;
4448 case nir_intrinsic_load_push_constant:
4449 result = visit_load_push_constant(ctx, instr);
4450 break;
4451 case nir_intrinsic_vulkan_resource_index: {
4452 LLVMValueRef index = get_src(ctx, instr->src[0]);
4453 unsigned desc_set = nir_intrinsic_desc_set(instr);
4454 unsigned binding = nir_intrinsic_binding(instr);
4455
4456 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4457 binding);
4458 break;
4459 }
4460 case nir_intrinsic_vulkan_resource_reindex:
4461 result = visit_vulkan_resource_reindex(ctx, instr);
4462 break;
4463 case nir_intrinsic_store_ssbo:
4464 visit_store_ssbo(ctx, instr);
4465 break;
4466 case nir_intrinsic_load_ssbo:
4467 result = visit_load_buffer(ctx, instr);
4468 break;
4469 case nir_intrinsic_ssbo_atomic_add:
4470 case nir_intrinsic_ssbo_atomic_imin:
4471 case nir_intrinsic_ssbo_atomic_umin:
4472 case nir_intrinsic_ssbo_atomic_imax:
4473 case nir_intrinsic_ssbo_atomic_umax:
4474 case nir_intrinsic_ssbo_atomic_and:
4475 case nir_intrinsic_ssbo_atomic_or:
4476 case nir_intrinsic_ssbo_atomic_xor:
4477 case nir_intrinsic_ssbo_atomic_exchange:
4478 case nir_intrinsic_ssbo_atomic_comp_swap:
4479 result = visit_atomic_ssbo(ctx, instr);
4480 break;
4481 case nir_intrinsic_load_ubo:
4482 result = visit_load_ubo_buffer(ctx, instr);
4483 break;
4484 case nir_intrinsic_get_buffer_size:
4485 result = visit_get_buffer_size(ctx, instr);
4486 break;
4487 case nir_intrinsic_load_var:
4488 result = visit_load_var(ctx, instr);
4489 break;
4490 case nir_intrinsic_store_var:
4491 visit_store_var(ctx, instr);
4492 break;
4493 case nir_intrinsic_load_shared:
4494 result = visit_load_shared(ctx, instr);
4495 break;
4496 case nir_intrinsic_store_shared:
4497 visit_store_shared(ctx, instr);
4498 break;
4499 case nir_intrinsic_image_samples:
4500 result = visit_image_samples(ctx, instr);
4501 break;
4502 case nir_intrinsic_image_load:
4503 result = visit_image_load(ctx, instr);
4504 break;
4505 case nir_intrinsic_image_store:
4506 visit_image_store(ctx, instr);
4507 break;
4508 case nir_intrinsic_image_atomic_add:
4509 case nir_intrinsic_image_atomic_min:
4510 case nir_intrinsic_image_atomic_max:
4511 case nir_intrinsic_image_atomic_and:
4512 case nir_intrinsic_image_atomic_or:
4513 case nir_intrinsic_image_atomic_xor:
4514 case nir_intrinsic_image_atomic_exchange:
4515 case nir_intrinsic_image_atomic_comp_swap:
4516 result = visit_image_atomic(ctx, instr);
4517 break;
4518 case nir_intrinsic_image_size:
4519 result = visit_image_size(ctx, instr);
4520 break;
4521 case nir_intrinsic_shader_clock:
4522 result = ac_build_shader_clock(&ctx->ac);
4523 break;
4524 case nir_intrinsic_discard:
4525 case nir_intrinsic_discard_if:
4526 emit_discard(ctx, instr);
4527 break;
4528 case nir_intrinsic_memory_barrier:
4529 case nir_intrinsic_group_memory_barrier:
4530 case nir_intrinsic_memory_barrier_atomic_counter:
4531 case nir_intrinsic_memory_barrier_buffer:
4532 case nir_intrinsic_memory_barrier_image:
4533 case nir_intrinsic_memory_barrier_shared:
4534 emit_membar(&ctx->ac, instr);
4535 break;
4536 case nir_intrinsic_barrier:
4537 emit_barrier(&ctx->ac, ctx->stage);
4538 break;
4539 case nir_intrinsic_shared_atomic_add:
4540 case nir_intrinsic_shared_atomic_imin:
4541 case nir_intrinsic_shared_atomic_umin:
4542 case nir_intrinsic_shared_atomic_imax:
4543 case nir_intrinsic_shared_atomic_umax:
4544 case nir_intrinsic_shared_atomic_and:
4545 case nir_intrinsic_shared_atomic_or:
4546 case nir_intrinsic_shared_atomic_xor:
4547 case nir_intrinsic_shared_atomic_exchange:
4548 case nir_intrinsic_shared_atomic_comp_swap: {
4549 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
4550 result = visit_var_atomic(ctx, instr, ptr, 1);
4551 break;
4552 }
4553 case nir_intrinsic_var_atomic_add:
4554 case nir_intrinsic_var_atomic_imin:
4555 case nir_intrinsic_var_atomic_umin:
4556 case nir_intrinsic_var_atomic_imax:
4557 case nir_intrinsic_var_atomic_umax:
4558 case nir_intrinsic_var_atomic_and:
4559 case nir_intrinsic_var_atomic_or:
4560 case nir_intrinsic_var_atomic_xor:
4561 case nir_intrinsic_var_atomic_exchange:
4562 case nir_intrinsic_var_atomic_comp_swap: {
4563 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4564 result = visit_var_atomic(ctx, instr, ptr, 0);
4565 break;
4566 }
4567 case nir_intrinsic_interp_var_at_centroid:
4568 case nir_intrinsic_interp_var_at_sample:
4569 case nir_intrinsic_interp_var_at_offset:
4570 result = visit_interp(ctx, instr);
4571 break;
4572 case nir_intrinsic_emit_vertex:
4573 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4574 break;
4575 case nir_intrinsic_end_primitive:
4576 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4577 break;
4578 case nir_intrinsic_load_tess_coord:
4579 result = ctx->abi->load_tess_coord(ctx->abi);
4580 break;
4581 case nir_intrinsic_load_tess_level_outer:
4582 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4583 break;
4584 case nir_intrinsic_load_tess_level_inner:
4585 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4586 break;
4587 case nir_intrinsic_load_patch_vertices_in:
4588 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4589 break;
4590 case nir_intrinsic_vote_all: {
4591 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4592 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4593 break;
4594 }
4595 case nir_intrinsic_vote_any: {
4596 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4597 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4598 break;
4599 }
4600 default:
4601 fprintf(stderr, "Unknown intrinsic: ");
4602 nir_print_instr(&instr->instr, stderr);
4603 fprintf(stderr, "\n");
4604 break;
4605 }
4606 if (result) {
4607 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4608 }
4609 }
4610
4611 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
4612 {
4613 return abi->base_vertex;
4614 }
4615
4616 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4617 LLVMValueRef buffer_ptr, bool write)
4618 {
4619 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4620 LLVMValueRef result;
4621
4622 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4623
4624 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4625 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4626
4627 return result;
4628 }
4629
4630 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4631 {
4632 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4633 LLVMValueRef result;
4634
4635 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4636
4637 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4638 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4639
4640 return result;
4641 }
4642
4643 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4644 unsigned descriptor_set,
4645 unsigned base_index,
4646 unsigned constant_index,
4647 LLVMValueRef index,
4648 enum ac_descriptor_type desc_type,
4649 bool image, bool write)
4650 {
4651 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4652 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4653 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4654 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4655 unsigned offset = binding->offset;
4656 unsigned stride = binding->size;
4657 unsigned type_size;
4658 LLVMBuilderRef builder = ctx->ac.builder;
4659 LLVMTypeRef type;
4660
4661 assert(base_index < layout->binding_count);
4662
4663 switch (desc_type) {
4664 case AC_DESC_IMAGE:
4665 type = ctx->ac.v8i32;
4666 type_size = 32;
4667 break;
4668 case AC_DESC_FMASK:
4669 type = ctx->ac.v8i32;
4670 offset += 32;
4671 type_size = 32;
4672 break;
4673 case AC_DESC_SAMPLER:
4674 type = ctx->ac.v4i32;
4675 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4676 offset += 64;
4677
4678 type_size = 16;
4679 break;
4680 case AC_DESC_BUFFER:
4681 type = ctx->ac.v4i32;
4682 type_size = 16;
4683 break;
4684 default:
4685 unreachable("invalid desc_type\n");
4686 }
4687
4688 offset += constant_index * stride;
4689
4690 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4691 (!index || binding->immutable_samplers_equal)) {
4692 if (binding->immutable_samplers_equal)
4693 constant_index = 0;
4694
4695 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4696
4697 LLVMValueRef constants[] = {
4698 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4699 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4700 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4701 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4702 };
4703 return ac_build_gather_values(&ctx->ac, constants, 4);
4704 }
4705
4706 assert(stride % type_size == 0);
4707
4708 if (!index)
4709 index = ctx->ac.i32_0;
4710
4711 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4712
4713 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4714 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4715
4716 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4717 }
4718
4719 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4720 const nir_deref_var *deref,
4721 enum ac_descriptor_type desc_type,
4722 const nir_tex_instr *tex_instr,
4723 bool image, bool write)
4724 {
4725 LLVMValueRef index = NULL;
4726 unsigned constant_index = 0;
4727 unsigned descriptor_set;
4728 unsigned base_index;
4729
4730 if (!deref) {
4731 assert(tex_instr && !image);
4732 descriptor_set = 0;
4733 base_index = tex_instr->sampler_index;
4734 } else {
4735 const nir_deref *tail = &deref->deref;
4736 while (tail->child) {
4737 const nir_deref_array *child = nir_deref_as_array(tail->child);
4738 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4739
4740 if (!array_size)
4741 array_size = 1;
4742
4743 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4744
4745 if (child->deref_array_type == nir_deref_array_type_indirect) {
4746 LLVMValueRef indirect = get_src(ctx, child->indirect);
4747
4748 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4749 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4750
4751 if (!index)
4752 index = indirect;
4753 else
4754 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4755 }
4756
4757 constant_index += child->base_offset * array_size;
4758
4759 tail = &child->deref;
4760 }
4761 descriptor_set = deref->var->data.descriptor_set;
4762 base_index = deref->var->data.binding;
4763 }
4764
4765 return ctx->abi->load_sampler_desc(ctx->abi,
4766 descriptor_set,
4767 base_index,
4768 constant_index, index,
4769 desc_type, image, write);
4770 }
4771
4772 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4773 struct ac_image_args *args,
4774 const nir_tex_instr *instr,
4775 nir_texop op,
4776 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4777 LLVMValueRef *param, unsigned count,
4778 unsigned dmask)
4779 {
4780 unsigned is_rect = 0;
4781 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4782
4783 if (op == nir_texop_lod)
4784 da = false;
4785 /* Pad to power of two vector */
4786 while (count < util_next_power_of_two(count))
4787 param[count++] = LLVMGetUndef(ctx->i32);
4788
4789 if (count > 1)
4790 args->addr = ac_build_gather_values(ctx, param, count);
4791 else
4792 args->addr = param[0];
4793
4794 args->resource = res_ptr;
4795 args->sampler = samp_ptr;
4796
4797 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4798 args->addr = param[0];
4799 return;
4800 }
4801
4802 args->dmask = dmask;
4803 args->unorm = is_rect;
4804 args->da = da;
4805 }
4806
4807 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4808 *
4809 * SI-CI:
4810 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4811 * filtering manually. The driver sets img7 to a mask clearing
4812 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4813 * s_and_b32 samp0, samp0, img7
4814 *
4815 * VI:
4816 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4817 */
4818 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4819 LLVMValueRef res, LLVMValueRef samp)
4820 {
4821 LLVMBuilderRef builder = ctx->ac.builder;
4822 LLVMValueRef img7, samp0;
4823
4824 if (ctx->ac.chip_class >= VI)
4825 return samp;
4826
4827 img7 = LLVMBuildExtractElement(builder, res,
4828 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4829 samp0 = LLVMBuildExtractElement(builder, samp,
4830 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4831 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4832 return LLVMBuildInsertElement(builder, samp, samp0,
4833 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4834 }
4835
4836 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4837 nir_tex_instr *instr,
4838 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4839 LLVMValueRef *fmask_ptr)
4840 {
4841 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4842 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4843 else
4844 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4845 if (samp_ptr) {
4846 if (instr->sampler)
4847 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4848 else
4849 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4850 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4851 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4852 }
4853 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4854 instr->op == nir_texop_samples_identical))
4855 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4856 }
4857
4858 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4859 LLVMValueRef coord)
4860 {
4861 coord = ac_to_float(ctx, coord);
4862 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4863 coord = ac_to_integer(ctx, coord);
4864 return coord;
4865 }
4866
4867 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4868 {
4869 LLVMValueRef result = NULL;
4870 struct ac_image_args args = { 0 };
4871 unsigned dmask = 0xf;
4872 LLVMValueRef address[16];
4873 LLVMValueRef coords[5];
4874 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4875 LLVMValueRef bias = NULL, offsets = NULL;
4876 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4877 LLVMValueRef ddx = NULL, ddy = NULL;
4878 LLVMValueRef derivs[6];
4879 unsigned chan, count = 0;
4880 unsigned const_src = 0, num_deriv_comp = 0;
4881 bool lod_is_zero = false;
4882
4883 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4884
4885 for (unsigned i = 0; i < instr->num_srcs; i++) {
4886 switch (instr->src[i].src_type) {
4887 case nir_tex_src_coord:
4888 coord = get_src(ctx, instr->src[i].src);
4889 break;
4890 case nir_tex_src_projector:
4891 break;
4892 case nir_tex_src_comparator:
4893 comparator = get_src(ctx, instr->src[i].src);
4894 break;
4895 case nir_tex_src_offset:
4896 offsets = get_src(ctx, instr->src[i].src);
4897 const_src = i;
4898 break;
4899 case nir_tex_src_bias:
4900 bias = get_src(ctx, instr->src[i].src);
4901 break;
4902 case nir_tex_src_lod: {
4903 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4904
4905 if (val && val->i32[0] == 0)
4906 lod_is_zero = true;
4907 lod = get_src(ctx, instr->src[i].src);
4908 break;
4909 }
4910 case nir_tex_src_ms_index:
4911 sample_index = get_src(ctx, instr->src[i].src);
4912 break;
4913 case nir_tex_src_ms_mcs:
4914 break;
4915 case nir_tex_src_ddx:
4916 ddx = get_src(ctx, instr->src[i].src);
4917 num_deriv_comp = instr->src[i].src.ssa->num_components;
4918 break;
4919 case nir_tex_src_ddy:
4920 ddy = get_src(ctx, instr->src[i].src);
4921 break;
4922 case nir_tex_src_texture_offset:
4923 case nir_tex_src_sampler_offset:
4924 case nir_tex_src_plane:
4925 default:
4926 break;
4927 }
4928 }
4929
4930 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4931 result = get_buffer_size(ctx, res_ptr, true);
4932 goto write_result;
4933 }
4934
4935 if (instr->op == nir_texop_texture_samples) {
4936 LLVMValueRef res, samples, is_msaa;
4937 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4938 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4939 LLVMConstInt(ctx->ac.i32, 3, false), "");
4940 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4941 LLVMConstInt(ctx->ac.i32, 28, false), "");
4942 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4943 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4944 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4945 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4946
4947 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4948 LLVMConstInt(ctx->ac.i32, 16, false), "");
4949 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4950 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4951 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4952 samples, "");
4953 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4954 ctx->ac.i32_1, "");
4955 result = samples;
4956 goto write_result;
4957 }
4958
4959 if (coord)
4960 for (chan = 0; chan < instr->coord_components; chan++)
4961 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4962
4963 if (offsets && instr->op != nir_texop_txf) {
4964 LLVMValueRef offset[3], pack;
4965 for (chan = 0; chan < 3; ++chan)
4966 offset[chan] = ctx->ac.i32_0;
4967
4968 args.offset = true;
4969 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4970 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4971 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4972 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4973 if (chan)
4974 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4975 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4976 }
4977 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4978 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4979 address[count++] = pack;
4980
4981 }
4982 /* pack LOD bias value */
4983 if (instr->op == nir_texop_txb && bias) {
4984 address[count++] = bias;
4985 }
4986
4987 /* Pack depth comparison value */
4988 if (instr->is_shadow && comparator) {
4989 LLVMValueRef z = ac_to_float(&ctx->ac,
4990 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4991
4992 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4993 * so the depth comparison value isn't clamped for Z16 and
4994 * Z24 anymore. Do it manually here.
4995 *
4996 * It's unnecessary if the original texture format was
4997 * Z32_FLOAT, but we don't know that here.
4998 */
4999 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5000 z = ac_build_clamp(&ctx->ac, z);
5001
5002 address[count++] = z;
5003 }
5004
5005 /* pack derivatives */
5006 if (ddx || ddy) {
5007 int num_src_deriv_channels, num_dest_deriv_channels;
5008 switch (instr->sampler_dim) {
5009 case GLSL_SAMPLER_DIM_3D:
5010 case GLSL_SAMPLER_DIM_CUBE:
5011 num_deriv_comp = 3;
5012 num_src_deriv_channels = 3;
5013 num_dest_deriv_channels = 3;
5014 break;
5015 case GLSL_SAMPLER_DIM_2D:
5016 default:
5017 num_src_deriv_channels = 2;
5018 num_dest_deriv_channels = 2;
5019 num_deriv_comp = 2;
5020 break;
5021 case GLSL_SAMPLER_DIM_1D:
5022 num_src_deriv_channels = 1;
5023 if (ctx->ac.chip_class >= GFX9) {
5024 num_dest_deriv_channels = 2;
5025 num_deriv_comp = 2;
5026 } else {
5027 num_dest_deriv_channels = 1;
5028 num_deriv_comp = 1;
5029 }
5030 break;
5031 }
5032
5033 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5034 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5035 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5036 }
5037 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5038 derivs[i] = ctx->ac.f32_0;
5039 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5040 }
5041 }
5042
5043 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5044 for (chan = 0; chan < instr->coord_components; chan++)
5045 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5046 if (instr->coord_components == 3)
5047 coords[3] = LLVMGetUndef(ctx->ac.f32);
5048 ac_prepare_cube_coords(&ctx->ac,
5049 instr->op == nir_texop_txd, instr->is_array,
5050 instr->op == nir_texop_lod, coords, derivs);
5051 if (num_deriv_comp)
5052 num_deriv_comp--;
5053 }
5054
5055 if (ddx || ddy) {
5056 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5057 address[count++] = derivs[i];
5058 }
5059
5060 /* Pack texture coordinates */
5061 if (coord) {
5062 address[count++] = coords[0];
5063 if (instr->coord_components > 1) {
5064 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5065 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5066 }
5067 address[count++] = coords[1];
5068 }
5069 if (instr->coord_components > 2) {
5070 if ((instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
5071 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
5072 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
5073 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
5074 instr->is_array &&
5075 instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
5076 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5077 }
5078 address[count++] = coords[2];
5079 }
5080
5081 if (ctx->ac.chip_class >= GFX9) {
5082 LLVMValueRef filler;
5083 if (instr->op == nir_texop_txf)
5084 filler = ctx->ac.i32_0;
5085 else
5086 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5087
5088 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5089 /* No nir_texop_lod, because it does not take a slice
5090 * even with array textures. */
5091 if (instr->is_array && instr->op != nir_texop_lod ) {
5092 address[count] = address[count - 1];
5093 address[count - 1] = filler;
5094 count++;
5095 } else
5096 address[count++] = filler;
5097 }
5098 }
5099 }
5100
5101 /* Pack LOD */
5102 if (lod && ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && !lod_is_zero)) {
5103 address[count++] = lod;
5104 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5105 address[count++] = sample_index;
5106 } else if(instr->op == nir_texop_txs) {
5107 count = 0;
5108 if (lod)
5109 address[count++] = lod;
5110 else
5111 address[count++] = ctx->ac.i32_0;
5112 }
5113
5114 for (chan = 0; chan < count; chan++) {
5115 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5116 address[chan], ctx->ac.i32, "");
5117 }
5118
5119 if (instr->op == nir_texop_samples_identical) {
5120 LLVMValueRef txf_address[4];
5121 struct ac_image_args txf_args = { 0 };
5122 unsigned txf_count = count;
5123 memcpy(txf_address, address, sizeof(txf_address));
5124
5125 if (!instr->is_array)
5126 txf_address[2] = ctx->ac.i32_0;
5127 txf_address[3] = ctx->ac.i32_0;
5128
5129 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5130 fmask_ptr, NULL,
5131 txf_address, txf_count, 0xf);
5132
5133 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5134
5135 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5136 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5137 goto write_result;
5138 }
5139
5140 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5141 instr->op != nir_texop_txs) {
5142 unsigned sample_chan = instr->is_array ? 3 : 2;
5143 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5144 address[0],
5145 address[1],
5146 instr->is_array ? address[2] : NULL,
5147 address[sample_chan],
5148 fmask_ptr);
5149 }
5150
5151 if (offsets && instr->op == nir_texop_txf) {
5152 nir_const_value *const_offset =
5153 nir_src_as_const_value(instr->src[const_src].src);
5154 int num_offsets = instr->src[const_src].src.ssa->num_components;
5155 assert(const_offset);
5156 num_offsets = MIN2(num_offsets, instr->coord_components);
5157 if (num_offsets > 2)
5158 address[2] = LLVMBuildAdd(ctx->ac.builder,
5159 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5160 if (num_offsets > 1)
5161 address[1] = LLVMBuildAdd(ctx->ac.builder,
5162 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5163 address[0] = LLVMBuildAdd(ctx->ac.builder,
5164 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5165
5166 }
5167
5168 /* TODO TG4 support */
5169 if (instr->op == nir_texop_tg4) {
5170 if (instr->is_shadow)
5171 dmask = 1;
5172 else
5173 dmask = 1 << instr->component;
5174 }
5175 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5176 res_ptr, samp_ptr, address, count, dmask);
5177
5178 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5179
5180 if (instr->op == nir_texop_query_levels)
5181 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5182 else if (instr->is_shadow && instr->is_new_style_shadow &&
5183 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5184 instr->op != nir_texop_tg4)
5185 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5186 else if (instr->op == nir_texop_txs &&
5187 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5188 instr->is_array) {
5189 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5190 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5191 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5192 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5193 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5194 } else if (ctx->ac.chip_class >= GFX9 &&
5195 instr->op == nir_texop_txs &&
5196 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5197 instr->is_array) {
5198 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5199 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5200 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5201 ctx->ac.i32_1, "");
5202 } else if (instr->dest.ssa.num_components != 4)
5203 result = ac_trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5204
5205 write_result:
5206 if (result) {
5207 assert(instr->dest.is_ssa);
5208 result = ac_to_integer(&ctx->ac, result);
5209 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5210 }
5211 }
5212
5213
5214 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5215 {
5216 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5217 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5218
5219 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5220 _mesa_hash_table_insert(ctx->phis, instr, result);
5221 }
5222
5223 static void visit_post_phi(struct ac_nir_context *ctx,
5224 nir_phi_instr *instr,
5225 LLVMValueRef llvm_phi)
5226 {
5227 nir_foreach_phi_src(src, instr) {
5228 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5229 LLVMValueRef llvm_src = get_src(ctx, src->src);
5230
5231 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5232 }
5233 }
5234
5235 static void phi_post_pass(struct ac_nir_context *ctx)
5236 {
5237 struct hash_entry *entry;
5238 hash_table_foreach(ctx->phis, entry) {
5239 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5240 (LLVMValueRef)entry->data);
5241 }
5242 }
5243
5244
5245 static void visit_ssa_undef(struct ac_nir_context *ctx,
5246 const nir_ssa_undef_instr *instr)
5247 {
5248 unsigned num_components = instr->def.num_components;
5249 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5250 LLVMValueRef undef;
5251
5252 if (num_components == 1)
5253 undef = LLVMGetUndef(type);
5254 else {
5255 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5256 }
5257 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5258 }
5259
5260 static void visit_jump(struct ac_llvm_context *ctx,
5261 const nir_jump_instr *instr)
5262 {
5263 switch (instr->type) {
5264 case nir_jump_break:
5265 ac_build_break(ctx);
5266 break;
5267 case nir_jump_continue:
5268 ac_build_continue(ctx);
5269 break;
5270 default:
5271 fprintf(stderr, "Unknown NIR jump instr: ");
5272 nir_print_instr(&instr->instr, stderr);
5273 fprintf(stderr, "\n");
5274 abort();
5275 }
5276 }
5277
5278 static void visit_cf_list(struct ac_nir_context *ctx,
5279 struct exec_list *list);
5280
5281 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5282 {
5283 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5284 nir_foreach_instr(instr, block)
5285 {
5286 switch (instr->type) {
5287 case nir_instr_type_alu:
5288 visit_alu(ctx, nir_instr_as_alu(instr));
5289 break;
5290 case nir_instr_type_load_const:
5291 visit_load_const(ctx, nir_instr_as_load_const(instr));
5292 break;
5293 case nir_instr_type_intrinsic:
5294 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5295 break;
5296 case nir_instr_type_tex:
5297 visit_tex(ctx, nir_instr_as_tex(instr));
5298 break;
5299 case nir_instr_type_phi:
5300 visit_phi(ctx, nir_instr_as_phi(instr));
5301 break;
5302 case nir_instr_type_ssa_undef:
5303 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5304 break;
5305 case nir_instr_type_jump:
5306 visit_jump(&ctx->ac, nir_instr_as_jump(instr));
5307 break;
5308 default:
5309 fprintf(stderr, "Unknown NIR instr type: ");
5310 nir_print_instr(instr, stderr);
5311 fprintf(stderr, "\n");
5312 abort();
5313 }
5314 }
5315
5316 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5317 }
5318
5319 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5320 {
5321 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5322
5323 nir_block *then_block =
5324 (nir_block *) exec_list_get_head(&if_stmt->then_list);
5325
5326 ac_build_uif(&ctx->ac, value, then_block->index);
5327
5328 visit_cf_list(ctx, &if_stmt->then_list);
5329
5330 if (!exec_list_is_empty(&if_stmt->else_list)) {
5331 nir_block *else_block =
5332 (nir_block *) exec_list_get_head(&if_stmt->else_list);
5333
5334 ac_build_else(&ctx->ac, else_block->index);
5335 visit_cf_list(ctx, &if_stmt->else_list);
5336 }
5337
5338 ac_build_endif(&ctx->ac, then_block->index);
5339 }
5340
5341 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5342 {
5343 nir_block *first_loop_block =
5344 (nir_block *) exec_list_get_head(&loop->body);
5345
5346 ac_build_bgnloop(&ctx->ac, first_loop_block->index);
5347
5348 visit_cf_list(ctx, &loop->body);
5349
5350 ac_build_endloop(&ctx->ac, first_loop_block->index);
5351 }
5352
5353 static void visit_cf_list(struct ac_nir_context *ctx,
5354 struct exec_list *list)
5355 {
5356 foreach_list_typed(nir_cf_node, node, node, list)
5357 {
5358 switch (node->type) {
5359 case nir_cf_node_block:
5360 visit_block(ctx, nir_cf_node_as_block(node));
5361 break;
5362
5363 case nir_cf_node_if:
5364 visit_if(ctx, nir_cf_node_as_if(node));
5365 break;
5366
5367 case nir_cf_node_loop:
5368 visit_loop(ctx, nir_cf_node_as_loop(node));
5369 break;
5370
5371 default:
5372 assert(0);
5373 }
5374 }
5375 }
5376
5377 static void
5378 handle_vs_input_decl(struct radv_shader_context *ctx,
5379 struct nir_variable *variable)
5380 {
5381 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5382 LLVMValueRef t_offset;
5383 LLVMValueRef t_list;
5384 LLVMValueRef input;
5385 LLVMValueRef buffer_index;
5386 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5387 int idx = variable->data.location;
5388 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5389 uint8_t input_usage_mask =
5390 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5391 unsigned num_channels = util_last_bit(input_usage_mask);
5392
5393 variable->data.driver_location = idx * 4;
5394
5395 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5396 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5397 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5398 ctx->abi.start_instance, "");
5399 if (ctx->options->key.vs.as_ls) {
5400 ctx->shader_info->vs.vgpr_comp_cnt =
5401 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5402 } else {
5403 ctx->shader_info->vs.vgpr_comp_cnt =
5404 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5405 }
5406 } else
5407 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5408 ctx->abi.base_vertex, "");
5409 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5410
5411 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5412
5413 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5414 buffer_index,
5415 ctx->ac.i32_0,
5416 num_channels, false, true);
5417
5418 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5419
5420 for (unsigned chan = 0; chan < 4; chan++) {
5421 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5422 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5423 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5424 input, llvm_chan, ""));
5425 }
5426 }
5427 }
5428
5429 static void interp_fs_input(struct radv_shader_context *ctx,
5430 unsigned attr,
5431 LLVMValueRef interp_param,
5432 LLVMValueRef prim_mask,
5433 LLVMValueRef result[4])
5434 {
5435 LLVMValueRef attr_number;
5436 unsigned chan;
5437 LLVMValueRef i, j;
5438 bool interp = interp_param != NULL;
5439
5440 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5441
5442 /* fs.constant returns the param from the middle vertex, so it's not
5443 * really useful for flat shading. It's meant to be used for custom
5444 * interpolation (but the intrinsic can't fetch from the other two
5445 * vertices).
5446 *
5447 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5448 * to do the right thing. The only reason we use fs.constant is that
5449 * fs.interp cannot be used on integers, because they can be equal
5450 * to NaN.
5451 */
5452 if (interp) {
5453 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5454 ctx->ac.v2f32, "");
5455
5456 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5457 ctx->ac.i32_0, "");
5458 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5459 ctx->ac.i32_1, "");
5460 }
5461
5462 for (chan = 0; chan < 4; chan++) {
5463 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5464
5465 if (interp) {
5466 result[chan] = ac_build_fs_interp(&ctx->ac,
5467 llvm_chan,
5468 attr_number,
5469 prim_mask, i, j);
5470 } else {
5471 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5472 LLVMConstInt(ctx->ac.i32, 2, false),
5473 llvm_chan,
5474 attr_number,
5475 prim_mask);
5476 }
5477 }
5478 }
5479
5480 static void
5481 handle_fs_input_decl(struct radv_shader_context *ctx,
5482 struct nir_variable *variable)
5483 {
5484 int idx = variable->data.location;
5485 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5486 LLVMValueRef interp;
5487
5488 variable->data.driver_location = idx * 4;
5489 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5490
5491 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5492 unsigned interp_type;
5493 if (variable->data.sample)
5494 interp_type = INTERP_SAMPLE;
5495 else if (variable->data.centroid)
5496 interp_type = INTERP_CENTROID;
5497 else
5498 interp_type = INTERP_CENTER;
5499
5500 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5501 } else
5502 interp = NULL;
5503
5504 for (unsigned i = 0; i < attrib_count; ++i)
5505 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5506
5507 }
5508
5509 static void
5510 handle_vs_inputs(struct radv_shader_context *ctx,
5511 struct nir_shader *nir) {
5512 nir_foreach_variable(variable, &nir->inputs)
5513 handle_vs_input_decl(ctx, variable);
5514 }
5515
5516 static void
5517 prepare_interp_optimize(struct radv_shader_context *ctx,
5518 struct nir_shader *nir)
5519 {
5520 if (!ctx->options->key.fs.multisample)
5521 return;
5522
5523 bool uses_center = false;
5524 bool uses_centroid = false;
5525 nir_foreach_variable(variable, &nir->inputs) {
5526 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5527 variable->data.sample)
5528 continue;
5529
5530 if (variable->data.centroid)
5531 uses_centroid = true;
5532 else
5533 uses_center = true;
5534 }
5535
5536 if (uses_center && uses_centroid) {
5537 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5538 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5539 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5540 }
5541 }
5542
5543 static void
5544 handle_fs_inputs(struct radv_shader_context *ctx,
5545 struct nir_shader *nir)
5546 {
5547 prepare_interp_optimize(ctx, nir);
5548
5549 nir_foreach_variable(variable, &nir->inputs)
5550 handle_fs_input_decl(ctx, variable);
5551
5552 unsigned index = 0;
5553
5554 if (ctx->shader_info->info.ps.uses_input_attachments ||
5555 ctx->shader_info->info.needs_multiview_view_index)
5556 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5557
5558 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5559 LLVMValueRef interp_param;
5560 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5561
5562 if (!(ctx->input_mask & (1ull << i)))
5563 continue;
5564
5565 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5566 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5567 interp_param = *inputs;
5568 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5569 inputs);
5570
5571 if (!interp_param)
5572 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5573 ++index;
5574 } else if (i == VARYING_SLOT_POS) {
5575 for(int i = 0; i < 3; ++i)
5576 inputs[i] = ctx->abi.frag_pos[i];
5577
5578 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5579 ctx->abi.frag_pos[3]);
5580 }
5581 }
5582 ctx->shader_info->fs.num_interp = index;
5583 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5584
5585 if (ctx->shader_info->info.needs_multiview_view_index)
5586 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5587 }
5588
5589 static void
5590 scan_shader_output_decl(struct radv_shader_context *ctx,
5591 struct nir_variable *variable,
5592 struct nir_shader *shader,
5593 gl_shader_stage stage)
5594 {
5595 int idx = variable->data.location + variable->data.index;
5596 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5597 uint64_t mask_attribs;
5598
5599 variable->data.driver_location = idx * 4;
5600
5601 /* tess ctrl has it's own load/store paths for outputs */
5602 if (stage == MESA_SHADER_TESS_CTRL)
5603 return;
5604
5605 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5606 if (stage == MESA_SHADER_VERTEX ||
5607 stage == MESA_SHADER_TESS_EVAL ||
5608 stage == MESA_SHADER_GEOMETRY) {
5609 if (idx == VARYING_SLOT_CLIP_DIST0) {
5610 int length = shader->info.clip_distance_array_size +
5611 shader->info.cull_distance_array_size;
5612 if (stage == MESA_SHADER_VERTEX) {
5613 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5614 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5615 }
5616 if (stage == MESA_SHADER_TESS_EVAL) {
5617 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5618 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5619 }
5620
5621 if (length > 4)
5622 attrib_count = 2;
5623 else
5624 attrib_count = 1;
5625 mask_attribs = 1ull << idx;
5626 }
5627 }
5628
5629 ctx->output_mask |= mask_attribs;
5630 }
5631
5632 void
5633 ac_handle_shader_output_decl(struct ac_llvm_context *ctx,
5634 struct ac_shader_abi *abi,
5635 struct nir_shader *nir,
5636 struct nir_variable *variable,
5637 gl_shader_stage stage)
5638 {
5639 unsigned output_loc = variable->data.driver_location / 4;
5640 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5641
5642 /* tess ctrl has it's own load/store paths for outputs */
5643 if (stage == MESA_SHADER_TESS_CTRL)
5644 return;
5645
5646 if (stage == MESA_SHADER_VERTEX ||
5647 stage == MESA_SHADER_TESS_EVAL ||
5648 stage == MESA_SHADER_GEOMETRY) {
5649 int idx = variable->data.location + variable->data.index;
5650 if (idx == VARYING_SLOT_CLIP_DIST0) {
5651 int length = nir->info.clip_distance_array_size +
5652 nir->info.cull_distance_array_size;
5653
5654 if (length > 4)
5655 attrib_count = 2;
5656 else
5657 attrib_count = 1;
5658 }
5659 }
5660
5661 for (unsigned i = 0; i < attrib_count; ++i) {
5662 for (unsigned chan = 0; chan < 4; chan++) {
5663 abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5664 ac_build_alloca_undef(ctx, ctx->f32, "");
5665 }
5666 }
5667 }
5668
5669 static LLVMTypeRef
5670 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5671 enum glsl_base_type type)
5672 {
5673 switch (type) {
5674 case GLSL_TYPE_INT:
5675 case GLSL_TYPE_UINT:
5676 case GLSL_TYPE_BOOL:
5677 case GLSL_TYPE_SUBROUTINE:
5678 return ac->i32;
5679 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5680 return ac->f32;
5681 case GLSL_TYPE_INT64:
5682 case GLSL_TYPE_UINT64:
5683 return ac->i64;
5684 case GLSL_TYPE_DOUBLE:
5685 return ac->f64;
5686 default:
5687 unreachable("unknown GLSL type");
5688 }
5689 }
5690
5691 static LLVMTypeRef
5692 glsl_to_llvm_type(struct ac_llvm_context *ac,
5693 const struct glsl_type *type)
5694 {
5695 if (glsl_type_is_scalar(type)) {
5696 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5697 }
5698
5699 if (glsl_type_is_vector(type)) {
5700 return LLVMVectorType(
5701 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5702 glsl_get_vector_elements(type));
5703 }
5704
5705 if (glsl_type_is_matrix(type)) {
5706 return LLVMArrayType(
5707 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5708 glsl_get_matrix_columns(type));
5709 }
5710
5711 if (glsl_type_is_array(type)) {
5712 return LLVMArrayType(
5713 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5714 glsl_get_length(type));
5715 }
5716
5717 assert(glsl_type_is_struct(type));
5718
5719 LLVMTypeRef member_types[glsl_get_length(type)];
5720
5721 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5722 member_types[i] =
5723 glsl_to_llvm_type(ac,
5724 glsl_get_struct_field(type, i));
5725 }
5726
5727 return LLVMStructTypeInContext(ac->context, member_types,
5728 glsl_get_length(type), false);
5729 }
5730
5731 static void
5732 setup_locals(struct ac_nir_context *ctx,
5733 struct nir_function *func)
5734 {
5735 int i, j;
5736 ctx->num_locals = 0;
5737 nir_foreach_variable(variable, &func->impl->locals) {
5738 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5739 variable->data.driver_location = ctx->num_locals * 4;
5740 variable->data.location_frac = 0;
5741 ctx->num_locals += attrib_count;
5742 }
5743 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5744 if (!ctx->locals)
5745 return;
5746
5747 for (i = 0; i < ctx->num_locals; i++) {
5748 for (j = 0; j < 4; j++) {
5749 ctx->locals[i * 4 + j] =
5750 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5751 }
5752 }
5753 }
5754
5755 static void
5756 setup_shared(struct ac_nir_context *ctx,
5757 struct nir_shader *nir)
5758 {
5759 nir_foreach_variable(variable, &nir->shared) {
5760 LLVMValueRef shared =
5761 LLVMAddGlobalInAddressSpace(
5762 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5763 variable->name ? variable->name : "",
5764 AC_LOCAL_ADDR_SPACE);
5765 _mesa_hash_table_insert(ctx->vars, variable, shared);
5766 }
5767 }
5768
5769 /* Initialize arguments for the shader export intrinsic */
5770 static void
5771 si_llvm_init_export_args(struct radv_shader_context *ctx,
5772 LLVMValueRef *values,
5773 unsigned enabled_channels,
5774 unsigned target,
5775 struct ac_export_args *args)
5776 {
5777 /* Specify the channels that are enabled. */
5778 args->enabled_channels = enabled_channels;
5779
5780 /* Specify whether the EXEC mask represents the valid mask */
5781 args->valid_mask = 0;
5782
5783 /* Specify whether this is the last export */
5784 args->done = 0;
5785
5786 /* Specify the target we are exporting */
5787 args->target = target;
5788
5789 args->compr = false;
5790 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5791 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5792 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5793 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5794
5795 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5796 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5797 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5798 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5799 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5800 unsigned chan;
5801
5802 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5803 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5804 unsigned bits, bool hi) = NULL;
5805
5806 switch(col_format) {
5807 case V_028714_SPI_SHADER_ZERO:
5808 args->enabled_channels = 0; /* writemask */
5809 args->target = V_008DFC_SQ_EXP_NULL;
5810 break;
5811
5812 case V_028714_SPI_SHADER_32_R:
5813 args->enabled_channels = 1;
5814 args->out[0] = values[0];
5815 break;
5816
5817 case V_028714_SPI_SHADER_32_GR:
5818 args->enabled_channels = 0x3;
5819 args->out[0] = values[0];
5820 args->out[1] = values[1];
5821 break;
5822
5823 case V_028714_SPI_SHADER_32_AR:
5824 args->enabled_channels = 0x9;
5825 args->out[0] = values[0];
5826 args->out[3] = values[3];
5827 break;
5828
5829 case V_028714_SPI_SHADER_FP16_ABGR:
5830 args->enabled_channels = 0x5;
5831 packf = ac_build_cvt_pkrtz_f16;
5832 break;
5833
5834 case V_028714_SPI_SHADER_UNORM16_ABGR:
5835 args->enabled_channels = 0x5;
5836 packf = ac_build_cvt_pknorm_u16;
5837 break;
5838
5839 case V_028714_SPI_SHADER_SNORM16_ABGR:
5840 args->enabled_channels = 0x5;
5841 packf = ac_build_cvt_pknorm_i16;
5842 break;
5843
5844 case V_028714_SPI_SHADER_UINT16_ABGR:
5845 args->enabled_channels = 0x5;
5846 packi = ac_build_cvt_pk_u16;
5847 break;
5848
5849 case V_028714_SPI_SHADER_SINT16_ABGR:
5850 args->enabled_channels = 0x5;
5851 packi = ac_build_cvt_pk_i16;
5852 break;
5853
5854 default:
5855 case V_028714_SPI_SHADER_32_ABGR:
5856 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5857 break;
5858 }
5859
5860 /* Pack f16 or norm_i16/u16. */
5861 if (packf) {
5862 for (chan = 0; chan < 2; chan++) {
5863 LLVMValueRef pack_args[2] = {
5864 values[2 * chan],
5865 values[2 * chan + 1]
5866 };
5867 LLVMValueRef packed;
5868
5869 packed = packf(&ctx->ac, pack_args);
5870 args->out[chan] = ac_to_float(&ctx->ac, packed);
5871 }
5872 args->compr = 1; /* COMPR flag */
5873 }
5874
5875 /* Pack i16/u16. */
5876 if (packi) {
5877 for (chan = 0; chan < 2; chan++) {
5878 LLVMValueRef pack_args[2] = {
5879 ac_to_integer(&ctx->ac, values[2 * chan]),
5880 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5881 };
5882 LLVMValueRef packed;
5883
5884 packed = packi(&ctx->ac, pack_args,
5885 is_int8 ? 8 : is_int10 ? 10 : 16,
5886 chan == 1);
5887 args->out[chan] = ac_to_float(&ctx->ac, packed);
5888 }
5889 args->compr = 1; /* COMPR flag */
5890 }
5891 return;
5892 }
5893
5894 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5895
5896 for (unsigned i = 0; i < 4; ++i) {
5897 if (!(args->enabled_channels & (1 << i)))
5898 continue;
5899
5900 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5901 }
5902 }
5903
5904 static void
5905 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5906 LLVMValueRef *values, unsigned enabled_channels)
5907 {
5908 struct ac_export_args args;
5909
5910 si_llvm_init_export_args(ctx, values, enabled_channels,
5911 V_008DFC_SQ_EXP_PARAM + index, &args);
5912 ac_build_export(&ctx->ac, &args);
5913 }
5914
5915 static LLVMValueRef
5916 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5917 {
5918 LLVMValueRef output =
5919 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5920
5921 return LLVMBuildLoad(ctx->ac.builder, output, "");
5922 }
5923
5924 static void
5925 handle_vs_outputs_post(struct radv_shader_context *ctx,
5926 bool export_prim_id,
5927 struct ac_vs_output_info *outinfo)
5928 {
5929 uint32_t param_count = 0;
5930 unsigned target;
5931 unsigned pos_idx, num_pos_exports = 0;
5932 struct ac_export_args args, pos_args[4] = {};
5933 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5934 int i;
5935
5936 if (ctx->options->key.has_multiview_view_index) {
5937 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5938 if(!*tmp_out) {
5939 for(unsigned i = 0; i < 4; ++i)
5940 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5941 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5942 }
5943
5944 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
5945 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5946 }
5947
5948 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5949 sizeof(outinfo->vs_output_param_offset));
5950
5951 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5952 LLVMValueRef slots[8];
5953 unsigned j;
5954
5955 if (outinfo->cull_dist_mask)
5956 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5957
5958 i = VARYING_SLOT_CLIP_DIST0;
5959 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5960 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
5961
5962 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5963 slots[i] = LLVMGetUndef(ctx->ac.f32);
5964
5965 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5966 target = V_008DFC_SQ_EXP_POS + 3;
5967 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
5968 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5969 &args, sizeof(args));
5970 }
5971
5972 target = V_008DFC_SQ_EXP_POS + 2;
5973 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
5974 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5975 &args, sizeof(args));
5976
5977 }
5978
5979 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5980 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5981 for (unsigned j = 0; j < 4; j++)
5982 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
5983 }
5984 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5985
5986 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5987 outinfo->writes_pointsize = true;
5988 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
5989 }
5990
5991 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5992 outinfo->writes_layer = true;
5993 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
5994 }
5995
5996 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5997 outinfo->writes_viewport_index = true;
5998 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
5999 }
6000
6001 if (outinfo->writes_pointsize ||
6002 outinfo->writes_layer ||
6003 outinfo->writes_viewport_index) {
6004 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6005 (outinfo->writes_layer == true ? 4 : 0));
6006 pos_args[1].valid_mask = 0;
6007 pos_args[1].done = 0;
6008 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6009 pos_args[1].compr = 0;
6010 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6011 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6012 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6013 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6014
6015 if (outinfo->writes_pointsize == true)
6016 pos_args[1].out[0] = psize_value;
6017 if (outinfo->writes_layer == true)
6018 pos_args[1].out[2] = layer_value;
6019 if (outinfo->writes_viewport_index == true) {
6020 if (ctx->options->chip_class >= GFX9) {
6021 /* GFX9 has the layer in out.z[10:0] and the viewport
6022 * index in out.z[19:16].
6023 */
6024 LLVMValueRef v = viewport_index_value;
6025 v = ac_to_integer(&ctx->ac, v);
6026 v = LLVMBuildShl(ctx->ac.builder, v,
6027 LLVMConstInt(ctx->ac.i32, 16, false),
6028 "");
6029 v = LLVMBuildOr(ctx->ac.builder, v,
6030 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6031
6032 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6033 pos_args[1].enabled_channels |= 1 << 2;
6034 } else {
6035 pos_args[1].out[3] = viewport_index_value;
6036 pos_args[1].enabled_channels |= 1 << 3;
6037 }
6038 }
6039 }
6040 for (i = 0; i < 4; i++) {
6041 if (pos_args[i].out[0])
6042 num_pos_exports++;
6043 }
6044
6045 pos_idx = 0;
6046 for (i = 0; i < 4; i++) {
6047 if (!pos_args[i].out[0])
6048 continue;
6049
6050 /* Specify the target we are exporting */
6051 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6052 if (pos_idx == num_pos_exports)
6053 pos_args[i].done = 1;
6054 ac_build_export(&ctx->ac, &pos_args[i]);
6055 }
6056
6057 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6058 LLVMValueRef values[4];
6059 if (!(ctx->output_mask & (1ull << i)))
6060 continue;
6061
6062 if (i != VARYING_SLOT_LAYER &&
6063 i != VARYING_SLOT_PRIMITIVE_ID &&
6064 i < VARYING_SLOT_VAR0)
6065 continue;
6066
6067 for (unsigned j = 0; j < 4; j++)
6068 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6069
6070 unsigned output_usage_mask;
6071
6072 if (ctx->stage == MESA_SHADER_VERTEX &&
6073 !ctx->is_gs_copy_shader) {
6074 output_usage_mask =
6075 ctx->shader_info->info.vs.output_usage_mask[i];
6076 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
6077 output_usage_mask =
6078 ctx->shader_info->info.tes.output_usage_mask[i];
6079 } else {
6080 /* Enable all channels for the GS copy shader because
6081 * we don't know the output usage mask currently.
6082 */
6083 output_usage_mask = 0xf;
6084 }
6085
6086 radv_export_param(ctx, param_count, values, output_usage_mask);
6087
6088 outinfo->vs_output_param_offset[i] = param_count++;
6089 }
6090
6091 if (export_prim_id) {
6092 LLVMValueRef values[4];
6093
6094 values[0] = ctx->vs_prim_id;
6095 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6096 ctx->shader_info->vs.vgpr_comp_cnt);
6097 for (unsigned j = 1; j < 4; j++)
6098 values[j] = ctx->ac.f32_0;
6099
6100 radv_export_param(ctx, param_count, values, 0xf);
6101
6102 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6103 outinfo->export_prim_id = true;
6104 }
6105
6106 outinfo->pos_exports = num_pos_exports;
6107 outinfo->param_exports = param_count;
6108 }
6109
6110 static void
6111 handle_es_outputs_post(struct radv_shader_context *ctx,
6112 struct ac_es_output_info *outinfo)
6113 {
6114 int j;
6115 uint64_t max_output_written = 0;
6116 LLVMValueRef lds_base = NULL;
6117
6118 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6119 int param_index;
6120 int length = 4;
6121
6122 if (!(ctx->output_mask & (1ull << i)))
6123 continue;
6124
6125 if (i == VARYING_SLOT_CLIP_DIST0)
6126 length = ctx->num_output_clips + ctx->num_output_culls;
6127
6128 param_index = shader_io_get_unique_index(i);
6129
6130 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6131 }
6132
6133 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6134
6135 if (ctx->ac.chip_class >= GFX9) {
6136 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6137 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6138 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6139 LLVMConstInt(ctx->ac.i32, 24, false),
6140 LLVMConstInt(ctx->ac.i32, 4, false), false);
6141 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6142 LLVMBuildMul(ctx->ac.builder, wave_idx,
6143 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6144 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6145 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6146 }
6147
6148 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6149 LLVMValueRef dw_addr = NULL;
6150 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6151 int param_index;
6152 int length = 4;
6153
6154 if (!(ctx->output_mask & (1ull << i)))
6155 continue;
6156
6157 if (i == VARYING_SLOT_CLIP_DIST0)
6158 length = ctx->num_output_clips + ctx->num_output_culls;
6159
6160 param_index = shader_io_get_unique_index(i);
6161
6162 if (lds_base) {
6163 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6164 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6165 "");
6166 }
6167 for (j = 0; j < length; j++) {
6168 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6169 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6170
6171 if (ctx->ac.chip_class >= GFX9) {
6172 ac_lds_store(&ctx->ac, dw_addr,
6173 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6174 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6175 } else {
6176 ac_build_buffer_store_dword(&ctx->ac,
6177 ctx->esgs_ring,
6178 out_val, 1,
6179 NULL, ctx->es2gs_offset,
6180 (4 * param_index + j) * 4,
6181 1, 1, true, true);
6182 }
6183 }
6184 }
6185 }
6186
6187 static void
6188 handle_ls_outputs_post(struct radv_shader_context *ctx)
6189 {
6190 LLVMValueRef vertex_id = ctx->rel_auto_id;
6191 LLVMValueRef vertex_dw_stride = ac_unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6192 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6193 vertex_dw_stride, "");
6194
6195 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6196 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6197 int length = 4;
6198
6199 if (!(ctx->output_mask & (1ull << i)))
6200 continue;
6201
6202 if (i == VARYING_SLOT_CLIP_DIST0)
6203 length = ctx->num_output_clips + ctx->num_output_culls;
6204 int param = shader_io_get_unique_index(i);
6205 mark_tess_output(ctx, false, param);
6206 if (length > 4)
6207 mark_tess_output(ctx, false, param + 1);
6208 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6209 LLVMConstInt(ctx->ac.i32, param * 4, false),
6210 "");
6211 for (unsigned j = 0; j < length; j++) {
6212 ac_lds_store(&ctx->ac, dw_addr,
6213 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6214 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6215 }
6216 }
6217 }
6218
6219 struct ac_build_if_state
6220 {
6221 struct radv_shader_context *ctx;
6222 LLVMValueRef condition;
6223 LLVMBasicBlockRef entry_block;
6224 LLVMBasicBlockRef true_block;
6225 LLVMBasicBlockRef false_block;
6226 LLVMBasicBlockRef merge_block;
6227 };
6228
6229 static LLVMBasicBlockRef
6230 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6231 {
6232 LLVMBasicBlockRef current_block;
6233 LLVMBasicBlockRef next_block;
6234 LLVMBasicBlockRef new_block;
6235
6236 /* get current basic block */
6237 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6238
6239 /* chqeck if there's another block after this one */
6240 next_block = LLVMGetNextBasicBlock(current_block);
6241 if (next_block) {
6242 /* insert the new block before the next block */
6243 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6244 }
6245 else {
6246 /* append new block after current block */
6247 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6248 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6249 }
6250 return new_block;
6251 }
6252
6253 static void
6254 ac_nir_build_if(struct ac_build_if_state *ifthen,
6255 struct radv_shader_context *ctx,
6256 LLVMValueRef condition)
6257 {
6258 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6259
6260 memset(ifthen, 0, sizeof *ifthen);
6261 ifthen->ctx = ctx;
6262 ifthen->condition = condition;
6263 ifthen->entry_block = block;
6264
6265 /* create endif/merge basic block for the phi functions */
6266 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6267
6268 /* create/insert true_block before merge_block */
6269 ifthen->true_block =
6270 LLVMInsertBasicBlockInContext(ctx->context,
6271 ifthen->merge_block,
6272 "if-true-block");
6273
6274 /* successive code goes into the true block */
6275 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6276 }
6277
6278 /**
6279 * End a conditional.
6280 */
6281 static void
6282 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6283 {
6284 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6285
6286 /* Insert branch to the merge block from current block */
6287 LLVMBuildBr(builder, ifthen->merge_block);
6288
6289 /*
6290 * Now patch in the various branch instructions.
6291 */
6292
6293 /* Insert the conditional branch instruction at the end of entry_block */
6294 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6295 if (ifthen->false_block) {
6296 /* we have an else clause */
6297 LLVMBuildCondBr(builder, ifthen->condition,
6298 ifthen->true_block, ifthen->false_block);
6299 }
6300 else {
6301 /* no else clause */
6302 LLVMBuildCondBr(builder, ifthen->condition,
6303 ifthen->true_block, ifthen->merge_block);
6304 }
6305
6306 /* Resume building code at end of the ifthen->merge_block */
6307 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6308 }
6309
6310 static void
6311 write_tess_factors(struct radv_shader_context *ctx)
6312 {
6313 unsigned stride, outer_comps, inner_comps;
6314 struct ac_build_if_state if_ctx, inner_if_ctx;
6315 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6316 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6317 unsigned tess_inner_index = 0, tess_outer_index;
6318 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
6319 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6320 int i;
6321 emit_barrier(&ctx->ac, ctx->stage);
6322
6323 switch (ctx->options->key.tcs.primitive_mode) {
6324 case GL_ISOLINES:
6325 stride = 2;
6326 outer_comps = 2;
6327 inner_comps = 0;
6328 break;
6329 case GL_TRIANGLES:
6330 stride = 4;
6331 outer_comps = 3;
6332 inner_comps = 1;
6333 break;
6334 case GL_QUADS:
6335 stride = 6;
6336 outer_comps = 4;
6337 inner_comps = 2;
6338 break;
6339 default:
6340 return;
6341 }
6342
6343 ac_nir_build_if(&if_ctx, ctx,
6344 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6345 invocation_id, ctx->ac.i32_0, ""));
6346
6347 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6348
6349 if (inner_comps) {
6350 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6351 mark_tess_output(ctx, true, tess_inner_index);
6352 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6353 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6354 }
6355
6356 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6357 mark_tess_output(ctx, true, tess_outer_index);
6358 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6359 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6360
6361 for (i = 0; i < 4; i++) {
6362 inner[i] = LLVMGetUndef(ctx->ac.i32);
6363 outer[i] = LLVMGetUndef(ctx->ac.i32);
6364 }
6365
6366 // LINES reverseal
6367 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6368 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6369 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6370 ctx->ac.i32_1, "");
6371 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6372 } else {
6373 for (i = 0; i < outer_comps; i++) {
6374 outer[i] = out[i] =
6375 ac_lds_load(&ctx->ac, lds_outer);
6376 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6377 ctx->ac.i32_1, "");
6378 }
6379 for (i = 0; i < inner_comps; i++) {
6380 inner[i] = out[outer_comps+i] =
6381 ac_lds_load(&ctx->ac, lds_inner);
6382 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6383 ctx->ac.i32_1, "");
6384 }
6385 }
6386
6387 /* Convert the outputs to vectors for stores. */
6388 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6389 vec1 = NULL;
6390
6391 if (stride > 4)
6392 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6393
6394
6395 buffer = ctx->hs_ring_tess_factor;
6396 tf_base = ctx->tess_factor_offset;
6397 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6398 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6399 unsigned tf_offset = 0;
6400
6401 if (ctx->options->chip_class <= VI) {
6402 ac_nir_build_if(&inner_if_ctx, ctx,
6403 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6404 rel_patch_id, ctx->ac.i32_0, ""));
6405
6406 /* Store the dynamic HS control word. */
6407 ac_build_buffer_store_dword(&ctx->ac, buffer,
6408 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6409 1, ctx->ac.i32_0, tf_base,
6410 0, 1, 0, true, false);
6411 tf_offset += 4;
6412
6413 ac_nir_build_endif(&inner_if_ctx);
6414 }
6415
6416 /* Store the tessellation factors. */
6417 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6418 MIN2(stride, 4), byteoffset, tf_base,
6419 tf_offset, 1, 0, true, false);
6420 if (vec1)
6421 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6422 stride - 4, byteoffset, tf_base,
6423 16 + tf_offset, 1, 0, true, false);
6424
6425 //store to offchip for TES to read - only if TES reads them
6426 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6427 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6428 LLVMValueRef tf_inner_offset;
6429 unsigned param_outer, param_inner;
6430
6431 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6432 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6433 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6434
6435 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6436 util_next_power_of_two(outer_comps));
6437
6438 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6439 outer_comps, tf_outer_offset,
6440 ctx->oc_lds, 0, 1, 0, true, false);
6441 if (inner_comps) {
6442 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6443 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6444 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6445
6446 inner_vec = inner_comps == 1 ? inner[0] :
6447 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6448 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6449 inner_comps, tf_inner_offset,
6450 ctx->oc_lds, 0, 1, 0, true, false);
6451 }
6452 }
6453 ac_nir_build_endif(&if_ctx);
6454 }
6455
6456 static void
6457 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6458 {
6459 write_tess_factors(ctx);
6460 }
6461
6462 static bool
6463 si_export_mrt_color(struct radv_shader_context *ctx,
6464 LLVMValueRef *color, unsigned index,
6465 struct ac_export_args *args)
6466 {
6467 /* Export */
6468 si_llvm_init_export_args(ctx, color, 0xf,
6469 V_008DFC_SQ_EXP_MRT + index, args);
6470 if (!args->enabled_channels)
6471 return false; /* unnecessary NULL export */
6472
6473 return true;
6474 }
6475
6476 static void
6477 radv_export_mrt_z(struct radv_shader_context *ctx,
6478 LLVMValueRef depth, LLVMValueRef stencil,
6479 LLVMValueRef samplemask)
6480 {
6481 struct ac_export_args args;
6482
6483 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6484
6485 ac_build_export(&ctx->ac, &args);
6486 }
6487
6488 static void
6489 handle_fs_outputs_post(struct radv_shader_context *ctx)
6490 {
6491 unsigned index = 0;
6492 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6493 struct ac_export_args color_args[8];
6494
6495 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6496 LLVMValueRef values[4];
6497
6498 if (!(ctx->output_mask & (1ull << i)))
6499 continue;
6500
6501 if (i < FRAG_RESULT_DATA0)
6502 continue;
6503
6504 for (unsigned j = 0; j < 4; j++)
6505 values[j] = ac_to_float(&ctx->ac,
6506 radv_load_output(ctx, i, j));
6507
6508 bool ret = si_export_mrt_color(ctx, values,
6509 i - FRAG_RESULT_DATA0,
6510 &color_args[index]);
6511 if (ret)
6512 index++;
6513 }
6514
6515 /* Process depth, stencil, samplemask. */
6516 if (ctx->shader_info->info.ps.writes_z) {
6517 depth = ac_to_float(&ctx->ac,
6518 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6519 }
6520 if (ctx->shader_info->info.ps.writes_stencil) {
6521 stencil = ac_to_float(&ctx->ac,
6522 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6523 }
6524 if (ctx->shader_info->info.ps.writes_sample_mask) {
6525 samplemask = ac_to_float(&ctx->ac,
6526 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6527 }
6528
6529 /* Set the DONE bit on last non-null color export only if Z isn't
6530 * exported.
6531 */
6532 if (index > 0 &&
6533 !ctx->shader_info->info.ps.writes_z &&
6534 !ctx->shader_info->info.ps.writes_stencil &&
6535 !ctx->shader_info->info.ps.writes_sample_mask) {
6536 unsigned last = index - 1;
6537
6538 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
6539 color_args[last].done = 1; /* DONE bit */
6540 }
6541
6542 /* Export PS outputs. */
6543 for (unsigned i = 0; i < index; i++)
6544 ac_build_export(&ctx->ac, &color_args[i]);
6545
6546 if (depth || stencil || samplemask)
6547 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6548 else if (!index)
6549 ac_build_export_null(&ctx->ac);
6550 }
6551
6552 static void
6553 emit_gs_epilogue(struct radv_shader_context *ctx)
6554 {
6555 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6556 }
6557
6558 static void
6559 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6560 LLVMValueRef *addrs)
6561 {
6562 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6563
6564 switch (ctx->stage) {
6565 case MESA_SHADER_VERTEX:
6566 if (ctx->options->key.vs.as_ls)
6567 handle_ls_outputs_post(ctx);
6568 else if (ctx->options->key.vs.as_es)
6569 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6570 else
6571 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6572 &ctx->shader_info->vs.outinfo);
6573 break;
6574 case MESA_SHADER_FRAGMENT:
6575 handle_fs_outputs_post(ctx);
6576 break;
6577 case MESA_SHADER_GEOMETRY:
6578 emit_gs_epilogue(ctx);
6579 break;
6580 case MESA_SHADER_TESS_CTRL:
6581 handle_tcs_outputs_post(ctx);
6582 break;
6583 case MESA_SHADER_TESS_EVAL:
6584 if (ctx->options->key.tes.as_es)
6585 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6586 else
6587 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6588 &ctx->shader_info->tes.outinfo);
6589 break;
6590 default:
6591 break;
6592 }
6593 }
6594
6595 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6596 {
6597 LLVMPassManagerRef passmgr;
6598 /* Create the pass manager */
6599 passmgr = LLVMCreateFunctionPassManagerForModule(
6600 ctx->ac.module);
6601
6602 /* This pass should eliminate all the load and store instructions */
6603 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6604
6605 /* Add some optimization passes */
6606 LLVMAddScalarReplAggregatesPass(passmgr);
6607 LLVMAddLICMPass(passmgr);
6608 LLVMAddAggressiveDCEPass(passmgr);
6609 LLVMAddCFGSimplificationPass(passmgr);
6610 LLVMAddInstructionCombiningPass(passmgr);
6611
6612 /* Run the pass */
6613 LLVMInitializeFunctionPassManager(passmgr);
6614 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6615 LLVMFinalizeFunctionPassManager(passmgr);
6616
6617 LLVMDisposeBuilder(ctx->ac.builder);
6618 LLVMDisposePassManager(passmgr);
6619
6620 ac_llvm_context_dispose(&ctx->ac);
6621 }
6622
6623 static void
6624 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6625 {
6626 struct ac_vs_output_info *outinfo;
6627
6628 switch (ctx->stage) {
6629 case MESA_SHADER_FRAGMENT:
6630 case MESA_SHADER_COMPUTE:
6631 case MESA_SHADER_TESS_CTRL:
6632 case MESA_SHADER_GEOMETRY:
6633 return;
6634 case MESA_SHADER_VERTEX:
6635 if (ctx->options->key.vs.as_ls ||
6636 ctx->options->key.vs.as_es)
6637 return;
6638 outinfo = &ctx->shader_info->vs.outinfo;
6639 break;
6640 case MESA_SHADER_TESS_EVAL:
6641 if (ctx->options->key.vs.as_es)
6642 return;
6643 outinfo = &ctx->shader_info->tes.outinfo;
6644 break;
6645 default:
6646 unreachable("Unhandled shader type");
6647 }
6648
6649 ac_optimize_vs_outputs(&ctx->ac,
6650 ctx->main_function,
6651 outinfo->vs_output_param_offset,
6652 VARYING_SLOT_MAX,
6653 &outinfo->param_exports);
6654 }
6655
6656 static void
6657 ac_setup_rings(struct radv_shader_context *ctx)
6658 {
6659 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6660 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6661 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6662 }
6663
6664 if (ctx->is_gs_copy_shader) {
6665 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6666 }
6667 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6668 LLVMValueRef tmp;
6669 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6670 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6671
6672 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6673
6674 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6675 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6676 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6677 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6678 }
6679
6680 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6681 ctx->stage == MESA_SHADER_TESS_EVAL) {
6682 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6683 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6684 }
6685 }
6686
6687 static unsigned
6688 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6689 const struct nir_shader *nir)
6690 {
6691 switch (nir->info.stage) {
6692 case MESA_SHADER_TESS_CTRL:
6693 return chip_class >= CIK ? 128 : 64;
6694 case MESA_SHADER_GEOMETRY:
6695 return chip_class >= GFX9 ? 128 : 64;
6696 case MESA_SHADER_COMPUTE:
6697 break;
6698 default:
6699 return 0;
6700 }
6701
6702 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6703 nir->info.cs.local_size[1] *
6704 nir->info.cs.local_size[2];
6705 return max_workgroup_size;
6706 }
6707
6708 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6709 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6710 {
6711 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6712 LLVMConstInt(ctx->ac.i32, 8, false),
6713 LLVMConstInt(ctx->ac.i32, 8, false), false);
6714 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6715 ctx->ac.i32_0, "");
6716 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6717 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6718 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6719 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6720 }
6721
6722 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6723 {
6724 for(int i = 5; i >= 0; --i) {
6725 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6726 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6727 LLVMConstInt(ctx->ac.i32, 16, false), false);
6728 }
6729
6730 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6731 LLVMConstInt(ctx->ac.i32, 16, false),
6732 LLVMConstInt(ctx->ac.i32, 8, false), false);
6733 }
6734
6735 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6736 struct nir_shader *nir)
6737 {
6738 struct ac_nir_context ctx = {};
6739 struct nir_function *func;
6740
6741 /* Last minute passes for both radv & radeonsi */
6742 ac_lower_subgroups(nir);
6743
6744 ctx.ac = *ac;
6745 ctx.abi = abi;
6746
6747 ctx.stage = nir->info.stage;
6748
6749 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6750
6751 nir_foreach_variable(variable, &nir->outputs)
6752 ac_handle_shader_output_decl(&ctx.ac, ctx.abi, nir, variable,
6753 ctx.stage);
6754
6755 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6756 _mesa_key_pointer_equal);
6757 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6758 _mesa_key_pointer_equal);
6759 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6760 _mesa_key_pointer_equal);
6761
6762 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6763
6764 setup_locals(&ctx, func);
6765
6766 if (nir->info.stage == MESA_SHADER_COMPUTE)
6767 setup_shared(&ctx, nir);
6768
6769 visit_cf_list(&ctx, &func->impl->body);
6770 phi_post_pass(&ctx);
6771
6772 if (nir->info.stage != MESA_SHADER_COMPUTE)
6773 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6774 ctx.abi->outputs);
6775
6776 free(ctx.locals);
6777 ralloc_free(ctx.defs);
6778 ralloc_free(ctx.phis);
6779 ralloc_free(ctx.vars);
6780 }
6781
6782 static
6783 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6784 struct nir_shader *const *shaders,
6785 int shader_count,
6786 struct ac_shader_variant_info *shader_info,
6787 const struct ac_nir_compiler_options *options,
6788 bool dump_shader)
6789 {
6790 struct radv_shader_context ctx = {0};
6791 unsigned i;
6792 ctx.options = options;
6793 ctx.shader_info = shader_info;
6794 ctx.context = LLVMContextCreate();
6795
6796 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6797 options->family);
6798 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6799 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6800
6801 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6802 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6803 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6804 LLVMDisposeTargetData(data_layout);
6805 LLVMDisposeMessage(data_layout_str);
6806
6807 enum ac_float_mode float_mode =
6808 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6809 AC_FLOAT_MODE_DEFAULT;
6810
6811 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6812
6813 memset(shader_info, 0, sizeof(*shader_info));
6814
6815 for(int i = 0; i < shader_count; ++i)
6816 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6817
6818 for (i = 0; i < AC_UD_MAX_SETS; i++)
6819 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6820 for (i = 0; i < AC_UD_MAX_UD; i++)
6821 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6822
6823 ctx.max_workgroup_size = 0;
6824 for (int i = 0; i < shader_count; ++i) {
6825 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6826 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6827 shaders[i]));
6828 }
6829
6830 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6831 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6832
6833 ctx.abi.inputs = &ctx.inputs[0];
6834 ctx.abi.emit_outputs = handle_shader_outputs_post;
6835 ctx.abi.emit_vertex = visit_emit_vertex;
6836 ctx.abi.load_ubo = radv_load_ubo;
6837 ctx.abi.load_ssbo = radv_load_ssbo;
6838 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6839 ctx.abi.load_resource = radv_load_resource;
6840 ctx.abi.clamp_shadow_reference = false;
6841
6842 if (shader_count >= 2)
6843 ac_init_exec_full_mask(&ctx.ac);
6844
6845 if (ctx.ac.chip_class == GFX9 &&
6846 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6847 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6848
6849 for(int i = 0; i < shader_count; ++i) {
6850 ctx.stage = shaders[i]->info.stage;
6851 ctx.output_mask = 0;
6852 ctx.tess_outputs_written = 0;
6853 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6854 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6855
6856 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6857 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6858 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6859 ctx.abi.load_inputs = load_gs_input;
6860 ctx.abi.emit_primitive = visit_end_primitive;
6861 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6862 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6863 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6864 ctx.abi.load_tess_varyings = load_tcs_varyings;
6865 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6866 ctx.abi.store_tcs_outputs = store_tcs_output;
6867 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6868 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6869 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6870 ctx.abi.load_tess_varyings = load_tes_input;
6871 ctx.abi.load_tess_coord = load_tess_coord;
6872 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6873 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6874 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6875 if (shader_info->info.vs.needs_instance_id) {
6876 if (ctx.options->key.vs.as_ls) {
6877 ctx.shader_info->vs.vgpr_comp_cnt =
6878 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6879 } else {
6880 ctx.shader_info->vs.vgpr_comp_cnt =
6881 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6882 }
6883 }
6884 ctx.abi.load_base_vertex = radv_load_base_vertex;
6885 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6886 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6887 ctx.abi.lookup_interp_param = lookup_interp_param;
6888 ctx.abi.load_sample_position = load_sample_position;
6889 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6890 ctx.abi.emit_kill = radv_emit_kill;
6891 }
6892
6893 if (i)
6894 emit_barrier(&ctx.ac, ctx.stage);
6895
6896 ac_setup_rings(&ctx);
6897
6898 LLVMBasicBlockRef merge_block;
6899 if (shader_count >= 2) {
6900 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6901 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6902 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6903
6904 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6905 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6906 LLVMConstInt(ctx.ac.i32, 8, false), false);
6907 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6908 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6909 thread_id, count, "");
6910 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6911
6912 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6913 }
6914
6915 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6916 handle_fs_inputs(&ctx, shaders[i]);
6917 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6918 handle_vs_inputs(&ctx, shaders[i]);
6919 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6920 prepare_gs_input_vgprs(&ctx);
6921
6922 nir_foreach_variable(variable, &shaders[i]->outputs)
6923 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6924
6925 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6926
6927 if (shader_count >= 2) {
6928 LLVMBuildBr(ctx.ac.builder, merge_block);
6929 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6930 }
6931
6932 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6933 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6934 shaders[i]->info.cull_distance_array_size > 4;
6935 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6936 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6937 shaders[i]->info.gs.vertices_out;
6938 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6939 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6940 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6941 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6942 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6943 }
6944 }
6945
6946 LLVMBuildRetVoid(ctx.ac.builder);
6947
6948 if (options->dump_preoptir)
6949 ac_dump_module(ctx.ac.module);
6950
6951 ac_llvm_finalize_module(&ctx);
6952
6953 if (shader_count == 1)
6954 ac_nir_eliminate_const_vs_outputs(&ctx);
6955
6956 if (dump_shader) {
6957 ctx.shader_info->private_mem_vgprs =
6958 ac_count_scratch_private_memory(ctx.main_function);
6959 }
6960
6961 return ctx.ac.module;
6962 }
6963
6964 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6965 {
6966 unsigned *retval = (unsigned *)context;
6967 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6968 char *description = LLVMGetDiagInfoDescription(di);
6969
6970 if (severity == LLVMDSError) {
6971 *retval = 1;
6972 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6973 description);
6974 }
6975
6976 LLVMDisposeMessage(description);
6977 }
6978
6979 static unsigned ac_llvm_compile(LLVMModuleRef M,
6980 struct ac_shader_binary *binary,
6981 LLVMTargetMachineRef tm)
6982 {
6983 unsigned retval = 0;
6984 char *err;
6985 LLVMContextRef llvm_ctx;
6986 LLVMMemoryBufferRef out_buffer;
6987 unsigned buffer_size;
6988 const char *buffer_data;
6989 LLVMBool mem_err;
6990
6991 /* Setup Diagnostic Handler*/
6992 llvm_ctx = LLVMGetModuleContext(M);
6993
6994 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6995 &retval);
6996
6997 /* Compile IR*/
6998 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6999 &err, &out_buffer);
7000
7001 /* Process Errors/Warnings */
7002 if (mem_err) {
7003 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7004 free(err);
7005 retval = 1;
7006 goto out;
7007 }
7008
7009 /* Extract Shader Code*/
7010 buffer_size = LLVMGetBufferSize(out_buffer);
7011 buffer_data = LLVMGetBufferStart(out_buffer);
7012
7013 ac_elf_read(buffer_data, buffer_size, binary);
7014
7015 /* Clean up */
7016 LLVMDisposeMemoryBuffer(out_buffer);
7017
7018 out:
7019 return retval;
7020 }
7021
7022 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7023 LLVMModuleRef llvm_module,
7024 struct ac_shader_binary *binary,
7025 struct ac_shader_config *config,
7026 struct ac_shader_variant_info *shader_info,
7027 gl_shader_stage stage,
7028 bool dump_shader, bool supports_spill)
7029 {
7030 if (dump_shader)
7031 ac_dump_module(llvm_module);
7032
7033 memset(binary, 0, sizeof(*binary));
7034 int v = ac_llvm_compile(llvm_module, binary, tm);
7035 if (v) {
7036 fprintf(stderr, "compile failed\n");
7037 }
7038
7039 if (dump_shader)
7040 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7041
7042 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7043
7044 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7045 LLVMDisposeModule(llvm_module);
7046 LLVMContextDispose(ctx);
7047
7048 if (stage == MESA_SHADER_FRAGMENT) {
7049 shader_info->num_input_vgprs = 0;
7050 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7051 shader_info->num_input_vgprs += 2;
7052 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7053 shader_info->num_input_vgprs += 2;
7054 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7055 shader_info->num_input_vgprs += 2;
7056 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7057 shader_info->num_input_vgprs += 3;
7058 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7059 shader_info->num_input_vgprs += 2;
7060 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7061 shader_info->num_input_vgprs += 2;
7062 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7063 shader_info->num_input_vgprs += 2;
7064 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7065 shader_info->num_input_vgprs += 1;
7066 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7067 shader_info->num_input_vgprs += 1;
7068 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7069 shader_info->num_input_vgprs += 1;
7070 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7071 shader_info->num_input_vgprs += 1;
7072 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7073 shader_info->num_input_vgprs += 1;
7074 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7075 shader_info->num_input_vgprs += 1;
7076 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7077 shader_info->num_input_vgprs += 1;
7078 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7079 shader_info->num_input_vgprs += 1;
7080 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7081 shader_info->num_input_vgprs += 1;
7082 }
7083 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7084
7085 /* +3 for scratch wave offset and VCC */
7086 config->num_sgprs = MAX2(config->num_sgprs,
7087 shader_info->num_input_sgprs + 3);
7088
7089 /* Enable 64-bit and 16-bit denormals, because there is no performance
7090 * cost.
7091 *
7092 * If denormals are enabled, all floating-point output modifiers are
7093 * ignored.
7094 *
7095 * Don't enable denormals for 32-bit floats, because:
7096 * - Floating-point output modifiers would be ignored by the hw.
7097 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7098 * have to stop using those.
7099 * - SI & CI would be very slow.
7100 */
7101 config->float_mode |= V_00B028_FP_64_DENORMS;
7102 }
7103
7104 static void
7105 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7106 {
7107 switch (nir->info.stage) {
7108 case MESA_SHADER_COMPUTE:
7109 for (int i = 0; i < 3; ++i)
7110 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7111 break;
7112 case MESA_SHADER_FRAGMENT:
7113 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7114 break;
7115 case MESA_SHADER_GEOMETRY:
7116 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7117 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7118 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7119 shader_info->gs.invocations = nir->info.gs.invocations;
7120 break;
7121 case MESA_SHADER_TESS_EVAL:
7122 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7123 shader_info->tes.spacing = nir->info.tess.spacing;
7124 shader_info->tes.ccw = nir->info.tess.ccw;
7125 shader_info->tes.point_mode = nir->info.tess.point_mode;
7126 shader_info->tes.as_es = options->key.tes.as_es;
7127 break;
7128 case MESA_SHADER_TESS_CTRL:
7129 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7130 break;
7131 case MESA_SHADER_VERTEX:
7132 shader_info->vs.as_es = options->key.vs.as_es;
7133 shader_info->vs.as_ls = options->key.vs.as_ls;
7134 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7135 if (options->key.vs.as_ls)
7136 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7137 break;
7138 default:
7139 break;
7140 }
7141 }
7142
7143 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7144 struct ac_shader_binary *binary,
7145 struct ac_shader_config *config,
7146 struct ac_shader_variant_info *shader_info,
7147 struct nir_shader *const *nir,
7148 int nir_count,
7149 const struct ac_nir_compiler_options *options,
7150 bool dump_shader)
7151 {
7152
7153 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7154 options, dump_shader);
7155
7156 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7157 for (int i = 0; i < nir_count; ++i)
7158 ac_fill_shader_info(shader_info, nir[i], options);
7159
7160 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7161 if (options->chip_class == GFX9) {
7162 if (nir_count == 2 &&
7163 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7164 shader_info->gs.es_type = nir[0]->info.stage;
7165 }
7166 }
7167 }
7168
7169 static void
7170 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7171 {
7172 LLVMValueRef vtx_offset =
7173 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7174 LLVMConstInt(ctx->ac.i32, 4, false), "");
7175 int idx = 0;
7176
7177 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7178 int length = 4;
7179 int slot = idx;
7180 int slot_inc = 1;
7181 if (!(ctx->output_mask & (1ull << i)))
7182 continue;
7183
7184 if (i == VARYING_SLOT_CLIP_DIST0) {
7185 /* unpack clip and cull from a single set of slots */
7186 length = ctx->num_output_clips + ctx->num_output_culls;
7187 if (length > 4)
7188 slot_inc = 2;
7189 }
7190
7191 for (unsigned j = 0; j < length; j++) {
7192 LLVMValueRef value, soffset;
7193
7194 soffset = LLVMConstInt(ctx->ac.i32,
7195 (slot * 4 + j) *
7196 ctx->gs_max_out_vertices * 16 * 4, false);
7197
7198 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7199 1, ctx->ac.i32_0,
7200 vtx_offset, soffset,
7201 0, 1, 1, true, false);
7202
7203 LLVMBuildStore(ctx->ac.builder,
7204 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7205 }
7206 idx += slot_inc;
7207 }
7208 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7209 }
7210
7211 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7212 struct nir_shader *geom_shader,
7213 struct ac_shader_binary *binary,
7214 struct ac_shader_config *config,
7215 struct ac_shader_variant_info *shader_info,
7216 const struct ac_nir_compiler_options *options,
7217 bool dump_shader)
7218 {
7219 struct radv_shader_context ctx = {0};
7220 ctx.context = LLVMContextCreate();
7221 ctx.options = options;
7222 ctx.shader_info = shader_info;
7223
7224 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7225 options->family);
7226 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7227
7228 ctx.is_gs_copy_shader = true;
7229 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7230
7231 enum ac_float_mode float_mode =
7232 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7233 AC_FLOAT_MODE_DEFAULT;
7234
7235 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7236 ctx.stage = MESA_SHADER_VERTEX;
7237
7238 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7239
7240 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7241 ac_setup_rings(&ctx);
7242
7243 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7244 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7245
7246 nir_foreach_variable(variable, &geom_shader->outputs) {
7247 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7248 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
7249 variable, MESA_SHADER_VERTEX);
7250 }
7251
7252 ac_gs_copy_shader_emit(&ctx);
7253
7254 LLVMBuildRetVoid(ctx.ac.builder);
7255
7256 ac_llvm_finalize_module(&ctx);
7257
7258 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7259 MESA_SHADER_VERTEX,
7260 dump_shader, options->supports_spill);
7261 }
7262
7263 void
7264 ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class chip_class)
7265 {
7266 /* While it would be nice not to have this flag, we are constrained
7267 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
7268 * on GFX9.
7269 */
7270 bool llvm_has_working_vgpr_indexing = chip_class <= VI;
7271
7272 /* TODO: Indirect indexing of GS inputs is unimplemented.
7273 *
7274 * TCS and TES load inputs directly from LDS or offchip memory, so
7275 * indirect indexing is trivial.
7276 */
7277 nir_variable_mode indirect_mask = 0;
7278 if (nir->info.stage == MESA_SHADER_GEOMETRY ||
7279 (nir->info.stage != MESA_SHADER_TESS_CTRL &&
7280 nir->info.stage != MESA_SHADER_TESS_EVAL &&
7281 !llvm_has_working_vgpr_indexing)) {
7282 indirect_mask |= nir_var_shader_in;
7283 }
7284 if (!llvm_has_working_vgpr_indexing &&
7285 nir->info.stage != MESA_SHADER_TESS_CTRL)
7286 indirect_mask |= nir_var_shader_out;
7287
7288 /* TODO: We shouldn't need to do this, however LLVM isn't currently
7289 * smart enough to handle indirects without causing excess spilling
7290 * causing the gpu to hang.
7291 *
7292 * See the following thread for more details of the problem:
7293 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
7294 */
7295 indirect_mask |= nir_var_local;
7296
7297 nir_lower_indirect_derefs(nir, indirect_mask);
7298 }