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radv: move to using common buffer load format.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83 LLVMValueRef ls_out_layout;
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef tcs_offchip_layout;
87 LLVMValueRef tcs_out_offsets;
88 LLVMValueRef tcs_out_layout;
89 LLVMValueRef tcs_in_layout;
90 LLVMValueRef oc_lds;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tcs_patch_id;
93 LLVMValueRef tcs_rel_ids;
94 LLVMValueRef tes_rel_patch_id;
95 LLVMValueRef tes_patch_id;
96 LLVMValueRef tes_u;
97 LLVMValueRef tes_v;
98
99 LLVMValueRef gsvs_ring_stride;
100 LLVMValueRef gsvs_num_entries;
101 LLVMValueRef gs2vs_offset;
102 LLVMValueRef gs_wave_id;
103 LLVMValueRef gs_vtx_offset[6];
104 LLVMValueRef gs_prim_id, gs_invocation_id;
105
106 LLVMValueRef esgs_ring;
107 LLVMValueRef gsvs_ring;
108 LLVMValueRef hs_ring_tess_offchip;
109 LLVMValueRef hs_ring_tess_factor;
110
111 LLVMValueRef prim_mask;
112 LLVMValueRef sample_positions;
113 LLVMValueRef persp_sample, persp_center, persp_centroid;
114 LLVMValueRef linear_sample, linear_center, linear_centroid;
115 LLVMValueRef front_face;
116 LLVMValueRef ancillary;
117 LLVMValueRef sample_coverage;
118 LLVMValueRef frag_pos[4];
119
120 LLVMBasicBlockRef continue_block;
121 LLVMBasicBlockRef break_block;
122
123 LLVMTypeRef i1;
124 LLVMTypeRef i8;
125 LLVMTypeRef i16;
126 LLVMTypeRef i32;
127 LLVMTypeRef i64;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v3i32;
130 LLVMTypeRef v4i32;
131 LLVMTypeRef v8i32;
132 LLVMTypeRef f64;
133 LLVMTypeRef f32;
134 LLVMTypeRef f16;
135 LLVMTypeRef v2f32;
136 LLVMTypeRef v4f32;
137 LLVMTypeRef v16i8;
138 LLVMTypeRef voidt;
139
140 LLVMValueRef i1true;
141 LLVMValueRef i1false;
142 LLVMValueRef i32zero;
143 LLVMValueRef i32one;
144 LLVMValueRef f32zero;
145 LLVMValueRef f32one;
146 LLVMValueRef v4f32empty;
147
148 unsigned uniform_md_kind;
149 LLVMValueRef empty_md;
150 gl_shader_stage stage;
151
152 LLVMValueRef lds;
153 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
154 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
155
156 LLVMValueRef shared_memory;
157 uint64_t input_mask;
158 uint64_t output_mask;
159 int num_locals;
160 LLVMValueRef *locals;
161 bool has_ddxy;
162 uint8_t num_output_clips;
163 uint8_t num_output_culls;
164
165 bool has_ds_bpermute;
166
167 bool is_gs_copy_shader;
168 LLVMValueRef gs_next_vertex;
169 unsigned gs_max_out_vertices;
170
171 unsigned tes_primitive_mode;
172 uint64_t tess_outputs_written;
173 uint64_t tess_patch_outputs_written;
174 };
175
176 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
177 nir_deref_var *deref,
178 enum desc_type desc_type);
179 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
180 {
181 return (index * 4) + chan;
182 }
183
184 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
185 {
186 /* handle patch indices separate */
187 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
188 return 0;
189 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
190 return 1;
191 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
192 return 2 + (slot - VARYING_SLOT_PATCH0);
193
194 if (slot == VARYING_SLOT_POS)
195 return 0;
196 if (slot == VARYING_SLOT_PSIZ)
197 return 1;
198 if (slot == VARYING_SLOT_CLIP_DIST0)
199 return 2;
200 /* 3 is reserved for clip dist as well */
201 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
202 return 4 + (slot - VARYING_SLOT_VAR0);
203 unreachable("illegal slot in get unique index\n");
204 }
205
206 static unsigned llvm_get_type_size(LLVMTypeRef type)
207 {
208 LLVMTypeKind kind = LLVMGetTypeKind(type);
209
210 switch (kind) {
211 case LLVMIntegerTypeKind:
212 return LLVMGetIntTypeWidth(type) / 8;
213 case LLVMFloatTypeKind:
214 return 4;
215 case LLVMPointerTypeKind:
216 return 8;
217 case LLVMVectorTypeKind:
218 return LLVMGetVectorSize(type) *
219 llvm_get_type_size(LLVMGetElementType(type));
220 default:
221 assert(0);
222 return 0;
223 }
224 }
225
226 static void set_llvm_calling_convention(LLVMValueRef func,
227 gl_shader_stage stage)
228 {
229 enum radeon_llvm_calling_convention calling_conv;
230
231 switch (stage) {
232 case MESA_SHADER_VERTEX:
233 case MESA_SHADER_TESS_CTRL:
234 case MESA_SHADER_TESS_EVAL:
235 calling_conv = RADEON_LLVM_AMDGPU_VS;
236 break;
237 case MESA_SHADER_GEOMETRY:
238 calling_conv = RADEON_LLVM_AMDGPU_GS;
239 break;
240 case MESA_SHADER_FRAGMENT:
241 calling_conv = RADEON_LLVM_AMDGPU_PS;
242 break;
243 case MESA_SHADER_COMPUTE:
244 calling_conv = RADEON_LLVM_AMDGPU_CS;
245 break;
246 default:
247 unreachable("Unhandle shader type");
248 }
249
250 LLVMSetFunctionCallConv(func, calling_conv);
251 }
252
253 static LLVMValueRef
254 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
255 LLVMBuilderRef builder, LLVMTypeRef *return_types,
256 unsigned num_return_elems, LLVMTypeRef *param_types,
257 unsigned param_count, unsigned array_params_mask,
258 unsigned sgpr_params, bool unsafe_math)
259 {
260 LLVMTypeRef main_function_type, ret_type;
261 LLVMBasicBlockRef main_function_body;
262
263 if (num_return_elems)
264 ret_type = LLVMStructTypeInContext(ctx, return_types,
265 num_return_elems, true);
266 else
267 ret_type = LLVMVoidTypeInContext(ctx);
268
269 /* Setup the function */
270 main_function_type =
271 LLVMFunctionType(ret_type, param_types, param_count, 0);
272 LLVMValueRef main_function =
273 LLVMAddFunction(module, "main", main_function_type);
274 main_function_body =
275 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
276 LLVMPositionBuilderAtEnd(builder, main_function_body);
277
278 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
279 for (unsigned i = 0; i < sgpr_params; ++i) {
280 if (array_params_mask & (1 << i)) {
281 LLVMValueRef P = LLVMGetParam(main_function, i);
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
283 ac_add_attr_dereferenceable(P, UINT64_MAX);
284 }
285 else {
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
287 }
288 }
289
290 if (unsafe_math) {
291 /* These were copied from some LLVM test. */
292 LLVMAddTargetDependentFunctionAttr(main_function,
293 "less-precise-fpmad",
294 "true");
295 LLVMAddTargetDependentFunctionAttr(main_function,
296 "no-infs-fp-math",
297 "true");
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "no-nans-fp-math",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "unsafe-fp-math",
303 "true");
304 }
305 return main_function;
306 }
307
308 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
309 {
310 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
311 CONST_ADDR_SPACE);
312 }
313
314 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
315 int idx,
316 LLVMTypeRef type)
317 {
318 LLVMValueRef offset;
319 LLVMValueRef ptr;
320 int addr_space;
321
322 offset = LLVMConstInt(ctx->i32, idx * 16, false);
323
324 ptr = ctx->shared_memory;
325 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
326 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
327 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
328 return ptr;
329 }
330
331 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
332 {
333 if (t == ctx->f16 || t == ctx->i16)
334 return ctx->i16;
335 else if (t == ctx->f32 || t == ctx->i32)
336 return ctx->i32;
337 else if (t == ctx->f64 || t == ctx->i64)
338 return ctx->i64;
339 else
340 unreachable("Unhandled integer size");
341 }
342
343 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
344 {
345 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
346 LLVMTypeRef elem_type = LLVMGetElementType(t);
347 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
348 LLVMGetVectorSize(t));
349 }
350 return to_integer_type_scalar(ctx, t);
351 }
352
353 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
354 {
355 LLVMTypeRef type = LLVMTypeOf(v);
356 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
357 }
358
359 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
360 {
361 if (t == ctx->i16 || t == ctx->f16)
362 return ctx->f16;
363 else if (t == ctx->i32 || t == ctx->f32)
364 return ctx->f32;
365 else if (t == ctx->i64 || t == ctx->f64)
366 return ctx->f64;
367 else
368 unreachable("Unhandled float size");
369 }
370
371 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
372 {
373 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
374 LLVMTypeRef elem_type = LLVMGetElementType(t);
375 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
376 LLVMGetVectorSize(t));
377 }
378 return to_float_type_scalar(ctx, t);
379 }
380
381 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
382 {
383 LLVMTypeRef type = LLVMTypeOf(v);
384 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
385 }
386
387 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
388 {
389 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
390 type = LLVMGetElementType(type);
391
392 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
393 return LLVMGetIntTypeWidth(type);
394
395 if (type == ctx->f16)
396 return 16;
397 if (type == ctx->f32)
398 return 32;
399 if (type == ctx->f64)
400 return 64;
401
402 unreachable("Unhandled type kind in get_elem_bits");
403 }
404
405 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
406 LLVMValueRef param, unsigned rshift,
407 unsigned bitwidth)
408 {
409 LLVMValueRef value = param;
410 if (rshift)
411 value = LLVMBuildLShr(ctx->builder, value,
412 LLVMConstInt(ctx->i32, rshift, false), "");
413
414 if (rshift + bitwidth < 32) {
415 unsigned mask = (1 << bitwidth) - 1;
416 value = LLVMBuildAnd(ctx->builder, value,
417 LLVMConstInt(ctx->i32, mask, false), "");
418 }
419 return value;
420 }
421
422 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
423 {
424 switch (ctx->stage) {
425 case MESA_SHADER_TESS_CTRL:
426 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
427 case MESA_SHADER_TESS_EVAL:
428 return ctx->tes_rel_patch_id;
429 break;
430 default:
431 unreachable("Illegal stage");
432 }
433 }
434
435 /* Tessellation shaders pass outputs to the next shader using LDS.
436 *
437 * LS outputs = TCS inputs
438 * TCS outputs = TES inputs
439 *
440 * The LDS layout is:
441 * - TCS inputs for patch 0
442 * - TCS inputs for patch 1
443 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
444 * - ...
445 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
446 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
447 * - TCS outputs for patch 1
448 * - Per-patch TCS outputs for patch 1
449 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
450 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
451 * - ...
452 *
453 * All three shaders VS(LS), TCS, TES share the same LDS space.
454 */
455 static LLVMValueRef
456 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
457 {
458 if (ctx->stage == MESA_SHADER_VERTEX)
459 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
460 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
461 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
462 else {
463 assert(0);
464 return NULL;
465 }
466 }
467
468 static LLVMValueRef
469 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
470 {
471 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
472 }
473
474 static LLVMValueRef
475 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
476 {
477 return LLVMBuildMul(ctx->builder,
478 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
479 LLVMConstInt(ctx->i32, 4, false), "");
480 }
481
482 static LLVMValueRef
483 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
484 {
485 return LLVMBuildMul(ctx->builder,
486 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
487 LLVMConstInt(ctx->i32, 4, false), "");
488 }
489
490 static LLVMValueRef
491 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
494 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
495
496 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
497 }
498
499 static LLVMValueRef
500 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
501 {
502 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
503 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
504 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
505
506 return LLVMBuildAdd(ctx->builder, patch0_offset,
507 LLVMBuildMul(ctx->builder, patch_stride,
508 rel_patch_id, ""),
509 "");
510 }
511
512 static LLVMValueRef
513 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
514 {
515 LLVMValueRef patch0_patch_data_offset =
516 get_tcs_out_patch0_patch_data_offset(ctx);
517 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
518 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
519
520 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
521 LLVMBuildMul(ctx->builder, patch_stride,
522 rel_patch_id, ""),
523 "");
524 }
525
526 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
527 {
528 ud_info->sgpr_idx = sgpr_idx;
529 ud_info->num_sgprs = num_sgprs;
530 ud_info->indirect = false;
531 ud_info->indirect_offset = 0;
532 }
533
534 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
535 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
536 {
537 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
538 }
539
540 #if 0
541 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
542 uint32_t indirect_offset)
543 {
544 ud_info->sgpr_idx = sgpr_idx;
545 ud_info->num_sgprs = num_sgprs;
546 ud_info->indirect = true;
547 ud_info->indirect_offset = indirect_offset;
548 }
549 #endif
550
551 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
552 {
553 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
554 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
555 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
556 "tess_lds");
557 }
558
559 static void create_function(struct nir_to_llvm_context *ctx)
560 {
561 LLVMTypeRef arg_types[23];
562 unsigned arg_idx = 0;
563 unsigned array_params_mask = 0;
564 unsigned sgpr_count = 0, user_sgpr_count;
565 unsigned i;
566 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
567 unsigned user_sgpr_idx;
568 bool need_push_constants;
569 bool need_ring_offsets = false;
570
571 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
572 if (ctx->stage == MESA_SHADER_GEOMETRY ||
573 ctx->stage == MESA_SHADER_VERTEX ||
574 ctx->stage == MESA_SHADER_TESS_CTRL ||
575 ctx->stage == MESA_SHADER_TESS_EVAL ||
576 ctx->is_gs_copy_shader)
577 need_ring_offsets = true;
578
579 need_push_constants = true;
580 if (!ctx->options->layout)
581 need_push_constants = false;
582 else if (!ctx->options->layout->push_constant_size &&
583 !ctx->options->layout->dynamic_offset_count)
584 need_push_constants = false;
585
586 if (need_ring_offsets && !ctx->options->supports_spill) {
587 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
588 }
589
590 /* 1 for each descriptor set */
591 for (unsigned i = 0; i < num_sets; ++i) {
592 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
593 array_params_mask |= (1 << arg_idx);
594 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
595 }
596 }
597
598 if (need_push_constants) {
599 /* 1 for push constants and dynamic descriptors */
600 array_params_mask |= (1 << arg_idx);
601 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
602 }
603
604 switch (ctx->stage) {
605 case MESA_SHADER_COMPUTE:
606 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
607 user_sgpr_count = arg_idx;
608 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
609 arg_types[arg_idx++] = ctx->i32;
610 sgpr_count = arg_idx;
611
612 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
613 break;
614 case MESA_SHADER_VERTEX:
615 if (!ctx->is_gs_copy_shader) {
616 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
617 arg_types[arg_idx++] = ctx->i32; // base vertex
618 arg_types[arg_idx++] = ctx->i32; // start instance
619 arg_types[arg_idx++] = ctx->i32; // draw index
620 }
621 user_sgpr_count = arg_idx;
622 if (ctx->options->key.vs.as_es)
623 arg_types[arg_idx++] = ctx->i32; //es2gs offset
624 else if (ctx->options->key.vs.as_ls) {
625 arg_types[arg_idx++] = ctx->i32; //ls out layout
626 user_sgpr_count++;
627 }
628 sgpr_count = arg_idx;
629 arg_types[arg_idx++] = ctx->i32; // vertex id
630 if (!ctx->is_gs_copy_shader) {
631 arg_types[arg_idx++] = ctx->i32; // rel auto id
632 arg_types[arg_idx++] = ctx->i32; // vs prim id
633 arg_types[arg_idx++] = ctx->i32; // instance id
634 }
635 break;
636 case MESA_SHADER_TESS_CTRL:
637 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
638 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
639 arg_types[arg_idx++] = ctx->i32; // tcs out layout
640 arg_types[arg_idx++] = ctx->i32; // tcs in layout
641 user_sgpr_count = arg_idx;
642 arg_types[arg_idx++] = ctx->i32; // param oc lds
643 arg_types[arg_idx++] = ctx->i32; // tess factor offset
644 sgpr_count = arg_idx;
645 arg_types[arg_idx++] = ctx->i32; // patch id
646 arg_types[arg_idx++] = ctx->i32; // rel ids;
647 break;
648 case MESA_SHADER_TESS_EVAL:
649 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
650 user_sgpr_count = arg_idx;
651 if (ctx->options->key.tes.as_es) {
652 arg_types[arg_idx++] = ctx->i32; // OC LDS
653 arg_types[arg_idx++] = ctx->i32; //
654 arg_types[arg_idx++] = ctx->i32; // es2gs offset
655 } else {
656 arg_types[arg_idx++] = ctx->i32; //
657 arg_types[arg_idx++] = ctx->i32; // OC LDS
658 }
659 sgpr_count = arg_idx;
660 arg_types[arg_idx++] = ctx->f32; // tes_u
661 arg_types[arg_idx++] = ctx->f32; // tes_v
662 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
663 arg_types[arg_idx++] = ctx->i32; // tes patch id
664 break;
665 case MESA_SHADER_GEOMETRY:
666 arg_types[arg_idx++] = ctx->i32; // gsvs stride
667 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
668 user_sgpr_count = arg_idx;
669 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
670 arg_types[arg_idx++] = ctx->i32; // wave id
671 sgpr_count = arg_idx;
672 arg_types[arg_idx++] = ctx->i32; // vtx0
673 arg_types[arg_idx++] = ctx->i32; // vtx1
674 arg_types[arg_idx++] = ctx->i32; // prim id
675 arg_types[arg_idx++] = ctx->i32; // vtx2
676 arg_types[arg_idx++] = ctx->i32; // vtx3
677 arg_types[arg_idx++] = ctx->i32; // vtx4
678 arg_types[arg_idx++] = ctx->i32; // vtx5
679 arg_types[arg_idx++] = ctx->i32; // GS instance id
680 break;
681 case MESA_SHADER_FRAGMENT:
682 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
683 user_sgpr_count = arg_idx;
684 arg_types[arg_idx++] = ctx->i32; /* prim mask */
685 sgpr_count = arg_idx;
686 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
687 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
688 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
689 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
690 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
691 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
692 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
693 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
694 arg_types[arg_idx++] = ctx->f32; /* pos x float */
695 arg_types[arg_idx++] = ctx->f32; /* pos y float */
696 arg_types[arg_idx++] = ctx->f32; /* pos z float */
697 arg_types[arg_idx++] = ctx->f32; /* pos w float */
698 arg_types[arg_idx++] = ctx->i32; /* front face */
699 arg_types[arg_idx++] = ctx->i32; /* ancillary */
700 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
701 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
702 break;
703 default:
704 unreachable("Shader stage not implemented");
705 }
706
707 ctx->main_function = create_llvm_function(
708 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
709 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
710 set_llvm_calling_convention(ctx->main_function, ctx->stage);
711
712 ctx->shader_info->num_input_sgprs = 0;
713 ctx->shader_info->num_input_vgprs = 0;
714
715 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
716 for (i = 0; i < user_sgpr_count; i++)
717 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
718
719 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
720 for (; i < sgpr_count; i++)
721 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
722
723 if (ctx->stage != MESA_SHADER_FRAGMENT)
724 for (; i < arg_idx; ++i)
725 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
726
727 arg_idx = 0;
728 user_sgpr_idx = 0;
729
730 if (ctx->options->supports_spill || need_ring_offsets) {
731 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
732 user_sgpr_idx += 2;
733 if (ctx->options->supports_spill) {
734 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
735 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
736 NULL, 0, AC_FUNC_ATTR_READNONE);
737 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
738 const_array(ctx->v16i8, 8), "");
739 } else
740 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
741 }
742
743 for (unsigned i = 0; i < num_sets; ++i) {
744 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
745 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
746 user_sgpr_idx += 2;
747 ctx->descriptor_sets[i] =
748 LLVMGetParam(ctx->main_function, arg_idx++);
749 } else
750 ctx->descriptor_sets[i] = NULL;
751 }
752
753 if (need_push_constants) {
754 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
755 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
756 user_sgpr_idx += 2;
757 }
758
759 switch (ctx->stage) {
760 case MESA_SHADER_COMPUTE:
761 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
762 user_sgpr_idx += 3;
763 ctx->num_work_groups =
764 LLVMGetParam(ctx->main_function, arg_idx++);
765 ctx->workgroup_ids =
766 LLVMGetParam(ctx->main_function, arg_idx++);
767 ctx->tg_size =
768 LLVMGetParam(ctx->main_function, arg_idx++);
769 ctx->local_invocation_ids =
770 LLVMGetParam(ctx->main_function, arg_idx++);
771 break;
772 case MESA_SHADER_VERTEX:
773 if (!ctx->is_gs_copy_shader) {
774 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
775 user_sgpr_idx += 2;
776 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
777 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
778 user_sgpr_idx += 3;
779 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
780 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
781 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
782 }
783 if (ctx->options->key.vs.as_es)
784 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
785 else if (ctx->options->key.vs.as_ls) {
786 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, user_sgpr_idx, 1);
787 user_sgpr_idx += 1;
788 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
789 }
790 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
791 if (!ctx->is_gs_copy_shader) {
792 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
793 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
794 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
795 }
796 if (ctx->options->key.vs.as_ls)
797 declare_tess_lds(ctx);
798 break;
799 case MESA_SHADER_TESS_CTRL:
800 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
801 user_sgpr_idx += 4;
802 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
803 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
804 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
805 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
806 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
807 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
808 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
809 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
810
811 declare_tess_lds(ctx);
812 break;
813 case MESA_SHADER_TESS_EVAL:
814 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
815 user_sgpr_idx += 1;
816 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
817 if (ctx->options->key.tes.as_es) {
818 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
819 arg_idx++;
820 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
821 } else {
822 arg_idx++;
823 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
824 }
825 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
826 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
827 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
828 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
829 break;
830 case MESA_SHADER_GEOMETRY:
831 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
832 user_sgpr_idx += 2;
833 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
834 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
835 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
836 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
837 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
838 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
839 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
840 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
841 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
842 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
843 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
844 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
845 break;
846 case MESA_SHADER_FRAGMENT:
847 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
848 user_sgpr_idx += 2;
849 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
850 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
851 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
852 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
853 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
854 arg_idx++;
855 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
856 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
857 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
858 arg_idx++; /* line stipple */
859 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
860 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
861 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
862 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
863 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
864 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
865 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
866 break;
867 default:
868 unreachable("Shader stage not implemented");
869 }
870 }
871
872 static void setup_types(struct nir_to_llvm_context *ctx)
873 {
874 LLVMValueRef args[4];
875
876 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
877 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
878 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
879 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
880 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
881 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
882 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
883 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
884 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
885 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
886 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
887 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
888 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
889 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
890 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
891 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
892
893 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
894 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
895 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
896 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
897 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
898 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
899
900 args[0] = ctx->f32zero;
901 args[1] = ctx->f32zero;
902 args[2] = ctx->f32zero;
903 args[3] = ctx->f32one;
904 ctx->v4f32empty = LLVMConstVector(args, 4);
905
906 ctx->uniform_md_kind =
907 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
908 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
909
910 args[0] = LLVMConstReal(ctx->f32, 2.5);
911 }
912
913 static int get_llvm_num_components(LLVMValueRef value)
914 {
915 LLVMTypeRef type = LLVMTypeOf(value);
916 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
917 ? LLVMGetVectorSize(type)
918 : 1;
919 return num_components;
920 }
921
922 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
923 LLVMValueRef value,
924 int index)
925 {
926 int count = get_llvm_num_components(value);
927
928 assert(index < count);
929 if (count == 1)
930 return value;
931
932 return LLVMBuildExtractElement(ctx->builder, value,
933 LLVMConstInt(ctx->i32, index, false), "");
934 }
935
936 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
937 LLVMValueRef value, unsigned count)
938 {
939 unsigned num_components = get_llvm_num_components(value);
940 if (count == num_components)
941 return value;
942
943 LLVMValueRef masks[] = {
944 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
945 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
946
947 if (count == 1)
948 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
949 "");
950
951 LLVMValueRef swizzle = LLVMConstVector(masks, count);
952 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
953 }
954
955 static void
956 build_store_values_extended(struct nir_to_llvm_context *ctx,
957 LLVMValueRef *values,
958 unsigned value_count,
959 unsigned value_stride,
960 LLVMValueRef vec)
961 {
962 LLVMBuilderRef builder = ctx->builder;
963 unsigned i;
964
965 if (value_count == 1) {
966 LLVMBuildStore(builder, vec, values[0]);
967 return;
968 }
969
970 for (i = 0; i < value_count; i++) {
971 LLVMValueRef ptr = values[i * value_stride];
972 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
973 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
974 LLVMBuildStore(builder, value, ptr);
975 }
976 }
977
978 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
979 nir_ssa_def *def)
980 {
981 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
982 if (def->num_components > 1) {
983 type = LLVMVectorType(type, def->num_components);
984 }
985 return type;
986 }
987
988 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
989 {
990 assert(src.is_ssa);
991 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
992 return (LLVMValueRef)entry->data;
993 }
994
995
996 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
997 struct nir_block *b)
998 {
999 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1000 return (LLVMBasicBlockRef)entry->data;
1001 }
1002
1003 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1004 nir_alu_src src,
1005 unsigned num_components)
1006 {
1007 LLVMValueRef value = get_src(ctx, src.src);
1008 bool need_swizzle = false;
1009
1010 assert(value);
1011 LLVMTypeRef type = LLVMTypeOf(value);
1012 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1013 ? LLVMGetVectorSize(type)
1014 : 1;
1015
1016 for (unsigned i = 0; i < num_components; ++i) {
1017 assert(src.swizzle[i] < src_components);
1018 if (src.swizzle[i] != i)
1019 need_swizzle = true;
1020 }
1021
1022 if (need_swizzle || num_components != src_components) {
1023 LLVMValueRef masks[] = {
1024 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1025 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1026 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1027 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1028
1029 if (src_components > 1 && num_components == 1) {
1030 value = LLVMBuildExtractElement(ctx->builder, value,
1031 masks[0], "");
1032 } else if (src_components == 1 && num_components > 1) {
1033 LLVMValueRef values[] = {value, value, value, value};
1034 value = ac_build_gather_values(&ctx->ac, values, num_components);
1035 } else {
1036 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1037 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1038 swizzle, "");
1039 }
1040 }
1041 assert(!src.negate);
1042 assert(!src.abs);
1043 return value;
1044 }
1045
1046 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
1047 LLVMIntPredicate pred, LLVMValueRef src0,
1048 LLVMValueRef src1)
1049 {
1050 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1051 return LLVMBuildSelect(ctx->builder, result,
1052 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1053 LLVMConstInt(ctx->i32, 0, false), "");
1054 }
1055
1056 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
1057 LLVMRealPredicate pred, LLVMValueRef src0,
1058 LLVMValueRef src1)
1059 {
1060 LLVMValueRef result;
1061 src0 = to_float(ctx, src0);
1062 src1 = to_float(ctx, src1);
1063 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1064 return LLVMBuildSelect(ctx->builder, result,
1065 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1066 LLVMConstInt(ctx->i32, 0, false), "");
1067 }
1068
1069 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
1070 const char *intrin,
1071 LLVMTypeRef result_type,
1072 LLVMValueRef src0)
1073 {
1074 char name[64];
1075 LLVMValueRef params[] = {
1076 to_float(ctx, src0),
1077 };
1078
1079 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1080 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1081 }
1082
1083 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
1084 const char *intrin,
1085 LLVMTypeRef result_type,
1086 LLVMValueRef src0, LLVMValueRef src1)
1087 {
1088 char name[64];
1089 LLVMValueRef params[] = {
1090 to_float(ctx, src0),
1091 to_float(ctx, src1),
1092 };
1093
1094 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1095 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1096 }
1097
1098 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
1099 const char *intrin,
1100 LLVMTypeRef result_type,
1101 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1102 {
1103 char name[64];
1104 LLVMValueRef params[] = {
1105 to_float(ctx, src0),
1106 to_float(ctx, src1),
1107 to_float(ctx, src2),
1108 };
1109
1110 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1111 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1112 }
1113
1114 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
1115 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1116 {
1117 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1118 ctx->i32zero, "");
1119 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1120 }
1121
1122 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1123 LLVMValueRef src0)
1124 {
1125 LLVMValueRef params[2] = {
1126 src0,
1127
1128 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1129 * add special code to check for x=0. The reason is that
1130 * the LLVM behavior for x=0 is different from what we
1131 * need here.
1132 *
1133 * The hardware already implements the correct behavior.
1134 */
1135 LLVMConstInt(ctx->i32, 1, false),
1136 };
1137 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1138 }
1139
1140 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1141 LLVMValueRef src0)
1142 {
1143 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1144 }
1145
1146 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1147 LLVMValueRef src0)
1148 {
1149 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1150 }
1151
1152 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1153 LLVMIntPredicate pred,
1154 LLVMValueRef src0, LLVMValueRef src1)
1155 {
1156 return LLVMBuildSelect(ctx->builder,
1157 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1158 src0,
1159 src1, "");
1160
1161 }
1162 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1163 LLVMValueRef src0)
1164 {
1165 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1166 LLVMBuildNeg(ctx->builder, src0, ""));
1167 }
1168
1169 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1170 LLVMValueRef src0)
1171 {
1172 LLVMValueRef cmp, val;
1173
1174 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1175 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1176 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1177 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1178 return val;
1179 }
1180
1181 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1182 LLVMValueRef src0)
1183 {
1184 LLVMValueRef cmp, val;
1185
1186 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1187 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1188 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1189 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1190 return val;
1191 }
1192
1193 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1194 LLVMValueRef src0)
1195 {
1196 const char *intr = "llvm.floor.f32";
1197 LLVMValueRef fsrc0 = to_float(ctx, src0);
1198 LLVMValueRef params[] = {
1199 fsrc0,
1200 };
1201 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1202 ctx->f32, params, 1,
1203 AC_FUNC_ATTR_READNONE);
1204 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1205 }
1206
1207 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1208 const char *intrin,
1209 LLVMValueRef src0, LLVMValueRef src1)
1210 {
1211 LLVMTypeRef ret_type;
1212 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1213 LLVMValueRef res;
1214 LLVMValueRef params[] = { src0, src1 };
1215 ret_type = LLVMStructTypeInContext(ctx->context, types,
1216 2, true);
1217
1218 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1219 params, 2, AC_FUNC_ATTR_READNONE);
1220
1221 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1222 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1223 return res;
1224 }
1225
1226 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1227 LLVMValueRef src0)
1228 {
1229 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1230 }
1231
1232 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1233 LLVMValueRef src0, LLVMValueRef src1)
1234 {
1235 LLVMValueRef dst64, result;
1236 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1237 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1238
1239 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1240 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1241 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1242 return result;
1243 }
1244
1245 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1246 LLVMValueRef src0, LLVMValueRef src1)
1247 {
1248 LLVMValueRef dst64, result;
1249 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1250 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1251
1252 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1253 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1254 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1255 return result;
1256 }
1257
1258 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1259 bool is_signed,
1260 LLVMValueRef srcs[3])
1261 {
1262 LLVMValueRef result;
1263 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1264
1265 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1266 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1267 return result;
1268 }
1269
1270 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1271 LLVMValueRef src0, LLVMValueRef src1,
1272 LLVMValueRef src2, LLVMValueRef src3)
1273 {
1274 LLVMValueRef bfi_args[3], result;
1275
1276 bfi_args[0] = LLVMBuildShl(ctx->builder,
1277 LLVMBuildSub(ctx->builder,
1278 LLVMBuildShl(ctx->builder,
1279 ctx->i32one,
1280 src3, ""),
1281 ctx->i32one, ""),
1282 src2, "");
1283 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1284 bfi_args[2] = src0;
1285
1286 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1287
1288 /* Calculate:
1289 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1290 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1291 */
1292 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1293 LLVMBuildAnd(ctx->builder, bfi_args[0],
1294 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1295
1296 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1297 return result;
1298 }
1299
1300 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1301 LLVMValueRef src0)
1302 {
1303 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1304 int i;
1305 LLVMValueRef comp[2];
1306
1307 src0 = to_float(ctx, src0);
1308 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1309 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1310 for (i = 0; i < 2; i++) {
1311 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1312 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1313 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1314 }
1315
1316 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1317 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1318
1319 return comp[0];
1320 }
1321
1322 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1323 LLVMValueRef src0)
1324 {
1325 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1326 LLVMValueRef temps[2], result, val;
1327 int i;
1328
1329 for (i = 0; i < 2; i++) {
1330 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1331 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1332 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1333 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1334 }
1335
1336 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1337 ctx->i32zero, "");
1338 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1339 ctx->i32one, "");
1340 return result;
1341 }
1342
1343 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1344 nir_op op,
1345 LLVMValueRef src0)
1346 {
1347 unsigned mask;
1348 int idx;
1349 LLVMValueRef result;
1350 ctx->has_ddxy = true;
1351
1352 if (!ctx->lds && !ctx->has_ds_bpermute)
1353 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1354 LLVMArrayType(ctx->i32, 64),
1355 "ddxy_lds", LOCAL_ADDR_SPACE);
1356
1357 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1358 mask = AC_TID_MASK_LEFT;
1359 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1360 mask = AC_TID_MASK_TOP;
1361 else
1362 mask = AC_TID_MASK_TOP_LEFT;
1363
1364 /* for DDX we want to next X pixel, DDY next Y pixel. */
1365 if (op == nir_op_fddx_fine ||
1366 op == nir_op_fddx_coarse ||
1367 op == nir_op_fddx)
1368 idx = 1;
1369 else
1370 idx = 2;
1371
1372 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1373 mask, idx, ctx->lds,
1374 src0);
1375 return result;
1376 }
1377
1378 /*
1379 * this takes an I,J coordinate pair,
1380 * and works out the X and Y derivatives.
1381 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1382 */
1383 static LLVMValueRef emit_ddxy_interp(
1384 struct nir_to_llvm_context *ctx,
1385 LLVMValueRef interp_ij)
1386 {
1387 LLVMValueRef result[4], a;
1388 unsigned i;
1389
1390 for (i = 0; i < 2; i++) {
1391 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1392 LLVMConstInt(ctx->i32, i, false), "");
1393 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1394 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1395 }
1396 return ac_build_gather_values(&ctx->ac, result, 4);
1397 }
1398
1399 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1400 {
1401 LLVMValueRef src[4], result = NULL;
1402 unsigned num_components = instr->dest.dest.ssa.num_components;
1403 unsigned src_components;
1404 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1405
1406 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1407 switch (instr->op) {
1408 case nir_op_vec2:
1409 case nir_op_vec3:
1410 case nir_op_vec4:
1411 src_components = 1;
1412 break;
1413 case nir_op_pack_half_2x16:
1414 src_components = 2;
1415 break;
1416 case nir_op_unpack_half_2x16:
1417 src_components = 1;
1418 break;
1419 default:
1420 src_components = num_components;
1421 break;
1422 }
1423 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1424 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1425
1426 switch (instr->op) {
1427 case nir_op_fmov:
1428 case nir_op_imov:
1429 result = src[0];
1430 break;
1431 case nir_op_fneg:
1432 src[0] = to_float(ctx, src[0]);
1433 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1434 break;
1435 case nir_op_ineg:
1436 result = LLVMBuildNeg(ctx->builder, src[0], "");
1437 break;
1438 case nir_op_inot:
1439 result = LLVMBuildNot(ctx->builder, src[0], "");
1440 break;
1441 case nir_op_iadd:
1442 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1443 break;
1444 case nir_op_fadd:
1445 src[0] = to_float(ctx, src[0]);
1446 src[1] = to_float(ctx, src[1]);
1447 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1448 break;
1449 case nir_op_fsub:
1450 src[0] = to_float(ctx, src[0]);
1451 src[1] = to_float(ctx, src[1]);
1452 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1453 break;
1454 case nir_op_isub:
1455 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1456 break;
1457 case nir_op_imul:
1458 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1459 break;
1460 case nir_op_imod:
1461 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1462 break;
1463 case nir_op_umod:
1464 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1465 break;
1466 case nir_op_fmod:
1467 src[0] = to_float(ctx, src[0]);
1468 src[1] = to_float(ctx, src[1]);
1469 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1470 result = emit_intrin_1f_param(ctx, "llvm.floor",
1471 to_float_type(ctx, def_type), result);
1472 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1473 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1474 break;
1475 case nir_op_frem:
1476 src[0] = to_float(ctx, src[0]);
1477 src[1] = to_float(ctx, src[1]);
1478 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1479 break;
1480 case nir_op_irem:
1481 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1482 break;
1483 case nir_op_idiv:
1484 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1485 break;
1486 case nir_op_udiv:
1487 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1488 break;
1489 case nir_op_fmul:
1490 src[0] = to_float(ctx, src[0]);
1491 src[1] = to_float(ctx, src[1]);
1492 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1493 break;
1494 case nir_op_fdiv:
1495 src[0] = to_float(ctx, src[0]);
1496 src[1] = to_float(ctx, src[1]);
1497 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1498 break;
1499 case nir_op_frcp:
1500 src[0] = to_float(ctx, src[0]);
1501 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1502 break;
1503 case nir_op_iand:
1504 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1505 break;
1506 case nir_op_ior:
1507 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1508 break;
1509 case nir_op_ixor:
1510 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1511 break;
1512 case nir_op_ishl:
1513 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1514 break;
1515 case nir_op_ishr:
1516 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1517 break;
1518 case nir_op_ushr:
1519 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1520 break;
1521 case nir_op_ilt:
1522 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1523 break;
1524 case nir_op_ine:
1525 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1526 break;
1527 case nir_op_ieq:
1528 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1529 break;
1530 case nir_op_ige:
1531 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1532 break;
1533 case nir_op_ult:
1534 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1535 break;
1536 case nir_op_uge:
1537 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1538 break;
1539 case nir_op_feq:
1540 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1541 break;
1542 case nir_op_fne:
1543 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1544 break;
1545 case nir_op_flt:
1546 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1547 break;
1548 case nir_op_fge:
1549 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1550 break;
1551 case nir_op_fabs:
1552 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1553 to_float_type(ctx, def_type), src[0]);
1554 break;
1555 case nir_op_iabs:
1556 result = emit_iabs(ctx, src[0]);
1557 break;
1558 case nir_op_imax:
1559 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1560 break;
1561 case nir_op_imin:
1562 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1563 break;
1564 case nir_op_umax:
1565 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1566 break;
1567 case nir_op_umin:
1568 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1569 break;
1570 case nir_op_isign:
1571 result = emit_isign(ctx, src[0]);
1572 break;
1573 case nir_op_fsign:
1574 src[0] = to_float(ctx, src[0]);
1575 result = emit_fsign(ctx, src[0]);
1576 break;
1577 case nir_op_ffloor:
1578 result = emit_intrin_1f_param(ctx, "llvm.floor",
1579 to_float_type(ctx, def_type), src[0]);
1580 break;
1581 case nir_op_ftrunc:
1582 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1583 to_float_type(ctx, def_type), src[0]);
1584 break;
1585 case nir_op_fceil:
1586 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1587 to_float_type(ctx, def_type), src[0]);
1588 break;
1589 case nir_op_fround_even:
1590 result = emit_intrin_1f_param(ctx, "llvm.rint",
1591 to_float_type(ctx, def_type),src[0]);
1592 break;
1593 case nir_op_ffract:
1594 result = emit_ffract(ctx, src[0]);
1595 break;
1596 case nir_op_fsin:
1597 result = emit_intrin_1f_param(ctx, "llvm.sin",
1598 to_float_type(ctx, def_type), src[0]);
1599 break;
1600 case nir_op_fcos:
1601 result = emit_intrin_1f_param(ctx, "llvm.cos",
1602 to_float_type(ctx, def_type), src[0]);
1603 break;
1604 case nir_op_fsqrt:
1605 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1606 to_float_type(ctx, def_type), src[0]);
1607 break;
1608 case nir_op_fexp2:
1609 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1610 to_float_type(ctx, def_type), src[0]);
1611 break;
1612 case nir_op_flog2:
1613 result = emit_intrin_1f_param(ctx, "llvm.log2",
1614 to_float_type(ctx, def_type), src[0]);
1615 break;
1616 case nir_op_frsq:
1617 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1618 to_float_type(ctx, def_type), src[0]);
1619 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1620 break;
1621 case nir_op_fpow:
1622 result = emit_intrin_2f_param(ctx, "llvm.pow",
1623 to_float_type(ctx, def_type), src[0], src[1]);
1624 break;
1625 case nir_op_fmax:
1626 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1627 to_float_type(ctx, def_type), src[0], src[1]);
1628 break;
1629 case nir_op_fmin:
1630 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1631 to_float_type(ctx, def_type), src[0], src[1]);
1632 break;
1633 case nir_op_ffma:
1634 result = emit_intrin_3f_param(ctx, "llvm.fma",
1635 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1636 break;
1637 case nir_op_ibitfield_extract:
1638 result = emit_bitfield_extract(ctx, true, src);
1639 break;
1640 case nir_op_ubitfield_extract:
1641 result = emit_bitfield_extract(ctx, false, src);
1642 break;
1643 case nir_op_bitfield_insert:
1644 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1645 break;
1646 case nir_op_bitfield_reverse:
1647 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1648 break;
1649 case nir_op_bit_count:
1650 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1651 break;
1652 case nir_op_vec2:
1653 case nir_op_vec3:
1654 case nir_op_vec4:
1655 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1656 src[i] = to_integer(ctx, src[i]);
1657 result = ac_build_gather_values(&ctx->ac, src, num_components);
1658 break;
1659 case nir_op_f2i32:
1660 case nir_op_f2i64:
1661 src[0] = to_float(ctx, src[0]);
1662 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1663 break;
1664 case nir_op_f2u32:
1665 case nir_op_f2u64:
1666 src[0] = to_float(ctx, src[0]);
1667 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1668 break;
1669 case nir_op_i2f32:
1670 case nir_op_i2f64:
1671 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1672 break;
1673 case nir_op_u2f32:
1674 case nir_op_u2f64:
1675 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1676 break;
1677 case nir_op_f2f64:
1678 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1679 break;
1680 case nir_op_f2f32:
1681 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1682 break;
1683 case nir_op_u2u32:
1684 case nir_op_u2u64:
1685 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1686 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1687 else
1688 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1689 break;
1690 case nir_op_i2i32:
1691 case nir_op_i2i64:
1692 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1693 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1694 else
1695 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1696 break;
1697 case nir_op_bcsel:
1698 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1699 break;
1700 case nir_op_find_lsb:
1701 result = emit_find_lsb(ctx, src[0]);
1702 break;
1703 case nir_op_ufind_msb:
1704 result = emit_ufind_msb(ctx, src[0]);
1705 break;
1706 case nir_op_ifind_msb:
1707 result = emit_ifind_msb(ctx, src[0]);
1708 break;
1709 case nir_op_uadd_carry:
1710 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1711 break;
1712 case nir_op_usub_borrow:
1713 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1714 break;
1715 case nir_op_b2f:
1716 result = emit_b2f(ctx, src[0]);
1717 break;
1718 case nir_op_fquantize2f16:
1719 src[0] = to_float(ctx, src[0]);
1720 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1721 /* need to convert back up to f32 */
1722 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1723 break;
1724 case nir_op_umul_high:
1725 result = emit_umul_high(ctx, src[0], src[1]);
1726 break;
1727 case nir_op_imul_high:
1728 result = emit_imul_high(ctx, src[0], src[1]);
1729 break;
1730 case nir_op_pack_half_2x16:
1731 result = emit_pack_half_2x16(ctx, src[0]);
1732 break;
1733 case nir_op_unpack_half_2x16:
1734 result = emit_unpack_half_2x16(ctx, src[0]);
1735 break;
1736 case nir_op_fddx:
1737 case nir_op_fddy:
1738 case nir_op_fddx_fine:
1739 case nir_op_fddy_fine:
1740 case nir_op_fddx_coarse:
1741 case nir_op_fddy_coarse:
1742 result = emit_ddxy(ctx, instr->op, src[0]);
1743 break;
1744 default:
1745 fprintf(stderr, "Unknown NIR alu instr: ");
1746 nir_print_instr(&instr->instr, stderr);
1747 fprintf(stderr, "\n");
1748 abort();
1749 }
1750
1751 if (result) {
1752 assert(instr->dest.dest.is_ssa);
1753 result = to_integer(ctx, result);
1754 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1755 result);
1756 }
1757 }
1758
1759 static void visit_load_const(struct nir_to_llvm_context *ctx,
1760 nir_load_const_instr *instr)
1761 {
1762 LLVMValueRef values[4], value = NULL;
1763 LLVMTypeRef element_type =
1764 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1765
1766 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1767 switch (instr->def.bit_size) {
1768 case 32:
1769 values[i] = LLVMConstInt(element_type,
1770 instr->value.u32[i], false);
1771 break;
1772 case 64:
1773 values[i] = LLVMConstInt(element_type,
1774 instr->value.u64[i], false);
1775 break;
1776 default:
1777 fprintf(stderr,
1778 "unsupported nir load_const bit_size: %d\n",
1779 instr->def.bit_size);
1780 abort();
1781 }
1782 }
1783 if (instr->def.num_components > 1) {
1784 value = LLVMConstVector(values, instr->def.num_components);
1785 } else
1786 value = values[0];
1787
1788 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1789 }
1790
1791 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1792 LLVMTypeRef type)
1793 {
1794 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1795 return LLVMBuildBitCast(ctx->builder, ptr,
1796 LLVMPointerType(type, addr_space), "");
1797 }
1798
1799 static LLVMValueRef
1800 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1801 {
1802 LLVMValueRef size =
1803 LLVMBuildExtractElement(ctx->builder, descriptor,
1804 LLVMConstInt(ctx->i32, 2, false), "");
1805
1806 /* VI only */
1807 if (ctx->options->chip_class >= VI && in_elements) {
1808 /* On VI, the descriptor contains the size in bytes,
1809 * but TXQ must return the size in elements.
1810 * The stride is always non-zero for resources using TXQ.
1811 */
1812 LLVMValueRef stride =
1813 LLVMBuildExtractElement(ctx->builder, descriptor,
1814 LLVMConstInt(ctx->i32, 1, false), "");
1815 stride = LLVMBuildLShr(ctx->builder, stride,
1816 LLVMConstInt(ctx->i32, 16, false), "");
1817 stride = LLVMBuildAnd(ctx->builder, stride,
1818 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1819
1820 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1821 }
1822 return size;
1823 }
1824
1825 /**
1826 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1827 * intrinsic names).
1828 */
1829 static void build_int_type_name(
1830 LLVMTypeRef type,
1831 char *buf, unsigned bufsize)
1832 {
1833 assert(bufsize >= 6);
1834
1835 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1836 snprintf(buf, bufsize, "v%ui32",
1837 LLVMGetVectorSize(type));
1838 else
1839 strcpy(buf, "i32");
1840 }
1841
1842 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1843 struct ac_image_args *args,
1844 nir_tex_instr *instr)
1845 {
1846 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1847 LLVMValueRef coord = args->addr;
1848 LLVMValueRef half_texel[2];
1849 LLVMValueRef compare_cube_wa;
1850 LLVMValueRef result;
1851 int c;
1852 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1853
1854 //TODO Rect
1855 {
1856 struct ac_image_args txq_args = { 0 };
1857
1858 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1859 txq_args.opcode = ac_image_get_resinfo;
1860 txq_args.dmask = 0xf;
1861 txq_args.addr = ctx->i32zero;
1862 txq_args.resource = args->resource;
1863 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1864
1865 for (c = 0; c < 2; c++) {
1866 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1867 LLVMConstInt(ctx->i32, c, false), "");
1868 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1869 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1870 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1871 LLVMConstReal(ctx->f32, -0.5), "");
1872 }
1873 }
1874
1875 LLVMValueRef orig_coords = args->addr;
1876
1877 for (c = 0; c < 2; c++) {
1878 LLVMValueRef tmp;
1879 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1880 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1881 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1882 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1883 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1884 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1885 }
1886
1887
1888 /*
1889 * Apparantly cube has issue with integer types that the workaround doesn't solve,
1890 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
1891 * workaround by sampling using a scaled type and converting.
1892 * This is taken from amdgpu-pro shaders.
1893 */
1894 /* NOTE this produces some ugly code compared to amdgpu-pro,
1895 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
1896 * and then reads them back. -pro generates two selects,
1897 * one s_cmp for the descriptor rewriting
1898 * one v_cmp for the coordinate and result changes.
1899 */
1900 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1901 LLVMValueRef tmp, tmp2;
1902
1903 /* workaround 8/8/8/8 uint/sint cube gather bug */
1904 /* first detect it then change to a scaled read and f2i */
1905 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
1906 tmp2 = tmp;
1907
1908 /* extract the DATA_FORMAT */
1909 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
1910 LLVMConstInt(ctx->i32, 6, false), false);
1911
1912 /* is the DATA_FORMAT == 8_8_8_8 */
1913 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
1914
1915 if (stype == GLSL_TYPE_UINT)
1916 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
1917 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
1918 LLVMConstInt(ctx->i32, 0x10000000, false), "");
1919 else
1920 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
1921 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
1922 LLVMConstInt(ctx->i32, 0x14000000, false), "");
1923
1924 /* replace the NUM FORMAT in the descriptor */
1925 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
1926 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
1927
1928 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
1929
1930 /* don't modify the coordinates for this case */
1931 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
1932 }
1933 args->addr = coord;
1934 result = ac_build_image_opcode(&ctx->ac, args);
1935
1936 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1937 LLVMValueRef tmp, tmp2;
1938
1939 /* if the cube workaround is in place, f2i the result. */
1940 for (c = 0; c < 4; c++) {
1941 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
1942 if (stype == GLSL_TYPE_UINT)
1943 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
1944 else
1945 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
1946 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1947 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
1948 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
1949 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1950 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
1951 }
1952 }
1953 return result;
1954 }
1955
1956 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1957 nir_tex_instr *instr,
1958 struct ac_image_args *args)
1959 {
1960 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
1961 return ac_build_buffer_load_format(&ctx->ac,
1962 args->resource,
1963 args->addr,
1964 LLVMConstInt(ctx->i32, 0, false),
1965 true);
1966 }
1967
1968 args->opcode = ac_image_sample;
1969 args->compare = instr->is_shadow;
1970
1971 switch (instr->op) {
1972 case nir_texop_txf:
1973 case nir_texop_txf_ms:
1974 case nir_texop_samples_identical:
1975 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
1976 args->compare = false;
1977 args->offset = false;
1978 break;
1979 case nir_texop_txb:
1980 args->bias = true;
1981 break;
1982 case nir_texop_txl:
1983 args->lod = true;
1984 break;
1985 case nir_texop_txs:
1986 case nir_texop_query_levels:
1987 args->opcode = ac_image_get_resinfo;
1988 break;
1989 case nir_texop_tex:
1990 if (ctx->stage != MESA_SHADER_FRAGMENT)
1991 args->level_zero = true;
1992 break;
1993 case nir_texop_txd:
1994 args->deriv = true;
1995 break;
1996 case nir_texop_tg4:
1997 args->opcode = ac_image_gather4;
1998 args->level_zero = true;
1999 break;
2000 case nir_texop_lod:
2001 args->opcode = ac_image_get_lod;
2002 args->compare = false;
2003 args->offset = false;
2004 break;
2005 default:
2006 break;
2007 }
2008
2009 if (instr->op == nir_texop_tg4) {
2010 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2011 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2012 return radv_lower_gather4_integer(ctx, args, instr);
2013 }
2014 }
2015 return ac_build_image_opcode(&ctx->ac, args);
2016 }
2017
2018 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2019 nir_intrinsic_instr *instr)
2020 {
2021 LLVMValueRef index = get_src(ctx, instr->src[0]);
2022 unsigned desc_set = nir_intrinsic_desc_set(instr);
2023 unsigned binding = nir_intrinsic_binding(instr);
2024 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2025 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2026 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2027 unsigned base_offset = layout->binding[binding].offset;
2028 LLVMValueRef offset, stride;
2029
2030 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2031 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2032 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2033 layout->binding[binding].dynamic_offset_offset;
2034 desc_ptr = ctx->push_constants;
2035 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2036 stride = LLVMConstInt(ctx->i32, 16, false);
2037 } else
2038 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2039
2040 offset = LLVMConstInt(ctx->i32, base_offset, false);
2041 index = LLVMBuildMul(ctx->builder, index, stride, "");
2042 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2043
2044 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2045 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2046 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2047
2048 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2049 }
2050
2051 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2052 nir_intrinsic_instr *instr)
2053 {
2054 LLVMValueRef ptr, addr;
2055
2056 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2057 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2058
2059 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2060 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2061
2062 return LLVMBuildLoad(ctx->builder, ptr, "");
2063 }
2064
2065 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2066 nir_intrinsic_instr *instr)
2067 {
2068 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2069
2070 return get_buffer_size(ctx, desc, false);
2071 }
2072 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2073 nir_intrinsic_instr *instr)
2074 {
2075 const char *store_name;
2076 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2077 LLVMTypeRef data_type = ctx->f32;
2078 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2079 int components_32bit = elem_size_mult * instr->num_components;
2080 unsigned writemask = nir_intrinsic_write_mask(instr);
2081 LLVMValueRef base_data, base_offset;
2082 LLVMValueRef params[6];
2083
2084 if (ctx->stage == MESA_SHADER_FRAGMENT)
2085 ctx->shader_info->fs.writes_memory = true;
2086
2087 params[1] = get_src(ctx, instr->src[1]);
2088 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2089 params[4] = ctx->i1false; /* glc */
2090 params[5] = ctx->i1false; /* slc */
2091
2092 if (components_32bit > 1)
2093 data_type = LLVMVectorType(ctx->f32, components_32bit);
2094
2095 base_data = to_float(ctx, src_data);
2096 base_data = trim_vector(ctx, base_data, instr->num_components);
2097 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2098 data_type, "");
2099 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2100 while (writemask) {
2101 int start, count;
2102 LLVMValueRef data;
2103 LLVMValueRef offset;
2104 LLVMValueRef tmp;
2105 u_bit_scan_consecutive_range(&writemask, &start, &count);
2106
2107 /* Due to an LLVM limitation, split 3-element writes
2108 * into a 2-element and a 1-element write. */
2109 if (count == 3) {
2110 writemask |= 1 << (start + 2);
2111 count = 2;
2112 }
2113
2114 start *= elem_size_mult;
2115 count *= elem_size_mult;
2116
2117 if (count > 4) {
2118 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2119 count = 4;
2120 }
2121
2122 if (count == 4) {
2123 store_name = "llvm.amdgcn.buffer.store.v4f32";
2124 data = base_data;
2125 } else if (count == 2) {
2126 tmp = LLVMBuildExtractElement(ctx->builder,
2127 base_data, LLVMConstInt(ctx->i32, start, false), "");
2128 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2129 ctx->i32zero, "");
2130
2131 tmp = LLVMBuildExtractElement(ctx->builder,
2132 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2133 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2134 ctx->i32one, "");
2135 store_name = "llvm.amdgcn.buffer.store.v2f32";
2136
2137 } else {
2138 assert(count == 1);
2139 if (get_llvm_num_components(base_data) > 1)
2140 data = LLVMBuildExtractElement(ctx->builder, base_data,
2141 LLVMConstInt(ctx->i32, start, false), "");
2142 else
2143 data = base_data;
2144 store_name = "llvm.amdgcn.buffer.store.f32";
2145 }
2146
2147 offset = base_offset;
2148 if (start != 0) {
2149 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2150 }
2151 params[0] = data;
2152 params[3] = offset;
2153 ac_build_intrinsic(&ctx->ac, store_name,
2154 ctx->voidt, params, 6, 0);
2155 }
2156 }
2157
2158 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2159 nir_intrinsic_instr *instr)
2160 {
2161 const char *name;
2162 LLVMValueRef params[6];
2163 int arg_count = 0;
2164 if (ctx->stage == MESA_SHADER_FRAGMENT)
2165 ctx->shader_info->fs.writes_memory = true;
2166
2167 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2168 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2169 }
2170 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2171 params[arg_count++] = get_src(ctx, instr->src[0]);
2172 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2173 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2174 params[arg_count++] = ctx->i1false; /* slc */
2175
2176 switch (instr->intrinsic) {
2177 case nir_intrinsic_ssbo_atomic_add:
2178 name = "llvm.amdgcn.buffer.atomic.add";
2179 break;
2180 case nir_intrinsic_ssbo_atomic_imin:
2181 name = "llvm.amdgcn.buffer.atomic.smin";
2182 break;
2183 case nir_intrinsic_ssbo_atomic_umin:
2184 name = "llvm.amdgcn.buffer.atomic.umin";
2185 break;
2186 case nir_intrinsic_ssbo_atomic_imax:
2187 name = "llvm.amdgcn.buffer.atomic.smax";
2188 break;
2189 case nir_intrinsic_ssbo_atomic_umax:
2190 name = "llvm.amdgcn.buffer.atomic.umax";
2191 break;
2192 case nir_intrinsic_ssbo_atomic_and:
2193 name = "llvm.amdgcn.buffer.atomic.and";
2194 break;
2195 case nir_intrinsic_ssbo_atomic_or:
2196 name = "llvm.amdgcn.buffer.atomic.or";
2197 break;
2198 case nir_intrinsic_ssbo_atomic_xor:
2199 name = "llvm.amdgcn.buffer.atomic.xor";
2200 break;
2201 case nir_intrinsic_ssbo_atomic_exchange:
2202 name = "llvm.amdgcn.buffer.atomic.swap";
2203 break;
2204 case nir_intrinsic_ssbo_atomic_comp_swap:
2205 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2206 break;
2207 default:
2208 abort();
2209 }
2210
2211 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2212 }
2213
2214 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2215 nir_intrinsic_instr *instr)
2216 {
2217 LLVMValueRef results[2];
2218 int load_components;
2219 int num_components = instr->num_components;
2220 if (instr->dest.ssa.bit_size == 64)
2221 num_components *= 2;
2222
2223 for (int i = 0; i < num_components; i += load_components) {
2224 load_components = MIN2(num_components - i, 4);
2225 const char *load_name;
2226 LLVMTypeRef data_type = ctx->f32;
2227 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2228 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2229
2230 if (load_components == 3)
2231 data_type = LLVMVectorType(ctx->f32, 4);
2232 else if (load_components > 1)
2233 data_type = LLVMVectorType(ctx->f32, load_components);
2234
2235 if (load_components >= 3)
2236 load_name = "llvm.amdgcn.buffer.load.v4f32";
2237 else if (load_components == 2)
2238 load_name = "llvm.amdgcn.buffer.load.v2f32";
2239 else if (load_components == 1)
2240 load_name = "llvm.amdgcn.buffer.load.f32";
2241 else
2242 unreachable("unhandled number of components");
2243
2244 LLVMValueRef params[] = {
2245 get_src(ctx, instr->src[0]),
2246 LLVMConstInt(ctx->i32, 0, false),
2247 offset,
2248 ctx->i1false,
2249 ctx->i1false,
2250 };
2251
2252 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2253
2254 }
2255
2256 LLVMValueRef ret = results[0];
2257 if (num_components > 4 || num_components == 3) {
2258 LLVMValueRef masks[] = {
2259 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2260 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2261 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2262 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2263 };
2264
2265 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2266 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2267 results[num_components > 4 ? 1 : 0], swizzle, "");
2268 }
2269
2270 return LLVMBuildBitCast(ctx->builder, ret,
2271 get_def_type(ctx, &instr->dest.ssa), "");
2272 }
2273
2274 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2275 nir_intrinsic_instr *instr)
2276 {
2277 LLVMValueRef results[8], ret;
2278 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2279 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2280 int num_components = instr->num_components;
2281
2282 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2283
2284 if (instr->dest.ssa.bit_size == 64)
2285 num_components *= 2;
2286
2287 for (unsigned i = 0; i < num_components; ++i) {
2288 LLVMValueRef params[] = {
2289 rsrc,
2290 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2291 offset, "")
2292 };
2293 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2294 params, 2,
2295 AC_FUNC_ATTR_READNONE |
2296 AC_FUNC_ATTR_LEGACY);
2297 }
2298
2299
2300 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2301 return LLVMBuildBitCast(ctx->builder, ret,
2302 get_def_type(ctx, &instr->dest.ssa), "");
2303 }
2304
2305 static void
2306 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2307 bool vs_in, unsigned *vertex_index_out,
2308 LLVMValueRef *vertex_index_ref,
2309 unsigned *const_out, LLVMValueRef *indir_out)
2310 {
2311 unsigned const_offset = 0;
2312 nir_deref *tail = &deref->deref;
2313 LLVMValueRef offset = NULL;
2314
2315 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2316 tail = tail->child;
2317 nir_deref_array *deref_array = nir_deref_as_array(tail);
2318 if (vertex_index_out)
2319 *vertex_index_out = deref_array->base_offset;
2320
2321 if (vertex_index_ref) {
2322 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2323 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2324 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2325 }
2326 *vertex_index_ref = vtx;
2327 }
2328 }
2329
2330 if (deref->var->data.compact) {
2331 assert(tail->child->deref_type == nir_deref_type_array);
2332 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2333 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2334 /* We always lower indirect dereferences for "compact" array vars. */
2335 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2336
2337 const_offset = deref_array->base_offset;
2338 goto out;
2339 }
2340
2341 while (tail->child != NULL) {
2342 const struct glsl_type *parent_type = tail->type;
2343 tail = tail->child;
2344
2345 if (tail->deref_type == nir_deref_type_array) {
2346 nir_deref_array *deref_array = nir_deref_as_array(tail);
2347 LLVMValueRef index, stride, local_offset;
2348 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2349
2350 const_offset += size * deref_array->base_offset;
2351 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2352 continue;
2353
2354 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2355 index = get_src(ctx, deref_array->indirect);
2356 stride = LLVMConstInt(ctx->i32, size, 0);
2357 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2358
2359 if (offset)
2360 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2361 else
2362 offset = local_offset;
2363 } else if (tail->deref_type == nir_deref_type_struct) {
2364 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2365
2366 for (unsigned i = 0; i < deref_struct->index; i++) {
2367 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2368 const_offset += glsl_count_attribute_slots(ft, vs_in);
2369 }
2370 } else
2371 unreachable("unsupported deref type");
2372
2373 }
2374 out:
2375 if (const_offset && offset)
2376 offset = LLVMBuildAdd(ctx->builder, offset,
2377 LLVMConstInt(ctx->i32, const_offset, 0),
2378 "");
2379
2380 *const_out = const_offset;
2381 *indir_out = offset;
2382 }
2383
2384 static LLVMValueRef
2385 lds_load(struct nir_to_llvm_context *ctx,
2386 LLVMValueRef dw_addr)
2387 {
2388 LLVMValueRef value;
2389 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2390 return value;
2391 }
2392
2393 static void
2394 lds_store(struct nir_to_llvm_context *ctx,
2395 LLVMValueRef dw_addr, LLVMValueRef value)
2396 {
2397 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2398 ac_build_indexed_store(&ctx->ac, ctx->lds,
2399 dw_addr, value);
2400 }
2401
2402 /* The offchip buffer layout for TCS->TES is
2403 *
2404 * - attribute 0 of patch 0 vertex 0
2405 * - attribute 0 of patch 0 vertex 1
2406 * - attribute 0 of patch 0 vertex 2
2407 * ...
2408 * - attribute 0 of patch 1 vertex 0
2409 * - attribute 0 of patch 1 vertex 1
2410 * ...
2411 * - attribute 1 of patch 0 vertex 0
2412 * - attribute 1 of patch 0 vertex 1
2413 * ...
2414 * - per patch attribute 0 of patch 0
2415 * - per patch attribute 0 of patch 1
2416 * ...
2417 *
2418 * Note that every attribute has 4 components.
2419 */
2420 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2421 LLVMValueRef vertex_index,
2422 LLVMValueRef param_index)
2423 {
2424 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2425 LLVMValueRef param_stride, constant16;
2426 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2427
2428 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2429 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2430 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2431 num_patches, "");
2432
2433 constant16 = LLVMConstInt(ctx->i32, 16, false);
2434 if (vertex_index) {
2435 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2436 vertices_per_patch, "");
2437
2438 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2439 vertex_index, "");
2440
2441 param_stride = total_vertices;
2442 } else {
2443 base_addr = rel_patch_id;
2444 param_stride = num_patches;
2445 }
2446
2447 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2448 LLVMBuildMul(ctx->builder, param_index,
2449 param_stride, ""), "");
2450
2451 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2452
2453 if (!vertex_index) {
2454 LLVMValueRef patch_data_offset =
2455 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2456
2457 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2458 patch_data_offset, "");
2459 }
2460 return base_addr;
2461 }
2462
2463 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2464 unsigned param,
2465 unsigned const_index,
2466 bool is_compact,
2467 LLVMValueRef vertex_index,
2468 LLVMValueRef indir_index)
2469 {
2470 LLVMValueRef param_index;
2471
2472 if (indir_index)
2473 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2474 indir_index, "");
2475 else {
2476 if (const_index && !is_compact)
2477 param += const_index;
2478 param_index = LLVMConstInt(ctx->i32, param, false);
2479 }
2480 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2481 }
2482
2483 static void
2484 mark_tess_output(struct nir_to_llvm_context *ctx,
2485 bool is_patch, uint32_t param)
2486
2487 {
2488 if (is_patch) {
2489 ctx->tess_patch_outputs_written |= (1ull << param);
2490 } else
2491 ctx->tess_outputs_written |= (1ull << param);
2492 }
2493
2494 static LLVMValueRef
2495 get_dw_address(struct nir_to_llvm_context *ctx,
2496 LLVMValueRef dw_addr,
2497 unsigned param,
2498 unsigned const_index,
2499 bool compact_const_index,
2500 LLVMValueRef vertex_index,
2501 LLVMValueRef stride,
2502 LLVMValueRef indir_index)
2503
2504 {
2505
2506 if (vertex_index) {
2507 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2508 LLVMBuildMul(ctx->builder,
2509 vertex_index,
2510 stride, ""), "");
2511 }
2512
2513 if (indir_index)
2514 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2515 LLVMBuildMul(ctx->builder, indir_index,
2516 LLVMConstInt(ctx->i32, 4, false), ""), "");
2517 else if (const_index && !compact_const_index)
2518 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2519 LLVMConstInt(ctx->i32, const_index, false), "");
2520
2521 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2522 LLVMConstInt(ctx->i32, param * 4, false), "");
2523
2524 if (const_index && compact_const_index)
2525 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2526 LLVMConstInt(ctx->i32, const_index, false), "");
2527 return dw_addr;
2528 }
2529
2530 static LLVMValueRef
2531 load_tcs_input(struct nir_to_llvm_context *ctx,
2532 nir_intrinsic_instr *instr)
2533 {
2534 LLVMValueRef dw_addr, stride;
2535 unsigned const_index;
2536 LLVMValueRef vertex_index;
2537 LLVMValueRef indir_index;
2538 unsigned param;
2539 LLVMValueRef value[4], result;
2540 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2541 const bool is_compact = instr->variables[0]->var->data.compact;
2542 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2543 radv_get_deref_offset(ctx, instr->variables[0],
2544 false, NULL, per_vertex ? &vertex_index : NULL,
2545 &const_index, &indir_index);
2546
2547 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2548 dw_addr = get_tcs_in_current_patch_offset(ctx);
2549 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2550 indir_index);
2551
2552 for (unsigned i = 0; i < instr->num_components; i++) {
2553 value[i] = lds_load(ctx, dw_addr);
2554 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2555 ctx->i32one, "");
2556 }
2557 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2558 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2559 return result;
2560 }
2561
2562 static LLVMValueRef
2563 load_tcs_output(struct nir_to_llvm_context *ctx,
2564 nir_intrinsic_instr *instr)
2565 {
2566 LLVMValueRef dw_addr, stride;
2567 LLVMValueRef value[4], result;
2568 LLVMValueRef vertex_index = NULL;
2569 LLVMValueRef indir_index = NULL;
2570 unsigned const_index = 0;
2571 unsigned param;
2572 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2573 const bool is_compact = instr->variables[0]->var->data.compact;
2574 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2575 radv_get_deref_offset(ctx, instr->variables[0],
2576 false, NULL, per_vertex ? &vertex_index : NULL,
2577 &const_index, &indir_index);
2578
2579 if (!instr->variables[0]->var->data.patch) {
2580 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2581 dw_addr = get_tcs_out_current_patch_offset(ctx);
2582 } else {
2583 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2584 }
2585
2586 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2587 indir_index);
2588
2589 for (unsigned i = 0; i < instr->num_components; i++) {
2590 value[i] = lds_load(ctx, dw_addr);
2591 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2592 ctx->i32one, "");
2593 }
2594 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2595 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2596 return result;
2597 }
2598
2599 static void
2600 store_tcs_output(struct nir_to_llvm_context *ctx,
2601 nir_intrinsic_instr *instr,
2602 LLVMValueRef src,
2603 unsigned writemask)
2604 {
2605 LLVMValueRef stride, dw_addr;
2606 LLVMValueRef buf_addr = NULL;
2607 LLVMValueRef vertex_index = NULL;
2608 LLVMValueRef indir_index = NULL;
2609 unsigned const_index = 0;
2610 unsigned param;
2611 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2612 const bool is_compact = instr->variables[0]->var->data.compact;
2613
2614 radv_get_deref_offset(ctx, instr->variables[0],
2615 false, NULL, per_vertex ? &vertex_index : NULL,
2616 &const_index, &indir_index);
2617
2618 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2619 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2620 is_compact && const_index > 3) {
2621 const_index -= 3;
2622 param++;
2623 }
2624
2625 if (!instr->variables[0]->var->data.patch) {
2626 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2627 dw_addr = get_tcs_out_current_patch_offset(ctx);
2628 } else {
2629 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2630 }
2631
2632 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2633
2634 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2635 indir_index);
2636 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2637 vertex_index, indir_index);
2638
2639 unsigned base = is_compact ? const_index : 0;
2640 for (unsigned chan = 0; chan < 8; chan++) {
2641 bool is_tess_factor = false;
2642 if (!(writemask & (1 << chan)))
2643 continue;
2644 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2645
2646 lds_store(ctx, dw_addr, value);
2647
2648 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2649 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2650 is_tess_factor = true;
2651
2652 if (!is_tess_factor && writemask != 0xF)
2653 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2654 buf_addr, ctx->oc_lds,
2655 4 * (base + chan), 1, 0, true, false);
2656
2657 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2658 ctx->i32one, "");
2659 }
2660
2661 if (writemask == 0xF) {
2662 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2663 buf_addr, ctx->oc_lds,
2664 (base * 4), 1, 0, true, false);
2665 }
2666 }
2667
2668 static LLVMValueRef
2669 load_tes_input(struct nir_to_llvm_context *ctx,
2670 nir_intrinsic_instr *instr)
2671 {
2672 LLVMValueRef buf_addr;
2673 LLVMValueRef result;
2674 LLVMValueRef vertex_index = NULL;
2675 LLVMValueRef indir_index = NULL;
2676 unsigned const_index = 0;
2677 unsigned param;
2678 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2679 const bool is_compact = instr->variables[0]->var->data.compact;
2680
2681 radv_get_deref_offset(ctx, instr->variables[0],
2682 false, NULL, per_vertex ? &vertex_index : NULL,
2683 &const_index, &indir_index);
2684 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2685 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2686 is_compact && const_index > 3) {
2687 const_index -= 3;
2688 param++;
2689 }
2690 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2691 is_compact, vertex_index, indir_index);
2692
2693 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2694 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true);
2695 result = trim_vector(ctx, result, instr->num_components);
2696 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2697 return result;
2698 }
2699
2700 static LLVMValueRef
2701 load_gs_input(struct nir_to_llvm_context *ctx,
2702 nir_intrinsic_instr *instr)
2703 {
2704 LLVMValueRef indir_index, vtx_offset;
2705 unsigned const_index;
2706 LLVMValueRef args[9];
2707 unsigned param, vtx_offset_param;
2708 LLVMValueRef value[4], result;
2709 unsigned vertex_index;
2710 radv_get_deref_offset(ctx, instr->variables[0],
2711 false, &vertex_index, NULL,
2712 &const_index, &indir_index);
2713 vtx_offset_param = vertex_index;
2714 assert(vtx_offset_param < 6);
2715 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2716 LLVMConstInt(ctx->i32, 4, false), "");
2717
2718 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2719 for (unsigned i = 0; i < instr->num_components; i++) {
2720
2721 args[0] = ctx->esgs_ring;
2722 args[1] = vtx_offset;
2723 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2724 args[3] = ctx->i32zero;
2725 args[4] = ctx->i32one; /* OFFEN */
2726 args[5] = ctx->i32zero; /* IDXEN */
2727 args[6] = ctx->i32one; /* GLC */
2728 args[7] = ctx->i32zero; /* SLC */
2729 args[8] = ctx->i32zero; /* TFE */
2730
2731 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2732 ctx->i32, args, 9,
2733 AC_FUNC_ATTR_READONLY |
2734 AC_FUNC_ATTR_LEGACY);
2735 }
2736 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2737
2738 return result;
2739 }
2740
2741 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2742 nir_intrinsic_instr *instr)
2743 {
2744 LLVMValueRef values[8];
2745 int idx = instr->variables[0]->var->data.driver_location;
2746 int ve = instr->dest.ssa.num_components;
2747 LLVMValueRef indir_index;
2748 LLVMValueRef ret;
2749 unsigned const_index;
2750 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2751 instr->variables[0]->var->data.mode == nir_var_shader_in;
2752 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2753 &const_index, &indir_index);
2754
2755 if (instr->dest.ssa.bit_size == 64)
2756 ve *= 2;
2757
2758 switch (instr->variables[0]->var->data.mode) {
2759 case nir_var_shader_in:
2760 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2761 return load_tcs_input(ctx, instr);
2762 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2763 return load_tes_input(ctx, instr);
2764 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2765 return load_gs_input(ctx, instr);
2766 }
2767 for (unsigned chan = 0; chan < ve; chan++) {
2768 if (indir_index) {
2769 unsigned count = glsl_count_attribute_slots(
2770 instr->variables[0]->var->type,
2771 ctx->stage == MESA_SHADER_VERTEX);
2772 count -= chan / 4;
2773 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2774 &ctx->ac, ctx->inputs + idx + chan, count,
2775 4, false);
2776
2777 values[chan] = LLVMBuildExtractElement(ctx->builder,
2778 tmp_vec,
2779 indir_index, "");
2780 } else
2781 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2782 }
2783 break;
2784 case nir_var_local:
2785 for (unsigned chan = 0; chan < ve; chan++) {
2786 if (indir_index) {
2787 unsigned count = glsl_count_attribute_slots(
2788 instr->variables[0]->var->type, false);
2789 count -= chan / 4;
2790 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2791 &ctx->ac, ctx->locals + idx + chan, count,
2792 4, true);
2793
2794 values[chan] = LLVMBuildExtractElement(ctx->builder,
2795 tmp_vec,
2796 indir_index, "");
2797 } else {
2798 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2799 }
2800 }
2801 break;
2802 case nir_var_shader_out:
2803 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2804 return load_tcs_output(ctx, instr);
2805 for (unsigned chan = 0; chan < ve; chan++) {
2806 if (indir_index) {
2807 unsigned count = glsl_count_attribute_slots(
2808 instr->variables[0]->var->type, false);
2809 count -= chan / 4;
2810 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2811 &ctx->ac, ctx->outputs + idx + chan, count,
2812 4, true);
2813
2814 values[chan] = LLVMBuildExtractElement(ctx->builder,
2815 tmp_vec,
2816 indir_index, "");
2817 } else {
2818 values[chan] = LLVMBuildLoad(ctx->builder,
2819 ctx->outputs[idx + chan + const_index * 4],
2820 "");
2821 }
2822 }
2823 break;
2824 case nir_var_shared: {
2825 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2826 LLVMValueRef derived_ptr;
2827
2828 if (indir_index)
2829 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2830
2831 for (unsigned chan = 0; chan < ve; chan++) {
2832 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2833 if (indir_index)
2834 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2835 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2836
2837 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2838 }
2839 break;
2840 }
2841 default:
2842 unreachable("unhandle variable mode");
2843 }
2844 ret = ac_build_gather_values(&ctx->ac, values, ve);
2845 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2846 }
2847
2848 static void
2849 visit_store_var(struct nir_to_llvm_context *ctx,
2850 nir_intrinsic_instr *instr)
2851 {
2852 LLVMValueRef temp_ptr, value;
2853 int idx = instr->variables[0]->var->data.driver_location;
2854 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2855 int writemask = instr->const_index[0];
2856 LLVMValueRef indir_index;
2857 unsigned const_index;
2858 radv_get_deref_offset(ctx, instr->variables[0], false,
2859 NULL, NULL, &const_index, &indir_index);
2860
2861 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2862 int old_writemask = writemask;
2863
2864 src = LLVMBuildBitCast(ctx->builder, src,
2865 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2866 "");
2867
2868 writemask = 0;
2869 for (unsigned chan = 0; chan < 4; chan++) {
2870 if (old_writemask & (1 << chan))
2871 writemask |= 3u << (2 * chan);
2872 }
2873 }
2874
2875 switch (instr->variables[0]->var->data.mode) {
2876 case nir_var_shader_out:
2877
2878 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
2879 store_tcs_output(ctx, instr, src, writemask);
2880 return;
2881 }
2882
2883 for (unsigned chan = 0; chan < 8; chan++) {
2884 int stride = 4;
2885 if (!(writemask & (1 << chan)))
2886 continue;
2887
2888 value = llvm_extract_elem(ctx, src, chan);
2889
2890 if (instr->variables[0]->var->data.compact)
2891 stride = 1;
2892 if (indir_index) {
2893 unsigned count = glsl_count_attribute_slots(
2894 instr->variables[0]->var->type, false);
2895 count -= chan / 4;
2896 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2897 &ctx->ac, ctx->outputs + idx + chan, count,
2898 stride, true);
2899
2900 if (get_llvm_num_components(tmp_vec) > 1) {
2901 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2902 value, indir_index, "");
2903 } else
2904 tmp_vec = value;
2905 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2906 count, stride, tmp_vec);
2907
2908 } else {
2909 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2910
2911 LLVMBuildStore(ctx->builder, value, temp_ptr);
2912 }
2913 }
2914 break;
2915 case nir_var_local:
2916 for (unsigned chan = 0; chan < 8; chan++) {
2917 if (!(writemask & (1 << chan)))
2918 continue;
2919
2920 value = llvm_extract_elem(ctx, src, chan);
2921 if (indir_index) {
2922 unsigned count = glsl_count_attribute_slots(
2923 instr->variables[0]->var->type, false);
2924 count -= chan / 4;
2925 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2926 &ctx->ac, ctx->locals + idx + chan, count,
2927 4, true);
2928
2929 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2930 value, indir_index, "");
2931 build_store_values_extended(ctx, ctx->locals + idx + chan,
2932 count, 4, tmp_vec);
2933 } else {
2934 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2935
2936 LLVMBuildStore(ctx->builder, value, temp_ptr);
2937 }
2938 }
2939 break;
2940 case nir_var_shared: {
2941 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2942
2943 if (indir_index)
2944 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2945
2946 for (unsigned chan = 0; chan < 8; chan++) {
2947 if (!(writemask & (1 << chan)))
2948 continue;
2949 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2950 LLVMValueRef derived_ptr;
2951
2952 if (indir_index)
2953 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2954
2955 value = llvm_extract_elem(ctx, src, chan);
2956 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2957 LLVMBuildStore(ctx->builder,
2958 to_integer(ctx, value), derived_ptr);
2959 }
2960 break;
2961 }
2962 default:
2963 break;
2964 }
2965 }
2966
2967 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2968 {
2969 switch (dim) {
2970 case GLSL_SAMPLER_DIM_BUF:
2971 return 1;
2972 case GLSL_SAMPLER_DIM_1D:
2973 return array ? 2 : 1;
2974 case GLSL_SAMPLER_DIM_2D:
2975 return array ? 3 : 2;
2976 case GLSL_SAMPLER_DIM_MS:
2977 return array ? 4 : 3;
2978 case GLSL_SAMPLER_DIM_3D:
2979 case GLSL_SAMPLER_DIM_CUBE:
2980 return 3;
2981 case GLSL_SAMPLER_DIM_RECT:
2982 case GLSL_SAMPLER_DIM_SUBPASS:
2983 return 2;
2984 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2985 return 3;
2986 default:
2987 break;
2988 }
2989 return 0;
2990 }
2991
2992
2993
2994 /* Adjust the sample index according to FMASK.
2995 *
2996 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2997 * which is the identity mapping. Each nibble says which physical sample
2998 * should be fetched to get that sample.
2999 *
3000 * For example, 0x11111100 means there are only 2 samples stored and
3001 * the second sample covers 3/4 of the pixel. When reading samples 0
3002 * and 1, return physical sample 0 (determined by the first two 0s
3003 * in FMASK), otherwise return physical sample 1.
3004 *
3005 * The sample index should be adjusted as follows:
3006 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3007 */
3008 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3009 LLVMValueRef coord_x, LLVMValueRef coord_y,
3010 LLVMValueRef coord_z,
3011 LLVMValueRef sample_index,
3012 LLVMValueRef fmask_desc_ptr)
3013 {
3014 LLVMValueRef fmask_load_address[4];
3015 LLVMValueRef res;
3016
3017 fmask_load_address[0] = coord_x;
3018 fmask_load_address[1] = coord_y;
3019 if (coord_z) {
3020 fmask_load_address[2] = coord_z;
3021 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3022 }
3023
3024 struct ac_image_args args = {0};
3025
3026 args.opcode = ac_image_load;
3027 args.da = coord_z ? true : false;
3028 args.resource = fmask_desc_ptr;
3029 args.dmask = 0xf;
3030 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3031
3032 res = ac_build_image_opcode(&ctx->ac, &args);
3033
3034 res = to_integer(ctx, res);
3035 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3036 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3037
3038 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3039 res,
3040 ctx->i32zero, "");
3041
3042 LLVMValueRef sample_index4 =
3043 LLVMBuildMul(ctx->builder, sample_index, four, "");
3044 LLVMValueRef shifted_fmask =
3045 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3046 LLVMValueRef final_sample =
3047 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3048
3049 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3050 * resource descriptor is 0 (invalid),
3051 */
3052 LLVMValueRef fmask_desc =
3053 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3054 ctx->v8i32, "");
3055
3056 LLVMValueRef fmask_word1 =
3057 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3058 ctx->i32one, "");
3059
3060 LLVMValueRef word1_is_nonzero =
3061 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3062 fmask_word1, ctx->i32zero, "");
3063
3064 /* Replace the MSAA sample index. */
3065 sample_index =
3066 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3067 final_sample, sample_index, "");
3068 return sample_index;
3069 }
3070
3071 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3072 nir_intrinsic_instr *instr)
3073 {
3074 const struct glsl_type *type = instr->variables[0]->var->type;
3075 if(instr->variables[0]->deref.child)
3076 type = instr->variables[0]->deref.child->type;
3077
3078 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3079 LLVMValueRef coords[4];
3080 LLVMValueRef masks[] = {
3081 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3082 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3083 };
3084 LLVMValueRef res;
3085 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3086
3087 int count;
3088 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3089 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3090 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3091 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3092 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3093
3094 count = image_type_to_components_count(dim,
3095 glsl_sampler_type_is_array(type));
3096
3097 if (is_ms) {
3098 LLVMValueRef fmask_load_address[3];
3099 int chan;
3100
3101 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3102 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3103 if (glsl_sampler_type_is_array(type))
3104 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3105 else
3106 fmask_load_address[2] = NULL;
3107 if (add_frag_pos) {
3108 for (chan = 0; chan < 2; ++chan)
3109 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3110 }
3111 sample_index = adjust_sample_index_using_fmask(ctx,
3112 fmask_load_address[0],
3113 fmask_load_address[1],
3114 fmask_load_address[2],
3115 sample_index,
3116 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3117 }
3118 if (count == 1) {
3119 if (instr->src[0].ssa->num_components)
3120 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3121 else
3122 res = src0;
3123 } else {
3124 int chan;
3125 if (is_ms)
3126 count--;
3127 for (chan = 0; chan < count; ++chan) {
3128 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3129 }
3130
3131 if (add_frag_pos) {
3132 for (chan = 0; chan < count; ++chan)
3133 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3134 }
3135 if (is_ms) {
3136 coords[count] = sample_index;
3137 count++;
3138 }
3139
3140 if (count == 3) {
3141 coords[3] = LLVMGetUndef(ctx->i32);
3142 count = 4;
3143 }
3144 res = ac_build_gather_values(&ctx->ac, coords, count);
3145 }
3146 return res;
3147 }
3148
3149 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3150 nir_intrinsic_instr *instr)
3151 {
3152 LLVMValueRef params[7];
3153 LLVMValueRef res;
3154 char intrinsic_name[64];
3155 const nir_variable *var = instr->variables[0]->var;
3156 const struct glsl_type *type = var->type;
3157 if(instr->variables[0]->deref.child)
3158 type = instr->variables[0]->deref.child->type;
3159
3160 type = glsl_without_array(type);
3161 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3162 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3163 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3164 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3165 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3166 params[3] = ctx->i1false; /* glc */
3167 params[4] = ctx->i1false; /* slc */
3168 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3169 params, 5, 0);
3170
3171 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3172 res = to_integer(ctx, res);
3173 } else {
3174 bool is_da = glsl_sampler_type_is_array(type) ||
3175 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3176 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3177 LLVMValueRef glc = ctx->i1false;
3178 LLVMValueRef slc = ctx->i1false;
3179
3180 params[0] = get_image_coords(ctx, instr);
3181 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3182 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3183 if (HAVE_LLVM <= 0x0309) {
3184 params[3] = ctx->i1false; /* r128 */
3185 params[4] = da;
3186 params[5] = glc;
3187 params[6] = slc;
3188 } else {
3189 LLVMValueRef lwe = ctx->i1false;
3190 params[3] = glc;
3191 params[4] = slc;
3192 params[5] = lwe;
3193 params[6] = da;
3194 }
3195
3196 ac_get_image_intr_name("llvm.amdgcn.image.load",
3197 ctx->v4f32, /* vdata */
3198 LLVMTypeOf(params[0]), /* coords */
3199 LLVMTypeOf(params[1]), /* rsrc */
3200 intrinsic_name, sizeof(intrinsic_name));
3201
3202 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3203 params, 7, AC_FUNC_ATTR_READONLY);
3204 }
3205 return to_integer(ctx, res);
3206 }
3207
3208 static void visit_image_store(struct nir_to_llvm_context *ctx,
3209 nir_intrinsic_instr *instr)
3210 {
3211 LLVMValueRef params[8];
3212 char intrinsic_name[64];
3213 const nir_variable *var = instr->variables[0]->var;
3214 const struct glsl_type *type = glsl_without_array(var->type);
3215
3216 if (ctx->stage == MESA_SHADER_FRAGMENT)
3217 ctx->shader_info->fs.writes_memory = true;
3218
3219 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3220 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
3221 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3222 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3223 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3224 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3225 params[4] = ctx->i1false; /* glc */
3226 params[5] = ctx->i1false; /* slc */
3227 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3228 params, 6, 0);
3229 } else {
3230 bool is_da = glsl_sampler_type_is_array(type) ||
3231 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3232 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3233 LLVMValueRef glc = ctx->i1false;
3234 LLVMValueRef slc = ctx->i1false;
3235
3236 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
3237 params[1] = get_image_coords(ctx, instr); /* coords */
3238 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3239 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3240 if (HAVE_LLVM <= 0x0309) {
3241 params[4] = ctx->i1false; /* r128 */
3242 params[5] = da;
3243 params[6] = glc;
3244 params[7] = slc;
3245 } else {
3246 LLVMValueRef lwe = ctx->i1false;
3247 params[4] = glc;
3248 params[5] = slc;
3249 params[6] = lwe;
3250 params[7] = da;
3251 }
3252
3253 ac_get_image_intr_name("llvm.amdgcn.image.store",
3254 LLVMTypeOf(params[0]), /* vdata */
3255 LLVMTypeOf(params[1]), /* coords */
3256 LLVMTypeOf(params[2]), /* rsrc */
3257 intrinsic_name, sizeof(intrinsic_name));
3258
3259 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3260 params, 8, 0);
3261 }
3262
3263 }
3264
3265 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3266 nir_intrinsic_instr *instr)
3267 {
3268 LLVMValueRef params[6];
3269 int param_count = 0;
3270 const nir_variable *var = instr->variables[0]->var;
3271
3272 const char *base_name = "llvm.amdgcn.image.atomic";
3273 const char *atomic_name;
3274 LLVMValueRef coords;
3275 char intrinsic_name[32], coords_type[8];
3276 const struct glsl_type *type = glsl_without_array(var->type);
3277
3278 if (ctx->stage == MESA_SHADER_FRAGMENT)
3279 ctx->shader_info->fs.writes_memory = true;
3280
3281 params[param_count++] = get_src(ctx, instr->src[2]);
3282 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3283 params[param_count++] = get_src(ctx, instr->src[3]);
3284
3285 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3286 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3287 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3288 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3289 params[param_count++] = ctx->i32zero; /* voffset */
3290 params[param_count++] = ctx->i1false; /* glc */
3291 params[param_count++] = ctx->i1false; /* slc */
3292 } else {
3293 bool da = glsl_sampler_type_is_array(type) ||
3294 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3295
3296 coords = params[param_count++] = get_image_coords(ctx, instr);
3297 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3298 params[param_count++] = ctx->i1false; /* r128 */
3299 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3300 params[param_count++] = ctx->i1false; /* slc */
3301 }
3302
3303 switch (instr->intrinsic) {
3304 case nir_intrinsic_image_atomic_add:
3305 atomic_name = "add";
3306 break;
3307 case nir_intrinsic_image_atomic_min:
3308 atomic_name = "smin";
3309 break;
3310 case nir_intrinsic_image_atomic_max:
3311 atomic_name = "smax";
3312 break;
3313 case nir_intrinsic_image_atomic_and:
3314 atomic_name = "and";
3315 break;
3316 case nir_intrinsic_image_atomic_or:
3317 atomic_name = "or";
3318 break;
3319 case nir_intrinsic_image_atomic_xor:
3320 atomic_name = "xor";
3321 break;
3322 case nir_intrinsic_image_atomic_exchange:
3323 atomic_name = "swap";
3324 break;
3325 case nir_intrinsic_image_atomic_comp_swap:
3326 atomic_name = "cmpswap";
3327 break;
3328 default:
3329 abort();
3330 }
3331 build_int_type_name(LLVMTypeOf(coords),
3332 coords_type, sizeof(coords_type));
3333
3334 snprintf(intrinsic_name, sizeof(intrinsic_name),
3335 "%s.%s.%s", base_name, atomic_name, coords_type);
3336 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3337 }
3338
3339 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3340 nir_intrinsic_instr *instr)
3341 {
3342 LLVMValueRef res;
3343 const nir_variable *var = instr->variables[0]->var;
3344 const struct glsl_type *type = instr->variables[0]->var->type;
3345 bool da = glsl_sampler_type_is_array(var->type) ||
3346 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3347 if(instr->variables[0]->deref.child)
3348 type = instr->variables[0]->deref.child->type;
3349
3350 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3351 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3352
3353 struct ac_image_args args = { 0 };
3354
3355 args.da = da;
3356 args.dmask = 0xf;
3357 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3358 args.opcode = ac_image_get_resinfo;
3359 args.addr = ctx->i32zero;
3360
3361 res = ac_build_image_opcode(&ctx->ac, &args);
3362
3363 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3364 glsl_sampler_type_is_array(type)) {
3365 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3366 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3367 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3368 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3369 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3370 }
3371 return res;
3372 }
3373
3374 #define NOOP_WAITCNT 0xf7f
3375 #define LGKM_CNT 0x07f
3376 #define VM_CNT 0xf70
3377
3378 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3379 unsigned simm16)
3380 {
3381 LLVMValueRef args[1] = {
3382 LLVMConstInt(ctx->i32, simm16, false),
3383 };
3384 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3385 ctx->voidt, args, 1, 0);
3386 }
3387
3388 static void emit_barrier(struct nir_to_llvm_context *ctx)
3389 {
3390 /* SI only (thanks to a hw bug workaround):
3391 * The real barrier instruction isn’t needed, because an entire patch
3392 * always fits into a single wave.
3393 */
3394 if (ctx->options->chip_class == SI &&
3395 ctx->stage == MESA_SHADER_TESS_CTRL) {
3396 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3397 return;
3398 }
3399 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3400 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3401 }
3402
3403 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3404 nir_intrinsic_instr *instr)
3405 {
3406 LLVMValueRef cond;
3407 ctx->shader_info->fs.can_discard = true;
3408
3409 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3410 get_src(ctx, instr->src[0]),
3411 ctx->i32zero, "");
3412
3413 cond = LLVMBuildSelect(ctx->builder, cond,
3414 LLVMConstReal(ctx->f32, -1.0f),
3415 ctx->f32zero, "");
3416 ac_build_kill(&ctx->ac, cond);
3417 }
3418
3419 static LLVMValueRef
3420 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3421 {
3422 LLVMValueRef result;
3423 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3424 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3425 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3426
3427 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3428 }
3429
3430 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3431 nir_intrinsic_instr *instr)
3432 {
3433 LLVMValueRef ptr, result;
3434 int idx = instr->variables[0]->var->data.driver_location;
3435 LLVMValueRef src = get_src(ctx, instr->src[0]);
3436 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3437
3438 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3439 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3440 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3441 ptr, src, src1,
3442 LLVMAtomicOrderingSequentiallyConsistent,
3443 LLVMAtomicOrderingSequentiallyConsistent,
3444 false);
3445 } else {
3446 LLVMAtomicRMWBinOp op;
3447 switch (instr->intrinsic) {
3448 case nir_intrinsic_var_atomic_add:
3449 op = LLVMAtomicRMWBinOpAdd;
3450 break;
3451 case nir_intrinsic_var_atomic_umin:
3452 op = LLVMAtomicRMWBinOpUMin;
3453 break;
3454 case nir_intrinsic_var_atomic_umax:
3455 op = LLVMAtomicRMWBinOpUMax;
3456 break;
3457 case nir_intrinsic_var_atomic_imin:
3458 op = LLVMAtomicRMWBinOpMin;
3459 break;
3460 case nir_intrinsic_var_atomic_imax:
3461 op = LLVMAtomicRMWBinOpMax;
3462 break;
3463 case nir_intrinsic_var_atomic_and:
3464 op = LLVMAtomicRMWBinOpAnd;
3465 break;
3466 case nir_intrinsic_var_atomic_or:
3467 op = LLVMAtomicRMWBinOpOr;
3468 break;
3469 case nir_intrinsic_var_atomic_xor:
3470 op = LLVMAtomicRMWBinOpXor;
3471 break;
3472 case nir_intrinsic_var_atomic_exchange:
3473 op = LLVMAtomicRMWBinOpXchg;
3474 break;
3475 default:
3476 return NULL;
3477 }
3478
3479 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3480 LLVMAtomicOrderingSequentiallyConsistent,
3481 false);
3482 }
3483 return result;
3484 }
3485
3486 #define INTERP_CENTER 0
3487 #define INTERP_CENTROID 1
3488 #define INTERP_SAMPLE 2
3489
3490 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3491 enum glsl_interp_mode interp, unsigned location)
3492 {
3493 switch (interp) {
3494 case INTERP_MODE_FLAT:
3495 default:
3496 return NULL;
3497 case INTERP_MODE_SMOOTH:
3498 case INTERP_MODE_NONE:
3499 if (location == INTERP_CENTER)
3500 return ctx->persp_center;
3501 else if (location == INTERP_CENTROID)
3502 return ctx->persp_centroid;
3503 else if (location == INTERP_SAMPLE)
3504 return ctx->persp_sample;
3505 break;
3506 case INTERP_MODE_NOPERSPECTIVE:
3507 if (location == INTERP_CENTER)
3508 return ctx->linear_center;
3509 else if (location == INTERP_CENTROID)
3510 return ctx->linear_centroid;
3511 else if (location == INTERP_SAMPLE)
3512 return ctx->linear_sample;
3513 break;
3514 }
3515 return NULL;
3516 }
3517
3518 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3519 LLVMValueRef sample_id)
3520 {
3521 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
3522 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
3523 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
3524 LLVMValueRef result[2];
3525
3526 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
3527 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
3528
3529 return ac_build_gather_values(&ctx->ac, result, 2);
3530 }
3531
3532 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3533 {
3534 LLVMValueRef values[2];
3535
3536 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3537 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3538 return ac_build_gather_values(&ctx->ac, values, 2);
3539 }
3540
3541 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3542 nir_intrinsic_instr *instr)
3543 {
3544 LLVMValueRef result[2];
3545 LLVMValueRef interp_param, attr_number;
3546 unsigned location;
3547 unsigned chan;
3548 LLVMValueRef src_c0, src_c1;
3549 LLVMValueRef src0;
3550 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3551 switch (instr->intrinsic) {
3552 case nir_intrinsic_interp_var_at_centroid:
3553 location = INTERP_CENTROID;
3554 break;
3555 case nir_intrinsic_interp_var_at_sample:
3556 location = INTERP_SAMPLE;
3557 src0 = get_src(ctx, instr->src[0]);
3558 break;
3559 case nir_intrinsic_interp_var_at_offset:
3560 location = INTERP_CENTER;
3561 src0 = get_src(ctx, instr->src[0]);
3562 default:
3563 break;
3564 }
3565
3566 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3567 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3568 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3569 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3570 LLVMValueRef sample_position;
3571 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3572
3573 /* fetch sample ID */
3574 sample_position = load_sample_position(ctx, src0);
3575
3576 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3577 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3578 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3579 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3580 }
3581 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3582 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3583
3584 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3585 LLVMValueRef ij_out[2];
3586 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3587
3588 /*
3589 * take the I then J parameters, and the DDX/Y for it, and
3590 * calculate the IJ inputs for the interpolator.
3591 * temp1 = ddx * offset/sample.x + I;
3592 * interp_param.I = ddy * offset/sample.y + temp1;
3593 * temp1 = ddx * offset/sample.x + J;
3594 * interp_param.J = ddy * offset/sample.y + temp1;
3595 */
3596 for (unsigned i = 0; i < 2; i++) {
3597 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3598 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3599 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3600 ddxy_out, ix_ll, "");
3601 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3602 ddxy_out, iy_ll, "");
3603 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3604 interp_param, ix_ll, "");
3605 LLVMValueRef temp1, temp2;
3606
3607 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3608 ctx->f32, "");
3609
3610 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3611 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3612
3613 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3614 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3615
3616 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3617 temp2, ctx->i32, "");
3618 }
3619 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3620
3621 }
3622
3623 for (chan = 0; chan < 2; chan++) {
3624 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3625
3626 if (interp_param) {
3627 interp_param = LLVMBuildBitCast(ctx->builder,
3628 interp_param, LLVMVectorType(ctx->f32, 2), "");
3629 LLVMValueRef i = LLVMBuildExtractElement(
3630 ctx->builder, interp_param, ctx->i32zero, "");
3631 LLVMValueRef j = LLVMBuildExtractElement(
3632 ctx->builder, interp_param, ctx->i32one, "");
3633
3634 result[chan] = ac_build_fs_interp(&ctx->ac,
3635 llvm_chan, attr_number,
3636 ctx->prim_mask, i, j);
3637 } else {
3638 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3639 LLVMConstInt(ctx->i32, 2, false),
3640 llvm_chan, attr_number,
3641 ctx->prim_mask);
3642 }
3643 }
3644 return ac_build_gather_values(&ctx->ac, result, 2);
3645 }
3646
3647 static void
3648 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3649 nir_intrinsic_instr *instr)
3650 {
3651 LLVMValueRef gs_next_vertex;
3652 LLVMValueRef can_emit, kill;
3653 int idx;
3654
3655 assert(instr->const_index[0] == 0);
3656 /* Write vertex attribute values to GSVS ring */
3657 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3658 ctx->gs_next_vertex,
3659 "");
3660
3661 /* If this thread has already emitted the declared maximum number of
3662 * vertices, kill it: excessive vertex emissions are not supposed to
3663 * have any effect, and GS threads have no externally observable
3664 * effects other than emitting vertices.
3665 */
3666 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3667 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3668
3669 kill = LLVMBuildSelect(ctx->builder, can_emit,
3670 LLVMConstReal(ctx->f32, 1.0f),
3671 LLVMConstReal(ctx->f32, -1.0f), "");
3672 ac_build_kill(&ctx->ac, kill);
3673
3674 /* loop num outputs */
3675 idx = 0;
3676 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3677 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3678 int length = 4;
3679 int slot = idx;
3680 int slot_inc = 1;
3681
3682 if (!(ctx->output_mask & (1ull << i)))
3683 continue;
3684
3685 if (i == VARYING_SLOT_CLIP_DIST0) {
3686 /* pack clip and cull into a single set of slots */
3687 length = ctx->num_output_clips + ctx->num_output_culls;
3688 if (length > 4)
3689 slot_inc = 2;
3690 }
3691 for (unsigned j = 0; j < length; j++) {
3692 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3693 out_ptr[j], "");
3694 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3695 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3696 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3697
3698 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3699
3700 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3701 out_val, 1,
3702 voffset, ctx->gs2vs_offset, 0,
3703 1, 1, true, true);
3704 }
3705 idx += slot_inc;
3706 }
3707
3708 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3709 ctx->i32one, "");
3710 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3711
3712 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3713 }
3714
3715 static void
3716 visit_end_primitive(struct nir_to_llvm_context *ctx,
3717 nir_intrinsic_instr *instr)
3718 {
3719 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3720 }
3721
3722 static LLVMValueRef
3723 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3724 nir_intrinsic_instr *instr)
3725 {
3726 LLVMValueRef coord[4] = {
3727 ctx->tes_u,
3728 ctx->tes_v,
3729 ctx->f32zero,
3730 ctx->f32zero,
3731 };
3732
3733 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3734 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3735 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3736
3737 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3738 return LLVMBuildBitCast(ctx->builder, result,
3739 get_def_type(ctx, &instr->dest.ssa), "");
3740 }
3741
3742 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3743 nir_intrinsic_instr *instr)
3744 {
3745 LLVMValueRef result = NULL;
3746
3747 switch (instr->intrinsic) {
3748 case nir_intrinsic_load_work_group_id: {
3749 result = ctx->workgroup_ids;
3750 break;
3751 }
3752 case nir_intrinsic_load_base_vertex: {
3753 result = ctx->base_vertex;
3754 break;
3755 }
3756 case nir_intrinsic_load_vertex_id_zero_base: {
3757 result = ctx->vertex_id;
3758 break;
3759 }
3760 case nir_intrinsic_load_local_invocation_id: {
3761 result = ctx->local_invocation_ids;
3762 break;
3763 }
3764 case nir_intrinsic_load_base_instance:
3765 result = ctx->start_instance;
3766 break;
3767 case nir_intrinsic_load_draw_id:
3768 result = ctx->draw_index;
3769 break;
3770 case nir_intrinsic_load_invocation_id:
3771 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3772 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3773 else
3774 result = ctx->gs_invocation_id;
3775 break;
3776 case nir_intrinsic_load_primitive_id:
3777 if (ctx->stage == MESA_SHADER_GEOMETRY)
3778 result = ctx->gs_prim_id;
3779 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
3780 result = ctx->tcs_patch_id;
3781 else if (ctx->stage == MESA_SHADER_TESS_EVAL)
3782 result = ctx->tes_patch_id;
3783 else
3784 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3785 break;
3786 case nir_intrinsic_load_sample_id:
3787 ctx->shader_info->fs.force_persample = true;
3788 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3789 break;
3790 case nir_intrinsic_load_sample_pos:
3791 ctx->shader_info->fs.force_persample = true;
3792 result = load_sample_pos(ctx);
3793 break;
3794 case nir_intrinsic_load_sample_mask_in:
3795 result = ctx->sample_coverage;
3796 break;
3797 case nir_intrinsic_load_front_face:
3798 result = ctx->front_face;
3799 break;
3800 case nir_intrinsic_load_instance_id:
3801 result = ctx->instance_id;
3802 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3803 ctx->shader_info->vs.vgpr_comp_cnt);
3804 break;
3805 case nir_intrinsic_load_num_work_groups:
3806 result = ctx->num_work_groups;
3807 break;
3808 case nir_intrinsic_load_local_invocation_index:
3809 result = visit_load_local_invocation_index(ctx);
3810 break;
3811 case nir_intrinsic_load_push_constant:
3812 result = visit_load_push_constant(ctx, instr);
3813 break;
3814 case nir_intrinsic_vulkan_resource_index:
3815 result = visit_vulkan_resource_index(ctx, instr);
3816 break;
3817 case nir_intrinsic_store_ssbo:
3818 visit_store_ssbo(ctx, instr);
3819 break;
3820 case nir_intrinsic_load_ssbo:
3821 result = visit_load_buffer(ctx, instr);
3822 break;
3823 case nir_intrinsic_ssbo_atomic_add:
3824 case nir_intrinsic_ssbo_atomic_imin:
3825 case nir_intrinsic_ssbo_atomic_umin:
3826 case nir_intrinsic_ssbo_atomic_imax:
3827 case nir_intrinsic_ssbo_atomic_umax:
3828 case nir_intrinsic_ssbo_atomic_and:
3829 case nir_intrinsic_ssbo_atomic_or:
3830 case nir_intrinsic_ssbo_atomic_xor:
3831 case nir_intrinsic_ssbo_atomic_exchange:
3832 case nir_intrinsic_ssbo_atomic_comp_swap:
3833 result = visit_atomic_ssbo(ctx, instr);
3834 break;
3835 case nir_intrinsic_load_ubo:
3836 result = visit_load_ubo_buffer(ctx, instr);
3837 break;
3838 case nir_intrinsic_get_buffer_size:
3839 result = visit_get_buffer_size(ctx, instr);
3840 break;
3841 case nir_intrinsic_load_var:
3842 result = visit_load_var(ctx, instr);
3843 break;
3844 case nir_intrinsic_store_var:
3845 visit_store_var(ctx, instr);
3846 break;
3847 case nir_intrinsic_image_load:
3848 result = visit_image_load(ctx, instr);
3849 break;
3850 case nir_intrinsic_image_store:
3851 visit_image_store(ctx, instr);
3852 break;
3853 case nir_intrinsic_image_atomic_add:
3854 case nir_intrinsic_image_atomic_min:
3855 case nir_intrinsic_image_atomic_max:
3856 case nir_intrinsic_image_atomic_and:
3857 case nir_intrinsic_image_atomic_or:
3858 case nir_intrinsic_image_atomic_xor:
3859 case nir_intrinsic_image_atomic_exchange:
3860 case nir_intrinsic_image_atomic_comp_swap:
3861 result = visit_image_atomic(ctx, instr);
3862 break;
3863 case nir_intrinsic_image_size:
3864 result = visit_image_size(ctx, instr);
3865 break;
3866 case nir_intrinsic_discard:
3867 ctx->shader_info->fs.can_discard = true;
3868 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3869 ctx->voidt,
3870 NULL, 0, AC_FUNC_ATTR_LEGACY);
3871 break;
3872 case nir_intrinsic_discard_if:
3873 emit_discard_if(ctx, instr);
3874 break;
3875 case nir_intrinsic_memory_barrier:
3876 emit_waitcnt(ctx, VM_CNT);
3877 break;
3878 case nir_intrinsic_barrier:
3879 emit_barrier(ctx);
3880 break;
3881 case nir_intrinsic_var_atomic_add:
3882 case nir_intrinsic_var_atomic_imin:
3883 case nir_intrinsic_var_atomic_umin:
3884 case nir_intrinsic_var_atomic_imax:
3885 case nir_intrinsic_var_atomic_umax:
3886 case nir_intrinsic_var_atomic_and:
3887 case nir_intrinsic_var_atomic_or:
3888 case nir_intrinsic_var_atomic_xor:
3889 case nir_intrinsic_var_atomic_exchange:
3890 case nir_intrinsic_var_atomic_comp_swap:
3891 result = visit_var_atomic(ctx, instr);
3892 break;
3893 case nir_intrinsic_interp_var_at_centroid:
3894 case nir_intrinsic_interp_var_at_sample:
3895 case nir_intrinsic_interp_var_at_offset:
3896 result = visit_interp(ctx, instr);
3897 break;
3898 case nir_intrinsic_emit_vertex:
3899 visit_emit_vertex(ctx, instr);
3900 break;
3901 case nir_intrinsic_end_primitive:
3902 visit_end_primitive(ctx, instr);
3903 break;
3904 case nir_intrinsic_load_tess_coord:
3905 result = visit_load_tess_coord(ctx, instr);
3906 break;
3907 case nir_intrinsic_load_patch_vertices_in:
3908 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
3909 break;
3910 default:
3911 fprintf(stderr, "Unknown intrinsic: ");
3912 nir_print_instr(&instr->instr, stderr);
3913 fprintf(stderr, "\n");
3914 break;
3915 }
3916 if (result) {
3917 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3918 }
3919 }
3920
3921 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3922 nir_deref_var *deref,
3923 enum desc_type desc_type)
3924 {
3925 unsigned desc_set = deref->var->data.descriptor_set;
3926 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3927 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3928 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3929 unsigned offset = binding->offset;
3930 unsigned stride = binding->size;
3931 unsigned type_size;
3932 LLVMBuilderRef builder = ctx->builder;
3933 LLVMTypeRef type;
3934 LLVMValueRef index = NULL;
3935 unsigned constant_index = 0;
3936
3937 assert(deref->var->data.binding < layout->binding_count);
3938
3939 switch (desc_type) {
3940 case DESC_IMAGE:
3941 type = ctx->v8i32;
3942 type_size = 32;
3943 break;
3944 case DESC_FMASK:
3945 type = ctx->v8i32;
3946 offset += 32;
3947 type_size = 32;
3948 break;
3949 case DESC_SAMPLER:
3950 type = ctx->v4i32;
3951 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3952 offset += 64;
3953
3954 type_size = 16;
3955 break;
3956 case DESC_BUFFER:
3957 type = ctx->v4i32;
3958 type_size = 16;
3959 break;
3960 default:
3961 unreachable("invalid desc_type\n");
3962 }
3963
3964 if (deref->deref.child) {
3965 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3966
3967 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3968 offset += child->base_offset * stride;
3969 if (child->deref_array_type == nir_deref_array_type_indirect) {
3970 index = get_src(ctx, child->indirect);
3971 }
3972
3973 constant_index = child->base_offset;
3974 }
3975 if (desc_type == DESC_SAMPLER && binding->immutable_samplers &&
3976 (!index || binding->immutable_samplers_equal)) {
3977 if (binding->immutable_samplers_equal)
3978 constant_index = 0;
3979
3980 LLVMValueRef constants[] = {
3981 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 0], 0),
3982 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 1], 0),
3983 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 2], 0),
3984 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 3], 0),
3985 };
3986 return ac_build_gather_values(&ctx->ac, constants, 4);
3987 }
3988
3989 assert(stride % type_size == 0);
3990
3991 if (!index)
3992 index = ctx->i32zero;
3993
3994 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3995
3996 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3997 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3998
3999 return ac_build_indexed_load_const(&ctx->ac, list, index);
4000 }
4001
4002 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4003 struct ac_image_args *args,
4004 nir_tex_instr *instr,
4005 nir_texop op,
4006 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4007 LLVMValueRef *param, unsigned count,
4008 unsigned dmask)
4009 {
4010 unsigned is_rect = 0;
4011 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4012
4013 if (op == nir_texop_lod)
4014 da = false;
4015 /* Pad to power of two vector */
4016 while (count < util_next_power_of_two(count))
4017 param[count++] = LLVMGetUndef(ctx->i32);
4018
4019 if (count > 1)
4020 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4021 else
4022 args->addr = param[0];
4023
4024 args->resource = res_ptr;
4025 args->sampler = samp_ptr;
4026
4027 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4028 args->addr = param[0];
4029 return;
4030 }
4031
4032 args->dmask = dmask;
4033 args->unorm = is_rect;
4034 args->da = da;
4035 }
4036
4037 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4038 *
4039 * SI-CI:
4040 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4041 * filtering manually. The driver sets img7 to a mask clearing
4042 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4043 * s_and_b32 samp0, samp0, img7
4044 *
4045 * VI:
4046 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4047 */
4048 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4049 LLVMValueRef res, LLVMValueRef samp)
4050 {
4051 LLVMBuilderRef builder = ctx->builder;
4052 LLVMValueRef img7, samp0;
4053
4054 if (ctx->options->chip_class >= VI)
4055 return samp;
4056
4057 img7 = LLVMBuildExtractElement(builder, res,
4058 LLVMConstInt(ctx->i32, 7, 0), "");
4059 samp0 = LLVMBuildExtractElement(builder, samp,
4060 LLVMConstInt(ctx->i32, 0, 0), "");
4061 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4062 return LLVMBuildInsertElement(builder, samp, samp0,
4063 LLVMConstInt(ctx->i32, 0, 0), "");
4064 }
4065
4066 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4067 nir_tex_instr *instr,
4068 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4069 LLVMValueRef *fmask_ptr)
4070 {
4071 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4072 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4073 else
4074 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4075 if (samp_ptr) {
4076 if (instr->sampler)
4077 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4078 else
4079 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4080 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4081 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4082 }
4083 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4084 instr->op == nir_texop_samples_identical))
4085 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4086 }
4087
4088 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4089 LLVMValueRef coord)
4090 {
4091 coord = to_float(ctx, coord);
4092 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4093 coord = to_integer(ctx, coord);
4094 return coord;
4095 }
4096
4097 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4098 {
4099 LLVMValueRef result = NULL;
4100 struct ac_image_args args = { 0 };
4101 unsigned dmask = 0xf;
4102 LLVMValueRef address[16];
4103 LLVMValueRef coords[5];
4104 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4105 LLVMValueRef bias = NULL, offsets = NULL;
4106 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4107 LLVMValueRef ddx = NULL, ddy = NULL;
4108 LLVMValueRef derivs[6];
4109 unsigned chan, count = 0;
4110 unsigned const_src = 0, num_deriv_comp = 0;
4111
4112 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4113
4114 for (unsigned i = 0; i < instr->num_srcs; i++) {
4115 switch (instr->src[i].src_type) {
4116 case nir_tex_src_coord:
4117 coord = get_src(ctx, instr->src[i].src);
4118 break;
4119 case nir_tex_src_projector:
4120 break;
4121 case nir_tex_src_comparator:
4122 comparator = get_src(ctx, instr->src[i].src);
4123 break;
4124 case nir_tex_src_offset:
4125 offsets = get_src(ctx, instr->src[i].src);
4126 const_src = i;
4127 break;
4128 case nir_tex_src_bias:
4129 bias = get_src(ctx, instr->src[i].src);
4130 break;
4131 case nir_tex_src_lod:
4132 lod = get_src(ctx, instr->src[i].src);
4133 break;
4134 case nir_tex_src_ms_index:
4135 sample_index = get_src(ctx, instr->src[i].src);
4136 break;
4137 case nir_tex_src_ms_mcs:
4138 break;
4139 case nir_tex_src_ddx:
4140 ddx = get_src(ctx, instr->src[i].src);
4141 num_deriv_comp = instr->src[i].src.ssa->num_components;
4142 break;
4143 case nir_tex_src_ddy:
4144 ddy = get_src(ctx, instr->src[i].src);
4145 break;
4146 case nir_tex_src_texture_offset:
4147 case nir_tex_src_sampler_offset:
4148 case nir_tex_src_plane:
4149 default:
4150 break;
4151 }
4152 }
4153
4154 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4155 result = get_buffer_size(ctx, res_ptr, true);
4156 goto write_result;
4157 }
4158
4159 if (instr->op == nir_texop_texture_samples) {
4160 LLVMValueRef res, samples, is_msaa;
4161 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4162 samples = LLVMBuildExtractElement(ctx->builder, res,
4163 LLVMConstInt(ctx->i32, 3, false), "");
4164 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4165 LLVMConstInt(ctx->i32, 28, false), "");
4166 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4167 LLVMConstInt(ctx->i32, 0xe, false), "");
4168 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4169 LLVMConstInt(ctx->i32, 0xe, false), "");
4170
4171 samples = LLVMBuildLShr(ctx->builder, samples,
4172 LLVMConstInt(ctx->i32, 16, false), "");
4173 samples = LLVMBuildAnd(ctx->builder, samples,
4174 LLVMConstInt(ctx->i32, 0xf, false), "");
4175 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4176 samples, "");
4177 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4178 ctx->i32one, "");
4179 result = samples;
4180 goto write_result;
4181 }
4182
4183 if (coord)
4184 for (chan = 0; chan < instr->coord_components; chan++)
4185 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4186
4187 if (offsets && instr->op != nir_texop_txf) {
4188 LLVMValueRef offset[3], pack;
4189 for (chan = 0; chan < 3; ++chan)
4190 offset[chan] = ctx->i32zero;
4191
4192 args.offset = true;
4193 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4194 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4195 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4196 LLVMConstInt(ctx->i32, 0x3f, false), "");
4197 if (chan)
4198 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4199 LLVMConstInt(ctx->i32, chan * 8, false), "");
4200 }
4201 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4202 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4203 address[count++] = pack;
4204
4205 }
4206 /* pack LOD bias value */
4207 if (instr->op == nir_texop_txb && bias) {
4208 address[count++] = bias;
4209 }
4210
4211 /* Pack depth comparison value */
4212 if (instr->is_shadow && comparator) {
4213 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4214 }
4215
4216 /* pack derivatives */
4217 if (ddx || ddy) {
4218 switch (instr->sampler_dim) {
4219 case GLSL_SAMPLER_DIM_3D:
4220 case GLSL_SAMPLER_DIM_CUBE:
4221 num_deriv_comp = 3;
4222 break;
4223 case GLSL_SAMPLER_DIM_2D:
4224 default:
4225 num_deriv_comp = 2;
4226 break;
4227 case GLSL_SAMPLER_DIM_1D:
4228 num_deriv_comp = 1;
4229 break;
4230 }
4231
4232 for (unsigned i = 0; i < num_deriv_comp; i++) {
4233 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
4234 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
4235 }
4236 }
4237
4238 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4239 for (chan = 0; chan < instr->coord_components; chan++)
4240 coords[chan] = to_float(ctx, coords[chan]);
4241 if (instr->coord_components == 3)
4242 coords[3] = LLVMGetUndef(ctx->f32);
4243 ac_prepare_cube_coords(&ctx->ac,
4244 instr->op == nir_texop_txd, instr->is_array,
4245 coords, derivs);
4246 if (num_deriv_comp)
4247 num_deriv_comp--;
4248 }
4249
4250 if (ddx || ddy) {
4251 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4252 address[count++] = derivs[i];
4253 }
4254
4255 /* Pack texture coordinates */
4256 if (coord) {
4257 address[count++] = coords[0];
4258 if (instr->coord_components > 1) {
4259 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4260 coords[1] = apply_round_slice(ctx, coords[1]);
4261 }
4262 address[count++] = coords[1];
4263 }
4264 if (instr->coord_components > 2) {
4265 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4266 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
4267 coords[2] = apply_round_slice(ctx, coords[2]);
4268 }
4269 address[count++] = coords[2];
4270 }
4271 }
4272
4273 /* Pack LOD */
4274 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
4275 address[count++] = lod;
4276 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4277 address[count++] = sample_index;
4278 } else if(instr->op == nir_texop_txs) {
4279 count = 0;
4280 if (lod)
4281 address[count++] = lod;
4282 else
4283 address[count++] = ctx->i32zero;
4284 }
4285
4286 for (chan = 0; chan < count; chan++) {
4287 address[chan] = LLVMBuildBitCast(ctx->builder,
4288 address[chan], ctx->i32, "");
4289 }
4290
4291 if (instr->op == nir_texop_samples_identical) {
4292 LLVMValueRef txf_address[4];
4293 struct ac_image_args txf_args = { 0 };
4294 unsigned txf_count = count;
4295 memcpy(txf_address, address, sizeof(txf_address));
4296
4297 if (!instr->is_array)
4298 txf_address[2] = ctx->i32zero;
4299 txf_address[3] = ctx->i32zero;
4300
4301 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4302 fmask_ptr, NULL,
4303 txf_address, txf_count, 0xf);
4304
4305 result = build_tex_intrinsic(ctx, instr, &txf_args);
4306
4307 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4308 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
4309 goto write_result;
4310 }
4311
4312 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4313 instr->op != nir_texop_txs) {
4314 unsigned sample_chan = instr->is_array ? 3 : 2;
4315 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4316 address[0],
4317 address[1],
4318 instr->is_array ? address[2] : NULL,
4319 address[sample_chan],
4320 fmask_ptr);
4321 }
4322
4323 if (offsets && instr->op == nir_texop_txf) {
4324 nir_const_value *const_offset =
4325 nir_src_as_const_value(instr->src[const_src].src);
4326 int num_offsets = instr->src[const_src].src.ssa->num_components;
4327 assert(const_offset);
4328 num_offsets = MIN2(num_offsets, instr->coord_components);
4329 if (num_offsets > 2)
4330 address[2] = LLVMBuildAdd(ctx->builder,
4331 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4332 if (num_offsets > 1)
4333 address[1] = LLVMBuildAdd(ctx->builder,
4334 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4335 address[0] = LLVMBuildAdd(ctx->builder,
4336 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4337
4338 }
4339
4340 /* TODO TG4 support */
4341 if (instr->op == nir_texop_tg4) {
4342 if (instr->is_shadow)
4343 dmask = 1;
4344 else
4345 dmask = 1 << instr->component;
4346 }
4347 set_tex_fetch_args(ctx, &args, instr, instr->op,
4348 res_ptr, samp_ptr, address, count, dmask);
4349
4350 result = build_tex_intrinsic(ctx, instr, &args);
4351
4352 if (instr->op == nir_texop_query_levels)
4353 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4354 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4355 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4356 else if (instr->op == nir_texop_txs &&
4357 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4358 instr->is_array) {
4359 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4360 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4361 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4362 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4363 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4364 } else if (instr->dest.ssa.num_components != 4)
4365 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4366
4367 write_result:
4368 if (result) {
4369 assert(instr->dest.is_ssa);
4370 result = to_integer(ctx, result);
4371 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4372 }
4373 }
4374
4375
4376 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4377 {
4378 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4379 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4380
4381 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4382 _mesa_hash_table_insert(ctx->phis, instr, result);
4383 }
4384
4385 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4386 nir_phi_instr *instr,
4387 LLVMValueRef llvm_phi)
4388 {
4389 nir_foreach_phi_src(src, instr) {
4390 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4391 LLVMValueRef llvm_src = get_src(ctx, src->src);
4392
4393 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4394 }
4395 }
4396
4397 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4398 {
4399 struct hash_entry *entry;
4400 hash_table_foreach(ctx->phis, entry) {
4401 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4402 (LLVMValueRef)entry->data);
4403 }
4404 }
4405
4406
4407 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4408 nir_ssa_undef_instr *instr)
4409 {
4410 unsigned num_components = instr->def.num_components;
4411 LLVMValueRef undef;
4412
4413 if (num_components == 1)
4414 undef = LLVMGetUndef(ctx->i32);
4415 else {
4416 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4417 }
4418 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4419 }
4420
4421 static void visit_jump(struct nir_to_llvm_context *ctx,
4422 nir_jump_instr *instr)
4423 {
4424 switch (instr->type) {
4425 case nir_jump_break:
4426 LLVMBuildBr(ctx->builder, ctx->break_block);
4427 LLVMClearInsertionPosition(ctx->builder);
4428 break;
4429 case nir_jump_continue:
4430 LLVMBuildBr(ctx->builder, ctx->continue_block);
4431 LLVMClearInsertionPosition(ctx->builder);
4432 break;
4433 default:
4434 fprintf(stderr, "Unknown NIR jump instr: ");
4435 nir_print_instr(&instr->instr, stderr);
4436 fprintf(stderr, "\n");
4437 abort();
4438 }
4439 }
4440
4441 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4442 struct exec_list *list);
4443
4444 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4445 {
4446 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4447 nir_foreach_instr(instr, block)
4448 {
4449 switch (instr->type) {
4450 case nir_instr_type_alu:
4451 visit_alu(ctx, nir_instr_as_alu(instr));
4452 break;
4453 case nir_instr_type_load_const:
4454 visit_load_const(ctx, nir_instr_as_load_const(instr));
4455 break;
4456 case nir_instr_type_intrinsic:
4457 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4458 break;
4459 case nir_instr_type_tex:
4460 visit_tex(ctx, nir_instr_as_tex(instr));
4461 break;
4462 case nir_instr_type_phi:
4463 visit_phi(ctx, nir_instr_as_phi(instr));
4464 break;
4465 case nir_instr_type_ssa_undef:
4466 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4467 break;
4468 case nir_instr_type_jump:
4469 visit_jump(ctx, nir_instr_as_jump(instr));
4470 break;
4471 default:
4472 fprintf(stderr, "Unknown NIR instr type: ");
4473 nir_print_instr(instr, stderr);
4474 fprintf(stderr, "\n");
4475 abort();
4476 }
4477 }
4478
4479 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4480 }
4481
4482 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4483 {
4484 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4485
4486 LLVMBasicBlockRef merge_block =
4487 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4488 LLVMBasicBlockRef if_block =
4489 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4490 LLVMBasicBlockRef else_block = merge_block;
4491 if (!exec_list_is_empty(&if_stmt->else_list))
4492 else_block = LLVMAppendBasicBlockInContext(
4493 ctx->context, ctx->main_function, "");
4494
4495 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4496 LLVMConstInt(ctx->i32, 0, false), "");
4497 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4498
4499 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4500 visit_cf_list(ctx, &if_stmt->then_list);
4501 if (LLVMGetInsertBlock(ctx->builder))
4502 LLVMBuildBr(ctx->builder, merge_block);
4503
4504 if (!exec_list_is_empty(&if_stmt->else_list)) {
4505 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4506 visit_cf_list(ctx, &if_stmt->else_list);
4507 if (LLVMGetInsertBlock(ctx->builder))
4508 LLVMBuildBr(ctx->builder, merge_block);
4509 }
4510
4511 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4512 }
4513
4514 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4515 {
4516 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4517 LLVMBasicBlockRef break_parent = ctx->break_block;
4518
4519 ctx->continue_block =
4520 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4521 ctx->break_block =
4522 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4523
4524 LLVMBuildBr(ctx->builder, ctx->continue_block);
4525 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4526 visit_cf_list(ctx, &loop->body);
4527
4528 if (LLVMGetInsertBlock(ctx->builder))
4529 LLVMBuildBr(ctx->builder, ctx->continue_block);
4530 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4531
4532 ctx->continue_block = continue_parent;
4533 ctx->break_block = break_parent;
4534 }
4535
4536 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4537 struct exec_list *list)
4538 {
4539 foreach_list_typed(nir_cf_node, node, node, list)
4540 {
4541 switch (node->type) {
4542 case nir_cf_node_block:
4543 visit_block(ctx, nir_cf_node_as_block(node));
4544 break;
4545
4546 case nir_cf_node_if:
4547 visit_if(ctx, nir_cf_node_as_if(node));
4548 break;
4549
4550 case nir_cf_node_loop:
4551 visit_loop(ctx, nir_cf_node_as_loop(node));
4552 break;
4553
4554 default:
4555 assert(0);
4556 }
4557 }
4558 }
4559
4560 static void
4561 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4562 struct nir_variable *variable)
4563 {
4564 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4565 LLVMValueRef t_offset;
4566 LLVMValueRef t_list;
4567 LLVMValueRef input;
4568 LLVMValueRef buffer_index;
4569 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4570 int idx = variable->data.location;
4571 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4572
4573 variable->data.driver_location = idx * 4;
4574
4575 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4576 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4577 ctx->start_instance, "");
4578 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4579 ctx->shader_info->vs.vgpr_comp_cnt);
4580 } else
4581 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4582 ctx->base_vertex, "");
4583
4584 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4585 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4586
4587 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4588
4589 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4590 buffer_index,
4591 LLVMConstInt(ctx->i32, 0, false),
4592 true);
4593
4594 for (unsigned chan = 0; chan < 4; chan++) {
4595 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4596 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4597 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4598 input, llvm_chan, ""));
4599 }
4600 }
4601 }
4602
4603 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4604 unsigned attr,
4605 LLVMValueRef interp_param,
4606 LLVMValueRef prim_mask,
4607 LLVMValueRef result[4])
4608 {
4609 LLVMValueRef attr_number;
4610 unsigned chan;
4611 LLVMValueRef i, j;
4612 bool interp = interp_param != NULL;
4613
4614 attr_number = LLVMConstInt(ctx->i32, attr, false);
4615
4616 /* fs.constant returns the param from the middle vertex, so it's not
4617 * really useful for flat shading. It's meant to be used for custom
4618 * interpolation (but the intrinsic can't fetch from the other two
4619 * vertices).
4620 *
4621 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4622 * to do the right thing. The only reason we use fs.constant is that
4623 * fs.interp cannot be used on integers, because they can be equal
4624 * to NaN.
4625 */
4626 if (interp) {
4627 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4628 LLVMVectorType(ctx->f32, 2), "");
4629
4630 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4631 ctx->i32zero, "");
4632 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4633 ctx->i32one, "");
4634 }
4635
4636 for (chan = 0; chan < 4; chan++) {
4637 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4638
4639 if (interp) {
4640 result[chan] = ac_build_fs_interp(&ctx->ac,
4641 llvm_chan,
4642 attr_number,
4643 prim_mask, i, j);
4644 } else {
4645 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4646 LLVMConstInt(ctx->i32, 2, false),
4647 llvm_chan,
4648 attr_number,
4649 prim_mask);
4650 }
4651 }
4652 }
4653
4654 static void
4655 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4656 struct nir_variable *variable)
4657 {
4658 int idx = variable->data.location;
4659 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4660 LLVMValueRef interp;
4661
4662 variable->data.driver_location = idx * 4;
4663 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4664
4665 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4666 unsigned interp_type;
4667 if (variable->data.sample) {
4668 interp_type = INTERP_SAMPLE;
4669 ctx->shader_info->fs.force_persample = true;
4670 } else if (variable->data.centroid)
4671 interp_type = INTERP_CENTROID;
4672 else
4673 interp_type = INTERP_CENTER;
4674
4675 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4676 } else
4677 interp = NULL;
4678
4679 for (unsigned i = 0; i < attrib_count; ++i)
4680 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4681
4682 }
4683
4684 static void
4685 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4686 struct nir_variable *variable)
4687 {
4688 switch (ctx->stage) {
4689 case MESA_SHADER_VERTEX:
4690 handle_vs_input_decl(ctx, variable);
4691 break;
4692 case MESA_SHADER_FRAGMENT:
4693 handle_fs_input_decl(ctx, variable);
4694 break;
4695 default:
4696 break;
4697 }
4698
4699 }
4700
4701 static void
4702 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4703 struct nir_shader *nir)
4704 {
4705 unsigned index = 0;
4706 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4707 LLVMValueRef interp_param;
4708 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4709
4710 if (!(ctx->input_mask & (1ull << i)))
4711 continue;
4712
4713 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4714 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4715 interp_param = *inputs;
4716 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4717 inputs);
4718
4719 if (!interp_param)
4720 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4721 ++index;
4722 } else if (i == VARYING_SLOT_POS) {
4723 for(int i = 0; i < 3; ++i)
4724 inputs[i] = ctx->frag_pos[i];
4725
4726 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4727 }
4728 }
4729 ctx->shader_info->fs.num_interp = index;
4730 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4731 ctx->shader_info->fs.has_pcoord = true;
4732 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4733 ctx->shader_info->fs.prim_id_input = true;
4734 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4735 ctx->shader_info->fs.layer_input = true;
4736 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4737 }
4738
4739 static LLVMValueRef
4740 ac_build_alloca(struct nir_to_llvm_context *ctx,
4741 LLVMTypeRef type,
4742 const char *name)
4743 {
4744 LLVMBuilderRef builder = ctx->builder;
4745 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4746 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4747 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4748 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4749 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4750 LLVMValueRef res;
4751
4752 if (first_instr) {
4753 LLVMPositionBuilderBefore(first_builder, first_instr);
4754 } else {
4755 LLVMPositionBuilderAtEnd(first_builder, first_block);
4756 }
4757
4758 res = LLVMBuildAlloca(first_builder, type, name);
4759 LLVMBuildStore(builder, LLVMConstNull(type), res);
4760
4761 LLVMDisposeBuilder(first_builder);
4762
4763 return res;
4764 }
4765
4766 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4767 LLVMTypeRef type,
4768 const char *name)
4769 {
4770 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4771 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4772 return ptr;
4773 }
4774
4775 static void
4776 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4777 struct nir_variable *variable)
4778 {
4779 int idx = variable->data.location + variable->data.index;
4780 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4781 uint64_t mask_attribs;
4782 variable->data.driver_location = idx * 4;
4783
4784 /* tess ctrl has it's own load/store paths for outputs */
4785 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4786 return;
4787
4788 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4789 if (ctx->stage == MESA_SHADER_VERTEX ||
4790 ctx->stage == MESA_SHADER_TESS_EVAL ||
4791 ctx->stage == MESA_SHADER_GEOMETRY) {
4792 if (idx == VARYING_SLOT_CLIP_DIST0) {
4793 int length = ctx->num_output_clips + ctx->num_output_culls;
4794 if (ctx->stage == MESA_SHADER_VERTEX) {
4795 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4796 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4797 }
4798 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4799 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4800 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4801 }
4802
4803 if (length > 4)
4804 attrib_count = 2;
4805 else
4806 attrib_count = 1;
4807 mask_attribs = 1ull << idx;
4808 }
4809 }
4810
4811 for (unsigned i = 0; i < attrib_count; ++i) {
4812 for (unsigned chan = 0; chan < 4; chan++) {
4813 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4814 si_build_alloca_undef(ctx, ctx->f32, "");
4815 }
4816 }
4817 ctx->output_mask |= mask_attribs;
4818 }
4819
4820 static void
4821 setup_locals(struct nir_to_llvm_context *ctx,
4822 struct nir_function *func)
4823 {
4824 int i, j;
4825 ctx->num_locals = 0;
4826 nir_foreach_variable(variable, &func->impl->locals) {
4827 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4828 variable->data.driver_location = ctx->num_locals * 4;
4829 ctx->num_locals += attrib_count;
4830 }
4831 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4832 if (!ctx->locals)
4833 return;
4834
4835 for (i = 0; i < ctx->num_locals; i++) {
4836 for (j = 0; j < 4; j++) {
4837 ctx->locals[i * 4 + j] =
4838 si_build_alloca_undef(ctx, ctx->f32, "temp");
4839 }
4840 }
4841 }
4842
4843 static LLVMValueRef
4844 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4845 {
4846 v = to_float(ctx, v);
4847 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4848 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4849 }
4850
4851
4852 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4853 LLVMValueRef src0, LLVMValueRef src1)
4854 {
4855 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4856 LLVMValueRef comp[2];
4857
4858 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4859 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4860 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4861 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4862 }
4863
4864 /* Initialize arguments for the shader export intrinsic */
4865 static void
4866 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4867 LLVMValueRef *values,
4868 unsigned target,
4869 struct ac_export_args *args)
4870 {
4871 /* Default is 0xf. Adjusted below depending on the format. */
4872 args->enabled_channels = 0xf;
4873
4874 /* Specify whether the EXEC mask represents the valid mask */
4875 args->valid_mask = 0;
4876
4877 /* Specify whether this is the last export */
4878 args->done = 0;
4879
4880 /* Specify the target we are exporting */
4881 args->target = target;
4882
4883 args->compr = false;
4884 args->out[0] = LLVMGetUndef(ctx->f32);
4885 args->out[1] = LLVMGetUndef(ctx->f32);
4886 args->out[2] = LLVMGetUndef(ctx->f32);
4887 args->out[3] = LLVMGetUndef(ctx->f32);
4888
4889 if (!values)
4890 return;
4891
4892 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4893 LLVMValueRef val[4];
4894 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4895 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4896 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4897
4898 switch(col_format) {
4899 case V_028714_SPI_SHADER_ZERO:
4900 args->enabled_channels = 0; /* writemask */
4901 args->target = V_008DFC_SQ_EXP_NULL;
4902 break;
4903
4904 case V_028714_SPI_SHADER_32_R:
4905 args->enabled_channels = 1;
4906 args->out[0] = values[0];
4907 break;
4908
4909 case V_028714_SPI_SHADER_32_GR:
4910 args->enabled_channels = 0x3;
4911 args->out[0] = values[0];
4912 args->out[1] = values[1];
4913 break;
4914
4915 case V_028714_SPI_SHADER_32_AR:
4916 args->enabled_channels = 0x9;
4917 args->out[0] = values[0];
4918 args->out[3] = values[3];
4919 break;
4920
4921 case V_028714_SPI_SHADER_FP16_ABGR:
4922 args->compr = 1;
4923
4924 for (unsigned chan = 0; chan < 2; chan++) {
4925 LLVMValueRef pack_args[2] = {
4926 values[2 * chan],
4927 values[2 * chan + 1]
4928 };
4929 LLVMValueRef packed;
4930
4931 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
4932 args->out[chan] = packed;
4933 }
4934 break;
4935
4936 case V_028714_SPI_SHADER_UNORM16_ABGR:
4937 for (unsigned chan = 0; chan < 4; chan++) {
4938 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
4939 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4940 LLVMConstReal(ctx->f32, 65535), "");
4941 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4942 LLVMConstReal(ctx->f32, 0.5), "");
4943 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4944 ctx->i32, "");
4945 }
4946
4947 args->compr = 1;
4948 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4949 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4950 break;
4951
4952 case V_028714_SPI_SHADER_SNORM16_ABGR:
4953 for (unsigned chan = 0; chan < 4; chan++) {
4954 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4955 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4956 LLVMConstReal(ctx->f32, 32767), "");
4957
4958 /* If positive, add 0.5, else add -0.5. */
4959 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4960 LLVMBuildSelect(ctx->builder,
4961 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4962 val[chan], ctx->f32zero, ""),
4963 LLVMConstReal(ctx->f32, 0.5),
4964 LLVMConstReal(ctx->f32, -0.5), ""), "");
4965 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4966 }
4967
4968 args->compr = 1;
4969 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4970 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4971 break;
4972
4973 case V_028714_SPI_SHADER_UINT16_ABGR: {
4974 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4975
4976 for (unsigned chan = 0; chan < 4; chan++) {
4977 val[chan] = to_integer(ctx, values[chan]);
4978 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4979 }
4980
4981 args->compr = 1;
4982 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4983 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4984 break;
4985 }
4986
4987 case V_028714_SPI_SHADER_SINT16_ABGR: {
4988 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4989 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4990
4991 /* Clamp. */
4992 for (unsigned chan = 0; chan < 4; chan++) {
4993 val[chan] = to_integer(ctx, values[chan]);
4994 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4995 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4996 }
4997
4998 args->compr = 1;
4999 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5000 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5001 break;
5002 }
5003
5004 default:
5005 case V_028714_SPI_SHADER_32_ABGR:
5006 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5007 break;
5008 }
5009 } else
5010 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5011
5012 for (unsigned i = 0; i < 4; ++i)
5013 args->out[i] = to_float(ctx, args->out[i]);
5014 }
5015
5016 static void
5017 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5018 struct ac_vs_output_info *outinfo)
5019 {
5020 uint32_t param_count = 0;
5021 unsigned target;
5022 unsigned pos_idx, num_pos_exports = 0;
5023 struct ac_export_args args, pos_args[4] = {};
5024 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5025 int i;
5026
5027 outinfo->prim_id_output = 0xffffffff;
5028 outinfo->layer_output = 0xffffffff;
5029 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5030 LLVMValueRef slots[8];
5031 unsigned j;
5032
5033 if (outinfo->cull_dist_mask)
5034 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5035
5036 i = VARYING_SLOT_CLIP_DIST0;
5037 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5038 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5039 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5040
5041 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5042 slots[i] = LLVMGetUndef(ctx->f32);
5043
5044 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5045 target = V_008DFC_SQ_EXP_POS + 3;
5046 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5047 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5048 &args, sizeof(args));
5049 }
5050
5051 target = V_008DFC_SQ_EXP_POS + 2;
5052 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5053 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5054 &args, sizeof(args));
5055
5056 }
5057
5058 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5059 LLVMValueRef values[4];
5060 if (!(ctx->output_mask & (1ull << i)))
5061 continue;
5062
5063 for (unsigned j = 0; j < 4; j++)
5064 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5065 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5066
5067 if (i == VARYING_SLOT_POS) {
5068 target = V_008DFC_SQ_EXP_POS;
5069 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5070 continue;
5071 } else if (i == VARYING_SLOT_PSIZ) {
5072 outinfo->writes_pointsize = true;
5073 psize_value = values[0];
5074 continue;
5075 } else if (i == VARYING_SLOT_LAYER) {
5076 outinfo->writes_layer = true;
5077 layer_value = values[0];
5078 outinfo->layer_output = param_count;
5079 target = V_008DFC_SQ_EXP_PARAM + param_count;
5080 param_count++;
5081 } else if (i == VARYING_SLOT_VIEWPORT) {
5082 outinfo->writes_viewport_index = true;
5083 viewport_index_value = values[0];
5084 continue;
5085 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5086 outinfo->prim_id_output = param_count;
5087 target = V_008DFC_SQ_EXP_PARAM + param_count;
5088 param_count++;
5089 } else if (i >= VARYING_SLOT_VAR0) {
5090 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5091 target = V_008DFC_SQ_EXP_PARAM + param_count;
5092 param_count++;
5093 }
5094
5095 si_llvm_init_export_args(ctx, values, target, &args);
5096
5097 if (target >= V_008DFC_SQ_EXP_POS &&
5098 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5099 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5100 &args, sizeof(args));
5101 } else {
5102 ac_build_export(&ctx->ac, &args);
5103 }
5104 }
5105
5106 /* We need to add the position output manually if it's missing. */
5107 if (!pos_args[0].out[0]) {
5108 pos_args[0].enabled_channels = 0xf;
5109 pos_args[0].valid_mask = 0;
5110 pos_args[0].done = 0;
5111 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5112 pos_args[0].compr = 0;
5113 pos_args[0].out[0] = ctx->f32zero; /* X */
5114 pos_args[0].out[1] = ctx->f32zero; /* Y */
5115 pos_args[0].out[2] = ctx->f32zero; /* Z */
5116 pos_args[0].out[3] = ctx->f32one; /* W */
5117 }
5118
5119 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5120 (outinfo->writes_layer == true ? 4 : 0) |
5121 (outinfo->writes_viewport_index == true ? 8 : 0));
5122 if (mask) {
5123 pos_args[1].enabled_channels = mask;
5124 pos_args[1].valid_mask = 0;
5125 pos_args[1].done = 0;
5126 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5127 pos_args[1].compr = 0;
5128 pos_args[1].out[0] = ctx->f32zero; /* X */
5129 pos_args[1].out[1] = ctx->f32zero; /* Y */
5130 pos_args[1].out[2] = ctx->f32zero; /* Z */
5131 pos_args[1].out[3] = ctx->f32zero; /* W */
5132
5133 if (outinfo->writes_pointsize == true)
5134 pos_args[1].out[0] = psize_value;
5135 if (outinfo->writes_layer == true)
5136 pos_args[1].out[2] = layer_value;
5137 if (outinfo->writes_viewport_index == true)
5138 pos_args[1].out[3] = viewport_index_value;
5139 }
5140 for (i = 0; i < 4; i++) {
5141 if (pos_args[i].out[0])
5142 num_pos_exports++;
5143 }
5144
5145 pos_idx = 0;
5146 for (i = 0; i < 4; i++) {
5147 if (!pos_args[i].out[0])
5148 continue;
5149
5150 /* Specify the target we are exporting */
5151 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5152 if (pos_idx == num_pos_exports)
5153 pos_args[i].done = 1;
5154 ac_build_export(&ctx->ac, &pos_args[i]);
5155 }
5156
5157 outinfo->pos_exports = num_pos_exports;
5158 outinfo->param_exports = param_count;
5159 }
5160
5161 static void
5162 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5163 struct ac_es_output_info *outinfo)
5164 {
5165 int j;
5166 uint64_t max_output_written = 0;
5167 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5168 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5169 int param_index;
5170 int length = 4;
5171
5172 if (!(ctx->output_mask & (1ull << i)))
5173 continue;
5174
5175 if (i == VARYING_SLOT_CLIP_DIST0)
5176 length = ctx->num_output_clips + ctx->num_output_culls;
5177
5178 param_index = shader_io_get_unique_index(i);
5179
5180 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5181
5182 for (j = 0; j < length; j++) {
5183 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5184 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5185
5186 ac_build_buffer_store_dword(&ctx->ac,
5187 ctx->esgs_ring,
5188 out_val, 1,
5189 NULL, ctx->es2gs_offset,
5190 (4 * param_index + j) * 4,
5191 1, 1, true, true);
5192 }
5193 }
5194 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5195 }
5196
5197 static void
5198 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5199 {
5200 LLVMValueRef vertex_id = ctx->rel_auto_id;
5201 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5202 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5203 vertex_dw_stride, "");
5204
5205 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5206 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5207 int length = 4;
5208
5209 if (!(ctx->output_mask & (1ull << i)))
5210 continue;
5211
5212 if (i == VARYING_SLOT_CLIP_DIST0)
5213 length = ctx->num_output_clips + ctx->num_output_culls;
5214 int param = shader_io_get_unique_index(i);
5215 mark_tess_output(ctx, false, param);
5216 if (length > 4)
5217 mark_tess_output(ctx, false, param + 1);
5218 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5219 LLVMConstInt(ctx->i32, param * 4, false),
5220 "");
5221 for (unsigned j = 0; j < length; j++) {
5222 lds_store(ctx, dw_addr,
5223 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5224 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5225 }
5226 }
5227 }
5228
5229 struct ac_build_if_state
5230 {
5231 struct nir_to_llvm_context *ctx;
5232 LLVMValueRef condition;
5233 LLVMBasicBlockRef entry_block;
5234 LLVMBasicBlockRef true_block;
5235 LLVMBasicBlockRef false_block;
5236 LLVMBasicBlockRef merge_block;
5237 };
5238
5239 static LLVMBasicBlockRef
5240 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5241 {
5242 LLVMBasicBlockRef current_block;
5243 LLVMBasicBlockRef next_block;
5244 LLVMBasicBlockRef new_block;
5245
5246 /* get current basic block */
5247 current_block = LLVMGetInsertBlock(ctx->builder);
5248
5249 /* chqeck if there's another block after this one */
5250 next_block = LLVMGetNextBasicBlock(current_block);
5251 if (next_block) {
5252 /* insert the new block before the next block */
5253 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5254 }
5255 else {
5256 /* append new block after current block */
5257 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5258 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5259 }
5260 return new_block;
5261 }
5262
5263 static void
5264 ac_nir_build_if(struct ac_build_if_state *ifthen,
5265 struct nir_to_llvm_context *ctx,
5266 LLVMValueRef condition)
5267 {
5268 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5269
5270 memset(ifthen, 0, sizeof *ifthen);
5271 ifthen->ctx = ctx;
5272 ifthen->condition = condition;
5273 ifthen->entry_block = block;
5274
5275 /* create endif/merge basic block for the phi functions */
5276 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5277
5278 /* create/insert true_block before merge_block */
5279 ifthen->true_block =
5280 LLVMInsertBasicBlockInContext(ctx->context,
5281 ifthen->merge_block,
5282 "if-true-block");
5283
5284 /* successive code goes into the true block */
5285 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5286 }
5287
5288 /**
5289 * End a conditional.
5290 */
5291 static void
5292 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5293 {
5294 LLVMBuilderRef builder = ifthen->ctx->builder;
5295
5296 /* Insert branch to the merge block from current block */
5297 LLVMBuildBr(builder, ifthen->merge_block);
5298
5299 /*
5300 * Now patch in the various branch instructions.
5301 */
5302
5303 /* Insert the conditional branch instruction at the end of entry_block */
5304 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5305 if (ifthen->false_block) {
5306 /* we have an else clause */
5307 LLVMBuildCondBr(builder, ifthen->condition,
5308 ifthen->true_block, ifthen->false_block);
5309 }
5310 else {
5311 /* no else clause */
5312 LLVMBuildCondBr(builder, ifthen->condition,
5313 ifthen->true_block, ifthen->merge_block);
5314 }
5315
5316 /* Resume building code at end of the ifthen->merge_block */
5317 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5318 }
5319
5320 static void
5321 write_tess_factors(struct nir_to_llvm_context *ctx)
5322 {
5323 unsigned stride, outer_comps, inner_comps;
5324 struct ac_build_if_state if_ctx, inner_if_ctx;
5325 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5326 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5327 unsigned tess_inner_index, tess_outer_index;
5328 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5329 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5330 int i;
5331 emit_barrier(ctx);
5332
5333 switch (ctx->options->key.tcs.primitive_mode) {
5334 case GL_ISOLINES:
5335 stride = 2;
5336 outer_comps = 2;
5337 inner_comps = 0;
5338 break;
5339 case GL_TRIANGLES:
5340 stride = 4;
5341 outer_comps = 3;
5342 inner_comps = 1;
5343 break;
5344 case GL_QUADS:
5345 stride = 6;
5346 outer_comps = 4;
5347 inner_comps = 2;
5348 break;
5349 default:
5350 return;
5351 }
5352
5353 ac_nir_build_if(&if_ctx, ctx,
5354 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5355 invocation_id, ctx->i32zero, ""));
5356
5357 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5358 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5359
5360 mark_tess_output(ctx, true, tess_inner_index);
5361 mark_tess_output(ctx, true, tess_outer_index);
5362 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5363 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5364 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5365 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5366 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5367
5368 for (i = 0; i < 4; i++) {
5369 inner[i] = LLVMGetUndef(ctx->i32);
5370 outer[i] = LLVMGetUndef(ctx->i32);
5371 }
5372
5373 // LINES reverseal
5374 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5375 outer[0] = out[1] = lds_load(ctx, lds_outer);
5376 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5377 LLVMConstInt(ctx->i32, 1, false), "");
5378 outer[1] = out[0] = lds_load(ctx, lds_outer);
5379 } else {
5380 for (i = 0; i < outer_comps; i++) {
5381 outer[i] = out[i] =
5382 lds_load(ctx, lds_outer);
5383 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5384 LLVMConstInt(ctx->i32, 1, false), "");
5385 }
5386 for (i = 0; i < inner_comps; i++) {
5387 inner[i] = out[outer_comps+i] =
5388 lds_load(ctx, lds_inner);
5389 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5390 LLVMConstInt(ctx->i32, 1, false), "");
5391 }
5392 }
5393
5394 /* Convert the outputs to vectors for stores. */
5395 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5396 vec1 = NULL;
5397
5398 if (stride > 4)
5399 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5400
5401
5402 buffer = ctx->hs_ring_tess_factor;
5403 tf_base = ctx->tess_factor_offset;
5404 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5405 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5406
5407 ac_nir_build_if(&inner_if_ctx, ctx,
5408 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5409 rel_patch_id, ctx->i32zero, ""));
5410
5411 /* Store the dynamic HS control word. */
5412 ac_build_buffer_store_dword(&ctx->ac, buffer,
5413 LLVMConstInt(ctx->i32, 0x80000000, false),
5414 1, ctx->i32zero, tf_base,
5415 0, 1, 0, true, false);
5416 ac_nir_build_endif(&inner_if_ctx);
5417
5418 /* Store the tessellation factors. */
5419 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5420 MIN2(stride, 4), byteoffset, tf_base,
5421 4, 1, 0, true, false);
5422 if (vec1)
5423 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5424 stride - 4, byteoffset, tf_base,
5425 20, 1, 0, true, false);
5426
5427 //TODO store to offchip for TES to read - only if TES reads them
5428 if (1) {
5429 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5430 LLVMValueRef tf_inner_offset;
5431 unsigned param_outer, param_inner;
5432
5433 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5434 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5435 LLVMConstInt(ctx->i32, param_outer, 0));
5436
5437 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5438 util_next_power_of_two(outer_comps));
5439
5440 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5441 outer_comps, tf_outer_offset,
5442 ctx->oc_lds, 0, 1, 0, true, false);
5443 if (inner_comps) {
5444 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5445 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5446 LLVMConstInt(ctx->i32, param_inner, 0));
5447
5448 inner_vec = inner_comps == 1 ? inner[0] :
5449 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5450 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5451 inner_comps, tf_inner_offset,
5452 ctx->oc_lds, 0, 1, 0, true, false);
5453 }
5454 }
5455 ac_nir_build_endif(&if_ctx);
5456 }
5457
5458 static void
5459 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5460 {
5461 write_tess_factors(ctx);
5462 }
5463
5464 static void
5465 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5466 LLVMValueRef *color, unsigned param, bool is_last)
5467 {
5468
5469 struct ac_export_args args;
5470
5471 /* Export */
5472 si_llvm_init_export_args(ctx, color, param,
5473 &args);
5474
5475 if (is_last) {
5476 args.valid_mask = 1; /* whether the EXEC mask is valid */
5477 args.done = 1; /* DONE bit */
5478 } else if (!args.enabled_channels)
5479 return; /* unnecessary NULL export */
5480
5481 ac_build_export(&ctx->ac, &args);
5482 }
5483
5484 static void
5485 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5486 LLVMValueRef depth, LLVMValueRef stencil,
5487 LLVMValueRef samplemask)
5488 {
5489 struct ac_export_args args;
5490
5491 args.enabled_channels = 0;
5492 args.valid_mask = 1;
5493 args.done = 1;
5494 args.target = V_008DFC_SQ_EXP_MRTZ;
5495 args.compr = false;
5496
5497 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5498 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5499 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5500 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5501
5502 if (depth) {
5503 args.out[0] = depth;
5504 args.enabled_channels |= 0x1;
5505 }
5506
5507 if (stencil) {
5508 args.out[1] = stencil;
5509 args.enabled_channels |= 0x2;
5510 }
5511
5512 if (samplemask) {
5513 args.out[2] = samplemask;
5514 args.enabled_channels |= 0x4;
5515 }
5516
5517 /* SI (except OLAND) has a bug that it only looks
5518 * at the X writemask component. */
5519 if (ctx->options->chip_class == SI &&
5520 ctx->options->family != CHIP_OLAND)
5521 args.enabled_channels |= 0x1;
5522
5523 ac_build_export(&ctx->ac, &args);
5524 }
5525
5526 static void
5527 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5528 {
5529 unsigned index = 0;
5530 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5531
5532 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5533 LLVMValueRef values[4];
5534
5535 if (!(ctx->output_mask & (1ull << i)))
5536 continue;
5537
5538 if (i == FRAG_RESULT_DEPTH) {
5539 ctx->shader_info->fs.writes_z = true;
5540 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
5541 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5542 } else if (i == FRAG_RESULT_STENCIL) {
5543 ctx->shader_info->fs.writes_stencil = true;
5544 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
5545 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5546 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5547 ctx->shader_info->fs.writes_sample_mask = true;
5548 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
5549 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5550 } else {
5551 bool last = false;
5552 for (unsigned j = 0; j < 4; j++)
5553 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5554 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5555
5556 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5557 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5558
5559 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
5560 index++;
5561 }
5562 }
5563
5564 if (depth || stencil || samplemask)
5565 si_export_mrt_z(ctx, depth, stencil, samplemask);
5566 else if (!index)
5567 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
5568
5569 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5570 }
5571
5572 static void
5573 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5574 {
5575 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5576 }
5577
5578 static void
5579 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5580 {
5581 switch (ctx->stage) {
5582 case MESA_SHADER_VERTEX:
5583 if (ctx->options->key.vs.as_ls)
5584 handle_ls_outputs_post(ctx);
5585 else if (ctx->options->key.vs.as_es)
5586 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5587 else
5588 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5589 break;
5590 case MESA_SHADER_FRAGMENT:
5591 handle_fs_outputs_post(ctx);
5592 break;
5593 case MESA_SHADER_GEOMETRY:
5594 emit_gs_epilogue(ctx);
5595 break;
5596 case MESA_SHADER_TESS_CTRL:
5597 handle_tcs_outputs_post(ctx);
5598 break;
5599 case MESA_SHADER_TESS_EVAL:
5600 if (ctx->options->key.tes.as_es)
5601 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5602 else
5603 handle_vs_outputs_post(ctx, &ctx->shader_info->tes.outinfo);
5604 break;
5605 default:
5606 break;
5607 }
5608 }
5609
5610 static void
5611 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5612 struct nir_variable *variable, uint32_t *offset, int idx)
5613 {
5614 unsigned size = glsl_count_attribute_slots(variable->type, false);
5615 variable->data.driver_location = *offset;
5616 *offset += size;
5617 }
5618
5619 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5620 {
5621 LLVMPassManagerRef passmgr;
5622 /* Create the pass manager */
5623 passmgr = LLVMCreateFunctionPassManagerForModule(
5624 ctx->module);
5625
5626 /* This pass should eliminate all the load and store instructions */
5627 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5628
5629 /* Add some optimization passes */
5630 LLVMAddScalarReplAggregatesPass(passmgr);
5631 LLVMAddLICMPass(passmgr);
5632 LLVMAddAggressiveDCEPass(passmgr);
5633 LLVMAddCFGSimplificationPass(passmgr);
5634 LLVMAddInstructionCombiningPass(passmgr);
5635
5636 /* Run the pass */
5637 LLVMInitializeFunctionPassManager(passmgr);
5638 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5639 LLVMFinalizeFunctionPassManager(passmgr);
5640
5641 LLVMDisposeBuilder(ctx->builder);
5642 LLVMDisposePassManager(passmgr);
5643 }
5644
5645 static void
5646 ac_setup_rings(struct nir_to_llvm_context *ctx)
5647 {
5648 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5649 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5650 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5651 }
5652
5653 if (ctx->is_gs_copy_shader) {
5654 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5655 }
5656 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5657 LLVMValueRef tmp;
5658 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5659 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5660
5661 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5662
5663 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5664 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5665 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5666 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5667
5668 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5669 }
5670
5671 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5672 ctx->stage == MESA_SHADER_TESS_EVAL) {
5673 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5674 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5675 }
5676 }
5677
5678 static
5679 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5680 struct nir_shader *nir,
5681 struct ac_shader_variant_info *shader_info,
5682 const struct ac_nir_compiler_options *options)
5683 {
5684 struct nir_to_llvm_context ctx = {0};
5685 struct nir_function *func;
5686 unsigned i;
5687 ctx.options = options;
5688 ctx.shader_info = shader_info;
5689 ctx.context = LLVMContextCreate();
5690 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5691
5692 ac_llvm_context_init(&ctx.ac, ctx.context);
5693 ctx.ac.module = ctx.module;
5694
5695 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5696
5697 memset(shader_info, 0, sizeof(*shader_info));
5698
5699 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5700
5701 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5702 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5703 LLVMSetDataLayout(ctx.module, data_layout_str);
5704 LLVMDisposeTargetData(data_layout);
5705 LLVMDisposeMessage(data_layout_str);
5706
5707 setup_types(&ctx);
5708
5709 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5710 ctx.ac.builder = ctx.builder;
5711 ctx.stage = nir->stage;
5712
5713 for (i = 0; i < AC_UD_MAX_SETS; i++)
5714 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5715 for (i = 0; i < AC_UD_MAX_UD; i++)
5716 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5717
5718 create_function(&ctx);
5719
5720 if (nir->stage == MESA_SHADER_COMPUTE) {
5721 int num_shared = 0;
5722 nir_foreach_variable(variable, &nir->shared)
5723 num_shared++;
5724 if (num_shared) {
5725 int idx = 0;
5726 uint32_t shared_size = 0;
5727 LLVMValueRef var;
5728 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5729 nir_foreach_variable(variable, &nir->shared) {
5730 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5731 idx++;
5732 }
5733
5734 shared_size *= 16;
5735 var = LLVMAddGlobalInAddressSpace(ctx.module,
5736 LLVMArrayType(ctx.i8, shared_size),
5737 "compute_lds",
5738 LOCAL_ADDR_SPACE);
5739 LLVMSetAlignment(var, 4);
5740 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5741 }
5742 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5743 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5744
5745 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
5746 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5747 ctx.tes_primitive_mode = nir->info->tess.primitive_mode;
5748 }
5749
5750 ac_setup_rings(&ctx);
5751
5752 nir_foreach_variable(variable, &nir->inputs)
5753 handle_shader_input_decl(&ctx, variable);
5754
5755 if (nir->stage == MESA_SHADER_FRAGMENT)
5756 handle_fs_inputs_pre(&ctx, nir);
5757
5758 ctx.num_output_clips = nir->info->clip_distance_array_size;
5759 ctx.num_output_culls = nir->info->cull_distance_array_size;
5760
5761 nir_foreach_variable(variable, &nir->outputs)
5762 handle_shader_output_decl(&ctx, variable);
5763
5764 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5765 _mesa_key_pointer_equal);
5766 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5767 _mesa_key_pointer_equal);
5768
5769 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5770
5771 setup_locals(&ctx, func);
5772
5773 visit_cf_list(&ctx, &func->impl->body);
5774 phi_post_pass(&ctx);
5775
5776 handle_shader_outputs_post(&ctx);
5777 LLVMBuildRetVoid(ctx.builder);
5778
5779 ac_llvm_finalize_module(&ctx);
5780 free(ctx.locals);
5781 ralloc_free(ctx.defs);
5782 ralloc_free(ctx.phis);
5783
5784 if (nir->stage == MESA_SHADER_GEOMETRY) {
5785 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
5786 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
5787 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5788 nir->info->gs.vertices_out;
5789 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
5790 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
5791 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
5792 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
5793 shader_info->vs.outputs_written = ctx.tess_outputs_written;
5794 }
5795
5796 return ctx.module;
5797 }
5798
5799 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
5800 {
5801 unsigned *retval = (unsigned *)context;
5802 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5803 char *description = LLVMGetDiagInfoDescription(di);
5804
5805 if (severity == LLVMDSError) {
5806 *retval = 1;
5807 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5808 description);
5809 }
5810
5811 LLVMDisposeMessage(description);
5812 }
5813
5814 static unsigned ac_llvm_compile(LLVMModuleRef M,
5815 struct ac_shader_binary *binary,
5816 LLVMTargetMachineRef tm)
5817 {
5818 unsigned retval = 0;
5819 char *err;
5820 LLVMContextRef llvm_ctx;
5821 LLVMMemoryBufferRef out_buffer;
5822 unsigned buffer_size;
5823 const char *buffer_data;
5824 LLVMBool mem_err;
5825
5826 /* Setup Diagnostic Handler*/
5827 llvm_ctx = LLVMGetModuleContext(M);
5828
5829 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5830 &retval);
5831
5832 /* Compile IR*/
5833 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5834 &err, &out_buffer);
5835
5836 /* Process Errors/Warnings */
5837 if (mem_err) {
5838 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5839 free(err);
5840 retval = 1;
5841 goto out;
5842 }
5843
5844 /* Extract Shader Code*/
5845 buffer_size = LLVMGetBufferSize(out_buffer);
5846 buffer_data = LLVMGetBufferStart(out_buffer);
5847
5848 ac_elf_read(buffer_data, buffer_size, binary);
5849
5850 /* Clean up */
5851 LLVMDisposeMemoryBuffer(out_buffer);
5852
5853 out:
5854 return retval;
5855 }
5856
5857 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5858 LLVMModuleRef llvm_module,
5859 struct ac_shader_binary *binary,
5860 struct ac_shader_config *config,
5861 struct ac_shader_variant_info *shader_info,
5862 gl_shader_stage stage,
5863 bool dump_shader, bool supports_spill)
5864 {
5865 if (dump_shader)
5866 ac_dump_module(llvm_module);
5867
5868 memset(binary, 0, sizeof(*binary));
5869 int v = ac_llvm_compile(llvm_module, binary, tm);
5870 if (v) {
5871 fprintf(stderr, "compile failed\n");
5872 }
5873
5874 if (dump_shader)
5875 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5876
5877 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5878
5879 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5880 LLVMDisposeModule(llvm_module);
5881 LLVMContextDispose(ctx);
5882
5883 if (stage == MESA_SHADER_FRAGMENT) {
5884 shader_info->num_input_vgprs = 0;
5885 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5886 shader_info->num_input_vgprs += 2;
5887 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5888 shader_info->num_input_vgprs += 2;
5889 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5890 shader_info->num_input_vgprs += 2;
5891 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5892 shader_info->num_input_vgprs += 3;
5893 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5894 shader_info->num_input_vgprs += 2;
5895 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5896 shader_info->num_input_vgprs += 2;
5897 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5898 shader_info->num_input_vgprs += 2;
5899 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5900 shader_info->num_input_vgprs += 1;
5901 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5902 shader_info->num_input_vgprs += 1;
5903 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5904 shader_info->num_input_vgprs += 1;
5905 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5906 shader_info->num_input_vgprs += 1;
5907 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5908 shader_info->num_input_vgprs += 1;
5909 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5910 shader_info->num_input_vgprs += 1;
5911 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5912 shader_info->num_input_vgprs += 1;
5913 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5914 shader_info->num_input_vgprs += 1;
5915 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5916 shader_info->num_input_vgprs += 1;
5917 }
5918 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5919
5920 /* +3 for scratch wave offset and VCC */
5921 config->num_sgprs = MAX2(config->num_sgprs,
5922 shader_info->num_input_sgprs + 3);
5923 }
5924
5925 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5926 struct ac_shader_binary *binary,
5927 struct ac_shader_config *config,
5928 struct ac_shader_variant_info *shader_info,
5929 struct nir_shader *nir,
5930 const struct ac_nir_compiler_options *options,
5931 bool dump_shader)
5932 {
5933
5934 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5935 options);
5936
5937 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5938 switch (nir->stage) {
5939 case MESA_SHADER_COMPUTE:
5940 for (int i = 0; i < 3; ++i)
5941 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5942 break;
5943 case MESA_SHADER_FRAGMENT:
5944 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5945 break;
5946 case MESA_SHADER_GEOMETRY:
5947 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5948 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5949 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5950 shader_info->gs.invocations = nir->info->gs.invocations;
5951 break;
5952 case MESA_SHADER_TESS_EVAL:
5953 shader_info->tes.primitive_mode = nir->info->tess.primitive_mode;
5954 shader_info->tes.spacing = nir->info->tess.spacing;
5955 shader_info->tes.ccw = nir->info->tess.ccw;
5956 shader_info->tes.point_mode = nir->info->tess.point_mode;
5957 shader_info->tes.as_es = options->key.tes.as_es;
5958 break;
5959 case MESA_SHADER_TESS_CTRL:
5960 shader_info->tcs.tcs_vertices_out = nir->info->tess.tcs_vertices_out;
5961 break;
5962 case MESA_SHADER_VERTEX:
5963 shader_info->vs.as_es = options->key.vs.as_es;
5964 shader_info->vs.as_ls = options->key.vs.as_ls;
5965 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
5966 if (options->key.vs.as_ls)
5967 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
5968 break;
5969 default:
5970 break;
5971 }
5972 }
5973
5974 static void
5975 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5976 {
5977 LLVMValueRef args[9];
5978 args[0] = ctx->gsvs_ring;
5979 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5980 args[3] = ctx->i32zero;
5981 args[4] = ctx->i32one; /* OFFEN */
5982 args[5] = ctx->i32zero; /* IDXEN */
5983 args[6] = ctx->i32one; /* GLC */
5984 args[7] = ctx->i32one; /* SLC */
5985 args[8] = ctx->i32zero; /* TFE */
5986
5987 int idx = 0;
5988
5989 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5990 int length = 4;
5991 int slot = idx;
5992 int slot_inc = 1;
5993 if (!(ctx->output_mask & (1ull << i)))
5994 continue;
5995
5996 if (i == VARYING_SLOT_CLIP_DIST0) {
5997 /* unpack clip and cull from a single set of slots */
5998 length = ctx->num_output_clips + ctx->num_output_culls;
5999 if (length > 4)
6000 slot_inc = 2;
6001 }
6002
6003 for (unsigned j = 0; j < length; j++) {
6004 LLVMValueRef value;
6005 args[2] = LLVMConstInt(ctx->i32,
6006 (slot * 4 + j) *
6007 ctx->gs_max_out_vertices * 16 * 4, false);
6008
6009 value = ac_build_intrinsic(&ctx->ac,
6010 "llvm.SI.buffer.load.dword.i32.i32",
6011 ctx->i32, args, 9,
6012 AC_FUNC_ATTR_READONLY |
6013 AC_FUNC_ATTR_LEGACY);
6014
6015 LLVMBuildStore(ctx->builder,
6016 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6017 }
6018 idx += slot_inc;
6019 }
6020 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
6021 }
6022
6023 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6024 struct nir_shader *geom_shader,
6025 struct ac_shader_binary *binary,
6026 struct ac_shader_config *config,
6027 struct ac_shader_variant_info *shader_info,
6028 const struct ac_nir_compiler_options *options,
6029 bool dump_shader)
6030 {
6031 struct nir_to_llvm_context ctx = {0};
6032 ctx.context = LLVMContextCreate();
6033 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6034 ctx.options = options;
6035 ctx.shader_info = shader_info;
6036
6037 ac_llvm_context_init(&ctx.ac, ctx.context);
6038 ctx.ac.module = ctx.module;
6039
6040 ctx.is_gs_copy_shader = true;
6041 LLVMSetTarget(ctx.module, "amdgcn--");
6042 setup_types(&ctx);
6043
6044 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6045 ctx.ac.builder = ctx.builder;
6046 ctx.stage = MESA_SHADER_VERTEX;
6047
6048 create_function(&ctx);
6049
6050 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
6051 ac_setup_rings(&ctx);
6052
6053 ctx.num_output_clips = geom_shader->info->clip_distance_array_size;
6054 ctx.num_output_culls = geom_shader->info->cull_distance_array_size;
6055
6056 nir_foreach_variable(variable, &geom_shader->outputs)
6057 handle_shader_output_decl(&ctx, variable);
6058
6059 ac_gs_copy_shader_emit(&ctx);
6060
6061 LLVMBuildRetVoid(ctx.builder);
6062
6063 ac_llvm_finalize_module(&ctx);
6064
6065 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6066 MESA_SHADER_VERTEX,
6067 dump_shader, options->supports_spill);
6068 }