projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv/ac: setup tessellation shader inputs.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83 LLVMValueRef ls_out_layout;
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef tcs_offchip_layout;
87 LLVMValueRef tcs_out_offsets;
88 LLVMValueRef tcs_out_layout;
89 LLVMValueRef tcs_in_layout;
90 LLVMValueRef oc_lds;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tcs_patch_id;
93 LLVMValueRef tcs_rel_ids;
94 LLVMValueRef tes_rel_patch_id;
95 LLVMValueRef tes_patch_id;
96 LLVMValueRef tes_u;
97 LLVMValueRef tes_v;
98
99 LLVMValueRef gsvs_ring_stride;
100 LLVMValueRef gsvs_num_entries;
101 LLVMValueRef gs2vs_offset;
102 LLVMValueRef gs_wave_id;
103 LLVMValueRef gs_vtx_offset[6];
104 LLVMValueRef gs_prim_id, gs_invocation_id;
105
106 LLVMValueRef esgs_ring;
107 LLVMValueRef gsvs_ring;
108 LLVMValueRef hs_ring_tess_offchip;
109 LLVMValueRef hs_ring_tess_factor;
110
111 LLVMValueRef prim_mask;
112 LLVMValueRef sample_positions;
113 LLVMValueRef persp_sample, persp_center, persp_centroid;
114 LLVMValueRef linear_sample, linear_center, linear_centroid;
115 LLVMValueRef front_face;
116 LLVMValueRef ancillary;
117 LLVMValueRef sample_coverage;
118 LLVMValueRef frag_pos[4];
119
120 LLVMBasicBlockRef continue_block;
121 LLVMBasicBlockRef break_block;
122
123 LLVMTypeRef i1;
124 LLVMTypeRef i8;
125 LLVMTypeRef i16;
126 LLVMTypeRef i32;
127 LLVMTypeRef i64;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v3i32;
130 LLVMTypeRef v4i32;
131 LLVMTypeRef v8i32;
132 LLVMTypeRef f64;
133 LLVMTypeRef f32;
134 LLVMTypeRef f16;
135 LLVMTypeRef v2f32;
136 LLVMTypeRef v4f32;
137 LLVMTypeRef v16i8;
138 LLVMTypeRef voidt;
139
140 LLVMValueRef i1true;
141 LLVMValueRef i1false;
142 LLVMValueRef i32zero;
143 LLVMValueRef i32one;
144 LLVMValueRef f32zero;
145 LLVMValueRef f32one;
146 LLVMValueRef v4f32empty;
147
148 unsigned uniform_md_kind;
149 LLVMValueRef empty_md;
150 gl_shader_stage stage;
151
152 LLVMValueRef lds;
153 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
154 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
155
156 LLVMValueRef shared_memory;
157 uint64_t input_mask;
158 uint64_t output_mask;
159 int num_locals;
160 LLVMValueRef *locals;
161 bool has_ddxy;
162 uint8_t num_output_clips;
163 uint8_t num_output_culls;
164
165 bool has_ds_bpermute;
166
167 bool is_gs_copy_shader;
168 LLVMValueRef gs_next_vertex;
169 unsigned gs_max_out_vertices;
170 };
171
172 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
173 nir_deref_var *deref,
174 enum desc_type desc_type);
175 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
176 {
177 return (index * 4) + chan;
178 }
179
180 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
181 {
182 if (slot == VARYING_SLOT_POS)
183 return 0;
184 if (slot == VARYING_SLOT_PSIZ)
185 return 1;
186 if (slot == VARYING_SLOT_CLIP_DIST0)
187 return 2;
188 /* 3 is reserved for clip dist as well */
189 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
190 return 4 + (slot - VARYING_SLOT_VAR0);
191 unreachable("illegal slot in get unique index\n");
192 }
193
194 static unsigned llvm_get_type_size(LLVMTypeRef type)
195 {
196 LLVMTypeKind kind = LLVMGetTypeKind(type);
197
198 switch (kind) {
199 case LLVMIntegerTypeKind:
200 return LLVMGetIntTypeWidth(type) / 8;
201 case LLVMFloatTypeKind:
202 return 4;
203 case LLVMPointerTypeKind:
204 return 8;
205 case LLVMVectorTypeKind:
206 return LLVMGetVectorSize(type) *
207 llvm_get_type_size(LLVMGetElementType(type));
208 default:
209 assert(0);
210 return 0;
211 }
212 }
213
214 static void set_llvm_calling_convention(LLVMValueRef func,
215 gl_shader_stage stage)
216 {
217 enum radeon_llvm_calling_convention calling_conv;
218
219 switch (stage) {
220 case MESA_SHADER_VERTEX:
221 case MESA_SHADER_TESS_CTRL:
222 case MESA_SHADER_TESS_EVAL:
223 calling_conv = RADEON_LLVM_AMDGPU_VS;
224 break;
225 case MESA_SHADER_GEOMETRY:
226 calling_conv = RADEON_LLVM_AMDGPU_GS;
227 break;
228 case MESA_SHADER_FRAGMENT:
229 calling_conv = RADEON_LLVM_AMDGPU_PS;
230 break;
231 case MESA_SHADER_COMPUTE:
232 calling_conv = RADEON_LLVM_AMDGPU_CS;
233 break;
234 default:
235 unreachable("Unhandle shader type");
236 }
237
238 LLVMSetFunctionCallConv(func, calling_conv);
239 }
240
241 static LLVMValueRef
242 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
243 LLVMBuilderRef builder, LLVMTypeRef *return_types,
244 unsigned num_return_elems, LLVMTypeRef *param_types,
245 unsigned param_count, unsigned array_params_mask,
246 unsigned sgpr_params, bool unsafe_math)
247 {
248 LLVMTypeRef main_function_type, ret_type;
249 LLVMBasicBlockRef main_function_body;
250
251 if (num_return_elems)
252 ret_type = LLVMStructTypeInContext(ctx, return_types,
253 num_return_elems, true);
254 else
255 ret_type = LLVMVoidTypeInContext(ctx);
256
257 /* Setup the function */
258 main_function_type =
259 LLVMFunctionType(ret_type, param_types, param_count, 0);
260 LLVMValueRef main_function =
261 LLVMAddFunction(module, "main", main_function_type);
262 main_function_body =
263 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
264 LLVMPositionBuilderAtEnd(builder, main_function_body);
265
266 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
267 for (unsigned i = 0; i < sgpr_params; ++i) {
268 if (array_params_mask & (1 << i)) {
269 LLVMValueRef P = LLVMGetParam(main_function, i);
270 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
271 ac_add_attr_dereferenceable(P, UINT64_MAX);
272 }
273 else {
274 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
275 }
276 }
277
278 if (unsafe_math) {
279 /* These were copied from some LLVM test. */
280 LLVMAddTargetDependentFunctionAttr(main_function,
281 "less-precise-fpmad",
282 "true");
283 LLVMAddTargetDependentFunctionAttr(main_function,
284 "no-infs-fp-math",
285 "true");
286 LLVMAddTargetDependentFunctionAttr(main_function,
287 "no-nans-fp-math",
288 "true");
289 LLVMAddTargetDependentFunctionAttr(main_function,
290 "unsafe-fp-math",
291 "true");
292 }
293 return main_function;
294 }
295
296 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
297 {
298 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
299 CONST_ADDR_SPACE);
300 }
301
302 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
303 int idx,
304 LLVMTypeRef type)
305 {
306 LLVMValueRef offset;
307 LLVMValueRef ptr;
308 int addr_space;
309
310 offset = LLVMConstInt(ctx->i32, idx * 16, false);
311
312 ptr = ctx->shared_memory;
313 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
314 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
315 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
316 return ptr;
317 }
318
319 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
320 {
321 if (t == ctx->f16 || t == ctx->i16)
322 return ctx->i16;
323 else if (t == ctx->f32 || t == ctx->i32)
324 return ctx->i32;
325 else if (t == ctx->f64 || t == ctx->i64)
326 return ctx->i64;
327 else
328 unreachable("Unhandled integer size");
329 }
330
331 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
332 {
333 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
334 LLVMTypeRef elem_type = LLVMGetElementType(t);
335 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
336 LLVMGetVectorSize(t));
337 }
338 return to_integer_type_scalar(ctx, t);
339 }
340
341 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
342 {
343 LLVMTypeRef type = LLVMTypeOf(v);
344 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
345 }
346
347 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
348 {
349 if (t == ctx->i16 || t == ctx->f16)
350 return ctx->f16;
351 else if (t == ctx->i32 || t == ctx->f32)
352 return ctx->f32;
353 else if (t == ctx->i64 || t == ctx->f64)
354 return ctx->f64;
355 else
356 unreachable("Unhandled float size");
357 }
358
359 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
360 {
361 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
362 LLVMTypeRef elem_type = LLVMGetElementType(t);
363 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
364 LLVMGetVectorSize(t));
365 }
366 return to_float_type_scalar(ctx, t);
367 }
368
369 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
370 {
371 LLVMTypeRef type = LLVMTypeOf(v);
372 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
373 }
374
375 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
376 {
377 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
378 type = LLVMGetElementType(type);
379
380 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
381 return LLVMGetIntTypeWidth(type);
382
383 if (type == ctx->f16)
384 return 16;
385 if (type == ctx->f32)
386 return 32;
387 if (type == ctx->f64)
388 return 64;
389
390 unreachable("Unhandled type kind in get_elem_bits");
391 }
392
393 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
394 LLVMValueRef param, unsigned rshift,
395 unsigned bitwidth)
396 {
397 LLVMValueRef value = param;
398 if (rshift)
399 value = LLVMBuildLShr(ctx->builder, value,
400 LLVMConstInt(ctx->i32, rshift, false), "");
401
402 if (rshift + bitwidth < 32) {
403 unsigned mask = (1 << bitwidth) - 1;
404 value = LLVMBuildAnd(ctx->builder, value,
405 LLVMConstInt(ctx->i32, mask, false), "");
406 }
407 return value;
408 }
409
410 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
411 {
412 ud_info->sgpr_idx = sgpr_idx;
413 ud_info->num_sgprs = num_sgprs;
414 ud_info->indirect = false;
415 ud_info->indirect_offset = 0;
416 }
417
418 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
419 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
420 {
421 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
422 }
423
424 #if 0
425 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
426 uint32_t indirect_offset)
427 {
428 ud_info->sgpr_idx = sgpr_idx;
429 ud_info->num_sgprs = num_sgprs;
430 ud_info->indirect = true;
431 ud_info->indirect_offset = indirect_offset;
432 }
433 #endif
434
435 static void create_function(struct nir_to_llvm_context *ctx)
436 {
437 LLVMTypeRef arg_types[23];
438 unsigned arg_idx = 0;
439 unsigned array_params_mask = 0;
440 unsigned sgpr_count = 0, user_sgpr_count;
441 unsigned i;
442 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
443 unsigned user_sgpr_idx;
444 bool need_push_constants;
445 bool need_ring_offsets = false;
446
447 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
448 if (ctx->stage == MESA_SHADER_GEOMETRY ||
449 ctx->stage == MESA_SHADER_VERTEX ||
450 ctx->stage == MESA_SHADER_TESS_CTRL ||
451 ctx->stage == MESA_SHADER_TESS_EVAL ||
452 ctx->is_gs_copy_shader)
453 need_ring_offsets = true;
454
455 need_push_constants = true;
456 if (!ctx->options->layout)
457 need_push_constants = false;
458 else if (!ctx->options->layout->push_constant_size &&
459 !ctx->options->layout->dynamic_offset_count)
460 need_push_constants = false;
461
462 if (need_ring_offsets && !ctx->options->supports_spill) {
463 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
464 }
465
466 /* 1 for each descriptor set */
467 for (unsigned i = 0; i < num_sets; ++i) {
468 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
469 array_params_mask |= (1 << arg_idx);
470 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
471 }
472 }
473
474 if (need_push_constants) {
475 /* 1 for push constants and dynamic descriptors */
476 array_params_mask |= (1 << arg_idx);
477 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
478 }
479
480 switch (ctx->stage) {
481 case MESA_SHADER_COMPUTE:
482 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
483 user_sgpr_count = arg_idx;
484 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
485 arg_types[arg_idx++] = ctx->i32;
486 sgpr_count = arg_idx;
487
488 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
489 break;
490 case MESA_SHADER_VERTEX:
491 if (!ctx->is_gs_copy_shader) {
492 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
493 arg_types[arg_idx++] = ctx->i32; // base vertex
494 arg_types[arg_idx++] = ctx->i32; // start instance
495 arg_types[arg_idx++] = ctx->i32; // draw index
496 }
497 user_sgpr_count = arg_idx;
498 if (ctx->options->key.vs.as_es)
499 arg_types[arg_idx++] = ctx->i32; //es2gs offset
500 else if (ctx->options->key.vs.as_ls) {
501 arg_types[arg_idx++] = ctx->i32; //ls out layout
502 user_sgpr_count++;
503 }
504 sgpr_count = arg_idx;
505 arg_types[arg_idx++] = ctx->i32; // vertex id
506 if (!ctx->is_gs_copy_shader) {
507 arg_types[arg_idx++] = ctx->i32; // rel auto id
508 arg_types[arg_idx++] = ctx->i32; // vs prim id
509 arg_types[arg_idx++] = ctx->i32; // instance id
510 }
511 break;
512 case MESA_SHADER_TESS_CTRL:
513 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
514 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
515 arg_types[arg_idx++] = ctx->i32; // tcs out layout
516 arg_types[arg_idx++] = ctx->i32; // tcs in layout
517 user_sgpr_count = arg_idx;
518 arg_types[arg_idx++] = ctx->i32; // param oc lds
519 arg_types[arg_idx++] = ctx->i32; // tess factor offset
520 sgpr_count = arg_idx;
521 arg_types[arg_idx++] = ctx->i32; // patch id
522 arg_types[arg_idx++] = ctx->i32; // rel ids;
523 break;
524 case MESA_SHADER_TESS_EVAL:
525 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
526 user_sgpr_count = arg_idx;
527 if (ctx->options->key.tes.as_es) {
528 arg_types[arg_idx++] = ctx->i32; // OC LDS
529 arg_types[arg_idx++] = ctx->i32; //
530 arg_types[arg_idx++] = ctx->i32; // es2gs offset
531 } else {
532 arg_types[arg_idx++] = ctx->i32; //
533 arg_types[arg_idx++] = ctx->i32; // OC LDS
534 }
535 sgpr_count = arg_idx;
536 arg_types[arg_idx++] = ctx->f32; // tes_u
537 arg_types[arg_idx++] = ctx->f32; // tes_v
538 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
539 arg_types[arg_idx++] = ctx->i32; // tes patch id
540 break;
541 case MESA_SHADER_GEOMETRY:
542 arg_types[arg_idx++] = ctx->i32; // gsvs stride
543 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
544 user_sgpr_count = arg_idx;
545 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
546 arg_types[arg_idx++] = ctx->i32; // wave id
547 sgpr_count = arg_idx;
548 arg_types[arg_idx++] = ctx->i32; // vtx0
549 arg_types[arg_idx++] = ctx->i32; // vtx1
550 arg_types[arg_idx++] = ctx->i32; // prim id
551 arg_types[arg_idx++] = ctx->i32; // vtx2
552 arg_types[arg_idx++] = ctx->i32; // vtx3
553 arg_types[arg_idx++] = ctx->i32; // vtx4
554 arg_types[arg_idx++] = ctx->i32; // vtx5
555 arg_types[arg_idx++] = ctx->i32; // GS instance id
556 break;
557 case MESA_SHADER_FRAGMENT:
558 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
559 user_sgpr_count = arg_idx;
560 arg_types[arg_idx++] = ctx->i32; /* prim mask */
561 sgpr_count = arg_idx;
562 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
563 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
564 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
565 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
566 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
567 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
568 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
569 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
570 arg_types[arg_idx++] = ctx->f32; /* pos x float */
571 arg_types[arg_idx++] = ctx->f32; /* pos y float */
572 arg_types[arg_idx++] = ctx->f32; /* pos z float */
573 arg_types[arg_idx++] = ctx->f32; /* pos w float */
574 arg_types[arg_idx++] = ctx->i32; /* front face */
575 arg_types[arg_idx++] = ctx->i32; /* ancillary */
576 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
577 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
578 break;
579 default:
580 unreachable("Shader stage not implemented");
581 }
582
583 ctx->main_function = create_llvm_function(
584 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
585 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
586 set_llvm_calling_convention(ctx->main_function, ctx->stage);
587
588 ctx->shader_info->num_input_sgprs = 0;
589 ctx->shader_info->num_input_vgprs = 0;
590
591 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
592 for (i = 0; i < user_sgpr_count; i++)
593 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
594
595 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
596 for (; i < sgpr_count; i++)
597 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
598
599 if (ctx->stage != MESA_SHADER_FRAGMENT)
600 for (; i < arg_idx; ++i)
601 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
602
603 arg_idx = 0;
604 user_sgpr_idx = 0;
605
606 if (ctx->options->supports_spill || need_ring_offsets) {
607 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
608 user_sgpr_idx += 2;
609 if (ctx->options->supports_spill) {
610 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
611 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
612 NULL, 0, AC_FUNC_ATTR_READNONE);
613 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
614 const_array(ctx->v16i8, 8), "");
615 } else
616 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
617 }
618
619 for (unsigned i = 0; i < num_sets; ++i) {
620 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
621 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
622 user_sgpr_idx += 2;
623 ctx->descriptor_sets[i] =
624 LLVMGetParam(ctx->main_function, arg_idx++);
625 } else
626 ctx->descriptor_sets[i] = NULL;
627 }
628
629 if (need_push_constants) {
630 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
631 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
632 user_sgpr_idx += 2;
633 }
634
635 switch (ctx->stage) {
636 case MESA_SHADER_COMPUTE:
637 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
638 user_sgpr_idx += 3;
639 ctx->num_work_groups =
640 LLVMGetParam(ctx->main_function, arg_idx++);
641 ctx->workgroup_ids =
642 LLVMGetParam(ctx->main_function, arg_idx++);
643 ctx->tg_size =
644 LLVMGetParam(ctx->main_function, arg_idx++);
645 ctx->local_invocation_ids =
646 LLVMGetParam(ctx->main_function, arg_idx++);
647 break;
648 case MESA_SHADER_VERTEX:
649 if (!ctx->is_gs_copy_shader) {
650 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
651 user_sgpr_idx += 2;
652 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
653 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
654 user_sgpr_idx += 3;
655 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
656 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
657 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
658 }
659 if (ctx->options->key.vs.as_es)
660 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
661 else if (ctx->options->key.vs.as_ls) {
662 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, user_sgpr_idx, 1);
663 user_sgpr_idx += 1;
664 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
665 }
666 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
667 if (!ctx->is_gs_copy_shader) {
668 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
669 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
670 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
671 }
672 break;
673 case MESA_SHADER_TESS_CTRL:
674 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
675 user_sgpr_idx += 4;
676 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
677 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
678 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
679 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
680 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
681 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
682 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
683 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
684 break;
685 case MESA_SHADER_TESS_EVAL:
686 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
687 user_sgpr_idx += 1;
688 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
689 if (ctx->options->key.tes.as_es) {
690 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
691 arg_idx++;
692 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
693 } else {
694 arg_idx++;
695 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
696 }
697 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
698 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
699 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
700 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
701 break;
702 case MESA_SHADER_GEOMETRY:
703 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
704 user_sgpr_idx += 2;
705 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
706 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
707 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
708 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
709 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
710 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
711 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
712 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
713 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
714 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
715 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
716 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
717 break;
718 case MESA_SHADER_FRAGMENT:
719 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
720 user_sgpr_idx += 2;
721 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
722 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
723 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
724 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
725 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
726 arg_idx++;
727 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
728 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
729 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
730 arg_idx++; /* line stipple */
731 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
732 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
733 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
734 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
735 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
736 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
737 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
738 break;
739 default:
740 unreachable("Shader stage not implemented");
741 }
742 }
743
744 static void setup_types(struct nir_to_llvm_context *ctx)
745 {
746 LLVMValueRef args[4];
747
748 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
749 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
750 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
751 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
752 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
753 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
754 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
755 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
756 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
757 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
758 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
759 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
760 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
761 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
762 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
763 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
764
765 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
766 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
767 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
768 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
769 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
770 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
771
772 args[0] = ctx->f32zero;
773 args[1] = ctx->f32zero;
774 args[2] = ctx->f32zero;
775 args[3] = ctx->f32one;
776 ctx->v4f32empty = LLVMConstVector(args, 4);
777
778 ctx->uniform_md_kind =
779 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
780 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
781
782 args[0] = LLVMConstReal(ctx->f32, 2.5);
783 }
784
785 static int get_llvm_num_components(LLVMValueRef value)
786 {
787 LLVMTypeRef type = LLVMTypeOf(value);
788 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
789 ? LLVMGetVectorSize(type)
790 : 1;
791 return num_components;
792 }
793
794 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
795 LLVMValueRef value,
796 int index)
797 {
798 int count = get_llvm_num_components(value);
799
800 assert(index < count);
801 if (count == 1)
802 return value;
803
804 return LLVMBuildExtractElement(ctx->builder, value,
805 LLVMConstInt(ctx->i32, index, false), "");
806 }
807
808 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
809 LLVMValueRef value, unsigned count)
810 {
811 unsigned num_components = get_llvm_num_components(value);
812 if (count == num_components)
813 return value;
814
815 LLVMValueRef masks[] = {
816 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
817 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
818
819 if (count == 1)
820 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
821 "");
822
823 LLVMValueRef swizzle = LLVMConstVector(masks, count);
824 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
825 }
826
827 static void
828 build_store_values_extended(struct nir_to_llvm_context *ctx,
829 LLVMValueRef *values,
830 unsigned value_count,
831 unsigned value_stride,
832 LLVMValueRef vec)
833 {
834 LLVMBuilderRef builder = ctx->builder;
835 unsigned i;
836
837 if (value_count == 1) {
838 LLVMBuildStore(builder, vec, values[0]);
839 return;
840 }
841
842 for (i = 0; i < value_count; i++) {
843 LLVMValueRef ptr = values[i * value_stride];
844 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
845 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
846 LLVMBuildStore(builder, value, ptr);
847 }
848 }
849
850 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
851 nir_ssa_def *def)
852 {
853 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
854 if (def->num_components > 1) {
855 type = LLVMVectorType(type, def->num_components);
856 }
857 return type;
858 }
859
860 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
861 {
862 assert(src.is_ssa);
863 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
864 return (LLVMValueRef)entry->data;
865 }
866
867
868 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
869 struct nir_block *b)
870 {
871 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
872 return (LLVMBasicBlockRef)entry->data;
873 }
874
875 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
876 nir_alu_src src,
877 unsigned num_components)
878 {
879 LLVMValueRef value = get_src(ctx, src.src);
880 bool need_swizzle = false;
881
882 assert(value);
883 LLVMTypeRef type = LLVMTypeOf(value);
884 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
885 ? LLVMGetVectorSize(type)
886 : 1;
887
888 for (unsigned i = 0; i < num_components; ++i) {
889 assert(src.swizzle[i] < src_components);
890 if (src.swizzle[i] != i)
891 need_swizzle = true;
892 }
893
894 if (need_swizzle || num_components != src_components) {
895 LLVMValueRef masks[] = {
896 LLVMConstInt(ctx->i32, src.swizzle[0], false),
897 LLVMConstInt(ctx->i32, src.swizzle[1], false),
898 LLVMConstInt(ctx->i32, src.swizzle[2], false),
899 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
900
901 if (src_components > 1 && num_components == 1) {
902 value = LLVMBuildExtractElement(ctx->builder, value,
903 masks[0], "");
904 } else if (src_components == 1 && num_components > 1) {
905 LLVMValueRef values[] = {value, value, value, value};
906 value = ac_build_gather_values(&ctx->ac, values, num_components);
907 } else {
908 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
909 value = LLVMBuildShuffleVector(ctx->builder, value, value,
910 swizzle, "");
911 }
912 }
913 assert(!src.negate);
914 assert(!src.abs);
915 return value;
916 }
917
918 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
919 LLVMIntPredicate pred, LLVMValueRef src0,
920 LLVMValueRef src1)
921 {
922 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
923 return LLVMBuildSelect(ctx->builder, result,
924 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
925 LLVMConstInt(ctx->i32, 0, false), "");
926 }
927
928 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
929 LLVMRealPredicate pred, LLVMValueRef src0,
930 LLVMValueRef src1)
931 {
932 LLVMValueRef result;
933 src0 = to_float(ctx, src0);
934 src1 = to_float(ctx, src1);
935 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
936 return LLVMBuildSelect(ctx->builder, result,
937 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
938 LLVMConstInt(ctx->i32, 0, false), "");
939 }
940
941 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
942 const char *intrin,
943 LLVMTypeRef result_type,
944 LLVMValueRef src0)
945 {
946 char name[64];
947 LLVMValueRef params[] = {
948 to_float(ctx, src0),
949 };
950
951 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
952 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
953 }
954
955 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
956 const char *intrin,
957 LLVMTypeRef result_type,
958 LLVMValueRef src0, LLVMValueRef src1)
959 {
960 char name[64];
961 LLVMValueRef params[] = {
962 to_float(ctx, src0),
963 to_float(ctx, src1),
964 };
965
966 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
967 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
968 }
969
970 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
971 const char *intrin,
972 LLVMTypeRef result_type,
973 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
974 {
975 char name[64];
976 LLVMValueRef params[] = {
977 to_float(ctx, src0),
978 to_float(ctx, src1),
979 to_float(ctx, src2),
980 };
981
982 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
983 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
984 }
985
986 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
987 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
988 {
989 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
990 ctx->i32zero, "");
991 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
992 }
993
994 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
995 LLVMValueRef src0)
996 {
997 LLVMValueRef params[2] = {
998 src0,
999
1000 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1001 * add special code to check for x=0. The reason is that
1002 * the LLVM behavior for x=0 is different from what we
1003 * need here.
1004 *
1005 * The hardware already implements the correct behavior.
1006 */
1007 LLVMConstInt(ctx->i32, 1, false),
1008 };
1009 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1010 }
1011
1012 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1013 LLVMValueRef src0)
1014 {
1015 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1016 }
1017
1018 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1019 LLVMValueRef src0)
1020 {
1021 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1022 }
1023
1024 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1025 LLVMIntPredicate pred,
1026 LLVMValueRef src0, LLVMValueRef src1)
1027 {
1028 return LLVMBuildSelect(ctx->builder,
1029 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1030 src0,
1031 src1, "");
1032
1033 }
1034 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1035 LLVMValueRef src0)
1036 {
1037 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1038 LLVMBuildNeg(ctx->builder, src0, ""));
1039 }
1040
1041 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1042 LLVMValueRef src0)
1043 {
1044 LLVMValueRef cmp, val;
1045
1046 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1047 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1048 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1049 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1050 return val;
1051 }
1052
1053 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1054 LLVMValueRef src0)
1055 {
1056 LLVMValueRef cmp, val;
1057
1058 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1059 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1060 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1061 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1062 return val;
1063 }
1064
1065 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1066 LLVMValueRef src0)
1067 {
1068 const char *intr = "llvm.floor.f32";
1069 LLVMValueRef fsrc0 = to_float(ctx, src0);
1070 LLVMValueRef params[] = {
1071 fsrc0,
1072 };
1073 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1074 ctx->f32, params, 1,
1075 AC_FUNC_ATTR_READNONE);
1076 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1077 }
1078
1079 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1080 const char *intrin,
1081 LLVMValueRef src0, LLVMValueRef src1)
1082 {
1083 LLVMTypeRef ret_type;
1084 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1085 LLVMValueRef res;
1086 LLVMValueRef params[] = { src0, src1 };
1087 ret_type = LLVMStructTypeInContext(ctx->context, types,
1088 2, true);
1089
1090 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1091 params, 2, AC_FUNC_ATTR_READNONE);
1092
1093 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1094 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1095 return res;
1096 }
1097
1098 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1099 LLVMValueRef src0)
1100 {
1101 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1102 }
1103
1104 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1105 LLVMValueRef src0, LLVMValueRef src1)
1106 {
1107 LLVMValueRef dst64, result;
1108 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1109 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1110
1111 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1112 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1113 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1114 return result;
1115 }
1116
1117 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1118 LLVMValueRef src0, LLVMValueRef src1)
1119 {
1120 LLVMValueRef dst64, result;
1121 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1122 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1123
1124 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1125 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1126 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1127 return result;
1128 }
1129
1130 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1131 bool is_signed,
1132 LLVMValueRef srcs[3])
1133 {
1134 LLVMValueRef result;
1135 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1136
1137 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1138 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1139 return result;
1140 }
1141
1142 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1143 LLVMValueRef src0, LLVMValueRef src1,
1144 LLVMValueRef src2, LLVMValueRef src3)
1145 {
1146 LLVMValueRef bfi_args[3], result;
1147
1148 bfi_args[0] = LLVMBuildShl(ctx->builder,
1149 LLVMBuildSub(ctx->builder,
1150 LLVMBuildShl(ctx->builder,
1151 ctx->i32one,
1152 src3, ""),
1153 ctx->i32one, ""),
1154 src2, "");
1155 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1156 bfi_args[2] = src0;
1157
1158 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1159
1160 /* Calculate:
1161 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1162 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1163 */
1164 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1165 LLVMBuildAnd(ctx->builder, bfi_args[0],
1166 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1167
1168 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1169 return result;
1170 }
1171
1172 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1173 LLVMValueRef src0)
1174 {
1175 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1176 int i;
1177 LLVMValueRef comp[2];
1178
1179 src0 = to_float(ctx, src0);
1180 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1181 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1182 for (i = 0; i < 2; i++) {
1183 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1184 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1185 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1186 }
1187
1188 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1189 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1190
1191 return comp[0];
1192 }
1193
1194 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1195 LLVMValueRef src0)
1196 {
1197 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1198 LLVMValueRef temps[2], result, val;
1199 int i;
1200
1201 for (i = 0; i < 2; i++) {
1202 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1203 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1204 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1205 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1206 }
1207
1208 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1209 ctx->i32zero, "");
1210 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1211 ctx->i32one, "");
1212 return result;
1213 }
1214
1215 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1216 nir_op op,
1217 LLVMValueRef src0)
1218 {
1219 unsigned mask;
1220 int idx;
1221 LLVMValueRef result;
1222 ctx->has_ddxy = true;
1223
1224 if (!ctx->lds && !ctx->has_ds_bpermute)
1225 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1226 LLVMArrayType(ctx->i32, 64),
1227 "ddxy_lds", LOCAL_ADDR_SPACE);
1228
1229 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1230 mask = AC_TID_MASK_LEFT;
1231 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1232 mask = AC_TID_MASK_TOP;
1233 else
1234 mask = AC_TID_MASK_TOP_LEFT;
1235
1236 /* for DDX we want to next X pixel, DDY next Y pixel. */
1237 if (op == nir_op_fddx_fine ||
1238 op == nir_op_fddx_coarse ||
1239 op == nir_op_fddx)
1240 idx = 1;
1241 else
1242 idx = 2;
1243
1244 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1245 mask, idx, ctx->lds,
1246 src0);
1247 return result;
1248 }
1249
1250 /*
1251 * this takes an I,J coordinate pair,
1252 * and works out the X and Y derivatives.
1253 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1254 */
1255 static LLVMValueRef emit_ddxy_interp(
1256 struct nir_to_llvm_context *ctx,
1257 LLVMValueRef interp_ij)
1258 {
1259 LLVMValueRef result[4], a;
1260 unsigned i;
1261
1262 for (i = 0; i < 2; i++) {
1263 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1264 LLVMConstInt(ctx->i32, i, false), "");
1265 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1266 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1267 }
1268 return ac_build_gather_values(&ctx->ac, result, 4);
1269 }
1270
1271 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1272 {
1273 LLVMValueRef src[4], result = NULL;
1274 unsigned num_components = instr->dest.dest.ssa.num_components;
1275 unsigned src_components;
1276 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1277
1278 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1279 switch (instr->op) {
1280 case nir_op_vec2:
1281 case nir_op_vec3:
1282 case nir_op_vec4:
1283 src_components = 1;
1284 break;
1285 case nir_op_pack_half_2x16:
1286 src_components = 2;
1287 break;
1288 case nir_op_unpack_half_2x16:
1289 src_components = 1;
1290 break;
1291 default:
1292 src_components = num_components;
1293 break;
1294 }
1295 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1296 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1297
1298 switch (instr->op) {
1299 case nir_op_fmov:
1300 case nir_op_imov:
1301 result = src[0];
1302 break;
1303 case nir_op_fneg:
1304 src[0] = to_float(ctx, src[0]);
1305 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1306 break;
1307 case nir_op_ineg:
1308 result = LLVMBuildNeg(ctx->builder, src[0], "");
1309 break;
1310 case nir_op_inot:
1311 result = LLVMBuildNot(ctx->builder, src[0], "");
1312 break;
1313 case nir_op_iadd:
1314 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1315 break;
1316 case nir_op_fadd:
1317 src[0] = to_float(ctx, src[0]);
1318 src[1] = to_float(ctx, src[1]);
1319 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1320 break;
1321 case nir_op_fsub:
1322 src[0] = to_float(ctx, src[0]);
1323 src[1] = to_float(ctx, src[1]);
1324 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1325 break;
1326 case nir_op_isub:
1327 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1328 break;
1329 case nir_op_imul:
1330 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1331 break;
1332 case nir_op_imod:
1333 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1334 break;
1335 case nir_op_umod:
1336 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1337 break;
1338 case nir_op_fmod:
1339 src[0] = to_float(ctx, src[0]);
1340 src[1] = to_float(ctx, src[1]);
1341 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1342 result = emit_intrin_1f_param(ctx, "llvm.floor",
1343 to_float_type(ctx, def_type), result);
1344 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1345 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1346 break;
1347 case nir_op_frem:
1348 src[0] = to_float(ctx, src[0]);
1349 src[1] = to_float(ctx, src[1]);
1350 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1351 break;
1352 case nir_op_irem:
1353 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1354 break;
1355 case nir_op_idiv:
1356 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1357 break;
1358 case nir_op_udiv:
1359 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1360 break;
1361 case nir_op_fmul:
1362 src[0] = to_float(ctx, src[0]);
1363 src[1] = to_float(ctx, src[1]);
1364 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1365 break;
1366 case nir_op_fdiv:
1367 src[0] = to_float(ctx, src[0]);
1368 src[1] = to_float(ctx, src[1]);
1369 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1370 break;
1371 case nir_op_frcp:
1372 src[0] = to_float(ctx, src[0]);
1373 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1374 break;
1375 case nir_op_iand:
1376 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1377 break;
1378 case nir_op_ior:
1379 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1380 break;
1381 case nir_op_ixor:
1382 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1383 break;
1384 case nir_op_ishl:
1385 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1386 break;
1387 case nir_op_ishr:
1388 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1389 break;
1390 case nir_op_ushr:
1391 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1392 break;
1393 case nir_op_ilt:
1394 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1395 break;
1396 case nir_op_ine:
1397 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1398 break;
1399 case nir_op_ieq:
1400 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1401 break;
1402 case nir_op_ige:
1403 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1404 break;
1405 case nir_op_ult:
1406 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1407 break;
1408 case nir_op_uge:
1409 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1410 break;
1411 case nir_op_feq:
1412 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1413 break;
1414 case nir_op_fne:
1415 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1416 break;
1417 case nir_op_flt:
1418 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1419 break;
1420 case nir_op_fge:
1421 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1422 break;
1423 case nir_op_fabs:
1424 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1425 to_float_type(ctx, def_type), src[0]);
1426 break;
1427 case nir_op_iabs:
1428 result = emit_iabs(ctx, src[0]);
1429 break;
1430 case nir_op_imax:
1431 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1432 break;
1433 case nir_op_imin:
1434 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1435 break;
1436 case nir_op_umax:
1437 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1438 break;
1439 case nir_op_umin:
1440 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1441 break;
1442 case nir_op_isign:
1443 result = emit_isign(ctx, src[0]);
1444 break;
1445 case nir_op_fsign:
1446 src[0] = to_float(ctx, src[0]);
1447 result = emit_fsign(ctx, src[0]);
1448 break;
1449 case nir_op_ffloor:
1450 result = emit_intrin_1f_param(ctx, "llvm.floor",
1451 to_float_type(ctx, def_type), src[0]);
1452 break;
1453 case nir_op_ftrunc:
1454 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1455 to_float_type(ctx, def_type), src[0]);
1456 break;
1457 case nir_op_fceil:
1458 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1459 to_float_type(ctx, def_type), src[0]);
1460 break;
1461 case nir_op_fround_even:
1462 result = emit_intrin_1f_param(ctx, "llvm.rint",
1463 to_float_type(ctx, def_type),src[0]);
1464 break;
1465 case nir_op_ffract:
1466 result = emit_ffract(ctx, src[0]);
1467 break;
1468 case nir_op_fsin:
1469 result = emit_intrin_1f_param(ctx, "llvm.sin",
1470 to_float_type(ctx, def_type), src[0]);
1471 break;
1472 case nir_op_fcos:
1473 result = emit_intrin_1f_param(ctx, "llvm.cos",
1474 to_float_type(ctx, def_type), src[0]);
1475 break;
1476 case nir_op_fsqrt:
1477 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1478 to_float_type(ctx, def_type), src[0]);
1479 break;
1480 case nir_op_fexp2:
1481 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1482 to_float_type(ctx, def_type), src[0]);
1483 break;
1484 case nir_op_flog2:
1485 result = emit_intrin_1f_param(ctx, "llvm.log2",
1486 to_float_type(ctx, def_type), src[0]);
1487 break;
1488 case nir_op_frsq:
1489 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1490 to_float_type(ctx, def_type), src[0]);
1491 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1492 break;
1493 case nir_op_fpow:
1494 result = emit_intrin_2f_param(ctx, "llvm.pow",
1495 to_float_type(ctx, def_type), src[0], src[1]);
1496 break;
1497 case nir_op_fmax:
1498 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1499 to_float_type(ctx, def_type), src[0], src[1]);
1500 break;
1501 case nir_op_fmin:
1502 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1503 to_float_type(ctx, def_type), src[0], src[1]);
1504 break;
1505 case nir_op_ffma:
1506 result = emit_intrin_3f_param(ctx, "llvm.fma",
1507 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1508 break;
1509 case nir_op_ibitfield_extract:
1510 result = emit_bitfield_extract(ctx, true, src);
1511 break;
1512 case nir_op_ubitfield_extract:
1513 result = emit_bitfield_extract(ctx, false, src);
1514 break;
1515 case nir_op_bitfield_insert:
1516 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1517 break;
1518 case nir_op_bitfield_reverse:
1519 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1520 break;
1521 case nir_op_bit_count:
1522 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1523 break;
1524 case nir_op_vec2:
1525 case nir_op_vec3:
1526 case nir_op_vec4:
1527 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1528 src[i] = to_integer(ctx, src[i]);
1529 result = ac_build_gather_values(&ctx->ac, src, num_components);
1530 break;
1531 case nir_op_f2i32:
1532 case nir_op_f2i64:
1533 src[0] = to_float(ctx, src[0]);
1534 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1535 break;
1536 case nir_op_f2u32:
1537 case nir_op_f2u64:
1538 src[0] = to_float(ctx, src[0]);
1539 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1540 break;
1541 case nir_op_i2f32:
1542 case nir_op_i2f64:
1543 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1544 break;
1545 case nir_op_u2f32:
1546 case nir_op_u2f64:
1547 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1548 break;
1549 case nir_op_f2f64:
1550 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1551 break;
1552 case nir_op_f2f32:
1553 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1554 break;
1555 case nir_op_u2u32:
1556 case nir_op_u2u64:
1557 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1558 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1559 else
1560 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1561 break;
1562 case nir_op_i2i32:
1563 case nir_op_i2i64:
1564 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1565 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1566 else
1567 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1568 break;
1569 case nir_op_bcsel:
1570 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1571 break;
1572 case nir_op_find_lsb:
1573 result = emit_find_lsb(ctx, src[0]);
1574 break;
1575 case nir_op_ufind_msb:
1576 result = emit_ufind_msb(ctx, src[0]);
1577 break;
1578 case nir_op_ifind_msb:
1579 result = emit_ifind_msb(ctx, src[0]);
1580 break;
1581 case nir_op_uadd_carry:
1582 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1583 break;
1584 case nir_op_usub_borrow:
1585 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1586 break;
1587 case nir_op_b2f:
1588 result = emit_b2f(ctx, src[0]);
1589 break;
1590 case nir_op_fquantize2f16:
1591 src[0] = to_float(ctx, src[0]);
1592 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1593 /* need to convert back up to f32 */
1594 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1595 break;
1596 case nir_op_umul_high:
1597 result = emit_umul_high(ctx, src[0], src[1]);
1598 break;
1599 case nir_op_imul_high:
1600 result = emit_imul_high(ctx, src[0], src[1]);
1601 break;
1602 case nir_op_pack_half_2x16:
1603 result = emit_pack_half_2x16(ctx, src[0]);
1604 break;
1605 case nir_op_unpack_half_2x16:
1606 result = emit_unpack_half_2x16(ctx, src[0]);
1607 break;
1608 case nir_op_fddx:
1609 case nir_op_fddy:
1610 case nir_op_fddx_fine:
1611 case nir_op_fddy_fine:
1612 case nir_op_fddx_coarse:
1613 case nir_op_fddy_coarse:
1614 result = emit_ddxy(ctx, instr->op, src[0]);
1615 break;
1616 default:
1617 fprintf(stderr, "Unknown NIR alu instr: ");
1618 nir_print_instr(&instr->instr, stderr);
1619 fprintf(stderr, "\n");
1620 abort();
1621 }
1622
1623 if (result) {
1624 assert(instr->dest.dest.is_ssa);
1625 result = to_integer(ctx, result);
1626 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1627 result);
1628 }
1629 }
1630
1631 static void visit_load_const(struct nir_to_llvm_context *ctx,
1632 nir_load_const_instr *instr)
1633 {
1634 LLVMValueRef values[4], value = NULL;
1635 LLVMTypeRef element_type =
1636 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1637
1638 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1639 switch (instr->def.bit_size) {
1640 case 32:
1641 values[i] = LLVMConstInt(element_type,
1642 instr->value.u32[i], false);
1643 break;
1644 case 64:
1645 values[i] = LLVMConstInt(element_type,
1646 instr->value.u64[i], false);
1647 break;
1648 default:
1649 fprintf(stderr,
1650 "unsupported nir load_const bit_size: %d\n",
1651 instr->def.bit_size);
1652 abort();
1653 }
1654 }
1655 if (instr->def.num_components > 1) {
1656 value = LLVMConstVector(values, instr->def.num_components);
1657 } else
1658 value = values[0];
1659
1660 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1661 }
1662
1663 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1664 LLVMTypeRef type)
1665 {
1666 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1667 return LLVMBuildBitCast(ctx->builder, ptr,
1668 LLVMPointerType(type, addr_space), "");
1669 }
1670
1671 static LLVMValueRef
1672 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1673 {
1674 LLVMValueRef size =
1675 LLVMBuildExtractElement(ctx->builder, descriptor,
1676 LLVMConstInt(ctx->i32, 2, false), "");
1677
1678 /* VI only */
1679 if (ctx->options->chip_class >= VI && in_elements) {
1680 /* On VI, the descriptor contains the size in bytes,
1681 * but TXQ must return the size in elements.
1682 * The stride is always non-zero for resources using TXQ.
1683 */
1684 LLVMValueRef stride =
1685 LLVMBuildExtractElement(ctx->builder, descriptor,
1686 LLVMConstInt(ctx->i32, 1, false), "");
1687 stride = LLVMBuildLShr(ctx->builder, stride,
1688 LLVMConstInt(ctx->i32, 16, false), "");
1689 stride = LLVMBuildAnd(ctx->builder, stride,
1690 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1691
1692 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1693 }
1694 return size;
1695 }
1696
1697 /**
1698 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1699 * intrinsic names).
1700 */
1701 static void build_int_type_name(
1702 LLVMTypeRef type,
1703 char *buf, unsigned bufsize)
1704 {
1705 assert(bufsize >= 6);
1706
1707 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1708 snprintf(buf, bufsize, "v%ui32",
1709 LLVMGetVectorSize(type));
1710 else
1711 strcpy(buf, "i32");
1712 }
1713
1714 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1715 struct ac_image_args *args,
1716 nir_tex_instr *instr)
1717 {
1718 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1719 LLVMValueRef coord = args->addr;
1720 LLVMValueRef half_texel[2];
1721 LLVMValueRef compare_cube_wa;
1722 LLVMValueRef result;
1723 int c;
1724 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1725
1726 //TODO Rect
1727 {
1728 struct ac_image_args txq_args = { 0 };
1729
1730 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1731 txq_args.opcode = ac_image_get_resinfo;
1732 txq_args.dmask = 0xf;
1733 txq_args.addr = ctx->i32zero;
1734 txq_args.resource = args->resource;
1735 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1736
1737 for (c = 0; c < 2; c++) {
1738 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1739 LLVMConstInt(ctx->i32, c, false), "");
1740 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1741 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1742 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1743 LLVMConstReal(ctx->f32, -0.5), "");
1744 }
1745 }
1746
1747 LLVMValueRef orig_coords = args->addr;
1748
1749 for (c = 0; c < 2; c++) {
1750 LLVMValueRef tmp;
1751 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1752 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1753 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1754 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1755 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1756 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1757 }
1758
1759
1760 /*
1761 * Apparantly cube has issue with integer types that the workaround doesn't solve,
1762 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
1763 * workaround by sampling using a scaled type and converting.
1764 * This is taken from amdgpu-pro shaders.
1765 */
1766 /* NOTE this produces some ugly code compared to amdgpu-pro,
1767 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
1768 * and then reads them back. -pro generates two selects,
1769 * one s_cmp for the descriptor rewriting
1770 * one v_cmp for the coordinate and result changes.
1771 */
1772 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1773 LLVMValueRef tmp, tmp2;
1774
1775 /* workaround 8/8/8/8 uint/sint cube gather bug */
1776 /* first detect it then change to a scaled read and f2i */
1777 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
1778 tmp2 = tmp;
1779
1780 /* extract the DATA_FORMAT */
1781 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
1782 LLVMConstInt(ctx->i32, 6, false), false);
1783
1784 /* is the DATA_FORMAT == 8_8_8_8 */
1785 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
1786
1787 if (stype == GLSL_TYPE_UINT)
1788 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
1789 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
1790 LLVMConstInt(ctx->i32, 0x10000000, false), "");
1791 else
1792 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
1793 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
1794 LLVMConstInt(ctx->i32, 0x14000000, false), "");
1795
1796 /* replace the NUM FORMAT in the descriptor */
1797 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
1798 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
1799
1800 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
1801
1802 /* don't modify the coordinates for this case */
1803 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
1804 }
1805 args->addr = coord;
1806 result = ac_build_image_opcode(&ctx->ac, args);
1807
1808 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1809 LLVMValueRef tmp, tmp2;
1810
1811 /* if the cube workaround is in place, f2i the result. */
1812 for (c = 0; c < 4; c++) {
1813 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
1814 if (stype == GLSL_TYPE_UINT)
1815 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
1816 else
1817 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
1818 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1819 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
1820 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
1821 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1822 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
1823 }
1824 }
1825 return result;
1826 }
1827
1828 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1829 nir_tex_instr *instr,
1830 struct ac_image_args *args)
1831 {
1832 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
1833 return ac_build_buffer_load_format(&ctx->ac,
1834 args->resource,
1835 args->addr,
1836 LLVMConstInt(ctx->i32, 0, false),
1837 true);
1838 }
1839
1840 args->opcode = ac_image_sample;
1841 args->compare = instr->is_shadow;
1842
1843 switch (instr->op) {
1844 case nir_texop_txf:
1845 case nir_texop_txf_ms:
1846 case nir_texop_samples_identical:
1847 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
1848 args->compare = false;
1849 args->offset = false;
1850 break;
1851 case nir_texop_txb:
1852 args->bias = true;
1853 break;
1854 case nir_texop_txl:
1855 args->lod = true;
1856 break;
1857 case nir_texop_txs:
1858 case nir_texop_query_levels:
1859 args->opcode = ac_image_get_resinfo;
1860 break;
1861 case nir_texop_tex:
1862 if (ctx->stage != MESA_SHADER_FRAGMENT)
1863 args->level_zero = true;
1864 break;
1865 case nir_texop_txd:
1866 args->deriv = true;
1867 break;
1868 case nir_texop_tg4:
1869 args->opcode = ac_image_gather4;
1870 args->level_zero = true;
1871 break;
1872 case nir_texop_lod:
1873 args->opcode = ac_image_get_lod;
1874 args->compare = false;
1875 args->offset = false;
1876 break;
1877 default:
1878 break;
1879 }
1880
1881 if (instr->op == nir_texop_tg4) {
1882 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1883 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1884 return radv_lower_gather4_integer(ctx, args, instr);
1885 }
1886 }
1887 return ac_build_image_opcode(&ctx->ac, args);
1888 }
1889
1890 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1891 nir_intrinsic_instr *instr)
1892 {
1893 LLVMValueRef index = get_src(ctx, instr->src[0]);
1894 unsigned desc_set = nir_intrinsic_desc_set(instr);
1895 unsigned binding = nir_intrinsic_binding(instr);
1896 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1897 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1898 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1899 unsigned base_offset = layout->binding[binding].offset;
1900 LLVMValueRef offset, stride;
1901
1902 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1903 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1904 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1905 layout->binding[binding].dynamic_offset_offset;
1906 desc_ptr = ctx->push_constants;
1907 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1908 stride = LLVMConstInt(ctx->i32, 16, false);
1909 } else
1910 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1911
1912 offset = LLVMConstInt(ctx->i32, base_offset, false);
1913 index = LLVMBuildMul(ctx->builder, index, stride, "");
1914 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1915
1916 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1917 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1918 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1919
1920 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1921 }
1922
1923 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1924 nir_intrinsic_instr *instr)
1925 {
1926 LLVMValueRef ptr, addr;
1927
1928 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1929 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1930
1931 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1932 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1933
1934 return LLVMBuildLoad(ctx->builder, ptr, "");
1935 }
1936
1937 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1938 nir_intrinsic_instr *instr)
1939 {
1940 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1941
1942 return get_buffer_size(ctx, desc, false);
1943 }
1944 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1945 nir_intrinsic_instr *instr)
1946 {
1947 const char *store_name;
1948 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1949 LLVMTypeRef data_type = ctx->f32;
1950 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1951 int components_32bit = elem_size_mult * instr->num_components;
1952 unsigned writemask = nir_intrinsic_write_mask(instr);
1953 LLVMValueRef base_data, base_offset;
1954 LLVMValueRef params[6];
1955
1956 if (ctx->stage == MESA_SHADER_FRAGMENT)
1957 ctx->shader_info->fs.writes_memory = true;
1958
1959 params[1] = get_src(ctx, instr->src[1]);
1960 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1961 params[4] = ctx->i1false; /* glc */
1962 params[5] = ctx->i1false; /* slc */
1963
1964 if (components_32bit > 1)
1965 data_type = LLVMVectorType(ctx->f32, components_32bit);
1966
1967 base_data = to_float(ctx, src_data);
1968 base_data = trim_vector(ctx, base_data, instr->num_components);
1969 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1970 data_type, "");
1971 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1972 while (writemask) {
1973 int start, count;
1974 LLVMValueRef data;
1975 LLVMValueRef offset;
1976 LLVMValueRef tmp;
1977 u_bit_scan_consecutive_range(&writemask, &start, &count);
1978
1979 /* Due to an LLVM limitation, split 3-element writes
1980 * into a 2-element and a 1-element write. */
1981 if (count == 3) {
1982 writemask |= 1 << (start + 2);
1983 count = 2;
1984 }
1985
1986 start *= elem_size_mult;
1987 count *= elem_size_mult;
1988
1989 if (count > 4) {
1990 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1991 count = 4;
1992 }
1993
1994 if (count == 4) {
1995 store_name = "llvm.amdgcn.buffer.store.v4f32";
1996 data = base_data;
1997 } else if (count == 2) {
1998 tmp = LLVMBuildExtractElement(ctx->builder,
1999 base_data, LLVMConstInt(ctx->i32, start, false), "");
2000 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2001 ctx->i32zero, "");
2002
2003 tmp = LLVMBuildExtractElement(ctx->builder,
2004 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2005 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2006 ctx->i32one, "");
2007 store_name = "llvm.amdgcn.buffer.store.v2f32";
2008
2009 } else {
2010 assert(count == 1);
2011 if (get_llvm_num_components(base_data) > 1)
2012 data = LLVMBuildExtractElement(ctx->builder, base_data,
2013 LLVMConstInt(ctx->i32, start, false), "");
2014 else
2015 data = base_data;
2016 store_name = "llvm.amdgcn.buffer.store.f32";
2017 }
2018
2019 offset = base_offset;
2020 if (start != 0) {
2021 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2022 }
2023 params[0] = data;
2024 params[3] = offset;
2025 ac_build_intrinsic(&ctx->ac, store_name,
2026 ctx->voidt, params, 6, 0);
2027 }
2028 }
2029
2030 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2031 nir_intrinsic_instr *instr)
2032 {
2033 const char *name;
2034 LLVMValueRef params[6];
2035 int arg_count = 0;
2036 if (ctx->stage == MESA_SHADER_FRAGMENT)
2037 ctx->shader_info->fs.writes_memory = true;
2038
2039 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2040 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2041 }
2042 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2043 params[arg_count++] = get_src(ctx, instr->src[0]);
2044 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2045 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2046 params[arg_count++] = ctx->i1false; /* slc */
2047
2048 switch (instr->intrinsic) {
2049 case nir_intrinsic_ssbo_atomic_add:
2050 name = "llvm.amdgcn.buffer.atomic.add";
2051 break;
2052 case nir_intrinsic_ssbo_atomic_imin:
2053 name = "llvm.amdgcn.buffer.atomic.smin";
2054 break;
2055 case nir_intrinsic_ssbo_atomic_umin:
2056 name = "llvm.amdgcn.buffer.atomic.umin";
2057 break;
2058 case nir_intrinsic_ssbo_atomic_imax:
2059 name = "llvm.amdgcn.buffer.atomic.smax";
2060 break;
2061 case nir_intrinsic_ssbo_atomic_umax:
2062 name = "llvm.amdgcn.buffer.atomic.umax";
2063 break;
2064 case nir_intrinsic_ssbo_atomic_and:
2065 name = "llvm.amdgcn.buffer.atomic.and";
2066 break;
2067 case nir_intrinsic_ssbo_atomic_or:
2068 name = "llvm.amdgcn.buffer.atomic.or";
2069 break;
2070 case nir_intrinsic_ssbo_atomic_xor:
2071 name = "llvm.amdgcn.buffer.atomic.xor";
2072 break;
2073 case nir_intrinsic_ssbo_atomic_exchange:
2074 name = "llvm.amdgcn.buffer.atomic.swap";
2075 break;
2076 case nir_intrinsic_ssbo_atomic_comp_swap:
2077 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2078 break;
2079 default:
2080 abort();
2081 }
2082
2083 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2084 }
2085
2086 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2087 nir_intrinsic_instr *instr)
2088 {
2089 LLVMValueRef results[2];
2090 int load_components;
2091 int num_components = instr->num_components;
2092 if (instr->dest.ssa.bit_size == 64)
2093 num_components *= 2;
2094
2095 for (int i = 0; i < num_components; i += load_components) {
2096 load_components = MIN2(num_components - i, 4);
2097 const char *load_name;
2098 LLVMTypeRef data_type = ctx->f32;
2099 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2100 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2101
2102 if (load_components == 3)
2103 data_type = LLVMVectorType(ctx->f32, 4);
2104 else if (load_components > 1)
2105 data_type = LLVMVectorType(ctx->f32, load_components);
2106
2107 if (load_components >= 3)
2108 load_name = "llvm.amdgcn.buffer.load.v4f32";
2109 else if (load_components == 2)
2110 load_name = "llvm.amdgcn.buffer.load.v2f32";
2111 else if (load_components == 1)
2112 load_name = "llvm.amdgcn.buffer.load.f32";
2113 else
2114 unreachable("unhandled number of components");
2115
2116 LLVMValueRef params[] = {
2117 get_src(ctx, instr->src[0]),
2118 LLVMConstInt(ctx->i32, 0, false),
2119 offset,
2120 ctx->i1false,
2121 ctx->i1false,
2122 };
2123
2124 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2125
2126 }
2127
2128 LLVMValueRef ret = results[0];
2129 if (num_components > 4 || num_components == 3) {
2130 LLVMValueRef masks[] = {
2131 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2132 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2133 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2134 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2135 };
2136
2137 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2138 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2139 results[num_components > 4 ? 1 : 0], swizzle, "");
2140 }
2141
2142 return LLVMBuildBitCast(ctx->builder, ret,
2143 get_def_type(ctx, &instr->dest.ssa), "");
2144 }
2145
2146 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2147 nir_intrinsic_instr *instr)
2148 {
2149 LLVMValueRef results[8], ret;
2150 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2151 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2152 int num_components = instr->num_components;
2153
2154 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2155
2156 if (instr->dest.ssa.bit_size == 64)
2157 num_components *= 2;
2158
2159 for (unsigned i = 0; i < num_components; ++i) {
2160 LLVMValueRef params[] = {
2161 rsrc,
2162 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2163 offset, "")
2164 };
2165 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2166 params, 2,
2167 AC_FUNC_ATTR_READNONE |
2168 AC_FUNC_ATTR_LEGACY);
2169 }
2170
2171
2172 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2173 return LLVMBuildBitCast(ctx->builder, ret,
2174 get_def_type(ctx, &instr->dest.ssa), "");
2175 }
2176
2177 static void
2178 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2179 bool vs_in, unsigned *vertex_index_out,
2180 unsigned *const_out, LLVMValueRef *indir_out)
2181 {
2182 unsigned const_offset = 0;
2183 LLVMValueRef offset = NULL;
2184
2185 if (vertex_index_out != NULL) {
2186 tail = tail->child;
2187 nir_deref_array *deref_array = nir_deref_as_array(tail);
2188 *vertex_index_out = deref_array->base_offset;
2189 }
2190
2191 while (tail->child != NULL) {
2192 const struct glsl_type *parent_type = tail->type;
2193 tail = tail->child;
2194
2195 if (tail->deref_type == nir_deref_type_array) {
2196 nir_deref_array *deref_array = nir_deref_as_array(tail);
2197 LLVMValueRef index, stride, local_offset;
2198 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2199
2200 const_offset += size * deref_array->base_offset;
2201 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2202 continue;
2203
2204 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2205 index = get_src(ctx, deref_array->indirect);
2206 stride = LLVMConstInt(ctx->i32, size, 0);
2207 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2208
2209 if (offset)
2210 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2211 else
2212 offset = local_offset;
2213 } else if (tail->deref_type == nir_deref_type_struct) {
2214 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2215
2216 for (unsigned i = 0; i < deref_struct->index; i++) {
2217 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2218 const_offset += glsl_count_attribute_slots(ft, vs_in);
2219 }
2220 } else
2221 unreachable("unsupported deref type");
2222
2223 }
2224
2225 if (const_offset && offset)
2226 offset = LLVMBuildAdd(ctx->builder, offset,
2227 LLVMConstInt(ctx->i32, const_offset, 0),
2228 "");
2229
2230 *const_out = const_offset;
2231 *indir_out = offset;
2232 }
2233
2234 static LLVMValueRef
2235 load_gs_input(struct nir_to_llvm_context *ctx,
2236 nir_intrinsic_instr *instr)
2237 {
2238 LLVMValueRef indir_index, vtx_offset;
2239 unsigned const_index;
2240 LLVMValueRef args[9];
2241 unsigned param, vtx_offset_param;
2242 LLVMValueRef value[4], result;
2243 unsigned vertex_index;
2244 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2245 false, &vertex_index,
2246 &const_index, &indir_index);
2247 vtx_offset_param = vertex_index;
2248 assert(vtx_offset_param < 6);
2249 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2250 LLVMConstInt(ctx->i32, 4, false), "");
2251
2252 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2253 for (unsigned i = 0; i < instr->num_components; i++) {
2254
2255 args[0] = ctx->esgs_ring;
2256 args[1] = vtx_offset;
2257 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2258 args[3] = ctx->i32zero;
2259 args[4] = ctx->i32one; /* OFFEN */
2260 args[5] = ctx->i32zero; /* IDXEN */
2261 args[6] = ctx->i32one; /* GLC */
2262 args[7] = ctx->i32zero; /* SLC */
2263 args[8] = ctx->i32zero; /* TFE */
2264
2265 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2266 ctx->i32, args, 9,
2267 AC_FUNC_ATTR_READONLY |
2268 AC_FUNC_ATTR_LEGACY);
2269 }
2270 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2271
2272 return result;
2273 }
2274
2275 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2276 nir_intrinsic_instr *instr)
2277 {
2278 LLVMValueRef values[8];
2279 int idx = instr->variables[0]->var->data.driver_location;
2280 int ve = instr->dest.ssa.num_components;
2281 LLVMValueRef indir_index;
2282 LLVMValueRef ret;
2283 unsigned const_index;
2284 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2285 instr->variables[0]->var->data.mode == nir_var_shader_in;
2286 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2287 &const_index, &indir_index);
2288
2289 if (instr->dest.ssa.bit_size == 64)
2290 ve *= 2;
2291
2292 switch (instr->variables[0]->var->data.mode) {
2293 case nir_var_shader_in:
2294 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2295 return load_gs_input(ctx, instr);
2296 }
2297 for (unsigned chan = 0; chan < ve; chan++) {
2298 if (indir_index) {
2299 unsigned count = glsl_count_attribute_slots(
2300 instr->variables[0]->var->type,
2301 ctx->stage == MESA_SHADER_VERTEX);
2302 count -= chan / 4;
2303 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2304 &ctx->ac, ctx->inputs + idx + chan, count,
2305 4, false);
2306
2307 values[chan] = LLVMBuildExtractElement(ctx->builder,
2308 tmp_vec,
2309 indir_index, "");
2310 } else
2311 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2312 }
2313 break;
2314 case nir_var_local:
2315 for (unsigned chan = 0; chan < ve; chan++) {
2316 if (indir_index) {
2317 unsigned count = glsl_count_attribute_slots(
2318 instr->variables[0]->var->type, false);
2319 count -= chan / 4;
2320 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2321 &ctx->ac, ctx->locals + idx + chan, count,
2322 4, true);
2323
2324 values[chan] = LLVMBuildExtractElement(ctx->builder,
2325 tmp_vec,
2326 indir_index, "");
2327 } else {
2328 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2329 }
2330 }
2331 break;
2332 case nir_var_shader_out:
2333 for (unsigned chan = 0; chan < ve; chan++) {
2334 if (indir_index) {
2335 unsigned count = glsl_count_attribute_slots(
2336 instr->variables[0]->var->type, false);
2337 count -= chan / 4;
2338 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2339 &ctx->ac, ctx->outputs + idx + chan, count,
2340 4, true);
2341
2342 values[chan] = LLVMBuildExtractElement(ctx->builder,
2343 tmp_vec,
2344 indir_index, "");
2345 } else {
2346 values[chan] = LLVMBuildLoad(ctx->builder,
2347 ctx->outputs[idx + chan + const_index * 4],
2348 "");
2349 }
2350 }
2351 break;
2352 case nir_var_shared: {
2353 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2354 LLVMValueRef derived_ptr;
2355
2356 if (indir_index)
2357 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2358
2359 for (unsigned chan = 0; chan < ve; chan++) {
2360 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2361 if (indir_index)
2362 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2363 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2364
2365 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2366 }
2367 break;
2368 }
2369 default:
2370 unreachable("unhandle variable mode");
2371 }
2372 ret = ac_build_gather_values(&ctx->ac, values, ve);
2373 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2374 }
2375
2376 static void
2377 visit_store_var(struct nir_to_llvm_context *ctx,
2378 nir_intrinsic_instr *instr)
2379 {
2380 LLVMValueRef temp_ptr, value;
2381 int idx = instr->variables[0]->var->data.driver_location;
2382 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2383 int writemask = instr->const_index[0];
2384 LLVMValueRef indir_index;
2385 unsigned const_index;
2386 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2387 NULL, &const_index, &indir_index);
2388
2389 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2390 int old_writemask = writemask;
2391
2392 src = LLVMBuildBitCast(ctx->builder, src,
2393 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2394 "");
2395
2396 writemask = 0;
2397 for (unsigned chan = 0; chan < 4; chan++) {
2398 if (old_writemask & (1 << chan))
2399 writemask |= 3u << (2 * chan);
2400 }
2401 }
2402
2403 switch (instr->variables[0]->var->data.mode) {
2404 case nir_var_shader_out:
2405 for (unsigned chan = 0; chan < 8; chan++) {
2406 int stride = 4;
2407 if (!(writemask & (1 << chan)))
2408 continue;
2409
2410 value = llvm_extract_elem(ctx, src, chan);
2411
2412 if (instr->variables[0]->var->data.compact)
2413 stride = 1;
2414 if (indir_index) {
2415 unsigned count = glsl_count_attribute_slots(
2416 instr->variables[0]->var->type, false);
2417 count -= chan / 4;
2418 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2419 &ctx->ac, ctx->outputs + idx + chan, count,
2420 stride, true);
2421
2422 if (get_llvm_num_components(tmp_vec) > 1) {
2423 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2424 value, indir_index, "");
2425 } else
2426 tmp_vec = value;
2427 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2428 count, stride, tmp_vec);
2429
2430 } else {
2431 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2432
2433 LLVMBuildStore(ctx->builder, value, temp_ptr);
2434 }
2435 }
2436 break;
2437 case nir_var_local:
2438 for (unsigned chan = 0; chan < 8; chan++) {
2439 if (!(writemask & (1 << chan)))
2440 continue;
2441
2442 value = llvm_extract_elem(ctx, src, chan);
2443 if (indir_index) {
2444 unsigned count = glsl_count_attribute_slots(
2445 instr->variables[0]->var->type, false);
2446 count -= chan / 4;
2447 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2448 &ctx->ac, ctx->locals + idx + chan, count,
2449 4, true);
2450
2451 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2452 value, indir_index, "");
2453 build_store_values_extended(ctx, ctx->locals + idx + chan,
2454 count, 4, tmp_vec);
2455 } else {
2456 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2457
2458 LLVMBuildStore(ctx->builder, value, temp_ptr);
2459 }
2460 }
2461 break;
2462 case nir_var_shared: {
2463 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2464
2465 if (indir_index)
2466 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2467
2468 for (unsigned chan = 0; chan < 8; chan++) {
2469 if (!(writemask & (1 << chan)))
2470 continue;
2471 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2472 LLVMValueRef derived_ptr;
2473
2474 if (indir_index)
2475 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2476
2477 value = llvm_extract_elem(ctx, src, chan);
2478 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2479 LLVMBuildStore(ctx->builder,
2480 to_integer(ctx, value), derived_ptr);
2481 }
2482 break;
2483 }
2484 default:
2485 break;
2486 }
2487 }
2488
2489 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2490 {
2491 switch (dim) {
2492 case GLSL_SAMPLER_DIM_BUF:
2493 return 1;
2494 case GLSL_SAMPLER_DIM_1D:
2495 return array ? 2 : 1;
2496 case GLSL_SAMPLER_DIM_2D:
2497 return array ? 3 : 2;
2498 case GLSL_SAMPLER_DIM_MS:
2499 return array ? 4 : 3;
2500 case GLSL_SAMPLER_DIM_3D:
2501 case GLSL_SAMPLER_DIM_CUBE:
2502 return 3;
2503 case GLSL_SAMPLER_DIM_RECT:
2504 case GLSL_SAMPLER_DIM_SUBPASS:
2505 return 2;
2506 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2507 return 3;
2508 default:
2509 break;
2510 }
2511 return 0;
2512 }
2513
2514
2515
2516 /* Adjust the sample index according to FMASK.
2517 *
2518 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2519 * which is the identity mapping. Each nibble says which physical sample
2520 * should be fetched to get that sample.
2521 *
2522 * For example, 0x11111100 means there are only 2 samples stored and
2523 * the second sample covers 3/4 of the pixel. When reading samples 0
2524 * and 1, return physical sample 0 (determined by the first two 0s
2525 * in FMASK), otherwise return physical sample 1.
2526 *
2527 * The sample index should be adjusted as follows:
2528 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2529 */
2530 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
2531 LLVMValueRef coord_x, LLVMValueRef coord_y,
2532 LLVMValueRef coord_z,
2533 LLVMValueRef sample_index,
2534 LLVMValueRef fmask_desc_ptr)
2535 {
2536 LLVMValueRef fmask_load_address[4];
2537 LLVMValueRef res;
2538
2539 fmask_load_address[0] = coord_x;
2540 fmask_load_address[1] = coord_y;
2541 if (coord_z) {
2542 fmask_load_address[2] = coord_z;
2543 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
2544 }
2545
2546 struct ac_image_args args = {0};
2547
2548 args.opcode = ac_image_load;
2549 args.da = coord_z ? true : false;
2550 args.resource = fmask_desc_ptr;
2551 args.dmask = 0xf;
2552 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
2553
2554 res = ac_build_image_opcode(&ctx->ac, &args);
2555
2556 res = to_integer(ctx, res);
2557 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
2558 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
2559
2560 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
2561 res,
2562 ctx->i32zero, "");
2563
2564 LLVMValueRef sample_index4 =
2565 LLVMBuildMul(ctx->builder, sample_index, four, "");
2566 LLVMValueRef shifted_fmask =
2567 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
2568 LLVMValueRef final_sample =
2569 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
2570
2571 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2572 * resource descriptor is 0 (invalid),
2573 */
2574 LLVMValueRef fmask_desc =
2575 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
2576 ctx->v8i32, "");
2577
2578 LLVMValueRef fmask_word1 =
2579 LLVMBuildExtractElement(ctx->builder, fmask_desc,
2580 ctx->i32one, "");
2581
2582 LLVMValueRef word1_is_nonzero =
2583 LLVMBuildICmp(ctx->builder, LLVMIntNE,
2584 fmask_word1, ctx->i32zero, "");
2585
2586 /* Replace the MSAA sample index. */
2587 sample_index =
2588 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
2589 final_sample, sample_index, "");
2590 return sample_index;
2591 }
2592
2593 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2594 nir_intrinsic_instr *instr)
2595 {
2596 const struct glsl_type *type = instr->variables[0]->var->type;
2597 if(instr->variables[0]->deref.child)
2598 type = instr->variables[0]->deref.child->type;
2599
2600 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2601 LLVMValueRef coords[4];
2602 LLVMValueRef masks[] = {
2603 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2604 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2605 };
2606 LLVMValueRef res;
2607 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2608
2609 int count;
2610 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2611 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2612 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2613 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2614 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2615
2616 count = image_type_to_components_count(dim,
2617 glsl_sampler_type_is_array(type));
2618
2619 if (is_ms) {
2620 LLVMValueRef fmask_load_address[3];
2621 int chan;
2622
2623 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2624 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
2625 if (glsl_sampler_type_is_array(type))
2626 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
2627 else
2628 fmask_load_address[2] = NULL;
2629 if (add_frag_pos) {
2630 for (chan = 0; chan < 2; ++chan)
2631 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2632 }
2633 sample_index = adjust_sample_index_using_fmask(ctx,
2634 fmask_load_address[0],
2635 fmask_load_address[1],
2636 fmask_load_address[2],
2637 sample_index,
2638 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
2639 }
2640 if (count == 1) {
2641 if (instr->src[0].ssa->num_components)
2642 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2643 else
2644 res = src0;
2645 } else {
2646 int chan;
2647 if (is_ms)
2648 count--;
2649 for (chan = 0; chan < count; ++chan) {
2650 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2651 }
2652
2653 if (add_frag_pos) {
2654 for (chan = 0; chan < count; ++chan)
2655 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2656 }
2657 if (is_ms) {
2658 coords[count] = sample_index;
2659 count++;
2660 }
2661
2662 if (count == 3) {
2663 coords[3] = LLVMGetUndef(ctx->i32);
2664 count = 4;
2665 }
2666 res = ac_build_gather_values(&ctx->ac, coords, count);
2667 }
2668 return res;
2669 }
2670
2671 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2672 nir_intrinsic_instr *instr)
2673 {
2674 LLVMValueRef params[7];
2675 LLVMValueRef res;
2676 char intrinsic_name[64];
2677 const nir_variable *var = instr->variables[0]->var;
2678 const struct glsl_type *type = var->type;
2679 if(instr->variables[0]->deref.child)
2680 type = instr->variables[0]->deref.child->type;
2681
2682 type = glsl_without_array(type);
2683 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2684 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2685 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2686 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2687 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2688 params[3] = ctx->i1false; /* glc */
2689 params[4] = ctx->i1false; /* slc */
2690 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2691 params, 5, 0);
2692
2693 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2694 res = to_integer(ctx, res);
2695 } else {
2696 bool is_da = glsl_sampler_type_is_array(type) ||
2697 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2698 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
2699 LLVMValueRef glc = ctx->i1false;
2700 LLVMValueRef slc = ctx->i1false;
2701
2702 params[0] = get_image_coords(ctx, instr);
2703 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2704 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2705 if (HAVE_LLVM <= 0x0309) {
2706 params[3] = ctx->i1false; /* r128 */
2707 params[4] = da;
2708 params[5] = glc;
2709 params[6] = slc;
2710 } else {
2711 LLVMValueRef lwe = ctx->i1false;
2712 params[3] = glc;
2713 params[4] = slc;
2714 params[5] = lwe;
2715 params[6] = da;
2716 }
2717
2718 ac_get_image_intr_name("llvm.amdgcn.image.load",
2719 ctx->v4f32, /* vdata */
2720 LLVMTypeOf(params[0]), /* coords */
2721 LLVMTypeOf(params[1]), /* rsrc */
2722 intrinsic_name, sizeof(intrinsic_name));
2723
2724 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2725 params, 7, AC_FUNC_ATTR_READONLY);
2726 }
2727 return to_integer(ctx, res);
2728 }
2729
2730 static void visit_image_store(struct nir_to_llvm_context *ctx,
2731 nir_intrinsic_instr *instr)
2732 {
2733 LLVMValueRef params[8];
2734 char intrinsic_name[64];
2735 const nir_variable *var = instr->variables[0]->var;
2736 const struct glsl_type *type = glsl_without_array(var->type);
2737
2738 if (ctx->stage == MESA_SHADER_FRAGMENT)
2739 ctx->shader_info->fs.writes_memory = true;
2740
2741 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2742 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2743 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2744 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2745 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2746 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2747 params[4] = ctx->i1false; /* glc */
2748 params[5] = ctx->i1false; /* slc */
2749 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2750 params, 6, 0);
2751 } else {
2752 bool is_da = glsl_sampler_type_is_array(type) ||
2753 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2754 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
2755 LLVMValueRef glc = ctx->i1false;
2756 LLVMValueRef slc = ctx->i1false;
2757
2758 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2759 params[1] = get_image_coords(ctx, instr); /* coords */
2760 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2761 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2762 if (HAVE_LLVM <= 0x0309) {
2763 params[4] = ctx->i1false; /* r128 */
2764 params[5] = da;
2765 params[6] = glc;
2766 params[7] = slc;
2767 } else {
2768 LLVMValueRef lwe = ctx->i1false;
2769 params[4] = glc;
2770 params[5] = slc;
2771 params[6] = lwe;
2772 params[7] = da;
2773 }
2774
2775 ac_get_image_intr_name("llvm.amdgcn.image.store",
2776 LLVMTypeOf(params[0]), /* vdata */
2777 LLVMTypeOf(params[1]), /* coords */
2778 LLVMTypeOf(params[2]), /* rsrc */
2779 intrinsic_name, sizeof(intrinsic_name));
2780
2781 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2782 params, 8, 0);
2783 }
2784
2785 }
2786
2787 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2788 nir_intrinsic_instr *instr)
2789 {
2790 LLVMValueRef params[6];
2791 int param_count = 0;
2792 const nir_variable *var = instr->variables[0]->var;
2793
2794 const char *base_name = "llvm.amdgcn.image.atomic";
2795 const char *atomic_name;
2796 LLVMValueRef coords;
2797 char intrinsic_name[32], coords_type[8];
2798 const struct glsl_type *type = glsl_without_array(var->type);
2799
2800 if (ctx->stage == MESA_SHADER_FRAGMENT)
2801 ctx->shader_info->fs.writes_memory = true;
2802
2803 params[param_count++] = get_src(ctx, instr->src[2]);
2804 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2805 params[param_count++] = get_src(ctx, instr->src[3]);
2806
2807 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2808 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2809 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2810 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2811 params[param_count++] = ctx->i32zero; /* voffset */
2812 params[param_count++] = ctx->i1false; /* glc */
2813 params[param_count++] = ctx->i1false; /* slc */
2814 } else {
2815 bool da = glsl_sampler_type_is_array(type) ||
2816 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2817
2818 coords = params[param_count++] = get_image_coords(ctx, instr);
2819 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2820 params[param_count++] = ctx->i1false; /* r128 */
2821 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
2822 params[param_count++] = ctx->i1false; /* slc */
2823 }
2824
2825 switch (instr->intrinsic) {
2826 case nir_intrinsic_image_atomic_add:
2827 atomic_name = "add";
2828 break;
2829 case nir_intrinsic_image_atomic_min:
2830 atomic_name = "smin";
2831 break;
2832 case nir_intrinsic_image_atomic_max:
2833 atomic_name = "smax";
2834 break;
2835 case nir_intrinsic_image_atomic_and:
2836 atomic_name = "and";
2837 break;
2838 case nir_intrinsic_image_atomic_or:
2839 atomic_name = "or";
2840 break;
2841 case nir_intrinsic_image_atomic_xor:
2842 atomic_name = "xor";
2843 break;
2844 case nir_intrinsic_image_atomic_exchange:
2845 atomic_name = "swap";
2846 break;
2847 case nir_intrinsic_image_atomic_comp_swap:
2848 atomic_name = "cmpswap";
2849 break;
2850 default:
2851 abort();
2852 }
2853 build_int_type_name(LLVMTypeOf(coords),
2854 coords_type, sizeof(coords_type));
2855
2856 snprintf(intrinsic_name, sizeof(intrinsic_name),
2857 "%s.%s.%s", base_name, atomic_name, coords_type);
2858 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2859 }
2860
2861 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2862 nir_intrinsic_instr *instr)
2863 {
2864 LLVMValueRef res;
2865 const nir_variable *var = instr->variables[0]->var;
2866 const struct glsl_type *type = instr->variables[0]->var->type;
2867 bool da = glsl_sampler_type_is_array(var->type) ||
2868 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2869 if(instr->variables[0]->deref.child)
2870 type = instr->variables[0]->deref.child->type;
2871
2872 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2873 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2874
2875 struct ac_image_args args = { 0 };
2876
2877 args.da = da;
2878 args.dmask = 0xf;
2879 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2880 args.opcode = ac_image_get_resinfo;
2881 args.addr = ctx->i32zero;
2882
2883 res = ac_build_image_opcode(&ctx->ac, &args);
2884
2885 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2886 glsl_sampler_type_is_array(type)) {
2887 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2888 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2889 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2890 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2891 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2892 }
2893 return res;
2894 }
2895
2896 #define NOOP_WAITCNT 0xf7f
2897 #define LGKM_CNT 0x07f
2898 #define VM_CNT 0xf70
2899
2900 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
2901 unsigned simm16)
2902 {
2903 LLVMValueRef args[1] = {
2904 LLVMConstInt(ctx->i32, simm16, false),
2905 };
2906 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2907 ctx->voidt, args, 1, 0);
2908 }
2909
2910 static void emit_barrier(struct nir_to_llvm_context *ctx)
2911 {
2912 // TODO tess
2913 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2914 ctx->voidt, NULL, 0, 0);
2915 }
2916
2917 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2918 nir_intrinsic_instr *instr)
2919 {
2920 LLVMValueRef cond;
2921 ctx->shader_info->fs.can_discard = true;
2922
2923 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2924 get_src(ctx, instr->src[0]),
2925 ctx->i32zero, "");
2926
2927 cond = LLVMBuildSelect(ctx->builder, cond,
2928 LLVMConstReal(ctx->f32, -1.0f),
2929 ctx->f32zero, "");
2930 ac_build_kill(&ctx->ac, cond);
2931 }
2932
2933 static LLVMValueRef
2934 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2935 {
2936 LLVMValueRef result;
2937 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2938 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2939 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2940
2941 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2942 }
2943
2944 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2945 nir_intrinsic_instr *instr)
2946 {
2947 LLVMValueRef ptr, result;
2948 int idx = instr->variables[0]->var->data.driver_location;
2949 LLVMValueRef src = get_src(ctx, instr->src[0]);
2950 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2951
2952 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2953 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2954 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2955 ptr, src, src1,
2956 LLVMAtomicOrderingSequentiallyConsistent,
2957 LLVMAtomicOrderingSequentiallyConsistent,
2958 false);
2959 } else {
2960 LLVMAtomicRMWBinOp op;
2961 switch (instr->intrinsic) {
2962 case nir_intrinsic_var_atomic_add:
2963 op = LLVMAtomicRMWBinOpAdd;
2964 break;
2965 case nir_intrinsic_var_atomic_umin:
2966 op = LLVMAtomicRMWBinOpUMin;
2967 break;
2968 case nir_intrinsic_var_atomic_umax:
2969 op = LLVMAtomicRMWBinOpUMax;
2970 break;
2971 case nir_intrinsic_var_atomic_imin:
2972 op = LLVMAtomicRMWBinOpMin;
2973 break;
2974 case nir_intrinsic_var_atomic_imax:
2975 op = LLVMAtomicRMWBinOpMax;
2976 break;
2977 case nir_intrinsic_var_atomic_and:
2978 op = LLVMAtomicRMWBinOpAnd;
2979 break;
2980 case nir_intrinsic_var_atomic_or:
2981 op = LLVMAtomicRMWBinOpOr;
2982 break;
2983 case nir_intrinsic_var_atomic_xor:
2984 op = LLVMAtomicRMWBinOpXor;
2985 break;
2986 case nir_intrinsic_var_atomic_exchange:
2987 op = LLVMAtomicRMWBinOpXchg;
2988 break;
2989 default:
2990 return NULL;
2991 }
2992
2993 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2994 LLVMAtomicOrderingSequentiallyConsistent,
2995 false);
2996 }
2997 return result;
2998 }
2999
3000 #define INTERP_CENTER 0
3001 #define INTERP_CENTROID 1
3002 #define INTERP_SAMPLE 2
3003
3004 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3005 enum glsl_interp_mode interp, unsigned location)
3006 {
3007 switch (interp) {
3008 case INTERP_MODE_FLAT:
3009 default:
3010 return NULL;
3011 case INTERP_MODE_SMOOTH:
3012 case INTERP_MODE_NONE:
3013 if (location == INTERP_CENTER)
3014 return ctx->persp_center;
3015 else if (location == INTERP_CENTROID)
3016 return ctx->persp_centroid;
3017 else if (location == INTERP_SAMPLE)
3018 return ctx->persp_sample;
3019 break;
3020 case INTERP_MODE_NOPERSPECTIVE:
3021 if (location == INTERP_CENTER)
3022 return ctx->linear_center;
3023 else if (location == INTERP_CENTROID)
3024 return ctx->linear_centroid;
3025 else if (location == INTERP_SAMPLE)
3026 return ctx->linear_sample;
3027 break;
3028 }
3029 return NULL;
3030 }
3031
3032 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3033 LLVMValueRef sample_id)
3034 {
3035 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
3036 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
3037 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
3038 LLVMValueRef result[2];
3039
3040 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
3041 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
3042
3043 return ac_build_gather_values(&ctx->ac, result, 2);
3044 }
3045
3046 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3047 {
3048 LLVMValueRef values[2];
3049
3050 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3051 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3052 return ac_build_gather_values(&ctx->ac, values, 2);
3053 }
3054
3055 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3056 nir_intrinsic_instr *instr)
3057 {
3058 LLVMValueRef result[2];
3059 LLVMValueRef interp_param, attr_number;
3060 unsigned location;
3061 unsigned chan;
3062 LLVMValueRef src_c0, src_c1;
3063 LLVMValueRef src0;
3064 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3065 switch (instr->intrinsic) {
3066 case nir_intrinsic_interp_var_at_centroid:
3067 location = INTERP_CENTROID;
3068 break;
3069 case nir_intrinsic_interp_var_at_sample:
3070 location = INTERP_SAMPLE;
3071 src0 = get_src(ctx, instr->src[0]);
3072 break;
3073 case nir_intrinsic_interp_var_at_offset:
3074 location = INTERP_CENTER;
3075 src0 = get_src(ctx, instr->src[0]);
3076 default:
3077 break;
3078 }
3079
3080 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3081 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3082 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3083 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3084 LLVMValueRef sample_position;
3085 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3086
3087 /* fetch sample ID */
3088 sample_position = load_sample_position(ctx, src0);
3089
3090 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3091 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3092 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3093 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3094 }
3095 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3096 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3097
3098 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3099 LLVMValueRef ij_out[2];
3100 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3101
3102 /*
3103 * take the I then J parameters, and the DDX/Y for it, and
3104 * calculate the IJ inputs for the interpolator.
3105 * temp1 = ddx * offset/sample.x + I;
3106 * interp_param.I = ddy * offset/sample.y + temp1;
3107 * temp1 = ddx * offset/sample.x + J;
3108 * interp_param.J = ddy * offset/sample.y + temp1;
3109 */
3110 for (unsigned i = 0; i < 2; i++) {
3111 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3112 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3113 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3114 ddxy_out, ix_ll, "");
3115 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3116 ddxy_out, iy_ll, "");
3117 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3118 interp_param, ix_ll, "");
3119 LLVMValueRef temp1, temp2;
3120
3121 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3122 ctx->f32, "");
3123
3124 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3125 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3126
3127 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3128 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3129
3130 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3131 temp2, ctx->i32, "");
3132 }
3133 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3134
3135 }
3136
3137 for (chan = 0; chan < 2; chan++) {
3138 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3139
3140 if (interp_param) {
3141 interp_param = LLVMBuildBitCast(ctx->builder,
3142 interp_param, LLVMVectorType(ctx->f32, 2), "");
3143 LLVMValueRef i = LLVMBuildExtractElement(
3144 ctx->builder, interp_param, ctx->i32zero, "");
3145 LLVMValueRef j = LLVMBuildExtractElement(
3146 ctx->builder, interp_param, ctx->i32one, "");
3147
3148 result[chan] = ac_build_fs_interp(&ctx->ac,
3149 llvm_chan, attr_number,
3150 ctx->prim_mask, i, j);
3151 } else {
3152 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3153 LLVMConstInt(ctx->i32, 2, false),
3154 llvm_chan, attr_number,
3155 ctx->prim_mask);
3156 }
3157 }
3158 return ac_build_gather_values(&ctx->ac, result, 2);
3159 }
3160
3161 static void
3162 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3163 nir_intrinsic_instr *instr)
3164 {
3165 LLVMValueRef gs_next_vertex;
3166 LLVMValueRef can_emit, kill;
3167 int idx;
3168
3169 assert(instr->const_index[0] == 0);
3170 /* Write vertex attribute values to GSVS ring */
3171 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3172 ctx->gs_next_vertex,
3173 "");
3174
3175 /* If this thread has already emitted the declared maximum number of
3176 * vertices, kill it: excessive vertex emissions are not supposed to
3177 * have any effect, and GS threads have no externally observable
3178 * effects other than emitting vertices.
3179 */
3180 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3181 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3182
3183 kill = LLVMBuildSelect(ctx->builder, can_emit,
3184 LLVMConstReal(ctx->f32, 1.0f),
3185 LLVMConstReal(ctx->f32, -1.0f), "");
3186 ac_build_kill(&ctx->ac, kill);
3187
3188 /* loop num outputs */
3189 idx = 0;
3190 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3191 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3192 int length = 4;
3193 int slot = idx;
3194 int slot_inc = 1;
3195
3196 if (!(ctx->output_mask & (1ull << i)))
3197 continue;
3198
3199 if (i == VARYING_SLOT_CLIP_DIST0) {
3200 /* pack clip and cull into a single set of slots */
3201 length = ctx->num_output_clips + ctx->num_output_culls;
3202 if (length > 4)
3203 slot_inc = 2;
3204 }
3205 for (unsigned j = 0; j < length; j++) {
3206 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3207 out_ptr[j], "");
3208 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3209 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3210 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3211
3212 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3213
3214 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3215 out_val, 1,
3216 voffset, ctx->gs2vs_offset, 0,
3217 1, 1, true, true);
3218 }
3219 idx += slot_inc;
3220 }
3221
3222 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3223 ctx->i32one, "");
3224 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3225
3226 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3227 }
3228
3229 static void
3230 visit_end_primitive(struct nir_to_llvm_context *ctx,
3231 nir_intrinsic_instr *instr)
3232 {
3233 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3234 }
3235
3236 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3237 nir_intrinsic_instr *instr)
3238 {
3239 LLVMValueRef result = NULL;
3240
3241 switch (instr->intrinsic) {
3242 case nir_intrinsic_load_work_group_id: {
3243 result = ctx->workgroup_ids;
3244 break;
3245 }
3246 case nir_intrinsic_load_base_vertex: {
3247 result = ctx->base_vertex;
3248 break;
3249 }
3250 case nir_intrinsic_load_vertex_id_zero_base: {
3251 result = ctx->vertex_id;
3252 break;
3253 }
3254 case nir_intrinsic_load_local_invocation_id: {
3255 result = ctx->local_invocation_ids;
3256 break;
3257 }
3258 case nir_intrinsic_load_base_instance:
3259 result = ctx->start_instance;
3260 break;
3261 case nir_intrinsic_load_draw_id:
3262 result = ctx->draw_index;
3263 break;
3264 case nir_intrinsic_load_invocation_id:
3265 result = ctx->gs_invocation_id;
3266 break;
3267 case nir_intrinsic_load_primitive_id:
3268 if (ctx->stage == MESA_SHADER_GEOMETRY)
3269 result = ctx->gs_prim_id;
3270 else
3271 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3272 break;
3273 case nir_intrinsic_load_sample_id:
3274 ctx->shader_info->fs.force_persample = true;
3275 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3276 break;
3277 case nir_intrinsic_load_sample_pos:
3278 ctx->shader_info->fs.force_persample = true;
3279 result = load_sample_pos(ctx);
3280 break;
3281 case nir_intrinsic_load_sample_mask_in:
3282 result = ctx->sample_coverage;
3283 break;
3284 case nir_intrinsic_load_front_face:
3285 result = ctx->front_face;
3286 break;
3287 case nir_intrinsic_load_instance_id:
3288 result = ctx->instance_id;
3289 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3290 ctx->shader_info->vs.vgpr_comp_cnt);
3291 break;
3292 case nir_intrinsic_load_num_work_groups:
3293 result = ctx->num_work_groups;
3294 break;
3295 case nir_intrinsic_load_local_invocation_index:
3296 result = visit_load_local_invocation_index(ctx);
3297 break;
3298 case nir_intrinsic_load_push_constant:
3299 result = visit_load_push_constant(ctx, instr);
3300 break;
3301 case nir_intrinsic_vulkan_resource_index:
3302 result = visit_vulkan_resource_index(ctx, instr);
3303 break;
3304 case nir_intrinsic_store_ssbo:
3305 visit_store_ssbo(ctx, instr);
3306 break;
3307 case nir_intrinsic_load_ssbo:
3308 result = visit_load_buffer(ctx, instr);
3309 break;
3310 case nir_intrinsic_ssbo_atomic_add:
3311 case nir_intrinsic_ssbo_atomic_imin:
3312 case nir_intrinsic_ssbo_atomic_umin:
3313 case nir_intrinsic_ssbo_atomic_imax:
3314 case nir_intrinsic_ssbo_atomic_umax:
3315 case nir_intrinsic_ssbo_atomic_and:
3316 case nir_intrinsic_ssbo_atomic_or:
3317 case nir_intrinsic_ssbo_atomic_xor:
3318 case nir_intrinsic_ssbo_atomic_exchange:
3319 case nir_intrinsic_ssbo_atomic_comp_swap:
3320 result = visit_atomic_ssbo(ctx, instr);
3321 break;
3322 case nir_intrinsic_load_ubo:
3323 result = visit_load_ubo_buffer(ctx, instr);
3324 break;
3325 case nir_intrinsic_get_buffer_size:
3326 result = visit_get_buffer_size(ctx, instr);
3327 break;
3328 case nir_intrinsic_load_var:
3329 result = visit_load_var(ctx, instr);
3330 break;
3331 case nir_intrinsic_store_var:
3332 visit_store_var(ctx, instr);
3333 break;
3334 case nir_intrinsic_image_load:
3335 result = visit_image_load(ctx, instr);
3336 break;
3337 case nir_intrinsic_image_store:
3338 visit_image_store(ctx, instr);
3339 break;
3340 case nir_intrinsic_image_atomic_add:
3341 case nir_intrinsic_image_atomic_min:
3342 case nir_intrinsic_image_atomic_max:
3343 case nir_intrinsic_image_atomic_and:
3344 case nir_intrinsic_image_atomic_or:
3345 case nir_intrinsic_image_atomic_xor:
3346 case nir_intrinsic_image_atomic_exchange:
3347 case nir_intrinsic_image_atomic_comp_swap:
3348 result = visit_image_atomic(ctx, instr);
3349 break;
3350 case nir_intrinsic_image_size:
3351 result = visit_image_size(ctx, instr);
3352 break;
3353 case nir_intrinsic_discard:
3354 ctx->shader_info->fs.can_discard = true;
3355 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3356 ctx->voidt,
3357 NULL, 0, AC_FUNC_ATTR_LEGACY);
3358 break;
3359 case nir_intrinsic_discard_if:
3360 emit_discard_if(ctx, instr);
3361 break;
3362 case nir_intrinsic_memory_barrier:
3363 emit_waitcnt(ctx, VM_CNT);
3364 break;
3365 case nir_intrinsic_barrier:
3366 emit_barrier(ctx);
3367 break;
3368 case nir_intrinsic_var_atomic_add:
3369 case nir_intrinsic_var_atomic_imin:
3370 case nir_intrinsic_var_atomic_umin:
3371 case nir_intrinsic_var_atomic_imax:
3372 case nir_intrinsic_var_atomic_umax:
3373 case nir_intrinsic_var_atomic_and:
3374 case nir_intrinsic_var_atomic_or:
3375 case nir_intrinsic_var_atomic_xor:
3376 case nir_intrinsic_var_atomic_exchange:
3377 case nir_intrinsic_var_atomic_comp_swap:
3378 result = visit_var_atomic(ctx, instr);
3379 break;
3380 case nir_intrinsic_interp_var_at_centroid:
3381 case nir_intrinsic_interp_var_at_sample:
3382 case nir_intrinsic_interp_var_at_offset:
3383 result = visit_interp(ctx, instr);
3384 break;
3385 case nir_intrinsic_emit_vertex:
3386 visit_emit_vertex(ctx, instr);
3387 break;
3388 case nir_intrinsic_end_primitive:
3389 visit_end_primitive(ctx, instr);
3390 break;
3391 default:
3392 fprintf(stderr, "Unknown intrinsic: ");
3393 nir_print_instr(&instr->instr, stderr);
3394 fprintf(stderr, "\n");
3395 break;
3396 }
3397 if (result) {
3398 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3399 }
3400 }
3401
3402 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3403 nir_deref_var *deref,
3404 enum desc_type desc_type)
3405 {
3406 unsigned desc_set = deref->var->data.descriptor_set;
3407 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3408 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3409 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3410 unsigned offset = binding->offset;
3411 unsigned stride = binding->size;
3412 unsigned type_size;
3413 LLVMBuilderRef builder = ctx->builder;
3414 LLVMTypeRef type;
3415 LLVMValueRef index = NULL;
3416 unsigned constant_index = 0;
3417
3418 assert(deref->var->data.binding < layout->binding_count);
3419
3420 switch (desc_type) {
3421 case DESC_IMAGE:
3422 type = ctx->v8i32;
3423 type_size = 32;
3424 break;
3425 case DESC_FMASK:
3426 type = ctx->v8i32;
3427 offset += 32;
3428 type_size = 32;
3429 break;
3430 case DESC_SAMPLER:
3431 type = ctx->v4i32;
3432 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3433 offset += 64;
3434
3435 type_size = 16;
3436 break;
3437 case DESC_BUFFER:
3438 type = ctx->v4i32;
3439 type_size = 16;
3440 break;
3441 default:
3442 unreachable("invalid desc_type\n");
3443 }
3444
3445 if (deref->deref.child) {
3446 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3447
3448 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3449 offset += child->base_offset * stride;
3450 if (child->deref_array_type == nir_deref_array_type_indirect) {
3451 index = get_src(ctx, child->indirect);
3452 }
3453
3454 constant_index = child->base_offset;
3455 }
3456 if (desc_type == DESC_SAMPLER && binding->immutable_samplers &&
3457 (!index || binding->immutable_samplers_equal)) {
3458 if (binding->immutable_samplers_equal)
3459 constant_index = 0;
3460
3461 LLVMValueRef constants[] = {
3462 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 0], 0),
3463 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 1], 0),
3464 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 2], 0),
3465 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 3], 0),
3466 };
3467 return ac_build_gather_values(&ctx->ac, constants, 4);
3468 }
3469
3470 assert(stride % type_size == 0);
3471
3472 if (!index)
3473 index = ctx->i32zero;
3474
3475 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3476
3477 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3478 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3479
3480 return ac_build_indexed_load_const(&ctx->ac, list, index);
3481 }
3482
3483 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3484 struct ac_image_args *args,
3485 nir_tex_instr *instr,
3486 nir_texop op,
3487 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3488 LLVMValueRef *param, unsigned count,
3489 unsigned dmask)
3490 {
3491 unsigned is_rect = 0;
3492 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3493
3494 if (op == nir_texop_lod)
3495 da = false;
3496 /* Pad to power of two vector */
3497 while (count < util_next_power_of_two(count))
3498 param[count++] = LLVMGetUndef(ctx->i32);
3499
3500 if (count > 1)
3501 args->addr = ac_build_gather_values(&ctx->ac, param, count);
3502 else
3503 args->addr = param[0];
3504
3505 args->resource = res_ptr;
3506 args->sampler = samp_ptr;
3507
3508 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3509 args->addr = param[0];
3510 return;
3511 }
3512
3513 args->dmask = dmask;
3514 args->unorm = is_rect;
3515 args->da = da;
3516 }
3517
3518 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3519 *
3520 * SI-CI:
3521 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3522 * filtering manually. The driver sets img7 to a mask clearing
3523 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3524 * s_and_b32 samp0, samp0, img7
3525 *
3526 * VI:
3527 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3528 */
3529 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3530 LLVMValueRef res, LLVMValueRef samp)
3531 {
3532 LLVMBuilderRef builder = ctx->builder;
3533 LLVMValueRef img7, samp0;
3534
3535 if (ctx->options->chip_class >= VI)
3536 return samp;
3537
3538 img7 = LLVMBuildExtractElement(builder, res,
3539 LLVMConstInt(ctx->i32, 7, 0), "");
3540 samp0 = LLVMBuildExtractElement(builder, samp,
3541 LLVMConstInt(ctx->i32, 0, 0), "");
3542 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3543 return LLVMBuildInsertElement(builder, samp, samp0,
3544 LLVMConstInt(ctx->i32, 0, 0), "");
3545 }
3546
3547 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3548 nir_tex_instr *instr,
3549 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3550 LLVMValueRef *fmask_ptr)
3551 {
3552 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3553 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3554 else
3555 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3556 if (samp_ptr) {
3557 if (instr->sampler)
3558 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3559 else
3560 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3561 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3562 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3563 }
3564 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3565 instr->op == nir_texop_samples_identical))
3566 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3567 }
3568
3569 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3570 LLVMValueRef coord)
3571 {
3572 coord = to_float(ctx, coord);
3573 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3574 coord = to_integer(ctx, coord);
3575 return coord;
3576 }
3577
3578 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3579 {
3580 LLVMValueRef result = NULL;
3581 struct ac_image_args args = { 0 };
3582 unsigned dmask = 0xf;
3583 LLVMValueRef address[16];
3584 LLVMValueRef coords[5];
3585 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3586 LLVMValueRef bias = NULL, offsets = NULL;
3587 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3588 LLVMValueRef ddx = NULL, ddy = NULL;
3589 LLVMValueRef derivs[6];
3590 unsigned chan, count = 0;
3591 unsigned const_src = 0, num_deriv_comp = 0;
3592
3593 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3594
3595 for (unsigned i = 0; i < instr->num_srcs; i++) {
3596 switch (instr->src[i].src_type) {
3597 case nir_tex_src_coord:
3598 coord = get_src(ctx, instr->src[i].src);
3599 break;
3600 case nir_tex_src_projector:
3601 break;
3602 case nir_tex_src_comparator:
3603 comparator = get_src(ctx, instr->src[i].src);
3604 break;
3605 case nir_tex_src_offset:
3606 offsets = get_src(ctx, instr->src[i].src);
3607 const_src = i;
3608 break;
3609 case nir_tex_src_bias:
3610 bias = get_src(ctx, instr->src[i].src);
3611 break;
3612 case nir_tex_src_lod:
3613 lod = get_src(ctx, instr->src[i].src);
3614 break;
3615 case nir_tex_src_ms_index:
3616 sample_index = get_src(ctx, instr->src[i].src);
3617 break;
3618 case nir_tex_src_ms_mcs:
3619 break;
3620 case nir_tex_src_ddx:
3621 ddx = get_src(ctx, instr->src[i].src);
3622 num_deriv_comp = instr->src[i].src.ssa->num_components;
3623 break;
3624 case nir_tex_src_ddy:
3625 ddy = get_src(ctx, instr->src[i].src);
3626 break;
3627 case nir_tex_src_texture_offset:
3628 case nir_tex_src_sampler_offset:
3629 case nir_tex_src_plane:
3630 default:
3631 break;
3632 }
3633 }
3634
3635 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3636 result = get_buffer_size(ctx, res_ptr, true);
3637 goto write_result;
3638 }
3639
3640 if (instr->op == nir_texop_texture_samples) {
3641 LLVMValueRef res, samples, is_msaa;
3642 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3643 samples = LLVMBuildExtractElement(ctx->builder, res,
3644 LLVMConstInt(ctx->i32, 3, false), "");
3645 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3646 LLVMConstInt(ctx->i32, 28, false), "");
3647 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3648 LLVMConstInt(ctx->i32, 0xe, false), "");
3649 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3650 LLVMConstInt(ctx->i32, 0xe, false), "");
3651
3652 samples = LLVMBuildLShr(ctx->builder, samples,
3653 LLVMConstInt(ctx->i32, 16, false), "");
3654 samples = LLVMBuildAnd(ctx->builder, samples,
3655 LLVMConstInt(ctx->i32, 0xf, false), "");
3656 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3657 samples, "");
3658 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3659 ctx->i32one, "");
3660 result = samples;
3661 goto write_result;
3662 }
3663
3664 if (coord)
3665 for (chan = 0; chan < instr->coord_components; chan++)
3666 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3667
3668 if (offsets && instr->op != nir_texop_txf) {
3669 LLVMValueRef offset[3], pack;
3670 for (chan = 0; chan < 3; ++chan)
3671 offset[chan] = ctx->i32zero;
3672
3673 args.offset = true;
3674 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3675 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3676 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3677 LLVMConstInt(ctx->i32, 0x3f, false), "");
3678 if (chan)
3679 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3680 LLVMConstInt(ctx->i32, chan * 8, false), "");
3681 }
3682 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3683 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3684 address[count++] = pack;
3685
3686 }
3687 /* pack LOD bias value */
3688 if (instr->op == nir_texop_txb && bias) {
3689 address[count++] = bias;
3690 }
3691
3692 /* Pack depth comparison value */
3693 if (instr->is_shadow && comparator) {
3694 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3695 }
3696
3697 /* pack derivatives */
3698 if (ddx || ddy) {
3699 switch (instr->sampler_dim) {
3700 case GLSL_SAMPLER_DIM_3D:
3701 case GLSL_SAMPLER_DIM_CUBE:
3702 num_deriv_comp = 3;
3703 break;
3704 case GLSL_SAMPLER_DIM_2D:
3705 default:
3706 num_deriv_comp = 2;
3707 break;
3708 case GLSL_SAMPLER_DIM_1D:
3709 num_deriv_comp = 1;
3710 break;
3711 }
3712
3713 for (unsigned i = 0; i < num_deriv_comp; i++) {
3714 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3715 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3716 }
3717 }
3718
3719 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3720 for (chan = 0; chan < instr->coord_components; chan++)
3721 coords[chan] = to_float(ctx, coords[chan]);
3722 if (instr->coord_components == 3)
3723 coords[3] = LLVMGetUndef(ctx->f32);
3724 ac_prepare_cube_coords(&ctx->ac,
3725 instr->op == nir_texop_txd, instr->is_array,
3726 coords, derivs);
3727 if (num_deriv_comp)
3728 num_deriv_comp--;
3729 }
3730
3731 if (ddx || ddy) {
3732 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3733 address[count++] = derivs[i];
3734 }
3735
3736 /* Pack texture coordinates */
3737 if (coord) {
3738 address[count++] = coords[0];
3739 if (instr->coord_components > 1) {
3740 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3741 coords[1] = apply_round_slice(ctx, coords[1]);
3742 }
3743 address[count++] = coords[1];
3744 }
3745 if (instr->coord_components > 2) {
3746 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3747 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3748 coords[2] = apply_round_slice(ctx, coords[2]);
3749 }
3750 address[count++] = coords[2];
3751 }
3752 }
3753
3754 /* Pack LOD */
3755 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3756 address[count++] = lod;
3757 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3758 address[count++] = sample_index;
3759 } else if(instr->op == nir_texop_txs) {
3760 count = 0;
3761 if (lod)
3762 address[count++] = lod;
3763 else
3764 address[count++] = ctx->i32zero;
3765 }
3766
3767 for (chan = 0; chan < count; chan++) {
3768 address[chan] = LLVMBuildBitCast(ctx->builder,
3769 address[chan], ctx->i32, "");
3770 }
3771
3772 if (instr->op == nir_texop_samples_identical) {
3773 LLVMValueRef txf_address[4];
3774 struct ac_image_args txf_args = { 0 };
3775 unsigned txf_count = count;
3776 memcpy(txf_address, address, sizeof(txf_address));
3777
3778 if (!instr->is_array)
3779 txf_address[2] = ctx->i32zero;
3780 txf_address[3] = ctx->i32zero;
3781
3782 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
3783 fmask_ptr, NULL,
3784 txf_address, txf_count, 0xf);
3785
3786 result = build_tex_intrinsic(ctx, instr, &txf_args);
3787
3788 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3789 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3790 goto write_result;
3791 }
3792
3793 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3794 instr->op != nir_texop_txs) {
3795 unsigned sample_chan = instr->is_array ? 3 : 2;
3796 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
3797 address[0],
3798 address[1],
3799 instr->is_array ? address[2] : NULL,
3800 address[sample_chan],
3801 fmask_ptr);
3802 }
3803
3804 if (offsets && instr->op == nir_texop_txf) {
3805 nir_const_value *const_offset =
3806 nir_src_as_const_value(instr->src[const_src].src);
3807 int num_offsets = instr->src[const_src].src.ssa->num_components;
3808 assert(const_offset);
3809 num_offsets = MIN2(num_offsets, instr->coord_components);
3810 if (num_offsets > 2)
3811 address[2] = LLVMBuildAdd(ctx->builder,
3812 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3813 if (num_offsets > 1)
3814 address[1] = LLVMBuildAdd(ctx->builder,
3815 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3816 address[0] = LLVMBuildAdd(ctx->builder,
3817 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3818
3819 }
3820
3821 /* TODO TG4 support */
3822 if (instr->op == nir_texop_tg4) {
3823 if (instr->is_shadow)
3824 dmask = 1;
3825 else
3826 dmask = 1 << instr->component;
3827 }
3828 set_tex_fetch_args(ctx, &args, instr, instr->op,
3829 res_ptr, samp_ptr, address, count, dmask);
3830
3831 result = build_tex_intrinsic(ctx, instr, &args);
3832
3833 if (instr->op == nir_texop_query_levels)
3834 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3835 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3836 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3837 else if (instr->op == nir_texop_txs &&
3838 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3839 instr->is_array) {
3840 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3841 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3842 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3843 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3844 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3845 } else if (instr->dest.ssa.num_components != 4)
3846 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3847
3848 write_result:
3849 if (result) {
3850 assert(instr->dest.is_ssa);
3851 result = to_integer(ctx, result);
3852 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3853 }
3854 }
3855
3856
3857 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3858 {
3859 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3860 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3861
3862 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3863 _mesa_hash_table_insert(ctx->phis, instr, result);
3864 }
3865
3866 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3867 nir_phi_instr *instr,
3868 LLVMValueRef llvm_phi)
3869 {
3870 nir_foreach_phi_src(src, instr) {
3871 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3872 LLVMValueRef llvm_src = get_src(ctx, src->src);
3873
3874 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3875 }
3876 }
3877
3878 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3879 {
3880 struct hash_entry *entry;
3881 hash_table_foreach(ctx->phis, entry) {
3882 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3883 (LLVMValueRef)entry->data);
3884 }
3885 }
3886
3887
3888 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3889 nir_ssa_undef_instr *instr)
3890 {
3891 unsigned num_components = instr->def.num_components;
3892 LLVMValueRef undef;
3893
3894 if (num_components == 1)
3895 undef = LLVMGetUndef(ctx->i32);
3896 else {
3897 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3898 }
3899 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3900 }
3901
3902 static void visit_jump(struct nir_to_llvm_context *ctx,
3903 nir_jump_instr *instr)
3904 {
3905 switch (instr->type) {
3906 case nir_jump_break:
3907 LLVMBuildBr(ctx->builder, ctx->break_block);
3908 LLVMClearInsertionPosition(ctx->builder);
3909 break;
3910 case nir_jump_continue:
3911 LLVMBuildBr(ctx->builder, ctx->continue_block);
3912 LLVMClearInsertionPosition(ctx->builder);
3913 break;
3914 default:
3915 fprintf(stderr, "Unknown NIR jump instr: ");
3916 nir_print_instr(&instr->instr, stderr);
3917 fprintf(stderr, "\n");
3918 abort();
3919 }
3920 }
3921
3922 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3923 struct exec_list *list);
3924
3925 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3926 {
3927 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3928 nir_foreach_instr(instr, block)
3929 {
3930 switch (instr->type) {
3931 case nir_instr_type_alu:
3932 visit_alu(ctx, nir_instr_as_alu(instr));
3933 break;
3934 case nir_instr_type_load_const:
3935 visit_load_const(ctx, nir_instr_as_load_const(instr));
3936 break;
3937 case nir_instr_type_intrinsic:
3938 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3939 break;
3940 case nir_instr_type_tex:
3941 visit_tex(ctx, nir_instr_as_tex(instr));
3942 break;
3943 case nir_instr_type_phi:
3944 visit_phi(ctx, nir_instr_as_phi(instr));
3945 break;
3946 case nir_instr_type_ssa_undef:
3947 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3948 break;
3949 case nir_instr_type_jump:
3950 visit_jump(ctx, nir_instr_as_jump(instr));
3951 break;
3952 default:
3953 fprintf(stderr, "Unknown NIR instr type: ");
3954 nir_print_instr(instr, stderr);
3955 fprintf(stderr, "\n");
3956 abort();
3957 }
3958 }
3959
3960 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3961 }
3962
3963 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3964 {
3965 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3966
3967 LLVMBasicBlockRef merge_block =
3968 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3969 LLVMBasicBlockRef if_block =
3970 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3971 LLVMBasicBlockRef else_block = merge_block;
3972 if (!exec_list_is_empty(&if_stmt->else_list))
3973 else_block = LLVMAppendBasicBlockInContext(
3974 ctx->context, ctx->main_function, "");
3975
3976 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3977 LLVMConstInt(ctx->i32, 0, false), "");
3978 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3979
3980 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3981 visit_cf_list(ctx, &if_stmt->then_list);
3982 if (LLVMGetInsertBlock(ctx->builder))
3983 LLVMBuildBr(ctx->builder, merge_block);
3984
3985 if (!exec_list_is_empty(&if_stmt->else_list)) {
3986 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3987 visit_cf_list(ctx, &if_stmt->else_list);
3988 if (LLVMGetInsertBlock(ctx->builder))
3989 LLVMBuildBr(ctx->builder, merge_block);
3990 }
3991
3992 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3993 }
3994
3995 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3996 {
3997 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3998 LLVMBasicBlockRef break_parent = ctx->break_block;
3999
4000 ctx->continue_block =
4001 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4002 ctx->break_block =
4003 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4004
4005 LLVMBuildBr(ctx->builder, ctx->continue_block);
4006 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4007 visit_cf_list(ctx, &loop->body);
4008
4009 if (LLVMGetInsertBlock(ctx->builder))
4010 LLVMBuildBr(ctx->builder, ctx->continue_block);
4011 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4012
4013 ctx->continue_block = continue_parent;
4014 ctx->break_block = break_parent;
4015 }
4016
4017 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4018 struct exec_list *list)
4019 {
4020 foreach_list_typed(nir_cf_node, node, node, list)
4021 {
4022 switch (node->type) {
4023 case nir_cf_node_block:
4024 visit_block(ctx, nir_cf_node_as_block(node));
4025 break;
4026
4027 case nir_cf_node_if:
4028 visit_if(ctx, nir_cf_node_as_if(node));
4029 break;
4030
4031 case nir_cf_node_loop:
4032 visit_loop(ctx, nir_cf_node_as_loop(node));
4033 break;
4034
4035 default:
4036 assert(0);
4037 }
4038 }
4039 }
4040
4041 static void
4042 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4043 struct nir_variable *variable)
4044 {
4045 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4046 LLVMValueRef t_offset;
4047 LLVMValueRef t_list;
4048 LLVMValueRef args[3];
4049 LLVMValueRef input;
4050 LLVMValueRef buffer_index;
4051 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4052 int idx = variable->data.location;
4053 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4054
4055 variable->data.driver_location = idx * 4;
4056
4057 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4058 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4059 ctx->start_instance, "");
4060 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4061 ctx->shader_info->vs.vgpr_comp_cnt);
4062 } else
4063 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4064 ctx->base_vertex, "");
4065
4066 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4067 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4068
4069 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4070 args[0] = t_list;
4071 args[1] = LLVMConstInt(ctx->i32, 0, false);
4072 args[2] = buffer_index;
4073 input = ac_build_intrinsic(&ctx->ac,
4074 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
4075 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND |
4076 AC_FUNC_ATTR_LEGACY);
4077
4078 for (unsigned chan = 0; chan < 4; chan++) {
4079 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4080 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4081 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4082 input, llvm_chan, ""));
4083 }
4084 }
4085 }
4086
4087 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4088 unsigned attr,
4089 LLVMValueRef interp_param,
4090 LLVMValueRef prim_mask,
4091 LLVMValueRef result[4])
4092 {
4093 LLVMValueRef attr_number;
4094 unsigned chan;
4095 LLVMValueRef i, j;
4096 bool interp = interp_param != NULL;
4097
4098 attr_number = LLVMConstInt(ctx->i32, attr, false);
4099
4100 /* fs.constant returns the param from the middle vertex, so it's not
4101 * really useful for flat shading. It's meant to be used for custom
4102 * interpolation (but the intrinsic can't fetch from the other two
4103 * vertices).
4104 *
4105 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4106 * to do the right thing. The only reason we use fs.constant is that
4107 * fs.interp cannot be used on integers, because they can be equal
4108 * to NaN.
4109 */
4110 if (interp) {
4111 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4112 LLVMVectorType(ctx->f32, 2), "");
4113
4114 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4115 ctx->i32zero, "");
4116 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4117 ctx->i32one, "");
4118 }
4119
4120 for (chan = 0; chan < 4; chan++) {
4121 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4122
4123 if (interp) {
4124 result[chan] = ac_build_fs_interp(&ctx->ac,
4125 llvm_chan,
4126 attr_number,
4127 prim_mask, i, j);
4128 } else {
4129 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4130 LLVMConstInt(ctx->i32, 2, false),
4131 llvm_chan,
4132 attr_number,
4133 prim_mask);
4134 }
4135 }
4136 }
4137
4138 static void
4139 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4140 struct nir_variable *variable)
4141 {
4142 int idx = variable->data.location;
4143 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4144 LLVMValueRef interp;
4145
4146 variable->data.driver_location = idx * 4;
4147 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4148
4149 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4150 unsigned interp_type;
4151 if (variable->data.sample) {
4152 interp_type = INTERP_SAMPLE;
4153 ctx->shader_info->fs.force_persample = true;
4154 } else if (variable->data.centroid)
4155 interp_type = INTERP_CENTROID;
4156 else
4157 interp_type = INTERP_CENTER;
4158
4159 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4160 } else
4161 interp = NULL;
4162
4163 for (unsigned i = 0; i < attrib_count; ++i)
4164 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4165
4166 }
4167
4168 static void
4169 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4170 struct nir_variable *variable)
4171 {
4172 switch (ctx->stage) {
4173 case MESA_SHADER_VERTEX:
4174 handle_vs_input_decl(ctx, variable);
4175 break;
4176 case MESA_SHADER_FRAGMENT:
4177 handle_fs_input_decl(ctx, variable);
4178 break;
4179 default:
4180 break;
4181 }
4182
4183 }
4184
4185 static void
4186 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4187 struct nir_shader *nir)
4188 {
4189 unsigned index = 0;
4190 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4191 LLVMValueRef interp_param;
4192 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4193
4194 if (!(ctx->input_mask & (1ull << i)))
4195 continue;
4196
4197 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4198 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4199 interp_param = *inputs;
4200 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4201 inputs);
4202
4203 if (!interp_param)
4204 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4205 ++index;
4206 } else if (i == VARYING_SLOT_POS) {
4207 for(int i = 0; i < 3; ++i)
4208 inputs[i] = ctx->frag_pos[i];
4209
4210 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4211 }
4212 }
4213 ctx->shader_info->fs.num_interp = index;
4214 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4215 ctx->shader_info->fs.has_pcoord = true;
4216 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4217 ctx->shader_info->fs.prim_id_input = true;
4218 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4219 ctx->shader_info->fs.layer_input = true;
4220 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4221 }
4222
4223 static LLVMValueRef
4224 ac_build_alloca(struct nir_to_llvm_context *ctx,
4225 LLVMTypeRef type,
4226 const char *name)
4227 {
4228 LLVMBuilderRef builder = ctx->builder;
4229 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4230 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4231 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4232 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4233 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4234 LLVMValueRef res;
4235
4236 if (first_instr) {
4237 LLVMPositionBuilderBefore(first_builder, first_instr);
4238 } else {
4239 LLVMPositionBuilderAtEnd(first_builder, first_block);
4240 }
4241
4242 res = LLVMBuildAlloca(first_builder, type, name);
4243 LLVMBuildStore(builder, LLVMConstNull(type), res);
4244
4245 LLVMDisposeBuilder(first_builder);
4246
4247 return res;
4248 }
4249
4250 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4251 LLVMTypeRef type,
4252 const char *name)
4253 {
4254 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4255 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4256 return ptr;
4257 }
4258
4259 static void
4260 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4261 struct nir_variable *variable)
4262 {
4263 int idx = variable->data.location + variable->data.index;
4264 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4265 uint64_t mask_attribs;
4266 variable->data.driver_location = idx * 4;
4267
4268 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4269 if (ctx->stage == MESA_SHADER_VERTEX ||
4270 ctx->stage == MESA_SHADER_GEOMETRY) {
4271 if (idx == VARYING_SLOT_CLIP_DIST0) {
4272 int length = ctx->num_output_clips + ctx->num_output_culls;
4273 if (ctx->stage == MESA_SHADER_VERTEX) {
4274 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4275 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4276 }
4277
4278 if (length > 4)
4279 attrib_count = 2;
4280 else
4281 attrib_count = 1;
4282 mask_attribs = 1ull << idx;
4283 }
4284 }
4285
4286 for (unsigned i = 0; i < attrib_count; ++i) {
4287 for (unsigned chan = 0; chan < 4; chan++) {
4288 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4289 si_build_alloca_undef(ctx, ctx->f32, "");
4290 }
4291 }
4292 ctx->output_mask |= mask_attribs;
4293 }
4294
4295 static void
4296 setup_locals(struct nir_to_llvm_context *ctx,
4297 struct nir_function *func)
4298 {
4299 int i, j;
4300 ctx->num_locals = 0;
4301 nir_foreach_variable(variable, &func->impl->locals) {
4302 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4303 variable->data.driver_location = ctx->num_locals * 4;
4304 ctx->num_locals += attrib_count;
4305 }
4306 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4307 if (!ctx->locals)
4308 return;
4309
4310 for (i = 0; i < ctx->num_locals; i++) {
4311 for (j = 0; j < 4; j++) {
4312 ctx->locals[i * 4 + j] =
4313 si_build_alloca_undef(ctx, ctx->f32, "temp");
4314 }
4315 }
4316 }
4317
4318 static LLVMValueRef
4319 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4320 {
4321 v = to_float(ctx, v);
4322 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4323 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4324 }
4325
4326
4327 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4328 LLVMValueRef src0, LLVMValueRef src1)
4329 {
4330 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4331 LLVMValueRef comp[2];
4332
4333 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4334 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4335 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4336 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4337 }
4338
4339 /* Initialize arguments for the shader export intrinsic */
4340 static void
4341 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4342 LLVMValueRef *values,
4343 unsigned target,
4344 struct ac_export_args *args)
4345 {
4346 /* Default is 0xf. Adjusted below depending on the format. */
4347 args->enabled_channels = 0xf;
4348
4349 /* Specify whether the EXEC mask represents the valid mask */
4350 args->valid_mask = 0;
4351
4352 /* Specify whether this is the last export */
4353 args->done = 0;
4354
4355 /* Specify the target we are exporting */
4356 args->target = target;
4357
4358 args->compr = false;
4359 args->out[0] = LLVMGetUndef(ctx->f32);
4360 args->out[1] = LLVMGetUndef(ctx->f32);
4361 args->out[2] = LLVMGetUndef(ctx->f32);
4362 args->out[3] = LLVMGetUndef(ctx->f32);
4363
4364 if (!values)
4365 return;
4366
4367 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4368 LLVMValueRef val[4];
4369 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4370 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4371 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4372
4373 switch(col_format) {
4374 case V_028714_SPI_SHADER_ZERO:
4375 args->enabled_channels = 0; /* writemask */
4376 args->target = V_008DFC_SQ_EXP_NULL;
4377 break;
4378
4379 case V_028714_SPI_SHADER_32_R:
4380 args->enabled_channels = 1;
4381 args->out[0] = values[0];
4382 break;
4383
4384 case V_028714_SPI_SHADER_32_GR:
4385 args->enabled_channels = 0x3;
4386 args->out[0] = values[0];
4387 args->out[1] = values[1];
4388 break;
4389
4390 case V_028714_SPI_SHADER_32_AR:
4391 args->enabled_channels = 0x9;
4392 args->out[0] = values[0];
4393 args->out[3] = values[3];
4394 break;
4395
4396 case V_028714_SPI_SHADER_FP16_ABGR:
4397 args->compr = 1;
4398
4399 for (unsigned chan = 0; chan < 2; chan++) {
4400 LLVMValueRef pack_args[2] = {
4401 values[2 * chan],
4402 values[2 * chan + 1]
4403 };
4404 LLVMValueRef packed;
4405
4406 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
4407 args->out[chan] = packed;
4408 }
4409 break;
4410
4411 case V_028714_SPI_SHADER_UNORM16_ABGR:
4412 for (unsigned chan = 0; chan < 4; chan++) {
4413 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
4414 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4415 LLVMConstReal(ctx->f32, 65535), "");
4416 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4417 LLVMConstReal(ctx->f32, 0.5), "");
4418 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4419 ctx->i32, "");
4420 }
4421
4422 args->compr = 1;
4423 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4424 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4425 break;
4426
4427 case V_028714_SPI_SHADER_SNORM16_ABGR:
4428 for (unsigned chan = 0; chan < 4; chan++) {
4429 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4430 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4431 LLVMConstReal(ctx->f32, 32767), "");
4432
4433 /* If positive, add 0.5, else add -0.5. */
4434 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4435 LLVMBuildSelect(ctx->builder,
4436 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4437 val[chan], ctx->f32zero, ""),
4438 LLVMConstReal(ctx->f32, 0.5),
4439 LLVMConstReal(ctx->f32, -0.5), ""), "");
4440 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4441 }
4442
4443 args->compr = 1;
4444 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4445 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4446 break;
4447
4448 case V_028714_SPI_SHADER_UINT16_ABGR: {
4449 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4450
4451 for (unsigned chan = 0; chan < 4; chan++) {
4452 val[chan] = to_integer(ctx, values[chan]);
4453 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4454 }
4455
4456 args->compr = 1;
4457 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4458 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4459 break;
4460 }
4461
4462 case V_028714_SPI_SHADER_SINT16_ABGR: {
4463 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4464 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4465
4466 /* Clamp. */
4467 for (unsigned chan = 0; chan < 4; chan++) {
4468 val[chan] = to_integer(ctx, values[chan]);
4469 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4470 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4471 }
4472
4473 args->compr = 1;
4474 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4475 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4476 break;
4477 }
4478
4479 default:
4480 case V_028714_SPI_SHADER_32_ABGR:
4481 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
4482 break;
4483 }
4484 } else
4485 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
4486
4487 for (unsigned i = 0; i < 4; ++i)
4488 args->out[i] = to_float(ctx, args->out[i]);
4489 }
4490
4491 static void
4492 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
4493 struct ac_vs_output_info *outinfo)
4494 {
4495 uint32_t param_count = 0;
4496 unsigned target;
4497 unsigned pos_idx, num_pos_exports = 0;
4498 struct ac_export_args args, pos_args[4] = {};
4499 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4500 int i;
4501
4502 outinfo->prim_id_output = 0xffffffff;
4503 outinfo->layer_output = 0xffffffff;
4504 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
4505 LLVMValueRef slots[8];
4506 unsigned j;
4507
4508 if (outinfo->cull_dist_mask)
4509 outinfo->cull_dist_mask <<= ctx->num_output_clips;
4510
4511 i = VARYING_SLOT_CLIP_DIST0;
4512 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
4513 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4514 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4515
4516 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
4517 slots[i] = LLVMGetUndef(ctx->f32);
4518
4519 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
4520 target = V_008DFC_SQ_EXP_POS + 3;
4521 si_llvm_init_export_args(ctx, &slots[4], target, &args);
4522 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4523 &args, sizeof(args));
4524 }
4525
4526 target = V_008DFC_SQ_EXP_POS + 2;
4527 si_llvm_init_export_args(ctx, &slots[0], target, &args);
4528 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4529 &args, sizeof(args));
4530
4531 }
4532
4533 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4534 LLVMValueRef values[4];
4535 if (!(ctx->output_mask & (1ull << i)))
4536 continue;
4537
4538 for (unsigned j = 0; j < 4; j++)
4539 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4540 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4541
4542 if (i == VARYING_SLOT_POS) {
4543 target = V_008DFC_SQ_EXP_POS;
4544 } else if (i == VARYING_SLOT_CLIP_DIST0) {
4545 continue;
4546 } else if (i == VARYING_SLOT_PSIZ) {
4547 outinfo->writes_pointsize = true;
4548 psize_value = values[0];
4549 continue;
4550 } else if (i == VARYING_SLOT_LAYER) {
4551 outinfo->writes_layer = true;
4552 layer_value = values[0];
4553 outinfo->layer_output = param_count;
4554 target = V_008DFC_SQ_EXP_PARAM + param_count;
4555 param_count++;
4556 } else if (i == VARYING_SLOT_VIEWPORT) {
4557 outinfo->writes_viewport_index = true;
4558 viewport_index_value = values[0];
4559 continue;
4560 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4561 outinfo->prim_id_output = param_count;
4562 target = V_008DFC_SQ_EXP_PARAM + param_count;
4563 param_count++;
4564 } else if (i >= VARYING_SLOT_VAR0) {
4565 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4566 target = V_008DFC_SQ_EXP_PARAM + param_count;
4567 param_count++;
4568 }
4569
4570 si_llvm_init_export_args(ctx, values, target, &args);
4571
4572 if (target >= V_008DFC_SQ_EXP_POS &&
4573 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4574 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4575 &args, sizeof(args));
4576 } else {
4577 ac_build_export(&ctx->ac, &args);
4578 }
4579 }
4580
4581 /* We need to add the position output manually if it's missing. */
4582 if (!pos_args[0].out[0]) {
4583 pos_args[0].enabled_channels = 0xf;
4584 pos_args[0].valid_mask = 0;
4585 pos_args[0].done = 0;
4586 pos_args[0].target = V_008DFC_SQ_EXP_POS;
4587 pos_args[0].compr = 0;
4588 pos_args[0].out[0] = ctx->f32zero; /* X */
4589 pos_args[0].out[1] = ctx->f32zero; /* Y */
4590 pos_args[0].out[2] = ctx->f32zero; /* Z */
4591 pos_args[0].out[3] = ctx->f32one; /* W */
4592 }
4593
4594 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
4595 (outinfo->writes_layer == true ? 4 : 0) |
4596 (outinfo->writes_viewport_index == true ? 8 : 0));
4597 if (mask) {
4598 pos_args[1].enabled_channels = mask;
4599 pos_args[1].valid_mask = 0;
4600 pos_args[1].done = 0;
4601 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
4602 pos_args[1].compr = 0;
4603 pos_args[1].out[0] = ctx->f32zero; /* X */
4604 pos_args[1].out[1] = ctx->f32zero; /* Y */
4605 pos_args[1].out[2] = ctx->f32zero; /* Z */
4606 pos_args[1].out[3] = ctx->f32zero; /* W */
4607
4608 if (outinfo->writes_pointsize == true)
4609 pos_args[1].out[0] = psize_value;
4610 if (outinfo->writes_layer == true)
4611 pos_args[1].out[2] = layer_value;
4612 if (outinfo->writes_viewport_index == true)
4613 pos_args[1].out[3] = viewport_index_value;
4614 }
4615 for (i = 0; i < 4; i++) {
4616 if (pos_args[i].out[0])
4617 num_pos_exports++;
4618 }
4619
4620 pos_idx = 0;
4621 for (i = 0; i < 4; i++) {
4622 if (!pos_args[i].out[0])
4623 continue;
4624
4625 /* Specify the target we are exporting */
4626 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
4627 if (pos_idx == num_pos_exports)
4628 pos_args[i].done = 1;
4629 ac_build_export(&ctx->ac, &pos_args[i]);
4630 }
4631
4632 outinfo->pos_exports = num_pos_exports;
4633 outinfo->param_exports = param_count;
4634 }
4635
4636 static void
4637 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
4638 struct ac_es_output_info *outinfo)
4639 {
4640 int j;
4641 uint64_t max_output_written = 0;
4642 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4643 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4644 int param_index;
4645 int length = 4;
4646
4647 if (!(ctx->output_mask & (1ull << i)))
4648 continue;
4649
4650 if (i == VARYING_SLOT_CLIP_DIST0)
4651 length = ctx->num_output_clips + ctx->num_output_culls;
4652
4653 param_index = shader_io_get_unique_index(i);
4654
4655 max_output_written = MAX2(param_index + (length > 4), max_output_written);
4656
4657 for (j = 0; j < length; j++) {
4658 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4659 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4660
4661 ac_build_buffer_store_dword(&ctx->ac,
4662 ctx->esgs_ring,
4663 out_val, 1,
4664 NULL, ctx->es2gs_offset,
4665 (4 * param_index + j) * 4,
4666 1, 1, true, true);
4667 }
4668 }
4669 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
4670 }
4671
4672 static void
4673 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4674 LLVMValueRef *color, unsigned param, bool is_last)
4675 {
4676
4677 struct ac_export_args args;
4678
4679 /* Export */
4680 si_llvm_init_export_args(ctx, color, param,
4681 &args);
4682
4683 if (is_last) {
4684 args.valid_mask = 1; /* whether the EXEC mask is valid */
4685 args.done = 1; /* DONE bit */
4686 } else if (!args.enabled_channels)
4687 return; /* unnecessary NULL export */
4688
4689 ac_build_export(&ctx->ac, &args);
4690 }
4691
4692 static void
4693 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4694 LLVMValueRef depth, LLVMValueRef stencil,
4695 LLVMValueRef samplemask)
4696 {
4697 struct ac_export_args args;
4698
4699 args.enabled_channels = 0;
4700 args.valid_mask = 1;
4701 args.done = 1;
4702 args.target = V_008DFC_SQ_EXP_MRTZ;
4703 args.compr = false;
4704
4705 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
4706 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4707 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4708 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4709
4710 if (depth) {
4711 args.out[0] = depth;
4712 args.enabled_channels |= 0x1;
4713 }
4714
4715 if (stencil) {
4716 args.out[1] = stencil;
4717 args.enabled_channels |= 0x2;
4718 }
4719
4720 if (samplemask) {
4721 args.out[2] = samplemask;
4722 args.enabled_channels |= 0x4;
4723 }
4724
4725 /* SI (except OLAND) has a bug that it only looks
4726 * at the X writemask component. */
4727 if (ctx->options->chip_class == SI &&
4728 ctx->options->family != CHIP_OLAND)
4729 args.enabled_channels |= 0x1;
4730
4731 ac_build_export(&ctx->ac, &args);
4732 }
4733
4734 static void
4735 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4736 {
4737 unsigned index = 0;
4738 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4739
4740 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4741 LLVMValueRef values[4];
4742
4743 if (!(ctx->output_mask & (1ull << i)))
4744 continue;
4745
4746 if (i == FRAG_RESULT_DEPTH) {
4747 ctx->shader_info->fs.writes_z = true;
4748 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4749 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4750 } else if (i == FRAG_RESULT_STENCIL) {
4751 ctx->shader_info->fs.writes_stencil = true;
4752 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4753 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4754 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
4755 ctx->shader_info->fs.writes_sample_mask = true;
4756 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
4757 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4758 } else {
4759 bool last = false;
4760 for (unsigned j = 0; j < 4; j++)
4761 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4762 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4763
4764 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
4765 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4766
4767 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4768 index++;
4769 }
4770 }
4771
4772 if (depth || stencil || samplemask)
4773 si_export_mrt_z(ctx, depth, stencil, samplemask);
4774 else if (!index)
4775 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4776
4777 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4778 }
4779
4780 static void
4781 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4782 {
4783 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4784 }
4785
4786 static void
4787 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4788 {
4789 switch (ctx->stage) {
4790 case MESA_SHADER_VERTEX:
4791 if (ctx->options->key.vs.as_es)
4792 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
4793 else
4794 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
4795 break;
4796 case MESA_SHADER_FRAGMENT:
4797 handle_fs_outputs_post(ctx);
4798 break;
4799 case MESA_SHADER_GEOMETRY:
4800 emit_gs_epilogue(ctx);
4801 break;
4802 default:
4803 break;
4804 }
4805 }
4806
4807 static void
4808 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4809 struct nir_variable *variable, uint32_t *offset, int idx)
4810 {
4811 unsigned size = glsl_count_attribute_slots(variable->type, false);
4812 variable->data.driver_location = *offset;
4813 *offset += size;
4814 }
4815
4816 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4817 {
4818 LLVMPassManagerRef passmgr;
4819 /* Create the pass manager */
4820 passmgr = LLVMCreateFunctionPassManagerForModule(
4821 ctx->module);
4822
4823 /* This pass should eliminate all the load and store instructions */
4824 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4825
4826 /* Add some optimization passes */
4827 LLVMAddScalarReplAggregatesPass(passmgr);
4828 LLVMAddLICMPass(passmgr);
4829 LLVMAddAggressiveDCEPass(passmgr);
4830 LLVMAddCFGSimplificationPass(passmgr);
4831 LLVMAddInstructionCombiningPass(passmgr);
4832
4833 /* Run the pass */
4834 LLVMInitializeFunctionPassManager(passmgr);
4835 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4836 LLVMFinalizeFunctionPassManager(passmgr);
4837
4838 LLVMDisposeBuilder(ctx->builder);
4839 LLVMDisposePassManager(passmgr);
4840 }
4841
4842 static void
4843 ac_setup_rings(struct nir_to_llvm_context *ctx)
4844 {
4845 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
4846 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
4847 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
4848 }
4849
4850 if (ctx->is_gs_copy_shader) {
4851 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
4852 }
4853 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4854 LLVMValueRef tmp;
4855 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
4856 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
4857
4858 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4859
4860 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4861 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4862 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4863 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4864
4865 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4866 }
4867
4868 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
4869 ctx->stage == MESA_SHADER_TESS_EVAL) {
4870 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
4871 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
4872 }
4873 }
4874
4875 static
4876 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4877 struct nir_shader *nir,
4878 struct ac_shader_variant_info *shader_info,
4879 const struct ac_nir_compiler_options *options)
4880 {
4881 struct nir_to_llvm_context ctx = {0};
4882 struct nir_function *func;
4883 unsigned i;
4884 ctx.options = options;
4885 ctx.shader_info = shader_info;
4886 ctx.context = LLVMContextCreate();
4887 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4888
4889 ac_llvm_context_init(&ctx.ac, ctx.context);
4890 ctx.ac.module = ctx.module;
4891
4892 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4893
4894 memset(shader_info, 0, sizeof(*shader_info));
4895
4896 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4897
4898 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
4899 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
4900 LLVMSetDataLayout(ctx.module, data_layout_str);
4901 LLVMDisposeTargetData(data_layout);
4902 LLVMDisposeMessage(data_layout_str);
4903
4904 setup_types(&ctx);
4905
4906 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4907 ctx.ac.builder = ctx.builder;
4908 ctx.stage = nir->stage;
4909
4910 for (i = 0; i < AC_UD_MAX_SETS; i++)
4911 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4912 for (i = 0; i < AC_UD_MAX_UD; i++)
4913 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4914
4915 create_function(&ctx);
4916
4917 if (nir->stage == MESA_SHADER_COMPUTE) {
4918 int num_shared = 0;
4919 nir_foreach_variable(variable, &nir->shared)
4920 num_shared++;
4921 if (num_shared) {
4922 int idx = 0;
4923 uint32_t shared_size = 0;
4924 LLVMValueRef var;
4925 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4926 nir_foreach_variable(variable, &nir->shared) {
4927 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4928 idx++;
4929 }
4930
4931 shared_size *= 16;
4932 var = LLVMAddGlobalInAddressSpace(ctx.module,
4933 LLVMArrayType(ctx.i8, shared_size),
4934 "compute_lds",
4935 LOCAL_ADDR_SPACE);
4936 LLVMSetAlignment(var, 4);
4937 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4938 }
4939 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4940 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4941
4942 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4943 }
4944
4945 ac_setup_rings(&ctx);
4946
4947 nir_foreach_variable(variable, &nir->inputs)
4948 handle_shader_input_decl(&ctx, variable);
4949
4950 if (nir->stage == MESA_SHADER_FRAGMENT)
4951 handle_fs_inputs_pre(&ctx, nir);
4952
4953 ctx.num_output_clips = nir->info->clip_distance_array_size;
4954 ctx.num_output_culls = nir->info->cull_distance_array_size;
4955
4956 nir_foreach_variable(variable, &nir->outputs)
4957 handle_shader_output_decl(&ctx, variable);
4958
4959 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4960 _mesa_key_pointer_equal);
4961 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4962 _mesa_key_pointer_equal);
4963
4964 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4965
4966 setup_locals(&ctx, func);
4967
4968 visit_cf_list(&ctx, &func->impl->body);
4969 phi_post_pass(&ctx);
4970
4971 handle_shader_outputs_post(&ctx);
4972 LLVMBuildRetVoid(ctx.builder);
4973
4974 ac_llvm_finalize_module(&ctx);
4975 free(ctx.locals);
4976 ralloc_free(ctx.defs);
4977 ralloc_free(ctx.phis);
4978
4979 if (nir->stage == MESA_SHADER_GEOMETRY) {
4980 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
4981 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
4982 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4983 nir->info->gs.vertices_out;
4984 }
4985 return ctx.module;
4986 }
4987
4988 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4989 {
4990 unsigned *retval = (unsigned *)context;
4991 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4992 char *description = LLVMGetDiagInfoDescription(di);
4993
4994 if (severity == LLVMDSError) {
4995 *retval = 1;
4996 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4997 description);
4998 }
4999
5000 LLVMDisposeMessage(description);
5001 }
5002
5003 static unsigned ac_llvm_compile(LLVMModuleRef M,
5004 struct ac_shader_binary *binary,
5005 LLVMTargetMachineRef tm)
5006 {
5007 unsigned retval = 0;
5008 char *err;
5009 LLVMContextRef llvm_ctx;
5010 LLVMMemoryBufferRef out_buffer;
5011 unsigned buffer_size;
5012 const char *buffer_data;
5013 LLVMBool mem_err;
5014
5015 /* Setup Diagnostic Handler*/
5016 llvm_ctx = LLVMGetModuleContext(M);
5017
5018 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5019 &retval);
5020
5021 /* Compile IR*/
5022 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5023 &err, &out_buffer);
5024
5025 /* Process Errors/Warnings */
5026 if (mem_err) {
5027 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5028 free(err);
5029 retval = 1;
5030 goto out;
5031 }
5032
5033 /* Extract Shader Code*/
5034 buffer_size = LLVMGetBufferSize(out_buffer);
5035 buffer_data = LLVMGetBufferStart(out_buffer);
5036
5037 ac_elf_read(buffer_data, buffer_size, binary);
5038
5039 /* Clean up */
5040 LLVMDisposeMemoryBuffer(out_buffer);
5041
5042 out:
5043 return retval;
5044 }
5045
5046 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5047 LLVMModuleRef llvm_module,
5048 struct ac_shader_binary *binary,
5049 struct ac_shader_config *config,
5050 struct ac_shader_variant_info *shader_info,
5051 gl_shader_stage stage,
5052 bool dump_shader, bool supports_spill)
5053 {
5054 if (dump_shader)
5055 ac_dump_module(llvm_module);
5056
5057 memset(binary, 0, sizeof(*binary));
5058 int v = ac_llvm_compile(llvm_module, binary, tm);
5059 if (v) {
5060 fprintf(stderr, "compile failed\n");
5061 }
5062
5063 if (dump_shader)
5064 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5065
5066 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5067
5068 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5069 LLVMDisposeModule(llvm_module);
5070 LLVMContextDispose(ctx);
5071
5072 if (stage == MESA_SHADER_FRAGMENT) {
5073 shader_info->num_input_vgprs = 0;
5074 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5075 shader_info->num_input_vgprs += 2;
5076 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5077 shader_info->num_input_vgprs += 2;
5078 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5079 shader_info->num_input_vgprs += 2;
5080 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5081 shader_info->num_input_vgprs += 3;
5082 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5083 shader_info->num_input_vgprs += 2;
5084 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5085 shader_info->num_input_vgprs += 2;
5086 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5087 shader_info->num_input_vgprs += 2;
5088 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5089 shader_info->num_input_vgprs += 1;
5090 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5091 shader_info->num_input_vgprs += 1;
5092 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5093 shader_info->num_input_vgprs += 1;
5094 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5095 shader_info->num_input_vgprs += 1;
5096 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5097 shader_info->num_input_vgprs += 1;
5098 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5099 shader_info->num_input_vgprs += 1;
5100 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5101 shader_info->num_input_vgprs += 1;
5102 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5103 shader_info->num_input_vgprs += 1;
5104 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5105 shader_info->num_input_vgprs += 1;
5106 }
5107 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5108
5109 /* +3 for scratch wave offset and VCC */
5110 config->num_sgprs = MAX2(config->num_sgprs,
5111 shader_info->num_input_sgprs + 3);
5112 }
5113
5114 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5115 struct ac_shader_binary *binary,
5116 struct ac_shader_config *config,
5117 struct ac_shader_variant_info *shader_info,
5118 struct nir_shader *nir,
5119 const struct ac_nir_compiler_options *options,
5120 bool dump_shader)
5121 {
5122
5123 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5124 options);
5125
5126 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5127 switch (nir->stage) {
5128 case MESA_SHADER_COMPUTE:
5129 for (int i = 0; i < 3; ++i)
5130 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5131 break;
5132 case MESA_SHADER_FRAGMENT:
5133 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5134 break;
5135 case MESA_SHADER_GEOMETRY:
5136 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5137 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5138 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5139 shader_info->gs.invocations = nir->info->gs.invocations;
5140 break;
5141 case MESA_SHADER_VERTEX:
5142 shader_info->vs.as_es = options->key.vs.as_es;
5143 break;
5144 default:
5145 break;
5146 }
5147 }
5148
5149 static void
5150 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5151 {
5152 LLVMValueRef args[9];
5153 args[0] = ctx->gsvs_ring;
5154 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5155 args[3] = ctx->i32zero;
5156 args[4] = ctx->i32one; /* OFFEN */
5157 args[5] = ctx->i32zero; /* IDXEN */
5158 args[6] = ctx->i32one; /* GLC */
5159 args[7] = ctx->i32one; /* SLC */
5160 args[8] = ctx->i32zero; /* TFE */
5161
5162 int idx = 0;
5163
5164 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5165 int length = 4;
5166 int slot = idx;
5167 int slot_inc = 1;
5168 if (!(ctx->output_mask & (1ull << i)))
5169 continue;
5170
5171 if (i == VARYING_SLOT_CLIP_DIST0) {
5172 /* unpack clip and cull from a single set of slots */
5173 length = ctx->num_output_clips + ctx->num_output_culls;
5174 if (length > 4)
5175 slot_inc = 2;
5176 }
5177
5178 for (unsigned j = 0; j < length; j++) {
5179 LLVMValueRef value;
5180 args[2] = LLVMConstInt(ctx->i32,
5181 (slot * 4 + j) *
5182 ctx->gs_max_out_vertices * 16 * 4, false);
5183
5184 value = ac_build_intrinsic(&ctx->ac,
5185 "llvm.SI.buffer.load.dword.i32.i32",
5186 ctx->i32, args, 9,
5187 AC_FUNC_ATTR_READONLY |
5188 AC_FUNC_ATTR_LEGACY);
5189
5190 LLVMBuildStore(ctx->builder,
5191 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5192 }
5193 idx += slot_inc;
5194 }
5195 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5196 }
5197
5198 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5199 struct nir_shader *geom_shader,
5200 struct ac_shader_binary *binary,
5201 struct ac_shader_config *config,
5202 struct ac_shader_variant_info *shader_info,
5203 const struct ac_nir_compiler_options *options,
5204 bool dump_shader)
5205 {
5206 struct nir_to_llvm_context ctx = {0};
5207 ctx.context = LLVMContextCreate();
5208 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5209 ctx.options = options;
5210 ctx.shader_info = shader_info;
5211
5212 ac_llvm_context_init(&ctx.ac, ctx.context);
5213 ctx.ac.module = ctx.module;
5214
5215 ctx.is_gs_copy_shader = true;
5216 LLVMSetTarget(ctx.module, "amdgcn--");
5217 setup_types(&ctx);
5218
5219 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5220 ctx.ac.builder = ctx.builder;
5221 ctx.stage = MESA_SHADER_VERTEX;
5222
5223 create_function(&ctx);
5224
5225 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5226 ac_setup_rings(&ctx);
5227
5228 ctx.num_output_clips = geom_shader->info->clip_distance_array_size;
5229 ctx.num_output_culls = geom_shader->info->cull_distance_array_size;
5230
5231 nir_foreach_variable(variable, &geom_shader->outputs)
5232 handle_shader_output_decl(&ctx, variable);
5233
5234 ac_gs_copy_shader_emit(&ctx);
5235
5236 LLVMBuildRetVoid(ctx.builder);
5237
5238 ac_llvm_finalize_module(&ctx);
5239
5240 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5241 MESA_SHADER_VERTEX,
5242 dump_shader, options->supports_spill);
5243 }