2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
38 enum radeon_llvm_calling_convention
{
39 RADEON_LLVM_AMDGPU_VS
= 87,
40 RADEON_LLVM_AMDGPU_GS
= 88,
41 RADEON_LLVM_AMDGPU_PS
= 89,
42 RADEON_LLVM_AMDGPU_CS
= 90,
43 RADEON_LLVM_AMDGPU_HS
= 93,
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 struct ac_nir_context
{
49 struct ac_llvm_context ac
;
50 struct ac_shader_abi
*abi
;
52 gl_shader_stage stage
;
54 struct hash_table
*defs
;
55 struct hash_table
*phis
;
56 struct hash_table
*vars
;
58 LLVMValueRef main_function
;
59 LLVMBasicBlockRef continue_block
;
60 LLVMBasicBlockRef break_block
;
66 struct radv_shader_context
{
67 struct ac_llvm_context ac
;
68 const struct ac_nir_compiler_options
*options
;
69 struct ac_shader_variant_info
*shader_info
;
70 struct ac_shader_abi abi
;
72 unsigned max_workgroup_size
;
73 LLVMContextRef context
;
74 LLVMValueRef main_function
;
76 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
77 LLVMValueRef ring_offsets
;
79 LLVMValueRef vertex_buffers
;
80 LLVMValueRef rel_auto_id
;
81 LLVMValueRef vs_prim_id
;
82 LLVMValueRef ls_out_layout
;
83 LLVMValueRef es2gs_offset
;
85 LLVMValueRef tcs_offchip_layout
;
86 LLVMValueRef tcs_out_offsets
;
87 LLVMValueRef tcs_out_layout
;
88 LLVMValueRef tcs_in_layout
;
90 LLVMValueRef merged_wave_info
;
91 LLVMValueRef tess_factor_offset
;
92 LLVMValueRef tes_rel_patch_id
;
96 LLVMValueRef gsvs_ring_stride
;
97 LLVMValueRef gsvs_num_entries
;
98 LLVMValueRef gs2vs_offset
;
99 LLVMValueRef gs_wave_id
;
100 LLVMValueRef gs_vtx_offset
[6];
102 LLVMValueRef esgs_ring
;
103 LLVMValueRef gsvs_ring
;
104 LLVMValueRef hs_ring_tess_offchip
;
105 LLVMValueRef hs_ring_tess_factor
;
107 LLVMValueRef sample_pos_offset
;
108 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
109 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
111 gl_shader_stage stage
;
113 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
116 uint64_t output_mask
;
117 uint8_t num_output_clips
;
118 uint8_t num_output_culls
;
120 bool is_gs_copy_shader
;
121 LLVMValueRef gs_next_vertex
;
122 unsigned gs_max_out_vertices
;
124 unsigned tes_primitive_mode
;
125 uint64_t tess_outputs_written
;
126 uint64_t tess_patch_outputs_written
;
128 uint32_t tcs_patch_outputs_read
;
129 uint64_t tcs_outputs_read
;
130 uint32_t tcs_vertices_per_patch
;
133 static inline struct radv_shader_context
*
134 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
136 struct radv_shader_context
*ctx
= NULL
;
137 return container_of(abi
, ctx
, abi
);
140 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
141 const nir_deref_var
*deref
,
142 enum ac_descriptor_type desc_type
,
143 const nir_tex_instr
*instr
,
144 bool image
, bool write
);
146 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
148 return (index
* 4) + chan
;
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
153 /* handle patch indices separate */
154 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
156 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
158 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
159 return 2 + (slot
- VARYING_SLOT_PATCH0
);
161 if (slot
== VARYING_SLOT_POS
)
163 if (slot
== VARYING_SLOT_PSIZ
)
165 if (slot
== VARYING_SLOT_CLIP_DIST0
)
167 /* 3 is reserved for clip dist as well */
168 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
169 return 4 + (slot
- VARYING_SLOT_VAR0
);
170 unreachable("illegal slot in get unique index\n");
173 static void set_llvm_calling_convention(LLVMValueRef func
,
174 gl_shader_stage stage
)
176 enum radeon_llvm_calling_convention calling_conv
;
179 case MESA_SHADER_VERTEX
:
180 case MESA_SHADER_TESS_EVAL
:
181 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
183 case MESA_SHADER_GEOMETRY
:
184 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
186 case MESA_SHADER_TESS_CTRL
:
187 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
189 case MESA_SHADER_FRAGMENT
:
190 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
192 case MESA_SHADER_COMPUTE
:
193 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
196 unreachable("Unhandle shader type");
199 LLVMSetFunctionCallConv(func
, calling_conv
);
204 LLVMTypeRef types
[MAX_ARGS
];
205 LLVMValueRef
*assign
[MAX_ARGS
];
206 unsigned array_params_mask
;
209 uint8_t num_sgprs_used
;
210 uint8_t num_vgprs_used
;
213 enum ac_arg_regfile
{
219 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
220 LLVMValueRef
*param_ptr
)
222 assert(info
->count
< MAX_ARGS
);
224 info
->assign
[info
->count
] = param_ptr
;
225 info
->types
[info
->count
] = type
;
228 if (regfile
== ARG_SGPR
) {
229 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
232 assert(regfile
== ARG_VGPR
);
233 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
238 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
240 info
->array_params_mask
|= (1 << info
->count
);
241 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
244 static void assign_arguments(LLVMValueRef main_function
,
245 struct arg_info
*info
)
248 for (i
= 0; i
< info
->count
; i
++) {
250 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
255 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
256 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
257 unsigned num_return_elems
,
258 struct arg_info
*args
,
259 unsigned max_workgroup_size
,
262 LLVMTypeRef main_function_type
, ret_type
;
263 LLVMBasicBlockRef main_function_body
;
265 if (num_return_elems
)
266 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
267 num_return_elems
, true);
269 ret_type
= LLVMVoidTypeInContext(ctx
);
271 /* Setup the function */
273 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
274 LLVMValueRef main_function
=
275 LLVMAddFunction(module
, "main", main_function_type
);
277 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
278 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
280 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
281 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
282 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
284 if (args
->array_params_mask
& (1 << i
)) {
285 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
286 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
287 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
291 if (max_workgroup_size
) {
292 ac_llvm_add_target_dep_function_attr(main_function
,
293 "amdgpu-max-work-group-size",
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function
,
299 "less-precise-fpmad",
301 LLVMAddTargetDependentFunctionAttr(main_function
,
304 LLVMAddTargetDependentFunctionAttr(main_function
,
307 LLVMAddTargetDependentFunctionAttr(main_function
,
310 LLVMAddTargetDependentFunctionAttr(main_function
,
311 "no-signed-zeros-fp-math",
314 return main_function
;
317 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
319 switch (ctx
->stage
) {
320 case MESA_SHADER_TESS_CTRL
:
321 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
322 case MESA_SHADER_TESS_EVAL
:
323 return ctx
->tes_rel_patch_id
;
326 unreachable("Illegal stage");
330 /* Tessellation shaders pass outputs to the next shader using LDS.
332 * LS outputs = TCS inputs
333 * TCS outputs = TES inputs
336 * - TCS inputs for patch 0
337 * - TCS inputs for patch 1
338 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
340 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
341 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
342 * - TCS outputs for patch 1
343 * - Per-patch TCS outputs for patch 1
344 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
345 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
348 * All three shaders VS(LS), TCS, TES share the same LDS space.
351 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
353 if (ctx
->stage
== MESA_SHADER_VERTEX
)
354 return ac_unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
355 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
356 return ac_unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
364 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
366 return ac_unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
370 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
372 return ac_unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
376 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
378 return LLVMBuildMul(ctx
->ac
.builder
,
379 ac_unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
380 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
384 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
386 return LLVMBuildMul(ctx
->ac
.builder
,
387 ac_unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
388 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
392 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
394 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
395 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
397 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
401 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
403 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
404 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
405 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
407 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_offset
,
408 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
414 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
416 LLVMValueRef patch0_patch_data_offset
=
417 get_tcs_out_patch0_patch_data_offset(ctx
);
418 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
419 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
421 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_patch_data_offset
,
422 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
428 set_loc(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
,
429 uint32_t indirect_offset
)
431 ud_info
->sgpr_idx
= *sgpr_idx
;
432 ud_info
->num_sgprs
= num_sgprs
;
433 ud_info
->indirect
= indirect_offset
> 0;
434 ud_info
->indirect_offset
= indirect_offset
;
435 *sgpr_idx
+= num_sgprs
;
439 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
442 struct ac_userdata_info
*ud_info
=
443 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
446 set_loc(ud_info
, sgpr_idx
, num_sgprs
, 0);
450 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
451 uint32_t indirect_offset
)
453 struct ac_userdata_info
*ud_info
=
454 &ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[idx
];
457 set_loc(ud_info
, sgpr_idx
, 2, indirect_offset
);
460 struct user_sgpr_info
{
461 bool need_ring_offsets
;
463 bool indirect_all_descriptor_sets
;
466 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
467 gl_shader_stage stage
)
470 case MESA_SHADER_VERTEX
:
471 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
472 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
475 case MESA_SHADER_TESS_EVAL
:
476 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
479 case MESA_SHADER_GEOMETRY
:
480 case MESA_SHADER_TESS_CTRL
:
481 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
491 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
495 count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
496 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
501 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
502 gl_shader_stage stage
,
503 bool has_previous_stage
,
504 gl_shader_stage previous_stage
,
505 bool needs_view_index
,
506 struct user_sgpr_info
*user_sgpr_info
)
508 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
510 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
511 if (stage
== MESA_SHADER_GEOMETRY
||
512 stage
== MESA_SHADER_VERTEX
||
513 stage
== MESA_SHADER_TESS_CTRL
||
514 stage
== MESA_SHADER_TESS_EVAL
||
515 ctx
->is_gs_copy_shader
)
516 user_sgpr_info
->need_ring_offsets
= true;
518 if (stage
== MESA_SHADER_FRAGMENT
&&
519 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
520 user_sgpr_info
->need_ring_offsets
= true;
522 /* 2 user sgprs will nearly always be allocated for scratch/rings */
523 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
524 user_sgpr_info
->sgpr_count
+= 2;
528 case MESA_SHADER_COMPUTE
:
529 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
530 user_sgpr_info
->sgpr_count
+= 3;
532 case MESA_SHADER_FRAGMENT
:
533 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
535 case MESA_SHADER_VERTEX
:
536 if (!ctx
->is_gs_copy_shader
)
537 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
538 if (ctx
->options
->key
.vs
.as_ls
)
539 user_sgpr_info
->sgpr_count
++;
541 case MESA_SHADER_TESS_CTRL
:
542 if (has_previous_stage
) {
543 if (previous_stage
== MESA_SHADER_VERTEX
)
544 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
545 user_sgpr_info
->sgpr_count
++;
547 user_sgpr_info
->sgpr_count
+= 4;
549 case MESA_SHADER_TESS_EVAL
:
550 user_sgpr_info
->sgpr_count
+= 1;
552 case MESA_SHADER_GEOMETRY
:
553 if (has_previous_stage
) {
554 if (previous_stage
== MESA_SHADER_VERTEX
) {
555 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
557 user_sgpr_info
->sgpr_count
++;
560 user_sgpr_info
->sgpr_count
+= 2;
566 if (needs_view_index
)
567 user_sgpr_info
->sgpr_count
++;
569 if (ctx
->shader_info
->info
.loads_push_constants
)
570 user_sgpr_info
->sgpr_count
+= 2;
572 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
? 32 : 16;
573 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_info
->sgpr_count
;
575 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
576 user_sgpr_info
->sgpr_count
+= 2;
577 user_sgpr_info
->indirect_all_descriptor_sets
= true;
579 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
584 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
585 gl_shader_stage stage
,
586 bool has_previous_stage
,
587 gl_shader_stage previous_stage
,
588 const struct user_sgpr_info
*user_sgpr_info
,
589 struct arg_info
*args
,
590 LLVMValueRef
*desc_sets
)
592 LLVMTypeRef type
= ac_array_in_const_addr_space(ctx
->ac
.i8
);
593 unsigned num_sets
= ctx
->options
->layout
?
594 ctx
->options
->layout
->num_sets
: 0;
595 unsigned stage_mask
= 1 << stage
;
597 if (has_previous_stage
)
598 stage_mask
|= 1 << previous_stage
;
600 /* 1 for each descriptor set */
601 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
602 for (unsigned i
= 0; i
< num_sets
; ++i
) {
603 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
604 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
605 add_array_arg(args
, type
,
606 &ctx
->descriptor_sets
[i
]);
610 add_array_arg(args
, ac_array_in_const_addr_space(type
), desc_sets
);
613 if (ctx
->shader_info
->info
.loads_push_constants
) {
614 /* 1 for push constants and dynamic descriptors */
615 add_array_arg(args
, type
, &ctx
->abi
.push_constants
);
620 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
621 gl_shader_stage stage
,
622 bool has_previous_stage
,
623 gl_shader_stage previous_stage
,
624 struct arg_info
*args
)
626 if (!ctx
->is_gs_copy_shader
&&
627 (stage
== MESA_SHADER_VERTEX
||
628 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
629 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
630 add_arg(args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
631 &ctx
->vertex_buffers
);
633 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
634 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
635 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
636 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
642 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
644 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
645 if (!ctx
->is_gs_copy_shader
) {
646 if (ctx
->options
->key
.vs
.as_ls
) {
647 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
648 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
650 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
651 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
653 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
658 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
660 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
661 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
662 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
663 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
667 set_global_input_locs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
668 bool has_previous_stage
, gl_shader_stage previous_stage
,
669 const struct user_sgpr_info
*user_sgpr_info
,
670 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
672 unsigned num_sets
= ctx
->options
->layout
?
673 ctx
->options
->layout
->num_sets
: 0;
674 unsigned stage_mask
= 1 << stage
;
676 if (has_previous_stage
)
677 stage_mask
|= 1 << previous_stage
;
679 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
680 for (unsigned i
= 0; i
< num_sets
; ++i
) {
681 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
682 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
683 set_loc_desc(ctx
, i
, user_sgpr_idx
, 0);
685 ctx
->descriptor_sets
[i
] = NULL
;
688 set_loc_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
691 for (unsigned i
= 0; i
< num_sets
; ++i
) {
692 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
693 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
694 set_loc_desc(ctx
, i
, user_sgpr_idx
, i
* 8);
695 ctx
->descriptor_sets
[i
] =
696 ac_build_load_to_sgpr(&ctx
->ac
,
698 LLVMConstInt(ctx
->ac
.i32
, i
, false));
701 ctx
->descriptor_sets
[i
] = NULL
;
703 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
706 if (ctx
->shader_info
->info
.loads_push_constants
) {
707 set_loc_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
712 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
713 gl_shader_stage stage
, bool has_previous_stage
,
714 gl_shader_stage previous_stage
,
715 uint8_t *user_sgpr_idx
)
717 if (!ctx
->is_gs_copy_shader
&&
718 (stage
== MESA_SHADER_VERTEX
||
719 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
720 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
721 set_loc_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
726 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
729 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
730 user_sgpr_idx
, vs_num
);
734 static void create_function(struct radv_shader_context
*ctx
,
735 gl_shader_stage stage
,
736 bool has_previous_stage
,
737 gl_shader_stage previous_stage
)
739 uint8_t user_sgpr_idx
;
740 struct user_sgpr_info user_sgpr_info
;
741 struct arg_info args
= {};
742 LLVMValueRef desc_sets
;
743 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
744 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
745 previous_stage
, needs_view_index
, &user_sgpr_info
);
747 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
748 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
753 case MESA_SHADER_COMPUTE
:
754 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
755 previous_stage
, &user_sgpr_info
,
758 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
759 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
760 &ctx
->abi
.num_work_groups
);
763 for (int i
= 0; i
< 3; i
++) {
764 ctx
->abi
.workgroup_ids
[i
] = NULL
;
765 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
766 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
767 &ctx
->abi
.workgroup_ids
[i
]);
771 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
772 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
773 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
774 &ctx
->abi
.local_invocation_ids
);
776 case MESA_SHADER_VERTEX
:
777 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
778 previous_stage
, &user_sgpr_info
,
780 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
781 previous_stage
, &args
);
783 if (needs_view_index
)
784 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
785 &ctx
->abi
.view_index
);
786 if (ctx
->options
->key
.vs
.as_es
)
787 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
789 else if (ctx
->options
->key
.vs
.as_ls
)
790 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
791 &ctx
->ls_out_layout
);
793 declare_vs_input_vgprs(ctx
, &args
);
795 case MESA_SHADER_TESS_CTRL
:
796 if (has_previous_stage
) {
797 // First 6 system regs
798 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
799 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
800 &ctx
->merged_wave_info
);
801 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
802 &ctx
->tess_factor_offset
);
804 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
805 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
806 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
808 declare_global_input_sgprs(ctx
, stage
,
811 &user_sgpr_info
, &args
,
813 declare_vs_specific_input_sgprs(ctx
, stage
,
815 previous_stage
, &args
);
817 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
818 &ctx
->ls_out_layout
);
820 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
821 &ctx
->tcs_offchip_layout
);
822 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
823 &ctx
->tcs_out_offsets
);
824 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
825 &ctx
->tcs_out_layout
);
826 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
827 &ctx
->tcs_in_layout
);
828 if (needs_view_index
)
829 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
830 &ctx
->abi
.view_index
);
832 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
833 &ctx
->abi
.tcs_patch_id
);
834 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
835 &ctx
->abi
.tcs_rel_ids
);
837 declare_vs_input_vgprs(ctx
, &args
);
839 declare_global_input_sgprs(ctx
, stage
,
842 &user_sgpr_info
, &args
,
845 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
846 &ctx
->tcs_offchip_layout
);
847 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
848 &ctx
->tcs_out_offsets
);
849 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
850 &ctx
->tcs_out_layout
);
851 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
852 &ctx
->tcs_in_layout
);
853 if (needs_view_index
)
854 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
855 &ctx
->abi
.view_index
);
857 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
858 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
859 &ctx
->tess_factor_offset
);
860 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
861 &ctx
->abi
.tcs_patch_id
);
862 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
863 &ctx
->abi
.tcs_rel_ids
);
866 case MESA_SHADER_TESS_EVAL
:
867 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
868 previous_stage
, &user_sgpr_info
,
871 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
);
872 if (needs_view_index
)
873 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
874 &ctx
->abi
.view_index
);
876 if (ctx
->options
->key
.tes
.as_es
) {
877 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
878 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
879 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
882 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
883 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
885 declare_tes_input_vgprs(ctx
, &args
);
887 case MESA_SHADER_GEOMETRY
:
888 if (has_previous_stage
) {
889 // First 6 system regs
890 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
892 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
893 &ctx
->merged_wave_info
);
894 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
896 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
897 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
898 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
900 declare_global_input_sgprs(ctx
, stage
,
903 &user_sgpr_info
, &args
,
906 if (previous_stage
== MESA_SHADER_TESS_EVAL
) {
907 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
908 &ctx
->tcs_offchip_layout
);
910 declare_vs_specific_input_sgprs(ctx
, stage
,
916 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
917 &ctx
->gsvs_ring_stride
);
918 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
919 &ctx
->gsvs_num_entries
);
920 if (needs_view_index
)
921 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
922 &ctx
->abi
.view_index
);
924 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
925 &ctx
->gs_vtx_offset
[0]);
926 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
927 &ctx
->gs_vtx_offset
[2]);
928 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
929 &ctx
->abi
.gs_prim_id
);
930 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
931 &ctx
->abi
.gs_invocation_id
);
932 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
933 &ctx
->gs_vtx_offset
[4]);
935 if (previous_stage
== MESA_SHADER_VERTEX
) {
936 declare_vs_input_vgprs(ctx
, &args
);
938 declare_tes_input_vgprs(ctx
, &args
);
941 declare_global_input_sgprs(ctx
, stage
,
944 &user_sgpr_info
, &args
,
947 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
948 &ctx
->gsvs_ring_stride
);
949 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
950 &ctx
->gsvs_num_entries
);
951 if (needs_view_index
)
952 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
953 &ctx
->abi
.view_index
);
955 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
956 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
957 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
958 &ctx
->gs_vtx_offset
[0]);
959 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
960 &ctx
->gs_vtx_offset
[1]);
961 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
962 &ctx
->abi
.gs_prim_id
);
963 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
964 &ctx
->gs_vtx_offset
[2]);
965 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
966 &ctx
->gs_vtx_offset
[3]);
967 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
968 &ctx
->gs_vtx_offset
[4]);
969 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
970 &ctx
->gs_vtx_offset
[5]);
971 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
972 &ctx
->abi
.gs_invocation_id
);
975 case MESA_SHADER_FRAGMENT
:
976 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
977 previous_stage
, &user_sgpr_info
,
980 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
981 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
982 &ctx
->sample_pos_offset
);
984 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
985 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
986 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
987 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
988 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
989 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
990 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
991 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
992 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
993 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
994 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
995 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
996 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
997 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
998 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
999 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1000 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1003 unreachable("Shader stage not implemented");
1006 ctx
->main_function
= create_llvm_function(
1007 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1008 ctx
->max_workgroup_size
,
1009 ctx
->options
->unsafe_math
);
1010 set_llvm_calling_convention(ctx
->main_function
, stage
);
1013 ctx
->shader_info
->num_input_vgprs
= 0;
1014 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1016 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1018 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1019 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1021 assign_arguments(ctx
->main_function
, &args
);
1025 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1026 set_loc_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1028 if (ctx
->options
->supports_spill
) {
1029 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1030 LLVMPointerType(ctx
->ac
.i8
, AC_CONST_ADDR_SPACE
),
1031 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1032 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1033 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1037 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1038 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1039 if (has_previous_stage
)
1042 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1043 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1046 case MESA_SHADER_COMPUTE
:
1047 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1048 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1052 case MESA_SHADER_VERTEX
:
1053 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1054 previous_stage
, &user_sgpr_idx
);
1055 if (ctx
->abi
.view_index
)
1056 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1057 if (ctx
->options
->key
.vs
.as_ls
) {
1058 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1062 case MESA_SHADER_TESS_CTRL
:
1063 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1064 previous_stage
, &user_sgpr_idx
);
1065 if (has_previous_stage
)
1066 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1068 set_loc_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
1069 if (ctx
->abi
.view_index
)
1070 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1072 case MESA_SHADER_TESS_EVAL
:
1073 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
1074 if (ctx
->abi
.view_index
)
1075 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1077 case MESA_SHADER_GEOMETRY
:
1078 if (has_previous_stage
) {
1079 if (previous_stage
== MESA_SHADER_VERTEX
)
1080 set_vs_specific_input_locs(ctx
, stage
,
1085 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
,
1088 set_loc_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
,
1090 if (ctx
->abi
.view_index
)
1091 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1093 case MESA_SHADER_FRAGMENT
:
1094 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1095 set_loc_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
,
1100 unreachable("Shader stage not implemented");
1103 if (stage
== MESA_SHADER_TESS_CTRL
||
1104 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_ls
) ||
1105 /* GFX9 has the ESGS ring buffer in LDS. */
1106 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1107 ac_declare_lds_as_pointer(&ctx
->ac
);
1110 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1114 build_store_values_extended(struct ac_llvm_context
*ac
,
1115 LLVMValueRef
*values
,
1116 unsigned value_count
,
1117 unsigned value_stride
,
1120 LLVMBuilderRef builder
= ac
->builder
;
1123 for (i
= 0; i
< value_count
; i
++) {
1124 LLVMValueRef ptr
= values
[i
* value_stride
];
1125 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1126 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1127 LLVMBuildStore(builder
, value
, ptr
);
1131 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1132 const nir_ssa_def
*def
)
1134 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1135 if (def
->num_components
> 1) {
1136 type
= LLVMVectorType(type
, def
->num_components
);
1141 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1144 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1145 return (LLVMValueRef
)entry
->data
;
1149 get_memory_ptr(struct ac_nir_context
*ctx
, nir_src src
)
1151 LLVMValueRef ptr
= get_src(ctx
, src
);
1152 ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ac
.lds
, &ptr
, 1, "");
1153 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
1155 return LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1156 LLVMPointerType(ctx
->ac
.i32
, addr_space
), "");
1159 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1160 const struct nir_block
*b
)
1162 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1163 return (LLVMBasicBlockRef
)entry
->data
;
1166 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1168 unsigned num_components
)
1170 LLVMValueRef value
= get_src(ctx
, src
.src
);
1171 bool need_swizzle
= false;
1174 unsigned src_components
= ac_get_llvm_num_components(value
);
1175 for (unsigned i
= 0; i
< num_components
; ++i
) {
1176 assert(src
.swizzle
[i
] < src_components
);
1177 if (src
.swizzle
[i
] != i
)
1178 need_swizzle
= true;
1181 if (need_swizzle
|| num_components
!= src_components
) {
1182 LLVMValueRef masks
[] = {
1183 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1184 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1185 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1186 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1188 if (src_components
> 1 && num_components
== 1) {
1189 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1191 } else if (src_components
== 1 && num_components
> 1) {
1192 LLVMValueRef values
[] = {value
, value
, value
, value
};
1193 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1195 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1196 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1200 assert(!src
.negate
);
1205 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1206 LLVMIntPredicate pred
, LLVMValueRef src0
,
1209 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1210 return LLVMBuildSelect(ctx
->builder
, result
,
1211 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1215 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1216 LLVMRealPredicate pred
, LLVMValueRef src0
,
1219 LLVMValueRef result
;
1220 src0
= ac_to_float(ctx
, src0
);
1221 src1
= ac_to_float(ctx
, src1
);
1222 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1223 return LLVMBuildSelect(ctx
->builder
, result
,
1224 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1228 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1230 LLVMTypeRef result_type
,
1234 LLVMValueRef params
[] = {
1235 ac_to_float(ctx
, src0
),
1238 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1239 ac_get_elem_bits(ctx
, result_type
));
1240 assert(length
< sizeof(name
));
1241 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1244 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1246 LLVMTypeRef result_type
,
1247 LLVMValueRef src0
, LLVMValueRef src1
)
1250 LLVMValueRef params
[] = {
1251 ac_to_float(ctx
, src0
),
1252 ac_to_float(ctx
, src1
),
1255 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1256 ac_get_elem_bits(ctx
, result_type
));
1257 assert(length
< sizeof(name
));
1258 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1261 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1263 LLVMTypeRef result_type
,
1264 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1267 LLVMValueRef params
[] = {
1268 ac_to_float(ctx
, src0
),
1269 ac_to_float(ctx
, src1
),
1270 ac_to_float(ctx
, src2
),
1273 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1274 ac_get_elem_bits(ctx
, result_type
));
1275 assert(length
< sizeof(name
));
1276 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1279 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1280 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1282 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1284 return LLVMBuildSelect(ctx
->builder
, v
, ac_to_integer(ctx
, src1
),
1285 ac_to_integer(ctx
, src2
), "");
1288 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1289 LLVMIntPredicate pred
,
1290 LLVMValueRef src0
, LLVMValueRef src1
)
1292 return LLVMBuildSelect(ctx
->builder
,
1293 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1298 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1301 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1302 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1305 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1307 LLVMValueRef src0
, LLVMValueRef src1
)
1309 LLVMTypeRef ret_type
;
1310 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1312 LLVMValueRef params
[] = { src0
, src1
};
1313 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1316 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1317 params
, 2, AC_FUNC_ATTR_READNONE
);
1319 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1320 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1324 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1327 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1330 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1333 src0
= ac_to_float(ctx
, src0
);
1334 LLVMValueRef zero
= LLVMConstNull(LLVMTypeOf(src0
));
1335 return LLVMBuildSExt(ctx
->builder
,
1336 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, zero
, ""),
1340 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1344 LLVMValueRef result
= LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1349 return LLVMBuildZExt(ctx
->builder
, result
, ctx
->i64
, "");
1352 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1355 LLVMValueRef zero
= LLVMConstNull(LLVMTypeOf(src0
));
1356 return LLVMBuildSExt(ctx
->builder
,
1357 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, zero
, ""),
1361 static LLVMValueRef
emit_f2f16(struct ac_llvm_context
*ctx
,
1364 LLVMValueRef result
;
1365 LLVMValueRef cond
= NULL
;
1367 src0
= ac_to_float(ctx
, src0
);
1368 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->f16
, "");
1370 if (ctx
->chip_class
>= VI
) {
1371 LLVMValueRef args
[2];
1372 /* Check if the result is a denormal - and flush to 0 if so. */
1374 args
[1] = LLVMConstInt(ctx
->i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1375 cond
= ac_build_intrinsic(ctx
, "llvm.amdgcn.class.f16", ctx
->i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1378 /* need to convert back up to f32 */
1379 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->f32
, "");
1381 if (ctx
->chip_class
>= VI
)
1382 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->f32_0
, result
, "");
1385 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1386 * so compare the result and flush to 0 if it's smaller.
1388 LLVMValueRef temp
, cond2
;
1389 temp
= emit_intrin_1f_param(ctx
, "llvm.fabs", ctx
->f32
, result
);
1390 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1391 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->i32
, 0x38800000, false), ctx
->f32
, ""),
1393 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1394 temp
, ctx
->f32_0
, "");
1395 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1396 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->f32_0
, result
, "");
1401 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1402 LLVMValueRef src0
, LLVMValueRef src1
)
1404 LLVMValueRef dst64
, result
;
1405 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1406 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1408 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1409 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1410 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1414 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1415 LLVMValueRef src0
, LLVMValueRef src1
)
1417 LLVMValueRef dst64
, result
;
1418 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1419 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1421 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1422 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1423 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1427 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1429 const LLVMValueRef srcs
[3])
1431 LLVMValueRef result
;
1432 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1434 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1435 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1439 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1440 LLVMValueRef src0
, LLVMValueRef src1
,
1441 LLVMValueRef src2
, LLVMValueRef src3
)
1443 LLVMValueRef bfi_args
[3], result
;
1445 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1446 LLVMBuildSub(ctx
->builder
,
1447 LLVMBuildShl(ctx
->builder
,
1452 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1455 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1458 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1459 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1461 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1462 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1463 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1465 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1469 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1472 LLVMValueRef comp
[2];
1474 src0
= ac_to_float(ctx
, src0
);
1475 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1476 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1478 return ac_build_cvt_pkrtz_f16(ctx
, comp
);
1481 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1484 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1485 LLVMValueRef temps
[2], result
, val
;
1488 for (i
= 0; i
< 2; i
++) {
1489 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1490 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1491 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1492 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1495 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), temps
[0],
1497 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1502 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1508 LLVMValueRef result
;
1510 if (op
== nir_op_fddx_fine
)
1511 mask
= AC_TID_MASK_LEFT
;
1512 else if (op
== nir_op_fddy_fine
)
1513 mask
= AC_TID_MASK_TOP
;
1515 mask
= AC_TID_MASK_TOP_LEFT
;
1517 /* for DDX we want to next X pixel, DDY next Y pixel. */
1518 if (op
== nir_op_fddx_fine
||
1519 op
== nir_op_fddx_coarse
||
1525 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1530 * this takes an I,J coordinate pair,
1531 * and works out the X and Y derivatives.
1532 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1534 static LLVMValueRef
emit_ddxy_interp(
1535 struct ac_nir_context
*ctx
,
1536 LLVMValueRef interp_ij
)
1538 LLVMValueRef result
[4], a
;
1541 for (i
= 0; i
< 2; i
++) {
1542 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1543 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1544 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1545 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1547 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1550 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1552 LLVMValueRef src
[4], result
= NULL
;
1553 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1554 unsigned src_components
;
1555 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1557 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1558 switch (instr
->op
) {
1564 case nir_op_pack_half_2x16
:
1567 case nir_op_unpack_half_2x16
:
1570 case nir_op_cube_face_coord
:
1571 case nir_op_cube_face_index
:
1575 src_components
= num_components
;
1578 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1579 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1581 switch (instr
->op
) {
1587 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1588 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1591 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1594 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1597 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1600 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1601 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1602 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1605 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1606 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1607 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1610 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1613 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1616 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1619 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1622 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1623 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1624 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1625 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1626 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1627 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1628 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1631 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1632 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1633 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1636 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1639 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1642 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1645 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1646 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1647 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1650 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1651 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1655 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1658 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1661 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1664 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1665 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1666 LLVMTypeOf(src
[0]), ""),
1670 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1671 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1672 LLVMTypeOf(src
[0]), ""),
1676 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1677 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1678 LLVMTypeOf(src
[0]), ""),
1682 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1685 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1688 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1691 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1694 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1697 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1700 result
= emit_float_cmp(&ctx
->ac
, LLVMRealOEQ
, src
[0], src
[1]);
1703 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1706 result
= emit_float_cmp(&ctx
->ac
, LLVMRealOLT
, src
[0], src
[1]);
1709 result
= emit_float_cmp(&ctx
->ac
, LLVMRealOGE
, src
[0], src
[1]);
1712 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1713 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1716 result
= emit_iabs(&ctx
->ac
, src
[0]);
1719 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1722 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1725 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1728 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1731 result
= ac_build_isign(&ctx
->ac
, src
[0],
1732 instr
->dest
.dest
.ssa
.bit_size
);
1735 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1736 result
= ac_build_fsign(&ctx
->ac
, src
[0],
1737 instr
->dest
.dest
.ssa
.bit_size
);
1740 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1741 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1744 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1745 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1748 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1749 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1751 case nir_op_fround_even
:
1752 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1753 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1756 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1757 result
= ac_build_fract(&ctx
->ac
, src
[0],
1758 instr
->dest
.dest
.ssa
.bit_size
);
1761 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1762 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1765 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1766 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1769 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1770 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1773 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1774 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1777 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1778 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1781 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1782 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1783 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1787 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1788 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1789 if (ctx
->ac
.chip_class
< GFX9
&&
1790 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1791 /* Only pre-GFX9 chips do not flush denorms. */
1792 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1793 ac_to_float_type(&ctx
->ac
, def_type
),
1798 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1799 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1800 if (ctx
->ac
.chip_class
< GFX9
&&
1801 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1802 /* Only pre-GFX9 chips do not flush denorms. */
1803 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1804 ac_to_float_type(&ctx
->ac
, def_type
),
1809 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1810 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1813 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1814 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) == 32)
1815 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ldexp.f32", ctx
->ac
.f32
, src
, 2, AC_FUNC_ATTR_READNONE
);
1817 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ldexp.f64", ctx
->ac
.f64
, src
, 2, AC_FUNC_ATTR_READNONE
);
1819 case nir_op_ibitfield_extract
:
1820 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1822 case nir_op_ubitfield_extract
:
1823 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1825 case nir_op_bitfield_insert
:
1826 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1828 case nir_op_bitfield_reverse
:
1829 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1831 case nir_op_bit_count
:
1832 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) == 32)
1833 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1835 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i64", ctx
->ac
.i64
, src
, 1, AC_FUNC_ATTR_READNONE
);
1836 result
= LLVMBuildTrunc(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
1842 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1843 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1844 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1848 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1849 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1853 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1854 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1858 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1859 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1863 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1864 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1867 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1868 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1871 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1872 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1876 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1877 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < ac_get_elem_bits(&ctx
->ac
, def_type
))
1878 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1880 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1884 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1885 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < ac_get_elem_bits(&ctx
->ac
, def_type
))
1886 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1888 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1891 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1893 case nir_op_find_lsb
:
1894 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1895 result
= ac_find_lsb(&ctx
->ac
, ctx
->ac
.i32
, src
[0]);
1897 case nir_op_ufind_msb
:
1898 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1899 result
= ac_build_umsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1901 case nir_op_ifind_msb
:
1902 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1903 result
= ac_build_imsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1905 case nir_op_uadd_carry
:
1906 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1907 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1908 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
1910 case nir_op_usub_borrow
:
1911 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1912 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1913 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
1916 result
= emit_b2f(&ctx
->ac
, src
[0]);
1919 result
= emit_f2b(&ctx
->ac
, src
[0]);
1922 result
= emit_b2i(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1925 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1926 result
= emit_i2b(&ctx
->ac
, src
[0]);
1928 case nir_op_fquantize2f16
:
1929 result
= emit_f2f16(&ctx
->ac
, src
[0]);
1931 case nir_op_umul_high
:
1932 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1933 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1934 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
1936 case nir_op_imul_high
:
1937 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1938 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1939 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
1941 case nir_op_pack_half_2x16
:
1942 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
1944 case nir_op_unpack_half_2x16
:
1945 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
1949 case nir_op_fddx_fine
:
1950 case nir_op_fddy_fine
:
1951 case nir_op_fddx_coarse
:
1952 case nir_op_fddy_coarse
:
1953 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
1956 case nir_op_unpack_64_2x32_split_x
: {
1957 assert(ac_get_llvm_num_components(src
[0]) == 1);
1958 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
1961 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
1966 case nir_op_unpack_64_2x32_split_y
: {
1967 assert(ac_get_llvm_num_components(src
[0]) == 1);
1968 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
1971 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
1976 case nir_op_pack_64_2x32_split
: {
1977 LLVMValueRef tmp
= LLVMGetUndef(ctx
->ac
.v2i32
);
1978 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
1979 src
[0], ctx
->ac
.i32_0
, "");
1980 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
1981 src
[1], ctx
->ac
.i32_1
, "");
1982 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
1986 case nir_op_cube_face_coord
: {
1987 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1988 LLVMValueRef results
[2];
1990 for (unsigned chan
= 0; chan
< 3; chan
++)
1991 in
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src
[0], chan
);
1992 results
[0] = ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.cubetc",
1993 ctx
->ac
.f32
, in
, 3, AC_FUNC_ATTR_READNONE
);
1994 results
[1] = ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.cubesc",
1995 ctx
->ac
.f32
, in
, 3, AC_FUNC_ATTR_READNONE
);
1996 result
= ac_build_gather_values(&ctx
->ac
, results
, 2);
2000 case nir_op_cube_face_index
: {
2001 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
2003 for (unsigned chan
= 0; chan
< 3; chan
++)
2004 in
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src
[0], chan
);
2005 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.cubeid",
2006 ctx
->ac
.f32
, in
, 3, AC_FUNC_ATTR_READNONE
);
2011 fprintf(stderr
, "Unknown NIR alu instr: ");
2012 nir_print_instr(&instr
->instr
, stderr
);
2013 fprintf(stderr
, "\n");
2018 assert(instr
->dest
.dest
.is_ssa
);
2019 result
= ac_to_integer(&ctx
->ac
, result
);
2020 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
2025 static void visit_load_const(struct ac_nir_context
*ctx
,
2026 const nir_load_const_instr
*instr
)
2028 LLVMValueRef values
[4], value
= NULL
;
2029 LLVMTypeRef element_type
=
2030 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
2032 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
2033 switch (instr
->def
.bit_size
) {
2035 values
[i
] = LLVMConstInt(element_type
,
2036 instr
->value
.u32
[i
], false);
2039 values
[i
] = LLVMConstInt(element_type
,
2040 instr
->value
.u64
[i
], false);
2044 "unsupported nir load_const bit_size: %d\n",
2045 instr
->def
.bit_size
);
2049 if (instr
->def
.num_components
> 1) {
2050 value
= LLVMConstVector(values
, instr
->def
.num_components
);
2054 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
2058 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
2061 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2062 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2065 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
2066 /* On VI, the descriptor contains the size in bytes,
2067 * but TXQ must return the size in elements.
2068 * The stride is always non-zero for resources using TXQ.
2070 LLVMValueRef stride
=
2071 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2073 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2074 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2075 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2076 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2078 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2084 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2087 static void build_int_type_name(
2089 char *buf
, unsigned bufsize
)
2091 assert(bufsize
>= 6);
2093 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2094 snprintf(buf
, bufsize
, "v%ui32",
2095 LLVMGetVectorSize(type
));
2100 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2101 struct ac_image_args
*args
,
2102 const nir_tex_instr
*instr
)
2104 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2105 LLVMValueRef coord
= args
->addr
;
2106 LLVMValueRef half_texel
[2];
2107 LLVMValueRef compare_cube_wa
= NULL
;
2108 LLVMValueRef result
;
2110 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2114 struct ac_image_args txq_args
= { 0 };
2116 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2117 txq_args
.opcode
= ac_image_get_resinfo
;
2118 txq_args
.dmask
= 0xf;
2119 txq_args
.addr
= ctx
->i32_0
;
2120 txq_args
.resource
= args
->resource
;
2121 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2123 for (c
= 0; c
< 2; c
++) {
2124 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2125 LLVMConstInt(ctx
->i32
, c
, false), "");
2126 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2127 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2128 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2129 LLVMConstReal(ctx
->f32
, -0.5), "");
2133 LLVMValueRef orig_coords
= args
->addr
;
2135 for (c
= 0; c
< 2; c
++) {
2137 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2138 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2139 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2140 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2141 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2142 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2147 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2148 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2149 * workaround by sampling using a scaled type and converting.
2150 * This is taken from amdgpu-pro shaders.
2152 /* NOTE this produces some ugly code compared to amdgpu-pro,
2153 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2154 * and then reads them back. -pro generates two selects,
2155 * one s_cmp for the descriptor rewriting
2156 * one v_cmp for the coordinate and result changes.
2158 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2159 LLVMValueRef tmp
, tmp2
;
2161 /* workaround 8/8/8/8 uint/sint cube gather bug */
2162 /* first detect it then change to a scaled read and f2i */
2163 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2166 /* extract the DATA_FORMAT */
2167 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2168 LLVMConstInt(ctx
->i32
, 6, false), false);
2170 /* is the DATA_FORMAT == 8_8_8_8 */
2171 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2173 if (stype
== GLSL_TYPE_UINT
)
2174 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2175 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2176 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2178 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2179 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2180 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2182 /* replace the NUM FORMAT in the descriptor */
2183 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2184 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2186 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2188 /* don't modify the coordinates for this case */
2189 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2192 result
= ac_build_image_opcode(ctx
, args
);
2194 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2195 LLVMValueRef tmp
, tmp2
;
2197 /* if the cube workaround is in place, f2i the result. */
2198 for (c
= 0; c
< 4; c
++) {
2199 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2200 if (stype
== GLSL_TYPE_UINT
)
2201 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2203 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2204 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2205 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2206 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2207 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2208 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2214 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2215 const nir_tex_instr
*instr
,
2217 struct ac_image_args
*args
)
2219 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2220 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
2222 return ac_build_buffer_load_format(&ctx
->ac
,
2226 util_last_bit(mask
),
2230 args
->opcode
= ac_image_sample
;
2231 args
->compare
= instr
->is_shadow
;
2233 switch (instr
->op
) {
2235 case nir_texop_txf_ms
:
2236 case nir_texop_samples_identical
:
2237 args
->opcode
= lod_is_zero
||
2238 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
?
2239 ac_image_load
: ac_image_load_mip
;
2240 args
->compare
= false;
2241 args
->offset
= false;
2248 args
->level_zero
= true;
2253 case nir_texop_query_levels
:
2254 args
->opcode
= ac_image_get_resinfo
;
2257 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2258 args
->level_zero
= true;
2264 args
->opcode
= ac_image_gather4
;
2265 args
->level_zero
= true;
2268 args
->opcode
= ac_image_get_lod
;
2269 args
->compare
= false;
2270 args
->offset
= false;
2276 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2277 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2278 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2279 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2282 return ac_build_image_opcode(&ctx
->ac
, args
);
2286 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
2287 unsigned desc_set
, unsigned binding
)
2289 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2290 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2291 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2292 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2293 unsigned base_offset
= layout
->binding
[binding
].offset
;
2294 LLVMValueRef offset
, stride
;
2296 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2297 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2298 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2299 layout
->binding
[binding
].dynamic_offset_offset
;
2300 desc_ptr
= ctx
->abi
.push_constants
;
2301 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2302 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2304 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
2306 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
2307 index
= LLVMBuildMul(ctx
->ac
.builder
, index
, stride
, "");
2308 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, index
, "");
2310 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2311 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
2312 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2317 static LLVMValueRef
visit_vulkan_resource_reindex(struct ac_nir_context
*ctx
,
2318 nir_intrinsic_instr
*instr
)
2320 LLVMValueRef ptr
= get_src(ctx
, instr
->src
[0]);
2321 LLVMValueRef index
= get_src(ctx
, instr
->src
[1]);
2323 LLVMValueRef result
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
2324 LLVMSetMetadata(result
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2328 static LLVMValueRef
visit_load_push_constant(struct ac_nir_context
*ctx
,
2329 nir_intrinsic_instr
*instr
)
2331 LLVMValueRef ptr
, addr
;
2333 addr
= LLVMConstInt(ctx
->ac
.i32
, nir_intrinsic_base(instr
), 0);
2334 addr
= LLVMBuildAdd(ctx
->ac
.builder
, addr
,
2335 get_src(ctx
, instr
->src
[0]), "");
2337 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->abi
->push_constants
, addr
);
2338 ptr
= ac_cast_ptr(&ctx
->ac
, ptr
, get_def_type(ctx
, &instr
->dest
.ssa
));
2340 return LLVMBuildLoad(ctx
->ac
.builder
, ptr
, "");
2343 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2344 const nir_intrinsic_instr
*instr
)
2346 LLVMValueRef index
= get_src(ctx
, instr
->src
[0]);
2348 return get_buffer_size(ctx
, ctx
->abi
->load_ssbo(ctx
->abi
, index
, false), false);
2351 static uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2353 uint32_t new_mask
= 0;
2354 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2355 if (mask
& (1u << i
))
2356 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2360 static LLVMValueRef
extract_vector_range(struct ac_llvm_context
*ctx
, LLVMValueRef src
,
2361 unsigned start
, unsigned count
)
2363 LLVMTypeRef type
= LLVMTypeOf(src
);
2365 if (LLVMGetTypeKind(type
) != LLVMVectorTypeKind
) {
2371 unsigned src_elements
= LLVMGetVectorSize(type
);
2372 assert(start
< src_elements
);
2373 assert(start
+ count
<= src_elements
);
2375 if (start
== 0 && count
== src_elements
)
2379 return LLVMBuildExtractElement(ctx
->builder
, src
, LLVMConstInt(ctx
->i32
, start
, false), "");
2382 LLVMValueRef indices
[8];
2383 for (unsigned i
= 0; i
< count
; ++i
)
2384 indices
[i
] = LLVMConstInt(ctx
->i32
, start
+ i
, false);
2386 LLVMValueRef swizzle
= LLVMConstVector(indices
, count
);
2387 return LLVMBuildShuffleVector(ctx
->builder
, src
, src
, swizzle
, "");
2390 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2391 nir_intrinsic_instr
*instr
)
2393 const char *store_name
;
2394 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2395 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2396 int elem_size_mult
= ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2397 int components_32bit
= elem_size_mult
* instr
->num_components
;
2398 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2399 LLVMValueRef base_data
, base_offset
;
2400 LLVMValueRef params
[6];
2402 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2403 get_src(ctx
, instr
->src
[1]), true);
2404 params
[2] = ctx
->ac
.i32_0
; /* vindex */
2405 params
[4] = ctx
->ac
.i1false
; /* glc */
2406 params
[5] = ctx
->ac
.i1false
; /* slc */
2408 if (components_32bit
> 1)
2409 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2411 writemask
= widen_mask(writemask
, elem_size_mult
);
2413 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2414 base_data
= ac_trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2415 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2417 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2421 LLVMValueRef offset
;
2423 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2425 /* Due to an LLVM limitation, split 3-element writes
2426 * into a 2-element and a 1-element write. */
2428 writemask
|= 1 << (start
+ 2);
2433 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2438 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2439 } else if (count
== 2) {
2440 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2444 store_name
= "llvm.amdgcn.buffer.store.f32";
2446 data
= extract_vector_range(&ctx
->ac
, base_data
, start
, count
);
2448 offset
= base_offset
;
2450 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2454 ac_build_intrinsic(&ctx
->ac
, store_name
,
2455 ctx
->ac
.voidt
, params
, 6, 0);
2459 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2460 const nir_intrinsic_instr
*instr
)
2463 LLVMValueRef params
[6];
2466 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2467 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2469 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2470 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2471 get_src(ctx
, instr
->src
[0]),
2473 params
[arg_count
++] = ctx
->ac
.i32_0
; /* vindex */
2474 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2475 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2477 switch (instr
->intrinsic
) {
2478 case nir_intrinsic_ssbo_atomic_add
:
2479 name
= "llvm.amdgcn.buffer.atomic.add";
2481 case nir_intrinsic_ssbo_atomic_imin
:
2482 name
= "llvm.amdgcn.buffer.atomic.smin";
2484 case nir_intrinsic_ssbo_atomic_umin
:
2485 name
= "llvm.amdgcn.buffer.atomic.umin";
2487 case nir_intrinsic_ssbo_atomic_imax
:
2488 name
= "llvm.amdgcn.buffer.atomic.smax";
2490 case nir_intrinsic_ssbo_atomic_umax
:
2491 name
= "llvm.amdgcn.buffer.atomic.umax";
2493 case nir_intrinsic_ssbo_atomic_and
:
2494 name
= "llvm.amdgcn.buffer.atomic.and";
2496 case nir_intrinsic_ssbo_atomic_or
:
2497 name
= "llvm.amdgcn.buffer.atomic.or";
2499 case nir_intrinsic_ssbo_atomic_xor
:
2500 name
= "llvm.amdgcn.buffer.atomic.xor";
2502 case nir_intrinsic_ssbo_atomic_exchange
:
2503 name
= "llvm.amdgcn.buffer.atomic.swap";
2505 case nir_intrinsic_ssbo_atomic_comp_swap
:
2506 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2512 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2515 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2516 const nir_intrinsic_instr
*instr
)
2518 LLVMValueRef results
[2];
2519 int load_components
;
2520 int num_components
= instr
->num_components
;
2521 if (instr
->dest
.ssa
.bit_size
== 64)
2522 num_components
*= 2;
2524 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2525 load_components
= MIN2(num_components
- i
, 4);
2526 const char *load_name
;
2527 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2528 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2529 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2531 if (load_components
== 3)
2532 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2533 else if (load_components
> 1)
2534 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2536 if (load_components
>= 3)
2537 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2538 else if (load_components
== 2)
2539 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2540 else if (load_components
== 1)
2541 load_name
= "llvm.amdgcn.buffer.load.f32";
2543 unreachable("unhandled number of components");
2545 LLVMValueRef params
[] = {
2546 ctx
->abi
->load_ssbo(ctx
->abi
,
2547 get_src(ctx
, instr
->src
[0]),
2555 results
[i
> 0 ? 1 : 0] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2559 LLVMValueRef ret
= results
[0];
2560 if (num_components
> 4 || num_components
== 3) {
2561 LLVMValueRef masks
[] = {
2562 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2563 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2564 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2565 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2568 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2569 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2570 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2573 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2574 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2577 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2578 const nir_intrinsic_instr
*instr
)
2581 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2582 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2583 int num_components
= instr
->num_components
;
2585 if (ctx
->abi
->load_ubo
)
2586 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2588 if (instr
->dest
.ssa
.bit_size
== 64)
2589 num_components
*= 2;
2591 ret
= ac_build_buffer_load(&ctx
->ac
, rsrc
, num_components
, NULL
, offset
,
2592 NULL
, 0, false, false, true, true);
2593 ret
= ac_trim_vector(&ctx
->ac
, ret
, num_components
);
2594 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2595 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2599 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2600 bool vs_in
, unsigned *vertex_index_out
,
2601 LLVMValueRef
*vertex_index_ref
,
2602 unsigned *const_out
, LLVMValueRef
*indir_out
)
2604 unsigned const_offset
= 0;
2605 nir_deref
*tail
= &deref
->deref
;
2606 LLVMValueRef offset
= NULL
;
2608 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2610 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2611 if (vertex_index_out
)
2612 *vertex_index_out
= deref_array
->base_offset
;
2614 if (vertex_index_ref
) {
2615 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2616 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2617 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2619 *vertex_index_ref
= vtx
;
2623 if (deref
->var
->data
.compact
) {
2624 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2625 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2626 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2627 /* We always lower indirect dereferences for "compact" array vars. */
2628 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2630 const_offset
= deref_array
->base_offset
;
2634 while (tail
->child
!= NULL
) {
2635 const struct glsl_type
*parent_type
= tail
->type
;
2638 if (tail
->deref_type
== nir_deref_type_array
) {
2639 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2640 LLVMValueRef index
, stride
, local_offset
;
2641 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2643 const_offset
+= size
* deref_array
->base_offset
;
2644 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2647 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2648 index
= get_src(ctx
, deref_array
->indirect
);
2649 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2650 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2653 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2655 offset
= local_offset
;
2656 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2657 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2659 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2660 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2661 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2664 unreachable("unsupported deref type");
2668 if (const_offset
&& offset
)
2669 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2670 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2673 *const_out
= const_offset
;
2674 *indir_out
= offset
;
2678 /* The offchip buffer layout for TCS->TES is
2680 * - attribute 0 of patch 0 vertex 0
2681 * - attribute 0 of patch 0 vertex 1
2682 * - attribute 0 of patch 0 vertex 2
2684 * - attribute 0 of patch 1 vertex 0
2685 * - attribute 0 of patch 1 vertex 1
2687 * - attribute 1 of patch 0 vertex 0
2688 * - attribute 1 of patch 0 vertex 1
2690 * - per patch attribute 0 of patch 0
2691 * - per patch attribute 0 of patch 1
2694 * Note that every attribute has 4 components.
2696 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
2697 LLVMValueRef vertex_index
,
2698 LLVMValueRef param_index
)
2700 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
;
2701 LLVMValueRef param_stride
, constant16
;
2702 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2704 vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
2705 num_patches
= ac_unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2707 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2709 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
2710 vertices_per_patch
, "");
2712 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
2715 param_stride
= LLVMBuildMul(ctx
->ac
.builder
, vertices_per_patch
,
2718 base_addr
= rel_patch_id
;
2719 param_stride
= num_patches
;
2722 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
2723 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
2724 param_stride
, ""), "");
2726 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
2728 if (!vertex_index
) {
2729 LLVMValueRef patch_data_offset
=
2730 ac_unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2732 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
2733 patch_data_offset
, "");
2738 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
2740 unsigned const_index
,
2742 LLVMValueRef vertex_index
,
2743 LLVMValueRef indir_index
)
2745 LLVMValueRef param_index
;
2748 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
2751 if (const_index
&& !is_compact
)
2752 param
+= const_index
;
2753 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
2755 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2759 mark_tess_output(struct radv_shader_context
*ctx
,
2760 bool is_patch
, uint32_t param
)
2764 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2766 ctx
->tess_outputs_written
|= (1ull << param
);
2770 get_dw_address(struct radv_shader_context
*ctx
,
2771 LLVMValueRef dw_addr
,
2773 unsigned const_index
,
2774 bool compact_const_index
,
2775 LLVMValueRef vertex_index
,
2776 LLVMValueRef stride
,
2777 LLVMValueRef indir_index
)
2782 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2783 LLVMBuildMul(ctx
->ac
.builder
,
2789 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2790 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
2791 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
2792 else if (const_index
&& !compact_const_index
)
2793 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2794 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2796 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2797 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
2799 if (const_index
&& compact_const_index
)
2800 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2801 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2806 load_tcs_varyings(struct ac_shader_abi
*abi
,
2808 LLVMValueRef vertex_index
,
2809 LLVMValueRef indir_index
,
2810 unsigned const_index
,
2812 unsigned driver_location
,
2814 unsigned num_components
,
2819 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2820 LLVMValueRef dw_addr
, stride
;
2821 LLVMValueRef value
[4], result
;
2822 unsigned param
= shader_io_get_unique_index(location
);
2825 stride
= ac_unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2826 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2829 stride
= get_tcs_out_vertex_stride(ctx
);
2830 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2832 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2837 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2840 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
2841 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2842 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2845 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
2850 store_tcs_output(struct ac_shader_abi
*abi
,
2851 LLVMValueRef vertex_index
,
2852 LLVMValueRef param_index
,
2853 unsigned const_index
,
2855 unsigned driver_location
,
2862 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2863 LLVMValueRef dw_addr
;
2864 LLVMValueRef stride
= NULL
;
2865 LLVMValueRef buf_addr
= NULL
;
2867 bool store_lds
= true;
2870 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
2873 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
2877 param
= shader_io_get_unique_index(location
);
2878 if (location
== VARYING_SLOT_CLIP_DIST0
&&
2879 is_compact
&& const_index
> 3) {
2885 stride
= get_tcs_out_vertex_stride(ctx
);
2886 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2888 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2891 mark_tess_output(ctx
, is_patch
, param
);
2893 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2895 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2896 vertex_index
, param_index
);
2898 bool is_tess_factor
= false;
2899 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2900 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2901 is_tess_factor
= true;
2903 unsigned base
= is_compact
? const_index
: 0;
2904 for (unsigned chan
= 0; chan
< 8; chan
++) {
2905 if (!(writemask
& (1 << chan
)))
2907 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
2909 if (store_lds
|| is_tess_factor
) {
2910 LLVMValueRef dw_addr_chan
=
2911 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2912 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
2913 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
2916 if (!is_tess_factor
&& writemask
!= 0xF)
2917 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
2918 buf_addr
, ctx
->oc_lds
,
2919 4 * (base
+ chan
), 1, 0, true, false);
2922 if (writemask
== 0xF) {
2923 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
2924 buf_addr
, ctx
->oc_lds
,
2925 (base
* 4), 1, 0, true, false);
2930 load_tes_input(struct ac_shader_abi
*abi
,
2932 LLVMValueRef vertex_index
,
2933 LLVMValueRef param_index
,
2934 unsigned const_index
,
2936 unsigned driver_location
,
2938 unsigned num_components
,
2943 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2944 LLVMValueRef buf_addr
;
2945 LLVMValueRef result
;
2946 unsigned param
= shader_io_get_unique_index(location
);
2948 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
2953 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
2954 is_compact
, vertex_index
, param_index
);
2956 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
2957 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
2959 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
2960 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
2961 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
2966 load_gs_input(struct ac_shader_abi
*abi
,
2968 unsigned driver_location
,
2970 unsigned num_components
,
2971 unsigned vertex_index
,
2972 unsigned const_index
,
2975 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2976 LLVMValueRef vtx_offset
;
2977 unsigned param
, vtx_offset_param
;
2978 LLVMValueRef value
[4], result
;
2980 vtx_offset_param
= vertex_index
;
2981 assert(vtx_offset_param
< 6);
2982 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
2983 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2985 param
= shader_io_get_unique_index(location
);
2987 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
2988 if (ctx
->ac
.chip_class
>= GFX9
) {
2989 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
2990 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2991 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
2992 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2994 LLVMValueRef soffset
=
2995 LLVMConstInt(ctx
->ac
.i32
,
2996 (param
* 4 + i
+ const_index
) * 256,
2999 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
3002 vtx_offset
, soffset
,
3003 0, 1, 0, true, false);
3005 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
],
3009 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
3010 result
= ac_to_integer(&ctx
->ac
, result
);
3015 build_gep_for_deref(struct ac_nir_context
*ctx
,
3016 nir_deref_var
*deref
)
3018 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
3019 assert(entry
->data
);
3020 LLVMValueRef val
= entry
->data
;
3021 nir_deref
*tail
= deref
->deref
.child
;
3022 while (tail
!= NULL
) {
3023 LLVMValueRef offset
;
3024 switch (tail
->deref_type
) {
3025 case nir_deref_type_array
: {
3026 nir_deref_array
*array
= nir_deref_as_array(tail
);
3027 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
3028 if (array
->deref_array_type
==
3029 nir_deref_array_type_indirect
) {
3030 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
3037 case nir_deref_type_struct
: {
3038 nir_deref_struct
*deref_struct
=
3039 nir_deref_as_struct(tail
);
3040 offset
= LLVMConstInt(ctx
->ac
.i32
,
3041 deref_struct
->index
, 0);
3045 unreachable("bad deref type");
3047 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
3053 static LLVMValueRef
load_tess_varyings(struct ac_nir_context
*ctx
,
3054 nir_intrinsic_instr
*instr
,
3057 LLVMValueRef result
;
3058 LLVMValueRef vertex_index
= NULL
;
3059 LLVMValueRef indir_index
= NULL
;
3060 unsigned const_index
= 0;
3061 unsigned location
= instr
->variables
[0]->var
->data
.location
;
3062 unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3063 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3064 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3066 get_deref_offset(ctx
, instr
->variables
[0],
3067 false, NULL
, is_patch
? NULL
: &vertex_index
,
3068 &const_index
, &indir_index
);
3070 LLVMTypeRef dest_type
= get_def_type(ctx
, &instr
->dest
.ssa
);
3072 LLVMTypeRef src_component_type
;
3073 if (LLVMGetTypeKind(dest_type
) == LLVMVectorTypeKind
)
3074 src_component_type
= LLVMGetElementType(dest_type
);
3076 src_component_type
= dest_type
;
3078 result
= ctx
->abi
->load_tess_varyings(ctx
->abi
, src_component_type
,
3079 vertex_index
, indir_index
,
3080 const_index
, location
, driver_location
,
3081 instr
->variables
[0]->var
->data
.location_frac
,
3082 instr
->num_components
,
3083 is_patch
, is_compact
, load_inputs
);
3084 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, dest_type
, "");
3087 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
3088 nir_intrinsic_instr
*instr
)
3090 LLVMValueRef values
[8];
3091 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3092 int ve
= instr
->dest
.ssa
.num_components
;
3093 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3094 LLVMValueRef indir_index
;
3096 unsigned const_index
;
3097 unsigned stride
= instr
->variables
[0]->var
->data
.compact
? 1 : 4;
3098 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3099 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3100 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3101 &const_index
, &indir_index
);
3103 if (instr
->dest
.ssa
.bit_size
== 64)
3106 switch (instr
->variables
[0]->var
->data
.mode
) {
3107 case nir_var_shader_in
:
3108 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3109 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3110 return load_tess_varyings(ctx
, instr
, true);
3113 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3114 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->dest
.ssa
.bit_size
);
3115 LLVMValueRef indir_index
;
3116 unsigned const_index
, vertex_index
;
3117 get_deref_offset(ctx
, instr
->variables
[0],
3118 false, &vertex_index
, NULL
,
3119 &const_index
, &indir_index
);
3121 return ctx
->abi
->load_inputs(ctx
->abi
, instr
->variables
[0]->var
->data
.location
,
3122 instr
->variables
[0]->var
->data
.driver_location
,
3123 instr
->variables
[0]->var
->data
.location_frac
,
3124 instr
->num_components
, vertex_index
, const_index
, type
);
3127 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3129 unsigned count
= glsl_count_attribute_slots(
3130 instr
->variables
[0]->var
->type
,
3131 ctx
->stage
== MESA_SHADER_VERTEX
);
3133 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3134 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3135 stride
, false, true);
3137 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3141 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* stride
];
3145 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3147 unsigned count
= glsl_count_attribute_slots(
3148 instr
->variables
[0]->var
->type
, false);
3150 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3151 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3152 stride
, true, true);
3154 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3158 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* stride
], "");
3162 case nir_var_shared
: {
3163 LLVMValueRef address
= build_gep_for_deref(ctx
,
3164 instr
->variables
[0]);
3165 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3166 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3167 get_def_type(ctx
, &instr
->dest
.ssa
),
3170 case nir_var_shader_out
:
3171 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3172 return load_tess_varyings(ctx
, instr
, false);
3175 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3177 unsigned count
= glsl_count_attribute_slots(
3178 instr
->variables
[0]->var
->type
, false);
3180 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3181 &ctx
->ac
, ctx
->abi
->outputs
+ idx
+ chan
, count
,
3182 stride
, true, true);
3184 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3188 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3189 ctx
->abi
->outputs
[idx
+ chan
+ const_index
* stride
],
3195 unreachable("unhandle variable mode");
3197 ret
= ac_build_varying_gather_values(&ctx
->ac
, values
, ve
, comp
);
3198 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3202 visit_store_var(struct ac_nir_context
*ctx
,
3203 nir_intrinsic_instr
*instr
)
3205 LLVMValueRef temp_ptr
, value
;
3206 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3207 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3208 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3209 int writemask
= instr
->const_index
[0] << comp
;
3210 LLVMValueRef indir_index
;
3211 unsigned const_index
;
3212 get_deref_offset(ctx
, instr
->variables
[0], false,
3213 NULL
, NULL
, &const_index
, &indir_index
);
3215 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3217 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3218 LLVMVectorType(ctx
->ac
.f32
, ac_get_llvm_num_components(src
) * 2),
3221 writemask
= widen_mask(writemask
, 2);
3224 switch (instr
->variables
[0]->var
->data
.mode
) {
3225 case nir_var_shader_out
:
3227 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3228 LLVMValueRef vertex_index
= NULL
;
3229 LLVMValueRef indir_index
= NULL
;
3230 unsigned const_index
= 0;
3231 const unsigned location
= instr
->variables
[0]->var
->data
.location
;
3232 const unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3233 const unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3234 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3235 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3237 get_deref_offset(ctx
, instr
->variables
[0],
3238 false, NULL
, is_patch
? NULL
: &vertex_index
,
3239 &const_index
, &indir_index
);
3241 ctx
->abi
->store_tcs_outputs(ctx
->abi
, vertex_index
, indir_index
,
3242 const_index
, location
, driver_location
,
3243 src
, comp
, is_patch
, is_compact
, writemask
);
3247 for (unsigned chan
= 0; chan
< 8; chan
++) {
3249 if (!(writemask
& (1 << chan
)))
3252 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
3254 if (instr
->variables
[0]->var
->data
.compact
)
3257 unsigned count
= glsl_count_attribute_slots(
3258 instr
->variables
[0]->var
->type
, false);
3260 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3261 &ctx
->ac
, ctx
->abi
->outputs
+ idx
+ chan
, count
,
3262 stride
, true, true);
3264 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3265 value
, indir_index
, "");
3266 build_store_values_extended(&ctx
->ac
, ctx
->abi
->outputs
+ idx
+ chan
,
3267 count
, stride
, tmp_vec
);
3270 temp_ptr
= ctx
->abi
->outputs
[idx
+ chan
+ const_index
* stride
];
3272 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3277 for (unsigned chan
= 0; chan
< 8; chan
++) {
3278 if (!(writemask
& (1 << chan
)))
3281 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3283 unsigned count
= glsl_count_attribute_slots(
3284 instr
->variables
[0]->var
->type
, false);
3286 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3287 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3290 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3291 value
, indir_index
, "");
3292 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3295 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3297 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3301 case nir_var_shared
: {
3302 int writemask
= instr
->const_index
[0];
3303 LLVMValueRef address
= build_gep_for_deref(ctx
,
3304 instr
->variables
[0]);
3305 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3306 unsigned components
=
3307 glsl_get_vector_elements(
3308 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3309 if (writemask
== (1 << components
) - 1) {
3310 val
= LLVMBuildBitCast(
3311 ctx
->ac
.builder
, val
,
3312 LLVMGetElementType(LLVMTypeOf(address
)), "");
3313 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3315 for (unsigned chan
= 0; chan
< 4; chan
++) {
3316 if (!(writemask
& (1 << chan
)))
3319 LLVMBuildStructGEP(ctx
->ac
.builder
,
3321 LLVMValueRef src
= ac_llvm_extract_elem(&ctx
->ac
, val
,
3323 src
= LLVMBuildBitCast(
3324 ctx
->ac
.builder
, src
,
3325 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3326 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3336 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3339 case GLSL_SAMPLER_DIM_BUF
:
3341 case GLSL_SAMPLER_DIM_1D
:
3342 return array
? 2 : 1;
3343 case GLSL_SAMPLER_DIM_2D
:
3344 return array
? 3 : 2;
3345 case GLSL_SAMPLER_DIM_MS
:
3346 return array
? 4 : 3;
3347 case GLSL_SAMPLER_DIM_3D
:
3348 case GLSL_SAMPLER_DIM_CUBE
:
3350 case GLSL_SAMPLER_DIM_RECT
:
3351 case GLSL_SAMPLER_DIM_SUBPASS
:
3353 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3362 glsl_is_array_image(const struct glsl_type
*type
)
3364 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3366 if (glsl_sampler_type_is_array(type
))
3369 return dim
== GLSL_SAMPLER_DIM_CUBE
||
3370 dim
== GLSL_SAMPLER_DIM_3D
||
3371 dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3372 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
;
3376 /* Adjust the sample index according to FMASK.
3378 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3379 * which is the identity mapping. Each nibble says which physical sample
3380 * should be fetched to get that sample.
3382 * For example, 0x11111100 means there are only 2 samples stored and
3383 * the second sample covers 3/4 of the pixel. When reading samples 0
3384 * and 1, return physical sample 0 (determined by the first two 0s
3385 * in FMASK), otherwise return physical sample 1.
3387 * The sample index should be adjusted as follows:
3388 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3390 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3391 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3392 LLVMValueRef coord_z
,
3393 LLVMValueRef sample_index
,
3394 LLVMValueRef fmask_desc_ptr
)
3396 LLVMValueRef fmask_load_address
[4];
3399 fmask_load_address
[0] = coord_x
;
3400 fmask_load_address
[1] = coord_y
;
3402 fmask_load_address
[2] = coord_z
;
3403 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3406 struct ac_image_args args
= {0};
3408 args
.opcode
= ac_image_load
;
3409 args
.da
= coord_z
? true : false;
3410 args
.resource
= fmask_desc_ptr
;
3412 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3414 res
= ac_build_image_opcode(ctx
, &args
);
3416 res
= ac_to_integer(ctx
, res
);
3417 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3418 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3420 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3424 LLVMValueRef sample_index4
=
3425 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3426 LLVMValueRef shifted_fmask
=
3427 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3428 LLVMValueRef final_sample
=
3429 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3431 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3432 * resource descriptor is 0 (invalid),
3434 LLVMValueRef fmask_desc
=
3435 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3438 LLVMValueRef fmask_word1
=
3439 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3442 LLVMValueRef word1_is_nonzero
=
3443 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3444 fmask_word1
, ctx
->i32_0
, "");
3446 /* Replace the MSAA sample index. */
3448 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3449 final_sample
, sample_index
, "");
3450 return sample_index
;
3453 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3454 const nir_intrinsic_instr
*instr
)
3456 const struct glsl_type
*type
= glsl_without_array(instr
->variables
[0]->var
->type
);
3458 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3459 LLVMValueRef coords
[4];
3460 LLVMValueRef masks
[] = {
3461 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3462 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3465 LLVMValueRef sample_index
= ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3468 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3469 bool is_array
= glsl_sampler_type_is_array(type
);
3470 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3471 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3472 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3473 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3474 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3475 count
= image_type_to_components_count(dim
, is_array
);
3478 LLVMValueRef fmask_load_address
[3];
3481 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3482 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3484 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3486 fmask_load_address
[2] = NULL
;
3488 for (chan
= 0; chan
< 2; ++chan
)
3489 fmask_load_address
[chan
] =
3490 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3491 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3492 ctx
->ac
.i32
, ""), "");
3493 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3495 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3496 fmask_load_address
[0],
3497 fmask_load_address
[1],
3498 fmask_load_address
[2],
3500 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, NULL
, true, false));
3502 if (count
== 1 && !gfx9_1d
) {
3503 if (instr
->src
[0].ssa
->num_components
)
3504 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3511 for (chan
= 0; chan
< count
; ++chan
) {
3512 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3515 for (chan
= 0; chan
< 2; ++chan
)
3516 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3517 ctx
->ac
.i32
, ""), "");
3518 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3524 coords
[2] = coords
[1];
3525 coords
[1] = ctx
->ac
.i32_0
;
3527 coords
[1] = ctx
->ac
.i32_0
;
3532 coords
[count
] = sample_index
;
3537 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3540 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3545 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3546 const nir_intrinsic_instr
*instr
)
3548 LLVMValueRef params
[7];
3550 char intrinsic_name
[64];
3551 const nir_variable
*var
= instr
->variables
[0]->var
;
3552 const struct glsl_type
*type
= var
->type
;
3554 if(instr
->variables
[0]->deref
.child
)
3555 type
= instr
->variables
[0]->deref
.child
->type
;
3557 type
= glsl_without_array(type
);
3559 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3560 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3561 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
3562 unsigned num_channels
= util_last_bit(mask
);
3563 LLVMValueRef rsrc
, vindex
;
3565 rsrc
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, false);
3566 vindex
= LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3569 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3570 res
= ac_build_buffer_load_format(&ctx
->ac
, rsrc
, vindex
,
3571 ctx
->ac
.i32_0
, num_channels
,
3573 res
= ac_build_expand_to_vec4(&ctx
->ac
, res
, num_channels
);
3575 res
= ac_trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3576 res
= ac_to_integer(&ctx
->ac
, res
);
3578 LLVMValueRef da
= glsl_is_array_image(type
) ? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3579 LLVMValueRef slc
= ctx
->ac
.i1false
;
3581 params
[0] = get_image_coords(ctx
, instr
);
3582 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3583 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3584 params
[3] = (var
->data
.image
._volatile
|| var
->data
.image
.coherent
) ?
3585 ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3587 params
[5] = ctx
->ac
.i1false
;
3590 ac_get_image_intr_name("llvm.amdgcn.image.load",
3591 ctx
->ac
.v4f32
, /* vdata */
3592 LLVMTypeOf(params
[0]), /* coords */
3593 LLVMTypeOf(params
[1]), /* rsrc */
3594 intrinsic_name
, sizeof(intrinsic_name
));
3596 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3597 params
, 7, AC_FUNC_ATTR_READONLY
);
3599 return ac_to_integer(&ctx
->ac
, res
);
3602 static void visit_image_store(struct ac_nir_context
*ctx
,
3603 nir_intrinsic_instr
*instr
)
3605 LLVMValueRef params
[8];
3606 char intrinsic_name
[64];
3607 const nir_variable
*var
= instr
->variables
[0]->var
;
3608 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3609 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3610 LLVMValueRef glc
= ctx
->ac
.i1false
;
3611 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3613 glc
= ctx
->ac
.i1true
;
3615 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3616 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3617 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, true);
3618 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3619 ctx
->ac
.i32_0
, ""); /* vindex */
3620 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3621 params
[4] = glc
; /* glc */
3622 params
[5] = ctx
->ac
.i1false
; /* slc */
3623 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3626 LLVMValueRef da
= glsl_is_array_image(type
) ? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3627 LLVMValueRef slc
= ctx
->ac
.i1false
;
3629 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3630 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3631 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, true);
3632 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3633 params
[4] = (force_glc
|| var
->data
.image
._volatile
|| var
->data
.image
.coherent
) ?
3634 ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3636 params
[6] = ctx
->ac
.i1false
;
3639 ac_get_image_intr_name("llvm.amdgcn.image.store",
3640 LLVMTypeOf(params
[0]), /* vdata */
3641 LLVMTypeOf(params
[1]), /* coords */
3642 LLVMTypeOf(params
[2]), /* rsrc */
3643 intrinsic_name
, sizeof(intrinsic_name
));
3645 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3651 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3652 const nir_intrinsic_instr
*instr
)
3654 LLVMValueRef params
[7];
3655 int param_count
= 0;
3656 const nir_variable
*var
= instr
->variables
[0]->var
;
3658 const char *atomic_name
;
3659 char intrinsic_name
[41];
3660 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3661 MAYBE_UNUSED
int length
;
3663 bool is_unsigned
= glsl_get_sampler_result_type(type
) == GLSL_TYPE_UINT
;
3665 switch (instr
->intrinsic
) {
3666 case nir_intrinsic_image_atomic_add
:
3667 atomic_name
= "add";
3669 case nir_intrinsic_image_atomic_min
:
3670 atomic_name
= is_unsigned
? "umin" : "smin";
3672 case nir_intrinsic_image_atomic_max
:
3673 atomic_name
= is_unsigned
? "umax" : "smax";
3675 case nir_intrinsic_image_atomic_and
:
3676 atomic_name
= "and";
3678 case nir_intrinsic_image_atomic_or
:
3681 case nir_intrinsic_image_atomic_xor
:
3682 atomic_name
= "xor";
3684 case nir_intrinsic_image_atomic_exchange
:
3685 atomic_name
= "swap";
3687 case nir_intrinsic_image_atomic_comp_swap
:
3688 atomic_name
= "cmpswap";
3694 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3695 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3696 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3698 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3699 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3701 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3702 ctx
->ac
.i32_0
, ""); /* vindex */
3703 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3704 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3706 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3707 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3709 char coords_type
[8];
3711 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3712 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3714 params
[param_count
++] = ctx
->ac
.i1false
; /* r128 */
3715 params
[param_count
++] = glsl_is_array_image(type
) ? ctx
->ac
.i1true
: ctx
->ac
.i1false
; /* da */
3716 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3718 build_int_type_name(LLVMTypeOf(coords
),
3719 coords_type
, sizeof(coords_type
));
3721 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3722 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3725 assert(length
< sizeof(intrinsic_name
));
3726 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3729 static LLVMValueRef
visit_image_samples(struct ac_nir_context
*ctx
,
3730 const nir_intrinsic_instr
*instr
)
3732 const nir_variable
*var
= instr
->variables
[0]->var
;
3733 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3735 struct ac_image_args args
= { 0 };
3736 args
.da
= glsl_is_array_image(type
);
3738 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0],
3739 AC_DESC_IMAGE
, NULL
, true, false);
3740 args
.opcode
= ac_image_get_resinfo
;
3741 args
.addr
= ctx
->ac
.i32_0
;
3743 return ac_build_image_opcode(&ctx
->ac
, &args
);
3746 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3747 const nir_intrinsic_instr
*instr
)
3750 const nir_variable
*var
= instr
->variables
[0]->var
;
3751 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3753 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3754 return get_buffer_size(ctx
,
3755 get_sampler_desc(ctx
, instr
->variables
[0],
3756 AC_DESC_BUFFER
, NULL
, true, false), true);
3758 struct ac_image_args args
= { 0 };
3760 args
.da
= glsl_is_array_image(type
);
3762 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3763 args
.opcode
= ac_image_get_resinfo
;
3764 args
.addr
= ctx
->ac
.i32_0
;
3766 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3768 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3770 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3771 glsl_sampler_type_is_array(type
)) {
3772 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3773 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3774 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3775 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3777 if (ctx
->ac
.chip_class
>= GFX9
&&
3778 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3779 glsl_sampler_type_is_array(type
)) {
3780 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3781 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3788 #define NOOP_WAITCNT 0xf7f
3789 #define LGKM_CNT 0x07f
3790 #define VM_CNT 0xf70
3792 static void emit_membar(struct ac_llvm_context
*ac
,
3793 const nir_intrinsic_instr
*instr
)
3795 unsigned waitcnt
= NOOP_WAITCNT
;
3797 switch (instr
->intrinsic
) {
3798 case nir_intrinsic_memory_barrier
:
3799 case nir_intrinsic_group_memory_barrier
:
3800 waitcnt
&= VM_CNT
& LGKM_CNT
;
3802 case nir_intrinsic_memory_barrier_atomic_counter
:
3803 case nir_intrinsic_memory_barrier_buffer
:
3804 case nir_intrinsic_memory_barrier_image
:
3807 case nir_intrinsic_memory_barrier_shared
:
3808 waitcnt
&= LGKM_CNT
;
3813 if (waitcnt
!= NOOP_WAITCNT
)
3814 ac_build_waitcnt(ac
, waitcnt
);
3817 static void emit_barrier(struct ac_llvm_context
*ac
, gl_shader_stage stage
)
3819 /* SI only (thanks to a hw bug workaround):
3820 * The real barrier instruction isn’t needed, because an entire patch
3821 * always fits into a single wave.
3823 if (ac
->chip_class
== SI
&& stage
== MESA_SHADER_TESS_CTRL
) {
3824 ac_build_waitcnt(ac
, LGKM_CNT
& VM_CNT
);
3827 ac_build_intrinsic(ac
, "llvm.amdgcn.s.barrier",
3828 ac
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3831 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
3833 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3834 ac_build_kill_if_false(&ctx
->ac
, visible
);
3837 static void emit_discard(struct ac_nir_context
*ctx
,
3838 const nir_intrinsic_instr
*instr
)
3842 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3843 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3844 get_src(ctx
, instr
->src
[0]),
3847 assert(instr
->intrinsic
== nir_intrinsic_discard
);
3848 cond
= LLVMConstInt(ctx
->ac
.i1
, false, 0);
3851 ctx
->abi
->emit_kill(ctx
->abi
, cond
);
3855 visit_load_helper_invocation(struct ac_nir_context
*ctx
)
3857 LLVMValueRef result
= ac_build_intrinsic(&ctx
->ac
,
3858 "llvm.amdgcn.ps.live",
3859 ctx
->ac
.i1
, NULL
, 0,
3860 AC_FUNC_ATTR_READNONE
);
3861 result
= LLVMBuildNot(ctx
->ac
.builder
, result
, "");
3862 return LLVMBuildSExt(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
3866 visit_load_local_invocation_index(struct ac_nir_context
*ctx
)
3868 LLVMValueRef result
;
3869 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3870 result
= LLVMBuildAnd(ctx
->ac
.builder
, ctx
->abi
->tg_size
,
3871 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3873 return LLVMBuildAdd(ctx
->ac
.builder
, result
, thread_id
, "");
3877 visit_load_subgroup_id(struct ac_nir_context
*ctx
)
3879 if (ctx
->stage
== MESA_SHADER_COMPUTE
) {
3880 LLVMValueRef result
;
3881 result
= LLVMBuildAnd(ctx
->ac
.builder
, ctx
->abi
->tg_size
,
3882 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3883 return LLVMBuildLShr(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 6, false), "");
3885 return LLVMConstInt(ctx
->ac
.i32
, 0, false);
3890 visit_load_num_subgroups(struct ac_nir_context
*ctx
)
3892 if (ctx
->stage
== MESA_SHADER_COMPUTE
) {
3893 return LLVMBuildAnd(ctx
->ac
.builder
, ctx
->abi
->tg_size
,
3894 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
3896 return LLVMConstInt(ctx
->ac
.i32
, 1, false);
3901 visit_first_invocation(struct ac_nir_context
*ctx
)
3903 LLVMValueRef active_set
= ac_build_ballot(&ctx
->ac
, ctx
->ac
.i32_1
);
3905 /* The second argument is whether cttz(0) should be defined, but we do not care. */
3906 LLVMValueRef args
[] = {active_set
, LLVMConstInt(ctx
->ac
.i1
, 0, false)};
3907 LLVMValueRef result
= ac_build_intrinsic(&ctx
->ac
,
3909 ctx
->ac
.i64
, args
, 2,
3910 AC_FUNC_ATTR_NOUNWIND
|
3911 AC_FUNC_ATTR_READNONE
);
3913 return LLVMBuildTrunc(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
3917 visit_load_shared(struct ac_nir_context
*ctx
,
3918 const nir_intrinsic_instr
*instr
)
3920 LLVMValueRef values
[4], derived_ptr
, index
, ret
;
3922 LLVMValueRef ptr
= get_memory_ptr(ctx
, instr
->src
[0]);
3924 for (int chan
= 0; chan
< instr
->num_components
; chan
++) {
3925 index
= LLVMConstInt(ctx
->ac
.i32
, chan
, 0);
3926 derived_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
3927 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, derived_ptr
, "");
3930 ret
= ac_build_gather_values(&ctx
->ac
, values
, instr
->num_components
);
3931 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3935 visit_store_shared(struct ac_nir_context
*ctx
,
3936 const nir_intrinsic_instr
*instr
)
3938 LLVMValueRef derived_ptr
, data
,index
;
3939 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3941 LLVMValueRef ptr
= get_memory_ptr(ctx
, instr
->src
[1]);
3942 LLVMValueRef src
= get_src(ctx
, instr
->src
[0]);
3944 int writemask
= nir_intrinsic_write_mask(instr
);
3945 for (int chan
= 0; chan
< 4; chan
++) {
3946 if (!(writemask
& (1 << chan
))) {
3949 data
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3950 index
= LLVMConstInt(ctx
->ac
.i32
, chan
, 0);
3951 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
3952 LLVMBuildStore(builder
, data
, derived_ptr
);
3956 static LLVMValueRef
visit_var_atomic(struct ac_nir_context
*ctx
,
3957 const nir_intrinsic_instr
*instr
,
3958 LLVMValueRef ptr
, int src_idx
)
3960 LLVMValueRef result
;
3961 LLVMValueRef src
= get_src(ctx
, instr
->src
[src_idx
]);
3963 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
||
3964 instr
->intrinsic
== nir_intrinsic_shared_atomic_comp_swap
) {
3965 LLVMValueRef src1
= get_src(ctx
, instr
->src
[src_idx
+ 1]);
3966 result
= LLVMBuildAtomicCmpXchg(ctx
->ac
.builder
,
3968 LLVMAtomicOrderingSequentiallyConsistent
,
3969 LLVMAtomicOrderingSequentiallyConsistent
,
3972 LLVMAtomicRMWBinOp op
;
3973 switch (instr
->intrinsic
) {
3974 case nir_intrinsic_var_atomic_add
:
3975 case nir_intrinsic_shared_atomic_add
:
3976 op
= LLVMAtomicRMWBinOpAdd
;
3978 case nir_intrinsic_var_atomic_umin
:
3979 case nir_intrinsic_shared_atomic_umin
:
3980 op
= LLVMAtomicRMWBinOpUMin
;
3982 case nir_intrinsic_var_atomic_umax
:
3983 case nir_intrinsic_shared_atomic_umax
:
3984 op
= LLVMAtomicRMWBinOpUMax
;
3986 case nir_intrinsic_var_atomic_imin
:
3987 case nir_intrinsic_shared_atomic_imin
:
3988 op
= LLVMAtomicRMWBinOpMin
;
3990 case nir_intrinsic_var_atomic_imax
:
3991 case nir_intrinsic_shared_atomic_imax
:
3992 op
= LLVMAtomicRMWBinOpMax
;
3994 case nir_intrinsic_var_atomic_and
:
3995 case nir_intrinsic_shared_atomic_and
:
3996 op
= LLVMAtomicRMWBinOpAnd
;
3998 case nir_intrinsic_var_atomic_or
:
3999 case nir_intrinsic_shared_atomic_or
:
4000 op
= LLVMAtomicRMWBinOpOr
;
4002 case nir_intrinsic_var_atomic_xor
:
4003 case nir_intrinsic_shared_atomic_xor
:
4004 op
= LLVMAtomicRMWBinOpXor
;
4006 case nir_intrinsic_var_atomic_exchange
:
4007 case nir_intrinsic_shared_atomic_exchange
:
4008 op
= LLVMAtomicRMWBinOpXchg
;
4014 result
= LLVMBuildAtomicRMW(ctx
->ac
.builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
4015 LLVMAtomicOrderingSequentiallyConsistent
,
4021 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
4022 enum glsl_interp_mode interp
, unsigned location
)
4024 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4027 case INTERP_MODE_FLAT
:
4030 case INTERP_MODE_SMOOTH
:
4031 case INTERP_MODE_NONE
:
4032 if (location
== INTERP_CENTER
)
4033 return ctx
->persp_center
;
4034 else if (location
== INTERP_CENTROID
)
4035 return ctx
->persp_centroid
;
4036 else if (location
== INTERP_SAMPLE
)
4037 return ctx
->persp_sample
;
4039 case INTERP_MODE_NOPERSPECTIVE
:
4040 if (location
== INTERP_CENTER
)
4041 return ctx
->linear_center
;
4042 else if (location
== INTERP_CENTROID
)
4043 return ctx
->linear_centroid
;
4044 else if (location
== INTERP_SAMPLE
)
4045 return ctx
->linear_sample
;
4051 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
4052 LLVMValueRef sample_id
)
4054 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4056 LLVMValueRef result
;
4057 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
4059 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
4060 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
4062 sample_id
= LLVMBuildAdd(ctx
->ac
.builder
, sample_id
, ctx
->sample_pos_offset
, "");
4063 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
4068 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
4070 LLVMValueRef values
[2];
4071 LLVMValueRef pos
[2];
4073 pos
[0] = ac_to_float(&ctx
->ac
, ctx
->abi
->frag_pos
[0]);
4074 pos
[1] = ac_to_float(&ctx
->ac
, ctx
->abi
->frag_pos
[1]);
4076 values
[0] = ac_build_fract(&ctx
->ac
, pos
[0], 32);
4077 values
[1] = ac_build_fract(&ctx
->ac
, pos
[1], 32);
4078 return ac_build_gather_values(&ctx
->ac
, values
, 2);
4081 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
4083 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4084 uint8_t log2_ps_iter_samples
= ctx
->shader_info
->info
.ps
.force_persample
?
4085 ctx
->options
->key
.fs
.log2_num_samples
:
4086 ctx
->options
->key
.fs
.log2_ps_iter_samples
;
4088 /* The bit pattern matches that used by fixed function fragment
4090 static const uint16_t ps_iter_masks
[] = {
4091 0xffff, /* not used */
4097 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
4099 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
4101 LLVMValueRef result
, sample_id
;
4102 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
4103 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
4104 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
4108 static LLVMValueRef
visit_interp(struct ac_nir_context
*ctx
,
4109 const nir_intrinsic_instr
*instr
)
4111 LLVMValueRef result
[4];
4112 LLVMValueRef interp_param
, attr_number
;
4115 LLVMValueRef src_c0
= NULL
;
4116 LLVMValueRef src_c1
= NULL
;
4117 LLVMValueRef src0
= NULL
;
4118 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
4119 switch (instr
->intrinsic
) {
4120 case nir_intrinsic_interp_var_at_centroid
:
4121 location
= INTERP_CENTROID
;
4123 case nir_intrinsic_interp_var_at_sample
:
4124 case nir_intrinsic_interp_var_at_offset
:
4125 location
= INTERP_CENTER
;
4126 src0
= get_src(ctx
, instr
->src
[0]);
4132 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
4133 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, ctx
->ac
.i32_0
, ""));
4134 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, ctx
->ac
.i32_1
, ""));
4135 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
4136 LLVMValueRef sample_position
;
4137 LLVMValueRef halfval
= LLVMConstReal(ctx
->ac
.f32
, 0.5f
);
4139 /* fetch sample ID */
4140 sample_position
= ctx
->abi
->load_sample_position(ctx
->abi
, src0
);
4142 src_c0
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
, ctx
->ac
.i32_0
, "");
4143 src_c0
= LLVMBuildFSub(ctx
->ac
.builder
, src_c0
, halfval
, "");
4144 src_c1
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
, ctx
->ac
.i32_1
, "");
4145 src_c1
= LLVMBuildFSub(ctx
->ac
.builder
, src_c1
, halfval
, "");
4147 interp_param
= ctx
->abi
->lookup_interp_param(ctx
->abi
, instr
->variables
[0]->var
->data
.interpolation
, location
);
4148 attr_number
= LLVMConstInt(ctx
->ac
.i32
, input_index
, false);
4150 if (location
== INTERP_CENTER
) {
4151 LLVMValueRef ij_out
[2];
4152 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
, interp_param
);
4155 * take the I then J parameters, and the DDX/Y for it, and
4156 * calculate the IJ inputs for the interpolator.
4157 * temp1 = ddx * offset/sample.x + I;
4158 * interp_param.I = ddy * offset/sample.y + temp1;
4159 * temp1 = ddx * offset/sample.x + J;
4160 * interp_param.J = ddy * offset/sample.y + temp1;
4162 for (unsigned i
= 0; i
< 2; i
++) {
4163 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->ac
.i32
, i
, false);
4164 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->ac
.i32
, i
+ 2, false);
4165 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4166 ddxy_out
, ix_ll
, "");
4167 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4168 ddxy_out
, iy_ll
, "");
4169 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4170 interp_param
, ix_ll
, "");
4171 LLVMValueRef temp1
, temp2
;
4173 interp_el
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_el
,
4176 temp1
= LLVMBuildFMul(ctx
->ac
.builder
, ddx_el
, src_c0
, "");
4177 temp1
= LLVMBuildFAdd(ctx
->ac
.builder
, temp1
, interp_el
, "");
4179 temp2
= LLVMBuildFMul(ctx
->ac
.builder
, ddy_el
, src_c1
, "");
4180 temp2
= LLVMBuildFAdd(ctx
->ac
.builder
, temp2
, temp1
, "");
4182 ij_out
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
,
4183 temp2
, ctx
->ac
.i32
, "");
4185 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4189 for (chan
= 0; chan
< 4; chan
++) {
4190 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
4193 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
,
4194 interp_param
, ctx
->ac
.v2f32
, "");
4195 LLVMValueRef i
= LLVMBuildExtractElement(
4196 ctx
->ac
.builder
, interp_param
, ctx
->ac
.i32_0
, "");
4197 LLVMValueRef j
= LLVMBuildExtractElement(
4198 ctx
->ac
.builder
, interp_param
, ctx
->ac
.i32_1
, "");
4200 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
4201 llvm_chan
, attr_number
,
4202 ctx
->abi
->prim_mask
, i
, j
);
4204 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
4205 LLVMConstInt(ctx
->ac
.i32
, 2, false),
4206 llvm_chan
, attr_number
,
4207 ctx
->abi
->prim_mask
);
4210 return ac_build_varying_gather_values(&ctx
->ac
, result
, instr
->num_components
,
4211 instr
->variables
[0]->var
->data
.location_frac
);
4215 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
4217 LLVMValueRef gs_next_vertex
;
4218 LLVMValueRef can_emit
;
4220 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4222 assert(stream
== 0);
4224 /* Write vertex attribute values to GSVS ring */
4225 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
4226 ctx
->gs_next_vertex
,
4229 /* If this thread has already emitted the declared maximum number of
4230 * vertices, kill it: excessive vertex emissions are not supposed to
4231 * have any effect, and GS threads have no externally observable
4232 * effects other than emitting vertices.
4234 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
4235 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
4236 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4238 /* loop num outputs */
4240 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4241 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
4246 if (!(ctx
->output_mask
& (1ull << i
)))
4249 if (i
== VARYING_SLOT_CLIP_DIST0
) {
4250 /* pack clip and cull into a single set of slots */
4251 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4255 for (unsigned j
= 0; j
< length
; j
++) {
4256 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
4258 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4259 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
4260 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4262 out_val
= LLVMBuildBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
4264 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4266 voffset
, ctx
->gs2vs_offset
, 0,
4272 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
4274 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4276 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4280 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
4282 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4283 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
4287 load_tess_coord(struct ac_shader_abi
*abi
)
4289 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4291 LLVMValueRef coord
[4] = {
4298 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4299 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
4300 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
4302 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
4306 load_patch_vertices_in(struct ac_shader_abi
*abi
)
4308 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4309 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
4312 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4313 nir_intrinsic_instr
*instr
)
4315 LLVMValueRef result
= NULL
;
4317 switch (instr
->intrinsic
) {
4318 case nir_intrinsic_ballot
:
4319 result
= ac_build_ballot(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4321 case nir_intrinsic_read_invocation
:
4322 case nir_intrinsic_read_first_invocation
: {
4323 LLVMValueRef args
[2];
4326 args
[0] = get_src(ctx
, instr
->src
[0]);
4329 const char *intr_name
;
4330 if (instr
->intrinsic
== nir_intrinsic_read_invocation
) {
4332 intr_name
= "llvm.amdgcn.readlane";
4335 args
[1] = get_src(ctx
, instr
->src
[1]);
4338 intr_name
= "llvm.amdgcn.readfirstlane";
4341 /* We currently have no other way to prevent LLVM from lifting the icmp
4342 * calls to a dominating basic block.
4344 ac_build_optimization_barrier(&ctx
->ac
, &args
[0]);
4346 result
= ac_build_intrinsic(&ctx
->ac
, intr_name
,
4347 ctx
->ac
.i32
, args
, num_args
,
4348 AC_FUNC_ATTR_READNONE
|
4349 AC_FUNC_ATTR_CONVERGENT
);
4352 case nir_intrinsic_load_subgroup_invocation
:
4353 result
= ac_get_thread_id(&ctx
->ac
);
4355 case nir_intrinsic_load_work_group_id
: {
4356 LLVMValueRef values
[3];
4358 for (int i
= 0; i
< 3; i
++) {
4359 values
[i
] = ctx
->abi
->workgroup_ids
[i
] ?
4360 ctx
->abi
->workgroup_ids
[i
] : ctx
->ac
.i32_0
;
4363 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
4366 case nir_intrinsic_load_base_vertex
: {
4367 result
= ctx
->abi
->load_base_vertex(ctx
->abi
);
4370 case nir_intrinsic_load_local_group_size
:
4371 result
= ctx
->abi
->load_local_group_size(ctx
->abi
);
4373 case nir_intrinsic_load_vertex_id
:
4374 result
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
->vertex_id
,
4375 ctx
->abi
->base_vertex
, "");
4377 case nir_intrinsic_load_vertex_id_zero_base
: {
4378 result
= ctx
->abi
->vertex_id
;
4381 case nir_intrinsic_load_local_invocation_id
: {
4382 result
= ctx
->abi
->local_invocation_ids
;
4385 case nir_intrinsic_load_base_instance
:
4386 result
= ctx
->abi
->start_instance
;
4388 case nir_intrinsic_load_draw_id
:
4389 result
= ctx
->abi
->draw_id
;
4391 case nir_intrinsic_load_view_index
:
4392 result
= ctx
->abi
->view_index
;
4394 case nir_intrinsic_load_invocation_id
:
4395 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4396 result
= ac_unpack_param(&ctx
->ac
, ctx
->abi
->tcs_rel_ids
, 8, 5);
4398 result
= ctx
->abi
->gs_invocation_id
;
4400 case nir_intrinsic_load_primitive_id
:
4401 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4402 result
= ctx
->abi
->gs_prim_id
;
4403 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4404 result
= ctx
->abi
->tcs_patch_id
;
4405 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4406 result
= ctx
->abi
->tes_patch_id
;
4408 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4410 case nir_intrinsic_load_sample_id
:
4411 result
= ac_unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4413 case nir_intrinsic_load_sample_pos
:
4414 result
= load_sample_pos(ctx
);
4416 case nir_intrinsic_load_sample_mask_in
:
4417 result
= ctx
->abi
->load_sample_mask_in(ctx
->abi
);
4419 case nir_intrinsic_load_frag_coord
: {
4420 LLVMValueRef values
[4] = {
4421 ctx
->abi
->frag_pos
[0],
4422 ctx
->abi
->frag_pos
[1],
4423 ctx
->abi
->frag_pos
[2],
4424 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4426 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4429 case nir_intrinsic_load_front_face
:
4430 result
= ctx
->abi
->front_face
;
4432 case nir_intrinsic_load_helper_invocation
:
4433 result
= visit_load_helper_invocation(ctx
);
4435 case nir_intrinsic_load_instance_id
:
4436 result
= ctx
->abi
->instance_id
;
4438 case nir_intrinsic_load_num_work_groups
:
4439 result
= ctx
->abi
->num_work_groups
;
4441 case nir_intrinsic_load_local_invocation_index
:
4442 result
= visit_load_local_invocation_index(ctx
);
4444 case nir_intrinsic_load_subgroup_id
:
4445 result
= visit_load_subgroup_id(ctx
);
4447 case nir_intrinsic_load_num_subgroups
:
4448 result
= visit_load_num_subgroups(ctx
);
4450 case nir_intrinsic_first_invocation
:
4451 result
= visit_first_invocation(ctx
);
4453 case nir_intrinsic_load_push_constant
:
4454 result
= visit_load_push_constant(ctx
, instr
);
4456 case nir_intrinsic_vulkan_resource_index
: {
4457 LLVMValueRef index
= get_src(ctx
, instr
->src
[0]);
4458 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4459 unsigned binding
= nir_intrinsic_binding(instr
);
4461 result
= ctx
->abi
->load_resource(ctx
->abi
, index
, desc_set
,
4465 case nir_intrinsic_vulkan_resource_reindex
:
4466 result
= visit_vulkan_resource_reindex(ctx
, instr
);
4468 case nir_intrinsic_store_ssbo
:
4469 visit_store_ssbo(ctx
, instr
);
4471 case nir_intrinsic_load_ssbo
:
4472 result
= visit_load_buffer(ctx
, instr
);
4474 case nir_intrinsic_ssbo_atomic_add
:
4475 case nir_intrinsic_ssbo_atomic_imin
:
4476 case nir_intrinsic_ssbo_atomic_umin
:
4477 case nir_intrinsic_ssbo_atomic_imax
:
4478 case nir_intrinsic_ssbo_atomic_umax
:
4479 case nir_intrinsic_ssbo_atomic_and
:
4480 case nir_intrinsic_ssbo_atomic_or
:
4481 case nir_intrinsic_ssbo_atomic_xor
:
4482 case nir_intrinsic_ssbo_atomic_exchange
:
4483 case nir_intrinsic_ssbo_atomic_comp_swap
:
4484 result
= visit_atomic_ssbo(ctx
, instr
);
4486 case nir_intrinsic_load_ubo
:
4487 result
= visit_load_ubo_buffer(ctx
, instr
);
4489 case nir_intrinsic_get_buffer_size
:
4490 result
= visit_get_buffer_size(ctx
, instr
);
4492 case nir_intrinsic_load_var
:
4493 result
= visit_load_var(ctx
, instr
);
4495 case nir_intrinsic_store_var
:
4496 visit_store_var(ctx
, instr
);
4498 case nir_intrinsic_load_shared
:
4499 result
= visit_load_shared(ctx
, instr
);
4501 case nir_intrinsic_store_shared
:
4502 visit_store_shared(ctx
, instr
);
4504 case nir_intrinsic_image_samples
:
4505 result
= visit_image_samples(ctx
, instr
);
4507 case nir_intrinsic_image_load
:
4508 result
= visit_image_load(ctx
, instr
);
4510 case nir_intrinsic_image_store
:
4511 visit_image_store(ctx
, instr
);
4513 case nir_intrinsic_image_atomic_add
:
4514 case nir_intrinsic_image_atomic_min
:
4515 case nir_intrinsic_image_atomic_max
:
4516 case nir_intrinsic_image_atomic_and
:
4517 case nir_intrinsic_image_atomic_or
:
4518 case nir_intrinsic_image_atomic_xor
:
4519 case nir_intrinsic_image_atomic_exchange
:
4520 case nir_intrinsic_image_atomic_comp_swap
:
4521 result
= visit_image_atomic(ctx
, instr
);
4523 case nir_intrinsic_image_size
:
4524 result
= visit_image_size(ctx
, instr
);
4526 case nir_intrinsic_shader_clock
:
4527 result
= ac_build_shader_clock(&ctx
->ac
);
4529 case nir_intrinsic_discard
:
4530 case nir_intrinsic_discard_if
:
4531 emit_discard(ctx
, instr
);
4533 case nir_intrinsic_memory_barrier
:
4534 case nir_intrinsic_group_memory_barrier
:
4535 case nir_intrinsic_memory_barrier_atomic_counter
:
4536 case nir_intrinsic_memory_barrier_buffer
:
4537 case nir_intrinsic_memory_barrier_image
:
4538 case nir_intrinsic_memory_barrier_shared
:
4539 emit_membar(&ctx
->ac
, instr
);
4541 case nir_intrinsic_barrier
:
4542 emit_barrier(&ctx
->ac
, ctx
->stage
);
4544 case nir_intrinsic_shared_atomic_add
:
4545 case nir_intrinsic_shared_atomic_imin
:
4546 case nir_intrinsic_shared_atomic_umin
:
4547 case nir_intrinsic_shared_atomic_imax
:
4548 case nir_intrinsic_shared_atomic_umax
:
4549 case nir_intrinsic_shared_atomic_and
:
4550 case nir_intrinsic_shared_atomic_or
:
4551 case nir_intrinsic_shared_atomic_xor
:
4552 case nir_intrinsic_shared_atomic_exchange
:
4553 case nir_intrinsic_shared_atomic_comp_swap
: {
4554 LLVMValueRef ptr
= get_memory_ptr(ctx
, instr
->src
[0]);
4555 result
= visit_var_atomic(ctx
, instr
, ptr
, 1);
4558 case nir_intrinsic_var_atomic_add
:
4559 case nir_intrinsic_var_atomic_imin
:
4560 case nir_intrinsic_var_atomic_umin
:
4561 case nir_intrinsic_var_atomic_imax
:
4562 case nir_intrinsic_var_atomic_umax
:
4563 case nir_intrinsic_var_atomic_and
:
4564 case nir_intrinsic_var_atomic_or
:
4565 case nir_intrinsic_var_atomic_xor
:
4566 case nir_intrinsic_var_atomic_exchange
:
4567 case nir_intrinsic_var_atomic_comp_swap
: {
4568 LLVMValueRef ptr
= build_gep_for_deref(ctx
, instr
->variables
[0]);
4569 result
= visit_var_atomic(ctx
, instr
, ptr
, 0);
4572 case nir_intrinsic_interp_var_at_centroid
:
4573 case nir_intrinsic_interp_var_at_sample
:
4574 case nir_intrinsic_interp_var_at_offset
:
4575 result
= visit_interp(ctx
, instr
);
4577 case nir_intrinsic_emit_vertex
:
4578 ctx
->abi
->emit_vertex(ctx
->abi
, nir_intrinsic_stream_id(instr
), ctx
->abi
->outputs
);
4580 case nir_intrinsic_end_primitive
:
4581 ctx
->abi
->emit_primitive(ctx
->abi
, nir_intrinsic_stream_id(instr
));
4583 case nir_intrinsic_load_tess_coord
:
4584 result
= ctx
->abi
->load_tess_coord(ctx
->abi
);
4586 case nir_intrinsic_load_tess_level_outer
:
4587 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_OUTER
);
4589 case nir_intrinsic_load_tess_level_inner
:
4590 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_INNER
);
4592 case nir_intrinsic_load_patch_vertices_in
:
4593 result
= ctx
->abi
->load_patch_vertices_in(ctx
->abi
);
4595 case nir_intrinsic_vote_all
: {
4596 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4597 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4600 case nir_intrinsic_vote_any
: {
4601 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4602 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4606 fprintf(stderr
, "Unknown intrinsic: ");
4607 nir_print_instr(&instr
->instr
, stderr
);
4608 fprintf(stderr
, "\n");
4612 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4616 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
4618 return abi
->base_vertex
;
4621 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4622 LLVMValueRef buffer_ptr
, bool write
)
4624 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4625 LLVMValueRef result
;
4627 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4629 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
4630 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4635 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
4637 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4638 LLVMValueRef result
;
4640 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4642 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
4643 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4648 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4649 unsigned descriptor_set
,
4650 unsigned base_index
,
4651 unsigned constant_index
,
4653 enum ac_descriptor_type desc_type
,
4654 bool image
, bool write
)
4656 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4657 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4658 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4659 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4660 unsigned offset
= binding
->offset
;
4661 unsigned stride
= binding
->size
;
4663 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4666 assert(base_index
< layout
->binding_count
);
4668 switch (desc_type
) {
4670 type
= ctx
->ac
.v8i32
;
4674 type
= ctx
->ac
.v8i32
;
4678 case AC_DESC_SAMPLER
:
4679 type
= ctx
->ac
.v4i32
;
4680 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4685 case AC_DESC_BUFFER
:
4686 type
= ctx
->ac
.v4i32
;
4690 unreachable("invalid desc_type\n");
4693 offset
+= constant_index
* stride
;
4695 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4696 (!index
|| binding
->immutable_samplers_equal
)) {
4697 if (binding
->immutable_samplers_equal
)
4700 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4702 LLVMValueRef constants
[] = {
4703 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
4704 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
4705 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
4706 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
4708 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4711 assert(stride
% type_size
== 0);
4714 index
= ctx
->ac
.i32_0
;
4716 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
4718 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
4719 list
= LLVMBuildPointerCast(builder
, list
, ac_array_in_const_addr_space(type
), "");
4721 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4724 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4725 const nir_deref_var
*deref
,
4726 enum ac_descriptor_type desc_type
,
4727 const nir_tex_instr
*tex_instr
,
4728 bool image
, bool write
)
4730 LLVMValueRef index
= NULL
;
4731 unsigned constant_index
= 0;
4732 unsigned descriptor_set
;
4733 unsigned base_index
;
4736 assert(tex_instr
&& !image
);
4738 base_index
= tex_instr
->sampler_index
;
4740 const nir_deref
*tail
= &deref
->deref
;
4741 while (tail
->child
) {
4742 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4743 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4748 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4750 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4751 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4753 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4754 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4759 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4762 constant_index
+= child
->base_offset
* array_size
;
4764 tail
= &child
->deref
;
4766 descriptor_set
= deref
->var
->data
.descriptor_set
;
4767 base_index
= deref
->var
->data
.binding
;
4770 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4773 constant_index
, index
,
4774 desc_type
, image
, write
);
4777 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4778 struct ac_image_args
*args
,
4779 const nir_tex_instr
*instr
,
4781 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4782 LLVMValueRef
*param
, unsigned count
,
4785 unsigned is_rect
= 0;
4786 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4788 if (op
== nir_texop_lod
)
4790 /* Pad to power of two vector */
4791 while (count
< util_next_power_of_two(count
))
4792 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4795 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4797 args
->addr
= param
[0];
4799 args
->resource
= res_ptr
;
4800 args
->sampler
= samp_ptr
;
4802 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4803 args
->addr
= param
[0];
4807 args
->dmask
= dmask
;
4808 args
->unorm
= is_rect
;
4812 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4815 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4816 * filtering manually. The driver sets img7 to a mask clearing
4817 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4818 * s_and_b32 samp0, samp0, img7
4821 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4823 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4824 LLVMValueRef res
, LLVMValueRef samp
)
4826 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4827 LLVMValueRef img7
, samp0
;
4829 if (ctx
->ac
.chip_class
>= VI
)
4832 img7
= LLVMBuildExtractElement(builder
, res
,
4833 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4834 samp0
= LLVMBuildExtractElement(builder
, samp
,
4835 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4836 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4837 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4838 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4841 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4842 nir_tex_instr
*instr
,
4843 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4844 LLVMValueRef
*fmask_ptr
)
4846 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4847 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, instr
, false, false);
4849 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, instr
, false, false);
4852 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, instr
, false, false);
4854 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, instr
, false, false);
4855 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4856 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4858 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4859 instr
->op
== nir_texop_samples_identical
))
4860 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, instr
, false, false);
4863 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4866 coord
= ac_to_float(ctx
, coord
);
4867 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4868 coord
= ac_to_integer(ctx
, coord
);
4872 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4874 LLVMValueRef result
= NULL
;
4875 struct ac_image_args args
= { 0 };
4876 unsigned dmask
= 0xf;
4877 LLVMValueRef address
[16];
4878 LLVMValueRef coords
[5];
4879 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4880 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4881 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4882 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4883 LLVMValueRef derivs
[6];
4884 unsigned chan
, count
= 0;
4885 unsigned const_src
= 0, num_deriv_comp
= 0;
4886 bool lod_is_zero
= false;
4888 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4890 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4891 switch (instr
->src
[i
].src_type
) {
4892 case nir_tex_src_coord
:
4893 coord
= get_src(ctx
, instr
->src
[i
].src
);
4895 case nir_tex_src_projector
:
4897 case nir_tex_src_comparator
:
4898 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4900 case nir_tex_src_offset
:
4901 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4904 case nir_tex_src_bias
:
4905 bias
= get_src(ctx
, instr
->src
[i
].src
);
4907 case nir_tex_src_lod
: {
4908 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4910 if (val
&& val
->i32
[0] == 0)
4912 lod
= get_src(ctx
, instr
->src
[i
].src
);
4915 case nir_tex_src_ms_index
:
4916 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4918 case nir_tex_src_ms_mcs
:
4920 case nir_tex_src_ddx
:
4921 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4922 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4924 case nir_tex_src_ddy
:
4925 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4927 case nir_tex_src_texture_offset
:
4928 case nir_tex_src_sampler_offset
:
4929 case nir_tex_src_plane
:
4935 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4936 result
= get_buffer_size(ctx
, res_ptr
, true);
4940 if (instr
->op
== nir_texop_texture_samples
) {
4941 LLVMValueRef res
, samples
, is_msaa
;
4942 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4943 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4944 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4945 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4946 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4947 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4948 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4949 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4950 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4952 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4953 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4954 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4955 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
4956 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
4958 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
4965 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4966 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, coord
, chan
);
4968 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4969 LLVMValueRef offset
[3], pack
;
4970 for (chan
= 0; chan
< 3; ++chan
)
4971 offset
[chan
] = ctx
->ac
.i32_0
;
4974 for (chan
= 0; chan
< ac_get_llvm_num_components(offsets
); chan
++) {
4975 offset
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
4976 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
4977 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
4979 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
4980 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
4982 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
4983 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
4984 address
[count
++] = pack
;
4987 /* pack LOD bias value */
4988 if (instr
->op
== nir_texop_txb
&& bias
) {
4989 address
[count
++] = bias
;
4992 /* Pack depth comparison value */
4993 if (instr
->is_shadow
&& comparator
) {
4994 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
4995 ac_llvm_extract_elem(&ctx
->ac
, comparator
, 0));
4997 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4998 * so the depth comparison value isn't clamped for Z16 and
4999 * Z24 anymore. Do it manually here.
5001 * It's unnecessary if the original texture format was
5002 * Z32_FLOAT, but we don't know that here.
5004 if (ctx
->ac
.chip_class
== VI
&& ctx
->abi
->clamp_shadow_reference
)
5005 z
= ac_build_clamp(&ctx
->ac
, z
);
5007 address
[count
++] = z
;
5010 /* pack derivatives */
5012 int num_src_deriv_channels
, num_dest_deriv_channels
;
5013 switch (instr
->sampler_dim
) {
5014 case GLSL_SAMPLER_DIM_3D
:
5015 case GLSL_SAMPLER_DIM_CUBE
:
5017 num_src_deriv_channels
= 3;
5018 num_dest_deriv_channels
= 3;
5020 case GLSL_SAMPLER_DIM_2D
:
5022 num_src_deriv_channels
= 2;
5023 num_dest_deriv_channels
= 2;
5026 case GLSL_SAMPLER_DIM_1D
:
5027 num_src_deriv_channels
= 1;
5028 if (ctx
->ac
.chip_class
>= GFX9
) {
5029 num_dest_deriv_channels
= 2;
5032 num_dest_deriv_channels
= 1;
5038 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
5039 derivs
[i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddx
, i
));
5040 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddy
, i
));
5042 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
5043 derivs
[i
] = ctx
->ac
.f32_0
;
5044 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
5048 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
5049 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
5050 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
5051 if (instr
->coord_components
== 3)
5052 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5053 ac_prepare_cube_coords(&ctx
->ac
,
5054 instr
->op
== nir_texop_txd
, instr
->is_array
,
5055 instr
->op
== nir_texop_lod
, coords
, derivs
);
5061 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
5062 address
[count
++] = derivs
[i
];
5065 /* Pack texture coordinates */
5067 address
[count
++] = coords
[0];
5068 if (instr
->coord_components
> 1) {
5069 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
5070 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
5072 address
[count
++] = coords
[1];
5074 if (instr
->coord_components
> 2) {
5075 if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
5076 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
5077 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
5078 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
5080 instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
5081 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
5083 address
[count
++] = coords
[2];
5086 if (ctx
->ac
.chip_class
>= GFX9
) {
5087 LLVMValueRef filler
;
5088 if (instr
->op
== nir_texop_txf
)
5089 filler
= ctx
->ac
.i32_0
;
5091 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
5093 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
5094 /* No nir_texop_lod, because it does not take a slice
5095 * even with array textures. */
5096 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
5097 address
[count
] = address
[count
- 1];
5098 address
[count
- 1] = filler
;
5101 address
[count
++] = filler
;
5107 if (lod
&& ((instr
->op
== nir_texop_txl
|| instr
->op
== nir_texop_txf
) && !lod_is_zero
)) {
5108 address
[count
++] = lod
;
5109 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
5110 address
[count
++] = sample_index
;
5111 } else if(instr
->op
== nir_texop_txs
) {
5114 address
[count
++] = lod
;
5116 address
[count
++] = ctx
->ac
.i32_0
;
5119 for (chan
= 0; chan
< count
; chan
++) {
5120 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
5121 address
[chan
], ctx
->ac
.i32
, "");
5124 if (instr
->op
== nir_texop_samples_identical
) {
5125 LLVMValueRef txf_address
[4];
5126 struct ac_image_args txf_args
= { 0 };
5127 unsigned txf_count
= count
;
5128 memcpy(txf_address
, address
, sizeof(txf_address
));
5130 if (!instr
->is_array
)
5131 txf_address
[2] = ctx
->ac
.i32_0
;
5132 txf_address
[3] = ctx
->ac
.i32_0
;
5134 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
5136 txf_address
, txf_count
, 0xf);
5138 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
5140 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5141 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
5145 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
5146 instr
->op
!= nir_texop_txs
) {
5147 unsigned sample_chan
= instr
->is_array
? 3 : 2;
5148 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
5151 instr
->is_array
? address
[2] : NULL
,
5152 address
[sample_chan
],
5156 if (offsets
&& instr
->op
== nir_texop_txf
) {
5157 nir_const_value
*const_offset
=
5158 nir_src_as_const_value(instr
->src
[const_src
].src
);
5159 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
5160 assert(const_offset
);
5161 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
5162 if (num_offsets
> 2)
5163 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
5164 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
5165 if (num_offsets
> 1)
5166 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
5167 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
5168 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
5169 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
5173 /* TODO TG4 support */
5174 if (instr
->op
== nir_texop_tg4
) {
5175 if (instr
->is_shadow
)
5178 dmask
= 1 << instr
->component
;
5180 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
5181 res_ptr
, samp_ptr
, address
, count
, dmask
);
5183 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
5185 if (instr
->op
== nir_texop_query_levels
)
5186 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
5187 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
5188 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
5189 instr
->op
!= nir_texop_tg4
)
5190 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5191 else if (instr
->op
== nir_texop_txs
&&
5192 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
5194 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5195 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
5196 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5197 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
5198 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
5199 } else if (ctx
->ac
.chip_class
>= GFX9
&&
5200 instr
->op
== nir_texop_txs
&&
5201 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
5203 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5204 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5205 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
5207 } else if (instr
->dest
.ssa
.num_components
!= 4)
5208 result
= ac_trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
5212 assert(instr
->dest
.is_ssa
);
5213 result
= ac_to_integer(&ctx
->ac
, result
);
5214 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5219 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
5221 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
5222 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
5224 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5225 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
5228 static void visit_post_phi(struct ac_nir_context
*ctx
,
5229 nir_phi_instr
*instr
,
5230 LLVMValueRef llvm_phi
)
5232 nir_foreach_phi_src(src
, instr
) {
5233 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
5234 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
5236 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
5240 static void phi_post_pass(struct ac_nir_context
*ctx
)
5242 struct hash_entry
*entry
;
5243 hash_table_foreach(ctx
->phis
, entry
) {
5244 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
5245 (LLVMValueRef
)entry
->data
);
5250 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
5251 const nir_ssa_undef_instr
*instr
)
5253 unsigned num_components
= instr
->def
.num_components
;
5254 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
5257 if (num_components
== 1)
5258 undef
= LLVMGetUndef(type
);
5260 undef
= LLVMGetUndef(LLVMVectorType(type
, num_components
));
5262 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
5265 static void visit_jump(struct ac_llvm_context
*ctx
,
5266 const nir_jump_instr
*instr
)
5268 switch (instr
->type
) {
5269 case nir_jump_break
:
5270 ac_build_break(ctx
);
5272 case nir_jump_continue
:
5273 ac_build_continue(ctx
);
5276 fprintf(stderr
, "Unknown NIR jump instr: ");
5277 nir_print_instr(&instr
->instr
, stderr
);
5278 fprintf(stderr
, "\n");
5283 static void visit_cf_list(struct ac_nir_context
*ctx
,
5284 struct exec_list
*list
);
5286 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
5288 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
5289 nir_foreach_instr(instr
, block
)
5291 switch (instr
->type
) {
5292 case nir_instr_type_alu
:
5293 visit_alu(ctx
, nir_instr_as_alu(instr
));
5295 case nir_instr_type_load_const
:
5296 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
5298 case nir_instr_type_intrinsic
:
5299 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
5301 case nir_instr_type_tex
:
5302 visit_tex(ctx
, nir_instr_as_tex(instr
));
5304 case nir_instr_type_phi
:
5305 visit_phi(ctx
, nir_instr_as_phi(instr
));
5307 case nir_instr_type_ssa_undef
:
5308 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
5310 case nir_instr_type_jump
:
5311 visit_jump(&ctx
->ac
, nir_instr_as_jump(instr
));
5314 fprintf(stderr
, "Unknown NIR instr type: ");
5315 nir_print_instr(instr
, stderr
);
5316 fprintf(stderr
, "\n");
5321 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
5324 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
5326 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
5328 nir_block
*then_block
=
5329 (nir_block
*) exec_list_get_head(&if_stmt
->then_list
);
5331 ac_build_uif(&ctx
->ac
, value
, then_block
->index
);
5333 visit_cf_list(ctx
, &if_stmt
->then_list
);
5335 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
5336 nir_block
*else_block
=
5337 (nir_block
*) exec_list_get_head(&if_stmt
->else_list
);
5339 ac_build_else(&ctx
->ac
, else_block
->index
);
5340 visit_cf_list(ctx
, &if_stmt
->else_list
);
5343 ac_build_endif(&ctx
->ac
, then_block
->index
);
5346 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
5348 nir_block
*first_loop_block
=
5349 (nir_block
*) exec_list_get_head(&loop
->body
);
5351 ac_build_bgnloop(&ctx
->ac
, first_loop_block
->index
);
5353 visit_cf_list(ctx
, &loop
->body
);
5355 ac_build_endloop(&ctx
->ac
, first_loop_block
->index
);
5358 static void visit_cf_list(struct ac_nir_context
*ctx
,
5359 struct exec_list
*list
)
5361 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5363 switch (node
->type
) {
5364 case nir_cf_node_block
:
5365 visit_block(ctx
, nir_cf_node_as_block(node
));
5368 case nir_cf_node_if
:
5369 visit_if(ctx
, nir_cf_node_as_if(node
));
5372 case nir_cf_node_loop
:
5373 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5383 handle_vs_input_decl(struct radv_shader_context
*ctx
,
5384 struct nir_variable
*variable
)
5386 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5387 LLVMValueRef t_offset
;
5388 LLVMValueRef t_list
;
5390 LLVMValueRef buffer_index
;
5391 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5392 int idx
= variable
->data
.location
;
5393 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5394 uint8_t input_usage_mask
=
5395 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
5396 unsigned num_channels
= util_last_bit(input_usage_mask
);
5398 variable
->data
.driver_location
= idx
* 4;
5400 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5401 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << (index
+ i
))) {
5402 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.instance_id
,
5403 ctx
->abi
.start_instance
, "");
5404 if (ctx
->options
->key
.vs
.as_ls
) {
5405 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5406 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5408 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5409 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5412 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
5413 ctx
->abi
.base_vertex
, "");
5414 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
5416 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5418 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5421 num_channels
, false, true);
5423 input
= ac_build_expand_to_vec4(&ctx
->ac
, input
, num_channels
);
5425 for (unsigned chan
= 0; chan
< 4; chan
++) {
5426 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5427 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5428 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
,
5429 input
, llvm_chan
, ""));
5434 static void interp_fs_input(struct radv_shader_context
*ctx
,
5436 LLVMValueRef interp_param
,
5437 LLVMValueRef prim_mask
,
5438 LLVMValueRef result
[4])
5440 LLVMValueRef attr_number
;
5443 bool interp
= interp_param
!= NULL
;
5445 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
5447 /* fs.constant returns the param from the middle vertex, so it's not
5448 * really useful for flat shading. It's meant to be used for custom
5449 * interpolation (but the intrinsic can't fetch from the other two
5452 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5453 * to do the right thing. The only reason we use fs.constant is that
5454 * fs.interp cannot be used on integers, because they can be equal
5458 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
5461 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
5463 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
5467 for (chan
= 0; chan
< 4; chan
++) {
5468 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5471 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5476 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5477 LLVMConstInt(ctx
->ac
.i32
, 2, false),
5486 handle_fs_input_decl(struct radv_shader_context
*ctx
,
5487 struct nir_variable
*variable
)
5489 int idx
= variable
->data
.location
;
5490 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5491 LLVMValueRef interp
;
5493 variable
->data
.driver_location
= idx
* 4;
5494 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5496 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5497 unsigned interp_type
;
5498 if (variable
->data
.sample
)
5499 interp_type
= INTERP_SAMPLE
;
5500 else if (variable
->data
.centroid
)
5501 interp_type
= INTERP_CENTROID
;
5503 interp_type
= INTERP_CENTER
;
5505 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
5509 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5510 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5515 handle_vs_inputs(struct radv_shader_context
*ctx
,
5516 struct nir_shader
*nir
) {
5517 nir_foreach_variable(variable
, &nir
->inputs
)
5518 handle_vs_input_decl(ctx
, variable
);
5522 prepare_interp_optimize(struct radv_shader_context
*ctx
,
5523 struct nir_shader
*nir
)
5525 if (!ctx
->options
->key
.fs
.multisample
)
5528 bool uses_center
= false;
5529 bool uses_centroid
= false;
5530 nir_foreach_variable(variable
, &nir
->inputs
) {
5531 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5532 variable
->data
.sample
)
5535 if (variable
->data
.centroid
)
5536 uses_centroid
= true;
5541 if (uses_center
&& uses_centroid
) {
5542 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
5543 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5544 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5549 handle_fs_inputs(struct radv_shader_context
*ctx
,
5550 struct nir_shader
*nir
)
5552 prepare_interp_optimize(ctx
, nir
);
5554 nir_foreach_variable(variable
, &nir
->inputs
)
5555 handle_fs_input_decl(ctx
, variable
);
5559 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5560 ctx
->shader_info
->info
.needs_multiview_view_index
)
5561 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5563 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5564 LLVMValueRef interp_param
;
5565 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5567 if (!(ctx
->input_mask
& (1ull << i
)))
5570 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5571 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5572 interp_param
= *inputs
;
5573 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
,
5577 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5579 } else if (i
== VARYING_SLOT_POS
) {
5580 for(int i
= 0; i
< 3; ++i
)
5581 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5583 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
5584 ctx
->abi
.frag_pos
[3]);
5587 ctx
->shader_info
->fs
.num_interp
= index
;
5588 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5590 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5591 ctx
->abi
.view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5595 scan_shader_output_decl(struct radv_shader_context
*ctx
,
5596 struct nir_variable
*variable
,
5597 struct nir_shader
*shader
,
5598 gl_shader_stage stage
)
5600 int idx
= variable
->data
.location
+ variable
->data
.index
;
5601 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5602 uint64_t mask_attribs
;
5604 variable
->data
.driver_location
= idx
* 4;
5606 /* tess ctrl has it's own load/store paths for outputs */
5607 if (stage
== MESA_SHADER_TESS_CTRL
)
5610 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5611 if (stage
== MESA_SHADER_VERTEX
||
5612 stage
== MESA_SHADER_TESS_EVAL
||
5613 stage
== MESA_SHADER_GEOMETRY
) {
5614 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5615 int length
= shader
->info
.clip_distance_array_size
+
5616 shader
->info
.cull_distance_array_size
;
5617 if (stage
== MESA_SHADER_VERTEX
) {
5618 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5619 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5621 if (stage
== MESA_SHADER_TESS_EVAL
) {
5622 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5623 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5630 mask_attribs
= 1ull << idx
;
5634 ctx
->output_mask
|= mask_attribs
;
5638 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5639 struct nir_shader
*nir
,
5640 struct nir_variable
*variable
)
5642 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5643 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5645 /* tess ctrl has it's own load/store paths for outputs */
5646 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5649 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5650 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5651 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5652 int idx
= variable
->data
.location
+ variable
->data
.index
;
5653 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5654 int length
= nir
->info
.clip_distance_array_size
+
5655 nir
->info
.cull_distance_array_size
;
5664 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5665 for (unsigned chan
= 0; chan
< 4; chan
++) {
5666 ctx
->abi
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5667 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5673 glsl_base_to_llvm_type(struct ac_llvm_context
*ac
,
5674 enum glsl_base_type type
)
5678 case GLSL_TYPE_UINT
:
5679 case GLSL_TYPE_BOOL
:
5680 case GLSL_TYPE_SUBROUTINE
:
5682 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5684 case GLSL_TYPE_INT64
:
5685 case GLSL_TYPE_UINT64
:
5687 case GLSL_TYPE_DOUBLE
:
5690 unreachable("unknown GLSL type");
5695 glsl_to_llvm_type(struct ac_llvm_context
*ac
,
5696 const struct glsl_type
*type
)
5698 if (glsl_type_is_scalar(type
)) {
5699 return glsl_base_to_llvm_type(ac
, glsl_get_base_type(type
));
5702 if (glsl_type_is_vector(type
)) {
5703 return LLVMVectorType(
5704 glsl_base_to_llvm_type(ac
, glsl_get_base_type(type
)),
5705 glsl_get_vector_elements(type
));
5708 if (glsl_type_is_matrix(type
)) {
5709 return LLVMArrayType(
5710 glsl_to_llvm_type(ac
, glsl_get_column_type(type
)),
5711 glsl_get_matrix_columns(type
));
5714 if (glsl_type_is_array(type
)) {
5715 return LLVMArrayType(
5716 glsl_to_llvm_type(ac
, glsl_get_array_element(type
)),
5717 glsl_get_length(type
));
5720 assert(glsl_type_is_struct(type
));
5722 LLVMTypeRef member_types
[glsl_get_length(type
)];
5724 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5726 glsl_to_llvm_type(ac
,
5727 glsl_get_struct_field(type
, i
));
5730 return LLVMStructTypeInContext(ac
->context
, member_types
,
5731 glsl_get_length(type
), false);
5735 setup_locals(struct ac_nir_context
*ctx
,
5736 struct nir_function
*func
)
5739 ctx
->num_locals
= 0;
5740 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5741 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5742 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5743 variable
->data
.location_frac
= 0;
5744 ctx
->num_locals
+= attrib_count
;
5746 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5750 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5751 for (j
= 0; j
< 4; j
++) {
5752 ctx
->locals
[i
* 4 + j
] =
5753 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5759 setup_shared(struct ac_nir_context
*ctx
,
5760 struct nir_shader
*nir
)
5762 nir_foreach_variable(variable
, &nir
->shared
) {
5763 LLVMValueRef shared
=
5764 LLVMAddGlobalInAddressSpace(
5765 ctx
->ac
.module
, glsl_to_llvm_type(&ctx
->ac
, variable
->type
),
5766 variable
->name
? variable
->name
: "",
5767 AC_LOCAL_ADDR_SPACE
);
5768 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5772 /* Initialize arguments for the shader export intrinsic */
5774 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
5775 LLVMValueRef
*values
,
5776 unsigned enabled_channels
,
5778 struct ac_export_args
*args
)
5780 /* Specify the channels that are enabled. */
5781 args
->enabled_channels
= enabled_channels
;
5783 /* Specify whether the EXEC mask represents the valid mask */
5784 args
->valid_mask
= 0;
5786 /* Specify whether this is the last export */
5789 /* Specify the target we are exporting */
5790 args
->target
= target
;
5792 args
->compr
= false;
5793 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
5794 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
5795 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
5796 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5798 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5799 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5800 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5801 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5802 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5805 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
5806 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
5807 unsigned bits
, bool hi
) = NULL
;
5809 switch(col_format
) {
5810 case V_028714_SPI_SHADER_ZERO
:
5811 args
->enabled_channels
= 0; /* writemask */
5812 args
->target
= V_008DFC_SQ_EXP_NULL
;
5815 case V_028714_SPI_SHADER_32_R
:
5816 args
->enabled_channels
= 1;
5817 args
->out
[0] = values
[0];
5820 case V_028714_SPI_SHADER_32_GR
:
5821 args
->enabled_channels
= 0x3;
5822 args
->out
[0] = values
[0];
5823 args
->out
[1] = values
[1];
5826 case V_028714_SPI_SHADER_32_AR
:
5827 args
->enabled_channels
= 0x9;
5828 args
->out
[0] = values
[0];
5829 args
->out
[3] = values
[3];
5832 case V_028714_SPI_SHADER_FP16_ABGR
:
5833 args
->enabled_channels
= 0x5;
5834 packf
= ac_build_cvt_pkrtz_f16
;
5837 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5838 args
->enabled_channels
= 0x5;
5839 packf
= ac_build_cvt_pknorm_u16
;
5842 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5843 args
->enabled_channels
= 0x5;
5844 packf
= ac_build_cvt_pknorm_i16
;
5847 case V_028714_SPI_SHADER_UINT16_ABGR
:
5848 args
->enabled_channels
= 0x5;
5849 packi
= ac_build_cvt_pk_u16
;
5852 case V_028714_SPI_SHADER_SINT16_ABGR
:
5853 args
->enabled_channels
= 0x5;
5854 packi
= ac_build_cvt_pk_i16
;
5858 case V_028714_SPI_SHADER_32_ABGR
:
5859 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5863 /* Pack f16 or norm_i16/u16. */
5865 for (chan
= 0; chan
< 2; chan
++) {
5866 LLVMValueRef pack_args
[2] = {
5868 values
[2 * chan
+ 1]
5870 LLVMValueRef packed
;
5872 packed
= packf(&ctx
->ac
, pack_args
);
5873 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
5875 args
->compr
= 1; /* COMPR flag */
5880 for (chan
= 0; chan
< 2; chan
++) {
5881 LLVMValueRef pack_args
[2] = {
5882 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
5883 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
5885 LLVMValueRef packed
;
5887 packed
= packi(&ctx
->ac
, pack_args
,
5888 is_int8
? 8 : is_int10
? 10 : 16,
5890 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
5892 args
->compr
= 1; /* COMPR flag */
5897 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5899 for (unsigned i
= 0; i
< 4; ++i
) {
5900 if (!(args
->enabled_channels
& (1 << i
)))
5903 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5908 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
5909 LLVMValueRef
*values
, unsigned enabled_channels
)
5911 struct ac_export_args args
;
5913 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
5914 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
5915 ac_build_export(&ctx
->ac
, &args
);
5919 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
5921 LLVMValueRef output
=
5922 ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(index
, chan
)];
5924 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
5928 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
5929 bool export_prim_id
,
5930 struct ac_vs_output_info
*outinfo
)
5932 uint32_t param_count
= 0;
5934 unsigned pos_idx
, num_pos_exports
= 0;
5935 struct ac_export_args args
, pos_args
[4] = {};
5936 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
5939 if (ctx
->options
->key
.has_multiview_view_index
) {
5940 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5942 for(unsigned i
= 0; i
< 4; ++i
)
5943 ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
5944 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5947 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
5948 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
5951 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
5952 sizeof(outinfo
->vs_output_param_offset
));
5954 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
5955 LLVMValueRef slots
[8];
5958 if (outinfo
->cull_dist_mask
)
5959 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
5961 i
= VARYING_SLOT_CLIP_DIST0
;
5962 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
5963 slots
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
5965 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
5966 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
5968 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
5969 target
= V_008DFC_SQ_EXP_POS
+ 3;
5970 si_llvm_init_export_args(ctx
, &slots
[4], 0xf, target
, &args
);
5971 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5972 &args
, sizeof(args
));
5975 target
= V_008DFC_SQ_EXP_POS
+ 2;
5976 si_llvm_init_export_args(ctx
, &slots
[0], 0xf, target
, &args
);
5977 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5978 &args
, sizeof(args
));
5982 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
5983 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
5984 for (unsigned j
= 0; j
< 4; j
++)
5985 pos_values
[j
] = radv_load_output(ctx
, VARYING_SLOT_POS
, j
);
5987 si_llvm_init_export_args(ctx
, pos_values
, 0xf, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
5989 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
5990 outinfo
->writes_pointsize
= true;
5991 psize_value
= radv_load_output(ctx
, VARYING_SLOT_PSIZ
, 0);
5994 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
5995 outinfo
->writes_layer
= true;
5996 layer_value
= radv_load_output(ctx
, VARYING_SLOT_LAYER
, 0);
5999 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
6000 outinfo
->writes_viewport_index
= true;
6001 viewport_index_value
= radv_load_output(ctx
, VARYING_SLOT_VIEWPORT
, 0);
6004 if (outinfo
->writes_pointsize
||
6005 outinfo
->writes_layer
||
6006 outinfo
->writes_viewport_index
) {
6007 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
6008 (outinfo
->writes_layer
== true ? 4 : 0));
6009 pos_args
[1].valid_mask
= 0;
6010 pos_args
[1].done
= 0;
6011 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
6012 pos_args
[1].compr
= 0;
6013 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
6014 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
6015 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
6016 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
6018 if (outinfo
->writes_pointsize
== true)
6019 pos_args
[1].out
[0] = psize_value
;
6020 if (outinfo
->writes_layer
== true)
6021 pos_args
[1].out
[2] = layer_value
;
6022 if (outinfo
->writes_viewport_index
== true) {
6023 if (ctx
->options
->chip_class
>= GFX9
) {
6024 /* GFX9 has the layer in out.z[10:0] and the viewport
6025 * index in out.z[19:16].
6027 LLVMValueRef v
= viewport_index_value
;
6028 v
= ac_to_integer(&ctx
->ac
, v
);
6029 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
6030 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6032 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
6033 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
6035 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
6036 pos_args
[1].enabled_channels
|= 1 << 2;
6038 pos_args
[1].out
[3] = viewport_index_value
;
6039 pos_args
[1].enabled_channels
|= 1 << 3;
6043 for (i
= 0; i
< 4; i
++) {
6044 if (pos_args
[i
].out
[0])
6049 for (i
= 0; i
< 4; i
++) {
6050 if (!pos_args
[i
].out
[0])
6053 /* Specify the target we are exporting */
6054 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
6055 if (pos_idx
== num_pos_exports
)
6056 pos_args
[i
].done
= 1;
6057 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
6060 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6061 LLVMValueRef values
[4];
6062 if (!(ctx
->output_mask
& (1ull << i
)))
6065 if (i
!= VARYING_SLOT_LAYER
&&
6066 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
6067 i
< VARYING_SLOT_VAR0
)
6070 for (unsigned j
= 0; j
< 4; j
++)
6071 values
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
6073 unsigned output_usage_mask
;
6075 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
6076 !ctx
->is_gs_copy_shader
) {
6078 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
6079 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6081 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
6083 /* Enable all channels for the GS copy shader because
6084 * we don't know the output usage mask currently.
6086 output_usage_mask
= 0xf;
6089 radv_export_param(ctx
, param_count
, values
, output_usage_mask
);
6091 outinfo
->vs_output_param_offset
[i
] = param_count
++;
6094 if (export_prim_id
) {
6095 LLVMValueRef values
[4];
6097 values
[0] = ctx
->vs_prim_id
;
6098 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
6099 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
6100 for (unsigned j
= 1; j
< 4; j
++)
6101 values
[j
] = ctx
->ac
.f32_0
;
6103 radv_export_param(ctx
, param_count
, values
, 0xf);
6105 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
6106 outinfo
->export_prim_id
= true;
6109 outinfo
->pos_exports
= num_pos_exports
;
6110 outinfo
->param_exports
= param_count
;
6114 handle_es_outputs_post(struct radv_shader_context
*ctx
,
6115 struct ac_es_output_info
*outinfo
)
6118 uint64_t max_output_written
= 0;
6119 LLVMValueRef lds_base
= NULL
;
6121 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6125 if (!(ctx
->output_mask
& (1ull << i
)))
6128 if (i
== VARYING_SLOT_CLIP_DIST0
)
6129 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6131 param_index
= shader_io_get_unique_index(i
);
6133 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
6136 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
6138 if (ctx
->ac
.chip_class
>= GFX9
) {
6139 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
6140 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
6141 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6142 LLVMConstInt(ctx
->ac
.i32
, 24, false),
6143 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
6144 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
6145 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
6146 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
6147 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
6148 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
6151 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6152 LLVMValueRef dw_addr
= NULL
;
6153 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
6157 if (!(ctx
->output_mask
& (1ull << i
)))
6160 if (i
== VARYING_SLOT_CLIP_DIST0
)
6161 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6163 param_index
= shader_io_get_unique_index(i
);
6166 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
6167 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
6170 for (j
= 0; j
< length
; j
++) {
6171 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
6172 out_val
= LLVMBuildBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
6174 if (ctx
->ac
.chip_class
>= GFX9
) {
6175 ac_lds_store(&ctx
->ac
, dw_addr
,
6176 LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], ""));
6177 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6179 ac_build_buffer_store_dword(&ctx
->ac
,
6182 NULL
, ctx
->es2gs_offset
,
6183 (4 * param_index
+ j
) * 4,
6191 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
6193 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
6194 LLVMValueRef vertex_dw_stride
= ac_unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
6195 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
6196 vertex_dw_stride
, "");
6198 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6199 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
6202 if (!(ctx
->output_mask
& (1ull << i
)))
6205 if (i
== VARYING_SLOT_CLIP_DIST0
)
6206 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6207 int param
= shader_io_get_unique_index(i
);
6208 mark_tess_output(ctx
, false, param
);
6210 mark_tess_output(ctx
, false, param
+ 1);
6211 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
6212 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
6214 for (unsigned j
= 0; j
< length
; j
++) {
6215 ac_lds_store(&ctx
->ac
, dw_addr
,
6216 LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], ""));
6217 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6222 struct ac_build_if_state
6224 struct radv_shader_context
*ctx
;
6225 LLVMValueRef condition
;
6226 LLVMBasicBlockRef entry_block
;
6227 LLVMBasicBlockRef true_block
;
6228 LLVMBasicBlockRef false_block
;
6229 LLVMBasicBlockRef merge_block
;
6232 static LLVMBasicBlockRef
6233 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
6235 LLVMBasicBlockRef current_block
;
6236 LLVMBasicBlockRef next_block
;
6237 LLVMBasicBlockRef new_block
;
6239 /* get current basic block */
6240 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
6242 /* chqeck if there's another block after this one */
6243 next_block
= LLVMGetNextBasicBlock(current_block
);
6245 /* insert the new block before the next block */
6246 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
6249 /* append new block after current block */
6250 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
6251 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
6257 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
6258 struct radv_shader_context
*ctx
,
6259 LLVMValueRef condition
)
6261 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
6263 memset(ifthen
, 0, sizeof *ifthen
);
6265 ifthen
->condition
= condition
;
6266 ifthen
->entry_block
= block
;
6268 /* create endif/merge basic block for the phi functions */
6269 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
6271 /* create/insert true_block before merge_block */
6272 ifthen
->true_block
=
6273 LLVMInsertBasicBlockInContext(ctx
->context
,
6274 ifthen
->merge_block
,
6277 /* successive code goes into the true block */
6278 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
6282 * End a conditional.
6285 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6287 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
6289 /* Insert branch to the merge block from current block */
6290 LLVMBuildBr(builder
, ifthen
->merge_block
);
6293 * Now patch in the various branch instructions.
6296 /* Insert the conditional branch instruction at the end of entry_block */
6297 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6298 if (ifthen
->false_block
) {
6299 /* we have an else clause */
6300 LLVMBuildCondBr(builder
, ifthen
->condition
,
6301 ifthen
->true_block
, ifthen
->false_block
);
6304 /* no else clause */
6305 LLVMBuildCondBr(builder
, ifthen
->condition
,
6306 ifthen
->true_block
, ifthen
->merge_block
);
6309 /* Resume building code at end of the ifthen->merge_block */
6310 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6314 write_tess_factors(struct radv_shader_context
*ctx
)
6316 unsigned stride
, outer_comps
, inner_comps
;
6317 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6318 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
6319 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
6320 unsigned tess_inner_index
= 0, tess_outer_index
;
6321 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
6322 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6324 emit_barrier(&ctx
->ac
, ctx
->stage
);
6326 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6346 ac_nir_build_if(&if_ctx
, ctx
,
6347 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
6348 invocation_id
, ctx
->ac
.i32_0
, ""));
6350 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6353 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6354 mark_tess_output(ctx
, true, tess_inner_index
);
6355 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
6356 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
6359 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6360 mark_tess_output(ctx
, true, tess_outer_index
);
6361 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
6362 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
6364 for (i
= 0; i
< 4; i
++) {
6365 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6366 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6370 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6371 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
6372 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
6374 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
6376 for (i
= 0; i
< outer_comps
; i
++) {
6378 ac_lds_load(&ctx
->ac
, lds_outer
);
6379 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
6382 for (i
= 0; i
< inner_comps
; i
++) {
6383 inner
[i
] = out
[outer_comps
+i
] =
6384 ac_lds_load(&ctx
->ac
, lds_inner
);
6385 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
6390 /* Convert the outputs to vectors for stores. */
6391 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6395 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6398 buffer
= ctx
->hs_ring_tess_factor
;
6399 tf_base
= ctx
->tess_factor_offset
;
6400 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
6401 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
6402 unsigned tf_offset
= 0;
6404 if (ctx
->options
->chip_class
<= VI
) {
6405 ac_nir_build_if(&inner_if_ctx
, ctx
,
6406 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
6407 rel_patch_id
, ctx
->ac
.i32_0
, ""));
6409 /* Store the dynamic HS control word. */
6410 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6411 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
6412 1, ctx
->ac
.i32_0
, tf_base
,
6413 0, 1, 0, true, false);
6416 ac_nir_build_endif(&inner_if_ctx
);
6419 /* Store the tessellation factors. */
6420 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6421 MIN2(stride
, 4), byteoffset
, tf_base
,
6422 tf_offset
, 1, 0, true, false);
6424 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6425 stride
- 4, byteoffset
, tf_base
,
6426 16 + tf_offset
, 1, 0, true, false);
6428 //store to offchip for TES to read - only if TES reads them
6429 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6430 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6431 LLVMValueRef tf_inner_offset
;
6432 unsigned param_outer
, param_inner
;
6434 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6435 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6436 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
6438 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6439 util_next_power_of_two(outer_comps
));
6441 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6442 outer_comps
, tf_outer_offset
,
6443 ctx
->oc_lds
, 0, 1, 0, true, false);
6445 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6446 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6447 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
6449 inner_vec
= inner_comps
== 1 ? inner
[0] :
6450 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6451 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6452 inner_comps
, tf_inner_offset
,
6453 ctx
->oc_lds
, 0, 1, 0, true, false);
6456 ac_nir_build_endif(&if_ctx
);
6460 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
6462 write_tess_factors(ctx
);
6466 si_export_mrt_color(struct radv_shader_context
*ctx
,
6467 LLVMValueRef
*color
, unsigned index
,
6468 struct ac_export_args
*args
)
6471 si_llvm_init_export_args(ctx
, color
, 0xf,
6472 V_008DFC_SQ_EXP_MRT
+ index
, args
);
6473 if (!args
->enabled_channels
)
6474 return false; /* unnecessary NULL export */
6480 radv_export_mrt_z(struct radv_shader_context
*ctx
,
6481 LLVMValueRef depth
, LLVMValueRef stencil
,
6482 LLVMValueRef samplemask
)
6484 struct ac_export_args args
;
6486 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
6488 ac_build_export(&ctx
->ac
, &args
);
6492 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
6495 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6496 struct ac_export_args color_args
[8];
6498 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6499 LLVMValueRef values
[4];
6501 if (!(ctx
->output_mask
& (1ull << i
)))
6504 if (i
< FRAG_RESULT_DATA0
)
6507 for (unsigned j
= 0; j
< 4; j
++)
6508 values
[j
] = ac_to_float(&ctx
->ac
,
6509 radv_load_output(ctx
, i
, j
));
6511 bool ret
= si_export_mrt_color(ctx
, values
,
6512 i
- FRAG_RESULT_DATA0
,
6513 &color_args
[index
]);
6518 /* Process depth, stencil, samplemask. */
6519 if (ctx
->shader_info
->info
.ps
.writes_z
) {
6520 depth
= ac_to_float(&ctx
->ac
,
6521 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
6523 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
6524 stencil
= ac_to_float(&ctx
->ac
,
6525 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
6527 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
6528 samplemask
= ac_to_float(&ctx
->ac
,
6529 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
6532 /* Set the DONE bit on last non-null color export only if Z isn't
6536 !ctx
->shader_info
->info
.ps
.writes_z
&&
6537 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
6538 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
6539 unsigned last
= index
- 1;
6541 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
6542 color_args
[last
].done
= 1; /* DONE bit */
6545 /* Export PS outputs. */
6546 for (unsigned i
= 0; i
< index
; i
++)
6547 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6549 if (depth
|| stencil
|| samplemask
)
6550 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6552 ac_build_export_null(&ctx
->ac
);
6556 emit_gs_epilogue(struct radv_shader_context
*ctx
)
6558 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6562 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6563 LLVMValueRef
*addrs
)
6565 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
6567 switch (ctx
->stage
) {
6568 case MESA_SHADER_VERTEX
:
6569 if (ctx
->options
->key
.vs
.as_ls
)
6570 handle_ls_outputs_post(ctx
);
6571 else if (ctx
->options
->key
.vs
.as_es
)
6572 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6574 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6575 &ctx
->shader_info
->vs
.outinfo
);
6577 case MESA_SHADER_FRAGMENT
:
6578 handle_fs_outputs_post(ctx
);
6580 case MESA_SHADER_GEOMETRY
:
6581 emit_gs_epilogue(ctx
);
6583 case MESA_SHADER_TESS_CTRL
:
6584 handle_tcs_outputs_post(ctx
);
6586 case MESA_SHADER_TESS_EVAL
:
6587 if (ctx
->options
->key
.tes
.as_es
)
6588 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6590 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6591 &ctx
->shader_info
->tes
.outinfo
);
6598 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
)
6600 LLVMPassManagerRef passmgr
;
6601 /* Create the pass manager */
6602 passmgr
= LLVMCreateFunctionPassManagerForModule(
6605 /* This pass should eliminate all the load and store instructions */
6606 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6608 /* Add some optimization passes */
6609 LLVMAddScalarReplAggregatesPass(passmgr
);
6610 LLVMAddLICMPass(passmgr
);
6611 LLVMAddAggressiveDCEPass(passmgr
);
6612 LLVMAddCFGSimplificationPass(passmgr
);
6613 LLVMAddInstructionCombiningPass(passmgr
);
6616 LLVMInitializeFunctionPassManager(passmgr
);
6617 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6618 LLVMFinalizeFunctionPassManager(passmgr
);
6620 LLVMDisposeBuilder(ctx
->ac
.builder
);
6621 LLVMDisposePassManager(passmgr
);
6623 ac_llvm_context_dispose(&ctx
->ac
);
6627 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
6629 struct ac_vs_output_info
*outinfo
;
6631 switch (ctx
->stage
) {
6632 case MESA_SHADER_FRAGMENT
:
6633 case MESA_SHADER_COMPUTE
:
6634 case MESA_SHADER_TESS_CTRL
:
6635 case MESA_SHADER_GEOMETRY
:
6637 case MESA_SHADER_VERTEX
:
6638 if (ctx
->options
->key
.vs
.as_ls
||
6639 ctx
->options
->key
.vs
.as_es
)
6641 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6643 case MESA_SHADER_TESS_EVAL
:
6644 if (ctx
->options
->key
.vs
.as_es
)
6646 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6649 unreachable("Unhandled shader type");
6652 ac_optimize_vs_outputs(&ctx
->ac
,
6654 outinfo
->vs_output_param_offset
,
6656 &outinfo
->param_exports
);
6660 ac_setup_rings(struct radv_shader_context
*ctx
)
6662 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6663 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6664 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
6667 if (ctx
->is_gs_copy_shader
) {
6668 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
6670 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6672 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
6673 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
6675 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
6677 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
6678 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
6679 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6680 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
6683 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6684 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6685 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
6686 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
6691 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6692 const struct nir_shader
*nir
)
6694 switch (nir
->info
.stage
) {
6695 case MESA_SHADER_TESS_CTRL
:
6696 return chip_class
>= CIK
? 128 : 64;
6697 case MESA_SHADER_GEOMETRY
:
6698 return chip_class
>= GFX9
? 128 : 64;
6699 case MESA_SHADER_COMPUTE
:
6705 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6706 nir
->info
.cs
.local_size
[1] *
6707 nir
->info
.cs
.local_size
[2];
6708 return max_workgroup_size
;
6711 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6712 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
6714 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6715 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6716 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6717 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6719 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6720 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6721 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
6722 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6725 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
6727 for(int i
= 5; i
>= 0; --i
) {
6728 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6729 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6730 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6733 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6734 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6735 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6738 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6739 struct nir_shader
*nir
)
6741 struct ac_nir_context ctx
= {};
6742 struct nir_function
*func
;
6744 /* Last minute passes for both radv & radeonsi */
6745 ac_lower_subgroups(nir
);
6750 ctx
.stage
= nir
->info
.stage
;
6752 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6754 nir_foreach_variable(variable
, &nir
->outputs
)
6755 handle_shader_output_decl(&ctx
, nir
, variable
);
6757 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6758 _mesa_key_pointer_equal
);
6759 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6760 _mesa_key_pointer_equal
);
6761 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6762 _mesa_key_pointer_equal
);
6764 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6766 setup_locals(&ctx
, func
);
6768 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6769 setup_shared(&ctx
, nir
);
6771 visit_cf_list(&ctx
, &func
->impl
->body
);
6772 phi_post_pass(&ctx
);
6774 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
6775 ctx
.abi
->emit_outputs(ctx
.abi
, AC_LLVM_MAX_OUTPUTS
,
6779 ralloc_free(ctx
.defs
);
6780 ralloc_free(ctx
.phis
);
6781 ralloc_free(ctx
.vars
);
6785 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6786 struct nir_shader
*const *shaders
,
6788 struct ac_shader_variant_info
*shader_info
,
6789 const struct ac_nir_compiler_options
*options
,
6792 struct radv_shader_context ctx
= {0};
6794 ctx
.options
= options
;
6795 ctx
.shader_info
= shader_info
;
6796 ctx
.context
= LLVMContextCreate();
6798 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
6800 ctx
.ac
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6801 LLVMSetTarget(ctx
.ac
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6803 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6804 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6805 LLVMSetDataLayout(ctx
.ac
.module
, data_layout_str
);
6806 LLVMDisposeTargetData(data_layout
);
6807 LLVMDisposeMessage(data_layout_str
);
6809 enum ac_float_mode float_mode
=
6810 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
6811 AC_FLOAT_MODE_DEFAULT
;
6813 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
6815 memset(shader_info
, 0, sizeof(*shader_info
));
6817 for(int i
= 0; i
< shader_count
; ++i
)
6818 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6820 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6821 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6822 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6823 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6825 ctx
.max_workgroup_size
= 0;
6826 for (int i
= 0; i
< shader_count
; ++i
) {
6827 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6828 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6832 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6833 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6835 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6836 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6837 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
6838 ctx
.abi
.load_ubo
= radv_load_ubo
;
6839 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6840 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6841 ctx
.abi
.load_resource
= radv_load_resource
;
6842 ctx
.abi
.clamp_shadow_reference
= false;
6844 if (shader_count
>= 2)
6845 ac_init_exec_full_mask(&ctx
.ac
);
6847 if (ctx
.ac
.chip_class
== GFX9
&&
6848 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6849 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6851 for(int i
= 0; i
< shader_count
; ++i
) {
6852 ctx
.stage
= shaders
[i
]->info
.stage
;
6853 ctx
.output_mask
= 0;
6854 ctx
.tess_outputs_written
= 0;
6855 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6856 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6858 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6859 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
6860 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6861 ctx
.abi
.load_inputs
= load_gs_input
;
6862 ctx
.abi
.emit_primitive
= visit_end_primitive
;
6863 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6864 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
6865 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
6866 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
6867 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6868 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
6869 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
6870 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6871 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6872 ctx
.abi
.load_tess_varyings
= load_tes_input
;
6873 ctx
.abi
.load_tess_coord
= load_tess_coord
;
6874 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6875 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
6876 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6877 if (shader_info
->info
.vs
.needs_instance_id
) {
6878 if (ctx
.options
->key
.vs
.as_ls
) {
6879 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6880 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6882 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6883 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6886 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
6887 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6888 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6889 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
6890 ctx
.abi
.load_sample_position
= load_sample_position
;
6891 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
6892 ctx
.abi
.emit_kill
= radv_emit_kill
;
6896 emit_barrier(&ctx
.ac
, ctx
.stage
);
6898 ac_setup_rings(&ctx
);
6900 LLVMBasicBlockRef merge_block
;
6901 if (shader_count
>= 2) {
6902 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6903 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6904 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6906 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6907 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6908 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6909 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6910 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6911 thread_id
, count
, "");
6912 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6914 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6917 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6918 handle_fs_inputs(&ctx
, shaders
[i
]);
6919 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
6920 handle_vs_inputs(&ctx
, shaders
[i
]);
6921 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
6922 prepare_gs_input_vgprs(&ctx
);
6924 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
6925 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
6927 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
6929 if (shader_count
>= 2) {
6930 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
6931 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
6934 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6935 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
6936 shaders
[i
]->info
.cull_distance_array_size
> 4;
6937 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6938 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6939 shaders
[i
]->info
.gs
.vertices_out
;
6940 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6941 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6942 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6943 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6944 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6948 LLVMBuildRetVoid(ctx
.ac
.builder
);
6950 if (options
->dump_preoptir
)
6951 ac_dump_module(ctx
.ac
.module
);
6953 ac_llvm_finalize_module(&ctx
);
6955 if (shader_count
== 1)
6956 ac_nir_eliminate_const_vs_outputs(&ctx
);
6959 ctx
.shader_info
->private_mem_vgprs
=
6960 ac_count_scratch_private_memory(ctx
.main_function
);
6963 return ctx
.ac
.module
;
6966 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
6968 unsigned *retval
= (unsigned *)context
;
6969 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
6970 char *description
= LLVMGetDiagInfoDescription(di
);
6972 if (severity
== LLVMDSError
) {
6974 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
6978 LLVMDisposeMessage(description
);
6981 static unsigned ac_llvm_compile(LLVMModuleRef M
,
6982 struct ac_shader_binary
*binary
,
6983 LLVMTargetMachineRef tm
)
6985 unsigned retval
= 0;
6987 LLVMContextRef llvm_ctx
;
6988 LLVMMemoryBufferRef out_buffer
;
6989 unsigned buffer_size
;
6990 const char *buffer_data
;
6993 /* Setup Diagnostic Handler*/
6994 llvm_ctx
= LLVMGetModuleContext(M
);
6996 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
7000 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
7003 /* Process Errors/Warnings */
7005 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
7011 /* Extract Shader Code*/
7012 buffer_size
= LLVMGetBufferSize(out_buffer
);
7013 buffer_data
= LLVMGetBufferStart(out_buffer
);
7015 ac_elf_read(buffer_data
, buffer_size
, binary
);
7018 LLVMDisposeMemoryBuffer(out_buffer
);
7024 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
7025 LLVMModuleRef llvm_module
,
7026 struct ac_shader_binary
*binary
,
7027 struct ac_shader_config
*config
,
7028 struct ac_shader_variant_info
*shader_info
,
7029 gl_shader_stage stage
,
7030 bool dump_shader
, bool supports_spill
)
7033 ac_dump_module(llvm_module
);
7035 memset(binary
, 0, sizeof(*binary
));
7036 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
7038 fprintf(stderr
, "compile failed\n");
7042 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
7044 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
7046 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
7047 LLVMDisposeModule(llvm_module
);
7048 LLVMContextDispose(ctx
);
7050 if (stage
== MESA_SHADER_FRAGMENT
) {
7051 shader_info
->num_input_vgprs
= 0;
7052 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
7053 shader_info
->num_input_vgprs
+= 2;
7054 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
7055 shader_info
->num_input_vgprs
+= 2;
7056 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
7057 shader_info
->num_input_vgprs
+= 2;
7058 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
7059 shader_info
->num_input_vgprs
+= 3;
7060 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
7061 shader_info
->num_input_vgprs
+= 2;
7062 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
7063 shader_info
->num_input_vgprs
+= 2;
7064 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
7065 shader_info
->num_input_vgprs
+= 2;
7066 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
7067 shader_info
->num_input_vgprs
+= 1;
7068 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
7069 shader_info
->num_input_vgprs
+= 1;
7070 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
7071 shader_info
->num_input_vgprs
+= 1;
7072 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
7073 shader_info
->num_input_vgprs
+= 1;
7074 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
7075 shader_info
->num_input_vgprs
+= 1;
7076 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
7077 shader_info
->num_input_vgprs
+= 1;
7078 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
7079 shader_info
->num_input_vgprs
+= 1;
7080 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
7081 shader_info
->num_input_vgprs
+= 1;
7082 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
7083 shader_info
->num_input_vgprs
+= 1;
7085 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
7087 /* +3 for scratch wave offset and VCC */
7088 config
->num_sgprs
= MAX2(config
->num_sgprs
,
7089 shader_info
->num_input_sgprs
+ 3);
7091 /* Enable 64-bit and 16-bit denormals, because there is no performance
7094 * If denormals are enabled, all floating-point output modifiers are
7097 * Don't enable denormals for 32-bit floats, because:
7098 * - Floating-point output modifiers would be ignored by the hw.
7099 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7100 * have to stop using those.
7101 * - SI & CI would be very slow.
7103 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
7107 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
7109 switch (nir
->info
.stage
) {
7110 case MESA_SHADER_COMPUTE
:
7111 for (int i
= 0; i
< 3; ++i
)
7112 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
7114 case MESA_SHADER_FRAGMENT
:
7115 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
7117 case MESA_SHADER_GEOMETRY
:
7118 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
7119 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
7120 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
7121 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
7123 case MESA_SHADER_TESS_EVAL
:
7124 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
7125 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
7126 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
7127 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
7128 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
7130 case MESA_SHADER_TESS_CTRL
:
7131 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
7133 case MESA_SHADER_VERTEX
:
7134 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
7135 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
7136 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7137 if (options
->key
.vs
.as_ls
)
7138 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
7145 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
7146 struct ac_shader_binary
*binary
,
7147 struct ac_shader_config
*config
,
7148 struct ac_shader_variant_info
*shader_info
,
7149 struct nir_shader
*const *nir
,
7151 const struct ac_nir_compiler_options
*options
,
7155 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
7156 options
, dump_shader
);
7158 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
7159 for (int i
= 0; i
< nir_count
; ++i
)
7160 ac_fill_shader_info(shader_info
, nir
[i
], options
);
7162 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7163 if (options
->chip_class
== GFX9
) {
7164 if (nir_count
== 2 &&
7165 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
7166 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
7172 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
7174 LLVMValueRef vtx_offset
=
7175 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
7176 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
7179 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
7183 if (!(ctx
->output_mask
& (1ull << i
)))
7186 if (i
== VARYING_SLOT_CLIP_DIST0
) {
7187 /* unpack clip and cull from a single set of slots */
7188 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
7193 for (unsigned j
= 0; j
< length
; j
++) {
7194 LLVMValueRef value
, soffset
;
7196 soffset
= LLVMConstInt(ctx
->ac
.i32
,
7198 ctx
->gs_max_out_vertices
* 16 * 4, false);
7200 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->gsvs_ring
,
7202 vtx_offset
, soffset
,
7203 0, 1, 1, true, false);
7205 LLVMBuildStore(ctx
->ac
.builder
,
7206 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
7210 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
7213 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
7214 struct nir_shader
*geom_shader
,
7215 struct ac_shader_binary
*binary
,
7216 struct ac_shader_config
*config
,
7217 struct ac_shader_variant_info
*shader_info
,
7218 const struct ac_nir_compiler_options
*options
,
7221 struct radv_shader_context ctx
= {0};
7222 ctx
.context
= LLVMContextCreate();
7223 ctx
.options
= options
;
7224 ctx
.shader_info
= shader_info
;
7226 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
7228 ctx
.ac
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
7230 ctx
.is_gs_copy_shader
= true;
7231 LLVMSetTarget(ctx
.ac
.module
, "amdgcn--");
7233 enum ac_float_mode float_mode
=
7234 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
7235 AC_FLOAT_MODE_DEFAULT
;
7237 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
7238 ctx
.stage
= MESA_SHADER_VERTEX
;
7240 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
7242 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
7243 ac_setup_rings(&ctx
);
7245 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
7246 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
7248 struct ac_nir_context nir_ctx
= {};
7249 nir_ctx
.ac
= ctx
.ac
;
7250 nir_ctx
.abi
= &ctx
.abi
;
7252 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
7253 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
7254 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
7257 ac_gs_copy_shader_emit(&ctx
);
7259 LLVMBuildRetVoid(ctx
.ac
.builder
);
7261 ac_llvm_finalize_module(&ctx
);
7263 ac_compile_llvm_module(tm
, ctx
.ac
.module
, binary
, config
, shader_info
,
7265 dump_shader
, options
->supports_spill
);
7269 ac_lower_indirect_derefs(struct nir_shader
*nir
, enum chip_class chip_class
)
7271 /* While it would be nice not to have this flag, we are constrained
7272 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
7275 bool llvm_has_working_vgpr_indexing
= chip_class
<= VI
;
7277 /* TODO: Indirect indexing of GS inputs is unimplemented.
7279 * TCS and TES load inputs directly from LDS or offchip memory, so
7280 * indirect indexing is trivial.
7282 nir_variable_mode indirect_mask
= 0;
7283 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
||
7284 (nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
&&
7285 nir
->info
.stage
!= MESA_SHADER_TESS_EVAL
&&
7286 !llvm_has_working_vgpr_indexing
)) {
7287 indirect_mask
|= nir_var_shader_in
;
7289 if (!llvm_has_working_vgpr_indexing
&&
7290 nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
)
7291 indirect_mask
|= nir_var_shader_out
;
7293 /* TODO: We shouldn't need to do this, however LLVM isn't currently
7294 * smart enough to handle indirects without causing excess spilling
7295 * causing the gpu to hang.
7297 * See the following thread for more details of the problem:
7298 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
7300 indirect_mask
|= nir_var_local
;
7302 nir_lower_indirect_derefs(nir
, indirect_mask
);