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radv/ac: use common interp code for new intrinsics
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 #define SENDMSG_GS 2
48 #define SENDMSG_GS_DONE 3
49
50 #define SENDMSG_GS_OP_NOP (0 << 4)
51 #define SENDMSG_GS_OP_CUT (1 << 4)
52 #define SENDMSG_GS_OP_EMIT (2 << 4)
53 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
54
55 enum desc_type {
56 DESC_IMAGE,
57 DESC_FMASK,
58 DESC_SAMPLER,
59 DESC_BUFFER,
60 };
61
62 struct nir_to_llvm_context {
63 struct ac_llvm_context ac;
64 const struct ac_nir_compiler_options *options;
65 struct ac_shader_variant_info *shader_info;
66
67 LLVMContextRef context;
68 LLVMModuleRef module;
69 LLVMBuilderRef builder;
70 LLVMValueRef main_function;
71
72 struct hash_table *defs;
73 struct hash_table *phis;
74
75 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
76 LLVMValueRef ring_offsets;
77 LLVMValueRef push_constants;
78 LLVMValueRef num_work_groups;
79 LLVMValueRef workgroup_ids;
80 LLVMValueRef local_invocation_ids;
81 LLVMValueRef tg_size;
82
83 LLVMValueRef vertex_buffers;
84 LLVMValueRef base_vertex;
85 LLVMValueRef start_instance;
86 LLVMValueRef draw_index;
87 LLVMValueRef vertex_id;
88 LLVMValueRef rel_auto_id;
89 LLVMValueRef vs_prim_id;
90 LLVMValueRef instance_id;
91
92 LLVMValueRef es2gs_offset;
93
94 LLVMValueRef gsvs_ring_stride;
95 LLVMValueRef gsvs_num_entries;
96 LLVMValueRef gs2vs_offset;
97 LLVMValueRef gs_wave_id;
98 LLVMValueRef gs_vtx_offset[6];
99 LLVMValueRef gs_prim_id, gs_invocation_id;
100
101 LLVMValueRef esgs_ring;
102 LLVMValueRef gsvs_ring;
103
104 LLVMValueRef prim_mask;
105 LLVMValueRef sample_positions;
106 LLVMValueRef persp_sample, persp_center, persp_centroid;
107 LLVMValueRef linear_sample, linear_center, linear_centroid;
108 LLVMValueRef front_face;
109 LLVMValueRef ancillary;
110 LLVMValueRef frag_pos[4];
111
112 LLVMBasicBlockRef continue_block;
113 LLVMBasicBlockRef break_block;
114
115 LLVMTypeRef i1;
116 LLVMTypeRef i8;
117 LLVMTypeRef i16;
118 LLVMTypeRef i32;
119 LLVMTypeRef i64;
120 LLVMTypeRef v2i32;
121 LLVMTypeRef v3i32;
122 LLVMTypeRef v4i32;
123 LLVMTypeRef v8i32;
124 LLVMTypeRef f64;
125 LLVMTypeRef f32;
126 LLVMTypeRef f16;
127 LLVMTypeRef v2f32;
128 LLVMTypeRef v4f32;
129 LLVMTypeRef v16i8;
130 LLVMTypeRef voidt;
131
132 LLVMValueRef i32zero;
133 LLVMValueRef i32one;
134 LLVMValueRef f32zero;
135 LLVMValueRef f32one;
136 LLVMValueRef v4f32empty;
137
138 unsigned uniform_md_kind;
139 LLVMValueRef empty_md;
140 gl_shader_stage stage;
141
142 LLVMValueRef lds;
143 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
144 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
145
146 LLVMValueRef shared_memory;
147 uint64_t input_mask;
148 uint64_t output_mask;
149 int num_locals;
150 LLVMValueRef *locals;
151 bool has_ddxy;
152 unsigned num_clips;
153 unsigned num_culls;
154
155 bool has_ds_bpermute;
156
157 bool is_gs_copy_shader;
158 LLVMValueRef gs_next_vertex;
159 unsigned gs_max_out_vertices;
160 };
161
162 struct ac_tex_info {
163 LLVMValueRef args[12];
164 int arg_count;
165 LLVMTypeRef dst_type;
166 bool has_offset;
167 };
168
169 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
170 nir_deref_var *deref,
171 enum desc_type desc_type);
172 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
173 {
174 return (index * 4) + chan;
175 }
176
177 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
178 {
179 if (slot == VARYING_SLOT_POS)
180 return 0;
181 if (slot == VARYING_SLOT_PSIZ)
182 return 1;
183 if (slot == VARYING_SLOT_CLIP_DIST0)
184 return 2;
185 if (slot == VARYING_SLOT_CLIP_DIST1)
186 return 3;
187 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
188 return 4 + (slot - VARYING_SLOT_VAR0);
189 unreachable("illegal slot in get unique index\n");
190 }
191
192 static unsigned llvm_get_type_size(LLVMTypeRef type)
193 {
194 LLVMTypeKind kind = LLVMGetTypeKind(type);
195
196 switch (kind) {
197 case LLVMIntegerTypeKind:
198 return LLVMGetIntTypeWidth(type) / 8;
199 case LLVMFloatTypeKind:
200 return 4;
201 case LLVMPointerTypeKind:
202 return 8;
203 case LLVMVectorTypeKind:
204 return LLVMGetVectorSize(type) *
205 llvm_get_type_size(LLVMGetElementType(type));
206 default:
207 assert(0);
208 return 0;
209 }
210 }
211
212 static void set_llvm_calling_convention(LLVMValueRef func,
213 gl_shader_stage stage)
214 {
215 enum radeon_llvm_calling_convention calling_conv;
216
217 switch (stage) {
218 case MESA_SHADER_VERTEX:
219 case MESA_SHADER_TESS_CTRL:
220 case MESA_SHADER_TESS_EVAL:
221 calling_conv = RADEON_LLVM_AMDGPU_VS;
222 break;
223 case MESA_SHADER_GEOMETRY:
224 calling_conv = RADEON_LLVM_AMDGPU_GS;
225 break;
226 case MESA_SHADER_FRAGMENT:
227 calling_conv = RADEON_LLVM_AMDGPU_PS;
228 break;
229 case MESA_SHADER_COMPUTE:
230 calling_conv = RADEON_LLVM_AMDGPU_CS;
231 break;
232 default:
233 unreachable("Unhandle shader type");
234 }
235
236 LLVMSetFunctionCallConv(func, calling_conv);
237 }
238
239 static LLVMValueRef
240 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
241 LLVMBuilderRef builder, LLVMTypeRef *return_types,
242 unsigned num_return_elems, LLVMTypeRef *param_types,
243 unsigned param_count, unsigned array_params_mask,
244 unsigned sgpr_params, bool unsafe_math)
245 {
246 LLVMTypeRef main_function_type, ret_type;
247 LLVMBasicBlockRef main_function_body;
248
249 if (num_return_elems)
250 ret_type = LLVMStructTypeInContext(ctx, return_types,
251 num_return_elems, true);
252 else
253 ret_type = LLVMVoidTypeInContext(ctx);
254
255 /* Setup the function */
256 main_function_type =
257 LLVMFunctionType(ret_type, param_types, param_count, 0);
258 LLVMValueRef main_function =
259 LLVMAddFunction(module, "main", main_function_type);
260 main_function_body =
261 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
262 LLVMPositionBuilderAtEnd(builder, main_function_body);
263
264 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
265 for (unsigned i = 0; i < sgpr_params; ++i) {
266 if (array_params_mask & (1 << i)) {
267 LLVMValueRef P = LLVMGetParam(main_function, i);
268 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
269 ac_add_attr_dereferenceable(P, UINT64_MAX);
270 }
271 else {
272 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
273 }
274 }
275
276 if (unsafe_math) {
277 /* These were copied from some LLVM test. */
278 LLVMAddTargetDependentFunctionAttr(main_function,
279 "less-precise-fpmad",
280 "true");
281 LLVMAddTargetDependentFunctionAttr(main_function,
282 "no-infs-fp-math",
283 "true");
284 LLVMAddTargetDependentFunctionAttr(main_function,
285 "no-nans-fp-math",
286 "true");
287 LLVMAddTargetDependentFunctionAttr(main_function,
288 "unsafe-fp-math",
289 "true");
290 }
291 return main_function;
292 }
293
294 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
295 {
296 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
297 CONST_ADDR_SPACE);
298 }
299
300 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
301 int idx,
302 LLVMTypeRef type)
303 {
304 LLVMValueRef offset;
305 LLVMValueRef ptr;
306 int addr_space;
307
308 offset = LLVMConstInt(ctx->i32, idx, false);
309
310 ptr = ctx->shared_memory;
311 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
312 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
313 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
314 return ptr;
315 }
316
317 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
318 {
319 if (t == ctx->f16 || t == ctx->i16)
320 return ctx->i16;
321 else if (t == ctx->f32 || t == ctx->i32)
322 return ctx->i32;
323 else if (t == ctx->f64 || t == ctx->i64)
324 return ctx->i64;
325 else
326 unreachable("Unhandled integer size");
327 }
328
329 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
330 {
331 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
332 LLVMTypeRef elem_type = LLVMGetElementType(t);
333 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
334 LLVMGetVectorSize(t));
335 }
336 return to_integer_type_scalar(ctx, t);
337 }
338
339 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
340 {
341 LLVMTypeRef type = LLVMTypeOf(v);
342 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
343 }
344
345 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
346 {
347 if (t == ctx->i16 || t == ctx->f16)
348 return ctx->f16;
349 else if (t == ctx->i32 || t == ctx->f32)
350 return ctx->f32;
351 else if (t == ctx->i64 || t == ctx->f64)
352 return ctx->f64;
353 else
354 unreachable("Unhandled float size");
355 }
356
357 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
358 {
359 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
360 LLVMTypeRef elem_type = LLVMGetElementType(t);
361 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
362 LLVMGetVectorSize(t));
363 }
364 return to_float_type_scalar(ctx, t);
365 }
366
367 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
368 {
369 LLVMTypeRef type = LLVMTypeOf(v);
370 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
371 }
372
373 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
374 {
375 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
376 type = LLVMGetElementType(type);
377
378 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
379 return LLVMGetIntTypeWidth(type);
380
381 if (type == ctx->f16)
382 return 16;
383 if (type == ctx->f32)
384 return 32;
385 if (type == ctx->f64)
386 return 64;
387
388 unreachable("Unhandled type kind in get_elem_bits");
389 }
390
391 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
392 LLVMValueRef param, unsigned rshift,
393 unsigned bitwidth)
394 {
395 LLVMValueRef value = param;
396 if (rshift)
397 value = LLVMBuildLShr(ctx->builder, value,
398 LLVMConstInt(ctx->i32, rshift, false), "");
399
400 if (rshift + bitwidth < 32) {
401 unsigned mask = (1 << bitwidth) - 1;
402 value = LLVMBuildAnd(ctx->builder, value,
403 LLVMConstInt(ctx->i32, mask, false), "");
404 }
405 return value;
406 }
407
408 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
409 {
410 ud_info->sgpr_idx = sgpr_idx;
411 ud_info->num_sgprs = num_sgprs;
412 ud_info->indirect = false;
413 ud_info->indirect_offset = 0;
414 }
415
416 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
417 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
418 {
419 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
420 }
421
422 #if 0
423 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
424 uint32_t indirect_offset)
425 {
426 ud_info->sgpr_idx = sgpr_idx;
427 ud_info->num_sgprs = num_sgprs;
428 ud_info->indirect = true;
429 ud_info->indirect_offset = indirect_offset;
430 }
431 #endif
432
433 static void create_function(struct nir_to_llvm_context *ctx)
434 {
435 LLVMTypeRef arg_types[23];
436 unsigned arg_idx = 0;
437 unsigned array_params_mask = 0;
438 unsigned sgpr_count = 0, user_sgpr_count;
439 unsigned i;
440 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
441 unsigned user_sgpr_idx;
442 bool need_push_constants;
443 bool need_ring_offsets = false;
444
445 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
446 if (ctx->stage == MESA_SHADER_GEOMETRY ||
447 ctx->stage == MESA_SHADER_VERTEX ||
448 ctx->is_gs_copy_shader)
449 need_ring_offsets = true;
450
451 need_push_constants = true;
452 if (!ctx->options->layout)
453 need_push_constants = false;
454 else if (!ctx->options->layout->push_constant_size &&
455 !ctx->options->layout->dynamic_offset_count)
456 need_push_constants = false;
457
458 if (need_ring_offsets && !ctx->options->supports_spill) {
459 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
460 }
461
462 /* 1 for each descriptor set */
463 for (unsigned i = 0; i < num_sets; ++i) {
464 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
465 array_params_mask |= (1 << arg_idx);
466 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
467 }
468 }
469
470 if (need_push_constants) {
471 /* 1 for push constants and dynamic descriptors */
472 array_params_mask |= (1 << arg_idx);
473 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
474 }
475
476 switch (ctx->stage) {
477 case MESA_SHADER_COMPUTE:
478 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
479 user_sgpr_count = arg_idx;
480 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
481 arg_types[arg_idx++] = ctx->i32;
482 sgpr_count = arg_idx;
483
484 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
485 break;
486 case MESA_SHADER_VERTEX:
487 if (!ctx->is_gs_copy_shader) {
488 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
489 arg_types[arg_idx++] = ctx->i32; // base vertex
490 arg_types[arg_idx++] = ctx->i32; // start instance
491 arg_types[arg_idx++] = ctx->i32; // draw index
492 }
493 user_sgpr_count = arg_idx;
494 if (ctx->options->key.vs.as_es)
495 arg_types[arg_idx++] = ctx->i32; //es2gs offset
496 sgpr_count = arg_idx;
497 arg_types[arg_idx++] = ctx->i32; // vertex id
498 if (!ctx->is_gs_copy_shader) {
499 arg_types[arg_idx++] = ctx->i32; // rel auto id
500 arg_types[arg_idx++] = ctx->i32; // vs prim id
501 arg_types[arg_idx++] = ctx->i32; // instance id
502 }
503 break;
504 case MESA_SHADER_GEOMETRY:
505 arg_types[arg_idx++] = ctx->i32; // gsvs stride
506 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
507 user_sgpr_count = arg_idx;
508 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
509 arg_types[arg_idx++] = ctx->i32; // wave id
510 sgpr_count = arg_idx;
511 arg_types[arg_idx++] = ctx->i32; // vtx0
512 arg_types[arg_idx++] = ctx->i32; // vtx1
513 arg_types[arg_idx++] = ctx->i32; // prim id
514 arg_types[arg_idx++] = ctx->i32; // vtx2
515 arg_types[arg_idx++] = ctx->i32; // vtx3
516 arg_types[arg_idx++] = ctx->i32; // vtx4
517 arg_types[arg_idx++] = ctx->i32; // vtx5
518 arg_types[arg_idx++] = ctx->i32; // GS instance id
519 break;
520 case MESA_SHADER_FRAGMENT:
521 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
522 user_sgpr_count = arg_idx;
523 arg_types[arg_idx++] = ctx->i32; /* prim mask */
524 sgpr_count = arg_idx;
525 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
526 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
527 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
528 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
529 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
530 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
531 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
532 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
533 arg_types[arg_idx++] = ctx->f32; /* pos x float */
534 arg_types[arg_idx++] = ctx->f32; /* pos y float */
535 arg_types[arg_idx++] = ctx->f32; /* pos z float */
536 arg_types[arg_idx++] = ctx->f32; /* pos w float */
537 arg_types[arg_idx++] = ctx->i32; /* front face */
538 arg_types[arg_idx++] = ctx->i32; /* ancillary */
539 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
540 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
541 break;
542 default:
543 unreachable("Shader stage not implemented");
544 }
545
546 ctx->main_function = create_llvm_function(
547 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
548 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
549 set_llvm_calling_convention(ctx->main_function, ctx->stage);
550
551 ctx->shader_info->num_input_sgprs = 0;
552 ctx->shader_info->num_input_vgprs = 0;
553
554 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
555 for (i = 0; i < user_sgpr_count; i++)
556 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
557
558 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
559 for (; i < sgpr_count; i++)
560 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
561
562 if (ctx->stage != MESA_SHADER_FRAGMENT)
563 for (; i < arg_idx; ++i)
564 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
565
566 arg_idx = 0;
567 user_sgpr_idx = 0;
568
569 if (ctx->options->supports_spill || need_ring_offsets) {
570 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
571 user_sgpr_idx += 2;
572 if (ctx->options->supports_spill) {
573 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
574 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
575 NULL, 0, AC_FUNC_ATTR_READNONE);
576 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
577 const_array(ctx->v16i8, 8), "");
578 } else
579 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
580 }
581
582 for (unsigned i = 0; i < num_sets; ++i) {
583 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
584 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
585 user_sgpr_idx += 2;
586 ctx->descriptor_sets[i] =
587 LLVMGetParam(ctx->main_function, arg_idx++);
588 } else
589 ctx->descriptor_sets[i] = NULL;
590 }
591
592 if (need_push_constants) {
593 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
594 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
595 user_sgpr_idx += 2;
596 }
597
598 switch (ctx->stage) {
599 case MESA_SHADER_COMPUTE:
600 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
601 user_sgpr_idx += 3;
602 ctx->num_work_groups =
603 LLVMGetParam(ctx->main_function, arg_idx++);
604 ctx->workgroup_ids =
605 LLVMGetParam(ctx->main_function, arg_idx++);
606 ctx->tg_size =
607 LLVMGetParam(ctx->main_function, arg_idx++);
608 ctx->local_invocation_ids =
609 LLVMGetParam(ctx->main_function, arg_idx++);
610 break;
611 case MESA_SHADER_VERTEX:
612 if (!ctx->is_gs_copy_shader) {
613 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
614 user_sgpr_idx += 2;
615 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
616 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
617 user_sgpr_idx += 3;
618 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
619 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
620 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
621 }
622 if (ctx->options->key.vs.as_es)
623 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
624 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
625 if (!ctx->is_gs_copy_shader) {
626 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
627 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
628 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
629 }
630 break;
631 case MESA_SHADER_GEOMETRY:
632 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
633 user_sgpr_idx += 2;
634 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
635 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
636 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
638 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
639 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
640 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
641 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
642 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
643 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
644 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
645 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
646 break;
647 case MESA_SHADER_FRAGMENT:
648 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
649 user_sgpr_idx += 2;
650 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
651 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
652 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
653 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
655 arg_idx++;
656 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
657 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
658 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
659 arg_idx++; /* line stipple */
660 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
661 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
662 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
663 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
664 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
665 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
666 break;
667 default:
668 unreachable("Shader stage not implemented");
669 }
670 }
671
672 static void setup_types(struct nir_to_llvm_context *ctx)
673 {
674 LLVMValueRef args[4];
675
676 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
677 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
678 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
679 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
680 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
681 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
682 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
683 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
684 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
685 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
686 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
687 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
688 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
689 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
690 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
691 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
692
693 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
694 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
695 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
696 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
697
698 args[0] = ctx->f32zero;
699 args[1] = ctx->f32zero;
700 args[2] = ctx->f32zero;
701 args[3] = ctx->f32one;
702 ctx->v4f32empty = LLVMConstVector(args, 4);
703
704 ctx->uniform_md_kind =
705 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
706 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
707
708 args[0] = LLVMConstReal(ctx->f32, 2.5);
709 }
710
711 static int get_llvm_num_components(LLVMValueRef value)
712 {
713 LLVMTypeRef type = LLVMTypeOf(value);
714 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
715 ? LLVMGetVectorSize(type)
716 : 1;
717 return num_components;
718 }
719
720 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
721 LLVMValueRef value,
722 int index)
723 {
724 int count = get_llvm_num_components(value);
725
726 assert(index < count);
727 if (count == 1)
728 return value;
729
730 return LLVMBuildExtractElement(ctx->builder, value,
731 LLVMConstInt(ctx->i32, index, false), "");
732 }
733
734 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
735 LLVMValueRef value, unsigned count)
736 {
737 unsigned num_components = get_llvm_num_components(value);
738 if (count == num_components)
739 return value;
740
741 LLVMValueRef masks[] = {
742 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
743 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
744
745 if (count == 1)
746 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
747 "");
748
749 LLVMValueRef swizzle = LLVMConstVector(masks, count);
750 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
751 }
752
753 static void
754 build_store_values_extended(struct nir_to_llvm_context *ctx,
755 LLVMValueRef *values,
756 unsigned value_count,
757 unsigned value_stride,
758 LLVMValueRef vec)
759 {
760 LLVMBuilderRef builder = ctx->builder;
761 unsigned i;
762
763 if (value_count == 1) {
764 LLVMBuildStore(builder, vec, values[0]);
765 return;
766 }
767
768 for (i = 0; i < value_count; i++) {
769 LLVMValueRef ptr = values[i * value_stride];
770 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
771 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
772 LLVMBuildStore(builder, value, ptr);
773 }
774 }
775
776 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
777 nir_ssa_def *def)
778 {
779 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
780 if (def->num_components > 1) {
781 type = LLVMVectorType(type, def->num_components);
782 }
783 return type;
784 }
785
786 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
787 {
788 assert(src.is_ssa);
789 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
790 return (LLVMValueRef)entry->data;
791 }
792
793
794 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
795 struct nir_block *b)
796 {
797 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
798 return (LLVMBasicBlockRef)entry->data;
799 }
800
801 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
802 nir_alu_src src,
803 unsigned num_components)
804 {
805 LLVMValueRef value = get_src(ctx, src.src);
806 bool need_swizzle = false;
807
808 assert(value);
809 LLVMTypeRef type = LLVMTypeOf(value);
810 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
811 ? LLVMGetVectorSize(type)
812 : 1;
813
814 for (unsigned i = 0; i < num_components; ++i) {
815 assert(src.swizzle[i] < src_components);
816 if (src.swizzle[i] != i)
817 need_swizzle = true;
818 }
819
820 if (need_swizzle || num_components != src_components) {
821 LLVMValueRef masks[] = {
822 LLVMConstInt(ctx->i32, src.swizzle[0], false),
823 LLVMConstInt(ctx->i32, src.swizzle[1], false),
824 LLVMConstInt(ctx->i32, src.swizzle[2], false),
825 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
826
827 if (src_components > 1 && num_components == 1) {
828 value = LLVMBuildExtractElement(ctx->builder, value,
829 masks[0], "");
830 } else if (src_components == 1 && num_components > 1) {
831 LLVMValueRef values[] = {value, value, value, value};
832 value = ac_build_gather_values(&ctx->ac, values, num_components);
833 } else {
834 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
835 value = LLVMBuildShuffleVector(ctx->builder, value, value,
836 swizzle, "");
837 }
838 }
839 assert(!src.negate);
840 assert(!src.abs);
841 return value;
842 }
843
844 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
845 LLVMIntPredicate pred, LLVMValueRef src0,
846 LLVMValueRef src1)
847 {
848 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
849 return LLVMBuildSelect(ctx->builder, result,
850 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
851 LLVMConstInt(ctx->i32, 0, false), "");
852 }
853
854 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
855 LLVMRealPredicate pred, LLVMValueRef src0,
856 LLVMValueRef src1)
857 {
858 LLVMValueRef result;
859 src0 = to_float(ctx, src0);
860 src1 = to_float(ctx, src1);
861 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
862 return LLVMBuildSelect(ctx->builder, result,
863 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
864 LLVMConstInt(ctx->i32, 0, false), "");
865 }
866
867 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
868 const char *intrin,
869 LLVMTypeRef result_type,
870 LLVMValueRef src0)
871 {
872 char name[64];
873 LLVMValueRef params[] = {
874 to_float(ctx, src0),
875 };
876
877 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
878 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
879 }
880
881 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
882 const char *intrin,
883 LLVMTypeRef result_type,
884 LLVMValueRef src0, LLVMValueRef src1)
885 {
886 char name[64];
887 LLVMValueRef params[] = {
888 to_float(ctx, src0),
889 to_float(ctx, src1),
890 };
891
892 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
893 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
894 }
895
896 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
897 const char *intrin,
898 LLVMTypeRef result_type,
899 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
900 {
901 char name[64];
902 LLVMValueRef params[] = {
903 to_float(ctx, src0),
904 to_float(ctx, src1),
905 to_float(ctx, src2),
906 };
907
908 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
909 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
910 }
911
912 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
913 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
914 {
915 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
916 ctx->i32zero, "");
917 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
918 }
919
920 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
921 LLVMValueRef src0)
922 {
923 LLVMValueRef params[2] = {
924 src0,
925
926 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
927 * add special code to check for x=0. The reason is that
928 * the LLVM behavior for x=0 is different from what we
929 * need here.
930 *
931 * The hardware already implements the correct behavior.
932 */
933 LLVMConstInt(ctx->i32, 1, false),
934 };
935 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
936 }
937
938 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
939 LLVMValueRef src0)
940 {
941 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.flbit.i32",
942 ctx->i32, &src0, 1,
943 AC_FUNC_ATTR_READNONE);
944
945 /* The HW returns the last bit index from MSB, but NIR wants
946 * the index from LSB. Invert it by doing "31 - msb". */
947 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
948 msb, "");
949
950 LLVMValueRef all_ones = LLVMConstInt(ctx->i32, -1, true);
951 LLVMValueRef cond = LLVMBuildOr(ctx->builder,
952 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
953 src0, ctx->i32zero, ""),
954 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
955 src0, all_ones, ""), "");
956
957 return LLVMBuildSelect(ctx->builder, cond, all_ones, msb, "");
958 }
959
960 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
961 LLVMValueRef src0)
962 {
963 LLVMValueRef args[2] = {
964 src0,
965 ctx->i32one,
966 };
967 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctlz.i32",
968 ctx->i32, args, ARRAY_SIZE(args),
969 AC_FUNC_ATTR_READNONE);
970
971 /* The HW returns the last bit index from MSB, but NIR wants
972 * the index from LSB. Invert it by doing "31 - msb". */
973 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
974 msb, "");
975
976 return LLVMBuildSelect(ctx->builder,
977 LLVMBuildICmp(ctx->builder, LLVMIntEQ, src0,
978 ctx->i32zero, ""),
979 LLVMConstInt(ctx->i32, -1, true), msb, "");
980 }
981
982 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
983 LLVMIntPredicate pred,
984 LLVMValueRef src0, LLVMValueRef src1)
985 {
986 return LLVMBuildSelect(ctx->builder,
987 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
988 src0,
989 src1, "");
990
991 }
992 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
993 LLVMValueRef src0)
994 {
995 return emit_minmax_int(ctx, LLVMIntSGT, src0,
996 LLVMBuildNeg(ctx->builder, src0, ""));
997 }
998
999 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1000 LLVMValueRef src0)
1001 {
1002 LLVMValueRef cmp, val;
1003
1004 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1005 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1006 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1007 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1008 return val;
1009 }
1010
1011 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1012 LLVMValueRef src0)
1013 {
1014 LLVMValueRef cmp, val;
1015
1016 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1017 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1018 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1019 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1020 return val;
1021 }
1022
1023 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1024 LLVMValueRef src0)
1025 {
1026 const char *intr = "llvm.floor.f32";
1027 LLVMValueRef fsrc0 = to_float(ctx, src0);
1028 LLVMValueRef params[] = {
1029 fsrc0,
1030 };
1031 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
1032 ctx->f32, params, 1,
1033 AC_FUNC_ATTR_READNONE);
1034 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1035 }
1036
1037 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1038 const char *intrin,
1039 LLVMValueRef src0, LLVMValueRef src1)
1040 {
1041 LLVMTypeRef ret_type;
1042 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1043 LLVMValueRef res;
1044 LLVMValueRef params[] = { src0, src1 };
1045 ret_type = LLVMStructTypeInContext(ctx->context, types,
1046 2, true);
1047
1048 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1049 params, 2, AC_FUNC_ATTR_READNONE);
1050
1051 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1052 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1053 return res;
1054 }
1055
1056 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1057 LLVMValueRef src0)
1058 {
1059 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1060 }
1061
1062 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1063 LLVMValueRef src0, LLVMValueRef src1)
1064 {
1065 LLVMValueRef dst64, result;
1066 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1067 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1068
1069 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1070 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1071 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1072 return result;
1073 }
1074
1075 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1076 LLVMValueRef src0, LLVMValueRef src1)
1077 {
1078 LLVMValueRef dst64, result;
1079 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1080 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1081
1082 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1083 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1084 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1085 return result;
1086 }
1087
1088 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1089 const char *intrin,
1090 LLVMValueRef srcs[3])
1091 {
1092 LLVMValueRef result;
1093 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1094 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1095
1096 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1097 return result;
1098 }
1099
1100 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1101 LLVMValueRef src0, LLVMValueRef src1,
1102 LLVMValueRef src2, LLVMValueRef src3)
1103 {
1104 LLVMValueRef bfi_args[3], result;
1105
1106 bfi_args[0] = LLVMBuildShl(ctx->builder,
1107 LLVMBuildSub(ctx->builder,
1108 LLVMBuildShl(ctx->builder,
1109 ctx->i32one,
1110 src3, ""),
1111 ctx->i32one, ""),
1112 src2, "");
1113 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1114 bfi_args[2] = src0;
1115
1116 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1117
1118 /* Calculate:
1119 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1120 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1121 */
1122 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1123 LLVMBuildAnd(ctx->builder, bfi_args[0],
1124 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1125
1126 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1127 return result;
1128 }
1129
1130 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1131 LLVMValueRef src0)
1132 {
1133 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1134 int i;
1135 LLVMValueRef comp[2];
1136
1137 src0 = to_float(ctx, src0);
1138 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1139 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1140 for (i = 0; i < 2; i++) {
1141 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1142 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1143 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1144 }
1145
1146 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1147 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1148
1149 return comp[0];
1150 }
1151
1152 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1153 LLVMValueRef src0)
1154 {
1155 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1156 LLVMValueRef temps[2], result, val;
1157 int i;
1158
1159 for (i = 0; i < 2; i++) {
1160 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1161 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1162 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1163 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1164 }
1165
1166 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1167 ctx->i32zero, "");
1168 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1169 ctx->i32one, "");
1170 return result;
1171 }
1172
1173 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1174 nir_op op,
1175 LLVMValueRef src0)
1176 {
1177 unsigned mask;
1178 int idx;
1179 LLVMValueRef result;
1180 ctx->has_ddxy = true;
1181
1182 if (!ctx->lds && !ctx->has_ds_bpermute)
1183 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1184 LLVMArrayType(ctx->i32, 64),
1185 "ddxy_lds", LOCAL_ADDR_SPACE);
1186
1187 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1188 mask = AC_TID_MASK_LEFT;
1189 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1190 mask = AC_TID_MASK_TOP;
1191 else
1192 mask = AC_TID_MASK_TOP_LEFT;
1193
1194 /* for DDX we want to next X pixel, DDY next Y pixel. */
1195 if (op == nir_op_fddx_fine ||
1196 op == nir_op_fddx_coarse ||
1197 op == nir_op_fddx)
1198 idx = 1;
1199 else
1200 idx = 2;
1201
1202 result = ac_emit_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1203 mask, idx, ctx->lds,
1204 src0);
1205 return result;
1206 }
1207
1208 /*
1209 * this takes an I,J coordinate pair,
1210 * and works out the X and Y derivatives.
1211 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1212 */
1213 static LLVMValueRef emit_ddxy_interp(
1214 struct nir_to_llvm_context *ctx,
1215 LLVMValueRef interp_ij)
1216 {
1217 LLVMValueRef result[4], a;
1218 unsigned i;
1219
1220 for (i = 0; i < 2; i++) {
1221 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1222 LLVMConstInt(ctx->i32, i, false), "");
1223 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1224 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1225 }
1226 return ac_build_gather_values(&ctx->ac, result, 4);
1227 }
1228
1229 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1230 {
1231 LLVMValueRef src[4], result = NULL;
1232 unsigned num_components = instr->dest.dest.ssa.num_components;
1233 unsigned src_components;
1234 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1235
1236 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1237 switch (instr->op) {
1238 case nir_op_vec2:
1239 case nir_op_vec3:
1240 case nir_op_vec4:
1241 src_components = 1;
1242 break;
1243 case nir_op_pack_half_2x16:
1244 src_components = 2;
1245 break;
1246 case nir_op_unpack_half_2x16:
1247 src_components = 1;
1248 break;
1249 default:
1250 src_components = num_components;
1251 break;
1252 }
1253 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1254 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1255
1256 switch (instr->op) {
1257 case nir_op_fmov:
1258 case nir_op_imov:
1259 result = src[0];
1260 break;
1261 case nir_op_fneg:
1262 src[0] = to_float(ctx, src[0]);
1263 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1264 break;
1265 case nir_op_ineg:
1266 result = LLVMBuildNeg(ctx->builder, src[0], "");
1267 break;
1268 case nir_op_inot:
1269 result = LLVMBuildNot(ctx->builder, src[0], "");
1270 break;
1271 case nir_op_iadd:
1272 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1273 break;
1274 case nir_op_fadd:
1275 src[0] = to_float(ctx, src[0]);
1276 src[1] = to_float(ctx, src[1]);
1277 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1278 break;
1279 case nir_op_fsub:
1280 src[0] = to_float(ctx, src[0]);
1281 src[1] = to_float(ctx, src[1]);
1282 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1283 break;
1284 case nir_op_isub:
1285 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1286 break;
1287 case nir_op_imul:
1288 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1289 break;
1290 case nir_op_imod:
1291 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1292 break;
1293 case nir_op_umod:
1294 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1295 break;
1296 case nir_op_fmod:
1297 src[0] = to_float(ctx, src[0]);
1298 src[1] = to_float(ctx, src[1]);
1299 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1300 result = emit_intrin_1f_param(ctx, "llvm.floor",
1301 to_float_type(ctx, def_type), result);
1302 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1303 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1304 break;
1305 case nir_op_frem:
1306 src[0] = to_float(ctx, src[0]);
1307 src[1] = to_float(ctx, src[1]);
1308 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1309 break;
1310 case nir_op_irem:
1311 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1312 break;
1313 case nir_op_idiv:
1314 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1315 break;
1316 case nir_op_udiv:
1317 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1318 break;
1319 case nir_op_fmul:
1320 src[0] = to_float(ctx, src[0]);
1321 src[1] = to_float(ctx, src[1]);
1322 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1323 break;
1324 case nir_op_fdiv:
1325 src[0] = to_float(ctx, src[0]);
1326 src[1] = to_float(ctx, src[1]);
1327 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1328 break;
1329 case nir_op_frcp:
1330 src[0] = to_float(ctx, src[0]);
1331 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1332 break;
1333 case nir_op_iand:
1334 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1335 break;
1336 case nir_op_ior:
1337 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1338 break;
1339 case nir_op_ixor:
1340 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1341 break;
1342 case nir_op_ishl:
1343 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1344 break;
1345 case nir_op_ishr:
1346 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1347 break;
1348 case nir_op_ushr:
1349 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1350 break;
1351 case nir_op_ilt:
1352 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1353 break;
1354 case nir_op_ine:
1355 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1356 break;
1357 case nir_op_ieq:
1358 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1359 break;
1360 case nir_op_ige:
1361 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1362 break;
1363 case nir_op_ult:
1364 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1365 break;
1366 case nir_op_uge:
1367 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1368 break;
1369 case nir_op_feq:
1370 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1371 break;
1372 case nir_op_fne:
1373 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1374 break;
1375 case nir_op_flt:
1376 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1377 break;
1378 case nir_op_fge:
1379 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1380 break;
1381 case nir_op_fabs:
1382 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1383 to_float_type(ctx, def_type), src[0]);
1384 break;
1385 case nir_op_iabs:
1386 result = emit_iabs(ctx, src[0]);
1387 break;
1388 case nir_op_imax:
1389 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1390 break;
1391 case nir_op_imin:
1392 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1393 break;
1394 case nir_op_umax:
1395 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1396 break;
1397 case nir_op_umin:
1398 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1399 break;
1400 case nir_op_isign:
1401 result = emit_isign(ctx, src[0]);
1402 break;
1403 case nir_op_fsign:
1404 src[0] = to_float(ctx, src[0]);
1405 result = emit_fsign(ctx, src[0]);
1406 break;
1407 case nir_op_ffloor:
1408 result = emit_intrin_1f_param(ctx, "llvm.floor",
1409 to_float_type(ctx, def_type), src[0]);
1410 break;
1411 case nir_op_ftrunc:
1412 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1413 to_float_type(ctx, def_type), src[0]);
1414 break;
1415 case nir_op_fceil:
1416 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1417 to_float_type(ctx, def_type), src[0]);
1418 break;
1419 case nir_op_fround_even:
1420 result = emit_intrin_1f_param(ctx, "llvm.rint",
1421 to_float_type(ctx, def_type),src[0]);
1422 break;
1423 case nir_op_ffract:
1424 result = emit_ffract(ctx, src[0]);
1425 break;
1426 case nir_op_fsin:
1427 result = emit_intrin_1f_param(ctx, "llvm.sin",
1428 to_float_type(ctx, def_type), src[0]);
1429 break;
1430 case nir_op_fcos:
1431 result = emit_intrin_1f_param(ctx, "llvm.cos",
1432 to_float_type(ctx, def_type), src[0]);
1433 break;
1434 case nir_op_fsqrt:
1435 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1436 to_float_type(ctx, def_type), src[0]);
1437 break;
1438 case nir_op_fexp2:
1439 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1440 to_float_type(ctx, def_type), src[0]);
1441 break;
1442 case nir_op_flog2:
1443 result = emit_intrin_1f_param(ctx, "llvm.log2",
1444 to_float_type(ctx, def_type), src[0]);
1445 break;
1446 case nir_op_frsq:
1447 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1448 to_float_type(ctx, def_type), src[0]);
1449 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1450 break;
1451 case nir_op_fpow:
1452 result = emit_intrin_2f_param(ctx, "llvm.pow",
1453 to_float_type(ctx, def_type), src[0], src[1]);
1454 break;
1455 case nir_op_fmax:
1456 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1457 to_float_type(ctx, def_type), src[0], src[1]);
1458 break;
1459 case nir_op_fmin:
1460 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1461 to_float_type(ctx, def_type), src[0], src[1]);
1462 break;
1463 case nir_op_ffma:
1464 result = emit_intrin_3f_param(ctx, "llvm.fma",
1465 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1466 break;
1467 case nir_op_ibitfield_extract:
1468 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1469 break;
1470 case nir_op_ubitfield_extract:
1471 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1472 break;
1473 case nir_op_bitfield_insert:
1474 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1475 break;
1476 case nir_op_bitfield_reverse:
1477 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1478 break;
1479 case nir_op_bit_count:
1480 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1481 break;
1482 case nir_op_vec2:
1483 case nir_op_vec3:
1484 case nir_op_vec4:
1485 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1486 src[i] = to_integer(ctx, src[i]);
1487 result = ac_build_gather_values(&ctx->ac, src, num_components);
1488 break;
1489 case nir_op_d2i:
1490 case nir_op_f2i:
1491 src[0] = to_float(ctx, src[0]);
1492 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1493 break;
1494 case nir_op_d2u:
1495 case nir_op_f2u:
1496 src[0] = to_float(ctx, src[0]);
1497 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1498 break;
1499 case nir_op_i2d:
1500 case nir_op_i2f:
1501 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1502 break;
1503 case nir_op_u2d:
1504 case nir_op_u2f:
1505 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1506 break;
1507 case nir_op_f2d:
1508 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1509 break;
1510 case nir_op_d2f:
1511 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1512 break;
1513 case nir_op_bcsel:
1514 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1515 break;
1516 case nir_op_find_lsb:
1517 result = emit_find_lsb(ctx, src[0]);
1518 break;
1519 case nir_op_ufind_msb:
1520 result = emit_ufind_msb(ctx, src[0]);
1521 break;
1522 case nir_op_ifind_msb:
1523 result = emit_ifind_msb(ctx, src[0]);
1524 break;
1525 case nir_op_uadd_carry:
1526 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1527 break;
1528 case nir_op_usub_borrow:
1529 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1530 break;
1531 case nir_op_b2f:
1532 result = emit_b2f(ctx, src[0]);
1533 break;
1534 case nir_op_fquantize2f16:
1535 src[0] = to_float(ctx, src[0]);
1536 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1537 /* need to convert back up to f32 */
1538 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1539 break;
1540 case nir_op_umul_high:
1541 result = emit_umul_high(ctx, src[0], src[1]);
1542 break;
1543 case nir_op_imul_high:
1544 result = emit_imul_high(ctx, src[0], src[1]);
1545 break;
1546 case nir_op_pack_half_2x16:
1547 result = emit_pack_half_2x16(ctx, src[0]);
1548 break;
1549 case nir_op_unpack_half_2x16:
1550 result = emit_unpack_half_2x16(ctx, src[0]);
1551 break;
1552 case nir_op_fddx:
1553 case nir_op_fddy:
1554 case nir_op_fddx_fine:
1555 case nir_op_fddy_fine:
1556 case nir_op_fddx_coarse:
1557 case nir_op_fddy_coarse:
1558 result = emit_ddxy(ctx, instr->op, src[0]);
1559 break;
1560 default:
1561 fprintf(stderr, "Unknown NIR alu instr: ");
1562 nir_print_instr(&instr->instr, stderr);
1563 fprintf(stderr, "\n");
1564 abort();
1565 }
1566
1567 if (result) {
1568 assert(instr->dest.dest.is_ssa);
1569 result = to_integer(ctx, result);
1570 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1571 result);
1572 }
1573 }
1574
1575 static void visit_load_const(struct nir_to_llvm_context *ctx,
1576 nir_load_const_instr *instr)
1577 {
1578 LLVMValueRef values[4], value = NULL;
1579 LLVMTypeRef element_type =
1580 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1581
1582 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1583 switch (instr->def.bit_size) {
1584 case 32:
1585 values[i] = LLVMConstInt(element_type,
1586 instr->value.u32[i], false);
1587 break;
1588 case 64:
1589 values[i] = LLVMConstInt(element_type,
1590 instr->value.u64[i], false);
1591 break;
1592 default:
1593 fprintf(stderr,
1594 "unsupported nir load_const bit_size: %d\n",
1595 instr->def.bit_size);
1596 abort();
1597 }
1598 }
1599 if (instr->def.num_components > 1) {
1600 value = LLVMConstVector(values, instr->def.num_components);
1601 } else
1602 value = values[0];
1603
1604 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1605 }
1606
1607 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1608 LLVMTypeRef type)
1609 {
1610 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1611 return LLVMBuildBitCast(ctx->builder, ptr,
1612 LLVMPointerType(type, addr_space), "");
1613 }
1614
1615 static LLVMValueRef
1616 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1617 {
1618 LLVMValueRef size =
1619 LLVMBuildExtractElement(ctx->builder, descriptor,
1620 LLVMConstInt(ctx->i32, 2, false), "");
1621
1622 /* VI only */
1623 if (ctx->options->chip_class >= VI && in_elements) {
1624 /* On VI, the descriptor contains the size in bytes,
1625 * but TXQ must return the size in elements.
1626 * The stride is always non-zero for resources using TXQ.
1627 */
1628 LLVMValueRef stride =
1629 LLVMBuildExtractElement(ctx->builder, descriptor,
1630 LLVMConstInt(ctx->i32, 1, false), "");
1631 stride = LLVMBuildLShr(ctx->builder, stride,
1632 LLVMConstInt(ctx->i32, 16, false), "");
1633 stride = LLVMBuildAnd(ctx->builder, stride,
1634 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1635
1636 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1637 }
1638 return size;
1639 }
1640
1641 /**
1642 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1643 * intrinsic names).
1644 */
1645 static void build_int_type_name(
1646 LLVMTypeRef type,
1647 char *buf, unsigned bufsize)
1648 {
1649 assert(bufsize >= 6);
1650
1651 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1652 snprintf(buf, bufsize, "v%ui32",
1653 LLVMGetVectorSize(type));
1654 else
1655 strcpy(buf, "i32");
1656 }
1657
1658 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1659 struct ac_tex_info *tinfo,
1660 nir_tex_instr *instr,
1661 const char *intr_name,
1662 unsigned coord_vgpr_index)
1663 {
1664 LLVMValueRef coord = tinfo->args[0];
1665 LLVMValueRef half_texel[2];
1666 int c;
1667
1668 //TODO Rect
1669 {
1670 LLVMValueRef txq_args[10];
1671 int txq_arg_count = 0;
1672 LLVMValueRef size;
1673 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1674 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1675 txq_args[txq_arg_count++] = tinfo->args[1];
1676 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1677 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1678 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1679 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1680 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1681 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1682 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1683 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1684 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1685 txq_args, txq_arg_count,
1686 AC_FUNC_ATTR_READNONE);
1687
1688 for (c = 0; c < 2; c++) {
1689 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1690 LLVMConstInt(ctx->i32, c, false), "");
1691 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1692 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1693 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1694 LLVMConstReal(ctx->f32, -0.5), "");
1695 }
1696 }
1697
1698 for (c = 0; c < 2; c++) {
1699 LLVMValueRef tmp;
1700 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1701 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1702 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1703 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1704 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1705 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1706 }
1707
1708 tinfo->args[0] = coord;
1709 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1710 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1711
1712 }
1713
1714 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1715 nir_tex_instr *instr,
1716 struct ac_tex_info *tinfo)
1717 {
1718 const char *name = "llvm.SI.image.sample";
1719 const char *infix = "";
1720 char intr_name[127];
1721 char type[64];
1722 bool is_shadow = instr->is_shadow;
1723 bool has_offset = tinfo->has_offset;
1724 switch (instr->op) {
1725 case nir_texop_txf:
1726 case nir_texop_txf_ms:
1727 case nir_texop_samples_identical:
1728 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1729 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1730 "llvm.SI.image.load.mip";
1731 is_shadow = false;
1732 has_offset = false;
1733 break;
1734 case nir_texop_txb:
1735 infix = ".b";
1736 break;
1737 case nir_texop_txl:
1738 infix = ".l";
1739 break;
1740 case nir_texop_txs:
1741 name = "llvm.SI.getresinfo";
1742 break;
1743 case nir_texop_query_levels:
1744 name = "llvm.SI.getresinfo";
1745 break;
1746 case nir_texop_tex:
1747 if (ctx->stage != MESA_SHADER_FRAGMENT)
1748 infix = ".lz";
1749 break;
1750 case nir_texop_txd:
1751 infix = ".d";
1752 break;
1753 case nir_texop_tg4:
1754 name = "llvm.SI.gather4";
1755 infix = ".lz";
1756 break;
1757 case nir_texop_lod:
1758 name = "llvm.SI.getlod";
1759 is_shadow = false;
1760 has_offset = false;
1761 break;
1762 default:
1763 break;
1764 }
1765
1766 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1767 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1768 has_offset ? ".o" : "", type);
1769
1770 if (instr->op == nir_texop_tg4) {
1771 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1772 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1773 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1774 (int)has_offset + (int)is_shadow);
1775 }
1776 }
1777 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1778 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1779
1780 }
1781
1782 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1783 nir_intrinsic_instr *instr)
1784 {
1785 LLVMValueRef index = get_src(ctx, instr->src[0]);
1786 unsigned desc_set = nir_intrinsic_desc_set(instr);
1787 unsigned binding = nir_intrinsic_binding(instr);
1788 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1789 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1790 unsigned base_offset = layout->binding[binding].offset;
1791 LLVMValueRef offset, stride;
1792
1793 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1794 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1795 desc_ptr = ctx->push_constants;
1796 base_offset = ctx->options->layout->push_constant_size;
1797 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1798 stride = LLVMConstInt(ctx->i32, 16, false);
1799 } else
1800 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1801
1802 offset = LLVMConstInt(ctx->i32, base_offset, false);
1803 index = LLVMBuildMul(ctx->builder, index, stride, "");
1804 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1805
1806 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1807 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1808 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1809
1810 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1811 }
1812
1813 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1814 nir_intrinsic_instr *instr)
1815 {
1816 LLVMValueRef ptr, addr;
1817
1818 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1819 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1820
1821 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1822 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1823
1824 return LLVMBuildLoad(ctx->builder, ptr, "");
1825 }
1826
1827 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1828 nir_intrinsic_instr *instr)
1829 {
1830 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1831
1832 return get_buffer_size(ctx, desc, false);
1833 }
1834 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1835 nir_intrinsic_instr *instr)
1836 {
1837 const char *store_name;
1838 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1839 LLVMTypeRef data_type = ctx->f32;
1840 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1841 int components_32bit = elem_size_mult * instr->num_components;
1842 unsigned writemask = nir_intrinsic_write_mask(instr);
1843 LLVMValueRef base_data, base_offset;
1844 LLVMValueRef params[6];
1845
1846 if (ctx->stage == MESA_SHADER_FRAGMENT)
1847 ctx->shader_info->fs.writes_memory = true;
1848
1849 params[1] = get_src(ctx, instr->src[1]);
1850 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1851 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1852 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1853
1854 if (components_32bit > 1)
1855 data_type = LLVMVectorType(ctx->f32, components_32bit);
1856
1857 base_data = to_float(ctx, src_data);
1858 base_data = trim_vector(ctx, base_data, instr->num_components);
1859 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1860 data_type, "");
1861 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1862 while (writemask) {
1863 int start, count;
1864 LLVMValueRef data;
1865 LLVMValueRef offset;
1866 LLVMValueRef tmp;
1867 u_bit_scan_consecutive_range(&writemask, &start, &count);
1868
1869 /* Due to an LLVM limitation, split 3-element writes
1870 * into a 2-element and a 1-element write. */
1871 if (count == 3) {
1872 writemask |= 1 << (start + 2);
1873 count = 2;
1874 }
1875
1876 start *= elem_size_mult;
1877 count *= elem_size_mult;
1878
1879 if (count > 4) {
1880 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1881 count = 4;
1882 }
1883
1884 if (count == 4) {
1885 store_name = "llvm.amdgcn.buffer.store.v4f32";
1886 data = base_data;
1887 } else if (count == 2) {
1888 tmp = LLVMBuildExtractElement(ctx->builder,
1889 base_data, LLVMConstInt(ctx->i32, start, false), "");
1890 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1891 ctx->i32zero, "");
1892
1893 tmp = LLVMBuildExtractElement(ctx->builder,
1894 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1895 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1896 ctx->i32one, "");
1897 store_name = "llvm.amdgcn.buffer.store.v2f32";
1898
1899 } else {
1900 assert(count == 1);
1901 if (get_llvm_num_components(base_data) > 1)
1902 data = LLVMBuildExtractElement(ctx->builder, base_data,
1903 LLVMConstInt(ctx->i32, start, false), "");
1904 else
1905 data = base_data;
1906 store_name = "llvm.amdgcn.buffer.store.f32";
1907 }
1908
1909 offset = base_offset;
1910 if (start != 0) {
1911 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1912 }
1913 params[0] = data;
1914 params[3] = offset;
1915 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1916 ctx->voidt, params, 6, 0);
1917 }
1918 }
1919
1920 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1921 nir_intrinsic_instr *instr)
1922 {
1923 const char *name;
1924 LLVMValueRef params[6];
1925 int arg_count = 0;
1926 if (ctx->stage == MESA_SHADER_FRAGMENT)
1927 ctx->shader_info->fs.writes_memory = true;
1928
1929 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1930 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1931 }
1932 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1933 params[arg_count++] = get_src(ctx, instr->src[0]);
1934 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1935 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1936 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1937
1938 switch (instr->intrinsic) {
1939 case nir_intrinsic_ssbo_atomic_add:
1940 name = "llvm.amdgcn.buffer.atomic.add";
1941 break;
1942 case nir_intrinsic_ssbo_atomic_imin:
1943 name = "llvm.amdgcn.buffer.atomic.smin";
1944 break;
1945 case nir_intrinsic_ssbo_atomic_umin:
1946 name = "llvm.amdgcn.buffer.atomic.umin";
1947 break;
1948 case nir_intrinsic_ssbo_atomic_imax:
1949 name = "llvm.amdgcn.buffer.atomic.smax";
1950 break;
1951 case nir_intrinsic_ssbo_atomic_umax:
1952 name = "llvm.amdgcn.buffer.atomic.umax";
1953 break;
1954 case nir_intrinsic_ssbo_atomic_and:
1955 name = "llvm.amdgcn.buffer.atomic.and";
1956 break;
1957 case nir_intrinsic_ssbo_atomic_or:
1958 name = "llvm.amdgcn.buffer.atomic.or";
1959 break;
1960 case nir_intrinsic_ssbo_atomic_xor:
1961 name = "llvm.amdgcn.buffer.atomic.xor";
1962 break;
1963 case nir_intrinsic_ssbo_atomic_exchange:
1964 name = "llvm.amdgcn.buffer.atomic.swap";
1965 break;
1966 case nir_intrinsic_ssbo_atomic_comp_swap:
1967 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1968 break;
1969 default:
1970 abort();
1971 }
1972
1973 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1974 }
1975
1976 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1977 nir_intrinsic_instr *instr)
1978 {
1979 LLVMValueRef results[2];
1980 int load_components;
1981 int num_components = instr->num_components;
1982 if (instr->dest.ssa.bit_size == 64)
1983 num_components *= 2;
1984
1985 for (int i = 0; i < num_components; i += load_components) {
1986 load_components = MIN2(num_components - i, 4);
1987 const char *load_name;
1988 LLVMTypeRef data_type = ctx->f32;
1989 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
1990 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
1991
1992 if (load_components == 3)
1993 data_type = LLVMVectorType(ctx->f32, 4);
1994 else if (load_components > 1)
1995 data_type = LLVMVectorType(ctx->f32, load_components);
1996
1997 if (load_components >= 3)
1998 load_name = "llvm.amdgcn.buffer.load.v4f32";
1999 else if (load_components == 2)
2000 load_name = "llvm.amdgcn.buffer.load.v2f32";
2001 else if (load_components == 1)
2002 load_name = "llvm.amdgcn.buffer.load.f32";
2003 else
2004 unreachable("unhandled number of components");
2005
2006 LLVMValueRef params[] = {
2007 get_src(ctx, instr->src[0]),
2008 LLVMConstInt(ctx->i32, 0, false),
2009 offset,
2010 LLVMConstInt(ctx->i1, 0, false),
2011 LLVMConstInt(ctx->i1, 0, false),
2012 };
2013
2014 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2015
2016 }
2017
2018 LLVMValueRef ret = results[0];
2019 if (num_components > 4 || num_components == 3) {
2020 LLVMValueRef masks[] = {
2021 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2022 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2023 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2024 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2025 };
2026
2027 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2028 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2029 results[num_components > 4 ? 1 : 0], swizzle, "");
2030 }
2031
2032 return LLVMBuildBitCast(ctx->builder, ret,
2033 get_def_type(ctx, &instr->dest.ssa), "");
2034 }
2035
2036 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2037 nir_intrinsic_instr *instr)
2038 {
2039 LLVMValueRef results[8], ret;
2040 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2041 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2042 int num_components = instr->num_components;
2043
2044 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2045
2046 if (instr->dest.ssa.bit_size == 64)
2047 num_components *= 2;
2048
2049 for (unsigned i = 0; i < num_components; ++i) {
2050 LLVMValueRef params[] = {
2051 rsrc,
2052 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2053 offset, "")
2054 };
2055 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2056 params, 2, AC_FUNC_ATTR_READNONE);
2057 }
2058
2059
2060 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2061 return LLVMBuildBitCast(ctx->builder, ret,
2062 get_def_type(ctx, &instr->dest.ssa), "");
2063 }
2064
2065 static void
2066 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2067 bool vs_in, unsigned *vertex_index_out,
2068 unsigned *const_out, LLVMValueRef *indir_out)
2069 {
2070 unsigned const_offset = 0;
2071 LLVMValueRef offset = NULL;
2072
2073 if (vertex_index_out != NULL) {
2074 tail = tail->child;
2075 nir_deref_array *deref_array = nir_deref_as_array(tail);
2076 *vertex_index_out = deref_array->base_offset;
2077 }
2078
2079 while (tail->child != NULL) {
2080 const struct glsl_type *parent_type = tail->type;
2081 tail = tail->child;
2082
2083 if (tail->deref_type == nir_deref_type_array) {
2084 nir_deref_array *deref_array = nir_deref_as_array(tail);
2085 LLVMValueRef index, stride, local_offset;
2086 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2087
2088 const_offset += size * deref_array->base_offset;
2089 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2090 continue;
2091
2092 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2093 index = get_src(ctx, deref_array->indirect);
2094 stride = LLVMConstInt(ctx->i32, size, 0);
2095 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2096
2097 if (offset)
2098 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2099 else
2100 offset = local_offset;
2101 } else if (tail->deref_type == nir_deref_type_struct) {
2102 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2103
2104 for (unsigned i = 0; i < deref_struct->index; i++) {
2105 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2106 const_offset += glsl_count_attribute_slots(ft, vs_in);
2107 }
2108 } else
2109 unreachable("unsupported deref type");
2110
2111 }
2112
2113 if (const_offset && offset)
2114 offset = LLVMBuildAdd(ctx->builder, offset,
2115 LLVMConstInt(ctx->i32, const_offset, 0),
2116 "");
2117
2118 *const_out = const_offset;
2119 *indir_out = offset;
2120 }
2121
2122 static LLVMValueRef
2123 load_gs_input(struct nir_to_llvm_context *ctx,
2124 nir_intrinsic_instr *instr)
2125 {
2126 LLVMValueRef indir_index, vtx_offset;
2127 unsigned const_index;
2128 LLVMValueRef args[9];
2129 unsigned param, vtx_offset_param;
2130 LLVMValueRef value[4], result;
2131 unsigned vertex_index;
2132 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2133 false, &vertex_index,
2134 &const_index, &indir_index);
2135 vtx_offset_param = vertex_index;
2136 assert(vtx_offset_param < 6);
2137 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2138 LLVMConstInt(ctx->i32, 4, false), "");
2139
2140 for (unsigned i = 0; i < instr->num_components; i++) {
2141 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2142 args[0] = ctx->esgs_ring;
2143 args[1] = vtx_offset;
2144 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2145 args[3] = ctx->i32zero;
2146 args[4] = ctx->i32one; /* OFFEN */
2147 args[5] = ctx->i32zero; /* IDXEN */
2148 args[6] = ctx->i32one; /* GLC */
2149 args[7] = ctx->i32zero; /* SLC */
2150 args[8] = ctx->i32zero; /* TFE */
2151
2152 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2153 ctx->i32, args, 9, AC_FUNC_ATTR_READONLY);
2154 }
2155 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2156
2157 return result;
2158 }
2159
2160 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2161 nir_intrinsic_instr *instr)
2162 {
2163 LLVMValueRef values[8];
2164 int idx = instr->variables[0]->var->data.driver_location;
2165 int ve = instr->dest.ssa.num_components;
2166 LLVMValueRef indir_index;
2167 LLVMValueRef ret;
2168 unsigned const_index;
2169 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2170 instr->variables[0]->var->data.mode == nir_var_shader_in;
2171 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2172 &const_index, &indir_index);
2173
2174 if (instr->dest.ssa.bit_size == 64)
2175 ve *= 2;
2176
2177 switch (instr->variables[0]->var->data.mode) {
2178 case nir_var_shader_in:
2179 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2180 return load_gs_input(ctx, instr);
2181 }
2182 for (unsigned chan = 0; chan < ve; chan++) {
2183 if (indir_index) {
2184 unsigned count = glsl_count_attribute_slots(
2185 instr->variables[0]->var->type,
2186 ctx->stage == MESA_SHADER_VERTEX);
2187 count -= chan / 4;
2188 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2189 &ctx->ac, ctx->inputs + idx + chan, count,
2190 4, false);
2191
2192 values[chan] = LLVMBuildExtractElement(ctx->builder,
2193 tmp_vec,
2194 indir_index, "");
2195 } else
2196 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2197 }
2198 break;
2199 case nir_var_local:
2200 for (unsigned chan = 0; chan < ve; chan++) {
2201 if (indir_index) {
2202 unsigned count = glsl_count_attribute_slots(
2203 instr->variables[0]->var->type, false);
2204 count -= chan / 4;
2205 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2206 &ctx->ac, ctx->locals + idx + chan, count,
2207 4, true);
2208
2209 values[chan] = LLVMBuildExtractElement(ctx->builder,
2210 tmp_vec,
2211 indir_index, "");
2212 } else {
2213 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2214 }
2215 }
2216 break;
2217 case nir_var_shader_out:
2218 for (unsigned chan = 0; chan < ve; chan++) {
2219 if (indir_index) {
2220 unsigned count = glsl_count_attribute_slots(
2221 instr->variables[0]->var->type, false);
2222 count -= chan / 4;
2223 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2224 &ctx->ac, ctx->outputs + idx + chan, count,
2225 4, true);
2226
2227 values[chan] = LLVMBuildExtractElement(ctx->builder,
2228 tmp_vec,
2229 indir_index, "");
2230 } else {
2231 values[chan] = LLVMBuildLoad(ctx->builder,
2232 ctx->outputs[idx + chan + const_index * 4],
2233 "");
2234 }
2235 }
2236 break;
2237 case nir_var_shared: {
2238 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2239 LLVMValueRef derived_ptr;
2240
2241 if (indir_index)
2242 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2243
2244 for (unsigned chan = 0; chan < ve; chan++) {
2245 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2246 if (indir_index)
2247 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2248 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2249
2250 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2251 }
2252 break;
2253 }
2254 default:
2255 unreachable("unhandle variable mode");
2256 }
2257 ret = ac_build_gather_values(&ctx->ac, values, ve);
2258 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2259 }
2260
2261 static void
2262 visit_store_var(struct nir_to_llvm_context *ctx,
2263 nir_intrinsic_instr *instr)
2264 {
2265 LLVMValueRef temp_ptr, value;
2266 int idx = instr->variables[0]->var->data.driver_location;
2267 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2268 int writemask = instr->const_index[0];
2269 LLVMValueRef indir_index;
2270 unsigned const_index;
2271 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2272 NULL, &const_index, &indir_index);
2273
2274 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2275 int old_writemask = writemask;
2276
2277 src = LLVMBuildBitCast(ctx->builder, src,
2278 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2279 "");
2280
2281 writemask = 0;
2282 for (unsigned chan = 0; chan < 4; chan++) {
2283 if (old_writemask & (1 << chan))
2284 writemask |= 3u << (2 * chan);
2285 }
2286 }
2287
2288 switch (instr->variables[0]->var->data.mode) {
2289 case nir_var_shader_out:
2290 for (unsigned chan = 0; chan < 8; chan++) {
2291 int stride = 4;
2292 if (!(writemask & (1 << chan)))
2293 continue;
2294
2295 value = llvm_extract_elem(ctx, src, chan);
2296
2297 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2298 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2299 stride = 1;
2300 if (indir_index) {
2301 unsigned count = glsl_count_attribute_slots(
2302 instr->variables[0]->var->type, false);
2303 count -= chan / 4;
2304 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2305 &ctx->ac, ctx->outputs + idx + chan, count,
2306 stride, true);
2307
2308 if (get_llvm_num_components(tmp_vec) > 1) {
2309 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2310 value, indir_index, "");
2311 } else
2312 tmp_vec = value;
2313 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2314 count, stride, tmp_vec);
2315
2316 } else {
2317 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2318
2319 LLVMBuildStore(ctx->builder, value, temp_ptr);
2320 }
2321 }
2322 break;
2323 case nir_var_local:
2324 for (unsigned chan = 0; chan < 8; chan++) {
2325 if (!(writemask & (1 << chan)))
2326 continue;
2327
2328 value = llvm_extract_elem(ctx, src, chan);
2329 if (indir_index) {
2330 unsigned count = glsl_count_attribute_slots(
2331 instr->variables[0]->var->type, false);
2332 count -= chan / 4;
2333 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2334 &ctx->ac, ctx->locals + idx + chan, count,
2335 4, true);
2336
2337 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2338 value, indir_index, "");
2339 build_store_values_extended(ctx, ctx->locals + idx + chan,
2340 count, 4, tmp_vec);
2341 } else {
2342 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2343
2344 LLVMBuildStore(ctx->builder, value, temp_ptr);
2345 }
2346 }
2347 break;
2348 case nir_var_shared: {
2349 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2350
2351 if (indir_index)
2352 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2353
2354 for (unsigned chan = 0; chan < 8; chan++) {
2355 if (!(writemask & (1 << chan)))
2356 continue;
2357 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2358 LLVMValueRef derived_ptr;
2359
2360 if (indir_index)
2361 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2362
2363 value = llvm_extract_elem(ctx, src, chan);
2364 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2365 LLVMBuildStore(ctx->builder,
2366 to_integer(ctx, value), derived_ptr);
2367 }
2368 break;
2369 }
2370 default:
2371 break;
2372 }
2373 }
2374
2375 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2376 {
2377 switch (dim) {
2378 case GLSL_SAMPLER_DIM_BUF:
2379 return 1;
2380 case GLSL_SAMPLER_DIM_1D:
2381 return array ? 2 : 1;
2382 case GLSL_SAMPLER_DIM_2D:
2383 return array ? 3 : 2;
2384 case GLSL_SAMPLER_DIM_MS:
2385 return array ? 4 : 3;
2386 case GLSL_SAMPLER_DIM_3D:
2387 case GLSL_SAMPLER_DIM_CUBE:
2388 return 3;
2389 case GLSL_SAMPLER_DIM_RECT:
2390 case GLSL_SAMPLER_DIM_SUBPASS:
2391 return 2;
2392 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2393 return 3;
2394 default:
2395 break;
2396 }
2397 return 0;
2398 }
2399
2400 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2401 nir_intrinsic_instr *instr)
2402 {
2403 const struct glsl_type *type = instr->variables[0]->var->type;
2404 if(instr->variables[0]->deref.child)
2405 type = instr->variables[0]->deref.child->type;
2406
2407 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2408 LLVMValueRef coords[4];
2409 LLVMValueRef masks[] = {
2410 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2411 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2412 };
2413 LLVMValueRef res;
2414 int count;
2415 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2416 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2417 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2418 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2419 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2420
2421 count = image_type_to_components_count(dim,
2422 glsl_sampler_type_is_array(type));
2423
2424 if (count == 1) {
2425 if (instr->src[0].ssa->num_components)
2426 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2427 else
2428 res = src0;
2429 } else {
2430 int chan;
2431 if (is_ms)
2432 count--;
2433 for (chan = 0; chan < count; ++chan) {
2434 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2435 }
2436
2437 if (add_frag_pos) {
2438 for (chan = 0; chan < count; ++chan)
2439 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2440 }
2441 if (is_ms) {
2442 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2443 count++;
2444 }
2445
2446 if (count == 3) {
2447 coords[3] = LLVMGetUndef(ctx->i32);
2448 count = 4;
2449 }
2450 res = ac_build_gather_values(&ctx->ac, coords, count);
2451 }
2452 return res;
2453 }
2454
2455 static void build_type_name_for_intr(
2456 LLVMTypeRef type,
2457 char *buf, unsigned bufsize)
2458 {
2459 LLVMTypeRef elem_type = type;
2460
2461 assert(bufsize >= 8);
2462
2463 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2464 int ret = snprintf(buf, bufsize, "v%u",
2465 LLVMGetVectorSize(type));
2466 if (ret < 0) {
2467 char *type_name = LLVMPrintTypeToString(type);
2468 fprintf(stderr, "Error building type name for: %s\n",
2469 type_name);
2470 return;
2471 }
2472 elem_type = LLVMGetElementType(type);
2473 buf += ret;
2474 bufsize -= ret;
2475 }
2476 switch (LLVMGetTypeKind(elem_type)) {
2477 default: break;
2478 case LLVMIntegerTypeKind:
2479 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2480 break;
2481 case LLVMFloatTypeKind:
2482 snprintf(buf, bufsize, "f32");
2483 break;
2484 case LLVMDoubleTypeKind:
2485 snprintf(buf, bufsize, "f64");
2486 break;
2487 }
2488 }
2489
2490 static void get_image_intr_name(const char *base_name,
2491 LLVMTypeRef data_type,
2492 LLVMTypeRef coords_type,
2493 LLVMTypeRef rsrc_type,
2494 char *out_name, unsigned out_len)
2495 {
2496 char coords_type_name[8];
2497
2498 build_type_name_for_intr(coords_type, coords_type_name,
2499 sizeof(coords_type_name));
2500
2501 if (HAVE_LLVM <= 0x0309) {
2502 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2503 } else {
2504 char data_type_name[8];
2505 char rsrc_type_name[8];
2506
2507 build_type_name_for_intr(data_type, data_type_name,
2508 sizeof(data_type_name));
2509 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2510 sizeof(rsrc_type_name));
2511 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2512 data_type_name, coords_type_name, rsrc_type_name);
2513 }
2514 }
2515
2516 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2517 nir_intrinsic_instr *instr)
2518 {
2519 LLVMValueRef params[7];
2520 LLVMValueRef res;
2521 char intrinsic_name[64];
2522 const nir_variable *var = instr->variables[0]->var;
2523 const struct glsl_type *type = var->type;
2524 if(instr->variables[0]->deref.child)
2525 type = instr->variables[0]->deref.child->type;
2526
2527 type = glsl_without_array(type);
2528 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2529 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2530 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2531 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2532 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2533 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2534 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2535 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2536 params, 5, 0);
2537
2538 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2539 res = to_integer(ctx, res);
2540 } else {
2541 bool is_da = glsl_sampler_type_is_array(type) ||
2542 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2543 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2544 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2545 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2546
2547 params[0] = get_image_coords(ctx, instr);
2548 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2549 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2550 if (HAVE_LLVM <= 0x0309) {
2551 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2552 params[4] = da;
2553 params[5] = glc;
2554 params[6] = slc;
2555 } else {
2556 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2557 params[3] = glc;
2558 params[4] = slc;
2559 params[5] = lwe;
2560 params[6] = da;
2561 }
2562
2563 get_image_intr_name("llvm.amdgcn.image.load",
2564 ctx->v4f32, /* vdata */
2565 LLVMTypeOf(params[0]), /* coords */
2566 LLVMTypeOf(params[1]), /* rsrc */
2567 intrinsic_name, sizeof(intrinsic_name));
2568
2569 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2570 params, 7, AC_FUNC_ATTR_READONLY);
2571 }
2572 return to_integer(ctx, res);
2573 }
2574
2575 static void visit_image_store(struct nir_to_llvm_context *ctx,
2576 nir_intrinsic_instr *instr)
2577 {
2578 LLVMValueRef params[8];
2579 char intrinsic_name[64];
2580 const nir_variable *var = instr->variables[0]->var;
2581 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2582 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2583 const struct glsl_type *type = glsl_without_array(var->type);
2584
2585 if (ctx->stage == MESA_SHADER_FRAGMENT)
2586 ctx->shader_info->fs.writes_memory = true;
2587
2588 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2589 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2590 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2591 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2592 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2593 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2594 params[4] = i1false; /* glc */
2595 params[5] = i1false; /* slc */
2596 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2597 params, 6, 0);
2598 } else {
2599 bool is_da = glsl_sampler_type_is_array(type) ||
2600 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2601 LLVMValueRef da = is_da ? i1true : i1false;
2602 LLVMValueRef glc = i1false;
2603 LLVMValueRef slc = i1false;
2604
2605 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2606 params[1] = get_image_coords(ctx, instr); /* coords */
2607 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2608 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2609 if (HAVE_LLVM <= 0x0309) {
2610 params[4] = i1false; /* r128 */
2611 params[5] = da;
2612 params[6] = glc;
2613 params[7] = slc;
2614 } else {
2615 LLVMValueRef lwe = i1false;
2616 params[4] = glc;
2617 params[5] = slc;
2618 params[6] = lwe;
2619 params[7] = da;
2620 }
2621
2622 get_image_intr_name("llvm.amdgcn.image.store",
2623 LLVMTypeOf(params[0]), /* vdata */
2624 LLVMTypeOf(params[1]), /* coords */
2625 LLVMTypeOf(params[2]), /* rsrc */
2626 intrinsic_name, sizeof(intrinsic_name));
2627
2628 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2629 params, 8, 0);
2630 }
2631
2632 }
2633
2634 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2635 nir_intrinsic_instr *instr)
2636 {
2637 LLVMValueRef params[6];
2638 int param_count = 0;
2639 const nir_variable *var = instr->variables[0]->var;
2640 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2641 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2642 const char *base_name = "llvm.amdgcn.image.atomic";
2643 const char *atomic_name;
2644 LLVMValueRef coords;
2645 char intrinsic_name[32], coords_type[8];
2646 const struct glsl_type *type = glsl_without_array(var->type);
2647
2648 if (ctx->stage == MESA_SHADER_FRAGMENT)
2649 ctx->shader_info->fs.writes_memory = true;
2650
2651 params[param_count++] = get_src(ctx, instr->src[2]);
2652 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2653 params[param_count++] = get_src(ctx, instr->src[3]);
2654
2655 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2656 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2657 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2658 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2659 params[param_count++] = ctx->i32zero; /* voffset */
2660 params[param_count++] = i1false; /* glc */
2661 params[param_count++] = i1false; /* slc */
2662 } else {
2663 bool da = glsl_sampler_type_is_array(type) ||
2664 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2665
2666 coords = params[param_count++] = get_image_coords(ctx, instr);
2667 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2668 params[param_count++] = i1false; /* r128 */
2669 params[param_count++] = da ? i1true : i1false; /* da */
2670 params[param_count++] = i1false; /* slc */
2671 }
2672
2673 switch (instr->intrinsic) {
2674 case nir_intrinsic_image_atomic_add:
2675 atomic_name = "add";
2676 break;
2677 case nir_intrinsic_image_atomic_min:
2678 atomic_name = "smin";
2679 break;
2680 case nir_intrinsic_image_atomic_max:
2681 atomic_name = "smax";
2682 break;
2683 case nir_intrinsic_image_atomic_and:
2684 atomic_name = "and";
2685 break;
2686 case nir_intrinsic_image_atomic_or:
2687 atomic_name = "or";
2688 break;
2689 case nir_intrinsic_image_atomic_xor:
2690 atomic_name = "xor";
2691 break;
2692 case nir_intrinsic_image_atomic_exchange:
2693 atomic_name = "swap";
2694 break;
2695 case nir_intrinsic_image_atomic_comp_swap:
2696 atomic_name = "cmpswap";
2697 break;
2698 default:
2699 abort();
2700 }
2701 build_int_type_name(LLVMTypeOf(coords),
2702 coords_type, sizeof(coords_type));
2703
2704 snprintf(intrinsic_name, sizeof(intrinsic_name),
2705 "%s.%s.%s", base_name, atomic_name, coords_type);
2706 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2707 }
2708
2709 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2710 nir_intrinsic_instr *instr)
2711 {
2712 LLVMValueRef res;
2713 LLVMValueRef params[10];
2714 const nir_variable *var = instr->variables[0]->var;
2715 const struct glsl_type *type = instr->variables[0]->var->type;
2716 bool da = glsl_sampler_type_is_array(var->type) ||
2717 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2718 if(instr->variables[0]->deref.child)
2719 type = instr->variables[0]->deref.child->type;
2720
2721 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2722 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2723 params[0] = ctx->i32zero;
2724 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2725 params[2] = LLVMConstInt(ctx->i32, 15, false);
2726 params[3] = ctx->i32zero;
2727 params[4] = ctx->i32zero;
2728 params[5] = da ? ctx->i32one : ctx->i32zero;
2729 params[6] = ctx->i32zero;
2730 params[7] = ctx->i32zero;
2731 params[8] = ctx->i32zero;
2732 params[9] = ctx->i32zero;
2733
2734 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2735 params, 10, AC_FUNC_ATTR_READNONE);
2736
2737 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2738 glsl_sampler_type_is_array(type)) {
2739 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2740 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2741 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2742 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2743 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2744 }
2745 return res;
2746 }
2747
2748 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2749 {
2750 LLVMValueRef args[1] = {
2751 LLVMConstInt(ctx->i32, 0xf70, false),
2752 };
2753 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2754 ctx->voidt, args, 1, 0);
2755 }
2756
2757 static void emit_barrier(struct nir_to_llvm_context *ctx)
2758 {
2759 // TODO tess
2760 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2761 ctx->voidt, NULL, 0, 0);
2762 }
2763
2764 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2765 nir_intrinsic_instr *instr)
2766 {
2767 LLVMValueRef cond;
2768 ctx->shader_info->fs.can_discard = true;
2769
2770 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2771 get_src(ctx, instr->src[0]),
2772 ctx->i32zero, "");
2773
2774 cond = LLVMBuildSelect(ctx->builder, cond,
2775 LLVMConstReal(ctx->f32, -1.0f),
2776 ctx->f32zero, "");
2777 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2778 ctx->voidt,
2779 &cond, 1, 0);
2780 }
2781
2782 static LLVMValueRef
2783 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2784 {
2785 LLVMValueRef result;
2786 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2787 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2788 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2789
2790 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2791 }
2792
2793 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2794 nir_intrinsic_instr *instr)
2795 {
2796 LLVMValueRef ptr, result;
2797 int idx = instr->variables[0]->var->data.driver_location;
2798 LLVMValueRef src = get_src(ctx, instr->src[0]);
2799 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2800
2801 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2802 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2803 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2804 ptr, src, src1,
2805 LLVMAtomicOrderingSequentiallyConsistent,
2806 LLVMAtomicOrderingSequentiallyConsistent,
2807 false);
2808 } else {
2809 LLVMAtomicRMWBinOp op;
2810 switch (instr->intrinsic) {
2811 case nir_intrinsic_var_atomic_add:
2812 op = LLVMAtomicRMWBinOpAdd;
2813 break;
2814 case nir_intrinsic_var_atomic_umin:
2815 op = LLVMAtomicRMWBinOpUMin;
2816 break;
2817 case nir_intrinsic_var_atomic_umax:
2818 op = LLVMAtomicRMWBinOpUMax;
2819 break;
2820 case nir_intrinsic_var_atomic_imin:
2821 op = LLVMAtomicRMWBinOpMin;
2822 break;
2823 case nir_intrinsic_var_atomic_imax:
2824 op = LLVMAtomicRMWBinOpMax;
2825 break;
2826 case nir_intrinsic_var_atomic_and:
2827 op = LLVMAtomicRMWBinOpAnd;
2828 break;
2829 case nir_intrinsic_var_atomic_or:
2830 op = LLVMAtomicRMWBinOpOr;
2831 break;
2832 case nir_intrinsic_var_atomic_xor:
2833 op = LLVMAtomicRMWBinOpXor;
2834 break;
2835 case nir_intrinsic_var_atomic_exchange:
2836 op = LLVMAtomicRMWBinOpXchg;
2837 break;
2838 default:
2839 return NULL;
2840 }
2841
2842 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2843 LLVMAtomicOrderingSequentiallyConsistent,
2844 false);
2845 }
2846 return result;
2847 }
2848
2849 #define INTERP_CENTER 0
2850 #define INTERP_CENTROID 1
2851 #define INTERP_SAMPLE 2
2852
2853 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2854 enum glsl_interp_mode interp, unsigned location)
2855 {
2856 switch (interp) {
2857 case INTERP_MODE_FLAT:
2858 default:
2859 return NULL;
2860 case INTERP_MODE_SMOOTH:
2861 case INTERP_MODE_NONE:
2862 if (location == INTERP_CENTER)
2863 return ctx->persp_center;
2864 else if (location == INTERP_CENTROID)
2865 return ctx->persp_centroid;
2866 else if (location == INTERP_SAMPLE)
2867 return ctx->persp_sample;
2868 break;
2869 case INTERP_MODE_NOPERSPECTIVE:
2870 if (location == INTERP_CENTER)
2871 return ctx->linear_center;
2872 else if (location == INTERP_CENTROID)
2873 return ctx->linear_centroid;
2874 else if (location == INTERP_SAMPLE)
2875 return ctx->linear_sample;
2876 break;
2877 }
2878 return NULL;
2879 }
2880
2881 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2882 LLVMValueRef sample_id)
2883 {
2884 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2885 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2886 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2887 LLVMValueRef result[2];
2888
2889 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2890 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2891
2892 return ac_build_gather_values(&ctx->ac, result, 2);
2893 }
2894
2895 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2896 {
2897 LLVMValueRef values[2];
2898
2899 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2900 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2901 return ac_build_gather_values(&ctx->ac, values, 2);
2902 }
2903
2904 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2905 nir_intrinsic_instr *instr)
2906 {
2907 LLVMValueRef result[2];
2908 LLVMValueRef interp_param, attr_number;
2909 unsigned location;
2910 unsigned chan;
2911 LLVMValueRef src_c0, src_c1;
2912 LLVMValueRef src0;
2913 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2914 switch (instr->intrinsic) {
2915 case nir_intrinsic_interp_var_at_centroid:
2916 location = INTERP_CENTROID;
2917 break;
2918 case nir_intrinsic_interp_var_at_sample:
2919 case nir_intrinsic_interp_var_at_offset:
2920 location = INTERP_SAMPLE;
2921 src0 = get_src(ctx, instr->src[0]);
2922 break;
2923 default:
2924 break;
2925 }
2926
2927 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2928 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2929 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2930 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2931 LLVMValueRef sample_position;
2932 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2933
2934 /* fetch sample ID */
2935 sample_position = load_sample_position(ctx, src0);
2936
2937 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2938 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2939 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2940 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2941 }
2942 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2943 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2944
2945 if (location == INTERP_SAMPLE) {
2946 LLVMValueRef ij_out[2];
2947 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2948
2949 /*
2950 * take the I then J parameters, and the DDX/Y for it, and
2951 * calculate the IJ inputs for the interpolator.
2952 * temp1 = ddx * offset/sample.x + I;
2953 * interp_param.I = ddy * offset/sample.y + temp1;
2954 * temp1 = ddx * offset/sample.x + J;
2955 * interp_param.J = ddy * offset/sample.y + temp1;
2956 */
2957 for (unsigned i = 0; i < 2; i++) {
2958 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
2959 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
2960 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
2961 ddxy_out, ix_ll, "");
2962 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
2963 ddxy_out, iy_ll, "");
2964 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
2965 interp_param, ix_ll, "");
2966 LLVMValueRef temp1, temp2;
2967
2968 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
2969 ctx->f32, "");
2970
2971 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
2972 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
2973
2974 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
2975 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
2976
2977 ij_out[i] = LLVMBuildBitCast(ctx->builder,
2978 temp2, ctx->i32, "");
2979 }
2980 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
2981
2982 }
2983
2984 for (chan = 0; chan < 2; chan++) {
2985 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
2986
2987 if (interp_param) {
2988 interp_param = LLVMBuildBitCast(ctx->builder,
2989 interp_param, LLVMVectorType(ctx->f32, 2), "");
2990 LLVMValueRef i = LLVMBuildExtractElement(
2991 ctx->builder, interp_param, ctx->i32zero, "");
2992 LLVMValueRef j = LLVMBuildExtractElement(
2993 ctx->builder, interp_param, ctx->i32one, "");
2994
2995 result[chan] = ac_build_fs_interp(&ctx->ac,
2996 llvm_chan, attr_number,
2997 ctx->prim_mask, i, j);
2998 } else {
2999 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3000 LLVMConstInt(ctx->i32, 2, false),
3001 llvm_chan, attr_number,
3002 ctx->prim_mask);
3003 }
3004 }
3005 return ac_build_gather_values(&ctx->ac, result, 2);
3006 }
3007
3008 static void
3009 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3010 nir_intrinsic_instr *instr)
3011 {
3012 LLVMValueRef gs_next_vertex;
3013 LLVMValueRef can_emit, kill;
3014 LLVMValueRef args[2];
3015 int idx;
3016
3017 assert(instr->const_index[0] == 0);
3018 /* Write vertex attribute values to GSVS ring */
3019 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3020 ctx->gs_next_vertex,
3021 "");
3022
3023 /* If this thread has already emitted the declared maximum number of
3024 * vertices, kill it: excessive vertex emissions are not supposed to
3025 * have any effect, and GS threads have no externally observable
3026 * effects other than emitting vertices.
3027 */
3028 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3029 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3030
3031 kill = LLVMBuildSelect(ctx->builder, can_emit,
3032 LLVMConstReal(ctx->f32, 1.0f),
3033 LLVMConstReal(ctx->f32, -1.0f), "");
3034 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3035 ctx->voidt, &kill, 1, 0);
3036
3037 /* loop num outputs */
3038 idx = 0;
3039 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3040 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3041 if (!(ctx->output_mask & (1ull << i)))
3042 continue;
3043
3044 for (unsigned j = 0; j < 4; j++) {
3045 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3046 out_ptr[j], "");
3047 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (idx * 4 + j) * ctx->gs_max_out_vertices, false);
3048 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3049 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3050
3051 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3052
3053 ac_build_tbuffer_store(&ctx->ac, ctx->gsvs_ring,
3054 out_val, 1,
3055 voffset, ctx->gs2vs_offset, 0,
3056 V_008F0C_BUF_DATA_FORMAT_32,
3057 V_008F0C_BUF_NUM_FORMAT_UINT,
3058 1, 0, 1, 1, 0);
3059 }
3060 idx++;
3061 }
3062
3063 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3064 ctx->i32one, "");
3065 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3066 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (0 << 8), false);
3067 args[1] = ctx->gs_wave_id;
3068 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
3069 ctx->voidt, args, 2, 0);
3070 }
3071
3072 static void
3073 visit_end_primitive(struct nir_to_llvm_context *ctx,
3074 nir_intrinsic_instr *instr)
3075 {
3076 LLVMValueRef args[2];
3077
3078 assert(instr->const_index[0] == 0);
3079 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_CUT | SENDMSG_GS | (0 << 8), false);
3080 args[1] = ctx->gs_wave_id;
3081
3082 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg", ctx->voidt,
3083 args, 2, 0);
3084 }
3085
3086 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3087 nir_intrinsic_instr *instr)
3088 {
3089 LLVMValueRef result = NULL;
3090
3091 switch (instr->intrinsic) {
3092 case nir_intrinsic_load_work_group_id: {
3093 result = ctx->workgroup_ids;
3094 break;
3095 }
3096 case nir_intrinsic_load_base_vertex: {
3097 result = ctx->base_vertex;
3098 break;
3099 }
3100 case nir_intrinsic_load_vertex_id_zero_base: {
3101 result = ctx->vertex_id;
3102 break;
3103 }
3104 case nir_intrinsic_load_local_invocation_id: {
3105 result = ctx->local_invocation_ids;
3106 break;
3107 }
3108 case nir_intrinsic_load_base_instance:
3109 result = ctx->start_instance;
3110 break;
3111 case nir_intrinsic_load_draw_id:
3112 result = ctx->draw_index;
3113 break;
3114 case nir_intrinsic_load_invocation_id:
3115 result = ctx->gs_invocation_id;
3116 break;
3117 case nir_intrinsic_load_primitive_id:
3118 if (ctx->stage == MESA_SHADER_GEOMETRY)
3119 result = ctx->gs_prim_id;
3120 else
3121 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3122 break;
3123 case nir_intrinsic_load_sample_id:
3124 ctx->shader_info->fs.force_persample = true;
3125 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3126 break;
3127 case nir_intrinsic_load_sample_pos:
3128 ctx->shader_info->fs.force_persample = true;
3129 result = load_sample_pos(ctx);
3130 break;
3131 case nir_intrinsic_load_front_face:
3132 result = ctx->front_face;
3133 break;
3134 case nir_intrinsic_load_instance_id:
3135 result = ctx->instance_id;
3136 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3137 ctx->shader_info->vs.vgpr_comp_cnt);
3138 break;
3139 case nir_intrinsic_load_num_work_groups:
3140 result = ctx->num_work_groups;
3141 break;
3142 case nir_intrinsic_load_local_invocation_index:
3143 result = visit_load_local_invocation_index(ctx);
3144 break;
3145 case nir_intrinsic_load_push_constant:
3146 result = visit_load_push_constant(ctx, instr);
3147 break;
3148 case nir_intrinsic_vulkan_resource_index:
3149 result = visit_vulkan_resource_index(ctx, instr);
3150 break;
3151 case nir_intrinsic_store_ssbo:
3152 visit_store_ssbo(ctx, instr);
3153 break;
3154 case nir_intrinsic_load_ssbo:
3155 result = visit_load_buffer(ctx, instr);
3156 break;
3157 case nir_intrinsic_ssbo_atomic_add:
3158 case nir_intrinsic_ssbo_atomic_imin:
3159 case nir_intrinsic_ssbo_atomic_umin:
3160 case nir_intrinsic_ssbo_atomic_imax:
3161 case nir_intrinsic_ssbo_atomic_umax:
3162 case nir_intrinsic_ssbo_atomic_and:
3163 case nir_intrinsic_ssbo_atomic_or:
3164 case nir_intrinsic_ssbo_atomic_xor:
3165 case nir_intrinsic_ssbo_atomic_exchange:
3166 case nir_intrinsic_ssbo_atomic_comp_swap:
3167 result = visit_atomic_ssbo(ctx, instr);
3168 break;
3169 case nir_intrinsic_load_ubo:
3170 result = visit_load_ubo_buffer(ctx, instr);
3171 break;
3172 case nir_intrinsic_get_buffer_size:
3173 result = visit_get_buffer_size(ctx, instr);
3174 break;
3175 case nir_intrinsic_load_var:
3176 result = visit_load_var(ctx, instr);
3177 break;
3178 case nir_intrinsic_store_var:
3179 visit_store_var(ctx, instr);
3180 break;
3181 case nir_intrinsic_image_load:
3182 result = visit_image_load(ctx, instr);
3183 break;
3184 case nir_intrinsic_image_store:
3185 visit_image_store(ctx, instr);
3186 break;
3187 case nir_intrinsic_image_atomic_add:
3188 case nir_intrinsic_image_atomic_min:
3189 case nir_intrinsic_image_atomic_max:
3190 case nir_intrinsic_image_atomic_and:
3191 case nir_intrinsic_image_atomic_or:
3192 case nir_intrinsic_image_atomic_xor:
3193 case nir_intrinsic_image_atomic_exchange:
3194 case nir_intrinsic_image_atomic_comp_swap:
3195 result = visit_image_atomic(ctx, instr);
3196 break;
3197 case nir_intrinsic_image_size:
3198 result = visit_image_size(ctx, instr);
3199 break;
3200 case nir_intrinsic_discard:
3201 ctx->shader_info->fs.can_discard = true;
3202 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3203 ctx->voidt,
3204 NULL, 0, 0);
3205 break;
3206 case nir_intrinsic_discard_if:
3207 emit_discard_if(ctx, instr);
3208 break;
3209 case nir_intrinsic_memory_barrier:
3210 emit_waitcnt(ctx);
3211 break;
3212 case nir_intrinsic_barrier:
3213 emit_barrier(ctx);
3214 break;
3215 case nir_intrinsic_var_atomic_add:
3216 case nir_intrinsic_var_atomic_imin:
3217 case nir_intrinsic_var_atomic_umin:
3218 case nir_intrinsic_var_atomic_imax:
3219 case nir_intrinsic_var_atomic_umax:
3220 case nir_intrinsic_var_atomic_and:
3221 case nir_intrinsic_var_atomic_or:
3222 case nir_intrinsic_var_atomic_xor:
3223 case nir_intrinsic_var_atomic_exchange:
3224 case nir_intrinsic_var_atomic_comp_swap:
3225 result = visit_var_atomic(ctx, instr);
3226 break;
3227 case nir_intrinsic_interp_var_at_centroid:
3228 case nir_intrinsic_interp_var_at_sample:
3229 case nir_intrinsic_interp_var_at_offset:
3230 result = visit_interp(ctx, instr);
3231 break;
3232 case nir_intrinsic_emit_vertex:
3233 visit_emit_vertex(ctx, instr);
3234 break;
3235 case nir_intrinsic_end_primitive:
3236 visit_end_primitive(ctx, instr);
3237 break;
3238 default:
3239 fprintf(stderr, "Unknown intrinsic: ");
3240 nir_print_instr(&instr->instr, stderr);
3241 fprintf(stderr, "\n");
3242 break;
3243 }
3244 if (result) {
3245 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3246 }
3247 }
3248
3249 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3250 nir_deref_var *deref,
3251 enum desc_type desc_type)
3252 {
3253 unsigned desc_set = deref->var->data.descriptor_set;
3254 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3255 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3256 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3257 unsigned offset = binding->offset;
3258 unsigned stride = binding->size;
3259 unsigned type_size;
3260 LLVMBuilderRef builder = ctx->builder;
3261 LLVMTypeRef type;
3262 LLVMValueRef index = NULL;
3263
3264 assert(deref->var->data.binding < layout->binding_count);
3265
3266 switch (desc_type) {
3267 case DESC_IMAGE:
3268 type = ctx->v8i32;
3269 type_size = 32;
3270 break;
3271 case DESC_FMASK:
3272 type = ctx->v8i32;
3273 offset += 32;
3274 type_size = 32;
3275 break;
3276 case DESC_SAMPLER:
3277 type = ctx->v4i32;
3278 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3279 offset += 64;
3280
3281 type_size = 16;
3282 break;
3283 case DESC_BUFFER:
3284 type = ctx->v4i32;
3285 type_size = 16;
3286 break;
3287 default:
3288 unreachable("invalid desc_type\n");
3289 }
3290
3291 if (deref->deref.child) {
3292 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3293
3294 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3295 offset += child->base_offset * stride;
3296 if (child->deref_array_type == nir_deref_array_type_indirect) {
3297 index = get_src(ctx, child->indirect);
3298 }
3299 }
3300
3301 assert(stride % type_size == 0);
3302
3303 if (!index)
3304 index = ctx->i32zero;
3305
3306 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3307
3308 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3309 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3310
3311 return ac_build_indexed_load_const(&ctx->ac, list, index);
3312 }
3313
3314 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3315 struct ac_tex_info *tinfo,
3316 nir_tex_instr *instr,
3317 nir_texop op,
3318 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3319 LLVMValueRef *param, unsigned count,
3320 unsigned dmask)
3321 {
3322 int num_args;
3323 unsigned is_rect = 0;
3324 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3325
3326 if (op == nir_texop_lod)
3327 da = false;
3328 /* Pad to power of two vector */
3329 while (count < util_next_power_of_two(count))
3330 param[count++] = LLVMGetUndef(ctx->i32);
3331
3332 if (count > 1)
3333 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3334 else
3335 tinfo->args[0] = param[0];
3336
3337 tinfo->args[1] = res_ptr;
3338 num_args = 2;
3339
3340 if (op == nir_texop_txf ||
3341 op == nir_texop_txf_ms ||
3342 op == nir_texop_query_levels ||
3343 op == nir_texop_texture_samples ||
3344 op == nir_texop_txs)
3345 tinfo->dst_type = ctx->v4i32;
3346 else {
3347 tinfo->dst_type = ctx->v4f32;
3348 tinfo->args[num_args++] = samp_ptr;
3349 }
3350
3351 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3352 tinfo->args[0] = res_ptr;
3353 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3354 tinfo->args[2] = param[0];
3355 tinfo->arg_count = 3;
3356 return;
3357 }
3358
3359 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3360 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3361 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3362 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3363 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3364 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3365 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3366 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3367
3368 tinfo->arg_count = num_args;
3369 }
3370
3371 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3372 *
3373 * SI-CI:
3374 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3375 * filtering manually. The driver sets img7 to a mask clearing
3376 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3377 * s_and_b32 samp0, samp0, img7
3378 *
3379 * VI:
3380 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3381 */
3382 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3383 LLVMValueRef res, LLVMValueRef samp)
3384 {
3385 LLVMBuilderRef builder = ctx->builder;
3386 LLVMValueRef img7, samp0;
3387
3388 if (ctx->options->chip_class >= VI)
3389 return samp;
3390
3391 img7 = LLVMBuildExtractElement(builder, res,
3392 LLVMConstInt(ctx->i32, 7, 0), "");
3393 samp0 = LLVMBuildExtractElement(builder, samp,
3394 LLVMConstInt(ctx->i32, 0, 0), "");
3395 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3396 return LLVMBuildInsertElement(builder, samp, samp0,
3397 LLVMConstInt(ctx->i32, 0, 0), "");
3398 }
3399
3400 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3401 nir_tex_instr *instr,
3402 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3403 LLVMValueRef *fmask_ptr)
3404 {
3405 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3406 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3407 else
3408 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3409 if (samp_ptr) {
3410 if (instr->sampler)
3411 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3412 else
3413 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3414 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3415 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3416 }
3417 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3418 instr->op == nir_texop_samples_identical))
3419 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3420 }
3421
3422 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3423 LLVMValueRef coord)
3424 {
3425 coord = to_float(ctx, coord);
3426 coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3427 coord = to_integer(ctx, coord);
3428 return coord;
3429 }
3430
3431 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3432 {
3433 LLVMValueRef result = NULL;
3434 struct ac_tex_info tinfo = { 0 };
3435 unsigned dmask = 0xf;
3436 LLVMValueRef address[16];
3437 LLVMValueRef coords[5];
3438 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3439 LLVMValueRef bias = NULL, offsets = NULL;
3440 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3441 LLVMValueRef ddx = NULL, ddy = NULL;
3442 LLVMValueRef derivs[6];
3443 unsigned chan, count = 0;
3444 unsigned const_src = 0, num_deriv_comp = 0;
3445
3446 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3447
3448 for (unsigned i = 0; i < instr->num_srcs; i++) {
3449 switch (instr->src[i].src_type) {
3450 case nir_tex_src_coord:
3451 coord = get_src(ctx, instr->src[i].src);
3452 break;
3453 case nir_tex_src_projector:
3454 break;
3455 case nir_tex_src_comparator:
3456 comparator = get_src(ctx, instr->src[i].src);
3457 break;
3458 case nir_tex_src_offset:
3459 offsets = get_src(ctx, instr->src[i].src);
3460 const_src = i;
3461 break;
3462 case nir_tex_src_bias:
3463 bias = get_src(ctx, instr->src[i].src);
3464 break;
3465 case nir_tex_src_lod:
3466 lod = get_src(ctx, instr->src[i].src);
3467 break;
3468 case nir_tex_src_ms_index:
3469 sample_index = get_src(ctx, instr->src[i].src);
3470 break;
3471 case nir_tex_src_ms_mcs:
3472 break;
3473 case nir_tex_src_ddx:
3474 ddx = get_src(ctx, instr->src[i].src);
3475 num_deriv_comp = instr->src[i].src.ssa->num_components;
3476 break;
3477 case nir_tex_src_ddy:
3478 ddy = get_src(ctx, instr->src[i].src);
3479 break;
3480 case nir_tex_src_texture_offset:
3481 case nir_tex_src_sampler_offset:
3482 case nir_tex_src_plane:
3483 default:
3484 break;
3485 }
3486 }
3487
3488 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3489 result = get_buffer_size(ctx, res_ptr, false);
3490 goto write_result;
3491 }
3492
3493 if (instr->op == nir_texop_texture_samples) {
3494 LLVMValueRef res, samples, is_msaa;
3495 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3496 samples = LLVMBuildExtractElement(ctx->builder, res,
3497 LLVMConstInt(ctx->i32, 3, false), "");
3498 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3499 LLVMConstInt(ctx->i32, 28, false), "");
3500 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3501 LLVMConstInt(ctx->i32, 0xe, false), "");
3502 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3503 LLVMConstInt(ctx->i32, 0xe, false), "");
3504
3505 samples = LLVMBuildLShr(ctx->builder, samples,
3506 LLVMConstInt(ctx->i32, 16, false), "");
3507 samples = LLVMBuildAnd(ctx->builder, samples,
3508 LLVMConstInt(ctx->i32, 0xf, false), "");
3509 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3510 samples, "");
3511 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3512 ctx->i32one, "");
3513 result = samples;
3514 goto write_result;
3515 }
3516
3517 if (coord)
3518 for (chan = 0; chan < instr->coord_components; chan++)
3519 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3520
3521 if (offsets && instr->op != nir_texop_txf) {
3522 LLVMValueRef offset[3], pack;
3523 for (chan = 0; chan < 3; ++chan)
3524 offset[chan] = ctx->i32zero;
3525
3526 tinfo.has_offset = true;
3527 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3528 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3529 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3530 LLVMConstInt(ctx->i32, 0x3f, false), "");
3531 if (chan)
3532 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3533 LLVMConstInt(ctx->i32, chan * 8, false), "");
3534 }
3535 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3536 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3537 address[count++] = pack;
3538
3539 }
3540 /* pack LOD bias value */
3541 if (instr->op == nir_texop_txb && bias) {
3542 address[count++] = bias;
3543 }
3544
3545 /* Pack depth comparison value */
3546 if (instr->is_shadow && comparator) {
3547 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3548 }
3549
3550 /* pack derivatives */
3551 if (ddx || ddy) {
3552 switch (instr->sampler_dim) {
3553 case GLSL_SAMPLER_DIM_3D:
3554 case GLSL_SAMPLER_DIM_CUBE:
3555 num_deriv_comp = 3;
3556 break;
3557 case GLSL_SAMPLER_DIM_2D:
3558 default:
3559 num_deriv_comp = 2;
3560 break;
3561 case GLSL_SAMPLER_DIM_1D:
3562 num_deriv_comp = 1;
3563 break;
3564 }
3565
3566 for (unsigned i = 0; i < num_deriv_comp; i++) {
3567 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3568 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3569 }
3570 }
3571
3572 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3573 for (chan = 0; chan < instr->coord_components; chan++)
3574 coords[chan] = to_float(ctx, coords[chan]);
3575 if (instr->coord_components == 3)
3576 coords[3] = LLVMGetUndef(ctx->f32);
3577 ac_prepare_cube_coords(&ctx->ac,
3578 instr->op == nir_texop_txd, instr->is_array,
3579 coords, derivs);
3580 if (num_deriv_comp)
3581 num_deriv_comp--;
3582 }
3583
3584 if (ddx || ddy) {
3585 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3586 address[count++] = derivs[i];
3587 }
3588
3589 /* Pack texture coordinates */
3590 if (coord) {
3591 address[count++] = coords[0];
3592 if (instr->coord_components > 1) {
3593 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3594 coords[1] = apply_round_slice(ctx, coords[1]);
3595 }
3596 address[count++] = coords[1];
3597 }
3598 if (instr->coord_components > 2) {
3599 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3600 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3601 coords[2] = apply_round_slice(ctx, coords[2]);
3602 }
3603 address[count++] = coords[2];
3604 }
3605 }
3606
3607 /* Pack LOD */
3608 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3609 address[count++] = lod;
3610 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3611 address[count++] = sample_index;
3612 } else if(instr->op == nir_texop_txs) {
3613 count = 0;
3614 if (lod)
3615 address[count++] = lod;
3616 else
3617 address[count++] = ctx->i32zero;
3618 }
3619
3620 for (chan = 0; chan < count; chan++) {
3621 address[chan] = LLVMBuildBitCast(ctx->builder,
3622 address[chan], ctx->i32, "");
3623 }
3624
3625 if (instr->op == nir_texop_samples_identical) {
3626 LLVMValueRef txf_address[4];
3627 struct ac_tex_info txf_info = { 0 };
3628 unsigned txf_count = count;
3629 memcpy(txf_address, address, sizeof(txf_address));
3630
3631 if (!instr->is_array)
3632 txf_address[2] = ctx->i32zero;
3633 txf_address[3] = ctx->i32zero;
3634
3635 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3636 fmask_ptr, NULL,
3637 txf_address, txf_count, 0xf);
3638
3639 result = build_tex_intrinsic(ctx, instr, &txf_info);
3640
3641 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3642 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3643 goto write_result;
3644 }
3645
3646 /* Adjust the sample index according to FMASK.
3647 *
3648 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3649 * which is the identity mapping. Each nibble says which physical sample
3650 * should be fetched to get that sample.
3651 *
3652 * For example, 0x11111100 means there are only 2 samples stored and
3653 * the second sample covers 3/4 of the pixel. When reading samples 0
3654 * and 1, return physical sample 0 (determined by the first two 0s
3655 * in FMASK), otherwise return physical sample 1.
3656 *
3657 * The sample index should be adjusted as follows:
3658 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3659 */
3660 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3661 instr->op != nir_texop_txs) {
3662 LLVMValueRef txf_address[4];
3663 struct ac_tex_info txf_info = { 0 };
3664 unsigned txf_count = count;
3665 memcpy(txf_address, address, sizeof(txf_address));
3666
3667 if (!instr->is_array)
3668 txf_address[2] = ctx->i32zero;
3669 txf_address[3] = ctx->i32zero;
3670
3671 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3672 fmask_ptr, NULL,
3673 txf_address, txf_count, 0xf);
3674
3675 result = build_tex_intrinsic(ctx, instr, &txf_info);
3676 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3677 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3678
3679 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3680 result,
3681 ctx->i32zero, "");
3682
3683 unsigned sample_chan = instr->is_array ? 3 : 2;
3684
3685 LLVMValueRef sample_index4 =
3686 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3687 LLVMValueRef shifted_fmask =
3688 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3689 LLVMValueRef final_sample =
3690 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3691
3692 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3693 * resource descriptor is 0 (invalid),
3694 */
3695 LLVMValueRef fmask_desc =
3696 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3697 ctx->v8i32, "");
3698
3699 LLVMValueRef fmask_word1 =
3700 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3701 ctx->i32one, "");
3702
3703 LLVMValueRef word1_is_nonzero =
3704 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3705 fmask_word1, ctx->i32zero, "");
3706
3707 /* Replace the MSAA sample index. */
3708 address[sample_chan] =
3709 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3710 final_sample, address[sample_chan], "");
3711 }
3712
3713 if (offsets && instr->op == nir_texop_txf) {
3714 nir_const_value *const_offset =
3715 nir_src_as_const_value(instr->src[const_src].src);
3716 int num_offsets = instr->src[const_src].src.ssa->num_components;
3717 assert(const_offset);
3718 num_offsets = MIN2(num_offsets, instr->coord_components);
3719 if (num_offsets > 2)
3720 address[2] = LLVMBuildAdd(ctx->builder,
3721 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3722 if (num_offsets > 1)
3723 address[1] = LLVMBuildAdd(ctx->builder,
3724 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3725 address[0] = LLVMBuildAdd(ctx->builder,
3726 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3727
3728 }
3729
3730 /* TODO TG4 support */
3731 if (instr->op == nir_texop_tg4) {
3732 if (instr->is_shadow)
3733 dmask = 1;
3734 else
3735 dmask = 1 << instr->component;
3736 }
3737 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3738 res_ptr, samp_ptr, address, count, dmask);
3739
3740 result = build_tex_intrinsic(ctx, instr, &tinfo);
3741
3742 if (instr->op == nir_texop_query_levels)
3743 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3744 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3745 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3746 else if (instr->op == nir_texop_txs &&
3747 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3748 instr->is_array) {
3749 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3750 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3751 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3752 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3753 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3754 } else if (instr->dest.ssa.num_components != 4)
3755 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3756
3757 write_result:
3758 if (result) {
3759 assert(instr->dest.is_ssa);
3760 result = to_integer(ctx, result);
3761 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3762 }
3763 }
3764
3765
3766 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3767 {
3768 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3769 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3770
3771 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3772 _mesa_hash_table_insert(ctx->phis, instr, result);
3773 }
3774
3775 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3776 nir_phi_instr *instr,
3777 LLVMValueRef llvm_phi)
3778 {
3779 nir_foreach_phi_src(src, instr) {
3780 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3781 LLVMValueRef llvm_src = get_src(ctx, src->src);
3782
3783 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3784 }
3785 }
3786
3787 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3788 {
3789 struct hash_entry *entry;
3790 hash_table_foreach(ctx->phis, entry) {
3791 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3792 (LLVMValueRef)entry->data);
3793 }
3794 }
3795
3796
3797 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3798 nir_ssa_undef_instr *instr)
3799 {
3800 unsigned num_components = instr->def.num_components;
3801 LLVMValueRef undef;
3802
3803 if (num_components == 1)
3804 undef = LLVMGetUndef(ctx->i32);
3805 else {
3806 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3807 }
3808 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3809 }
3810
3811 static void visit_jump(struct nir_to_llvm_context *ctx,
3812 nir_jump_instr *instr)
3813 {
3814 switch (instr->type) {
3815 case nir_jump_break:
3816 LLVMBuildBr(ctx->builder, ctx->break_block);
3817 LLVMClearInsertionPosition(ctx->builder);
3818 break;
3819 case nir_jump_continue:
3820 LLVMBuildBr(ctx->builder, ctx->continue_block);
3821 LLVMClearInsertionPosition(ctx->builder);
3822 break;
3823 default:
3824 fprintf(stderr, "Unknown NIR jump instr: ");
3825 nir_print_instr(&instr->instr, stderr);
3826 fprintf(stderr, "\n");
3827 abort();
3828 }
3829 }
3830
3831 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3832 struct exec_list *list);
3833
3834 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3835 {
3836 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3837 nir_foreach_instr(instr, block)
3838 {
3839 switch (instr->type) {
3840 case nir_instr_type_alu:
3841 visit_alu(ctx, nir_instr_as_alu(instr));
3842 break;
3843 case nir_instr_type_load_const:
3844 visit_load_const(ctx, nir_instr_as_load_const(instr));
3845 break;
3846 case nir_instr_type_intrinsic:
3847 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3848 break;
3849 case nir_instr_type_tex:
3850 visit_tex(ctx, nir_instr_as_tex(instr));
3851 break;
3852 case nir_instr_type_phi:
3853 visit_phi(ctx, nir_instr_as_phi(instr));
3854 break;
3855 case nir_instr_type_ssa_undef:
3856 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3857 break;
3858 case nir_instr_type_jump:
3859 visit_jump(ctx, nir_instr_as_jump(instr));
3860 break;
3861 default:
3862 fprintf(stderr, "Unknown NIR instr type: ");
3863 nir_print_instr(instr, stderr);
3864 fprintf(stderr, "\n");
3865 abort();
3866 }
3867 }
3868
3869 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3870 }
3871
3872 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3873 {
3874 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3875
3876 LLVMBasicBlockRef merge_block =
3877 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3878 LLVMBasicBlockRef if_block =
3879 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3880 LLVMBasicBlockRef else_block = merge_block;
3881 if (!exec_list_is_empty(&if_stmt->else_list))
3882 else_block = LLVMAppendBasicBlockInContext(
3883 ctx->context, ctx->main_function, "");
3884
3885 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3886 LLVMConstInt(ctx->i32, 0, false), "");
3887 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3888
3889 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3890 visit_cf_list(ctx, &if_stmt->then_list);
3891 if (LLVMGetInsertBlock(ctx->builder))
3892 LLVMBuildBr(ctx->builder, merge_block);
3893
3894 if (!exec_list_is_empty(&if_stmt->else_list)) {
3895 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3896 visit_cf_list(ctx, &if_stmt->else_list);
3897 if (LLVMGetInsertBlock(ctx->builder))
3898 LLVMBuildBr(ctx->builder, merge_block);
3899 }
3900
3901 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3902 }
3903
3904 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3905 {
3906 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3907 LLVMBasicBlockRef break_parent = ctx->break_block;
3908
3909 ctx->continue_block =
3910 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3911 ctx->break_block =
3912 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3913
3914 LLVMBuildBr(ctx->builder, ctx->continue_block);
3915 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3916 visit_cf_list(ctx, &loop->body);
3917
3918 if (LLVMGetInsertBlock(ctx->builder))
3919 LLVMBuildBr(ctx->builder, ctx->continue_block);
3920 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3921
3922 ctx->continue_block = continue_parent;
3923 ctx->break_block = break_parent;
3924 }
3925
3926 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3927 struct exec_list *list)
3928 {
3929 foreach_list_typed(nir_cf_node, node, node, list)
3930 {
3931 switch (node->type) {
3932 case nir_cf_node_block:
3933 visit_block(ctx, nir_cf_node_as_block(node));
3934 break;
3935
3936 case nir_cf_node_if:
3937 visit_if(ctx, nir_cf_node_as_if(node));
3938 break;
3939
3940 case nir_cf_node_loop:
3941 visit_loop(ctx, nir_cf_node_as_loop(node));
3942 break;
3943
3944 default:
3945 assert(0);
3946 }
3947 }
3948 }
3949
3950 static void
3951 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3952 struct nir_variable *variable)
3953 {
3954 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3955 LLVMValueRef t_offset;
3956 LLVMValueRef t_list;
3957 LLVMValueRef args[3];
3958 LLVMValueRef input;
3959 LLVMValueRef buffer_index;
3960 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3961 int idx = variable->data.location;
3962 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3963
3964 variable->data.driver_location = idx * 4;
3965
3966 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3967 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3968 ctx->start_instance, "");
3969 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3970 ctx->shader_info->vs.vgpr_comp_cnt);
3971 } else
3972 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3973 ctx->base_vertex, "");
3974
3975 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3976 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3977
3978 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
3979 args[0] = t_list;
3980 args[1] = LLVMConstInt(ctx->i32, 0, false);
3981 args[2] = buffer_index;
3982 input = ac_emit_llvm_intrinsic(&ctx->ac,
3983 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3984 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3985
3986 for (unsigned chan = 0; chan < 4; chan++) {
3987 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3988 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3989 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3990 input, llvm_chan, ""));
3991 }
3992 }
3993 }
3994
3995
3996 static void interp_fs_input(struct nir_to_llvm_context *ctx,
3997 unsigned attr,
3998 LLVMValueRef interp_param,
3999 LLVMValueRef prim_mask,
4000 LLVMValueRef result[4])
4001 {
4002 LLVMValueRef attr_number;
4003 unsigned chan;
4004 LLVMValueRef i, j;
4005 bool interp = interp_param != NULL;
4006
4007 attr_number = LLVMConstInt(ctx->i32, attr, false);
4008
4009 /* fs.constant returns the param from the middle vertex, so it's not
4010 * really useful for flat shading. It's meant to be used for custom
4011 * interpolation (but the intrinsic can't fetch from the other two
4012 * vertices).
4013 *
4014 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4015 * to do the right thing. The only reason we use fs.constant is that
4016 * fs.interp cannot be used on integers, because they can be equal
4017 * to NaN.
4018 */
4019 if (interp) {
4020 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4021 LLVMVectorType(ctx->f32, 2), "");
4022
4023 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4024 ctx->i32zero, "");
4025 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4026 ctx->i32one, "");
4027 }
4028
4029 for (chan = 0; chan < 4; chan++) {
4030 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4031
4032 if (interp) {
4033 result[chan] = ac_build_fs_interp(&ctx->ac,
4034 llvm_chan,
4035 attr_number,
4036 prim_mask, i, j);
4037 } else {
4038 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4039 LLVMConstInt(ctx->i32, 2, false),
4040 llvm_chan,
4041 attr_number,
4042 prim_mask);
4043 }
4044 }
4045 }
4046
4047 static void
4048 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4049 struct nir_variable *variable)
4050 {
4051 int idx = variable->data.location;
4052 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4053 LLVMValueRef interp;
4054
4055 variable->data.driver_location = idx * 4;
4056 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4057
4058 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4059 unsigned interp_type;
4060 if (variable->data.sample) {
4061 interp_type = INTERP_SAMPLE;
4062 ctx->shader_info->fs.force_persample = true;
4063 } else if (variable->data.centroid)
4064 interp_type = INTERP_CENTROID;
4065 else
4066 interp_type = INTERP_CENTER;
4067
4068 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4069 } else
4070 interp = NULL;
4071
4072 for (unsigned i = 0; i < attrib_count; ++i)
4073 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4074
4075 }
4076
4077 static void
4078 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4079 struct nir_variable *variable)
4080 {
4081 switch (ctx->stage) {
4082 case MESA_SHADER_VERTEX:
4083 handle_vs_input_decl(ctx, variable);
4084 break;
4085 case MESA_SHADER_FRAGMENT:
4086 handle_fs_input_decl(ctx, variable);
4087 break;
4088 default:
4089 break;
4090 }
4091
4092 }
4093
4094 static void
4095 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4096 struct nir_shader *nir)
4097 {
4098 unsigned index = 0;
4099 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4100 LLVMValueRef interp_param;
4101 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4102
4103 if (!(ctx->input_mask & (1ull << i)))
4104 continue;
4105
4106 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4107 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4108 interp_param = *inputs;
4109 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4110 inputs);
4111
4112 if (!interp_param)
4113 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4114 ++index;
4115 } else if (i == VARYING_SLOT_POS) {
4116 for(int i = 0; i < 3; ++i)
4117 inputs[i] = ctx->frag_pos[i];
4118
4119 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4120 }
4121 }
4122 ctx->shader_info->fs.num_interp = index;
4123 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4124 ctx->shader_info->fs.has_pcoord = true;
4125 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4126 ctx->shader_info->fs.prim_id_input = true;
4127 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4128 ctx->shader_info->fs.layer_input = true;
4129 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4130 }
4131
4132 static LLVMValueRef
4133 ac_build_alloca(struct nir_to_llvm_context *ctx,
4134 LLVMTypeRef type,
4135 const char *name)
4136 {
4137 LLVMBuilderRef builder = ctx->builder;
4138 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4139 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4140 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4141 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4142 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4143 LLVMValueRef res;
4144
4145 if (first_instr) {
4146 LLVMPositionBuilderBefore(first_builder, first_instr);
4147 } else {
4148 LLVMPositionBuilderAtEnd(first_builder, first_block);
4149 }
4150
4151 res = LLVMBuildAlloca(first_builder, type, name);
4152 LLVMBuildStore(builder, LLVMConstNull(type), res);
4153
4154 LLVMDisposeBuilder(first_builder);
4155
4156 return res;
4157 }
4158
4159 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4160 LLVMTypeRef type,
4161 const char *name)
4162 {
4163 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4164 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4165 return ptr;
4166 }
4167
4168 static void
4169 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4170 struct nir_variable *variable)
4171 {
4172 int idx = variable->data.location + variable->data.index;
4173 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4174
4175 variable->data.driver_location = idx * 4;
4176
4177 if (ctx->stage == MESA_SHADER_VERTEX ||
4178 ctx->stage == MESA_SHADER_GEOMETRY) {
4179 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4180 idx == VARYING_SLOT_CULL_DIST0) {
4181 int length = glsl_get_length(variable->type);
4182 if (ctx->stage == MESA_SHADER_VERTEX) {
4183 if (idx == VARYING_SLOT_CLIP_DIST0) {
4184 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4185 ctx->num_clips = length;
4186 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4187 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4188 ctx->num_culls = length;
4189 }
4190 }
4191 if (length > 4)
4192 attrib_count = 2;
4193 else
4194 attrib_count = 1;
4195 }
4196 }
4197
4198 for (unsigned i = 0; i < attrib_count; ++i) {
4199 for (unsigned chan = 0; chan < 4; chan++) {
4200 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4201 si_build_alloca_undef(ctx, ctx->f32, "");
4202 }
4203 }
4204 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4205 }
4206
4207 static void
4208 setup_locals(struct nir_to_llvm_context *ctx,
4209 struct nir_function *func)
4210 {
4211 int i, j;
4212 ctx->num_locals = 0;
4213 nir_foreach_variable(variable, &func->impl->locals) {
4214 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4215 variable->data.driver_location = ctx->num_locals * 4;
4216 ctx->num_locals += attrib_count;
4217 }
4218 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4219 if (!ctx->locals)
4220 return;
4221
4222 for (i = 0; i < ctx->num_locals; i++) {
4223 for (j = 0; j < 4; j++) {
4224 ctx->locals[i * 4 + j] =
4225 si_build_alloca_undef(ctx, ctx->f32, "temp");
4226 }
4227 }
4228 }
4229
4230 static LLVMValueRef
4231 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4232 {
4233 v = to_float(ctx, v);
4234 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4235 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4236 }
4237
4238
4239 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4240 LLVMValueRef src0, LLVMValueRef src1)
4241 {
4242 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4243 LLVMValueRef comp[2];
4244
4245 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4246 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4247 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4248 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4249 }
4250
4251 /* Initialize arguments for the shader export intrinsic */
4252 static void
4253 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4254 LLVMValueRef *values,
4255 unsigned target,
4256 LLVMValueRef *args)
4257 {
4258 /* Default is 0xf. Adjusted below depending on the format. */
4259 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4260 /* Specify whether the EXEC mask represents the valid mask */
4261 args[1] = LLVMConstInt(ctx->i32, 0, false);
4262
4263 /* Specify whether this is the last export */
4264 args[2] = LLVMConstInt(ctx->i32, 0, false);
4265 /* Specify the target we are exporting */
4266 args[3] = LLVMConstInt(ctx->i32, target, false);
4267
4268 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4269 args[5] = LLVMGetUndef(ctx->f32);
4270 args[6] = LLVMGetUndef(ctx->f32);
4271 args[7] = LLVMGetUndef(ctx->f32);
4272 args[8] = LLVMGetUndef(ctx->f32);
4273
4274 if (!values)
4275 return;
4276
4277 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4278 LLVMValueRef val[4];
4279 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4280 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4281 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4282
4283 switch(col_format) {
4284 case V_028714_SPI_SHADER_ZERO:
4285 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4286 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4287 break;
4288
4289 case V_028714_SPI_SHADER_32_R:
4290 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4291 args[5] = values[0];
4292 break;
4293
4294 case V_028714_SPI_SHADER_32_GR:
4295 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4296 args[5] = values[0];
4297 args[6] = values[1];
4298 break;
4299
4300 case V_028714_SPI_SHADER_32_AR:
4301 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4302 args[5] = values[0];
4303 args[8] = values[3];
4304 break;
4305
4306 case V_028714_SPI_SHADER_FP16_ABGR:
4307 args[4] = ctx->i32one;
4308
4309 for (unsigned chan = 0; chan < 2; chan++) {
4310 LLVMValueRef pack_args[2] = {
4311 values[2 * chan],
4312 values[2 * chan + 1]
4313 };
4314 LLVMValueRef packed;
4315
4316 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4317 ctx->i32, pack_args, 2,
4318 AC_FUNC_ATTR_READNONE);
4319 args[chan + 5] = packed;
4320 }
4321 break;
4322
4323 case V_028714_SPI_SHADER_UNORM16_ABGR:
4324 for (unsigned chan = 0; chan < 4; chan++) {
4325 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4326 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4327 LLVMConstReal(ctx->f32, 65535), "");
4328 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4329 LLVMConstReal(ctx->f32, 0.5), "");
4330 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4331 ctx->i32, "");
4332 }
4333
4334 args[4] = ctx->i32one;
4335 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4336 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4337 break;
4338
4339 case V_028714_SPI_SHADER_SNORM16_ABGR:
4340 for (unsigned chan = 0; chan < 4; chan++) {
4341 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4342 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4343 LLVMConstReal(ctx->f32, 32767), "");
4344
4345 /* If positive, add 0.5, else add -0.5. */
4346 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4347 LLVMBuildSelect(ctx->builder,
4348 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4349 val[chan], ctx->f32zero, ""),
4350 LLVMConstReal(ctx->f32, 0.5),
4351 LLVMConstReal(ctx->f32, -0.5), ""), "");
4352 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4353 }
4354
4355 args[4] = ctx->i32one;
4356 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4357 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4358 break;
4359
4360 case V_028714_SPI_SHADER_UINT16_ABGR: {
4361 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4362
4363 for (unsigned chan = 0; chan < 4; chan++) {
4364 val[chan] = to_integer(ctx, values[chan]);
4365 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4366 }
4367
4368 args[4] = ctx->i32one;
4369 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4370 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4371 break;
4372 }
4373
4374 case V_028714_SPI_SHADER_SINT16_ABGR: {
4375 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4376 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4377
4378 /* Clamp. */
4379 for (unsigned chan = 0; chan < 4; chan++) {
4380 val[chan] = to_integer(ctx, values[chan]);
4381 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4382 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4383 }
4384
4385 args[4] = ctx->i32one;
4386 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4387 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4388 break;
4389 }
4390
4391 default:
4392 case V_028714_SPI_SHADER_32_ABGR:
4393 memcpy(&args[5], values, sizeof(values[0]) * 4);
4394 break;
4395 }
4396 } else
4397 memcpy(&args[5], values, sizeof(values[0]) * 4);
4398
4399 for (unsigned i = 5; i < 9; ++i)
4400 args[i] = to_float(ctx, args[i]);
4401 }
4402
4403 static void
4404 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4405 {
4406 uint32_t param_count = 0;
4407 unsigned target;
4408 unsigned pos_idx, num_pos_exports = 0;
4409 LLVMValueRef args[9];
4410 LLVMValueRef pos_args[4][9] = { { 0 } };
4411 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4412 int i;
4413 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4414 (1ull << VARYING_SLOT_CLIP_DIST1) |
4415 (1ull << VARYING_SLOT_CULL_DIST0) |
4416 (1ull << VARYING_SLOT_CULL_DIST1));
4417
4418 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4419 ctx->shader_info->vs.layer_output = 0xffffffff;
4420 if (clip_mask) {
4421 LLVMValueRef slots[8];
4422 unsigned j;
4423
4424 if (ctx->shader_info->vs.cull_dist_mask)
4425 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_clips;
4426
4427 i = VARYING_SLOT_CLIP_DIST0;
4428 for (j = 0; j < ctx->num_clips; j++)
4429 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4430 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4431 i = VARYING_SLOT_CULL_DIST0;
4432 for (j = 0; j < ctx->num_culls; j++)
4433 slots[ctx->num_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4434 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4435
4436 for (i = ctx->num_clips + ctx->num_culls; i < 8; i++)
4437 slots[i] = LLVMGetUndef(ctx->f32);
4438
4439 if (ctx->num_clips + ctx->num_culls > 4) {
4440 target = V_008DFC_SQ_EXP_POS + 3;
4441 si_llvm_init_export_args(ctx, &slots[4], target, args);
4442 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4443 args, sizeof(args));
4444 }
4445
4446 target = V_008DFC_SQ_EXP_POS + 2;
4447 si_llvm_init_export_args(ctx, &slots[0], target, args);
4448 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4449 args, sizeof(args));
4450
4451 }
4452
4453 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4454 LLVMValueRef values[4];
4455 if (!(ctx->output_mask & (1ull << i)))
4456 continue;
4457
4458 for (unsigned j = 0; j < 4; j++)
4459 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4460 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4461
4462 if (i == VARYING_SLOT_POS) {
4463 target = V_008DFC_SQ_EXP_POS;
4464 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4465 i == VARYING_SLOT_CLIP_DIST1 ||
4466 i == VARYING_SLOT_CULL_DIST0 ||
4467 i == VARYING_SLOT_CULL_DIST1) {
4468 continue;
4469 } else if (i == VARYING_SLOT_PSIZ) {
4470 ctx->shader_info->vs.writes_pointsize = true;
4471 psize_value = values[0];
4472 continue;
4473 } else if (i == VARYING_SLOT_LAYER) {
4474 ctx->shader_info->vs.writes_layer = true;
4475 layer_value = values[0];
4476 ctx->shader_info->vs.layer_output = param_count;
4477 target = V_008DFC_SQ_EXP_PARAM + param_count;
4478 param_count++;
4479 } else if (i == VARYING_SLOT_VIEWPORT) {
4480 ctx->shader_info->vs.writes_viewport_index = true;
4481 viewport_index_value = values[0];
4482 continue;
4483 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4484 ctx->shader_info->vs.prim_id_output = param_count;
4485 target = V_008DFC_SQ_EXP_PARAM + param_count;
4486 param_count++;
4487 } else if (i >= VARYING_SLOT_VAR0) {
4488 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4489 target = V_008DFC_SQ_EXP_PARAM + param_count;
4490 param_count++;
4491 }
4492
4493 si_llvm_init_export_args(ctx, values, target, args);
4494
4495 if (target >= V_008DFC_SQ_EXP_POS &&
4496 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4497 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4498 args, sizeof(args));
4499 } else {
4500 ac_emit_llvm_intrinsic(&ctx->ac,
4501 "llvm.SI.export",
4502 ctx->voidt,
4503 args, 9, 0);
4504 }
4505 }
4506
4507 /* We need to add the position output manually if it's missing. */
4508 if (!pos_args[0][0]) {
4509 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4510 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4511 pos_args[0][2] = ctx->i32zero; /* last export? */
4512 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4513 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4514 pos_args[0][5] = ctx->f32zero; /* X */
4515 pos_args[0][6] = ctx->f32zero; /* Y */
4516 pos_args[0][7] = ctx->f32zero; /* Z */
4517 pos_args[0][8] = ctx->f32one; /* W */
4518 }
4519
4520 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4521 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4522 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4523 if (mask) {
4524 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4525 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4526 pos_args[1][2] = ctx->i32zero; /* last export? */
4527 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4528 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4529 pos_args[1][5] = ctx->f32zero; /* X */
4530 pos_args[1][6] = ctx->f32zero; /* Y */
4531 pos_args[1][7] = ctx->f32zero; /* Z */
4532 pos_args[1][8] = ctx->f32zero; /* W */
4533
4534 if (ctx->shader_info->vs.writes_pointsize == true)
4535 pos_args[1][5] = psize_value;
4536 if (ctx->shader_info->vs.writes_layer == true)
4537 pos_args[1][7] = layer_value;
4538 if (ctx->shader_info->vs.writes_viewport_index == true)
4539 pos_args[1][8] = viewport_index_value;
4540 }
4541 for (i = 0; i < 4; i++) {
4542 if (pos_args[i][0])
4543 num_pos_exports++;
4544 }
4545
4546 pos_idx = 0;
4547 for (i = 0; i < 4; i++) {
4548 if (!pos_args[i][0])
4549 continue;
4550
4551 /* Specify the target we are exporting */
4552 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4553 if (pos_idx == num_pos_exports)
4554 pos_args[i][2] = ctx->i32one;
4555 ac_emit_llvm_intrinsic(&ctx->ac,
4556 "llvm.SI.export",
4557 ctx->voidt,
4558 pos_args[i], 9, 0);
4559 }
4560
4561 ctx->shader_info->vs.pos_exports = num_pos_exports;
4562 ctx->shader_info->vs.param_exports = param_count;
4563 }
4564
4565 static void
4566 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4567 {
4568 int j;
4569 uint64_t max_output_written = 0;
4570 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4571 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4572 int param_index;
4573 if (!(ctx->output_mask & (1ull << i)))
4574 continue;
4575
4576 param_index = shader_io_get_unique_index(i);
4577
4578 if (param_index > max_output_written)
4579 max_output_written = param_index;
4580
4581 for (j = 0; j < 4; j++) {
4582 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4583 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4584
4585 ac_build_tbuffer_store(&ctx->ac,
4586 ctx->esgs_ring,
4587 out_val, 1,
4588 LLVMGetUndef(ctx->i32), ctx->es2gs_offset,
4589 (4 * param_index + j) * 4,
4590 V_008F0C_BUF_DATA_FORMAT_32,
4591 V_008F0C_BUF_NUM_FORMAT_UINT,
4592 0, 0, 1, 1, 0);
4593 }
4594 }
4595 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4596 }
4597
4598 static void
4599 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4600 LLVMValueRef *color, unsigned param, bool is_last)
4601 {
4602 LLVMValueRef args[9];
4603 /* Export */
4604 si_llvm_init_export_args(ctx, color, param,
4605 args);
4606
4607 if (is_last) {
4608 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4609 args[2] = ctx->i32one; /* DONE bit */
4610 } else if (args[0] == ctx->i32zero)
4611 return; /* unnecessary NULL export */
4612
4613 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4614 ctx->voidt, args, 9, 0);
4615 }
4616
4617 static void
4618 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4619 LLVMValueRef depth, LLVMValueRef stencil,
4620 LLVMValueRef samplemask)
4621 {
4622 LLVMValueRef args[9];
4623 unsigned mask = 0;
4624 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4625 args[2] = ctx->i32one; /* DONE bit */
4626 /* Specify the target we are exporting */
4627 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4628
4629 args[4] = ctx->i32zero; /* COMP flag */
4630 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4631 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4632 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4633 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4634
4635 if (depth) {
4636 args[5] = depth;
4637 mask |= 0x1;
4638 }
4639
4640 if (stencil) {
4641 args[6] = stencil;
4642 mask |= 0x2;
4643 }
4644
4645 if (samplemask) {
4646 args[7] = samplemask;
4647 mask |= 0x04;
4648 }
4649
4650 /* SI (except OLAND) has a bug that it only looks
4651 * at the X writemask component. */
4652 if (ctx->options->chip_class == SI &&
4653 ctx->options->family != CHIP_OLAND)
4654 mask |= 0x01;
4655
4656 args[0] = LLVMConstInt(ctx->i32, mask, false);
4657 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4658 ctx->voidt, args, 9, 0);
4659 }
4660
4661 static void
4662 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4663 {
4664 unsigned index = 0;
4665 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4666
4667 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4668 LLVMValueRef values[4];
4669
4670 if (!(ctx->output_mask & (1ull << i)))
4671 continue;
4672
4673 if (i == FRAG_RESULT_DEPTH) {
4674 ctx->shader_info->fs.writes_z = true;
4675 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4676 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4677 } else if (i == FRAG_RESULT_STENCIL) {
4678 ctx->shader_info->fs.writes_stencil = true;
4679 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4680 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4681 } else {
4682 bool last = false;
4683 for (unsigned j = 0; j < 4; j++)
4684 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4685 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4686
4687 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4688 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4689
4690 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4691 index++;
4692 }
4693 }
4694
4695 if (depth || stencil)
4696 si_export_mrt_z(ctx, depth, stencil, samplemask);
4697 else if (!index)
4698 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4699
4700 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4701 }
4702
4703 static void
4704 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4705 {
4706 LLVMValueRef args[2];
4707
4708 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE, false);
4709 args[1] = ctx->gs_wave_id;
4710 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
4711 ctx->voidt, args, 2, 0);
4712 }
4713
4714 static void
4715 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4716 {
4717 switch (ctx->stage) {
4718 case MESA_SHADER_VERTEX:
4719 if (ctx->options->key.vs.as_es)
4720 handle_es_outputs_post(ctx);
4721 else
4722 handle_vs_outputs_post(ctx);
4723 break;
4724 case MESA_SHADER_FRAGMENT:
4725 handle_fs_outputs_post(ctx);
4726 break;
4727 case MESA_SHADER_GEOMETRY:
4728 emit_gs_epilogue(ctx);
4729 break;
4730 default:
4731 break;
4732 }
4733 }
4734
4735 static void
4736 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4737 struct nir_variable *variable, uint32_t *offset, int idx)
4738 {
4739 unsigned size = glsl_count_attribute_slots(variable->type, false);
4740 variable->data.driver_location = *offset;
4741 *offset += size;
4742 }
4743
4744 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4745 {
4746 LLVMPassManagerRef passmgr;
4747 /* Create the pass manager */
4748 passmgr = LLVMCreateFunctionPassManagerForModule(
4749 ctx->module);
4750
4751 /* This pass should eliminate all the load and store instructions */
4752 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4753
4754 /* Add some optimization passes */
4755 LLVMAddScalarReplAggregatesPass(passmgr);
4756 LLVMAddLICMPass(passmgr);
4757 LLVMAddAggressiveDCEPass(passmgr);
4758 LLVMAddCFGSimplificationPass(passmgr);
4759 LLVMAddInstructionCombiningPass(passmgr);
4760
4761 /* Run the pass */
4762 LLVMInitializeFunctionPassManager(passmgr);
4763 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4764 LLVMFinalizeFunctionPassManager(passmgr);
4765
4766 LLVMDisposeBuilder(ctx->builder);
4767 LLVMDisposePassManager(passmgr);
4768 }
4769
4770 static void
4771 ac_setup_rings(struct nir_to_llvm_context *ctx)
4772 {
4773 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4774 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4775 }
4776
4777 if (ctx->is_gs_copy_shader) {
4778 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4779 }
4780 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4781 LLVMValueRef tmp;
4782 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4783 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4784
4785 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4786
4787 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4788 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4789 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4790 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4791
4792 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4793 }
4794 }
4795
4796 static
4797 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4798 struct nir_shader *nir,
4799 struct ac_shader_variant_info *shader_info,
4800 const struct ac_nir_compiler_options *options)
4801 {
4802 struct nir_to_llvm_context ctx = {0};
4803 struct nir_function *func;
4804 unsigned i;
4805 ctx.options = options;
4806 ctx.shader_info = shader_info;
4807 ctx.context = LLVMContextCreate();
4808 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4809
4810 ac_llvm_context_init(&ctx.ac, ctx.context);
4811 ctx.ac.module = ctx.module;
4812
4813 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4814
4815 memset(shader_info, 0, sizeof(*shader_info));
4816
4817 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4818 setup_types(&ctx);
4819
4820 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4821 ctx.ac.builder = ctx.builder;
4822 ctx.stage = nir->stage;
4823
4824 for (i = 0; i < AC_UD_MAX_SETS; i++)
4825 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4826 for (i = 0; i < AC_UD_MAX_UD; i++)
4827 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4828
4829 create_function(&ctx);
4830
4831 if (nir->stage == MESA_SHADER_COMPUTE) {
4832 int num_shared = 0;
4833 nir_foreach_variable(variable, &nir->shared)
4834 num_shared++;
4835 if (num_shared) {
4836 int idx = 0;
4837 uint32_t shared_size = 0;
4838 LLVMValueRef var;
4839 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4840 nir_foreach_variable(variable, &nir->shared) {
4841 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4842 idx++;
4843 }
4844
4845 shared_size *= 16;
4846 var = LLVMAddGlobalInAddressSpace(ctx.module,
4847 LLVMArrayType(ctx.i8, shared_size),
4848 "compute_lds",
4849 LOCAL_ADDR_SPACE);
4850 LLVMSetAlignment(var, 4);
4851 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4852 }
4853 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4854 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4855
4856 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4857 }
4858
4859 ac_setup_rings(&ctx);
4860
4861 nir_foreach_variable(variable, &nir->inputs)
4862 handle_shader_input_decl(&ctx, variable);
4863
4864 if (nir->stage == MESA_SHADER_FRAGMENT)
4865 handle_fs_inputs_pre(&ctx, nir);
4866
4867 nir_foreach_variable(variable, &nir->outputs)
4868 handle_shader_output_decl(&ctx, variable);
4869
4870 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4871 _mesa_key_pointer_equal);
4872 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4873 _mesa_key_pointer_equal);
4874
4875 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4876
4877 setup_locals(&ctx, func);
4878
4879 visit_cf_list(&ctx, &func->impl->body);
4880 phi_post_pass(&ctx);
4881
4882 handle_shader_outputs_post(&ctx);
4883 LLVMBuildRetVoid(ctx.builder);
4884
4885 ac_llvm_finalize_module(&ctx);
4886 free(ctx.locals);
4887 ralloc_free(ctx.defs);
4888 ralloc_free(ctx.phis);
4889
4890 if (nir->stage == MESA_SHADER_GEOMETRY) {
4891 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4892 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4893 nir->info->gs.vertices_out;
4894 }
4895 return ctx.module;
4896 }
4897
4898 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4899 {
4900 unsigned *retval = (unsigned *)context;
4901 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4902 char *description = LLVMGetDiagInfoDescription(di);
4903
4904 if (severity == LLVMDSError) {
4905 *retval = 1;
4906 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4907 description);
4908 }
4909
4910 LLVMDisposeMessage(description);
4911 }
4912
4913 static unsigned ac_llvm_compile(LLVMModuleRef M,
4914 struct ac_shader_binary *binary,
4915 LLVMTargetMachineRef tm)
4916 {
4917 unsigned retval = 0;
4918 char *err;
4919 LLVMContextRef llvm_ctx;
4920 LLVMMemoryBufferRef out_buffer;
4921 unsigned buffer_size;
4922 const char *buffer_data;
4923 LLVMBool mem_err;
4924
4925 /* Setup Diagnostic Handler*/
4926 llvm_ctx = LLVMGetModuleContext(M);
4927
4928 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4929 &retval);
4930
4931 /* Compile IR*/
4932 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4933 &err, &out_buffer);
4934
4935 /* Process Errors/Warnings */
4936 if (mem_err) {
4937 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4938 free(err);
4939 retval = 1;
4940 goto out;
4941 }
4942
4943 /* Extract Shader Code*/
4944 buffer_size = LLVMGetBufferSize(out_buffer);
4945 buffer_data = LLVMGetBufferStart(out_buffer);
4946
4947 ac_elf_read(buffer_data, buffer_size, binary);
4948
4949 /* Clean up */
4950 LLVMDisposeMemoryBuffer(out_buffer);
4951
4952 out:
4953 return retval;
4954 }
4955
4956 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4957 LLVMModuleRef llvm_module,
4958 struct ac_shader_binary *binary,
4959 struct ac_shader_config *config,
4960 struct ac_shader_variant_info *shader_info,
4961 gl_shader_stage stage,
4962 bool dump_shader, bool supports_spill)
4963 {
4964 if (dump_shader)
4965 ac_dump_module(llvm_module);
4966
4967 memset(binary, 0, sizeof(*binary));
4968 int v = ac_llvm_compile(llvm_module, binary, tm);
4969 if (v) {
4970 fprintf(stderr, "compile failed\n");
4971 }
4972
4973 if (dump_shader)
4974 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4975
4976 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4977
4978 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4979 LLVMDisposeModule(llvm_module);
4980 LLVMContextDispose(ctx);
4981
4982 if (stage == MESA_SHADER_FRAGMENT) {
4983 shader_info->num_input_vgprs = 0;
4984 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4985 shader_info->num_input_vgprs += 2;
4986 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4987 shader_info->num_input_vgprs += 2;
4988 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4989 shader_info->num_input_vgprs += 2;
4990 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4991 shader_info->num_input_vgprs += 3;
4992 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
4993 shader_info->num_input_vgprs += 2;
4994 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
4995 shader_info->num_input_vgprs += 2;
4996 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
4997 shader_info->num_input_vgprs += 2;
4998 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
4999 shader_info->num_input_vgprs += 1;
5000 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5001 shader_info->num_input_vgprs += 1;
5002 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5003 shader_info->num_input_vgprs += 1;
5004 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5005 shader_info->num_input_vgprs += 1;
5006 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5007 shader_info->num_input_vgprs += 1;
5008 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5009 shader_info->num_input_vgprs += 1;
5010 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5011 shader_info->num_input_vgprs += 1;
5012 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5013 shader_info->num_input_vgprs += 1;
5014 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5015 shader_info->num_input_vgprs += 1;
5016 }
5017 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5018
5019 /* +3 for scratch wave offset and VCC */
5020 config->num_sgprs = MAX2(config->num_sgprs,
5021 shader_info->num_input_sgprs + 3);
5022 }
5023
5024 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5025 struct ac_shader_binary *binary,
5026 struct ac_shader_config *config,
5027 struct ac_shader_variant_info *shader_info,
5028 struct nir_shader *nir,
5029 const struct ac_nir_compiler_options *options,
5030 bool dump_shader)
5031 {
5032
5033 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5034 options);
5035
5036 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5037 switch (nir->stage) {
5038 case MESA_SHADER_COMPUTE:
5039 for (int i = 0; i < 3; ++i)
5040 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5041 break;
5042 case MESA_SHADER_FRAGMENT:
5043 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5044 break;
5045 case MESA_SHADER_GEOMETRY:
5046 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5047 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5048 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5049 shader_info->gs.invocations = nir->info->gs.invocations;
5050 break;
5051 case MESA_SHADER_VERTEX:
5052 shader_info->vs.as_es = options->key.vs.as_es;
5053 break;
5054 default:
5055 break;
5056 }
5057 }
5058
5059 static void
5060 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5061 {
5062 LLVMValueRef args[9];
5063 args[0] = ctx->gsvs_ring;
5064 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5065 args[3] = ctx->i32zero;
5066 args[4] = ctx->i32one; /* OFFEN */
5067 args[5] = ctx->i32zero; /* IDXEN */
5068 args[6] = ctx->i32one; /* GLC */
5069 args[7] = ctx->i32one; /* SLC */
5070 args[8] = ctx->i32zero; /* TFE */
5071
5072 int idx = 0;
5073 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5074 if (!(ctx->output_mask & (1ull << i)))
5075 continue;
5076
5077 for (unsigned j = 0; j < 4; j++) {
5078 LLVMValueRef value;
5079 args[2] = LLVMConstInt(ctx->i32,
5080 (idx * 4 + j) *
5081 ctx->gs_max_out_vertices * 16 * 4, false);
5082
5083 value = ac_emit_llvm_intrinsic(&ctx->ac,
5084 "llvm.SI.buffer.load.dword.i32.i32",
5085 ctx->i32, args, 9,
5086 AC_FUNC_ATTR_READONLY);
5087
5088 LLVMBuildStore(ctx->builder,
5089 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5090 }
5091 idx++;
5092 }
5093 handle_vs_outputs_post(ctx);
5094 }
5095
5096 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5097 struct nir_shader *geom_shader,
5098 struct ac_shader_binary *binary,
5099 struct ac_shader_config *config,
5100 struct ac_shader_variant_info *shader_info,
5101 const struct ac_nir_compiler_options *options,
5102 bool dump_shader)
5103 {
5104 struct nir_to_llvm_context ctx = {0};
5105 ctx.context = LLVMContextCreate();
5106 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5107 ctx.options = options;
5108 ctx.shader_info = shader_info;
5109
5110 ac_llvm_context_init(&ctx.ac, ctx.context);
5111 ctx.ac.module = ctx.module;
5112
5113 ctx.is_gs_copy_shader = true;
5114 LLVMSetTarget(ctx.module, "amdgcn--");
5115 setup_types(&ctx);
5116
5117 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5118 ctx.ac.builder = ctx.builder;
5119 ctx.stage = MESA_SHADER_VERTEX;
5120
5121 create_function(&ctx);
5122
5123 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5124 ac_setup_rings(&ctx);
5125
5126 nir_foreach_variable(variable, &geom_shader->outputs)
5127 handle_shader_output_decl(&ctx, variable);
5128
5129 ac_gs_copy_shader_emit(&ctx);
5130
5131 LLVMBuildRetVoid(ctx.builder);
5132
5133 ac_llvm_finalize_module(&ctx);
5134
5135 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5136 MESA_SHADER_VERTEX,
5137 dump_shader, options->supports_spill);
5138 }