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ac/nir: Sanitize location_frac for local variables.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 gl_shader_stage stage;
135
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137
138 uint64_t input_mask;
139 uint64_t output_mask;
140 uint8_t num_output_clips;
141 uint8_t num_output_culls;
142
143 bool is_gs_copy_shader;
144 LLVMValueRef gs_next_vertex;
145 unsigned gs_max_out_vertices;
146
147 unsigned tes_primitive_mode;
148 uint64_t tess_outputs_written;
149 uint64_t tess_patch_outputs_written;
150
151 uint32_t tcs_patch_outputs_read;
152 uint64_t tcs_outputs_read;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMTypeRef
163 nir2llvmtype(struct ac_nir_context *ctx,
164 const struct glsl_type *type)
165 {
166 switch (glsl_get_base_type(glsl_without_array(type))) {
167 case GLSL_TYPE_UINT:
168 case GLSL_TYPE_INT:
169 return ctx->ac.i32;
170 case GLSL_TYPE_UINT64:
171 case GLSL_TYPE_INT64:
172 return ctx->ac.i64;
173 case GLSL_TYPE_DOUBLE:
174 return ctx->ac.f64;
175 case GLSL_TYPE_FLOAT:
176 return ctx->ac.f32;
177 default:
178 assert(!"Unsupported type in nir2llvmtype()");
179 break;
180 }
181 return 0;
182 }
183
184 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
185 const nir_deref_var *deref,
186 enum ac_descriptor_type desc_type,
187 const nir_tex_instr *instr,
188 bool image, bool write);
189
190 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
191 {
192 return (index * 4) + chan;
193 }
194
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
196 {
197 /* handle patch indices separate */
198 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
199 return 0;
200 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
201 return 1;
202 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
203 return 2 + (slot - VARYING_SLOT_PATCH0);
204
205 if (slot == VARYING_SLOT_POS)
206 return 0;
207 if (slot == VARYING_SLOT_PSIZ)
208 return 1;
209 if (slot == VARYING_SLOT_CLIP_DIST0)
210 return 2;
211 /* 3 is reserved for clip dist as well */
212 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
213 return 4 + (slot - VARYING_SLOT_VAR0);
214 unreachable("illegal slot in get unique index\n");
215 }
216
217 static void set_llvm_calling_convention(LLVMValueRef func,
218 gl_shader_stage stage)
219 {
220 enum radeon_llvm_calling_convention calling_conv;
221
222 switch (stage) {
223 case MESA_SHADER_VERTEX:
224 case MESA_SHADER_TESS_EVAL:
225 calling_conv = RADEON_LLVM_AMDGPU_VS;
226 break;
227 case MESA_SHADER_GEOMETRY:
228 calling_conv = RADEON_LLVM_AMDGPU_GS;
229 break;
230 case MESA_SHADER_TESS_CTRL:
231 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t sgpr_count;
253 uint8_t num_sgprs_used;
254 uint8_t num_vgprs_used;
255 };
256
257 enum ac_arg_regfile {
258 ARG_SGPR,
259 ARG_VGPR,
260 };
261
262 static void
263 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
264 LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271
272 if (regfile == ARG_SGPR) {
273 info->num_sgprs_used += ac_get_type_size(type) / 4;
274 info->sgpr_count++;
275 } else {
276 assert(regfile == ARG_VGPR);
277 info->num_vgprs_used += ac_get_type_size(type) / 4;
278 }
279 }
280
281 static inline void
282 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 info->array_params_mask |= (1 << info->count);
285 add_arg(info, ARG_SGPR, type, param_ptr);
286 }
287
288 static void assign_arguments(LLVMValueRef main_function,
289 struct arg_info *info)
290 {
291 unsigned i;
292 for (i = 0; i < info->count; i++) {
293 if (info->assign[i])
294 *info->assign[i] = LLVMGetParam(main_function, i);
295 }
296 }
297
298 static LLVMValueRef
299 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
300 LLVMBuilderRef builder, LLVMTypeRef *return_types,
301 unsigned num_return_elems,
302 struct arg_info *args,
303 unsigned max_workgroup_size,
304 bool unsafe_math)
305 {
306 LLVMTypeRef main_function_type, ret_type;
307 LLVMBasicBlockRef main_function_body;
308
309 if (num_return_elems)
310 ret_type = LLVMStructTypeInContext(ctx, return_types,
311 num_return_elems, true);
312 else
313 ret_type = LLVMVoidTypeInContext(ctx);
314
315 /* Setup the function */
316 main_function_type =
317 LLVMFunctionType(ret_type, args->types, args->count, 0);
318 LLVMValueRef main_function =
319 LLVMAddFunction(module, "main", main_function_type);
320 main_function_body =
321 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
322 LLVMPositionBuilderAtEnd(builder, main_function_body);
323
324 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
325 for (unsigned i = 0; i < args->sgpr_count; ++i) {
326 if (args->array_params_mask & (1 << i)) {
327 LLVMValueRef P = LLVMGetParam(main_function, i);
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
329 ac_add_attr_dereferenceable(P, UINT64_MAX);
330 }
331 else {
332 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
333 }
334 }
335
336 if (max_workgroup_size) {
337 ac_llvm_add_target_dep_function_attr(main_function,
338 "amdgpu-max-work-group-size",
339 max_workgroup_size);
340 }
341 if (unsafe_math) {
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function,
344 "less-precise-fpmad",
345 "true");
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "no-infs-fp-math",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-nans-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "unsafe-fp-math",
354 "true");
355 }
356 return main_function;
357 }
358
359 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
360 {
361 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
362 CONST_ADDR_SPACE);
363 }
364
365 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
401 {
402 switch (ctx->stage) {
403 case MESA_SHADER_TESS_CTRL:
404 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
405 case MESA_SHADER_TESS_EVAL:
406 return ctx->tes_rel_patch_id;
407 break;
408 default:
409 unreachable("Illegal stage");
410 }
411 }
412
413 /* Tessellation shaders pass outputs to the next shader using LDS.
414 *
415 * LS outputs = TCS inputs
416 * TCS outputs = TES inputs
417 *
418 * The LDS layout is:
419 * - TCS inputs for patch 0
420 * - TCS inputs for patch 1
421 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
422 * - ...
423 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
424 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
425 * - TCS outputs for patch 1
426 * - Per-patch TCS outputs for patch 1
427 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
428 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
429 * - ...
430 *
431 * All three shaders VS(LS), TCS, TES share the same LDS space.
432 */
433 static LLVMValueRef
434 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
435 {
436 if (ctx->stage == MESA_SHADER_VERTEX)
437 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
438 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
439 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
440 else {
441 assert(0);
442 return NULL;
443 }
444 }
445
446 static LLVMValueRef
447 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
448 {
449 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
450 }
451
452 static LLVMValueRef
453 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
454 {
455 return LLVMBuildMul(ctx->builder,
456 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
457 LLVMConstInt(ctx->ac.i32, 4, false), "");
458 }
459
460 static LLVMValueRef
461 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
462 {
463 return LLVMBuildMul(ctx->builder,
464 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
465 LLVMConstInt(ctx->ac.i32, 4, false), "");
466 }
467
468 static LLVMValueRef
469 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
470 {
471 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
472 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
473
474 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
475 }
476
477 static LLVMValueRef
478 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
479 {
480 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
481 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
482 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
483
484 return LLVMBuildAdd(ctx->builder, patch0_offset,
485 LLVMBuildMul(ctx->builder, patch_stride,
486 rel_patch_id, ""),
487 "");
488 }
489
490 static LLVMValueRef
491 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch0_patch_data_offset =
494 get_tcs_out_patch0_patch_data_offset(ctx);
495 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
496 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
497
498 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
499 LLVMBuildMul(ctx->builder, patch_stride,
500 rel_patch_id, ""),
501 "");
502 }
503
504 static void
505 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
506 uint32_t indirect_offset)
507 {
508 ud_info->sgpr_idx = *sgpr_idx;
509 ud_info->num_sgprs = num_sgprs;
510 ud_info->indirect = indirect_offset > 0;
511 ud_info->indirect_offset = indirect_offset;
512 *sgpr_idx += num_sgprs;
513 }
514
515 static void
516 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
517 uint8_t num_sgprs)
518 {
519 struct ac_userdata_info *ud_info =
520 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
521 assert(ud_info);
522
523 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
524 }
525
526 static void
527 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
528 uint32_t indirect_offset)
529 {
530 struct ac_userdata_info *ud_info =
531 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
532 assert(ud_info);
533
534 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
535 }
536
537 struct user_sgpr_info {
538 bool need_ring_offsets;
539 uint8_t sgpr_count;
540 bool indirect_all_descriptor_sets;
541 };
542
543 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
544 gl_shader_stage stage,
545 struct user_sgpr_info *user_sgpr_info)
546 {
547 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
548
549 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
550 if (stage == MESA_SHADER_GEOMETRY ||
551 stage == MESA_SHADER_VERTEX ||
552 stage == MESA_SHADER_TESS_CTRL ||
553 stage == MESA_SHADER_TESS_EVAL ||
554 ctx->is_gs_copy_shader)
555 user_sgpr_info->need_ring_offsets = true;
556
557 if (stage == MESA_SHADER_FRAGMENT &&
558 ctx->shader_info->info.ps.needs_sample_positions)
559 user_sgpr_info->need_ring_offsets = true;
560
561 /* 2 user sgprs will nearly always be allocated for scratch/rings */
562 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
563 user_sgpr_info->sgpr_count += 2;
564 }
565
566 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
567 switch (stage) {
568 case MESA_SHADER_COMPUTE:
569 if (ctx->shader_info->info.cs.uses_grid_size)
570 user_sgpr_info->sgpr_count += 3;
571 break;
572 case MESA_SHADER_FRAGMENT:
573 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
574 break;
575 case MESA_SHADER_VERTEX:
576 if (!ctx->is_gs_copy_shader) {
577 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
578 if (ctx->shader_info->info.vs.needs_draw_id) {
579 user_sgpr_info->sgpr_count += 3;
580 } else {
581 user_sgpr_info->sgpr_count += 2;
582 }
583 }
584 if (ctx->options->key.vs.as_ls)
585 user_sgpr_info->sgpr_count++;
586 break;
587 case MESA_SHADER_TESS_CTRL:
588 user_sgpr_info->sgpr_count += 4;
589 break;
590 case MESA_SHADER_TESS_EVAL:
591 user_sgpr_info->sgpr_count += 1;
592 break;
593 case MESA_SHADER_GEOMETRY:
594 user_sgpr_info->sgpr_count += 2;
595 break;
596 default:
597 break;
598 }
599
600 if (ctx->shader_info->info.loads_push_constants)
601 user_sgpr_info->sgpr_count += 2;
602
603 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
604 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
605
606 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
607 user_sgpr_info->sgpr_count += 2;
608 user_sgpr_info->indirect_all_descriptor_sets = true;
609 } else {
610 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
611 }
612 }
613
614 static void
615 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
616 gl_shader_stage stage,
617 bool has_previous_stage,
618 gl_shader_stage previous_stage,
619 const struct user_sgpr_info *user_sgpr_info,
620 struct arg_info *args,
621 LLVMValueRef *desc_sets)
622 {
623 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
624 unsigned num_sets = ctx->options->layout ?
625 ctx->options->layout->num_sets : 0;
626 unsigned stage_mask = 1 << stage;
627
628 if (has_previous_stage)
629 stage_mask |= 1 << previous_stage;
630
631 /* 1 for each descriptor set */
632 if (!user_sgpr_info->indirect_all_descriptor_sets) {
633 for (unsigned i = 0; i < num_sets; ++i) {
634 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
635 add_array_arg(args, type,
636 &ctx->descriptor_sets[i]);
637 }
638 }
639 } else {
640 add_array_arg(args, const_array(type, 32), desc_sets);
641 }
642
643 if (ctx->shader_info->info.loads_push_constants) {
644 /* 1 for push constants and dynamic descriptors */
645 add_array_arg(args, type, &ctx->push_constants);
646 }
647 }
648
649 static void
650 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
651 gl_shader_stage stage,
652 bool has_previous_stage,
653 gl_shader_stage previous_stage,
654 struct arg_info *args)
655 {
656 if (!ctx->is_gs_copy_shader &&
657 (stage == MESA_SHADER_VERTEX ||
658 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
659 if (ctx->shader_info->info.vs.has_vertex_buffers) {
660 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
661 &ctx->vertex_buffers);
662 }
663 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
664 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
665 if (ctx->shader_info->info.vs.needs_draw_id) {
666 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
667 }
668 }
669 }
670
671 static void
672 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
673 {
674 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
675 if (!ctx->is_gs_copy_shader) {
676 if (ctx->options->key.vs.as_ls) {
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
678 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
679 } else {
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
681 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
682 }
683 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
684 }
685 }
686
687 static void
688 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
689 {
690 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
691 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
692 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
693 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
694 }
695
696 static void
697 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
698 bool has_previous_stage, gl_shader_stage previous_stage,
699 const struct user_sgpr_info *user_sgpr_info,
700 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
701 {
702 unsigned num_sets = ctx->options->layout ?
703 ctx->options->layout->num_sets : 0;
704 unsigned stage_mask = 1 << stage;
705
706 if (has_previous_stage)
707 stage_mask |= 1 << previous_stage;
708
709 if (!user_sgpr_info->indirect_all_descriptor_sets) {
710 for (unsigned i = 0; i < num_sets; ++i) {
711 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
712 set_loc_desc(ctx, i, user_sgpr_idx, 0);
713 } else
714 ctx->descriptor_sets[i] = NULL;
715 }
716 } else {
717 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
718 user_sgpr_idx, 2);
719
720 for (unsigned i = 0; i < num_sets; ++i) {
721 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
722 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
723 ctx->descriptor_sets[i] =
724 ac_build_load_to_sgpr(&ctx->ac,
725 desc_sets,
726 LLVMConstInt(ctx->ac.i32, i, false));
727
728 } else
729 ctx->descriptor_sets[i] = NULL;
730 }
731 ctx->shader_info->need_indirect_descriptor_sets = true;
732 }
733
734 if (ctx->shader_info->info.loads_push_constants) {
735 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
736 }
737 }
738
739 static void
740 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
741 gl_shader_stage stage, bool has_previous_stage,
742 gl_shader_stage previous_stage,
743 uint8_t *user_sgpr_idx)
744 {
745 if (!ctx->is_gs_copy_shader &&
746 (stage == MESA_SHADER_VERTEX ||
747 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
748 if (ctx->shader_info->info.vs.has_vertex_buffers) {
749 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
750 user_sgpr_idx, 2);
751 }
752
753 unsigned vs_num = 2;
754 if (ctx->shader_info->info.vs.needs_draw_id)
755 vs_num++;
756
757 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
758 user_sgpr_idx, vs_num);
759 }
760 }
761
762 static void create_function(struct nir_to_llvm_context *ctx,
763 gl_shader_stage stage,
764 bool has_previous_stage,
765 gl_shader_stage previous_stage)
766 {
767 uint8_t user_sgpr_idx;
768 struct user_sgpr_info user_sgpr_info;
769 struct arg_info args = {};
770 LLVMValueRef desc_sets;
771
772 allocate_user_sgprs(ctx, stage, &user_sgpr_info);
773
774 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
775 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
776 &ctx->ring_offsets);
777 }
778
779 switch (stage) {
780 case MESA_SHADER_COMPUTE:
781 declare_global_input_sgprs(ctx, stage, has_previous_stage,
782 previous_stage, &user_sgpr_info,
783 &args, &desc_sets);
784
785 if (ctx->shader_info->info.cs.uses_grid_size) {
786 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
787 &ctx->num_work_groups);
788 }
789
790 for (int i = 0; i < 3; i++) {
791 ctx->workgroup_ids[i] = NULL;
792 if (ctx->shader_info->info.cs.uses_block_id[i]) {
793 add_arg(&args, ARG_SGPR, ctx->ac.i32,
794 &ctx->workgroup_ids[i]);
795 }
796 }
797
798 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
799 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
800 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
801 &ctx->local_invocation_ids);
802 break;
803 case MESA_SHADER_VERTEX:
804 declare_global_input_sgprs(ctx, stage, has_previous_stage,
805 previous_stage, &user_sgpr_info,
806 &args, &desc_sets);
807 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
808 previous_stage, &args);
809
810 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
811 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
812 if (ctx->options->key.vs.as_es)
813 add_arg(&args, ARG_SGPR, ctx->ac.i32,
814 &ctx->es2gs_offset);
815 else if (ctx->options->key.vs.as_ls)
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->ls_out_layout);
818
819 declare_vs_input_vgprs(ctx, &args);
820 break;
821 case MESA_SHADER_TESS_CTRL:
822 if (has_previous_stage) {
823 // First 6 system regs
824 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
825 add_arg(&args, ARG_SGPR, ctx->ac.i32,
826 &ctx->merged_wave_info);
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->tess_factor_offset);
829
830 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
831 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
832 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
833
834 declare_global_input_sgprs(ctx, stage,
835 has_previous_stage,
836 previous_stage,
837 &user_sgpr_info, &args,
838 &desc_sets);
839 declare_vs_specific_input_sgprs(ctx, stage,
840 has_previous_stage,
841 previous_stage, &args);
842
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->ls_out_layout);
845
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_offchip_layout);
848 add_arg(&args, ARG_SGPR, ctx->ac.i32,
849 &ctx->tcs_out_offsets);
850 add_arg(&args, ARG_SGPR, ctx->ac.i32,
851 &ctx->tcs_out_layout);
852 add_arg(&args, ARG_SGPR, ctx->ac.i32,
853 &ctx->tcs_in_layout);
854 if (ctx->shader_info->info.needs_multiview_view_index)
855 add_arg(&args, ARG_SGPR, ctx->ac.i32,
856 &ctx->view_index);
857
858 add_arg(&args, ARG_VGPR, ctx->ac.i32,
859 &ctx->abi.tcs_patch_id);
860 add_arg(&args, ARG_VGPR, ctx->ac.i32,
861 &ctx->abi.tcs_rel_ids);
862
863 declare_vs_input_vgprs(ctx, &args);
864 } else {
865 declare_global_input_sgprs(ctx, stage,
866 has_previous_stage,
867 previous_stage,
868 &user_sgpr_info, &args,
869 &desc_sets);
870
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_offchip_layout);
873 add_arg(&args, ARG_SGPR, ctx->ac.i32,
874 &ctx->tcs_out_offsets);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tcs_out_layout);
877 add_arg(&args, ARG_SGPR, ctx->ac.i32,
878 &ctx->tcs_in_layout);
879 if (ctx->shader_info->info.needs_multiview_view_index)
880 add_arg(&args, ARG_SGPR, ctx->ac.i32,
881 &ctx->view_index);
882
883 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
884 add_arg(&args, ARG_SGPR, ctx->ac.i32,
885 &ctx->tess_factor_offset);
886 add_arg(&args, ARG_VGPR, ctx->ac.i32,
887 &ctx->abi.tcs_patch_id);
888 add_arg(&args, ARG_VGPR, ctx->ac.i32,
889 &ctx->abi.tcs_rel_ids);
890 }
891 break;
892 case MESA_SHADER_TESS_EVAL:
893 declare_global_input_sgprs(ctx, stage, has_previous_stage,
894 previous_stage, &user_sgpr_info,
895 &args, &desc_sets);
896
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
898 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
900
901 if (ctx->options->key.tes.as_es) {
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
903 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
904 add_arg(&args, ARG_SGPR, ctx->ac.i32,
905 &ctx->es2gs_offset);
906 } else {
907 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
908 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
909 }
910 declare_tes_input_vgprs(ctx, &args);
911 break;
912 case MESA_SHADER_GEOMETRY:
913 if (has_previous_stage) {
914 // First 6 system regs
915 add_arg(&args, ARG_SGPR, ctx->ac.i32,
916 &ctx->gs2vs_offset);
917 add_arg(&args, ARG_SGPR, ctx->ac.i32,
918 &ctx->merged_wave_info);
919 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
920
921 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
922 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
923 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
924
925 declare_global_input_sgprs(ctx, stage,
926 has_previous_stage,
927 previous_stage,
928 &user_sgpr_info, &args,
929 &desc_sets);
930
931 if (previous_stage == MESA_SHADER_TESS_EVAL) {
932 add_arg(&args, ARG_SGPR, ctx->ac.i32,
933 &ctx->tcs_offchip_layout);
934 } else {
935 declare_vs_specific_input_sgprs(ctx, stage,
936 has_previous_stage,
937 previous_stage,
938 &args);
939 }
940
941 add_arg(&args, ARG_SGPR, ctx->ac.i32,
942 &ctx->gsvs_ring_stride);
943 add_arg(&args, ARG_SGPR, ctx->ac.i32,
944 &ctx->gsvs_num_entries);
945 if (ctx->shader_info->info.needs_multiview_view_index)
946 add_arg(&args, ARG_SGPR, ctx->ac.i32,
947 &ctx->view_index);
948
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[0]);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->gs_vtx_offset[2]);
953 add_arg(&args, ARG_VGPR, ctx->ac.i32,
954 &ctx->abi.gs_prim_id);
955 add_arg(&args, ARG_VGPR, ctx->ac.i32,
956 &ctx->abi.gs_invocation_id);
957 add_arg(&args, ARG_VGPR, ctx->ac.i32,
958 &ctx->gs_vtx_offset[4]);
959
960 if (previous_stage == MESA_SHADER_VERTEX) {
961 declare_vs_input_vgprs(ctx, &args);
962 } else {
963 declare_tes_input_vgprs(ctx, &args);
964 }
965 } else {
966 declare_global_input_sgprs(ctx, stage,
967 has_previous_stage,
968 previous_stage,
969 &user_sgpr_info, &args,
970 &desc_sets);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32,
973 &ctx->gsvs_ring_stride);
974 add_arg(&args, ARG_SGPR, ctx->ac.i32,
975 &ctx->gsvs_num_entries);
976 if (ctx->shader_info->info.needs_multiview_view_index)
977 add_arg(&args, ARG_SGPR, ctx->ac.i32,
978 &ctx->view_index);
979
980 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
981 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[0]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[1]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->abi.gs_prim_id);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[2]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->gs_vtx_offset[3]);
992 add_arg(&args, ARG_VGPR, ctx->ac.i32,
993 &ctx->gs_vtx_offset[4]);
994 add_arg(&args, ARG_VGPR, ctx->ac.i32,
995 &ctx->gs_vtx_offset[5]);
996 add_arg(&args, ARG_VGPR, ctx->ac.i32,
997 &ctx->abi.gs_invocation_id);
998 }
999 break;
1000 case MESA_SHADER_FRAGMENT:
1001 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1002 previous_stage, &user_sgpr_info,
1003 &args, &desc_sets);
1004
1005 if (ctx->shader_info->info.ps.needs_sample_positions)
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1007 &ctx->sample_pos_offset);
1008
1009 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1011 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1012 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1013 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1014 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1015 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1016 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1017 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1018 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1019 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1020 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1021 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1022 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1023 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1024 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1025 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1026 break;
1027 default:
1028 unreachable("Shader stage not implemented");
1029 }
1030
1031 ctx->main_function = create_llvm_function(
1032 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1033 ctx->max_workgroup_size,
1034 ctx->options->unsafe_math);
1035 set_llvm_calling_convention(ctx->main_function, stage);
1036
1037
1038 ctx->shader_info->num_input_vgprs = 0;
1039 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1040
1041 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1042
1043 if (ctx->stage != MESA_SHADER_FRAGMENT)
1044 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1045
1046 assign_arguments(ctx->main_function, &args);
1047
1048 user_sgpr_idx = 0;
1049
1050 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1051 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1052 &user_sgpr_idx, 2);
1053 if (ctx->options->supports_spill) {
1054 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1055 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1056 NULL, 0, AC_FUNC_ATTR_READNONE);
1057 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1058 const_array(ctx->ac.v4i32, 16), "");
1059 }
1060 }
1061
1062 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1063 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1064 if (has_previous_stage)
1065 user_sgpr_idx = 0;
1066
1067 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1068 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1069
1070 switch (stage) {
1071 case MESA_SHADER_COMPUTE:
1072 if (ctx->shader_info->info.cs.uses_grid_size) {
1073 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1074 &user_sgpr_idx, 3);
1075 }
1076 break;
1077 case MESA_SHADER_VERTEX:
1078 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1079 previous_stage, &user_sgpr_idx);
1080 if (ctx->view_index)
1081 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1082 if (ctx->options->key.vs.as_ls) {
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 }
1086 if (ctx->options->key.vs.as_ls)
1087 ac_declare_lds_as_pointer(&ctx->ac);
1088 break;
1089 case MESA_SHADER_TESS_CTRL:
1090 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1091 previous_stage, &user_sgpr_idx);
1092 if (has_previous_stage)
1093 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1094 &user_sgpr_idx, 1);
1095 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1096 if (ctx->view_index)
1097 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1098 ac_declare_lds_as_pointer(&ctx->ac);
1099 break;
1100 case MESA_SHADER_TESS_EVAL:
1101 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1102 if (ctx->view_index)
1103 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1104 break;
1105 case MESA_SHADER_GEOMETRY:
1106 if (has_previous_stage) {
1107 if (previous_stage == MESA_SHADER_VERTEX)
1108 set_vs_specific_input_locs(ctx, stage,
1109 has_previous_stage,
1110 previous_stage,
1111 &user_sgpr_idx);
1112 else
1113 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1114 &user_sgpr_idx, 1);
1115 }
1116 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1117 &user_sgpr_idx, 2);
1118 if (ctx->view_index)
1119 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1120 if (has_previous_stage)
1121 ac_declare_lds_as_pointer(&ctx->ac);
1122 break;
1123 case MESA_SHADER_FRAGMENT:
1124 if (ctx->shader_info->info.ps.needs_sample_positions) {
1125 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1126 &user_sgpr_idx, 1);
1127 }
1128 break;
1129 default:
1130 unreachable("Shader stage not implemented");
1131 }
1132
1133 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1134 }
1135
1136 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1137 LLVMValueRef value, unsigned count)
1138 {
1139 unsigned num_components = ac_get_llvm_num_components(value);
1140 if (count == num_components)
1141 return value;
1142
1143 LLVMValueRef masks[] = {
1144 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1145 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1146
1147 if (count == 1)
1148 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1149 "");
1150
1151 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1152 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1153 }
1154
1155 static void
1156 build_store_values_extended(struct ac_llvm_context *ac,
1157 LLVMValueRef *values,
1158 unsigned value_count,
1159 unsigned value_stride,
1160 LLVMValueRef vec)
1161 {
1162 LLVMBuilderRef builder = ac->builder;
1163 unsigned i;
1164
1165 for (i = 0; i < value_count; i++) {
1166 LLVMValueRef ptr = values[i * value_stride];
1167 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1168 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1169 LLVMBuildStore(builder, value, ptr);
1170 }
1171 }
1172
1173 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1174 const nir_ssa_def *def)
1175 {
1176 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1177 if (def->num_components > 1) {
1178 type = LLVMVectorType(type, def->num_components);
1179 }
1180 return type;
1181 }
1182
1183 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1184 {
1185 assert(src.is_ssa);
1186 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1187 return (LLVMValueRef)entry->data;
1188 }
1189
1190
1191 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1192 const struct nir_block *b)
1193 {
1194 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1195 return (LLVMBasicBlockRef)entry->data;
1196 }
1197
1198 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1199 nir_alu_src src,
1200 unsigned num_components)
1201 {
1202 LLVMValueRef value = get_src(ctx, src.src);
1203 bool need_swizzle = false;
1204
1205 assert(value);
1206 LLVMTypeRef type = LLVMTypeOf(value);
1207 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1208 ? LLVMGetVectorSize(type)
1209 : 1;
1210
1211 for (unsigned i = 0; i < num_components; ++i) {
1212 assert(src.swizzle[i] < src_components);
1213 if (src.swizzle[i] != i)
1214 need_swizzle = true;
1215 }
1216
1217 if (need_swizzle || num_components != src_components) {
1218 LLVMValueRef masks[] = {
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1220 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1221 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1222 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1223
1224 if (src_components > 1 && num_components == 1) {
1225 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1226 masks[0], "");
1227 } else if (src_components == 1 && num_components > 1) {
1228 LLVMValueRef values[] = {value, value, value, value};
1229 value = ac_build_gather_values(&ctx->ac, values, num_components);
1230 } else {
1231 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1232 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1233 swizzle, "");
1234 }
1235 }
1236 assert(!src.negate);
1237 assert(!src.abs);
1238 return value;
1239 }
1240
1241 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1242 LLVMIntPredicate pred, LLVMValueRef src0,
1243 LLVMValueRef src1)
1244 {
1245 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1246 return LLVMBuildSelect(ctx->builder, result,
1247 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1248 ctx->i32_0, "");
1249 }
1250
1251 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1252 LLVMRealPredicate pred, LLVMValueRef src0,
1253 LLVMValueRef src1)
1254 {
1255 LLVMValueRef result;
1256 src0 = ac_to_float(ctx, src0);
1257 src1 = ac_to_float(ctx, src1);
1258 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1259 return LLVMBuildSelect(ctx->builder, result,
1260 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1261 ctx->i32_0, "");
1262 }
1263
1264 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1265 const char *intrin,
1266 LLVMTypeRef result_type,
1267 LLVMValueRef src0)
1268 {
1269 char name[64];
1270 LLVMValueRef params[] = {
1271 ac_to_float(ctx, src0),
1272 };
1273
1274 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1275 get_elem_bits(ctx, result_type));
1276 assert(length < sizeof(name));
1277 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1278 }
1279
1280 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0, LLVMValueRef src1)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 ac_to_float(ctx, src1),
1289 };
1290
1291 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1292 get_elem_bits(ctx, result_type));
1293 assert(length < sizeof(name));
1294 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1295 }
1296
1297 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1298 const char *intrin,
1299 LLVMTypeRef result_type,
1300 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1301 {
1302 char name[64];
1303 LLVMValueRef params[] = {
1304 ac_to_float(ctx, src0),
1305 ac_to_float(ctx, src1),
1306 ac_to_float(ctx, src2),
1307 };
1308
1309 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1310 get_elem_bits(ctx, result_type));
1311 assert(length < sizeof(name));
1312 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1313 }
1314
1315 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1319 ctx->i32_0, "");
1320 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1321 }
1322
1323 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1324 LLVMIntPredicate pred,
1325 LLVMValueRef src0, LLVMValueRef src1)
1326 {
1327 return LLVMBuildSelect(ctx->builder,
1328 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1329 src0,
1330 src1, "");
1331
1332 }
1333 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1334 LLVMValueRef src0)
1335 {
1336 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1337 LLVMBuildNeg(ctx->builder, src0, ""));
1338 }
1339
1340 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1341 LLVMValueRef src0)
1342 {
1343 LLVMValueRef cmp, val;
1344
1345 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1346 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1347 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1348 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1349 return val;
1350 }
1351
1352 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1353 LLVMValueRef src0)
1354 {
1355 LLVMValueRef cmp, val;
1356
1357 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1358 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1359 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1360 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1361 return val;
1362 }
1363
1364 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1365 LLVMValueRef src0)
1366 {
1367 const char *intr = "llvm.floor.f32";
1368 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1369 LLVMValueRef params[] = {
1370 fsrc0,
1371 };
1372 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1373 ctx->f32, params, 1,
1374 AC_FUNC_ATTR_READNONE);
1375 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1376 }
1377
1378 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1379 const char *intrin,
1380 LLVMValueRef src0, LLVMValueRef src1)
1381 {
1382 LLVMTypeRef ret_type;
1383 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1384 LLVMValueRef res;
1385 LLVMValueRef params[] = { src0, src1 };
1386 ret_type = LLVMStructTypeInContext(ctx->context, types,
1387 2, true);
1388
1389 res = ac_build_intrinsic(ctx, intrin, ret_type,
1390 params, 2, AC_FUNC_ATTR_READNONE);
1391
1392 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1393 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1394 return res;
1395 }
1396
1397 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1398 LLVMValueRef src0)
1399 {
1400 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1401 }
1402
1403 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1404 LLVMValueRef src0)
1405 {
1406 src0 = ac_to_float(ctx, src0);
1407 return LLVMBuildSExt(ctx->builder,
1408 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1409 ctx->i32, "");
1410 }
1411
1412 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1413 LLVMValueRef src0)
1414 {
1415 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1416 }
1417
1418 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1419 LLVMValueRef src0)
1420 {
1421 return LLVMBuildSExt(ctx->builder,
1422 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1423 ctx->i32, "");
1424 }
1425
1426 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1427 LLVMValueRef src0)
1428 {
1429 LLVMValueRef result;
1430 LLVMValueRef cond = NULL;
1431
1432 src0 = ac_to_float(&ctx->ac, src0);
1433 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1434
1435 if (ctx->options->chip_class >= VI) {
1436 LLVMValueRef args[2];
1437 /* Check if the result is a denormal - and flush to 0 if so. */
1438 args[0] = result;
1439 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1440 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1441 }
1442
1443 /* need to convert back up to f32 */
1444 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1445
1446 if (ctx->options->chip_class >= VI)
1447 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1448 else {
1449 /* for SI/CIK */
1450 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1451 * so compare the result and flush to 0 if it's smaller.
1452 */
1453 LLVMValueRef temp, cond2;
1454 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1455 ctx->ac.f32, result);
1456 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1457 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1458 temp, "");
1459 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1460 temp, ctx->ac.f32_0, "");
1461 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1462 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1463 }
1464 return result;
1465 }
1466
1467 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1468 LLVMValueRef src0, LLVMValueRef src1)
1469 {
1470 LLVMValueRef dst64, result;
1471 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1472 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1473
1474 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1475 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1476 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1477 return result;
1478 }
1479
1480 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1481 LLVMValueRef src0, LLVMValueRef src1)
1482 {
1483 LLVMValueRef dst64, result;
1484 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1485 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1486
1487 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1488 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1489 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1490 return result;
1491 }
1492
1493 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1494 bool is_signed,
1495 const LLVMValueRef srcs[3])
1496 {
1497 LLVMValueRef result;
1498 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1499
1500 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1501 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1502 return result;
1503 }
1504
1505 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1506 LLVMValueRef src0, LLVMValueRef src1,
1507 LLVMValueRef src2, LLVMValueRef src3)
1508 {
1509 LLVMValueRef bfi_args[3], result;
1510
1511 bfi_args[0] = LLVMBuildShl(ctx->builder,
1512 LLVMBuildSub(ctx->builder,
1513 LLVMBuildShl(ctx->builder,
1514 ctx->i32_1,
1515 src3, ""),
1516 ctx->i32_1, ""),
1517 src2, "");
1518 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1519 bfi_args[2] = src0;
1520
1521 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1522
1523 /* Calculate:
1524 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1525 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1526 */
1527 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1528 LLVMBuildAnd(ctx->builder, bfi_args[0],
1529 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1530
1531 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1532 return result;
1533 }
1534
1535 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1536 LLVMValueRef src0)
1537 {
1538 LLVMValueRef comp[2];
1539
1540 src0 = ac_to_float(ctx, src0);
1541 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1542 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1543
1544 return ac_build_cvt_pkrtz_f16(ctx, comp);
1545 }
1546
1547 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1548 LLVMValueRef src0)
1549 {
1550 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1551 LLVMValueRef temps[2], result, val;
1552 int i;
1553
1554 for (i = 0; i < 2; i++) {
1555 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1556 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1557 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1558 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1559 }
1560
1561 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1562 ctx->i32_0, "");
1563 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1564 ctx->i32_1, "");
1565 return result;
1566 }
1567
1568 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1569 nir_op op,
1570 LLVMValueRef src0)
1571 {
1572 unsigned mask;
1573 int idx;
1574 LLVMValueRef result;
1575
1576 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1577 mask = AC_TID_MASK_LEFT;
1578 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1579 mask = AC_TID_MASK_TOP;
1580 else
1581 mask = AC_TID_MASK_TOP_LEFT;
1582
1583 /* for DDX we want to next X pixel, DDY next Y pixel. */
1584 if (op == nir_op_fddx_fine ||
1585 op == nir_op_fddx_coarse ||
1586 op == nir_op_fddx)
1587 idx = 1;
1588 else
1589 idx = 2;
1590
1591 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1592 return result;
1593 }
1594
1595 /*
1596 * this takes an I,J coordinate pair,
1597 * and works out the X and Y derivatives.
1598 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1599 */
1600 static LLVMValueRef emit_ddxy_interp(
1601 struct ac_nir_context *ctx,
1602 LLVMValueRef interp_ij)
1603 {
1604 LLVMValueRef result[4], a;
1605 unsigned i;
1606
1607 for (i = 0; i < 2; i++) {
1608 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1609 LLVMConstInt(ctx->ac.i32, i, false), "");
1610 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1611 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1612 }
1613 return ac_build_gather_values(&ctx->ac, result, 4);
1614 }
1615
1616 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1617 {
1618 LLVMValueRef src[4], result = NULL;
1619 unsigned num_components = instr->dest.dest.ssa.num_components;
1620 unsigned src_components;
1621 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1622
1623 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1624 switch (instr->op) {
1625 case nir_op_vec2:
1626 case nir_op_vec3:
1627 case nir_op_vec4:
1628 src_components = 1;
1629 break;
1630 case nir_op_pack_half_2x16:
1631 src_components = 2;
1632 break;
1633 case nir_op_unpack_half_2x16:
1634 src_components = 1;
1635 break;
1636 default:
1637 src_components = num_components;
1638 break;
1639 }
1640 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1641 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1642
1643 switch (instr->op) {
1644 case nir_op_fmov:
1645 case nir_op_imov:
1646 result = src[0];
1647 break;
1648 case nir_op_fneg:
1649 src[0] = ac_to_float(&ctx->ac, src[0]);
1650 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1651 break;
1652 case nir_op_ineg:
1653 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1654 break;
1655 case nir_op_inot:
1656 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1657 break;
1658 case nir_op_iadd:
1659 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1660 break;
1661 case nir_op_fadd:
1662 src[0] = ac_to_float(&ctx->ac, src[0]);
1663 src[1] = ac_to_float(&ctx->ac, src[1]);
1664 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1665 break;
1666 case nir_op_fsub:
1667 src[0] = ac_to_float(&ctx->ac, src[0]);
1668 src[1] = ac_to_float(&ctx->ac, src[1]);
1669 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1670 break;
1671 case nir_op_isub:
1672 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1673 break;
1674 case nir_op_imul:
1675 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1676 break;
1677 case nir_op_imod:
1678 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1679 break;
1680 case nir_op_umod:
1681 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1682 break;
1683 case nir_op_fmod:
1684 src[0] = ac_to_float(&ctx->ac, src[0]);
1685 src[1] = ac_to_float(&ctx->ac, src[1]);
1686 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1687 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1688 ac_to_float_type(&ctx->ac, def_type), result);
1689 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1690 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1691 break;
1692 case nir_op_frem:
1693 src[0] = ac_to_float(&ctx->ac, src[0]);
1694 src[1] = ac_to_float(&ctx->ac, src[1]);
1695 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1696 break;
1697 case nir_op_irem:
1698 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1699 break;
1700 case nir_op_idiv:
1701 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_udiv:
1704 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1705 break;
1706 case nir_op_fmul:
1707 src[0] = ac_to_float(&ctx->ac, src[0]);
1708 src[1] = ac_to_float(&ctx->ac, src[1]);
1709 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1710 break;
1711 case nir_op_fdiv:
1712 src[0] = ac_to_float(&ctx->ac, src[0]);
1713 src[1] = ac_to_float(&ctx->ac, src[1]);
1714 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1715 break;
1716 case nir_op_frcp:
1717 src[0] = ac_to_float(&ctx->ac, src[0]);
1718 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1719 break;
1720 case nir_op_iand:
1721 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1722 break;
1723 case nir_op_ior:
1724 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1725 break;
1726 case nir_op_ixor:
1727 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1728 break;
1729 case nir_op_ishl:
1730 result = LLVMBuildShl(ctx->ac.builder, src[0],
1731 LLVMBuildZExt(ctx->ac.builder, src[1],
1732 LLVMTypeOf(src[0]), ""),
1733 "");
1734 break;
1735 case nir_op_ishr:
1736 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1737 LLVMBuildZExt(ctx->ac.builder, src[1],
1738 LLVMTypeOf(src[0]), ""),
1739 "");
1740 break;
1741 case nir_op_ushr:
1742 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1743 LLVMBuildZExt(ctx->ac.builder, src[1],
1744 LLVMTypeOf(src[0]), ""),
1745 "");
1746 break;
1747 case nir_op_ilt:
1748 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1749 break;
1750 case nir_op_ine:
1751 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1752 break;
1753 case nir_op_ieq:
1754 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1755 break;
1756 case nir_op_ige:
1757 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1758 break;
1759 case nir_op_ult:
1760 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1761 break;
1762 case nir_op_uge:
1763 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1764 break;
1765 case nir_op_feq:
1766 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1767 break;
1768 case nir_op_fne:
1769 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1770 break;
1771 case nir_op_flt:
1772 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1773 break;
1774 case nir_op_fge:
1775 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1776 break;
1777 case nir_op_fabs:
1778 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1779 ac_to_float_type(&ctx->ac, def_type), src[0]);
1780 break;
1781 case nir_op_iabs:
1782 result = emit_iabs(&ctx->ac, src[0]);
1783 break;
1784 case nir_op_imax:
1785 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1786 break;
1787 case nir_op_imin:
1788 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1789 break;
1790 case nir_op_umax:
1791 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1792 break;
1793 case nir_op_umin:
1794 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1795 break;
1796 case nir_op_isign:
1797 result = emit_isign(&ctx->ac, src[0]);
1798 break;
1799 case nir_op_fsign:
1800 src[0] = ac_to_float(&ctx->ac, src[0]);
1801 result = emit_fsign(&ctx->ac, src[0]);
1802 break;
1803 case nir_op_ffloor:
1804 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1805 ac_to_float_type(&ctx->ac, def_type), src[0]);
1806 break;
1807 case nir_op_ftrunc:
1808 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1809 ac_to_float_type(&ctx->ac, def_type), src[0]);
1810 break;
1811 case nir_op_fceil:
1812 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1813 ac_to_float_type(&ctx->ac, def_type), src[0]);
1814 break;
1815 case nir_op_fround_even:
1816 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1817 ac_to_float_type(&ctx->ac, def_type),src[0]);
1818 break;
1819 case nir_op_ffract:
1820 result = emit_ffract(&ctx->ac, src[0]);
1821 break;
1822 case nir_op_fsin:
1823 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1824 ac_to_float_type(&ctx->ac, def_type), src[0]);
1825 break;
1826 case nir_op_fcos:
1827 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1828 ac_to_float_type(&ctx->ac, def_type), src[0]);
1829 break;
1830 case nir_op_fsqrt:
1831 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1832 ac_to_float_type(&ctx->ac, def_type), src[0]);
1833 break;
1834 case nir_op_fexp2:
1835 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1836 ac_to_float_type(&ctx->ac, def_type), src[0]);
1837 break;
1838 case nir_op_flog2:
1839 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1840 ac_to_float_type(&ctx->ac, def_type), src[0]);
1841 break;
1842 case nir_op_frsq:
1843 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1844 ac_to_float_type(&ctx->ac, def_type), src[0]);
1845 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1846 break;
1847 case nir_op_fpow:
1848 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1849 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1850 break;
1851 case nir_op_fmax:
1852 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1853 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1854 if (instr->dest.dest.ssa.bit_size == 32)
1855 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1856 ac_to_float_type(&ctx->ac, def_type),
1857 result);
1858 break;
1859 case nir_op_fmin:
1860 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1861 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1862 if (instr->dest.dest.ssa.bit_size == 32)
1863 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1864 ac_to_float_type(&ctx->ac, def_type),
1865 result);
1866 break;
1867 case nir_op_ffma:
1868 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1869 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1870 break;
1871 case nir_op_ibitfield_extract:
1872 result = emit_bitfield_extract(&ctx->ac, true, src);
1873 break;
1874 case nir_op_ubitfield_extract:
1875 result = emit_bitfield_extract(&ctx->ac, false, src);
1876 break;
1877 case nir_op_bitfield_insert:
1878 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1879 break;
1880 case nir_op_bitfield_reverse:
1881 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1882 break;
1883 case nir_op_bit_count:
1884 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1885 break;
1886 case nir_op_vec2:
1887 case nir_op_vec3:
1888 case nir_op_vec4:
1889 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1890 src[i] = ac_to_integer(&ctx->ac, src[i]);
1891 result = ac_build_gather_values(&ctx->ac, src, num_components);
1892 break;
1893 case nir_op_f2i32:
1894 case nir_op_f2i64:
1895 src[0] = ac_to_float(&ctx->ac, src[0]);
1896 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1897 break;
1898 case nir_op_f2u32:
1899 case nir_op_f2u64:
1900 src[0] = ac_to_float(&ctx->ac, src[0]);
1901 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1902 break;
1903 case nir_op_i2f32:
1904 case nir_op_i2f64:
1905 src[0] = ac_to_integer(&ctx->ac, src[0]);
1906 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1907 break;
1908 case nir_op_u2f32:
1909 case nir_op_u2f64:
1910 src[0] = ac_to_integer(&ctx->ac, src[0]);
1911 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1912 break;
1913 case nir_op_f2f64:
1914 src[0] = ac_to_float(&ctx->ac, src[0]);
1915 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1916 break;
1917 case nir_op_f2f32:
1918 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1919 break;
1920 case nir_op_u2u32:
1921 case nir_op_u2u64:
1922 src[0] = ac_to_integer(&ctx->ac, src[0]);
1923 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1924 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1925 else
1926 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1927 break;
1928 case nir_op_i2i32:
1929 case nir_op_i2i64:
1930 src[0] = ac_to_integer(&ctx->ac, src[0]);
1931 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1932 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1933 else
1934 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1935 break;
1936 case nir_op_bcsel:
1937 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1938 break;
1939 case nir_op_find_lsb:
1940 src[0] = ac_to_integer(&ctx->ac, src[0]);
1941 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1942 break;
1943 case nir_op_ufind_msb:
1944 src[0] = ac_to_integer(&ctx->ac, src[0]);
1945 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1946 break;
1947 case nir_op_ifind_msb:
1948 src[0] = ac_to_integer(&ctx->ac, src[0]);
1949 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1950 break;
1951 case nir_op_uadd_carry:
1952 src[0] = ac_to_integer(&ctx->ac, src[0]);
1953 src[1] = ac_to_integer(&ctx->ac, src[1]);
1954 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1955 break;
1956 case nir_op_usub_borrow:
1957 src[0] = ac_to_integer(&ctx->ac, src[0]);
1958 src[1] = ac_to_integer(&ctx->ac, src[1]);
1959 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1960 break;
1961 case nir_op_b2f:
1962 result = emit_b2f(&ctx->ac, src[0]);
1963 break;
1964 case nir_op_f2b:
1965 result = emit_f2b(&ctx->ac, src[0]);
1966 break;
1967 case nir_op_b2i:
1968 result = emit_b2i(&ctx->ac, src[0]);
1969 break;
1970 case nir_op_i2b:
1971 src[0] = ac_to_integer(&ctx->ac, src[0]);
1972 result = emit_i2b(&ctx->ac, src[0]);
1973 break;
1974 case nir_op_fquantize2f16:
1975 result = emit_f2f16(ctx->nctx, src[0]);
1976 break;
1977 case nir_op_umul_high:
1978 src[0] = ac_to_integer(&ctx->ac, src[0]);
1979 src[1] = ac_to_integer(&ctx->ac, src[1]);
1980 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1981 break;
1982 case nir_op_imul_high:
1983 src[0] = ac_to_integer(&ctx->ac, src[0]);
1984 src[1] = ac_to_integer(&ctx->ac, src[1]);
1985 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1986 break;
1987 case nir_op_pack_half_2x16:
1988 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1989 break;
1990 case nir_op_unpack_half_2x16:
1991 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1992 break;
1993 case nir_op_fddx:
1994 case nir_op_fddy:
1995 case nir_op_fddx_fine:
1996 case nir_op_fddy_fine:
1997 case nir_op_fddx_coarse:
1998 case nir_op_fddy_coarse:
1999 result = emit_ddxy(ctx, instr->op, src[0]);
2000 break;
2001
2002 case nir_op_unpack_64_2x32_split_x: {
2003 assert(instr->src[0].src.ssa->num_components == 1);
2004 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2005 ctx->ac.v2i32,
2006 "");
2007 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2008 ctx->ac.i32_0, "");
2009 break;
2010 }
2011
2012 case nir_op_unpack_64_2x32_split_y: {
2013 assert(instr->src[0].src.ssa->num_components == 1);
2014 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2015 ctx->ac.v2i32,
2016 "");
2017 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2018 ctx->ac.i32_1, "");
2019 break;
2020 }
2021
2022 case nir_op_pack_64_2x32_split: {
2023 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2024 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2025 src[0], ctx->ac.i32_0, "");
2026 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2027 src[1], ctx->ac.i32_1, "");
2028 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2029 break;
2030 }
2031
2032 default:
2033 fprintf(stderr, "Unknown NIR alu instr: ");
2034 nir_print_instr(&instr->instr, stderr);
2035 fprintf(stderr, "\n");
2036 abort();
2037 }
2038
2039 if (result) {
2040 assert(instr->dest.dest.is_ssa);
2041 result = ac_to_integer(&ctx->ac, result);
2042 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2043 result);
2044 }
2045 }
2046
2047 static void visit_load_const(struct ac_nir_context *ctx,
2048 const nir_load_const_instr *instr)
2049 {
2050 LLVMValueRef values[4], value = NULL;
2051 LLVMTypeRef element_type =
2052 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2053
2054 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2055 switch (instr->def.bit_size) {
2056 case 32:
2057 values[i] = LLVMConstInt(element_type,
2058 instr->value.u32[i], false);
2059 break;
2060 case 64:
2061 values[i] = LLVMConstInt(element_type,
2062 instr->value.u64[i], false);
2063 break;
2064 default:
2065 fprintf(stderr,
2066 "unsupported nir load_const bit_size: %d\n",
2067 instr->def.bit_size);
2068 abort();
2069 }
2070 }
2071 if (instr->def.num_components > 1) {
2072 value = LLVMConstVector(values, instr->def.num_components);
2073 } else
2074 value = values[0];
2075
2076 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2077 }
2078
2079 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2080 LLVMTypeRef type)
2081 {
2082 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2083 return LLVMBuildBitCast(ctx->builder, ptr,
2084 LLVMPointerType(type, addr_space), "");
2085 }
2086
2087 static LLVMValueRef
2088 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2089 {
2090 LLVMValueRef size =
2091 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2092 LLVMConstInt(ctx->ac.i32, 2, false), "");
2093
2094 /* VI only */
2095 if (ctx->ac.chip_class == VI && in_elements) {
2096 /* On VI, the descriptor contains the size in bytes,
2097 * but TXQ must return the size in elements.
2098 * The stride is always non-zero for resources using TXQ.
2099 */
2100 LLVMValueRef stride =
2101 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2102 ctx->ac.i32_1, "");
2103 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2104 LLVMConstInt(ctx->ac.i32, 16, false), "");
2105 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2106 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2107
2108 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2109 }
2110 return size;
2111 }
2112
2113 /**
2114 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2115 * intrinsic names).
2116 */
2117 static void build_int_type_name(
2118 LLVMTypeRef type,
2119 char *buf, unsigned bufsize)
2120 {
2121 assert(bufsize >= 6);
2122
2123 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2124 snprintf(buf, bufsize, "v%ui32",
2125 LLVMGetVectorSize(type));
2126 else
2127 strcpy(buf, "i32");
2128 }
2129
2130 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2131 struct ac_image_args *args,
2132 const nir_tex_instr *instr)
2133 {
2134 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2135 LLVMValueRef coord = args->addr;
2136 LLVMValueRef half_texel[2];
2137 LLVMValueRef compare_cube_wa = NULL;
2138 LLVMValueRef result;
2139 int c;
2140 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2141
2142 //TODO Rect
2143 {
2144 struct ac_image_args txq_args = { 0 };
2145
2146 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2147 txq_args.opcode = ac_image_get_resinfo;
2148 txq_args.dmask = 0xf;
2149 txq_args.addr = ctx->i32_0;
2150 txq_args.resource = args->resource;
2151 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2152
2153 for (c = 0; c < 2; c++) {
2154 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2155 LLVMConstInt(ctx->i32, c, false), "");
2156 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2157 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2158 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2159 LLVMConstReal(ctx->f32, -0.5), "");
2160 }
2161 }
2162
2163 LLVMValueRef orig_coords = args->addr;
2164
2165 for (c = 0; c < 2; c++) {
2166 LLVMValueRef tmp;
2167 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2168 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2169 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2170 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2171 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2172 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2173 }
2174
2175
2176 /*
2177 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2178 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2179 * workaround by sampling using a scaled type and converting.
2180 * This is taken from amdgpu-pro shaders.
2181 */
2182 /* NOTE this produces some ugly code compared to amdgpu-pro,
2183 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2184 * and then reads them back. -pro generates two selects,
2185 * one s_cmp for the descriptor rewriting
2186 * one v_cmp for the coordinate and result changes.
2187 */
2188 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2189 LLVMValueRef tmp, tmp2;
2190
2191 /* workaround 8/8/8/8 uint/sint cube gather bug */
2192 /* first detect it then change to a scaled read and f2i */
2193 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2194 tmp2 = tmp;
2195
2196 /* extract the DATA_FORMAT */
2197 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2198 LLVMConstInt(ctx->i32, 6, false), false);
2199
2200 /* is the DATA_FORMAT == 8_8_8_8 */
2201 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2202
2203 if (stype == GLSL_TYPE_UINT)
2204 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2205 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2206 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2207 else
2208 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2209 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2210 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2211
2212 /* replace the NUM FORMAT in the descriptor */
2213 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2214 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2215
2216 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2217
2218 /* don't modify the coordinates for this case */
2219 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2220 }
2221 args->addr = coord;
2222 result = ac_build_image_opcode(ctx, args);
2223
2224 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2225 LLVMValueRef tmp, tmp2;
2226
2227 /* if the cube workaround is in place, f2i the result. */
2228 for (c = 0; c < 4; c++) {
2229 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2230 if (stype == GLSL_TYPE_UINT)
2231 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2232 else
2233 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2234 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2235 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2236 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2237 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2238 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2239 }
2240 }
2241 return result;
2242 }
2243
2244 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2245 const nir_tex_instr *instr,
2246 bool lod_is_zero,
2247 struct ac_image_args *args)
2248 {
2249 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2250 return ac_build_buffer_load_format(&ctx->ac,
2251 args->resource,
2252 args->addr,
2253 ctx->ac.i32_0,
2254 true);
2255 }
2256
2257 args->opcode = ac_image_sample;
2258 args->compare = instr->is_shadow;
2259
2260 switch (instr->op) {
2261 case nir_texop_txf:
2262 case nir_texop_txf_ms:
2263 case nir_texop_samples_identical:
2264 args->opcode = lod_is_zero ||
2265 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2266 ac_image_load : ac_image_load_mip;
2267 args->compare = false;
2268 args->offset = false;
2269 break;
2270 case nir_texop_txb:
2271 args->bias = true;
2272 break;
2273 case nir_texop_txl:
2274 if (lod_is_zero)
2275 args->level_zero = true;
2276 else
2277 args->lod = true;
2278 break;
2279 case nir_texop_txs:
2280 case nir_texop_query_levels:
2281 args->opcode = ac_image_get_resinfo;
2282 break;
2283 case nir_texop_tex:
2284 if (ctx->stage != MESA_SHADER_FRAGMENT)
2285 args->level_zero = true;
2286 break;
2287 case nir_texop_txd:
2288 args->deriv = true;
2289 break;
2290 case nir_texop_tg4:
2291 args->opcode = ac_image_gather4;
2292 args->level_zero = true;
2293 break;
2294 case nir_texop_lod:
2295 args->opcode = ac_image_get_lod;
2296 args->compare = false;
2297 args->offset = false;
2298 break;
2299 default:
2300 break;
2301 }
2302
2303 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2304 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2305 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2306 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2307 }
2308 }
2309 return ac_build_image_opcode(&ctx->ac, args);
2310 }
2311
2312 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2313 nir_intrinsic_instr *instr)
2314 {
2315 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2316 unsigned desc_set = nir_intrinsic_desc_set(instr);
2317 unsigned binding = nir_intrinsic_binding(instr);
2318 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2319 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2320 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2321 unsigned base_offset = layout->binding[binding].offset;
2322 LLVMValueRef offset, stride;
2323
2324 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2325 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2326 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2327 layout->binding[binding].dynamic_offset_offset;
2328 desc_ptr = ctx->push_constants;
2329 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2330 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2331 } else
2332 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2333
2334 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2335 index = LLVMBuildMul(ctx->builder, index, stride, "");
2336 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2337
2338 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2339 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2340 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2341
2342 return desc_ptr;
2343 }
2344
2345 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2346 nir_intrinsic_instr *instr)
2347 {
2348 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2349 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2350
2351 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2352 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2353 return result;
2354 }
2355
2356 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2357 nir_intrinsic_instr *instr)
2358 {
2359 LLVMValueRef ptr, addr;
2360
2361 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2362 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2363
2364 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2365 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2366
2367 return LLVMBuildLoad(ctx->builder, ptr, "");
2368 }
2369
2370 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2371 const nir_intrinsic_instr *instr)
2372 {
2373 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2374
2375 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2376 }
2377 static void visit_store_ssbo(struct ac_nir_context *ctx,
2378 nir_intrinsic_instr *instr)
2379 {
2380 const char *store_name;
2381 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2382 LLVMTypeRef data_type = ctx->ac.f32;
2383 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2384 int components_32bit = elem_size_mult * instr->num_components;
2385 unsigned writemask = nir_intrinsic_write_mask(instr);
2386 LLVMValueRef base_data, base_offset;
2387 LLVMValueRef params[6];
2388
2389 params[1] = ctx->abi->load_ssbo(ctx->abi,
2390 get_src(ctx, instr->src[1]), true);
2391 params[2] = ctx->ac.i32_0; /* vindex */
2392 params[4] = ctx->ac.i1false; /* glc */
2393 params[5] = ctx->ac.i1false; /* slc */
2394
2395 if (components_32bit > 1)
2396 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2397
2398 base_data = ac_to_float(&ctx->ac, src_data);
2399 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2400 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2401 data_type, "");
2402 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2403 while (writemask) {
2404 int start, count;
2405 LLVMValueRef data;
2406 LLVMValueRef offset;
2407 LLVMValueRef tmp;
2408 u_bit_scan_consecutive_range(&writemask, &start, &count);
2409
2410 /* Due to an LLVM limitation, split 3-element writes
2411 * into a 2-element and a 1-element write. */
2412 if (count == 3) {
2413 writemask |= 1 << (start + 2);
2414 count = 2;
2415 }
2416
2417 start *= elem_size_mult;
2418 count *= elem_size_mult;
2419
2420 if (count > 4) {
2421 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2422 count = 4;
2423 }
2424
2425 if (count == 4) {
2426 store_name = "llvm.amdgcn.buffer.store.v4f32";
2427 data = base_data;
2428 } else if (count == 2) {
2429 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2430 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2431 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2432 ctx->ac.i32_0, "");
2433
2434 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2435 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2436 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2437 ctx->ac.i32_1, "");
2438 store_name = "llvm.amdgcn.buffer.store.v2f32";
2439
2440 } else {
2441 assert(count == 1);
2442 if (ac_get_llvm_num_components(base_data) > 1)
2443 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2444 LLVMConstInt(ctx->ac.i32, start, false), "");
2445 else
2446 data = base_data;
2447 store_name = "llvm.amdgcn.buffer.store.f32";
2448 }
2449
2450 offset = base_offset;
2451 if (start != 0) {
2452 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2453 }
2454 params[0] = data;
2455 params[3] = offset;
2456 ac_build_intrinsic(&ctx->ac, store_name,
2457 ctx->ac.voidt, params, 6, 0);
2458 }
2459 }
2460
2461 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2462 const nir_intrinsic_instr *instr)
2463 {
2464 const char *name;
2465 LLVMValueRef params[6];
2466 int arg_count = 0;
2467
2468 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2469 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2470 }
2471 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2472 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2473 get_src(ctx, instr->src[0]),
2474 true);
2475 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2476 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2477 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2478
2479 switch (instr->intrinsic) {
2480 case nir_intrinsic_ssbo_atomic_add:
2481 name = "llvm.amdgcn.buffer.atomic.add";
2482 break;
2483 case nir_intrinsic_ssbo_atomic_imin:
2484 name = "llvm.amdgcn.buffer.atomic.smin";
2485 break;
2486 case nir_intrinsic_ssbo_atomic_umin:
2487 name = "llvm.amdgcn.buffer.atomic.umin";
2488 break;
2489 case nir_intrinsic_ssbo_atomic_imax:
2490 name = "llvm.amdgcn.buffer.atomic.smax";
2491 break;
2492 case nir_intrinsic_ssbo_atomic_umax:
2493 name = "llvm.amdgcn.buffer.atomic.umax";
2494 break;
2495 case nir_intrinsic_ssbo_atomic_and:
2496 name = "llvm.amdgcn.buffer.atomic.and";
2497 break;
2498 case nir_intrinsic_ssbo_atomic_or:
2499 name = "llvm.amdgcn.buffer.atomic.or";
2500 break;
2501 case nir_intrinsic_ssbo_atomic_xor:
2502 name = "llvm.amdgcn.buffer.atomic.xor";
2503 break;
2504 case nir_intrinsic_ssbo_atomic_exchange:
2505 name = "llvm.amdgcn.buffer.atomic.swap";
2506 break;
2507 case nir_intrinsic_ssbo_atomic_comp_swap:
2508 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2509 break;
2510 default:
2511 abort();
2512 }
2513
2514 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2515 }
2516
2517 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2518 const nir_intrinsic_instr *instr)
2519 {
2520 LLVMValueRef results[2];
2521 int load_components;
2522 int num_components = instr->num_components;
2523 if (instr->dest.ssa.bit_size == 64)
2524 num_components *= 2;
2525
2526 for (int i = 0; i < num_components; i += load_components) {
2527 load_components = MIN2(num_components - i, 4);
2528 const char *load_name;
2529 LLVMTypeRef data_type = ctx->ac.f32;
2530 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2531 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2532
2533 if (load_components == 3)
2534 data_type = LLVMVectorType(ctx->ac.f32, 4);
2535 else if (load_components > 1)
2536 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2537
2538 if (load_components >= 3)
2539 load_name = "llvm.amdgcn.buffer.load.v4f32";
2540 else if (load_components == 2)
2541 load_name = "llvm.amdgcn.buffer.load.v2f32";
2542 else if (load_components == 1)
2543 load_name = "llvm.amdgcn.buffer.load.f32";
2544 else
2545 unreachable("unhandled number of components");
2546
2547 LLVMValueRef params[] = {
2548 ctx->abi->load_ssbo(ctx->abi,
2549 get_src(ctx, instr->src[0]),
2550 false),
2551 ctx->ac.i32_0,
2552 offset,
2553 ctx->ac.i1false,
2554 ctx->ac.i1false,
2555 };
2556
2557 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2558
2559 }
2560
2561 assume(results[0]);
2562 LLVMValueRef ret = results[0];
2563 if (num_components > 4 || num_components == 3) {
2564 LLVMValueRef masks[] = {
2565 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2566 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2567 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2568 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2569 };
2570
2571 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2572 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2573 results[num_components > 4 ? 1 : 0], swizzle, "");
2574 }
2575
2576 return LLVMBuildBitCast(ctx->ac.builder, ret,
2577 get_def_type(ctx, &instr->dest.ssa), "");
2578 }
2579
2580 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2581 const nir_intrinsic_instr *instr)
2582 {
2583 LLVMValueRef ret;
2584 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2585 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2586 int num_components = instr->num_components;
2587
2588 if (ctx->abi->load_ubo)
2589 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2590
2591 if (instr->dest.ssa.bit_size == 64)
2592 num_components *= 2;
2593
2594 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2595 NULL, 0, false, false, true, true);
2596
2597 return LLVMBuildBitCast(ctx->ac.builder, ret,
2598 get_def_type(ctx, &instr->dest.ssa), "");
2599 }
2600
2601 static void
2602 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2603 bool vs_in, unsigned *vertex_index_out,
2604 LLVMValueRef *vertex_index_ref,
2605 unsigned *const_out, LLVMValueRef *indir_out)
2606 {
2607 unsigned const_offset = 0;
2608 nir_deref *tail = &deref->deref;
2609 LLVMValueRef offset = NULL;
2610
2611 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2612 tail = tail->child;
2613 nir_deref_array *deref_array = nir_deref_as_array(tail);
2614 if (vertex_index_out)
2615 *vertex_index_out = deref_array->base_offset;
2616
2617 if (vertex_index_ref) {
2618 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2619 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2620 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2621 }
2622 *vertex_index_ref = vtx;
2623 }
2624 }
2625
2626 if (deref->var->data.compact) {
2627 assert(tail->child->deref_type == nir_deref_type_array);
2628 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2629 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2630 /* We always lower indirect dereferences for "compact" array vars. */
2631 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2632
2633 const_offset = deref_array->base_offset;
2634 goto out;
2635 }
2636
2637 while (tail->child != NULL) {
2638 const struct glsl_type *parent_type = tail->type;
2639 tail = tail->child;
2640
2641 if (tail->deref_type == nir_deref_type_array) {
2642 nir_deref_array *deref_array = nir_deref_as_array(tail);
2643 LLVMValueRef index, stride, local_offset;
2644 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2645
2646 const_offset += size * deref_array->base_offset;
2647 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2648 continue;
2649
2650 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2651 index = get_src(ctx, deref_array->indirect);
2652 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2653 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2654
2655 if (offset)
2656 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2657 else
2658 offset = local_offset;
2659 } else if (tail->deref_type == nir_deref_type_struct) {
2660 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2661
2662 for (unsigned i = 0; i < deref_struct->index; i++) {
2663 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2664 const_offset += glsl_count_attribute_slots(ft, vs_in);
2665 }
2666 } else
2667 unreachable("unsupported deref type");
2668
2669 }
2670 out:
2671 if (const_offset && offset)
2672 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2673 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2674 "");
2675
2676 *const_out = const_offset;
2677 *indir_out = offset;
2678 }
2679
2680
2681 /* The offchip buffer layout for TCS->TES is
2682 *
2683 * - attribute 0 of patch 0 vertex 0
2684 * - attribute 0 of patch 0 vertex 1
2685 * - attribute 0 of patch 0 vertex 2
2686 * ...
2687 * - attribute 0 of patch 1 vertex 0
2688 * - attribute 0 of patch 1 vertex 1
2689 * ...
2690 * - attribute 1 of patch 0 vertex 0
2691 * - attribute 1 of patch 0 vertex 1
2692 * ...
2693 * - per patch attribute 0 of patch 0
2694 * - per patch attribute 0 of patch 1
2695 * ...
2696 *
2697 * Note that every attribute has 4 components.
2698 */
2699 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2700 LLVMValueRef vertex_index,
2701 LLVMValueRef param_index)
2702 {
2703 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2704 LLVMValueRef param_stride, constant16;
2705 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2706
2707 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2708 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2709 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2710 num_patches, "");
2711
2712 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2713 if (vertex_index) {
2714 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2715 vertices_per_patch, "");
2716
2717 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2718 vertex_index, "");
2719
2720 param_stride = total_vertices;
2721 } else {
2722 base_addr = rel_patch_id;
2723 param_stride = num_patches;
2724 }
2725
2726 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2727 LLVMBuildMul(ctx->builder, param_index,
2728 param_stride, ""), "");
2729
2730 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2731
2732 if (!vertex_index) {
2733 LLVMValueRef patch_data_offset =
2734 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2735
2736 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2737 patch_data_offset, "");
2738 }
2739 return base_addr;
2740 }
2741
2742 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2743 unsigned param,
2744 unsigned const_index,
2745 bool is_compact,
2746 LLVMValueRef vertex_index,
2747 LLVMValueRef indir_index)
2748 {
2749 LLVMValueRef param_index;
2750
2751 if (indir_index)
2752 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2753 indir_index, "");
2754 else {
2755 if (const_index && !is_compact)
2756 param += const_index;
2757 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2758 }
2759 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2760 }
2761
2762 static void
2763 mark_tess_output(struct nir_to_llvm_context *ctx,
2764 bool is_patch, uint32_t param)
2765
2766 {
2767 if (is_patch) {
2768 ctx->tess_patch_outputs_written |= (1ull << param);
2769 } else
2770 ctx->tess_outputs_written |= (1ull << param);
2771 }
2772
2773 static LLVMValueRef
2774 get_dw_address(struct nir_to_llvm_context *ctx,
2775 LLVMValueRef dw_addr,
2776 unsigned param,
2777 unsigned const_index,
2778 bool compact_const_index,
2779 LLVMValueRef vertex_index,
2780 LLVMValueRef stride,
2781 LLVMValueRef indir_index)
2782
2783 {
2784
2785 if (vertex_index) {
2786 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2787 LLVMBuildMul(ctx->builder,
2788 vertex_index,
2789 stride, ""), "");
2790 }
2791
2792 if (indir_index)
2793 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2794 LLVMBuildMul(ctx->builder, indir_index,
2795 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2796 else if (const_index && !compact_const_index)
2797 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2798 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2799
2800 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2801 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2802
2803 if (const_index && compact_const_index)
2804 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2805 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2806 return dw_addr;
2807 }
2808
2809 static LLVMValueRef
2810 load_tcs_input(struct ac_shader_abi *abi,
2811 LLVMValueRef vertex_index,
2812 LLVMValueRef indir_index,
2813 unsigned const_index,
2814 unsigned location,
2815 unsigned driver_location,
2816 unsigned component,
2817 unsigned num_components,
2818 bool is_patch,
2819 bool is_compact)
2820 {
2821 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2822 LLVMValueRef dw_addr, stride;
2823 LLVMValueRef value[4], result;
2824 unsigned param = shader_io_get_unique_index(location);
2825
2826 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2827 dw_addr = get_tcs_in_current_patch_offset(ctx);
2828 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2829 indir_index);
2830
2831 for (unsigned i = 0; i < num_components + component; i++) {
2832 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2833 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2834 ctx->ac.i32_1, "");
2835 }
2836 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2837 return result;
2838 }
2839
2840 static LLVMValueRef
2841 load_tcs_output(struct nir_to_llvm_context *ctx,
2842 nir_intrinsic_instr *instr)
2843 {
2844 LLVMValueRef dw_addr;
2845 LLVMValueRef stride = NULL;
2846 LLVMValueRef value[4], result;
2847 LLVMValueRef vertex_index = NULL;
2848 LLVMValueRef indir_index = NULL;
2849 unsigned const_index = 0;
2850 unsigned param;
2851 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2852 const bool is_compact = instr->variables[0]->var->data.compact;
2853 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2854 get_deref_offset(ctx->nir, instr->variables[0],
2855 false, NULL, per_vertex ? &vertex_index : NULL,
2856 &const_index, &indir_index);
2857
2858 if (!instr->variables[0]->var->data.patch) {
2859 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2860 dw_addr = get_tcs_out_current_patch_offset(ctx);
2861 } else {
2862 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2863 }
2864
2865 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2866 indir_index);
2867
2868 unsigned comp = instr->variables[0]->var->data.location_frac;
2869 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2870 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2871 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2872 ctx->ac.i32_1, "");
2873 }
2874 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2875 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2876 return result;
2877 }
2878
2879 static void
2880 store_tcs_output(struct ac_shader_abi *abi,
2881 LLVMValueRef vertex_index,
2882 LLVMValueRef param_index,
2883 unsigned const_index,
2884 unsigned location,
2885 unsigned driver_location,
2886 LLVMValueRef src,
2887 unsigned component,
2888 bool is_patch,
2889 bool is_compact,
2890 unsigned writemask)
2891 {
2892 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2893 LLVMValueRef dw_addr;
2894 LLVMValueRef stride = NULL;
2895 LLVMValueRef buf_addr = NULL;
2896 unsigned param;
2897 bool store_lds = true;
2898
2899 if (is_patch) {
2900 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2901 store_lds = false;
2902 } else {
2903 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2904 store_lds = false;
2905 }
2906
2907 param = shader_io_get_unique_index(location);
2908 if (location == VARYING_SLOT_CLIP_DIST0 &&
2909 is_compact && const_index > 3) {
2910 const_index -= 3;
2911 param++;
2912 }
2913
2914 if (!is_patch) {
2915 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2916 dw_addr = get_tcs_out_current_patch_offset(ctx);
2917 } else {
2918 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2919 }
2920
2921 mark_tess_output(ctx, is_patch, param);
2922
2923 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2924 param_index);
2925 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2926 vertex_index, param_index);
2927
2928 bool is_tess_factor = false;
2929 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2930 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2931 is_tess_factor = true;
2932
2933 unsigned base = is_compact ? const_index : 0;
2934 for (unsigned chan = 0; chan < 8; chan++) {
2935 if (!(writemask & (1 << chan)))
2936 continue;
2937 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2938
2939 if (store_lds || is_tess_factor)
2940 ac_lds_store(&ctx->ac, dw_addr, value);
2941
2942 if (!is_tess_factor && writemask != 0xF)
2943 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2944 buf_addr, ctx->oc_lds,
2945 4 * (base + chan), 1, 0, true, false);
2946
2947 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2948 ctx->ac.i32_1, "");
2949 }
2950
2951 if (writemask == 0xF) {
2952 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2953 buf_addr, ctx->oc_lds,
2954 (base * 4), 1, 0, true, false);
2955 }
2956 }
2957
2958 static LLVMValueRef
2959 load_tes_input(struct ac_shader_abi *abi,
2960 LLVMValueRef vertex_index,
2961 LLVMValueRef param_index,
2962 unsigned const_index,
2963 unsigned location,
2964 unsigned driver_location,
2965 unsigned component,
2966 unsigned num_components,
2967 bool is_patch,
2968 bool is_compact)
2969 {
2970 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2971 LLVMValueRef buf_addr;
2972 LLVMValueRef result;
2973 unsigned param = shader_io_get_unique_index(location);
2974
2975 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2976 const_index -= 3;
2977 param++;
2978 }
2979
2980 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2981 is_compact, vertex_index, param_index);
2982
2983 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
2984 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2985
2986 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
2987 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2988 result = trim_vector(&ctx->ac, result, num_components);
2989 return result;
2990 }
2991
2992 static LLVMValueRef
2993 load_gs_input(struct ac_shader_abi *abi,
2994 unsigned location,
2995 unsigned driver_location,
2996 unsigned component,
2997 unsigned num_components,
2998 unsigned vertex_index,
2999 unsigned const_index,
3000 LLVMTypeRef type)
3001 {
3002 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3003 LLVMValueRef vtx_offset;
3004 LLVMValueRef args[9];
3005 unsigned param, vtx_offset_param;
3006 LLVMValueRef value[4], result;
3007
3008 vtx_offset_param = vertex_index;
3009 assert(vtx_offset_param < 6);
3010 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3011 LLVMConstInt(ctx->ac.i32, 4, false), "");
3012
3013 param = shader_io_get_unique_index(location);
3014
3015 for (unsigned i = component; i < num_components + component; i++) {
3016 if (ctx->ac.chip_class >= GFX9) {
3017 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3018 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3019 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3020 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3021 } else {
3022 args[0] = ctx->esgs_ring;
3023 args[1] = vtx_offset;
3024 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3025 args[3] = ctx->ac.i32_0;
3026 args[4] = ctx->ac.i32_1; /* OFFEN */
3027 args[5] = ctx->ac.i32_0; /* IDXEN */
3028 args[6] = ctx->ac.i32_1; /* GLC */
3029 args[7] = ctx->ac.i32_0; /* SLC */
3030 args[8] = ctx->ac.i32_0; /* TFE */
3031
3032 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3033 ctx->ac.i32, args, 9,
3034 AC_FUNC_ATTR_READONLY |
3035 AC_FUNC_ATTR_LEGACY);
3036 }
3037 }
3038 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3039
3040 return result;
3041 }
3042
3043 static LLVMValueRef
3044 build_gep_for_deref(struct ac_nir_context *ctx,
3045 nir_deref_var *deref)
3046 {
3047 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3048 assert(entry->data);
3049 LLVMValueRef val = entry->data;
3050 nir_deref *tail = deref->deref.child;
3051 while (tail != NULL) {
3052 LLVMValueRef offset;
3053 switch (tail->deref_type) {
3054 case nir_deref_type_array: {
3055 nir_deref_array *array = nir_deref_as_array(tail);
3056 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3057 if (array->deref_array_type ==
3058 nir_deref_array_type_indirect) {
3059 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3060 get_src(ctx,
3061 array->indirect),
3062 "");
3063 }
3064 break;
3065 }
3066 case nir_deref_type_struct: {
3067 nir_deref_struct *deref_struct =
3068 nir_deref_as_struct(tail);
3069 offset = LLVMConstInt(ctx->ac.i32,
3070 deref_struct->index, 0);
3071 break;
3072 }
3073 default:
3074 unreachable("bad deref type");
3075 }
3076 val = ac_build_gep0(&ctx->ac, val, offset);
3077 tail = tail->child;
3078 }
3079 return val;
3080 }
3081
3082 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3083 nir_intrinsic_instr *instr)
3084 {
3085 LLVMValueRef values[8];
3086 int idx = instr->variables[0]->var->data.driver_location;
3087 int ve = instr->dest.ssa.num_components;
3088 unsigned comp = instr->variables[0]->var->data.location_frac;
3089 LLVMValueRef indir_index;
3090 LLVMValueRef ret;
3091 unsigned const_index;
3092 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3093 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3094 instr->variables[0]->var->data.mode == nir_var_shader_in;
3095 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3096 &const_index, &indir_index);
3097
3098 if (instr->dest.ssa.bit_size == 64)
3099 ve *= 2;
3100
3101 switch (instr->variables[0]->var->data.mode) {
3102 case nir_var_shader_in:
3103 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3104 ctx->stage == MESA_SHADER_TESS_EVAL) {
3105 LLVMValueRef result;
3106 LLVMValueRef vertex_index = NULL;
3107 LLVMValueRef indir_index = NULL;
3108 unsigned const_index = 0;
3109 unsigned location = instr->variables[0]->var->data.location;
3110 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3111 const bool is_patch = instr->variables[0]->var->data.patch;
3112 const bool is_compact = instr->variables[0]->var->data.compact;
3113
3114 get_deref_offset(ctx, instr->variables[0],
3115 false, NULL, is_patch ? NULL : &vertex_index,
3116 &const_index, &indir_index);
3117
3118 result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, indir_index,
3119 const_index, location, driver_location,
3120 instr->variables[0]->var->data.location_frac,
3121 instr->num_components,
3122 is_patch, is_compact);
3123 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3124 }
3125
3126 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3127 LLVMValueRef indir_index;
3128 unsigned const_index, vertex_index;
3129 get_deref_offset(ctx, instr->variables[0],
3130 false, &vertex_index, NULL,
3131 &const_index, &indir_index);
3132 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3133 instr->variables[0]->var->data.driver_location,
3134 instr->variables[0]->var->data.location_frac, ve,
3135 vertex_index, const_index,
3136 nir2llvmtype(ctx, instr->variables[0]->var->type));
3137 }
3138
3139 for (unsigned chan = comp; chan < ve + comp; chan++) {
3140 if (indir_index) {
3141 unsigned count = glsl_count_attribute_slots(
3142 instr->variables[0]->var->type,
3143 ctx->stage == MESA_SHADER_VERTEX);
3144 count -= chan / 4;
3145 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3146 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3147 stride, false, true);
3148
3149 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3150 tmp_vec,
3151 indir_index, "");
3152 } else
3153 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3154 }
3155 break;
3156 case nir_var_local:
3157 for (unsigned chan = 0; chan < ve; chan++) {
3158 if (indir_index) {
3159 unsigned count = glsl_count_attribute_slots(
3160 instr->variables[0]->var->type, false);
3161 count -= chan / 4;
3162 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3163 &ctx->ac, ctx->locals + idx + chan, count,
3164 stride, true, true);
3165
3166 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3167 tmp_vec,
3168 indir_index, "");
3169 } else {
3170 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3171 }
3172 }
3173 break;
3174 case nir_var_shared: {
3175 LLVMValueRef address = build_gep_for_deref(ctx,
3176 instr->variables[0]);
3177 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3178 return LLVMBuildBitCast(ctx->ac.builder, val,
3179 get_def_type(ctx, &instr->dest.ssa),
3180 "");
3181 }
3182 case nir_var_shader_out:
3183 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3184 return load_tcs_output(ctx->nctx, instr);
3185
3186 for (unsigned chan = comp; chan < ve + comp; chan++) {
3187 if (indir_index) {
3188 unsigned count = glsl_count_attribute_slots(
3189 instr->variables[0]->var->type, false);
3190 count -= chan / 4;
3191 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3192 &ctx->ac, ctx->outputs + idx + chan, count,
3193 stride, true, true);
3194
3195 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3196 tmp_vec,
3197 indir_index, "");
3198 } else {
3199 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3200 ctx->outputs[idx + chan + const_index * stride],
3201 "");
3202 }
3203 }
3204 break;
3205 default:
3206 unreachable("unhandle variable mode");
3207 }
3208 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3209 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3210 }
3211
3212 static void
3213 visit_store_var(struct ac_nir_context *ctx,
3214 nir_intrinsic_instr *instr)
3215 {
3216 LLVMValueRef temp_ptr, value;
3217 int idx = instr->variables[0]->var->data.driver_location;
3218 unsigned comp = instr->variables[0]->var->data.location_frac;
3219 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3220 int writemask = instr->const_index[0] << comp;
3221 LLVMValueRef indir_index;
3222 unsigned const_index;
3223 get_deref_offset(ctx, instr->variables[0], false,
3224 NULL, NULL, &const_index, &indir_index);
3225
3226 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3227 int old_writemask = writemask;
3228
3229 src = LLVMBuildBitCast(ctx->ac.builder, src,
3230 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3231 "");
3232
3233 writemask = 0;
3234 for (unsigned chan = 0; chan < 4; chan++) {
3235 if (old_writemask & (1 << chan))
3236 writemask |= 3u << (2 * chan);
3237 }
3238 }
3239
3240 switch (instr->variables[0]->var->data.mode) {
3241 case nir_var_shader_out:
3242
3243 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3244 LLVMValueRef vertex_index = NULL;
3245 LLVMValueRef indir_index = NULL;
3246 unsigned const_index = 0;
3247 const unsigned location = instr->variables[0]->var->data.location;
3248 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3249 const unsigned comp = instr->variables[0]->var->data.location_frac;
3250 const bool is_patch = instr->variables[0]->var->data.patch;
3251 const bool is_compact = instr->variables[0]->var->data.compact;
3252
3253 get_deref_offset(ctx, instr->variables[0],
3254 false, NULL, is_patch ? NULL : &vertex_index,
3255 &const_index, &indir_index);
3256
3257 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3258 const_index, location, driver_location,
3259 src, comp, is_patch, is_compact, writemask);
3260 return;
3261 }
3262
3263 for (unsigned chan = 0; chan < 8; chan++) {
3264 int stride = 4;
3265 if (!(writemask & (1 << chan)))
3266 continue;
3267
3268 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3269
3270 if (instr->variables[0]->var->data.compact)
3271 stride = 1;
3272 if (indir_index) {
3273 unsigned count = glsl_count_attribute_slots(
3274 instr->variables[0]->var->type, false);
3275 count -= chan / 4;
3276 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3277 &ctx->ac, ctx->outputs + idx + chan, count,
3278 stride, true, true);
3279
3280 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3281 value, indir_index, "");
3282 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3283 count, stride, tmp_vec);
3284
3285 } else {
3286 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3287
3288 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3289 }
3290 }
3291 break;
3292 case nir_var_local:
3293 for (unsigned chan = 0; chan < 8; chan++) {
3294 if (!(writemask & (1 << chan)))
3295 continue;
3296
3297 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3298 if (indir_index) {
3299 unsigned count = glsl_count_attribute_slots(
3300 instr->variables[0]->var->type, false);
3301 count -= chan / 4;
3302 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3303 &ctx->ac, ctx->locals + idx + chan, count,
3304 4, true, true);
3305
3306 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3307 value, indir_index, "");
3308 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3309 count, 4, tmp_vec);
3310 } else {
3311 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3312
3313 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3314 }
3315 }
3316 break;
3317 case nir_var_shared: {
3318 int writemask = instr->const_index[0];
3319 LLVMValueRef address = build_gep_for_deref(ctx,
3320 instr->variables[0]);
3321 LLVMValueRef val = get_src(ctx, instr->src[0]);
3322 unsigned components =
3323 glsl_get_vector_elements(
3324 nir_deref_tail(&instr->variables[0]->deref)->type);
3325 if (writemask == (1 << components) - 1) {
3326 val = LLVMBuildBitCast(
3327 ctx->ac.builder, val,
3328 LLVMGetElementType(LLVMTypeOf(address)), "");
3329 LLVMBuildStore(ctx->ac.builder, val, address);
3330 } else {
3331 for (unsigned chan = 0; chan < 4; chan++) {
3332 if (!(writemask & (1 << chan)))
3333 continue;
3334 LLVMValueRef ptr =
3335 LLVMBuildStructGEP(ctx->ac.builder,
3336 address, chan, "");
3337 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3338 chan);
3339 src = LLVMBuildBitCast(
3340 ctx->ac.builder, src,
3341 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3342 LLVMBuildStore(ctx->ac.builder, src, ptr);
3343 }
3344 }
3345 break;
3346 }
3347 default:
3348 break;
3349 }
3350 }
3351
3352 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3353 {
3354 switch (dim) {
3355 case GLSL_SAMPLER_DIM_BUF:
3356 return 1;
3357 case GLSL_SAMPLER_DIM_1D:
3358 return array ? 2 : 1;
3359 case GLSL_SAMPLER_DIM_2D:
3360 return array ? 3 : 2;
3361 case GLSL_SAMPLER_DIM_MS:
3362 return array ? 4 : 3;
3363 case GLSL_SAMPLER_DIM_3D:
3364 case GLSL_SAMPLER_DIM_CUBE:
3365 return 3;
3366 case GLSL_SAMPLER_DIM_RECT:
3367 case GLSL_SAMPLER_DIM_SUBPASS:
3368 return 2;
3369 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3370 return 3;
3371 default:
3372 break;
3373 }
3374 return 0;
3375 }
3376
3377
3378
3379 /* Adjust the sample index according to FMASK.
3380 *
3381 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3382 * which is the identity mapping. Each nibble says which physical sample
3383 * should be fetched to get that sample.
3384 *
3385 * For example, 0x11111100 means there are only 2 samples stored and
3386 * the second sample covers 3/4 of the pixel. When reading samples 0
3387 * and 1, return physical sample 0 (determined by the first two 0s
3388 * in FMASK), otherwise return physical sample 1.
3389 *
3390 * The sample index should be adjusted as follows:
3391 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3392 */
3393 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3394 LLVMValueRef coord_x, LLVMValueRef coord_y,
3395 LLVMValueRef coord_z,
3396 LLVMValueRef sample_index,
3397 LLVMValueRef fmask_desc_ptr)
3398 {
3399 LLVMValueRef fmask_load_address[4];
3400 LLVMValueRef res;
3401
3402 fmask_load_address[0] = coord_x;
3403 fmask_load_address[1] = coord_y;
3404 if (coord_z) {
3405 fmask_load_address[2] = coord_z;
3406 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3407 }
3408
3409 struct ac_image_args args = {0};
3410
3411 args.opcode = ac_image_load;
3412 args.da = coord_z ? true : false;
3413 args.resource = fmask_desc_ptr;
3414 args.dmask = 0xf;
3415 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3416
3417 res = ac_build_image_opcode(ctx, &args);
3418
3419 res = ac_to_integer(ctx, res);
3420 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3421 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3422
3423 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3424 res,
3425 ctx->i32_0, "");
3426
3427 LLVMValueRef sample_index4 =
3428 LLVMBuildMul(ctx->builder, sample_index, four, "");
3429 LLVMValueRef shifted_fmask =
3430 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3431 LLVMValueRef final_sample =
3432 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3433
3434 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3435 * resource descriptor is 0 (invalid),
3436 */
3437 LLVMValueRef fmask_desc =
3438 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3439 ctx->v8i32, "");
3440
3441 LLVMValueRef fmask_word1 =
3442 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3443 ctx->i32_1, "");
3444
3445 LLVMValueRef word1_is_nonzero =
3446 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3447 fmask_word1, ctx->i32_0, "");
3448
3449 /* Replace the MSAA sample index. */
3450 sample_index =
3451 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3452 final_sample, sample_index, "");
3453 return sample_index;
3454 }
3455
3456 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3457 const nir_intrinsic_instr *instr)
3458 {
3459 const struct glsl_type *type = instr->variables[0]->var->type;
3460 if(instr->variables[0]->deref.child)
3461 type = instr->variables[0]->deref.child->type;
3462
3463 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3464 LLVMValueRef coords[4];
3465 LLVMValueRef masks[] = {
3466 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3467 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3468 };
3469 LLVMValueRef res;
3470 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3471
3472 int count;
3473 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3474 bool is_array = glsl_sampler_type_is_array(type);
3475 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3476 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3477 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3478 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3479 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3480 count = image_type_to_components_count(dim, is_array);
3481
3482 if (is_ms) {
3483 LLVMValueRef fmask_load_address[3];
3484 int chan;
3485
3486 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3487 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3488 if (is_array)
3489 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3490 else
3491 fmask_load_address[2] = NULL;
3492 if (add_frag_pos) {
3493 for (chan = 0; chan < 2; ++chan)
3494 fmask_load_address[chan] =
3495 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3496 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3497 ctx->ac.i32, ""), "");
3498 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3499 }
3500 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3501 fmask_load_address[0],
3502 fmask_load_address[1],
3503 fmask_load_address[2],
3504 sample_index,
3505 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3506 }
3507 if (count == 1 && !gfx9_1d) {
3508 if (instr->src[0].ssa->num_components)
3509 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3510 else
3511 res = src0;
3512 } else {
3513 int chan;
3514 if (is_ms)
3515 count--;
3516 for (chan = 0; chan < count; ++chan) {
3517 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3518 }
3519 if (add_frag_pos) {
3520 for (chan = 0; chan < 2; ++chan)
3521 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3522 ctx->ac.i32, ""), "");
3523 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3524 count++;
3525 }
3526
3527 if (gfx9_1d) {
3528 if (is_array) {
3529 coords[2] = coords[1];
3530 coords[1] = ctx->ac.i32_0;
3531 } else
3532 coords[1] = ctx->ac.i32_0;
3533 count++;
3534 }
3535
3536 if (is_ms) {
3537 coords[count] = sample_index;
3538 count++;
3539 }
3540
3541 if (count == 3) {
3542 coords[3] = LLVMGetUndef(ctx->ac.i32);
3543 count = 4;
3544 }
3545 res = ac_build_gather_values(&ctx->ac, coords, count);
3546 }
3547 return res;
3548 }
3549
3550 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3551 const nir_intrinsic_instr *instr)
3552 {
3553 LLVMValueRef params[7];
3554 LLVMValueRef res;
3555 char intrinsic_name[64];
3556 const nir_variable *var = instr->variables[0]->var;
3557 const struct glsl_type *type = var->type;
3558
3559 if(instr->variables[0]->deref.child)
3560 type = instr->variables[0]->deref.child->type;
3561
3562 type = glsl_without_array(type);
3563 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3564 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3565 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3566 ctx->ac.i32_0, ""); /* vindex */
3567 params[2] = ctx->ac.i32_0; /* voffset */
3568 params[3] = ctx->ac.i1false; /* glc */
3569 params[4] = ctx->ac.i1false; /* slc */
3570 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3571 params, 5, 0);
3572
3573 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3574 res = ac_to_integer(&ctx->ac, res);
3575 } else {
3576 bool is_da = glsl_sampler_type_is_array(type) ||
3577 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3578 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3579 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3580 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3581 LLVMValueRef glc = ctx->ac.i1false;
3582 LLVMValueRef slc = ctx->ac.i1false;
3583
3584 params[0] = get_image_coords(ctx, instr);
3585 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3586 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3587 if (HAVE_LLVM <= 0x0309) {
3588 params[3] = ctx->ac.i1false; /* r128 */
3589 params[4] = da;
3590 params[5] = glc;
3591 params[6] = slc;
3592 } else {
3593 LLVMValueRef lwe = ctx->ac.i1false;
3594 params[3] = glc;
3595 params[4] = slc;
3596 params[5] = lwe;
3597 params[6] = da;
3598 }
3599
3600 ac_get_image_intr_name("llvm.amdgcn.image.load",
3601 ctx->ac.v4f32, /* vdata */
3602 LLVMTypeOf(params[0]), /* coords */
3603 LLVMTypeOf(params[1]), /* rsrc */
3604 intrinsic_name, sizeof(intrinsic_name));
3605
3606 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3607 params, 7, AC_FUNC_ATTR_READONLY);
3608 }
3609 return ac_to_integer(&ctx->ac, res);
3610 }
3611
3612 static void visit_image_store(struct ac_nir_context *ctx,
3613 nir_intrinsic_instr *instr)
3614 {
3615 LLVMValueRef params[8];
3616 char intrinsic_name[64];
3617 const nir_variable *var = instr->variables[0]->var;
3618 const struct glsl_type *type = glsl_without_array(var->type);
3619 LLVMValueRef glc = ctx->ac.i1false;
3620 bool force_glc = ctx->ac.chip_class == SI;
3621 if (force_glc)
3622 glc = ctx->ac.i1true;
3623
3624 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3625 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3626 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3627 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3628 ctx->ac.i32_0, ""); /* vindex */
3629 params[3] = ctx->ac.i32_0; /* voffset */
3630 params[4] = glc; /* glc */
3631 params[5] = ctx->ac.i1false; /* slc */
3632 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3633 params, 6, 0);
3634 } else {
3635 bool is_da = glsl_sampler_type_is_array(type) ||
3636 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3637 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3638 LLVMValueRef slc = ctx->ac.i1false;
3639
3640 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3641 params[1] = get_image_coords(ctx, instr); /* coords */
3642 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3643 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3644 if (HAVE_LLVM <= 0x0309) {
3645 params[4] = ctx->ac.i1false; /* r128 */
3646 params[5] = da;
3647 params[6] = glc;
3648 params[7] = slc;
3649 } else {
3650 LLVMValueRef lwe = ctx->ac.i1false;
3651 params[4] = glc;
3652 params[5] = slc;
3653 params[6] = lwe;
3654 params[7] = da;
3655 }
3656
3657 ac_get_image_intr_name("llvm.amdgcn.image.store",
3658 LLVMTypeOf(params[0]), /* vdata */
3659 LLVMTypeOf(params[1]), /* coords */
3660 LLVMTypeOf(params[2]), /* rsrc */
3661 intrinsic_name, sizeof(intrinsic_name));
3662
3663 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3664 params, 8, 0);
3665 }
3666
3667 }
3668
3669 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3670 const nir_intrinsic_instr *instr)
3671 {
3672 LLVMValueRef params[7];
3673 int param_count = 0;
3674 const nir_variable *var = instr->variables[0]->var;
3675
3676 const char *atomic_name;
3677 char intrinsic_name[41];
3678 const struct glsl_type *type = glsl_without_array(var->type);
3679 MAYBE_UNUSED int length;
3680
3681 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3682
3683 switch (instr->intrinsic) {
3684 case nir_intrinsic_image_atomic_add:
3685 atomic_name = "add";
3686 break;
3687 case nir_intrinsic_image_atomic_min:
3688 atomic_name = is_unsigned ? "umin" : "smin";
3689 break;
3690 case nir_intrinsic_image_atomic_max:
3691 atomic_name = is_unsigned ? "umax" : "smax";
3692 break;
3693 case nir_intrinsic_image_atomic_and:
3694 atomic_name = "and";
3695 break;
3696 case nir_intrinsic_image_atomic_or:
3697 atomic_name = "or";
3698 break;
3699 case nir_intrinsic_image_atomic_xor:
3700 atomic_name = "xor";
3701 break;
3702 case nir_intrinsic_image_atomic_exchange:
3703 atomic_name = "swap";
3704 break;
3705 case nir_intrinsic_image_atomic_comp_swap:
3706 atomic_name = "cmpswap";
3707 break;
3708 default:
3709 abort();
3710 }
3711
3712 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3713 params[param_count++] = get_src(ctx, instr->src[3]);
3714 params[param_count++] = get_src(ctx, instr->src[2]);
3715
3716 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3717 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3718 NULL, true, true);
3719 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3720 ctx->ac.i32_0, ""); /* vindex */
3721 params[param_count++] = ctx->ac.i32_0; /* voffset */
3722 params[param_count++] = ctx->ac.i1false; /* slc */
3723
3724 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3725 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3726 } else {
3727 char coords_type[8];
3728
3729 bool da = glsl_sampler_type_is_array(type) ||
3730 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3731
3732 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3733 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3734 NULL, true, true);
3735 params[param_count++] = ctx->ac.i1false; /* r128 */
3736 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3737 params[param_count++] = ctx->ac.i1false; /* slc */
3738
3739 build_int_type_name(LLVMTypeOf(coords),
3740 coords_type, sizeof(coords_type));
3741
3742 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3743 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3744 }
3745
3746 assert(length < sizeof(intrinsic_name));
3747 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3748 }
3749
3750 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3751 const nir_intrinsic_instr *instr)
3752 {
3753 LLVMValueRef res;
3754 const nir_variable *var = instr->variables[0]->var;
3755 const struct glsl_type *type = instr->variables[0]->var->type;
3756 bool da = glsl_sampler_type_is_array(var->type) ||
3757 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3758 if(instr->variables[0]->deref.child)
3759 type = instr->variables[0]->deref.child->type;
3760
3761 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3762 return get_buffer_size(ctx,
3763 get_sampler_desc(ctx, instr->variables[0],
3764 AC_DESC_BUFFER, NULL, true, false), true);
3765
3766 struct ac_image_args args = { 0 };
3767
3768 args.da = da;
3769 args.dmask = 0xf;
3770 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3771 args.opcode = ac_image_get_resinfo;
3772 args.addr = ctx->ac.i32_0;
3773
3774 res = ac_build_image_opcode(&ctx->ac, &args);
3775
3776 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3777
3778 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3779 glsl_sampler_type_is_array(type)) {
3780 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3781 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3782 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3783 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3784 }
3785 if (ctx->ac.chip_class >= GFX9 &&
3786 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3787 glsl_sampler_type_is_array(type)) {
3788 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3789 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3790 ctx->ac.i32_1, "");
3791
3792 }
3793 return res;
3794 }
3795
3796 #define NOOP_WAITCNT 0xf7f
3797 #define LGKM_CNT 0x07f
3798 #define VM_CNT 0xf70
3799
3800 static void emit_membar(struct nir_to_llvm_context *ctx,
3801 const nir_intrinsic_instr *instr)
3802 {
3803 unsigned waitcnt = NOOP_WAITCNT;
3804
3805 switch (instr->intrinsic) {
3806 case nir_intrinsic_memory_barrier:
3807 case nir_intrinsic_group_memory_barrier:
3808 waitcnt &= VM_CNT & LGKM_CNT;
3809 break;
3810 case nir_intrinsic_memory_barrier_atomic_counter:
3811 case nir_intrinsic_memory_barrier_buffer:
3812 case nir_intrinsic_memory_barrier_image:
3813 waitcnt &= VM_CNT;
3814 break;
3815 case nir_intrinsic_memory_barrier_shared:
3816 waitcnt &= LGKM_CNT;
3817 break;
3818 default:
3819 break;
3820 }
3821 if (waitcnt != NOOP_WAITCNT)
3822 ac_build_waitcnt(&ctx->ac, waitcnt);
3823 }
3824
3825 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3826 {
3827 /* SI only (thanks to a hw bug workaround):
3828 * The real barrier instruction isn’t needed, because an entire patch
3829 * always fits into a single wave.
3830 */
3831 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3832 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3833 return;
3834 }
3835 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3836 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3837 }
3838
3839 static void emit_discard_if(struct ac_nir_context *ctx,
3840 const nir_intrinsic_instr *instr)
3841 {
3842 LLVMValueRef cond;
3843
3844 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3845 get_src(ctx, instr->src[0]),
3846 ctx->ac.i32_0, "");
3847 ac_build_kill_if_false(&ctx->ac, cond);
3848 }
3849
3850 static LLVMValueRef
3851 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3852 {
3853 LLVMValueRef result;
3854 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3855 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3856 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3857
3858 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3859 }
3860
3861 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3862 const nir_intrinsic_instr *instr)
3863 {
3864 LLVMValueRef ptr, result;
3865 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3866 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3867
3868 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3869 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3870 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3871 ptr, src, src1,
3872 LLVMAtomicOrderingSequentiallyConsistent,
3873 LLVMAtomicOrderingSequentiallyConsistent,
3874 false);
3875 } else {
3876 LLVMAtomicRMWBinOp op;
3877 switch (instr->intrinsic) {
3878 case nir_intrinsic_var_atomic_add:
3879 op = LLVMAtomicRMWBinOpAdd;
3880 break;
3881 case nir_intrinsic_var_atomic_umin:
3882 op = LLVMAtomicRMWBinOpUMin;
3883 break;
3884 case nir_intrinsic_var_atomic_umax:
3885 op = LLVMAtomicRMWBinOpUMax;
3886 break;
3887 case nir_intrinsic_var_atomic_imin:
3888 op = LLVMAtomicRMWBinOpMin;
3889 break;
3890 case nir_intrinsic_var_atomic_imax:
3891 op = LLVMAtomicRMWBinOpMax;
3892 break;
3893 case nir_intrinsic_var_atomic_and:
3894 op = LLVMAtomicRMWBinOpAnd;
3895 break;
3896 case nir_intrinsic_var_atomic_or:
3897 op = LLVMAtomicRMWBinOpOr;
3898 break;
3899 case nir_intrinsic_var_atomic_xor:
3900 op = LLVMAtomicRMWBinOpXor;
3901 break;
3902 case nir_intrinsic_var_atomic_exchange:
3903 op = LLVMAtomicRMWBinOpXchg;
3904 break;
3905 default:
3906 return NULL;
3907 }
3908
3909 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3910 LLVMAtomicOrderingSequentiallyConsistent,
3911 false);
3912 }
3913 return result;
3914 }
3915
3916 #define INTERP_CENTER 0
3917 #define INTERP_CENTROID 1
3918 #define INTERP_SAMPLE 2
3919
3920 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3921 enum glsl_interp_mode interp, unsigned location)
3922 {
3923 switch (interp) {
3924 case INTERP_MODE_FLAT:
3925 default:
3926 return NULL;
3927 case INTERP_MODE_SMOOTH:
3928 case INTERP_MODE_NONE:
3929 if (location == INTERP_CENTER)
3930 return ctx->persp_center;
3931 else if (location == INTERP_CENTROID)
3932 return ctx->persp_centroid;
3933 else if (location == INTERP_SAMPLE)
3934 return ctx->persp_sample;
3935 break;
3936 case INTERP_MODE_NOPERSPECTIVE:
3937 if (location == INTERP_CENTER)
3938 return ctx->linear_center;
3939 else if (location == INTERP_CENTROID)
3940 return ctx->linear_centroid;
3941 else if (location == INTERP_SAMPLE)
3942 return ctx->linear_sample;
3943 break;
3944 }
3945 return NULL;
3946 }
3947
3948 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3949 LLVMValueRef sample_id)
3950 {
3951 LLVMValueRef result;
3952 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3953
3954 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3955 const_array(ctx->ac.v2f32, 64), "");
3956
3957 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3958 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3959
3960 return result;
3961 }
3962
3963 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3964 {
3965 LLVMValueRef values[2];
3966
3967 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3968 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3969 return ac_build_gather_values(&ctx->ac, values, 2);
3970 }
3971
3972 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3973 const nir_intrinsic_instr *instr)
3974 {
3975 LLVMValueRef result[4];
3976 LLVMValueRef interp_param, attr_number;
3977 unsigned location;
3978 unsigned chan;
3979 LLVMValueRef src_c0 = NULL;
3980 LLVMValueRef src_c1 = NULL;
3981 LLVMValueRef src0 = NULL;
3982 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3983 switch (instr->intrinsic) {
3984 case nir_intrinsic_interp_var_at_centroid:
3985 location = INTERP_CENTROID;
3986 break;
3987 case nir_intrinsic_interp_var_at_sample:
3988 case nir_intrinsic_interp_var_at_offset:
3989 location = INTERP_CENTER;
3990 src0 = get_src(ctx->nir, instr->src[0]);
3991 break;
3992 default:
3993 break;
3994 }
3995
3996 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3997 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3998 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3999 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4000 LLVMValueRef sample_position;
4001 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4002
4003 /* fetch sample ID */
4004 sample_position = load_sample_position(ctx, src0);
4005
4006 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4007 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4008 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4009 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4010 }
4011 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4012 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4013
4014 if (location == INTERP_CENTER) {
4015 LLVMValueRef ij_out[2];
4016 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4017
4018 /*
4019 * take the I then J parameters, and the DDX/Y for it, and
4020 * calculate the IJ inputs for the interpolator.
4021 * temp1 = ddx * offset/sample.x + I;
4022 * interp_param.I = ddy * offset/sample.y + temp1;
4023 * temp1 = ddx * offset/sample.x + J;
4024 * interp_param.J = ddy * offset/sample.y + temp1;
4025 */
4026 for (unsigned i = 0; i < 2; i++) {
4027 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4028 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4029 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4030 ddxy_out, ix_ll, "");
4031 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4032 ddxy_out, iy_ll, "");
4033 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4034 interp_param, ix_ll, "");
4035 LLVMValueRef temp1, temp2;
4036
4037 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4038 ctx->ac.f32, "");
4039
4040 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4041 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4042
4043 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4044 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4045
4046 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4047 temp2, ctx->ac.i32, "");
4048 }
4049 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4050
4051 }
4052
4053 for (chan = 0; chan < 4; chan++) {
4054 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4055
4056 if (interp_param) {
4057 interp_param = LLVMBuildBitCast(ctx->builder,
4058 interp_param, ctx->ac.v2f32, "");
4059 LLVMValueRef i = LLVMBuildExtractElement(
4060 ctx->builder, interp_param, ctx->ac.i32_0, "");
4061 LLVMValueRef j = LLVMBuildExtractElement(
4062 ctx->builder, interp_param, ctx->ac.i32_1, "");
4063
4064 result[chan] = ac_build_fs_interp(&ctx->ac,
4065 llvm_chan, attr_number,
4066 ctx->prim_mask, i, j);
4067 } else {
4068 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4069 LLVMConstInt(ctx->ac.i32, 2, false),
4070 llvm_chan, attr_number,
4071 ctx->prim_mask);
4072 }
4073 }
4074 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4075 instr->variables[0]->var->data.location_frac);
4076 }
4077
4078 static void
4079 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4080 {
4081 LLVMValueRef gs_next_vertex;
4082 LLVMValueRef can_emit;
4083 int idx;
4084 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4085
4086 /* Write vertex attribute values to GSVS ring */
4087 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4088 ctx->gs_next_vertex,
4089 "");
4090
4091 /* If this thread has already emitted the declared maximum number of
4092 * vertices, kill it: excessive vertex emissions are not supposed to
4093 * have any effect, and GS threads have no externally observable
4094 * effects other than emitting vertices.
4095 */
4096 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4097 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4098 ac_build_kill_if_false(&ctx->ac, can_emit);
4099
4100 /* loop num outputs */
4101 idx = 0;
4102 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4103 LLVMValueRef *out_ptr = &addrs[i * 4];
4104 int length = 4;
4105 int slot = idx;
4106 int slot_inc = 1;
4107
4108 if (!(ctx->output_mask & (1ull << i)))
4109 continue;
4110
4111 if (i == VARYING_SLOT_CLIP_DIST0) {
4112 /* pack clip and cull into a single set of slots */
4113 length = ctx->num_output_clips + ctx->num_output_culls;
4114 if (length > 4)
4115 slot_inc = 2;
4116 }
4117 for (unsigned j = 0; j < length; j++) {
4118 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4119 out_ptr[j], "");
4120 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4121 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4122 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4123
4124 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4125
4126 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4127 out_val, 1,
4128 voffset, ctx->gs2vs_offset, 0,
4129 1, 1, true, true);
4130 }
4131 idx += slot_inc;
4132 }
4133
4134 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4135 ctx->ac.i32_1, "");
4136 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4137
4138 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4139 }
4140
4141 static void
4142 visit_end_primitive(struct nir_to_llvm_context *ctx,
4143 const nir_intrinsic_instr *instr)
4144 {
4145 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4146 }
4147
4148 static LLVMValueRef
4149 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4150 unsigned num_components)
4151 {
4152 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4153
4154 LLVMValueRef coord[4] = {
4155 ctx->tes_u,
4156 ctx->tes_v,
4157 ctx->ac.f32_0,
4158 ctx->ac.f32_0,
4159 };
4160
4161 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4162 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4163 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4164
4165 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4166 return LLVMBuildBitCast(ctx->builder, result, type, "");
4167 }
4168
4169 static void visit_intrinsic(struct ac_nir_context *ctx,
4170 nir_intrinsic_instr *instr)
4171 {
4172 LLVMValueRef result = NULL;
4173
4174 switch (instr->intrinsic) {
4175 case nir_intrinsic_load_work_group_id: {
4176 LLVMValueRef values[3];
4177
4178 for (int i = 0; i < 3; i++) {
4179 values[i] = ctx->nctx->workgroup_ids[i] ?
4180 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4181 }
4182
4183 result = ac_build_gather_values(&ctx->ac, values, 3);
4184 break;
4185 }
4186 case nir_intrinsic_load_base_vertex: {
4187 result = ctx->abi->base_vertex;
4188 break;
4189 }
4190 case nir_intrinsic_load_vertex_id_zero_base: {
4191 result = ctx->abi->vertex_id;
4192 break;
4193 }
4194 case nir_intrinsic_load_local_invocation_id: {
4195 result = ctx->nctx->local_invocation_ids;
4196 break;
4197 }
4198 case nir_intrinsic_load_base_instance:
4199 result = ctx->abi->start_instance;
4200 break;
4201 case nir_intrinsic_load_draw_id:
4202 result = ctx->abi->draw_id;
4203 break;
4204 case nir_intrinsic_load_view_index:
4205 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4206 break;
4207 case nir_intrinsic_load_invocation_id:
4208 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4209 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4210 else
4211 result = ctx->abi->gs_invocation_id;
4212 break;
4213 case nir_intrinsic_load_primitive_id:
4214 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4215 result = ctx->abi->gs_prim_id;
4216 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4217 result = ctx->abi->tcs_patch_id;
4218 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4219 result = ctx->abi->tes_patch_id;
4220 } else
4221 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4222 break;
4223 case nir_intrinsic_load_sample_id:
4224 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4225 break;
4226 case nir_intrinsic_load_sample_pos:
4227 result = load_sample_pos(ctx);
4228 break;
4229 case nir_intrinsic_load_sample_mask_in:
4230 result = ctx->abi->sample_coverage;
4231 break;
4232 case nir_intrinsic_load_frag_coord: {
4233 LLVMValueRef values[4] = {
4234 ctx->abi->frag_pos[0],
4235 ctx->abi->frag_pos[1],
4236 ctx->abi->frag_pos[2],
4237 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4238 };
4239 result = ac_build_gather_values(&ctx->ac, values, 4);
4240 break;
4241 }
4242 case nir_intrinsic_load_front_face:
4243 result = ctx->abi->front_face;
4244 break;
4245 case nir_intrinsic_load_instance_id:
4246 result = ctx->abi->instance_id;
4247 break;
4248 case nir_intrinsic_load_num_work_groups:
4249 result = ctx->nctx->num_work_groups;
4250 break;
4251 case nir_intrinsic_load_local_invocation_index:
4252 result = visit_load_local_invocation_index(ctx->nctx);
4253 break;
4254 case nir_intrinsic_load_push_constant:
4255 result = visit_load_push_constant(ctx->nctx, instr);
4256 break;
4257 case nir_intrinsic_vulkan_resource_index:
4258 result = visit_vulkan_resource_index(ctx->nctx, instr);
4259 break;
4260 case nir_intrinsic_vulkan_resource_reindex:
4261 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4262 break;
4263 case nir_intrinsic_store_ssbo:
4264 visit_store_ssbo(ctx, instr);
4265 break;
4266 case nir_intrinsic_load_ssbo:
4267 result = visit_load_buffer(ctx, instr);
4268 break;
4269 case nir_intrinsic_ssbo_atomic_add:
4270 case nir_intrinsic_ssbo_atomic_imin:
4271 case nir_intrinsic_ssbo_atomic_umin:
4272 case nir_intrinsic_ssbo_atomic_imax:
4273 case nir_intrinsic_ssbo_atomic_umax:
4274 case nir_intrinsic_ssbo_atomic_and:
4275 case nir_intrinsic_ssbo_atomic_or:
4276 case nir_intrinsic_ssbo_atomic_xor:
4277 case nir_intrinsic_ssbo_atomic_exchange:
4278 case nir_intrinsic_ssbo_atomic_comp_swap:
4279 result = visit_atomic_ssbo(ctx, instr);
4280 break;
4281 case nir_intrinsic_load_ubo:
4282 result = visit_load_ubo_buffer(ctx, instr);
4283 break;
4284 case nir_intrinsic_get_buffer_size:
4285 result = visit_get_buffer_size(ctx, instr);
4286 break;
4287 case nir_intrinsic_load_var:
4288 result = visit_load_var(ctx, instr);
4289 break;
4290 case nir_intrinsic_store_var:
4291 visit_store_var(ctx, instr);
4292 break;
4293 case nir_intrinsic_image_load:
4294 result = visit_image_load(ctx, instr);
4295 break;
4296 case nir_intrinsic_image_store:
4297 visit_image_store(ctx, instr);
4298 break;
4299 case nir_intrinsic_image_atomic_add:
4300 case nir_intrinsic_image_atomic_min:
4301 case nir_intrinsic_image_atomic_max:
4302 case nir_intrinsic_image_atomic_and:
4303 case nir_intrinsic_image_atomic_or:
4304 case nir_intrinsic_image_atomic_xor:
4305 case nir_intrinsic_image_atomic_exchange:
4306 case nir_intrinsic_image_atomic_comp_swap:
4307 result = visit_image_atomic(ctx, instr);
4308 break;
4309 case nir_intrinsic_image_size:
4310 result = visit_image_size(ctx, instr);
4311 break;
4312 case nir_intrinsic_discard:
4313 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4314 LLVMVoidTypeInContext(ctx->ac.context),
4315 NULL, 0, AC_FUNC_ATTR_LEGACY);
4316 break;
4317 case nir_intrinsic_discard_if:
4318 emit_discard_if(ctx, instr);
4319 break;
4320 case nir_intrinsic_memory_barrier:
4321 case nir_intrinsic_group_memory_barrier:
4322 case nir_intrinsic_memory_barrier_atomic_counter:
4323 case nir_intrinsic_memory_barrier_buffer:
4324 case nir_intrinsic_memory_barrier_image:
4325 case nir_intrinsic_memory_barrier_shared:
4326 emit_membar(ctx->nctx, instr);
4327 break;
4328 case nir_intrinsic_barrier:
4329 emit_barrier(&ctx->ac, ctx->stage);
4330 break;
4331 case nir_intrinsic_var_atomic_add:
4332 case nir_intrinsic_var_atomic_imin:
4333 case nir_intrinsic_var_atomic_umin:
4334 case nir_intrinsic_var_atomic_imax:
4335 case nir_intrinsic_var_atomic_umax:
4336 case nir_intrinsic_var_atomic_and:
4337 case nir_intrinsic_var_atomic_or:
4338 case nir_intrinsic_var_atomic_xor:
4339 case nir_intrinsic_var_atomic_exchange:
4340 case nir_intrinsic_var_atomic_comp_swap:
4341 result = visit_var_atomic(ctx->nctx, instr);
4342 break;
4343 case nir_intrinsic_interp_var_at_centroid:
4344 case nir_intrinsic_interp_var_at_sample:
4345 case nir_intrinsic_interp_var_at_offset:
4346 result = visit_interp(ctx->nctx, instr);
4347 break;
4348 case nir_intrinsic_emit_vertex:
4349 assert(instr->const_index[0] == 0);
4350 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4351 break;
4352 case nir_intrinsic_end_primitive:
4353 visit_end_primitive(ctx->nctx, instr);
4354 break;
4355 case nir_intrinsic_load_tess_coord: {
4356 LLVMTypeRef type = ctx->nctx ?
4357 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4358 NULL;
4359 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4360 break;
4361 }
4362 case nir_intrinsic_load_tess_level_outer:
4363 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4364 break;
4365 case nir_intrinsic_load_tess_level_inner:
4366 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4367 break;
4368 case nir_intrinsic_load_patch_vertices_in:
4369 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4370 break;
4371 default:
4372 fprintf(stderr, "Unknown intrinsic: ");
4373 nir_print_instr(&instr->instr, stderr);
4374 fprintf(stderr, "\n");
4375 break;
4376 }
4377 if (result) {
4378 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4379 }
4380 }
4381
4382 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4383 LLVMValueRef buffer_ptr, bool write)
4384 {
4385 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4386
4387 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4388 ctx->shader_info->fs.writes_memory = true;
4389
4390 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4391 }
4392
4393 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4394 {
4395 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4396
4397 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4398 }
4399
4400 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4401 unsigned descriptor_set,
4402 unsigned base_index,
4403 unsigned constant_index,
4404 LLVMValueRef index,
4405 enum ac_descriptor_type desc_type,
4406 bool image, bool write)
4407 {
4408 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4409 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4410 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4411 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4412 unsigned offset = binding->offset;
4413 unsigned stride = binding->size;
4414 unsigned type_size;
4415 LLVMBuilderRef builder = ctx->builder;
4416 LLVMTypeRef type;
4417
4418 assert(base_index < layout->binding_count);
4419
4420 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4421 ctx->shader_info->fs.writes_memory = true;
4422
4423 switch (desc_type) {
4424 case AC_DESC_IMAGE:
4425 type = ctx->ac.v8i32;
4426 type_size = 32;
4427 break;
4428 case AC_DESC_FMASK:
4429 type = ctx->ac.v8i32;
4430 offset += 32;
4431 type_size = 32;
4432 break;
4433 case AC_DESC_SAMPLER:
4434 type = ctx->ac.v4i32;
4435 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4436 offset += 64;
4437
4438 type_size = 16;
4439 break;
4440 case AC_DESC_BUFFER:
4441 type = ctx->ac.v4i32;
4442 type_size = 16;
4443 break;
4444 default:
4445 unreachable("invalid desc_type\n");
4446 }
4447
4448 offset += constant_index * stride;
4449
4450 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4451 (!index || binding->immutable_samplers_equal)) {
4452 if (binding->immutable_samplers_equal)
4453 constant_index = 0;
4454
4455 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4456
4457 LLVMValueRef constants[] = {
4458 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4459 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4460 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4461 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4462 };
4463 return ac_build_gather_values(&ctx->ac, constants, 4);
4464 }
4465
4466 assert(stride % type_size == 0);
4467
4468 if (!index)
4469 index = ctx->ac.i32_0;
4470
4471 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4472
4473 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4474 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4475
4476 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4477 }
4478
4479 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4480 const nir_deref_var *deref,
4481 enum ac_descriptor_type desc_type,
4482 const nir_tex_instr *tex_instr,
4483 bool image, bool write)
4484 {
4485 LLVMValueRef index = NULL;
4486 unsigned constant_index = 0;
4487 unsigned descriptor_set;
4488 unsigned base_index;
4489
4490 if (!deref) {
4491 assert(tex_instr && !image);
4492 descriptor_set = 0;
4493 base_index = tex_instr->sampler_index;
4494 } else {
4495 const nir_deref *tail = &deref->deref;
4496 while (tail->child) {
4497 const nir_deref_array *child = nir_deref_as_array(tail->child);
4498 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4499
4500 if (!array_size)
4501 array_size = 1;
4502
4503 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4504
4505 if (child->deref_array_type == nir_deref_array_type_indirect) {
4506 LLVMValueRef indirect = get_src(ctx, child->indirect);
4507
4508 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4509 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4510
4511 if (!index)
4512 index = indirect;
4513 else
4514 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4515 }
4516
4517 constant_index += child->base_offset * array_size;
4518
4519 tail = &child->deref;
4520 }
4521 descriptor_set = deref->var->data.descriptor_set;
4522 base_index = deref->var->data.binding;
4523 }
4524
4525 return ctx->abi->load_sampler_desc(ctx->abi,
4526 descriptor_set,
4527 base_index,
4528 constant_index, index,
4529 desc_type, image, write);
4530 }
4531
4532 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4533 struct ac_image_args *args,
4534 const nir_tex_instr *instr,
4535 nir_texop op,
4536 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4537 LLVMValueRef *param, unsigned count,
4538 unsigned dmask)
4539 {
4540 unsigned is_rect = 0;
4541 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4542
4543 if (op == nir_texop_lod)
4544 da = false;
4545 /* Pad to power of two vector */
4546 while (count < util_next_power_of_two(count))
4547 param[count++] = LLVMGetUndef(ctx->i32);
4548
4549 if (count > 1)
4550 args->addr = ac_build_gather_values(ctx, param, count);
4551 else
4552 args->addr = param[0];
4553
4554 args->resource = res_ptr;
4555 args->sampler = samp_ptr;
4556
4557 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4558 args->addr = param[0];
4559 return;
4560 }
4561
4562 args->dmask = dmask;
4563 args->unorm = is_rect;
4564 args->da = da;
4565 }
4566
4567 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4568 *
4569 * SI-CI:
4570 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4571 * filtering manually. The driver sets img7 to a mask clearing
4572 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4573 * s_and_b32 samp0, samp0, img7
4574 *
4575 * VI:
4576 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4577 */
4578 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4579 LLVMValueRef res, LLVMValueRef samp)
4580 {
4581 LLVMBuilderRef builder = ctx->ac.builder;
4582 LLVMValueRef img7, samp0;
4583
4584 if (ctx->ac.chip_class >= VI)
4585 return samp;
4586
4587 img7 = LLVMBuildExtractElement(builder, res,
4588 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4589 samp0 = LLVMBuildExtractElement(builder, samp,
4590 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4591 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4592 return LLVMBuildInsertElement(builder, samp, samp0,
4593 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4594 }
4595
4596 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4597 nir_tex_instr *instr,
4598 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4599 LLVMValueRef *fmask_ptr)
4600 {
4601 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4602 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4603 else
4604 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4605 if (samp_ptr) {
4606 if (instr->sampler)
4607 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4608 else
4609 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4610 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4611 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4612 }
4613 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4614 instr->op == nir_texop_samples_identical))
4615 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4616 }
4617
4618 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4619 LLVMValueRef coord)
4620 {
4621 coord = ac_to_float(ctx, coord);
4622 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4623 coord = ac_to_integer(ctx, coord);
4624 return coord;
4625 }
4626
4627 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4628 {
4629 LLVMValueRef result = NULL;
4630 struct ac_image_args args = { 0 };
4631 unsigned dmask = 0xf;
4632 LLVMValueRef address[16];
4633 LLVMValueRef coords[5];
4634 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4635 LLVMValueRef bias = NULL, offsets = NULL;
4636 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4637 LLVMValueRef ddx = NULL, ddy = NULL;
4638 LLVMValueRef derivs[6];
4639 unsigned chan, count = 0;
4640 unsigned const_src = 0, num_deriv_comp = 0;
4641 bool lod_is_zero = false;
4642
4643 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4644
4645 for (unsigned i = 0; i < instr->num_srcs; i++) {
4646 switch (instr->src[i].src_type) {
4647 case nir_tex_src_coord:
4648 coord = get_src(ctx, instr->src[i].src);
4649 break;
4650 case nir_tex_src_projector:
4651 break;
4652 case nir_tex_src_comparator:
4653 comparator = get_src(ctx, instr->src[i].src);
4654 break;
4655 case nir_tex_src_offset:
4656 offsets = get_src(ctx, instr->src[i].src);
4657 const_src = i;
4658 break;
4659 case nir_tex_src_bias:
4660 bias = get_src(ctx, instr->src[i].src);
4661 break;
4662 case nir_tex_src_lod: {
4663 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4664
4665 if (val && val->i32[0] == 0)
4666 lod_is_zero = true;
4667 lod = get_src(ctx, instr->src[i].src);
4668 break;
4669 }
4670 case nir_tex_src_ms_index:
4671 sample_index = get_src(ctx, instr->src[i].src);
4672 break;
4673 case nir_tex_src_ms_mcs:
4674 break;
4675 case nir_tex_src_ddx:
4676 ddx = get_src(ctx, instr->src[i].src);
4677 num_deriv_comp = instr->src[i].src.ssa->num_components;
4678 break;
4679 case nir_tex_src_ddy:
4680 ddy = get_src(ctx, instr->src[i].src);
4681 break;
4682 case nir_tex_src_texture_offset:
4683 case nir_tex_src_sampler_offset:
4684 case nir_tex_src_plane:
4685 default:
4686 break;
4687 }
4688 }
4689
4690 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4691 result = get_buffer_size(ctx, res_ptr, true);
4692 goto write_result;
4693 }
4694
4695 if (instr->op == nir_texop_texture_samples) {
4696 LLVMValueRef res, samples, is_msaa;
4697 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4698 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4699 LLVMConstInt(ctx->ac.i32, 3, false), "");
4700 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4701 LLVMConstInt(ctx->ac.i32, 28, false), "");
4702 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4703 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4704 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4705 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4706
4707 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4708 LLVMConstInt(ctx->ac.i32, 16, false), "");
4709 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4710 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4711 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4712 samples, "");
4713 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4714 ctx->ac.i32_1, "");
4715 result = samples;
4716 goto write_result;
4717 }
4718
4719 if (coord)
4720 for (chan = 0; chan < instr->coord_components; chan++)
4721 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4722
4723 if (offsets && instr->op != nir_texop_txf) {
4724 LLVMValueRef offset[3], pack;
4725 for (chan = 0; chan < 3; ++chan)
4726 offset[chan] = ctx->ac.i32_0;
4727
4728 args.offset = true;
4729 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4730 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4731 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4732 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4733 if (chan)
4734 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4735 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4736 }
4737 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4738 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4739 address[count++] = pack;
4740
4741 }
4742 /* pack LOD bias value */
4743 if (instr->op == nir_texop_txb && bias) {
4744 address[count++] = bias;
4745 }
4746
4747 /* Pack depth comparison value */
4748 if (instr->is_shadow && comparator) {
4749 LLVMValueRef z = ac_to_float(&ctx->ac,
4750 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4751
4752 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4753 * so the depth comparison value isn't clamped for Z16 and
4754 * Z24 anymore. Do it manually here.
4755 *
4756 * It's unnecessary if the original texture format was
4757 * Z32_FLOAT, but we don't know that here.
4758 */
4759 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4760 z = ac_build_clamp(&ctx->ac, z);
4761
4762 address[count++] = z;
4763 }
4764
4765 /* pack derivatives */
4766 if (ddx || ddy) {
4767 int num_src_deriv_channels, num_dest_deriv_channels;
4768 switch (instr->sampler_dim) {
4769 case GLSL_SAMPLER_DIM_3D:
4770 case GLSL_SAMPLER_DIM_CUBE:
4771 num_deriv_comp = 3;
4772 num_src_deriv_channels = 3;
4773 num_dest_deriv_channels = 3;
4774 break;
4775 case GLSL_SAMPLER_DIM_2D:
4776 default:
4777 num_src_deriv_channels = 2;
4778 num_dest_deriv_channels = 2;
4779 num_deriv_comp = 2;
4780 break;
4781 case GLSL_SAMPLER_DIM_1D:
4782 num_src_deriv_channels = 1;
4783 if (ctx->ac.chip_class >= GFX9) {
4784 num_dest_deriv_channels = 2;
4785 num_deriv_comp = 2;
4786 } else {
4787 num_dest_deriv_channels = 1;
4788 num_deriv_comp = 1;
4789 }
4790 break;
4791 }
4792
4793 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4794 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4795 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4796 }
4797 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4798 derivs[i] = ctx->ac.f32_0;
4799 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4800 }
4801 }
4802
4803 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4804 for (chan = 0; chan < instr->coord_components; chan++)
4805 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4806 if (instr->coord_components == 3)
4807 coords[3] = LLVMGetUndef(ctx->ac.f32);
4808 ac_prepare_cube_coords(&ctx->ac,
4809 instr->op == nir_texop_txd, instr->is_array,
4810 instr->op == nir_texop_lod, coords, derivs);
4811 if (num_deriv_comp)
4812 num_deriv_comp--;
4813 }
4814
4815 if (ddx || ddy) {
4816 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4817 address[count++] = derivs[i];
4818 }
4819
4820 /* Pack texture coordinates */
4821 if (coord) {
4822 address[count++] = coords[0];
4823 if (instr->coord_components > 1) {
4824 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4825 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4826 }
4827 address[count++] = coords[1];
4828 }
4829 if (instr->coord_components > 2) {
4830 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4831 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4832 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4833 instr->op != nir_texop_txf) {
4834 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4835 }
4836 address[count++] = coords[2];
4837 }
4838
4839 if (ctx->ac.chip_class >= GFX9) {
4840 LLVMValueRef filler;
4841 if (instr->op == nir_texop_txf)
4842 filler = ctx->ac.i32_0;
4843 else
4844 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4845
4846 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4847 /* No nir_texop_lod, because it does not take a slice
4848 * even with array textures. */
4849 if (instr->is_array && instr->op != nir_texop_lod ) {
4850 address[count] = address[count - 1];
4851 address[count - 1] = filler;
4852 count++;
4853 } else
4854 address[count++] = filler;
4855 }
4856 }
4857 }
4858
4859 /* Pack LOD */
4860 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4861 instr->op == nir_texop_txf)) {
4862 address[count++] = lod;
4863 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4864 address[count++] = sample_index;
4865 } else if(instr->op == nir_texop_txs) {
4866 count = 0;
4867 if (lod)
4868 address[count++] = lod;
4869 else
4870 address[count++] = ctx->ac.i32_0;
4871 }
4872
4873 for (chan = 0; chan < count; chan++) {
4874 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4875 address[chan], ctx->ac.i32, "");
4876 }
4877
4878 if (instr->op == nir_texop_samples_identical) {
4879 LLVMValueRef txf_address[4];
4880 struct ac_image_args txf_args = { 0 };
4881 unsigned txf_count = count;
4882 memcpy(txf_address, address, sizeof(txf_address));
4883
4884 if (!instr->is_array)
4885 txf_address[2] = ctx->ac.i32_0;
4886 txf_address[3] = ctx->ac.i32_0;
4887
4888 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4889 fmask_ptr, NULL,
4890 txf_address, txf_count, 0xf);
4891
4892 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4893
4894 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4895 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4896 goto write_result;
4897 }
4898
4899 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4900 instr->op != nir_texop_txs) {
4901 unsigned sample_chan = instr->is_array ? 3 : 2;
4902 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4903 address[0],
4904 address[1],
4905 instr->is_array ? address[2] : NULL,
4906 address[sample_chan],
4907 fmask_ptr);
4908 }
4909
4910 if (offsets && instr->op == nir_texop_txf) {
4911 nir_const_value *const_offset =
4912 nir_src_as_const_value(instr->src[const_src].src);
4913 int num_offsets = instr->src[const_src].src.ssa->num_components;
4914 assert(const_offset);
4915 num_offsets = MIN2(num_offsets, instr->coord_components);
4916 if (num_offsets > 2)
4917 address[2] = LLVMBuildAdd(ctx->ac.builder,
4918 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4919 if (num_offsets > 1)
4920 address[1] = LLVMBuildAdd(ctx->ac.builder,
4921 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4922 address[0] = LLVMBuildAdd(ctx->ac.builder,
4923 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4924
4925 }
4926
4927 /* TODO TG4 support */
4928 if (instr->op == nir_texop_tg4) {
4929 if (instr->is_shadow)
4930 dmask = 1;
4931 else
4932 dmask = 1 << instr->component;
4933 }
4934 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4935 res_ptr, samp_ptr, address, count, dmask);
4936
4937 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4938
4939 if (instr->op == nir_texop_query_levels)
4940 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4941 else if (instr->is_shadow && instr->is_new_style_shadow &&
4942 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4943 instr->op != nir_texop_tg4)
4944 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4945 else if (instr->op == nir_texop_txs &&
4946 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4947 instr->is_array) {
4948 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4949 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4950 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4951 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4952 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4953 } else if (ctx->ac.chip_class >= GFX9 &&
4954 instr->op == nir_texop_txs &&
4955 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4956 instr->is_array) {
4957 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4958 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4959 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4960 ctx->ac.i32_1, "");
4961 } else if (instr->dest.ssa.num_components != 4)
4962 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4963
4964 write_result:
4965 if (result) {
4966 assert(instr->dest.is_ssa);
4967 result = ac_to_integer(&ctx->ac, result);
4968 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4969 }
4970 }
4971
4972
4973 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4974 {
4975 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4976 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4977
4978 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4979 _mesa_hash_table_insert(ctx->phis, instr, result);
4980 }
4981
4982 static void visit_post_phi(struct ac_nir_context *ctx,
4983 nir_phi_instr *instr,
4984 LLVMValueRef llvm_phi)
4985 {
4986 nir_foreach_phi_src(src, instr) {
4987 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4988 LLVMValueRef llvm_src = get_src(ctx, src->src);
4989
4990 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4991 }
4992 }
4993
4994 static void phi_post_pass(struct ac_nir_context *ctx)
4995 {
4996 struct hash_entry *entry;
4997 hash_table_foreach(ctx->phis, entry) {
4998 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4999 (LLVMValueRef)entry->data);
5000 }
5001 }
5002
5003
5004 static void visit_ssa_undef(struct ac_nir_context *ctx,
5005 const nir_ssa_undef_instr *instr)
5006 {
5007 unsigned num_components = instr->def.num_components;
5008 LLVMValueRef undef;
5009
5010 if (num_components == 1)
5011 undef = LLVMGetUndef(ctx->ac.i32);
5012 else {
5013 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5014 }
5015 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5016 }
5017
5018 static void visit_jump(struct ac_nir_context *ctx,
5019 const nir_jump_instr *instr)
5020 {
5021 switch (instr->type) {
5022 case nir_jump_break:
5023 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5024 LLVMClearInsertionPosition(ctx->ac.builder);
5025 break;
5026 case nir_jump_continue:
5027 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5028 LLVMClearInsertionPosition(ctx->ac.builder);
5029 break;
5030 default:
5031 fprintf(stderr, "Unknown NIR jump instr: ");
5032 nir_print_instr(&instr->instr, stderr);
5033 fprintf(stderr, "\n");
5034 abort();
5035 }
5036 }
5037
5038 static void visit_cf_list(struct ac_nir_context *ctx,
5039 struct exec_list *list);
5040
5041 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5042 {
5043 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5044 nir_foreach_instr(instr, block)
5045 {
5046 switch (instr->type) {
5047 case nir_instr_type_alu:
5048 visit_alu(ctx, nir_instr_as_alu(instr));
5049 break;
5050 case nir_instr_type_load_const:
5051 visit_load_const(ctx, nir_instr_as_load_const(instr));
5052 break;
5053 case nir_instr_type_intrinsic:
5054 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5055 break;
5056 case nir_instr_type_tex:
5057 visit_tex(ctx, nir_instr_as_tex(instr));
5058 break;
5059 case nir_instr_type_phi:
5060 visit_phi(ctx, nir_instr_as_phi(instr));
5061 break;
5062 case nir_instr_type_ssa_undef:
5063 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5064 break;
5065 case nir_instr_type_jump:
5066 visit_jump(ctx, nir_instr_as_jump(instr));
5067 break;
5068 default:
5069 fprintf(stderr, "Unknown NIR instr type: ");
5070 nir_print_instr(instr, stderr);
5071 fprintf(stderr, "\n");
5072 abort();
5073 }
5074 }
5075
5076 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5077 }
5078
5079 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5080 {
5081 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5082
5083 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5084 LLVMBasicBlockRef merge_block =
5085 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5086 LLVMBasicBlockRef if_block =
5087 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5088 LLVMBasicBlockRef else_block = merge_block;
5089 if (!exec_list_is_empty(&if_stmt->else_list))
5090 else_block = LLVMAppendBasicBlockInContext(
5091 ctx->ac.context, fn, "");
5092
5093 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5094 ctx->ac.i32_0, "");
5095 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5096
5097 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5098 visit_cf_list(ctx, &if_stmt->then_list);
5099 if (LLVMGetInsertBlock(ctx->ac.builder))
5100 LLVMBuildBr(ctx->ac.builder, merge_block);
5101
5102 if (!exec_list_is_empty(&if_stmt->else_list)) {
5103 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5104 visit_cf_list(ctx, &if_stmt->else_list);
5105 if (LLVMGetInsertBlock(ctx->ac.builder))
5106 LLVMBuildBr(ctx->ac.builder, merge_block);
5107 }
5108
5109 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5110 }
5111
5112 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5113 {
5114 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5115 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5116 LLVMBasicBlockRef break_parent = ctx->break_block;
5117
5118 ctx->continue_block =
5119 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5120 ctx->break_block =
5121 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5122
5123 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5124 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5125 visit_cf_list(ctx, &loop->body);
5126
5127 if (LLVMGetInsertBlock(ctx->ac.builder))
5128 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5129 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5130
5131 ctx->continue_block = continue_parent;
5132 ctx->break_block = break_parent;
5133 }
5134
5135 static void visit_cf_list(struct ac_nir_context *ctx,
5136 struct exec_list *list)
5137 {
5138 foreach_list_typed(nir_cf_node, node, node, list)
5139 {
5140 switch (node->type) {
5141 case nir_cf_node_block:
5142 visit_block(ctx, nir_cf_node_as_block(node));
5143 break;
5144
5145 case nir_cf_node_if:
5146 visit_if(ctx, nir_cf_node_as_if(node));
5147 break;
5148
5149 case nir_cf_node_loop:
5150 visit_loop(ctx, nir_cf_node_as_loop(node));
5151 break;
5152
5153 default:
5154 assert(0);
5155 }
5156 }
5157 }
5158
5159 static void
5160 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5161 struct nir_variable *variable)
5162 {
5163 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5164 LLVMValueRef t_offset;
5165 LLVMValueRef t_list;
5166 LLVMValueRef input;
5167 LLVMValueRef buffer_index;
5168 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5169 int idx = variable->data.location;
5170 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5171
5172 variable->data.driver_location = idx * 4;
5173
5174 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5175 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5176 ctx->abi.start_instance, "");
5177 if (ctx->options->key.vs.as_ls) {
5178 ctx->shader_info->vs.vgpr_comp_cnt =
5179 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5180 } else {
5181 ctx->shader_info->vs.vgpr_comp_cnt =
5182 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5183 }
5184 } else
5185 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5186 ctx->abi.base_vertex, "");
5187
5188 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5189 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5190
5191 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5192
5193 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5194 buffer_index,
5195 ctx->ac.i32_0,
5196 true);
5197
5198 for (unsigned chan = 0; chan < 4; chan++) {
5199 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5200 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5201 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5202 input, llvm_chan, ""));
5203 }
5204 }
5205 }
5206
5207 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5208 unsigned attr,
5209 LLVMValueRef interp_param,
5210 LLVMValueRef prim_mask,
5211 LLVMValueRef result[4])
5212 {
5213 LLVMValueRef attr_number;
5214 unsigned chan;
5215 LLVMValueRef i, j;
5216 bool interp = interp_param != NULL;
5217
5218 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5219
5220 /* fs.constant returns the param from the middle vertex, so it's not
5221 * really useful for flat shading. It's meant to be used for custom
5222 * interpolation (but the intrinsic can't fetch from the other two
5223 * vertices).
5224 *
5225 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5226 * to do the right thing. The only reason we use fs.constant is that
5227 * fs.interp cannot be used on integers, because they can be equal
5228 * to NaN.
5229 */
5230 if (interp) {
5231 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5232 ctx->ac.v2f32, "");
5233
5234 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5235 ctx->ac.i32_0, "");
5236 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5237 ctx->ac.i32_1, "");
5238 }
5239
5240 for (chan = 0; chan < 4; chan++) {
5241 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5242
5243 if (interp) {
5244 result[chan] = ac_build_fs_interp(&ctx->ac,
5245 llvm_chan,
5246 attr_number,
5247 prim_mask, i, j);
5248 } else {
5249 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5250 LLVMConstInt(ctx->ac.i32, 2, false),
5251 llvm_chan,
5252 attr_number,
5253 prim_mask);
5254 }
5255 }
5256 }
5257
5258 static void
5259 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5260 struct nir_variable *variable)
5261 {
5262 int idx = variable->data.location;
5263 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5264 LLVMValueRef interp;
5265
5266 variable->data.driver_location = idx * 4;
5267 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5268
5269 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5270 unsigned interp_type;
5271 if (variable->data.sample) {
5272 interp_type = INTERP_SAMPLE;
5273 ctx->shader_info->info.ps.force_persample = true;
5274 } else if (variable->data.centroid)
5275 interp_type = INTERP_CENTROID;
5276 else
5277 interp_type = INTERP_CENTER;
5278
5279 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5280 } else
5281 interp = NULL;
5282
5283 for (unsigned i = 0; i < attrib_count; ++i)
5284 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5285
5286 }
5287
5288 static void
5289 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5290 struct nir_shader *nir) {
5291 nir_foreach_variable(variable, &nir->inputs)
5292 handle_vs_input_decl(ctx, variable);
5293 }
5294
5295 static void
5296 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5297 struct nir_shader *nir)
5298 {
5299 if (!ctx->options->key.fs.multisample)
5300 return;
5301
5302 bool uses_center = false;
5303 bool uses_centroid = false;
5304 nir_foreach_variable(variable, &nir->inputs) {
5305 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5306 variable->data.sample)
5307 continue;
5308
5309 if (variable->data.centroid)
5310 uses_centroid = true;
5311 else
5312 uses_center = true;
5313 }
5314
5315 if (uses_center && uses_centroid) {
5316 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5317 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5318 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5319 }
5320 }
5321
5322 static void
5323 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5324 struct nir_shader *nir)
5325 {
5326 prepare_interp_optimize(ctx, nir);
5327
5328 nir_foreach_variable(variable, &nir->inputs)
5329 handle_fs_input_decl(ctx, variable);
5330
5331 unsigned index = 0;
5332
5333 if (ctx->shader_info->info.ps.uses_input_attachments ||
5334 ctx->shader_info->info.needs_multiview_view_index)
5335 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5336
5337 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5338 LLVMValueRef interp_param;
5339 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5340
5341 if (!(ctx->input_mask & (1ull << i)))
5342 continue;
5343
5344 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5345 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5346 interp_param = *inputs;
5347 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5348 inputs);
5349
5350 if (!interp_param)
5351 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5352 ++index;
5353 } else if (i == VARYING_SLOT_POS) {
5354 for(int i = 0; i < 3; ++i)
5355 inputs[i] = ctx->abi.frag_pos[i];
5356
5357 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5358 ctx->abi.frag_pos[3]);
5359 }
5360 }
5361 ctx->shader_info->fs.num_interp = index;
5362 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5363 ctx->shader_info->fs.has_pcoord = true;
5364 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5365 ctx->shader_info->fs.prim_id_input = true;
5366 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5367 ctx->shader_info->fs.layer_input = true;
5368 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5369
5370 if (ctx->shader_info->info.needs_multiview_view_index)
5371 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5372 }
5373
5374 static LLVMValueRef
5375 ac_build_alloca(struct ac_llvm_context *ac,
5376 LLVMTypeRef type,
5377 const char *name)
5378 {
5379 LLVMBuilderRef builder = ac->builder;
5380 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5381 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5382 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5383 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5384 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5385 LLVMValueRef res;
5386
5387 if (first_instr) {
5388 LLVMPositionBuilderBefore(first_builder, first_instr);
5389 } else {
5390 LLVMPositionBuilderAtEnd(first_builder, first_block);
5391 }
5392
5393 res = LLVMBuildAlloca(first_builder, type, name);
5394 LLVMBuildStore(builder, LLVMConstNull(type), res);
5395
5396 LLVMDisposeBuilder(first_builder);
5397
5398 return res;
5399 }
5400
5401 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5402 LLVMTypeRef type,
5403 const char *name)
5404 {
5405 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5406 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5407 return ptr;
5408 }
5409
5410 static void
5411 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5412 struct nir_variable *variable,
5413 struct nir_shader *shader,
5414 gl_shader_stage stage)
5415 {
5416 int idx = variable->data.location + variable->data.index;
5417 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5418 uint64_t mask_attribs;
5419
5420 variable->data.driver_location = idx * 4;
5421
5422 /* tess ctrl has it's own load/store paths for outputs */
5423 if (stage == MESA_SHADER_TESS_CTRL)
5424 return;
5425
5426 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5427 if (stage == MESA_SHADER_VERTEX ||
5428 stage == MESA_SHADER_TESS_EVAL ||
5429 stage == MESA_SHADER_GEOMETRY) {
5430 if (idx == VARYING_SLOT_CLIP_DIST0) {
5431 int length = shader->info.clip_distance_array_size +
5432 shader->info.cull_distance_array_size;
5433 if (stage == MESA_SHADER_VERTEX) {
5434 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5435 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5436 }
5437 if (stage == MESA_SHADER_TESS_EVAL) {
5438 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5439 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5440 }
5441
5442 if (length > 4)
5443 attrib_count = 2;
5444 else
5445 attrib_count = 1;
5446 mask_attribs = 1ull << idx;
5447 }
5448 }
5449
5450 ctx->output_mask |= mask_attribs;
5451 }
5452
5453 static void
5454 handle_shader_output_decl(struct ac_nir_context *ctx,
5455 struct nir_shader *nir,
5456 struct nir_variable *variable)
5457 {
5458 unsigned output_loc = variable->data.driver_location / 4;
5459 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5460
5461 /* tess ctrl has it's own load/store paths for outputs */
5462 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5463 return;
5464
5465 if (ctx->stage == MESA_SHADER_VERTEX ||
5466 ctx->stage == MESA_SHADER_TESS_EVAL ||
5467 ctx->stage == MESA_SHADER_GEOMETRY) {
5468 int idx = variable->data.location + variable->data.index;
5469 if (idx == VARYING_SLOT_CLIP_DIST0) {
5470 int length = nir->info.clip_distance_array_size +
5471 nir->info.cull_distance_array_size;
5472
5473 if (length > 4)
5474 attrib_count = 2;
5475 else
5476 attrib_count = 1;
5477 }
5478 }
5479
5480 for (unsigned i = 0; i < attrib_count; ++i) {
5481 for (unsigned chan = 0; chan < 4; chan++) {
5482 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5483 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5484 }
5485 }
5486 }
5487
5488 static LLVMTypeRef
5489 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5490 enum glsl_base_type type)
5491 {
5492 switch (type) {
5493 case GLSL_TYPE_INT:
5494 case GLSL_TYPE_UINT:
5495 case GLSL_TYPE_BOOL:
5496 case GLSL_TYPE_SUBROUTINE:
5497 return ctx->ac.i32;
5498 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5499 return ctx->ac.f32;
5500 case GLSL_TYPE_INT64:
5501 case GLSL_TYPE_UINT64:
5502 return ctx->ac.i64;
5503 case GLSL_TYPE_DOUBLE:
5504 return ctx->ac.f64;
5505 default:
5506 unreachable("unknown GLSL type");
5507 }
5508 }
5509
5510 static LLVMTypeRef
5511 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5512 const struct glsl_type *type)
5513 {
5514 if (glsl_type_is_scalar(type)) {
5515 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5516 }
5517
5518 if (glsl_type_is_vector(type)) {
5519 return LLVMVectorType(
5520 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5521 glsl_get_vector_elements(type));
5522 }
5523
5524 if (glsl_type_is_matrix(type)) {
5525 return LLVMArrayType(
5526 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5527 glsl_get_matrix_columns(type));
5528 }
5529
5530 if (glsl_type_is_array(type)) {
5531 return LLVMArrayType(
5532 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5533 glsl_get_length(type));
5534 }
5535
5536 assert(glsl_type_is_struct(type));
5537
5538 LLVMTypeRef member_types[glsl_get_length(type)];
5539
5540 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5541 member_types[i] =
5542 glsl_to_llvm_type(ctx,
5543 glsl_get_struct_field(type, i));
5544 }
5545
5546 return LLVMStructTypeInContext(ctx->context, member_types,
5547 glsl_get_length(type), false);
5548 }
5549
5550 static void
5551 setup_locals(struct ac_nir_context *ctx,
5552 struct nir_function *func)
5553 {
5554 int i, j;
5555 ctx->num_locals = 0;
5556 nir_foreach_variable(variable, &func->impl->locals) {
5557 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5558 variable->data.driver_location = ctx->num_locals * 4;
5559 variable->data.location_frac = 0;
5560 ctx->num_locals += attrib_count;
5561 }
5562 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5563 if (!ctx->locals)
5564 return;
5565
5566 for (i = 0; i < ctx->num_locals; i++) {
5567 for (j = 0; j < 4; j++) {
5568 ctx->locals[i * 4 + j] =
5569 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5570 }
5571 }
5572 }
5573
5574 static void
5575 setup_shared(struct ac_nir_context *ctx,
5576 struct nir_shader *nir)
5577 {
5578 nir_foreach_variable(variable, &nir->shared) {
5579 LLVMValueRef shared =
5580 LLVMAddGlobalInAddressSpace(
5581 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5582 variable->name ? variable->name : "",
5583 LOCAL_ADDR_SPACE);
5584 _mesa_hash_table_insert(ctx->vars, variable, shared);
5585 }
5586 }
5587
5588 static LLVMValueRef
5589 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5590 {
5591 v = ac_to_float(ctx, v);
5592 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5593 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5594 }
5595
5596
5597 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5598 LLVMValueRef src0, LLVMValueRef src1)
5599 {
5600 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5601 LLVMValueRef comp[2];
5602
5603 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5604 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5605 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5606 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5607 }
5608
5609 /* Initialize arguments for the shader export intrinsic */
5610 static void
5611 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5612 LLVMValueRef *values,
5613 unsigned target,
5614 struct ac_export_args *args)
5615 {
5616 /* Default is 0xf. Adjusted below depending on the format. */
5617 args->enabled_channels = 0xf;
5618
5619 /* Specify whether the EXEC mask represents the valid mask */
5620 args->valid_mask = 0;
5621
5622 /* Specify whether this is the last export */
5623 args->done = 0;
5624
5625 /* Specify the target we are exporting */
5626 args->target = target;
5627
5628 args->compr = false;
5629 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5630 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5631 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5632 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5633
5634 if (!values)
5635 return;
5636
5637 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5638 LLVMValueRef val[4];
5639 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5640 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5641 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5642 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5643
5644 switch(col_format) {
5645 case V_028714_SPI_SHADER_ZERO:
5646 args->enabled_channels = 0; /* writemask */
5647 args->target = V_008DFC_SQ_EXP_NULL;
5648 break;
5649
5650 case V_028714_SPI_SHADER_32_R:
5651 args->enabled_channels = 1;
5652 args->out[0] = values[0];
5653 break;
5654
5655 case V_028714_SPI_SHADER_32_GR:
5656 args->enabled_channels = 0x3;
5657 args->out[0] = values[0];
5658 args->out[1] = values[1];
5659 break;
5660
5661 case V_028714_SPI_SHADER_32_AR:
5662 args->enabled_channels = 0x9;
5663 args->out[0] = values[0];
5664 args->out[3] = values[3];
5665 break;
5666
5667 case V_028714_SPI_SHADER_FP16_ABGR:
5668 args->compr = 1;
5669
5670 for (unsigned chan = 0; chan < 2; chan++) {
5671 LLVMValueRef pack_args[2] = {
5672 values[2 * chan],
5673 values[2 * chan + 1]
5674 };
5675 LLVMValueRef packed;
5676
5677 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5678 args->out[chan] = packed;
5679 }
5680 break;
5681
5682 case V_028714_SPI_SHADER_UNORM16_ABGR:
5683 for (unsigned chan = 0; chan < 4; chan++) {
5684 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5685 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5686 LLVMConstReal(ctx->ac.f32, 65535), "");
5687 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5688 LLVMConstReal(ctx->ac.f32, 0.5), "");
5689 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5690 ctx->ac.i32, "");
5691 }
5692
5693 args->compr = 1;
5694 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5695 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5696 break;
5697
5698 case V_028714_SPI_SHADER_SNORM16_ABGR:
5699 for (unsigned chan = 0; chan < 4; chan++) {
5700 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5701 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5702 LLVMConstReal(ctx->ac.f32, 32767), "");
5703
5704 /* If positive, add 0.5, else add -0.5. */
5705 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5706 LLVMBuildSelect(ctx->builder,
5707 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5708 val[chan], ctx->ac.f32_0, ""),
5709 LLVMConstReal(ctx->ac.f32, 0.5),
5710 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5711 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5712 }
5713
5714 args->compr = 1;
5715 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5716 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5717 break;
5718
5719 case V_028714_SPI_SHADER_UINT16_ABGR: {
5720 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5721 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5722 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5723
5724 for (unsigned chan = 0; chan < 4; chan++) {
5725 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5726 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5727 }
5728
5729 args->compr = 1;
5730 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5731 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5732 break;
5733 }
5734
5735 case V_028714_SPI_SHADER_SINT16_ABGR: {
5736 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5737 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5738 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5739 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5740 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5741 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5742
5743 /* Clamp. */
5744 for (unsigned chan = 0; chan < 4; chan++) {
5745 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5746 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5747 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5748 }
5749
5750 args->compr = 1;
5751 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5752 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5753 break;
5754 }
5755
5756 default:
5757 case V_028714_SPI_SHADER_32_ABGR:
5758 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5759 break;
5760 }
5761 } else
5762 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5763
5764 for (unsigned i = 0; i < 4; ++i)
5765 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5766 }
5767
5768 static void
5769 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5770 bool export_prim_id,
5771 struct ac_vs_output_info *outinfo)
5772 {
5773 uint32_t param_count = 0;
5774 unsigned target;
5775 unsigned pos_idx, num_pos_exports = 0;
5776 struct ac_export_args args, pos_args[4] = {};
5777 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5778 int i;
5779
5780 if (ctx->options->key.has_multiview_view_index) {
5781 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5782 if(!*tmp_out) {
5783 for(unsigned i = 0; i < 4; ++i)
5784 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5785 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5786 }
5787
5788 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5789 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5790 }
5791
5792 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5793 sizeof(outinfo->vs_output_param_offset));
5794
5795 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5796 LLVMValueRef slots[8];
5797 unsigned j;
5798
5799 if (outinfo->cull_dist_mask)
5800 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5801
5802 i = VARYING_SLOT_CLIP_DIST0;
5803 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5804 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5805 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5806
5807 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5808 slots[i] = LLVMGetUndef(ctx->ac.f32);
5809
5810 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5811 target = V_008DFC_SQ_EXP_POS + 3;
5812 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5813 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5814 &args, sizeof(args));
5815 }
5816
5817 target = V_008DFC_SQ_EXP_POS + 2;
5818 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5819 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5820 &args, sizeof(args));
5821
5822 }
5823
5824 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5825 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5826 for (unsigned j = 0; j < 4; j++)
5827 pos_values[j] = LLVMBuildLoad(ctx->builder,
5828 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5829 }
5830 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5831
5832 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5833 outinfo->writes_pointsize = true;
5834 psize_value = LLVMBuildLoad(ctx->builder,
5835 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5836 }
5837
5838 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5839 outinfo->writes_layer = true;
5840 layer_value = LLVMBuildLoad(ctx->builder,
5841 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5842 }
5843
5844 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5845 outinfo->writes_viewport_index = true;
5846 viewport_index_value = LLVMBuildLoad(ctx->builder,
5847 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5848 }
5849
5850 if (outinfo->writes_pointsize ||
5851 outinfo->writes_layer ||
5852 outinfo->writes_viewport_index) {
5853 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5854 (outinfo->writes_layer == true ? 4 : 0));
5855 pos_args[1].valid_mask = 0;
5856 pos_args[1].done = 0;
5857 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5858 pos_args[1].compr = 0;
5859 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5860 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5861 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5862 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5863
5864 if (outinfo->writes_pointsize == true)
5865 pos_args[1].out[0] = psize_value;
5866 if (outinfo->writes_layer == true)
5867 pos_args[1].out[2] = layer_value;
5868 if (outinfo->writes_viewport_index == true) {
5869 if (ctx->options->chip_class >= GFX9) {
5870 /* GFX9 has the layer in out.z[10:0] and the viewport
5871 * index in out.z[19:16].
5872 */
5873 LLVMValueRef v = viewport_index_value;
5874 v = ac_to_integer(&ctx->ac, v);
5875 v = LLVMBuildShl(ctx->builder, v,
5876 LLVMConstInt(ctx->ac.i32, 16, false),
5877 "");
5878 v = LLVMBuildOr(ctx->builder, v,
5879 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5880
5881 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5882 pos_args[1].enabled_channels |= 1 << 2;
5883 } else {
5884 pos_args[1].out[3] = viewport_index_value;
5885 pos_args[1].enabled_channels |= 1 << 3;
5886 }
5887 }
5888 }
5889 for (i = 0; i < 4; i++) {
5890 if (pos_args[i].out[0])
5891 num_pos_exports++;
5892 }
5893
5894 pos_idx = 0;
5895 for (i = 0; i < 4; i++) {
5896 if (!pos_args[i].out[0])
5897 continue;
5898
5899 /* Specify the target we are exporting */
5900 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5901 if (pos_idx == num_pos_exports)
5902 pos_args[i].done = 1;
5903 ac_build_export(&ctx->ac, &pos_args[i]);
5904 }
5905
5906 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5907 LLVMValueRef values[4];
5908 if (!(ctx->output_mask & (1ull << i)))
5909 continue;
5910
5911 for (unsigned j = 0; j < 4; j++)
5912 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5913 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5914
5915 if (i == VARYING_SLOT_LAYER) {
5916 target = V_008DFC_SQ_EXP_PARAM + param_count;
5917 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5918 param_count++;
5919 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5920 target = V_008DFC_SQ_EXP_PARAM + param_count;
5921 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5922 param_count++;
5923 } else if (i >= VARYING_SLOT_VAR0) {
5924 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5925 target = V_008DFC_SQ_EXP_PARAM + param_count;
5926 outinfo->vs_output_param_offset[i] = param_count;
5927 param_count++;
5928 } else
5929 continue;
5930
5931 si_llvm_init_export_args(ctx, values, target, &args);
5932
5933 if (target >= V_008DFC_SQ_EXP_POS &&
5934 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5935 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5936 &args, sizeof(args));
5937 } else {
5938 ac_build_export(&ctx->ac, &args);
5939 }
5940 }
5941
5942 if (export_prim_id) {
5943 LLVMValueRef values[4];
5944 target = V_008DFC_SQ_EXP_PARAM + param_count;
5945 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5946 param_count++;
5947
5948 values[0] = ctx->vs_prim_id;
5949 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5950 ctx->shader_info->vs.vgpr_comp_cnt);
5951 for (unsigned j = 1; j < 4; j++)
5952 values[j] = ctx->ac.f32_0;
5953 si_llvm_init_export_args(ctx, values, target, &args);
5954 ac_build_export(&ctx->ac, &args);
5955 outinfo->export_prim_id = true;
5956 }
5957
5958 outinfo->pos_exports = num_pos_exports;
5959 outinfo->param_exports = param_count;
5960 }
5961
5962 static void
5963 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5964 struct ac_es_output_info *outinfo)
5965 {
5966 int j;
5967 uint64_t max_output_written = 0;
5968 LLVMValueRef lds_base = NULL;
5969
5970 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5971 int param_index;
5972 int length = 4;
5973
5974 if (!(ctx->output_mask & (1ull << i)))
5975 continue;
5976
5977 if (i == VARYING_SLOT_CLIP_DIST0)
5978 length = ctx->num_output_clips + ctx->num_output_culls;
5979
5980 param_index = shader_io_get_unique_index(i);
5981
5982 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5983 }
5984
5985 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5986
5987 if (ctx->ac.chip_class >= GFX9) {
5988 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5989 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5990 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5991 LLVMConstInt(ctx->ac.i32, 24, false),
5992 LLVMConstInt(ctx->ac.i32, 4, false), false);
5993 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5994 LLVMBuildMul(ctx->ac.builder, wave_idx,
5995 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5996 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5997 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5998 }
5999
6000 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6001 LLVMValueRef dw_addr;
6002 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6003 int param_index;
6004 int length = 4;
6005
6006 if (!(ctx->output_mask & (1ull << i)))
6007 continue;
6008
6009 if (i == VARYING_SLOT_CLIP_DIST0)
6010 length = ctx->num_output_clips + ctx->num_output_culls;
6011
6012 param_index = shader_io_get_unique_index(i);
6013
6014 if (lds_base) {
6015 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6016 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6017 "");
6018 }
6019 for (j = 0; j < length; j++) {
6020 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6021 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6022
6023 if (ctx->ac.chip_class >= GFX9) {
6024 ac_lds_store(&ctx->ac, dw_addr,
6025 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6026 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6027 } else {
6028 ac_build_buffer_store_dword(&ctx->ac,
6029 ctx->esgs_ring,
6030 out_val, 1,
6031 NULL, ctx->es2gs_offset,
6032 (4 * param_index + j) * 4,
6033 1, 1, true, true);
6034 }
6035 }
6036 }
6037 }
6038
6039 static void
6040 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6041 {
6042 LLVMValueRef vertex_id = ctx->rel_auto_id;
6043 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6044 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6045 vertex_dw_stride, "");
6046
6047 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6048 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6049 int length = 4;
6050
6051 if (!(ctx->output_mask & (1ull << i)))
6052 continue;
6053
6054 if (i == VARYING_SLOT_CLIP_DIST0)
6055 length = ctx->num_output_clips + ctx->num_output_culls;
6056 int param = shader_io_get_unique_index(i);
6057 mark_tess_output(ctx, false, param);
6058 if (length > 4)
6059 mark_tess_output(ctx, false, param + 1);
6060 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6061 LLVMConstInt(ctx->ac.i32, param * 4, false),
6062 "");
6063 for (unsigned j = 0; j < length; j++) {
6064 ac_lds_store(&ctx->ac, dw_addr,
6065 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6066 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6067 }
6068 }
6069 }
6070
6071 struct ac_build_if_state
6072 {
6073 struct nir_to_llvm_context *ctx;
6074 LLVMValueRef condition;
6075 LLVMBasicBlockRef entry_block;
6076 LLVMBasicBlockRef true_block;
6077 LLVMBasicBlockRef false_block;
6078 LLVMBasicBlockRef merge_block;
6079 };
6080
6081 static LLVMBasicBlockRef
6082 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6083 {
6084 LLVMBasicBlockRef current_block;
6085 LLVMBasicBlockRef next_block;
6086 LLVMBasicBlockRef new_block;
6087
6088 /* get current basic block */
6089 current_block = LLVMGetInsertBlock(ctx->builder);
6090
6091 /* chqeck if there's another block after this one */
6092 next_block = LLVMGetNextBasicBlock(current_block);
6093 if (next_block) {
6094 /* insert the new block before the next block */
6095 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6096 }
6097 else {
6098 /* append new block after current block */
6099 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6100 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6101 }
6102 return new_block;
6103 }
6104
6105 static void
6106 ac_nir_build_if(struct ac_build_if_state *ifthen,
6107 struct nir_to_llvm_context *ctx,
6108 LLVMValueRef condition)
6109 {
6110 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6111
6112 memset(ifthen, 0, sizeof *ifthen);
6113 ifthen->ctx = ctx;
6114 ifthen->condition = condition;
6115 ifthen->entry_block = block;
6116
6117 /* create endif/merge basic block for the phi functions */
6118 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6119
6120 /* create/insert true_block before merge_block */
6121 ifthen->true_block =
6122 LLVMInsertBasicBlockInContext(ctx->context,
6123 ifthen->merge_block,
6124 "if-true-block");
6125
6126 /* successive code goes into the true block */
6127 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6128 }
6129
6130 /**
6131 * End a conditional.
6132 */
6133 static void
6134 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6135 {
6136 LLVMBuilderRef builder = ifthen->ctx->builder;
6137
6138 /* Insert branch to the merge block from current block */
6139 LLVMBuildBr(builder, ifthen->merge_block);
6140
6141 /*
6142 * Now patch in the various branch instructions.
6143 */
6144
6145 /* Insert the conditional branch instruction at the end of entry_block */
6146 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6147 if (ifthen->false_block) {
6148 /* we have an else clause */
6149 LLVMBuildCondBr(builder, ifthen->condition,
6150 ifthen->true_block, ifthen->false_block);
6151 }
6152 else {
6153 /* no else clause */
6154 LLVMBuildCondBr(builder, ifthen->condition,
6155 ifthen->true_block, ifthen->merge_block);
6156 }
6157
6158 /* Resume building code at end of the ifthen->merge_block */
6159 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6160 }
6161
6162 static void
6163 write_tess_factors(struct nir_to_llvm_context *ctx)
6164 {
6165 unsigned stride, outer_comps, inner_comps;
6166 struct ac_build_if_state if_ctx, inner_if_ctx;
6167 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6168 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6169 unsigned tess_inner_index, tess_outer_index;
6170 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6171 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6172 int i;
6173 emit_barrier(&ctx->ac, ctx->stage);
6174
6175 switch (ctx->options->key.tcs.primitive_mode) {
6176 case GL_ISOLINES:
6177 stride = 2;
6178 outer_comps = 2;
6179 inner_comps = 0;
6180 break;
6181 case GL_TRIANGLES:
6182 stride = 4;
6183 outer_comps = 3;
6184 inner_comps = 1;
6185 break;
6186 case GL_QUADS:
6187 stride = 6;
6188 outer_comps = 4;
6189 inner_comps = 2;
6190 break;
6191 default:
6192 return;
6193 }
6194
6195 ac_nir_build_if(&if_ctx, ctx,
6196 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6197 invocation_id, ctx->ac.i32_0, ""));
6198
6199 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6200 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6201
6202 mark_tess_output(ctx, true, tess_inner_index);
6203 mark_tess_output(ctx, true, tess_outer_index);
6204 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6205 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6206 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6207 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6208 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6209
6210 for (i = 0; i < 4; i++) {
6211 inner[i] = LLVMGetUndef(ctx->ac.i32);
6212 outer[i] = LLVMGetUndef(ctx->ac.i32);
6213 }
6214
6215 // LINES reverseal
6216 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6217 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6218 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6219 ctx->ac.i32_1, "");
6220 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6221 } else {
6222 for (i = 0; i < outer_comps; i++) {
6223 outer[i] = out[i] =
6224 ac_lds_load(&ctx->ac, lds_outer);
6225 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6226 ctx->ac.i32_1, "");
6227 }
6228 for (i = 0; i < inner_comps; i++) {
6229 inner[i] = out[outer_comps+i] =
6230 ac_lds_load(&ctx->ac, lds_inner);
6231 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6232 ctx->ac.i32_1, "");
6233 }
6234 }
6235
6236 /* Convert the outputs to vectors for stores. */
6237 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6238 vec1 = NULL;
6239
6240 if (stride > 4)
6241 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6242
6243
6244 buffer = ctx->hs_ring_tess_factor;
6245 tf_base = ctx->tess_factor_offset;
6246 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6247 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6248 unsigned tf_offset = 0;
6249
6250 if (ctx->options->chip_class <= VI) {
6251 ac_nir_build_if(&inner_if_ctx, ctx,
6252 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6253 rel_patch_id, ctx->ac.i32_0, ""));
6254
6255 /* Store the dynamic HS control word. */
6256 ac_build_buffer_store_dword(&ctx->ac, buffer,
6257 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6258 1, ctx->ac.i32_0, tf_base,
6259 0, 1, 0, true, false);
6260 tf_offset += 4;
6261
6262 ac_nir_build_endif(&inner_if_ctx);
6263 }
6264
6265 /* Store the tessellation factors. */
6266 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6267 MIN2(stride, 4), byteoffset, tf_base,
6268 tf_offset, 1, 0, true, false);
6269 if (vec1)
6270 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6271 stride - 4, byteoffset, tf_base,
6272 16 + tf_offset, 1, 0, true, false);
6273
6274 //store to offchip for TES to read - only if TES reads them
6275 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6276 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6277 LLVMValueRef tf_inner_offset;
6278 unsigned param_outer, param_inner;
6279
6280 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6281 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6282 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6283
6284 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6285 util_next_power_of_two(outer_comps));
6286
6287 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6288 outer_comps, tf_outer_offset,
6289 ctx->oc_lds, 0, 1, 0, true, false);
6290 if (inner_comps) {
6291 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6292 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6293 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6294
6295 inner_vec = inner_comps == 1 ? inner[0] :
6296 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6297 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6298 inner_comps, tf_inner_offset,
6299 ctx->oc_lds, 0, 1, 0, true, false);
6300 }
6301 }
6302 ac_nir_build_endif(&if_ctx);
6303 }
6304
6305 static void
6306 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6307 {
6308 write_tess_factors(ctx);
6309 }
6310
6311 static bool
6312 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6313 LLVMValueRef *color, unsigned param, bool is_last,
6314 struct ac_export_args *args)
6315 {
6316 /* Export */
6317 si_llvm_init_export_args(ctx, color, param,
6318 args);
6319
6320 if (is_last) {
6321 args->valid_mask = 1; /* whether the EXEC mask is valid */
6322 args->done = 1; /* DONE bit */
6323 } else if (!args->enabled_channels)
6324 return false; /* unnecessary NULL export */
6325
6326 return true;
6327 }
6328
6329 static void
6330 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6331 LLVMValueRef depth, LLVMValueRef stencil,
6332 LLVMValueRef samplemask)
6333 {
6334 struct ac_export_args args;
6335
6336 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6337
6338 ac_build_export(&ctx->ac, &args);
6339 }
6340
6341 static void
6342 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6343 {
6344 unsigned index = 0;
6345 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6346 struct ac_export_args color_args[8];
6347
6348 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6349 LLVMValueRef values[4];
6350
6351 if (!(ctx->output_mask & (1ull << i)))
6352 continue;
6353
6354 if (i == FRAG_RESULT_DEPTH) {
6355 ctx->shader_info->fs.writes_z = true;
6356 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6357 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6358 } else if (i == FRAG_RESULT_STENCIL) {
6359 ctx->shader_info->fs.writes_stencil = true;
6360 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6361 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6362 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6363 ctx->shader_info->fs.writes_sample_mask = true;
6364 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6365 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6366 } else {
6367 bool last = false;
6368 for (unsigned j = 0; j < 4; j++)
6369 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6370 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6371
6372 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6373 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6374
6375 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6376 if (ret)
6377 index++;
6378 }
6379 }
6380
6381 for (unsigned i = 0; i < index; i++)
6382 ac_build_export(&ctx->ac, &color_args[i]);
6383 if (depth || stencil || samplemask)
6384 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6385 else if (!index) {
6386 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6387 ac_build_export(&ctx->ac, &color_args[0]);
6388 }
6389
6390 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6391 }
6392
6393 static void
6394 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6395 {
6396 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6397 }
6398
6399 static void
6400 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6401 LLVMValueRef *addrs)
6402 {
6403 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6404
6405 switch (ctx->stage) {
6406 case MESA_SHADER_VERTEX:
6407 if (ctx->options->key.vs.as_ls)
6408 handle_ls_outputs_post(ctx);
6409 else if (ctx->options->key.vs.as_es)
6410 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6411 else
6412 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6413 &ctx->shader_info->vs.outinfo);
6414 break;
6415 case MESA_SHADER_FRAGMENT:
6416 handle_fs_outputs_post(ctx);
6417 break;
6418 case MESA_SHADER_GEOMETRY:
6419 emit_gs_epilogue(ctx);
6420 break;
6421 case MESA_SHADER_TESS_CTRL:
6422 handle_tcs_outputs_post(ctx);
6423 break;
6424 case MESA_SHADER_TESS_EVAL:
6425 if (ctx->options->key.tes.as_es)
6426 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6427 else
6428 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6429 &ctx->shader_info->tes.outinfo);
6430 break;
6431 default:
6432 break;
6433 }
6434 }
6435
6436 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6437 {
6438 LLVMPassManagerRef passmgr;
6439 /* Create the pass manager */
6440 passmgr = LLVMCreateFunctionPassManagerForModule(
6441 ctx->module);
6442
6443 /* This pass should eliminate all the load and store instructions */
6444 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6445
6446 /* Add some optimization passes */
6447 LLVMAddScalarReplAggregatesPass(passmgr);
6448 LLVMAddLICMPass(passmgr);
6449 LLVMAddAggressiveDCEPass(passmgr);
6450 LLVMAddCFGSimplificationPass(passmgr);
6451 LLVMAddInstructionCombiningPass(passmgr);
6452
6453 /* Run the pass */
6454 LLVMInitializeFunctionPassManager(passmgr);
6455 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6456 LLVMFinalizeFunctionPassManager(passmgr);
6457
6458 LLVMDisposeBuilder(ctx->builder);
6459 LLVMDisposePassManager(passmgr);
6460 }
6461
6462 static void
6463 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6464 {
6465 struct ac_vs_output_info *outinfo;
6466
6467 switch (ctx->stage) {
6468 case MESA_SHADER_FRAGMENT:
6469 case MESA_SHADER_COMPUTE:
6470 case MESA_SHADER_TESS_CTRL:
6471 case MESA_SHADER_GEOMETRY:
6472 return;
6473 case MESA_SHADER_VERTEX:
6474 if (ctx->options->key.vs.as_ls ||
6475 ctx->options->key.vs.as_es)
6476 return;
6477 outinfo = &ctx->shader_info->vs.outinfo;
6478 break;
6479 case MESA_SHADER_TESS_EVAL:
6480 if (ctx->options->key.vs.as_es)
6481 return;
6482 outinfo = &ctx->shader_info->tes.outinfo;
6483 break;
6484 default:
6485 unreachable("Unhandled shader type");
6486 }
6487
6488 ac_optimize_vs_outputs(&ctx->ac,
6489 ctx->main_function,
6490 outinfo->vs_output_param_offset,
6491 VARYING_SLOT_MAX,
6492 &outinfo->param_exports);
6493 }
6494
6495 static void
6496 ac_setup_rings(struct nir_to_llvm_context *ctx)
6497 {
6498 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6499 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6500 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6501 }
6502
6503 if (ctx->is_gs_copy_shader) {
6504 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6505 }
6506 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6507 LLVMValueRef tmp;
6508 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6509 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6510
6511 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6512
6513 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6514 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6515 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6516 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6517 }
6518
6519 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6520 ctx->stage == MESA_SHADER_TESS_EVAL) {
6521 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6522 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6523 }
6524 }
6525
6526 static unsigned
6527 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6528 const struct nir_shader *nir)
6529 {
6530 switch (nir->info.stage) {
6531 case MESA_SHADER_TESS_CTRL:
6532 return chip_class >= CIK ? 128 : 64;
6533 case MESA_SHADER_GEOMETRY:
6534 return chip_class >= GFX9 ? 128 : 64;
6535 case MESA_SHADER_COMPUTE:
6536 break;
6537 default:
6538 return 0;
6539 }
6540
6541 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6542 nir->info.cs.local_size[1] *
6543 nir->info.cs.local_size[2];
6544 return max_workgroup_size;
6545 }
6546
6547 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6548 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6549 {
6550 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6551 LLVMConstInt(ctx->ac.i32, 8, false),
6552 LLVMConstInt(ctx->ac.i32, 8, false), false);
6553 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6554 ctx->ac.i32_0, "");
6555 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6556 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6557 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6558 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6559 }
6560
6561 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6562 {
6563 for(int i = 5; i >= 0; --i) {
6564 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6565 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6566 LLVMConstInt(ctx->ac.i32, 16, false), false);
6567 }
6568
6569 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6570 LLVMConstInt(ctx->ac.i32, 16, false),
6571 LLVMConstInt(ctx->ac.i32, 8, false), false);
6572 }
6573
6574 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6575 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6576 {
6577 struct ac_nir_context ctx = {};
6578 struct nir_function *func;
6579
6580 ctx.ac = *ac;
6581 ctx.abi = abi;
6582
6583 ctx.nctx = nctx;
6584 if (nctx)
6585 nctx->nir = &ctx;
6586
6587 ctx.stage = nir->info.stage;
6588
6589 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6590
6591 nir_foreach_variable(variable, &nir->outputs)
6592 handle_shader_output_decl(&ctx, nir, variable);
6593
6594 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6595 _mesa_key_pointer_equal);
6596 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6597 _mesa_key_pointer_equal);
6598 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6599 _mesa_key_pointer_equal);
6600
6601 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6602
6603 setup_locals(&ctx, func);
6604
6605 if (nir->info.stage == MESA_SHADER_COMPUTE)
6606 setup_shared(&ctx, nir);
6607
6608 visit_cf_list(&ctx, &func->impl->body);
6609 phi_post_pass(&ctx);
6610
6611 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6612 ctx.outputs);
6613
6614 free(ctx.locals);
6615 ralloc_free(ctx.defs);
6616 ralloc_free(ctx.phis);
6617 ralloc_free(ctx.vars);
6618
6619 if (nctx)
6620 nctx->nir = NULL;
6621 }
6622
6623 static
6624 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6625 struct nir_shader *const *shaders,
6626 int shader_count,
6627 struct ac_shader_variant_info *shader_info,
6628 const struct ac_nir_compiler_options *options)
6629 {
6630 struct nir_to_llvm_context ctx = {0};
6631 unsigned i;
6632 ctx.options = options;
6633 ctx.shader_info = shader_info;
6634 ctx.context = LLVMContextCreate();
6635 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6636
6637 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6638 options->family);
6639 ctx.ac.module = ctx.module;
6640 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6641
6642 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6643 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6644 LLVMSetDataLayout(ctx.module, data_layout_str);
6645 LLVMDisposeTargetData(data_layout);
6646 LLVMDisposeMessage(data_layout_str);
6647
6648 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6649 ctx.ac.builder = ctx.builder;
6650
6651 memset(shader_info, 0, sizeof(*shader_info));
6652
6653 for(int i = 0; i < shader_count; ++i)
6654 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6655
6656 for (i = 0; i < AC_UD_MAX_SETS; i++)
6657 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6658 for (i = 0; i < AC_UD_MAX_UD; i++)
6659 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6660
6661 ctx.max_workgroup_size = 0;
6662 for (int i = 0; i < shader_count; ++i) {
6663 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6664 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6665 shaders[i]));
6666 }
6667
6668 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6669 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6670
6671 ctx.abi.inputs = &ctx.inputs[0];
6672 ctx.abi.emit_outputs = handle_shader_outputs_post;
6673 ctx.abi.emit_vertex = visit_emit_vertex;
6674 ctx.abi.load_ubo = radv_load_ubo;
6675 ctx.abi.load_ssbo = radv_load_ssbo;
6676 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6677 ctx.abi.clamp_shadow_reference = false;
6678
6679 if (shader_count >= 2)
6680 ac_init_exec_full_mask(&ctx.ac);
6681
6682 if (ctx.ac.chip_class == GFX9 &&
6683 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6684 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6685
6686 for(int i = 0; i < shader_count; ++i) {
6687 ctx.stage = shaders[i]->info.stage;
6688 ctx.output_mask = 0;
6689 ctx.tess_outputs_written = 0;
6690 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6691 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6692
6693 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6694 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6695 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6696 ctx.abi.load_inputs = load_gs_input;
6697 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6698 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6699 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6700 ctx.abi.load_tess_inputs = load_tcs_input;
6701 ctx.abi.store_tcs_outputs = store_tcs_output;
6702 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6703 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6704 ctx.abi.load_tess_inputs = load_tes_input;
6705 ctx.abi.load_tess_coord = load_tess_coord;
6706 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6707 if (shader_info->info.vs.needs_instance_id) {
6708 if (ctx.ac.chip_class == GFX9 &&
6709 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL) {
6710 ctx.shader_info->vs.vgpr_comp_cnt =
6711 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6712 } else {
6713 ctx.shader_info->vs.vgpr_comp_cnt =
6714 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6715 }
6716 }
6717 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6718 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6719 }
6720
6721 if (i)
6722 emit_barrier(&ctx.ac, ctx.stage);
6723
6724 ac_setup_rings(&ctx);
6725
6726 LLVMBasicBlockRef merge_block;
6727 if (shader_count >= 2) {
6728 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6729 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6730 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6731
6732 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6733 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6734 LLVMConstInt(ctx.ac.i32, 8, false), false);
6735 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6736 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6737 thread_id, count, "");
6738 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6739
6740 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6741 }
6742
6743 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6744 handle_fs_inputs(&ctx, shaders[i]);
6745 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6746 handle_vs_inputs(&ctx, shaders[i]);
6747 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6748 prepare_gs_input_vgprs(&ctx);
6749
6750 nir_foreach_variable(variable, &shaders[i]->outputs)
6751 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6752
6753 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6754
6755 if (shader_count >= 2) {
6756 LLVMBuildBr(ctx.ac.builder, merge_block);
6757 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6758 }
6759
6760 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6761 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6762 shaders[i]->info.cull_distance_array_size > 4;
6763 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6764 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6765 shaders[i]->info.gs.vertices_out;
6766 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6767 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6768 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6769 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6770 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6771 }
6772 }
6773
6774 LLVMBuildRetVoid(ctx.builder);
6775
6776 ac_llvm_finalize_module(&ctx);
6777
6778 if (shader_count == 1)
6779 ac_nir_eliminate_const_vs_outputs(&ctx);
6780
6781 return ctx.module;
6782 }
6783
6784 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6785 {
6786 unsigned *retval = (unsigned *)context;
6787 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6788 char *description = LLVMGetDiagInfoDescription(di);
6789
6790 if (severity == LLVMDSError) {
6791 *retval = 1;
6792 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6793 description);
6794 }
6795
6796 LLVMDisposeMessage(description);
6797 }
6798
6799 static unsigned ac_llvm_compile(LLVMModuleRef M,
6800 struct ac_shader_binary *binary,
6801 LLVMTargetMachineRef tm)
6802 {
6803 unsigned retval = 0;
6804 char *err;
6805 LLVMContextRef llvm_ctx;
6806 LLVMMemoryBufferRef out_buffer;
6807 unsigned buffer_size;
6808 const char *buffer_data;
6809 LLVMBool mem_err;
6810
6811 /* Setup Diagnostic Handler*/
6812 llvm_ctx = LLVMGetModuleContext(M);
6813
6814 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6815 &retval);
6816
6817 /* Compile IR*/
6818 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6819 &err, &out_buffer);
6820
6821 /* Process Errors/Warnings */
6822 if (mem_err) {
6823 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6824 free(err);
6825 retval = 1;
6826 goto out;
6827 }
6828
6829 /* Extract Shader Code*/
6830 buffer_size = LLVMGetBufferSize(out_buffer);
6831 buffer_data = LLVMGetBufferStart(out_buffer);
6832
6833 ac_elf_read(buffer_data, buffer_size, binary);
6834
6835 /* Clean up */
6836 LLVMDisposeMemoryBuffer(out_buffer);
6837
6838 out:
6839 return retval;
6840 }
6841
6842 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6843 LLVMModuleRef llvm_module,
6844 struct ac_shader_binary *binary,
6845 struct ac_shader_config *config,
6846 struct ac_shader_variant_info *shader_info,
6847 gl_shader_stage stage,
6848 bool dump_shader, bool supports_spill)
6849 {
6850 if (dump_shader)
6851 ac_dump_module(llvm_module);
6852
6853 memset(binary, 0, sizeof(*binary));
6854 int v = ac_llvm_compile(llvm_module, binary, tm);
6855 if (v) {
6856 fprintf(stderr, "compile failed\n");
6857 }
6858
6859 if (dump_shader)
6860 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6861
6862 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6863
6864 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6865 LLVMDisposeModule(llvm_module);
6866 LLVMContextDispose(ctx);
6867
6868 if (stage == MESA_SHADER_FRAGMENT) {
6869 shader_info->num_input_vgprs = 0;
6870 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6871 shader_info->num_input_vgprs += 2;
6872 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6873 shader_info->num_input_vgprs += 2;
6874 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6875 shader_info->num_input_vgprs += 2;
6876 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6877 shader_info->num_input_vgprs += 3;
6878 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6879 shader_info->num_input_vgprs += 2;
6880 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6881 shader_info->num_input_vgprs += 2;
6882 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6883 shader_info->num_input_vgprs += 2;
6884 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6885 shader_info->num_input_vgprs += 1;
6886 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6887 shader_info->num_input_vgprs += 1;
6888 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6889 shader_info->num_input_vgprs += 1;
6890 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6891 shader_info->num_input_vgprs += 1;
6892 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6893 shader_info->num_input_vgprs += 1;
6894 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6895 shader_info->num_input_vgprs += 1;
6896 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6897 shader_info->num_input_vgprs += 1;
6898 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6899 shader_info->num_input_vgprs += 1;
6900 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6901 shader_info->num_input_vgprs += 1;
6902 }
6903 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6904
6905 /* +3 for scratch wave offset and VCC */
6906 config->num_sgprs = MAX2(config->num_sgprs,
6907 shader_info->num_input_sgprs + 3);
6908
6909 /* Enable 64-bit and 16-bit denormals, because there is no performance
6910 * cost.
6911 *
6912 * If denormals are enabled, all floating-point output modifiers are
6913 * ignored.
6914 *
6915 * Don't enable denormals for 32-bit floats, because:
6916 * - Floating-point output modifiers would be ignored by the hw.
6917 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6918 * have to stop using those.
6919 * - SI & CI would be very slow.
6920 */
6921 config->float_mode |= V_00B028_FP_64_DENORMS;
6922 }
6923
6924 static void
6925 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6926 {
6927 switch (nir->info.stage) {
6928 case MESA_SHADER_COMPUTE:
6929 for (int i = 0; i < 3; ++i)
6930 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6931 break;
6932 case MESA_SHADER_FRAGMENT:
6933 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6934 break;
6935 case MESA_SHADER_GEOMETRY:
6936 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6937 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6938 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6939 shader_info->gs.invocations = nir->info.gs.invocations;
6940 break;
6941 case MESA_SHADER_TESS_EVAL:
6942 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6943 shader_info->tes.spacing = nir->info.tess.spacing;
6944 shader_info->tes.ccw = nir->info.tess.ccw;
6945 shader_info->tes.point_mode = nir->info.tess.point_mode;
6946 shader_info->tes.as_es = options->key.tes.as_es;
6947 break;
6948 case MESA_SHADER_TESS_CTRL:
6949 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6950 break;
6951 case MESA_SHADER_VERTEX:
6952 shader_info->vs.as_es = options->key.vs.as_es;
6953 shader_info->vs.as_ls = options->key.vs.as_ls;
6954 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
6955 if (options->key.vs.as_ls)
6956 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6957 break;
6958 default:
6959 break;
6960 }
6961 }
6962
6963 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6964 struct ac_shader_binary *binary,
6965 struct ac_shader_config *config,
6966 struct ac_shader_variant_info *shader_info,
6967 struct nir_shader *const *nir,
6968 int nir_count,
6969 const struct ac_nir_compiler_options *options,
6970 bool dump_shader)
6971 {
6972
6973 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6974 options);
6975
6976 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6977 for (int i = 0; i < nir_count; ++i)
6978 ac_fill_shader_info(shader_info, nir[i], options);
6979
6980 /* Determine the ES type (VS or TES) for the GS on GFX9. */
6981 if (options->chip_class == GFX9) {
6982 if (nir_count == 2 &&
6983 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
6984 shader_info->gs.es_type = nir[0]->info.stage;
6985 }
6986 }
6987 }
6988
6989 static void
6990 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6991 {
6992 LLVMValueRef args[9];
6993 args[0] = ctx->gsvs_ring;
6994 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6995 args[3] = ctx->ac.i32_0;
6996 args[4] = ctx->ac.i32_1; /* OFFEN */
6997 args[5] = ctx->ac.i32_0; /* IDXEN */
6998 args[6] = ctx->ac.i32_1; /* GLC */
6999 args[7] = ctx->ac.i32_1; /* SLC */
7000 args[8] = ctx->ac.i32_0; /* TFE */
7001
7002 int idx = 0;
7003
7004 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7005 int length = 4;
7006 int slot = idx;
7007 int slot_inc = 1;
7008 if (!(ctx->output_mask & (1ull << i)))
7009 continue;
7010
7011 if (i == VARYING_SLOT_CLIP_DIST0) {
7012 /* unpack clip and cull from a single set of slots */
7013 length = ctx->num_output_clips + ctx->num_output_culls;
7014 if (length > 4)
7015 slot_inc = 2;
7016 }
7017
7018 for (unsigned j = 0; j < length; j++) {
7019 LLVMValueRef value;
7020 args[2] = LLVMConstInt(ctx->ac.i32,
7021 (slot * 4 + j) *
7022 ctx->gs_max_out_vertices * 16 * 4, false);
7023
7024 value = ac_build_intrinsic(&ctx->ac,
7025 "llvm.SI.buffer.load.dword.i32.i32",
7026 ctx->ac.i32, args, 9,
7027 AC_FUNC_ATTR_READONLY |
7028 AC_FUNC_ATTR_LEGACY);
7029
7030 LLVMBuildStore(ctx->builder,
7031 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7032 }
7033 idx += slot_inc;
7034 }
7035 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7036 }
7037
7038 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7039 struct nir_shader *geom_shader,
7040 struct ac_shader_binary *binary,
7041 struct ac_shader_config *config,
7042 struct ac_shader_variant_info *shader_info,
7043 const struct ac_nir_compiler_options *options,
7044 bool dump_shader)
7045 {
7046 struct nir_to_llvm_context ctx = {0};
7047 ctx.context = LLVMContextCreate();
7048 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7049 ctx.options = options;
7050 ctx.shader_info = shader_info;
7051
7052 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7053 options->family);
7054 ctx.ac.module = ctx.module;
7055
7056 ctx.is_gs_copy_shader = true;
7057 LLVMSetTarget(ctx.module, "amdgcn--");
7058
7059 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7060 ctx.ac.builder = ctx.builder;
7061 ctx.stage = MESA_SHADER_VERTEX;
7062
7063 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7064
7065 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7066 ac_setup_rings(&ctx);
7067
7068 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7069 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7070
7071 struct ac_nir_context nir_ctx = {};
7072 nir_ctx.ac = ctx.ac;
7073 nir_ctx.abi = &ctx.abi;
7074
7075 nir_ctx.nctx = &ctx;
7076 ctx.nir = &nir_ctx;
7077
7078 nir_foreach_variable(variable, &geom_shader->outputs) {
7079 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7080 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7081 }
7082
7083 ac_gs_copy_shader_emit(&ctx);
7084
7085 ctx.nir = NULL;
7086
7087 LLVMBuildRetVoid(ctx.builder);
7088
7089 ac_llvm_finalize_module(&ctx);
7090
7091 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7092 MESA_SHADER_VERTEX,
7093 dump_shader, options->supports_spill);
7094 }