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amd/common: remove unnecessary user_sgpr_count
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tcs_patch_id;
115 LLVMValueRef tcs_rel_ids;
116 LLVMValueRef tes_rel_patch_id;
117 LLVMValueRef tes_patch_id;
118 LLVMValueRef tes_u;
119 LLVMValueRef tes_v;
120
121 LLVMValueRef gsvs_ring_stride;
122 LLVMValueRef gsvs_num_entries;
123 LLVMValueRef gs2vs_offset;
124 LLVMValueRef gs_wave_id;
125 LLVMValueRef gs_vtx_offset[6];
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153
154 uint32_t tcs_patch_outputs_read;
155 uint64_t tcs_outputs_read;
156 };
157
158 static inline struct nir_to_llvm_context *
159 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
160 {
161 struct nir_to_llvm_context *ctx = NULL;
162 return container_of(abi, ctx, abi);
163 }
164
165 static LLVMTypeRef
166 nir2llvmtype(struct ac_nir_context *ctx,
167 const struct glsl_type *type)
168 {
169 switch (glsl_get_base_type(glsl_without_array(type))) {
170 case GLSL_TYPE_UINT:
171 case GLSL_TYPE_INT:
172 return ctx->ac.i32;
173 case GLSL_TYPE_UINT64:
174 case GLSL_TYPE_INT64:
175 return ctx->ac.i64;
176 case GLSL_TYPE_DOUBLE:
177 return ctx->ac.f64;
178 case GLSL_TYPE_FLOAT:
179 return ctx->ac.f32;
180 default:
181 assert(!"Unsupported type in nir2llvmtype()");
182 break;
183 }
184 return 0;
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 const nir_tex_instr *instr,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t sgpr_count;
256 uint8_t num_user_sgprs_used;
257 uint8_t num_sgprs_used;
258 uint8_t num_vgprs_used;
259 };
260
261 static inline void
262 add_argument(struct arg_info *info,
263 LLVMTypeRef type, LLVMValueRef *param_ptr)
264 {
265 assert(info->count < MAX_ARGS);
266 info->assign[info->count] = param_ptr;
267 info->types[info->count] = type;
268 info->count++;
269 }
270
271 static inline void
272 add_sgpr_argument(struct arg_info *info,
273 LLVMTypeRef type, LLVMValueRef *param_ptr)
274 {
275 add_argument(info, type, param_ptr);
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 }
279
280 static inline void
281 add_user_sgpr_argument(struct arg_info *info,
282 LLVMTypeRef type,
283 LLVMValueRef *param_ptr)
284 {
285 add_sgpr_argument(info, type, param_ptr);
286 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
287 }
288
289 static inline void
290 add_vgpr_argument(struct arg_info *info,
291 LLVMTypeRef type,
292 LLVMValueRef *param_ptr)
293 {
294 add_argument(info, type, param_ptr);
295 info->num_vgprs_used += ac_get_type_size(type) / 4;
296 }
297
298 static inline void
299 add_user_sgpr_array_argument(struct arg_info *info,
300 LLVMTypeRef type,
301 LLVMValueRef *param_ptr)
302 {
303 info->array_params_mask |= (1 << info->count);
304 add_user_sgpr_argument(info, type, param_ptr);
305 }
306
307 static void assign_arguments(LLVMValueRef main_function,
308 struct arg_info *info)
309 {
310 unsigned i;
311 for (i = 0; i < info->count; i++) {
312 if (info->assign[i])
313 *info->assign[i] = LLVMGetParam(main_function, i);
314 }
315 }
316
317 static LLVMValueRef
318 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
319 LLVMBuilderRef builder, LLVMTypeRef *return_types,
320 unsigned num_return_elems,
321 struct arg_info *args,
322 unsigned max_workgroup_size,
323 bool unsafe_math)
324 {
325 LLVMTypeRef main_function_type, ret_type;
326 LLVMBasicBlockRef main_function_body;
327
328 if (num_return_elems)
329 ret_type = LLVMStructTypeInContext(ctx, return_types,
330 num_return_elems, true);
331 else
332 ret_type = LLVMVoidTypeInContext(ctx);
333
334 /* Setup the function */
335 main_function_type =
336 LLVMFunctionType(ret_type, args->types, args->count, 0);
337 LLVMValueRef main_function =
338 LLVMAddFunction(module, "main", main_function_type);
339 main_function_body =
340 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
341 LLVMPositionBuilderAtEnd(builder, main_function_body);
342
343 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
344 for (unsigned i = 0; i < args->sgpr_count; ++i) {
345 if (args->array_params_mask & (1 << i)) {
346 LLVMValueRef P = LLVMGetParam(main_function, i);
347 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
348 ac_add_attr_dereferenceable(P, UINT64_MAX);
349 }
350 else {
351 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
352 }
353 }
354
355 if (max_workgroup_size) {
356 ac_llvm_add_target_dep_function_attr(main_function,
357 "amdgpu-max-work-group-size",
358 max_workgroup_size);
359 }
360 if (unsafe_math) {
361 /* These were copied from some LLVM test. */
362 LLVMAddTargetDependentFunctionAttr(main_function,
363 "less-precise-fpmad",
364 "true");
365 LLVMAddTargetDependentFunctionAttr(main_function,
366 "no-infs-fp-math",
367 "true");
368 LLVMAddTargetDependentFunctionAttr(main_function,
369 "no-nans-fp-math",
370 "true");
371 LLVMAddTargetDependentFunctionAttr(main_function,
372 "unsafe-fp-math",
373 "true");
374 }
375 return main_function;
376 }
377
378 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
379 {
380 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
381 CONST_ADDR_SPACE);
382 }
383
384 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
385 {
386 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
387 type = LLVMGetElementType(type);
388
389 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
390 return LLVMGetIntTypeWidth(type);
391
392 if (type == ctx->f16)
393 return 16;
394 if (type == ctx->f32)
395 return 32;
396 if (type == ctx->f64)
397 return 64;
398
399 unreachable("Unhandled type kind in get_elem_bits");
400 }
401
402 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
403 LLVMValueRef param, unsigned rshift,
404 unsigned bitwidth)
405 {
406 LLVMValueRef value = param;
407 if (rshift)
408 value = LLVMBuildLShr(ctx->builder, value,
409 LLVMConstInt(ctx->i32, rshift, false), "");
410
411 if (rshift + bitwidth < 32) {
412 unsigned mask = (1 << bitwidth) - 1;
413 value = LLVMBuildAnd(ctx->builder, value,
414 LLVMConstInt(ctx->i32, mask, false), "");
415 }
416 return value;
417 }
418
419 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
420 {
421 switch (ctx->stage) {
422 case MESA_SHADER_TESS_CTRL:
423 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
424 case MESA_SHADER_TESS_EVAL:
425 return ctx->tes_rel_patch_id;
426 break;
427 default:
428 unreachable("Illegal stage");
429 }
430 }
431
432 /* Tessellation shaders pass outputs to the next shader using LDS.
433 *
434 * LS outputs = TCS inputs
435 * TCS outputs = TES inputs
436 *
437 * The LDS layout is:
438 * - TCS inputs for patch 0
439 * - TCS inputs for patch 1
440 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
441 * - ...
442 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
443 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
444 * - TCS outputs for patch 1
445 * - Per-patch TCS outputs for patch 1
446 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
447 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
448 * - ...
449 *
450 * All three shaders VS(LS), TCS, TES share the same LDS space.
451 */
452 static LLVMValueRef
453 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
454 {
455 if (ctx->stage == MESA_SHADER_VERTEX)
456 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
457 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
458 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
459 else {
460 assert(0);
461 return NULL;
462 }
463 }
464
465 static LLVMValueRef
466 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
467 {
468 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
469 }
470
471 static LLVMValueRef
472 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
473 {
474 return LLVMBuildMul(ctx->builder,
475 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
476 LLVMConstInt(ctx->ac.i32, 4, false), "");
477 }
478
479 static LLVMValueRef
480 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
481 {
482 return LLVMBuildMul(ctx->builder,
483 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
484 LLVMConstInt(ctx->ac.i32, 4, false), "");
485 }
486
487 static LLVMValueRef
488 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
489 {
490 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
491 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
492
493 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
494 }
495
496 static LLVMValueRef
497 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
498 {
499 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
500 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
501 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
502
503 return LLVMBuildAdd(ctx->builder, patch0_offset,
504 LLVMBuildMul(ctx->builder, patch_stride,
505 rel_patch_id, ""),
506 "");
507 }
508
509 static LLVMValueRef
510 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
511 {
512 LLVMValueRef patch0_patch_data_offset =
513 get_tcs_out_patch0_patch_data_offset(ctx);
514 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
515 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
516
517 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
518 LLVMBuildMul(ctx->builder, patch_stride,
519 rel_patch_id, ""),
520 "");
521 }
522
523 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
524 {
525 ud_info->sgpr_idx = *sgpr_idx;
526 ud_info->num_sgprs = num_sgprs;
527 ud_info->indirect = false;
528 ud_info->indirect_offset = 0;
529 *sgpr_idx += num_sgprs;
530 }
531
532 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
533 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
534 {
535 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
536 }
537
538
539 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
540 uint32_t indirect_offset)
541 {
542 ud_info->sgpr_idx = sgpr_idx;
543 ud_info->num_sgprs = num_sgprs;
544 ud_info->indirect = true;
545 ud_info->indirect_offset = indirect_offset;
546 }
547
548 struct user_sgpr_info {
549 bool need_ring_offsets;
550 uint8_t sgpr_count;
551 bool indirect_all_descriptor_sets;
552 };
553
554 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
555 struct user_sgpr_info *user_sgpr_info)
556 {
557 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
558
559 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
560 if (ctx->stage == MESA_SHADER_GEOMETRY ||
561 ctx->stage == MESA_SHADER_VERTEX ||
562 ctx->stage == MESA_SHADER_TESS_CTRL ||
563 ctx->stage == MESA_SHADER_TESS_EVAL ||
564 ctx->is_gs_copy_shader)
565 user_sgpr_info->need_ring_offsets = true;
566
567 if (ctx->stage == MESA_SHADER_FRAGMENT &&
568 ctx->shader_info->info.ps.needs_sample_positions)
569 user_sgpr_info->need_ring_offsets = true;
570
571 /* 2 user sgprs will nearly always be allocated for scratch/rings */
572 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
573 user_sgpr_info->sgpr_count += 2;
574 }
575
576 switch (ctx->stage) {
577 case MESA_SHADER_COMPUTE:
578 if (ctx->shader_info->info.cs.uses_grid_size)
579 user_sgpr_info->sgpr_count += 3;
580 break;
581 case MESA_SHADER_FRAGMENT:
582 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
583 break;
584 case MESA_SHADER_VERTEX:
585 if (!ctx->is_gs_copy_shader) {
586 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
587 if (ctx->shader_info->info.vs.needs_draw_id) {
588 user_sgpr_info->sgpr_count += 3;
589 } else {
590 user_sgpr_info->sgpr_count += 2;
591 }
592 }
593 if (ctx->options->key.vs.as_ls)
594 user_sgpr_info->sgpr_count++;
595 break;
596 case MESA_SHADER_TESS_CTRL:
597 user_sgpr_info->sgpr_count += 4;
598 break;
599 case MESA_SHADER_TESS_EVAL:
600 user_sgpr_info->sgpr_count += 1;
601 break;
602 case MESA_SHADER_GEOMETRY:
603 user_sgpr_info->sgpr_count += 2;
604 break;
605 default:
606 break;
607 }
608
609 if (ctx->shader_info->info.needs_push_constants)
610 user_sgpr_info->sgpr_count += 2;
611
612 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
613 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
614 user_sgpr_info->sgpr_count += 2;
615 user_sgpr_info->indirect_all_descriptor_sets = true;
616 } else {
617 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
618 }
619 }
620
621 static void
622 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
623 gl_shader_stage stage,
624 bool has_previous_stage,
625 gl_shader_stage previous_stage,
626 const struct user_sgpr_info *user_sgpr_info,
627 struct arg_info *args,
628 LLVMValueRef *desc_sets)
629 {
630 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
631 unsigned stage_mask = 1 << stage;
632 if (has_previous_stage)
633 stage_mask |= 1 << previous_stage;
634
635 /* 1 for each descriptor set */
636 if (!user_sgpr_info->indirect_all_descriptor_sets) {
637 for (unsigned i = 0; i < num_sets; ++i) {
638 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
639 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->descriptor_sets[i]);
640 }
641 }
642 } else
643 add_user_sgpr_array_argument(args, const_array(const_array(ctx->ac.i8, 1024 * 1024), 32), desc_sets);
644
645 if (ctx->shader_info->info.needs_push_constants) {
646 /* 1 for push constants and dynamic descriptors */
647 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->push_constants);
648 }
649 }
650
651 static void
652 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
653 gl_shader_stage stage,
654 bool has_previous_stage,
655 gl_shader_stage previous_stage,
656 const struct user_sgpr_info *user_sgpr_info,
657 LLVMValueRef desc_sets,
658 uint8_t *user_sgpr_idx)
659 {
660 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
661 unsigned stage_mask = 1 << stage;
662 if (has_previous_stage)
663 stage_mask |= 1 << previous_stage;
664
665 if (!user_sgpr_info->indirect_all_descriptor_sets) {
666 for (unsigned i = 0; i < num_sets; ++i) {
667 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
668 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
669 } else
670 ctx->descriptor_sets[i] = NULL;
671 }
672 } else {
673 uint32_t desc_sgpr_idx = *user_sgpr_idx;
674 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
675
676 for (unsigned i = 0; i < num_sets; ++i) {
677 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
678 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
679 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
680
681 } else
682 ctx->descriptor_sets[i] = NULL;
683 }
684 ctx->shader_info->need_indirect_descriptor_sets = true;
685 }
686
687 if (ctx->shader_info->info.needs_push_constants) {
688 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
689 }
690 }
691
692 static void
693 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
694 gl_shader_stage stage,
695 bool has_previous_stage,
696 gl_shader_stage previous_stage,
697 struct arg_info *args)
698 {
699 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
700 if (ctx->shader_info->info.vs.has_vertex_buffers)
701 add_user_sgpr_argument(args, const_array(ctx->ac.v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
702 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.base_vertex); // base vertex
703 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.start_instance);// start instance
704 if (ctx->shader_info->info.vs.needs_draw_id)
705 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.draw_id); // draw id
706 }
707 }
708
709 static void
710 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
711 gl_shader_stage stage,
712 bool has_previous_stage,
713 gl_shader_stage previous_stage,
714 uint8_t *user_sgpr_idx)
715 {
716 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
717 if (ctx->shader_info->info.vs.has_vertex_buffers) {
718 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
719 }
720 unsigned vs_num = 2;
721 if (ctx->shader_info->info.vs.needs_draw_id)
722 vs_num++;
723
724 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
725 }
726 }
727
728
729 static void create_function(struct nir_to_llvm_context *ctx,
730 gl_shader_stage stage,
731 bool has_previous_stage,
732 gl_shader_stage previous_stage)
733 {
734 uint8_t user_sgpr_idx;
735 struct user_sgpr_info user_sgpr_info;
736 struct arg_info args = {};
737 LLVMValueRef desc_sets;
738
739 allocate_user_sgprs(ctx, &user_sgpr_info);
740
741 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
742 add_user_sgpr_argument(&args, const_array(ctx->ac.v4i32, 16), &ctx->ring_offsets); /* address of rings */
743 }
744
745 switch (stage) {
746 case MESA_SHADER_COMPUTE:
747 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
748 if (ctx->shader_info->info.cs.uses_grid_size) {
749 add_user_sgpr_argument(&args, ctx->ac.v3i32,
750 &ctx->num_work_groups);
751 }
752
753 for (int i = 0; i < 3; i++) {
754 ctx->workgroup_ids[i] = NULL;
755 if (ctx->shader_info->info.cs.uses_block_id[i]) {
756 add_sgpr_argument(&args, ctx->ac.i32,
757 &ctx->workgroup_ids[i]);
758 }
759 }
760
761 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
762 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
763 add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
764 break;
765 case MESA_SHADER_VERTEX:
766 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
767 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
768 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
769 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
770 if (ctx->options->key.vs.as_es)
771 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
772 else if (ctx->options->key.vs.as_ls)
773 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
774 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
775 if (!ctx->is_gs_copy_shader) {
776 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
777 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
778 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
779 }
780 break;
781 case MESA_SHADER_TESS_CTRL:
782 if (has_previous_stage) {
783 // First 6 system regs
784 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
785 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
786 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
787
788 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
789 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
790 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
791
792 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
793 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
794 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
795
796 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
797 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
798 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
799 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
800 if (ctx->shader_info->info.needs_multiview_view_index)
801 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
802
803 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
804 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
805 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
806 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
807 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
808 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
809 } else {
810 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
811 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
812 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
813 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
814 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
815 if (ctx->shader_info->info.needs_multiview_view_index)
816 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
817 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
818 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
819 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
820 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
821 }
822 break;
823 case MESA_SHADER_TESS_EVAL:
824 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
825 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
826 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
827 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
828 if (ctx->options->key.tes.as_es) {
829 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
830 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
831 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
832 } else {
833 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
834 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
835 }
836 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
837 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
838 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
839 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
840 break;
841 case MESA_SHADER_GEOMETRY:
842 if (has_previous_stage) {
843 // First 6 system regs
844 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
845 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
846 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
847
848 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
849 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
850 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
851
852 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
853 if (previous_stage == MESA_SHADER_TESS_EVAL)
854 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
855 else
856 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
857 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
858 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
859 if (ctx->shader_info->info.needs_multiview_view_index)
860 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
861
862 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx01
863 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]); // vtx23
864 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
865 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
866 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
867
868 if (previous_stage == MESA_SHADER_VERTEX) {
869 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
870 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
871 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
872 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
873 } else {
874 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
875 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
876 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
877 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
878 }
879 } else {
880 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
881 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
882 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
883 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
884 if (ctx->shader_info->info.needs_multiview_view_index)
885 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
886 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
887 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
888 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx0
889 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[1]); // vtx1
890 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
891 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]);
892 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[3]);
893 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
894 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[5]);
895 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
896 }
897 break;
898 case MESA_SHADER_FRAGMENT:
899 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
900 if (ctx->shader_info->info.ps.needs_sample_positions)
901 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */
902 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
903 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /* persp sample */
904 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /* persp center */
905 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid); /* persp centroid */
906 add_vgpr_argument(&args, ctx->ac.v3i32, NULL); /* persp pull model */
907 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_sample); /* linear sample */
908 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_center); /* linear center */
909 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_centroid); /* linear centroid */
910 add_vgpr_argument(&args, ctx->ac.f32, NULL); /* line stipple tex */
911 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[0]); /* pos x float */
912 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[1]); /* pos y float */
913 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[2]); /* pos z float */
914 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[3]); /* pos w float */
915 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */
916 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */
917 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.sample_coverage); /* sample coverage */
918 add_vgpr_argument(&args, ctx->ac.i32, NULL); /* fixed pt */
919 break;
920 default:
921 unreachable("Shader stage not implemented");
922 }
923
924 ctx->main_function = create_llvm_function(
925 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
926 ctx->max_workgroup_size,
927 ctx->options->unsafe_math);
928 set_llvm_calling_convention(ctx->main_function, stage);
929
930
931 ctx->shader_info->num_input_vgprs = 0;
932 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
933
934 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
935
936 if (ctx->stage != MESA_SHADER_FRAGMENT)
937 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
938
939 assign_arguments(ctx->main_function, &args);
940
941 user_sgpr_idx = 0;
942
943 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
944 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
945 if (ctx->options->supports_spill) {
946 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
947 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
948 NULL, 0, AC_FUNC_ATTR_READNONE);
949 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
950 const_array(ctx->ac.v4i32, 16), "");
951 }
952 }
953
954 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
955 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
956 if (has_previous_stage)
957 user_sgpr_idx = 0;
958
959 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
960
961 switch (stage) {
962 case MESA_SHADER_COMPUTE:
963 if (ctx->shader_info->info.cs.uses_grid_size) {
964 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE,
965 &user_sgpr_idx, 3);
966 }
967 break;
968 case MESA_SHADER_VERTEX:
969 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
970 if (ctx->view_index)
971 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
972 if (ctx->options->key.vs.as_ls) {
973 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
974 }
975 if (ctx->options->key.vs.as_ls)
976 ac_declare_lds_as_pointer(&ctx->ac);
977 break;
978 case MESA_SHADER_TESS_CTRL:
979 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
980 if (has_previous_stage)
981 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
982 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
983 if (ctx->view_index)
984 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
985 ac_declare_lds_as_pointer(&ctx->ac);
986 break;
987 case MESA_SHADER_TESS_EVAL:
988 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
989 if (ctx->view_index)
990 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
991 break;
992 case MESA_SHADER_GEOMETRY:
993 if (has_previous_stage) {
994 if (previous_stage == MESA_SHADER_VERTEX)
995 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
996 else
997 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
998 }
999 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
1000 if (ctx->view_index)
1001 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1002 if (has_previous_stage)
1003 ac_declare_lds_as_pointer(&ctx->ac);
1004 break;
1005 case MESA_SHADER_FRAGMENT:
1006 if (ctx->shader_info->info.ps.needs_sample_positions) {
1007 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
1008 }
1009 break;
1010 default:
1011 unreachable("Shader stage not implemented");
1012 }
1013
1014 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1015 }
1016
1017 static int get_llvm_num_components(LLVMValueRef value)
1018 {
1019 LLVMTypeRef type = LLVMTypeOf(value);
1020 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1021 ? LLVMGetVectorSize(type)
1022 : 1;
1023 return num_components;
1024 }
1025
1026 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1027 LLVMValueRef value,
1028 int index)
1029 {
1030 int count = get_llvm_num_components(value);
1031
1032 if (count == 1)
1033 return value;
1034
1035 return LLVMBuildExtractElement(ac->builder, value,
1036 LLVMConstInt(ac->i32, index, false), "");
1037 }
1038
1039 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1040 LLVMValueRef value, unsigned count)
1041 {
1042 unsigned num_components = get_llvm_num_components(value);
1043 if (count == num_components)
1044 return value;
1045
1046 LLVMValueRef masks[] = {
1047 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1048 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1049
1050 if (count == 1)
1051 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1052 "");
1053
1054 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1055 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1056 }
1057
1058 static void
1059 build_store_values_extended(struct ac_llvm_context *ac,
1060 LLVMValueRef *values,
1061 unsigned value_count,
1062 unsigned value_stride,
1063 LLVMValueRef vec)
1064 {
1065 LLVMBuilderRef builder = ac->builder;
1066 unsigned i;
1067
1068 for (i = 0; i < value_count; i++) {
1069 LLVMValueRef ptr = values[i * value_stride];
1070 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1071 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1072 LLVMBuildStore(builder, value, ptr);
1073 }
1074 }
1075
1076 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1077 const nir_ssa_def *def)
1078 {
1079 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1080 if (def->num_components > 1) {
1081 type = LLVMVectorType(type, def->num_components);
1082 }
1083 return type;
1084 }
1085
1086 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1087 {
1088 assert(src.is_ssa);
1089 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1090 return (LLVMValueRef)entry->data;
1091 }
1092
1093
1094 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1095 const struct nir_block *b)
1096 {
1097 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1098 return (LLVMBasicBlockRef)entry->data;
1099 }
1100
1101 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1102 nir_alu_src src,
1103 unsigned num_components)
1104 {
1105 LLVMValueRef value = get_src(ctx, src.src);
1106 bool need_swizzle = false;
1107
1108 assert(value);
1109 LLVMTypeRef type = LLVMTypeOf(value);
1110 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1111 ? LLVMGetVectorSize(type)
1112 : 1;
1113
1114 for (unsigned i = 0; i < num_components; ++i) {
1115 assert(src.swizzle[i] < src_components);
1116 if (src.swizzle[i] != i)
1117 need_swizzle = true;
1118 }
1119
1120 if (need_swizzle || num_components != src_components) {
1121 LLVMValueRef masks[] = {
1122 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1123 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1124 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1125 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1126
1127 if (src_components > 1 && num_components == 1) {
1128 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1129 masks[0], "");
1130 } else if (src_components == 1 && num_components > 1) {
1131 LLVMValueRef values[] = {value, value, value, value};
1132 value = ac_build_gather_values(&ctx->ac, values, num_components);
1133 } else {
1134 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1135 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1136 swizzle, "");
1137 }
1138 }
1139 assert(!src.negate);
1140 assert(!src.abs);
1141 return value;
1142 }
1143
1144 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1145 LLVMIntPredicate pred, LLVMValueRef src0,
1146 LLVMValueRef src1)
1147 {
1148 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1149 return LLVMBuildSelect(ctx->builder, result,
1150 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1151 ctx->i32_0, "");
1152 }
1153
1154 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1155 LLVMRealPredicate pred, LLVMValueRef src0,
1156 LLVMValueRef src1)
1157 {
1158 LLVMValueRef result;
1159 src0 = ac_to_float(ctx, src0);
1160 src1 = ac_to_float(ctx, src1);
1161 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1162 return LLVMBuildSelect(ctx->builder, result,
1163 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1164 ctx->i32_0, "");
1165 }
1166
1167 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1168 const char *intrin,
1169 LLVMTypeRef result_type,
1170 LLVMValueRef src0)
1171 {
1172 char name[64];
1173 LLVMValueRef params[] = {
1174 ac_to_float(ctx, src0),
1175 };
1176
1177 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1178 get_elem_bits(ctx, result_type));
1179 assert(length < sizeof(name));
1180 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1181 }
1182
1183 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1184 const char *intrin,
1185 LLVMTypeRef result_type,
1186 LLVMValueRef src0, LLVMValueRef src1)
1187 {
1188 char name[64];
1189 LLVMValueRef params[] = {
1190 ac_to_float(ctx, src0),
1191 ac_to_float(ctx, src1),
1192 };
1193
1194 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1195 get_elem_bits(ctx, result_type));
1196 assert(length < sizeof(name));
1197 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1198 }
1199
1200 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1201 const char *intrin,
1202 LLVMTypeRef result_type,
1203 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1204 {
1205 char name[64];
1206 LLVMValueRef params[] = {
1207 ac_to_float(ctx, src0),
1208 ac_to_float(ctx, src1),
1209 ac_to_float(ctx, src2),
1210 };
1211
1212 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1213 get_elem_bits(ctx, result_type));
1214 assert(length < sizeof(name));
1215 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1216 }
1217
1218 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1219 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1220 {
1221 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1222 ctx->i32_0, "");
1223 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1224 }
1225
1226 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1227 LLVMIntPredicate pred,
1228 LLVMValueRef src0, LLVMValueRef src1)
1229 {
1230 return LLVMBuildSelect(ctx->builder,
1231 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1232 src0,
1233 src1, "");
1234
1235 }
1236 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1237 LLVMValueRef src0)
1238 {
1239 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1240 LLVMBuildNeg(ctx->builder, src0, ""));
1241 }
1242
1243 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1244 LLVMValueRef src0)
1245 {
1246 LLVMValueRef cmp, val;
1247
1248 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1249 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1250 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1251 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1252 return val;
1253 }
1254
1255 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1256 LLVMValueRef src0)
1257 {
1258 LLVMValueRef cmp, val;
1259
1260 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1261 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1262 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1263 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1264 return val;
1265 }
1266
1267 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1268 LLVMValueRef src0)
1269 {
1270 const char *intr = "llvm.floor.f32";
1271 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1272 LLVMValueRef params[] = {
1273 fsrc0,
1274 };
1275 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1276 ctx->f32, params, 1,
1277 AC_FUNC_ATTR_READNONE);
1278 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1279 }
1280
1281 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1282 const char *intrin,
1283 LLVMValueRef src0, LLVMValueRef src1)
1284 {
1285 LLVMTypeRef ret_type;
1286 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1287 LLVMValueRef res;
1288 LLVMValueRef params[] = { src0, src1 };
1289 ret_type = LLVMStructTypeInContext(ctx->context, types,
1290 2, true);
1291
1292 res = ac_build_intrinsic(ctx, intrin, ret_type,
1293 params, 2, AC_FUNC_ATTR_READNONE);
1294
1295 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1296 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1297 return res;
1298 }
1299
1300 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1301 LLVMValueRef src0)
1302 {
1303 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1304 }
1305
1306 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1307 LLVMValueRef src0)
1308 {
1309 src0 = ac_to_float(ctx, src0);
1310 return LLVMBuildSExt(ctx->builder,
1311 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1312 ctx->i32, "");
1313 }
1314
1315 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1316 LLVMValueRef src0)
1317 {
1318 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1319 }
1320
1321 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1322 LLVMValueRef src0)
1323 {
1324 return LLVMBuildSExt(ctx->builder,
1325 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1326 ctx->i32, "");
1327 }
1328
1329 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1330 LLVMValueRef src0)
1331 {
1332 LLVMValueRef result;
1333 LLVMValueRef cond = NULL;
1334
1335 src0 = ac_to_float(&ctx->ac, src0);
1336 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1337
1338 if (ctx->options->chip_class >= VI) {
1339 LLVMValueRef args[2];
1340 /* Check if the result is a denormal - and flush to 0 if so. */
1341 args[0] = result;
1342 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1343 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1344 }
1345
1346 /* need to convert back up to f32 */
1347 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1348
1349 if (ctx->options->chip_class >= VI)
1350 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1351 else {
1352 /* for SI/CIK */
1353 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1354 * so compare the result and flush to 0 if it's smaller.
1355 */
1356 LLVMValueRef temp, cond2;
1357 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1358 ctx->ac.f32, result);
1359 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1360 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1361 temp, "");
1362 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1363 temp, ctx->ac.f32_0, "");
1364 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1365 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1366 }
1367 return result;
1368 }
1369
1370 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1371 LLVMValueRef src0, LLVMValueRef src1)
1372 {
1373 LLVMValueRef dst64, result;
1374 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1375 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1376
1377 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1378 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1379 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1380 return result;
1381 }
1382
1383 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1384 LLVMValueRef src0, LLVMValueRef src1)
1385 {
1386 LLVMValueRef dst64, result;
1387 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1388 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1389
1390 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1391 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1392 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1393 return result;
1394 }
1395
1396 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1397 bool is_signed,
1398 const LLVMValueRef srcs[3])
1399 {
1400 LLVMValueRef result;
1401 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1402
1403 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1404 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1405 return result;
1406 }
1407
1408 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1409 LLVMValueRef src0, LLVMValueRef src1,
1410 LLVMValueRef src2, LLVMValueRef src3)
1411 {
1412 LLVMValueRef bfi_args[3], result;
1413
1414 bfi_args[0] = LLVMBuildShl(ctx->builder,
1415 LLVMBuildSub(ctx->builder,
1416 LLVMBuildShl(ctx->builder,
1417 ctx->i32_1,
1418 src3, ""),
1419 ctx->i32_1, ""),
1420 src2, "");
1421 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1422 bfi_args[2] = src0;
1423
1424 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1425
1426 /* Calculate:
1427 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1428 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1429 */
1430 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1431 LLVMBuildAnd(ctx->builder, bfi_args[0],
1432 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1433
1434 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1435 return result;
1436 }
1437
1438 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1439 LLVMValueRef src0)
1440 {
1441 LLVMValueRef comp[2];
1442
1443 src0 = ac_to_float(ctx, src0);
1444 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1445 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1446
1447 return ac_build_cvt_pkrtz_f16(ctx, comp);
1448 }
1449
1450 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1451 LLVMValueRef src0)
1452 {
1453 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1454 LLVMValueRef temps[2], result, val;
1455 int i;
1456
1457 for (i = 0; i < 2; i++) {
1458 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1459 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1460 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1461 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1462 }
1463
1464 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1465 ctx->i32_0, "");
1466 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1467 ctx->i32_1, "");
1468 return result;
1469 }
1470
1471 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1472 nir_op op,
1473 LLVMValueRef src0)
1474 {
1475 unsigned mask;
1476 int idx;
1477 LLVMValueRef result;
1478
1479 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1480 mask = AC_TID_MASK_LEFT;
1481 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1482 mask = AC_TID_MASK_TOP;
1483 else
1484 mask = AC_TID_MASK_TOP_LEFT;
1485
1486 /* for DDX we want to next X pixel, DDY next Y pixel. */
1487 if (op == nir_op_fddx_fine ||
1488 op == nir_op_fddx_coarse ||
1489 op == nir_op_fddx)
1490 idx = 1;
1491 else
1492 idx = 2;
1493
1494 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1495 return result;
1496 }
1497
1498 /*
1499 * this takes an I,J coordinate pair,
1500 * and works out the X and Y derivatives.
1501 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1502 */
1503 static LLVMValueRef emit_ddxy_interp(
1504 struct ac_nir_context *ctx,
1505 LLVMValueRef interp_ij)
1506 {
1507 LLVMValueRef result[4], a;
1508 unsigned i;
1509
1510 for (i = 0; i < 2; i++) {
1511 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1512 LLVMConstInt(ctx->ac.i32, i, false), "");
1513 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1514 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1515 }
1516 return ac_build_gather_values(&ctx->ac, result, 4);
1517 }
1518
1519 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1520 {
1521 LLVMValueRef src[4], result = NULL;
1522 unsigned num_components = instr->dest.dest.ssa.num_components;
1523 unsigned src_components;
1524 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1525
1526 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1527 switch (instr->op) {
1528 case nir_op_vec2:
1529 case nir_op_vec3:
1530 case nir_op_vec4:
1531 src_components = 1;
1532 break;
1533 case nir_op_pack_half_2x16:
1534 src_components = 2;
1535 break;
1536 case nir_op_unpack_half_2x16:
1537 src_components = 1;
1538 break;
1539 default:
1540 src_components = num_components;
1541 break;
1542 }
1543 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1544 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1545
1546 switch (instr->op) {
1547 case nir_op_fmov:
1548 case nir_op_imov:
1549 result = src[0];
1550 break;
1551 case nir_op_fneg:
1552 src[0] = ac_to_float(&ctx->ac, src[0]);
1553 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1554 break;
1555 case nir_op_ineg:
1556 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1557 break;
1558 case nir_op_inot:
1559 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1560 break;
1561 case nir_op_iadd:
1562 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1563 break;
1564 case nir_op_fadd:
1565 src[0] = ac_to_float(&ctx->ac, src[0]);
1566 src[1] = ac_to_float(&ctx->ac, src[1]);
1567 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1568 break;
1569 case nir_op_fsub:
1570 src[0] = ac_to_float(&ctx->ac, src[0]);
1571 src[1] = ac_to_float(&ctx->ac, src[1]);
1572 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1573 break;
1574 case nir_op_isub:
1575 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1576 break;
1577 case nir_op_imul:
1578 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1579 break;
1580 case nir_op_imod:
1581 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1582 break;
1583 case nir_op_umod:
1584 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1585 break;
1586 case nir_op_fmod:
1587 src[0] = ac_to_float(&ctx->ac, src[0]);
1588 src[1] = ac_to_float(&ctx->ac, src[1]);
1589 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1590 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1591 ac_to_float_type(&ctx->ac, def_type), result);
1592 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1593 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1594 break;
1595 case nir_op_frem:
1596 src[0] = ac_to_float(&ctx->ac, src[0]);
1597 src[1] = ac_to_float(&ctx->ac, src[1]);
1598 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1599 break;
1600 case nir_op_irem:
1601 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1602 break;
1603 case nir_op_idiv:
1604 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1605 break;
1606 case nir_op_udiv:
1607 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1608 break;
1609 case nir_op_fmul:
1610 src[0] = ac_to_float(&ctx->ac, src[0]);
1611 src[1] = ac_to_float(&ctx->ac, src[1]);
1612 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1613 break;
1614 case nir_op_fdiv:
1615 src[0] = ac_to_float(&ctx->ac, src[0]);
1616 src[1] = ac_to_float(&ctx->ac, src[1]);
1617 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1618 break;
1619 case nir_op_frcp:
1620 src[0] = ac_to_float(&ctx->ac, src[0]);
1621 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1622 break;
1623 case nir_op_iand:
1624 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1625 break;
1626 case nir_op_ior:
1627 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1628 break;
1629 case nir_op_ixor:
1630 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1631 break;
1632 case nir_op_ishl:
1633 result = LLVMBuildShl(ctx->ac.builder, src[0],
1634 LLVMBuildZExt(ctx->ac.builder, src[1],
1635 LLVMTypeOf(src[0]), ""),
1636 "");
1637 break;
1638 case nir_op_ishr:
1639 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1640 LLVMBuildZExt(ctx->ac.builder, src[1],
1641 LLVMTypeOf(src[0]), ""),
1642 "");
1643 break;
1644 case nir_op_ushr:
1645 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1646 LLVMBuildZExt(ctx->ac.builder, src[1],
1647 LLVMTypeOf(src[0]), ""),
1648 "");
1649 break;
1650 case nir_op_ilt:
1651 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1652 break;
1653 case nir_op_ine:
1654 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1655 break;
1656 case nir_op_ieq:
1657 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1658 break;
1659 case nir_op_ige:
1660 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1661 break;
1662 case nir_op_ult:
1663 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1664 break;
1665 case nir_op_uge:
1666 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1667 break;
1668 case nir_op_feq:
1669 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1670 break;
1671 case nir_op_fne:
1672 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1673 break;
1674 case nir_op_flt:
1675 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1676 break;
1677 case nir_op_fge:
1678 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1679 break;
1680 case nir_op_fabs:
1681 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1682 ac_to_float_type(&ctx->ac, def_type), src[0]);
1683 break;
1684 case nir_op_iabs:
1685 result = emit_iabs(&ctx->ac, src[0]);
1686 break;
1687 case nir_op_imax:
1688 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1689 break;
1690 case nir_op_imin:
1691 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1692 break;
1693 case nir_op_umax:
1694 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1695 break;
1696 case nir_op_umin:
1697 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1698 break;
1699 case nir_op_isign:
1700 result = emit_isign(&ctx->ac, src[0]);
1701 break;
1702 case nir_op_fsign:
1703 src[0] = ac_to_float(&ctx->ac, src[0]);
1704 result = emit_fsign(&ctx->ac, src[0]);
1705 break;
1706 case nir_op_ffloor:
1707 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1708 ac_to_float_type(&ctx->ac, def_type), src[0]);
1709 break;
1710 case nir_op_ftrunc:
1711 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1712 ac_to_float_type(&ctx->ac, def_type), src[0]);
1713 break;
1714 case nir_op_fceil:
1715 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1716 ac_to_float_type(&ctx->ac, def_type), src[0]);
1717 break;
1718 case nir_op_fround_even:
1719 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1720 ac_to_float_type(&ctx->ac, def_type),src[0]);
1721 break;
1722 case nir_op_ffract:
1723 result = emit_ffract(&ctx->ac, src[0]);
1724 break;
1725 case nir_op_fsin:
1726 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1727 ac_to_float_type(&ctx->ac, def_type), src[0]);
1728 break;
1729 case nir_op_fcos:
1730 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1731 ac_to_float_type(&ctx->ac, def_type), src[0]);
1732 break;
1733 case nir_op_fsqrt:
1734 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1735 ac_to_float_type(&ctx->ac, def_type), src[0]);
1736 break;
1737 case nir_op_fexp2:
1738 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1739 ac_to_float_type(&ctx->ac, def_type), src[0]);
1740 break;
1741 case nir_op_flog2:
1742 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1743 ac_to_float_type(&ctx->ac, def_type), src[0]);
1744 break;
1745 case nir_op_frsq:
1746 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1747 ac_to_float_type(&ctx->ac, def_type), src[0]);
1748 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1749 break;
1750 case nir_op_fpow:
1751 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1752 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1753 break;
1754 case nir_op_fmax:
1755 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1756 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1757 if (instr->dest.dest.ssa.bit_size == 32)
1758 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1759 ac_to_float_type(&ctx->ac, def_type),
1760 result);
1761 break;
1762 case nir_op_fmin:
1763 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1764 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1765 if (instr->dest.dest.ssa.bit_size == 32)
1766 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1767 ac_to_float_type(&ctx->ac, def_type),
1768 result);
1769 break;
1770 case nir_op_ffma:
1771 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1772 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1773 break;
1774 case nir_op_ibitfield_extract:
1775 result = emit_bitfield_extract(&ctx->ac, true, src);
1776 break;
1777 case nir_op_ubitfield_extract:
1778 result = emit_bitfield_extract(&ctx->ac, false, src);
1779 break;
1780 case nir_op_bitfield_insert:
1781 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1782 break;
1783 case nir_op_bitfield_reverse:
1784 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1785 break;
1786 case nir_op_bit_count:
1787 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1788 break;
1789 case nir_op_vec2:
1790 case nir_op_vec3:
1791 case nir_op_vec4:
1792 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1793 src[i] = ac_to_integer(&ctx->ac, src[i]);
1794 result = ac_build_gather_values(&ctx->ac, src, num_components);
1795 break;
1796 case nir_op_f2i32:
1797 case nir_op_f2i64:
1798 src[0] = ac_to_float(&ctx->ac, src[0]);
1799 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1800 break;
1801 case nir_op_f2u32:
1802 case nir_op_f2u64:
1803 src[0] = ac_to_float(&ctx->ac, src[0]);
1804 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1805 break;
1806 case nir_op_i2f32:
1807 case nir_op_i2f64:
1808 src[0] = ac_to_integer(&ctx->ac, src[0]);
1809 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1810 break;
1811 case nir_op_u2f32:
1812 case nir_op_u2f64:
1813 src[0] = ac_to_integer(&ctx->ac, src[0]);
1814 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1815 break;
1816 case nir_op_f2f64:
1817 src[0] = ac_to_float(&ctx->ac, src[0]);
1818 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1819 break;
1820 case nir_op_f2f32:
1821 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1822 break;
1823 case nir_op_u2u32:
1824 case nir_op_u2u64:
1825 src[0] = ac_to_integer(&ctx->ac, src[0]);
1826 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1827 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1828 else
1829 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1830 break;
1831 case nir_op_i2i32:
1832 case nir_op_i2i64:
1833 src[0] = ac_to_integer(&ctx->ac, src[0]);
1834 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1835 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1836 else
1837 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1838 break;
1839 case nir_op_bcsel:
1840 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1841 break;
1842 case nir_op_find_lsb:
1843 src[0] = ac_to_integer(&ctx->ac, src[0]);
1844 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1845 break;
1846 case nir_op_ufind_msb:
1847 src[0] = ac_to_integer(&ctx->ac, src[0]);
1848 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1849 break;
1850 case nir_op_ifind_msb:
1851 src[0] = ac_to_integer(&ctx->ac, src[0]);
1852 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1853 break;
1854 case nir_op_uadd_carry:
1855 src[0] = ac_to_integer(&ctx->ac, src[0]);
1856 src[1] = ac_to_integer(&ctx->ac, src[1]);
1857 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1858 break;
1859 case nir_op_usub_borrow:
1860 src[0] = ac_to_integer(&ctx->ac, src[0]);
1861 src[1] = ac_to_integer(&ctx->ac, src[1]);
1862 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1863 break;
1864 case nir_op_b2f:
1865 result = emit_b2f(&ctx->ac, src[0]);
1866 break;
1867 case nir_op_f2b:
1868 result = emit_f2b(&ctx->ac, src[0]);
1869 break;
1870 case nir_op_b2i:
1871 result = emit_b2i(&ctx->ac, src[0]);
1872 break;
1873 case nir_op_i2b:
1874 src[0] = ac_to_integer(&ctx->ac, src[0]);
1875 result = emit_i2b(&ctx->ac, src[0]);
1876 break;
1877 case nir_op_fquantize2f16:
1878 result = emit_f2f16(ctx->nctx, src[0]);
1879 break;
1880 case nir_op_umul_high:
1881 src[0] = ac_to_integer(&ctx->ac, src[0]);
1882 src[1] = ac_to_integer(&ctx->ac, src[1]);
1883 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1884 break;
1885 case nir_op_imul_high:
1886 src[0] = ac_to_integer(&ctx->ac, src[0]);
1887 src[1] = ac_to_integer(&ctx->ac, src[1]);
1888 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1889 break;
1890 case nir_op_pack_half_2x16:
1891 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1892 break;
1893 case nir_op_unpack_half_2x16:
1894 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1895 break;
1896 case nir_op_fddx:
1897 case nir_op_fddy:
1898 case nir_op_fddx_fine:
1899 case nir_op_fddy_fine:
1900 case nir_op_fddx_coarse:
1901 case nir_op_fddy_coarse:
1902 result = emit_ddxy(ctx, instr->op, src[0]);
1903 break;
1904
1905 case nir_op_unpack_64_2x32_split_x: {
1906 assert(instr->src[0].src.ssa->num_components == 1);
1907 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1908 ctx->ac.v2i32,
1909 "");
1910 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1911 ctx->ac.i32_0, "");
1912 break;
1913 }
1914
1915 case nir_op_unpack_64_2x32_split_y: {
1916 assert(instr->src[0].src.ssa->num_components == 1);
1917 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1918 ctx->ac.v2i32,
1919 "");
1920 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1921 ctx->ac.i32_1, "");
1922 break;
1923 }
1924
1925 case nir_op_pack_64_2x32_split: {
1926 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1927 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1928 src[0], ctx->ac.i32_0, "");
1929 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1930 src[1], ctx->ac.i32_1, "");
1931 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1932 break;
1933 }
1934
1935 default:
1936 fprintf(stderr, "Unknown NIR alu instr: ");
1937 nir_print_instr(&instr->instr, stderr);
1938 fprintf(stderr, "\n");
1939 abort();
1940 }
1941
1942 if (result) {
1943 assert(instr->dest.dest.is_ssa);
1944 result = ac_to_integer(&ctx->ac, result);
1945 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1946 result);
1947 }
1948 }
1949
1950 static void visit_load_const(struct ac_nir_context *ctx,
1951 const nir_load_const_instr *instr)
1952 {
1953 LLVMValueRef values[4], value = NULL;
1954 LLVMTypeRef element_type =
1955 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1956
1957 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1958 switch (instr->def.bit_size) {
1959 case 32:
1960 values[i] = LLVMConstInt(element_type,
1961 instr->value.u32[i], false);
1962 break;
1963 case 64:
1964 values[i] = LLVMConstInt(element_type,
1965 instr->value.u64[i], false);
1966 break;
1967 default:
1968 fprintf(stderr,
1969 "unsupported nir load_const bit_size: %d\n",
1970 instr->def.bit_size);
1971 abort();
1972 }
1973 }
1974 if (instr->def.num_components > 1) {
1975 value = LLVMConstVector(values, instr->def.num_components);
1976 } else
1977 value = values[0];
1978
1979 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1980 }
1981
1982 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1983 LLVMTypeRef type)
1984 {
1985 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1986 return LLVMBuildBitCast(ctx->builder, ptr,
1987 LLVMPointerType(type, addr_space), "");
1988 }
1989
1990 static LLVMValueRef
1991 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1992 {
1993 LLVMValueRef size =
1994 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1995 LLVMConstInt(ctx->ac.i32, 2, false), "");
1996
1997 /* VI only */
1998 if (ctx->ac.chip_class == VI && in_elements) {
1999 /* On VI, the descriptor contains the size in bytes,
2000 * but TXQ must return the size in elements.
2001 * The stride is always non-zero for resources using TXQ.
2002 */
2003 LLVMValueRef stride =
2004 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2005 ctx->ac.i32_1, "");
2006 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2007 LLVMConstInt(ctx->ac.i32, 16, false), "");
2008 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2009 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2010
2011 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2012 }
2013 return size;
2014 }
2015
2016 /**
2017 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2018 * intrinsic names).
2019 */
2020 static void build_int_type_name(
2021 LLVMTypeRef type,
2022 char *buf, unsigned bufsize)
2023 {
2024 assert(bufsize >= 6);
2025
2026 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2027 snprintf(buf, bufsize, "v%ui32",
2028 LLVMGetVectorSize(type));
2029 else
2030 strcpy(buf, "i32");
2031 }
2032
2033 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2034 struct ac_image_args *args,
2035 const nir_tex_instr *instr)
2036 {
2037 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2038 LLVMValueRef coord = args->addr;
2039 LLVMValueRef half_texel[2];
2040 LLVMValueRef compare_cube_wa = NULL;
2041 LLVMValueRef result;
2042 int c;
2043 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2044
2045 //TODO Rect
2046 {
2047 struct ac_image_args txq_args = { 0 };
2048
2049 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2050 txq_args.opcode = ac_image_get_resinfo;
2051 txq_args.dmask = 0xf;
2052 txq_args.addr = ctx->i32_0;
2053 txq_args.resource = args->resource;
2054 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2055
2056 for (c = 0; c < 2; c++) {
2057 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2058 LLVMConstInt(ctx->i32, c, false), "");
2059 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2060 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2061 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2062 LLVMConstReal(ctx->f32, -0.5), "");
2063 }
2064 }
2065
2066 LLVMValueRef orig_coords = args->addr;
2067
2068 for (c = 0; c < 2; c++) {
2069 LLVMValueRef tmp;
2070 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2071 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2072 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2073 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2074 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2075 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2076 }
2077
2078
2079 /*
2080 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2081 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2082 * workaround by sampling using a scaled type and converting.
2083 * This is taken from amdgpu-pro shaders.
2084 */
2085 /* NOTE this produces some ugly code compared to amdgpu-pro,
2086 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2087 * and then reads them back. -pro generates two selects,
2088 * one s_cmp for the descriptor rewriting
2089 * one v_cmp for the coordinate and result changes.
2090 */
2091 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2092 LLVMValueRef tmp, tmp2;
2093
2094 /* workaround 8/8/8/8 uint/sint cube gather bug */
2095 /* first detect it then change to a scaled read and f2i */
2096 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2097 tmp2 = tmp;
2098
2099 /* extract the DATA_FORMAT */
2100 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2101 LLVMConstInt(ctx->i32, 6, false), false);
2102
2103 /* is the DATA_FORMAT == 8_8_8_8 */
2104 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2105
2106 if (stype == GLSL_TYPE_UINT)
2107 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2108 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2109 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2110 else
2111 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2112 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2113 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2114
2115 /* replace the NUM FORMAT in the descriptor */
2116 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2117 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2118
2119 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2120
2121 /* don't modify the coordinates for this case */
2122 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2123 }
2124 args->addr = coord;
2125 result = ac_build_image_opcode(ctx, args);
2126
2127 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2128 LLVMValueRef tmp, tmp2;
2129
2130 /* if the cube workaround is in place, f2i the result. */
2131 for (c = 0; c < 4; c++) {
2132 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2133 if (stype == GLSL_TYPE_UINT)
2134 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2135 else
2136 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2137 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2138 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2139 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2140 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2141 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2142 }
2143 }
2144 return result;
2145 }
2146
2147 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2148 const nir_tex_instr *instr,
2149 bool lod_is_zero,
2150 struct ac_image_args *args)
2151 {
2152 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2153 return ac_build_buffer_load_format(&ctx->ac,
2154 args->resource,
2155 args->addr,
2156 ctx->ac.i32_0,
2157 true);
2158 }
2159
2160 args->opcode = ac_image_sample;
2161 args->compare = instr->is_shadow;
2162
2163 switch (instr->op) {
2164 case nir_texop_txf:
2165 case nir_texop_txf_ms:
2166 case nir_texop_samples_identical:
2167 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2168 args->compare = false;
2169 args->offset = false;
2170 break;
2171 case nir_texop_txb:
2172 args->bias = true;
2173 break;
2174 case nir_texop_txl:
2175 if (lod_is_zero)
2176 args->level_zero = true;
2177 else
2178 args->lod = true;
2179 break;
2180 case nir_texop_txs:
2181 case nir_texop_query_levels:
2182 args->opcode = ac_image_get_resinfo;
2183 break;
2184 case nir_texop_tex:
2185 if (ctx->stage != MESA_SHADER_FRAGMENT)
2186 args->level_zero = true;
2187 break;
2188 case nir_texop_txd:
2189 args->deriv = true;
2190 break;
2191 case nir_texop_tg4:
2192 args->opcode = ac_image_gather4;
2193 args->level_zero = true;
2194 break;
2195 case nir_texop_lod:
2196 args->opcode = ac_image_get_lod;
2197 args->compare = false;
2198 args->offset = false;
2199 break;
2200 default:
2201 break;
2202 }
2203
2204 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2205 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2206 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2207 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2208 }
2209 }
2210 return ac_build_image_opcode(&ctx->ac, args);
2211 }
2212
2213 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2214 nir_intrinsic_instr *instr)
2215 {
2216 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2217 unsigned desc_set = nir_intrinsic_desc_set(instr);
2218 unsigned binding = nir_intrinsic_binding(instr);
2219 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2220 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2221 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2222 unsigned base_offset = layout->binding[binding].offset;
2223 LLVMValueRef offset, stride;
2224
2225 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2226 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2227 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2228 layout->binding[binding].dynamic_offset_offset;
2229 desc_ptr = ctx->push_constants;
2230 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2231 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2232 } else
2233 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2234
2235 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2236 index = LLVMBuildMul(ctx->builder, index, stride, "");
2237 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2238
2239 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2240 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2241 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2242
2243 return desc_ptr;
2244 }
2245
2246 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2247 nir_intrinsic_instr *instr)
2248 {
2249 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2250 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2251
2252 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2253 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2254 return result;
2255 }
2256
2257 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2258 nir_intrinsic_instr *instr)
2259 {
2260 LLVMValueRef ptr, addr;
2261
2262 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2263 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2264
2265 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2266 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2267
2268 return LLVMBuildLoad(ctx->builder, ptr, "");
2269 }
2270
2271 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2272 const nir_intrinsic_instr *instr)
2273 {
2274 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2275
2276 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2277 }
2278 static void visit_store_ssbo(struct ac_nir_context *ctx,
2279 nir_intrinsic_instr *instr)
2280 {
2281 const char *store_name;
2282 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2283 LLVMTypeRef data_type = ctx->ac.f32;
2284 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2285 int components_32bit = elem_size_mult * instr->num_components;
2286 unsigned writemask = nir_intrinsic_write_mask(instr);
2287 LLVMValueRef base_data, base_offset;
2288 LLVMValueRef params[6];
2289
2290 params[1] = ctx->abi->load_ssbo(ctx->abi,
2291 get_src(ctx, instr->src[1]), true);
2292 params[2] = ctx->ac.i32_0; /* vindex */
2293 params[4] = ctx->ac.i1false; /* glc */
2294 params[5] = ctx->ac.i1false; /* slc */
2295
2296 if (components_32bit > 1)
2297 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2298
2299 base_data = ac_to_float(&ctx->ac, src_data);
2300 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2301 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2302 data_type, "");
2303 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2304 while (writemask) {
2305 int start, count;
2306 LLVMValueRef data;
2307 LLVMValueRef offset;
2308 LLVMValueRef tmp;
2309 u_bit_scan_consecutive_range(&writemask, &start, &count);
2310
2311 /* Due to an LLVM limitation, split 3-element writes
2312 * into a 2-element and a 1-element write. */
2313 if (count == 3) {
2314 writemask |= 1 << (start + 2);
2315 count = 2;
2316 }
2317
2318 start *= elem_size_mult;
2319 count *= elem_size_mult;
2320
2321 if (count > 4) {
2322 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2323 count = 4;
2324 }
2325
2326 if (count == 4) {
2327 store_name = "llvm.amdgcn.buffer.store.v4f32";
2328 data = base_data;
2329 } else if (count == 2) {
2330 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2331 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2332 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2333 ctx->ac.i32_0, "");
2334
2335 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2336 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2337 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2338 ctx->ac.i32_1, "");
2339 store_name = "llvm.amdgcn.buffer.store.v2f32";
2340
2341 } else {
2342 assert(count == 1);
2343 if (get_llvm_num_components(base_data) > 1)
2344 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2345 LLVMConstInt(ctx->ac.i32, start, false), "");
2346 else
2347 data = base_data;
2348 store_name = "llvm.amdgcn.buffer.store.f32";
2349 }
2350
2351 offset = base_offset;
2352 if (start != 0) {
2353 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2354 }
2355 params[0] = data;
2356 params[3] = offset;
2357 ac_build_intrinsic(&ctx->ac, store_name,
2358 ctx->ac.voidt, params, 6, 0);
2359 }
2360 }
2361
2362 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2363 const nir_intrinsic_instr *instr)
2364 {
2365 const char *name;
2366 LLVMValueRef params[6];
2367 int arg_count = 0;
2368
2369 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2370 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2371 }
2372 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2373 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2374 get_src(ctx, instr->src[0]),
2375 true);
2376 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2377 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2378 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2379
2380 switch (instr->intrinsic) {
2381 case nir_intrinsic_ssbo_atomic_add:
2382 name = "llvm.amdgcn.buffer.atomic.add";
2383 break;
2384 case nir_intrinsic_ssbo_atomic_imin:
2385 name = "llvm.amdgcn.buffer.atomic.smin";
2386 break;
2387 case nir_intrinsic_ssbo_atomic_umin:
2388 name = "llvm.amdgcn.buffer.atomic.umin";
2389 break;
2390 case nir_intrinsic_ssbo_atomic_imax:
2391 name = "llvm.amdgcn.buffer.atomic.smax";
2392 break;
2393 case nir_intrinsic_ssbo_atomic_umax:
2394 name = "llvm.amdgcn.buffer.atomic.umax";
2395 break;
2396 case nir_intrinsic_ssbo_atomic_and:
2397 name = "llvm.amdgcn.buffer.atomic.and";
2398 break;
2399 case nir_intrinsic_ssbo_atomic_or:
2400 name = "llvm.amdgcn.buffer.atomic.or";
2401 break;
2402 case nir_intrinsic_ssbo_atomic_xor:
2403 name = "llvm.amdgcn.buffer.atomic.xor";
2404 break;
2405 case nir_intrinsic_ssbo_atomic_exchange:
2406 name = "llvm.amdgcn.buffer.atomic.swap";
2407 break;
2408 case nir_intrinsic_ssbo_atomic_comp_swap:
2409 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2410 break;
2411 default:
2412 abort();
2413 }
2414
2415 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2416 }
2417
2418 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2419 const nir_intrinsic_instr *instr)
2420 {
2421 LLVMValueRef results[2];
2422 int load_components;
2423 int num_components = instr->num_components;
2424 if (instr->dest.ssa.bit_size == 64)
2425 num_components *= 2;
2426
2427 for (int i = 0; i < num_components; i += load_components) {
2428 load_components = MIN2(num_components - i, 4);
2429 const char *load_name;
2430 LLVMTypeRef data_type = ctx->ac.f32;
2431 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2432 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2433
2434 if (load_components == 3)
2435 data_type = LLVMVectorType(ctx->ac.f32, 4);
2436 else if (load_components > 1)
2437 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2438
2439 if (load_components >= 3)
2440 load_name = "llvm.amdgcn.buffer.load.v4f32";
2441 else if (load_components == 2)
2442 load_name = "llvm.amdgcn.buffer.load.v2f32";
2443 else if (load_components == 1)
2444 load_name = "llvm.amdgcn.buffer.load.f32";
2445 else
2446 unreachable("unhandled number of components");
2447
2448 LLVMValueRef params[] = {
2449 ctx->abi->load_ssbo(ctx->abi,
2450 get_src(ctx, instr->src[0]),
2451 false),
2452 ctx->ac.i32_0,
2453 offset,
2454 ctx->ac.i1false,
2455 ctx->ac.i1false,
2456 };
2457
2458 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2459
2460 }
2461
2462 assume(results[0]);
2463 LLVMValueRef ret = results[0];
2464 if (num_components > 4 || num_components == 3) {
2465 LLVMValueRef masks[] = {
2466 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2467 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2468 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2469 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2470 };
2471
2472 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2473 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2474 results[num_components > 4 ? 1 : 0], swizzle, "");
2475 }
2476
2477 return LLVMBuildBitCast(ctx->ac.builder, ret,
2478 get_def_type(ctx, &instr->dest.ssa), "");
2479 }
2480
2481 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2482 const nir_intrinsic_instr *instr)
2483 {
2484 LLVMValueRef results[8], ret;
2485 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2486 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2487 int num_components = instr->num_components;
2488
2489 if (ctx->abi->load_ubo)
2490 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2491
2492 if (instr->dest.ssa.bit_size == 64)
2493 num_components *= 2;
2494
2495 for (unsigned i = 0; i < num_components; ++i) {
2496 LLVMValueRef params[] = {
2497 rsrc,
2498 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2499 offset, "")
2500 };
2501 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2502 params, 2,
2503 AC_FUNC_ATTR_READNONE |
2504 AC_FUNC_ATTR_LEGACY);
2505 }
2506
2507
2508 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2509 return LLVMBuildBitCast(ctx->ac.builder, ret,
2510 get_def_type(ctx, &instr->dest.ssa), "");
2511 }
2512
2513 static void
2514 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2515 bool vs_in, unsigned *vertex_index_out,
2516 LLVMValueRef *vertex_index_ref,
2517 unsigned *const_out, LLVMValueRef *indir_out)
2518 {
2519 unsigned const_offset = 0;
2520 nir_deref *tail = &deref->deref;
2521 LLVMValueRef offset = NULL;
2522
2523 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2524 tail = tail->child;
2525 nir_deref_array *deref_array = nir_deref_as_array(tail);
2526 if (vertex_index_out)
2527 *vertex_index_out = deref_array->base_offset;
2528
2529 if (vertex_index_ref) {
2530 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2531 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2532 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2533 }
2534 *vertex_index_ref = vtx;
2535 }
2536 }
2537
2538 if (deref->var->data.compact) {
2539 assert(tail->child->deref_type == nir_deref_type_array);
2540 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2541 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2542 /* We always lower indirect dereferences for "compact" array vars. */
2543 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2544
2545 const_offset = deref_array->base_offset;
2546 goto out;
2547 }
2548
2549 while (tail->child != NULL) {
2550 const struct glsl_type *parent_type = tail->type;
2551 tail = tail->child;
2552
2553 if (tail->deref_type == nir_deref_type_array) {
2554 nir_deref_array *deref_array = nir_deref_as_array(tail);
2555 LLVMValueRef index, stride, local_offset;
2556 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2557
2558 const_offset += size * deref_array->base_offset;
2559 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2560 continue;
2561
2562 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2563 index = get_src(ctx, deref_array->indirect);
2564 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2565 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2566
2567 if (offset)
2568 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2569 else
2570 offset = local_offset;
2571 } else if (tail->deref_type == nir_deref_type_struct) {
2572 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2573
2574 for (unsigned i = 0; i < deref_struct->index; i++) {
2575 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2576 const_offset += glsl_count_attribute_slots(ft, vs_in);
2577 }
2578 } else
2579 unreachable("unsupported deref type");
2580
2581 }
2582 out:
2583 if (const_offset && offset)
2584 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2585 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2586 "");
2587
2588 *const_out = const_offset;
2589 *indir_out = offset;
2590 }
2591
2592
2593 /* The offchip buffer layout for TCS->TES is
2594 *
2595 * - attribute 0 of patch 0 vertex 0
2596 * - attribute 0 of patch 0 vertex 1
2597 * - attribute 0 of patch 0 vertex 2
2598 * ...
2599 * - attribute 0 of patch 1 vertex 0
2600 * - attribute 0 of patch 1 vertex 1
2601 * ...
2602 * - attribute 1 of patch 0 vertex 0
2603 * - attribute 1 of patch 0 vertex 1
2604 * ...
2605 * - per patch attribute 0 of patch 0
2606 * - per patch attribute 0 of patch 1
2607 * ...
2608 *
2609 * Note that every attribute has 4 components.
2610 */
2611 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2612 LLVMValueRef vertex_index,
2613 LLVMValueRef param_index)
2614 {
2615 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2616 LLVMValueRef param_stride, constant16;
2617 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2618
2619 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2620 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2621 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2622 num_patches, "");
2623
2624 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2625 if (vertex_index) {
2626 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2627 vertices_per_patch, "");
2628
2629 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2630 vertex_index, "");
2631
2632 param_stride = total_vertices;
2633 } else {
2634 base_addr = rel_patch_id;
2635 param_stride = num_patches;
2636 }
2637
2638 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2639 LLVMBuildMul(ctx->builder, param_index,
2640 param_stride, ""), "");
2641
2642 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2643
2644 if (!vertex_index) {
2645 LLVMValueRef patch_data_offset =
2646 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2647
2648 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2649 patch_data_offset, "");
2650 }
2651 return base_addr;
2652 }
2653
2654 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2655 unsigned param,
2656 unsigned const_index,
2657 bool is_compact,
2658 LLVMValueRef vertex_index,
2659 LLVMValueRef indir_index)
2660 {
2661 LLVMValueRef param_index;
2662
2663 if (indir_index)
2664 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2665 indir_index, "");
2666 else {
2667 if (const_index && !is_compact)
2668 param += const_index;
2669 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2670 }
2671 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2672 }
2673
2674 static void
2675 mark_tess_output(struct nir_to_llvm_context *ctx,
2676 bool is_patch, uint32_t param)
2677
2678 {
2679 if (is_patch) {
2680 ctx->tess_patch_outputs_written |= (1ull << param);
2681 } else
2682 ctx->tess_outputs_written |= (1ull << param);
2683 }
2684
2685 static LLVMValueRef
2686 get_dw_address(struct nir_to_llvm_context *ctx,
2687 LLVMValueRef dw_addr,
2688 unsigned param,
2689 unsigned const_index,
2690 bool compact_const_index,
2691 LLVMValueRef vertex_index,
2692 LLVMValueRef stride,
2693 LLVMValueRef indir_index)
2694
2695 {
2696
2697 if (vertex_index) {
2698 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2699 LLVMBuildMul(ctx->builder,
2700 vertex_index,
2701 stride, ""), "");
2702 }
2703
2704 if (indir_index)
2705 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2706 LLVMBuildMul(ctx->builder, indir_index,
2707 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2708 else if (const_index && !compact_const_index)
2709 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2710 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2711
2712 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2713 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2714
2715 if (const_index && compact_const_index)
2716 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2717 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2718 return dw_addr;
2719 }
2720
2721 static LLVMValueRef
2722 load_tcs_input(struct nir_to_llvm_context *ctx,
2723 nir_intrinsic_instr *instr)
2724 {
2725 LLVMValueRef dw_addr, stride;
2726 unsigned const_index;
2727 LLVMValueRef vertex_index;
2728 LLVMValueRef indir_index;
2729 unsigned param;
2730 LLVMValueRef value[4], result;
2731 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2732 const bool is_compact = instr->variables[0]->var->data.compact;
2733 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2734 get_deref_offset(ctx->nir, instr->variables[0],
2735 false, NULL, per_vertex ? &vertex_index : NULL,
2736 &const_index, &indir_index);
2737
2738 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2739 dw_addr = get_tcs_in_current_patch_offset(ctx);
2740 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2741 indir_index);
2742
2743 unsigned comp = instr->variables[0]->var->data.location_frac;
2744 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2745 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2746 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2747 ctx->ac.i32_1, "");
2748 }
2749 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2750 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2751 return result;
2752 }
2753
2754 static LLVMValueRef
2755 load_tcs_output(struct nir_to_llvm_context *ctx,
2756 nir_intrinsic_instr *instr)
2757 {
2758 LLVMValueRef dw_addr;
2759 LLVMValueRef stride = NULL;
2760 LLVMValueRef value[4], result;
2761 LLVMValueRef vertex_index = NULL;
2762 LLVMValueRef indir_index = NULL;
2763 unsigned const_index = 0;
2764 unsigned param;
2765 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2766 const bool is_compact = instr->variables[0]->var->data.compact;
2767 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2768 get_deref_offset(ctx->nir, instr->variables[0],
2769 false, NULL, per_vertex ? &vertex_index : NULL,
2770 &const_index, &indir_index);
2771
2772 if (!instr->variables[0]->var->data.patch) {
2773 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2774 dw_addr = get_tcs_out_current_patch_offset(ctx);
2775 } else {
2776 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2777 }
2778
2779 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2780 indir_index);
2781
2782 unsigned comp = instr->variables[0]->var->data.location_frac;
2783 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2784 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2785 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2786 ctx->ac.i32_1, "");
2787 }
2788 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2789 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2790 return result;
2791 }
2792
2793 static void
2794 store_tcs_output(struct nir_to_llvm_context *ctx,
2795 nir_intrinsic_instr *instr,
2796 LLVMValueRef src,
2797 unsigned writemask)
2798 {
2799 LLVMValueRef dw_addr;
2800 LLVMValueRef stride = NULL;
2801 LLVMValueRef buf_addr = NULL;
2802 LLVMValueRef vertex_index = NULL;
2803 LLVMValueRef indir_index = NULL;
2804 unsigned const_index = 0;
2805 unsigned param;
2806 const unsigned comp = instr->variables[0]->var->data.location_frac;
2807 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2808 const bool is_compact = instr->variables[0]->var->data.compact;
2809 bool store_lds = true;
2810
2811 if (instr->variables[0]->var->data.patch) {
2812 if (!(ctx->tcs_patch_outputs_read & (1U << (instr->variables[0]->var->data.location - VARYING_SLOT_PATCH0))))
2813 store_lds = false;
2814 } else {
2815 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2816 store_lds = false;
2817 }
2818 get_deref_offset(ctx->nir, instr->variables[0],
2819 false, NULL, per_vertex ? &vertex_index : NULL,
2820 &const_index, &indir_index);
2821
2822 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2823 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2824 is_compact && const_index > 3) {
2825 const_index -= 3;
2826 param++;
2827 }
2828
2829 if (!instr->variables[0]->var->data.patch) {
2830 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2831 dw_addr = get_tcs_out_current_patch_offset(ctx);
2832 } else {
2833 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2834 }
2835
2836 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2837
2838 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2839 indir_index);
2840 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2841 vertex_index, indir_index);
2842
2843 bool is_tess_factor = false;
2844 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2845 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2846 is_tess_factor = true;
2847
2848 unsigned base = is_compact ? const_index : 0;
2849 for (unsigned chan = 0; chan < 8; chan++) {
2850 if (!(writemask & (1 << chan)))
2851 continue;
2852 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2853
2854 if (store_lds || is_tess_factor)
2855 ac_lds_store(&ctx->ac, dw_addr, value);
2856
2857 if (!is_tess_factor && writemask != 0xF)
2858 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2859 buf_addr, ctx->oc_lds,
2860 4 * (base + chan), 1, 0, true, false);
2861
2862 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2863 ctx->ac.i32_1, "");
2864 }
2865
2866 if (writemask == 0xF) {
2867 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2868 buf_addr, ctx->oc_lds,
2869 (base * 4), 1, 0, true, false);
2870 }
2871 }
2872
2873 static LLVMValueRef
2874 load_tes_input(struct nir_to_llvm_context *ctx,
2875 const nir_intrinsic_instr *instr)
2876 {
2877 LLVMValueRef buf_addr;
2878 LLVMValueRef result;
2879 LLVMValueRef vertex_index = NULL;
2880 LLVMValueRef indir_index = NULL;
2881 unsigned const_index = 0;
2882 unsigned param;
2883 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2884 const bool is_compact = instr->variables[0]->var->data.compact;
2885
2886 get_deref_offset(ctx->nir, instr->variables[0],
2887 false, NULL, per_vertex ? &vertex_index : NULL,
2888 &const_index, &indir_index);
2889 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2890 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2891 is_compact && const_index > 3) {
2892 const_index -= 3;
2893 param++;
2894 }
2895
2896 unsigned comp = instr->variables[0]->var->data.location_frac;
2897 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2898 is_compact, vertex_index, indir_index);
2899
2900 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2901 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2902
2903 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2904 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2905 result = trim_vector(&ctx->ac, result, instr->num_components);
2906 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2907 return result;
2908 }
2909
2910 static LLVMValueRef
2911 load_gs_input(struct ac_shader_abi *abi,
2912 unsigned location,
2913 unsigned driver_location,
2914 unsigned component,
2915 unsigned num_components,
2916 unsigned vertex_index,
2917 unsigned const_index,
2918 LLVMTypeRef type)
2919 {
2920 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2921 LLVMValueRef vtx_offset;
2922 LLVMValueRef args[9];
2923 unsigned param, vtx_offset_param;
2924 LLVMValueRef value[4], result;
2925
2926 vtx_offset_param = vertex_index;
2927 assert(vtx_offset_param < 6);
2928 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2929 LLVMConstInt(ctx->ac.i32, 4, false), "");
2930
2931 param = shader_io_get_unique_index(location);
2932
2933 for (unsigned i = component; i < num_components + component; i++) {
2934 if (ctx->ac.chip_class >= GFX9) {
2935 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2936 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2937 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2938 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2939 } else {
2940 args[0] = ctx->esgs_ring;
2941 args[1] = vtx_offset;
2942 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
2943 args[3] = ctx->ac.i32_0;
2944 args[4] = ctx->ac.i32_1; /* OFFEN */
2945 args[5] = ctx->ac.i32_0; /* IDXEN */
2946 args[6] = ctx->ac.i32_1; /* GLC */
2947 args[7] = ctx->ac.i32_0; /* SLC */
2948 args[8] = ctx->ac.i32_0; /* TFE */
2949
2950 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2951 ctx->ac.i32, args, 9,
2952 AC_FUNC_ATTR_READONLY |
2953 AC_FUNC_ATTR_LEGACY);
2954 }
2955 }
2956 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2957
2958 return result;
2959 }
2960
2961 static LLVMValueRef
2962 build_gep_for_deref(struct ac_nir_context *ctx,
2963 nir_deref_var *deref)
2964 {
2965 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2966 assert(entry->data);
2967 LLVMValueRef val = entry->data;
2968 nir_deref *tail = deref->deref.child;
2969 while (tail != NULL) {
2970 LLVMValueRef offset;
2971 switch (tail->deref_type) {
2972 case nir_deref_type_array: {
2973 nir_deref_array *array = nir_deref_as_array(tail);
2974 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2975 if (array->deref_array_type ==
2976 nir_deref_array_type_indirect) {
2977 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2978 get_src(ctx,
2979 array->indirect),
2980 "");
2981 }
2982 break;
2983 }
2984 case nir_deref_type_struct: {
2985 nir_deref_struct *deref_struct =
2986 nir_deref_as_struct(tail);
2987 offset = LLVMConstInt(ctx->ac.i32,
2988 deref_struct->index, 0);
2989 break;
2990 }
2991 default:
2992 unreachable("bad deref type");
2993 }
2994 val = ac_build_gep0(&ctx->ac, val, offset);
2995 tail = tail->child;
2996 }
2997 return val;
2998 }
2999
3000 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3001 nir_intrinsic_instr *instr)
3002 {
3003 LLVMValueRef values[8];
3004 int idx = instr->variables[0]->var->data.driver_location;
3005 int ve = instr->dest.ssa.num_components;
3006 unsigned comp = instr->variables[0]->var->data.location_frac;
3007 LLVMValueRef indir_index;
3008 LLVMValueRef ret;
3009 unsigned const_index;
3010 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3011 instr->variables[0]->var->data.mode == nir_var_shader_in;
3012 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3013 &const_index, &indir_index);
3014
3015 if (instr->dest.ssa.bit_size == 64)
3016 ve *= 2;
3017
3018 switch (instr->variables[0]->var->data.mode) {
3019 case nir_var_shader_in:
3020 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3021 return load_tcs_input(ctx->nctx, instr);
3022 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3023 return load_tes_input(ctx->nctx, instr);
3024 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3025 LLVMValueRef indir_index;
3026 unsigned const_index, vertex_index;
3027 get_deref_offset(ctx, instr->variables[0],
3028 false, &vertex_index, NULL,
3029 &const_index, &indir_index);
3030 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3031 instr->variables[0]->var->data.driver_location,
3032 instr->variables[0]->var->data.location_frac, ve,
3033 vertex_index, const_index,
3034 nir2llvmtype(ctx, instr->variables[0]->var->type));
3035 }
3036
3037 for (unsigned chan = comp; chan < ve + comp; chan++) {
3038 if (indir_index) {
3039 unsigned count = glsl_count_attribute_slots(
3040 instr->variables[0]->var->type,
3041 ctx->stage == MESA_SHADER_VERTEX);
3042 count -= chan / 4;
3043 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3044 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3045 4, false, true);
3046
3047 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3048 tmp_vec,
3049 indir_index, "");
3050 } else
3051 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3052 }
3053 break;
3054 case nir_var_local:
3055 for (unsigned chan = 0; chan < ve; chan++) {
3056 if (indir_index) {
3057 unsigned count = glsl_count_attribute_slots(
3058 instr->variables[0]->var->type, false);
3059 count -= chan / 4;
3060 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3061 &ctx->ac, ctx->locals + idx + chan, count,
3062 4, true, true);
3063
3064 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3065 tmp_vec,
3066 indir_index, "");
3067 } else {
3068 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3069 }
3070 }
3071 break;
3072 case nir_var_shared: {
3073 LLVMValueRef address = build_gep_for_deref(ctx,
3074 instr->variables[0]);
3075 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3076 return LLVMBuildBitCast(ctx->ac.builder, val,
3077 get_def_type(ctx, &instr->dest.ssa),
3078 "");
3079 }
3080 case nir_var_shader_out:
3081 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3082 return load_tcs_output(ctx->nctx, instr);
3083
3084 for (unsigned chan = comp; chan < ve + comp; chan++) {
3085 if (indir_index) {
3086 unsigned count = glsl_count_attribute_slots(
3087 instr->variables[0]->var->type, false);
3088 count -= chan / 4;
3089 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3090 &ctx->ac, ctx->outputs + idx + chan, count,
3091 4, true, true);
3092
3093 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3094 tmp_vec,
3095 indir_index, "");
3096 } else {
3097 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3098 ctx->outputs[idx + chan + const_index * 4],
3099 "");
3100 }
3101 }
3102 break;
3103 default:
3104 unreachable("unhandle variable mode");
3105 }
3106 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3107 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3108 }
3109
3110 static void
3111 visit_store_var(struct ac_nir_context *ctx,
3112 nir_intrinsic_instr *instr)
3113 {
3114 LLVMValueRef temp_ptr, value;
3115 int idx = instr->variables[0]->var->data.driver_location;
3116 unsigned comp = instr->variables[0]->var->data.location_frac;
3117 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3118 int writemask = instr->const_index[0] << comp;
3119 LLVMValueRef indir_index;
3120 unsigned const_index;
3121 get_deref_offset(ctx, instr->variables[0], false,
3122 NULL, NULL, &const_index, &indir_index);
3123
3124 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3125 int old_writemask = writemask;
3126
3127 src = LLVMBuildBitCast(ctx->ac.builder, src,
3128 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3129 "");
3130
3131 writemask = 0;
3132 for (unsigned chan = 0; chan < 4; chan++) {
3133 if (old_writemask & (1 << chan))
3134 writemask |= 3u << (2 * chan);
3135 }
3136 }
3137
3138 switch (instr->variables[0]->var->data.mode) {
3139 case nir_var_shader_out:
3140
3141 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3142 store_tcs_output(ctx->nctx, instr, src, writemask);
3143 return;
3144 }
3145
3146 for (unsigned chan = 0; chan < 8; chan++) {
3147 int stride = 4;
3148 if (!(writemask & (1 << chan)))
3149 continue;
3150
3151 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3152
3153 if (instr->variables[0]->var->data.compact)
3154 stride = 1;
3155 if (indir_index) {
3156 unsigned count = glsl_count_attribute_slots(
3157 instr->variables[0]->var->type, false);
3158 count -= chan / 4;
3159 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3160 &ctx->ac, ctx->outputs + idx + chan, count,
3161 stride, true, true);
3162
3163 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3164 value, indir_index, "");
3165 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3166 count, stride, tmp_vec);
3167
3168 } else {
3169 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3170
3171 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3172 }
3173 }
3174 break;
3175 case nir_var_local:
3176 for (unsigned chan = 0; chan < 8; chan++) {
3177 if (!(writemask & (1 << chan)))
3178 continue;
3179
3180 value = llvm_extract_elem(&ctx->ac, src, chan);
3181 if (indir_index) {
3182 unsigned count = glsl_count_attribute_slots(
3183 instr->variables[0]->var->type, false);
3184 count -= chan / 4;
3185 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3186 &ctx->ac, ctx->locals + idx + chan, count,
3187 4, true, true);
3188
3189 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3190 value, indir_index, "");
3191 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3192 count, 4, tmp_vec);
3193 } else {
3194 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3195
3196 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3197 }
3198 }
3199 break;
3200 case nir_var_shared: {
3201 int writemask = instr->const_index[0];
3202 LLVMValueRef address = build_gep_for_deref(ctx,
3203 instr->variables[0]);
3204 LLVMValueRef val = get_src(ctx, instr->src[0]);
3205 unsigned components =
3206 glsl_get_vector_elements(
3207 nir_deref_tail(&instr->variables[0]->deref)->type);
3208 if (writemask == (1 << components) - 1) {
3209 val = LLVMBuildBitCast(
3210 ctx->ac.builder, val,
3211 LLVMGetElementType(LLVMTypeOf(address)), "");
3212 LLVMBuildStore(ctx->ac.builder, val, address);
3213 } else {
3214 for (unsigned chan = 0; chan < 4; chan++) {
3215 if (!(writemask & (1 << chan)))
3216 continue;
3217 LLVMValueRef ptr =
3218 LLVMBuildStructGEP(ctx->ac.builder,
3219 address, chan, "");
3220 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3221 chan);
3222 src = LLVMBuildBitCast(
3223 ctx->ac.builder, src,
3224 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3225 LLVMBuildStore(ctx->ac.builder, src, ptr);
3226 }
3227 }
3228 break;
3229 }
3230 default:
3231 break;
3232 }
3233 }
3234
3235 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3236 {
3237 switch (dim) {
3238 case GLSL_SAMPLER_DIM_BUF:
3239 return 1;
3240 case GLSL_SAMPLER_DIM_1D:
3241 return array ? 2 : 1;
3242 case GLSL_SAMPLER_DIM_2D:
3243 return array ? 3 : 2;
3244 case GLSL_SAMPLER_DIM_MS:
3245 return array ? 4 : 3;
3246 case GLSL_SAMPLER_DIM_3D:
3247 case GLSL_SAMPLER_DIM_CUBE:
3248 return 3;
3249 case GLSL_SAMPLER_DIM_RECT:
3250 case GLSL_SAMPLER_DIM_SUBPASS:
3251 return 2;
3252 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3253 return 3;
3254 default:
3255 break;
3256 }
3257 return 0;
3258 }
3259
3260
3261
3262 /* Adjust the sample index according to FMASK.
3263 *
3264 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3265 * which is the identity mapping. Each nibble says which physical sample
3266 * should be fetched to get that sample.
3267 *
3268 * For example, 0x11111100 means there are only 2 samples stored and
3269 * the second sample covers 3/4 of the pixel. When reading samples 0
3270 * and 1, return physical sample 0 (determined by the first two 0s
3271 * in FMASK), otherwise return physical sample 1.
3272 *
3273 * The sample index should be adjusted as follows:
3274 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3275 */
3276 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3277 LLVMValueRef coord_x, LLVMValueRef coord_y,
3278 LLVMValueRef coord_z,
3279 LLVMValueRef sample_index,
3280 LLVMValueRef fmask_desc_ptr)
3281 {
3282 LLVMValueRef fmask_load_address[4];
3283 LLVMValueRef res;
3284
3285 fmask_load_address[0] = coord_x;
3286 fmask_load_address[1] = coord_y;
3287 if (coord_z) {
3288 fmask_load_address[2] = coord_z;
3289 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3290 }
3291
3292 struct ac_image_args args = {0};
3293
3294 args.opcode = ac_image_load;
3295 args.da = coord_z ? true : false;
3296 args.resource = fmask_desc_ptr;
3297 args.dmask = 0xf;
3298 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3299
3300 res = ac_build_image_opcode(ctx, &args);
3301
3302 res = ac_to_integer(ctx, res);
3303 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3304 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3305
3306 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3307 res,
3308 ctx->i32_0, "");
3309
3310 LLVMValueRef sample_index4 =
3311 LLVMBuildMul(ctx->builder, sample_index, four, "");
3312 LLVMValueRef shifted_fmask =
3313 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3314 LLVMValueRef final_sample =
3315 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3316
3317 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3318 * resource descriptor is 0 (invalid),
3319 */
3320 LLVMValueRef fmask_desc =
3321 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3322 ctx->v8i32, "");
3323
3324 LLVMValueRef fmask_word1 =
3325 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3326 ctx->i32_1, "");
3327
3328 LLVMValueRef word1_is_nonzero =
3329 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3330 fmask_word1, ctx->i32_0, "");
3331
3332 /* Replace the MSAA sample index. */
3333 sample_index =
3334 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3335 final_sample, sample_index, "");
3336 return sample_index;
3337 }
3338
3339 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3340 const nir_intrinsic_instr *instr)
3341 {
3342 const struct glsl_type *type = instr->variables[0]->var->type;
3343 if(instr->variables[0]->deref.child)
3344 type = instr->variables[0]->deref.child->type;
3345
3346 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3347 LLVMValueRef coords[4];
3348 LLVMValueRef masks[] = {
3349 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3350 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3351 };
3352 LLVMValueRef res;
3353 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3354
3355 int count;
3356 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3357 bool is_array = glsl_sampler_type_is_array(type);
3358 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3359 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3360 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3361 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3362 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3363 count = image_type_to_components_count(dim, is_array);
3364
3365 if (is_ms) {
3366 LLVMValueRef fmask_load_address[3];
3367 int chan;
3368
3369 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3370 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3371 if (is_array)
3372 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3373 else
3374 fmask_load_address[2] = NULL;
3375 if (add_frag_pos) {
3376 for (chan = 0; chan < 2; ++chan)
3377 fmask_load_address[chan] =
3378 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3379 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3380 ctx->ac.i32, ""), "");
3381 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3382 }
3383 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3384 fmask_load_address[0],
3385 fmask_load_address[1],
3386 fmask_load_address[2],
3387 sample_index,
3388 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3389 }
3390 if (count == 1 && !gfx9_1d) {
3391 if (instr->src[0].ssa->num_components)
3392 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3393 else
3394 res = src0;
3395 } else {
3396 int chan;
3397 if (is_ms)
3398 count--;
3399 for (chan = 0; chan < count; ++chan) {
3400 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3401 }
3402 if (add_frag_pos) {
3403 for (chan = 0; chan < 2; ++chan)
3404 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3405 ctx->ac.i32, ""), "");
3406 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3407 count++;
3408 }
3409
3410 if (gfx9_1d) {
3411 if (is_array) {
3412 coords[2] = coords[1];
3413 coords[1] = ctx->ac.i32_0;
3414 } else
3415 coords[1] = ctx->ac.i32_0;
3416 count++;
3417 }
3418
3419 if (is_ms) {
3420 coords[count] = sample_index;
3421 count++;
3422 }
3423
3424 if (count == 3) {
3425 coords[3] = LLVMGetUndef(ctx->ac.i32);
3426 count = 4;
3427 }
3428 res = ac_build_gather_values(&ctx->ac, coords, count);
3429 }
3430 return res;
3431 }
3432
3433 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3434 const nir_intrinsic_instr *instr)
3435 {
3436 LLVMValueRef params[7];
3437 LLVMValueRef res;
3438 char intrinsic_name[64];
3439 const nir_variable *var = instr->variables[0]->var;
3440 const struct glsl_type *type = var->type;
3441
3442 if(instr->variables[0]->deref.child)
3443 type = instr->variables[0]->deref.child->type;
3444
3445 type = glsl_without_array(type);
3446 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3447 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3448 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3449 ctx->ac.i32_0, ""); /* vindex */
3450 params[2] = ctx->ac.i32_0; /* voffset */
3451 params[3] = ctx->ac.i1false; /* glc */
3452 params[4] = ctx->ac.i1false; /* slc */
3453 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3454 params, 5, 0);
3455
3456 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3457 res = ac_to_integer(&ctx->ac, res);
3458 } else {
3459 bool is_da = glsl_sampler_type_is_array(type) ||
3460 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3461 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3462 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3463 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3464 LLVMValueRef glc = ctx->ac.i1false;
3465 LLVMValueRef slc = ctx->ac.i1false;
3466
3467 params[0] = get_image_coords(ctx, instr);
3468 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3469 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3470 if (HAVE_LLVM <= 0x0309) {
3471 params[3] = ctx->ac.i1false; /* r128 */
3472 params[4] = da;
3473 params[5] = glc;
3474 params[6] = slc;
3475 } else {
3476 LLVMValueRef lwe = ctx->ac.i1false;
3477 params[3] = glc;
3478 params[4] = slc;
3479 params[5] = lwe;
3480 params[6] = da;
3481 }
3482
3483 ac_get_image_intr_name("llvm.amdgcn.image.load",
3484 ctx->ac.v4f32, /* vdata */
3485 LLVMTypeOf(params[0]), /* coords */
3486 LLVMTypeOf(params[1]), /* rsrc */
3487 intrinsic_name, sizeof(intrinsic_name));
3488
3489 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3490 params, 7, AC_FUNC_ATTR_READONLY);
3491 }
3492 return ac_to_integer(&ctx->ac, res);
3493 }
3494
3495 static void visit_image_store(struct ac_nir_context *ctx,
3496 nir_intrinsic_instr *instr)
3497 {
3498 LLVMValueRef params[8];
3499 char intrinsic_name[64];
3500 const nir_variable *var = instr->variables[0]->var;
3501 const struct glsl_type *type = glsl_without_array(var->type);
3502 LLVMValueRef glc = ctx->ac.i1false;
3503 bool force_glc = ctx->ac.chip_class == SI;
3504 if (force_glc)
3505 glc = ctx->ac.i1true;
3506
3507 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3508 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3509 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3510 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3511 ctx->ac.i32_0, ""); /* vindex */
3512 params[3] = ctx->ac.i32_0; /* voffset */
3513 params[4] = glc; /* glc */
3514 params[5] = ctx->ac.i1false; /* slc */
3515 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3516 params, 6, 0);
3517 } else {
3518 bool is_da = glsl_sampler_type_is_array(type) ||
3519 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3520 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3521 LLVMValueRef slc = ctx->ac.i1false;
3522
3523 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3524 params[1] = get_image_coords(ctx, instr); /* coords */
3525 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3526 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3527 if (HAVE_LLVM <= 0x0309) {
3528 params[4] = ctx->ac.i1false; /* r128 */
3529 params[5] = da;
3530 params[6] = glc;
3531 params[7] = slc;
3532 } else {
3533 LLVMValueRef lwe = ctx->ac.i1false;
3534 params[4] = glc;
3535 params[5] = slc;
3536 params[6] = lwe;
3537 params[7] = da;
3538 }
3539
3540 ac_get_image_intr_name("llvm.amdgcn.image.store",
3541 LLVMTypeOf(params[0]), /* vdata */
3542 LLVMTypeOf(params[1]), /* coords */
3543 LLVMTypeOf(params[2]), /* rsrc */
3544 intrinsic_name, sizeof(intrinsic_name));
3545
3546 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3547 params, 8, 0);
3548 }
3549
3550 }
3551
3552 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3553 const nir_intrinsic_instr *instr)
3554 {
3555 LLVMValueRef params[7];
3556 int param_count = 0;
3557 const nir_variable *var = instr->variables[0]->var;
3558
3559 const char *atomic_name;
3560 char intrinsic_name[41];
3561 const struct glsl_type *type = glsl_without_array(var->type);
3562 MAYBE_UNUSED int length;
3563
3564 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3565
3566 switch (instr->intrinsic) {
3567 case nir_intrinsic_image_atomic_add:
3568 atomic_name = "add";
3569 break;
3570 case nir_intrinsic_image_atomic_min:
3571 atomic_name = is_unsigned ? "umin" : "smin";
3572 break;
3573 case nir_intrinsic_image_atomic_max:
3574 atomic_name = is_unsigned ? "umax" : "smax";
3575 break;
3576 case nir_intrinsic_image_atomic_and:
3577 atomic_name = "and";
3578 break;
3579 case nir_intrinsic_image_atomic_or:
3580 atomic_name = "or";
3581 break;
3582 case nir_intrinsic_image_atomic_xor:
3583 atomic_name = "xor";
3584 break;
3585 case nir_intrinsic_image_atomic_exchange:
3586 atomic_name = "swap";
3587 break;
3588 case nir_intrinsic_image_atomic_comp_swap:
3589 atomic_name = "cmpswap";
3590 break;
3591 default:
3592 abort();
3593 }
3594
3595 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3596 params[param_count++] = get_src(ctx, instr->src[3]);
3597 params[param_count++] = get_src(ctx, instr->src[2]);
3598
3599 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3600 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3601 NULL, true, true);
3602 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3603 ctx->ac.i32_0, ""); /* vindex */
3604 params[param_count++] = ctx->ac.i32_0; /* voffset */
3605 params[param_count++] = ctx->ac.i1false; /* slc */
3606
3607 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3608 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3609 } else {
3610 char coords_type[8];
3611
3612 bool da = glsl_sampler_type_is_array(type) ||
3613 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3614
3615 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3616 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3617 NULL, true, true);
3618 params[param_count++] = ctx->ac.i1false; /* r128 */
3619 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3620 params[param_count++] = ctx->ac.i1false; /* slc */
3621
3622 build_int_type_name(LLVMTypeOf(coords),
3623 coords_type, sizeof(coords_type));
3624
3625 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3626 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3627 }
3628
3629 assert(length < sizeof(intrinsic_name));
3630 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3631 }
3632
3633 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3634 const nir_intrinsic_instr *instr)
3635 {
3636 LLVMValueRef res;
3637 const nir_variable *var = instr->variables[0]->var;
3638 const struct glsl_type *type = instr->variables[0]->var->type;
3639 bool da = glsl_sampler_type_is_array(var->type) ||
3640 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3641 if(instr->variables[0]->deref.child)
3642 type = instr->variables[0]->deref.child->type;
3643
3644 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3645 return get_buffer_size(ctx,
3646 get_sampler_desc(ctx, instr->variables[0],
3647 AC_DESC_BUFFER, NULL, true, false), true);
3648
3649 struct ac_image_args args = { 0 };
3650
3651 args.da = da;
3652 args.dmask = 0xf;
3653 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3654 args.opcode = ac_image_get_resinfo;
3655 args.addr = ctx->ac.i32_0;
3656
3657 res = ac_build_image_opcode(&ctx->ac, &args);
3658
3659 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3660
3661 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3662 glsl_sampler_type_is_array(type)) {
3663 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3664 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3665 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3666 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3667 }
3668 if (ctx->ac.chip_class >= GFX9 &&
3669 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3670 glsl_sampler_type_is_array(type)) {
3671 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3672 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3673 ctx->ac.i32_1, "");
3674
3675 }
3676 return res;
3677 }
3678
3679 #define NOOP_WAITCNT 0xf7f
3680 #define LGKM_CNT 0x07f
3681 #define VM_CNT 0xf70
3682
3683 static void emit_membar(struct nir_to_llvm_context *ctx,
3684 const nir_intrinsic_instr *instr)
3685 {
3686 unsigned waitcnt = NOOP_WAITCNT;
3687
3688 switch (instr->intrinsic) {
3689 case nir_intrinsic_memory_barrier:
3690 case nir_intrinsic_group_memory_barrier:
3691 waitcnt &= VM_CNT & LGKM_CNT;
3692 break;
3693 case nir_intrinsic_memory_barrier_atomic_counter:
3694 case nir_intrinsic_memory_barrier_buffer:
3695 case nir_intrinsic_memory_barrier_image:
3696 waitcnt &= VM_CNT;
3697 break;
3698 case nir_intrinsic_memory_barrier_shared:
3699 waitcnt &= LGKM_CNT;
3700 break;
3701 default:
3702 break;
3703 }
3704 if (waitcnt != NOOP_WAITCNT)
3705 ac_build_waitcnt(&ctx->ac, waitcnt);
3706 }
3707
3708 static void emit_barrier(struct nir_to_llvm_context *ctx)
3709 {
3710 /* SI only (thanks to a hw bug workaround):
3711 * The real barrier instruction isn’t needed, because an entire patch
3712 * always fits into a single wave.
3713 */
3714 if (ctx->options->chip_class == SI &&
3715 ctx->stage == MESA_SHADER_TESS_CTRL) {
3716 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3717 return;
3718 }
3719 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3720 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3721 }
3722
3723 static void emit_discard_if(struct ac_nir_context *ctx,
3724 const nir_intrinsic_instr *instr)
3725 {
3726 LLVMValueRef cond;
3727
3728 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3729 get_src(ctx, instr->src[0]),
3730 ctx->ac.i32_0, "");
3731 ac_build_kill_if_false(&ctx->ac, cond);
3732 }
3733
3734 static LLVMValueRef
3735 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3736 {
3737 LLVMValueRef result;
3738 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3739 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3740 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3741
3742 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3743 }
3744
3745 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3746 const nir_intrinsic_instr *instr)
3747 {
3748 LLVMValueRef ptr, result;
3749 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3750 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3751
3752 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3753 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3754 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3755 ptr, src, src1,
3756 LLVMAtomicOrderingSequentiallyConsistent,
3757 LLVMAtomicOrderingSequentiallyConsistent,
3758 false);
3759 } else {
3760 LLVMAtomicRMWBinOp op;
3761 switch (instr->intrinsic) {
3762 case nir_intrinsic_var_atomic_add:
3763 op = LLVMAtomicRMWBinOpAdd;
3764 break;
3765 case nir_intrinsic_var_atomic_umin:
3766 op = LLVMAtomicRMWBinOpUMin;
3767 break;
3768 case nir_intrinsic_var_atomic_umax:
3769 op = LLVMAtomicRMWBinOpUMax;
3770 break;
3771 case nir_intrinsic_var_atomic_imin:
3772 op = LLVMAtomicRMWBinOpMin;
3773 break;
3774 case nir_intrinsic_var_atomic_imax:
3775 op = LLVMAtomicRMWBinOpMax;
3776 break;
3777 case nir_intrinsic_var_atomic_and:
3778 op = LLVMAtomicRMWBinOpAnd;
3779 break;
3780 case nir_intrinsic_var_atomic_or:
3781 op = LLVMAtomicRMWBinOpOr;
3782 break;
3783 case nir_intrinsic_var_atomic_xor:
3784 op = LLVMAtomicRMWBinOpXor;
3785 break;
3786 case nir_intrinsic_var_atomic_exchange:
3787 op = LLVMAtomicRMWBinOpXchg;
3788 break;
3789 default:
3790 return NULL;
3791 }
3792
3793 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3794 LLVMAtomicOrderingSequentiallyConsistent,
3795 false);
3796 }
3797 return result;
3798 }
3799
3800 #define INTERP_CENTER 0
3801 #define INTERP_CENTROID 1
3802 #define INTERP_SAMPLE 2
3803
3804 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3805 enum glsl_interp_mode interp, unsigned location)
3806 {
3807 switch (interp) {
3808 case INTERP_MODE_FLAT:
3809 default:
3810 return NULL;
3811 case INTERP_MODE_SMOOTH:
3812 case INTERP_MODE_NONE:
3813 if (location == INTERP_CENTER)
3814 return ctx->persp_center;
3815 else if (location == INTERP_CENTROID)
3816 return ctx->persp_centroid;
3817 else if (location == INTERP_SAMPLE)
3818 return ctx->persp_sample;
3819 break;
3820 case INTERP_MODE_NOPERSPECTIVE:
3821 if (location == INTERP_CENTER)
3822 return ctx->linear_center;
3823 else if (location == INTERP_CENTROID)
3824 return ctx->linear_centroid;
3825 else if (location == INTERP_SAMPLE)
3826 return ctx->linear_sample;
3827 break;
3828 }
3829 return NULL;
3830 }
3831
3832 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3833 LLVMValueRef sample_id)
3834 {
3835 LLVMValueRef result;
3836 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3837
3838 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3839 const_array(ctx->ac.v2f32, 64), "");
3840
3841 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3842 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3843
3844 return result;
3845 }
3846
3847 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3848 {
3849 LLVMValueRef values[2];
3850
3851 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3852 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3853 return ac_build_gather_values(&ctx->ac, values, 2);
3854 }
3855
3856 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3857 const nir_intrinsic_instr *instr)
3858 {
3859 LLVMValueRef result[4];
3860 LLVMValueRef interp_param, attr_number;
3861 unsigned location;
3862 unsigned chan;
3863 LLVMValueRef src_c0 = NULL;
3864 LLVMValueRef src_c1 = NULL;
3865 LLVMValueRef src0 = NULL;
3866 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3867 switch (instr->intrinsic) {
3868 case nir_intrinsic_interp_var_at_centroid:
3869 location = INTERP_CENTROID;
3870 break;
3871 case nir_intrinsic_interp_var_at_sample:
3872 case nir_intrinsic_interp_var_at_offset:
3873 location = INTERP_CENTER;
3874 src0 = get_src(ctx->nir, instr->src[0]);
3875 break;
3876 default:
3877 break;
3878 }
3879
3880 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3881 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3882 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3883 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3884 LLVMValueRef sample_position;
3885 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3886
3887 /* fetch sample ID */
3888 sample_position = load_sample_position(ctx, src0);
3889
3890 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3891 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3892 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3893 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3894 }
3895 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3896 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3897
3898 if (location == INTERP_CENTER) {
3899 LLVMValueRef ij_out[2];
3900 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3901
3902 /*
3903 * take the I then J parameters, and the DDX/Y for it, and
3904 * calculate the IJ inputs for the interpolator.
3905 * temp1 = ddx * offset/sample.x + I;
3906 * interp_param.I = ddy * offset/sample.y + temp1;
3907 * temp1 = ddx * offset/sample.x + J;
3908 * interp_param.J = ddy * offset/sample.y + temp1;
3909 */
3910 for (unsigned i = 0; i < 2; i++) {
3911 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
3912 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
3913 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3914 ddxy_out, ix_ll, "");
3915 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3916 ddxy_out, iy_ll, "");
3917 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3918 interp_param, ix_ll, "");
3919 LLVMValueRef temp1, temp2;
3920
3921 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3922 ctx->ac.f32, "");
3923
3924 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3925 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3926
3927 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3928 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3929
3930 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3931 temp2, ctx->ac.i32, "");
3932 }
3933 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3934
3935 }
3936
3937 for (chan = 0; chan < 4; chan++) {
3938 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
3939
3940 if (interp_param) {
3941 interp_param = LLVMBuildBitCast(ctx->builder,
3942 interp_param, ctx->ac.v2f32, "");
3943 LLVMValueRef i = LLVMBuildExtractElement(
3944 ctx->builder, interp_param, ctx->ac.i32_0, "");
3945 LLVMValueRef j = LLVMBuildExtractElement(
3946 ctx->builder, interp_param, ctx->ac.i32_1, "");
3947
3948 result[chan] = ac_build_fs_interp(&ctx->ac,
3949 llvm_chan, attr_number,
3950 ctx->prim_mask, i, j);
3951 } else {
3952 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3953 LLVMConstInt(ctx->ac.i32, 2, false),
3954 llvm_chan, attr_number,
3955 ctx->prim_mask);
3956 }
3957 }
3958 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
3959 instr->variables[0]->var->data.location_frac);
3960 }
3961
3962 static void
3963 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
3964 {
3965 LLVMValueRef gs_next_vertex;
3966 LLVMValueRef can_emit;
3967 int idx;
3968 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3969
3970 /* Write vertex attribute values to GSVS ring */
3971 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3972 ctx->gs_next_vertex,
3973 "");
3974
3975 /* If this thread has already emitted the declared maximum number of
3976 * vertices, kill it: excessive vertex emissions are not supposed to
3977 * have any effect, and GS threads have no externally observable
3978 * effects other than emitting vertices.
3979 */
3980 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3981 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
3982 ac_build_kill_if_false(&ctx->ac, can_emit);
3983
3984 /* loop num outputs */
3985 idx = 0;
3986 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3987 LLVMValueRef *out_ptr = &addrs[i * 4];
3988 int length = 4;
3989 int slot = idx;
3990 int slot_inc = 1;
3991
3992 if (!(ctx->output_mask & (1ull << i)))
3993 continue;
3994
3995 if (i == VARYING_SLOT_CLIP_DIST0) {
3996 /* pack clip and cull into a single set of slots */
3997 length = ctx->num_output_clips + ctx->num_output_culls;
3998 if (length > 4)
3999 slot_inc = 2;
4000 }
4001 for (unsigned j = 0; j < length; j++) {
4002 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4003 out_ptr[j], "");
4004 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4005 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4006 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4007
4008 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4009
4010 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4011 out_val, 1,
4012 voffset, ctx->gs2vs_offset, 0,
4013 1, 1, true, true);
4014 }
4015 idx += slot_inc;
4016 }
4017
4018 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4019 ctx->ac.i32_1, "");
4020 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4021
4022 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4023 }
4024
4025 static void
4026 visit_end_primitive(struct nir_to_llvm_context *ctx,
4027 const nir_intrinsic_instr *instr)
4028 {
4029 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4030 }
4031
4032 static LLVMValueRef
4033 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4034 const nir_intrinsic_instr *instr)
4035 {
4036 LLVMValueRef coord[4] = {
4037 ctx->tes_u,
4038 ctx->tes_v,
4039 ctx->ac.f32_0,
4040 ctx->ac.f32_0,
4041 };
4042
4043 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4044 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4045 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4046
4047 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4048 return LLVMBuildBitCast(ctx->builder, result,
4049 get_def_type(ctx->nir, &instr->dest.ssa), "");
4050 }
4051
4052 static void visit_intrinsic(struct ac_nir_context *ctx,
4053 nir_intrinsic_instr *instr)
4054 {
4055 LLVMValueRef result = NULL;
4056
4057 switch (instr->intrinsic) {
4058 case nir_intrinsic_load_work_group_id: {
4059 LLVMValueRef values[3];
4060
4061 for (int i = 0; i < 3; i++) {
4062 values[i] = ctx->nctx->workgroup_ids[i] ?
4063 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4064 }
4065
4066 result = ac_build_gather_values(&ctx->ac, values, 3);
4067 break;
4068 }
4069 case nir_intrinsic_load_base_vertex: {
4070 result = ctx->abi->base_vertex;
4071 break;
4072 }
4073 case nir_intrinsic_load_vertex_id_zero_base: {
4074 result = ctx->abi->vertex_id;
4075 break;
4076 }
4077 case nir_intrinsic_load_local_invocation_id: {
4078 result = ctx->nctx->local_invocation_ids;
4079 break;
4080 }
4081 case nir_intrinsic_load_base_instance:
4082 result = ctx->abi->start_instance;
4083 break;
4084 case nir_intrinsic_load_draw_id:
4085 result = ctx->abi->draw_id;
4086 break;
4087 case nir_intrinsic_load_view_index:
4088 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4089 break;
4090 case nir_intrinsic_load_invocation_id:
4091 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4092 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4093 else
4094 result = ctx->abi->gs_invocation_id;
4095 break;
4096 case nir_intrinsic_load_primitive_id:
4097 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4098 if (ctx->nctx)
4099 ctx->nctx->shader_info->gs.uses_prim_id = true;
4100 result = ctx->abi->gs_prim_id;
4101 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4102 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4103 result = ctx->nctx->tcs_patch_id;
4104 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4105 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4106 result = ctx->nctx->tes_patch_id;
4107 } else
4108 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4109 break;
4110 case nir_intrinsic_load_sample_id:
4111 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4112 break;
4113 case nir_intrinsic_load_sample_pos:
4114 result = load_sample_pos(ctx);
4115 break;
4116 case nir_intrinsic_load_sample_mask_in:
4117 result = ctx->abi->sample_coverage;
4118 break;
4119 case nir_intrinsic_load_frag_coord: {
4120 LLVMValueRef values[4] = {
4121 ctx->abi->frag_pos[0],
4122 ctx->abi->frag_pos[1],
4123 ctx->abi->frag_pos[2],
4124 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4125 };
4126 result = ac_build_gather_values(&ctx->ac, values, 4);
4127 break;
4128 }
4129 case nir_intrinsic_load_front_face:
4130 result = ctx->abi->front_face;
4131 break;
4132 case nir_intrinsic_load_instance_id:
4133 result = ctx->abi->instance_id;
4134 break;
4135 case nir_intrinsic_load_num_work_groups:
4136 result = ctx->nctx->num_work_groups;
4137 break;
4138 case nir_intrinsic_load_local_invocation_index:
4139 result = visit_load_local_invocation_index(ctx->nctx);
4140 break;
4141 case nir_intrinsic_load_push_constant:
4142 result = visit_load_push_constant(ctx->nctx, instr);
4143 break;
4144 case nir_intrinsic_vulkan_resource_index:
4145 result = visit_vulkan_resource_index(ctx->nctx, instr);
4146 break;
4147 case nir_intrinsic_vulkan_resource_reindex:
4148 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4149 break;
4150 case nir_intrinsic_store_ssbo:
4151 visit_store_ssbo(ctx, instr);
4152 break;
4153 case nir_intrinsic_load_ssbo:
4154 result = visit_load_buffer(ctx, instr);
4155 break;
4156 case nir_intrinsic_ssbo_atomic_add:
4157 case nir_intrinsic_ssbo_atomic_imin:
4158 case nir_intrinsic_ssbo_atomic_umin:
4159 case nir_intrinsic_ssbo_atomic_imax:
4160 case nir_intrinsic_ssbo_atomic_umax:
4161 case nir_intrinsic_ssbo_atomic_and:
4162 case nir_intrinsic_ssbo_atomic_or:
4163 case nir_intrinsic_ssbo_atomic_xor:
4164 case nir_intrinsic_ssbo_atomic_exchange:
4165 case nir_intrinsic_ssbo_atomic_comp_swap:
4166 result = visit_atomic_ssbo(ctx, instr);
4167 break;
4168 case nir_intrinsic_load_ubo:
4169 result = visit_load_ubo_buffer(ctx, instr);
4170 break;
4171 case nir_intrinsic_get_buffer_size:
4172 result = visit_get_buffer_size(ctx, instr);
4173 break;
4174 case nir_intrinsic_load_var:
4175 result = visit_load_var(ctx, instr);
4176 break;
4177 case nir_intrinsic_store_var:
4178 visit_store_var(ctx, instr);
4179 break;
4180 case nir_intrinsic_image_load:
4181 result = visit_image_load(ctx, instr);
4182 break;
4183 case nir_intrinsic_image_store:
4184 visit_image_store(ctx, instr);
4185 break;
4186 case nir_intrinsic_image_atomic_add:
4187 case nir_intrinsic_image_atomic_min:
4188 case nir_intrinsic_image_atomic_max:
4189 case nir_intrinsic_image_atomic_and:
4190 case nir_intrinsic_image_atomic_or:
4191 case nir_intrinsic_image_atomic_xor:
4192 case nir_intrinsic_image_atomic_exchange:
4193 case nir_intrinsic_image_atomic_comp_swap:
4194 result = visit_image_atomic(ctx, instr);
4195 break;
4196 case nir_intrinsic_image_size:
4197 result = visit_image_size(ctx, instr);
4198 break;
4199 case nir_intrinsic_discard:
4200 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4201 LLVMVoidTypeInContext(ctx->ac.context),
4202 NULL, 0, AC_FUNC_ATTR_LEGACY);
4203 break;
4204 case nir_intrinsic_discard_if:
4205 emit_discard_if(ctx, instr);
4206 break;
4207 case nir_intrinsic_memory_barrier:
4208 case nir_intrinsic_group_memory_barrier:
4209 case nir_intrinsic_memory_barrier_atomic_counter:
4210 case nir_intrinsic_memory_barrier_buffer:
4211 case nir_intrinsic_memory_barrier_image:
4212 case nir_intrinsic_memory_barrier_shared:
4213 emit_membar(ctx->nctx, instr);
4214 break;
4215 case nir_intrinsic_barrier:
4216 emit_barrier(ctx->nctx);
4217 break;
4218 case nir_intrinsic_var_atomic_add:
4219 case nir_intrinsic_var_atomic_imin:
4220 case nir_intrinsic_var_atomic_umin:
4221 case nir_intrinsic_var_atomic_imax:
4222 case nir_intrinsic_var_atomic_umax:
4223 case nir_intrinsic_var_atomic_and:
4224 case nir_intrinsic_var_atomic_or:
4225 case nir_intrinsic_var_atomic_xor:
4226 case nir_intrinsic_var_atomic_exchange:
4227 case nir_intrinsic_var_atomic_comp_swap:
4228 result = visit_var_atomic(ctx->nctx, instr);
4229 break;
4230 case nir_intrinsic_interp_var_at_centroid:
4231 case nir_intrinsic_interp_var_at_sample:
4232 case nir_intrinsic_interp_var_at_offset:
4233 result = visit_interp(ctx->nctx, instr);
4234 break;
4235 case nir_intrinsic_emit_vertex:
4236 assert(instr->const_index[0] == 0);
4237 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4238 break;
4239 case nir_intrinsic_end_primitive:
4240 visit_end_primitive(ctx->nctx, instr);
4241 break;
4242 case nir_intrinsic_load_tess_coord:
4243 result = visit_load_tess_coord(ctx->nctx, instr);
4244 break;
4245 case nir_intrinsic_load_patch_vertices_in:
4246 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4247 break;
4248 default:
4249 fprintf(stderr, "Unknown intrinsic: ");
4250 nir_print_instr(&instr->instr, stderr);
4251 fprintf(stderr, "\n");
4252 break;
4253 }
4254 if (result) {
4255 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4256 }
4257 }
4258
4259 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4260 LLVMValueRef buffer_ptr, bool write)
4261 {
4262 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4263
4264 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4265 ctx->shader_info->fs.writes_memory = true;
4266
4267 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4268 }
4269
4270 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4271 {
4272 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4273
4274 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4275 }
4276
4277 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4278 unsigned descriptor_set,
4279 unsigned base_index,
4280 unsigned constant_index,
4281 LLVMValueRef index,
4282 enum ac_descriptor_type desc_type,
4283 bool image, bool write)
4284 {
4285 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4286 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4287 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4288 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4289 unsigned offset = binding->offset;
4290 unsigned stride = binding->size;
4291 unsigned type_size;
4292 LLVMBuilderRef builder = ctx->builder;
4293 LLVMTypeRef type;
4294
4295 assert(base_index < layout->binding_count);
4296
4297 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4298 ctx->shader_info->fs.writes_memory = true;
4299
4300 switch (desc_type) {
4301 case AC_DESC_IMAGE:
4302 type = ctx->ac.v8i32;
4303 type_size = 32;
4304 break;
4305 case AC_DESC_FMASK:
4306 type = ctx->ac.v8i32;
4307 offset += 32;
4308 type_size = 32;
4309 break;
4310 case AC_DESC_SAMPLER:
4311 type = ctx->ac.v4i32;
4312 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4313 offset += 64;
4314
4315 type_size = 16;
4316 break;
4317 case AC_DESC_BUFFER:
4318 type = ctx->ac.v4i32;
4319 type_size = 16;
4320 break;
4321 default:
4322 unreachable("invalid desc_type\n");
4323 }
4324
4325 offset += constant_index * stride;
4326
4327 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4328 (!index || binding->immutable_samplers_equal)) {
4329 if (binding->immutable_samplers_equal)
4330 constant_index = 0;
4331
4332 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4333
4334 LLVMValueRef constants[] = {
4335 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4336 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4337 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4338 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4339 };
4340 return ac_build_gather_values(&ctx->ac, constants, 4);
4341 }
4342
4343 assert(stride % type_size == 0);
4344
4345 if (!index)
4346 index = ctx->ac.i32_0;
4347
4348 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4349
4350 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4351 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4352
4353 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4354 }
4355
4356 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4357 const nir_deref_var *deref,
4358 enum ac_descriptor_type desc_type,
4359 const nir_tex_instr *tex_instr,
4360 bool image, bool write)
4361 {
4362 LLVMValueRef index = NULL;
4363 unsigned constant_index = 0;
4364 unsigned descriptor_set;
4365 unsigned base_index;
4366
4367 if (!deref) {
4368 assert(tex_instr && !image);
4369 descriptor_set = 0;
4370 base_index = tex_instr->sampler_index;
4371 } else {
4372 const nir_deref *tail = &deref->deref;
4373 while (tail->child) {
4374 const nir_deref_array *child = nir_deref_as_array(tail->child);
4375 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4376
4377 if (!array_size)
4378 array_size = 1;
4379
4380 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4381
4382 if (child->deref_array_type == nir_deref_array_type_indirect) {
4383 LLVMValueRef indirect = get_src(ctx, child->indirect);
4384
4385 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4386 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4387
4388 if (!index)
4389 index = indirect;
4390 else
4391 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4392 }
4393
4394 constant_index += child->base_offset * array_size;
4395
4396 tail = &child->deref;
4397 }
4398 descriptor_set = deref->var->data.descriptor_set;
4399 base_index = deref->var->data.binding;
4400 }
4401
4402 return ctx->abi->load_sampler_desc(ctx->abi,
4403 descriptor_set,
4404 base_index,
4405 constant_index, index,
4406 desc_type, image, write);
4407 }
4408
4409 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4410 struct ac_image_args *args,
4411 const nir_tex_instr *instr,
4412 nir_texop op,
4413 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4414 LLVMValueRef *param, unsigned count,
4415 unsigned dmask)
4416 {
4417 unsigned is_rect = 0;
4418 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4419
4420 if (op == nir_texop_lod)
4421 da = false;
4422 /* Pad to power of two vector */
4423 while (count < util_next_power_of_two(count))
4424 param[count++] = LLVMGetUndef(ctx->i32);
4425
4426 if (count > 1)
4427 args->addr = ac_build_gather_values(ctx, param, count);
4428 else
4429 args->addr = param[0];
4430
4431 args->resource = res_ptr;
4432 args->sampler = samp_ptr;
4433
4434 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4435 args->addr = param[0];
4436 return;
4437 }
4438
4439 args->dmask = dmask;
4440 args->unorm = is_rect;
4441 args->da = da;
4442 }
4443
4444 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4445 *
4446 * SI-CI:
4447 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4448 * filtering manually. The driver sets img7 to a mask clearing
4449 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4450 * s_and_b32 samp0, samp0, img7
4451 *
4452 * VI:
4453 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4454 */
4455 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4456 LLVMValueRef res, LLVMValueRef samp)
4457 {
4458 LLVMBuilderRef builder = ctx->ac.builder;
4459 LLVMValueRef img7, samp0;
4460
4461 if (ctx->ac.chip_class >= VI)
4462 return samp;
4463
4464 img7 = LLVMBuildExtractElement(builder, res,
4465 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4466 samp0 = LLVMBuildExtractElement(builder, samp,
4467 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4468 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4469 return LLVMBuildInsertElement(builder, samp, samp0,
4470 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4471 }
4472
4473 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4474 nir_tex_instr *instr,
4475 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4476 LLVMValueRef *fmask_ptr)
4477 {
4478 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4479 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4480 else
4481 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4482 if (samp_ptr) {
4483 if (instr->sampler)
4484 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4485 else
4486 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4487 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4488 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4489 }
4490 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4491 instr->op == nir_texop_samples_identical))
4492 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4493 }
4494
4495 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4496 LLVMValueRef coord)
4497 {
4498 coord = ac_to_float(ctx, coord);
4499 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4500 coord = ac_to_integer(ctx, coord);
4501 return coord;
4502 }
4503
4504 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4505 {
4506 LLVMValueRef result = NULL;
4507 struct ac_image_args args = { 0 };
4508 unsigned dmask = 0xf;
4509 LLVMValueRef address[16];
4510 LLVMValueRef coords[5];
4511 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4512 LLVMValueRef bias = NULL, offsets = NULL;
4513 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4514 LLVMValueRef ddx = NULL, ddy = NULL;
4515 LLVMValueRef derivs[6];
4516 unsigned chan, count = 0;
4517 unsigned const_src = 0, num_deriv_comp = 0;
4518 bool lod_is_zero = false;
4519
4520 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4521
4522 for (unsigned i = 0; i < instr->num_srcs; i++) {
4523 switch (instr->src[i].src_type) {
4524 case nir_tex_src_coord:
4525 coord = get_src(ctx, instr->src[i].src);
4526 break;
4527 case nir_tex_src_projector:
4528 break;
4529 case nir_tex_src_comparator:
4530 comparator = get_src(ctx, instr->src[i].src);
4531 break;
4532 case nir_tex_src_offset:
4533 offsets = get_src(ctx, instr->src[i].src);
4534 const_src = i;
4535 break;
4536 case nir_tex_src_bias:
4537 bias = get_src(ctx, instr->src[i].src);
4538 break;
4539 case nir_tex_src_lod: {
4540 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4541
4542 if (val && val->i32[0] == 0)
4543 lod_is_zero = true;
4544 lod = get_src(ctx, instr->src[i].src);
4545 break;
4546 }
4547 case nir_tex_src_ms_index:
4548 sample_index = get_src(ctx, instr->src[i].src);
4549 break;
4550 case nir_tex_src_ms_mcs:
4551 break;
4552 case nir_tex_src_ddx:
4553 ddx = get_src(ctx, instr->src[i].src);
4554 num_deriv_comp = instr->src[i].src.ssa->num_components;
4555 break;
4556 case nir_tex_src_ddy:
4557 ddy = get_src(ctx, instr->src[i].src);
4558 break;
4559 case nir_tex_src_texture_offset:
4560 case nir_tex_src_sampler_offset:
4561 case nir_tex_src_plane:
4562 default:
4563 break;
4564 }
4565 }
4566
4567 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4568 result = get_buffer_size(ctx, res_ptr, true);
4569 goto write_result;
4570 }
4571
4572 if (instr->op == nir_texop_texture_samples) {
4573 LLVMValueRef res, samples, is_msaa;
4574 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4575 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4576 LLVMConstInt(ctx->ac.i32, 3, false), "");
4577 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4578 LLVMConstInt(ctx->ac.i32, 28, false), "");
4579 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4580 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4581 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4582 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4583
4584 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4585 LLVMConstInt(ctx->ac.i32, 16, false), "");
4586 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4587 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4588 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4589 samples, "");
4590 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4591 ctx->ac.i32_1, "");
4592 result = samples;
4593 goto write_result;
4594 }
4595
4596 if (coord)
4597 for (chan = 0; chan < instr->coord_components; chan++)
4598 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4599
4600 if (offsets && instr->op != nir_texop_txf) {
4601 LLVMValueRef offset[3], pack;
4602 for (chan = 0; chan < 3; ++chan)
4603 offset[chan] = ctx->ac.i32_0;
4604
4605 args.offset = true;
4606 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4607 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4608 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4609 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4610 if (chan)
4611 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4612 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4613 }
4614 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4615 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4616 address[count++] = pack;
4617
4618 }
4619 /* pack LOD bias value */
4620 if (instr->op == nir_texop_txb && bias) {
4621 address[count++] = bias;
4622 }
4623
4624 /* Pack depth comparison value */
4625 if (instr->is_shadow && comparator) {
4626 LLVMValueRef z = ac_to_float(&ctx->ac,
4627 llvm_extract_elem(&ctx->ac, comparator, 0));
4628
4629 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4630 * so the depth comparison value isn't clamped for Z16 and
4631 * Z24 anymore. Do it manually here.
4632 *
4633 * It's unnecessary if the original texture format was
4634 * Z32_FLOAT, but we don't know that here.
4635 */
4636 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4637 z = ac_build_clamp(&ctx->ac, z);
4638
4639 address[count++] = z;
4640 }
4641
4642 /* pack derivatives */
4643 if (ddx || ddy) {
4644 int num_src_deriv_channels, num_dest_deriv_channels;
4645 switch (instr->sampler_dim) {
4646 case GLSL_SAMPLER_DIM_3D:
4647 case GLSL_SAMPLER_DIM_CUBE:
4648 num_deriv_comp = 3;
4649 num_src_deriv_channels = 3;
4650 num_dest_deriv_channels = 3;
4651 break;
4652 case GLSL_SAMPLER_DIM_2D:
4653 default:
4654 num_src_deriv_channels = 2;
4655 num_dest_deriv_channels = 2;
4656 num_deriv_comp = 2;
4657 break;
4658 case GLSL_SAMPLER_DIM_1D:
4659 num_src_deriv_channels = 1;
4660 if (ctx->ac.chip_class >= GFX9) {
4661 num_dest_deriv_channels = 2;
4662 num_deriv_comp = 2;
4663 } else {
4664 num_dest_deriv_channels = 1;
4665 num_deriv_comp = 1;
4666 }
4667 break;
4668 }
4669
4670 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4671 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4672 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4673 }
4674 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4675 derivs[i] = ctx->ac.f32_0;
4676 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4677 }
4678 }
4679
4680 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4681 for (chan = 0; chan < instr->coord_components; chan++)
4682 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4683 if (instr->coord_components == 3)
4684 coords[3] = LLVMGetUndef(ctx->ac.f32);
4685 ac_prepare_cube_coords(&ctx->ac,
4686 instr->op == nir_texop_txd, instr->is_array,
4687 instr->op == nir_texop_lod, coords, derivs);
4688 if (num_deriv_comp)
4689 num_deriv_comp--;
4690 }
4691
4692 if (ddx || ddy) {
4693 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4694 address[count++] = derivs[i];
4695 }
4696
4697 /* Pack texture coordinates */
4698 if (coord) {
4699 address[count++] = coords[0];
4700 if (instr->coord_components > 1) {
4701 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4702 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4703 }
4704 address[count++] = coords[1];
4705 }
4706 if (instr->coord_components > 2) {
4707 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4708 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4709 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4710 instr->op != nir_texop_txf) {
4711 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4712 }
4713 address[count++] = coords[2];
4714 }
4715
4716 if (ctx->ac.chip_class >= GFX9) {
4717 LLVMValueRef filler;
4718 if (instr->op == nir_texop_txf)
4719 filler = ctx->ac.i32_0;
4720 else
4721 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4722
4723 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4724 /* No nir_texop_lod, because it does not take a slice
4725 * even with array textures. */
4726 if (instr->is_array && instr->op != nir_texop_lod ) {
4727 address[count] = address[count - 1];
4728 address[count - 1] = filler;
4729 count++;
4730 } else
4731 address[count++] = filler;
4732 }
4733 }
4734 }
4735
4736 /* Pack LOD */
4737 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4738 instr->op == nir_texop_txf)) {
4739 address[count++] = lod;
4740 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4741 address[count++] = sample_index;
4742 } else if(instr->op == nir_texop_txs) {
4743 count = 0;
4744 if (lod)
4745 address[count++] = lod;
4746 else
4747 address[count++] = ctx->ac.i32_0;
4748 }
4749
4750 for (chan = 0; chan < count; chan++) {
4751 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4752 address[chan], ctx->ac.i32, "");
4753 }
4754
4755 if (instr->op == nir_texop_samples_identical) {
4756 LLVMValueRef txf_address[4];
4757 struct ac_image_args txf_args = { 0 };
4758 unsigned txf_count = count;
4759 memcpy(txf_address, address, sizeof(txf_address));
4760
4761 if (!instr->is_array)
4762 txf_address[2] = ctx->ac.i32_0;
4763 txf_address[3] = ctx->ac.i32_0;
4764
4765 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4766 fmask_ptr, NULL,
4767 txf_address, txf_count, 0xf);
4768
4769 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4770
4771 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4772 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4773 goto write_result;
4774 }
4775
4776 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4777 instr->op != nir_texop_txs) {
4778 unsigned sample_chan = instr->is_array ? 3 : 2;
4779 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4780 address[0],
4781 address[1],
4782 instr->is_array ? address[2] : NULL,
4783 address[sample_chan],
4784 fmask_ptr);
4785 }
4786
4787 if (offsets && instr->op == nir_texop_txf) {
4788 nir_const_value *const_offset =
4789 nir_src_as_const_value(instr->src[const_src].src);
4790 int num_offsets = instr->src[const_src].src.ssa->num_components;
4791 assert(const_offset);
4792 num_offsets = MIN2(num_offsets, instr->coord_components);
4793 if (num_offsets > 2)
4794 address[2] = LLVMBuildAdd(ctx->ac.builder,
4795 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4796 if (num_offsets > 1)
4797 address[1] = LLVMBuildAdd(ctx->ac.builder,
4798 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4799 address[0] = LLVMBuildAdd(ctx->ac.builder,
4800 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4801
4802 }
4803
4804 /* TODO TG4 support */
4805 if (instr->op == nir_texop_tg4) {
4806 if (instr->is_shadow)
4807 dmask = 1;
4808 else
4809 dmask = 1 << instr->component;
4810 }
4811 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4812 res_ptr, samp_ptr, address, count, dmask);
4813
4814 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4815
4816 if (instr->op == nir_texop_query_levels)
4817 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4818 else if (instr->is_shadow && instr->is_new_style_shadow &&
4819 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4820 instr->op != nir_texop_tg4)
4821 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4822 else if (instr->op == nir_texop_txs &&
4823 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4824 instr->is_array) {
4825 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4826 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4827 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4828 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4829 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4830 } else if (ctx->ac.chip_class >= GFX9 &&
4831 instr->op == nir_texop_txs &&
4832 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4833 instr->is_array) {
4834 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4835 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4836 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4837 ctx->ac.i32_1, "");
4838 } else if (instr->dest.ssa.num_components != 4)
4839 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4840
4841 write_result:
4842 if (result) {
4843 assert(instr->dest.is_ssa);
4844 result = ac_to_integer(&ctx->ac, result);
4845 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4846 }
4847 }
4848
4849
4850 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4851 {
4852 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4853 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4854
4855 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4856 _mesa_hash_table_insert(ctx->phis, instr, result);
4857 }
4858
4859 static void visit_post_phi(struct ac_nir_context *ctx,
4860 nir_phi_instr *instr,
4861 LLVMValueRef llvm_phi)
4862 {
4863 nir_foreach_phi_src(src, instr) {
4864 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4865 LLVMValueRef llvm_src = get_src(ctx, src->src);
4866
4867 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4868 }
4869 }
4870
4871 static void phi_post_pass(struct ac_nir_context *ctx)
4872 {
4873 struct hash_entry *entry;
4874 hash_table_foreach(ctx->phis, entry) {
4875 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4876 (LLVMValueRef)entry->data);
4877 }
4878 }
4879
4880
4881 static void visit_ssa_undef(struct ac_nir_context *ctx,
4882 const nir_ssa_undef_instr *instr)
4883 {
4884 unsigned num_components = instr->def.num_components;
4885 LLVMValueRef undef;
4886
4887 if (num_components == 1)
4888 undef = LLVMGetUndef(ctx->ac.i32);
4889 else {
4890 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4891 }
4892 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4893 }
4894
4895 static void visit_jump(struct ac_nir_context *ctx,
4896 const nir_jump_instr *instr)
4897 {
4898 switch (instr->type) {
4899 case nir_jump_break:
4900 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4901 LLVMClearInsertionPosition(ctx->ac.builder);
4902 break;
4903 case nir_jump_continue:
4904 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4905 LLVMClearInsertionPosition(ctx->ac.builder);
4906 break;
4907 default:
4908 fprintf(stderr, "Unknown NIR jump instr: ");
4909 nir_print_instr(&instr->instr, stderr);
4910 fprintf(stderr, "\n");
4911 abort();
4912 }
4913 }
4914
4915 static void visit_cf_list(struct ac_nir_context *ctx,
4916 struct exec_list *list);
4917
4918 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4919 {
4920 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4921 nir_foreach_instr(instr, block)
4922 {
4923 switch (instr->type) {
4924 case nir_instr_type_alu:
4925 visit_alu(ctx, nir_instr_as_alu(instr));
4926 break;
4927 case nir_instr_type_load_const:
4928 visit_load_const(ctx, nir_instr_as_load_const(instr));
4929 break;
4930 case nir_instr_type_intrinsic:
4931 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4932 break;
4933 case nir_instr_type_tex:
4934 visit_tex(ctx, nir_instr_as_tex(instr));
4935 break;
4936 case nir_instr_type_phi:
4937 visit_phi(ctx, nir_instr_as_phi(instr));
4938 break;
4939 case nir_instr_type_ssa_undef:
4940 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4941 break;
4942 case nir_instr_type_jump:
4943 visit_jump(ctx, nir_instr_as_jump(instr));
4944 break;
4945 default:
4946 fprintf(stderr, "Unknown NIR instr type: ");
4947 nir_print_instr(instr, stderr);
4948 fprintf(stderr, "\n");
4949 abort();
4950 }
4951 }
4952
4953 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4954 }
4955
4956 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4957 {
4958 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4959
4960 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4961 LLVMBasicBlockRef merge_block =
4962 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4963 LLVMBasicBlockRef if_block =
4964 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4965 LLVMBasicBlockRef else_block = merge_block;
4966 if (!exec_list_is_empty(&if_stmt->else_list))
4967 else_block = LLVMAppendBasicBlockInContext(
4968 ctx->ac.context, fn, "");
4969
4970 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4971 ctx->ac.i32_0, "");
4972 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4973
4974 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4975 visit_cf_list(ctx, &if_stmt->then_list);
4976 if (LLVMGetInsertBlock(ctx->ac.builder))
4977 LLVMBuildBr(ctx->ac.builder, merge_block);
4978
4979 if (!exec_list_is_empty(&if_stmt->else_list)) {
4980 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4981 visit_cf_list(ctx, &if_stmt->else_list);
4982 if (LLVMGetInsertBlock(ctx->ac.builder))
4983 LLVMBuildBr(ctx->ac.builder, merge_block);
4984 }
4985
4986 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4987 }
4988
4989 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4990 {
4991 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4992 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4993 LLVMBasicBlockRef break_parent = ctx->break_block;
4994
4995 ctx->continue_block =
4996 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4997 ctx->break_block =
4998 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4999
5000 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5001 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5002 visit_cf_list(ctx, &loop->body);
5003
5004 if (LLVMGetInsertBlock(ctx->ac.builder))
5005 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5006 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5007
5008 ctx->continue_block = continue_parent;
5009 ctx->break_block = break_parent;
5010 }
5011
5012 static void visit_cf_list(struct ac_nir_context *ctx,
5013 struct exec_list *list)
5014 {
5015 foreach_list_typed(nir_cf_node, node, node, list)
5016 {
5017 switch (node->type) {
5018 case nir_cf_node_block:
5019 visit_block(ctx, nir_cf_node_as_block(node));
5020 break;
5021
5022 case nir_cf_node_if:
5023 visit_if(ctx, nir_cf_node_as_if(node));
5024 break;
5025
5026 case nir_cf_node_loop:
5027 visit_loop(ctx, nir_cf_node_as_loop(node));
5028 break;
5029
5030 default:
5031 assert(0);
5032 }
5033 }
5034 }
5035
5036 static void
5037 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5038 struct nir_variable *variable)
5039 {
5040 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5041 LLVMValueRef t_offset;
5042 LLVMValueRef t_list;
5043 LLVMValueRef input;
5044 LLVMValueRef buffer_index;
5045 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5046 int idx = variable->data.location;
5047 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5048
5049 variable->data.driver_location = idx * 4;
5050
5051 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5052 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5053 ctx->abi.start_instance, "");
5054 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5055 ctx->shader_info->vs.vgpr_comp_cnt);
5056 } else
5057 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5058 ctx->abi.base_vertex, "");
5059
5060 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5061 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5062
5063 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5064
5065 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5066 buffer_index,
5067 ctx->ac.i32_0,
5068 true);
5069
5070 for (unsigned chan = 0; chan < 4; chan++) {
5071 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5072 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5073 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5074 input, llvm_chan, ""));
5075 }
5076 }
5077 }
5078
5079 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5080 unsigned attr,
5081 LLVMValueRef interp_param,
5082 LLVMValueRef prim_mask,
5083 LLVMValueRef result[4])
5084 {
5085 LLVMValueRef attr_number;
5086 unsigned chan;
5087 LLVMValueRef i, j;
5088 bool interp = interp_param != NULL;
5089
5090 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5091
5092 /* fs.constant returns the param from the middle vertex, so it's not
5093 * really useful for flat shading. It's meant to be used for custom
5094 * interpolation (but the intrinsic can't fetch from the other two
5095 * vertices).
5096 *
5097 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5098 * to do the right thing. The only reason we use fs.constant is that
5099 * fs.interp cannot be used on integers, because they can be equal
5100 * to NaN.
5101 */
5102 if (interp) {
5103 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5104 ctx->ac.v2f32, "");
5105
5106 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5107 ctx->ac.i32_0, "");
5108 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5109 ctx->ac.i32_1, "");
5110 }
5111
5112 for (chan = 0; chan < 4; chan++) {
5113 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5114
5115 if (interp) {
5116 result[chan] = ac_build_fs_interp(&ctx->ac,
5117 llvm_chan,
5118 attr_number,
5119 prim_mask, i, j);
5120 } else {
5121 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5122 LLVMConstInt(ctx->ac.i32, 2, false),
5123 llvm_chan,
5124 attr_number,
5125 prim_mask);
5126 }
5127 }
5128 }
5129
5130 static void
5131 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5132 struct nir_variable *variable)
5133 {
5134 int idx = variable->data.location;
5135 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5136 LLVMValueRef interp;
5137
5138 variable->data.driver_location = idx * 4;
5139 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5140
5141 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5142 unsigned interp_type;
5143 if (variable->data.sample) {
5144 interp_type = INTERP_SAMPLE;
5145 ctx->shader_info->info.ps.force_persample = true;
5146 } else if (variable->data.centroid)
5147 interp_type = INTERP_CENTROID;
5148 else
5149 interp_type = INTERP_CENTER;
5150
5151 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5152 } else
5153 interp = NULL;
5154
5155 for (unsigned i = 0; i < attrib_count; ++i)
5156 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5157
5158 }
5159
5160 static void
5161 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5162 struct nir_shader *nir) {
5163 nir_foreach_variable(variable, &nir->inputs)
5164 handle_vs_input_decl(ctx, variable);
5165 }
5166
5167 static void
5168 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5169 struct nir_shader *nir)
5170 {
5171 if (!ctx->options->key.fs.multisample)
5172 return;
5173
5174 bool uses_center = false;
5175 bool uses_centroid = false;
5176 nir_foreach_variable(variable, &nir->inputs) {
5177 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5178 variable->data.sample)
5179 continue;
5180
5181 if (variable->data.centroid)
5182 uses_centroid = true;
5183 else
5184 uses_center = true;
5185 }
5186
5187 if (uses_center && uses_centroid) {
5188 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5189 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5190 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5191 }
5192 }
5193
5194 static void
5195 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5196 struct nir_shader *nir)
5197 {
5198 prepare_interp_optimize(ctx, nir);
5199
5200 nir_foreach_variable(variable, &nir->inputs)
5201 handle_fs_input_decl(ctx, variable);
5202
5203 unsigned index = 0;
5204
5205 if (ctx->shader_info->info.ps.uses_input_attachments ||
5206 ctx->shader_info->info.needs_multiview_view_index)
5207 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5208
5209 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5210 LLVMValueRef interp_param;
5211 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5212
5213 if (!(ctx->input_mask & (1ull << i)))
5214 continue;
5215
5216 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5217 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5218 interp_param = *inputs;
5219 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5220 inputs);
5221
5222 if (!interp_param)
5223 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5224 ++index;
5225 } else if (i == VARYING_SLOT_POS) {
5226 for(int i = 0; i < 3; ++i)
5227 inputs[i] = ctx->abi.frag_pos[i];
5228
5229 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5230 ctx->abi.frag_pos[3]);
5231 }
5232 }
5233 ctx->shader_info->fs.num_interp = index;
5234 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5235 ctx->shader_info->fs.has_pcoord = true;
5236 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5237 ctx->shader_info->fs.prim_id_input = true;
5238 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5239 ctx->shader_info->fs.layer_input = true;
5240 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5241
5242 if (ctx->shader_info->info.needs_multiview_view_index)
5243 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5244 }
5245
5246 static LLVMValueRef
5247 ac_build_alloca(struct ac_llvm_context *ac,
5248 LLVMTypeRef type,
5249 const char *name)
5250 {
5251 LLVMBuilderRef builder = ac->builder;
5252 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5253 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5254 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5255 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5256 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5257 LLVMValueRef res;
5258
5259 if (first_instr) {
5260 LLVMPositionBuilderBefore(first_builder, first_instr);
5261 } else {
5262 LLVMPositionBuilderAtEnd(first_builder, first_block);
5263 }
5264
5265 res = LLVMBuildAlloca(first_builder, type, name);
5266 LLVMBuildStore(builder, LLVMConstNull(type), res);
5267
5268 LLVMDisposeBuilder(first_builder);
5269
5270 return res;
5271 }
5272
5273 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5274 LLVMTypeRef type,
5275 const char *name)
5276 {
5277 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5278 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5279 return ptr;
5280 }
5281
5282 static void
5283 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5284 struct nir_variable *variable,
5285 struct nir_shader *shader,
5286 gl_shader_stage stage)
5287 {
5288 int idx = variable->data.location + variable->data.index;
5289 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5290 uint64_t mask_attribs;
5291
5292 variable->data.driver_location = idx * 4;
5293
5294 /* tess ctrl has it's own load/store paths for outputs */
5295 if (stage == MESA_SHADER_TESS_CTRL)
5296 return;
5297
5298 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5299 if (stage == MESA_SHADER_VERTEX ||
5300 stage == MESA_SHADER_TESS_EVAL ||
5301 stage == MESA_SHADER_GEOMETRY) {
5302 if (idx == VARYING_SLOT_CLIP_DIST0) {
5303 int length = shader->info.clip_distance_array_size +
5304 shader->info.cull_distance_array_size;
5305 if (stage == MESA_SHADER_VERTEX) {
5306 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5307 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5308 }
5309 if (stage == MESA_SHADER_TESS_EVAL) {
5310 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5311 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5312 }
5313
5314 if (length > 4)
5315 attrib_count = 2;
5316 else
5317 attrib_count = 1;
5318 mask_attribs = 1ull << idx;
5319 }
5320 }
5321
5322 ctx->output_mask |= mask_attribs;
5323 }
5324
5325 static void
5326 handle_shader_output_decl(struct ac_nir_context *ctx,
5327 struct nir_shader *nir,
5328 struct nir_variable *variable)
5329 {
5330 unsigned output_loc = variable->data.driver_location / 4;
5331 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5332
5333 /* tess ctrl has it's own load/store paths for outputs */
5334 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5335 return;
5336
5337 if (ctx->stage == MESA_SHADER_VERTEX ||
5338 ctx->stage == MESA_SHADER_TESS_EVAL ||
5339 ctx->stage == MESA_SHADER_GEOMETRY) {
5340 int idx = variable->data.location + variable->data.index;
5341 if (idx == VARYING_SLOT_CLIP_DIST0) {
5342 int length = nir->info.clip_distance_array_size +
5343 nir->info.cull_distance_array_size;
5344
5345 if (length > 4)
5346 attrib_count = 2;
5347 else
5348 attrib_count = 1;
5349 }
5350 }
5351
5352 for (unsigned i = 0; i < attrib_count; ++i) {
5353 for (unsigned chan = 0; chan < 4; chan++) {
5354 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5355 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5356 }
5357 }
5358 }
5359
5360 static LLVMTypeRef
5361 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5362 enum glsl_base_type type)
5363 {
5364 switch (type) {
5365 case GLSL_TYPE_INT:
5366 case GLSL_TYPE_UINT:
5367 case GLSL_TYPE_BOOL:
5368 case GLSL_TYPE_SUBROUTINE:
5369 return ctx->ac.i32;
5370 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5371 return ctx->ac.f32;
5372 case GLSL_TYPE_INT64:
5373 case GLSL_TYPE_UINT64:
5374 return ctx->ac.i64;
5375 case GLSL_TYPE_DOUBLE:
5376 return ctx->ac.f64;
5377 default:
5378 unreachable("unknown GLSL type");
5379 }
5380 }
5381
5382 static LLVMTypeRef
5383 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5384 const struct glsl_type *type)
5385 {
5386 if (glsl_type_is_scalar(type)) {
5387 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5388 }
5389
5390 if (glsl_type_is_vector(type)) {
5391 return LLVMVectorType(
5392 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5393 glsl_get_vector_elements(type));
5394 }
5395
5396 if (glsl_type_is_matrix(type)) {
5397 return LLVMArrayType(
5398 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5399 glsl_get_matrix_columns(type));
5400 }
5401
5402 if (glsl_type_is_array(type)) {
5403 return LLVMArrayType(
5404 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5405 glsl_get_length(type));
5406 }
5407
5408 assert(glsl_type_is_struct(type));
5409
5410 LLVMTypeRef member_types[glsl_get_length(type)];
5411
5412 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5413 member_types[i] =
5414 glsl_to_llvm_type(ctx,
5415 glsl_get_struct_field(type, i));
5416 }
5417
5418 return LLVMStructTypeInContext(ctx->context, member_types,
5419 glsl_get_length(type), false);
5420 }
5421
5422 static void
5423 setup_locals(struct ac_nir_context *ctx,
5424 struct nir_function *func)
5425 {
5426 int i, j;
5427 ctx->num_locals = 0;
5428 nir_foreach_variable(variable, &func->impl->locals) {
5429 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5430 variable->data.driver_location = ctx->num_locals * 4;
5431 ctx->num_locals += attrib_count;
5432 }
5433 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5434 if (!ctx->locals)
5435 return;
5436
5437 for (i = 0; i < ctx->num_locals; i++) {
5438 for (j = 0; j < 4; j++) {
5439 ctx->locals[i * 4 + j] =
5440 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5441 }
5442 }
5443 }
5444
5445 static void
5446 setup_shared(struct ac_nir_context *ctx,
5447 struct nir_shader *nir)
5448 {
5449 nir_foreach_variable(variable, &nir->shared) {
5450 LLVMValueRef shared =
5451 LLVMAddGlobalInAddressSpace(
5452 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5453 variable->name ? variable->name : "",
5454 LOCAL_ADDR_SPACE);
5455 _mesa_hash_table_insert(ctx->vars, variable, shared);
5456 }
5457 }
5458
5459 static LLVMValueRef
5460 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5461 {
5462 v = ac_to_float(ctx, v);
5463 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5464 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5465 }
5466
5467
5468 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5469 LLVMValueRef src0, LLVMValueRef src1)
5470 {
5471 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5472 LLVMValueRef comp[2];
5473
5474 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5475 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5476 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5477 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5478 }
5479
5480 /* Initialize arguments for the shader export intrinsic */
5481 static void
5482 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5483 LLVMValueRef *values,
5484 unsigned target,
5485 struct ac_export_args *args)
5486 {
5487 /* Default is 0xf. Adjusted below depending on the format. */
5488 args->enabled_channels = 0xf;
5489
5490 /* Specify whether the EXEC mask represents the valid mask */
5491 args->valid_mask = 0;
5492
5493 /* Specify whether this is the last export */
5494 args->done = 0;
5495
5496 /* Specify the target we are exporting */
5497 args->target = target;
5498
5499 args->compr = false;
5500 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5501 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5502 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5503 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5504
5505 if (!values)
5506 return;
5507
5508 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5509 LLVMValueRef val[4];
5510 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5511 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5512 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5513 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5514
5515 switch(col_format) {
5516 case V_028714_SPI_SHADER_ZERO:
5517 args->enabled_channels = 0; /* writemask */
5518 args->target = V_008DFC_SQ_EXP_NULL;
5519 break;
5520
5521 case V_028714_SPI_SHADER_32_R:
5522 args->enabled_channels = 1;
5523 args->out[0] = values[0];
5524 break;
5525
5526 case V_028714_SPI_SHADER_32_GR:
5527 args->enabled_channels = 0x3;
5528 args->out[0] = values[0];
5529 args->out[1] = values[1];
5530 break;
5531
5532 case V_028714_SPI_SHADER_32_AR:
5533 args->enabled_channels = 0x9;
5534 args->out[0] = values[0];
5535 args->out[3] = values[3];
5536 break;
5537
5538 case V_028714_SPI_SHADER_FP16_ABGR:
5539 args->compr = 1;
5540
5541 for (unsigned chan = 0; chan < 2; chan++) {
5542 LLVMValueRef pack_args[2] = {
5543 values[2 * chan],
5544 values[2 * chan + 1]
5545 };
5546 LLVMValueRef packed;
5547
5548 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5549 args->out[chan] = packed;
5550 }
5551 break;
5552
5553 case V_028714_SPI_SHADER_UNORM16_ABGR:
5554 for (unsigned chan = 0; chan < 4; chan++) {
5555 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5556 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5557 LLVMConstReal(ctx->ac.f32, 65535), "");
5558 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5559 LLVMConstReal(ctx->ac.f32, 0.5), "");
5560 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5561 ctx->ac.i32, "");
5562 }
5563
5564 args->compr = 1;
5565 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5566 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5567 break;
5568
5569 case V_028714_SPI_SHADER_SNORM16_ABGR:
5570 for (unsigned chan = 0; chan < 4; chan++) {
5571 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5572 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5573 LLVMConstReal(ctx->ac.f32, 32767), "");
5574
5575 /* If positive, add 0.5, else add -0.5. */
5576 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5577 LLVMBuildSelect(ctx->builder,
5578 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5579 val[chan], ctx->ac.f32_0, ""),
5580 LLVMConstReal(ctx->ac.f32, 0.5),
5581 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5582 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5583 }
5584
5585 args->compr = 1;
5586 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5587 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5588 break;
5589
5590 case V_028714_SPI_SHADER_UINT16_ABGR: {
5591 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5592 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5593 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5594
5595 for (unsigned chan = 0; chan < 4; chan++) {
5596 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5597 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5598 }
5599
5600 args->compr = 1;
5601 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5602 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5603 break;
5604 }
5605
5606 case V_028714_SPI_SHADER_SINT16_ABGR: {
5607 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5608 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5609 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5610 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5611 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5612 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5613
5614 /* Clamp. */
5615 for (unsigned chan = 0; chan < 4; chan++) {
5616 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5617 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5618 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5619 }
5620
5621 args->compr = 1;
5622 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5623 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5624 break;
5625 }
5626
5627 default:
5628 case V_028714_SPI_SHADER_32_ABGR:
5629 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5630 break;
5631 }
5632 } else
5633 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5634
5635 for (unsigned i = 0; i < 4; ++i)
5636 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5637 }
5638
5639 static void
5640 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5641 bool export_prim_id,
5642 struct ac_vs_output_info *outinfo)
5643 {
5644 uint32_t param_count = 0;
5645 unsigned target;
5646 unsigned pos_idx, num_pos_exports = 0;
5647 struct ac_export_args args, pos_args[4] = {};
5648 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5649 int i;
5650
5651 if (ctx->options->key.has_multiview_view_index) {
5652 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5653 if(!*tmp_out) {
5654 for(unsigned i = 0; i < 4; ++i)
5655 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5656 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5657 }
5658
5659 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5660 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5661 }
5662
5663 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5664 sizeof(outinfo->vs_output_param_offset));
5665
5666 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5667 LLVMValueRef slots[8];
5668 unsigned j;
5669
5670 if (outinfo->cull_dist_mask)
5671 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5672
5673 i = VARYING_SLOT_CLIP_DIST0;
5674 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5675 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5676 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5677
5678 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5679 slots[i] = LLVMGetUndef(ctx->ac.f32);
5680
5681 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5682 target = V_008DFC_SQ_EXP_POS + 3;
5683 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5684 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5685 &args, sizeof(args));
5686 }
5687
5688 target = V_008DFC_SQ_EXP_POS + 2;
5689 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5690 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5691 &args, sizeof(args));
5692
5693 }
5694
5695 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5696 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5697 for (unsigned j = 0; j < 4; j++)
5698 pos_values[j] = LLVMBuildLoad(ctx->builder,
5699 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5700 }
5701 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5702
5703 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5704 outinfo->writes_pointsize = true;
5705 psize_value = LLVMBuildLoad(ctx->builder,
5706 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5707 }
5708
5709 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5710 outinfo->writes_layer = true;
5711 layer_value = LLVMBuildLoad(ctx->builder,
5712 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5713 }
5714
5715 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5716 outinfo->writes_viewport_index = true;
5717 viewport_index_value = LLVMBuildLoad(ctx->builder,
5718 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5719 }
5720
5721 if (outinfo->writes_pointsize ||
5722 outinfo->writes_layer ||
5723 outinfo->writes_viewport_index) {
5724 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5725 (outinfo->writes_layer == true ? 4 : 0));
5726 pos_args[1].valid_mask = 0;
5727 pos_args[1].done = 0;
5728 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5729 pos_args[1].compr = 0;
5730 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5731 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5732 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5733 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5734
5735 if (outinfo->writes_pointsize == true)
5736 pos_args[1].out[0] = psize_value;
5737 if (outinfo->writes_layer == true)
5738 pos_args[1].out[2] = layer_value;
5739 if (outinfo->writes_viewport_index == true) {
5740 if (ctx->options->chip_class >= GFX9) {
5741 /* GFX9 has the layer in out.z[10:0] and the viewport
5742 * index in out.z[19:16].
5743 */
5744 LLVMValueRef v = viewport_index_value;
5745 v = ac_to_integer(&ctx->ac, v);
5746 v = LLVMBuildShl(ctx->builder, v,
5747 LLVMConstInt(ctx->ac.i32, 16, false),
5748 "");
5749 v = LLVMBuildOr(ctx->builder, v,
5750 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5751
5752 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5753 pos_args[1].enabled_channels |= 1 << 2;
5754 } else {
5755 pos_args[1].out[3] = viewport_index_value;
5756 pos_args[1].enabled_channels |= 1 << 3;
5757 }
5758 }
5759 }
5760 for (i = 0; i < 4; i++) {
5761 if (pos_args[i].out[0])
5762 num_pos_exports++;
5763 }
5764
5765 pos_idx = 0;
5766 for (i = 0; i < 4; i++) {
5767 if (!pos_args[i].out[0])
5768 continue;
5769
5770 /* Specify the target we are exporting */
5771 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5772 if (pos_idx == num_pos_exports)
5773 pos_args[i].done = 1;
5774 ac_build_export(&ctx->ac, &pos_args[i]);
5775 }
5776
5777 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5778 LLVMValueRef values[4];
5779 if (!(ctx->output_mask & (1ull << i)))
5780 continue;
5781
5782 for (unsigned j = 0; j < 4; j++)
5783 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5784 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5785
5786 if (i == VARYING_SLOT_LAYER) {
5787 target = V_008DFC_SQ_EXP_PARAM + param_count;
5788 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5789 param_count++;
5790 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5791 target = V_008DFC_SQ_EXP_PARAM + param_count;
5792 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5793 param_count++;
5794 } else if (i >= VARYING_SLOT_VAR0) {
5795 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5796 target = V_008DFC_SQ_EXP_PARAM + param_count;
5797 outinfo->vs_output_param_offset[i] = param_count;
5798 param_count++;
5799 } else
5800 continue;
5801
5802 si_llvm_init_export_args(ctx, values, target, &args);
5803
5804 if (target >= V_008DFC_SQ_EXP_POS &&
5805 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5806 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5807 &args, sizeof(args));
5808 } else {
5809 ac_build_export(&ctx->ac, &args);
5810 }
5811 }
5812
5813 if (export_prim_id) {
5814 LLVMValueRef values[4];
5815 target = V_008DFC_SQ_EXP_PARAM + param_count;
5816 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5817 param_count++;
5818
5819 values[0] = ctx->vs_prim_id;
5820 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5821 ctx->shader_info->vs.vgpr_comp_cnt);
5822 for (unsigned j = 1; j < 4; j++)
5823 values[j] = ctx->ac.f32_0;
5824 si_llvm_init_export_args(ctx, values, target, &args);
5825 ac_build_export(&ctx->ac, &args);
5826 outinfo->export_prim_id = true;
5827 }
5828
5829 outinfo->pos_exports = num_pos_exports;
5830 outinfo->param_exports = param_count;
5831 }
5832
5833 static void
5834 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5835 struct ac_es_output_info *outinfo)
5836 {
5837 int j;
5838 uint64_t max_output_written = 0;
5839 LLVMValueRef lds_base = NULL;
5840
5841 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5842 int param_index;
5843 int length = 4;
5844
5845 if (!(ctx->output_mask & (1ull << i)))
5846 continue;
5847
5848 if (i == VARYING_SLOT_CLIP_DIST0)
5849 length = ctx->num_output_clips + ctx->num_output_culls;
5850
5851 param_index = shader_io_get_unique_index(i);
5852
5853 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5854 }
5855
5856 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5857
5858 if (ctx->ac.chip_class >= GFX9) {
5859 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5860 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5861 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5862 LLVMConstInt(ctx->ac.i32, 24, false),
5863 LLVMConstInt(ctx->ac.i32, 4, false), false);
5864 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5865 LLVMBuildMul(ctx->ac.builder, wave_idx,
5866 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5867 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5868 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5869 }
5870
5871 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5872 LLVMValueRef dw_addr;
5873 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5874 int param_index;
5875 int length = 4;
5876
5877 if (!(ctx->output_mask & (1ull << i)))
5878 continue;
5879
5880 if (i == VARYING_SLOT_CLIP_DIST0)
5881 length = ctx->num_output_clips + ctx->num_output_culls;
5882
5883 param_index = shader_io_get_unique_index(i);
5884
5885 if (lds_base) {
5886 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5887 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5888 "");
5889 }
5890 for (j = 0; j < length; j++) {
5891 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5892 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5893
5894 if (ctx->ac.chip_class >= GFX9) {
5895 ac_lds_store(&ctx->ac, dw_addr,
5896 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5897 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5898 } else {
5899 ac_build_buffer_store_dword(&ctx->ac,
5900 ctx->esgs_ring,
5901 out_val, 1,
5902 NULL, ctx->es2gs_offset,
5903 (4 * param_index + j) * 4,
5904 1, 1, true, true);
5905 }
5906 }
5907 }
5908 }
5909
5910 static void
5911 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5912 {
5913 LLVMValueRef vertex_id = ctx->rel_auto_id;
5914 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5915 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5916 vertex_dw_stride, "");
5917
5918 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5919 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5920 int length = 4;
5921
5922 if (!(ctx->output_mask & (1ull << i)))
5923 continue;
5924
5925 if (i == VARYING_SLOT_CLIP_DIST0)
5926 length = ctx->num_output_clips + ctx->num_output_culls;
5927 int param = shader_io_get_unique_index(i);
5928 mark_tess_output(ctx, false, param);
5929 if (length > 4)
5930 mark_tess_output(ctx, false, param + 1);
5931 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5932 LLVMConstInt(ctx->ac.i32, param * 4, false),
5933 "");
5934 for (unsigned j = 0; j < length; j++) {
5935 ac_lds_store(&ctx->ac, dw_addr,
5936 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5937 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5938 }
5939 }
5940 }
5941
5942 struct ac_build_if_state
5943 {
5944 struct nir_to_llvm_context *ctx;
5945 LLVMValueRef condition;
5946 LLVMBasicBlockRef entry_block;
5947 LLVMBasicBlockRef true_block;
5948 LLVMBasicBlockRef false_block;
5949 LLVMBasicBlockRef merge_block;
5950 };
5951
5952 static LLVMBasicBlockRef
5953 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5954 {
5955 LLVMBasicBlockRef current_block;
5956 LLVMBasicBlockRef next_block;
5957 LLVMBasicBlockRef new_block;
5958
5959 /* get current basic block */
5960 current_block = LLVMGetInsertBlock(ctx->builder);
5961
5962 /* chqeck if there's another block after this one */
5963 next_block = LLVMGetNextBasicBlock(current_block);
5964 if (next_block) {
5965 /* insert the new block before the next block */
5966 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5967 }
5968 else {
5969 /* append new block after current block */
5970 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5971 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5972 }
5973 return new_block;
5974 }
5975
5976 static void
5977 ac_nir_build_if(struct ac_build_if_state *ifthen,
5978 struct nir_to_llvm_context *ctx,
5979 LLVMValueRef condition)
5980 {
5981 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5982
5983 memset(ifthen, 0, sizeof *ifthen);
5984 ifthen->ctx = ctx;
5985 ifthen->condition = condition;
5986 ifthen->entry_block = block;
5987
5988 /* create endif/merge basic block for the phi functions */
5989 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5990
5991 /* create/insert true_block before merge_block */
5992 ifthen->true_block =
5993 LLVMInsertBasicBlockInContext(ctx->context,
5994 ifthen->merge_block,
5995 "if-true-block");
5996
5997 /* successive code goes into the true block */
5998 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5999 }
6000
6001 /**
6002 * End a conditional.
6003 */
6004 static void
6005 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6006 {
6007 LLVMBuilderRef builder = ifthen->ctx->builder;
6008
6009 /* Insert branch to the merge block from current block */
6010 LLVMBuildBr(builder, ifthen->merge_block);
6011
6012 /*
6013 * Now patch in the various branch instructions.
6014 */
6015
6016 /* Insert the conditional branch instruction at the end of entry_block */
6017 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6018 if (ifthen->false_block) {
6019 /* we have an else clause */
6020 LLVMBuildCondBr(builder, ifthen->condition,
6021 ifthen->true_block, ifthen->false_block);
6022 }
6023 else {
6024 /* no else clause */
6025 LLVMBuildCondBr(builder, ifthen->condition,
6026 ifthen->true_block, ifthen->merge_block);
6027 }
6028
6029 /* Resume building code at end of the ifthen->merge_block */
6030 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6031 }
6032
6033 static void
6034 write_tess_factors(struct nir_to_llvm_context *ctx)
6035 {
6036 unsigned stride, outer_comps, inner_comps;
6037 struct ac_build_if_state if_ctx, inner_if_ctx;
6038 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6039 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6040 unsigned tess_inner_index, tess_outer_index;
6041 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6042 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6043 int i;
6044 emit_barrier(ctx);
6045
6046 switch (ctx->options->key.tcs.primitive_mode) {
6047 case GL_ISOLINES:
6048 stride = 2;
6049 outer_comps = 2;
6050 inner_comps = 0;
6051 break;
6052 case GL_TRIANGLES:
6053 stride = 4;
6054 outer_comps = 3;
6055 inner_comps = 1;
6056 break;
6057 case GL_QUADS:
6058 stride = 6;
6059 outer_comps = 4;
6060 inner_comps = 2;
6061 break;
6062 default:
6063 return;
6064 }
6065
6066 ac_nir_build_if(&if_ctx, ctx,
6067 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6068 invocation_id, ctx->ac.i32_0, ""));
6069
6070 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6071 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6072
6073 mark_tess_output(ctx, true, tess_inner_index);
6074 mark_tess_output(ctx, true, tess_outer_index);
6075 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6076 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6077 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6078 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6079 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6080
6081 for (i = 0; i < 4; i++) {
6082 inner[i] = LLVMGetUndef(ctx->ac.i32);
6083 outer[i] = LLVMGetUndef(ctx->ac.i32);
6084 }
6085
6086 // LINES reverseal
6087 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6088 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6089 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6090 ctx->ac.i32_1, "");
6091 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6092 } else {
6093 for (i = 0; i < outer_comps; i++) {
6094 outer[i] = out[i] =
6095 ac_lds_load(&ctx->ac, lds_outer);
6096 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6097 ctx->ac.i32_1, "");
6098 }
6099 for (i = 0; i < inner_comps; i++) {
6100 inner[i] = out[outer_comps+i] =
6101 ac_lds_load(&ctx->ac, lds_inner);
6102 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6103 ctx->ac.i32_1, "");
6104 }
6105 }
6106
6107 /* Convert the outputs to vectors for stores. */
6108 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6109 vec1 = NULL;
6110
6111 if (stride > 4)
6112 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6113
6114
6115 buffer = ctx->hs_ring_tess_factor;
6116 tf_base = ctx->tess_factor_offset;
6117 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6118 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6119 unsigned tf_offset = 0;
6120
6121 if (ctx->options->chip_class <= VI) {
6122 ac_nir_build_if(&inner_if_ctx, ctx,
6123 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6124 rel_patch_id, ctx->ac.i32_0, ""));
6125
6126 /* Store the dynamic HS control word. */
6127 ac_build_buffer_store_dword(&ctx->ac, buffer,
6128 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6129 1, ctx->ac.i32_0, tf_base,
6130 0, 1, 0, true, false);
6131 tf_offset += 4;
6132
6133 ac_nir_build_endif(&inner_if_ctx);
6134 }
6135
6136 /* Store the tessellation factors. */
6137 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6138 MIN2(stride, 4), byteoffset, tf_base,
6139 tf_offset, 1, 0, true, false);
6140 if (vec1)
6141 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6142 stride - 4, byteoffset, tf_base,
6143 16 + tf_offset, 1, 0, true, false);
6144
6145 //store to offchip for TES to read - only if TES reads them
6146 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6147 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6148 LLVMValueRef tf_inner_offset;
6149 unsigned param_outer, param_inner;
6150
6151 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6152 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6153 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6154
6155 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6156 util_next_power_of_two(outer_comps));
6157
6158 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6159 outer_comps, tf_outer_offset,
6160 ctx->oc_lds, 0, 1, 0, true, false);
6161 if (inner_comps) {
6162 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6163 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6164 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6165
6166 inner_vec = inner_comps == 1 ? inner[0] :
6167 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6168 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6169 inner_comps, tf_inner_offset,
6170 ctx->oc_lds, 0, 1, 0, true, false);
6171 }
6172 }
6173 ac_nir_build_endif(&if_ctx);
6174 }
6175
6176 static void
6177 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6178 {
6179 write_tess_factors(ctx);
6180 }
6181
6182 static bool
6183 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6184 LLVMValueRef *color, unsigned param, bool is_last,
6185 struct ac_export_args *args)
6186 {
6187 /* Export */
6188 si_llvm_init_export_args(ctx, color, param,
6189 args);
6190
6191 if (is_last) {
6192 args->valid_mask = 1; /* whether the EXEC mask is valid */
6193 args->done = 1; /* DONE bit */
6194 } else if (!args->enabled_channels)
6195 return false; /* unnecessary NULL export */
6196
6197 return true;
6198 }
6199
6200 static void
6201 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6202 LLVMValueRef depth, LLVMValueRef stencil,
6203 LLVMValueRef samplemask)
6204 {
6205 struct ac_export_args args;
6206
6207 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6208
6209 ac_build_export(&ctx->ac, &args);
6210 }
6211
6212 static void
6213 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6214 {
6215 unsigned index = 0;
6216 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6217 struct ac_export_args color_args[8];
6218
6219 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6220 LLVMValueRef values[4];
6221
6222 if (!(ctx->output_mask & (1ull << i)))
6223 continue;
6224
6225 if (i == FRAG_RESULT_DEPTH) {
6226 ctx->shader_info->fs.writes_z = true;
6227 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6228 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6229 } else if (i == FRAG_RESULT_STENCIL) {
6230 ctx->shader_info->fs.writes_stencil = true;
6231 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6232 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6233 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6234 ctx->shader_info->fs.writes_sample_mask = true;
6235 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6236 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6237 } else {
6238 bool last = false;
6239 for (unsigned j = 0; j < 4; j++)
6240 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6241 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6242
6243 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6244 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6245
6246 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6247 if (ret)
6248 index++;
6249 }
6250 }
6251
6252 for (unsigned i = 0; i < index; i++)
6253 ac_build_export(&ctx->ac, &color_args[i]);
6254 if (depth || stencil || samplemask)
6255 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6256 else if (!index) {
6257 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6258 ac_build_export(&ctx->ac, &color_args[0]);
6259 }
6260
6261 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6262 }
6263
6264 static void
6265 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6266 {
6267 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6268 }
6269
6270 static void
6271 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6272 LLVMValueRef *addrs)
6273 {
6274 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6275
6276 switch (ctx->stage) {
6277 case MESA_SHADER_VERTEX:
6278 if (ctx->options->key.vs.as_ls)
6279 handle_ls_outputs_post(ctx);
6280 else if (ctx->options->key.vs.as_es)
6281 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6282 else
6283 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6284 &ctx->shader_info->vs.outinfo);
6285 break;
6286 case MESA_SHADER_FRAGMENT:
6287 handle_fs_outputs_post(ctx);
6288 break;
6289 case MESA_SHADER_GEOMETRY:
6290 emit_gs_epilogue(ctx);
6291 break;
6292 case MESA_SHADER_TESS_CTRL:
6293 handle_tcs_outputs_post(ctx);
6294 break;
6295 case MESA_SHADER_TESS_EVAL:
6296 if (ctx->options->key.tes.as_es)
6297 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6298 else
6299 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6300 &ctx->shader_info->tes.outinfo);
6301 break;
6302 default:
6303 break;
6304 }
6305 }
6306
6307 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6308 {
6309 LLVMPassManagerRef passmgr;
6310 /* Create the pass manager */
6311 passmgr = LLVMCreateFunctionPassManagerForModule(
6312 ctx->module);
6313
6314 /* This pass should eliminate all the load and store instructions */
6315 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6316
6317 /* Add some optimization passes */
6318 LLVMAddScalarReplAggregatesPass(passmgr);
6319 LLVMAddLICMPass(passmgr);
6320 LLVMAddAggressiveDCEPass(passmgr);
6321 LLVMAddCFGSimplificationPass(passmgr);
6322 LLVMAddInstructionCombiningPass(passmgr);
6323
6324 /* Run the pass */
6325 LLVMInitializeFunctionPassManager(passmgr);
6326 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6327 LLVMFinalizeFunctionPassManager(passmgr);
6328
6329 LLVMDisposeBuilder(ctx->builder);
6330 LLVMDisposePassManager(passmgr);
6331 }
6332
6333 static void
6334 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6335 {
6336 struct ac_vs_output_info *outinfo;
6337
6338 switch (ctx->stage) {
6339 case MESA_SHADER_FRAGMENT:
6340 case MESA_SHADER_COMPUTE:
6341 case MESA_SHADER_TESS_CTRL:
6342 case MESA_SHADER_GEOMETRY:
6343 return;
6344 case MESA_SHADER_VERTEX:
6345 if (ctx->options->key.vs.as_ls ||
6346 ctx->options->key.vs.as_es)
6347 return;
6348 outinfo = &ctx->shader_info->vs.outinfo;
6349 break;
6350 case MESA_SHADER_TESS_EVAL:
6351 if (ctx->options->key.vs.as_es)
6352 return;
6353 outinfo = &ctx->shader_info->tes.outinfo;
6354 break;
6355 default:
6356 unreachable("Unhandled shader type");
6357 }
6358
6359 ac_optimize_vs_outputs(&ctx->ac,
6360 ctx->main_function,
6361 outinfo->vs_output_param_offset,
6362 VARYING_SLOT_MAX,
6363 &outinfo->param_exports);
6364 }
6365
6366 static void
6367 ac_setup_rings(struct nir_to_llvm_context *ctx)
6368 {
6369 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6370 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6371 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6372 }
6373
6374 if (ctx->is_gs_copy_shader) {
6375 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6376 }
6377 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6378 LLVMValueRef tmp;
6379 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6380 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6381
6382 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6383
6384 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6385 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6386 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6387 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6388 }
6389
6390 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6391 ctx->stage == MESA_SHADER_TESS_EVAL) {
6392 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6393 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6394 }
6395 }
6396
6397 static unsigned
6398 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6399 const struct nir_shader *nir)
6400 {
6401 switch (nir->info.stage) {
6402 case MESA_SHADER_TESS_CTRL:
6403 return chip_class >= CIK ? 128 : 64;
6404 case MESA_SHADER_GEOMETRY:
6405 return chip_class >= GFX9 ? 128 : 64;
6406 case MESA_SHADER_COMPUTE:
6407 break;
6408 default:
6409 return 0;
6410 }
6411
6412 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6413 nir->info.cs.local_size[1] *
6414 nir->info.cs.local_size[2];
6415 return max_workgroup_size;
6416 }
6417
6418 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6419 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6420 {
6421 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6422 LLVMConstInt(ctx->ac.i32, 8, false),
6423 LLVMConstInt(ctx->ac.i32, 8, false), false);
6424 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6425 ctx->ac.i32_0, "");
6426 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6427 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6428 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6429 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6430 }
6431
6432 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6433 {
6434 for(int i = 5; i >= 0; --i) {
6435 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6436 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6437 LLVMConstInt(ctx->ac.i32, 16, false), false);
6438 }
6439
6440 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6441 LLVMConstInt(ctx->ac.i32, 16, false),
6442 LLVMConstInt(ctx->ac.i32, 8, false), false);
6443 }
6444
6445 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6446 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6447 {
6448 struct ac_nir_context ctx = {};
6449 struct nir_function *func;
6450
6451 ctx.ac = *ac;
6452 ctx.abi = abi;
6453
6454 ctx.nctx = nctx;
6455 if (nctx)
6456 nctx->nir = &ctx;
6457
6458 ctx.stage = nir->info.stage;
6459
6460 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6461
6462 nir_foreach_variable(variable, &nir->outputs)
6463 handle_shader_output_decl(&ctx, nir, variable);
6464
6465 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6466 _mesa_key_pointer_equal);
6467 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6468 _mesa_key_pointer_equal);
6469 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6470 _mesa_key_pointer_equal);
6471
6472 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6473
6474 setup_locals(&ctx, func);
6475
6476 if (nir->info.stage == MESA_SHADER_COMPUTE)
6477 setup_shared(&ctx, nir);
6478
6479 visit_cf_list(&ctx, &func->impl->body);
6480 phi_post_pass(&ctx);
6481
6482 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6483 ctx.outputs);
6484
6485 free(ctx.locals);
6486 ralloc_free(ctx.defs);
6487 ralloc_free(ctx.phis);
6488 ralloc_free(ctx.vars);
6489
6490 if (nctx)
6491 nctx->nir = NULL;
6492 }
6493
6494 static
6495 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6496 struct nir_shader *const *shaders,
6497 int shader_count,
6498 struct ac_shader_variant_info *shader_info,
6499 const struct ac_nir_compiler_options *options)
6500 {
6501 struct nir_to_llvm_context ctx = {0};
6502 unsigned i;
6503 ctx.options = options;
6504 ctx.shader_info = shader_info;
6505 ctx.context = LLVMContextCreate();
6506 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6507
6508 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6509 options->family);
6510 ctx.ac.module = ctx.module;
6511 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6512
6513 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6514 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6515 LLVMSetDataLayout(ctx.module, data_layout_str);
6516 LLVMDisposeTargetData(data_layout);
6517 LLVMDisposeMessage(data_layout_str);
6518
6519 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6520 ctx.ac.builder = ctx.builder;
6521
6522 memset(shader_info, 0, sizeof(*shader_info));
6523
6524 for(int i = 0; i < shader_count; ++i)
6525 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6526
6527 for (i = 0; i < AC_UD_MAX_SETS; i++)
6528 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6529 for (i = 0; i < AC_UD_MAX_UD; i++)
6530 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6531
6532 ctx.max_workgroup_size = 0;
6533 for (int i = 0; i < shader_count; ++i) {
6534 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6535 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6536 shaders[i]));
6537 }
6538
6539 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6540 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6541
6542 ctx.abi.inputs = &ctx.inputs[0];
6543 ctx.abi.emit_outputs = handle_shader_outputs_post;
6544 ctx.abi.emit_vertex = visit_emit_vertex;
6545 ctx.abi.load_ubo = radv_load_ubo;
6546 ctx.abi.load_ssbo = radv_load_ssbo;
6547 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6548 ctx.abi.clamp_shadow_reference = false;
6549
6550 if (shader_count >= 2)
6551 ac_init_exec_full_mask(&ctx.ac);
6552
6553 if (ctx.ac.chip_class == GFX9 &&
6554 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6555 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6556
6557 for(int i = 0; i < shader_count; ++i) {
6558 ctx.stage = shaders[i]->info.stage;
6559 ctx.output_mask = 0;
6560 ctx.tess_outputs_written = 0;
6561 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6562 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6563
6564 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6565 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6566 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6567 ctx.abi.load_inputs = load_gs_input;
6568 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6569 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6570 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6571 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6572 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6573 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6574 if (shader_info->info.vs.needs_instance_id) {
6575 ctx.shader_info->vs.vgpr_comp_cnt =
6576 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6577 }
6578 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6579 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6580 }
6581
6582 if (i)
6583 emit_barrier(&ctx);
6584
6585 ac_setup_rings(&ctx);
6586
6587 LLVMBasicBlockRef merge_block;
6588 if (shader_count >= 2) {
6589 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6590 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6591 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6592
6593 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6594 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6595 LLVMConstInt(ctx.ac.i32, 8, false), false);
6596 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6597 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6598 thread_id, count, "");
6599 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6600
6601 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6602 }
6603
6604 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6605 handle_fs_inputs(&ctx, shaders[i]);
6606 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6607 handle_vs_inputs(&ctx, shaders[i]);
6608 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6609 prepare_gs_input_vgprs(&ctx);
6610
6611 nir_foreach_variable(variable, &shaders[i]->outputs)
6612 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6613
6614 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6615
6616 if (shader_count >= 2) {
6617 LLVMBuildBr(ctx.ac.builder, merge_block);
6618 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6619 }
6620
6621 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6622 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6623 shaders[i]->info.cull_distance_array_size > 4;
6624 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6625 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6626 shaders[i]->info.gs.vertices_out;
6627 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6628 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6629 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6630 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6631 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6632 }
6633 }
6634
6635 LLVMBuildRetVoid(ctx.builder);
6636
6637 ac_llvm_finalize_module(&ctx);
6638
6639 if (shader_count == 1)
6640 ac_nir_eliminate_const_vs_outputs(&ctx);
6641
6642 return ctx.module;
6643 }
6644
6645 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6646 {
6647 unsigned *retval = (unsigned *)context;
6648 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6649 char *description = LLVMGetDiagInfoDescription(di);
6650
6651 if (severity == LLVMDSError) {
6652 *retval = 1;
6653 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6654 description);
6655 }
6656
6657 LLVMDisposeMessage(description);
6658 }
6659
6660 static unsigned ac_llvm_compile(LLVMModuleRef M,
6661 struct ac_shader_binary *binary,
6662 LLVMTargetMachineRef tm)
6663 {
6664 unsigned retval = 0;
6665 char *err;
6666 LLVMContextRef llvm_ctx;
6667 LLVMMemoryBufferRef out_buffer;
6668 unsigned buffer_size;
6669 const char *buffer_data;
6670 LLVMBool mem_err;
6671
6672 /* Setup Diagnostic Handler*/
6673 llvm_ctx = LLVMGetModuleContext(M);
6674
6675 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6676 &retval);
6677
6678 /* Compile IR*/
6679 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6680 &err, &out_buffer);
6681
6682 /* Process Errors/Warnings */
6683 if (mem_err) {
6684 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6685 free(err);
6686 retval = 1;
6687 goto out;
6688 }
6689
6690 /* Extract Shader Code*/
6691 buffer_size = LLVMGetBufferSize(out_buffer);
6692 buffer_data = LLVMGetBufferStart(out_buffer);
6693
6694 ac_elf_read(buffer_data, buffer_size, binary);
6695
6696 /* Clean up */
6697 LLVMDisposeMemoryBuffer(out_buffer);
6698
6699 out:
6700 return retval;
6701 }
6702
6703 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6704 LLVMModuleRef llvm_module,
6705 struct ac_shader_binary *binary,
6706 struct ac_shader_config *config,
6707 struct ac_shader_variant_info *shader_info,
6708 gl_shader_stage stage,
6709 bool dump_shader, bool supports_spill)
6710 {
6711 if (dump_shader)
6712 ac_dump_module(llvm_module);
6713
6714 memset(binary, 0, sizeof(*binary));
6715 int v = ac_llvm_compile(llvm_module, binary, tm);
6716 if (v) {
6717 fprintf(stderr, "compile failed\n");
6718 }
6719
6720 if (dump_shader)
6721 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6722
6723 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6724
6725 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6726 LLVMDisposeModule(llvm_module);
6727 LLVMContextDispose(ctx);
6728
6729 if (stage == MESA_SHADER_FRAGMENT) {
6730 shader_info->num_input_vgprs = 0;
6731 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6732 shader_info->num_input_vgprs += 2;
6733 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6734 shader_info->num_input_vgprs += 2;
6735 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6736 shader_info->num_input_vgprs += 2;
6737 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6738 shader_info->num_input_vgprs += 3;
6739 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6740 shader_info->num_input_vgprs += 2;
6741 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6742 shader_info->num_input_vgprs += 2;
6743 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6744 shader_info->num_input_vgprs += 2;
6745 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6746 shader_info->num_input_vgprs += 1;
6747 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6748 shader_info->num_input_vgprs += 1;
6749 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6750 shader_info->num_input_vgprs += 1;
6751 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6752 shader_info->num_input_vgprs += 1;
6753 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6754 shader_info->num_input_vgprs += 1;
6755 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6756 shader_info->num_input_vgprs += 1;
6757 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6758 shader_info->num_input_vgprs += 1;
6759 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6760 shader_info->num_input_vgprs += 1;
6761 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6762 shader_info->num_input_vgprs += 1;
6763 }
6764 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6765
6766 /* +3 for scratch wave offset and VCC */
6767 config->num_sgprs = MAX2(config->num_sgprs,
6768 shader_info->num_input_sgprs + 3);
6769 }
6770
6771 static void
6772 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6773 {
6774 switch (nir->info.stage) {
6775 case MESA_SHADER_COMPUTE:
6776 for (int i = 0; i < 3; ++i)
6777 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6778 break;
6779 case MESA_SHADER_FRAGMENT:
6780 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6781 break;
6782 case MESA_SHADER_GEOMETRY:
6783 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6784 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6785 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6786 shader_info->gs.invocations = nir->info.gs.invocations;
6787 break;
6788 case MESA_SHADER_TESS_EVAL:
6789 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6790 shader_info->tes.spacing = nir->info.tess.spacing;
6791 shader_info->tes.ccw = nir->info.tess.ccw;
6792 shader_info->tes.point_mode = nir->info.tess.point_mode;
6793 shader_info->tes.as_es = options->key.tes.as_es;
6794 break;
6795 case MESA_SHADER_TESS_CTRL:
6796 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6797 break;
6798 case MESA_SHADER_VERTEX:
6799 shader_info->vs.as_es = options->key.vs.as_es;
6800 shader_info->vs.as_ls = options->key.vs.as_ls;
6801 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6802 if (options->key.vs.as_ls)
6803 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6804 break;
6805 default:
6806 break;
6807 }
6808 }
6809
6810 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6811 struct ac_shader_binary *binary,
6812 struct ac_shader_config *config,
6813 struct ac_shader_variant_info *shader_info,
6814 struct nir_shader *const *nir,
6815 int nir_count,
6816 const struct ac_nir_compiler_options *options,
6817 bool dump_shader)
6818 {
6819
6820 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6821 options);
6822
6823 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6824 for (int i = 0; i < nir_count; ++i)
6825 ac_fill_shader_info(shader_info, nir[i], options);
6826 }
6827
6828 static void
6829 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6830 {
6831 LLVMValueRef args[9];
6832 args[0] = ctx->gsvs_ring;
6833 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6834 args[3] = ctx->ac.i32_0;
6835 args[4] = ctx->ac.i32_1; /* OFFEN */
6836 args[5] = ctx->ac.i32_0; /* IDXEN */
6837 args[6] = ctx->ac.i32_1; /* GLC */
6838 args[7] = ctx->ac.i32_1; /* SLC */
6839 args[8] = ctx->ac.i32_0; /* TFE */
6840
6841 int idx = 0;
6842
6843 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6844 int length = 4;
6845 int slot = idx;
6846 int slot_inc = 1;
6847 if (!(ctx->output_mask & (1ull << i)))
6848 continue;
6849
6850 if (i == VARYING_SLOT_CLIP_DIST0) {
6851 /* unpack clip and cull from a single set of slots */
6852 length = ctx->num_output_clips + ctx->num_output_culls;
6853 if (length > 4)
6854 slot_inc = 2;
6855 }
6856
6857 for (unsigned j = 0; j < length; j++) {
6858 LLVMValueRef value;
6859 args[2] = LLVMConstInt(ctx->ac.i32,
6860 (slot * 4 + j) *
6861 ctx->gs_max_out_vertices * 16 * 4, false);
6862
6863 value = ac_build_intrinsic(&ctx->ac,
6864 "llvm.SI.buffer.load.dword.i32.i32",
6865 ctx->ac.i32, args, 9,
6866 AC_FUNC_ATTR_READONLY |
6867 AC_FUNC_ATTR_LEGACY);
6868
6869 LLVMBuildStore(ctx->builder,
6870 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6871 }
6872 idx += slot_inc;
6873 }
6874 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6875 }
6876
6877 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6878 struct nir_shader *geom_shader,
6879 struct ac_shader_binary *binary,
6880 struct ac_shader_config *config,
6881 struct ac_shader_variant_info *shader_info,
6882 const struct ac_nir_compiler_options *options,
6883 bool dump_shader)
6884 {
6885 struct nir_to_llvm_context ctx = {0};
6886 ctx.context = LLVMContextCreate();
6887 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6888 ctx.options = options;
6889 ctx.shader_info = shader_info;
6890
6891 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6892 options->family);
6893 ctx.ac.module = ctx.module;
6894
6895 ctx.is_gs_copy_shader = true;
6896 LLVMSetTarget(ctx.module, "amdgcn--");
6897
6898 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6899 ctx.ac.builder = ctx.builder;
6900 ctx.stage = MESA_SHADER_VERTEX;
6901
6902 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6903
6904 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6905 ac_setup_rings(&ctx);
6906
6907 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6908 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6909
6910 struct ac_nir_context nir_ctx = {};
6911 nir_ctx.ac = ctx.ac;
6912 nir_ctx.abi = &ctx.abi;
6913
6914 nir_ctx.nctx = &ctx;
6915 ctx.nir = &nir_ctx;
6916
6917 nir_foreach_variable(variable, &geom_shader->outputs) {
6918 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6919 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6920 }
6921
6922 ac_gs_copy_shader_emit(&ctx);
6923
6924 ctx.nir = NULL;
6925
6926 LLVMBuildRetVoid(ctx.builder);
6927
6928 ac_llvm_finalize_module(&ctx);
6929
6930 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6931 MESA_SHADER_VERTEX,
6932 dump_shader, options->supports_spill);
6933 }