projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ac/nir: Make intrinsic_name buffer long enough
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 #include "ac_exp_param.h"
35
36 enum radeon_llvm_calling_convention {
37 RADEON_LLVM_AMDGPU_VS = 87,
38 RADEON_LLVM_AMDGPU_GS = 88,
39 RADEON_LLVM_AMDGPU_PS = 89,
40 RADEON_LLVM_AMDGPU_CS = 90,
41 };
42
43 #define CONST_ADDR_SPACE 2
44 #define LOCAL_ADDR_SPACE 3
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 enum desc_type {
50 DESC_IMAGE,
51 DESC_FMASK,
52 DESC_SAMPLER,
53 DESC_BUFFER,
54 };
55
56 struct nir_to_llvm_context {
57 struct ac_llvm_context ac;
58 const struct ac_nir_compiler_options *options;
59 struct ac_shader_variant_info *shader_info;
60 unsigned max_workgroup_size;
61 LLVMContextRef context;
62 LLVMModuleRef module;
63 LLVMBuilderRef builder;
64 LLVMValueRef main_function;
65
66 struct hash_table *defs;
67 struct hash_table *phis;
68
69 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
70 LLVMValueRef ring_offsets;
71 LLVMValueRef push_constants;
72 LLVMValueRef num_work_groups;
73 LLVMValueRef workgroup_ids;
74 LLVMValueRef local_invocation_ids;
75 LLVMValueRef tg_size;
76
77 LLVMValueRef vertex_buffers;
78 LLVMValueRef base_vertex;
79 LLVMValueRef start_instance;
80 LLVMValueRef draw_index;
81 LLVMValueRef vertex_id;
82 LLVMValueRef rel_auto_id;
83 LLVMValueRef vs_prim_id;
84 LLVMValueRef instance_id;
85 LLVMValueRef ls_out_layout;
86 LLVMValueRef es2gs_offset;
87
88 LLVMValueRef tcs_offchip_layout;
89 LLVMValueRef tcs_out_offsets;
90 LLVMValueRef tcs_out_layout;
91 LLVMValueRef tcs_in_layout;
92 LLVMValueRef oc_lds;
93 LLVMValueRef tess_factor_offset;
94 LLVMValueRef tcs_patch_id;
95 LLVMValueRef tcs_rel_ids;
96 LLVMValueRef tes_rel_patch_id;
97 LLVMValueRef tes_patch_id;
98 LLVMValueRef tes_u;
99 LLVMValueRef tes_v;
100
101 LLVMValueRef gsvs_ring_stride;
102 LLVMValueRef gsvs_num_entries;
103 LLVMValueRef gs2vs_offset;
104 LLVMValueRef gs_wave_id;
105 LLVMValueRef gs_vtx_offset[6];
106 LLVMValueRef gs_prim_id, gs_invocation_id;
107
108 LLVMValueRef esgs_ring;
109 LLVMValueRef gsvs_ring;
110 LLVMValueRef hs_ring_tess_offchip;
111 LLVMValueRef hs_ring_tess_factor;
112
113 LLVMValueRef prim_mask;
114 LLVMValueRef sample_pos_offset;
115 LLVMValueRef persp_sample, persp_center, persp_centroid;
116 LLVMValueRef linear_sample, linear_center, linear_centroid;
117 LLVMValueRef front_face;
118 LLVMValueRef ancillary;
119 LLVMValueRef sample_coverage;
120 LLVMValueRef frag_pos[4];
121
122 LLVMBasicBlockRef continue_block;
123 LLVMBasicBlockRef break_block;
124
125 LLVMTypeRef i1;
126 LLVMTypeRef i8;
127 LLVMTypeRef i16;
128 LLVMTypeRef i32;
129 LLVMTypeRef i64;
130 LLVMTypeRef v2i32;
131 LLVMTypeRef v3i32;
132 LLVMTypeRef v4i32;
133 LLVMTypeRef v8i32;
134 LLVMTypeRef f64;
135 LLVMTypeRef f32;
136 LLVMTypeRef f16;
137 LLVMTypeRef v2f32;
138 LLVMTypeRef v4f32;
139 LLVMTypeRef v16i8;
140 LLVMTypeRef voidt;
141
142 LLVMValueRef i1true;
143 LLVMValueRef i1false;
144 LLVMValueRef i32zero;
145 LLVMValueRef i32one;
146 LLVMValueRef f32zero;
147 LLVMValueRef f32one;
148 LLVMValueRef v4f32empty;
149
150 unsigned uniform_md_kind;
151 LLVMValueRef empty_md;
152 gl_shader_stage stage;
153
154 LLVMValueRef lds;
155 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
156 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
157
158 LLVMValueRef shared_memory;
159 uint64_t input_mask;
160 uint64_t output_mask;
161 int num_locals;
162 LLVMValueRef *locals;
163 uint8_t num_output_clips;
164 uint8_t num_output_culls;
165
166 bool has_ds_bpermute;
167
168 bool is_gs_copy_shader;
169 LLVMValueRef gs_next_vertex;
170 unsigned gs_max_out_vertices;
171
172 unsigned tes_primitive_mode;
173 uint64_t tess_outputs_written;
174 uint64_t tess_patch_outputs_written;
175 };
176
177 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
178 const nir_deref_var *deref,
179 enum desc_type desc_type);
180 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
181 {
182 return (index * 4) + chan;
183 }
184
185 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
186 {
187 /* handle patch indices separate */
188 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
189 return 0;
190 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
191 return 1;
192 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
193 return 2 + (slot - VARYING_SLOT_PATCH0);
194
195 if (slot == VARYING_SLOT_POS)
196 return 0;
197 if (slot == VARYING_SLOT_PSIZ)
198 return 1;
199 if (slot == VARYING_SLOT_CLIP_DIST0)
200 return 2;
201 /* 3 is reserved for clip dist as well */
202 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
203 return 4 + (slot - VARYING_SLOT_VAR0);
204 unreachable("illegal slot in get unique index\n");
205 }
206
207 static unsigned llvm_get_type_size(LLVMTypeRef type)
208 {
209 LLVMTypeKind kind = LLVMGetTypeKind(type);
210
211 switch (kind) {
212 case LLVMIntegerTypeKind:
213 return LLVMGetIntTypeWidth(type) / 8;
214 case LLVMFloatTypeKind:
215 return 4;
216 case LLVMPointerTypeKind:
217 return 8;
218 case LLVMVectorTypeKind:
219 return LLVMGetVectorSize(type) *
220 llvm_get_type_size(LLVMGetElementType(type));
221 default:
222 assert(0);
223 return 0;
224 }
225 }
226
227 static void set_llvm_calling_convention(LLVMValueRef func,
228 gl_shader_stage stage)
229 {
230 enum radeon_llvm_calling_convention calling_conv;
231
232 switch (stage) {
233 case MESA_SHADER_VERTEX:
234 case MESA_SHADER_TESS_CTRL:
235 case MESA_SHADER_TESS_EVAL:
236 calling_conv = RADEON_LLVM_AMDGPU_VS;
237 break;
238 case MESA_SHADER_GEOMETRY:
239 calling_conv = RADEON_LLVM_AMDGPU_GS;
240 break;
241 case MESA_SHADER_FRAGMENT:
242 calling_conv = RADEON_LLVM_AMDGPU_PS;
243 break;
244 case MESA_SHADER_COMPUTE:
245 calling_conv = RADEON_LLVM_AMDGPU_CS;
246 break;
247 default:
248 unreachable("Unhandle shader type");
249 }
250
251 LLVMSetFunctionCallConv(func, calling_conv);
252 }
253
254 #define MAX_ARGS 23
255 struct arg_info {
256 LLVMTypeRef types[MAX_ARGS];
257 LLVMValueRef *assign[MAX_ARGS];
258 unsigned array_params_mask;
259 uint8_t count;
260 uint8_t user_sgpr_count;
261 uint8_t sgpr_count;
262 uint8_t num_user_sgprs_used;
263 uint8_t num_sgprs_used;
264 uint8_t num_vgprs_used;
265 };
266
267 static inline void
268 add_argument(struct arg_info *info,
269 LLVMTypeRef type, LLVMValueRef *param_ptr)
270 {
271 assert(info->count < MAX_ARGS);
272 info->assign[info->count] = param_ptr;
273 info->types[info->count] = type;
274 info->count++;
275 }
276
277 static inline void
278 add_sgpr_argument(struct arg_info *info,
279 LLVMTypeRef type, LLVMValueRef *param_ptr)
280 {
281 add_argument(info, type, param_ptr);
282 info->num_sgprs_used += llvm_get_type_size(type) / 4;
283 info->sgpr_count++;
284 }
285
286 static inline void
287 add_user_sgpr_argument(struct arg_info *info,
288 LLVMTypeRef type,
289 LLVMValueRef *param_ptr)
290 {
291 add_sgpr_argument(info, type, param_ptr);
292 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
293 info->user_sgpr_count++;
294 }
295
296 static inline void
297 add_vgpr_argument(struct arg_info *info,
298 LLVMTypeRef type,
299 LLVMValueRef *param_ptr)
300 {
301 add_argument(info, type, param_ptr);
302 info->num_vgprs_used += llvm_get_type_size(type) / 4;
303 }
304
305 static inline void
306 add_user_sgpr_array_argument(struct arg_info *info,
307 LLVMTypeRef type,
308 LLVMValueRef *param_ptr)
309 {
310 info->array_params_mask |= (1 << info->count);
311 add_user_sgpr_argument(info, type, param_ptr);
312 }
313
314 static void assign_arguments(LLVMValueRef main_function,
315 struct arg_info *info)
316 {
317 unsigned i;
318 for (i = 0; i < info->count; i++) {
319 if (info->assign[i])
320 *info->assign[i] = LLVMGetParam(main_function, i);
321 }
322 }
323
324 static LLVMValueRef
325 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
326 LLVMBuilderRef builder, LLVMTypeRef *return_types,
327 unsigned num_return_elems,
328 struct arg_info *args,
329 unsigned max_workgroup_size,
330 bool unsafe_math)
331 {
332 LLVMTypeRef main_function_type, ret_type;
333 LLVMBasicBlockRef main_function_body;
334
335 if (num_return_elems)
336 ret_type = LLVMStructTypeInContext(ctx, return_types,
337 num_return_elems, true);
338 else
339 ret_type = LLVMVoidTypeInContext(ctx);
340
341 /* Setup the function */
342 main_function_type =
343 LLVMFunctionType(ret_type, args->types, args->count, 0);
344 LLVMValueRef main_function =
345 LLVMAddFunction(module, "main", main_function_type);
346 main_function_body =
347 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
348 LLVMPositionBuilderAtEnd(builder, main_function_body);
349
350 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
351 for (unsigned i = 0; i < args->sgpr_count; ++i) {
352 if (args->array_params_mask & (1 << i)) {
353 LLVMValueRef P = LLVMGetParam(main_function, i);
354 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
355 ac_add_attr_dereferenceable(P, UINT64_MAX);
356 }
357 else {
358 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
359 }
360 }
361
362 if (max_workgroup_size) {
363 ac_llvm_add_target_dep_function_attr(main_function,
364 "amdgpu-max-work-group-size",
365 max_workgroup_size);
366 }
367 if (unsafe_math) {
368 /* These were copied from some LLVM test. */
369 LLVMAddTargetDependentFunctionAttr(main_function,
370 "less-precise-fpmad",
371 "true");
372 LLVMAddTargetDependentFunctionAttr(main_function,
373 "no-infs-fp-math",
374 "true");
375 LLVMAddTargetDependentFunctionAttr(main_function,
376 "no-nans-fp-math",
377 "true");
378 LLVMAddTargetDependentFunctionAttr(main_function,
379 "unsafe-fp-math",
380 "true");
381 }
382 return main_function;
383 }
384
385 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
386 {
387 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
388 CONST_ADDR_SPACE);
389 }
390
391 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
392 int idx,
393 LLVMTypeRef type)
394 {
395 LLVMValueRef offset;
396 LLVMValueRef ptr;
397 int addr_space;
398
399 offset = LLVMConstInt(ctx->i32, idx * 16, false);
400
401 ptr = ctx->shared_memory;
402 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
403 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
404 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
405 return ptr;
406 }
407
408 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
409 {
410 if (t == ctx->f16 || t == ctx->i16)
411 return ctx->i16;
412 else if (t == ctx->f32 || t == ctx->i32)
413 return ctx->i32;
414 else if (t == ctx->f64 || t == ctx->i64)
415 return ctx->i64;
416 else
417 unreachable("Unhandled integer size");
418 }
419
420 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
421 {
422 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
423 LLVMTypeRef elem_type = LLVMGetElementType(t);
424 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
425 LLVMGetVectorSize(t));
426 }
427 return to_integer_type_scalar(ctx, t);
428 }
429
430 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
431 {
432 LLVMTypeRef type = LLVMTypeOf(v);
433 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
434 }
435
436 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
437 {
438 if (t == ctx->i16 || t == ctx->f16)
439 return ctx->f16;
440 else if (t == ctx->i32 || t == ctx->f32)
441 return ctx->f32;
442 else if (t == ctx->i64 || t == ctx->f64)
443 return ctx->f64;
444 else
445 unreachable("Unhandled float size");
446 }
447
448 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
449 {
450 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
451 LLVMTypeRef elem_type = LLVMGetElementType(t);
452 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
453 LLVMGetVectorSize(t));
454 }
455 return to_float_type_scalar(ctx, t);
456 }
457
458 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
459 {
460 LLVMTypeRef type = LLVMTypeOf(v);
461 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
462 }
463
464 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
465 {
466 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
467 type = LLVMGetElementType(type);
468
469 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
470 return LLVMGetIntTypeWidth(type);
471
472 if (type == ctx->f16)
473 return 16;
474 if (type == ctx->f32)
475 return 32;
476 if (type == ctx->f64)
477 return 64;
478
479 unreachable("Unhandled type kind in get_elem_bits");
480 }
481
482 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
483 LLVMValueRef param, unsigned rshift,
484 unsigned bitwidth)
485 {
486 LLVMValueRef value = param;
487 if (rshift)
488 value = LLVMBuildLShr(ctx->builder, value,
489 LLVMConstInt(ctx->i32, rshift, false), "");
490
491 if (rshift + bitwidth < 32) {
492 unsigned mask = (1 << bitwidth) - 1;
493 value = LLVMBuildAnd(ctx->builder, value,
494 LLVMConstInt(ctx->i32, mask, false), "");
495 }
496 return value;
497 }
498
499 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
500 {
501 switch (ctx->stage) {
502 case MESA_SHADER_TESS_CTRL:
503 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
504 case MESA_SHADER_TESS_EVAL:
505 return ctx->tes_rel_patch_id;
506 break;
507 default:
508 unreachable("Illegal stage");
509 }
510 }
511
512 /* Tessellation shaders pass outputs to the next shader using LDS.
513 *
514 * LS outputs = TCS inputs
515 * TCS outputs = TES inputs
516 *
517 * The LDS layout is:
518 * - TCS inputs for patch 0
519 * - TCS inputs for patch 1
520 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
521 * - ...
522 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
523 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
524 * - TCS outputs for patch 1
525 * - Per-patch TCS outputs for patch 1
526 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
527 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
528 * - ...
529 *
530 * All three shaders VS(LS), TCS, TES share the same LDS space.
531 */
532 static LLVMValueRef
533 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
534 {
535 if (ctx->stage == MESA_SHADER_VERTEX)
536 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
537 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
538 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
539 else {
540 assert(0);
541 return NULL;
542 }
543 }
544
545 static LLVMValueRef
546 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
547 {
548 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
549 }
550
551 static LLVMValueRef
552 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
553 {
554 return LLVMBuildMul(ctx->builder,
555 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
556 LLVMConstInt(ctx->i32, 4, false), "");
557 }
558
559 static LLVMValueRef
560 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
561 {
562 return LLVMBuildMul(ctx->builder,
563 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
564 LLVMConstInt(ctx->i32, 4, false), "");
565 }
566
567 static LLVMValueRef
568 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
569 {
570 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
571 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
572
573 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
574 }
575
576 static LLVMValueRef
577 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
578 {
579 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
580 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
581 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
582
583 return LLVMBuildAdd(ctx->builder, patch0_offset,
584 LLVMBuildMul(ctx->builder, patch_stride,
585 rel_patch_id, ""),
586 "");
587 }
588
589 static LLVMValueRef
590 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
591 {
592 LLVMValueRef patch0_patch_data_offset =
593 get_tcs_out_patch0_patch_data_offset(ctx);
594 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
595 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
596
597 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
598 LLVMBuildMul(ctx->builder, patch_stride,
599 rel_patch_id, ""),
600 "");
601 }
602
603 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
604 {
605 ud_info->sgpr_idx = *sgpr_idx;
606 ud_info->num_sgprs = num_sgprs;
607 ud_info->indirect = false;
608 ud_info->indirect_offset = 0;
609 *sgpr_idx += num_sgprs;
610 }
611
612 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
613 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
614 {
615 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
616 }
617
618
619 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
620 uint32_t indirect_offset)
621 {
622 ud_info->sgpr_idx = sgpr_idx;
623 ud_info->num_sgprs = num_sgprs;
624 ud_info->indirect = true;
625 ud_info->indirect_offset = indirect_offset;
626 }
627
628 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
629 {
630 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
631 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
632 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
633 "tess_lds");
634 }
635
636 struct user_sgpr_info {
637 bool need_ring_offsets;
638 uint8_t sgpr_count;
639 bool indirect_all_descriptor_sets;
640 };
641
642 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
643 struct user_sgpr_info *user_sgpr_info)
644 {
645 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
646
647 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
648 if (ctx->stage == MESA_SHADER_GEOMETRY ||
649 ctx->stage == MESA_SHADER_VERTEX ||
650 ctx->stage == MESA_SHADER_TESS_CTRL ||
651 ctx->stage == MESA_SHADER_TESS_EVAL ||
652 ctx->is_gs_copy_shader)
653 user_sgpr_info->need_ring_offsets = true;
654
655 if (ctx->stage == MESA_SHADER_FRAGMENT &&
656 ctx->shader_info->info.ps.needs_sample_positions)
657 user_sgpr_info->need_ring_offsets = true;
658
659 /* 2 user sgprs will nearly always be allocated for scratch/rings */
660 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
661 user_sgpr_info->sgpr_count += 2;
662 }
663
664 switch (ctx->stage) {
665 case MESA_SHADER_COMPUTE:
666 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
667 break;
668 case MESA_SHADER_FRAGMENT:
669 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
670 break;
671 case MESA_SHADER_VERTEX:
672 if (!ctx->is_gs_copy_shader) {
673 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
674 if (ctx->shader_info->info.vs.needs_draw_id) {
675 user_sgpr_info->sgpr_count += 3;
676 } else {
677 user_sgpr_info->sgpr_count += 2;
678 }
679 }
680 if (ctx->options->key.vs.as_ls)
681 user_sgpr_info->sgpr_count++;
682 break;
683 case MESA_SHADER_TESS_CTRL:
684 user_sgpr_info->sgpr_count += 4;
685 break;
686 case MESA_SHADER_TESS_EVAL:
687 user_sgpr_info->sgpr_count += 1;
688 break;
689 case MESA_SHADER_GEOMETRY:
690 user_sgpr_info->sgpr_count += 2;
691 break;
692 default:
693 break;
694 }
695
696 if (ctx->shader_info->info.needs_push_constants)
697 user_sgpr_info->sgpr_count += 2;
698
699 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
700 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
701 user_sgpr_info->sgpr_count += 2;
702 user_sgpr_info->indirect_all_descriptor_sets = true;
703 } else {
704 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
705 }
706 }
707
708 static void create_function(struct nir_to_llvm_context *ctx)
709 {
710 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
711 uint8_t user_sgpr_idx;
712 struct user_sgpr_info user_sgpr_info;
713 struct arg_info args = {};
714 LLVMValueRef desc_sets;
715
716 allocate_user_sgprs(ctx, &user_sgpr_info);
717 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
718 add_user_sgpr_argument(&args, const_array(ctx->v16i8, 16), &ctx->ring_offsets); /* address of rings */
719 }
720
721 /* 1 for each descriptor set */
722 if (!user_sgpr_info.indirect_all_descriptor_sets) {
723 for (unsigned i = 0; i < num_sets; ++i) {
724 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
725 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
726 }
727 }
728 } else
729 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
730
731 if (ctx->shader_info->info.needs_push_constants) {
732 /* 1 for push constants and dynamic descriptors */
733 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
734 }
735
736 switch (ctx->stage) {
737 case MESA_SHADER_COMPUTE:
738 if (ctx->shader_info->info.cs.grid_components_used)
739 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
740 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
741 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
742 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
743 break;
744 case MESA_SHADER_VERTEX:
745 if (!ctx->is_gs_copy_shader) {
746 if (ctx->shader_info->info.vs.has_vertex_buffers)
747 add_user_sgpr_argument(&args, const_array(ctx->v16i8, 16), &ctx->vertex_buffers); /* vertex buffers */
748 add_user_sgpr_argument(&args, ctx->i32, &ctx->base_vertex); // base vertex
749 add_user_sgpr_argument(&args, ctx->i32, &ctx->start_instance);// start instance
750 if (ctx->shader_info->info.vs.needs_draw_id)
751 add_user_sgpr_argument(&args, ctx->i32, &ctx->draw_index); // draw id
752 }
753 if (ctx->options->key.vs.as_es)
754 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
755 else if (ctx->options->key.vs.as_ls)
756 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
757 add_vgpr_argument(&args, ctx->i32, &ctx->vertex_id); // vertex id
758 if (!ctx->is_gs_copy_shader) {
759 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
760 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
761 add_vgpr_argument(&args, ctx->i32, &ctx->instance_id); // instance id
762 }
763 break;
764 case MESA_SHADER_TESS_CTRL:
765 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
766 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
767 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
768 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
769 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
770 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
771 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
772 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
773 break;
774 case MESA_SHADER_TESS_EVAL:
775 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
776 if (ctx->options->key.tes.as_es) {
777 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
778 add_sgpr_argument(&args, ctx->i32, NULL); //
779 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
780 } else {
781 add_sgpr_argument(&args, ctx->i32, NULL); //
782 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
783 }
784 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
785 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
786 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
787 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
788 break;
789 case MESA_SHADER_GEOMETRY:
790 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
791 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
792 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
793 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
796 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
797 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
798 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
799 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
800 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
801 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
802 break;
803 case MESA_SHADER_FRAGMENT:
804 if (ctx->shader_info->info.ps.needs_sample_positions)
805 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
806 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
807 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
808 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
809 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
810 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
811 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
812 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
813 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
814 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
815 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos x float */
816 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos y float */
817 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos z float */
818 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos w float */
819 add_vgpr_argument(&args, ctx->i32, &ctx->front_face); /* front face */
820 add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /* ancillary */
821 add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /* sample coverage */
822 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
823 break;
824 default:
825 unreachable("Shader stage not implemented");
826 }
827
828 ctx->main_function = create_llvm_function(
829 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
830 ctx->max_workgroup_size,
831 ctx->options->unsafe_math);
832 set_llvm_calling_convention(ctx->main_function, ctx->stage);
833
834
835 ctx->shader_info->num_input_vgprs = 0;
836 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
837 ctx->options->supports_spill ? 2 : 0;
838
839 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
840 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
841
842 if (ctx->stage != MESA_SHADER_FRAGMENT)
843 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
844
845 assign_arguments(ctx->main_function, &args);
846
847 user_sgpr_idx = 0;
848
849 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
850 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
851 if (ctx->options->supports_spill) {
852 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
853 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
854 NULL, 0, AC_FUNC_ATTR_READNONE);
855 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
856 const_array(ctx->v16i8, 16), "");
857 }
858 }
859
860 if (!user_sgpr_info.indirect_all_descriptor_sets) {
861 for (unsigned i = 0; i < num_sets; ++i) {
862 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
863 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
864 } else
865 ctx->descriptor_sets[i] = NULL;
866 }
867 } else {
868 uint32_t desc_sgpr_idx = user_sgpr_idx;
869 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
870
871 for (unsigned i = 0; i < num_sets; ++i) {
872 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
873 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
874 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
875
876 } else
877 ctx->descriptor_sets[i] = NULL;
878 }
879 ctx->shader_info->need_indirect_descriptor_sets = true;
880 }
881
882 if (ctx->shader_info->info.needs_push_constants) {
883 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
884 }
885
886 switch (ctx->stage) {
887 case MESA_SHADER_COMPUTE:
888 if (ctx->shader_info->info.cs.grid_components_used) {
889 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
890 }
891 break;
892 case MESA_SHADER_VERTEX:
893 if (!ctx->is_gs_copy_shader) {
894 if (ctx->shader_info->info.vs.has_vertex_buffers) {
895 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
896 }
897 unsigned vs_num = 2;
898 if (ctx->shader_info->info.vs.needs_draw_id)
899 vs_num++;
900
901 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
902 }
903 if (ctx->options->key.vs.as_ls) {
904 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
905 }
906 if (ctx->options->key.vs.as_ls)
907 declare_tess_lds(ctx);
908 break;
909 case MESA_SHADER_TESS_CTRL:
910 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
911 declare_tess_lds(ctx);
912 break;
913 case MESA_SHADER_TESS_EVAL:
914 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
915 break;
916 case MESA_SHADER_GEOMETRY:
917 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
918 break;
919 case MESA_SHADER_FRAGMENT:
920 if (ctx->shader_info->info.ps.needs_sample_positions) {
921 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
922 }
923 break;
924 default:
925 unreachable("Shader stage not implemented");
926 }
927 }
928
929 static void setup_types(struct nir_to_llvm_context *ctx)
930 {
931 LLVMValueRef args[4];
932
933 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
934 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
935 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
936 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
937 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
938 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
939 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
940 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
941 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
942 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
943 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
944 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
945 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
946 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
947 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
948 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
949
950 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
951 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
952 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
953 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
954 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
955 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
956
957 args[0] = ctx->f32zero;
958 args[1] = ctx->f32zero;
959 args[2] = ctx->f32zero;
960 args[3] = ctx->f32one;
961 ctx->v4f32empty = LLVMConstVector(args, 4);
962
963 ctx->uniform_md_kind =
964 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
965 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
966
967 args[0] = LLVMConstReal(ctx->f32, 2.5);
968 }
969
970 static int get_llvm_num_components(LLVMValueRef value)
971 {
972 LLVMTypeRef type = LLVMTypeOf(value);
973 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
974 ? LLVMGetVectorSize(type)
975 : 1;
976 return num_components;
977 }
978
979 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
980 LLVMValueRef value,
981 int index)
982 {
983 int count = get_llvm_num_components(value);
984
985 assert(index < count);
986 if (count == 1)
987 return value;
988
989 return LLVMBuildExtractElement(ctx->builder, value,
990 LLVMConstInt(ctx->i32, index, false), "");
991 }
992
993 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
994 LLVMValueRef value, unsigned count)
995 {
996 unsigned num_components = get_llvm_num_components(value);
997 if (count == num_components)
998 return value;
999
1000 LLVMValueRef masks[] = {
1001 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1002 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1003
1004 if (count == 1)
1005 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1006 "");
1007
1008 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1009 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1010 }
1011
1012 static void
1013 build_store_values_extended(struct nir_to_llvm_context *ctx,
1014 LLVMValueRef *values,
1015 unsigned value_count,
1016 unsigned value_stride,
1017 LLVMValueRef vec)
1018 {
1019 LLVMBuilderRef builder = ctx->builder;
1020 unsigned i;
1021
1022 if (value_count == 1) {
1023 LLVMBuildStore(builder, vec, values[0]);
1024 return;
1025 }
1026
1027 for (i = 0; i < value_count; i++) {
1028 LLVMValueRef ptr = values[i * value_stride];
1029 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
1030 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1031 LLVMBuildStore(builder, value, ptr);
1032 }
1033 }
1034
1035 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
1036 const nir_ssa_def *def)
1037 {
1038 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
1039 if (def->num_components > 1) {
1040 type = LLVMVectorType(type, def->num_components);
1041 }
1042 return type;
1043 }
1044
1045 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
1046 {
1047 assert(src.is_ssa);
1048 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1049 return (LLVMValueRef)entry->data;
1050 }
1051
1052
1053 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1054 const struct nir_block *b)
1055 {
1056 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1057 return (LLVMBasicBlockRef)entry->data;
1058 }
1059
1060 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1061 nir_alu_src src,
1062 unsigned num_components)
1063 {
1064 LLVMValueRef value = get_src(ctx, src.src);
1065 bool need_swizzle = false;
1066
1067 assert(value);
1068 LLVMTypeRef type = LLVMTypeOf(value);
1069 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1070 ? LLVMGetVectorSize(type)
1071 : 1;
1072
1073 for (unsigned i = 0; i < num_components; ++i) {
1074 assert(src.swizzle[i] < src_components);
1075 if (src.swizzle[i] != i)
1076 need_swizzle = true;
1077 }
1078
1079 if (need_swizzle || num_components != src_components) {
1080 LLVMValueRef masks[] = {
1081 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1082 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1083 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1084 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1085
1086 if (src_components > 1 && num_components == 1) {
1087 value = LLVMBuildExtractElement(ctx->builder, value,
1088 masks[0], "");
1089 } else if (src_components == 1 && num_components > 1) {
1090 LLVMValueRef values[] = {value, value, value, value};
1091 value = ac_build_gather_values(&ctx->ac, values, num_components);
1092 } else {
1093 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1094 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1095 swizzle, "");
1096 }
1097 }
1098 assert(!src.negate);
1099 assert(!src.abs);
1100 return value;
1101 }
1102
1103 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1104 LLVMIntPredicate pred, LLVMValueRef src0,
1105 LLVMValueRef src1)
1106 {
1107 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1108 return LLVMBuildSelect(ctx->builder, result,
1109 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1110 LLVMConstInt(ctx->i32, 0, false), "");
1111 }
1112
1113 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1114 LLVMRealPredicate pred, LLVMValueRef src0,
1115 LLVMValueRef src1)
1116 {
1117 LLVMValueRef result;
1118 src0 = to_float(ctx, src0);
1119 src1 = to_float(ctx, src1);
1120 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1121 return LLVMBuildSelect(ctx->builder, result,
1122 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1123 LLVMConstInt(ctx->i32, 0, false), "");
1124 }
1125
1126 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1127 const char *intrin,
1128 LLVMTypeRef result_type,
1129 LLVMValueRef src0)
1130 {
1131 char name[64];
1132 LLVMValueRef params[] = {
1133 to_float(ctx, src0),
1134 };
1135
1136 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1137 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1138 }
1139
1140 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1141 const char *intrin,
1142 LLVMTypeRef result_type,
1143 LLVMValueRef src0, LLVMValueRef src1)
1144 {
1145 char name[64];
1146 LLVMValueRef params[] = {
1147 to_float(ctx, src0),
1148 to_float(ctx, src1),
1149 };
1150
1151 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1152 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1153 }
1154
1155 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1156 const char *intrin,
1157 LLVMTypeRef result_type,
1158 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1159 {
1160 char name[64];
1161 LLVMValueRef params[] = {
1162 to_float(ctx, src0),
1163 to_float(ctx, src1),
1164 to_float(ctx, src2),
1165 };
1166
1167 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1168 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1169 }
1170
1171 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1172 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1173 {
1174 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1175 ctx->i32_0, "");
1176 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1177 }
1178
1179 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1180 LLVMValueRef src0)
1181 {
1182 LLVMValueRef params[2] = {
1183 src0,
1184
1185 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1186 * add special code to check for x=0. The reason is that
1187 * the LLVM behavior for x=0 is different from what we
1188 * need here.
1189 *
1190 * The hardware already implements the correct behavior.
1191 */
1192 LLVMConstInt(ctx->i1, 1, false),
1193 };
1194 return ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1195 }
1196
1197 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1198 LLVMValueRef src0)
1199 {
1200 return ac_build_imsb(ctx, src0, ctx->i32);
1201 }
1202
1203 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1204 LLVMValueRef src0)
1205 {
1206 return ac_build_umsb(ctx, src0, ctx->i32);
1207 }
1208
1209 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1210 LLVMIntPredicate pred,
1211 LLVMValueRef src0, LLVMValueRef src1)
1212 {
1213 return LLVMBuildSelect(ctx->builder,
1214 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1215 src0,
1216 src1, "");
1217
1218 }
1219 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1220 LLVMValueRef src0)
1221 {
1222 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1223 LLVMBuildNeg(ctx->builder, src0, ""));
1224 }
1225
1226 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1227 LLVMValueRef src0)
1228 {
1229 LLVMValueRef cmp, val;
1230
1231 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1232 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1233 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1234 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1235 return val;
1236 }
1237
1238 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1239 LLVMValueRef src0)
1240 {
1241 LLVMValueRef cmp, val;
1242
1243 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1244 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1245 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1246 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1247 return val;
1248 }
1249
1250 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1251 LLVMValueRef src0)
1252 {
1253 const char *intr = "llvm.floor.f32";
1254 LLVMValueRef fsrc0 = to_float(ctx, src0);
1255 LLVMValueRef params[] = {
1256 fsrc0,
1257 };
1258 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1259 ctx->f32, params, 1,
1260 AC_FUNC_ATTR_READNONE);
1261 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1262 }
1263
1264 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1265 const char *intrin,
1266 LLVMValueRef src0, LLVMValueRef src1)
1267 {
1268 LLVMTypeRef ret_type;
1269 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1270 LLVMValueRef res;
1271 LLVMValueRef params[] = { src0, src1 };
1272 ret_type = LLVMStructTypeInContext(ctx->context, types,
1273 2, true);
1274
1275 res = ac_build_intrinsic(ctx, intrin, ret_type,
1276 params, 2, AC_FUNC_ATTR_READNONE);
1277
1278 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1279 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1280 return res;
1281 }
1282
1283 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1284 LLVMValueRef src0)
1285 {
1286 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1287 }
1288
1289 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1290 LLVMValueRef src0)
1291 {
1292 src0 = to_float(ctx, src0);
1293 return LLVMBuildSExt(ctx->builder,
1294 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1295 ctx->i32, "");
1296 }
1297
1298 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1299 LLVMValueRef src0)
1300 {
1301 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1302 }
1303
1304 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1305 LLVMValueRef src0)
1306 {
1307 return LLVMBuildSExt(ctx->builder,
1308 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1309 ctx->i32, "");
1310 }
1311
1312 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1313 LLVMValueRef src0)
1314 {
1315 LLVMValueRef result;
1316 LLVMValueRef cond;
1317
1318 src0 = to_float(&ctx->ac, src0);
1319 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1320
1321 /* TODO SI/CIK options here */
1322 if (ctx->options->chip_class >= VI) {
1323 LLVMValueRef args[2];
1324 /* Check if the result is a denormal - and flush to 0 if so. */
1325 args[0] = result;
1326 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1327 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1328 }
1329
1330 /* need to convert back up to f32 */
1331 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1332
1333 if (ctx->options->chip_class >= VI)
1334 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1335
1336 return result;
1337 }
1338
1339 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1340 LLVMValueRef src0, LLVMValueRef src1)
1341 {
1342 LLVMValueRef dst64, result;
1343 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1344 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1345
1346 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1347 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1348 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1349 return result;
1350 }
1351
1352 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1353 LLVMValueRef src0, LLVMValueRef src1)
1354 {
1355 LLVMValueRef dst64, result;
1356 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1357 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1358
1359 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1360 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1361 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1362 return result;
1363 }
1364
1365 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1366 bool is_signed,
1367 const LLVMValueRef srcs[3])
1368 {
1369 LLVMValueRef result;
1370 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1371
1372 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1373 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1374 return result;
1375 }
1376
1377 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1378 LLVMValueRef src0, LLVMValueRef src1,
1379 LLVMValueRef src2, LLVMValueRef src3)
1380 {
1381 LLVMValueRef bfi_args[3], result;
1382
1383 bfi_args[0] = LLVMBuildShl(ctx->builder,
1384 LLVMBuildSub(ctx->builder,
1385 LLVMBuildShl(ctx->builder,
1386 ctx->i32_1,
1387 src3, ""),
1388 ctx->i32_1, ""),
1389 src2, "");
1390 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1391 bfi_args[2] = src0;
1392
1393 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1394
1395 /* Calculate:
1396 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1397 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1398 */
1399 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1400 LLVMBuildAnd(ctx->builder, bfi_args[0],
1401 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1402
1403 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1404 return result;
1405 }
1406
1407 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1408 LLVMValueRef src0)
1409 {
1410 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1411 int i;
1412 LLVMValueRef comp[2];
1413
1414 src0 = to_float(ctx, src0);
1415 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1416 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1417 for (i = 0; i < 2; i++) {
1418 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1419 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1420 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1421 }
1422
1423 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1424 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1425
1426 return comp[0];
1427 }
1428
1429 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1430 LLVMValueRef src0)
1431 {
1432 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1433 LLVMValueRef temps[2], result, val;
1434 int i;
1435
1436 for (i = 0; i < 2; i++) {
1437 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1438 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1439 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1440 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1441 }
1442
1443 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1444 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1445 ctx->i32_0, "");
1446 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1447 ctx->i32_1, "");
1448 return result;
1449 }
1450
1451 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1452 nir_op op,
1453 LLVMValueRef src0)
1454 {
1455 unsigned mask;
1456 int idx;
1457 LLVMValueRef result;
1458
1459 if (!ctx->lds && !ctx->has_ds_bpermute)
1460 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1461 LLVMArrayType(ctx->i32, 64),
1462 "ddxy_lds", LOCAL_ADDR_SPACE);
1463
1464 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1465 mask = AC_TID_MASK_LEFT;
1466 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1467 mask = AC_TID_MASK_TOP;
1468 else
1469 mask = AC_TID_MASK_TOP_LEFT;
1470
1471 /* for DDX we want to next X pixel, DDY next Y pixel. */
1472 if (op == nir_op_fddx_fine ||
1473 op == nir_op_fddx_coarse ||
1474 op == nir_op_fddx)
1475 idx = 1;
1476 else
1477 idx = 2;
1478
1479 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1480 mask, idx, ctx->lds,
1481 src0);
1482 return result;
1483 }
1484
1485 /*
1486 * this takes an I,J coordinate pair,
1487 * and works out the X and Y derivatives.
1488 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1489 */
1490 static LLVMValueRef emit_ddxy_interp(
1491 struct nir_to_llvm_context *ctx,
1492 LLVMValueRef interp_ij)
1493 {
1494 LLVMValueRef result[4], a;
1495 unsigned i;
1496
1497 for (i = 0; i < 2; i++) {
1498 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1499 LLVMConstInt(ctx->i32, i, false), "");
1500 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1501 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1502 }
1503 return ac_build_gather_values(&ctx->ac, result, 4);
1504 }
1505
1506 static void visit_alu(struct nir_to_llvm_context *ctx, const nir_alu_instr *instr)
1507 {
1508 LLVMValueRef src[4], result = NULL;
1509 unsigned num_components = instr->dest.dest.ssa.num_components;
1510 unsigned src_components;
1511 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1512
1513 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1514 switch (instr->op) {
1515 case nir_op_vec2:
1516 case nir_op_vec3:
1517 case nir_op_vec4:
1518 src_components = 1;
1519 break;
1520 case nir_op_pack_half_2x16:
1521 src_components = 2;
1522 break;
1523 case nir_op_unpack_half_2x16:
1524 src_components = 1;
1525 break;
1526 default:
1527 src_components = num_components;
1528 break;
1529 }
1530 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1531 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1532
1533 switch (instr->op) {
1534 case nir_op_fmov:
1535 case nir_op_imov:
1536 result = src[0];
1537 break;
1538 case nir_op_fneg:
1539 src[0] = to_float(&ctx->ac, src[0]);
1540 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1541 break;
1542 case nir_op_ineg:
1543 result = LLVMBuildNeg(ctx->builder, src[0], "");
1544 break;
1545 case nir_op_inot:
1546 result = LLVMBuildNot(ctx->builder, src[0], "");
1547 break;
1548 case nir_op_iadd:
1549 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1550 break;
1551 case nir_op_fadd:
1552 src[0] = to_float(&ctx->ac, src[0]);
1553 src[1] = to_float(&ctx->ac, src[1]);
1554 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1555 break;
1556 case nir_op_fsub:
1557 src[0] = to_float(&ctx->ac, src[0]);
1558 src[1] = to_float(&ctx->ac, src[1]);
1559 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1560 break;
1561 case nir_op_isub:
1562 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1563 break;
1564 case nir_op_imul:
1565 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1566 break;
1567 case nir_op_imod:
1568 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1569 break;
1570 case nir_op_umod:
1571 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1572 break;
1573 case nir_op_fmod:
1574 src[0] = to_float(&ctx->ac, src[0]);
1575 src[1] = to_float(&ctx->ac, src[1]);
1576 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1577 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1578 to_float_type(&ctx->ac, def_type), result);
1579 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1580 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1581 break;
1582 case nir_op_frem:
1583 src[0] = to_float(&ctx->ac, src[0]);
1584 src[1] = to_float(&ctx->ac, src[1]);
1585 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1586 break;
1587 case nir_op_irem:
1588 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1589 break;
1590 case nir_op_idiv:
1591 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1592 break;
1593 case nir_op_udiv:
1594 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1595 break;
1596 case nir_op_fmul:
1597 src[0] = to_float(&ctx->ac, src[0]);
1598 src[1] = to_float(&ctx->ac, src[1]);
1599 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1600 break;
1601 case nir_op_fdiv:
1602 src[0] = to_float(&ctx->ac, src[0]);
1603 src[1] = to_float(&ctx->ac, src[1]);
1604 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1605 break;
1606 case nir_op_frcp:
1607 src[0] = to_float(&ctx->ac, src[0]);
1608 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1609 break;
1610 case nir_op_iand:
1611 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1612 break;
1613 case nir_op_ior:
1614 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1615 break;
1616 case nir_op_ixor:
1617 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1618 break;
1619 case nir_op_ishl:
1620 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1621 break;
1622 case nir_op_ishr:
1623 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1624 break;
1625 case nir_op_ushr:
1626 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1627 break;
1628 case nir_op_ilt:
1629 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1630 break;
1631 case nir_op_ine:
1632 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1633 break;
1634 case nir_op_ieq:
1635 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1636 break;
1637 case nir_op_ige:
1638 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1639 break;
1640 case nir_op_ult:
1641 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1642 break;
1643 case nir_op_uge:
1644 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1645 break;
1646 case nir_op_feq:
1647 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1648 break;
1649 case nir_op_fne:
1650 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1651 break;
1652 case nir_op_flt:
1653 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1654 break;
1655 case nir_op_fge:
1656 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1657 break;
1658 case nir_op_fabs:
1659 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1660 to_float_type(&ctx->ac, def_type), src[0]);
1661 break;
1662 case nir_op_iabs:
1663 result = emit_iabs(&ctx->ac, src[0]);
1664 break;
1665 case nir_op_imax:
1666 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1667 break;
1668 case nir_op_imin:
1669 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1670 break;
1671 case nir_op_umax:
1672 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1673 break;
1674 case nir_op_umin:
1675 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1676 break;
1677 case nir_op_isign:
1678 result = emit_isign(&ctx->ac, src[0]);
1679 break;
1680 case nir_op_fsign:
1681 src[0] = to_float(&ctx->ac, src[0]);
1682 result = emit_fsign(&ctx->ac, src[0]);
1683 break;
1684 case nir_op_ffloor:
1685 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1686 to_float_type(&ctx->ac, def_type), src[0]);
1687 break;
1688 case nir_op_ftrunc:
1689 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1690 to_float_type(&ctx->ac, def_type), src[0]);
1691 break;
1692 case nir_op_fceil:
1693 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1694 to_float_type(&ctx->ac, def_type), src[0]);
1695 break;
1696 case nir_op_fround_even:
1697 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1698 to_float_type(&ctx->ac, def_type),src[0]);
1699 break;
1700 case nir_op_ffract:
1701 result = emit_ffract(&ctx->ac, src[0]);
1702 break;
1703 case nir_op_fsin:
1704 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1705 to_float_type(&ctx->ac, def_type), src[0]);
1706 break;
1707 case nir_op_fcos:
1708 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1709 to_float_type(&ctx->ac, def_type), src[0]);
1710 break;
1711 case nir_op_fsqrt:
1712 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1713 to_float_type(&ctx->ac, def_type), src[0]);
1714 break;
1715 case nir_op_fexp2:
1716 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1717 to_float_type(&ctx->ac, def_type), src[0]);
1718 break;
1719 case nir_op_flog2:
1720 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1721 to_float_type(&ctx->ac, def_type), src[0]);
1722 break;
1723 case nir_op_frsq:
1724 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1725 to_float_type(&ctx->ac, def_type), src[0]);
1726 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1727 break;
1728 case nir_op_fpow:
1729 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1730 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1731 break;
1732 case nir_op_fmax:
1733 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1734 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1735 if (instr->dest.dest.ssa.bit_size == 32)
1736 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1737 to_float_type(&ctx->ac, def_type),
1738 result);
1739 break;
1740 case nir_op_fmin:
1741 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1742 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1743 if (instr->dest.dest.ssa.bit_size == 32)
1744 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1745 to_float_type(&ctx->ac, def_type),
1746 result);
1747 break;
1748 case nir_op_ffma:
1749 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1750 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1751 break;
1752 case nir_op_ibitfield_extract:
1753 result = emit_bitfield_extract(&ctx->ac, true, src);
1754 break;
1755 case nir_op_ubitfield_extract:
1756 result = emit_bitfield_extract(&ctx->ac, false, src);
1757 break;
1758 case nir_op_bitfield_insert:
1759 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1760 break;
1761 case nir_op_bitfield_reverse:
1762 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1763 break;
1764 case nir_op_bit_count:
1765 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1766 break;
1767 case nir_op_vec2:
1768 case nir_op_vec3:
1769 case nir_op_vec4:
1770 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1771 src[i] = to_integer(&ctx->ac, src[i]);
1772 result = ac_build_gather_values(&ctx->ac, src, num_components);
1773 break;
1774 case nir_op_f2i32:
1775 case nir_op_f2i64:
1776 src[0] = to_float(&ctx->ac, src[0]);
1777 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1778 break;
1779 case nir_op_f2u32:
1780 case nir_op_f2u64:
1781 src[0] = to_float(&ctx->ac, src[0]);
1782 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1783 break;
1784 case nir_op_i2f32:
1785 case nir_op_i2f64:
1786 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(&ctx->ac, def_type), "");
1787 break;
1788 case nir_op_u2f32:
1789 case nir_op_u2f64:
1790 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(&ctx->ac, def_type), "");
1791 break;
1792 case nir_op_f2f64:
1793 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(&ctx->ac, def_type), "");
1794 break;
1795 case nir_op_f2f32:
1796 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(&ctx->ac, def_type), "");
1797 break;
1798 case nir_op_u2u32:
1799 case nir_op_u2u64:
1800 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1801 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1802 else
1803 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1804 break;
1805 case nir_op_i2i32:
1806 case nir_op_i2i64:
1807 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1808 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1809 else
1810 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1811 break;
1812 case nir_op_bcsel:
1813 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1814 break;
1815 case nir_op_find_lsb:
1816 result = emit_find_lsb(&ctx->ac, src[0]);
1817 break;
1818 case nir_op_ufind_msb:
1819 result = emit_ufind_msb(&ctx->ac, src[0]);
1820 break;
1821 case nir_op_ifind_msb:
1822 result = emit_ifind_msb(&ctx->ac, src[0]);
1823 break;
1824 case nir_op_uadd_carry:
1825 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1826 break;
1827 case nir_op_usub_borrow:
1828 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1829 break;
1830 case nir_op_b2f:
1831 result = emit_b2f(&ctx->ac, src[0]);
1832 break;
1833 case nir_op_f2b:
1834 result = emit_f2b(&ctx->ac, src[0]);
1835 break;
1836 case nir_op_b2i:
1837 result = emit_b2i(&ctx->ac, src[0]);
1838 break;
1839 case nir_op_i2b:
1840 result = emit_i2b(&ctx->ac, src[0]);
1841 break;
1842 case nir_op_fquantize2f16:
1843 result = emit_f2f16(ctx, src[0]);
1844 break;
1845 case nir_op_umul_high:
1846 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1847 break;
1848 case nir_op_imul_high:
1849 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1850 break;
1851 case nir_op_pack_half_2x16:
1852 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1853 break;
1854 case nir_op_unpack_half_2x16:
1855 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1856 break;
1857 case nir_op_fddx:
1858 case nir_op_fddy:
1859 case nir_op_fddx_fine:
1860 case nir_op_fddy_fine:
1861 case nir_op_fddx_coarse:
1862 case nir_op_fddy_coarse:
1863 result = emit_ddxy(ctx, instr->op, src[0]);
1864 break;
1865 default:
1866 fprintf(stderr, "Unknown NIR alu instr: ");
1867 nir_print_instr(&instr->instr, stderr);
1868 fprintf(stderr, "\n");
1869 abort();
1870 }
1871
1872 if (result) {
1873 assert(instr->dest.dest.is_ssa);
1874 result = to_integer(&ctx->ac, result);
1875 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1876 result);
1877 }
1878 }
1879
1880 static void visit_load_const(struct nir_to_llvm_context *ctx,
1881 const nir_load_const_instr *instr)
1882 {
1883 LLVMValueRef values[4], value = NULL;
1884 LLVMTypeRef element_type =
1885 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1886
1887 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1888 switch (instr->def.bit_size) {
1889 case 32:
1890 values[i] = LLVMConstInt(element_type,
1891 instr->value.u32[i], false);
1892 break;
1893 case 64:
1894 values[i] = LLVMConstInt(element_type,
1895 instr->value.u64[i], false);
1896 break;
1897 default:
1898 fprintf(stderr,
1899 "unsupported nir load_const bit_size: %d\n",
1900 instr->def.bit_size);
1901 abort();
1902 }
1903 }
1904 if (instr->def.num_components > 1) {
1905 value = LLVMConstVector(values, instr->def.num_components);
1906 } else
1907 value = values[0];
1908
1909 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1910 }
1911
1912 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1913 LLVMTypeRef type)
1914 {
1915 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1916 return LLVMBuildBitCast(ctx->builder, ptr,
1917 LLVMPointerType(type, addr_space), "");
1918 }
1919
1920 static LLVMValueRef
1921 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1922 {
1923 LLVMValueRef size =
1924 LLVMBuildExtractElement(ctx->builder, descriptor,
1925 LLVMConstInt(ctx->i32, 2, false), "");
1926
1927 /* VI only */
1928 if (ctx->options->chip_class >= VI && in_elements) {
1929 /* On VI, the descriptor contains the size in bytes,
1930 * but TXQ must return the size in elements.
1931 * The stride is always non-zero for resources using TXQ.
1932 */
1933 LLVMValueRef stride =
1934 LLVMBuildExtractElement(ctx->builder, descriptor,
1935 LLVMConstInt(ctx->i32, 1, false), "");
1936 stride = LLVMBuildLShr(ctx->builder, stride,
1937 LLVMConstInt(ctx->i32, 16, false), "");
1938 stride = LLVMBuildAnd(ctx->builder, stride,
1939 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1940
1941 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1942 }
1943 return size;
1944 }
1945
1946 /**
1947 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1948 * intrinsic names).
1949 */
1950 static void build_int_type_name(
1951 LLVMTypeRef type,
1952 char *buf, unsigned bufsize)
1953 {
1954 assert(bufsize >= 6);
1955
1956 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1957 snprintf(buf, bufsize, "v%ui32",
1958 LLVMGetVectorSize(type));
1959 else
1960 strcpy(buf, "i32");
1961 }
1962
1963 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1964 struct ac_image_args *args,
1965 const nir_tex_instr *instr)
1966 {
1967 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1968 LLVMValueRef coord = args->addr;
1969 LLVMValueRef half_texel[2];
1970 LLVMValueRef compare_cube_wa;
1971 LLVMValueRef result;
1972 int c;
1973 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1974
1975 //TODO Rect
1976 {
1977 struct ac_image_args txq_args = { 0 };
1978
1979 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1980 txq_args.opcode = ac_image_get_resinfo;
1981 txq_args.dmask = 0xf;
1982 txq_args.addr = ctx->i32zero;
1983 txq_args.resource = args->resource;
1984 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1985
1986 for (c = 0; c < 2; c++) {
1987 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1988 LLVMConstInt(ctx->i32, c, false), "");
1989 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1990 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1991 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1992 LLVMConstReal(ctx->f32, -0.5), "");
1993 }
1994 }
1995
1996 LLVMValueRef orig_coords = args->addr;
1997
1998 for (c = 0; c < 2; c++) {
1999 LLVMValueRef tmp;
2000 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2001 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2002 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2003 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2004 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2005 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2006 }
2007
2008
2009 /*
2010 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2011 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2012 * workaround by sampling using a scaled type and converting.
2013 * This is taken from amdgpu-pro shaders.
2014 */
2015 /* NOTE this produces some ugly code compared to amdgpu-pro,
2016 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2017 * and then reads them back. -pro generates two selects,
2018 * one s_cmp for the descriptor rewriting
2019 * one v_cmp for the coordinate and result changes.
2020 */
2021 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2022 LLVMValueRef tmp, tmp2;
2023
2024 /* workaround 8/8/8/8 uint/sint cube gather bug */
2025 /* first detect it then change to a scaled read and f2i */
2026 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
2027 tmp2 = tmp;
2028
2029 /* extract the DATA_FORMAT */
2030 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
2031 LLVMConstInt(ctx->i32, 6, false), false);
2032
2033 /* is the DATA_FORMAT == 8_8_8_8 */
2034 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2035
2036 if (stype == GLSL_TYPE_UINT)
2037 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2038 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2039 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2040 else
2041 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2042 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2043 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2044
2045 /* replace the NUM FORMAT in the descriptor */
2046 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2047 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2048
2049 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
2050
2051 /* don't modify the coordinates for this case */
2052 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2053 }
2054 args->addr = coord;
2055 result = ac_build_image_opcode(&ctx->ac, args);
2056
2057 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2058 LLVMValueRef tmp, tmp2;
2059
2060 /* if the cube workaround is in place, f2i the result. */
2061 for (c = 0; c < 4; c++) {
2062 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2063 if (stype == GLSL_TYPE_UINT)
2064 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2065 else
2066 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2067 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2068 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2069 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2070 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2071 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2072 }
2073 }
2074 return result;
2075 }
2076
2077 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
2078 const nir_tex_instr *instr,
2079 bool lod_is_zero,
2080 struct ac_image_args *args)
2081 {
2082 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2083 return ac_build_buffer_load_format(&ctx->ac,
2084 args->resource,
2085 args->addr,
2086 LLVMConstInt(ctx->i32, 0, false),
2087 true);
2088 }
2089
2090 args->opcode = ac_image_sample;
2091 args->compare = instr->is_shadow;
2092
2093 switch (instr->op) {
2094 case nir_texop_txf:
2095 case nir_texop_txf_ms:
2096 case nir_texop_samples_identical:
2097 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2098 args->compare = false;
2099 args->offset = false;
2100 break;
2101 case nir_texop_txb:
2102 args->bias = true;
2103 break;
2104 case nir_texop_txl:
2105 if (lod_is_zero)
2106 args->level_zero = true;
2107 else
2108 args->lod = true;
2109 break;
2110 case nir_texop_txs:
2111 case nir_texop_query_levels:
2112 args->opcode = ac_image_get_resinfo;
2113 break;
2114 case nir_texop_tex:
2115 if (ctx->stage != MESA_SHADER_FRAGMENT)
2116 args->level_zero = true;
2117 break;
2118 case nir_texop_txd:
2119 args->deriv = true;
2120 break;
2121 case nir_texop_tg4:
2122 args->opcode = ac_image_gather4;
2123 args->level_zero = true;
2124 break;
2125 case nir_texop_lod:
2126 args->opcode = ac_image_get_lod;
2127 args->compare = false;
2128 args->offset = false;
2129 break;
2130 default:
2131 break;
2132 }
2133
2134 if (instr->op == nir_texop_tg4) {
2135 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2136 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2137 return radv_lower_gather4_integer(ctx, args, instr);
2138 }
2139 }
2140 return ac_build_image_opcode(&ctx->ac, args);
2141 }
2142
2143 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2144 nir_intrinsic_instr *instr)
2145 {
2146 LLVMValueRef index = get_src(ctx, instr->src[0]);
2147 unsigned desc_set = nir_intrinsic_desc_set(instr);
2148 unsigned binding = nir_intrinsic_binding(instr);
2149 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2150 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2151 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2152 unsigned base_offset = layout->binding[binding].offset;
2153 LLVMValueRef offset, stride;
2154
2155 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2156 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2157 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2158 layout->binding[binding].dynamic_offset_offset;
2159 desc_ptr = ctx->push_constants;
2160 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2161 stride = LLVMConstInt(ctx->i32, 16, false);
2162 } else
2163 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2164
2165 offset = LLVMConstInt(ctx->i32, base_offset, false);
2166 index = LLVMBuildMul(ctx->builder, index, stride, "");
2167 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2168
2169 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2170 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2171 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2172
2173 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2174 }
2175
2176 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2177 nir_intrinsic_instr *instr)
2178 {
2179 LLVMValueRef ptr, addr;
2180
2181 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2182 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2183
2184 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2185 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2186
2187 return LLVMBuildLoad(ctx->builder, ptr, "");
2188 }
2189
2190 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2191 const nir_intrinsic_instr *instr)
2192 {
2193 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2194
2195 return get_buffer_size(ctx, desc, false);
2196 }
2197 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2198 nir_intrinsic_instr *instr)
2199 {
2200 const char *store_name;
2201 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2202 LLVMTypeRef data_type = ctx->f32;
2203 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2204 int components_32bit = elem_size_mult * instr->num_components;
2205 unsigned writemask = nir_intrinsic_write_mask(instr);
2206 LLVMValueRef base_data, base_offset;
2207 LLVMValueRef params[6];
2208
2209 if (ctx->stage == MESA_SHADER_FRAGMENT)
2210 ctx->shader_info->fs.writes_memory = true;
2211
2212 params[1] = get_src(ctx, instr->src[1]);
2213 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2214 params[4] = ctx->i1false; /* glc */
2215 params[5] = ctx->i1false; /* slc */
2216
2217 if (components_32bit > 1)
2218 data_type = LLVMVectorType(ctx->f32, components_32bit);
2219
2220 base_data = to_float(&ctx->ac, src_data);
2221 base_data = trim_vector(ctx, base_data, instr->num_components);
2222 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2223 data_type, "");
2224 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2225 while (writemask) {
2226 int start, count;
2227 LLVMValueRef data;
2228 LLVMValueRef offset;
2229 LLVMValueRef tmp;
2230 u_bit_scan_consecutive_range(&writemask, &start, &count);
2231
2232 /* Due to an LLVM limitation, split 3-element writes
2233 * into a 2-element and a 1-element write. */
2234 if (count == 3) {
2235 writemask |= 1 << (start + 2);
2236 count = 2;
2237 }
2238
2239 start *= elem_size_mult;
2240 count *= elem_size_mult;
2241
2242 if (count > 4) {
2243 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2244 count = 4;
2245 }
2246
2247 if (count == 4) {
2248 store_name = "llvm.amdgcn.buffer.store.v4f32";
2249 data = base_data;
2250 } else if (count == 2) {
2251 tmp = LLVMBuildExtractElement(ctx->builder,
2252 base_data, LLVMConstInt(ctx->i32, start, false), "");
2253 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2254 ctx->i32zero, "");
2255
2256 tmp = LLVMBuildExtractElement(ctx->builder,
2257 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2258 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2259 ctx->i32one, "");
2260 store_name = "llvm.amdgcn.buffer.store.v2f32";
2261
2262 } else {
2263 assert(count == 1);
2264 if (get_llvm_num_components(base_data) > 1)
2265 data = LLVMBuildExtractElement(ctx->builder, base_data,
2266 LLVMConstInt(ctx->i32, start, false), "");
2267 else
2268 data = base_data;
2269 store_name = "llvm.amdgcn.buffer.store.f32";
2270 }
2271
2272 offset = base_offset;
2273 if (start != 0) {
2274 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2275 }
2276 params[0] = data;
2277 params[3] = offset;
2278 ac_build_intrinsic(&ctx->ac, store_name,
2279 ctx->voidt, params, 6, 0);
2280 }
2281 }
2282
2283 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2284 const nir_intrinsic_instr *instr)
2285 {
2286 const char *name;
2287 LLVMValueRef params[6];
2288 int arg_count = 0;
2289 if (ctx->stage == MESA_SHADER_FRAGMENT)
2290 ctx->shader_info->fs.writes_memory = true;
2291
2292 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2293 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2294 }
2295 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2296 params[arg_count++] = get_src(ctx, instr->src[0]);
2297 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2298 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2299 params[arg_count++] = ctx->i1false; /* slc */
2300
2301 switch (instr->intrinsic) {
2302 case nir_intrinsic_ssbo_atomic_add:
2303 name = "llvm.amdgcn.buffer.atomic.add";
2304 break;
2305 case nir_intrinsic_ssbo_atomic_imin:
2306 name = "llvm.amdgcn.buffer.atomic.smin";
2307 break;
2308 case nir_intrinsic_ssbo_atomic_umin:
2309 name = "llvm.amdgcn.buffer.atomic.umin";
2310 break;
2311 case nir_intrinsic_ssbo_atomic_imax:
2312 name = "llvm.amdgcn.buffer.atomic.smax";
2313 break;
2314 case nir_intrinsic_ssbo_atomic_umax:
2315 name = "llvm.amdgcn.buffer.atomic.umax";
2316 break;
2317 case nir_intrinsic_ssbo_atomic_and:
2318 name = "llvm.amdgcn.buffer.atomic.and";
2319 break;
2320 case nir_intrinsic_ssbo_atomic_or:
2321 name = "llvm.amdgcn.buffer.atomic.or";
2322 break;
2323 case nir_intrinsic_ssbo_atomic_xor:
2324 name = "llvm.amdgcn.buffer.atomic.xor";
2325 break;
2326 case nir_intrinsic_ssbo_atomic_exchange:
2327 name = "llvm.amdgcn.buffer.atomic.swap";
2328 break;
2329 case nir_intrinsic_ssbo_atomic_comp_swap:
2330 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2331 break;
2332 default:
2333 abort();
2334 }
2335
2336 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2337 }
2338
2339 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2340 const nir_intrinsic_instr *instr)
2341 {
2342 LLVMValueRef results[2];
2343 int load_components;
2344 int num_components = instr->num_components;
2345 if (instr->dest.ssa.bit_size == 64)
2346 num_components *= 2;
2347
2348 for (int i = 0; i < num_components; i += load_components) {
2349 load_components = MIN2(num_components - i, 4);
2350 const char *load_name;
2351 LLVMTypeRef data_type = ctx->f32;
2352 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2353 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2354
2355 if (load_components == 3)
2356 data_type = LLVMVectorType(ctx->f32, 4);
2357 else if (load_components > 1)
2358 data_type = LLVMVectorType(ctx->f32, load_components);
2359
2360 if (load_components >= 3)
2361 load_name = "llvm.amdgcn.buffer.load.v4f32";
2362 else if (load_components == 2)
2363 load_name = "llvm.amdgcn.buffer.load.v2f32";
2364 else if (load_components == 1)
2365 load_name = "llvm.amdgcn.buffer.load.f32";
2366 else
2367 unreachable("unhandled number of components");
2368
2369 LLVMValueRef params[] = {
2370 get_src(ctx, instr->src[0]),
2371 LLVMConstInt(ctx->i32, 0, false),
2372 offset,
2373 ctx->i1false,
2374 ctx->i1false,
2375 };
2376
2377 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2378
2379 }
2380
2381 LLVMValueRef ret = results[0];
2382 if (num_components > 4 || num_components == 3) {
2383 LLVMValueRef masks[] = {
2384 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2385 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2386 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2387 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2388 };
2389
2390 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2391 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2392 results[num_components > 4 ? 1 : 0], swizzle, "");
2393 }
2394
2395 return LLVMBuildBitCast(ctx->builder, ret,
2396 get_def_type(ctx, &instr->dest.ssa), "");
2397 }
2398
2399 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2400 const nir_intrinsic_instr *instr)
2401 {
2402 LLVMValueRef results[8], ret;
2403 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2404 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2405 int num_components = instr->num_components;
2406
2407 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2408
2409 if (instr->dest.ssa.bit_size == 64)
2410 num_components *= 2;
2411
2412 for (unsigned i = 0; i < num_components; ++i) {
2413 LLVMValueRef params[] = {
2414 rsrc,
2415 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2416 offset, "")
2417 };
2418 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2419 params, 2,
2420 AC_FUNC_ATTR_READNONE |
2421 AC_FUNC_ATTR_LEGACY);
2422 }
2423
2424
2425 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2426 return LLVMBuildBitCast(ctx->builder, ret,
2427 get_def_type(ctx, &instr->dest.ssa), "");
2428 }
2429
2430 static void
2431 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2432 bool vs_in, unsigned *vertex_index_out,
2433 LLVMValueRef *vertex_index_ref,
2434 unsigned *const_out, LLVMValueRef *indir_out)
2435 {
2436 unsigned const_offset = 0;
2437 nir_deref *tail = &deref->deref;
2438 LLVMValueRef offset = NULL;
2439
2440 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2441 tail = tail->child;
2442 nir_deref_array *deref_array = nir_deref_as_array(tail);
2443 if (vertex_index_out)
2444 *vertex_index_out = deref_array->base_offset;
2445
2446 if (vertex_index_ref) {
2447 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2448 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2449 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2450 }
2451 *vertex_index_ref = vtx;
2452 }
2453 }
2454
2455 if (deref->var->data.compact) {
2456 assert(tail->child->deref_type == nir_deref_type_array);
2457 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2458 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2459 /* We always lower indirect dereferences for "compact" array vars. */
2460 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2461
2462 const_offset = deref_array->base_offset;
2463 goto out;
2464 }
2465
2466 while (tail->child != NULL) {
2467 const struct glsl_type *parent_type = tail->type;
2468 tail = tail->child;
2469
2470 if (tail->deref_type == nir_deref_type_array) {
2471 nir_deref_array *deref_array = nir_deref_as_array(tail);
2472 LLVMValueRef index, stride, local_offset;
2473 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2474
2475 const_offset += size * deref_array->base_offset;
2476 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2477 continue;
2478
2479 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2480 index = get_src(ctx, deref_array->indirect);
2481 stride = LLVMConstInt(ctx->i32, size, 0);
2482 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2483
2484 if (offset)
2485 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2486 else
2487 offset = local_offset;
2488 } else if (tail->deref_type == nir_deref_type_struct) {
2489 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2490
2491 for (unsigned i = 0; i < deref_struct->index; i++) {
2492 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2493 const_offset += glsl_count_attribute_slots(ft, vs_in);
2494 }
2495 } else
2496 unreachable("unsupported deref type");
2497
2498 }
2499 out:
2500 if (const_offset && offset)
2501 offset = LLVMBuildAdd(ctx->builder, offset,
2502 LLVMConstInt(ctx->i32, const_offset, 0),
2503 "");
2504
2505 *const_out = const_offset;
2506 *indir_out = offset;
2507 }
2508
2509 static LLVMValueRef
2510 lds_load(struct nir_to_llvm_context *ctx,
2511 LLVMValueRef dw_addr)
2512 {
2513 LLVMValueRef value;
2514 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2515 return value;
2516 }
2517
2518 static void
2519 lds_store(struct nir_to_llvm_context *ctx,
2520 LLVMValueRef dw_addr, LLVMValueRef value)
2521 {
2522 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2523 ac_build_indexed_store(&ctx->ac, ctx->lds,
2524 dw_addr, value);
2525 }
2526
2527 /* The offchip buffer layout for TCS->TES is
2528 *
2529 * - attribute 0 of patch 0 vertex 0
2530 * - attribute 0 of patch 0 vertex 1
2531 * - attribute 0 of patch 0 vertex 2
2532 * ...
2533 * - attribute 0 of patch 1 vertex 0
2534 * - attribute 0 of patch 1 vertex 1
2535 * ...
2536 * - attribute 1 of patch 0 vertex 0
2537 * - attribute 1 of patch 0 vertex 1
2538 * ...
2539 * - per patch attribute 0 of patch 0
2540 * - per patch attribute 0 of patch 1
2541 * ...
2542 *
2543 * Note that every attribute has 4 components.
2544 */
2545 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2546 LLVMValueRef vertex_index,
2547 LLVMValueRef param_index)
2548 {
2549 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2550 LLVMValueRef param_stride, constant16;
2551 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2552
2553 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2554 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2555 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2556 num_patches, "");
2557
2558 constant16 = LLVMConstInt(ctx->i32, 16, false);
2559 if (vertex_index) {
2560 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2561 vertices_per_patch, "");
2562
2563 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2564 vertex_index, "");
2565
2566 param_stride = total_vertices;
2567 } else {
2568 base_addr = rel_patch_id;
2569 param_stride = num_patches;
2570 }
2571
2572 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2573 LLVMBuildMul(ctx->builder, param_index,
2574 param_stride, ""), "");
2575
2576 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2577
2578 if (!vertex_index) {
2579 LLVMValueRef patch_data_offset =
2580 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2581
2582 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2583 patch_data_offset, "");
2584 }
2585 return base_addr;
2586 }
2587
2588 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2589 unsigned param,
2590 unsigned const_index,
2591 bool is_compact,
2592 LLVMValueRef vertex_index,
2593 LLVMValueRef indir_index)
2594 {
2595 LLVMValueRef param_index;
2596
2597 if (indir_index)
2598 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2599 indir_index, "");
2600 else {
2601 if (const_index && !is_compact)
2602 param += const_index;
2603 param_index = LLVMConstInt(ctx->i32, param, false);
2604 }
2605 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2606 }
2607
2608 static void
2609 mark_tess_output(struct nir_to_llvm_context *ctx,
2610 bool is_patch, uint32_t param)
2611
2612 {
2613 if (is_patch) {
2614 ctx->tess_patch_outputs_written |= (1ull << param);
2615 } else
2616 ctx->tess_outputs_written |= (1ull << param);
2617 }
2618
2619 static LLVMValueRef
2620 get_dw_address(struct nir_to_llvm_context *ctx,
2621 LLVMValueRef dw_addr,
2622 unsigned param,
2623 unsigned const_index,
2624 bool compact_const_index,
2625 LLVMValueRef vertex_index,
2626 LLVMValueRef stride,
2627 LLVMValueRef indir_index)
2628
2629 {
2630
2631 if (vertex_index) {
2632 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2633 LLVMBuildMul(ctx->builder,
2634 vertex_index,
2635 stride, ""), "");
2636 }
2637
2638 if (indir_index)
2639 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2640 LLVMBuildMul(ctx->builder, indir_index,
2641 LLVMConstInt(ctx->i32, 4, false), ""), "");
2642 else if (const_index && !compact_const_index)
2643 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2644 LLVMConstInt(ctx->i32, const_index, false), "");
2645
2646 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2647 LLVMConstInt(ctx->i32, param * 4, false), "");
2648
2649 if (const_index && compact_const_index)
2650 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2651 LLVMConstInt(ctx->i32, const_index, false), "");
2652 return dw_addr;
2653 }
2654
2655 static LLVMValueRef
2656 load_tcs_input(struct nir_to_llvm_context *ctx,
2657 nir_intrinsic_instr *instr)
2658 {
2659 LLVMValueRef dw_addr, stride;
2660 unsigned const_index;
2661 LLVMValueRef vertex_index;
2662 LLVMValueRef indir_index;
2663 unsigned param;
2664 LLVMValueRef value[4], result;
2665 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2666 const bool is_compact = instr->variables[0]->var->data.compact;
2667 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2668 radv_get_deref_offset(ctx, instr->variables[0],
2669 false, NULL, per_vertex ? &vertex_index : NULL,
2670 &const_index, &indir_index);
2671
2672 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2673 dw_addr = get_tcs_in_current_patch_offset(ctx);
2674 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2675 indir_index);
2676
2677 for (unsigned i = 0; i < instr->num_components; i++) {
2678 value[i] = lds_load(ctx, dw_addr);
2679 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2680 ctx->i32one, "");
2681 }
2682 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2683 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2684 return result;
2685 }
2686
2687 static LLVMValueRef
2688 load_tcs_output(struct nir_to_llvm_context *ctx,
2689 nir_intrinsic_instr *instr)
2690 {
2691 LLVMValueRef dw_addr, stride;
2692 LLVMValueRef value[4], result;
2693 LLVMValueRef vertex_index = NULL;
2694 LLVMValueRef indir_index = NULL;
2695 unsigned const_index = 0;
2696 unsigned param;
2697 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2698 const bool is_compact = instr->variables[0]->var->data.compact;
2699 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2700 radv_get_deref_offset(ctx, instr->variables[0],
2701 false, NULL, per_vertex ? &vertex_index : NULL,
2702 &const_index, &indir_index);
2703
2704 if (!instr->variables[0]->var->data.patch) {
2705 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2706 dw_addr = get_tcs_out_current_patch_offset(ctx);
2707 } else {
2708 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2709 }
2710
2711 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2712 indir_index);
2713
2714 for (unsigned i = 0; i < instr->num_components; i++) {
2715 value[i] = lds_load(ctx, dw_addr);
2716 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2717 ctx->i32one, "");
2718 }
2719 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2720 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2721 return result;
2722 }
2723
2724 static void
2725 store_tcs_output(struct nir_to_llvm_context *ctx,
2726 nir_intrinsic_instr *instr,
2727 LLVMValueRef src,
2728 unsigned writemask)
2729 {
2730 LLVMValueRef stride, dw_addr;
2731 LLVMValueRef buf_addr = NULL;
2732 LLVMValueRef vertex_index = NULL;
2733 LLVMValueRef indir_index = NULL;
2734 unsigned const_index = 0;
2735 unsigned param;
2736 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2737 const bool is_compact = instr->variables[0]->var->data.compact;
2738
2739 radv_get_deref_offset(ctx, instr->variables[0],
2740 false, NULL, per_vertex ? &vertex_index : NULL,
2741 &const_index, &indir_index);
2742
2743 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2744 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2745 is_compact && const_index > 3) {
2746 const_index -= 3;
2747 param++;
2748 }
2749
2750 if (!instr->variables[0]->var->data.patch) {
2751 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2752 dw_addr = get_tcs_out_current_patch_offset(ctx);
2753 } else {
2754 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2755 }
2756
2757 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2758
2759 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2760 indir_index);
2761 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2762 vertex_index, indir_index);
2763
2764 unsigned base = is_compact ? const_index : 0;
2765 for (unsigned chan = 0; chan < 8; chan++) {
2766 bool is_tess_factor = false;
2767 if (!(writemask & (1 << chan)))
2768 continue;
2769 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2770
2771 lds_store(ctx, dw_addr, value);
2772
2773 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2774 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2775 is_tess_factor = true;
2776
2777 if (!is_tess_factor && writemask != 0xF)
2778 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2779 buf_addr, ctx->oc_lds,
2780 4 * (base + chan), 1, 0, true, false);
2781
2782 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2783 ctx->i32one, "");
2784 }
2785
2786 if (writemask == 0xF) {
2787 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2788 buf_addr, ctx->oc_lds,
2789 (base * 4), 1, 0, true, false);
2790 }
2791 }
2792
2793 static LLVMValueRef
2794 load_tes_input(struct nir_to_llvm_context *ctx,
2795 const nir_intrinsic_instr *instr)
2796 {
2797 LLVMValueRef buf_addr;
2798 LLVMValueRef result;
2799 LLVMValueRef vertex_index = NULL;
2800 LLVMValueRef indir_index = NULL;
2801 unsigned const_index = 0;
2802 unsigned param;
2803 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2804 const bool is_compact = instr->variables[0]->var->data.compact;
2805
2806 radv_get_deref_offset(ctx, instr->variables[0],
2807 false, NULL, per_vertex ? &vertex_index : NULL,
2808 &const_index, &indir_index);
2809 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2810 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2811 is_compact && const_index > 3) {
2812 const_index -= 3;
2813 param++;
2814 }
2815 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2816 is_compact, vertex_index, indir_index);
2817
2818 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2819 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2820 result = trim_vector(ctx, result, instr->num_components);
2821 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2822 return result;
2823 }
2824
2825 static LLVMValueRef
2826 load_gs_input(struct nir_to_llvm_context *ctx,
2827 nir_intrinsic_instr *instr)
2828 {
2829 LLVMValueRef indir_index, vtx_offset;
2830 unsigned const_index;
2831 LLVMValueRef args[9];
2832 unsigned param, vtx_offset_param;
2833 LLVMValueRef value[4], result;
2834 unsigned vertex_index;
2835 radv_get_deref_offset(ctx, instr->variables[0],
2836 false, &vertex_index, NULL,
2837 &const_index, &indir_index);
2838 vtx_offset_param = vertex_index;
2839 assert(vtx_offset_param < 6);
2840 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2841 LLVMConstInt(ctx->i32, 4, false), "");
2842
2843 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2844 for (unsigned i = 0; i < instr->num_components; i++) {
2845
2846 args[0] = ctx->esgs_ring;
2847 args[1] = vtx_offset;
2848 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2849 args[3] = ctx->i32zero;
2850 args[4] = ctx->i32one; /* OFFEN */
2851 args[5] = ctx->i32zero; /* IDXEN */
2852 args[6] = ctx->i32one; /* GLC */
2853 args[7] = ctx->i32zero; /* SLC */
2854 args[8] = ctx->i32zero; /* TFE */
2855
2856 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2857 ctx->i32, args, 9,
2858 AC_FUNC_ATTR_READONLY |
2859 AC_FUNC_ATTR_LEGACY);
2860 }
2861 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2862
2863 return result;
2864 }
2865
2866 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2867 nir_intrinsic_instr *instr)
2868 {
2869 LLVMValueRef values[8];
2870 int idx = instr->variables[0]->var->data.driver_location;
2871 int ve = instr->dest.ssa.num_components;
2872 LLVMValueRef indir_index;
2873 LLVMValueRef ret;
2874 unsigned const_index;
2875 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2876 instr->variables[0]->var->data.mode == nir_var_shader_in;
2877 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2878 &const_index, &indir_index);
2879
2880 if (instr->dest.ssa.bit_size == 64)
2881 ve *= 2;
2882
2883 switch (instr->variables[0]->var->data.mode) {
2884 case nir_var_shader_in:
2885 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2886 return load_tcs_input(ctx, instr);
2887 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2888 return load_tes_input(ctx, instr);
2889 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2890 return load_gs_input(ctx, instr);
2891 }
2892 for (unsigned chan = 0; chan < ve; chan++) {
2893 if (indir_index) {
2894 unsigned count = glsl_count_attribute_slots(
2895 instr->variables[0]->var->type,
2896 ctx->stage == MESA_SHADER_VERTEX);
2897 count -= chan / 4;
2898 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2899 &ctx->ac, ctx->inputs + idx + chan, count,
2900 4, false);
2901
2902 values[chan] = LLVMBuildExtractElement(ctx->builder,
2903 tmp_vec,
2904 indir_index, "");
2905 } else
2906 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2907 }
2908 break;
2909 case nir_var_local:
2910 for (unsigned chan = 0; chan < ve; chan++) {
2911 if (indir_index) {
2912 unsigned count = glsl_count_attribute_slots(
2913 instr->variables[0]->var->type, false);
2914 count -= chan / 4;
2915 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2916 &ctx->ac, ctx->locals + idx + chan, count,
2917 4, true);
2918
2919 values[chan] = LLVMBuildExtractElement(ctx->builder,
2920 tmp_vec,
2921 indir_index, "");
2922 } else {
2923 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2924 }
2925 }
2926 break;
2927 case nir_var_shader_out:
2928 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2929 return load_tcs_output(ctx, instr);
2930 for (unsigned chan = 0; chan < ve; chan++) {
2931 if (indir_index) {
2932 unsigned count = glsl_count_attribute_slots(
2933 instr->variables[0]->var->type, false);
2934 count -= chan / 4;
2935 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2936 &ctx->ac, ctx->outputs + idx + chan, count,
2937 4, true);
2938
2939 values[chan] = LLVMBuildExtractElement(ctx->builder,
2940 tmp_vec,
2941 indir_index, "");
2942 } else {
2943 values[chan] = LLVMBuildLoad(ctx->builder,
2944 ctx->outputs[idx + chan + const_index * 4],
2945 "");
2946 }
2947 }
2948 break;
2949 case nir_var_shared: {
2950 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2951 LLVMValueRef derived_ptr;
2952
2953 if (indir_index)
2954 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2955
2956 for (unsigned chan = 0; chan < ve; chan++) {
2957 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2958 if (indir_index)
2959 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2960 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2961
2962 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2963 }
2964 break;
2965 }
2966 default:
2967 unreachable("unhandle variable mode");
2968 }
2969 ret = ac_build_gather_values(&ctx->ac, values, ve);
2970 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2971 }
2972
2973 static void
2974 visit_store_var(struct nir_to_llvm_context *ctx,
2975 nir_intrinsic_instr *instr)
2976 {
2977 LLVMValueRef temp_ptr, value;
2978 int idx = instr->variables[0]->var->data.driver_location;
2979 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
2980 int writemask = instr->const_index[0];
2981 LLVMValueRef indir_index;
2982 unsigned const_index;
2983 radv_get_deref_offset(ctx, instr->variables[0], false,
2984 NULL, NULL, &const_index, &indir_index);
2985
2986 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
2987 int old_writemask = writemask;
2988
2989 src = LLVMBuildBitCast(ctx->builder, src,
2990 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2991 "");
2992
2993 writemask = 0;
2994 for (unsigned chan = 0; chan < 4; chan++) {
2995 if (old_writemask & (1 << chan))
2996 writemask |= 3u << (2 * chan);
2997 }
2998 }
2999
3000 switch (instr->variables[0]->var->data.mode) {
3001 case nir_var_shader_out:
3002
3003 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3004 store_tcs_output(ctx, instr, src, writemask);
3005 return;
3006 }
3007
3008 for (unsigned chan = 0; chan < 8; chan++) {
3009 int stride = 4;
3010 if (!(writemask & (1 << chan)))
3011 continue;
3012
3013 value = llvm_extract_elem(ctx, src, chan);
3014
3015 if (instr->variables[0]->var->data.compact)
3016 stride = 1;
3017 if (indir_index) {
3018 unsigned count = glsl_count_attribute_slots(
3019 instr->variables[0]->var->type, false);
3020 count -= chan / 4;
3021 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3022 &ctx->ac, ctx->outputs + idx + chan, count,
3023 stride, true);
3024
3025 if (get_llvm_num_components(tmp_vec) > 1) {
3026 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3027 value, indir_index, "");
3028 } else
3029 tmp_vec = value;
3030 build_store_values_extended(ctx, ctx->outputs + idx + chan,
3031 count, stride, tmp_vec);
3032
3033 } else {
3034 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3035
3036 LLVMBuildStore(ctx->builder, value, temp_ptr);
3037 }
3038 }
3039 break;
3040 case nir_var_local:
3041 for (unsigned chan = 0; chan < 8; chan++) {
3042 if (!(writemask & (1 << chan)))
3043 continue;
3044
3045 value = llvm_extract_elem(ctx, src, chan);
3046 if (indir_index) {
3047 unsigned count = glsl_count_attribute_slots(
3048 instr->variables[0]->var->type, false);
3049 count -= chan / 4;
3050 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3051 &ctx->ac, ctx->locals + idx + chan, count,
3052 4, true);
3053
3054 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3055 value, indir_index, "");
3056 build_store_values_extended(ctx, ctx->locals + idx + chan,
3057 count, 4, tmp_vec);
3058 } else {
3059 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3060
3061 LLVMBuildStore(ctx->builder, value, temp_ptr);
3062 }
3063 }
3064 break;
3065 case nir_var_shared: {
3066 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3067
3068 if (indir_index)
3069 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
3070
3071 for (unsigned chan = 0; chan < 8; chan++) {
3072 if (!(writemask & (1 << chan)))
3073 continue;
3074 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
3075 LLVMValueRef derived_ptr;
3076
3077 if (indir_index)
3078 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
3079
3080 value = llvm_extract_elem(ctx, src, chan);
3081 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
3082 LLVMBuildStore(ctx->builder,
3083 to_integer(&ctx->ac, value), derived_ptr);
3084 }
3085 break;
3086 }
3087 default:
3088 break;
3089 }
3090 }
3091
3092 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3093 {
3094 switch (dim) {
3095 case GLSL_SAMPLER_DIM_BUF:
3096 return 1;
3097 case GLSL_SAMPLER_DIM_1D:
3098 return array ? 2 : 1;
3099 case GLSL_SAMPLER_DIM_2D:
3100 return array ? 3 : 2;
3101 case GLSL_SAMPLER_DIM_MS:
3102 return array ? 4 : 3;
3103 case GLSL_SAMPLER_DIM_3D:
3104 case GLSL_SAMPLER_DIM_CUBE:
3105 return 3;
3106 case GLSL_SAMPLER_DIM_RECT:
3107 case GLSL_SAMPLER_DIM_SUBPASS:
3108 return 2;
3109 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3110 return 3;
3111 default:
3112 break;
3113 }
3114 return 0;
3115 }
3116
3117
3118
3119 /* Adjust the sample index according to FMASK.
3120 *
3121 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3122 * which is the identity mapping. Each nibble says which physical sample
3123 * should be fetched to get that sample.
3124 *
3125 * For example, 0x11111100 means there are only 2 samples stored and
3126 * the second sample covers 3/4 of the pixel. When reading samples 0
3127 * and 1, return physical sample 0 (determined by the first two 0s
3128 * in FMASK), otherwise return physical sample 1.
3129 *
3130 * The sample index should be adjusted as follows:
3131 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3132 */
3133 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3134 LLVMValueRef coord_x, LLVMValueRef coord_y,
3135 LLVMValueRef coord_z,
3136 LLVMValueRef sample_index,
3137 LLVMValueRef fmask_desc_ptr)
3138 {
3139 LLVMValueRef fmask_load_address[4];
3140 LLVMValueRef res;
3141
3142 fmask_load_address[0] = coord_x;
3143 fmask_load_address[1] = coord_y;
3144 if (coord_z) {
3145 fmask_load_address[2] = coord_z;
3146 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3147 }
3148
3149 struct ac_image_args args = {0};
3150
3151 args.opcode = ac_image_load;
3152 args.da = coord_z ? true : false;
3153 args.resource = fmask_desc_ptr;
3154 args.dmask = 0xf;
3155 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3156
3157 res = ac_build_image_opcode(&ctx->ac, &args);
3158
3159 res = to_integer(&ctx->ac, res);
3160 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3161 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3162
3163 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3164 res,
3165 ctx->i32zero, "");
3166
3167 LLVMValueRef sample_index4 =
3168 LLVMBuildMul(ctx->builder, sample_index, four, "");
3169 LLVMValueRef shifted_fmask =
3170 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3171 LLVMValueRef final_sample =
3172 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3173
3174 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3175 * resource descriptor is 0 (invalid),
3176 */
3177 LLVMValueRef fmask_desc =
3178 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3179 ctx->v8i32, "");
3180
3181 LLVMValueRef fmask_word1 =
3182 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3183 ctx->i32one, "");
3184
3185 LLVMValueRef word1_is_nonzero =
3186 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3187 fmask_word1, ctx->i32zero, "");
3188
3189 /* Replace the MSAA sample index. */
3190 sample_index =
3191 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3192 final_sample, sample_index, "");
3193 return sample_index;
3194 }
3195
3196 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3197 const nir_intrinsic_instr *instr)
3198 {
3199 const struct glsl_type *type = instr->variables[0]->var->type;
3200 if(instr->variables[0]->deref.child)
3201 type = instr->variables[0]->deref.child->type;
3202
3203 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3204 LLVMValueRef coords[4];
3205 LLVMValueRef masks[] = {
3206 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3207 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3208 };
3209 LLVMValueRef res;
3210 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3211
3212 int count;
3213 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3214 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3215 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3216 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3217 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3218
3219 count = image_type_to_components_count(dim,
3220 glsl_sampler_type_is_array(type));
3221
3222 if (is_ms) {
3223 LLVMValueRef fmask_load_address[3];
3224 int chan;
3225
3226 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3227 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3228 if (glsl_sampler_type_is_array(type))
3229 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3230 else
3231 fmask_load_address[2] = NULL;
3232 if (add_frag_pos) {
3233 for (chan = 0; chan < 2; ++chan)
3234 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3235 }
3236 sample_index = adjust_sample_index_using_fmask(ctx,
3237 fmask_load_address[0],
3238 fmask_load_address[1],
3239 fmask_load_address[2],
3240 sample_index,
3241 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3242 }
3243 if (count == 1) {
3244 if (instr->src[0].ssa->num_components)
3245 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3246 else
3247 res = src0;
3248 } else {
3249 int chan;
3250 if (is_ms)
3251 count--;
3252 for (chan = 0; chan < count; ++chan) {
3253 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3254 }
3255
3256 if (add_frag_pos) {
3257 for (chan = 0; chan < count; ++chan)
3258 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3259 }
3260 if (is_ms) {
3261 coords[count] = sample_index;
3262 count++;
3263 }
3264
3265 if (count == 3) {
3266 coords[3] = LLVMGetUndef(ctx->i32);
3267 count = 4;
3268 }
3269 res = ac_build_gather_values(&ctx->ac, coords, count);
3270 }
3271 return res;
3272 }
3273
3274 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3275 const nir_intrinsic_instr *instr)
3276 {
3277 LLVMValueRef params[7];
3278 LLVMValueRef res;
3279 char intrinsic_name[64];
3280 const nir_variable *var = instr->variables[0]->var;
3281 const struct glsl_type *type = var->type;
3282 if(instr->variables[0]->deref.child)
3283 type = instr->variables[0]->deref.child->type;
3284
3285 type = glsl_without_array(type);
3286 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3287 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3288 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3289 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3290 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3291 params[3] = ctx->i1false; /* glc */
3292 params[4] = ctx->i1false; /* slc */
3293 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3294 params, 5, 0);
3295
3296 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3297 res = to_integer(&ctx->ac, res);
3298 } else {
3299 bool is_da = glsl_sampler_type_is_array(type) ||
3300 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3301 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3302 LLVMValueRef glc = ctx->i1false;
3303 LLVMValueRef slc = ctx->i1false;
3304
3305 params[0] = get_image_coords(ctx, instr);
3306 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3307 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3308 if (HAVE_LLVM <= 0x0309) {
3309 params[3] = ctx->i1false; /* r128 */
3310 params[4] = da;
3311 params[5] = glc;
3312 params[6] = slc;
3313 } else {
3314 LLVMValueRef lwe = ctx->i1false;
3315 params[3] = glc;
3316 params[4] = slc;
3317 params[5] = lwe;
3318 params[6] = da;
3319 }
3320
3321 ac_get_image_intr_name("llvm.amdgcn.image.load",
3322 ctx->v4f32, /* vdata */
3323 LLVMTypeOf(params[0]), /* coords */
3324 LLVMTypeOf(params[1]), /* rsrc */
3325 intrinsic_name, sizeof(intrinsic_name));
3326
3327 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3328 params, 7, AC_FUNC_ATTR_READONLY);
3329 }
3330 return to_integer(&ctx->ac, res);
3331 }
3332
3333 static void visit_image_store(struct nir_to_llvm_context *ctx,
3334 nir_intrinsic_instr *instr)
3335 {
3336 LLVMValueRef params[8];
3337 char intrinsic_name[64];
3338 const nir_variable *var = instr->variables[0]->var;
3339 const struct glsl_type *type = glsl_without_array(var->type);
3340
3341 if (ctx->stage == MESA_SHADER_FRAGMENT)
3342 ctx->shader_info->fs.writes_memory = true;
3343
3344 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3345 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3346 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3347 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3348 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3349 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3350 params[4] = ctx->i1false; /* glc */
3351 params[5] = ctx->i1false; /* slc */
3352 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3353 params, 6, 0);
3354 } else {
3355 bool is_da = glsl_sampler_type_is_array(type) ||
3356 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3357 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3358 LLVMValueRef glc = ctx->i1false;
3359 LLVMValueRef slc = ctx->i1false;
3360
3361 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3362 params[1] = get_image_coords(ctx, instr); /* coords */
3363 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3364 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3365 if (HAVE_LLVM <= 0x0309) {
3366 params[4] = ctx->i1false; /* r128 */
3367 params[5] = da;
3368 params[6] = glc;
3369 params[7] = slc;
3370 } else {
3371 LLVMValueRef lwe = ctx->i1false;
3372 params[4] = glc;
3373 params[5] = slc;
3374 params[6] = lwe;
3375 params[7] = da;
3376 }
3377
3378 ac_get_image_intr_name("llvm.amdgcn.image.store",
3379 LLVMTypeOf(params[0]), /* vdata */
3380 LLVMTypeOf(params[1]), /* coords */
3381 LLVMTypeOf(params[2]), /* rsrc */
3382 intrinsic_name, sizeof(intrinsic_name));
3383
3384 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3385 params, 8, 0);
3386 }
3387
3388 }
3389
3390 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3391 const nir_intrinsic_instr *instr)
3392 {
3393 LLVMValueRef params[6];
3394 int param_count = 0;
3395 const nir_variable *var = instr->variables[0]->var;
3396
3397 const char *base_name = "llvm.amdgcn.image.atomic";
3398 const char *atomic_name;
3399 LLVMValueRef coords;
3400 char intrinsic_name[41], coords_type[8];
3401 const struct glsl_type *type = glsl_without_array(var->type);
3402
3403 if (ctx->stage == MESA_SHADER_FRAGMENT)
3404 ctx->shader_info->fs.writes_memory = true;
3405
3406 params[param_count++] = get_src(ctx, instr->src[2]);
3407 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3408 params[param_count++] = get_src(ctx, instr->src[3]);
3409
3410 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3411 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3412 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3413 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3414 params[param_count++] = ctx->i32zero; /* voffset */
3415 params[param_count++] = ctx->i1false; /* glc */
3416 params[param_count++] = ctx->i1false; /* slc */
3417 } else {
3418 bool da = glsl_sampler_type_is_array(type) ||
3419 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3420
3421 coords = params[param_count++] = get_image_coords(ctx, instr);
3422 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3423 params[param_count++] = ctx->i1false; /* r128 */
3424 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3425 params[param_count++] = ctx->i1false; /* slc */
3426 }
3427
3428 switch (instr->intrinsic) {
3429 case nir_intrinsic_image_atomic_add:
3430 atomic_name = "add";
3431 break;
3432 case nir_intrinsic_image_atomic_min:
3433 atomic_name = "smin";
3434 break;
3435 case nir_intrinsic_image_atomic_max:
3436 atomic_name = "smax";
3437 break;
3438 case nir_intrinsic_image_atomic_and:
3439 atomic_name = "and";
3440 break;
3441 case nir_intrinsic_image_atomic_or:
3442 atomic_name = "or";
3443 break;
3444 case nir_intrinsic_image_atomic_xor:
3445 atomic_name = "xor";
3446 break;
3447 case nir_intrinsic_image_atomic_exchange:
3448 atomic_name = "swap";
3449 break;
3450 case nir_intrinsic_image_atomic_comp_swap:
3451 atomic_name = "cmpswap";
3452 break;
3453 default:
3454 abort();
3455 }
3456 build_int_type_name(LLVMTypeOf(coords),
3457 coords_type, sizeof(coords_type));
3458
3459 snprintf(intrinsic_name, sizeof(intrinsic_name),
3460 "%s.%s.%s", base_name, atomic_name, coords_type);
3461 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3462 }
3463
3464 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3465 const nir_intrinsic_instr *instr)
3466 {
3467 LLVMValueRef res;
3468 const nir_variable *var = instr->variables[0]->var;
3469 const struct glsl_type *type = instr->variables[0]->var->type;
3470 bool da = glsl_sampler_type_is_array(var->type) ||
3471 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3472 if(instr->variables[0]->deref.child)
3473 type = instr->variables[0]->deref.child->type;
3474
3475 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3476 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3477
3478 struct ac_image_args args = { 0 };
3479
3480 args.da = da;
3481 args.dmask = 0xf;
3482 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3483 args.opcode = ac_image_get_resinfo;
3484 args.addr = ctx->i32zero;
3485
3486 res = ac_build_image_opcode(&ctx->ac, &args);
3487
3488 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3489 glsl_sampler_type_is_array(type)) {
3490 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3491 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3492 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3493 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3494 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3495 }
3496 return res;
3497 }
3498
3499 #define NOOP_WAITCNT 0xf7f
3500 #define LGKM_CNT 0x07f
3501 #define VM_CNT 0xf70
3502
3503 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3504 unsigned simm16)
3505 {
3506 LLVMValueRef args[1] = {
3507 LLVMConstInt(ctx->i32, simm16, false),
3508 };
3509 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3510 ctx->voidt, args, 1, 0);
3511 }
3512
3513 static void emit_barrier(struct nir_to_llvm_context *ctx)
3514 {
3515 /* SI only (thanks to a hw bug workaround):
3516 * The real barrier instruction isn’t needed, because an entire patch
3517 * always fits into a single wave.
3518 */
3519 if (ctx->options->chip_class == SI &&
3520 ctx->stage == MESA_SHADER_TESS_CTRL) {
3521 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3522 return;
3523 }
3524 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3525 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3526 }
3527
3528 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3529 const nir_intrinsic_instr *instr)
3530 {
3531 LLVMValueRef cond;
3532 ctx->shader_info->fs.can_discard = true;
3533
3534 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3535 get_src(ctx, instr->src[0]),
3536 ctx->i32zero, "");
3537
3538 cond = LLVMBuildSelect(ctx->builder, cond,
3539 LLVMConstReal(ctx->f32, -1.0f),
3540 ctx->f32zero, "");
3541 ac_build_kill(&ctx->ac, cond);
3542 }
3543
3544 static LLVMValueRef
3545 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3546 {
3547 LLVMValueRef result;
3548 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3549 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3550 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3551
3552 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3553 }
3554
3555 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3556 const nir_intrinsic_instr *instr)
3557 {
3558 LLVMValueRef ptr, result;
3559 int idx = instr->variables[0]->var->data.driver_location;
3560 LLVMValueRef src = get_src(ctx, instr->src[0]);
3561 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3562
3563 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3564 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3565 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3566 ptr, src, src1,
3567 LLVMAtomicOrderingSequentiallyConsistent,
3568 LLVMAtomicOrderingSequentiallyConsistent,
3569 false);
3570 } else {
3571 LLVMAtomicRMWBinOp op;
3572 switch (instr->intrinsic) {
3573 case nir_intrinsic_var_atomic_add:
3574 op = LLVMAtomicRMWBinOpAdd;
3575 break;
3576 case nir_intrinsic_var_atomic_umin:
3577 op = LLVMAtomicRMWBinOpUMin;
3578 break;
3579 case nir_intrinsic_var_atomic_umax:
3580 op = LLVMAtomicRMWBinOpUMax;
3581 break;
3582 case nir_intrinsic_var_atomic_imin:
3583 op = LLVMAtomicRMWBinOpMin;
3584 break;
3585 case nir_intrinsic_var_atomic_imax:
3586 op = LLVMAtomicRMWBinOpMax;
3587 break;
3588 case nir_intrinsic_var_atomic_and:
3589 op = LLVMAtomicRMWBinOpAnd;
3590 break;
3591 case nir_intrinsic_var_atomic_or:
3592 op = LLVMAtomicRMWBinOpOr;
3593 break;
3594 case nir_intrinsic_var_atomic_xor:
3595 op = LLVMAtomicRMWBinOpXor;
3596 break;
3597 case nir_intrinsic_var_atomic_exchange:
3598 op = LLVMAtomicRMWBinOpXchg;
3599 break;
3600 default:
3601 return NULL;
3602 }
3603
3604 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3605 LLVMAtomicOrderingSequentiallyConsistent,
3606 false);
3607 }
3608 return result;
3609 }
3610
3611 #define INTERP_CENTER 0
3612 #define INTERP_CENTROID 1
3613 #define INTERP_SAMPLE 2
3614
3615 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3616 enum glsl_interp_mode interp, unsigned location)
3617 {
3618 switch (interp) {
3619 case INTERP_MODE_FLAT:
3620 default:
3621 return NULL;
3622 case INTERP_MODE_SMOOTH:
3623 case INTERP_MODE_NONE:
3624 if (location == INTERP_CENTER)
3625 return ctx->persp_center;
3626 else if (location == INTERP_CENTROID)
3627 return ctx->persp_centroid;
3628 else if (location == INTERP_SAMPLE)
3629 return ctx->persp_sample;
3630 break;
3631 case INTERP_MODE_NOPERSPECTIVE:
3632 if (location == INTERP_CENTER)
3633 return ctx->linear_center;
3634 else if (location == INTERP_CENTROID)
3635 return ctx->linear_centroid;
3636 else if (location == INTERP_SAMPLE)
3637 return ctx->linear_sample;
3638 break;
3639 }
3640 return NULL;
3641 }
3642
3643 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3644 LLVMValueRef sample_id)
3645 {
3646 LLVMValueRef result;
3647 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3648
3649 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3650 const_array(ctx->v2f32, 64), "");
3651
3652 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3653 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3654
3655 return result;
3656 }
3657
3658 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3659 {
3660 LLVMValueRef values[2];
3661
3662 values[0] = emit_ffract(&ctx->ac, ctx->frag_pos[0]);
3663 values[1] = emit_ffract(&ctx->ac, ctx->frag_pos[1]);
3664 return ac_build_gather_values(&ctx->ac, values, 2);
3665 }
3666
3667 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3668 const nir_intrinsic_instr *instr)
3669 {
3670 LLVMValueRef result[2];
3671 LLVMValueRef interp_param, attr_number;
3672 unsigned location;
3673 unsigned chan;
3674 LLVMValueRef src_c0, src_c1;
3675 LLVMValueRef src0;
3676 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3677 switch (instr->intrinsic) {
3678 case nir_intrinsic_interp_var_at_centroid:
3679 location = INTERP_CENTROID;
3680 break;
3681 case nir_intrinsic_interp_var_at_sample:
3682 case nir_intrinsic_interp_var_at_offset:
3683 location = INTERP_CENTER;
3684 src0 = get_src(ctx, instr->src[0]);
3685 break;
3686 default:
3687 break;
3688 }
3689
3690 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3691 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3692 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3693 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3694 LLVMValueRef sample_position;
3695 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3696
3697 /* fetch sample ID */
3698 sample_position = load_sample_position(ctx, src0);
3699
3700 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3701 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3702 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3703 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3704 }
3705 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3706 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3707
3708 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3709 LLVMValueRef ij_out[2];
3710 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3711
3712 /*
3713 * take the I then J parameters, and the DDX/Y for it, and
3714 * calculate the IJ inputs for the interpolator.
3715 * temp1 = ddx * offset/sample.x + I;
3716 * interp_param.I = ddy * offset/sample.y + temp1;
3717 * temp1 = ddx * offset/sample.x + J;
3718 * interp_param.J = ddy * offset/sample.y + temp1;
3719 */
3720 for (unsigned i = 0; i < 2; i++) {
3721 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3722 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3723 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3724 ddxy_out, ix_ll, "");
3725 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3726 ddxy_out, iy_ll, "");
3727 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3728 interp_param, ix_ll, "");
3729 LLVMValueRef temp1, temp2;
3730
3731 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3732 ctx->f32, "");
3733
3734 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3735 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3736
3737 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3738 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3739
3740 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3741 temp2, ctx->i32, "");
3742 }
3743 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3744
3745 }
3746
3747 for (chan = 0; chan < 2; chan++) {
3748 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3749
3750 if (interp_param) {
3751 interp_param = LLVMBuildBitCast(ctx->builder,
3752 interp_param, LLVMVectorType(ctx->f32, 2), "");
3753 LLVMValueRef i = LLVMBuildExtractElement(
3754 ctx->builder, interp_param, ctx->i32zero, "");
3755 LLVMValueRef j = LLVMBuildExtractElement(
3756 ctx->builder, interp_param, ctx->i32one, "");
3757
3758 result[chan] = ac_build_fs_interp(&ctx->ac,
3759 llvm_chan, attr_number,
3760 ctx->prim_mask, i, j);
3761 } else {
3762 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3763 LLVMConstInt(ctx->i32, 2, false),
3764 llvm_chan, attr_number,
3765 ctx->prim_mask);
3766 }
3767 }
3768 return ac_build_gather_values(&ctx->ac, result, 2);
3769 }
3770
3771 static void
3772 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3773 const nir_intrinsic_instr *instr)
3774 {
3775 LLVMValueRef gs_next_vertex;
3776 LLVMValueRef can_emit, kill;
3777 int idx;
3778
3779 assert(instr->const_index[0] == 0);
3780 /* Write vertex attribute values to GSVS ring */
3781 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3782 ctx->gs_next_vertex,
3783 "");
3784
3785 /* If this thread has already emitted the declared maximum number of
3786 * vertices, kill it: excessive vertex emissions are not supposed to
3787 * have any effect, and GS threads have no externally observable
3788 * effects other than emitting vertices.
3789 */
3790 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3791 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3792
3793 kill = LLVMBuildSelect(ctx->builder, can_emit,
3794 LLVMConstReal(ctx->f32, 1.0f),
3795 LLVMConstReal(ctx->f32, -1.0f), "");
3796 ac_build_kill(&ctx->ac, kill);
3797
3798 /* loop num outputs */
3799 idx = 0;
3800 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3801 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3802 int length = 4;
3803 int slot = idx;
3804 int slot_inc = 1;
3805
3806 if (!(ctx->output_mask & (1ull << i)))
3807 continue;
3808
3809 if (i == VARYING_SLOT_CLIP_DIST0) {
3810 /* pack clip and cull into a single set of slots */
3811 length = ctx->num_output_clips + ctx->num_output_culls;
3812 if (length > 4)
3813 slot_inc = 2;
3814 }
3815 for (unsigned j = 0; j < length; j++) {
3816 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3817 out_ptr[j], "");
3818 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3819 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3820 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3821
3822 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3823
3824 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3825 out_val, 1,
3826 voffset, ctx->gs2vs_offset, 0,
3827 1, 1, true, true);
3828 }
3829 idx += slot_inc;
3830 }
3831
3832 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3833 ctx->i32one, "");
3834 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3835
3836 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3837 }
3838
3839 static void
3840 visit_end_primitive(struct nir_to_llvm_context *ctx,
3841 const nir_intrinsic_instr *instr)
3842 {
3843 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3844 }
3845
3846 static LLVMValueRef
3847 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3848 const nir_intrinsic_instr *instr)
3849 {
3850 LLVMValueRef coord[4] = {
3851 ctx->tes_u,
3852 ctx->tes_v,
3853 ctx->f32zero,
3854 ctx->f32zero,
3855 };
3856
3857 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3858 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3859 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3860
3861 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3862 return LLVMBuildBitCast(ctx->builder, result,
3863 get_def_type(ctx, &instr->dest.ssa), "");
3864 }
3865
3866 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3867 nir_intrinsic_instr *instr)
3868 {
3869 LLVMValueRef result = NULL;
3870
3871 switch (instr->intrinsic) {
3872 case nir_intrinsic_load_work_group_id: {
3873 result = ctx->workgroup_ids;
3874 break;
3875 }
3876 case nir_intrinsic_load_base_vertex: {
3877 result = ctx->base_vertex;
3878 break;
3879 }
3880 case nir_intrinsic_load_vertex_id_zero_base: {
3881 result = ctx->vertex_id;
3882 break;
3883 }
3884 case nir_intrinsic_load_local_invocation_id: {
3885 result = ctx->local_invocation_ids;
3886 break;
3887 }
3888 case nir_intrinsic_load_base_instance:
3889 result = ctx->start_instance;
3890 break;
3891 case nir_intrinsic_load_draw_id:
3892 result = ctx->draw_index;
3893 break;
3894 case nir_intrinsic_load_invocation_id:
3895 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3896 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3897 else
3898 result = ctx->gs_invocation_id;
3899 break;
3900 case nir_intrinsic_load_primitive_id:
3901 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3902 ctx->shader_info->gs.uses_prim_id = true;
3903 result = ctx->gs_prim_id;
3904 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3905 ctx->shader_info->tcs.uses_prim_id = true;
3906 result = ctx->tcs_patch_id;
3907 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
3908 ctx->shader_info->tcs.uses_prim_id = true;
3909 result = ctx->tes_patch_id;
3910 } else
3911 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3912 break;
3913 case nir_intrinsic_load_sample_id:
3914 ctx->shader_info->fs.force_persample = true;
3915 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3916 break;
3917 case nir_intrinsic_load_sample_pos:
3918 ctx->shader_info->fs.force_persample = true;
3919 result = load_sample_pos(ctx);
3920 break;
3921 case nir_intrinsic_load_sample_mask_in:
3922 result = ctx->sample_coverage;
3923 break;
3924 case nir_intrinsic_load_front_face:
3925 result = ctx->front_face;
3926 break;
3927 case nir_intrinsic_load_instance_id:
3928 result = ctx->instance_id;
3929 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3930 ctx->shader_info->vs.vgpr_comp_cnt);
3931 break;
3932 case nir_intrinsic_load_num_work_groups:
3933 result = ctx->num_work_groups;
3934 break;
3935 case nir_intrinsic_load_local_invocation_index:
3936 result = visit_load_local_invocation_index(ctx);
3937 break;
3938 case nir_intrinsic_load_push_constant:
3939 result = visit_load_push_constant(ctx, instr);
3940 break;
3941 case nir_intrinsic_vulkan_resource_index:
3942 result = visit_vulkan_resource_index(ctx, instr);
3943 break;
3944 case nir_intrinsic_store_ssbo:
3945 visit_store_ssbo(ctx, instr);
3946 break;
3947 case nir_intrinsic_load_ssbo:
3948 result = visit_load_buffer(ctx, instr);
3949 break;
3950 case nir_intrinsic_ssbo_atomic_add:
3951 case nir_intrinsic_ssbo_atomic_imin:
3952 case nir_intrinsic_ssbo_atomic_umin:
3953 case nir_intrinsic_ssbo_atomic_imax:
3954 case nir_intrinsic_ssbo_atomic_umax:
3955 case nir_intrinsic_ssbo_atomic_and:
3956 case nir_intrinsic_ssbo_atomic_or:
3957 case nir_intrinsic_ssbo_atomic_xor:
3958 case nir_intrinsic_ssbo_atomic_exchange:
3959 case nir_intrinsic_ssbo_atomic_comp_swap:
3960 result = visit_atomic_ssbo(ctx, instr);
3961 break;
3962 case nir_intrinsic_load_ubo:
3963 result = visit_load_ubo_buffer(ctx, instr);
3964 break;
3965 case nir_intrinsic_get_buffer_size:
3966 result = visit_get_buffer_size(ctx, instr);
3967 break;
3968 case nir_intrinsic_load_var:
3969 result = visit_load_var(ctx, instr);
3970 break;
3971 case nir_intrinsic_store_var:
3972 visit_store_var(ctx, instr);
3973 break;
3974 case nir_intrinsic_image_load:
3975 result = visit_image_load(ctx, instr);
3976 break;
3977 case nir_intrinsic_image_store:
3978 visit_image_store(ctx, instr);
3979 break;
3980 case nir_intrinsic_image_atomic_add:
3981 case nir_intrinsic_image_atomic_min:
3982 case nir_intrinsic_image_atomic_max:
3983 case nir_intrinsic_image_atomic_and:
3984 case nir_intrinsic_image_atomic_or:
3985 case nir_intrinsic_image_atomic_xor:
3986 case nir_intrinsic_image_atomic_exchange:
3987 case nir_intrinsic_image_atomic_comp_swap:
3988 result = visit_image_atomic(ctx, instr);
3989 break;
3990 case nir_intrinsic_image_size:
3991 result = visit_image_size(ctx, instr);
3992 break;
3993 case nir_intrinsic_discard:
3994 ctx->shader_info->fs.can_discard = true;
3995 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3996 ctx->voidt,
3997 NULL, 0, AC_FUNC_ATTR_LEGACY);
3998 break;
3999 case nir_intrinsic_discard_if:
4000 emit_discard_if(ctx, instr);
4001 break;
4002 case nir_intrinsic_memory_barrier:
4003 emit_waitcnt(ctx, VM_CNT);
4004 break;
4005 case nir_intrinsic_barrier:
4006 emit_barrier(ctx);
4007 break;
4008 case nir_intrinsic_var_atomic_add:
4009 case nir_intrinsic_var_atomic_imin:
4010 case nir_intrinsic_var_atomic_umin:
4011 case nir_intrinsic_var_atomic_imax:
4012 case nir_intrinsic_var_atomic_umax:
4013 case nir_intrinsic_var_atomic_and:
4014 case nir_intrinsic_var_atomic_or:
4015 case nir_intrinsic_var_atomic_xor:
4016 case nir_intrinsic_var_atomic_exchange:
4017 case nir_intrinsic_var_atomic_comp_swap:
4018 result = visit_var_atomic(ctx, instr);
4019 break;
4020 case nir_intrinsic_interp_var_at_centroid:
4021 case nir_intrinsic_interp_var_at_sample:
4022 case nir_intrinsic_interp_var_at_offset:
4023 result = visit_interp(ctx, instr);
4024 break;
4025 case nir_intrinsic_emit_vertex:
4026 visit_emit_vertex(ctx, instr);
4027 break;
4028 case nir_intrinsic_end_primitive:
4029 visit_end_primitive(ctx, instr);
4030 break;
4031 case nir_intrinsic_load_tess_coord:
4032 result = visit_load_tess_coord(ctx, instr);
4033 break;
4034 case nir_intrinsic_load_patch_vertices_in:
4035 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
4036 break;
4037 default:
4038 fprintf(stderr, "Unknown intrinsic: ");
4039 nir_print_instr(&instr->instr, stderr);
4040 fprintf(stderr, "\n");
4041 break;
4042 }
4043 if (result) {
4044 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4045 }
4046 }
4047
4048 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
4049 const nir_deref_var *deref,
4050 enum desc_type desc_type)
4051 {
4052 unsigned desc_set = deref->var->data.descriptor_set;
4053 LLVMValueRef list = ctx->descriptor_sets[desc_set];
4054 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4055 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
4056 unsigned offset = binding->offset;
4057 unsigned stride = binding->size;
4058 unsigned type_size;
4059 LLVMBuilderRef builder = ctx->builder;
4060 LLVMTypeRef type;
4061 LLVMValueRef index = NULL;
4062 unsigned constant_index = 0;
4063
4064 assert(deref->var->data.binding < layout->binding_count);
4065
4066 switch (desc_type) {
4067 case DESC_IMAGE:
4068 type = ctx->v8i32;
4069 type_size = 32;
4070 break;
4071 case DESC_FMASK:
4072 type = ctx->v8i32;
4073 offset += 32;
4074 type_size = 32;
4075 break;
4076 case DESC_SAMPLER:
4077 type = ctx->v4i32;
4078 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4079 offset += 64;
4080
4081 type_size = 16;
4082 break;
4083 case DESC_BUFFER:
4084 type = ctx->v4i32;
4085 type_size = 16;
4086 break;
4087 default:
4088 unreachable("invalid desc_type\n");
4089 }
4090
4091 if (deref->deref.child) {
4092 const nir_deref_array *child =
4093 (const nir_deref_array *)deref->deref.child;
4094
4095 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4096 offset += child->base_offset * stride;
4097 if (child->deref_array_type == nir_deref_array_type_indirect) {
4098 index = get_src(ctx, child->indirect);
4099 }
4100
4101 constant_index = child->base_offset;
4102 }
4103 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
4104 (!index || binding->immutable_samplers_equal)) {
4105 if (binding->immutable_samplers_equal)
4106 constant_index = 0;
4107
4108 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4109
4110 LLVMValueRef constants[] = {
4111 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4112 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4113 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4114 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4115 };
4116 return ac_build_gather_values(&ctx->ac, constants, 4);
4117 }
4118
4119 assert(stride % type_size == 0);
4120
4121 if (!index)
4122 index = ctx->i32zero;
4123
4124 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4125
4126 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4127 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4128
4129 return ac_build_indexed_load_const(&ctx->ac, list, index);
4130 }
4131
4132 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4133 struct ac_image_args *args,
4134 const nir_tex_instr *instr,
4135 nir_texop op,
4136 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4137 LLVMValueRef *param, unsigned count,
4138 unsigned dmask)
4139 {
4140 unsigned is_rect = 0;
4141 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4142
4143 if (op == nir_texop_lod)
4144 da = false;
4145 /* Pad to power of two vector */
4146 while (count < util_next_power_of_two(count))
4147 param[count++] = LLVMGetUndef(ctx->i32);
4148
4149 if (count > 1)
4150 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4151 else
4152 args->addr = param[0];
4153
4154 args->resource = res_ptr;
4155 args->sampler = samp_ptr;
4156
4157 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4158 args->addr = param[0];
4159 return;
4160 }
4161
4162 args->dmask = dmask;
4163 args->unorm = is_rect;
4164 args->da = da;
4165 }
4166
4167 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4168 *
4169 * SI-CI:
4170 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4171 * filtering manually. The driver sets img7 to a mask clearing
4172 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4173 * s_and_b32 samp0, samp0, img7
4174 *
4175 * VI:
4176 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4177 */
4178 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4179 LLVMValueRef res, LLVMValueRef samp)
4180 {
4181 LLVMBuilderRef builder = ctx->builder;
4182 LLVMValueRef img7, samp0;
4183
4184 if (ctx->options->chip_class >= VI)
4185 return samp;
4186
4187 img7 = LLVMBuildExtractElement(builder, res,
4188 LLVMConstInt(ctx->i32, 7, 0), "");
4189 samp0 = LLVMBuildExtractElement(builder, samp,
4190 LLVMConstInt(ctx->i32, 0, 0), "");
4191 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4192 return LLVMBuildInsertElement(builder, samp, samp0,
4193 LLVMConstInt(ctx->i32, 0, 0), "");
4194 }
4195
4196 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4197 nir_tex_instr *instr,
4198 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4199 LLVMValueRef *fmask_ptr)
4200 {
4201 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4202 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4203 else
4204 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4205 if (samp_ptr) {
4206 if (instr->sampler)
4207 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4208 else
4209 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4210 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4211 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4212 }
4213 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4214 instr->op == nir_texop_samples_identical))
4215 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4216 }
4217
4218 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4219 LLVMValueRef coord)
4220 {
4221 coord = to_float(&ctx->ac, coord);
4222 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4223 coord = to_integer(&ctx->ac, coord);
4224 return coord;
4225 }
4226
4227 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4228 {
4229 LLVMValueRef result = NULL;
4230 struct ac_image_args args = { 0 };
4231 unsigned dmask = 0xf;
4232 LLVMValueRef address[16];
4233 LLVMValueRef coords[5];
4234 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4235 LLVMValueRef bias = NULL, offsets = NULL;
4236 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4237 LLVMValueRef ddx = NULL, ddy = NULL;
4238 LLVMValueRef derivs[6];
4239 unsigned chan, count = 0;
4240 unsigned const_src = 0, num_deriv_comp = 0;
4241 bool lod_is_zero = false;
4242 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4243
4244 for (unsigned i = 0; i < instr->num_srcs; i++) {
4245 switch (instr->src[i].src_type) {
4246 case nir_tex_src_coord:
4247 coord = get_src(ctx, instr->src[i].src);
4248 break;
4249 case nir_tex_src_projector:
4250 break;
4251 case nir_tex_src_comparator:
4252 comparator = get_src(ctx, instr->src[i].src);
4253 break;
4254 case nir_tex_src_offset:
4255 offsets = get_src(ctx, instr->src[i].src);
4256 const_src = i;
4257 break;
4258 case nir_tex_src_bias:
4259 bias = get_src(ctx, instr->src[i].src);
4260 break;
4261 case nir_tex_src_lod: {
4262 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4263
4264 if (val && val->i32[0] == 0)
4265 lod_is_zero = true;
4266 lod = get_src(ctx, instr->src[i].src);
4267 break;
4268 }
4269 case nir_tex_src_ms_index:
4270 sample_index = get_src(ctx, instr->src[i].src);
4271 break;
4272 case nir_tex_src_ms_mcs:
4273 break;
4274 case nir_tex_src_ddx:
4275 ddx = get_src(ctx, instr->src[i].src);
4276 num_deriv_comp = instr->src[i].src.ssa->num_components;
4277 break;
4278 case nir_tex_src_ddy:
4279 ddy = get_src(ctx, instr->src[i].src);
4280 break;
4281 case nir_tex_src_texture_offset:
4282 case nir_tex_src_sampler_offset:
4283 case nir_tex_src_plane:
4284 default:
4285 break;
4286 }
4287 }
4288
4289 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4290 result = get_buffer_size(ctx, res_ptr, true);
4291 goto write_result;
4292 }
4293
4294 if (instr->op == nir_texop_texture_samples) {
4295 LLVMValueRef res, samples, is_msaa;
4296 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4297 samples = LLVMBuildExtractElement(ctx->builder, res,
4298 LLVMConstInt(ctx->i32, 3, false), "");
4299 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4300 LLVMConstInt(ctx->i32, 28, false), "");
4301 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4302 LLVMConstInt(ctx->i32, 0xe, false), "");
4303 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4304 LLVMConstInt(ctx->i32, 0xe, false), "");
4305
4306 samples = LLVMBuildLShr(ctx->builder, samples,
4307 LLVMConstInt(ctx->i32, 16, false), "");
4308 samples = LLVMBuildAnd(ctx->builder, samples,
4309 LLVMConstInt(ctx->i32, 0xf, false), "");
4310 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4311 samples, "");
4312 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4313 ctx->i32one, "");
4314 result = samples;
4315 goto write_result;
4316 }
4317
4318 if (coord)
4319 for (chan = 0; chan < instr->coord_components; chan++)
4320 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4321
4322 if (offsets && instr->op != nir_texop_txf) {
4323 LLVMValueRef offset[3], pack;
4324 for (chan = 0; chan < 3; ++chan)
4325 offset[chan] = ctx->i32zero;
4326
4327 args.offset = true;
4328 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4329 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4330 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4331 LLVMConstInt(ctx->i32, 0x3f, false), "");
4332 if (chan)
4333 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4334 LLVMConstInt(ctx->i32, chan * 8, false), "");
4335 }
4336 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4337 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4338 address[count++] = pack;
4339
4340 }
4341 /* pack LOD bias value */
4342 if (instr->op == nir_texop_txb && bias) {
4343 address[count++] = bias;
4344 }
4345
4346 /* Pack depth comparison value */
4347 if (instr->is_shadow && comparator) {
4348 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4349 }
4350
4351 /* pack derivatives */
4352 if (ddx || ddy) {
4353 switch (instr->sampler_dim) {
4354 case GLSL_SAMPLER_DIM_3D:
4355 case GLSL_SAMPLER_DIM_CUBE:
4356 num_deriv_comp = 3;
4357 break;
4358 case GLSL_SAMPLER_DIM_2D:
4359 default:
4360 num_deriv_comp = 2;
4361 break;
4362 case GLSL_SAMPLER_DIM_1D:
4363 num_deriv_comp = 1;
4364 break;
4365 }
4366
4367 for (unsigned i = 0; i < num_deriv_comp; i++) {
4368 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(ctx, ddx, i));
4369 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(ctx, ddy, i));
4370 }
4371 }
4372
4373 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4374 if (instr->is_array && instr->op != nir_texop_lod)
4375 coords[3] = apply_round_slice(ctx, coords[3]);
4376 for (chan = 0; chan < instr->coord_components; chan++)
4377 coords[chan] = to_float(&ctx->ac, coords[chan]);
4378 if (instr->coord_components == 3)
4379 coords[3] = LLVMGetUndef(ctx->f32);
4380 ac_prepare_cube_coords(&ctx->ac,
4381 instr->op == nir_texop_txd, instr->is_array,
4382 coords, derivs);
4383 if (num_deriv_comp)
4384 num_deriv_comp--;
4385 }
4386
4387 if (ddx || ddy) {
4388 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4389 address[count++] = derivs[i];
4390 }
4391
4392 /* Pack texture coordinates */
4393 if (coord) {
4394 address[count++] = coords[0];
4395 if (instr->coord_components > 1) {
4396 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4397 coords[1] = apply_round_slice(ctx, coords[1]);
4398 }
4399 address[count++] = coords[1];
4400 }
4401 if (instr->coord_components > 2) {
4402 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4403 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4404 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4405 instr->op != nir_texop_txf) {
4406 coords[2] = apply_round_slice(ctx, coords[2]);
4407 }
4408 address[count++] = coords[2];
4409 }
4410 }
4411
4412 /* Pack LOD */
4413 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4414 instr->op == nir_texop_txf)) {
4415 address[count++] = lod;
4416 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4417 address[count++] = sample_index;
4418 } else if(instr->op == nir_texop_txs) {
4419 count = 0;
4420 if (lod)
4421 address[count++] = lod;
4422 else
4423 address[count++] = ctx->i32zero;
4424 }
4425
4426 for (chan = 0; chan < count; chan++) {
4427 address[chan] = LLVMBuildBitCast(ctx->builder,
4428 address[chan], ctx->i32, "");
4429 }
4430
4431 if (instr->op == nir_texop_samples_identical) {
4432 LLVMValueRef txf_address[4];
4433 struct ac_image_args txf_args = { 0 };
4434 unsigned txf_count = count;
4435 memcpy(txf_address, address, sizeof(txf_address));
4436
4437 if (!instr->is_array)
4438 txf_address[2] = ctx->i32zero;
4439 txf_address[3] = ctx->i32zero;
4440
4441 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4442 fmask_ptr, NULL,
4443 txf_address, txf_count, 0xf);
4444
4445 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4446
4447 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4448 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->i32zero);
4449 goto write_result;
4450 }
4451
4452 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4453 instr->op != nir_texop_txs) {
4454 unsigned sample_chan = instr->is_array ? 3 : 2;
4455 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4456 address[0],
4457 address[1],
4458 instr->is_array ? address[2] : NULL,
4459 address[sample_chan],
4460 fmask_ptr);
4461 }
4462
4463 if (offsets && instr->op == nir_texop_txf) {
4464 nir_const_value *const_offset =
4465 nir_src_as_const_value(instr->src[const_src].src);
4466 int num_offsets = instr->src[const_src].src.ssa->num_components;
4467 assert(const_offset);
4468 num_offsets = MIN2(num_offsets, instr->coord_components);
4469 if (num_offsets > 2)
4470 address[2] = LLVMBuildAdd(ctx->builder,
4471 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4472 if (num_offsets > 1)
4473 address[1] = LLVMBuildAdd(ctx->builder,
4474 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4475 address[0] = LLVMBuildAdd(ctx->builder,
4476 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4477
4478 }
4479
4480 /* TODO TG4 support */
4481 if (instr->op == nir_texop_tg4) {
4482 if (instr->is_shadow)
4483 dmask = 1;
4484 else
4485 dmask = 1 << instr->component;
4486 }
4487 set_tex_fetch_args(ctx, &args, instr, instr->op,
4488 res_ptr, samp_ptr, address, count, dmask);
4489
4490 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4491
4492 if (instr->op == nir_texop_query_levels)
4493 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4494 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4495 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4496 else if (instr->op == nir_texop_txs &&
4497 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4498 instr->is_array) {
4499 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4500 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4501 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4502 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4503 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4504 } else if (instr->dest.ssa.num_components != 4)
4505 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4506
4507 write_result:
4508 if (result) {
4509 assert(instr->dest.is_ssa);
4510 result = to_integer(&ctx->ac, result);
4511 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4512 }
4513 }
4514
4515
4516 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4517 {
4518 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4519 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4520
4521 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4522 _mesa_hash_table_insert(ctx->phis, instr, result);
4523 }
4524
4525 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4526 nir_phi_instr *instr,
4527 LLVMValueRef llvm_phi)
4528 {
4529 nir_foreach_phi_src(src, instr) {
4530 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4531 LLVMValueRef llvm_src = get_src(ctx, src->src);
4532
4533 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4534 }
4535 }
4536
4537 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4538 {
4539 struct hash_entry *entry;
4540 hash_table_foreach(ctx->phis, entry) {
4541 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4542 (LLVMValueRef)entry->data);
4543 }
4544 }
4545
4546
4547 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4548 const nir_ssa_undef_instr *instr)
4549 {
4550 unsigned num_components = instr->def.num_components;
4551 LLVMValueRef undef;
4552
4553 if (num_components == 1)
4554 undef = LLVMGetUndef(ctx->i32);
4555 else {
4556 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4557 }
4558 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4559 }
4560
4561 static void visit_jump(struct nir_to_llvm_context *ctx,
4562 const nir_jump_instr *instr)
4563 {
4564 switch (instr->type) {
4565 case nir_jump_break:
4566 LLVMBuildBr(ctx->builder, ctx->break_block);
4567 LLVMClearInsertionPosition(ctx->builder);
4568 break;
4569 case nir_jump_continue:
4570 LLVMBuildBr(ctx->builder, ctx->continue_block);
4571 LLVMClearInsertionPosition(ctx->builder);
4572 break;
4573 default:
4574 fprintf(stderr, "Unknown NIR jump instr: ");
4575 nir_print_instr(&instr->instr, stderr);
4576 fprintf(stderr, "\n");
4577 abort();
4578 }
4579 }
4580
4581 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4582 struct exec_list *list);
4583
4584 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4585 {
4586 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4587 nir_foreach_instr(instr, block)
4588 {
4589 switch (instr->type) {
4590 case nir_instr_type_alu:
4591 visit_alu(ctx, nir_instr_as_alu(instr));
4592 break;
4593 case nir_instr_type_load_const:
4594 visit_load_const(ctx, nir_instr_as_load_const(instr));
4595 break;
4596 case nir_instr_type_intrinsic:
4597 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4598 break;
4599 case nir_instr_type_tex:
4600 visit_tex(ctx, nir_instr_as_tex(instr));
4601 break;
4602 case nir_instr_type_phi:
4603 visit_phi(ctx, nir_instr_as_phi(instr));
4604 break;
4605 case nir_instr_type_ssa_undef:
4606 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4607 break;
4608 case nir_instr_type_jump:
4609 visit_jump(ctx, nir_instr_as_jump(instr));
4610 break;
4611 default:
4612 fprintf(stderr, "Unknown NIR instr type: ");
4613 nir_print_instr(instr, stderr);
4614 fprintf(stderr, "\n");
4615 abort();
4616 }
4617 }
4618
4619 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4620 }
4621
4622 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4623 {
4624 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4625
4626 LLVMBasicBlockRef merge_block =
4627 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4628 LLVMBasicBlockRef if_block =
4629 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4630 LLVMBasicBlockRef else_block = merge_block;
4631 if (!exec_list_is_empty(&if_stmt->else_list))
4632 else_block = LLVMAppendBasicBlockInContext(
4633 ctx->context, ctx->main_function, "");
4634
4635 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4636 LLVMConstInt(ctx->i32, 0, false), "");
4637 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4638
4639 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4640 visit_cf_list(ctx, &if_stmt->then_list);
4641 if (LLVMGetInsertBlock(ctx->builder))
4642 LLVMBuildBr(ctx->builder, merge_block);
4643
4644 if (!exec_list_is_empty(&if_stmt->else_list)) {
4645 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4646 visit_cf_list(ctx, &if_stmt->else_list);
4647 if (LLVMGetInsertBlock(ctx->builder))
4648 LLVMBuildBr(ctx->builder, merge_block);
4649 }
4650
4651 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4652 }
4653
4654 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4655 {
4656 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4657 LLVMBasicBlockRef break_parent = ctx->break_block;
4658
4659 ctx->continue_block =
4660 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4661 ctx->break_block =
4662 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4663
4664 LLVMBuildBr(ctx->builder, ctx->continue_block);
4665 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4666 visit_cf_list(ctx, &loop->body);
4667
4668 if (LLVMGetInsertBlock(ctx->builder))
4669 LLVMBuildBr(ctx->builder, ctx->continue_block);
4670 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4671
4672 ctx->continue_block = continue_parent;
4673 ctx->break_block = break_parent;
4674 }
4675
4676 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4677 struct exec_list *list)
4678 {
4679 foreach_list_typed(nir_cf_node, node, node, list)
4680 {
4681 switch (node->type) {
4682 case nir_cf_node_block:
4683 visit_block(ctx, nir_cf_node_as_block(node));
4684 break;
4685
4686 case nir_cf_node_if:
4687 visit_if(ctx, nir_cf_node_as_if(node));
4688 break;
4689
4690 case nir_cf_node_loop:
4691 visit_loop(ctx, nir_cf_node_as_loop(node));
4692 break;
4693
4694 default:
4695 assert(0);
4696 }
4697 }
4698 }
4699
4700 static void
4701 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4702 struct nir_variable *variable)
4703 {
4704 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4705 LLVMValueRef t_offset;
4706 LLVMValueRef t_list;
4707 LLVMValueRef input;
4708 LLVMValueRef buffer_index;
4709 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4710 int idx = variable->data.location;
4711 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4712
4713 variable->data.driver_location = idx * 4;
4714
4715 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4716 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4717 ctx->start_instance, "");
4718 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4719 ctx->shader_info->vs.vgpr_comp_cnt);
4720 } else
4721 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4722 ctx->base_vertex, "");
4723
4724 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4725 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4726
4727 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4728
4729 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4730 buffer_index,
4731 LLVMConstInt(ctx->i32, 0, false),
4732 true);
4733
4734 for (unsigned chan = 0; chan < 4; chan++) {
4735 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4736 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4737 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4738 input, llvm_chan, ""));
4739 }
4740 }
4741 }
4742
4743 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4744 unsigned attr,
4745 LLVMValueRef interp_param,
4746 LLVMValueRef prim_mask,
4747 LLVMValueRef result[4])
4748 {
4749 LLVMValueRef attr_number;
4750 unsigned chan;
4751 LLVMValueRef i, j;
4752 bool interp = interp_param != NULL;
4753
4754 attr_number = LLVMConstInt(ctx->i32, attr, false);
4755
4756 /* fs.constant returns the param from the middle vertex, so it's not
4757 * really useful for flat shading. It's meant to be used for custom
4758 * interpolation (but the intrinsic can't fetch from the other two
4759 * vertices).
4760 *
4761 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4762 * to do the right thing. The only reason we use fs.constant is that
4763 * fs.interp cannot be used on integers, because they can be equal
4764 * to NaN.
4765 */
4766 if (interp) {
4767 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4768 LLVMVectorType(ctx->f32, 2), "");
4769
4770 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4771 ctx->i32zero, "");
4772 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4773 ctx->i32one, "");
4774 }
4775
4776 for (chan = 0; chan < 4; chan++) {
4777 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4778
4779 if (interp) {
4780 result[chan] = ac_build_fs_interp(&ctx->ac,
4781 llvm_chan,
4782 attr_number,
4783 prim_mask, i, j);
4784 } else {
4785 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4786 LLVMConstInt(ctx->i32, 2, false),
4787 llvm_chan,
4788 attr_number,
4789 prim_mask);
4790 }
4791 }
4792 }
4793
4794 static void
4795 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4796 struct nir_variable *variable)
4797 {
4798 int idx = variable->data.location;
4799 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4800 LLVMValueRef interp;
4801
4802 variable->data.driver_location = idx * 4;
4803 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4804
4805 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4806 unsigned interp_type;
4807 if (variable->data.sample) {
4808 interp_type = INTERP_SAMPLE;
4809 ctx->shader_info->fs.force_persample = true;
4810 } else if (variable->data.centroid)
4811 interp_type = INTERP_CENTROID;
4812 else
4813 interp_type = INTERP_CENTER;
4814
4815 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4816 } else
4817 interp = NULL;
4818
4819 for (unsigned i = 0; i < attrib_count; ++i)
4820 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4821
4822 }
4823
4824 static void
4825 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4826 struct nir_variable *variable)
4827 {
4828 switch (ctx->stage) {
4829 case MESA_SHADER_VERTEX:
4830 handle_vs_input_decl(ctx, variable);
4831 break;
4832 case MESA_SHADER_FRAGMENT:
4833 handle_fs_input_decl(ctx, variable);
4834 break;
4835 default:
4836 break;
4837 }
4838
4839 }
4840
4841 static void
4842 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4843 struct nir_shader *nir)
4844 {
4845 unsigned index = 0;
4846 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4847 LLVMValueRef interp_param;
4848 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4849
4850 if (!(ctx->input_mask & (1ull << i)))
4851 continue;
4852
4853 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4854 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4855 interp_param = *inputs;
4856 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4857 inputs);
4858
4859 if (!interp_param)
4860 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4861 ++index;
4862 } else if (i == VARYING_SLOT_POS) {
4863 for(int i = 0; i < 3; ++i)
4864 inputs[i] = ctx->frag_pos[i];
4865
4866 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4867 }
4868 }
4869 ctx->shader_info->fs.num_interp = index;
4870 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4871 ctx->shader_info->fs.has_pcoord = true;
4872 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4873 ctx->shader_info->fs.prim_id_input = true;
4874 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4875 ctx->shader_info->fs.layer_input = true;
4876 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4877 }
4878
4879 static LLVMValueRef
4880 ac_build_alloca(struct nir_to_llvm_context *ctx,
4881 LLVMTypeRef type,
4882 const char *name)
4883 {
4884 LLVMBuilderRef builder = ctx->builder;
4885 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4886 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4887 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4888 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4889 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4890 LLVMValueRef res;
4891
4892 if (first_instr) {
4893 LLVMPositionBuilderBefore(first_builder, first_instr);
4894 } else {
4895 LLVMPositionBuilderAtEnd(first_builder, first_block);
4896 }
4897
4898 res = LLVMBuildAlloca(first_builder, type, name);
4899 LLVMBuildStore(builder, LLVMConstNull(type), res);
4900
4901 LLVMDisposeBuilder(first_builder);
4902
4903 return res;
4904 }
4905
4906 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4907 LLVMTypeRef type,
4908 const char *name)
4909 {
4910 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4911 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4912 return ptr;
4913 }
4914
4915 static void
4916 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4917 struct nir_variable *variable)
4918 {
4919 int idx = variable->data.location + variable->data.index;
4920 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4921 uint64_t mask_attribs;
4922 variable->data.driver_location = idx * 4;
4923
4924 /* tess ctrl has it's own load/store paths for outputs */
4925 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4926 return;
4927
4928 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4929 if (ctx->stage == MESA_SHADER_VERTEX ||
4930 ctx->stage == MESA_SHADER_TESS_EVAL ||
4931 ctx->stage == MESA_SHADER_GEOMETRY) {
4932 if (idx == VARYING_SLOT_CLIP_DIST0) {
4933 int length = ctx->num_output_clips + ctx->num_output_culls;
4934 if (ctx->stage == MESA_SHADER_VERTEX) {
4935 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4936 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4937 }
4938 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4939 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4940 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4941 }
4942
4943 if (length > 4)
4944 attrib_count = 2;
4945 else
4946 attrib_count = 1;
4947 mask_attribs = 1ull << idx;
4948 }
4949 }
4950
4951 for (unsigned i = 0; i < attrib_count; ++i) {
4952 for (unsigned chan = 0; chan < 4; chan++) {
4953 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4954 si_build_alloca_undef(ctx, ctx->f32, "");
4955 }
4956 }
4957 ctx->output_mask |= mask_attribs;
4958 }
4959
4960 static void
4961 setup_locals(struct nir_to_llvm_context *ctx,
4962 struct nir_function *func)
4963 {
4964 int i, j;
4965 ctx->num_locals = 0;
4966 nir_foreach_variable(variable, &func->impl->locals) {
4967 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4968 variable->data.driver_location = ctx->num_locals * 4;
4969 ctx->num_locals += attrib_count;
4970 }
4971 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4972 if (!ctx->locals)
4973 return;
4974
4975 for (i = 0; i < ctx->num_locals; i++) {
4976 for (j = 0; j < 4; j++) {
4977 ctx->locals[i * 4 + j] =
4978 si_build_alloca_undef(ctx, ctx->f32, "temp");
4979 }
4980 }
4981 }
4982
4983 static LLVMValueRef
4984 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4985 {
4986 v = to_float(ctx, v);
4987 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4988 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4989 }
4990
4991
4992 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4993 LLVMValueRef src0, LLVMValueRef src1)
4994 {
4995 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4996 LLVMValueRef comp[2];
4997
4998 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4999 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5000 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5001 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5002 }
5003
5004 /* Initialize arguments for the shader export intrinsic */
5005 static void
5006 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5007 LLVMValueRef *values,
5008 unsigned target,
5009 struct ac_export_args *args)
5010 {
5011 /* Default is 0xf. Adjusted below depending on the format. */
5012 args->enabled_channels = 0xf;
5013
5014 /* Specify whether the EXEC mask represents the valid mask */
5015 args->valid_mask = 0;
5016
5017 /* Specify whether this is the last export */
5018 args->done = 0;
5019
5020 /* Specify the target we are exporting */
5021 args->target = target;
5022
5023 args->compr = false;
5024 args->out[0] = LLVMGetUndef(ctx->f32);
5025 args->out[1] = LLVMGetUndef(ctx->f32);
5026 args->out[2] = LLVMGetUndef(ctx->f32);
5027 args->out[3] = LLVMGetUndef(ctx->f32);
5028
5029 if (!values)
5030 return;
5031
5032 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5033 LLVMValueRef val[4];
5034 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5035 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5036 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5037
5038 switch(col_format) {
5039 case V_028714_SPI_SHADER_ZERO:
5040 args->enabled_channels = 0; /* writemask */
5041 args->target = V_008DFC_SQ_EXP_NULL;
5042 break;
5043
5044 case V_028714_SPI_SHADER_32_R:
5045 args->enabled_channels = 1;
5046 args->out[0] = values[0];
5047 break;
5048
5049 case V_028714_SPI_SHADER_32_GR:
5050 args->enabled_channels = 0x3;
5051 args->out[0] = values[0];
5052 args->out[1] = values[1];
5053 break;
5054
5055 case V_028714_SPI_SHADER_32_AR:
5056 args->enabled_channels = 0x9;
5057 args->out[0] = values[0];
5058 args->out[3] = values[3];
5059 break;
5060
5061 case V_028714_SPI_SHADER_FP16_ABGR:
5062 args->compr = 1;
5063
5064 for (unsigned chan = 0; chan < 2; chan++) {
5065 LLVMValueRef pack_args[2] = {
5066 values[2 * chan],
5067 values[2 * chan + 1]
5068 };
5069 LLVMValueRef packed;
5070
5071 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5072 args->out[chan] = packed;
5073 }
5074 break;
5075
5076 case V_028714_SPI_SHADER_UNORM16_ABGR:
5077 for (unsigned chan = 0; chan < 4; chan++) {
5078 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5079 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5080 LLVMConstReal(ctx->f32, 65535), "");
5081 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5082 LLVMConstReal(ctx->f32, 0.5), "");
5083 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5084 ctx->i32, "");
5085 }
5086
5087 args->compr = 1;
5088 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5089 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5090 break;
5091
5092 case V_028714_SPI_SHADER_SNORM16_ABGR:
5093 for (unsigned chan = 0; chan < 4; chan++) {
5094 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5095 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5096 LLVMConstReal(ctx->f32, 32767), "");
5097
5098 /* If positive, add 0.5, else add -0.5. */
5099 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5100 LLVMBuildSelect(ctx->builder,
5101 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5102 val[chan], ctx->f32zero, ""),
5103 LLVMConstReal(ctx->f32, 0.5),
5104 LLVMConstReal(ctx->f32, -0.5), ""), "");
5105 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5106 }
5107
5108 args->compr = 1;
5109 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5110 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5111 break;
5112
5113 case V_028714_SPI_SHADER_UINT16_ABGR: {
5114 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5115
5116 for (unsigned chan = 0; chan < 4; chan++) {
5117 val[chan] = to_integer(&ctx->ac, values[chan]);
5118 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], max);
5119 }
5120
5121 args->compr = 1;
5122 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5123 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5124 break;
5125 }
5126
5127 case V_028714_SPI_SHADER_SINT16_ABGR: {
5128 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5129 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5130
5131 /* Clamp. */
5132 for (unsigned chan = 0; chan < 4; chan++) {
5133 val[chan] = to_integer(&ctx->ac, values[chan]);
5134 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], max);
5135 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], min);
5136 }
5137
5138 args->compr = 1;
5139 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5140 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5141 break;
5142 }
5143
5144 default:
5145 case V_028714_SPI_SHADER_32_ABGR:
5146 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5147 break;
5148 }
5149 } else
5150 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5151
5152 for (unsigned i = 0; i < 4; ++i)
5153 args->out[i] = to_float(&ctx->ac, args->out[i]);
5154 }
5155
5156 static void
5157 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5158 bool export_prim_id,
5159 struct ac_vs_output_info *outinfo)
5160 {
5161 uint32_t param_count = 0;
5162 unsigned target;
5163 unsigned pos_idx, num_pos_exports = 0;
5164 struct ac_export_args args, pos_args[4] = {};
5165 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5166 int i;
5167
5168 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5169 sizeof(outinfo->vs_output_param_offset));
5170
5171 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5172 LLVMValueRef slots[8];
5173 unsigned j;
5174
5175 if (outinfo->cull_dist_mask)
5176 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5177
5178 i = VARYING_SLOT_CLIP_DIST0;
5179 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5180 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5181 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5182
5183 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5184 slots[i] = LLVMGetUndef(ctx->f32);
5185
5186 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5187 target = V_008DFC_SQ_EXP_POS + 3;
5188 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5189 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5190 &args, sizeof(args));
5191 }
5192
5193 target = V_008DFC_SQ_EXP_POS + 2;
5194 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5195 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5196 &args, sizeof(args));
5197
5198 }
5199
5200 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5201 LLVMValueRef values[4];
5202 if (!(ctx->output_mask & (1ull << i)))
5203 continue;
5204
5205 for (unsigned j = 0; j < 4; j++)
5206 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5207 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5208
5209 if (i == VARYING_SLOT_POS) {
5210 target = V_008DFC_SQ_EXP_POS;
5211 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5212 continue;
5213 } else if (i == VARYING_SLOT_PSIZ) {
5214 outinfo->writes_pointsize = true;
5215 psize_value = values[0];
5216 continue;
5217 } else if (i == VARYING_SLOT_LAYER) {
5218 outinfo->writes_layer = true;
5219 layer_value = values[0];
5220 target = V_008DFC_SQ_EXP_PARAM + param_count;
5221 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5222 param_count++;
5223 } else if (i == VARYING_SLOT_VIEWPORT) {
5224 outinfo->writes_viewport_index = true;
5225 viewport_index_value = values[0];
5226 continue;
5227 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5228 target = V_008DFC_SQ_EXP_PARAM + param_count;
5229 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5230 param_count++;
5231 } else if (i >= VARYING_SLOT_VAR0) {
5232 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5233 target = V_008DFC_SQ_EXP_PARAM + param_count;
5234 outinfo->vs_output_param_offset[i] = param_count;
5235 param_count++;
5236 }
5237
5238 si_llvm_init_export_args(ctx, values, target, &args);
5239
5240 if (target >= V_008DFC_SQ_EXP_POS &&
5241 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5242 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5243 &args, sizeof(args));
5244 } else {
5245 ac_build_export(&ctx->ac, &args);
5246 }
5247 }
5248
5249 /* We need to add the position output manually if it's missing. */
5250 if (!pos_args[0].out[0]) {
5251 pos_args[0].enabled_channels = 0xf;
5252 pos_args[0].valid_mask = 0;
5253 pos_args[0].done = 0;
5254 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5255 pos_args[0].compr = 0;
5256 pos_args[0].out[0] = ctx->f32zero; /* X */
5257 pos_args[0].out[1] = ctx->f32zero; /* Y */
5258 pos_args[0].out[2] = ctx->f32zero; /* Z */
5259 pos_args[0].out[3] = ctx->f32one; /* W */
5260 }
5261
5262 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5263 (outinfo->writes_layer == true ? 4 : 0) |
5264 (outinfo->writes_viewport_index == true ? 8 : 0));
5265 if (mask) {
5266 pos_args[1].enabled_channels = mask;
5267 pos_args[1].valid_mask = 0;
5268 pos_args[1].done = 0;
5269 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5270 pos_args[1].compr = 0;
5271 pos_args[1].out[0] = ctx->f32zero; /* X */
5272 pos_args[1].out[1] = ctx->f32zero; /* Y */
5273 pos_args[1].out[2] = ctx->f32zero; /* Z */
5274 pos_args[1].out[3] = ctx->f32zero; /* W */
5275
5276 if (outinfo->writes_pointsize == true)
5277 pos_args[1].out[0] = psize_value;
5278 if (outinfo->writes_layer == true)
5279 pos_args[1].out[2] = layer_value;
5280 if (outinfo->writes_viewport_index == true)
5281 pos_args[1].out[3] = viewport_index_value;
5282 }
5283 for (i = 0; i < 4; i++) {
5284 if (pos_args[i].out[0])
5285 num_pos_exports++;
5286 }
5287
5288 pos_idx = 0;
5289 for (i = 0; i < 4; i++) {
5290 if (!pos_args[i].out[0])
5291 continue;
5292
5293 /* Specify the target we are exporting */
5294 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5295 if (pos_idx == num_pos_exports)
5296 pos_args[i].done = 1;
5297 ac_build_export(&ctx->ac, &pos_args[i]);
5298 }
5299
5300
5301 if (export_prim_id) {
5302 LLVMValueRef values[4];
5303 target = V_008DFC_SQ_EXP_PARAM + param_count;
5304 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5305 param_count++;
5306
5307 values[0] = ctx->vs_prim_id;
5308 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5309 ctx->shader_info->vs.vgpr_comp_cnt);
5310 for (unsigned j = 1; j < 4; j++)
5311 values[j] = ctx->f32zero;
5312 si_llvm_init_export_args(ctx, values, target, &args);
5313 ac_build_export(&ctx->ac, &args);
5314 outinfo->export_prim_id = true;
5315 }
5316
5317 outinfo->pos_exports = num_pos_exports;
5318 outinfo->param_exports = param_count;
5319 }
5320
5321 static void
5322 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5323 struct ac_es_output_info *outinfo)
5324 {
5325 int j;
5326 uint64_t max_output_written = 0;
5327 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5328 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5329 int param_index;
5330 int length = 4;
5331
5332 if (!(ctx->output_mask & (1ull << i)))
5333 continue;
5334
5335 if (i == VARYING_SLOT_CLIP_DIST0)
5336 length = ctx->num_output_clips + ctx->num_output_culls;
5337
5338 param_index = shader_io_get_unique_index(i);
5339
5340 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5341
5342 for (j = 0; j < length; j++) {
5343 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5344 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5345
5346 ac_build_buffer_store_dword(&ctx->ac,
5347 ctx->esgs_ring,
5348 out_val, 1,
5349 NULL, ctx->es2gs_offset,
5350 (4 * param_index + j) * 4,
5351 1, 1, true, true);
5352 }
5353 }
5354 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5355 }
5356
5357 static void
5358 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5359 {
5360 LLVMValueRef vertex_id = ctx->rel_auto_id;
5361 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5362 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5363 vertex_dw_stride, "");
5364
5365 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5366 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5367 int length = 4;
5368
5369 if (!(ctx->output_mask & (1ull << i)))
5370 continue;
5371
5372 if (i == VARYING_SLOT_CLIP_DIST0)
5373 length = ctx->num_output_clips + ctx->num_output_culls;
5374 int param = shader_io_get_unique_index(i);
5375 mark_tess_output(ctx, false, param);
5376 if (length > 4)
5377 mark_tess_output(ctx, false, param + 1);
5378 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5379 LLVMConstInt(ctx->i32, param * 4, false),
5380 "");
5381 for (unsigned j = 0; j < length; j++) {
5382 lds_store(ctx, dw_addr,
5383 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5384 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5385 }
5386 }
5387 }
5388
5389 struct ac_build_if_state
5390 {
5391 struct nir_to_llvm_context *ctx;
5392 LLVMValueRef condition;
5393 LLVMBasicBlockRef entry_block;
5394 LLVMBasicBlockRef true_block;
5395 LLVMBasicBlockRef false_block;
5396 LLVMBasicBlockRef merge_block;
5397 };
5398
5399 static LLVMBasicBlockRef
5400 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5401 {
5402 LLVMBasicBlockRef current_block;
5403 LLVMBasicBlockRef next_block;
5404 LLVMBasicBlockRef new_block;
5405
5406 /* get current basic block */
5407 current_block = LLVMGetInsertBlock(ctx->builder);
5408
5409 /* chqeck if there's another block after this one */
5410 next_block = LLVMGetNextBasicBlock(current_block);
5411 if (next_block) {
5412 /* insert the new block before the next block */
5413 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5414 }
5415 else {
5416 /* append new block after current block */
5417 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5418 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5419 }
5420 return new_block;
5421 }
5422
5423 static void
5424 ac_nir_build_if(struct ac_build_if_state *ifthen,
5425 struct nir_to_llvm_context *ctx,
5426 LLVMValueRef condition)
5427 {
5428 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5429
5430 memset(ifthen, 0, sizeof *ifthen);
5431 ifthen->ctx = ctx;
5432 ifthen->condition = condition;
5433 ifthen->entry_block = block;
5434
5435 /* create endif/merge basic block for the phi functions */
5436 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5437
5438 /* create/insert true_block before merge_block */
5439 ifthen->true_block =
5440 LLVMInsertBasicBlockInContext(ctx->context,
5441 ifthen->merge_block,
5442 "if-true-block");
5443
5444 /* successive code goes into the true block */
5445 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5446 }
5447
5448 /**
5449 * End a conditional.
5450 */
5451 static void
5452 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5453 {
5454 LLVMBuilderRef builder = ifthen->ctx->builder;
5455
5456 /* Insert branch to the merge block from current block */
5457 LLVMBuildBr(builder, ifthen->merge_block);
5458
5459 /*
5460 * Now patch in the various branch instructions.
5461 */
5462
5463 /* Insert the conditional branch instruction at the end of entry_block */
5464 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5465 if (ifthen->false_block) {
5466 /* we have an else clause */
5467 LLVMBuildCondBr(builder, ifthen->condition,
5468 ifthen->true_block, ifthen->false_block);
5469 }
5470 else {
5471 /* no else clause */
5472 LLVMBuildCondBr(builder, ifthen->condition,
5473 ifthen->true_block, ifthen->merge_block);
5474 }
5475
5476 /* Resume building code at end of the ifthen->merge_block */
5477 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5478 }
5479
5480 static void
5481 write_tess_factors(struct nir_to_llvm_context *ctx)
5482 {
5483 unsigned stride, outer_comps, inner_comps;
5484 struct ac_build_if_state if_ctx, inner_if_ctx;
5485 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5486 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5487 unsigned tess_inner_index, tess_outer_index;
5488 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5489 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5490 int i;
5491 emit_barrier(ctx);
5492
5493 switch (ctx->options->key.tcs.primitive_mode) {
5494 case GL_ISOLINES:
5495 stride = 2;
5496 outer_comps = 2;
5497 inner_comps = 0;
5498 break;
5499 case GL_TRIANGLES:
5500 stride = 4;
5501 outer_comps = 3;
5502 inner_comps = 1;
5503 break;
5504 case GL_QUADS:
5505 stride = 6;
5506 outer_comps = 4;
5507 inner_comps = 2;
5508 break;
5509 default:
5510 return;
5511 }
5512
5513 ac_nir_build_if(&if_ctx, ctx,
5514 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5515 invocation_id, ctx->i32zero, ""));
5516
5517 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5518 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5519
5520 mark_tess_output(ctx, true, tess_inner_index);
5521 mark_tess_output(ctx, true, tess_outer_index);
5522 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5523 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5524 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5525 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5526 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5527
5528 for (i = 0; i < 4; i++) {
5529 inner[i] = LLVMGetUndef(ctx->i32);
5530 outer[i] = LLVMGetUndef(ctx->i32);
5531 }
5532
5533 // LINES reverseal
5534 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5535 outer[0] = out[1] = lds_load(ctx, lds_outer);
5536 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5537 LLVMConstInt(ctx->i32, 1, false), "");
5538 outer[1] = out[0] = lds_load(ctx, lds_outer);
5539 } else {
5540 for (i = 0; i < outer_comps; i++) {
5541 outer[i] = out[i] =
5542 lds_load(ctx, lds_outer);
5543 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5544 LLVMConstInt(ctx->i32, 1, false), "");
5545 }
5546 for (i = 0; i < inner_comps; i++) {
5547 inner[i] = out[outer_comps+i] =
5548 lds_load(ctx, lds_inner);
5549 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5550 LLVMConstInt(ctx->i32, 1, false), "");
5551 }
5552 }
5553
5554 /* Convert the outputs to vectors for stores. */
5555 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5556 vec1 = NULL;
5557
5558 if (stride > 4)
5559 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5560
5561
5562 buffer = ctx->hs_ring_tess_factor;
5563 tf_base = ctx->tess_factor_offset;
5564 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5565 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5566
5567 ac_nir_build_if(&inner_if_ctx, ctx,
5568 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5569 rel_patch_id, ctx->i32zero, ""));
5570
5571 /* Store the dynamic HS control word. */
5572 ac_build_buffer_store_dword(&ctx->ac, buffer,
5573 LLVMConstInt(ctx->i32, 0x80000000, false),
5574 1, ctx->i32zero, tf_base,
5575 0, 1, 0, true, false);
5576 ac_nir_build_endif(&inner_if_ctx);
5577
5578 /* Store the tessellation factors. */
5579 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5580 MIN2(stride, 4), byteoffset, tf_base,
5581 4, 1, 0, true, false);
5582 if (vec1)
5583 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5584 stride - 4, byteoffset, tf_base,
5585 20, 1, 0, true, false);
5586
5587 //TODO store to offchip for TES to read - only if TES reads them
5588 if (1) {
5589 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5590 LLVMValueRef tf_inner_offset;
5591 unsigned param_outer, param_inner;
5592
5593 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5594 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5595 LLVMConstInt(ctx->i32, param_outer, 0));
5596
5597 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5598 util_next_power_of_two(outer_comps));
5599
5600 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5601 outer_comps, tf_outer_offset,
5602 ctx->oc_lds, 0, 1, 0, true, false);
5603 if (inner_comps) {
5604 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5605 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5606 LLVMConstInt(ctx->i32, param_inner, 0));
5607
5608 inner_vec = inner_comps == 1 ? inner[0] :
5609 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5610 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5611 inner_comps, tf_inner_offset,
5612 ctx->oc_lds, 0, 1, 0, true, false);
5613 }
5614 }
5615 ac_nir_build_endif(&if_ctx);
5616 }
5617
5618 static void
5619 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5620 {
5621 write_tess_factors(ctx);
5622 }
5623
5624 static bool
5625 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5626 LLVMValueRef *color, unsigned param, bool is_last,
5627 struct ac_export_args *args)
5628 {
5629 /* Export */
5630 si_llvm_init_export_args(ctx, color, param,
5631 args);
5632
5633 if (is_last) {
5634 args->valid_mask = 1; /* whether the EXEC mask is valid */
5635 args->done = 1; /* DONE bit */
5636 } else if (!args->enabled_channels)
5637 return false; /* unnecessary NULL export */
5638
5639 return true;
5640 }
5641
5642 static void
5643 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5644 LLVMValueRef depth, LLVMValueRef stencil,
5645 LLVMValueRef samplemask)
5646 {
5647 struct ac_export_args args;
5648
5649 args.enabled_channels = 0;
5650 args.valid_mask = 1;
5651 args.done = 1;
5652 args.target = V_008DFC_SQ_EXP_MRTZ;
5653 args.compr = false;
5654
5655 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5656 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5657 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5658 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5659
5660 if (depth) {
5661 args.out[0] = depth;
5662 args.enabled_channels |= 0x1;
5663 }
5664
5665 if (stencil) {
5666 args.out[1] = stencil;
5667 args.enabled_channels |= 0x2;
5668 }
5669
5670 if (samplemask) {
5671 args.out[2] = samplemask;
5672 args.enabled_channels |= 0x4;
5673 }
5674
5675 /* SI (except OLAND) has a bug that it only looks
5676 * at the X writemask component. */
5677 if (ctx->options->chip_class == SI &&
5678 ctx->options->family != CHIP_OLAND)
5679 args.enabled_channels |= 0x1;
5680
5681 ac_build_export(&ctx->ac, &args);
5682 }
5683
5684 static void
5685 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5686 {
5687 unsigned index = 0;
5688 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5689 struct ac_export_args color_args[8];
5690
5691 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5692 LLVMValueRef values[4];
5693
5694 if (!(ctx->output_mask & (1ull << i)))
5695 continue;
5696
5697 if (i == FRAG_RESULT_DEPTH) {
5698 ctx->shader_info->fs.writes_z = true;
5699 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5700 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5701 } else if (i == FRAG_RESULT_STENCIL) {
5702 ctx->shader_info->fs.writes_stencil = true;
5703 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5704 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5705 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5706 ctx->shader_info->fs.writes_sample_mask = true;
5707 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5708 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5709 } else {
5710 bool last = false;
5711 for (unsigned j = 0; j < 4; j++)
5712 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5713 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5714
5715 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5716 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5717
5718 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5719 if (ret)
5720 index++;
5721 }
5722 }
5723
5724 for (unsigned i = 0; i < index; i++)
5725 ac_build_export(&ctx->ac, &color_args[i]);
5726 if (depth || stencil || samplemask)
5727 si_export_mrt_z(ctx, depth, stencil, samplemask);
5728 else if (!index) {
5729 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5730 ac_build_export(&ctx->ac, &color_args[0]);
5731 }
5732
5733 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5734 }
5735
5736 static void
5737 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5738 {
5739 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5740 }
5741
5742 static void
5743 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5744 {
5745 switch (ctx->stage) {
5746 case MESA_SHADER_VERTEX:
5747 if (ctx->options->key.vs.as_ls)
5748 handle_ls_outputs_post(ctx);
5749 else if (ctx->options->key.vs.as_es)
5750 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5751 else
5752 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
5753 &ctx->shader_info->vs.outinfo);
5754 break;
5755 case MESA_SHADER_FRAGMENT:
5756 handle_fs_outputs_post(ctx);
5757 break;
5758 case MESA_SHADER_GEOMETRY:
5759 emit_gs_epilogue(ctx);
5760 break;
5761 case MESA_SHADER_TESS_CTRL:
5762 handle_tcs_outputs_post(ctx);
5763 break;
5764 case MESA_SHADER_TESS_EVAL:
5765 if (ctx->options->key.tes.as_es)
5766 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5767 else
5768 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
5769 &ctx->shader_info->tes.outinfo);
5770 break;
5771 default:
5772 break;
5773 }
5774 }
5775
5776 static void
5777 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5778 struct nir_variable *variable, uint32_t *offset, int idx)
5779 {
5780 unsigned size = glsl_count_attribute_slots(variable->type, false);
5781 variable->data.driver_location = *offset;
5782 *offset += size;
5783 }
5784
5785 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5786 {
5787 LLVMPassManagerRef passmgr;
5788 /* Create the pass manager */
5789 passmgr = LLVMCreateFunctionPassManagerForModule(
5790 ctx->module);
5791
5792 /* This pass should eliminate all the load and store instructions */
5793 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5794
5795 /* Add some optimization passes */
5796 LLVMAddScalarReplAggregatesPass(passmgr);
5797 LLVMAddLICMPass(passmgr);
5798 LLVMAddAggressiveDCEPass(passmgr);
5799 LLVMAddCFGSimplificationPass(passmgr);
5800 LLVMAddInstructionCombiningPass(passmgr);
5801
5802 /* Run the pass */
5803 LLVMInitializeFunctionPassManager(passmgr);
5804 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5805 LLVMFinalizeFunctionPassManager(passmgr);
5806
5807 LLVMDisposeBuilder(ctx->builder);
5808 LLVMDisposePassManager(passmgr);
5809 }
5810
5811 static void
5812 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
5813 {
5814 struct ac_vs_output_info *outinfo;
5815
5816 switch (ctx->stage) {
5817 case MESA_SHADER_FRAGMENT:
5818 case MESA_SHADER_COMPUTE:
5819 case MESA_SHADER_TESS_CTRL:
5820 case MESA_SHADER_GEOMETRY:
5821 return;
5822 case MESA_SHADER_VERTEX:
5823 if (ctx->options->key.vs.as_ls ||
5824 ctx->options->key.vs.as_es)
5825 return;
5826 outinfo = &ctx->shader_info->vs.outinfo;
5827 break;
5828 case MESA_SHADER_TESS_EVAL:
5829 if (ctx->options->key.vs.as_es)
5830 return;
5831 outinfo = &ctx->shader_info->tes.outinfo;
5832 break;
5833 default:
5834 unreachable("Unhandled shader type");
5835 }
5836
5837 ac_optimize_vs_outputs(&ctx->ac,
5838 ctx->main_function,
5839 outinfo->vs_output_param_offset,
5840 VARYING_SLOT_MAX,
5841 &outinfo->param_exports);
5842 }
5843
5844 static void
5845 ac_setup_rings(struct nir_to_llvm_context *ctx)
5846 {
5847 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5848 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5849 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5850 }
5851
5852 if (ctx->is_gs_copy_shader) {
5853 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5854 }
5855 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5856 LLVMValueRef tmp;
5857 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5858 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5859
5860 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5861
5862 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5863 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5864 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5865 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5866
5867 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5868 }
5869
5870 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5871 ctx->stage == MESA_SHADER_TESS_EVAL) {
5872 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5873 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5874 }
5875 }
5876
5877 static unsigned
5878 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
5879 const struct nir_shader *nir)
5880 {
5881 switch (nir->stage) {
5882 case MESA_SHADER_TESS_CTRL:
5883 return chip_class >= CIK ? 128 : 64;
5884 case MESA_SHADER_GEOMETRY:
5885 return 64;
5886 case MESA_SHADER_COMPUTE:
5887 break;
5888 default:
5889 return 0;
5890 }
5891
5892 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
5893 nir->info.cs.local_size[1] *
5894 nir->info.cs.local_size[2];
5895 return max_workgroup_size;
5896 }
5897
5898 static
5899 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5900 struct nir_shader *nir,
5901 struct ac_shader_variant_info *shader_info,
5902 const struct ac_nir_compiler_options *options)
5903 {
5904 struct nir_to_llvm_context ctx = {0};
5905 struct nir_function *func;
5906 unsigned i;
5907 ctx.options = options;
5908 ctx.shader_info = shader_info;
5909 ctx.context = LLVMContextCreate();
5910 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5911
5912 ac_llvm_context_init(&ctx.ac, ctx.context);
5913 ctx.ac.module = ctx.module;
5914
5915 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5916
5917 memset(shader_info, 0, sizeof(*shader_info));
5918
5919 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5920
5921 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5922
5923 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5924 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5925 LLVMSetDataLayout(ctx.module, data_layout_str);
5926 LLVMDisposeTargetData(data_layout);
5927 LLVMDisposeMessage(data_layout_str);
5928
5929 setup_types(&ctx);
5930
5931 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5932 ctx.ac.builder = ctx.builder;
5933 ctx.stage = nir->stage;
5934 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
5935
5936 for (i = 0; i < AC_UD_MAX_SETS; i++)
5937 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5938 for (i = 0; i < AC_UD_MAX_UD; i++)
5939 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5940
5941 create_function(&ctx);
5942
5943 if (nir->stage == MESA_SHADER_COMPUTE) {
5944 int num_shared = 0;
5945 nir_foreach_variable(variable, &nir->shared)
5946 num_shared++;
5947 if (num_shared) {
5948 int idx = 0;
5949 uint32_t shared_size = 0;
5950 LLVMValueRef var;
5951 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5952 nir_foreach_variable(variable, &nir->shared) {
5953 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5954 idx++;
5955 }
5956
5957 shared_size *= 16;
5958 var = LLVMAddGlobalInAddressSpace(ctx.module,
5959 LLVMArrayType(ctx.i8, shared_size),
5960 "compute_lds",
5961 LOCAL_ADDR_SPACE);
5962 LLVMSetAlignment(var, 4);
5963 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5964 }
5965 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5966 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5967
5968 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
5969 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5970 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
5971 }
5972
5973 ac_setup_rings(&ctx);
5974
5975 nir_foreach_variable(variable, &nir->inputs)
5976 handle_shader_input_decl(&ctx, variable);
5977
5978 if (nir->stage == MESA_SHADER_FRAGMENT)
5979 handle_fs_inputs_pre(&ctx, nir);
5980
5981 ctx.num_output_clips = nir->info.clip_distance_array_size;
5982 ctx.num_output_culls = nir->info.cull_distance_array_size;
5983
5984 nir_foreach_variable(variable, &nir->outputs)
5985 handle_shader_output_decl(&ctx, variable);
5986
5987 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5988 _mesa_key_pointer_equal);
5989 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5990 _mesa_key_pointer_equal);
5991
5992 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5993
5994 setup_locals(&ctx, func);
5995
5996 visit_cf_list(&ctx, &func->impl->body);
5997 phi_post_pass(&ctx);
5998
5999 handle_shader_outputs_post(&ctx);
6000 LLVMBuildRetVoid(ctx.builder);
6001
6002 ac_llvm_finalize_module(&ctx);
6003
6004 ac_nir_eliminate_const_vs_outputs(&ctx);
6005 free(ctx.locals);
6006 ralloc_free(ctx.defs);
6007 ralloc_free(ctx.phis);
6008
6009 if (nir->stage == MESA_SHADER_GEOMETRY) {
6010 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6011 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6012 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6013 nir->info.gs.vertices_out;
6014 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6015 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6016 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6017 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6018 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6019 }
6020
6021 return ctx.module;
6022 }
6023
6024 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6025 {
6026 unsigned *retval = (unsigned *)context;
6027 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6028 char *description = LLVMGetDiagInfoDescription(di);
6029
6030 if (severity == LLVMDSError) {
6031 *retval = 1;
6032 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6033 description);
6034 }
6035
6036 LLVMDisposeMessage(description);
6037 }
6038
6039 static unsigned ac_llvm_compile(LLVMModuleRef M,
6040 struct ac_shader_binary *binary,
6041 LLVMTargetMachineRef tm)
6042 {
6043 unsigned retval = 0;
6044 char *err;
6045 LLVMContextRef llvm_ctx;
6046 LLVMMemoryBufferRef out_buffer;
6047 unsigned buffer_size;
6048 const char *buffer_data;
6049 LLVMBool mem_err;
6050
6051 /* Setup Diagnostic Handler*/
6052 llvm_ctx = LLVMGetModuleContext(M);
6053
6054 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6055 &retval);
6056
6057 /* Compile IR*/
6058 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6059 &err, &out_buffer);
6060
6061 /* Process Errors/Warnings */
6062 if (mem_err) {
6063 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6064 free(err);
6065 retval = 1;
6066 goto out;
6067 }
6068
6069 /* Extract Shader Code*/
6070 buffer_size = LLVMGetBufferSize(out_buffer);
6071 buffer_data = LLVMGetBufferStart(out_buffer);
6072
6073 ac_elf_read(buffer_data, buffer_size, binary);
6074
6075 /* Clean up */
6076 LLVMDisposeMemoryBuffer(out_buffer);
6077
6078 out:
6079 return retval;
6080 }
6081
6082 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6083 LLVMModuleRef llvm_module,
6084 struct ac_shader_binary *binary,
6085 struct ac_shader_config *config,
6086 struct ac_shader_variant_info *shader_info,
6087 gl_shader_stage stage,
6088 bool dump_shader, bool supports_spill)
6089 {
6090 if (dump_shader)
6091 ac_dump_module(llvm_module);
6092
6093 memset(binary, 0, sizeof(*binary));
6094 int v = ac_llvm_compile(llvm_module, binary, tm);
6095 if (v) {
6096 fprintf(stderr, "compile failed\n");
6097 }
6098
6099 if (dump_shader)
6100 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6101
6102 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6103
6104 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6105 LLVMDisposeModule(llvm_module);
6106 LLVMContextDispose(ctx);
6107
6108 if (stage == MESA_SHADER_FRAGMENT) {
6109 shader_info->num_input_vgprs = 0;
6110 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6111 shader_info->num_input_vgprs += 2;
6112 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6113 shader_info->num_input_vgprs += 2;
6114 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6115 shader_info->num_input_vgprs += 2;
6116 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6117 shader_info->num_input_vgprs += 3;
6118 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6119 shader_info->num_input_vgprs += 2;
6120 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6121 shader_info->num_input_vgprs += 2;
6122 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6123 shader_info->num_input_vgprs += 2;
6124 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6125 shader_info->num_input_vgprs += 1;
6126 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6127 shader_info->num_input_vgprs += 1;
6128 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6129 shader_info->num_input_vgprs += 1;
6130 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6131 shader_info->num_input_vgprs += 1;
6132 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6133 shader_info->num_input_vgprs += 1;
6134 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6135 shader_info->num_input_vgprs += 1;
6136 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6137 shader_info->num_input_vgprs += 1;
6138 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6139 shader_info->num_input_vgprs += 1;
6140 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6141 shader_info->num_input_vgprs += 1;
6142 }
6143 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6144
6145 /* +3 for scratch wave offset and VCC */
6146 config->num_sgprs = MAX2(config->num_sgprs,
6147 shader_info->num_input_sgprs + 3);
6148 }
6149
6150 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6151 struct ac_shader_binary *binary,
6152 struct ac_shader_config *config,
6153 struct ac_shader_variant_info *shader_info,
6154 struct nir_shader *nir,
6155 const struct ac_nir_compiler_options *options,
6156 bool dump_shader)
6157 {
6158
6159 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6160 options);
6161
6162 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6163 switch (nir->stage) {
6164 case MESA_SHADER_COMPUTE:
6165 for (int i = 0; i < 3; ++i)
6166 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6167 break;
6168 case MESA_SHADER_FRAGMENT:
6169 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6170 break;
6171 case MESA_SHADER_GEOMETRY:
6172 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6173 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6174 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6175 shader_info->gs.invocations = nir->info.gs.invocations;
6176 break;
6177 case MESA_SHADER_TESS_EVAL:
6178 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6179 shader_info->tes.spacing = nir->info.tess.spacing;
6180 shader_info->tes.ccw = nir->info.tess.ccw;
6181 shader_info->tes.point_mode = nir->info.tess.point_mode;
6182 shader_info->tes.as_es = options->key.tes.as_es;
6183 break;
6184 case MESA_SHADER_TESS_CTRL:
6185 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6186 break;
6187 case MESA_SHADER_VERTEX:
6188 shader_info->vs.as_es = options->key.vs.as_es;
6189 shader_info->vs.as_ls = options->key.vs.as_ls;
6190 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6191 if (options->key.vs.as_ls)
6192 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6193 break;
6194 default:
6195 break;
6196 }
6197 }
6198
6199 static void
6200 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6201 {
6202 LLVMValueRef args[9];
6203 args[0] = ctx->gsvs_ring;
6204 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6205 args[3] = ctx->i32zero;
6206 args[4] = ctx->i32one; /* OFFEN */
6207 args[5] = ctx->i32zero; /* IDXEN */
6208 args[6] = ctx->i32one; /* GLC */
6209 args[7] = ctx->i32one; /* SLC */
6210 args[8] = ctx->i32zero; /* TFE */
6211
6212 int idx = 0;
6213
6214 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6215 int length = 4;
6216 int slot = idx;
6217 int slot_inc = 1;
6218 if (!(ctx->output_mask & (1ull << i)))
6219 continue;
6220
6221 if (i == VARYING_SLOT_CLIP_DIST0) {
6222 /* unpack clip and cull from a single set of slots */
6223 length = ctx->num_output_clips + ctx->num_output_culls;
6224 if (length > 4)
6225 slot_inc = 2;
6226 }
6227
6228 for (unsigned j = 0; j < length; j++) {
6229 LLVMValueRef value;
6230 args[2] = LLVMConstInt(ctx->i32,
6231 (slot * 4 + j) *
6232 ctx->gs_max_out_vertices * 16 * 4, false);
6233
6234 value = ac_build_intrinsic(&ctx->ac,
6235 "llvm.SI.buffer.load.dword.i32.i32",
6236 ctx->i32, args, 9,
6237 AC_FUNC_ATTR_READONLY |
6238 AC_FUNC_ATTR_LEGACY);
6239
6240 LLVMBuildStore(ctx->builder,
6241 to_float(&ctx->ac, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6242 }
6243 idx += slot_inc;
6244 }
6245 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6246 }
6247
6248 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6249 struct nir_shader *geom_shader,
6250 struct ac_shader_binary *binary,
6251 struct ac_shader_config *config,
6252 struct ac_shader_variant_info *shader_info,
6253 const struct ac_nir_compiler_options *options,
6254 bool dump_shader)
6255 {
6256 struct nir_to_llvm_context ctx = {0};
6257 ctx.context = LLVMContextCreate();
6258 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6259 ctx.options = options;
6260 ctx.shader_info = shader_info;
6261
6262 ac_llvm_context_init(&ctx.ac, ctx.context);
6263 ctx.ac.module = ctx.module;
6264
6265 ctx.is_gs_copy_shader = true;
6266 LLVMSetTarget(ctx.module, "amdgcn--");
6267 setup_types(&ctx);
6268
6269 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6270 ctx.ac.builder = ctx.builder;
6271 ctx.stage = MESA_SHADER_VERTEX;
6272
6273 create_function(&ctx);
6274
6275 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6276 ac_setup_rings(&ctx);
6277
6278 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6279 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6280
6281 nir_foreach_variable(variable, &geom_shader->outputs)
6282 handle_shader_output_decl(&ctx, variable);
6283
6284 ac_gs_copy_shader_emit(&ctx);
6285
6286 LLVMBuildRetVoid(ctx.builder);
6287
6288 ac_llvm_finalize_module(&ctx);
6289
6290 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6291 MESA_SHADER_VERTEX,
6292 dump_shader, options->supports_spill);
6293 }