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ac/nir: add and use ac_shader_abi::load_sampler_desc
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct nir_to_llvm_context;
51
52 struct ac_nir_context {
53 struct ac_llvm_context ac;
54 struct ac_shader_abi *abi;
55
56 gl_shader_stage stage;
57
58 struct hash_table *defs;
59 struct hash_table *phis;
60 struct hash_table *vars;
61
62 LLVMValueRef main_function;
63 LLVMBasicBlockRef continue_block;
64 LLVMBasicBlockRef break_block;
65
66 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
67
68 int num_locals;
69 LLVMValueRef *locals;
70
71 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
72 };
73
74 struct nir_to_llvm_context {
75 struct ac_llvm_context ac;
76 const struct ac_nir_compiler_options *options;
77 struct ac_shader_variant_info *shader_info;
78 struct ac_shader_abi abi;
79 struct ac_nir_context *nir;
80
81 unsigned max_workgroup_size;
82 LLVMContextRef context;
83 LLVMModuleRef module;
84 LLVMBuilderRef builder;
85 LLVMValueRef main_function;
86
87 struct hash_table *defs;
88 struct hash_table *phis;
89
90 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
91 LLVMValueRef ring_offsets;
92 LLVMValueRef push_constants;
93 LLVMValueRef num_work_groups;
94 LLVMValueRef workgroup_ids;
95 LLVMValueRef local_invocation_ids;
96 LLVMValueRef tg_size;
97
98 LLVMValueRef vertex_buffers;
99 LLVMValueRef rel_auto_id;
100 LLVMValueRef vs_prim_id;
101 LLVMValueRef ls_out_layout;
102 LLVMValueRef es2gs_offset;
103
104 LLVMValueRef tcs_offchip_layout;
105 LLVMValueRef tcs_out_offsets;
106 LLVMValueRef tcs_out_layout;
107 LLVMValueRef tcs_in_layout;
108 LLVMValueRef oc_lds;
109 LLVMValueRef tess_factor_offset;
110 LLVMValueRef tcs_patch_id;
111 LLVMValueRef tcs_rel_ids;
112 LLVMValueRef tes_rel_patch_id;
113 LLVMValueRef tes_patch_id;
114 LLVMValueRef tes_u;
115 LLVMValueRef tes_v;
116
117 LLVMValueRef gsvs_ring_stride;
118 LLVMValueRef gsvs_num_entries;
119 LLVMValueRef gs2vs_offset;
120 LLVMValueRef gs_wave_id;
121 LLVMValueRef gs_vtx_offset[6];
122 LLVMValueRef gs_prim_id, gs_invocation_id;
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133 LLVMValueRef front_face;
134 LLVMValueRef ancillary;
135 LLVMValueRef sample_coverage;
136 LLVMValueRef frag_pos[4];
137
138 LLVMTypeRef i1;
139 LLVMTypeRef i8;
140 LLVMTypeRef i16;
141 LLVMTypeRef i32;
142 LLVMTypeRef i64;
143 LLVMTypeRef v2i32;
144 LLVMTypeRef v3i32;
145 LLVMTypeRef v4i32;
146 LLVMTypeRef v8i32;
147 LLVMTypeRef f64;
148 LLVMTypeRef f32;
149 LLVMTypeRef f16;
150 LLVMTypeRef v2f32;
151 LLVMTypeRef v4f32;
152 LLVMTypeRef voidt;
153
154 LLVMValueRef i1true;
155 LLVMValueRef i1false;
156 LLVMValueRef i32zero;
157 LLVMValueRef i32one;
158 LLVMValueRef f32zero;
159 LLVMValueRef f32one;
160 LLVMValueRef v4f32empty;
161
162 unsigned uniform_md_kind;
163 LLVMValueRef empty_md;
164 gl_shader_stage stage;
165
166 LLVMValueRef lds;
167 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
168
169 uint64_t input_mask;
170 uint64_t output_mask;
171 uint8_t num_output_clips;
172 uint8_t num_output_culls;
173
174 bool has_ds_bpermute;
175
176 bool is_gs_copy_shader;
177 LLVMValueRef gs_next_vertex;
178 unsigned gs_max_out_vertices;
179
180 unsigned tes_primitive_mode;
181 uint64_t tess_outputs_written;
182 uint64_t tess_patch_outputs_written;
183 };
184
185 static inline struct nir_to_llvm_context *
186 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
187 {
188 struct nir_to_llvm_context *ctx = NULL;
189 return container_of(abi, ctx, abi);
190 }
191
192 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
193 const nir_deref_var *deref,
194 enum ac_descriptor_type desc_type);
195
196 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
197 {
198 return (index * 4) + chan;
199 }
200
201 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
202 {
203 /* handle patch indices separate */
204 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
205 return 0;
206 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
207 return 1;
208 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
209 return 2 + (slot - VARYING_SLOT_PATCH0);
210
211 if (slot == VARYING_SLOT_POS)
212 return 0;
213 if (slot == VARYING_SLOT_PSIZ)
214 return 1;
215 if (slot == VARYING_SLOT_CLIP_DIST0)
216 return 2;
217 /* 3 is reserved for clip dist as well */
218 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
219 return 4 + (slot - VARYING_SLOT_VAR0);
220 unreachable("illegal slot in get unique index\n");
221 }
222
223 static unsigned llvm_get_type_size(LLVMTypeRef type)
224 {
225 LLVMTypeKind kind = LLVMGetTypeKind(type);
226
227 switch (kind) {
228 case LLVMIntegerTypeKind:
229 return LLVMGetIntTypeWidth(type) / 8;
230 case LLVMFloatTypeKind:
231 return 4;
232 case LLVMPointerTypeKind:
233 return 8;
234 case LLVMVectorTypeKind:
235 return LLVMGetVectorSize(type) *
236 llvm_get_type_size(LLVMGetElementType(type));
237 default:
238 assert(0);
239 return 0;
240 }
241 }
242
243 static void set_llvm_calling_convention(LLVMValueRef func,
244 gl_shader_stage stage)
245 {
246 enum radeon_llvm_calling_convention calling_conv;
247
248 switch (stage) {
249 case MESA_SHADER_VERTEX:
250 case MESA_SHADER_TESS_CTRL:
251 case MESA_SHADER_TESS_EVAL:
252 calling_conv = RADEON_LLVM_AMDGPU_VS;
253 break;
254 case MESA_SHADER_GEOMETRY:
255 calling_conv = RADEON_LLVM_AMDGPU_GS;
256 break;
257 case MESA_SHADER_FRAGMENT:
258 calling_conv = RADEON_LLVM_AMDGPU_PS;
259 break;
260 case MESA_SHADER_COMPUTE:
261 calling_conv = RADEON_LLVM_AMDGPU_CS;
262 break;
263 default:
264 unreachable("Unhandle shader type");
265 }
266
267 LLVMSetFunctionCallConv(func, calling_conv);
268 }
269
270 #define MAX_ARGS 23
271 struct arg_info {
272 LLVMTypeRef types[MAX_ARGS];
273 LLVMValueRef *assign[MAX_ARGS];
274 unsigned array_params_mask;
275 uint8_t count;
276 uint8_t user_sgpr_count;
277 uint8_t sgpr_count;
278 uint8_t num_user_sgprs_used;
279 uint8_t num_sgprs_used;
280 uint8_t num_vgprs_used;
281 };
282
283 static inline void
284 add_argument(struct arg_info *info,
285 LLVMTypeRef type, LLVMValueRef *param_ptr)
286 {
287 assert(info->count < MAX_ARGS);
288 info->assign[info->count] = param_ptr;
289 info->types[info->count] = type;
290 info->count++;
291 }
292
293 static inline void
294 add_sgpr_argument(struct arg_info *info,
295 LLVMTypeRef type, LLVMValueRef *param_ptr)
296 {
297 add_argument(info, type, param_ptr);
298 info->num_sgprs_used += llvm_get_type_size(type) / 4;
299 info->sgpr_count++;
300 }
301
302 static inline void
303 add_user_sgpr_argument(struct arg_info *info,
304 LLVMTypeRef type,
305 LLVMValueRef *param_ptr)
306 {
307 add_sgpr_argument(info, type, param_ptr);
308 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
309 info->user_sgpr_count++;
310 }
311
312 static inline void
313 add_vgpr_argument(struct arg_info *info,
314 LLVMTypeRef type,
315 LLVMValueRef *param_ptr)
316 {
317 add_argument(info, type, param_ptr);
318 info->num_vgprs_used += llvm_get_type_size(type) / 4;
319 }
320
321 static inline void
322 add_user_sgpr_array_argument(struct arg_info *info,
323 LLVMTypeRef type,
324 LLVMValueRef *param_ptr)
325 {
326 info->array_params_mask |= (1 << info->count);
327 add_user_sgpr_argument(info, type, param_ptr);
328 }
329
330 static void assign_arguments(LLVMValueRef main_function,
331 struct arg_info *info)
332 {
333 unsigned i;
334 for (i = 0; i < info->count; i++) {
335 if (info->assign[i])
336 *info->assign[i] = LLVMGetParam(main_function, i);
337 }
338 }
339
340 static LLVMValueRef
341 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
342 LLVMBuilderRef builder, LLVMTypeRef *return_types,
343 unsigned num_return_elems,
344 struct arg_info *args,
345 unsigned max_workgroup_size,
346 bool unsafe_math)
347 {
348 LLVMTypeRef main_function_type, ret_type;
349 LLVMBasicBlockRef main_function_body;
350
351 if (num_return_elems)
352 ret_type = LLVMStructTypeInContext(ctx, return_types,
353 num_return_elems, true);
354 else
355 ret_type = LLVMVoidTypeInContext(ctx);
356
357 /* Setup the function */
358 main_function_type =
359 LLVMFunctionType(ret_type, args->types, args->count, 0);
360 LLVMValueRef main_function =
361 LLVMAddFunction(module, "main", main_function_type);
362 main_function_body =
363 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
364 LLVMPositionBuilderAtEnd(builder, main_function_body);
365
366 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
367 for (unsigned i = 0; i < args->sgpr_count; ++i) {
368 if (args->array_params_mask & (1 << i)) {
369 LLVMValueRef P = LLVMGetParam(main_function, i);
370 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
371 ac_add_attr_dereferenceable(P, UINT64_MAX);
372 }
373 else {
374 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
375 }
376 }
377
378 if (max_workgroup_size) {
379 ac_llvm_add_target_dep_function_attr(main_function,
380 "amdgpu-max-work-group-size",
381 max_workgroup_size);
382 }
383 if (unsafe_math) {
384 /* These were copied from some LLVM test. */
385 LLVMAddTargetDependentFunctionAttr(main_function,
386 "less-precise-fpmad",
387 "true");
388 LLVMAddTargetDependentFunctionAttr(main_function,
389 "no-infs-fp-math",
390 "true");
391 LLVMAddTargetDependentFunctionAttr(main_function,
392 "no-nans-fp-math",
393 "true");
394 LLVMAddTargetDependentFunctionAttr(main_function,
395 "unsafe-fp-math",
396 "true");
397 }
398 return main_function;
399 }
400
401 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
402 {
403 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
404 CONST_ADDR_SPACE);
405 }
406
407 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
408 {
409 if (t == ctx->f16 || t == ctx->i16)
410 return ctx->i16;
411 else if (t == ctx->f32 || t == ctx->i32)
412 return ctx->i32;
413 else if (t == ctx->f64 || t == ctx->i64)
414 return ctx->i64;
415 else
416 unreachable("Unhandled integer size");
417 }
418
419 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
420 {
421 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
422 LLVMTypeRef elem_type = LLVMGetElementType(t);
423 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
424 LLVMGetVectorSize(t));
425 }
426 return to_integer_type_scalar(ctx, t);
427 }
428
429 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
430 {
431 LLVMTypeRef type = LLVMTypeOf(v);
432 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
433 }
434
435 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
436 {
437 if (t == ctx->i16 || t == ctx->f16)
438 return ctx->f16;
439 else if (t == ctx->i32 || t == ctx->f32)
440 return ctx->f32;
441 else if (t == ctx->i64 || t == ctx->f64)
442 return ctx->f64;
443 else
444 unreachable("Unhandled float size");
445 }
446
447 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
448 {
449 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
450 LLVMTypeRef elem_type = LLVMGetElementType(t);
451 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
452 LLVMGetVectorSize(t));
453 }
454 return to_float_type_scalar(ctx, t);
455 }
456
457 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
458 {
459 LLVMTypeRef type = LLVMTypeOf(v);
460 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
461 }
462
463 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
464 {
465 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
466 type = LLVMGetElementType(type);
467
468 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
469 return LLVMGetIntTypeWidth(type);
470
471 if (type == ctx->f16)
472 return 16;
473 if (type == ctx->f32)
474 return 32;
475 if (type == ctx->f64)
476 return 64;
477
478 unreachable("Unhandled type kind in get_elem_bits");
479 }
480
481 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
482 LLVMValueRef param, unsigned rshift,
483 unsigned bitwidth)
484 {
485 LLVMValueRef value = param;
486 if (rshift)
487 value = LLVMBuildLShr(ctx->builder, value,
488 LLVMConstInt(ctx->i32, rshift, false), "");
489
490 if (rshift + bitwidth < 32) {
491 unsigned mask = (1 << bitwidth) - 1;
492 value = LLVMBuildAnd(ctx->builder, value,
493 LLVMConstInt(ctx->i32, mask, false), "");
494 }
495 return value;
496 }
497
498 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
499 {
500 switch (ctx->stage) {
501 case MESA_SHADER_TESS_CTRL:
502 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
503 case MESA_SHADER_TESS_EVAL:
504 return ctx->tes_rel_patch_id;
505 break;
506 default:
507 unreachable("Illegal stage");
508 }
509 }
510
511 /* Tessellation shaders pass outputs to the next shader using LDS.
512 *
513 * LS outputs = TCS inputs
514 * TCS outputs = TES inputs
515 *
516 * The LDS layout is:
517 * - TCS inputs for patch 0
518 * - TCS inputs for patch 1
519 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
520 * - ...
521 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
522 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
523 * - TCS outputs for patch 1
524 * - Per-patch TCS outputs for patch 1
525 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
526 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
527 * - ...
528 *
529 * All three shaders VS(LS), TCS, TES share the same LDS space.
530 */
531 static LLVMValueRef
532 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
533 {
534 if (ctx->stage == MESA_SHADER_VERTEX)
535 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
536 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
537 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
538 else {
539 assert(0);
540 return NULL;
541 }
542 }
543
544 static LLVMValueRef
545 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
546 {
547 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
548 }
549
550 static LLVMValueRef
551 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
552 {
553 return LLVMBuildMul(ctx->builder,
554 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
555 LLVMConstInt(ctx->i32, 4, false), "");
556 }
557
558 static LLVMValueRef
559 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
560 {
561 return LLVMBuildMul(ctx->builder,
562 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
563 LLVMConstInt(ctx->i32, 4, false), "");
564 }
565
566 static LLVMValueRef
567 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
568 {
569 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
570 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
571
572 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
573 }
574
575 static LLVMValueRef
576 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
577 {
578 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
579 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
580 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
581
582 return LLVMBuildAdd(ctx->builder, patch0_offset,
583 LLVMBuildMul(ctx->builder, patch_stride,
584 rel_patch_id, ""),
585 "");
586 }
587
588 static LLVMValueRef
589 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
590 {
591 LLVMValueRef patch0_patch_data_offset =
592 get_tcs_out_patch0_patch_data_offset(ctx);
593 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
594 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
595
596 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
597 LLVMBuildMul(ctx->builder, patch_stride,
598 rel_patch_id, ""),
599 "");
600 }
601
602 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
603 {
604 ud_info->sgpr_idx = *sgpr_idx;
605 ud_info->num_sgprs = num_sgprs;
606 ud_info->indirect = false;
607 ud_info->indirect_offset = 0;
608 *sgpr_idx += num_sgprs;
609 }
610
611 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
612 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
613 {
614 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
615 }
616
617
618 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
619 uint32_t indirect_offset)
620 {
621 ud_info->sgpr_idx = sgpr_idx;
622 ud_info->num_sgprs = num_sgprs;
623 ud_info->indirect = true;
624 ud_info->indirect_offset = indirect_offset;
625 }
626
627 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
628 {
629 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
630 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
631 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
632 "tess_lds");
633 }
634
635 struct user_sgpr_info {
636 bool need_ring_offsets;
637 uint8_t sgpr_count;
638 bool indirect_all_descriptor_sets;
639 };
640
641 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
642 struct user_sgpr_info *user_sgpr_info)
643 {
644 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
645
646 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
647 if (ctx->stage == MESA_SHADER_GEOMETRY ||
648 ctx->stage == MESA_SHADER_VERTEX ||
649 ctx->stage == MESA_SHADER_TESS_CTRL ||
650 ctx->stage == MESA_SHADER_TESS_EVAL ||
651 ctx->is_gs_copy_shader)
652 user_sgpr_info->need_ring_offsets = true;
653
654 if (ctx->stage == MESA_SHADER_FRAGMENT &&
655 ctx->shader_info->info.ps.needs_sample_positions)
656 user_sgpr_info->need_ring_offsets = true;
657
658 /* 2 user sgprs will nearly always be allocated for scratch/rings */
659 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
660 user_sgpr_info->sgpr_count += 2;
661 }
662
663 switch (ctx->stage) {
664 case MESA_SHADER_COMPUTE:
665 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
666 break;
667 case MESA_SHADER_FRAGMENT:
668 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
669 break;
670 case MESA_SHADER_VERTEX:
671 if (!ctx->is_gs_copy_shader) {
672 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
673 if (ctx->shader_info->info.vs.needs_draw_id) {
674 user_sgpr_info->sgpr_count += 3;
675 } else {
676 user_sgpr_info->sgpr_count += 2;
677 }
678 }
679 if (ctx->options->key.vs.as_ls)
680 user_sgpr_info->sgpr_count++;
681 break;
682 case MESA_SHADER_TESS_CTRL:
683 user_sgpr_info->sgpr_count += 4;
684 break;
685 case MESA_SHADER_TESS_EVAL:
686 user_sgpr_info->sgpr_count += 1;
687 break;
688 case MESA_SHADER_GEOMETRY:
689 user_sgpr_info->sgpr_count += 2;
690 break;
691 default:
692 break;
693 }
694
695 if (ctx->shader_info->info.needs_push_constants)
696 user_sgpr_info->sgpr_count += 2;
697
698 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
699 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
700 user_sgpr_info->sgpr_count += 2;
701 user_sgpr_info->indirect_all_descriptor_sets = true;
702 } else {
703 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
704 }
705 }
706
707 static void create_function(struct nir_to_llvm_context *ctx)
708 {
709 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
710 uint8_t user_sgpr_idx;
711 struct user_sgpr_info user_sgpr_info;
712 struct arg_info args = {};
713 LLVMValueRef desc_sets;
714
715 allocate_user_sgprs(ctx, &user_sgpr_info);
716 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
717 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
718 }
719
720 /* 1 for each descriptor set */
721 if (!user_sgpr_info.indirect_all_descriptor_sets) {
722 for (unsigned i = 0; i < num_sets; ++i) {
723 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
724 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
725 }
726 }
727 } else
728 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
729
730 if (ctx->shader_info->info.needs_push_constants) {
731 /* 1 for push constants and dynamic descriptors */
732 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
733 }
734
735 switch (ctx->stage) {
736 case MESA_SHADER_COMPUTE:
737 if (ctx->shader_info->info.cs.grid_components_used)
738 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
739 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
740 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
741 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
742 break;
743 case MESA_SHADER_VERTEX:
744 if (!ctx->is_gs_copy_shader) {
745 if (ctx->shader_info->info.vs.has_vertex_buffers)
746 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
747 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
748 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
749 if (ctx->shader_info->info.vs.needs_draw_id)
750 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
751 }
752 if (ctx->options->key.vs.as_es)
753 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
754 else if (ctx->options->key.vs.as_ls)
755 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
756 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
757 if (!ctx->is_gs_copy_shader) {
758 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
759 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
760 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
761 }
762 break;
763 case MESA_SHADER_TESS_CTRL:
764 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
765 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
766 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
767 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
768 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
769 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
770 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
771 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
772 break;
773 case MESA_SHADER_TESS_EVAL:
774 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
775 if (ctx->options->key.tes.as_es) {
776 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
777 add_sgpr_argument(&args, ctx->i32, NULL); //
778 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
779 } else {
780 add_sgpr_argument(&args, ctx->i32, NULL); //
781 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
782 }
783 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
784 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
785 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
786 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
787 break;
788 case MESA_SHADER_GEOMETRY:
789 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
790 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
791 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
792 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
793 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
796 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
797 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
798 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
799 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
800 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
801 break;
802 case MESA_SHADER_FRAGMENT:
803 if (ctx->shader_info->info.ps.needs_sample_positions)
804 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
805 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
806 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
807 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
808 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
809 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
810 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
811 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
812 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
813 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
814 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos x float */
815 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos y float */
816 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos z float */
817 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos w float */
818 add_vgpr_argument(&args, ctx->i32, &ctx->front_face); /* front face */
819 add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /* ancillary */
820 add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /* sample coverage */
821 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
822 break;
823 default:
824 unreachable("Shader stage not implemented");
825 }
826
827 ctx->main_function = create_llvm_function(
828 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
829 ctx->max_workgroup_size,
830 ctx->options->unsafe_math);
831 set_llvm_calling_convention(ctx->main_function, ctx->stage);
832
833
834 ctx->shader_info->num_input_vgprs = 0;
835 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
836 ctx->options->supports_spill ? 2 : 0;
837
838 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
839 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
840
841 if (ctx->stage != MESA_SHADER_FRAGMENT)
842 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
843
844 assign_arguments(ctx->main_function, &args);
845
846 user_sgpr_idx = 0;
847
848 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
849 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
850 if (ctx->options->supports_spill) {
851 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
852 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
853 NULL, 0, AC_FUNC_ATTR_READNONE);
854 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
855 const_array(ctx->v4i32, 16), "");
856 }
857 }
858
859 if (!user_sgpr_info.indirect_all_descriptor_sets) {
860 for (unsigned i = 0; i < num_sets; ++i) {
861 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
862 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
863 } else
864 ctx->descriptor_sets[i] = NULL;
865 }
866 } else {
867 uint32_t desc_sgpr_idx = user_sgpr_idx;
868 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
869
870 for (unsigned i = 0; i < num_sets; ++i) {
871 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
872 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
873 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
874
875 } else
876 ctx->descriptor_sets[i] = NULL;
877 }
878 ctx->shader_info->need_indirect_descriptor_sets = true;
879 }
880
881 if (ctx->shader_info->info.needs_push_constants) {
882 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
883 }
884
885 switch (ctx->stage) {
886 case MESA_SHADER_COMPUTE:
887 if (ctx->shader_info->info.cs.grid_components_used) {
888 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
889 }
890 break;
891 case MESA_SHADER_VERTEX:
892 if (!ctx->is_gs_copy_shader) {
893 if (ctx->shader_info->info.vs.has_vertex_buffers) {
894 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
895 }
896 unsigned vs_num = 2;
897 if (ctx->shader_info->info.vs.needs_draw_id)
898 vs_num++;
899
900 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
901 }
902 if (ctx->options->key.vs.as_ls) {
903 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
904 }
905 if (ctx->options->key.vs.as_ls)
906 declare_tess_lds(ctx);
907 break;
908 case MESA_SHADER_TESS_CTRL:
909 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
910 declare_tess_lds(ctx);
911 break;
912 case MESA_SHADER_TESS_EVAL:
913 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
914 break;
915 case MESA_SHADER_GEOMETRY:
916 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
917 break;
918 case MESA_SHADER_FRAGMENT:
919 if (ctx->shader_info->info.ps.needs_sample_positions) {
920 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
921 }
922 break;
923 default:
924 unreachable("Shader stage not implemented");
925 }
926 }
927
928 static void setup_types(struct nir_to_llvm_context *ctx)
929 {
930 LLVMValueRef args[4];
931
932 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
933 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
934 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
935 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
936 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
937 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
938 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
939 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
940 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
941 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
942 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
943 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
944 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
945 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
946 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
947
948 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
949 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
950 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
951 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
952 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
953 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
954
955 args[0] = ctx->f32zero;
956 args[1] = ctx->f32zero;
957 args[2] = ctx->f32zero;
958 args[3] = ctx->f32one;
959 ctx->v4f32empty = LLVMConstVector(args, 4);
960
961 ctx->uniform_md_kind =
962 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
963 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
964
965 args[0] = LLVMConstReal(ctx->f32, 2.5);
966 }
967
968 static int get_llvm_num_components(LLVMValueRef value)
969 {
970 LLVMTypeRef type = LLVMTypeOf(value);
971 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
972 ? LLVMGetVectorSize(type)
973 : 1;
974 return num_components;
975 }
976
977 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
978 LLVMValueRef value,
979 int index)
980 {
981 int count = get_llvm_num_components(value);
982
983 assert(index < count);
984 if (count == 1)
985 return value;
986
987 return LLVMBuildExtractElement(ac->builder, value,
988 LLVMConstInt(ac->i32, index, false), "");
989 }
990
991 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
992 LLVMValueRef value, unsigned count)
993 {
994 unsigned num_components = get_llvm_num_components(value);
995 if (count == num_components)
996 return value;
997
998 LLVMValueRef masks[] = {
999 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1000 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1001
1002 if (count == 1)
1003 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1004 "");
1005
1006 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1007 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1008 }
1009
1010 static void
1011 build_store_values_extended(struct ac_llvm_context *ac,
1012 LLVMValueRef *values,
1013 unsigned value_count,
1014 unsigned value_stride,
1015 LLVMValueRef vec)
1016 {
1017 LLVMBuilderRef builder = ac->builder;
1018 unsigned i;
1019
1020 if (value_count == 1) {
1021 LLVMBuildStore(builder, vec, values[0]);
1022 return;
1023 }
1024
1025 for (i = 0; i < value_count; i++) {
1026 LLVMValueRef ptr = values[i * value_stride];
1027 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1028 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1029 LLVMBuildStore(builder, value, ptr);
1030 }
1031 }
1032
1033 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1034 const nir_ssa_def *def)
1035 {
1036 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1037 if (def->num_components > 1) {
1038 type = LLVMVectorType(type, def->num_components);
1039 }
1040 return type;
1041 }
1042
1043 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1044 {
1045 assert(src.is_ssa);
1046 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1047 return (LLVMValueRef)entry->data;
1048 }
1049
1050
1051 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1052 const struct nir_block *b)
1053 {
1054 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1055 return (LLVMBasicBlockRef)entry->data;
1056 }
1057
1058 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1059 nir_alu_src src,
1060 unsigned num_components)
1061 {
1062 LLVMValueRef value = get_src(ctx, src.src);
1063 bool need_swizzle = false;
1064
1065 assert(value);
1066 LLVMTypeRef type = LLVMTypeOf(value);
1067 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1068 ? LLVMGetVectorSize(type)
1069 : 1;
1070
1071 for (unsigned i = 0; i < num_components; ++i) {
1072 assert(src.swizzle[i] < src_components);
1073 if (src.swizzle[i] != i)
1074 need_swizzle = true;
1075 }
1076
1077 if (need_swizzle || num_components != src_components) {
1078 LLVMValueRef masks[] = {
1079 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1080 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1081 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1082 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1083
1084 if (src_components > 1 && num_components == 1) {
1085 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1086 masks[0], "");
1087 } else if (src_components == 1 && num_components > 1) {
1088 LLVMValueRef values[] = {value, value, value, value};
1089 value = ac_build_gather_values(&ctx->ac, values, num_components);
1090 } else {
1091 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1092 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1093 swizzle, "");
1094 }
1095 }
1096 assert(!src.negate);
1097 assert(!src.abs);
1098 return value;
1099 }
1100
1101 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1102 LLVMIntPredicate pred, LLVMValueRef src0,
1103 LLVMValueRef src1)
1104 {
1105 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1106 return LLVMBuildSelect(ctx->builder, result,
1107 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1108 LLVMConstInt(ctx->i32, 0, false), "");
1109 }
1110
1111 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1112 LLVMRealPredicate pred, LLVMValueRef src0,
1113 LLVMValueRef src1)
1114 {
1115 LLVMValueRef result;
1116 src0 = to_float(ctx, src0);
1117 src1 = to_float(ctx, src1);
1118 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1119 return LLVMBuildSelect(ctx->builder, result,
1120 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1121 LLVMConstInt(ctx->i32, 0, false), "");
1122 }
1123
1124 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1125 const char *intrin,
1126 LLVMTypeRef result_type,
1127 LLVMValueRef src0)
1128 {
1129 char name[64];
1130 LLVMValueRef params[] = {
1131 to_float(ctx, src0),
1132 };
1133
1134 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1135 get_elem_bits(ctx, result_type));
1136 assert(length < sizeof(name));
1137 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1138 }
1139
1140 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1141 const char *intrin,
1142 LLVMTypeRef result_type,
1143 LLVMValueRef src0, LLVMValueRef src1)
1144 {
1145 char name[64];
1146 LLVMValueRef params[] = {
1147 to_float(ctx, src0),
1148 to_float(ctx, src1),
1149 };
1150
1151 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1152 get_elem_bits(ctx, result_type));
1153 assert(length < sizeof(name));
1154 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1155 }
1156
1157 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1158 const char *intrin,
1159 LLVMTypeRef result_type,
1160 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1161 {
1162 char name[64];
1163 LLVMValueRef params[] = {
1164 to_float(ctx, src0),
1165 to_float(ctx, src1),
1166 to_float(ctx, src2),
1167 };
1168
1169 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1170 get_elem_bits(ctx, result_type));
1171 assert(length < sizeof(name));
1172 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1173 }
1174
1175 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1176 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1177 {
1178 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1179 ctx->i32_0, "");
1180 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1181 }
1182
1183 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1184 LLVMValueRef src0)
1185 {
1186 LLVMValueRef params[2] = {
1187 src0,
1188
1189 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1190 * add special code to check for x=0. The reason is that
1191 * the LLVM behavior for x=0 is different from what we
1192 * need here.
1193 *
1194 * The hardware already implements the correct behavior.
1195 */
1196 LLVMConstInt(ctx->i1, 1, false),
1197 };
1198 return ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1199 }
1200
1201 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1202 LLVMValueRef src0)
1203 {
1204 return ac_build_imsb(ctx, src0, ctx->i32);
1205 }
1206
1207 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1208 LLVMValueRef src0)
1209 {
1210 return ac_build_umsb(ctx, src0, ctx->i32);
1211 }
1212
1213 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1214 LLVMIntPredicate pred,
1215 LLVMValueRef src0, LLVMValueRef src1)
1216 {
1217 return LLVMBuildSelect(ctx->builder,
1218 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1219 src0,
1220 src1, "");
1221
1222 }
1223 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1224 LLVMValueRef src0)
1225 {
1226 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1227 LLVMBuildNeg(ctx->builder, src0, ""));
1228 }
1229
1230 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1231 LLVMValueRef src0)
1232 {
1233 LLVMValueRef cmp, val;
1234
1235 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1236 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1237 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1238 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1239 return val;
1240 }
1241
1242 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1243 LLVMValueRef src0)
1244 {
1245 LLVMValueRef cmp, val;
1246
1247 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1248 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1249 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1250 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1251 return val;
1252 }
1253
1254 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1255 LLVMValueRef src0)
1256 {
1257 const char *intr = "llvm.floor.f32";
1258 LLVMValueRef fsrc0 = to_float(ctx, src0);
1259 LLVMValueRef params[] = {
1260 fsrc0,
1261 };
1262 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1263 ctx->f32, params, 1,
1264 AC_FUNC_ATTR_READNONE);
1265 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1266 }
1267
1268 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1269 const char *intrin,
1270 LLVMValueRef src0, LLVMValueRef src1)
1271 {
1272 LLVMTypeRef ret_type;
1273 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1274 LLVMValueRef res;
1275 LLVMValueRef params[] = { src0, src1 };
1276 ret_type = LLVMStructTypeInContext(ctx->context, types,
1277 2, true);
1278
1279 res = ac_build_intrinsic(ctx, intrin, ret_type,
1280 params, 2, AC_FUNC_ATTR_READNONE);
1281
1282 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1283 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1284 return res;
1285 }
1286
1287 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1288 LLVMValueRef src0)
1289 {
1290 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1291 }
1292
1293 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1294 LLVMValueRef src0)
1295 {
1296 src0 = to_float(ctx, src0);
1297 return LLVMBuildSExt(ctx->builder,
1298 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1299 ctx->i32, "");
1300 }
1301
1302 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1303 LLVMValueRef src0)
1304 {
1305 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1306 }
1307
1308 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1309 LLVMValueRef src0)
1310 {
1311 return LLVMBuildSExt(ctx->builder,
1312 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1313 ctx->i32, "");
1314 }
1315
1316 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1317 LLVMValueRef src0)
1318 {
1319 LLVMValueRef result;
1320 LLVMValueRef cond;
1321
1322 src0 = to_float(&ctx->ac, src0);
1323 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1324
1325 /* TODO SI/CIK options here */
1326 if (ctx->options->chip_class >= VI) {
1327 LLVMValueRef args[2];
1328 /* Check if the result is a denormal - and flush to 0 if so. */
1329 args[0] = result;
1330 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1331 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1332 }
1333
1334 /* need to convert back up to f32 */
1335 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1336
1337 if (ctx->options->chip_class >= VI)
1338 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1339
1340 return result;
1341 }
1342
1343 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1344 LLVMValueRef src0, LLVMValueRef src1)
1345 {
1346 LLVMValueRef dst64, result;
1347 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1348 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1349
1350 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1351 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1352 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1353 return result;
1354 }
1355
1356 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0, LLVMValueRef src1)
1358 {
1359 LLVMValueRef dst64, result;
1360 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1361 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1362
1363 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1364 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1365 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1366 return result;
1367 }
1368
1369 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1370 bool is_signed,
1371 const LLVMValueRef srcs[3])
1372 {
1373 LLVMValueRef result;
1374 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1375
1376 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1377 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1378 return result;
1379 }
1380
1381 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1382 LLVMValueRef src0, LLVMValueRef src1,
1383 LLVMValueRef src2, LLVMValueRef src3)
1384 {
1385 LLVMValueRef bfi_args[3], result;
1386
1387 bfi_args[0] = LLVMBuildShl(ctx->builder,
1388 LLVMBuildSub(ctx->builder,
1389 LLVMBuildShl(ctx->builder,
1390 ctx->i32_1,
1391 src3, ""),
1392 ctx->i32_1, ""),
1393 src2, "");
1394 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1395 bfi_args[2] = src0;
1396
1397 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1398
1399 /* Calculate:
1400 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1401 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1402 */
1403 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1404 LLVMBuildAnd(ctx->builder, bfi_args[0],
1405 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1406
1407 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1408 return result;
1409 }
1410
1411 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1412 LLVMValueRef src0)
1413 {
1414 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1415 int i;
1416 LLVMValueRef comp[2];
1417
1418 src0 = to_float(ctx, src0);
1419 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1420 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1421 for (i = 0; i < 2; i++) {
1422 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1423 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1424 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1425 }
1426
1427 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1428 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1429
1430 return comp[0];
1431 }
1432
1433 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1434 LLVMValueRef src0)
1435 {
1436 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1437 LLVMValueRef temps[2], result, val;
1438 int i;
1439
1440 for (i = 0; i < 2; i++) {
1441 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1442 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1443 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1444 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1445 }
1446
1447 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1448 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1449 ctx->i32_0, "");
1450 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1451 ctx->i32_1, "");
1452 return result;
1453 }
1454
1455 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1456 nir_op op,
1457 LLVMValueRef src0)
1458 {
1459 unsigned mask;
1460 int idx;
1461 LLVMValueRef result;
1462
1463 if (!ctx->lds && !ctx->has_ds_bpermute)
1464 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1465 LLVMArrayType(ctx->i32, 64),
1466 "ddxy_lds", LOCAL_ADDR_SPACE);
1467
1468 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1469 mask = AC_TID_MASK_LEFT;
1470 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1471 mask = AC_TID_MASK_TOP;
1472 else
1473 mask = AC_TID_MASK_TOP_LEFT;
1474
1475 /* for DDX we want to next X pixel, DDY next Y pixel. */
1476 if (op == nir_op_fddx_fine ||
1477 op == nir_op_fddx_coarse ||
1478 op == nir_op_fddx)
1479 idx = 1;
1480 else
1481 idx = 2;
1482
1483 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1484 mask, idx, ctx->lds,
1485 src0);
1486 return result;
1487 }
1488
1489 /*
1490 * this takes an I,J coordinate pair,
1491 * and works out the X and Y derivatives.
1492 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1493 */
1494 static LLVMValueRef emit_ddxy_interp(
1495 struct nir_to_llvm_context *ctx,
1496 LLVMValueRef interp_ij)
1497 {
1498 LLVMValueRef result[4], a;
1499 unsigned i;
1500
1501 for (i = 0; i < 2; i++) {
1502 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1503 LLVMConstInt(ctx->i32, i, false), "");
1504 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1505 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1506 }
1507 return ac_build_gather_values(&ctx->ac, result, 4);
1508 }
1509
1510 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1511 {
1512 LLVMValueRef src[4], result = NULL;
1513 unsigned num_components = instr->dest.dest.ssa.num_components;
1514 unsigned src_components;
1515 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1516
1517 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1518 switch (instr->op) {
1519 case nir_op_vec2:
1520 case nir_op_vec3:
1521 case nir_op_vec4:
1522 src_components = 1;
1523 break;
1524 case nir_op_pack_half_2x16:
1525 src_components = 2;
1526 break;
1527 case nir_op_unpack_half_2x16:
1528 src_components = 1;
1529 break;
1530 default:
1531 src_components = num_components;
1532 break;
1533 }
1534 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1535 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1536
1537 switch (instr->op) {
1538 case nir_op_fmov:
1539 case nir_op_imov:
1540 result = src[0];
1541 break;
1542 case nir_op_fneg:
1543 src[0] = to_float(&ctx->ac, src[0]);
1544 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1545 break;
1546 case nir_op_ineg:
1547 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1548 break;
1549 case nir_op_inot:
1550 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1551 break;
1552 case nir_op_iadd:
1553 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1554 break;
1555 case nir_op_fadd:
1556 src[0] = to_float(&ctx->ac, src[0]);
1557 src[1] = to_float(&ctx->ac, src[1]);
1558 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1559 break;
1560 case nir_op_fsub:
1561 src[0] = to_float(&ctx->ac, src[0]);
1562 src[1] = to_float(&ctx->ac, src[1]);
1563 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1564 break;
1565 case nir_op_isub:
1566 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1567 break;
1568 case nir_op_imul:
1569 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1570 break;
1571 case nir_op_imod:
1572 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1573 break;
1574 case nir_op_umod:
1575 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1576 break;
1577 case nir_op_fmod:
1578 src[0] = to_float(&ctx->ac, src[0]);
1579 src[1] = to_float(&ctx->ac, src[1]);
1580 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1581 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1582 to_float_type(&ctx->ac, def_type), result);
1583 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1584 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1585 break;
1586 case nir_op_frem:
1587 src[0] = to_float(&ctx->ac, src[0]);
1588 src[1] = to_float(&ctx->ac, src[1]);
1589 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1590 break;
1591 case nir_op_irem:
1592 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1593 break;
1594 case nir_op_idiv:
1595 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1596 break;
1597 case nir_op_udiv:
1598 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1599 break;
1600 case nir_op_fmul:
1601 src[0] = to_float(&ctx->ac, src[0]);
1602 src[1] = to_float(&ctx->ac, src[1]);
1603 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1604 break;
1605 case nir_op_fdiv:
1606 src[0] = to_float(&ctx->ac, src[0]);
1607 src[1] = to_float(&ctx->ac, src[1]);
1608 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1609 break;
1610 case nir_op_frcp:
1611 src[0] = to_float(&ctx->ac, src[0]);
1612 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1613 break;
1614 case nir_op_iand:
1615 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1616 break;
1617 case nir_op_ior:
1618 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1619 break;
1620 case nir_op_ixor:
1621 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1622 break;
1623 case nir_op_ishl:
1624 result = LLVMBuildShl(ctx->ac.builder, src[0],
1625 LLVMBuildZExt(ctx->ac.builder, src[1],
1626 LLVMTypeOf(src[0]), ""),
1627 "");
1628 break;
1629 case nir_op_ishr:
1630 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1631 LLVMBuildZExt(ctx->ac.builder, src[1],
1632 LLVMTypeOf(src[0]), ""),
1633 "");
1634 break;
1635 case nir_op_ushr:
1636 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1637 LLVMBuildZExt(ctx->ac.builder, src[1],
1638 LLVMTypeOf(src[0]), ""),
1639 "");
1640 break;
1641 case nir_op_ilt:
1642 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1643 break;
1644 case nir_op_ine:
1645 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1646 break;
1647 case nir_op_ieq:
1648 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1649 break;
1650 case nir_op_ige:
1651 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1652 break;
1653 case nir_op_ult:
1654 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1655 break;
1656 case nir_op_uge:
1657 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1658 break;
1659 case nir_op_feq:
1660 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1661 break;
1662 case nir_op_fne:
1663 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1664 break;
1665 case nir_op_flt:
1666 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1667 break;
1668 case nir_op_fge:
1669 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1670 break;
1671 case nir_op_fabs:
1672 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1673 to_float_type(&ctx->ac, def_type), src[0]);
1674 break;
1675 case nir_op_iabs:
1676 result = emit_iabs(&ctx->ac, src[0]);
1677 break;
1678 case nir_op_imax:
1679 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1680 break;
1681 case nir_op_imin:
1682 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1683 break;
1684 case nir_op_umax:
1685 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1686 break;
1687 case nir_op_umin:
1688 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1689 break;
1690 case nir_op_isign:
1691 result = emit_isign(&ctx->ac, src[0]);
1692 break;
1693 case nir_op_fsign:
1694 src[0] = to_float(&ctx->ac, src[0]);
1695 result = emit_fsign(&ctx->ac, src[0]);
1696 break;
1697 case nir_op_ffloor:
1698 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1699 to_float_type(&ctx->ac, def_type), src[0]);
1700 break;
1701 case nir_op_ftrunc:
1702 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1703 to_float_type(&ctx->ac, def_type), src[0]);
1704 break;
1705 case nir_op_fceil:
1706 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1707 to_float_type(&ctx->ac, def_type), src[0]);
1708 break;
1709 case nir_op_fround_even:
1710 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1711 to_float_type(&ctx->ac, def_type),src[0]);
1712 break;
1713 case nir_op_ffract:
1714 result = emit_ffract(&ctx->ac, src[0]);
1715 break;
1716 case nir_op_fsin:
1717 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1718 to_float_type(&ctx->ac, def_type), src[0]);
1719 break;
1720 case nir_op_fcos:
1721 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1722 to_float_type(&ctx->ac, def_type), src[0]);
1723 break;
1724 case nir_op_fsqrt:
1725 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1726 to_float_type(&ctx->ac, def_type), src[0]);
1727 break;
1728 case nir_op_fexp2:
1729 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1730 to_float_type(&ctx->ac, def_type), src[0]);
1731 break;
1732 case nir_op_flog2:
1733 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1734 to_float_type(&ctx->ac, def_type), src[0]);
1735 break;
1736 case nir_op_frsq:
1737 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1738 to_float_type(&ctx->ac, def_type), src[0]);
1739 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1740 break;
1741 case nir_op_fpow:
1742 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1743 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1744 break;
1745 case nir_op_fmax:
1746 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1747 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1748 if (instr->dest.dest.ssa.bit_size == 32)
1749 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1750 to_float_type(&ctx->ac, def_type),
1751 result);
1752 break;
1753 case nir_op_fmin:
1754 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1755 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1756 if (instr->dest.dest.ssa.bit_size == 32)
1757 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1758 to_float_type(&ctx->ac, def_type),
1759 result);
1760 break;
1761 case nir_op_ffma:
1762 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1763 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1764 break;
1765 case nir_op_ibitfield_extract:
1766 result = emit_bitfield_extract(&ctx->ac, true, src);
1767 break;
1768 case nir_op_ubitfield_extract:
1769 result = emit_bitfield_extract(&ctx->ac, false, src);
1770 break;
1771 case nir_op_bitfield_insert:
1772 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1773 break;
1774 case nir_op_bitfield_reverse:
1775 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1776 break;
1777 case nir_op_bit_count:
1778 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1779 break;
1780 case nir_op_vec2:
1781 case nir_op_vec3:
1782 case nir_op_vec4:
1783 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1784 src[i] = to_integer(&ctx->ac, src[i]);
1785 result = ac_build_gather_values(&ctx->ac, src, num_components);
1786 break;
1787 case nir_op_f2i32:
1788 case nir_op_f2i64:
1789 src[0] = to_float(&ctx->ac, src[0]);
1790 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1791 break;
1792 case nir_op_f2u32:
1793 case nir_op_f2u64:
1794 src[0] = to_float(&ctx->ac, src[0]);
1795 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1796 break;
1797 case nir_op_i2f32:
1798 case nir_op_i2f64:
1799 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1800 break;
1801 case nir_op_u2f32:
1802 case nir_op_u2f64:
1803 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1804 break;
1805 case nir_op_f2f64:
1806 result = LLVMBuildFPExt(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1807 break;
1808 case nir_op_f2f32:
1809 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1810 break;
1811 case nir_op_u2u32:
1812 case nir_op_u2u64:
1813 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1814 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1815 else
1816 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1817 break;
1818 case nir_op_i2i32:
1819 case nir_op_i2i64:
1820 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1821 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1822 else
1823 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1824 break;
1825 case nir_op_bcsel:
1826 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1827 break;
1828 case nir_op_find_lsb:
1829 result = emit_find_lsb(&ctx->ac, src[0]);
1830 break;
1831 case nir_op_ufind_msb:
1832 result = emit_ufind_msb(&ctx->ac, src[0]);
1833 break;
1834 case nir_op_ifind_msb:
1835 result = emit_ifind_msb(&ctx->ac, src[0]);
1836 break;
1837 case nir_op_uadd_carry:
1838 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1839 break;
1840 case nir_op_usub_borrow:
1841 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1842 break;
1843 case nir_op_b2f:
1844 result = emit_b2f(&ctx->ac, src[0]);
1845 break;
1846 case nir_op_f2b:
1847 result = emit_f2b(&ctx->ac, src[0]);
1848 break;
1849 case nir_op_b2i:
1850 result = emit_b2i(&ctx->ac, src[0]);
1851 break;
1852 case nir_op_i2b:
1853 result = emit_i2b(&ctx->ac, src[0]);
1854 break;
1855 case nir_op_fquantize2f16:
1856 result = emit_f2f16(ctx->nctx, src[0]);
1857 break;
1858 case nir_op_umul_high:
1859 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1860 break;
1861 case nir_op_imul_high:
1862 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1863 break;
1864 case nir_op_pack_half_2x16:
1865 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1866 break;
1867 case nir_op_unpack_half_2x16:
1868 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1869 break;
1870 case nir_op_fddx:
1871 case nir_op_fddy:
1872 case nir_op_fddx_fine:
1873 case nir_op_fddy_fine:
1874 case nir_op_fddx_coarse:
1875 case nir_op_fddy_coarse:
1876 result = emit_ddxy(ctx->nctx, instr->op, src[0]);
1877 break;
1878
1879 case nir_op_unpack_64_2x32_split_x: {
1880 assert(instr->src[0].src.ssa->num_components == 1);
1881 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1882 LLVMVectorType(ctx->ac.i32, 2),
1883 "");
1884 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1885 ctx->ac.i32_0, "");
1886 break;
1887 }
1888
1889 case nir_op_unpack_64_2x32_split_y: {
1890 assert(instr->src[0].src.ssa->num_components == 1);
1891 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1892 LLVMVectorType(ctx->ac.i32, 2),
1893 "");
1894 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1895 ctx->ac.i32_0, "");
1896 break;
1897 }
1898
1899 case nir_op_pack_64_2x32_split: {
1900 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1901 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1902 src[0], ctx->ac.i32_0, "");
1903 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1904 src[1], ctx->ac.i32_1, "");
1905 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1906 break;
1907 }
1908
1909 default:
1910 fprintf(stderr, "Unknown NIR alu instr: ");
1911 nir_print_instr(&instr->instr, stderr);
1912 fprintf(stderr, "\n");
1913 abort();
1914 }
1915
1916 if (result) {
1917 assert(instr->dest.dest.is_ssa);
1918 result = to_integer(&ctx->ac, result);
1919 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1920 result);
1921 }
1922 }
1923
1924 static void visit_load_const(struct ac_nir_context *ctx,
1925 const nir_load_const_instr *instr)
1926 {
1927 LLVMValueRef values[4], value = NULL;
1928 LLVMTypeRef element_type =
1929 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1930
1931 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1932 switch (instr->def.bit_size) {
1933 case 32:
1934 values[i] = LLVMConstInt(element_type,
1935 instr->value.u32[i], false);
1936 break;
1937 case 64:
1938 values[i] = LLVMConstInt(element_type,
1939 instr->value.u64[i], false);
1940 break;
1941 default:
1942 fprintf(stderr,
1943 "unsupported nir load_const bit_size: %d\n",
1944 instr->def.bit_size);
1945 abort();
1946 }
1947 }
1948 if (instr->def.num_components > 1) {
1949 value = LLVMConstVector(values, instr->def.num_components);
1950 } else
1951 value = values[0];
1952
1953 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1954 }
1955
1956 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1957 LLVMTypeRef type)
1958 {
1959 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1960 return LLVMBuildBitCast(ctx->builder, ptr,
1961 LLVMPointerType(type, addr_space), "");
1962 }
1963
1964 static LLVMValueRef
1965 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1966 {
1967 LLVMValueRef size =
1968 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1969 LLVMConstInt(ctx->ac.i32, 2, false), "");
1970
1971 /* VI only */
1972 if (ctx->abi->chip_class >= VI && in_elements) {
1973 /* On VI, the descriptor contains the size in bytes,
1974 * but TXQ must return the size in elements.
1975 * The stride is always non-zero for resources using TXQ.
1976 */
1977 LLVMValueRef stride =
1978 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1979 LLVMConstInt(ctx->ac.i32, 1, false), "");
1980 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1981 LLVMConstInt(ctx->ac.i32, 16, false), "");
1982 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1983 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1984
1985 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1986 }
1987 return size;
1988 }
1989
1990 /**
1991 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1992 * intrinsic names).
1993 */
1994 static void build_int_type_name(
1995 LLVMTypeRef type,
1996 char *buf, unsigned bufsize)
1997 {
1998 assert(bufsize >= 6);
1999
2000 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2001 snprintf(buf, bufsize, "v%ui32",
2002 LLVMGetVectorSize(type));
2003 else
2004 strcpy(buf, "i32");
2005 }
2006
2007 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2008 struct ac_image_args *args,
2009 const nir_tex_instr *instr)
2010 {
2011 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2012 LLVMValueRef coord = args->addr;
2013 LLVMValueRef half_texel[2];
2014 LLVMValueRef compare_cube_wa;
2015 LLVMValueRef result;
2016 int c;
2017 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2018
2019 //TODO Rect
2020 {
2021 struct ac_image_args txq_args = { 0 };
2022
2023 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2024 txq_args.opcode = ac_image_get_resinfo;
2025 txq_args.dmask = 0xf;
2026 txq_args.addr = ctx->i32_0;
2027 txq_args.resource = args->resource;
2028 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2029
2030 for (c = 0; c < 2; c++) {
2031 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2032 LLVMConstInt(ctx->i32, c, false), "");
2033 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2034 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2035 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2036 LLVMConstReal(ctx->f32, -0.5), "");
2037 }
2038 }
2039
2040 LLVMValueRef orig_coords = args->addr;
2041
2042 for (c = 0; c < 2; c++) {
2043 LLVMValueRef tmp;
2044 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2045 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2046 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2047 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2048 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2049 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2050 }
2051
2052
2053 /*
2054 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2055 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2056 * workaround by sampling using a scaled type and converting.
2057 * This is taken from amdgpu-pro shaders.
2058 */
2059 /* NOTE this produces some ugly code compared to amdgpu-pro,
2060 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2061 * and then reads them back. -pro generates two selects,
2062 * one s_cmp for the descriptor rewriting
2063 * one v_cmp for the coordinate and result changes.
2064 */
2065 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2066 LLVMValueRef tmp, tmp2;
2067
2068 /* workaround 8/8/8/8 uint/sint cube gather bug */
2069 /* first detect it then change to a scaled read and f2i */
2070 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2071 tmp2 = tmp;
2072
2073 /* extract the DATA_FORMAT */
2074 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2075 LLVMConstInt(ctx->i32, 6, false), false);
2076
2077 /* is the DATA_FORMAT == 8_8_8_8 */
2078 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2079
2080 if (stype == GLSL_TYPE_UINT)
2081 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2082 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2083 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2084 else
2085 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2086 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2087 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2088
2089 /* replace the NUM FORMAT in the descriptor */
2090 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2091 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2092
2093 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2094
2095 /* don't modify the coordinates for this case */
2096 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2097 }
2098 args->addr = coord;
2099 result = ac_build_image_opcode(ctx, args);
2100
2101 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2102 LLVMValueRef tmp, tmp2;
2103
2104 /* if the cube workaround is in place, f2i the result. */
2105 for (c = 0; c < 4; c++) {
2106 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2107 if (stype == GLSL_TYPE_UINT)
2108 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2109 else
2110 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2111 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2112 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2113 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2114 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2115 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2116 }
2117 }
2118 return result;
2119 }
2120
2121 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2122 const nir_tex_instr *instr,
2123 bool lod_is_zero,
2124 struct ac_image_args *args)
2125 {
2126 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2127 return ac_build_buffer_load_format(&ctx->ac,
2128 args->resource,
2129 args->addr,
2130 LLVMConstInt(ctx->ac.i32, 0, false),
2131 true);
2132 }
2133
2134 args->opcode = ac_image_sample;
2135 args->compare = instr->is_shadow;
2136
2137 switch (instr->op) {
2138 case nir_texop_txf:
2139 case nir_texop_txf_ms:
2140 case nir_texop_samples_identical:
2141 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2142 args->compare = false;
2143 args->offset = false;
2144 break;
2145 case nir_texop_txb:
2146 args->bias = true;
2147 break;
2148 case nir_texop_txl:
2149 if (lod_is_zero)
2150 args->level_zero = true;
2151 else
2152 args->lod = true;
2153 break;
2154 case nir_texop_txs:
2155 case nir_texop_query_levels:
2156 args->opcode = ac_image_get_resinfo;
2157 break;
2158 case nir_texop_tex:
2159 if (ctx->stage != MESA_SHADER_FRAGMENT)
2160 args->level_zero = true;
2161 break;
2162 case nir_texop_txd:
2163 args->deriv = true;
2164 break;
2165 case nir_texop_tg4:
2166 args->opcode = ac_image_gather4;
2167 args->level_zero = true;
2168 break;
2169 case nir_texop_lod:
2170 args->opcode = ac_image_get_lod;
2171 args->compare = false;
2172 args->offset = false;
2173 break;
2174 default:
2175 break;
2176 }
2177
2178 if (instr->op == nir_texop_tg4) {
2179 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2180 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2181 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2182 }
2183 }
2184 return ac_build_image_opcode(&ctx->ac, args);
2185 }
2186
2187 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2188 nir_intrinsic_instr *instr)
2189 {
2190 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2191 unsigned desc_set = nir_intrinsic_desc_set(instr);
2192 unsigned binding = nir_intrinsic_binding(instr);
2193 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2194 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2195 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2196 unsigned base_offset = layout->binding[binding].offset;
2197 LLVMValueRef offset, stride;
2198
2199 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2200 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2201 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2202 layout->binding[binding].dynamic_offset_offset;
2203 desc_ptr = ctx->push_constants;
2204 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2205 stride = LLVMConstInt(ctx->i32, 16, false);
2206 } else
2207 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2208
2209 offset = LLVMConstInt(ctx->i32, base_offset, false);
2210 index = LLVMBuildMul(ctx->builder, index, stride, "");
2211 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2212
2213 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2214 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2215 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2216
2217 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2218 }
2219
2220 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2221 nir_intrinsic_instr *instr)
2222 {
2223 LLVMValueRef ptr, addr;
2224
2225 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2226 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2227
2228 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2229 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2230
2231 return LLVMBuildLoad(ctx->builder, ptr, "");
2232 }
2233
2234 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2235 const nir_intrinsic_instr *instr)
2236 {
2237 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2238
2239 return get_buffer_size(ctx, desc, false);
2240 }
2241 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2242 nir_intrinsic_instr *instr)
2243 {
2244 const char *store_name;
2245 LLVMValueRef src_data = get_src(ctx->nir, instr->src[0]);
2246 LLVMTypeRef data_type = ctx->f32;
2247 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2248 int components_32bit = elem_size_mult * instr->num_components;
2249 unsigned writemask = nir_intrinsic_write_mask(instr);
2250 LLVMValueRef base_data, base_offset;
2251 LLVMValueRef params[6];
2252
2253 if (ctx->stage == MESA_SHADER_FRAGMENT)
2254 ctx->shader_info->fs.writes_memory = true;
2255
2256 params[1] = get_src(ctx->nir, instr->src[1]);
2257 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2258 params[4] = ctx->i1false; /* glc */
2259 params[5] = ctx->i1false; /* slc */
2260
2261 if (components_32bit > 1)
2262 data_type = LLVMVectorType(ctx->f32, components_32bit);
2263
2264 base_data = to_float(&ctx->ac, src_data);
2265 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2266 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2267 data_type, "");
2268 base_offset = get_src(ctx->nir, instr->src[2]); /* voffset */
2269 while (writemask) {
2270 int start, count;
2271 LLVMValueRef data;
2272 LLVMValueRef offset;
2273 LLVMValueRef tmp;
2274 u_bit_scan_consecutive_range(&writemask, &start, &count);
2275
2276 /* Due to an LLVM limitation, split 3-element writes
2277 * into a 2-element and a 1-element write. */
2278 if (count == 3) {
2279 writemask |= 1 << (start + 2);
2280 count = 2;
2281 }
2282
2283 start *= elem_size_mult;
2284 count *= elem_size_mult;
2285
2286 if (count > 4) {
2287 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2288 count = 4;
2289 }
2290
2291 if (count == 4) {
2292 store_name = "llvm.amdgcn.buffer.store.v4f32";
2293 data = base_data;
2294 } else if (count == 2) {
2295 tmp = LLVMBuildExtractElement(ctx->builder,
2296 base_data, LLVMConstInt(ctx->i32, start, false), "");
2297 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2298 ctx->i32zero, "");
2299
2300 tmp = LLVMBuildExtractElement(ctx->builder,
2301 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2302 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2303 ctx->i32one, "");
2304 store_name = "llvm.amdgcn.buffer.store.v2f32";
2305
2306 } else {
2307 assert(count == 1);
2308 if (get_llvm_num_components(base_data) > 1)
2309 data = LLVMBuildExtractElement(ctx->builder, base_data,
2310 LLVMConstInt(ctx->i32, start, false), "");
2311 else
2312 data = base_data;
2313 store_name = "llvm.amdgcn.buffer.store.f32";
2314 }
2315
2316 offset = base_offset;
2317 if (start != 0) {
2318 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2319 }
2320 params[0] = data;
2321 params[3] = offset;
2322 ac_build_intrinsic(&ctx->ac, store_name,
2323 ctx->voidt, params, 6, 0);
2324 }
2325 }
2326
2327 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2328 const nir_intrinsic_instr *instr)
2329 {
2330 const char *name;
2331 LLVMValueRef params[6];
2332 int arg_count = 0;
2333 if (ctx->stage == MESA_SHADER_FRAGMENT)
2334 ctx->shader_info->fs.writes_memory = true;
2335
2336 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2337 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx->nir, instr->src[3]), 0);
2338 }
2339 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx->nir, instr->src[2]), 0);
2340 params[arg_count++] = get_src(ctx->nir, instr->src[0]);
2341 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2342 params[arg_count++] = get_src(ctx->nir, instr->src[1]); /* voffset */
2343 params[arg_count++] = ctx->i1false; /* slc */
2344
2345 switch (instr->intrinsic) {
2346 case nir_intrinsic_ssbo_atomic_add:
2347 name = "llvm.amdgcn.buffer.atomic.add";
2348 break;
2349 case nir_intrinsic_ssbo_atomic_imin:
2350 name = "llvm.amdgcn.buffer.atomic.smin";
2351 break;
2352 case nir_intrinsic_ssbo_atomic_umin:
2353 name = "llvm.amdgcn.buffer.atomic.umin";
2354 break;
2355 case nir_intrinsic_ssbo_atomic_imax:
2356 name = "llvm.amdgcn.buffer.atomic.smax";
2357 break;
2358 case nir_intrinsic_ssbo_atomic_umax:
2359 name = "llvm.amdgcn.buffer.atomic.umax";
2360 break;
2361 case nir_intrinsic_ssbo_atomic_and:
2362 name = "llvm.amdgcn.buffer.atomic.and";
2363 break;
2364 case nir_intrinsic_ssbo_atomic_or:
2365 name = "llvm.amdgcn.buffer.atomic.or";
2366 break;
2367 case nir_intrinsic_ssbo_atomic_xor:
2368 name = "llvm.amdgcn.buffer.atomic.xor";
2369 break;
2370 case nir_intrinsic_ssbo_atomic_exchange:
2371 name = "llvm.amdgcn.buffer.atomic.swap";
2372 break;
2373 case nir_intrinsic_ssbo_atomic_comp_swap:
2374 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2375 break;
2376 default:
2377 abort();
2378 }
2379
2380 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2381 }
2382
2383 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2384 const nir_intrinsic_instr *instr)
2385 {
2386 LLVMValueRef results[2];
2387 int load_components;
2388 int num_components = instr->num_components;
2389 if (instr->dest.ssa.bit_size == 64)
2390 num_components *= 2;
2391
2392 for (int i = 0; i < num_components; i += load_components) {
2393 load_components = MIN2(num_components - i, 4);
2394 const char *load_name;
2395 LLVMTypeRef data_type = ctx->f32;
2396 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2397 offset = LLVMBuildAdd(ctx->builder, get_src(ctx->nir, instr->src[1]), offset, "");
2398
2399 if (load_components == 3)
2400 data_type = LLVMVectorType(ctx->f32, 4);
2401 else if (load_components > 1)
2402 data_type = LLVMVectorType(ctx->f32, load_components);
2403
2404 if (load_components >= 3)
2405 load_name = "llvm.amdgcn.buffer.load.v4f32";
2406 else if (load_components == 2)
2407 load_name = "llvm.amdgcn.buffer.load.v2f32";
2408 else if (load_components == 1)
2409 load_name = "llvm.amdgcn.buffer.load.f32";
2410 else
2411 unreachable("unhandled number of components");
2412
2413 LLVMValueRef params[] = {
2414 get_src(ctx->nir, instr->src[0]),
2415 LLVMConstInt(ctx->i32, 0, false),
2416 offset,
2417 ctx->i1false,
2418 ctx->i1false,
2419 };
2420
2421 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2422
2423 }
2424
2425 LLVMValueRef ret = results[0];
2426 if (num_components > 4 || num_components == 3) {
2427 LLVMValueRef masks[] = {
2428 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2429 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2430 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2431 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2432 };
2433
2434 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2435 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2436 results[num_components > 4 ? 1 : 0], swizzle, "");
2437 }
2438
2439 return LLVMBuildBitCast(ctx->builder, ret,
2440 get_def_type(ctx->nir, &instr->dest.ssa), "");
2441 }
2442
2443 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2444 const nir_intrinsic_instr *instr)
2445 {
2446 LLVMValueRef results[8], ret;
2447 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2448 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2449 int num_components = instr->num_components;
2450
2451 if (ctx->abi->load_ubo)
2452 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2453
2454 if (instr->dest.ssa.bit_size == 64)
2455 num_components *= 2;
2456
2457 for (unsigned i = 0; i < num_components; ++i) {
2458 LLVMValueRef params[] = {
2459 rsrc,
2460 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2461 offset, "")
2462 };
2463 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2464 params, 2,
2465 AC_FUNC_ATTR_READNONE |
2466 AC_FUNC_ATTR_LEGACY);
2467 }
2468
2469
2470 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2471 return LLVMBuildBitCast(ctx->ac.builder, ret,
2472 get_def_type(ctx, &instr->dest.ssa), "");
2473 }
2474
2475 static void
2476 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2477 bool vs_in, unsigned *vertex_index_out,
2478 LLVMValueRef *vertex_index_ref,
2479 unsigned *const_out, LLVMValueRef *indir_out)
2480 {
2481 unsigned const_offset = 0;
2482 nir_deref *tail = &deref->deref;
2483 LLVMValueRef offset = NULL;
2484
2485 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2486 tail = tail->child;
2487 nir_deref_array *deref_array = nir_deref_as_array(tail);
2488 if (vertex_index_out)
2489 *vertex_index_out = deref_array->base_offset;
2490
2491 if (vertex_index_ref) {
2492 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2493 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2494 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2495 }
2496 *vertex_index_ref = vtx;
2497 }
2498 }
2499
2500 if (deref->var->data.compact) {
2501 assert(tail->child->deref_type == nir_deref_type_array);
2502 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2503 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2504 /* We always lower indirect dereferences for "compact" array vars. */
2505 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2506
2507 const_offset = deref_array->base_offset;
2508 goto out;
2509 }
2510
2511 while (tail->child != NULL) {
2512 const struct glsl_type *parent_type = tail->type;
2513 tail = tail->child;
2514
2515 if (tail->deref_type == nir_deref_type_array) {
2516 nir_deref_array *deref_array = nir_deref_as_array(tail);
2517 LLVMValueRef index, stride, local_offset;
2518 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2519
2520 const_offset += size * deref_array->base_offset;
2521 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2522 continue;
2523
2524 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2525 index = get_src(ctx, deref_array->indirect);
2526 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2527 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2528
2529 if (offset)
2530 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2531 else
2532 offset = local_offset;
2533 } else if (tail->deref_type == nir_deref_type_struct) {
2534 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2535
2536 for (unsigned i = 0; i < deref_struct->index; i++) {
2537 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2538 const_offset += glsl_count_attribute_slots(ft, vs_in);
2539 }
2540 } else
2541 unreachable("unsupported deref type");
2542
2543 }
2544 out:
2545 if (const_offset && offset)
2546 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2547 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2548 "");
2549
2550 *const_out = const_offset;
2551 *indir_out = offset;
2552 }
2553
2554 static LLVMValueRef
2555 lds_load(struct nir_to_llvm_context *ctx,
2556 LLVMValueRef dw_addr)
2557 {
2558 LLVMValueRef value;
2559 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2560 return value;
2561 }
2562
2563 static void
2564 lds_store(struct nir_to_llvm_context *ctx,
2565 LLVMValueRef dw_addr, LLVMValueRef value)
2566 {
2567 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2568 ac_build_indexed_store(&ctx->ac, ctx->lds,
2569 dw_addr, value);
2570 }
2571
2572 /* The offchip buffer layout for TCS->TES is
2573 *
2574 * - attribute 0 of patch 0 vertex 0
2575 * - attribute 0 of patch 0 vertex 1
2576 * - attribute 0 of patch 0 vertex 2
2577 * ...
2578 * - attribute 0 of patch 1 vertex 0
2579 * - attribute 0 of patch 1 vertex 1
2580 * ...
2581 * - attribute 1 of patch 0 vertex 0
2582 * - attribute 1 of patch 0 vertex 1
2583 * ...
2584 * - per patch attribute 0 of patch 0
2585 * - per patch attribute 0 of patch 1
2586 * ...
2587 *
2588 * Note that every attribute has 4 components.
2589 */
2590 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2591 LLVMValueRef vertex_index,
2592 LLVMValueRef param_index)
2593 {
2594 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2595 LLVMValueRef param_stride, constant16;
2596 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2597
2598 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2599 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2600 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2601 num_patches, "");
2602
2603 constant16 = LLVMConstInt(ctx->i32, 16, false);
2604 if (vertex_index) {
2605 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2606 vertices_per_patch, "");
2607
2608 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2609 vertex_index, "");
2610
2611 param_stride = total_vertices;
2612 } else {
2613 base_addr = rel_patch_id;
2614 param_stride = num_patches;
2615 }
2616
2617 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2618 LLVMBuildMul(ctx->builder, param_index,
2619 param_stride, ""), "");
2620
2621 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2622
2623 if (!vertex_index) {
2624 LLVMValueRef patch_data_offset =
2625 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2626
2627 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2628 patch_data_offset, "");
2629 }
2630 return base_addr;
2631 }
2632
2633 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2634 unsigned param,
2635 unsigned const_index,
2636 bool is_compact,
2637 LLVMValueRef vertex_index,
2638 LLVMValueRef indir_index)
2639 {
2640 LLVMValueRef param_index;
2641
2642 if (indir_index)
2643 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2644 indir_index, "");
2645 else {
2646 if (const_index && !is_compact)
2647 param += const_index;
2648 param_index = LLVMConstInt(ctx->i32, param, false);
2649 }
2650 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2651 }
2652
2653 static void
2654 mark_tess_output(struct nir_to_llvm_context *ctx,
2655 bool is_patch, uint32_t param)
2656
2657 {
2658 if (is_patch) {
2659 ctx->tess_patch_outputs_written |= (1ull << param);
2660 } else
2661 ctx->tess_outputs_written |= (1ull << param);
2662 }
2663
2664 static LLVMValueRef
2665 get_dw_address(struct nir_to_llvm_context *ctx,
2666 LLVMValueRef dw_addr,
2667 unsigned param,
2668 unsigned const_index,
2669 bool compact_const_index,
2670 LLVMValueRef vertex_index,
2671 LLVMValueRef stride,
2672 LLVMValueRef indir_index)
2673
2674 {
2675
2676 if (vertex_index) {
2677 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2678 LLVMBuildMul(ctx->builder,
2679 vertex_index,
2680 stride, ""), "");
2681 }
2682
2683 if (indir_index)
2684 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2685 LLVMBuildMul(ctx->builder, indir_index,
2686 LLVMConstInt(ctx->i32, 4, false), ""), "");
2687 else if (const_index && !compact_const_index)
2688 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2689 LLVMConstInt(ctx->i32, const_index, false), "");
2690
2691 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2692 LLVMConstInt(ctx->i32, param * 4, false), "");
2693
2694 if (const_index && compact_const_index)
2695 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2696 LLVMConstInt(ctx->i32, const_index, false), "");
2697 return dw_addr;
2698 }
2699
2700 static LLVMValueRef
2701 load_tcs_input(struct nir_to_llvm_context *ctx,
2702 nir_intrinsic_instr *instr)
2703 {
2704 LLVMValueRef dw_addr, stride;
2705 unsigned const_index;
2706 LLVMValueRef vertex_index;
2707 LLVMValueRef indir_index;
2708 unsigned param;
2709 LLVMValueRef value[4], result;
2710 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2711 const bool is_compact = instr->variables[0]->var->data.compact;
2712 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2713 get_deref_offset(ctx->nir, instr->variables[0],
2714 false, NULL, per_vertex ? &vertex_index : NULL,
2715 &const_index, &indir_index);
2716
2717 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2718 dw_addr = get_tcs_in_current_patch_offset(ctx);
2719 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2720 indir_index);
2721
2722 for (unsigned i = 0; i < instr->num_components; i++) {
2723 value[i] = lds_load(ctx, dw_addr);
2724 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2725 ctx->i32one, "");
2726 }
2727 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2728 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2729 return result;
2730 }
2731
2732 static LLVMValueRef
2733 load_tcs_output(struct nir_to_llvm_context *ctx,
2734 nir_intrinsic_instr *instr)
2735 {
2736 LLVMValueRef dw_addr, stride;
2737 LLVMValueRef value[4], result;
2738 LLVMValueRef vertex_index = NULL;
2739 LLVMValueRef indir_index = NULL;
2740 unsigned const_index = 0;
2741 unsigned param;
2742 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2743 const bool is_compact = instr->variables[0]->var->data.compact;
2744 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2745 get_deref_offset(ctx->nir, instr->variables[0],
2746 false, NULL, per_vertex ? &vertex_index : NULL,
2747 &const_index, &indir_index);
2748
2749 if (!instr->variables[0]->var->data.patch) {
2750 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2751 dw_addr = get_tcs_out_current_patch_offset(ctx);
2752 } else {
2753 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2754 }
2755
2756 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2757 indir_index);
2758
2759 for (unsigned i = 0; i < instr->num_components; i++) {
2760 value[i] = lds_load(ctx, dw_addr);
2761 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2762 ctx->i32one, "");
2763 }
2764 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2765 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2766 return result;
2767 }
2768
2769 static void
2770 store_tcs_output(struct nir_to_llvm_context *ctx,
2771 nir_intrinsic_instr *instr,
2772 LLVMValueRef src,
2773 unsigned writemask)
2774 {
2775 LLVMValueRef stride, dw_addr;
2776 LLVMValueRef buf_addr = NULL;
2777 LLVMValueRef vertex_index = NULL;
2778 LLVMValueRef indir_index = NULL;
2779 unsigned const_index = 0;
2780 unsigned param;
2781 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2782 const bool is_compact = instr->variables[0]->var->data.compact;
2783
2784 get_deref_offset(ctx->nir, instr->variables[0],
2785 false, NULL, per_vertex ? &vertex_index : NULL,
2786 &const_index, &indir_index);
2787
2788 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2789 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2790 is_compact && const_index > 3) {
2791 const_index -= 3;
2792 param++;
2793 }
2794
2795 if (!instr->variables[0]->var->data.patch) {
2796 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2797 dw_addr = get_tcs_out_current_patch_offset(ctx);
2798 } else {
2799 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2800 }
2801
2802 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2803
2804 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2805 indir_index);
2806 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2807 vertex_index, indir_index);
2808
2809 unsigned base = is_compact ? const_index : 0;
2810 for (unsigned chan = 0; chan < 8; chan++) {
2811 bool is_tess_factor = false;
2812 if (!(writemask & (1 << chan)))
2813 continue;
2814 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2815
2816 lds_store(ctx, dw_addr, value);
2817
2818 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2819 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2820 is_tess_factor = true;
2821
2822 if (!is_tess_factor && writemask != 0xF)
2823 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2824 buf_addr, ctx->oc_lds,
2825 4 * (base + chan), 1, 0, true, false);
2826
2827 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2828 ctx->i32one, "");
2829 }
2830
2831 if (writemask == 0xF) {
2832 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2833 buf_addr, ctx->oc_lds,
2834 (base * 4), 1, 0, true, false);
2835 }
2836 }
2837
2838 static LLVMValueRef
2839 load_tes_input(struct nir_to_llvm_context *ctx,
2840 const nir_intrinsic_instr *instr)
2841 {
2842 LLVMValueRef buf_addr;
2843 LLVMValueRef result;
2844 LLVMValueRef vertex_index = NULL;
2845 LLVMValueRef indir_index = NULL;
2846 unsigned const_index = 0;
2847 unsigned param;
2848 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2849 const bool is_compact = instr->variables[0]->var->data.compact;
2850
2851 get_deref_offset(ctx->nir, instr->variables[0],
2852 false, NULL, per_vertex ? &vertex_index : NULL,
2853 &const_index, &indir_index);
2854 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2855 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2856 is_compact && const_index > 3) {
2857 const_index -= 3;
2858 param++;
2859 }
2860 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2861 is_compact, vertex_index, indir_index);
2862
2863 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2864 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2865 result = trim_vector(&ctx->ac, result, instr->num_components);
2866 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2867 return result;
2868 }
2869
2870 static LLVMValueRef
2871 load_gs_input(struct nir_to_llvm_context *ctx,
2872 nir_intrinsic_instr *instr)
2873 {
2874 LLVMValueRef indir_index, vtx_offset;
2875 unsigned const_index;
2876 LLVMValueRef args[9];
2877 unsigned param, vtx_offset_param;
2878 LLVMValueRef value[4], result;
2879 unsigned vertex_index;
2880 get_deref_offset(ctx->nir, instr->variables[0],
2881 false, &vertex_index, NULL,
2882 &const_index, &indir_index);
2883 vtx_offset_param = vertex_index;
2884 assert(vtx_offset_param < 6);
2885 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2886 LLVMConstInt(ctx->i32, 4, false), "");
2887
2888 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2889 for (unsigned i = 0; i < instr->num_components; i++) {
2890
2891 args[0] = ctx->esgs_ring;
2892 args[1] = vtx_offset;
2893 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2894 args[3] = ctx->i32zero;
2895 args[4] = ctx->i32one; /* OFFEN */
2896 args[5] = ctx->i32zero; /* IDXEN */
2897 args[6] = ctx->i32one; /* GLC */
2898 args[7] = ctx->i32zero; /* SLC */
2899 args[8] = ctx->i32zero; /* TFE */
2900
2901 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2902 ctx->i32, args, 9,
2903 AC_FUNC_ATTR_READONLY |
2904 AC_FUNC_ATTR_LEGACY);
2905 }
2906 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2907
2908 return result;
2909 }
2910
2911 static LLVMValueRef
2912 build_gep_for_deref(struct ac_nir_context *ctx,
2913 nir_deref_var *deref)
2914 {
2915 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2916 assert(entry->data);
2917 LLVMValueRef val = entry->data;
2918 nir_deref *tail = deref->deref.child;
2919 while (tail != NULL) {
2920 LLVMValueRef offset;
2921 switch (tail->deref_type) {
2922 case nir_deref_type_array: {
2923 nir_deref_array *array = nir_deref_as_array(tail);
2924 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2925 if (array->deref_array_type ==
2926 nir_deref_array_type_indirect) {
2927 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2928 get_src(ctx,
2929 array->indirect),
2930 "");
2931 }
2932 break;
2933 }
2934 case nir_deref_type_struct: {
2935 nir_deref_struct *deref_struct =
2936 nir_deref_as_struct(tail);
2937 offset = LLVMConstInt(ctx->ac.i32,
2938 deref_struct->index, 0);
2939 break;
2940 }
2941 default:
2942 unreachable("bad deref type");
2943 }
2944 val = ac_build_gep0(&ctx->ac, val, offset);
2945 tail = tail->child;
2946 }
2947 return val;
2948 }
2949
2950 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2951 nir_intrinsic_instr *instr)
2952 {
2953 LLVMValueRef values[8];
2954 int idx = instr->variables[0]->var->data.driver_location;
2955 int ve = instr->dest.ssa.num_components;
2956 LLVMValueRef indir_index;
2957 LLVMValueRef ret;
2958 unsigned const_index;
2959 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2960 instr->variables[0]->var->data.mode == nir_var_shader_in;
2961 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2962 &const_index, &indir_index);
2963
2964 if (instr->dest.ssa.bit_size == 64)
2965 ve *= 2;
2966
2967 switch (instr->variables[0]->var->data.mode) {
2968 case nir_var_shader_in:
2969 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2970 return load_tcs_input(ctx->nctx, instr);
2971 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2972 return load_tes_input(ctx->nctx, instr);
2973 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2974 return load_gs_input(ctx->nctx, instr);
2975 }
2976 for (unsigned chan = 0; chan < ve; chan++) {
2977 if (indir_index) {
2978 unsigned count = glsl_count_attribute_slots(
2979 instr->variables[0]->var->type,
2980 ctx->stage == MESA_SHADER_VERTEX);
2981 count -= chan / 4;
2982 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2983 &ctx->ac, ctx->abi->inputs + idx + chan, count,
2984 4, false);
2985
2986 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2987 tmp_vec,
2988 indir_index, "");
2989 } else
2990 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
2991 }
2992 break;
2993 case nir_var_local:
2994 for (unsigned chan = 0; chan < ve; chan++) {
2995 if (indir_index) {
2996 unsigned count = glsl_count_attribute_slots(
2997 instr->variables[0]->var->type, false);
2998 count -= chan / 4;
2999 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3000 &ctx->ac, ctx->locals + idx + chan, count,
3001 4, true);
3002
3003 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3004 tmp_vec,
3005 indir_index, "");
3006 } else {
3007 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3008 }
3009 }
3010 break;
3011 case nir_var_shared: {
3012 LLVMValueRef address = build_gep_for_deref(ctx,
3013 instr->variables[0]);
3014 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3015 return LLVMBuildBitCast(ctx->ac.builder, val,
3016 get_def_type(ctx, &instr->dest.ssa),
3017 "");
3018 }
3019 case nir_var_shader_out:
3020 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3021 return load_tcs_output(ctx->nctx, instr);
3022 for (unsigned chan = 0; chan < ve; chan++) {
3023 if (indir_index) {
3024 unsigned count = glsl_count_attribute_slots(
3025 instr->variables[0]->var->type, false);
3026 count -= chan / 4;
3027 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3028 &ctx->ac, ctx->outputs + idx + chan, count,
3029 4, true);
3030
3031 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3032 tmp_vec,
3033 indir_index, "");
3034 } else {
3035 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3036 ctx->outputs[idx + chan + const_index * 4],
3037 "");
3038 }
3039 }
3040 break;
3041 default:
3042 unreachable("unhandle variable mode");
3043 }
3044 ret = ac_build_gather_values(&ctx->ac, values, ve);
3045 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3046 }
3047
3048 static void
3049 visit_store_var(struct ac_nir_context *ctx,
3050 nir_intrinsic_instr *instr)
3051 {
3052 LLVMValueRef temp_ptr, value;
3053 int idx = instr->variables[0]->var->data.driver_location;
3054 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3055 int writemask = instr->const_index[0];
3056 LLVMValueRef indir_index;
3057 unsigned const_index;
3058 get_deref_offset(ctx, instr->variables[0], false,
3059 NULL, NULL, &const_index, &indir_index);
3060
3061 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3062 int old_writemask = writemask;
3063
3064 src = LLVMBuildBitCast(ctx->ac.builder, src,
3065 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3066 "");
3067
3068 writemask = 0;
3069 for (unsigned chan = 0; chan < 4; chan++) {
3070 if (old_writemask & (1 << chan))
3071 writemask |= 3u << (2 * chan);
3072 }
3073 }
3074
3075 switch (instr->variables[0]->var->data.mode) {
3076 case nir_var_shader_out:
3077
3078 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3079 store_tcs_output(ctx->nctx, instr, src, writemask);
3080 return;
3081 }
3082
3083 for (unsigned chan = 0; chan < 8; chan++) {
3084 int stride = 4;
3085 if (!(writemask & (1 << chan)))
3086 continue;
3087
3088 value = llvm_extract_elem(&ctx->ac, src, chan);
3089
3090 if (instr->variables[0]->var->data.compact)
3091 stride = 1;
3092 if (indir_index) {
3093 unsigned count = glsl_count_attribute_slots(
3094 instr->variables[0]->var->type, false);
3095 count -= chan / 4;
3096 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3097 &ctx->ac, ctx->outputs + idx + chan, count,
3098 stride, true);
3099
3100 if (get_llvm_num_components(tmp_vec) > 1) {
3101 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3102 value, indir_index, "");
3103 } else
3104 tmp_vec = value;
3105 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3106 count, stride, tmp_vec);
3107
3108 } else {
3109 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3110
3111 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3112 }
3113 }
3114 break;
3115 case nir_var_local:
3116 for (unsigned chan = 0; chan < 8; chan++) {
3117 if (!(writemask & (1 << chan)))
3118 continue;
3119
3120 value = llvm_extract_elem(&ctx->ac, src, chan);
3121 if (indir_index) {
3122 unsigned count = glsl_count_attribute_slots(
3123 instr->variables[0]->var->type, false);
3124 count -= chan / 4;
3125 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3126 &ctx->ac, ctx->locals + idx + chan, count,
3127 4, true);
3128
3129 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3130 value, indir_index, "");
3131 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3132 count, 4, tmp_vec);
3133 } else {
3134 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3135
3136 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3137 }
3138 }
3139 break;
3140 case nir_var_shared: {
3141 int writemask = instr->const_index[0];
3142 LLVMValueRef address = build_gep_for_deref(ctx,
3143 instr->variables[0]);
3144 LLVMValueRef val = get_src(ctx, instr->src[0]);
3145 unsigned components =
3146 glsl_get_vector_elements(
3147 nir_deref_tail(&instr->variables[0]->deref)->type);
3148 if (writemask == (1 << components) - 1) {
3149 val = LLVMBuildBitCast(
3150 ctx->ac.builder, val,
3151 LLVMGetElementType(LLVMTypeOf(address)), "");
3152 LLVMBuildStore(ctx->ac.builder, val, address);
3153 } else {
3154 for (unsigned chan = 0; chan < 4; chan++) {
3155 if (!(writemask & (1 << chan)))
3156 continue;
3157 LLVMValueRef ptr =
3158 LLVMBuildStructGEP(ctx->ac.builder,
3159 address, chan, "");
3160 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3161 chan);
3162 src = LLVMBuildBitCast(
3163 ctx->ac.builder, src,
3164 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3165 LLVMBuildStore(ctx->ac.builder, src, ptr);
3166 }
3167 }
3168 break;
3169 }
3170 default:
3171 break;
3172 }
3173 }
3174
3175 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3176 {
3177 switch (dim) {
3178 case GLSL_SAMPLER_DIM_BUF:
3179 return 1;
3180 case GLSL_SAMPLER_DIM_1D:
3181 return array ? 2 : 1;
3182 case GLSL_SAMPLER_DIM_2D:
3183 return array ? 3 : 2;
3184 case GLSL_SAMPLER_DIM_MS:
3185 return array ? 4 : 3;
3186 case GLSL_SAMPLER_DIM_3D:
3187 case GLSL_SAMPLER_DIM_CUBE:
3188 return 3;
3189 case GLSL_SAMPLER_DIM_RECT:
3190 case GLSL_SAMPLER_DIM_SUBPASS:
3191 return 2;
3192 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3193 return 3;
3194 default:
3195 break;
3196 }
3197 return 0;
3198 }
3199
3200
3201
3202 /* Adjust the sample index according to FMASK.
3203 *
3204 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3205 * which is the identity mapping. Each nibble says which physical sample
3206 * should be fetched to get that sample.
3207 *
3208 * For example, 0x11111100 means there are only 2 samples stored and
3209 * the second sample covers 3/4 of the pixel. When reading samples 0
3210 * and 1, return physical sample 0 (determined by the first two 0s
3211 * in FMASK), otherwise return physical sample 1.
3212 *
3213 * The sample index should be adjusted as follows:
3214 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3215 */
3216 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3217 LLVMValueRef coord_x, LLVMValueRef coord_y,
3218 LLVMValueRef coord_z,
3219 LLVMValueRef sample_index,
3220 LLVMValueRef fmask_desc_ptr)
3221 {
3222 LLVMValueRef fmask_load_address[4];
3223 LLVMValueRef res;
3224
3225 fmask_load_address[0] = coord_x;
3226 fmask_load_address[1] = coord_y;
3227 if (coord_z) {
3228 fmask_load_address[2] = coord_z;
3229 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3230 }
3231
3232 struct ac_image_args args = {0};
3233
3234 args.opcode = ac_image_load;
3235 args.da = coord_z ? true : false;
3236 args.resource = fmask_desc_ptr;
3237 args.dmask = 0xf;
3238 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3239
3240 res = ac_build_image_opcode(ctx, &args);
3241
3242 res = to_integer(ctx, res);
3243 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3244 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3245
3246 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3247 res,
3248 ctx->i32_0, "");
3249
3250 LLVMValueRef sample_index4 =
3251 LLVMBuildMul(ctx->builder, sample_index, four, "");
3252 LLVMValueRef shifted_fmask =
3253 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3254 LLVMValueRef final_sample =
3255 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3256
3257 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3258 * resource descriptor is 0 (invalid),
3259 */
3260 LLVMValueRef fmask_desc =
3261 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3262 ctx->v8i32, "");
3263
3264 LLVMValueRef fmask_word1 =
3265 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3266 ctx->i32_1, "");
3267
3268 LLVMValueRef word1_is_nonzero =
3269 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3270 fmask_word1, ctx->i32_0, "");
3271
3272 /* Replace the MSAA sample index. */
3273 sample_index =
3274 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3275 final_sample, sample_index, "");
3276 return sample_index;
3277 }
3278
3279 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3280 const nir_intrinsic_instr *instr)
3281 {
3282 const struct glsl_type *type = instr->variables[0]->var->type;
3283 if(instr->variables[0]->deref.child)
3284 type = instr->variables[0]->deref.child->type;
3285
3286 LLVMValueRef src0 = get_src(ctx->nir, instr->src[0]);
3287 LLVMValueRef coords[4];
3288 LLVMValueRef masks[] = {
3289 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3290 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3291 };
3292 LLVMValueRef res;
3293 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx->nir, instr->src[1]), 0);
3294
3295 int count;
3296 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3297 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3298 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3299 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3300 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3301
3302 count = image_type_to_components_count(dim,
3303 glsl_sampler_type_is_array(type));
3304
3305 if (is_ms) {
3306 LLVMValueRef fmask_load_address[3];
3307 int chan;
3308
3309 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3310 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3311 if (glsl_sampler_type_is_array(type))
3312 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3313 else
3314 fmask_load_address[2] = NULL;
3315 if (add_frag_pos) {
3316 for (chan = 0; chan < 2; ++chan)
3317 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3318 }
3319 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3320 fmask_load_address[0],
3321 fmask_load_address[1],
3322 fmask_load_address[2],
3323 sample_index,
3324 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK));
3325 }
3326 if (count == 1) {
3327 if (instr->src[0].ssa->num_components)
3328 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3329 else
3330 res = src0;
3331 } else {
3332 int chan;
3333 if (is_ms)
3334 count--;
3335 for (chan = 0; chan < count; ++chan) {
3336 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3337 }
3338
3339 if (add_frag_pos) {
3340 for (chan = 0; chan < count; ++chan)
3341 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3342 }
3343 if (is_ms) {
3344 coords[count] = sample_index;
3345 count++;
3346 }
3347
3348 if (count == 3) {
3349 coords[3] = LLVMGetUndef(ctx->i32);
3350 count = 4;
3351 }
3352 res = ac_build_gather_values(&ctx->ac, coords, count);
3353 }
3354 return res;
3355 }
3356
3357 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3358 const nir_intrinsic_instr *instr)
3359 {
3360 LLVMValueRef params[7];
3361 LLVMValueRef res;
3362 char intrinsic_name[64];
3363 const nir_variable *var = instr->variables[0]->var;
3364 const struct glsl_type *type = var->type;
3365 if(instr->variables[0]->deref.child)
3366 type = instr->variables[0]->deref.child->type;
3367
3368 type = glsl_without_array(type);
3369 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3370 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER);
3371 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx->nir, instr->src[0]),
3372 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3373 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3374 params[3] = ctx->i1false; /* glc */
3375 params[4] = ctx->i1false; /* slc */
3376 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3377 params, 5, 0);
3378
3379 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3380 res = to_integer(&ctx->ac, res);
3381 } else {
3382 bool is_da = glsl_sampler_type_is_array(type) ||
3383 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3384 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3385 LLVMValueRef glc = ctx->i1false;
3386 LLVMValueRef slc = ctx->i1false;
3387
3388 params[0] = get_image_coords(ctx, instr);
3389 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE);
3390 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3391 if (HAVE_LLVM <= 0x0309) {
3392 params[3] = ctx->i1false; /* r128 */
3393 params[4] = da;
3394 params[5] = glc;
3395 params[6] = slc;
3396 } else {
3397 LLVMValueRef lwe = ctx->i1false;
3398 params[3] = glc;
3399 params[4] = slc;
3400 params[5] = lwe;
3401 params[6] = da;
3402 }
3403
3404 ac_get_image_intr_name("llvm.amdgcn.image.load",
3405 ctx->v4f32, /* vdata */
3406 LLVMTypeOf(params[0]), /* coords */
3407 LLVMTypeOf(params[1]), /* rsrc */
3408 intrinsic_name, sizeof(intrinsic_name));
3409
3410 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3411 params, 7, AC_FUNC_ATTR_READONLY);
3412 }
3413 return to_integer(&ctx->ac, res);
3414 }
3415
3416 static void visit_image_store(struct nir_to_llvm_context *ctx,
3417 nir_intrinsic_instr *instr)
3418 {
3419 LLVMValueRef params[8];
3420 char intrinsic_name[64];
3421 const nir_variable *var = instr->variables[0]->var;
3422 const struct glsl_type *type = glsl_without_array(var->type);
3423 LLVMValueRef glc = ctx->i1false;
3424 bool force_glc = ctx->options->chip_class == SI;
3425 if (force_glc)
3426 glc = ctx->i1true;
3427 if (ctx->stage == MESA_SHADER_FRAGMENT)
3428 ctx->shader_info->fs.writes_memory = true;
3429
3430 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3431 params[0] = to_float(&ctx->ac, get_src(ctx->nir, instr->src[2])); /* data */
3432 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER);
3433 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx->nir, instr->src[0]),
3434 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3435 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3436 params[4] = glc; /* glc */
3437 params[5] = ctx->i1false; /* slc */
3438 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3439 params, 6, 0);
3440 } else {
3441 bool is_da = glsl_sampler_type_is_array(type) ||
3442 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3443 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3444 LLVMValueRef slc = ctx->i1false;
3445
3446 params[0] = to_float(&ctx->ac, get_src(ctx->nir, instr->src[2]));
3447 params[1] = get_image_coords(ctx, instr); /* coords */
3448 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE);
3449 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3450 if (HAVE_LLVM <= 0x0309) {
3451 params[4] = ctx->i1false; /* r128 */
3452 params[5] = da;
3453 params[6] = glc;
3454 params[7] = slc;
3455 } else {
3456 LLVMValueRef lwe = ctx->i1false;
3457 params[4] = glc;
3458 params[5] = slc;
3459 params[6] = lwe;
3460 params[7] = da;
3461 }
3462
3463 ac_get_image_intr_name("llvm.amdgcn.image.store",
3464 LLVMTypeOf(params[0]), /* vdata */
3465 LLVMTypeOf(params[1]), /* coords */
3466 LLVMTypeOf(params[2]), /* rsrc */
3467 intrinsic_name, sizeof(intrinsic_name));
3468
3469 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3470 params, 8, 0);
3471 }
3472
3473 }
3474
3475 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3476 const nir_intrinsic_instr *instr)
3477 {
3478 LLVMValueRef params[6];
3479 int param_count = 0;
3480 const nir_variable *var = instr->variables[0]->var;
3481
3482 const char *atomic_name;
3483 char intrinsic_name[41];
3484 const struct glsl_type *type = glsl_without_array(var->type);
3485 MAYBE_UNUSED int length;
3486
3487 if (ctx->stage == MESA_SHADER_FRAGMENT)
3488 ctx->shader_info->fs.writes_memory = true;
3489
3490 switch (instr->intrinsic) {
3491 case nir_intrinsic_image_atomic_add:
3492 atomic_name = "add";
3493 break;
3494 case nir_intrinsic_image_atomic_min:
3495 atomic_name = "smin";
3496 break;
3497 case nir_intrinsic_image_atomic_max:
3498 atomic_name = "smax";
3499 break;
3500 case nir_intrinsic_image_atomic_and:
3501 atomic_name = "and";
3502 break;
3503 case nir_intrinsic_image_atomic_or:
3504 atomic_name = "or";
3505 break;
3506 case nir_intrinsic_image_atomic_xor:
3507 atomic_name = "xor";
3508 break;
3509 case nir_intrinsic_image_atomic_exchange:
3510 atomic_name = "swap";
3511 break;
3512 case nir_intrinsic_image_atomic_comp_swap:
3513 atomic_name = "cmpswap";
3514 break;
3515 default:
3516 abort();
3517 }
3518
3519 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3520 params[param_count++] = get_src(ctx->nir, instr->src[3]);
3521 params[param_count++] = get_src(ctx->nir, instr->src[2]);
3522
3523 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3524 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER);
3525 params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx->nir, instr->src[0]),
3526 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3527 params[param_count++] = ctx->i32zero; /* voffset */
3528 params[param_count++] = ctx->i1false; /* slc */
3529
3530 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3531 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3532 } else {
3533 char coords_type[8];
3534
3535 bool da = glsl_sampler_type_is_array(type) ||
3536 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3537
3538 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3539 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE);
3540 params[param_count++] = ctx->i1false; /* r128 */
3541 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3542 params[param_count++] = ctx->i1false; /* slc */
3543
3544 build_int_type_name(LLVMTypeOf(coords),
3545 coords_type, sizeof(coords_type));
3546
3547 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3548 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3549 }
3550
3551 assert(length < sizeof(intrinsic_name));
3552 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3553 }
3554
3555 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3556 const nir_intrinsic_instr *instr)
3557 {
3558 LLVMValueRef res;
3559 const nir_variable *var = instr->variables[0]->var;
3560 const struct glsl_type *type = instr->variables[0]->var->type;
3561 bool da = glsl_sampler_type_is_array(var->type) ||
3562 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3563 if(instr->variables[0]->deref.child)
3564 type = instr->variables[0]->deref.child->type;
3565
3566 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3567 return get_buffer_size(ctx, get_sampler_desc(ctx->nctx, instr->variables[0], AC_DESC_BUFFER), true);
3568
3569 struct ac_image_args args = { 0 };
3570
3571 args.da = da;
3572 args.dmask = 0xf;
3573 args.resource = get_sampler_desc(ctx->nctx, instr->variables[0], AC_DESC_IMAGE);
3574 args.opcode = ac_image_get_resinfo;
3575 args.addr = ctx->ac.i32_0;
3576
3577 res = ac_build_image_opcode(&ctx->ac, &args);
3578
3579 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3580 glsl_sampler_type_is_array(type)) {
3581 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3582 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3583 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3584 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3585 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3586 }
3587 return res;
3588 }
3589
3590 #define NOOP_WAITCNT 0xf7f
3591 #define LGKM_CNT 0x07f
3592 #define VM_CNT 0xf70
3593
3594 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3595 unsigned simm16)
3596 {
3597 LLVMValueRef args[1] = {
3598 LLVMConstInt(ctx->i32, simm16, false),
3599 };
3600 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3601 ctx->voidt, args, 1, 0);
3602 }
3603
3604 static void emit_barrier(struct nir_to_llvm_context *ctx)
3605 {
3606 /* SI only (thanks to a hw bug workaround):
3607 * The real barrier instruction isn’t needed, because an entire patch
3608 * always fits into a single wave.
3609 */
3610 if (ctx->options->chip_class == SI &&
3611 ctx->stage == MESA_SHADER_TESS_CTRL) {
3612 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3613 return;
3614 }
3615 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3616 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3617 }
3618
3619 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3620 const nir_intrinsic_instr *instr)
3621 {
3622 LLVMValueRef cond;
3623 ctx->shader_info->fs.can_discard = true;
3624
3625 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3626 get_src(ctx->nir, instr->src[0]),
3627 ctx->i32zero, "");
3628
3629 cond = LLVMBuildSelect(ctx->builder, cond,
3630 LLVMConstReal(ctx->f32, -1.0f),
3631 ctx->f32zero, "");
3632 ac_build_kill(&ctx->ac, cond);
3633 }
3634
3635 static LLVMValueRef
3636 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3637 {
3638 LLVMValueRef result;
3639 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3640 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3641 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3642
3643 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3644 }
3645
3646 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3647 const nir_intrinsic_instr *instr)
3648 {
3649 LLVMValueRef ptr, result;
3650 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3651 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3652
3653 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3654 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3655 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3656 ptr, src, src1,
3657 LLVMAtomicOrderingSequentiallyConsistent,
3658 LLVMAtomicOrderingSequentiallyConsistent,
3659 false);
3660 } else {
3661 LLVMAtomicRMWBinOp op;
3662 switch (instr->intrinsic) {
3663 case nir_intrinsic_var_atomic_add:
3664 op = LLVMAtomicRMWBinOpAdd;
3665 break;
3666 case nir_intrinsic_var_atomic_umin:
3667 op = LLVMAtomicRMWBinOpUMin;
3668 break;
3669 case nir_intrinsic_var_atomic_umax:
3670 op = LLVMAtomicRMWBinOpUMax;
3671 break;
3672 case nir_intrinsic_var_atomic_imin:
3673 op = LLVMAtomicRMWBinOpMin;
3674 break;
3675 case nir_intrinsic_var_atomic_imax:
3676 op = LLVMAtomicRMWBinOpMax;
3677 break;
3678 case nir_intrinsic_var_atomic_and:
3679 op = LLVMAtomicRMWBinOpAnd;
3680 break;
3681 case nir_intrinsic_var_atomic_or:
3682 op = LLVMAtomicRMWBinOpOr;
3683 break;
3684 case nir_intrinsic_var_atomic_xor:
3685 op = LLVMAtomicRMWBinOpXor;
3686 break;
3687 case nir_intrinsic_var_atomic_exchange:
3688 op = LLVMAtomicRMWBinOpXchg;
3689 break;
3690 default:
3691 return NULL;
3692 }
3693
3694 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3695 LLVMAtomicOrderingSequentiallyConsistent,
3696 false);
3697 }
3698 return result;
3699 }
3700
3701 #define INTERP_CENTER 0
3702 #define INTERP_CENTROID 1
3703 #define INTERP_SAMPLE 2
3704
3705 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3706 enum glsl_interp_mode interp, unsigned location)
3707 {
3708 switch (interp) {
3709 case INTERP_MODE_FLAT:
3710 default:
3711 return NULL;
3712 case INTERP_MODE_SMOOTH:
3713 case INTERP_MODE_NONE:
3714 if (location == INTERP_CENTER)
3715 return ctx->persp_center;
3716 else if (location == INTERP_CENTROID)
3717 return ctx->persp_centroid;
3718 else if (location == INTERP_SAMPLE)
3719 return ctx->persp_sample;
3720 break;
3721 case INTERP_MODE_NOPERSPECTIVE:
3722 if (location == INTERP_CENTER)
3723 return ctx->linear_center;
3724 else if (location == INTERP_CENTROID)
3725 return ctx->linear_centroid;
3726 else if (location == INTERP_SAMPLE)
3727 return ctx->linear_sample;
3728 break;
3729 }
3730 return NULL;
3731 }
3732
3733 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3734 LLVMValueRef sample_id)
3735 {
3736 LLVMValueRef result;
3737 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3738
3739 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3740 const_array(ctx->v2f32, 64), "");
3741
3742 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3743 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3744
3745 return result;
3746 }
3747
3748 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3749 {
3750 LLVMValueRef values[2];
3751
3752 values[0] = emit_ffract(&ctx->ac, ctx->frag_pos[0]);
3753 values[1] = emit_ffract(&ctx->ac, ctx->frag_pos[1]);
3754 return ac_build_gather_values(&ctx->ac, values, 2);
3755 }
3756
3757 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3758 const nir_intrinsic_instr *instr)
3759 {
3760 LLVMValueRef result[2];
3761 LLVMValueRef interp_param, attr_number;
3762 unsigned location;
3763 unsigned chan;
3764 LLVMValueRef src_c0, src_c1;
3765 LLVMValueRef src0;
3766 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3767 switch (instr->intrinsic) {
3768 case nir_intrinsic_interp_var_at_centroid:
3769 location = INTERP_CENTROID;
3770 break;
3771 case nir_intrinsic_interp_var_at_sample:
3772 case nir_intrinsic_interp_var_at_offset:
3773 location = INTERP_CENTER;
3774 src0 = get_src(ctx->nir, instr->src[0]);
3775 break;
3776 default:
3777 break;
3778 }
3779
3780 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3781 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3782 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3783 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3784 LLVMValueRef sample_position;
3785 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3786
3787 /* fetch sample ID */
3788 sample_position = load_sample_position(ctx, src0);
3789
3790 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3791 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3792 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3793 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3794 }
3795 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3796 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3797
3798 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3799 LLVMValueRef ij_out[2];
3800 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3801
3802 /*
3803 * take the I then J parameters, and the DDX/Y for it, and
3804 * calculate the IJ inputs for the interpolator.
3805 * temp1 = ddx * offset/sample.x + I;
3806 * interp_param.I = ddy * offset/sample.y + temp1;
3807 * temp1 = ddx * offset/sample.x + J;
3808 * interp_param.J = ddy * offset/sample.y + temp1;
3809 */
3810 for (unsigned i = 0; i < 2; i++) {
3811 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3812 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3813 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3814 ddxy_out, ix_ll, "");
3815 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3816 ddxy_out, iy_ll, "");
3817 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3818 interp_param, ix_ll, "");
3819 LLVMValueRef temp1, temp2;
3820
3821 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3822 ctx->f32, "");
3823
3824 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3825 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3826
3827 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3828 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3829
3830 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3831 temp2, ctx->i32, "");
3832 }
3833 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3834
3835 }
3836
3837 for (chan = 0; chan < 2; chan++) {
3838 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3839
3840 if (interp_param) {
3841 interp_param = LLVMBuildBitCast(ctx->builder,
3842 interp_param, LLVMVectorType(ctx->f32, 2), "");
3843 LLVMValueRef i = LLVMBuildExtractElement(
3844 ctx->builder, interp_param, ctx->i32zero, "");
3845 LLVMValueRef j = LLVMBuildExtractElement(
3846 ctx->builder, interp_param, ctx->i32one, "");
3847
3848 result[chan] = ac_build_fs_interp(&ctx->ac,
3849 llvm_chan, attr_number,
3850 ctx->prim_mask, i, j);
3851 } else {
3852 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3853 LLVMConstInt(ctx->i32, 2, false),
3854 llvm_chan, attr_number,
3855 ctx->prim_mask);
3856 }
3857 }
3858 return ac_build_gather_values(&ctx->ac, result, 2);
3859 }
3860
3861 static void
3862 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3863 const nir_intrinsic_instr *instr)
3864 {
3865 LLVMValueRef gs_next_vertex;
3866 LLVMValueRef can_emit, kill;
3867 int idx;
3868
3869 assert(instr->const_index[0] == 0);
3870 /* Write vertex attribute values to GSVS ring */
3871 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3872 ctx->gs_next_vertex,
3873 "");
3874
3875 /* If this thread has already emitted the declared maximum number of
3876 * vertices, kill it: excessive vertex emissions are not supposed to
3877 * have any effect, and GS threads have no externally observable
3878 * effects other than emitting vertices.
3879 */
3880 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3881 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3882
3883 kill = LLVMBuildSelect(ctx->builder, can_emit,
3884 LLVMConstReal(ctx->f32, 1.0f),
3885 LLVMConstReal(ctx->f32, -1.0f), "");
3886 ac_build_kill(&ctx->ac, kill);
3887
3888 /* loop num outputs */
3889 idx = 0;
3890 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3891 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3892 int length = 4;
3893 int slot = idx;
3894 int slot_inc = 1;
3895
3896 if (!(ctx->output_mask & (1ull << i)))
3897 continue;
3898
3899 if (i == VARYING_SLOT_CLIP_DIST0) {
3900 /* pack clip and cull into a single set of slots */
3901 length = ctx->num_output_clips + ctx->num_output_culls;
3902 if (length > 4)
3903 slot_inc = 2;
3904 }
3905 for (unsigned j = 0; j < length; j++) {
3906 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3907 out_ptr[j], "");
3908 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3909 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3910 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3911
3912 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3913
3914 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3915 out_val, 1,
3916 voffset, ctx->gs2vs_offset, 0,
3917 1, 1, true, true);
3918 }
3919 idx += slot_inc;
3920 }
3921
3922 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3923 ctx->i32one, "");
3924 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3925
3926 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3927 }
3928
3929 static void
3930 visit_end_primitive(struct nir_to_llvm_context *ctx,
3931 const nir_intrinsic_instr *instr)
3932 {
3933 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3934 }
3935
3936 static LLVMValueRef
3937 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3938 const nir_intrinsic_instr *instr)
3939 {
3940 LLVMValueRef coord[4] = {
3941 ctx->tes_u,
3942 ctx->tes_v,
3943 ctx->f32zero,
3944 ctx->f32zero,
3945 };
3946
3947 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3948 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3949 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3950
3951 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3952 return LLVMBuildBitCast(ctx->builder, result,
3953 get_def_type(ctx->nir, &instr->dest.ssa), "");
3954 }
3955
3956 static void visit_intrinsic(struct ac_nir_context *ctx,
3957 nir_intrinsic_instr *instr)
3958 {
3959 LLVMValueRef result = NULL;
3960
3961 switch (instr->intrinsic) {
3962 case nir_intrinsic_load_work_group_id: {
3963 result = ctx->nctx->workgroup_ids;
3964 break;
3965 }
3966 case nir_intrinsic_load_base_vertex: {
3967 result = ctx->abi->base_vertex;
3968 break;
3969 }
3970 case nir_intrinsic_load_vertex_id_zero_base: {
3971 result = ctx->abi->vertex_id;
3972 break;
3973 }
3974 case nir_intrinsic_load_local_invocation_id: {
3975 result = ctx->nctx->local_invocation_ids;
3976 break;
3977 }
3978 case nir_intrinsic_load_base_instance:
3979 result = ctx->abi->start_instance;
3980 break;
3981 case nir_intrinsic_load_draw_id:
3982 result = ctx->abi->draw_id;
3983 break;
3984 case nir_intrinsic_load_invocation_id:
3985 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3986 result = unpack_param(ctx->nctx, ctx->nctx->tcs_rel_ids, 8, 5);
3987 else
3988 result = ctx->nctx->gs_invocation_id;
3989 break;
3990 case nir_intrinsic_load_primitive_id:
3991 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3992 ctx->nctx->shader_info->gs.uses_prim_id = true;
3993 result = ctx->nctx->gs_prim_id;
3994 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3995 ctx->nctx->shader_info->tcs.uses_prim_id = true;
3996 result = ctx->nctx->tcs_patch_id;
3997 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
3998 ctx->nctx->shader_info->tcs.uses_prim_id = true;
3999 result = ctx->nctx->tes_patch_id;
4000 } else
4001 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4002 break;
4003 case nir_intrinsic_load_sample_id:
4004 ctx->nctx->shader_info->fs.force_persample = true;
4005 result = unpack_param(ctx->nctx, ctx->nctx->ancillary, 8, 4);
4006 break;
4007 case nir_intrinsic_load_sample_pos:
4008 ctx->nctx->shader_info->fs.force_persample = true;
4009 result = load_sample_pos(ctx->nctx);
4010 break;
4011 case nir_intrinsic_load_sample_mask_in:
4012 result = ctx->nctx->sample_coverage;
4013 break;
4014 case nir_intrinsic_load_front_face:
4015 result = ctx->nctx->front_face;
4016 break;
4017 case nir_intrinsic_load_instance_id:
4018 result = ctx->abi->instance_id;
4019 ctx->nctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4020 ctx->nctx->shader_info->vs.vgpr_comp_cnt);
4021 break;
4022 case nir_intrinsic_load_num_work_groups:
4023 result = ctx->nctx->num_work_groups;
4024 break;
4025 case nir_intrinsic_load_local_invocation_index:
4026 result = visit_load_local_invocation_index(ctx->nctx);
4027 break;
4028 case nir_intrinsic_load_push_constant:
4029 result = visit_load_push_constant(ctx->nctx, instr);
4030 break;
4031 case nir_intrinsic_vulkan_resource_index:
4032 result = visit_vulkan_resource_index(ctx->nctx, instr);
4033 break;
4034 case nir_intrinsic_store_ssbo:
4035 visit_store_ssbo(ctx->nctx, instr);
4036 break;
4037 case nir_intrinsic_load_ssbo:
4038 result = visit_load_buffer(ctx->nctx, instr);
4039 break;
4040 case nir_intrinsic_ssbo_atomic_add:
4041 case nir_intrinsic_ssbo_atomic_imin:
4042 case nir_intrinsic_ssbo_atomic_umin:
4043 case nir_intrinsic_ssbo_atomic_imax:
4044 case nir_intrinsic_ssbo_atomic_umax:
4045 case nir_intrinsic_ssbo_atomic_and:
4046 case nir_intrinsic_ssbo_atomic_or:
4047 case nir_intrinsic_ssbo_atomic_xor:
4048 case nir_intrinsic_ssbo_atomic_exchange:
4049 case nir_intrinsic_ssbo_atomic_comp_swap:
4050 result = visit_atomic_ssbo(ctx->nctx, instr);
4051 break;
4052 case nir_intrinsic_load_ubo:
4053 result = visit_load_ubo_buffer(ctx, instr);
4054 break;
4055 case nir_intrinsic_get_buffer_size:
4056 result = visit_get_buffer_size(ctx, instr);
4057 break;
4058 case nir_intrinsic_load_var:
4059 result = visit_load_var(ctx, instr);
4060 break;
4061 case nir_intrinsic_store_var:
4062 visit_store_var(ctx, instr);
4063 break;
4064 case nir_intrinsic_image_load:
4065 result = visit_image_load(ctx->nctx, instr);
4066 break;
4067 case nir_intrinsic_image_store:
4068 visit_image_store(ctx->nctx, instr);
4069 break;
4070 case nir_intrinsic_image_atomic_add:
4071 case nir_intrinsic_image_atomic_min:
4072 case nir_intrinsic_image_atomic_max:
4073 case nir_intrinsic_image_atomic_and:
4074 case nir_intrinsic_image_atomic_or:
4075 case nir_intrinsic_image_atomic_xor:
4076 case nir_intrinsic_image_atomic_exchange:
4077 case nir_intrinsic_image_atomic_comp_swap:
4078 result = visit_image_atomic(ctx->nctx, instr);
4079 break;
4080 case nir_intrinsic_image_size:
4081 result = visit_image_size(ctx, instr);
4082 break;
4083 case nir_intrinsic_discard:
4084 ctx->nctx->shader_info->fs.can_discard = true;
4085 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4086 LLVMVoidTypeInContext(ctx->ac.context),
4087 NULL, 0, AC_FUNC_ATTR_LEGACY);
4088 break;
4089 case nir_intrinsic_discard_if:
4090 emit_discard_if(ctx->nctx, instr);
4091 break;
4092 case nir_intrinsic_memory_barrier:
4093 emit_waitcnt(ctx->nctx, VM_CNT);
4094 break;
4095 case nir_intrinsic_barrier:
4096 emit_barrier(ctx->nctx);
4097 break;
4098 case nir_intrinsic_var_atomic_add:
4099 case nir_intrinsic_var_atomic_imin:
4100 case nir_intrinsic_var_atomic_umin:
4101 case nir_intrinsic_var_atomic_imax:
4102 case nir_intrinsic_var_atomic_umax:
4103 case nir_intrinsic_var_atomic_and:
4104 case nir_intrinsic_var_atomic_or:
4105 case nir_intrinsic_var_atomic_xor:
4106 case nir_intrinsic_var_atomic_exchange:
4107 case nir_intrinsic_var_atomic_comp_swap:
4108 result = visit_var_atomic(ctx->nctx, instr);
4109 break;
4110 case nir_intrinsic_interp_var_at_centroid:
4111 case nir_intrinsic_interp_var_at_sample:
4112 case nir_intrinsic_interp_var_at_offset:
4113 result = visit_interp(ctx->nctx, instr);
4114 break;
4115 case nir_intrinsic_emit_vertex:
4116 visit_emit_vertex(ctx->nctx, instr);
4117 break;
4118 case nir_intrinsic_end_primitive:
4119 visit_end_primitive(ctx->nctx, instr);
4120 break;
4121 case nir_intrinsic_load_tess_coord:
4122 result = visit_load_tess_coord(ctx->nctx, instr);
4123 break;
4124 case nir_intrinsic_load_patch_vertices_in:
4125 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4126 break;
4127 default:
4128 fprintf(stderr, "Unknown intrinsic: ");
4129 nir_print_instr(&instr->instr, stderr);
4130 fprintf(stderr, "\n");
4131 break;
4132 }
4133 if (result) {
4134 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4135 }
4136 }
4137
4138 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4139 unsigned descriptor_set,
4140 unsigned base_index,
4141 unsigned constant_index,
4142 LLVMValueRef index,
4143 enum ac_descriptor_type desc_type)
4144 {
4145 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4146 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4147 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4148 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4149 unsigned offset = binding->offset;
4150 unsigned stride = binding->size;
4151 unsigned type_size;
4152 LLVMBuilderRef builder = ctx->builder;
4153 LLVMTypeRef type;
4154
4155 assert(base_index < layout->binding_count);
4156
4157 switch (desc_type) {
4158 case AC_DESC_IMAGE:
4159 type = ctx->v8i32;
4160 type_size = 32;
4161 break;
4162 case AC_DESC_FMASK:
4163 type = ctx->v8i32;
4164 offset += 32;
4165 type_size = 32;
4166 break;
4167 case AC_DESC_SAMPLER:
4168 type = ctx->v4i32;
4169 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4170 offset += 64;
4171
4172 type_size = 16;
4173 break;
4174 case AC_DESC_BUFFER:
4175 type = ctx->v4i32;
4176 type_size = 16;
4177 break;
4178 default:
4179 unreachable("invalid desc_type\n");
4180 }
4181
4182 offset += constant_index * stride;
4183
4184 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4185 (!index || binding->immutable_samplers_equal)) {
4186 if (binding->immutable_samplers_equal)
4187 constant_index = 0;
4188
4189 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4190
4191 LLVMValueRef constants[] = {
4192 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4193 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4194 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4195 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4196 };
4197 return ac_build_gather_values(&ctx->ac, constants, 4);
4198 }
4199
4200 assert(stride % type_size == 0);
4201
4202 if (!index)
4203 index = ctx->i32zero;
4204
4205 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4206
4207 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4208 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4209
4210 return ac_build_indexed_load_const(&ctx->ac, list, index);
4211 }
4212
4213 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
4214 const nir_deref_var *deref,
4215 enum ac_descriptor_type desc_type)
4216 {
4217 LLVMValueRef index = NULL;
4218 unsigned constant_index = 0;
4219
4220 if (deref->deref.child) {
4221 const nir_deref_array *child =
4222 (const nir_deref_array *)deref->deref.child;
4223
4224 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4225 if (child->deref_array_type == nir_deref_array_type_indirect) {
4226 index = get_src(ctx->nir, child->indirect);
4227 }
4228
4229 constant_index = child->base_offset;
4230 }
4231
4232 return ctx->abi.load_sampler_desc(&ctx->abi,
4233 deref->var->data.descriptor_set,
4234 deref->var->data.binding,
4235 constant_index, index,
4236 desc_type);
4237 }
4238
4239 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4240 struct ac_image_args *args,
4241 const nir_tex_instr *instr,
4242 nir_texop op,
4243 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4244 LLVMValueRef *param, unsigned count,
4245 unsigned dmask)
4246 {
4247 unsigned is_rect = 0;
4248 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4249
4250 if (op == nir_texop_lod)
4251 da = false;
4252 /* Pad to power of two vector */
4253 while (count < util_next_power_of_two(count))
4254 param[count++] = LLVMGetUndef(ctx->i32);
4255
4256 if (count > 1)
4257 args->addr = ac_build_gather_values(ctx, param, count);
4258 else
4259 args->addr = param[0];
4260
4261 args->resource = res_ptr;
4262 args->sampler = samp_ptr;
4263
4264 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4265 args->addr = param[0];
4266 return;
4267 }
4268
4269 args->dmask = dmask;
4270 args->unorm = is_rect;
4271 args->da = da;
4272 }
4273
4274 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4275 *
4276 * SI-CI:
4277 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4278 * filtering manually. The driver sets img7 to a mask clearing
4279 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4280 * s_and_b32 samp0, samp0, img7
4281 *
4282 * VI:
4283 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4284 */
4285 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4286 LLVMValueRef res, LLVMValueRef samp)
4287 {
4288 LLVMBuilderRef builder = ctx->builder;
4289 LLVMValueRef img7, samp0;
4290
4291 if (ctx->options->chip_class >= VI)
4292 return samp;
4293
4294 img7 = LLVMBuildExtractElement(builder, res,
4295 LLVMConstInt(ctx->i32, 7, 0), "");
4296 samp0 = LLVMBuildExtractElement(builder, samp,
4297 LLVMConstInt(ctx->i32, 0, 0), "");
4298 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4299 return LLVMBuildInsertElement(builder, samp, samp0,
4300 LLVMConstInt(ctx->i32, 0, 0), "");
4301 }
4302
4303 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4304 nir_tex_instr *instr,
4305 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4306 LLVMValueRef *fmask_ptr)
4307 {
4308 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4309 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER);
4310 else
4311 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE);
4312 if (samp_ptr) {
4313 if (instr->sampler)
4314 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER);
4315 else
4316 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER);
4317 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4318 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4319 }
4320 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4321 instr->op == nir_texop_samples_identical))
4322 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK);
4323 }
4324
4325 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4326 LLVMValueRef coord)
4327 {
4328 coord = to_float(ctx, coord);
4329 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4330 coord = to_integer(ctx, coord);
4331 return coord;
4332 }
4333
4334 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4335 {
4336 LLVMValueRef result = NULL;
4337 struct ac_image_args args = { 0 };
4338 unsigned dmask = 0xf;
4339 LLVMValueRef address[16];
4340 LLVMValueRef coords[5];
4341 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4342 LLVMValueRef bias = NULL, offsets = NULL;
4343 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4344 LLVMValueRef ddx = NULL, ddy = NULL;
4345 LLVMValueRef derivs[6];
4346 unsigned chan, count = 0;
4347 unsigned const_src = 0, num_deriv_comp = 0;
4348 bool lod_is_zero = false;
4349
4350 tex_fetch_ptrs(ctx->nctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4351
4352 for (unsigned i = 0; i < instr->num_srcs; i++) {
4353 switch (instr->src[i].src_type) {
4354 case nir_tex_src_coord:
4355 coord = get_src(ctx, instr->src[i].src);
4356 break;
4357 case nir_tex_src_projector:
4358 break;
4359 case nir_tex_src_comparator:
4360 comparator = get_src(ctx, instr->src[i].src);
4361 break;
4362 case nir_tex_src_offset:
4363 offsets = get_src(ctx, instr->src[i].src);
4364 const_src = i;
4365 break;
4366 case nir_tex_src_bias:
4367 bias = get_src(ctx, instr->src[i].src);
4368 break;
4369 case nir_tex_src_lod: {
4370 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4371
4372 if (val && val->i32[0] == 0)
4373 lod_is_zero = true;
4374 lod = get_src(ctx, instr->src[i].src);
4375 break;
4376 }
4377 case nir_tex_src_ms_index:
4378 sample_index = get_src(ctx, instr->src[i].src);
4379 break;
4380 case nir_tex_src_ms_mcs:
4381 break;
4382 case nir_tex_src_ddx:
4383 ddx = get_src(ctx, instr->src[i].src);
4384 num_deriv_comp = instr->src[i].src.ssa->num_components;
4385 break;
4386 case nir_tex_src_ddy:
4387 ddy = get_src(ctx, instr->src[i].src);
4388 break;
4389 case nir_tex_src_texture_offset:
4390 case nir_tex_src_sampler_offset:
4391 case nir_tex_src_plane:
4392 default:
4393 break;
4394 }
4395 }
4396
4397 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4398 result = get_buffer_size(ctx, res_ptr, true);
4399 goto write_result;
4400 }
4401
4402 if (instr->op == nir_texop_texture_samples) {
4403 LLVMValueRef res, samples, is_msaa;
4404 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4405 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4406 LLVMConstInt(ctx->ac.i32, 3, false), "");
4407 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4408 LLVMConstInt(ctx->ac.i32, 28, false), "");
4409 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4410 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4411 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4412 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4413
4414 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4415 LLVMConstInt(ctx->ac.i32, 16, false), "");
4416 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4417 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4418 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4419 samples, "");
4420 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4421 ctx->ac.i32_1, "");
4422 result = samples;
4423 goto write_result;
4424 }
4425
4426 if (coord)
4427 for (chan = 0; chan < instr->coord_components; chan++)
4428 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4429
4430 if (offsets && instr->op != nir_texop_txf) {
4431 LLVMValueRef offset[3], pack;
4432 for (chan = 0; chan < 3; ++chan)
4433 offset[chan] = ctx->ac.i32_0;
4434
4435 args.offset = true;
4436 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4437 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4438 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4439 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4440 if (chan)
4441 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4442 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4443 }
4444 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4445 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4446 address[count++] = pack;
4447
4448 }
4449 /* pack LOD bias value */
4450 if (instr->op == nir_texop_txb && bias) {
4451 address[count++] = bias;
4452 }
4453
4454 /* Pack depth comparison value */
4455 if (instr->is_shadow && comparator) {
4456 address[count++] = llvm_extract_elem(&ctx->ac, comparator, 0);
4457 }
4458
4459 /* pack derivatives */
4460 if (ddx || ddy) {
4461 switch (instr->sampler_dim) {
4462 case GLSL_SAMPLER_DIM_3D:
4463 case GLSL_SAMPLER_DIM_CUBE:
4464 num_deriv_comp = 3;
4465 break;
4466 case GLSL_SAMPLER_DIM_2D:
4467 default:
4468 num_deriv_comp = 2;
4469 break;
4470 case GLSL_SAMPLER_DIM_1D:
4471 num_deriv_comp = 1;
4472 break;
4473 }
4474
4475 for (unsigned i = 0; i < num_deriv_comp; i++) {
4476 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4477 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4478 }
4479 }
4480
4481 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4482 if (instr->is_array && instr->op != nir_texop_lod)
4483 coords[3] = apply_round_slice(&ctx->ac, coords[3]);
4484 for (chan = 0; chan < instr->coord_components; chan++)
4485 coords[chan] = to_float(&ctx->ac, coords[chan]);
4486 if (instr->coord_components == 3)
4487 coords[3] = LLVMGetUndef(ctx->ac.f32);
4488 ac_prepare_cube_coords(&ctx->ac,
4489 instr->op == nir_texop_txd, instr->is_array,
4490 coords, derivs);
4491 if (num_deriv_comp)
4492 num_deriv_comp--;
4493 }
4494
4495 if (ddx || ddy) {
4496 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4497 address[count++] = derivs[i];
4498 }
4499
4500 /* Pack texture coordinates */
4501 if (coord) {
4502 address[count++] = coords[0];
4503 if (instr->coord_components > 1) {
4504 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4505 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4506 }
4507 address[count++] = coords[1];
4508 }
4509 if (instr->coord_components > 2) {
4510 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4511 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4512 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4513 instr->op != nir_texop_txf) {
4514 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4515 }
4516 address[count++] = coords[2];
4517 }
4518 }
4519
4520 /* Pack LOD */
4521 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4522 instr->op == nir_texop_txf)) {
4523 address[count++] = lod;
4524 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4525 address[count++] = sample_index;
4526 } else if(instr->op == nir_texop_txs) {
4527 count = 0;
4528 if (lod)
4529 address[count++] = lod;
4530 else
4531 address[count++] = ctx->ac.i32_0;
4532 }
4533
4534 for (chan = 0; chan < count; chan++) {
4535 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4536 address[chan], ctx->ac.i32, "");
4537 }
4538
4539 if (instr->op == nir_texop_samples_identical) {
4540 LLVMValueRef txf_address[4];
4541 struct ac_image_args txf_args = { 0 };
4542 unsigned txf_count = count;
4543 memcpy(txf_address, address, sizeof(txf_address));
4544
4545 if (!instr->is_array)
4546 txf_address[2] = ctx->ac.i32_0;
4547 txf_address[3] = ctx->ac.i32_0;
4548
4549 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4550 fmask_ptr, NULL,
4551 txf_address, txf_count, 0xf);
4552
4553 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4554
4555 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4556 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4557 goto write_result;
4558 }
4559
4560 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4561 instr->op != nir_texop_txs) {
4562 unsigned sample_chan = instr->is_array ? 3 : 2;
4563 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4564 address[0],
4565 address[1],
4566 instr->is_array ? address[2] : NULL,
4567 address[sample_chan],
4568 fmask_ptr);
4569 }
4570
4571 if (offsets && instr->op == nir_texop_txf) {
4572 nir_const_value *const_offset =
4573 nir_src_as_const_value(instr->src[const_src].src);
4574 int num_offsets = instr->src[const_src].src.ssa->num_components;
4575 assert(const_offset);
4576 num_offsets = MIN2(num_offsets, instr->coord_components);
4577 if (num_offsets > 2)
4578 address[2] = LLVMBuildAdd(ctx->ac.builder,
4579 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4580 if (num_offsets > 1)
4581 address[1] = LLVMBuildAdd(ctx->ac.builder,
4582 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4583 address[0] = LLVMBuildAdd(ctx->ac.builder,
4584 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4585
4586 }
4587
4588 /* TODO TG4 support */
4589 if (instr->op == nir_texop_tg4) {
4590 if (instr->is_shadow)
4591 dmask = 1;
4592 else
4593 dmask = 1 << instr->component;
4594 }
4595 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4596 res_ptr, samp_ptr, address, count, dmask);
4597
4598 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4599
4600 if (instr->op == nir_texop_query_levels)
4601 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4602 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4603 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4604 else if (instr->op == nir_texop_txs &&
4605 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4606 instr->is_array) {
4607 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4608 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4609 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4610 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4611 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4612 } else if (instr->dest.ssa.num_components != 4)
4613 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4614
4615 write_result:
4616 if (result) {
4617 assert(instr->dest.is_ssa);
4618 result = to_integer(&ctx->ac, result);
4619 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4620 }
4621 }
4622
4623
4624 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4625 {
4626 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4627 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4628
4629 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4630 _mesa_hash_table_insert(ctx->phis, instr, result);
4631 }
4632
4633 static void visit_post_phi(struct ac_nir_context *ctx,
4634 nir_phi_instr *instr,
4635 LLVMValueRef llvm_phi)
4636 {
4637 nir_foreach_phi_src(src, instr) {
4638 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4639 LLVMValueRef llvm_src = get_src(ctx, src->src);
4640
4641 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4642 }
4643 }
4644
4645 static void phi_post_pass(struct ac_nir_context *ctx)
4646 {
4647 struct hash_entry *entry;
4648 hash_table_foreach(ctx->phis, entry) {
4649 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4650 (LLVMValueRef)entry->data);
4651 }
4652 }
4653
4654
4655 static void visit_ssa_undef(struct ac_nir_context *ctx,
4656 const nir_ssa_undef_instr *instr)
4657 {
4658 unsigned num_components = instr->def.num_components;
4659 LLVMValueRef undef;
4660
4661 if (num_components == 1)
4662 undef = LLVMGetUndef(ctx->ac.i32);
4663 else {
4664 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4665 }
4666 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4667 }
4668
4669 static void visit_jump(struct ac_nir_context *ctx,
4670 const nir_jump_instr *instr)
4671 {
4672 switch (instr->type) {
4673 case nir_jump_break:
4674 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4675 LLVMClearInsertionPosition(ctx->ac.builder);
4676 break;
4677 case nir_jump_continue:
4678 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4679 LLVMClearInsertionPosition(ctx->ac.builder);
4680 break;
4681 default:
4682 fprintf(stderr, "Unknown NIR jump instr: ");
4683 nir_print_instr(&instr->instr, stderr);
4684 fprintf(stderr, "\n");
4685 abort();
4686 }
4687 }
4688
4689 static void visit_cf_list(struct ac_nir_context *ctx,
4690 struct exec_list *list);
4691
4692 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4693 {
4694 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4695 nir_foreach_instr(instr, block)
4696 {
4697 switch (instr->type) {
4698 case nir_instr_type_alu:
4699 visit_alu(ctx, nir_instr_as_alu(instr));
4700 break;
4701 case nir_instr_type_load_const:
4702 visit_load_const(ctx, nir_instr_as_load_const(instr));
4703 break;
4704 case nir_instr_type_intrinsic:
4705 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4706 break;
4707 case nir_instr_type_tex:
4708 visit_tex(ctx, nir_instr_as_tex(instr));
4709 break;
4710 case nir_instr_type_phi:
4711 visit_phi(ctx, nir_instr_as_phi(instr));
4712 break;
4713 case nir_instr_type_ssa_undef:
4714 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4715 break;
4716 case nir_instr_type_jump:
4717 visit_jump(ctx, nir_instr_as_jump(instr));
4718 break;
4719 default:
4720 fprintf(stderr, "Unknown NIR instr type: ");
4721 nir_print_instr(instr, stderr);
4722 fprintf(stderr, "\n");
4723 abort();
4724 }
4725 }
4726
4727 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4728 }
4729
4730 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4731 {
4732 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4733
4734 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4735 LLVMBasicBlockRef merge_block =
4736 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4737 LLVMBasicBlockRef if_block =
4738 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4739 LLVMBasicBlockRef else_block = merge_block;
4740 if (!exec_list_is_empty(&if_stmt->else_list))
4741 else_block = LLVMAppendBasicBlockInContext(
4742 ctx->ac.context, fn, "");
4743
4744 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4745 LLVMConstInt(ctx->ac.i32, 0, false), "");
4746 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4747
4748 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4749 visit_cf_list(ctx, &if_stmt->then_list);
4750 if (LLVMGetInsertBlock(ctx->ac.builder))
4751 LLVMBuildBr(ctx->ac.builder, merge_block);
4752
4753 if (!exec_list_is_empty(&if_stmt->else_list)) {
4754 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4755 visit_cf_list(ctx, &if_stmt->else_list);
4756 if (LLVMGetInsertBlock(ctx->ac.builder))
4757 LLVMBuildBr(ctx->ac.builder, merge_block);
4758 }
4759
4760 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4761 }
4762
4763 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4764 {
4765 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4766 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4767 LLVMBasicBlockRef break_parent = ctx->break_block;
4768
4769 ctx->continue_block =
4770 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4771 ctx->break_block =
4772 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4773
4774 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4775 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4776 visit_cf_list(ctx, &loop->body);
4777
4778 if (LLVMGetInsertBlock(ctx->ac.builder))
4779 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4780 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4781
4782 ctx->continue_block = continue_parent;
4783 ctx->break_block = break_parent;
4784 }
4785
4786 static void visit_cf_list(struct ac_nir_context *ctx,
4787 struct exec_list *list)
4788 {
4789 foreach_list_typed(nir_cf_node, node, node, list)
4790 {
4791 switch (node->type) {
4792 case nir_cf_node_block:
4793 visit_block(ctx, nir_cf_node_as_block(node));
4794 break;
4795
4796 case nir_cf_node_if:
4797 visit_if(ctx, nir_cf_node_as_if(node));
4798 break;
4799
4800 case nir_cf_node_loop:
4801 visit_loop(ctx, nir_cf_node_as_loop(node));
4802 break;
4803
4804 default:
4805 assert(0);
4806 }
4807 }
4808 }
4809
4810 static void
4811 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4812 struct nir_variable *variable)
4813 {
4814 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4815 LLVMValueRef t_offset;
4816 LLVMValueRef t_list;
4817 LLVMValueRef input;
4818 LLVMValueRef buffer_index;
4819 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4820 int idx = variable->data.location;
4821 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4822
4823 variable->data.driver_location = idx * 4;
4824
4825 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4826 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4827 ctx->abi.start_instance, "");
4828 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4829 ctx->shader_info->vs.vgpr_comp_cnt);
4830 } else
4831 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4832 ctx->abi.base_vertex, "");
4833
4834 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4835 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4836
4837 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4838
4839 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4840 buffer_index,
4841 LLVMConstInt(ctx->i32, 0, false),
4842 true);
4843
4844 for (unsigned chan = 0; chan < 4; chan++) {
4845 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4846 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4847 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4848 input, llvm_chan, ""));
4849 }
4850 }
4851 }
4852
4853 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4854 unsigned attr,
4855 LLVMValueRef interp_param,
4856 LLVMValueRef prim_mask,
4857 LLVMValueRef result[4])
4858 {
4859 LLVMValueRef attr_number;
4860 unsigned chan;
4861 LLVMValueRef i, j;
4862 bool interp = interp_param != NULL;
4863
4864 attr_number = LLVMConstInt(ctx->i32, attr, false);
4865
4866 /* fs.constant returns the param from the middle vertex, so it's not
4867 * really useful for flat shading. It's meant to be used for custom
4868 * interpolation (but the intrinsic can't fetch from the other two
4869 * vertices).
4870 *
4871 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4872 * to do the right thing. The only reason we use fs.constant is that
4873 * fs.interp cannot be used on integers, because they can be equal
4874 * to NaN.
4875 */
4876 if (interp) {
4877 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4878 LLVMVectorType(ctx->f32, 2), "");
4879
4880 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4881 ctx->i32zero, "");
4882 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4883 ctx->i32one, "");
4884 }
4885
4886 for (chan = 0; chan < 4; chan++) {
4887 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4888
4889 if (interp) {
4890 result[chan] = ac_build_fs_interp(&ctx->ac,
4891 llvm_chan,
4892 attr_number,
4893 prim_mask, i, j);
4894 } else {
4895 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4896 LLVMConstInt(ctx->i32, 2, false),
4897 llvm_chan,
4898 attr_number,
4899 prim_mask);
4900 }
4901 }
4902 }
4903
4904 static void
4905 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4906 struct nir_variable *variable)
4907 {
4908 int idx = variable->data.location;
4909 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4910 LLVMValueRef interp;
4911
4912 variable->data.driver_location = idx * 4;
4913 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4914
4915 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4916 unsigned interp_type;
4917 if (variable->data.sample) {
4918 interp_type = INTERP_SAMPLE;
4919 ctx->shader_info->fs.force_persample = true;
4920 } else if (variable->data.centroid)
4921 interp_type = INTERP_CENTROID;
4922 else
4923 interp_type = INTERP_CENTER;
4924
4925 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4926 } else
4927 interp = NULL;
4928
4929 for (unsigned i = 0; i < attrib_count; ++i)
4930 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4931
4932 }
4933
4934 static void
4935 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4936 struct nir_variable *variable)
4937 {
4938 switch (ctx->stage) {
4939 case MESA_SHADER_VERTEX:
4940 handle_vs_input_decl(ctx, variable);
4941 break;
4942 case MESA_SHADER_FRAGMENT:
4943 handle_fs_input_decl(ctx, variable);
4944 break;
4945 default:
4946 break;
4947 }
4948
4949 }
4950
4951 static void
4952 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4953 struct nir_shader *nir)
4954 {
4955 unsigned index = 0;
4956 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4957 LLVMValueRef interp_param;
4958 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4959
4960 if (!(ctx->input_mask & (1ull << i)))
4961 continue;
4962
4963 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4964 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4965 interp_param = *inputs;
4966 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4967 inputs);
4968
4969 if (!interp_param)
4970 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4971 ++index;
4972 } else if (i == VARYING_SLOT_POS) {
4973 for(int i = 0; i < 3; ++i)
4974 inputs[i] = ctx->frag_pos[i];
4975
4976 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4977 }
4978 }
4979 ctx->shader_info->fs.num_interp = index;
4980 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4981 ctx->shader_info->fs.has_pcoord = true;
4982 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4983 ctx->shader_info->fs.prim_id_input = true;
4984 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4985 ctx->shader_info->fs.layer_input = true;
4986 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4987 }
4988
4989 static LLVMValueRef
4990 ac_build_alloca(struct ac_llvm_context *ac,
4991 LLVMTypeRef type,
4992 const char *name)
4993 {
4994 LLVMBuilderRef builder = ac->builder;
4995 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4996 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4997 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4998 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4999 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5000 LLVMValueRef res;
5001
5002 if (first_instr) {
5003 LLVMPositionBuilderBefore(first_builder, first_instr);
5004 } else {
5005 LLVMPositionBuilderAtEnd(first_builder, first_block);
5006 }
5007
5008 res = LLVMBuildAlloca(first_builder, type, name);
5009 LLVMBuildStore(builder, LLVMConstNull(type), res);
5010
5011 LLVMDisposeBuilder(first_builder);
5012
5013 return res;
5014 }
5015
5016 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5017 LLVMTypeRef type,
5018 const char *name)
5019 {
5020 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5021 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5022 return ptr;
5023 }
5024
5025 static void
5026 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5027 struct nir_variable *variable)
5028 {
5029 int idx = variable->data.location + variable->data.index;
5030 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5031 uint64_t mask_attribs;
5032
5033 variable->data.driver_location = idx * 4;
5034
5035 /* tess ctrl has it's own load/store paths for outputs */
5036 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5037 return;
5038
5039 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5040 if (ctx->stage == MESA_SHADER_VERTEX ||
5041 ctx->stage == MESA_SHADER_TESS_EVAL ||
5042 ctx->stage == MESA_SHADER_GEOMETRY) {
5043 if (idx == VARYING_SLOT_CLIP_DIST0) {
5044 int length = ctx->num_output_clips + ctx->num_output_culls;
5045 if (ctx->stage == MESA_SHADER_VERTEX) {
5046 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5047 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5048 }
5049 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5050 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5051 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5052 }
5053
5054 if (length > 4)
5055 attrib_count = 2;
5056 else
5057 attrib_count = 1;
5058 mask_attribs = 1ull << idx;
5059 }
5060 }
5061
5062 ctx->output_mask |= mask_attribs;
5063 }
5064
5065 static void
5066 handle_shader_output_decl(struct ac_nir_context *ctx,
5067 struct nir_shader *nir,
5068 struct nir_variable *variable)
5069 {
5070 unsigned output_loc = variable->data.driver_location / 4;
5071 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5072
5073 /* tess ctrl has it's own load/store paths for outputs */
5074 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5075 return;
5076
5077 if (ctx->stage == MESA_SHADER_VERTEX ||
5078 ctx->stage == MESA_SHADER_TESS_EVAL ||
5079 ctx->stage == MESA_SHADER_GEOMETRY) {
5080 int idx = variable->data.location + variable->data.index;
5081 if (idx == VARYING_SLOT_CLIP_DIST0) {
5082 int length = nir->info.clip_distance_array_size +
5083 nir->info.cull_distance_array_size;
5084
5085 if (length > 4)
5086 attrib_count = 2;
5087 else
5088 attrib_count = 1;
5089 }
5090 }
5091
5092 for (unsigned i = 0; i < attrib_count; ++i) {
5093 for (unsigned chan = 0; chan < 4; chan++) {
5094 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5095 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5096 }
5097 }
5098 }
5099
5100 static LLVMTypeRef
5101 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5102 enum glsl_base_type type)
5103 {
5104 switch (type) {
5105 case GLSL_TYPE_INT:
5106 case GLSL_TYPE_UINT:
5107 case GLSL_TYPE_BOOL:
5108 case GLSL_TYPE_SUBROUTINE:
5109 return ctx->i32;
5110 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5111 return ctx->f32;
5112 case GLSL_TYPE_INT64:
5113 case GLSL_TYPE_UINT64:
5114 return ctx->i64;
5115 case GLSL_TYPE_DOUBLE:
5116 return ctx->f64;
5117 default:
5118 unreachable("unknown GLSL type");
5119 }
5120 }
5121
5122 static LLVMTypeRef
5123 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5124 const struct glsl_type *type)
5125 {
5126 if (glsl_type_is_scalar(type)) {
5127 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5128 }
5129
5130 if (glsl_type_is_vector(type)) {
5131 return LLVMVectorType(
5132 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5133 glsl_get_vector_elements(type));
5134 }
5135
5136 if (glsl_type_is_matrix(type)) {
5137 return LLVMArrayType(
5138 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5139 glsl_get_matrix_columns(type));
5140 }
5141
5142 if (glsl_type_is_array(type)) {
5143 return LLVMArrayType(
5144 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5145 glsl_get_length(type));
5146 }
5147
5148 assert(glsl_type_is_struct(type));
5149
5150 LLVMTypeRef member_types[glsl_get_length(type)];
5151
5152 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5153 member_types[i] =
5154 glsl_to_llvm_type(ctx,
5155 glsl_get_struct_field(type, i));
5156 }
5157
5158 return LLVMStructTypeInContext(ctx->context, member_types,
5159 glsl_get_length(type), false);
5160 }
5161
5162 static void
5163 setup_locals(struct ac_nir_context *ctx,
5164 struct nir_function *func)
5165 {
5166 int i, j;
5167 ctx->num_locals = 0;
5168 nir_foreach_variable(variable, &func->impl->locals) {
5169 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5170 variable->data.driver_location = ctx->num_locals * 4;
5171 ctx->num_locals += attrib_count;
5172 }
5173 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5174 if (!ctx->locals)
5175 return;
5176
5177 for (i = 0; i < ctx->num_locals; i++) {
5178 for (j = 0; j < 4; j++) {
5179 ctx->locals[i * 4 + j] =
5180 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5181 }
5182 }
5183 }
5184
5185 static void
5186 setup_shared(struct ac_nir_context *ctx,
5187 struct nir_shader *nir)
5188 {
5189 nir_foreach_variable(variable, &nir->shared) {
5190 LLVMValueRef shared =
5191 LLVMAddGlobalInAddressSpace(
5192 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5193 variable->name ? variable->name : "",
5194 LOCAL_ADDR_SPACE);
5195 _mesa_hash_table_insert(ctx->vars, variable, shared);
5196 }
5197 }
5198
5199 static LLVMValueRef
5200 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5201 {
5202 v = to_float(ctx, v);
5203 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5204 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5205 }
5206
5207
5208 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5209 LLVMValueRef src0, LLVMValueRef src1)
5210 {
5211 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5212 LLVMValueRef comp[2];
5213
5214 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5215 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5216 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5217 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5218 }
5219
5220 /* Initialize arguments for the shader export intrinsic */
5221 static void
5222 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5223 LLVMValueRef *values,
5224 unsigned target,
5225 struct ac_export_args *args)
5226 {
5227 /* Default is 0xf. Adjusted below depending on the format. */
5228 args->enabled_channels = 0xf;
5229
5230 /* Specify whether the EXEC mask represents the valid mask */
5231 args->valid_mask = 0;
5232
5233 /* Specify whether this is the last export */
5234 args->done = 0;
5235
5236 /* Specify the target we are exporting */
5237 args->target = target;
5238
5239 args->compr = false;
5240 args->out[0] = LLVMGetUndef(ctx->f32);
5241 args->out[1] = LLVMGetUndef(ctx->f32);
5242 args->out[2] = LLVMGetUndef(ctx->f32);
5243 args->out[3] = LLVMGetUndef(ctx->f32);
5244
5245 if (!values)
5246 return;
5247
5248 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5249 LLVMValueRef val[4];
5250 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5251 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5252 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5253
5254 switch(col_format) {
5255 case V_028714_SPI_SHADER_ZERO:
5256 args->enabled_channels = 0; /* writemask */
5257 args->target = V_008DFC_SQ_EXP_NULL;
5258 break;
5259
5260 case V_028714_SPI_SHADER_32_R:
5261 args->enabled_channels = 1;
5262 args->out[0] = values[0];
5263 break;
5264
5265 case V_028714_SPI_SHADER_32_GR:
5266 args->enabled_channels = 0x3;
5267 args->out[0] = values[0];
5268 args->out[1] = values[1];
5269 break;
5270
5271 case V_028714_SPI_SHADER_32_AR:
5272 args->enabled_channels = 0x9;
5273 args->out[0] = values[0];
5274 args->out[3] = values[3];
5275 break;
5276
5277 case V_028714_SPI_SHADER_FP16_ABGR:
5278 args->compr = 1;
5279
5280 for (unsigned chan = 0; chan < 2; chan++) {
5281 LLVMValueRef pack_args[2] = {
5282 values[2 * chan],
5283 values[2 * chan + 1]
5284 };
5285 LLVMValueRef packed;
5286
5287 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5288 args->out[chan] = packed;
5289 }
5290 break;
5291
5292 case V_028714_SPI_SHADER_UNORM16_ABGR:
5293 for (unsigned chan = 0; chan < 4; chan++) {
5294 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5295 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5296 LLVMConstReal(ctx->f32, 65535), "");
5297 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5298 LLVMConstReal(ctx->f32, 0.5), "");
5299 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5300 ctx->i32, "");
5301 }
5302
5303 args->compr = 1;
5304 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5305 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5306 break;
5307
5308 case V_028714_SPI_SHADER_SNORM16_ABGR:
5309 for (unsigned chan = 0; chan < 4; chan++) {
5310 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5311 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5312 LLVMConstReal(ctx->f32, 32767), "");
5313
5314 /* If positive, add 0.5, else add -0.5. */
5315 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5316 LLVMBuildSelect(ctx->builder,
5317 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5318 val[chan], ctx->f32zero, ""),
5319 LLVMConstReal(ctx->f32, 0.5),
5320 LLVMConstReal(ctx->f32, -0.5), ""), "");
5321 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5322 }
5323
5324 args->compr = 1;
5325 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5326 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5327 break;
5328
5329 case V_028714_SPI_SHADER_UINT16_ABGR: {
5330 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5331
5332 for (unsigned chan = 0; chan < 4; chan++) {
5333 val[chan] = to_integer(&ctx->ac, values[chan]);
5334 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], max);
5335 }
5336
5337 args->compr = 1;
5338 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5339 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5340 break;
5341 }
5342
5343 case V_028714_SPI_SHADER_SINT16_ABGR: {
5344 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5345 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5346
5347 /* Clamp. */
5348 for (unsigned chan = 0; chan < 4; chan++) {
5349 val[chan] = to_integer(&ctx->ac, values[chan]);
5350 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], max);
5351 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], min);
5352 }
5353
5354 args->compr = 1;
5355 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5356 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5357 break;
5358 }
5359
5360 default:
5361 case V_028714_SPI_SHADER_32_ABGR:
5362 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5363 break;
5364 }
5365 } else
5366 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5367
5368 for (unsigned i = 0; i < 4; ++i)
5369 args->out[i] = to_float(&ctx->ac, args->out[i]);
5370 }
5371
5372 static void
5373 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5374 bool export_prim_id,
5375 struct ac_vs_output_info *outinfo)
5376 {
5377 uint32_t param_count = 0;
5378 unsigned target;
5379 unsigned pos_idx, num_pos_exports = 0;
5380 struct ac_export_args args, pos_args[4] = {};
5381 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5382 int i;
5383
5384 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5385 sizeof(outinfo->vs_output_param_offset));
5386
5387 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5388 LLVMValueRef slots[8];
5389 unsigned j;
5390
5391 if (outinfo->cull_dist_mask)
5392 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5393
5394 i = VARYING_SLOT_CLIP_DIST0;
5395 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5396 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5397 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5398
5399 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5400 slots[i] = LLVMGetUndef(ctx->f32);
5401
5402 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5403 target = V_008DFC_SQ_EXP_POS + 3;
5404 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5405 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5406 &args, sizeof(args));
5407 }
5408
5409 target = V_008DFC_SQ_EXP_POS + 2;
5410 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5411 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5412 &args, sizeof(args));
5413
5414 }
5415
5416 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5417 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5418 for (unsigned j = 0; j < 4; j++)
5419 pos_values[j] = LLVMBuildLoad(ctx->builder,
5420 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5421 }
5422 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5423
5424 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5425 outinfo->writes_pointsize = true;
5426 psize_value = LLVMBuildLoad(ctx->builder,
5427 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5428 }
5429
5430 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5431 outinfo->writes_layer = true;
5432 layer_value = LLVMBuildLoad(ctx->builder,
5433 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5434 }
5435
5436 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5437 outinfo->writes_viewport_index = true;
5438 viewport_index_value = LLVMBuildLoad(ctx->builder,
5439 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5440 }
5441
5442 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5443 (outinfo->writes_layer == true ? 4 : 0) |
5444 (outinfo->writes_viewport_index == true ? 8 : 0));
5445 if (mask) {
5446 pos_args[1].enabled_channels = mask;
5447 pos_args[1].valid_mask = 0;
5448 pos_args[1].done = 0;
5449 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5450 pos_args[1].compr = 0;
5451 pos_args[1].out[0] = ctx->f32zero; /* X */
5452 pos_args[1].out[1] = ctx->f32zero; /* Y */
5453 pos_args[1].out[2] = ctx->f32zero; /* Z */
5454 pos_args[1].out[3] = ctx->f32zero; /* W */
5455
5456 if (outinfo->writes_pointsize == true)
5457 pos_args[1].out[0] = psize_value;
5458 if (outinfo->writes_layer == true)
5459 pos_args[1].out[2] = layer_value;
5460 if (outinfo->writes_viewport_index == true)
5461 pos_args[1].out[3] = viewport_index_value;
5462 }
5463 for (i = 0; i < 4; i++) {
5464 if (pos_args[i].out[0])
5465 num_pos_exports++;
5466 }
5467
5468 pos_idx = 0;
5469 for (i = 0; i < 4; i++) {
5470 if (!pos_args[i].out[0])
5471 continue;
5472
5473 /* Specify the target we are exporting */
5474 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5475 if (pos_idx == num_pos_exports)
5476 pos_args[i].done = 1;
5477 ac_build_export(&ctx->ac, &pos_args[i]);
5478 }
5479
5480 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5481 LLVMValueRef values[4];
5482 if (!(ctx->output_mask & (1ull << i)))
5483 continue;
5484
5485 for (unsigned j = 0; j < 4; j++)
5486 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5487 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5488
5489 if (i == VARYING_SLOT_LAYER) {
5490 target = V_008DFC_SQ_EXP_PARAM + param_count;
5491 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5492 param_count++;
5493 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5494 target = V_008DFC_SQ_EXP_PARAM + param_count;
5495 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5496 param_count++;
5497 } else if (i >= VARYING_SLOT_VAR0) {
5498 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5499 target = V_008DFC_SQ_EXP_PARAM + param_count;
5500 outinfo->vs_output_param_offset[i] = param_count;
5501 param_count++;
5502 } else
5503 continue;
5504
5505 si_llvm_init_export_args(ctx, values, target, &args);
5506
5507 if (target >= V_008DFC_SQ_EXP_POS &&
5508 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5509 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5510 &args, sizeof(args));
5511 } else {
5512 ac_build_export(&ctx->ac, &args);
5513 }
5514 }
5515
5516 if (export_prim_id) {
5517 LLVMValueRef values[4];
5518 target = V_008DFC_SQ_EXP_PARAM + param_count;
5519 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5520 param_count++;
5521
5522 values[0] = ctx->vs_prim_id;
5523 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5524 ctx->shader_info->vs.vgpr_comp_cnt);
5525 for (unsigned j = 1; j < 4; j++)
5526 values[j] = ctx->f32zero;
5527 si_llvm_init_export_args(ctx, values, target, &args);
5528 ac_build_export(&ctx->ac, &args);
5529 outinfo->export_prim_id = true;
5530 }
5531
5532 outinfo->pos_exports = num_pos_exports;
5533 outinfo->param_exports = param_count;
5534 }
5535
5536 static void
5537 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5538 struct ac_es_output_info *outinfo)
5539 {
5540 int j;
5541 uint64_t max_output_written = 0;
5542 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5543 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5544 int param_index;
5545 int length = 4;
5546
5547 if (!(ctx->output_mask & (1ull << i)))
5548 continue;
5549
5550 if (i == VARYING_SLOT_CLIP_DIST0)
5551 length = ctx->num_output_clips + ctx->num_output_culls;
5552
5553 param_index = shader_io_get_unique_index(i);
5554
5555 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5556
5557 for (j = 0; j < length; j++) {
5558 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5559 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5560
5561 ac_build_buffer_store_dword(&ctx->ac,
5562 ctx->esgs_ring,
5563 out_val, 1,
5564 NULL, ctx->es2gs_offset,
5565 (4 * param_index + j) * 4,
5566 1, 1, true, true);
5567 }
5568 }
5569 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5570 }
5571
5572 static void
5573 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5574 {
5575 LLVMValueRef vertex_id = ctx->rel_auto_id;
5576 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5577 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5578 vertex_dw_stride, "");
5579
5580 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5581 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5582 int length = 4;
5583
5584 if (!(ctx->output_mask & (1ull << i)))
5585 continue;
5586
5587 if (i == VARYING_SLOT_CLIP_DIST0)
5588 length = ctx->num_output_clips + ctx->num_output_culls;
5589 int param = shader_io_get_unique_index(i);
5590 mark_tess_output(ctx, false, param);
5591 if (length > 4)
5592 mark_tess_output(ctx, false, param + 1);
5593 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5594 LLVMConstInt(ctx->i32, param * 4, false),
5595 "");
5596 for (unsigned j = 0; j < length; j++) {
5597 lds_store(ctx, dw_addr,
5598 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5599 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5600 }
5601 }
5602 }
5603
5604 struct ac_build_if_state
5605 {
5606 struct nir_to_llvm_context *ctx;
5607 LLVMValueRef condition;
5608 LLVMBasicBlockRef entry_block;
5609 LLVMBasicBlockRef true_block;
5610 LLVMBasicBlockRef false_block;
5611 LLVMBasicBlockRef merge_block;
5612 };
5613
5614 static LLVMBasicBlockRef
5615 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5616 {
5617 LLVMBasicBlockRef current_block;
5618 LLVMBasicBlockRef next_block;
5619 LLVMBasicBlockRef new_block;
5620
5621 /* get current basic block */
5622 current_block = LLVMGetInsertBlock(ctx->builder);
5623
5624 /* chqeck if there's another block after this one */
5625 next_block = LLVMGetNextBasicBlock(current_block);
5626 if (next_block) {
5627 /* insert the new block before the next block */
5628 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5629 }
5630 else {
5631 /* append new block after current block */
5632 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5633 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5634 }
5635 return new_block;
5636 }
5637
5638 static void
5639 ac_nir_build_if(struct ac_build_if_state *ifthen,
5640 struct nir_to_llvm_context *ctx,
5641 LLVMValueRef condition)
5642 {
5643 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5644
5645 memset(ifthen, 0, sizeof *ifthen);
5646 ifthen->ctx = ctx;
5647 ifthen->condition = condition;
5648 ifthen->entry_block = block;
5649
5650 /* create endif/merge basic block for the phi functions */
5651 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5652
5653 /* create/insert true_block before merge_block */
5654 ifthen->true_block =
5655 LLVMInsertBasicBlockInContext(ctx->context,
5656 ifthen->merge_block,
5657 "if-true-block");
5658
5659 /* successive code goes into the true block */
5660 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5661 }
5662
5663 /**
5664 * End a conditional.
5665 */
5666 static void
5667 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5668 {
5669 LLVMBuilderRef builder = ifthen->ctx->builder;
5670
5671 /* Insert branch to the merge block from current block */
5672 LLVMBuildBr(builder, ifthen->merge_block);
5673
5674 /*
5675 * Now patch in the various branch instructions.
5676 */
5677
5678 /* Insert the conditional branch instruction at the end of entry_block */
5679 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5680 if (ifthen->false_block) {
5681 /* we have an else clause */
5682 LLVMBuildCondBr(builder, ifthen->condition,
5683 ifthen->true_block, ifthen->false_block);
5684 }
5685 else {
5686 /* no else clause */
5687 LLVMBuildCondBr(builder, ifthen->condition,
5688 ifthen->true_block, ifthen->merge_block);
5689 }
5690
5691 /* Resume building code at end of the ifthen->merge_block */
5692 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5693 }
5694
5695 static void
5696 write_tess_factors(struct nir_to_llvm_context *ctx)
5697 {
5698 unsigned stride, outer_comps, inner_comps;
5699 struct ac_build_if_state if_ctx, inner_if_ctx;
5700 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5701 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5702 unsigned tess_inner_index, tess_outer_index;
5703 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5704 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5705 int i;
5706 emit_barrier(ctx);
5707
5708 switch (ctx->options->key.tcs.primitive_mode) {
5709 case GL_ISOLINES:
5710 stride = 2;
5711 outer_comps = 2;
5712 inner_comps = 0;
5713 break;
5714 case GL_TRIANGLES:
5715 stride = 4;
5716 outer_comps = 3;
5717 inner_comps = 1;
5718 break;
5719 case GL_QUADS:
5720 stride = 6;
5721 outer_comps = 4;
5722 inner_comps = 2;
5723 break;
5724 default:
5725 return;
5726 }
5727
5728 ac_nir_build_if(&if_ctx, ctx,
5729 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5730 invocation_id, ctx->i32zero, ""));
5731
5732 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5733 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5734
5735 mark_tess_output(ctx, true, tess_inner_index);
5736 mark_tess_output(ctx, true, tess_outer_index);
5737 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5738 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5739 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5740 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5741 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5742
5743 for (i = 0; i < 4; i++) {
5744 inner[i] = LLVMGetUndef(ctx->i32);
5745 outer[i] = LLVMGetUndef(ctx->i32);
5746 }
5747
5748 // LINES reverseal
5749 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5750 outer[0] = out[1] = lds_load(ctx, lds_outer);
5751 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5752 LLVMConstInt(ctx->i32, 1, false), "");
5753 outer[1] = out[0] = lds_load(ctx, lds_outer);
5754 } else {
5755 for (i = 0; i < outer_comps; i++) {
5756 outer[i] = out[i] =
5757 lds_load(ctx, lds_outer);
5758 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5759 LLVMConstInt(ctx->i32, 1, false), "");
5760 }
5761 for (i = 0; i < inner_comps; i++) {
5762 inner[i] = out[outer_comps+i] =
5763 lds_load(ctx, lds_inner);
5764 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5765 LLVMConstInt(ctx->i32, 1, false), "");
5766 }
5767 }
5768
5769 /* Convert the outputs to vectors for stores. */
5770 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5771 vec1 = NULL;
5772
5773 if (stride > 4)
5774 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5775
5776
5777 buffer = ctx->hs_ring_tess_factor;
5778 tf_base = ctx->tess_factor_offset;
5779 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5780 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5781
5782 ac_nir_build_if(&inner_if_ctx, ctx,
5783 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5784 rel_patch_id, ctx->i32zero, ""));
5785
5786 /* Store the dynamic HS control word. */
5787 ac_build_buffer_store_dword(&ctx->ac, buffer,
5788 LLVMConstInt(ctx->i32, 0x80000000, false),
5789 1, ctx->i32zero, tf_base,
5790 0, 1, 0, true, false);
5791 ac_nir_build_endif(&inner_if_ctx);
5792
5793 /* Store the tessellation factors. */
5794 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5795 MIN2(stride, 4), byteoffset, tf_base,
5796 4, 1, 0, true, false);
5797 if (vec1)
5798 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5799 stride - 4, byteoffset, tf_base,
5800 20, 1, 0, true, false);
5801
5802 //TODO store to offchip for TES to read - only if TES reads them
5803 if (1) {
5804 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5805 LLVMValueRef tf_inner_offset;
5806 unsigned param_outer, param_inner;
5807
5808 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5809 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5810 LLVMConstInt(ctx->i32, param_outer, 0));
5811
5812 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5813 util_next_power_of_two(outer_comps));
5814
5815 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5816 outer_comps, tf_outer_offset,
5817 ctx->oc_lds, 0, 1, 0, true, false);
5818 if (inner_comps) {
5819 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5820 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5821 LLVMConstInt(ctx->i32, param_inner, 0));
5822
5823 inner_vec = inner_comps == 1 ? inner[0] :
5824 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5825 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5826 inner_comps, tf_inner_offset,
5827 ctx->oc_lds, 0, 1, 0, true, false);
5828 }
5829 }
5830 ac_nir_build_endif(&if_ctx);
5831 }
5832
5833 static void
5834 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5835 {
5836 write_tess_factors(ctx);
5837 }
5838
5839 static bool
5840 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5841 LLVMValueRef *color, unsigned param, bool is_last,
5842 struct ac_export_args *args)
5843 {
5844 /* Export */
5845 si_llvm_init_export_args(ctx, color, param,
5846 args);
5847
5848 if (is_last) {
5849 args->valid_mask = 1; /* whether the EXEC mask is valid */
5850 args->done = 1; /* DONE bit */
5851 } else if (!args->enabled_channels)
5852 return false; /* unnecessary NULL export */
5853
5854 return true;
5855 }
5856
5857 static void
5858 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5859 LLVMValueRef depth, LLVMValueRef stencil,
5860 LLVMValueRef samplemask)
5861 {
5862 struct ac_export_args args;
5863
5864 args.enabled_channels = 0;
5865 args.valid_mask = 1;
5866 args.done = 1;
5867 args.target = V_008DFC_SQ_EXP_MRTZ;
5868 args.compr = false;
5869
5870 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5871 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5872 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5873 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5874
5875 if (depth) {
5876 args.out[0] = depth;
5877 args.enabled_channels |= 0x1;
5878 }
5879
5880 if (stencil) {
5881 args.out[1] = stencil;
5882 args.enabled_channels |= 0x2;
5883 }
5884
5885 if (samplemask) {
5886 args.out[2] = samplemask;
5887 args.enabled_channels |= 0x4;
5888 }
5889
5890 /* SI (except OLAND and HAINAN) has a bug that it only looks
5891 * at the X writemask component. */
5892 if (ctx->options->chip_class == SI &&
5893 ctx->options->family != CHIP_OLAND &&
5894 ctx->options->family != CHIP_HAINAN)
5895 args.enabled_channels |= 0x1;
5896
5897 ac_build_export(&ctx->ac, &args);
5898 }
5899
5900 static void
5901 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5902 {
5903 unsigned index = 0;
5904 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5905 struct ac_export_args color_args[8];
5906
5907 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5908 LLVMValueRef values[4];
5909
5910 if (!(ctx->output_mask & (1ull << i)))
5911 continue;
5912
5913 if (i == FRAG_RESULT_DEPTH) {
5914 ctx->shader_info->fs.writes_z = true;
5915 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5916 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5917 } else if (i == FRAG_RESULT_STENCIL) {
5918 ctx->shader_info->fs.writes_stencil = true;
5919 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5920 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5921 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5922 ctx->shader_info->fs.writes_sample_mask = true;
5923 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5924 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5925 } else {
5926 bool last = false;
5927 for (unsigned j = 0; j < 4; j++)
5928 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5929 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5930
5931 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5932 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5933
5934 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5935 if (ret)
5936 index++;
5937 }
5938 }
5939
5940 for (unsigned i = 0; i < index; i++)
5941 ac_build_export(&ctx->ac, &color_args[i]);
5942 if (depth || stencil || samplemask)
5943 si_export_mrt_z(ctx, depth, stencil, samplemask);
5944 else if (!index) {
5945 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5946 ac_build_export(&ctx->ac, &color_args[0]);
5947 }
5948
5949 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5950 }
5951
5952 static void
5953 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5954 {
5955 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5956 }
5957
5958 static void
5959 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
5960 LLVMValueRef *addrs)
5961 {
5962 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
5963
5964 switch (ctx->stage) {
5965 case MESA_SHADER_VERTEX:
5966 if (ctx->options->key.vs.as_ls)
5967 handle_ls_outputs_post(ctx);
5968 else if (ctx->options->key.vs.as_es)
5969 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5970 else
5971 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
5972 &ctx->shader_info->vs.outinfo);
5973 break;
5974 case MESA_SHADER_FRAGMENT:
5975 handle_fs_outputs_post(ctx);
5976 break;
5977 case MESA_SHADER_GEOMETRY:
5978 emit_gs_epilogue(ctx);
5979 break;
5980 case MESA_SHADER_TESS_CTRL:
5981 handle_tcs_outputs_post(ctx);
5982 break;
5983 case MESA_SHADER_TESS_EVAL:
5984 if (ctx->options->key.tes.as_es)
5985 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5986 else
5987 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
5988 &ctx->shader_info->tes.outinfo);
5989 break;
5990 default:
5991 break;
5992 }
5993 }
5994
5995 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5996 {
5997 LLVMPassManagerRef passmgr;
5998 /* Create the pass manager */
5999 passmgr = LLVMCreateFunctionPassManagerForModule(
6000 ctx->module);
6001
6002 /* This pass should eliminate all the load and store instructions */
6003 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6004
6005 /* Add some optimization passes */
6006 LLVMAddScalarReplAggregatesPass(passmgr);
6007 LLVMAddLICMPass(passmgr);
6008 LLVMAddAggressiveDCEPass(passmgr);
6009 LLVMAddCFGSimplificationPass(passmgr);
6010 LLVMAddInstructionCombiningPass(passmgr);
6011
6012 /* Run the pass */
6013 LLVMInitializeFunctionPassManager(passmgr);
6014 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6015 LLVMFinalizeFunctionPassManager(passmgr);
6016
6017 LLVMDisposeBuilder(ctx->builder);
6018 LLVMDisposePassManager(passmgr);
6019 }
6020
6021 static void
6022 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6023 {
6024 struct ac_vs_output_info *outinfo;
6025
6026 switch (ctx->stage) {
6027 case MESA_SHADER_FRAGMENT:
6028 case MESA_SHADER_COMPUTE:
6029 case MESA_SHADER_TESS_CTRL:
6030 case MESA_SHADER_GEOMETRY:
6031 return;
6032 case MESA_SHADER_VERTEX:
6033 if (ctx->options->key.vs.as_ls ||
6034 ctx->options->key.vs.as_es)
6035 return;
6036 outinfo = &ctx->shader_info->vs.outinfo;
6037 break;
6038 case MESA_SHADER_TESS_EVAL:
6039 if (ctx->options->key.vs.as_es)
6040 return;
6041 outinfo = &ctx->shader_info->tes.outinfo;
6042 break;
6043 default:
6044 unreachable("Unhandled shader type");
6045 }
6046
6047 ac_optimize_vs_outputs(&ctx->ac,
6048 ctx->main_function,
6049 outinfo->vs_output_param_offset,
6050 VARYING_SLOT_MAX,
6051 &outinfo->param_exports);
6052 }
6053
6054 static void
6055 ac_setup_rings(struct nir_to_llvm_context *ctx)
6056 {
6057 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6058 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6059 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6060 }
6061
6062 if (ctx->is_gs_copy_shader) {
6063 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6064 }
6065 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6066 LLVMValueRef tmp;
6067 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6068 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6069
6070 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6071
6072 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6073 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6074 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6075 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6076 }
6077
6078 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6079 ctx->stage == MESA_SHADER_TESS_EVAL) {
6080 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6081 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6082 }
6083 }
6084
6085 static unsigned
6086 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6087 const struct nir_shader *nir)
6088 {
6089 switch (nir->stage) {
6090 case MESA_SHADER_TESS_CTRL:
6091 return chip_class >= CIK ? 128 : 64;
6092 case MESA_SHADER_GEOMETRY:
6093 return 64;
6094 case MESA_SHADER_COMPUTE:
6095 break;
6096 default:
6097 return 0;
6098 }
6099
6100 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6101 nir->info.cs.local_size[1] *
6102 nir->info.cs.local_size[2];
6103 return max_workgroup_size;
6104 }
6105
6106 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6107 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6108 {
6109 struct ac_nir_context ctx = {};
6110 struct nir_function *func;
6111
6112 ctx.ac = *ac;
6113 ctx.abi = abi;
6114
6115 ctx.nctx = nctx;
6116 if (nctx)
6117 nctx->nir = &ctx;
6118
6119 ctx.stage = nir->stage;
6120
6121 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6122
6123 nir_foreach_variable(variable, &nir->outputs)
6124 handle_shader_output_decl(&ctx, nir, variable);
6125
6126 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6127 _mesa_key_pointer_equal);
6128 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6129 _mesa_key_pointer_equal);
6130 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6131 _mesa_key_pointer_equal);
6132
6133 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6134
6135 setup_locals(&ctx, func);
6136
6137 if (nir->stage == MESA_SHADER_COMPUTE)
6138 setup_shared(&ctx, nir);
6139
6140 visit_cf_list(&ctx, &func->impl->body);
6141 phi_post_pass(&ctx);
6142
6143 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6144 ctx.outputs);
6145
6146 free(ctx.locals);
6147 ralloc_free(ctx.defs);
6148 ralloc_free(ctx.phis);
6149 ralloc_free(ctx.vars);
6150
6151 if (nctx)
6152 nctx->nir = NULL;
6153 }
6154
6155 static
6156 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6157 struct nir_shader *nir,
6158 struct ac_shader_variant_info *shader_info,
6159 const struct ac_nir_compiler_options *options)
6160 {
6161 struct nir_to_llvm_context ctx = {0};
6162 unsigned i;
6163 ctx.options = options;
6164 ctx.shader_info = shader_info;
6165 ctx.context = LLVMContextCreate();
6166 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6167
6168 ac_llvm_context_init(&ctx.ac, ctx.context);
6169 ctx.ac.module = ctx.module;
6170
6171 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
6172
6173 memset(shader_info, 0, sizeof(*shader_info));
6174
6175 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6176
6177 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6178
6179 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6180 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6181 LLVMSetDataLayout(ctx.module, data_layout_str);
6182 LLVMDisposeTargetData(data_layout);
6183 LLVMDisposeMessage(data_layout_str);
6184
6185 setup_types(&ctx);
6186
6187 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6188 ctx.ac.builder = ctx.builder;
6189 ctx.stage = nir->stage;
6190 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6191
6192 for (i = 0; i < AC_UD_MAX_SETS; i++)
6193 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6194 for (i = 0; i < AC_UD_MAX_UD; i++)
6195 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6196
6197 create_function(&ctx);
6198
6199 if (nir->stage == MESA_SHADER_GEOMETRY) {
6200 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6201
6202 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6203 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6204 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6205 }
6206
6207 ac_setup_rings(&ctx);
6208
6209 ctx.num_output_clips = nir->info.clip_distance_array_size;
6210 ctx.num_output_culls = nir->info.cull_distance_array_size;
6211
6212 nir_foreach_variable(variable, &nir->inputs)
6213 handle_shader_input_decl(&ctx, variable);
6214
6215 if (nir->stage == MESA_SHADER_FRAGMENT)
6216 handle_fs_inputs_pre(&ctx, nir);
6217
6218 ctx.abi.chip_class = options->chip_class;
6219 ctx.abi.inputs = &ctx.inputs[0];
6220 ctx.abi.emit_outputs = handle_shader_outputs_post;
6221 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6222
6223 nir_foreach_variable(variable, &nir->outputs)
6224 scan_shader_output_decl(&ctx, variable);
6225
6226 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6227
6228 LLVMBuildRetVoid(ctx.builder);
6229
6230 ac_llvm_finalize_module(&ctx);
6231
6232 ac_nir_eliminate_const_vs_outputs(&ctx);
6233
6234 if (nir->stage == MESA_SHADER_GEOMETRY) {
6235 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6236 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6237 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6238 nir->info.gs.vertices_out;
6239 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6240 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6241 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6242 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6243 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6244 }
6245
6246 return ctx.module;
6247 }
6248
6249 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6250 {
6251 unsigned *retval = (unsigned *)context;
6252 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6253 char *description = LLVMGetDiagInfoDescription(di);
6254
6255 if (severity == LLVMDSError) {
6256 *retval = 1;
6257 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6258 description);
6259 }
6260
6261 LLVMDisposeMessage(description);
6262 }
6263
6264 static unsigned ac_llvm_compile(LLVMModuleRef M,
6265 struct ac_shader_binary *binary,
6266 LLVMTargetMachineRef tm)
6267 {
6268 unsigned retval = 0;
6269 char *err;
6270 LLVMContextRef llvm_ctx;
6271 LLVMMemoryBufferRef out_buffer;
6272 unsigned buffer_size;
6273 const char *buffer_data;
6274 LLVMBool mem_err;
6275
6276 /* Setup Diagnostic Handler*/
6277 llvm_ctx = LLVMGetModuleContext(M);
6278
6279 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6280 &retval);
6281
6282 /* Compile IR*/
6283 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6284 &err, &out_buffer);
6285
6286 /* Process Errors/Warnings */
6287 if (mem_err) {
6288 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6289 free(err);
6290 retval = 1;
6291 goto out;
6292 }
6293
6294 /* Extract Shader Code*/
6295 buffer_size = LLVMGetBufferSize(out_buffer);
6296 buffer_data = LLVMGetBufferStart(out_buffer);
6297
6298 ac_elf_read(buffer_data, buffer_size, binary);
6299
6300 /* Clean up */
6301 LLVMDisposeMemoryBuffer(out_buffer);
6302
6303 out:
6304 return retval;
6305 }
6306
6307 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6308 LLVMModuleRef llvm_module,
6309 struct ac_shader_binary *binary,
6310 struct ac_shader_config *config,
6311 struct ac_shader_variant_info *shader_info,
6312 gl_shader_stage stage,
6313 bool dump_shader, bool supports_spill)
6314 {
6315 if (dump_shader)
6316 ac_dump_module(llvm_module);
6317
6318 memset(binary, 0, sizeof(*binary));
6319 int v = ac_llvm_compile(llvm_module, binary, tm);
6320 if (v) {
6321 fprintf(stderr, "compile failed\n");
6322 }
6323
6324 if (dump_shader)
6325 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6326
6327 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6328
6329 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6330 LLVMDisposeModule(llvm_module);
6331 LLVMContextDispose(ctx);
6332
6333 if (stage == MESA_SHADER_FRAGMENT) {
6334 shader_info->num_input_vgprs = 0;
6335 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6336 shader_info->num_input_vgprs += 2;
6337 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6338 shader_info->num_input_vgprs += 2;
6339 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6340 shader_info->num_input_vgprs += 2;
6341 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6342 shader_info->num_input_vgprs += 3;
6343 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6344 shader_info->num_input_vgprs += 2;
6345 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6346 shader_info->num_input_vgprs += 2;
6347 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6348 shader_info->num_input_vgprs += 2;
6349 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6350 shader_info->num_input_vgprs += 1;
6351 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6352 shader_info->num_input_vgprs += 1;
6353 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6354 shader_info->num_input_vgprs += 1;
6355 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6356 shader_info->num_input_vgprs += 1;
6357 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6358 shader_info->num_input_vgprs += 1;
6359 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6360 shader_info->num_input_vgprs += 1;
6361 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6362 shader_info->num_input_vgprs += 1;
6363 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6364 shader_info->num_input_vgprs += 1;
6365 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6366 shader_info->num_input_vgprs += 1;
6367 }
6368 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6369
6370 /* +3 for scratch wave offset and VCC */
6371 config->num_sgprs = MAX2(config->num_sgprs,
6372 shader_info->num_input_sgprs + 3);
6373 }
6374
6375 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6376 struct ac_shader_binary *binary,
6377 struct ac_shader_config *config,
6378 struct ac_shader_variant_info *shader_info,
6379 struct nir_shader *nir,
6380 const struct ac_nir_compiler_options *options,
6381 bool dump_shader)
6382 {
6383
6384 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6385 options);
6386
6387 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6388 switch (nir->stage) {
6389 case MESA_SHADER_COMPUTE:
6390 for (int i = 0; i < 3; ++i)
6391 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6392 break;
6393 case MESA_SHADER_FRAGMENT:
6394 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6395 break;
6396 case MESA_SHADER_GEOMETRY:
6397 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6398 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6399 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6400 shader_info->gs.invocations = nir->info.gs.invocations;
6401 break;
6402 case MESA_SHADER_TESS_EVAL:
6403 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6404 shader_info->tes.spacing = nir->info.tess.spacing;
6405 shader_info->tes.ccw = nir->info.tess.ccw;
6406 shader_info->tes.point_mode = nir->info.tess.point_mode;
6407 shader_info->tes.as_es = options->key.tes.as_es;
6408 break;
6409 case MESA_SHADER_TESS_CTRL:
6410 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6411 break;
6412 case MESA_SHADER_VERTEX:
6413 shader_info->vs.as_es = options->key.vs.as_es;
6414 shader_info->vs.as_ls = options->key.vs.as_ls;
6415 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6416 if (options->key.vs.as_ls)
6417 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6418 break;
6419 default:
6420 break;
6421 }
6422 }
6423
6424 static void
6425 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6426 {
6427 LLVMValueRef args[9];
6428 args[0] = ctx->gsvs_ring;
6429 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6430 args[3] = ctx->i32zero;
6431 args[4] = ctx->i32one; /* OFFEN */
6432 args[5] = ctx->i32zero; /* IDXEN */
6433 args[6] = ctx->i32one; /* GLC */
6434 args[7] = ctx->i32one; /* SLC */
6435 args[8] = ctx->i32zero; /* TFE */
6436
6437 int idx = 0;
6438
6439 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6440 int length = 4;
6441 int slot = idx;
6442 int slot_inc = 1;
6443 if (!(ctx->output_mask & (1ull << i)))
6444 continue;
6445
6446 if (i == VARYING_SLOT_CLIP_DIST0) {
6447 /* unpack clip and cull from a single set of slots */
6448 length = ctx->num_output_clips + ctx->num_output_culls;
6449 if (length > 4)
6450 slot_inc = 2;
6451 }
6452
6453 for (unsigned j = 0; j < length; j++) {
6454 LLVMValueRef value;
6455 args[2] = LLVMConstInt(ctx->i32,
6456 (slot * 4 + j) *
6457 ctx->gs_max_out_vertices * 16 * 4, false);
6458
6459 value = ac_build_intrinsic(&ctx->ac,
6460 "llvm.SI.buffer.load.dword.i32.i32",
6461 ctx->i32, args, 9,
6462 AC_FUNC_ATTR_READONLY |
6463 AC_FUNC_ATTR_LEGACY);
6464
6465 LLVMBuildStore(ctx->builder,
6466 to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6467 }
6468 idx += slot_inc;
6469 }
6470 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6471 }
6472
6473 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6474 struct nir_shader *geom_shader,
6475 struct ac_shader_binary *binary,
6476 struct ac_shader_config *config,
6477 struct ac_shader_variant_info *shader_info,
6478 const struct ac_nir_compiler_options *options,
6479 bool dump_shader)
6480 {
6481 struct nir_to_llvm_context ctx = {0};
6482 ctx.context = LLVMContextCreate();
6483 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6484 ctx.options = options;
6485 ctx.shader_info = shader_info;
6486
6487 ac_llvm_context_init(&ctx.ac, ctx.context);
6488 ctx.ac.module = ctx.module;
6489
6490 ctx.is_gs_copy_shader = true;
6491 LLVMSetTarget(ctx.module, "amdgcn--");
6492 setup_types(&ctx);
6493
6494 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6495 ctx.ac.builder = ctx.builder;
6496 ctx.stage = MESA_SHADER_VERTEX;
6497
6498 create_function(&ctx);
6499
6500 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6501 ac_setup_rings(&ctx);
6502
6503 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6504 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6505
6506 struct ac_nir_context nir_ctx = {};
6507 nir_ctx.ac = ctx.ac;
6508 nir_ctx.abi = &ctx.abi;
6509
6510 nir_ctx.nctx = &ctx;
6511 ctx.nir = &nir_ctx;
6512
6513 nir_foreach_variable(variable, &geom_shader->outputs) {
6514 scan_shader_output_decl(&ctx, variable);
6515 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6516 }
6517
6518 ac_gs_copy_shader_emit(&ctx);
6519
6520 ctx.nir = NULL;
6521
6522 LLVMBuildRetVoid(ctx.builder);
6523
6524 ac_llvm_finalize_module(&ctx);
6525
6526 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6527 MESA_SHADER_VERTEX,
6528 dump_shader, options->supports_spill);
6529 }