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nir: Rework conversion opcodes
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef gsvs_ring_stride;
87 LLVMValueRef gsvs_num_entries;
88 LLVMValueRef gs2vs_offset;
89 LLVMValueRef gs_wave_id;
90 LLVMValueRef gs_vtx_offset[6];
91 LLVMValueRef gs_prim_id, gs_invocation_id;
92
93 LLVMValueRef esgs_ring;
94 LLVMValueRef gsvs_ring;
95
96 LLVMValueRef prim_mask;
97 LLVMValueRef sample_positions;
98 LLVMValueRef persp_sample, persp_center, persp_centroid;
99 LLVMValueRef linear_sample, linear_center, linear_centroid;
100 LLVMValueRef front_face;
101 LLVMValueRef ancillary;
102 LLVMValueRef sample_coverage;
103 LLVMValueRef frag_pos[4];
104
105 LLVMBasicBlockRef continue_block;
106 LLVMBasicBlockRef break_block;
107
108 LLVMTypeRef i1;
109 LLVMTypeRef i8;
110 LLVMTypeRef i16;
111 LLVMTypeRef i32;
112 LLVMTypeRef i64;
113 LLVMTypeRef v2i32;
114 LLVMTypeRef v3i32;
115 LLVMTypeRef v4i32;
116 LLVMTypeRef v8i32;
117 LLVMTypeRef f64;
118 LLVMTypeRef f32;
119 LLVMTypeRef f16;
120 LLVMTypeRef v2f32;
121 LLVMTypeRef v4f32;
122 LLVMTypeRef v16i8;
123 LLVMTypeRef voidt;
124
125 LLVMValueRef i1true;
126 LLVMValueRef i1false;
127 LLVMValueRef i32zero;
128 LLVMValueRef i32one;
129 LLVMValueRef f32zero;
130 LLVMValueRef f32one;
131 LLVMValueRef v4f32empty;
132
133 unsigned uniform_md_kind;
134 LLVMValueRef empty_md;
135 gl_shader_stage stage;
136
137 LLVMValueRef lds;
138 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
139 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
140
141 LLVMValueRef shared_memory;
142 uint64_t input_mask;
143 uint64_t output_mask;
144 int num_locals;
145 LLVMValueRef *locals;
146 bool has_ddxy;
147 uint8_t num_input_clips;
148 uint8_t num_input_culls;
149 uint8_t num_output_clips;
150 uint8_t num_output_culls;
151
152 bool has_ds_bpermute;
153
154 bool is_gs_copy_shader;
155 LLVMValueRef gs_next_vertex;
156 unsigned gs_max_out_vertices;
157 };
158
159 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
160 nir_deref_var *deref,
161 enum desc_type desc_type);
162 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
163 {
164 return (index * 4) + chan;
165 }
166
167 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
168 {
169 if (slot == VARYING_SLOT_POS)
170 return 0;
171 if (slot == VARYING_SLOT_PSIZ)
172 return 1;
173 if (slot == VARYING_SLOT_CLIP_DIST0 ||
174 slot == VARYING_SLOT_CULL_DIST0)
175 return 2;
176 if (slot == VARYING_SLOT_CLIP_DIST1 ||
177 slot == VARYING_SLOT_CULL_DIST1)
178 return 3;
179 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
180 return 4 + (slot - VARYING_SLOT_VAR0);
181 unreachable("illegal slot in get unique index\n");
182 }
183
184 static unsigned llvm_get_type_size(LLVMTypeRef type)
185 {
186 LLVMTypeKind kind = LLVMGetTypeKind(type);
187
188 switch (kind) {
189 case LLVMIntegerTypeKind:
190 return LLVMGetIntTypeWidth(type) / 8;
191 case LLVMFloatTypeKind:
192 return 4;
193 case LLVMPointerTypeKind:
194 return 8;
195 case LLVMVectorTypeKind:
196 return LLVMGetVectorSize(type) *
197 llvm_get_type_size(LLVMGetElementType(type));
198 default:
199 assert(0);
200 return 0;
201 }
202 }
203
204 static void set_llvm_calling_convention(LLVMValueRef func,
205 gl_shader_stage stage)
206 {
207 enum radeon_llvm_calling_convention calling_conv;
208
209 switch (stage) {
210 case MESA_SHADER_VERTEX:
211 case MESA_SHADER_TESS_CTRL:
212 case MESA_SHADER_TESS_EVAL:
213 calling_conv = RADEON_LLVM_AMDGPU_VS;
214 break;
215 case MESA_SHADER_GEOMETRY:
216 calling_conv = RADEON_LLVM_AMDGPU_GS;
217 break;
218 case MESA_SHADER_FRAGMENT:
219 calling_conv = RADEON_LLVM_AMDGPU_PS;
220 break;
221 case MESA_SHADER_COMPUTE:
222 calling_conv = RADEON_LLVM_AMDGPU_CS;
223 break;
224 default:
225 unreachable("Unhandle shader type");
226 }
227
228 LLVMSetFunctionCallConv(func, calling_conv);
229 }
230
231 static LLVMValueRef
232 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
233 LLVMBuilderRef builder, LLVMTypeRef *return_types,
234 unsigned num_return_elems, LLVMTypeRef *param_types,
235 unsigned param_count, unsigned array_params_mask,
236 unsigned sgpr_params, bool unsafe_math)
237 {
238 LLVMTypeRef main_function_type, ret_type;
239 LLVMBasicBlockRef main_function_body;
240
241 if (num_return_elems)
242 ret_type = LLVMStructTypeInContext(ctx, return_types,
243 num_return_elems, true);
244 else
245 ret_type = LLVMVoidTypeInContext(ctx);
246
247 /* Setup the function */
248 main_function_type =
249 LLVMFunctionType(ret_type, param_types, param_count, 0);
250 LLVMValueRef main_function =
251 LLVMAddFunction(module, "main", main_function_type);
252 main_function_body =
253 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
254 LLVMPositionBuilderAtEnd(builder, main_function_body);
255
256 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
257 for (unsigned i = 0; i < sgpr_params; ++i) {
258 if (array_params_mask & (1 << i)) {
259 LLVMValueRef P = LLVMGetParam(main_function, i);
260 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
261 ac_add_attr_dereferenceable(P, UINT64_MAX);
262 }
263 else {
264 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
265 }
266 }
267
268 if (unsafe_math) {
269 /* These were copied from some LLVM test. */
270 LLVMAddTargetDependentFunctionAttr(main_function,
271 "less-precise-fpmad",
272 "true");
273 LLVMAddTargetDependentFunctionAttr(main_function,
274 "no-infs-fp-math",
275 "true");
276 LLVMAddTargetDependentFunctionAttr(main_function,
277 "no-nans-fp-math",
278 "true");
279 LLVMAddTargetDependentFunctionAttr(main_function,
280 "unsafe-fp-math",
281 "true");
282 }
283 return main_function;
284 }
285
286 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
287 {
288 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
289 CONST_ADDR_SPACE);
290 }
291
292 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
293 int idx,
294 LLVMTypeRef type)
295 {
296 LLVMValueRef offset;
297 LLVMValueRef ptr;
298 int addr_space;
299
300 offset = LLVMConstInt(ctx->i32, idx, false);
301
302 ptr = ctx->shared_memory;
303 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
304 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
305 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
306 return ptr;
307 }
308
309 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
310 {
311 if (t == ctx->f16 || t == ctx->i16)
312 return ctx->i16;
313 else if (t == ctx->f32 || t == ctx->i32)
314 return ctx->i32;
315 else if (t == ctx->f64 || t == ctx->i64)
316 return ctx->i64;
317 else
318 unreachable("Unhandled integer size");
319 }
320
321 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
322 {
323 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
324 LLVMTypeRef elem_type = LLVMGetElementType(t);
325 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
326 LLVMGetVectorSize(t));
327 }
328 return to_integer_type_scalar(ctx, t);
329 }
330
331 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
332 {
333 LLVMTypeRef type = LLVMTypeOf(v);
334 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
335 }
336
337 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
338 {
339 if (t == ctx->i16 || t == ctx->f16)
340 return ctx->f16;
341 else if (t == ctx->i32 || t == ctx->f32)
342 return ctx->f32;
343 else if (t == ctx->i64 || t == ctx->f64)
344 return ctx->f64;
345 else
346 unreachable("Unhandled float size");
347 }
348
349 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
350 {
351 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
352 LLVMTypeRef elem_type = LLVMGetElementType(t);
353 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
354 LLVMGetVectorSize(t));
355 }
356 return to_float_type_scalar(ctx, t);
357 }
358
359 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
360 {
361 LLVMTypeRef type = LLVMTypeOf(v);
362 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
363 }
364
365 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
401 {
402 ud_info->sgpr_idx = sgpr_idx;
403 ud_info->num_sgprs = num_sgprs;
404 ud_info->indirect = false;
405 ud_info->indirect_offset = 0;
406 }
407
408 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
409 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
410 {
411 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
412 }
413
414 #if 0
415 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
416 uint32_t indirect_offset)
417 {
418 ud_info->sgpr_idx = sgpr_idx;
419 ud_info->num_sgprs = num_sgprs;
420 ud_info->indirect = true;
421 ud_info->indirect_offset = indirect_offset;
422 }
423 #endif
424
425 static void create_function(struct nir_to_llvm_context *ctx)
426 {
427 LLVMTypeRef arg_types[23];
428 unsigned arg_idx = 0;
429 unsigned array_params_mask = 0;
430 unsigned sgpr_count = 0, user_sgpr_count;
431 unsigned i;
432 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
433 unsigned user_sgpr_idx;
434 bool need_push_constants;
435 bool need_ring_offsets = false;
436
437 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
438 if (ctx->stage == MESA_SHADER_GEOMETRY ||
439 ctx->stage == MESA_SHADER_VERTEX ||
440 ctx->is_gs_copy_shader)
441 need_ring_offsets = true;
442
443 need_push_constants = true;
444 if (!ctx->options->layout)
445 need_push_constants = false;
446 else if (!ctx->options->layout->push_constant_size &&
447 !ctx->options->layout->dynamic_offset_count)
448 need_push_constants = false;
449
450 if (need_ring_offsets && !ctx->options->supports_spill) {
451 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
452 }
453
454 /* 1 for each descriptor set */
455 for (unsigned i = 0; i < num_sets; ++i) {
456 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
457 array_params_mask |= (1 << arg_idx);
458 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
459 }
460 }
461
462 if (need_push_constants) {
463 /* 1 for push constants and dynamic descriptors */
464 array_params_mask |= (1 << arg_idx);
465 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
466 }
467
468 switch (ctx->stage) {
469 case MESA_SHADER_COMPUTE:
470 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
471 user_sgpr_count = arg_idx;
472 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
473 arg_types[arg_idx++] = ctx->i32;
474 sgpr_count = arg_idx;
475
476 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
477 break;
478 case MESA_SHADER_VERTEX:
479 if (!ctx->is_gs_copy_shader) {
480 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
481 arg_types[arg_idx++] = ctx->i32; // base vertex
482 arg_types[arg_idx++] = ctx->i32; // start instance
483 arg_types[arg_idx++] = ctx->i32; // draw index
484 }
485 user_sgpr_count = arg_idx;
486 if (ctx->options->key.vs.as_es)
487 arg_types[arg_idx++] = ctx->i32; //es2gs offset
488 sgpr_count = arg_idx;
489 arg_types[arg_idx++] = ctx->i32; // vertex id
490 if (!ctx->is_gs_copy_shader) {
491 arg_types[arg_idx++] = ctx->i32; // rel auto id
492 arg_types[arg_idx++] = ctx->i32; // vs prim id
493 arg_types[arg_idx++] = ctx->i32; // instance id
494 }
495 break;
496 case MESA_SHADER_GEOMETRY:
497 arg_types[arg_idx++] = ctx->i32; // gsvs stride
498 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
499 user_sgpr_count = arg_idx;
500 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
501 arg_types[arg_idx++] = ctx->i32; // wave id
502 sgpr_count = arg_idx;
503 arg_types[arg_idx++] = ctx->i32; // vtx0
504 arg_types[arg_idx++] = ctx->i32; // vtx1
505 arg_types[arg_idx++] = ctx->i32; // prim id
506 arg_types[arg_idx++] = ctx->i32; // vtx2
507 arg_types[arg_idx++] = ctx->i32; // vtx3
508 arg_types[arg_idx++] = ctx->i32; // vtx4
509 arg_types[arg_idx++] = ctx->i32; // vtx5
510 arg_types[arg_idx++] = ctx->i32; // GS instance id
511 break;
512 case MESA_SHADER_FRAGMENT:
513 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
514 user_sgpr_count = arg_idx;
515 arg_types[arg_idx++] = ctx->i32; /* prim mask */
516 sgpr_count = arg_idx;
517 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
518 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
519 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
520 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
521 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
522 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
523 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
524 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
525 arg_types[arg_idx++] = ctx->f32; /* pos x float */
526 arg_types[arg_idx++] = ctx->f32; /* pos y float */
527 arg_types[arg_idx++] = ctx->f32; /* pos z float */
528 arg_types[arg_idx++] = ctx->f32; /* pos w float */
529 arg_types[arg_idx++] = ctx->i32; /* front face */
530 arg_types[arg_idx++] = ctx->i32; /* ancillary */
531 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
532 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
533 break;
534 default:
535 unreachable("Shader stage not implemented");
536 }
537
538 ctx->main_function = create_llvm_function(
539 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
540 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
541 set_llvm_calling_convention(ctx->main_function, ctx->stage);
542
543 ctx->shader_info->num_input_sgprs = 0;
544 ctx->shader_info->num_input_vgprs = 0;
545
546 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
547 for (i = 0; i < user_sgpr_count; i++)
548 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
549
550 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
551 for (; i < sgpr_count; i++)
552 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
553
554 if (ctx->stage != MESA_SHADER_FRAGMENT)
555 for (; i < arg_idx; ++i)
556 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
557
558 arg_idx = 0;
559 user_sgpr_idx = 0;
560
561 if (ctx->options->supports_spill || need_ring_offsets) {
562 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
563 user_sgpr_idx += 2;
564 if (ctx->options->supports_spill) {
565 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
566 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
567 NULL, 0, AC_FUNC_ATTR_READNONE);
568 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
569 const_array(ctx->v16i8, 8), "");
570 } else
571 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
572 }
573
574 for (unsigned i = 0; i < num_sets; ++i) {
575 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
576 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
577 user_sgpr_idx += 2;
578 ctx->descriptor_sets[i] =
579 LLVMGetParam(ctx->main_function, arg_idx++);
580 } else
581 ctx->descriptor_sets[i] = NULL;
582 }
583
584 if (need_push_constants) {
585 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
586 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
587 user_sgpr_idx += 2;
588 }
589
590 switch (ctx->stage) {
591 case MESA_SHADER_COMPUTE:
592 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
593 user_sgpr_idx += 3;
594 ctx->num_work_groups =
595 LLVMGetParam(ctx->main_function, arg_idx++);
596 ctx->workgroup_ids =
597 LLVMGetParam(ctx->main_function, arg_idx++);
598 ctx->tg_size =
599 LLVMGetParam(ctx->main_function, arg_idx++);
600 ctx->local_invocation_ids =
601 LLVMGetParam(ctx->main_function, arg_idx++);
602 break;
603 case MESA_SHADER_VERTEX:
604 if (!ctx->is_gs_copy_shader) {
605 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
606 user_sgpr_idx += 2;
607 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
608 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
609 user_sgpr_idx += 3;
610 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
611 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
612 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
613 }
614 if (ctx->options->key.vs.as_es)
615 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
616 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
617 if (!ctx->is_gs_copy_shader) {
618 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
619 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
620 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
621 }
622 break;
623 case MESA_SHADER_GEOMETRY:
624 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
625 user_sgpr_idx += 2;
626 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
627 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
628 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
629 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
630 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
631 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
632 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
633 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
635 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
636 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
638 break;
639 case MESA_SHADER_FRAGMENT:
640 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
641 user_sgpr_idx += 2;
642 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
643 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
644 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
645 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
646 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
647 arg_idx++;
648 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
651 arg_idx++; /* line stipple */
652 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
653 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
655 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
656 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
657 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
658 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
659 break;
660 default:
661 unreachable("Shader stage not implemented");
662 }
663 }
664
665 static void setup_types(struct nir_to_llvm_context *ctx)
666 {
667 LLVMValueRef args[4];
668
669 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
670 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
671 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
672 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
673 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
674 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
675 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
676 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
677 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
678 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
679 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
680 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
681 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
682 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
683 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
684 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
685
686 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
687 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
688 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
689 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
690 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
691 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
692
693 args[0] = ctx->f32zero;
694 args[1] = ctx->f32zero;
695 args[2] = ctx->f32zero;
696 args[3] = ctx->f32one;
697 ctx->v4f32empty = LLVMConstVector(args, 4);
698
699 ctx->uniform_md_kind =
700 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
701 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
702
703 args[0] = LLVMConstReal(ctx->f32, 2.5);
704 }
705
706 static int get_llvm_num_components(LLVMValueRef value)
707 {
708 LLVMTypeRef type = LLVMTypeOf(value);
709 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
710 ? LLVMGetVectorSize(type)
711 : 1;
712 return num_components;
713 }
714
715 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
716 LLVMValueRef value,
717 int index)
718 {
719 int count = get_llvm_num_components(value);
720
721 assert(index < count);
722 if (count == 1)
723 return value;
724
725 return LLVMBuildExtractElement(ctx->builder, value,
726 LLVMConstInt(ctx->i32, index, false), "");
727 }
728
729 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
730 LLVMValueRef value, unsigned count)
731 {
732 unsigned num_components = get_llvm_num_components(value);
733 if (count == num_components)
734 return value;
735
736 LLVMValueRef masks[] = {
737 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
738 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
739
740 if (count == 1)
741 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
742 "");
743
744 LLVMValueRef swizzle = LLVMConstVector(masks, count);
745 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
746 }
747
748 static void
749 build_store_values_extended(struct nir_to_llvm_context *ctx,
750 LLVMValueRef *values,
751 unsigned value_count,
752 unsigned value_stride,
753 LLVMValueRef vec)
754 {
755 LLVMBuilderRef builder = ctx->builder;
756 unsigned i;
757
758 if (value_count == 1) {
759 LLVMBuildStore(builder, vec, values[0]);
760 return;
761 }
762
763 for (i = 0; i < value_count; i++) {
764 LLVMValueRef ptr = values[i * value_stride];
765 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
766 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
767 LLVMBuildStore(builder, value, ptr);
768 }
769 }
770
771 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
772 nir_ssa_def *def)
773 {
774 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
775 if (def->num_components > 1) {
776 type = LLVMVectorType(type, def->num_components);
777 }
778 return type;
779 }
780
781 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
782 {
783 assert(src.is_ssa);
784 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
785 return (LLVMValueRef)entry->data;
786 }
787
788
789 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
790 struct nir_block *b)
791 {
792 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
793 return (LLVMBasicBlockRef)entry->data;
794 }
795
796 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
797 nir_alu_src src,
798 unsigned num_components)
799 {
800 LLVMValueRef value = get_src(ctx, src.src);
801 bool need_swizzle = false;
802
803 assert(value);
804 LLVMTypeRef type = LLVMTypeOf(value);
805 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
806 ? LLVMGetVectorSize(type)
807 : 1;
808
809 for (unsigned i = 0; i < num_components; ++i) {
810 assert(src.swizzle[i] < src_components);
811 if (src.swizzle[i] != i)
812 need_swizzle = true;
813 }
814
815 if (need_swizzle || num_components != src_components) {
816 LLVMValueRef masks[] = {
817 LLVMConstInt(ctx->i32, src.swizzle[0], false),
818 LLVMConstInt(ctx->i32, src.swizzle[1], false),
819 LLVMConstInt(ctx->i32, src.swizzle[2], false),
820 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
821
822 if (src_components > 1 && num_components == 1) {
823 value = LLVMBuildExtractElement(ctx->builder, value,
824 masks[0], "");
825 } else if (src_components == 1 && num_components > 1) {
826 LLVMValueRef values[] = {value, value, value, value};
827 value = ac_build_gather_values(&ctx->ac, values, num_components);
828 } else {
829 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
830 value = LLVMBuildShuffleVector(ctx->builder, value, value,
831 swizzle, "");
832 }
833 }
834 assert(!src.negate);
835 assert(!src.abs);
836 return value;
837 }
838
839 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
840 LLVMIntPredicate pred, LLVMValueRef src0,
841 LLVMValueRef src1)
842 {
843 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
844 return LLVMBuildSelect(ctx->builder, result,
845 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
846 LLVMConstInt(ctx->i32, 0, false), "");
847 }
848
849 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
850 LLVMRealPredicate pred, LLVMValueRef src0,
851 LLVMValueRef src1)
852 {
853 LLVMValueRef result;
854 src0 = to_float(ctx, src0);
855 src1 = to_float(ctx, src1);
856 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
857 return LLVMBuildSelect(ctx->builder, result,
858 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
859 LLVMConstInt(ctx->i32, 0, false), "");
860 }
861
862 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
863 const char *intrin,
864 LLVMTypeRef result_type,
865 LLVMValueRef src0)
866 {
867 char name[64];
868 LLVMValueRef params[] = {
869 to_float(ctx, src0),
870 };
871
872 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
873 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
874 }
875
876 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
877 const char *intrin,
878 LLVMTypeRef result_type,
879 LLVMValueRef src0, LLVMValueRef src1)
880 {
881 char name[64];
882 LLVMValueRef params[] = {
883 to_float(ctx, src0),
884 to_float(ctx, src1),
885 };
886
887 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
888 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
889 }
890
891 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
892 const char *intrin,
893 LLVMTypeRef result_type,
894 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
895 {
896 char name[64];
897 LLVMValueRef params[] = {
898 to_float(ctx, src0),
899 to_float(ctx, src1),
900 to_float(ctx, src2),
901 };
902
903 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
904 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
905 }
906
907 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
908 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
909 {
910 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
911 ctx->i32zero, "");
912 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
913 }
914
915 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
916 LLVMValueRef src0)
917 {
918 LLVMValueRef params[2] = {
919 src0,
920
921 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
922 * add special code to check for x=0. The reason is that
923 * the LLVM behavior for x=0 is different from what we
924 * need here.
925 *
926 * The hardware already implements the correct behavior.
927 */
928 LLVMConstInt(ctx->i32, 1, false),
929 };
930 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
931 }
932
933 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
934 LLVMValueRef src0)
935 {
936 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
937 }
938
939 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
940 LLVMValueRef src0)
941 {
942 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
943 }
944
945 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
946 LLVMIntPredicate pred,
947 LLVMValueRef src0, LLVMValueRef src1)
948 {
949 return LLVMBuildSelect(ctx->builder,
950 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
951 src0,
952 src1, "");
953
954 }
955 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
956 LLVMValueRef src0)
957 {
958 return emit_minmax_int(ctx, LLVMIntSGT, src0,
959 LLVMBuildNeg(ctx->builder, src0, ""));
960 }
961
962 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
963 LLVMValueRef src0)
964 {
965 LLVMValueRef cmp, val;
966
967 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
968 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
969 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
970 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
971 return val;
972 }
973
974 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
975 LLVMValueRef src0)
976 {
977 LLVMValueRef cmp, val;
978
979 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
980 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
981 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
982 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
983 return val;
984 }
985
986 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
987 LLVMValueRef src0)
988 {
989 const char *intr = "llvm.floor.f32";
990 LLVMValueRef fsrc0 = to_float(ctx, src0);
991 LLVMValueRef params[] = {
992 fsrc0,
993 };
994 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
995 ctx->f32, params, 1,
996 AC_FUNC_ATTR_READNONE);
997 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
998 }
999
1000 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1001 const char *intrin,
1002 LLVMValueRef src0, LLVMValueRef src1)
1003 {
1004 LLVMTypeRef ret_type;
1005 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1006 LLVMValueRef res;
1007 LLVMValueRef params[] = { src0, src1 };
1008 ret_type = LLVMStructTypeInContext(ctx->context, types,
1009 2, true);
1010
1011 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1012 params, 2, AC_FUNC_ATTR_READNONE);
1013
1014 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1015 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1016 return res;
1017 }
1018
1019 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1020 LLVMValueRef src0)
1021 {
1022 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1023 }
1024
1025 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1026 LLVMValueRef src0, LLVMValueRef src1)
1027 {
1028 LLVMValueRef dst64, result;
1029 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1030 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1031
1032 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1033 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1034 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1035 return result;
1036 }
1037
1038 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1039 LLVMValueRef src0, LLVMValueRef src1)
1040 {
1041 LLVMValueRef dst64, result;
1042 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1043 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1044
1045 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1046 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1047 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1048 return result;
1049 }
1050
1051 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1052 bool is_signed,
1053 LLVMValueRef srcs[3])
1054 {
1055 LLVMValueRef result;
1056 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1057
1058 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1059 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1060 return result;
1061 }
1062
1063 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1064 LLVMValueRef src0, LLVMValueRef src1,
1065 LLVMValueRef src2, LLVMValueRef src3)
1066 {
1067 LLVMValueRef bfi_args[3], result;
1068
1069 bfi_args[0] = LLVMBuildShl(ctx->builder,
1070 LLVMBuildSub(ctx->builder,
1071 LLVMBuildShl(ctx->builder,
1072 ctx->i32one,
1073 src3, ""),
1074 ctx->i32one, ""),
1075 src2, "");
1076 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1077 bfi_args[2] = src0;
1078
1079 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1080
1081 /* Calculate:
1082 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1083 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1084 */
1085 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1086 LLVMBuildAnd(ctx->builder, bfi_args[0],
1087 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1088
1089 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1090 return result;
1091 }
1092
1093 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1094 LLVMValueRef src0)
1095 {
1096 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1097 int i;
1098 LLVMValueRef comp[2];
1099
1100 src0 = to_float(ctx, src0);
1101 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1102 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1103 for (i = 0; i < 2; i++) {
1104 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1105 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1106 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1107 }
1108
1109 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1110 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1111
1112 return comp[0];
1113 }
1114
1115 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1116 LLVMValueRef src0)
1117 {
1118 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1119 LLVMValueRef temps[2], result, val;
1120 int i;
1121
1122 for (i = 0; i < 2; i++) {
1123 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1124 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1125 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1126 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1127 }
1128
1129 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1130 ctx->i32zero, "");
1131 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1132 ctx->i32one, "");
1133 return result;
1134 }
1135
1136 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1137 nir_op op,
1138 LLVMValueRef src0)
1139 {
1140 unsigned mask;
1141 int idx;
1142 LLVMValueRef result;
1143 ctx->has_ddxy = true;
1144
1145 if (!ctx->lds && !ctx->has_ds_bpermute)
1146 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1147 LLVMArrayType(ctx->i32, 64),
1148 "ddxy_lds", LOCAL_ADDR_SPACE);
1149
1150 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1151 mask = AC_TID_MASK_LEFT;
1152 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1153 mask = AC_TID_MASK_TOP;
1154 else
1155 mask = AC_TID_MASK_TOP_LEFT;
1156
1157 /* for DDX we want to next X pixel, DDY next Y pixel. */
1158 if (op == nir_op_fddx_fine ||
1159 op == nir_op_fddx_coarse ||
1160 op == nir_op_fddx)
1161 idx = 1;
1162 else
1163 idx = 2;
1164
1165 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1166 mask, idx, ctx->lds,
1167 src0);
1168 return result;
1169 }
1170
1171 /*
1172 * this takes an I,J coordinate pair,
1173 * and works out the X and Y derivatives.
1174 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1175 */
1176 static LLVMValueRef emit_ddxy_interp(
1177 struct nir_to_llvm_context *ctx,
1178 LLVMValueRef interp_ij)
1179 {
1180 LLVMValueRef result[4], a;
1181 unsigned i;
1182
1183 for (i = 0; i < 2; i++) {
1184 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1185 LLVMConstInt(ctx->i32, i, false), "");
1186 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1187 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1188 }
1189 return ac_build_gather_values(&ctx->ac, result, 4);
1190 }
1191
1192 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1193 {
1194 LLVMValueRef src[4], result = NULL;
1195 unsigned num_components = instr->dest.dest.ssa.num_components;
1196 unsigned src_components;
1197 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1198
1199 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1200 switch (instr->op) {
1201 case nir_op_vec2:
1202 case nir_op_vec3:
1203 case nir_op_vec4:
1204 src_components = 1;
1205 break;
1206 case nir_op_pack_half_2x16:
1207 src_components = 2;
1208 break;
1209 case nir_op_unpack_half_2x16:
1210 src_components = 1;
1211 break;
1212 default:
1213 src_components = num_components;
1214 break;
1215 }
1216 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1217 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1218
1219 switch (instr->op) {
1220 case nir_op_fmov:
1221 case nir_op_imov:
1222 result = src[0];
1223 break;
1224 case nir_op_fneg:
1225 src[0] = to_float(ctx, src[0]);
1226 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1227 break;
1228 case nir_op_ineg:
1229 result = LLVMBuildNeg(ctx->builder, src[0], "");
1230 break;
1231 case nir_op_inot:
1232 result = LLVMBuildNot(ctx->builder, src[0], "");
1233 break;
1234 case nir_op_iadd:
1235 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1236 break;
1237 case nir_op_fadd:
1238 src[0] = to_float(ctx, src[0]);
1239 src[1] = to_float(ctx, src[1]);
1240 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1241 break;
1242 case nir_op_fsub:
1243 src[0] = to_float(ctx, src[0]);
1244 src[1] = to_float(ctx, src[1]);
1245 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1246 break;
1247 case nir_op_isub:
1248 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1249 break;
1250 case nir_op_imul:
1251 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1252 break;
1253 case nir_op_imod:
1254 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1255 break;
1256 case nir_op_umod:
1257 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1258 break;
1259 case nir_op_fmod:
1260 src[0] = to_float(ctx, src[0]);
1261 src[1] = to_float(ctx, src[1]);
1262 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1263 result = emit_intrin_1f_param(ctx, "llvm.floor",
1264 to_float_type(ctx, def_type), result);
1265 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1266 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1267 break;
1268 case nir_op_frem:
1269 src[0] = to_float(ctx, src[0]);
1270 src[1] = to_float(ctx, src[1]);
1271 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1272 break;
1273 case nir_op_irem:
1274 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1275 break;
1276 case nir_op_idiv:
1277 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1278 break;
1279 case nir_op_udiv:
1280 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1281 break;
1282 case nir_op_fmul:
1283 src[0] = to_float(ctx, src[0]);
1284 src[1] = to_float(ctx, src[1]);
1285 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1286 break;
1287 case nir_op_fdiv:
1288 src[0] = to_float(ctx, src[0]);
1289 src[1] = to_float(ctx, src[1]);
1290 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1291 break;
1292 case nir_op_frcp:
1293 src[0] = to_float(ctx, src[0]);
1294 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1295 break;
1296 case nir_op_iand:
1297 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1298 break;
1299 case nir_op_ior:
1300 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1301 break;
1302 case nir_op_ixor:
1303 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1304 break;
1305 case nir_op_ishl:
1306 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1307 break;
1308 case nir_op_ishr:
1309 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1310 break;
1311 case nir_op_ushr:
1312 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1313 break;
1314 case nir_op_ilt:
1315 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1316 break;
1317 case nir_op_ine:
1318 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1319 break;
1320 case nir_op_ieq:
1321 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1322 break;
1323 case nir_op_ige:
1324 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1325 break;
1326 case nir_op_ult:
1327 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1328 break;
1329 case nir_op_uge:
1330 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1331 break;
1332 case nir_op_feq:
1333 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1334 break;
1335 case nir_op_fne:
1336 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1337 break;
1338 case nir_op_flt:
1339 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1340 break;
1341 case nir_op_fge:
1342 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1343 break;
1344 case nir_op_fabs:
1345 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1346 to_float_type(ctx, def_type), src[0]);
1347 break;
1348 case nir_op_iabs:
1349 result = emit_iabs(ctx, src[0]);
1350 break;
1351 case nir_op_imax:
1352 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1353 break;
1354 case nir_op_imin:
1355 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1356 break;
1357 case nir_op_umax:
1358 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1359 break;
1360 case nir_op_umin:
1361 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1362 break;
1363 case nir_op_isign:
1364 result = emit_isign(ctx, src[0]);
1365 break;
1366 case nir_op_fsign:
1367 src[0] = to_float(ctx, src[0]);
1368 result = emit_fsign(ctx, src[0]);
1369 break;
1370 case nir_op_ffloor:
1371 result = emit_intrin_1f_param(ctx, "llvm.floor",
1372 to_float_type(ctx, def_type), src[0]);
1373 break;
1374 case nir_op_ftrunc:
1375 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1376 to_float_type(ctx, def_type), src[0]);
1377 break;
1378 case nir_op_fceil:
1379 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1380 to_float_type(ctx, def_type), src[0]);
1381 break;
1382 case nir_op_fround_even:
1383 result = emit_intrin_1f_param(ctx, "llvm.rint",
1384 to_float_type(ctx, def_type),src[0]);
1385 break;
1386 case nir_op_ffract:
1387 result = emit_ffract(ctx, src[0]);
1388 break;
1389 case nir_op_fsin:
1390 result = emit_intrin_1f_param(ctx, "llvm.sin",
1391 to_float_type(ctx, def_type), src[0]);
1392 break;
1393 case nir_op_fcos:
1394 result = emit_intrin_1f_param(ctx, "llvm.cos",
1395 to_float_type(ctx, def_type), src[0]);
1396 break;
1397 case nir_op_fsqrt:
1398 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1399 to_float_type(ctx, def_type), src[0]);
1400 break;
1401 case nir_op_fexp2:
1402 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1403 to_float_type(ctx, def_type), src[0]);
1404 break;
1405 case nir_op_flog2:
1406 result = emit_intrin_1f_param(ctx, "llvm.log2",
1407 to_float_type(ctx, def_type), src[0]);
1408 break;
1409 case nir_op_frsq:
1410 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1411 to_float_type(ctx, def_type), src[0]);
1412 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1413 break;
1414 case nir_op_fpow:
1415 result = emit_intrin_2f_param(ctx, "llvm.pow",
1416 to_float_type(ctx, def_type), src[0], src[1]);
1417 break;
1418 case nir_op_fmax:
1419 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1420 to_float_type(ctx, def_type), src[0], src[1]);
1421 break;
1422 case nir_op_fmin:
1423 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1424 to_float_type(ctx, def_type), src[0], src[1]);
1425 break;
1426 case nir_op_ffma:
1427 result = emit_intrin_3f_param(ctx, "llvm.fma",
1428 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1429 break;
1430 case nir_op_ibitfield_extract:
1431 result = emit_bitfield_extract(ctx, true, src);
1432 break;
1433 case nir_op_ubitfield_extract:
1434 result = emit_bitfield_extract(ctx, false, src);
1435 break;
1436 case nir_op_bitfield_insert:
1437 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1438 break;
1439 case nir_op_bitfield_reverse:
1440 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1441 break;
1442 case nir_op_bit_count:
1443 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1444 break;
1445 case nir_op_vec2:
1446 case nir_op_vec3:
1447 case nir_op_vec4:
1448 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1449 src[i] = to_integer(ctx, src[i]);
1450 result = ac_build_gather_values(&ctx->ac, src, num_components);
1451 break;
1452 case nir_op_f2i32:
1453 case nir_op_f2i64:
1454 src[0] = to_float(ctx, src[0]);
1455 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1456 break;
1457 case nir_op_f2u32:
1458 case nir_op_f2u64:
1459 src[0] = to_float(ctx, src[0]);
1460 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1461 break;
1462 case nir_op_i2f32:
1463 case nir_op_i2f64:
1464 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1465 break;
1466 case nir_op_u2f32:
1467 case nir_op_u2f64:
1468 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1469 break;
1470 case nir_op_f2f64:
1471 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1472 break;
1473 case nir_op_f2f32:
1474 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1475 break;
1476 case nir_op_u2u32:
1477 case nir_op_u2u64:
1478 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1479 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1480 else
1481 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1482 break;
1483 case nir_op_i2i32:
1484 case nir_op_i2i64:
1485 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1486 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1487 else
1488 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1489 break;
1490 case nir_op_bcsel:
1491 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1492 break;
1493 case nir_op_find_lsb:
1494 result = emit_find_lsb(ctx, src[0]);
1495 break;
1496 case nir_op_ufind_msb:
1497 result = emit_ufind_msb(ctx, src[0]);
1498 break;
1499 case nir_op_ifind_msb:
1500 result = emit_ifind_msb(ctx, src[0]);
1501 break;
1502 case nir_op_uadd_carry:
1503 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1504 break;
1505 case nir_op_usub_borrow:
1506 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1507 break;
1508 case nir_op_b2f:
1509 result = emit_b2f(ctx, src[0]);
1510 break;
1511 case nir_op_fquantize2f16:
1512 src[0] = to_float(ctx, src[0]);
1513 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1514 /* need to convert back up to f32 */
1515 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1516 break;
1517 case nir_op_umul_high:
1518 result = emit_umul_high(ctx, src[0], src[1]);
1519 break;
1520 case nir_op_imul_high:
1521 result = emit_imul_high(ctx, src[0], src[1]);
1522 break;
1523 case nir_op_pack_half_2x16:
1524 result = emit_pack_half_2x16(ctx, src[0]);
1525 break;
1526 case nir_op_unpack_half_2x16:
1527 result = emit_unpack_half_2x16(ctx, src[0]);
1528 break;
1529 case nir_op_fddx:
1530 case nir_op_fddy:
1531 case nir_op_fddx_fine:
1532 case nir_op_fddy_fine:
1533 case nir_op_fddx_coarse:
1534 case nir_op_fddy_coarse:
1535 result = emit_ddxy(ctx, instr->op, src[0]);
1536 break;
1537 default:
1538 fprintf(stderr, "Unknown NIR alu instr: ");
1539 nir_print_instr(&instr->instr, stderr);
1540 fprintf(stderr, "\n");
1541 abort();
1542 }
1543
1544 if (result) {
1545 assert(instr->dest.dest.is_ssa);
1546 result = to_integer(ctx, result);
1547 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1548 result);
1549 }
1550 }
1551
1552 static void visit_load_const(struct nir_to_llvm_context *ctx,
1553 nir_load_const_instr *instr)
1554 {
1555 LLVMValueRef values[4], value = NULL;
1556 LLVMTypeRef element_type =
1557 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1558
1559 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1560 switch (instr->def.bit_size) {
1561 case 32:
1562 values[i] = LLVMConstInt(element_type,
1563 instr->value.u32[i], false);
1564 break;
1565 case 64:
1566 values[i] = LLVMConstInt(element_type,
1567 instr->value.u64[i], false);
1568 break;
1569 default:
1570 fprintf(stderr,
1571 "unsupported nir load_const bit_size: %d\n",
1572 instr->def.bit_size);
1573 abort();
1574 }
1575 }
1576 if (instr->def.num_components > 1) {
1577 value = LLVMConstVector(values, instr->def.num_components);
1578 } else
1579 value = values[0];
1580
1581 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1582 }
1583
1584 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1585 LLVMTypeRef type)
1586 {
1587 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1588 return LLVMBuildBitCast(ctx->builder, ptr,
1589 LLVMPointerType(type, addr_space), "");
1590 }
1591
1592 static LLVMValueRef
1593 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1594 {
1595 LLVMValueRef size =
1596 LLVMBuildExtractElement(ctx->builder, descriptor,
1597 LLVMConstInt(ctx->i32, 2, false), "");
1598
1599 /* VI only */
1600 if (ctx->options->chip_class >= VI && in_elements) {
1601 /* On VI, the descriptor contains the size in bytes,
1602 * but TXQ must return the size in elements.
1603 * The stride is always non-zero for resources using TXQ.
1604 */
1605 LLVMValueRef stride =
1606 LLVMBuildExtractElement(ctx->builder, descriptor,
1607 LLVMConstInt(ctx->i32, 1, false), "");
1608 stride = LLVMBuildLShr(ctx->builder, stride,
1609 LLVMConstInt(ctx->i32, 16, false), "");
1610 stride = LLVMBuildAnd(ctx->builder, stride,
1611 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1612
1613 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1614 }
1615 return size;
1616 }
1617
1618 /**
1619 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1620 * intrinsic names).
1621 */
1622 static void build_int_type_name(
1623 LLVMTypeRef type,
1624 char *buf, unsigned bufsize)
1625 {
1626 assert(bufsize >= 6);
1627
1628 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1629 snprintf(buf, bufsize, "v%ui32",
1630 LLVMGetVectorSize(type));
1631 else
1632 strcpy(buf, "i32");
1633 }
1634
1635 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1636 struct ac_image_args *args,
1637 nir_tex_instr *instr)
1638 {
1639 LLVMValueRef coord = args->addr;
1640 LLVMValueRef half_texel[2];
1641 int c;
1642 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1643
1644 //TODO Rect
1645 {
1646 struct ac_image_args txq_args = { 0 };
1647
1648 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1649 txq_args.opcode = ac_image_get_resinfo;
1650 txq_args.dmask = 0xf;
1651 txq_args.addr = ctx->i32zero;
1652 txq_args.resource = args->resource;
1653 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1654
1655 for (c = 0; c < 2; c++) {
1656 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1657 LLVMConstInt(ctx->i32, c, false), "");
1658 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1659 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1660 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1661 LLVMConstReal(ctx->f32, -0.5), "");
1662 }
1663 }
1664
1665 for (c = 0; c < 2; c++) {
1666 LLVMValueRef tmp;
1667 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1668 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1669 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1670 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1671 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1672 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1673 }
1674
1675 args->addr = coord;
1676 return ac_build_image_opcode(&ctx->ac, args);
1677 }
1678
1679 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1680 nir_tex_instr *instr,
1681 struct ac_image_args *args)
1682 {
1683 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
1684 return ac_build_buffer_load_format(&ctx->ac,
1685 args->resource,
1686 args->addr,
1687 LLVMConstInt(ctx->i32, 0, false),
1688 true);
1689 }
1690
1691 args->opcode = ac_image_sample;
1692 args->compare = instr->is_shadow;
1693
1694 switch (instr->op) {
1695 case nir_texop_txf:
1696 case nir_texop_txf_ms:
1697 case nir_texop_samples_identical:
1698 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
1699 args->compare = false;
1700 args->offset = false;
1701 break;
1702 case nir_texop_txb:
1703 args->bias = true;
1704 break;
1705 case nir_texop_txl:
1706 args->lod = true;
1707 break;
1708 case nir_texop_txs:
1709 case nir_texop_query_levels:
1710 args->opcode = ac_image_get_resinfo;
1711 break;
1712 case nir_texop_tex:
1713 if (ctx->stage != MESA_SHADER_FRAGMENT)
1714 args->level_zero = true;
1715 break;
1716 case nir_texop_txd:
1717 args->deriv = true;
1718 break;
1719 case nir_texop_tg4:
1720 args->opcode = ac_image_gather4;
1721 args->level_zero = true;
1722 break;
1723 case nir_texop_lod:
1724 args->opcode = ac_image_get_lod;
1725 args->compare = false;
1726 args->offset = false;
1727 break;
1728 default:
1729 break;
1730 }
1731
1732 if (instr->op == nir_texop_tg4) {
1733 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1734 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1735 return radv_lower_gather4_integer(ctx, args, instr);
1736 }
1737 }
1738 return ac_build_image_opcode(&ctx->ac, args);
1739 }
1740
1741 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1742 nir_intrinsic_instr *instr)
1743 {
1744 LLVMValueRef index = get_src(ctx, instr->src[0]);
1745 unsigned desc_set = nir_intrinsic_desc_set(instr);
1746 unsigned binding = nir_intrinsic_binding(instr);
1747 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1748 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1749 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1750 unsigned base_offset = layout->binding[binding].offset;
1751 LLVMValueRef offset, stride;
1752
1753 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1754 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1755 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1756 layout->binding[binding].dynamic_offset_offset;
1757 desc_ptr = ctx->push_constants;
1758 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1759 stride = LLVMConstInt(ctx->i32, 16, false);
1760 } else
1761 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1762
1763 offset = LLVMConstInt(ctx->i32, base_offset, false);
1764 index = LLVMBuildMul(ctx->builder, index, stride, "");
1765 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1766
1767 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1768 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1769 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1770
1771 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1772 }
1773
1774 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1775 nir_intrinsic_instr *instr)
1776 {
1777 LLVMValueRef ptr, addr;
1778
1779 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1780 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1781
1782 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1783 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1784
1785 return LLVMBuildLoad(ctx->builder, ptr, "");
1786 }
1787
1788 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1789 nir_intrinsic_instr *instr)
1790 {
1791 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1792
1793 return get_buffer_size(ctx, desc, false);
1794 }
1795 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1796 nir_intrinsic_instr *instr)
1797 {
1798 const char *store_name;
1799 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1800 LLVMTypeRef data_type = ctx->f32;
1801 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1802 int components_32bit = elem_size_mult * instr->num_components;
1803 unsigned writemask = nir_intrinsic_write_mask(instr);
1804 LLVMValueRef base_data, base_offset;
1805 LLVMValueRef params[6];
1806
1807 if (ctx->stage == MESA_SHADER_FRAGMENT)
1808 ctx->shader_info->fs.writes_memory = true;
1809
1810 params[1] = get_src(ctx, instr->src[1]);
1811 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1812 params[4] = ctx->i1false; /* glc */
1813 params[5] = ctx->i1false; /* slc */
1814
1815 if (components_32bit > 1)
1816 data_type = LLVMVectorType(ctx->f32, components_32bit);
1817
1818 base_data = to_float(ctx, src_data);
1819 base_data = trim_vector(ctx, base_data, instr->num_components);
1820 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1821 data_type, "");
1822 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1823 while (writemask) {
1824 int start, count;
1825 LLVMValueRef data;
1826 LLVMValueRef offset;
1827 LLVMValueRef tmp;
1828 u_bit_scan_consecutive_range(&writemask, &start, &count);
1829
1830 /* Due to an LLVM limitation, split 3-element writes
1831 * into a 2-element and a 1-element write. */
1832 if (count == 3) {
1833 writemask |= 1 << (start + 2);
1834 count = 2;
1835 }
1836
1837 start *= elem_size_mult;
1838 count *= elem_size_mult;
1839
1840 if (count > 4) {
1841 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1842 count = 4;
1843 }
1844
1845 if (count == 4) {
1846 store_name = "llvm.amdgcn.buffer.store.v4f32";
1847 data = base_data;
1848 } else if (count == 2) {
1849 tmp = LLVMBuildExtractElement(ctx->builder,
1850 base_data, LLVMConstInt(ctx->i32, start, false), "");
1851 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1852 ctx->i32zero, "");
1853
1854 tmp = LLVMBuildExtractElement(ctx->builder,
1855 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1856 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1857 ctx->i32one, "");
1858 store_name = "llvm.amdgcn.buffer.store.v2f32";
1859
1860 } else {
1861 assert(count == 1);
1862 if (get_llvm_num_components(base_data) > 1)
1863 data = LLVMBuildExtractElement(ctx->builder, base_data,
1864 LLVMConstInt(ctx->i32, start, false), "");
1865 else
1866 data = base_data;
1867 store_name = "llvm.amdgcn.buffer.store.f32";
1868 }
1869
1870 offset = base_offset;
1871 if (start != 0) {
1872 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1873 }
1874 params[0] = data;
1875 params[3] = offset;
1876 ac_build_intrinsic(&ctx->ac, store_name,
1877 ctx->voidt, params, 6, 0);
1878 }
1879 }
1880
1881 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1882 nir_intrinsic_instr *instr)
1883 {
1884 const char *name;
1885 LLVMValueRef params[6];
1886 int arg_count = 0;
1887 if (ctx->stage == MESA_SHADER_FRAGMENT)
1888 ctx->shader_info->fs.writes_memory = true;
1889
1890 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1891 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1892 }
1893 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1894 params[arg_count++] = get_src(ctx, instr->src[0]);
1895 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1896 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1897 params[arg_count++] = ctx->i1false; /* slc */
1898
1899 switch (instr->intrinsic) {
1900 case nir_intrinsic_ssbo_atomic_add:
1901 name = "llvm.amdgcn.buffer.atomic.add";
1902 break;
1903 case nir_intrinsic_ssbo_atomic_imin:
1904 name = "llvm.amdgcn.buffer.atomic.smin";
1905 break;
1906 case nir_intrinsic_ssbo_atomic_umin:
1907 name = "llvm.amdgcn.buffer.atomic.umin";
1908 break;
1909 case nir_intrinsic_ssbo_atomic_imax:
1910 name = "llvm.amdgcn.buffer.atomic.smax";
1911 break;
1912 case nir_intrinsic_ssbo_atomic_umax:
1913 name = "llvm.amdgcn.buffer.atomic.umax";
1914 break;
1915 case nir_intrinsic_ssbo_atomic_and:
1916 name = "llvm.amdgcn.buffer.atomic.and";
1917 break;
1918 case nir_intrinsic_ssbo_atomic_or:
1919 name = "llvm.amdgcn.buffer.atomic.or";
1920 break;
1921 case nir_intrinsic_ssbo_atomic_xor:
1922 name = "llvm.amdgcn.buffer.atomic.xor";
1923 break;
1924 case nir_intrinsic_ssbo_atomic_exchange:
1925 name = "llvm.amdgcn.buffer.atomic.swap";
1926 break;
1927 case nir_intrinsic_ssbo_atomic_comp_swap:
1928 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1929 break;
1930 default:
1931 abort();
1932 }
1933
1934 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1935 }
1936
1937 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1938 nir_intrinsic_instr *instr)
1939 {
1940 LLVMValueRef results[2];
1941 int load_components;
1942 int num_components = instr->num_components;
1943 if (instr->dest.ssa.bit_size == 64)
1944 num_components *= 2;
1945
1946 for (int i = 0; i < num_components; i += load_components) {
1947 load_components = MIN2(num_components - i, 4);
1948 const char *load_name;
1949 LLVMTypeRef data_type = ctx->f32;
1950 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
1951 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
1952
1953 if (load_components == 3)
1954 data_type = LLVMVectorType(ctx->f32, 4);
1955 else if (load_components > 1)
1956 data_type = LLVMVectorType(ctx->f32, load_components);
1957
1958 if (load_components >= 3)
1959 load_name = "llvm.amdgcn.buffer.load.v4f32";
1960 else if (load_components == 2)
1961 load_name = "llvm.amdgcn.buffer.load.v2f32";
1962 else if (load_components == 1)
1963 load_name = "llvm.amdgcn.buffer.load.f32";
1964 else
1965 unreachable("unhandled number of components");
1966
1967 LLVMValueRef params[] = {
1968 get_src(ctx, instr->src[0]),
1969 LLVMConstInt(ctx->i32, 0, false),
1970 offset,
1971 ctx->i1false,
1972 ctx->i1false,
1973 };
1974
1975 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
1976
1977 }
1978
1979 LLVMValueRef ret = results[0];
1980 if (num_components > 4 || num_components == 3) {
1981 LLVMValueRef masks[] = {
1982 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1983 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
1984 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
1985 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
1986 };
1987
1988 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1989 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
1990 results[num_components > 4 ? 1 : 0], swizzle, "");
1991 }
1992
1993 return LLVMBuildBitCast(ctx->builder, ret,
1994 get_def_type(ctx, &instr->dest.ssa), "");
1995 }
1996
1997 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
1998 nir_intrinsic_instr *instr)
1999 {
2000 LLVMValueRef results[8], ret;
2001 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2002 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2003 int num_components = instr->num_components;
2004
2005 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2006
2007 if (instr->dest.ssa.bit_size == 64)
2008 num_components *= 2;
2009
2010 for (unsigned i = 0; i < num_components; ++i) {
2011 LLVMValueRef params[] = {
2012 rsrc,
2013 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2014 offset, "")
2015 };
2016 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2017 params, 2,
2018 AC_FUNC_ATTR_READNONE |
2019 AC_FUNC_ATTR_LEGACY);
2020 }
2021
2022
2023 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2024 return LLVMBuildBitCast(ctx->builder, ret,
2025 get_def_type(ctx, &instr->dest.ssa), "");
2026 }
2027
2028 static void
2029 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2030 bool vs_in, unsigned *vertex_index_out,
2031 unsigned *const_out, LLVMValueRef *indir_out)
2032 {
2033 unsigned const_offset = 0;
2034 LLVMValueRef offset = NULL;
2035
2036 if (vertex_index_out != NULL) {
2037 tail = tail->child;
2038 nir_deref_array *deref_array = nir_deref_as_array(tail);
2039 *vertex_index_out = deref_array->base_offset;
2040 }
2041
2042 while (tail->child != NULL) {
2043 const struct glsl_type *parent_type = tail->type;
2044 tail = tail->child;
2045
2046 if (tail->deref_type == nir_deref_type_array) {
2047 nir_deref_array *deref_array = nir_deref_as_array(tail);
2048 LLVMValueRef index, stride, local_offset;
2049 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2050
2051 const_offset += size * deref_array->base_offset;
2052 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2053 continue;
2054
2055 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2056 index = get_src(ctx, deref_array->indirect);
2057 stride = LLVMConstInt(ctx->i32, size, 0);
2058 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2059
2060 if (offset)
2061 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2062 else
2063 offset = local_offset;
2064 } else if (tail->deref_type == nir_deref_type_struct) {
2065 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2066
2067 for (unsigned i = 0; i < deref_struct->index; i++) {
2068 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2069 const_offset += glsl_count_attribute_slots(ft, vs_in);
2070 }
2071 } else
2072 unreachable("unsupported deref type");
2073
2074 }
2075
2076 if (const_offset && offset)
2077 offset = LLVMBuildAdd(ctx->builder, offset,
2078 LLVMConstInt(ctx->i32, const_offset, 0),
2079 "");
2080
2081 *const_out = const_offset;
2082 *indir_out = offset;
2083 }
2084
2085 static LLVMValueRef
2086 load_gs_input(struct nir_to_llvm_context *ctx,
2087 nir_intrinsic_instr *instr)
2088 {
2089 LLVMValueRef indir_index, vtx_offset;
2090 unsigned const_index;
2091 LLVMValueRef args[9];
2092 unsigned param, vtx_offset_param;
2093 LLVMValueRef value[4], result;
2094 unsigned vertex_index;
2095 unsigned cull_offset = 0;
2096 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2097 false, &vertex_index,
2098 &const_index, &indir_index);
2099 vtx_offset_param = vertex_index;
2100 assert(vtx_offset_param < 6);
2101 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2102 LLVMConstInt(ctx->i32, 4, false), "");
2103
2104 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2105 if (instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2106 cull_offset += ctx->num_input_clips;
2107 for (unsigned i = 0; i < instr->num_components; i++) {
2108
2109 args[0] = ctx->esgs_ring;
2110 args[1] = vtx_offset;
2111 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index + cull_offset) * 256, false);
2112 args[3] = ctx->i32zero;
2113 args[4] = ctx->i32one; /* OFFEN */
2114 args[5] = ctx->i32zero; /* IDXEN */
2115 args[6] = ctx->i32one; /* GLC */
2116 args[7] = ctx->i32zero; /* SLC */
2117 args[8] = ctx->i32zero; /* TFE */
2118
2119 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2120 ctx->i32, args, 9,
2121 AC_FUNC_ATTR_READONLY |
2122 AC_FUNC_ATTR_LEGACY);
2123 }
2124 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2125
2126 return result;
2127 }
2128
2129 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2130 nir_intrinsic_instr *instr)
2131 {
2132 LLVMValueRef values[8];
2133 int idx = instr->variables[0]->var->data.driver_location;
2134 int ve = instr->dest.ssa.num_components;
2135 LLVMValueRef indir_index;
2136 LLVMValueRef ret;
2137 unsigned const_index;
2138 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2139 instr->variables[0]->var->data.mode == nir_var_shader_in;
2140 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2141 &const_index, &indir_index);
2142
2143 if (instr->dest.ssa.bit_size == 64)
2144 ve *= 2;
2145
2146 switch (instr->variables[0]->var->data.mode) {
2147 case nir_var_shader_in:
2148 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2149 return load_gs_input(ctx, instr);
2150 }
2151 for (unsigned chan = 0; chan < ve; chan++) {
2152 if (indir_index) {
2153 unsigned count = glsl_count_attribute_slots(
2154 instr->variables[0]->var->type,
2155 ctx->stage == MESA_SHADER_VERTEX);
2156 count -= chan / 4;
2157 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2158 &ctx->ac, ctx->inputs + idx + chan, count,
2159 4, false);
2160
2161 values[chan] = LLVMBuildExtractElement(ctx->builder,
2162 tmp_vec,
2163 indir_index, "");
2164 } else
2165 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2166 }
2167 break;
2168 case nir_var_local:
2169 for (unsigned chan = 0; chan < ve; chan++) {
2170 if (indir_index) {
2171 unsigned count = glsl_count_attribute_slots(
2172 instr->variables[0]->var->type, false);
2173 count -= chan / 4;
2174 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2175 &ctx->ac, ctx->locals + idx + chan, count,
2176 4, true);
2177
2178 values[chan] = LLVMBuildExtractElement(ctx->builder,
2179 tmp_vec,
2180 indir_index, "");
2181 } else {
2182 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2183 }
2184 }
2185 break;
2186 case nir_var_shader_out:
2187 for (unsigned chan = 0; chan < ve; chan++) {
2188 if (indir_index) {
2189 unsigned count = glsl_count_attribute_slots(
2190 instr->variables[0]->var->type, false);
2191 count -= chan / 4;
2192 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2193 &ctx->ac, ctx->outputs + idx + chan, count,
2194 4, true);
2195
2196 values[chan] = LLVMBuildExtractElement(ctx->builder,
2197 tmp_vec,
2198 indir_index, "");
2199 } else {
2200 values[chan] = LLVMBuildLoad(ctx->builder,
2201 ctx->outputs[idx + chan + const_index * 4],
2202 "");
2203 }
2204 }
2205 break;
2206 case nir_var_shared: {
2207 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2208 LLVMValueRef derived_ptr;
2209
2210 if (indir_index)
2211 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2212
2213 for (unsigned chan = 0; chan < ve; chan++) {
2214 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2215 if (indir_index)
2216 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2217 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2218
2219 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2220 }
2221 break;
2222 }
2223 default:
2224 unreachable("unhandle variable mode");
2225 }
2226 ret = ac_build_gather_values(&ctx->ac, values, ve);
2227 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2228 }
2229
2230 static void
2231 visit_store_var(struct nir_to_llvm_context *ctx,
2232 nir_intrinsic_instr *instr)
2233 {
2234 LLVMValueRef temp_ptr, value;
2235 int idx = instr->variables[0]->var->data.driver_location;
2236 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2237 int writemask = instr->const_index[0];
2238 LLVMValueRef indir_index;
2239 unsigned const_index;
2240 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2241 NULL, &const_index, &indir_index);
2242
2243 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2244 int old_writemask = writemask;
2245
2246 src = LLVMBuildBitCast(ctx->builder, src,
2247 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2248 "");
2249
2250 writemask = 0;
2251 for (unsigned chan = 0; chan < 4; chan++) {
2252 if (old_writemask & (1 << chan))
2253 writemask |= 3u << (2 * chan);
2254 }
2255 }
2256
2257 switch (instr->variables[0]->var->data.mode) {
2258 case nir_var_shader_out:
2259 for (unsigned chan = 0; chan < 8; chan++) {
2260 int stride = 4;
2261 if (!(writemask & (1 << chan)))
2262 continue;
2263
2264 value = llvm_extract_elem(ctx, src, chan);
2265
2266 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2267 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2268 stride = 1;
2269 if (indir_index) {
2270 unsigned count = glsl_count_attribute_slots(
2271 instr->variables[0]->var->type, false);
2272 count -= chan / 4;
2273 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2274 &ctx->ac, ctx->outputs + idx + chan, count,
2275 stride, true);
2276
2277 if (get_llvm_num_components(tmp_vec) > 1) {
2278 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2279 value, indir_index, "");
2280 } else
2281 tmp_vec = value;
2282 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2283 count, stride, tmp_vec);
2284
2285 } else {
2286 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2287
2288 LLVMBuildStore(ctx->builder, value, temp_ptr);
2289 }
2290 }
2291 break;
2292 case nir_var_local:
2293 for (unsigned chan = 0; chan < 8; chan++) {
2294 if (!(writemask & (1 << chan)))
2295 continue;
2296
2297 value = llvm_extract_elem(ctx, src, chan);
2298 if (indir_index) {
2299 unsigned count = glsl_count_attribute_slots(
2300 instr->variables[0]->var->type, false);
2301 count -= chan / 4;
2302 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2303 &ctx->ac, ctx->locals + idx + chan, count,
2304 4, true);
2305
2306 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2307 value, indir_index, "");
2308 build_store_values_extended(ctx, ctx->locals + idx + chan,
2309 count, 4, tmp_vec);
2310 } else {
2311 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2312
2313 LLVMBuildStore(ctx->builder, value, temp_ptr);
2314 }
2315 }
2316 break;
2317 case nir_var_shared: {
2318 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2319
2320 if (indir_index)
2321 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2322
2323 for (unsigned chan = 0; chan < 8; chan++) {
2324 if (!(writemask & (1 << chan)))
2325 continue;
2326 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2327 LLVMValueRef derived_ptr;
2328
2329 if (indir_index)
2330 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2331
2332 value = llvm_extract_elem(ctx, src, chan);
2333 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2334 LLVMBuildStore(ctx->builder,
2335 to_integer(ctx, value), derived_ptr);
2336 }
2337 break;
2338 }
2339 default:
2340 break;
2341 }
2342 }
2343
2344 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2345 {
2346 switch (dim) {
2347 case GLSL_SAMPLER_DIM_BUF:
2348 return 1;
2349 case GLSL_SAMPLER_DIM_1D:
2350 return array ? 2 : 1;
2351 case GLSL_SAMPLER_DIM_2D:
2352 return array ? 3 : 2;
2353 case GLSL_SAMPLER_DIM_MS:
2354 return array ? 4 : 3;
2355 case GLSL_SAMPLER_DIM_3D:
2356 case GLSL_SAMPLER_DIM_CUBE:
2357 return 3;
2358 case GLSL_SAMPLER_DIM_RECT:
2359 case GLSL_SAMPLER_DIM_SUBPASS:
2360 return 2;
2361 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2362 return 3;
2363 default:
2364 break;
2365 }
2366 return 0;
2367 }
2368
2369
2370
2371 /* Adjust the sample index according to FMASK.
2372 *
2373 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2374 * which is the identity mapping. Each nibble says which physical sample
2375 * should be fetched to get that sample.
2376 *
2377 * For example, 0x11111100 means there are only 2 samples stored and
2378 * the second sample covers 3/4 of the pixel. When reading samples 0
2379 * and 1, return physical sample 0 (determined by the first two 0s
2380 * in FMASK), otherwise return physical sample 1.
2381 *
2382 * The sample index should be adjusted as follows:
2383 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2384 */
2385 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
2386 LLVMValueRef coord_x, LLVMValueRef coord_y,
2387 LLVMValueRef coord_z,
2388 LLVMValueRef sample_index,
2389 LLVMValueRef fmask_desc_ptr)
2390 {
2391 LLVMValueRef fmask_load_address[4];
2392 LLVMValueRef res;
2393
2394 fmask_load_address[0] = coord_x;
2395 fmask_load_address[1] = coord_y;
2396 if (coord_z) {
2397 fmask_load_address[2] = coord_z;
2398 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
2399 }
2400
2401 struct ac_image_args args = {0};
2402
2403 args.opcode = ac_image_load;
2404 args.da = coord_z ? true : false;
2405 args.resource = fmask_desc_ptr;
2406 args.dmask = 0xf;
2407 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
2408
2409 res = ac_build_image_opcode(&ctx->ac, &args);
2410
2411 res = to_integer(ctx, res);
2412 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
2413 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
2414
2415 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
2416 res,
2417 ctx->i32zero, "");
2418
2419 LLVMValueRef sample_index4 =
2420 LLVMBuildMul(ctx->builder, sample_index, four, "");
2421 LLVMValueRef shifted_fmask =
2422 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
2423 LLVMValueRef final_sample =
2424 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
2425
2426 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2427 * resource descriptor is 0 (invalid),
2428 */
2429 LLVMValueRef fmask_desc =
2430 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
2431 ctx->v8i32, "");
2432
2433 LLVMValueRef fmask_word1 =
2434 LLVMBuildExtractElement(ctx->builder, fmask_desc,
2435 ctx->i32one, "");
2436
2437 LLVMValueRef word1_is_nonzero =
2438 LLVMBuildICmp(ctx->builder, LLVMIntNE,
2439 fmask_word1, ctx->i32zero, "");
2440
2441 /* Replace the MSAA sample index. */
2442 sample_index =
2443 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
2444 final_sample, sample_index, "");
2445 return sample_index;
2446 }
2447
2448 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2449 nir_intrinsic_instr *instr)
2450 {
2451 const struct glsl_type *type = instr->variables[0]->var->type;
2452 if(instr->variables[0]->deref.child)
2453 type = instr->variables[0]->deref.child->type;
2454
2455 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2456 LLVMValueRef coords[4];
2457 LLVMValueRef masks[] = {
2458 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2459 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2460 };
2461 LLVMValueRef res;
2462 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2463
2464 int count;
2465 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2466 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2467 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2468 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2469 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2470
2471 count = image_type_to_components_count(dim,
2472 glsl_sampler_type_is_array(type));
2473
2474 if (is_ms) {
2475 LLVMValueRef fmask_load_address[3];
2476 int chan;
2477
2478 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2479 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
2480 if (glsl_sampler_type_is_array(type))
2481 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
2482 else
2483 fmask_load_address[2] = NULL;
2484 if (add_frag_pos) {
2485 for (chan = 0; chan < 2; ++chan)
2486 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2487 }
2488 sample_index = adjust_sample_index_using_fmask(ctx,
2489 fmask_load_address[0],
2490 fmask_load_address[1],
2491 fmask_load_address[2],
2492 sample_index,
2493 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
2494 }
2495 if (count == 1) {
2496 if (instr->src[0].ssa->num_components)
2497 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2498 else
2499 res = src0;
2500 } else {
2501 int chan;
2502 if (is_ms)
2503 count--;
2504 for (chan = 0; chan < count; ++chan) {
2505 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2506 }
2507
2508 if (add_frag_pos) {
2509 for (chan = 0; chan < count; ++chan)
2510 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2511 }
2512 if (is_ms) {
2513 coords[count] = sample_index;
2514 count++;
2515 }
2516
2517 if (count == 3) {
2518 coords[3] = LLVMGetUndef(ctx->i32);
2519 count = 4;
2520 }
2521 res = ac_build_gather_values(&ctx->ac, coords, count);
2522 }
2523 return res;
2524 }
2525
2526 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2527 nir_intrinsic_instr *instr)
2528 {
2529 LLVMValueRef params[7];
2530 LLVMValueRef res;
2531 char intrinsic_name[64];
2532 const nir_variable *var = instr->variables[0]->var;
2533 const struct glsl_type *type = var->type;
2534 if(instr->variables[0]->deref.child)
2535 type = instr->variables[0]->deref.child->type;
2536
2537 type = glsl_without_array(type);
2538 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2539 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2540 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2541 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2542 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2543 params[3] = ctx->i1false; /* glc */
2544 params[4] = ctx->i1false; /* slc */
2545 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2546 params, 5, 0);
2547
2548 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2549 res = to_integer(ctx, res);
2550 } else {
2551 bool is_da = glsl_sampler_type_is_array(type) ||
2552 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2553 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
2554 LLVMValueRef glc = ctx->i1false;
2555 LLVMValueRef slc = ctx->i1false;
2556
2557 params[0] = get_image_coords(ctx, instr);
2558 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2559 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2560 if (HAVE_LLVM <= 0x0309) {
2561 params[3] = ctx->i1false; /* r128 */
2562 params[4] = da;
2563 params[5] = glc;
2564 params[6] = slc;
2565 } else {
2566 LLVMValueRef lwe = ctx->i1false;
2567 params[3] = glc;
2568 params[4] = slc;
2569 params[5] = lwe;
2570 params[6] = da;
2571 }
2572
2573 ac_get_image_intr_name("llvm.amdgcn.image.load",
2574 ctx->v4f32, /* vdata */
2575 LLVMTypeOf(params[0]), /* coords */
2576 LLVMTypeOf(params[1]), /* rsrc */
2577 intrinsic_name, sizeof(intrinsic_name));
2578
2579 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2580 params, 7, AC_FUNC_ATTR_READONLY);
2581 }
2582 return to_integer(ctx, res);
2583 }
2584
2585 static void visit_image_store(struct nir_to_llvm_context *ctx,
2586 nir_intrinsic_instr *instr)
2587 {
2588 LLVMValueRef params[8];
2589 char intrinsic_name[64];
2590 const nir_variable *var = instr->variables[0]->var;
2591 const struct glsl_type *type = glsl_without_array(var->type);
2592
2593 if (ctx->stage == MESA_SHADER_FRAGMENT)
2594 ctx->shader_info->fs.writes_memory = true;
2595
2596 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2597 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2598 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2599 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2600 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2601 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2602 params[4] = ctx->i1false; /* glc */
2603 params[5] = ctx->i1false; /* slc */
2604 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2605 params, 6, 0);
2606 } else {
2607 bool is_da = glsl_sampler_type_is_array(type) ||
2608 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2609 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
2610 LLVMValueRef glc = ctx->i1false;
2611 LLVMValueRef slc = ctx->i1false;
2612
2613 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2614 params[1] = get_image_coords(ctx, instr); /* coords */
2615 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2616 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2617 if (HAVE_LLVM <= 0x0309) {
2618 params[4] = ctx->i1false; /* r128 */
2619 params[5] = da;
2620 params[6] = glc;
2621 params[7] = slc;
2622 } else {
2623 LLVMValueRef lwe = ctx->i1false;
2624 params[4] = glc;
2625 params[5] = slc;
2626 params[6] = lwe;
2627 params[7] = da;
2628 }
2629
2630 ac_get_image_intr_name("llvm.amdgcn.image.store",
2631 LLVMTypeOf(params[0]), /* vdata */
2632 LLVMTypeOf(params[1]), /* coords */
2633 LLVMTypeOf(params[2]), /* rsrc */
2634 intrinsic_name, sizeof(intrinsic_name));
2635
2636 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2637 params, 8, 0);
2638 }
2639
2640 }
2641
2642 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2643 nir_intrinsic_instr *instr)
2644 {
2645 LLVMValueRef params[6];
2646 int param_count = 0;
2647 const nir_variable *var = instr->variables[0]->var;
2648
2649 const char *base_name = "llvm.amdgcn.image.atomic";
2650 const char *atomic_name;
2651 LLVMValueRef coords;
2652 char intrinsic_name[32], coords_type[8];
2653 const struct glsl_type *type = glsl_without_array(var->type);
2654
2655 if (ctx->stage == MESA_SHADER_FRAGMENT)
2656 ctx->shader_info->fs.writes_memory = true;
2657
2658 params[param_count++] = get_src(ctx, instr->src[2]);
2659 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2660 params[param_count++] = get_src(ctx, instr->src[3]);
2661
2662 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2663 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2664 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2665 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2666 params[param_count++] = ctx->i32zero; /* voffset */
2667 params[param_count++] = ctx->i1false; /* glc */
2668 params[param_count++] = ctx->i1false; /* slc */
2669 } else {
2670 bool da = glsl_sampler_type_is_array(type) ||
2671 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2672
2673 coords = params[param_count++] = get_image_coords(ctx, instr);
2674 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2675 params[param_count++] = ctx->i1false; /* r128 */
2676 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
2677 params[param_count++] = ctx->i1false; /* slc */
2678 }
2679
2680 switch (instr->intrinsic) {
2681 case nir_intrinsic_image_atomic_add:
2682 atomic_name = "add";
2683 break;
2684 case nir_intrinsic_image_atomic_min:
2685 atomic_name = "smin";
2686 break;
2687 case nir_intrinsic_image_atomic_max:
2688 atomic_name = "smax";
2689 break;
2690 case nir_intrinsic_image_atomic_and:
2691 atomic_name = "and";
2692 break;
2693 case nir_intrinsic_image_atomic_or:
2694 atomic_name = "or";
2695 break;
2696 case nir_intrinsic_image_atomic_xor:
2697 atomic_name = "xor";
2698 break;
2699 case nir_intrinsic_image_atomic_exchange:
2700 atomic_name = "swap";
2701 break;
2702 case nir_intrinsic_image_atomic_comp_swap:
2703 atomic_name = "cmpswap";
2704 break;
2705 default:
2706 abort();
2707 }
2708 build_int_type_name(LLVMTypeOf(coords),
2709 coords_type, sizeof(coords_type));
2710
2711 snprintf(intrinsic_name, sizeof(intrinsic_name),
2712 "%s.%s.%s", base_name, atomic_name, coords_type);
2713 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2714 }
2715
2716 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2717 nir_intrinsic_instr *instr)
2718 {
2719 LLVMValueRef res;
2720 const nir_variable *var = instr->variables[0]->var;
2721 const struct glsl_type *type = instr->variables[0]->var->type;
2722 bool da = glsl_sampler_type_is_array(var->type) ||
2723 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2724 if(instr->variables[0]->deref.child)
2725 type = instr->variables[0]->deref.child->type;
2726
2727 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2728 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2729
2730 struct ac_image_args args = { 0 };
2731
2732 args.da = da;
2733 args.dmask = 0xf;
2734 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2735 args.opcode = ac_image_get_resinfo;
2736 args.addr = ctx->i32zero;
2737
2738 res = ac_build_image_opcode(&ctx->ac, &args);
2739
2740 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2741 glsl_sampler_type_is_array(type)) {
2742 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2743 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2744 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2745 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2746 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2747 }
2748 return res;
2749 }
2750
2751 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2752 {
2753 LLVMValueRef args[1] = {
2754 LLVMConstInt(ctx->i32, 0xf70, false),
2755 };
2756 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2757 ctx->voidt, args, 1, 0);
2758 }
2759
2760 static void emit_barrier(struct nir_to_llvm_context *ctx)
2761 {
2762 // TODO tess
2763 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2764 ctx->voidt, NULL, 0, 0);
2765 }
2766
2767 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2768 nir_intrinsic_instr *instr)
2769 {
2770 LLVMValueRef cond;
2771 ctx->shader_info->fs.can_discard = true;
2772
2773 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2774 get_src(ctx, instr->src[0]),
2775 ctx->i32zero, "");
2776
2777 cond = LLVMBuildSelect(ctx->builder, cond,
2778 LLVMConstReal(ctx->f32, -1.0f),
2779 ctx->f32zero, "");
2780 ac_build_kill(&ctx->ac, cond);
2781 }
2782
2783 static LLVMValueRef
2784 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2785 {
2786 LLVMValueRef result;
2787 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2788 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2789 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2790
2791 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2792 }
2793
2794 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2795 nir_intrinsic_instr *instr)
2796 {
2797 LLVMValueRef ptr, result;
2798 int idx = instr->variables[0]->var->data.driver_location;
2799 LLVMValueRef src = get_src(ctx, instr->src[0]);
2800 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2801
2802 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2803 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2804 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2805 ptr, src, src1,
2806 LLVMAtomicOrderingSequentiallyConsistent,
2807 LLVMAtomicOrderingSequentiallyConsistent,
2808 false);
2809 } else {
2810 LLVMAtomicRMWBinOp op;
2811 switch (instr->intrinsic) {
2812 case nir_intrinsic_var_atomic_add:
2813 op = LLVMAtomicRMWBinOpAdd;
2814 break;
2815 case nir_intrinsic_var_atomic_umin:
2816 op = LLVMAtomicRMWBinOpUMin;
2817 break;
2818 case nir_intrinsic_var_atomic_umax:
2819 op = LLVMAtomicRMWBinOpUMax;
2820 break;
2821 case nir_intrinsic_var_atomic_imin:
2822 op = LLVMAtomicRMWBinOpMin;
2823 break;
2824 case nir_intrinsic_var_atomic_imax:
2825 op = LLVMAtomicRMWBinOpMax;
2826 break;
2827 case nir_intrinsic_var_atomic_and:
2828 op = LLVMAtomicRMWBinOpAnd;
2829 break;
2830 case nir_intrinsic_var_atomic_or:
2831 op = LLVMAtomicRMWBinOpOr;
2832 break;
2833 case nir_intrinsic_var_atomic_xor:
2834 op = LLVMAtomicRMWBinOpXor;
2835 break;
2836 case nir_intrinsic_var_atomic_exchange:
2837 op = LLVMAtomicRMWBinOpXchg;
2838 break;
2839 default:
2840 return NULL;
2841 }
2842
2843 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2844 LLVMAtomicOrderingSequentiallyConsistent,
2845 false);
2846 }
2847 return result;
2848 }
2849
2850 #define INTERP_CENTER 0
2851 #define INTERP_CENTROID 1
2852 #define INTERP_SAMPLE 2
2853
2854 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2855 enum glsl_interp_mode interp, unsigned location)
2856 {
2857 switch (interp) {
2858 case INTERP_MODE_FLAT:
2859 default:
2860 return NULL;
2861 case INTERP_MODE_SMOOTH:
2862 case INTERP_MODE_NONE:
2863 if (location == INTERP_CENTER)
2864 return ctx->persp_center;
2865 else if (location == INTERP_CENTROID)
2866 return ctx->persp_centroid;
2867 else if (location == INTERP_SAMPLE)
2868 return ctx->persp_sample;
2869 break;
2870 case INTERP_MODE_NOPERSPECTIVE:
2871 if (location == INTERP_CENTER)
2872 return ctx->linear_center;
2873 else if (location == INTERP_CENTROID)
2874 return ctx->linear_centroid;
2875 else if (location == INTERP_SAMPLE)
2876 return ctx->linear_sample;
2877 break;
2878 }
2879 return NULL;
2880 }
2881
2882 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2883 LLVMValueRef sample_id)
2884 {
2885 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2886 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2887 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2888 LLVMValueRef result[2];
2889
2890 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2891 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2892
2893 return ac_build_gather_values(&ctx->ac, result, 2);
2894 }
2895
2896 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2897 {
2898 LLVMValueRef values[2];
2899
2900 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2901 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2902 return ac_build_gather_values(&ctx->ac, values, 2);
2903 }
2904
2905 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2906 nir_intrinsic_instr *instr)
2907 {
2908 LLVMValueRef result[2];
2909 LLVMValueRef interp_param, attr_number;
2910 unsigned location;
2911 unsigned chan;
2912 LLVMValueRef src_c0, src_c1;
2913 LLVMValueRef src0;
2914 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2915 switch (instr->intrinsic) {
2916 case nir_intrinsic_interp_var_at_centroid:
2917 location = INTERP_CENTROID;
2918 break;
2919 case nir_intrinsic_interp_var_at_sample:
2920 location = INTERP_SAMPLE;
2921 src0 = get_src(ctx, instr->src[0]);
2922 break;
2923 case nir_intrinsic_interp_var_at_offset:
2924 location = INTERP_CENTER;
2925 src0 = get_src(ctx, instr->src[0]);
2926 default:
2927 break;
2928 }
2929
2930 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2931 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2932 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2933 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2934 LLVMValueRef sample_position;
2935 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2936
2937 /* fetch sample ID */
2938 sample_position = load_sample_position(ctx, src0);
2939
2940 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2941 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2942 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2943 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2944 }
2945 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2946 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2947
2948 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
2949 LLVMValueRef ij_out[2];
2950 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2951
2952 /*
2953 * take the I then J parameters, and the DDX/Y for it, and
2954 * calculate the IJ inputs for the interpolator.
2955 * temp1 = ddx * offset/sample.x + I;
2956 * interp_param.I = ddy * offset/sample.y + temp1;
2957 * temp1 = ddx * offset/sample.x + J;
2958 * interp_param.J = ddy * offset/sample.y + temp1;
2959 */
2960 for (unsigned i = 0; i < 2; i++) {
2961 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
2962 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
2963 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
2964 ddxy_out, ix_ll, "");
2965 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
2966 ddxy_out, iy_ll, "");
2967 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
2968 interp_param, ix_ll, "");
2969 LLVMValueRef temp1, temp2;
2970
2971 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
2972 ctx->f32, "");
2973
2974 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
2975 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
2976
2977 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
2978 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
2979
2980 ij_out[i] = LLVMBuildBitCast(ctx->builder,
2981 temp2, ctx->i32, "");
2982 }
2983 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
2984
2985 }
2986
2987 for (chan = 0; chan < 2; chan++) {
2988 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
2989
2990 if (interp_param) {
2991 interp_param = LLVMBuildBitCast(ctx->builder,
2992 interp_param, LLVMVectorType(ctx->f32, 2), "");
2993 LLVMValueRef i = LLVMBuildExtractElement(
2994 ctx->builder, interp_param, ctx->i32zero, "");
2995 LLVMValueRef j = LLVMBuildExtractElement(
2996 ctx->builder, interp_param, ctx->i32one, "");
2997
2998 result[chan] = ac_build_fs_interp(&ctx->ac,
2999 llvm_chan, attr_number,
3000 ctx->prim_mask, i, j);
3001 } else {
3002 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3003 LLVMConstInt(ctx->i32, 2, false),
3004 llvm_chan, attr_number,
3005 ctx->prim_mask);
3006 }
3007 }
3008 return ac_build_gather_values(&ctx->ac, result, 2);
3009 }
3010
3011 static void
3012 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3013 nir_intrinsic_instr *instr)
3014 {
3015 LLVMValueRef gs_next_vertex;
3016 LLVMValueRef can_emit, kill;
3017 int idx;
3018 int clip_cull_slot = -1;
3019 assert(instr->const_index[0] == 0);
3020 /* Write vertex attribute values to GSVS ring */
3021 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3022 ctx->gs_next_vertex,
3023 "");
3024
3025 /* If this thread has already emitted the declared maximum number of
3026 * vertices, kill it: excessive vertex emissions are not supposed to
3027 * have any effect, and GS threads have no externally observable
3028 * effects other than emitting vertices.
3029 */
3030 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3031 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3032
3033 kill = LLVMBuildSelect(ctx->builder, can_emit,
3034 LLVMConstReal(ctx->f32, 1.0f),
3035 LLVMConstReal(ctx->f32, -1.0f), "");
3036 ac_build_kill(&ctx->ac, kill);
3037
3038 /* loop num outputs */
3039 idx = 0;
3040 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3041 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3042 int length = 4;
3043 int start = 0;
3044 int slot = idx;
3045 int slot_inc = 1;
3046
3047 if (!(ctx->output_mask & (1ull << i)))
3048 continue;
3049
3050 if (i == VARYING_SLOT_CLIP_DIST1 ||
3051 i == VARYING_SLOT_CULL_DIST1)
3052 continue;
3053
3054 if (i == VARYING_SLOT_CLIP_DIST0 ||
3055 i == VARYING_SLOT_CULL_DIST0) {
3056 /* pack clip and cull into a single set of slots */
3057 if (clip_cull_slot == -1) {
3058 clip_cull_slot = idx;
3059 if (ctx->num_output_clips + ctx->num_output_culls > 4)
3060 slot_inc = 2;
3061 } else {
3062 slot = clip_cull_slot;
3063 slot_inc = 0;
3064 }
3065 if (i == VARYING_SLOT_CLIP_DIST0)
3066 length = ctx->num_output_clips;
3067 if (i == VARYING_SLOT_CULL_DIST0) {
3068 start = ctx->num_output_clips;
3069 length = ctx->num_output_culls;
3070 }
3071 }
3072 for (unsigned j = 0; j < length; j++) {
3073 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3074 out_ptr[j], "");
3075 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j + start) * ctx->gs_max_out_vertices, false);
3076 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3077 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3078
3079 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3080
3081 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3082 out_val, 1,
3083 voffset, ctx->gs2vs_offset, 0,
3084 1, 1, true, true);
3085 }
3086 idx += slot_inc;
3087 }
3088
3089 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3090 ctx->i32one, "");
3091 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3092
3093 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3094 }
3095
3096 static void
3097 visit_end_primitive(struct nir_to_llvm_context *ctx,
3098 nir_intrinsic_instr *instr)
3099 {
3100 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3101 }
3102
3103 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3104 nir_intrinsic_instr *instr)
3105 {
3106 LLVMValueRef result = NULL;
3107
3108 switch (instr->intrinsic) {
3109 case nir_intrinsic_load_work_group_id: {
3110 result = ctx->workgroup_ids;
3111 break;
3112 }
3113 case nir_intrinsic_load_base_vertex: {
3114 result = ctx->base_vertex;
3115 break;
3116 }
3117 case nir_intrinsic_load_vertex_id_zero_base: {
3118 result = ctx->vertex_id;
3119 break;
3120 }
3121 case nir_intrinsic_load_local_invocation_id: {
3122 result = ctx->local_invocation_ids;
3123 break;
3124 }
3125 case nir_intrinsic_load_base_instance:
3126 result = ctx->start_instance;
3127 break;
3128 case nir_intrinsic_load_draw_id:
3129 result = ctx->draw_index;
3130 break;
3131 case nir_intrinsic_load_invocation_id:
3132 result = ctx->gs_invocation_id;
3133 break;
3134 case nir_intrinsic_load_primitive_id:
3135 if (ctx->stage == MESA_SHADER_GEOMETRY)
3136 result = ctx->gs_prim_id;
3137 else
3138 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3139 break;
3140 case nir_intrinsic_load_sample_id:
3141 ctx->shader_info->fs.force_persample = true;
3142 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3143 break;
3144 case nir_intrinsic_load_sample_pos:
3145 ctx->shader_info->fs.force_persample = true;
3146 result = load_sample_pos(ctx);
3147 break;
3148 case nir_intrinsic_load_sample_mask_in:
3149 result = ctx->sample_coverage;
3150 break;
3151 case nir_intrinsic_load_front_face:
3152 result = ctx->front_face;
3153 break;
3154 case nir_intrinsic_load_instance_id:
3155 result = ctx->instance_id;
3156 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3157 ctx->shader_info->vs.vgpr_comp_cnt);
3158 break;
3159 case nir_intrinsic_load_num_work_groups:
3160 result = ctx->num_work_groups;
3161 break;
3162 case nir_intrinsic_load_local_invocation_index:
3163 result = visit_load_local_invocation_index(ctx);
3164 break;
3165 case nir_intrinsic_load_push_constant:
3166 result = visit_load_push_constant(ctx, instr);
3167 break;
3168 case nir_intrinsic_vulkan_resource_index:
3169 result = visit_vulkan_resource_index(ctx, instr);
3170 break;
3171 case nir_intrinsic_store_ssbo:
3172 visit_store_ssbo(ctx, instr);
3173 break;
3174 case nir_intrinsic_load_ssbo:
3175 result = visit_load_buffer(ctx, instr);
3176 break;
3177 case nir_intrinsic_ssbo_atomic_add:
3178 case nir_intrinsic_ssbo_atomic_imin:
3179 case nir_intrinsic_ssbo_atomic_umin:
3180 case nir_intrinsic_ssbo_atomic_imax:
3181 case nir_intrinsic_ssbo_atomic_umax:
3182 case nir_intrinsic_ssbo_atomic_and:
3183 case nir_intrinsic_ssbo_atomic_or:
3184 case nir_intrinsic_ssbo_atomic_xor:
3185 case nir_intrinsic_ssbo_atomic_exchange:
3186 case nir_intrinsic_ssbo_atomic_comp_swap:
3187 result = visit_atomic_ssbo(ctx, instr);
3188 break;
3189 case nir_intrinsic_load_ubo:
3190 result = visit_load_ubo_buffer(ctx, instr);
3191 break;
3192 case nir_intrinsic_get_buffer_size:
3193 result = visit_get_buffer_size(ctx, instr);
3194 break;
3195 case nir_intrinsic_load_var:
3196 result = visit_load_var(ctx, instr);
3197 break;
3198 case nir_intrinsic_store_var:
3199 visit_store_var(ctx, instr);
3200 break;
3201 case nir_intrinsic_image_load:
3202 result = visit_image_load(ctx, instr);
3203 break;
3204 case nir_intrinsic_image_store:
3205 visit_image_store(ctx, instr);
3206 break;
3207 case nir_intrinsic_image_atomic_add:
3208 case nir_intrinsic_image_atomic_min:
3209 case nir_intrinsic_image_atomic_max:
3210 case nir_intrinsic_image_atomic_and:
3211 case nir_intrinsic_image_atomic_or:
3212 case nir_intrinsic_image_atomic_xor:
3213 case nir_intrinsic_image_atomic_exchange:
3214 case nir_intrinsic_image_atomic_comp_swap:
3215 result = visit_image_atomic(ctx, instr);
3216 break;
3217 case nir_intrinsic_image_size:
3218 result = visit_image_size(ctx, instr);
3219 break;
3220 case nir_intrinsic_discard:
3221 ctx->shader_info->fs.can_discard = true;
3222 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3223 ctx->voidt,
3224 NULL, 0, AC_FUNC_ATTR_LEGACY);
3225 break;
3226 case nir_intrinsic_discard_if:
3227 emit_discard_if(ctx, instr);
3228 break;
3229 case nir_intrinsic_memory_barrier:
3230 emit_waitcnt(ctx);
3231 break;
3232 case nir_intrinsic_barrier:
3233 emit_barrier(ctx);
3234 break;
3235 case nir_intrinsic_var_atomic_add:
3236 case nir_intrinsic_var_atomic_imin:
3237 case nir_intrinsic_var_atomic_umin:
3238 case nir_intrinsic_var_atomic_imax:
3239 case nir_intrinsic_var_atomic_umax:
3240 case nir_intrinsic_var_atomic_and:
3241 case nir_intrinsic_var_atomic_or:
3242 case nir_intrinsic_var_atomic_xor:
3243 case nir_intrinsic_var_atomic_exchange:
3244 case nir_intrinsic_var_atomic_comp_swap:
3245 result = visit_var_atomic(ctx, instr);
3246 break;
3247 case nir_intrinsic_interp_var_at_centroid:
3248 case nir_intrinsic_interp_var_at_sample:
3249 case nir_intrinsic_interp_var_at_offset:
3250 result = visit_interp(ctx, instr);
3251 break;
3252 case nir_intrinsic_emit_vertex:
3253 visit_emit_vertex(ctx, instr);
3254 break;
3255 case nir_intrinsic_end_primitive:
3256 visit_end_primitive(ctx, instr);
3257 break;
3258 default:
3259 fprintf(stderr, "Unknown intrinsic: ");
3260 nir_print_instr(&instr->instr, stderr);
3261 fprintf(stderr, "\n");
3262 break;
3263 }
3264 if (result) {
3265 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3266 }
3267 }
3268
3269 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3270 nir_deref_var *deref,
3271 enum desc_type desc_type)
3272 {
3273 unsigned desc_set = deref->var->data.descriptor_set;
3274 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3275 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3276 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3277 unsigned offset = binding->offset;
3278 unsigned stride = binding->size;
3279 unsigned type_size;
3280 LLVMBuilderRef builder = ctx->builder;
3281 LLVMTypeRef type;
3282 LLVMValueRef index = NULL;
3283 unsigned constant_index = 0;
3284
3285 assert(deref->var->data.binding < layout->binding_count);
3286
3287 switch (desc_type) {
3288 case DESC_IMAGE:
3289 type = ctx->v8i32;
3290 type_size = 32;
3291 break;
3292 case DESC_FMASK:
3293 type = ctx->v8i32;
3294 offset += 32;
3295 type_size = 32;
3296 break;
3297 case DESC_SAMPLER:
3298 type = ctx->v4i32;
3299 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3300 offset += 64;
3301
3302 type_size = 16;
3303 break;
3304 case DESC_BUFFER:
3305 type = ctx->v4i32;
3306 type_size = 16;
3307 break;
3308 default:
3309 unreachable("invalid desc_type\n");
3310 }
3311
3312 if (deref->deref.child) {
3313 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3314
3315 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3316 offset += child->base_offset * stride;
3317 if (child->deref_array_type == nir_deref_array_type_indirect) {
3318 index = get_src(ctx, child->indirect);
3319 }
3320
3321 constant_index = child->base_offset;
3322 }
3323 if (desc_type == DESC_SAMPLER && binding->immutable_samplers &&
3324 (!index || binding->immutable_samplers_equal)) {
3325 if (binding->immutable_samplers_equal)
3326 constant_index = 0;
3327
3328 LLVMValueRef constants[] = {
3329 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 0], 0),
3330 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 1], 0),
3331 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 2], 0),
3332 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 3], 0),
3333 };
3334 return ac_build_gather_values(&ctx->ac, constants, 4);
3335 }
3336
3337 assert(stride % type_size == 0);
3338
3339 if (!index)
3340 index = ctx->i32zero;
3341
3342 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3343
3344 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3345 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3346
3347 return ac_build_indexed_load_const(&ctx->ac, list, index);
3348 }
3349
3350 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3351 struct ac_image_args *args,
3352 nir_tex_instr *instr,
3353 nir_texop op,
3354 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3355 LLVMValueRef *param, unsigned count,
3356 unsigned dmask)
3357 {
3358 unsigned is_rect = 0;
3359 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3360
3361 if (op == nir_texop_lod)
3362 da = false;
3363 /* Pad to power of two vector */
3364 while (count < util_next_power_of_two(count))
3365 param[count++] = LLVMGetUndef(ctx->i32);
3366
3367 if (count > 1)
3368 args->addr = ac_build_gather_values(&ctx->ac, param, count);
3369 else
3370 args->addr = param[0];
3371
3372 args->resource = res_ptr;
3373 args->sampler = samp_ptr;
3374
3375 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3376 args->addr = param[0];
3377 return;
3378 }
3379
3380 args->dmask = dmask;
3381 args->unorm = is_rect;
3382 args->da = da;
3383 }
3384
3385 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3386 *
3387 * SI-CI:
3388 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3389 * filtering manually. The driver sets img7 to a mask clearing
3390 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3391 * s_and_b32 samp0, samp0, img7
3392 *
3393 * VI:
3394 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3395 */
3396 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3397 LLVMValueRef res, LLVMValueRef samp)
3398 {
3399 LLVMBuilderRef builder = ctx->builder;
3400 LLVMValueRef img7, samp0;
3401
3402 if (ctx->options->chip_class >= VI)
3403 return samp;
3404
3405 img7 = LLVMBuildExtractElement(builder, res,
3406 LLVMConstInt(ctx->i32, 7, 0), "");
3407 samp0 = LLVMBuildExtractElement(builder, samp,
3408 LLVMConstInt(ctx->i32, 0, 0), "");
3409 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3410 return LLVMBuildInsertElement(builder, samp, samp0,
3411 LLVMConstInt(ctx->i32, 0, 0), "");
3412 }
3413
3414 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3415 nir_tex_instr *instr,
3416 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3417 LLVMValueRef *fmask_ptr)
3418 {
3419 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3420 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3421 else
3422 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3423 if (samp_ptr) {
3424 if (instr->sampler)
3425 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3426 else
3427 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3428 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3429 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3430 }
3431 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3432 instr->op == nir_texop_samples_identical))
3433 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3434 }
3435
3436 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3437 LLVMValueRef coord)
3438 {
3439 coord = to_float(ctx, coord);
3440 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3441 coord = to_integer(ctx, coord);
3442 return coord;
3443 }
3444
3445 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3446 {
3447 LLVMValueRef result = NULL;
3448 struct ac_image_args args = { 0 };
3449 unsigned dmask = 0xf;
3450 LLVMValueRef address[16];
3451 LLVMValueRef coords[5];
3452 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3453 LLVMValueRef bias = NULL, offsets = NULL;
3454 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3455 LLVMValueRef ddx = NULL, ddy = NULL;
3456 LLVMValueRef derivs[6];
3457 unsigned chan, count = 0;
3458 unsigned const_src = 0, num_deriv_comp = 0;
3459
3460 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3461
3462 for (unsigned i = 0; i < instr->num_srcs; i++) {
3463 switch (instr->src[i].src_type) {
3464 case nir_tex_src_coord:
3465 coord = get_src(ctx, instr->src[i].src);
3466 break;
3467 case nir_tex_src_projector:
3468 break;
3469 case nir_tex_src_comparator:
3470 comparator = get_src(ctx, instr->src[i].src);
3471 break;
3472 case nir_tex_src_offset:
3473 offsets = get_src(ctx, instr->src[i].src);
3474 const_src = i;
3475 break;
3476 case nir_tex_src_bias:
3477 bias = get_src(ctx, instr->src[i].src);
3478 break;
3479 case nir_tex_src_lod:
3480 lod = get_src(ctx, instr->src[i].src);
3481 break;
3482 case nir_tex_src_ms_index:
3483 sample_index = get_src(ctx, instr->src[i].src);
3484 break;
3485 case nir_tex_src_ms_mcs:
3486 break;
3487 case nir_tex_src_ddx:
3488 ddx = get_src(ctx, instr->src[i].src);
3489 num_deriv_comp = instr->src[i].src.ssa->num_components;
3490 break;
3491 case nir_tex_src_ddy:
3492 ddy = get_src(ctx, instr->src[i].src);
3493 break;
3494 case nir_tex_src_texture_offset:
3495 case nir_tex_src_sampler_offset:
3496 case nir_tex_src_plane:
3497 default:
3498 break;
3499 }
3500 }
3501
3502 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3503 result = get_buffer_size(ctx, res_ptr, true);
3504 goto write_result;
3505 }
3506
3507 if (instr->op == nir_texop_texture_samples) {
3508 LLVMValueRef res, samples, is_msaa;
3509 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3510 samples = LLVMBuildExtractElement(ctx->builder, res,
3511 LLVMConstInt(ctx->i32, 3, false), "");
3512 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3513 LLVMConstInt(ctx->i32, 28, false), "");
3514 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3515 LLVMConstInt(ctx->i32, 0xe, false), "");
3516 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3517 LLVMConstInt(ctx->i32, 0xe, false), "");
3518
3519 samples = LLVMBuildLShr(ctx->builder, samples,
3520 LLVMConstInt(ctx->i32, 16, false), "");
3521 samples = LLVMBuildAnd(ctx->builder, samples,
3522 LLVMConstInt(ctx->i32, 0xf, false), "");
3523 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3524 samples, "");
3525 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3526 ctx->i32one, "");
3527 result = samples;
3528 goto write_result;
3529 }
3530
3531 if (coord)
3532 for (chan = 0; chan < instr->coord_components; chan++)
3533 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3534
3535 if (offsets && instr->op != nir_texop_txf) {
3536 LLVMValueRef offset[3], pack;
3537 for (chan = 0; chan < 3; ++chan)
3538 offset[chan] = ctx->i32zero;
3539
3540 args.offset = true;
3541 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3542 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3543 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3544 LLVMConstInt(ctx->i32, 0x3f, false), "");
3545 if (chan)
3546 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3547 LLVMConstInt(ctx->i32, chan * 8, false), "");
3548 }
3549 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3550 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3551 address[count++] = pack;
3552
3553 }
3554 /* pack LOD bias value */
3555 if (instr->op == nir_texop_txb && bias) {
3556 address[count++] = bias;
3557 }
3558
3559 /* Pack depth comparison value */
3560 if (instr->is_shadow && comparator) {
3561 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3562 }
3563
3564 /* pack derivatives */
3565 if (ddx || ddy) {
3566 switch (instr->sampler_dim) {
3567 case GLSL_SAMPLER_DIM_3D:
3568 case GLSL_SAMPLER_DIM_CUBE:
3569 num_deriv_comp = 3;
3570 break;
3571 case GLSL_SAMPLER_DIM_2D:
3572 default:
3573 num_deriv_comp = 2;
3574 break;
3575 case GLSL_SAMPLER_DIM_1D:
3576 num_deriv_comp = 1;
3577 break;
3578 }
3579
3580 for (unsigned i = 0; i < num_deriv_comp; i++) {
3581 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3582 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3583 }
3584 }
3585
3586 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3587 for (chan = 0; chan < instr->coord_components; chan++)
3588 coords[chan] = to_float(ctx, coords[chan]);
3589 if (instr->coord_components == 3)
3590 coords[3] = LLVMGetUndef(ctx->f32);
3591 ac_prepare_cube_coords(&ctx->ac,
3592 instr->op == nir_texop_txd, instr->is_array,
3593 coords, derivs);
3594 if (num_deriv_comp)
3595 num_deriv_comp--;
3596 }
3597
3598 if (ddx || ddy) {
3599 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3600 address[count++] = derivs[i];
3601 }
3602
3603 /* Pack texture coordinates */
3604 if (coord) {
3605 address[count++] = coords[0];
3606 if (instr->coord_components > 1) {
3607 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3608 coords[1] = apply_round_slice(ctx, coords[1]);
3609 }
3610 address[count++] = coords[1];
3611 }
3612 if (instr->coord_components > 2) {
3613 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3614 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3615 coords[2] = apply_round_slice(ctx, coords[2]);
3616 }
3617 address[count++] = coords[2];
3618 }
3619 }
3620
3621 /* Pack LOD */
3622 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3623 address[count++] = lod;
3624 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3625 address[count++] = sample_index;
3626 } else if(instr->op == nir_texop_txs) {
3627 count = 0;
3628 if (lod)
3629 address[count++] = lod;
3630 else
3631 address[count++] = ctx->i32zero;
3632 }
3633
3634 for (chan = 0; chan < count; chan++) {
3635 address[chan] = LLVMBuildBitCast(ctx->builder,
3636 address[chan], ctx->i32, "");
3637 }
3638
3639 if (instr->op == nir_texop_samples_identical) {
3640 LLVMValueRef txf_address[4];
3641 struct ac_image_args txf_args = { 0 };
3642 unsigned txf_count = count;
3643 memcpy(txf_address, address, sizeof(txf_address));
3644
3645 if (!instr->is_array)
3646 txf_address[2] = ctx->i32zero;
3647 txf_address[3] = ctx->i32zero;
3648
3649 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
3650 fmask_ptr, NULL,
3651 txf_address, txf_count, 0xf);
3652
3653 result = build_tex_intrinsic(ctx, instr, &txf_args);
3654
3655 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3656 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3657 goto write_result;
3658 }
3659
3660 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3661 instr->op != nir_texop_txs) {
3662 unsigned sample_chan = instr->is_array ? 3 : 2;
3663 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
3664 address[0],
3665 address[1],
3666 instr->is_array ? address[2] : NULL,
3667 address[sample_chan],
3668 fmask_ptr);
3669 }
3670
3671 if (offsets && instr->op == nir_texop_txf) {
3672 nir_const_value *const_offset =
3673 nir_src_as_const_value(instr->src[const_src].src);
3674 int num_offsets = instr->src[const_src].src.ssa->num_components;
3675 assert(const_offset);
3676 num_offsets = MIN2(num_offsets, instr->coord_components);
3677 if (num_offsets > 2)
3678 address[2] = LLVMBuildAdd(ctx->builder,
3679 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3680 if (num_offsets > 1)
3681 address[1] = LLVMBuildAdd(ctx->builder,
3682 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3683 address[0] = LLVMBuildAdd(ctx->builder,
3684 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3685
3686 }
3687
3688 /* TODO TG4 support */
3689 if (instr->op == nir_texop_tg4) {
3690 if (instr->is_shadow)
3691 dmask = 1;
3692 else
3693 dmask = 1 << instr->component;
3694 }
3695 set_tex_fetch_args(ctx, &args, instr, instr->op,
3696 res_ptr, samp_ptr, address, count, dmask);
3697
3698 result = build_tex_intrinsic(ctx, instr, &args);
3699
3700 if (instr->op == nir_texop_query_levels)
3701 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3702 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3703 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3704 else if (instr->op == nir_texop_txs &&
3705 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3706 instr->is_array) {
3707 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3708 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3709 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3710 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3711 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3712 } else if (instr->dest.ssa.num_components != 4)
3713 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3714
3715 write_result:
3716 if (result) {
3717 assert(instr->dest.is_ssa);
3718 result = to_integer(ctx, result);
3719 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3720 }
3721 }
3722
3723
3724 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3725 {
3726 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3727 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3728
3729 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3730 _mesa_hash_table_insert(ctx->phis, instr, result);
3731 }
3732
3733 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3734 nir_phi_instr *instr,
3735 LLVMValueRef llvm_phi)
3736 {
3737 nir_foreach_phi_src(src, instr) {
3738 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3739 LLVMValueRef llvm_src = get_src(ctx, src->src);
3740
3741 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3742 }
3743 }
3744
3745 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3746 {
3747 struct hash_entry *entry;
3748 hash_table_foreach(ctx->phis, entry) {
3749 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3750 (LLVMValueRef)entry->data);
3751 }
3752 }
3753
3754
3755 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3756 nir_ssa_undef_instr *instr)
3757 {
3758 unsigned num_components = instr->def.num_components;
3759 LLVMValueRef undef;
3760
3761 if (num_components == 1)
3762 undef = LLVMGetUndef(ctx->i32);
3763 else {
3764 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3765 }
3766 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3767 }
3768
3769 static void visit_jump(struct nir_to_llvm_context *ctx,
3770 nir_jump_instr *instr)
3771 {
3772 switch (instr->type) {
3773 case nir_jump_break:
3774 LLVMBuildBr(ctx->builder, ctx->break_block);
3775 LLVMClearInsertionPosition(ctx->builder);
3776 break;
3777 case nir_jump_continue:
3778 LLVMBuildBr(ctx->builder, ctx->continue_block);
3779 LLVMClearInsertionPosition(ctx->builder);
3780 break;
3781 default:
3782 fprintf(stderr, "Unknown NIR jump instr: ");
3783 nir_print_instr(&instr->instr, stderr);
3784 fprintf(stderr, "\n");
3785 abort();
3786 }
3787 }
3788
3789 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3790 struct exec_list *list);
3791
3792 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3793 {
3794 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3795 nir_foreach_instr(instr, block)
3796 {
3797 switch (instr->type) {
3798 case nir_instr_type_alu:
3799 visit_alu(ctx, nir_instr_as_alu(instr));
3800 break;
3801 case nir_instr_type_load_const:
3802 visit_load_const(ctx, nir_instr_as_load_const(instr));
3803 break;
3804 case nir_instr_type_intrinsic:
3805 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3806 break;
3807 case nir_instr_type_tex:
3808 visit_tex(ctx, nir_instr_as_tex(instr));
3809 break;
3810 case nir_instr_type_phi:
3811 visit_phi(ctx, nir_instr_as_phi(instr));
3812 break;
3813 case nir_instr_type_ssa_undef:
3814 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3815 break;
3816 case nir_instr_type_jump:
3817 visit_jump(ctx, nir_instr_as_jump(instr));
3818 break;
3819 default:
3820 fprintf(stderr, "Unknown NIR instr type: ");
3821 nir_print_instr(instr, stderr);
3822 fprintf(stderr, "\n");
3823 abort();
3824 }
3825 }
3826
3827 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3828 }
3829
3830 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3831 {
3832 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3833
3834 LLVMBasicBlockRef merge_block =
3835 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3836 LLVMBasicBlockRef if_block =
3837 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3838 LLVMBasicBlockRef else_block = merge_block;
3839 if (!exec_list_is_empty(&if_stmt->else_list))
3840 else_block = LLVMAppendBasicBlockInContext(
3841 ctx->context, ctx->main_function, "");
3842
3843 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3844 LLVMConstInt(ctx->i32, 0, false), "");
3845 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3846
3847 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3848 visit_cf_list(ctx, &if_stmt->then_list);
3849 if (LLVMGetInsertBlock(ctx->builder))
3850 LLVMBuildBr(ctx->builder, merge_block);
3851
3852 if (!exec_list_is_empty(&if_stmt->else_list)) {
3853 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3854 visit_cf_list(ctx, &if_stmt->else_list);
3855 if (LLVMGetInsertBlock(ctx->builder))
3856 LLVMBuildBr(ctx->builder, merge_block);
3857 }
3858
3859 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3860 }
3861
3862 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3863 {
3864 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3865 LLVMBasicBlockRef break_parent = ctx->break_block;
3866
3867 ctx->continue_block =
3868 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3869 ctx->break_block =
3870 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3871
3872 LLVMBuildBr(ctx->builder, ctx->continue_block);
3873 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3874 visit_cf_list(ctx, &loop->body);
3875
3876 if (LLVMGetInsertBlock(ctx->builder))
3877 LLVMBuildBr(ctx->builder, ctx->continue_block);
3878 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3879
3880 ctx->continue_block = continue_parent;
3881 ctx->break_block = break_parent;
3882 }
3883
3884 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3885 struct exec_list *list)
3886 {
3887 foreach_list_typed(nir_cf_node, node, node, list)
3888 {
3889 switch (node->type) {
3890 case nir_cf_node_block:
3891 visit_block(ctx, nir_cf_node_as_block(node));
3892 break;
3893
3894 case nir_cf_node_if:
3895 visit_if(ctx, nir_cf_node_as_if(node));
3896 break;
3897
3898 case nir_cf_node_loop:
3899 visit_loop(ctx, nir_cf_node_as_loop(node));
3900 break;
3901
3902 default:
3903 assert(0);
3904 }
3905 }
3906 }
3907
3908 static void
3909 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3910 struct nir_variable *variable)
3911 {
3912 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3913 LLVMValueRef t_offset;
3914 LLVMValueRef t_list;
3915 LLVMValueRef args[3];
3916 LLVMValueRef input;
3917 LLVMValueRef buffer_index;
3918 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3919 int idx = variable->data.location;
3920 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3921
3922 variable->data.driver_location = idx * 4;
3923
3924 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3925 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3926 ctx->start_instance, "");
3927 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3928 ctx->shader_info->vs.vgpr_comp_cnt);
3929 } else
3930 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3931 ctx->base_vertex, "");
3932
3933 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3934 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3935
3936 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
3937 args[0] = t_list;
3938 args[1] = LLVMConstInt(ctx->i32, 0, false);
3939 args[2] = buffer_index;
3940 input = ac_build_intrinsic(&ctx->ac,
3941 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3942 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND |
3943 AC_FUNC_ATTR_LEGACY);
3944
3945 for (unsigned chan = 0; chan < 4; chan++) {
3946 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3947 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3948 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3949 input, llvm_chan, ""));
3950 }
3951 }
3952 }
3953
3954 static void
3955 handle_gs_input_decl(struct nir_to_llvm_context *ctx,
3956 struct nir_variable *variable)
3957 {
3958 int idx = variable->data.location;
3959
3960 if (idx == VARYING_SLOT_CLIP_DIST0 ||
3961 idx == VARYING_SLOT_CULL_DIST0) {
3962 int length = glsl_get_length(glsl_get_array_element(variable->type));
3963 if (idx == VARYING_SLOT_CLIP_DIST0)
3964 ctx->num_input_clips = length;
3965 else
3966 ctx->num_input_culls = length;
3967 }
3968 }
3969
3970 static void interp_fs_input(struct nir_to_llvm_context *ctx,
3971 unsigned attr,
3972 LLVMValueRef interp_param,
3973 LLVMValueRef prim_mask,
3974 LLVMValueRef result[4])
3975 {
3976 LLVMValueRef attr_number;
3977 unsigned chan;
3978 LLVMValueRef i, j;
3979 bool interp = interp_param != NULL;
3980
3981 attr_number = LLVMConstInt(ctx->i32, attr, false);
3982
3983 /* fs.constant returns the param from the middle vertex, so it's not
3984 * really useful for flat shading. It's meant to be used for custom
3985 * interpolation (but the intrinsic can't fetch from the other two
3986 * vertices).
3987 *
3988 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
3989 * to do the right thing. The only reason we use fs.constant is that
3990 * fs.interp cannot be used on integers, because they can be equal
3991 * to NaN.
3992 */
3993 if (interp) {
3994 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
3995 LLVMVectorType(ctx->f32, 2), "");
3996
3997 i = LLVMBuildExtractElement(ctx->builder, interp_param,
3998 ctx->i32zero, "");
3999 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4000 ctx->i32one, "");
4001 }
4002
4003 for (chan = 0; chan < 4; chan++) {
4004 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4005
4006 if (interp) {
4007 result[chan] = ac_build_fs_interp(&ctx->ac,
4008 llvm_chan,
4009 attr_number,
4010 prim_mask, i, j);
4011 } else {
4012 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4013 LLVMConstInt(ctx->i32, 2, false),
4014 llvm_chan,
4015 attr_number,
4016 prim_mask);
4017 }
4018 }
4019 }
4020
4021 static void
4022 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4023 struct nir_variable *variable)
4024 {
4025 int idx = variable->data.location;
4026 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4027 LLVMValueRef interp;
4028
4029 variable->data.driver_location = idx * 4;
4030 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4031
4032 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4033 unsigned interp_type;
4034 if (variable->data.sample) {
4035 interp_type = INTERP_SAMPLE;
4036 ctx->shader_info->fs.force_persample = true;
4037 } else if (variable->data.centroid)
4038 interp_type = INTERP_CENTROID;
4039 else
4040 interp_type = INTERP_CENTER;
4041
4042 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4043 } else
4044 interp = NULL;
4045
4046 for (unsigned i = 0; i < attrib_count; ++i)
4047 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4048
4049 }
4050
4051 static void
4052 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4053 struct nir_variable *variable)
4054 {
4055 switch (ctx->stage) {
4056 case MESA_SHADER_VERTEX:
4057 handle_vs_input_decl(ctx, variable);
4058 break;
4059 case MESA_SHADER_FRAGMENT:
4060 handle_fs_input_decl(ctx, variable);
4061 break;
4062 case MESA_SHADER_GEOMETRY:
4063 handle_gs_input_decl(ctx, variable);
4064 break;
4065 default:
4066 break;
4067 }
4068
4069 }
4070
4071 static void
4072 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4073 struct nir_shader *nir)
4074 {
4075 unsigned index = 0;
4076 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4077 LLVMValueRef interp_param;
4078 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4079
4080 if (!(ctx->input_mask & (1ull << i)))
4081 continue;
4082
4083 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4084 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4085 interp_param = *inputs;
4086 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4087 inputs);
4088
4089 if (!interp_param)
4090 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4091 ++index;
4092 } else if (i == VARYING_SLOT_POS) {
4093 for(int i = 0; i < 3; ++i)
4094 inputs[i] = ctx->frag_pos[i];
4095
4096 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4097 }
4098 }
4099 ctx->shader_info->fs.num_interp = index;
4100 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4101 ctx->shader_info->fs.has_pcoord = true;
4102 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4103 ctx->shader_info->fs.prim_id_input = true;
4104 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4105 ctx->shader_info->fs.layer_input = true;
4106 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4107 }
4108
4109 static LLVMValueRef
4110 ac_build_alloca(struct nir_to_llvm_context *ctx,
4111 LLVMTypeRef type,
4112 const char *name)
4113 {
4114 LLVMBuilderRef builder = ctx->builder;
4115 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4116 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4117 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4118 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4119 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4120 LLVMValueRef res;
4121
4122 if (first_instr) {
4123 LLVMPositionBuilderBefore(first_builder, first_instr);
4124 } else {
4125 LLVMPositionBuilderAtEnd(first_builder, first_block);
4126 }
4127
4128 res = LLVMBuildAlloca(first_builder, type, name);
4129 LLVMBuildStore(builder, LLVMConstNull(type), res);
4130
4131 LLVMDisposeBuilder(first_builder);
4132
4133 return res;
4134 }
4135
4136 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4137 LLVMTypeRef type,
4138 const char *name)
4139 {
4140 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4141 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4142 return ptr;
4143 }
4144
4145 static void
4146 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4147 struct nir_variable *variable)
4148 {
4149 int idx = variable->data.location + variable->data.index;
4150 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4151
4152 variable->data.driver_location = idx * 4;
4153
4154 if (ctx->stage == MESA_SHADER_VERTEX ||
4155 ctx->stage == MESA_SHADER_GEOMETRY) {
4156 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4157 idx == VARYING_SLOT_CULL_DIST0) {
4158 int length = glsl_get_length(variable->type);
4159 if (idx == VARYING_SLOT_CLIP_DIST0) {
4160 if (ctx->stage == MESA_SHADER_VERTEX)
4161 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4162 ctx->num_output_clips = length;
4163 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4164 if (ctx->stage == MESA_SHADER_VERTEX)
4165 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4166 ctx->num_output_culls = length;
4167 }
4168 if (length > 4)
4169 attrib_count = 2;
4170 else
4171 attrib_count = 1;
4172 }
4173 }
4174
4175 for (unsigned i = 0; i < attrib_count; ++i) {
4176 for (unsigned chan = 0; chan < 4; chan++) {
4177 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4178 si_build_alloca_undef(ctx, ctx->f32, "");
4179 }
4180 }
4181 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4182 }
4183
4184 static void
4185 setup_locals(struct nir_to_llvm_context *ctx,
4186 struct nir_function *func)
4187 {
4188 int i, j;
4189 ctx->num_locals = 0;
4190 nir_foreach_variable(variable, &func->impl->locals) {
4191 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4192 variable->data.driver_location = ctx->num_locals * 4;
4193 ctx->num_locals += attrib_count;
4194 }
4195 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4196 if (!ctx->locals)
4197 return;
4198
4199 for (i = 0; i < ctx->num_locals; i++) {
4200 for (j = 0; j < 4; j++) {
4201 ctx->locals[i * 4 + j] =
4202 si_build_alloca_undef(ctx, ctx->f32, "temp");
4203 }
4204 }
4205 }
4206
4207 static LLVMValueRef
4208 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4209 {
4210 v = to_float(ctx, v);
4211 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4212 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4213 }
4214
4215
4216 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4217 LLVMValueRef src0, LLVMValueRef src1)
4218 {
4219 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4220 LLVMValueRef comp[2];
4221
4222 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4223 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4224 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4225 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4226 }
4227
4228 /* Initialize arguments for the shader export intrinsic */
4229 static void
4230 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4231 LLVMValueRef *values,
4232 unsigned target,
4233 struct ac_export_args *args)
4234 {
4235 /* Default is 0xf. Adjusted below depending on the format. */
4236 args->enabled_channels = 0xf;
4237
4238 /* Specify whether the EXEC mask represents the valid mask */
4239 args->valid_mask = 0;
4240
4241 /* Specify whether this is the last export */
4242 args->done = 0;
4243
4244 /* Specify the target we are exporting */
4245 args->target = target;
4246
4247 args->compr = false;
4248 args->out[0] = LLVMGetUndef(ctx->f32);
4249 args->out[1] = LLVMGetUndef(ctx->f32);
4250 args->out[2] = LLVMGetUndef(ctx->f32);
4251 args->out[3] = LLVMGetUndef(ctx->f32);
4252
4253 if (!values)
4254 return;
4255
4256 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4257 LLVMValueRef val[4];
4258 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4259 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4260 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4261
4262 switch(col_format) {
4263 case V_028714_SPI_SHADER_ZERO:
4264 args->enabled_channels = 0; /* writemask */
4265 args->target = V_008DFC_SQ_EXP_NULL;
4266 break;
4267
4268 case V_028714_SPI_SHADER_32_R:
4269 args->enabled_channels = 1;
4270 args->out[0] = values[0];
4271 break;
4272
4273 case V_028714_SPI_SHADER_32_GR:
4274 args->enabled_channels = 0x3;
4275 args->out[0] = values[0];
4276 args->out[1] = values[1];
4277 break;
4278
4279 case V_028714_SPI_SHADER_32_AR:
4280 args->enabled_channels = 0x9;
4281 args->out[0] = values[0];
4282 args->out[3] = values[3];
4283 break;
4284
4285 case V_028714_SPI_SHADER_FP16_ABGR:
4286 args->compr = 1;
4287
4288 for (unsigned chan = 0; chan < 2; chan++) {
4289 LLVMValueRef pack_args[2] = {
4290 values[2 * chan],
4291 values[2 * chan + 1]
4292 };
4293 LLVMValueRef packed;
4294
4295 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
4296 args->out[chan] = packed;
4297 }
4298 break;
4299
4300 case V_028714_SPI_SHADER_UNORM16_ABGR:
4301 for (unsigned chan = 0; chan < 4; chan++) {
4302 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
4303 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4304 LLVMConstReal(ctx->f32, 65535), "");
4305 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4306 LLVMConstReal(ctx->f32, 0.5), "");
4307 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4308 ctx->i32, "");
4309 }
4310
4311 args->compr = 1;
4312 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4313 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4314 break;
4315
4316 case V_028714_SPI_SHADER_SNORM16_ABGR:
4317 for (unsigned chan = 0; chan < 4; chan++) {
4318 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4319 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4320 LLVMConstReal(ctx->f32, 32767), "");
4321
4322 /* If positive, add 0.5, else add -0.5. */
4323 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4324 LLVMBuildSelect(ctx->builder,
4325 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4326 val[chan], ctx->f32zero, ""),
4327 LLVMConstReal(ctx->f32, 0.5),
4328 LLVMConstReal(ctx->f32, -0.5), ""), "");
4329 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4330 }
4331
4332 args->compr = 1;
4333 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4334 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4335 break;
4336
4337 case V_028714_SPI_SHADER_UINT16_ABGR: {
4338 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4339
4340 for (unsigned chan = 0; chan < 4; chan++) {
4341 val[chan] = to_integer(ctx, values[chan]);
4342 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4343 }
4344
4345 args->compr = 1;
4346 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4347 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4348 break;
4349 }
4350
4351 case V_028714_SPI_SHADER_SINT16_ABGR: {
4352 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4353 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4354
4355 /* Clamp. */
4356 for (unsigned chan = 0; chan < 4; chan++) {
4357 val[chan] = to_integer(ctx, values[chan]);
4358 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4359 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4360 }
4361
4362 args->compr = 1;
4363 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4364 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4365 break;
4366 }
4367
4368 default:
4369 case V_028714_SPI_SHADER_32_ABGR:
4370 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
4371 break;
4372 }
4373 } else
4374 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
4375
4376 for (unsigned i = 0; i < 4; ++i)
4377 args->out[i] = to_float(ctx, args->out[i]);
4378 }
4379
4380 static void
4381 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4382 {
4383 uint32_t param_count = 0;
4384 unsigned target;
4385 unsigned pos_idx, num_pos_exports = 0;
4386 struct ac_export_args args, pos_args[4] = {};
4387 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4388 int i;
4389 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4390 (1ull << VARYING_SLOT_CLIP_DIST1) |
4391 (1ull << VARYING_SLOT_CULL_DIST0) |
4392 (1ull << VARYING_SLOT_CULL_DIST1));
4393
4394 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4395 ctx->shader_info->vs.layer_output = 0xffffffff;
4396 if (clip_mask) {
4397 LLVMValueRef slots[8];
4398 unsigned j;
4399
4400 if (ctx->shader_info->vs.cull_dist_mask)
4401 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_output_clips;
4402
4403 i = VARYING_SLOT_CLIP_DIST0;
4404 for (j = 0; j < ctx->num_output_clips; j++)
4405 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4406 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4407 i = VARYING_SLOT_CULL_DIST0;
4408 for (j = 0; j < ctx->num_output_culls; j++)
4409 slots[ctx->num_output_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4410 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4411
4412 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
4413 slots[i] = LLVMGetUndef(ctx->f32);
4414
4415 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
4416 target = V_008DFC_SQ_EXP_POS + 3;
4417 si_llvm_init_export_args(ctx, &slots[4], target, &args);
4418 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4419 &args, sizeof(args));
4420 }
4421
4422 target = V_008DFC_SQ_EXP_POS + 2;
4423 si_llvm_init_export_args(ctx, &slots[0], target, &args);
4424 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4425 &args, sizeof(args));
4426
4427 }
4428
4429 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4430 LLVMValueRef values[4];
4431 if (!(ctx->output_mask & (1ull << i)))
4432 continue;
4433
4434 for (unsigned j = 0; j < 4; j++)
4435 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4436 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4437
4438 if (i == VARYING_SLOT_POS) {
4439 target = V_008DFC_SQ_EXP_POS;
4440 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4441 i == VARYING_SLOT_CLIP_DIST1 ||
4442 i == VARYING_SLOT_CULL_DIST0 ||
4443 i == VARYING_SLOT_CULL_DIST1) {
4444 continue;
4445 } else if (i == VARYING_SLOT_PSIZ) {
4446 ctx->shader_info->vs.writes_pointsize = true;
4447 psize_value = values[0];
4448 continue;
4449 } else if (i == VARYING_SLOT_LAYER) {
4450 ctx->shader_info->vs.writes_layer = true;
4451 layer_value = values[0];
4452 ctx->shader_info->vs.layer_output = param_count;
4453 target = V_008DFC_SQ_EXP_PARAM + param_count;
4454 param_count++;
4455 } else if (i == VARYING_SLOT_VIEWPORT) {
4456 ctx->shader_info->vs.writes_viewport_index = true;
4457 viewport_index_value = values[0];
4458 continue;
4459 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4460 ctx->shader_info->vs.prim_id_output = param_count;
4461 target = V_008DFC_SQ_EXP_PARAM + param_count;
4462 param_count++;
4463 } else if (i >= VARYING_SLOT_VAR0) {
4464 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4465 target = V_008DFC_SQ_EXP_PARAM + param_count;
4466 param_count++;
4467 }
4468
4469 si_llvm_init_export_args(ctx, values, target, &args);
4470
4471 if (target >= V_008DFC_SQ_EXP_POS &&
4472 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4473 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4474 &args, sizeof(args));
4475 } else {
4476 ac_build_export(&ctx->ac, &args);
4477 }
4478 }
4479
4480 /* We need to add the position output manually if it's missing. */
4481 if (!pos_args[0].out[0]) {
4482 pos_args[0].enabled_channels = 0xf;
4483 pos_args[0].valid_mask = 0;
4484 pos_args[0].done = 0;
4485 pos_args[0].target = V_008DFC_SQ_EXP_POS;
4486 pos_args[0].compr = 0;
4487 pos_args[0].out[0] = ctx->f32zero; /* X */
4488 pos_args[0].out[1] = ctx->f32zero; /* Y */
4489 pos_args[0].out[2] = ctx->f32zero; /* Z */
4490 pos_args[0].out[3] = ctx->f32one; /* W */
4491 }
4492
4493 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4494 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4495 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4496 if (mask) {
4497 pos_args[1].enabled_channels = mask;
4498 pos_args[1].valid_mask = 0;
4499 pos_args[1].done = 0;
4500 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
4501 pos_args[1].compr = 0;
4502 pos_args[1].out[0] = ctx->f32zero; /* X */
4503 pos_args[1].out[1] = ctx->f32zero; /* Y */
4504 pos_args[1].out[2] = ctx->f32zero; /* Z */
4505 pos_args[1].out[3] = ctx->f32zero; /* W */
4506
4507 if (ctx->shader_info->vs.writes_pointsize == true)
4508 pos_args[1].out[0] = psize_value;
4509 if (ctx->shader_info->vs.writes_layer == true)
4510 pos_args[1].out[2] = layer_value;
4511 if (ctx->shader_info->vs.writes_viewport_index == true)
4512 pos_args[1].out[3] = viewport_index_value;
4513 }
4514 for (i = 0; i < 4; i++) {
4515 if (pos_args[i].out[0])
4516 num_pos_exports++;
4517 }
4518
4519 pos_idx = 0;
4520 for (i = 0; i < 4; i++) {
4521 if (!pos_args[i].out[0])
4522 continue;
4523
4524 /* Specify the target we are exporting */
4525 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
4526 if (pos_idx == num_pos_exports)
4527 pos_args[i].done = 1;
4528 ac_build_export(&ctx->ac, &pos_args[i]);
4529 }
4530
4531 ctx->shader_info->vs.pos_exports = num_pos_exports;
4532 ctx->shader_info->vs.param_exports = param_count;
4533 }
4534
4535 static void
4536 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4537 {
4538 int j;
4539 uint64_t max_output_written = 0;
4540 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4541 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4542 int param_index;
4543 int length = 4;
4544 int start = 0;
4545 if (!(ctx->output_mask & (1ull << i)))
4546 continue;
4547
4548 if (i == VARYING_SLOT_CLIP_DIST0) {
4549 length = ctx->num_output_clips;
4550 } else if (i == VARYING_SLOT_CULL_DIST0) {
4551 start = ctx->num_output_clips;
4552 length = ctx->num_output_culls;
4553 }
4554 param_index = shader_io_get_unique_index(i);
4555
4556 if (param_index > max_output_written)
4557 max_output_written = param_index;
4558
4559 for (j = 0; j < length; j++) {
4560 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4561 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4562
4563 ac_build_buffer_store_dword(&ctx->ac,
4564 ctx->esgs_ring,
4565 out_val, 1,
4566 NULL, ctx->es2gs_offset,
4567 (4 * param_index + j + start) * 4,
4568 1, 1, true, true);
4569 }
4570 }
4571 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4572 }
4573
4574 static void
4575 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4576 LLVMValueRef *color, unsigned param, bool is_last)
4577 {
4578
4579 struct ac_export_args args;
4580
4581 /* Export */
4582 si_llvm_init_export_args(ctx, color, param,
4583 &args);
4584
4585 if (is_last) {
4586 args.valid_mask = 1; /* whether the EXEC mask is valid */
4587 args.done = 1; /* DONE bit */
4588 } else if (!args.enabled_channels)
4589 return; /* unnecessary NULL export */
4590
4591 ac_build_export(&ctx->ac, &args);
4592 }
4593
4594 static void
4595 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4596 LLVMValueRef depth, LLVMValueRef stencil,
4597 LLVMValueRef samplemask)
4598 {
4599 struct ac_export_args args;
4600
4601 args.enabled_channels = 0;
4602 args.valid_mask = 1;
4603 args.done = 1;
4604 args.target = V_008DFC_SQ_EXP_MRTZ;
4605 args.compr = false;
4606
4607 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
4608 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4609 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4610 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4611
4612 if (depth) {
4613 args.out[0] = depth;
4614 args.enabled_channels |= 0x1;
4615 }
4616
4617 if (stencil) {
4618 args.out[1] = stencil;
4619 args.enabled_channels |= 0x2;
4620 }
4621
4622 if (samplemask) {
4623 args.out[2] = samplemask;
4624 args.enabled_channels |= 0x4;
4625 }
4626
4627 /* SI (except OLAND) has a bug that it only looks
4628 * at the X writemask component. */
4629 if (ctx->options->chip_class == SI &&
4630 ctx->options->family != CHIP_OLAND)
4631 args.enabled_channels |= 0x1;
4632
4633 ac_build_export(&ctx->ac, &args);
4634 }
4635
4636 static void
4637 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4638 {
4639 unsigned index = 0;
4640 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4641
4642 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4643 LLVMValueRef values[4];
4644
4645 if (!(ctx->output_mask & (1ull << i)))
4646 continue;
4647
4648 if (i == FRAG_RESULT_DEPTH) {
4649 ctx->shader_info->fs.writes_z = true;
4650 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4651 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4652 } else if (i == FRAG_RESULT_STENCIL) {
4653 ctx->shader_info->fs.writes_stencil = true;
4654 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4655 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4656 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
4657 ctx->shader_info->fs.writes_sample_mask = true;
4658 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
4659 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4660 } else {
4661 bool last = false;
4662 for (unsigned j = 0; j < 4; j++)
4663 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4664 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4665
4666 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
4667 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4668
4669 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4670 index++;
4671 }
4672 }
4673
4674 if (depth || stencil || samplemask)
4675 si_export_mrt_z(ctx, depth, stencil, samplemask);
4676 else if (!index)
4677 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4678
4679 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4680 }
4681
4682 static void
4683 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4684 {
4685 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4686 }
4687
4688 static void
4689 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4690 {
4691 switch (ctx->stage) {
4692 case MESA_SHADER_VERTEX:
4693 if (ctx->options->key.vs.as_es)
4694 handle_es_outputs_post(ctx);
4695 else
4696 handle_vs_outputs_post(ctx);
4697 break;
4698 case MESA_SHADER_FRAGMENT:
4699 handle_fs_outputs_post(ctx);
4700 break;
4701 case MESA_SHADER_GEOMETRY:
4702 emit_gs_epilogue(ctx);
4703 break;
4704 default:
4705 break;
4706 }
4707 }
4708
4709 static void
4710 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4711 struct nir_variable *variable, uint32_t *offset, int idx)
4712 {
4713 unsigned size = glsl_count_attribute_slots(variable->type, false);
4714 variable->data.driver_location = *offset;
4715 *offset += size;
4716 }
4717
4718 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4719 {
4720 LLVMPassManagerRef passmgr;
4721 /* Create the pass manager */
4722 passmgr = LLVMCreateFunctionPassManagerForModule(
4723 ctx->module);
4724
4725 /* This pass should eliminate all the load and store instructions */
4726 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4727
4728 /* Add some optimization passes */
4729 LLVMAddScalarReplAggregatesPass(passmgr);
4730 LLVMAddLICMPass(passmgr);
4731 LLVMAddAggressiveDCEPass(passmgr);
4732 LLVMAddCFGSimplificationPass(passmgr);
4733 LLVMAddInstructionCombiningPass(passmgr);
4734
4735 /* Run the pass */
4736 LLVMInitializeFunctionPassManager(passmgr);
4737 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4738 LLVMFinalizeFunctionPassManager(passmgr);
4739
4740 LLVMDisposeBuilder(ctx->builder);
4741 LLVMDisposePassManager(passmgr);
4742 }
4743
4744 static void
4745 ac_setup_rings(struct nir_to_llvm_context *ctx)
4746 {
4747 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4748 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4749 }
4750
4751 if (ctx->is_gs_copy_shader) {
4752 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4753 }
4754 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4755 LLVMValueRef tmp;
4756 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4757 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4758
4759 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4760
4761 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4762 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4763 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4764 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4765
4766 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4767 }
4768 }
4769
4770 static
4771 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4772 struct nir_shader *nir,
4773 struct ac_shader_variant_info *shader_info,
4774 const struct ac_nir_compiler_options *options)
4775 {
4776 struct nir_to_llvm_context ctx = {0};
4777 struct nir_function *func;
4778 unsigned i;
4779 ctx.options = options;
4780 ctx.shader_info = shader_info;
4781 ctx.context = LLVMContextCreate();
4782 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4783
4784 ac_llvm_context_init(&ctx.ac, ctx.context);
4785 ctx.ac.module = ctx.module;
4786
4787 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4788
4789 memset(shader_info, 0, sizeof(*shader_info));
4790
4791 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4792
4793 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
4794 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
4795 LLVMSetDataLayout(ctx.module, data_layout_str);
4796 LLVMDisposeTargetData(data_layout);
4797 LLVMDisposeMessage(data_layout_str);
4798
4799 setup_types(&ctx);
4800
4801 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4802 ctx.ac.builder = ctx.builder;
4803 ctx.stage = nir->stage;
4804
4805 for (i = 0; i < AC_UD_MAX_SETS; i++)
4806 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4807 for (i = 0; i < AC_UD_MAX_UD; i++)
4808 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4809
4810 create_function(&ctx);
4811
4812 if (nir->stage == MESA_SHADER_COMPUTE) {
4813 int num_shared = 0;
4814 nir_foreach_variable(variable, &nir->shared)
4815 num_shared++;
4816 if (num_shared) {
4817 int idx = 0;
4818 uint32_t shared_size = 0;
4819 LLVMValueRef var;
4820 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4821 nir_foreach_variable(variable, &nir->shared) {
4822 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4823 idx++;
4824 }
4825
4826 shared_size *= 16;
4827 var = LLVMAddGlobalInAddressSpace(ctx.module,
4828 LLVMArrayType(ctx.i8, shared_size),
4829 "compute_lds",
4830 LOCAL_ADDR_SPACE);
4831 LLVMSetAlignment(var, 4);
4832 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4833 }
4834 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4835 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4836
4837 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4838 }
4839
4840 ac_setup_rings(&ctx);
4841
4842 nir_foreach_variable(variable, &nir->inputs)
4843 handle_shader_input_decl(&ctx, variable);
4844
4845 if (nir->stage == MESA_SHADER_FRAGMENT)
4846 handle_fs_inputs_pre(&ctx, nir);
4847
4848 nir_foreach_variable(variable, &nir->outputs)
4849 handle_shader_output_decl(&ctx, variable);
4850
4851 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4852 _mesa_key_pointer_equal);
4853 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4854 _mesa_key_pointer_equal);
4855
4856 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4857
4858 setup_locals(&ctx, func);
4859
4860 visit_cf_list(&ctx, &func->impl->body);
4861 phi_post_pass(&ctx);
4862
4863 handle_shader_outputs_post(&ctx);
4864 LLVMBuildRetVoid(ctx.builder);
4865
4866 ac_llvm_finalize_module(&ctx);
4867 free(ctx.locals);
4868 ralloc_free(ctx.defs);
4869 ralloc_free(ctx.phis);
4870
4871 if (nir->stage == MESA_SHADER_GEOMETRY) {
4872 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4873 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4874 nir->info->gs.vertices_out;
4875 }
4876 return ctx.module;
4877 }
4878
4879 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4880 {
4881 unsigned *retval = (unsigned *)context;
4882 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4883 char *description = LLVMGetDiagInfoDescription(di);
4884
4885 if (severity == LLVMDSError) {
4886 *retval = 1;
4887 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4888 description);
4889 }
4890
4891 LLVMDisposeMessage(description);
4892 }
4893
4894 static unsigned ac_llvm_compile(LLVMModuleRef M,
4895 struct ac_shader_binary *binary,
4896 LLVMTargetMachineRef tm)
4897 {
4898 unsigned retval = 0;
4899 char *err;
4900 LLVMContextRef llvm_ctx;
4901 LLVMMemoryBufferRef out_buffer;
4902 unsigned buffer_size;
4903 const char *buffer_data;
4904 LLVMBool mem_err;
4905
4906 /* Setup Diagnostic Handler*/
4907 llvm_ctx = LLVMGetModuleContext(M);
4908
4909 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4910 &retval);
4911
4912 /* Compile IR*/
4913 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4914 &err, &out_buffer);
4915
4916 /* Process Errors/Warnings */
4917 if (mem_err) {
4918 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4919 free(err);
4920 retval = 1;
4921 goto out;
4922 }
4923
4924 /* Extract Shader Code*/
4925 buffer_size = LLVMGetBufferSize(out_buffer);
4926 buffer_data = LLVMGetBufferStart(out_buffer);
4927
4928 ac_elf_read(buffer_data, buffer_size, binary);
4929
4930 /* Clean up */
4931 LLVMDisposeMemoryBuffer(out_buffer);
4932
4933 out:
4934 return retval;
4935 }
4936
4937 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4938 LLVMModuleRef llvm_module,
4939 struct ac_shader_binary *binary,
4940 struct ac_shader_config *config,
4941 struct ac_shader_variant_info *shader_info,
4942 gl_shader_stage stage,
4943 bool dump_shader, bool supports_spill)
4944 {
4945 if (dump_shader)
4946 ac_dump_module(llvm_module);
4947
4948 memset(binary, 0, sizeof(*binary));
4949 int v = ac_llvm_compile(llvm_module, binary, tm);
4950 if (v) {
4951 fprintf(stderr, "compile failed\n");
4952 }
4953
4954 if (dump_shader)
4955 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4956
4957 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4958
4959 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4960 LLVMDisposeModule(llvm_module);
4961 LLVMContextDispose(ctx);
4962
4963 if (stage == MESA_SHADER_FRAGMENT) {
4964 shader_info->num_input_vgprs = 0;
4965 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4966 shader_info->num_input_vgprs += 2;
4967 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4968 shader_info->num_input_vgprs += 2;
4969 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4970 shader_info->num_input_vgprs += 2;
4971 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4972 shader_info->num_input_vgprs += 3;
4973 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
4974 shader_info->num_input_vgprs += 2;
4975 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
4976 shader_info->num_input_vgprs += 2;
4977 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
4978 shader_info->num_input_vgprs += 2;
4979 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
4980 shader_info->num_input_vgprs += 1;
4981 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
4982 shader_info->num_input_vgprs += 1;
4983 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
4984 shader_info->num_input_vgprs += 1;
4985 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
4986 shader_info->num_input_vgprs += 1;
4987 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
4988 shader_info->num_input_vgprs += 1;
4989 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
4990 shader_info->num_input_vgprs += 1;
4991 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
4992 shader_info->num_input_vgprs += 1;
4993 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
4994 shader_info->num_input_vgprs += 1;
4995 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
4996 shader_info->num_input_vgprs += 1;
4997 }
4998 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
4999
5000 /* +3 for scratch wave offset and VCC */
5001 config->num_sgprs = MAX2(config->num_sgprs,
5002 shader_info->num_input_sgprs + 3);
5003 }
5004
5005 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5006 struct ac_shader_binary *binary,
5007 struct ac_shader_config *config,
5008 struct ac_shader_variant_info *shader_info,
5009 struct nir_shader *nir,
5010 const struct ac_nir_compiler_options *options,
5011 bool dump_shader)
5012 {
5013
5014 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5015 options);
5016
5017 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5018 switch (nir->stage) {
5019 case MESA_SHADER_COMPUTE:
5020 for (int i = 0; i < 3; ++i)
5021 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5022 break;
5023 case MESA_SHADER_FRAGMENT:
5024 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5025 break;
5026 case MESA_SHADER_GEOMETRY:
5027 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5028 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5029 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5030 shader_info->gs.invocations = nir->info->gs.invocations;
5031 break;
5032 case MESA_SHADER_VERTEX:
5033 shader_info->vs.as_es = options->key.vs.as_es;
5034 break;
5035 default:
5036 break;
5037 }
5038 }
5039
5040 static void
5041 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5042 {
5043 LLVMValueRef args[9];
5044 args[0] = ctx->gsvs_ring;
5045 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5046 args[3] = ctx->i32zero;
5047 args[4] = ctx->i32one; /* OFFEN */
5048 args[5] = ctx->i32zero; /* IDXEN */
5049 args[6] = ctx->i32one; /* GLC */
5050 args[7] = ctx->i32one; /* SLC */
5051 args[8] = ctx->i32zero; /* TFE */
5052
5053 int idx = 0;
5054 int clip_cull_slot = -1;
5055 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5056 int length = 4;
5057 int start = 0;
5058 int slot = idx;
5059 int slot_inc = 1;
5060 if (!(ctx->output_mask & (1ull << i)))
5061 continue;
5062
5063 if (i == VARYING_SLOT_CLIP_DIST1 ||
5064 i == VARYING_SLOT_CULL_DIST1)
5065 continue;
5066
5067 if (i == VARYING_SLOT_CLIP_DIST0 ||
5068 i == VARYING_SLOT_CULL_DIST0) {
5069 /* unpack clip and cull from a single set of slots */
5070 if (clip_cull_slot == -1) {
5071 clip_cull_slot = idx;
5072 if (ctx->num_output_clips + ctx->num_output_culls > 4)
5073 slot_inc = 2;
5074 } else {
5075 slot = clip_cull_slot;
5076 slot_inc = 0;
5077 }
5078 if (i == VARYING_SLOT_CLIP_DIST0)
5079 length = ctx->num_output_clips;
5080 if (i == VARYING_SLOT_CULL_DIST0) {
5081 start = ctx->num_output_clips;
5082 length = ctx->num_output_culls;
5083 }
5084 }
5085
5086 for (unsigned j = 0; j < length; j++) {
5087 LLVMValueRef value;
5088 args[2] = LLVMConstInt(ctx->i32,
5089 (slot * 4 + j + start) *
5090 ctx->gs_max_out_vertices * 16 * 4, false);
5091
5092 value = ac_build_intrinsic(&ctx->ac,
5093 "llvm.SI.buffer.load.dword.i32.i32",
5094 ctx->i32, args, 9,
5095 AC_FUNC_ATTR_READONLY |
5096 AC_FUNC_ATTR_LEGACY);
5097
5098 LLVMBuildStore(ctx->builder,
5099 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5100 }
5101 idx += slot_inc;
5102 }
5103 handle_vs_outputs_post(ctx);
5104 }
5105
5106 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5107 struct nir_shader *geom_shader,
5108 struct ac_shader_binary *binary,
5109 struct ac_shader_config *config,
5110 struct ac_shader_variant_info *shader_info,
5111 const struct ac_nir_compiler_options *options,
5112 bool dump_shader)
5113 {
5114 struct nir_to_llvm_context ctx = {0};
5115 ctx.context = LLVMContextCreate();
5116 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5117 ctx.options = options;
5118 ctx.shader_info = shader_info;
5119
5120 ac_llvm_context_init(&ctx.ac, ctx.context);
5121 ctx.ac.module = ctx.module;
5122
5123 ctx.is_gs_copy_shader = true;
5124 LLVMSetTarget(ctx.module, "amdgcn--");
5125 setup_types(&ctx);
5126
5127 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5128 ctx.ac.builder = ctx.builder;
5129 ctx.stage = MESA_SHADER_VERTEX;
5130
5131 create_function(&ctx);
5132
5133 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5134 ac_setup_rings(&ctx);
5135
5136 nir_foreach_variable(variable, &geom_shader->outputs)
5137 handle_shader_output_decl(&ctx, variable);
5138
5139 ac_gs_copy_shader_emit(&ctx);
5140
5141 LLVMBuildRetVoid(ctx.builder);
5142
5143 ac_llvm_finalize_module(&ctx);
5144
5145 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5146 MESA_SHADER_VERTEX,
5147 dump_shader, options->supports_spill);
5148 }