projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ac/radv: cleanup some tcs output values access
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 };
131
132 static inline struct radv_shader_context *
133 radv_shader_context_from_abi(struct ac_shader_abi *abi)
134 {
135 struct radv_shader_context *ctx = NULL;
136 return container_of(abi, ctx, abi);
137 }
138
139 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
140 const nir_deref_var *deref,
141 enum ac_descriptor_type desc_type,
142 const nir_tex_instr *instr,
143 bool image, bool write);
144
145 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
146 {
147 return (index * 4) + chan;
148 }
149
150 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
151 {
152 /* handle patch indices separate */
153 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
154 return 0;
155 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
156 return 1;
157 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
158 return 2 + (slot - VARYING_SLOT_PATCH0);
159
160 if (slot == VARYING_SLOT_POS)
161 return 0;
162 if (slot == VARYING_SLOT_PSIZ)
163 return 1;
164 if (slot == VARYING_SLOT_CLIP_DIST0)
165 return 2;
166 /* 3 is reserved for clip dist as well */
167 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
168 return 4 + (slot - VARYING_SLOT_VAR0);
169 unreachable("illegal slot in get unique index\n");
170 }
171
172 static void set_llvm_calling_convention(LLVMValueRef func,
173 gl_shader_stage stage)
174 {
175 enum radeon_llvm_calling_convention calling_conv;
176
177 switch (stage) {
178 case MESA_SHADER_VERTEX:
179 case MESA_SHADER_TESS_EVAL:
180 calling_conv = RADEON_LLVM_AMDGPU_VS;
181 break;
182 case MESA_SHADER_GEOMETRY:
183 calling_conv = RADEON_LLVM_AMDGPU_GS;
184 break;
185 case MESA_SHADER_TESS_CTRL:
186 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
187 break;
188 case MESA_SHADER_FRAGMENT:
189 calling_conv = RADEON_LLVM_AMDGPU_PS;
190 break;
191 case MESA_SHADER_COMPUTE:
192 calling_conv = RADEON_LLVM_AMDGPU_CS;
193 break;
194 default:
195 unreachable("Unhandle shader type");
196 }
197
198 LLVMSetFunctionCallConv(func, calling_conv);
199 }
200
201 #define MAX_ARGS 23
202 struct arg_info {
203 LLVMTypeRef types[MAX_ARGS];
204 LLVMValueRef *assign[MAX_ARGS];
205 unsigned array_params_mask;
206 uint8_t count;
207 uint8_t sgpr_count;
208 uint8_t num_sgprs_used;
209 uint8_t num_vgprs_used;
210 };
211
212 enum ac_arg_regfile {
213 ARG_SGPR,
214 ARG_VGPR,
215 };
216
217 static void
218 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
219 LLVMValueRef *param_ptr)
220 {
221 assert(info->count < MAX_ARGS);
222
223 info->assign[info->count] = param_ptr;
224 info->types[info->count] = type;
225 info->count++;
226
227 if (regfile == ARG_SGPR) {
228 info->num_sgprs_used += ac_get_type_size(type) / 4;
229 info->sgpr_count++;
230 } else {
231 assert(regfile == ARG_VGPR);
232 info->num_vgprs_used += ac_get_type_size(type) / 4;
233 }
234 }
235
236 static inline void
237 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
238 {
239 info->array_params_mask |= (1 << info->count);
240 add_arg(info, ARG_SGPR, type, param_ptr);
241 }
242
243 static void assign_arguments(LLVMValueRef main_function,
244 struct arg_info *info)
245 {
246 unsigned i;
247 for (i = 0; i < info->count; i++) {
248 if (info->assign[i])
249 *info->assign[i] = LLVMGetParam(main_function, i);
250 }
251 }
252
253 static LLVMValueRef
254 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
255 LLVMBuilderRef builder, LLVMTypeRef *return_types,
256 unsigned num_return_elems,
257 struct arg_info *args,
258 unsigned max_workgroup_size,
259 bool unsafe_math)
260 {
261 LLVMTypeRef main_function_type, ret_type;
262 LLVMBasicBlockRef main_function_body;
263
264 if (num_return_elems)
265 ret_type = LLVMStructTypeInContext(ctx, return_types,
266 num_return_elems, true);
267 else
268 ret_type = LLVMVoidTypeInContext(ctx);
269
270 /* Setup the function */
271 main_function_type =
272 LLVMFunctionType(ret_type, args->types, args->count, 0);
273 LLVMValueRef main_function =
274 LLVMAddFunction(module, "main", main_function_type);
275 main_function_body =
276 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
277 LLVMPositionBuilderAtEnd(builder, main_function_body);
278
279 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
280 for (unsigned i = 0; i < args->sgpr_count; ++i) {
281 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
282
283 if (args->array_params_mask & (1 << i)) {
284 LLVMValueRef P = LLVMGetParam(main_function, i);
285 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
286 ac_add_attr_dereferenceable(P, UINT64_MAX);
287 }
288 }
289
290 if (max_workgroup_size) {
291 ac_llvm_add_target_dep_function_attr(main_function,
292 "amdgpu-max-work-group-size",
293 max_workgroup_size);
294 }
295 if (unsafe_math) {
296 /* These were copied from some LLVM test. */
297 LLVMAddTargetDependentFunctionAttr(main_function,
298 "less-precise-fpmad",
299 "true");
300 LLVMAddTargetDependentFunctionAttr(main_function,
301 "no-infs-fp-math",
302 "true");
303 LLVMAddTargetDependentFunctionAttr(main_function,
304 "no-nans-fp-math",
305 "true");
306 LLVMAddTargetDependentFunctionAttr(main_function,
307 "unsafe-fp-math",
308 "true");
309 LLVMAddTargetDependentFunctionAttr(main_function,
310 "no-signed-zeros-fp-math",
311 "true");
312 }
313 return main_function;
314 }
315
316 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
317 LLVMValueRef param, unsigned rshift,
318 unsigned bitwidth)
319 {
320 LLVMValueRef value = param;
321 if (rshift)
322 value = LLVMBuildLShr(ctx->builder, value,
323 LLVMConstInt(ctx->i32, rshift, false), "");
324
325 if (rshift + bitwidth < 32) {
326 unsigned mask = (1 << bitwidth) - 1;
327 value = LLVMBuildAnd(ctx->builder, value,
328 LLVMConstInt(ctx->i32, mask, false), "");
329 }
330 return value;
331 }
332
333 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
334 {
335 switch (ctx->stage) {
336 case MESA_SHADER_TESS_CTRL:
337 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
338 case MESA_SHADER_TESS_EVAL:
339 return ctx->tes_rel_patch_id;
340 break;
341 default:
342 unreachable("Illegal stage");
343 }
344 }
345
346 /* Tessellation shaders pass outputs to the next shader using LDS.
347 *
348 * LS outputs = TCS inputs
349 * TCS outputs = TES inputs
350 *
351 * The LDS layout is:
352 * - TCS inputs for patch 0
353 * - TCS inputs for patch 1
354 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
355 * - ...
356 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
357 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
358 * - TCS outputs for patch 1
359 * - Per-patch TCS outputs for patch 1
360 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
361 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
362 * - ...
363 *
364 * All three shaders VS(LS), TCS, TES share the same LDS space.
365 */
366 static LLVMValueRef
367 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
368 {
369 if (ctx->stage == MESA_SHADER_VERTEX)
370 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
371 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
372 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
373 else {
374 assert(0);
375 return NULL;
376 }
377 }
378
379 static LLVMValueRef
380 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
381 {
382 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
383 }
384
385 static LLVMValueRef
386 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
387 {
388 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
389 }
390
391 static LLVMValueRef
392 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
393 {
394 return LLVMBuildMul(ctx->ac.builder,
395 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
396 LLVMConstInt(ctx->ac.i32, 4, false), "");
397 }
398
399 static LLVMValueRef
400 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
401 {
402 return LLVMBuildMul(ctx->ac.builder,
403 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
404 LLVMConstInt(ctx->ac.i32, 4, false), "");
405 }
406
407 static LLVMValueRef
408 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
409 {
410 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
411 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
412
413 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
414 }
415
416 static LLVMValueRef
417 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
418 {
419 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
420 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
421 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
422
423 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
424 LLVMBuildMul(ctx->ac.builder, patch_stride,
425 rel_patch_id, ""),
426 "");
427 }
428
429 static LLVMValueRef
430 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
431 {
432 LLVMValueRef patch0_patch_data_offset =
433 get_tcs_out_patch0_patch_data_offset(ctx);
434 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
435 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
436
437 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
438 LLVMBuildMul(ctx->ac.builder, patch_stride,
439 rel_patch_id, ""),
440 "");
441 }
442
443 static void
444 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
445 uint32_t indirect_offset)
446 {
447 ud_info->sgpr_idx = *sgpr_idx;
448 ud_info->num_sgprs = num_sgprs;
449 ud_info->indirect = indirect_offset > 0;
450 ud_info->indirect_offset = indirect_offset;
451 *sgpr_idx += num_sgprs;
452 }
453
454 static void
455 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
456 uint8_t num_sgprs)
457 {
458 struct ac_userdata_info *ud_info =
459 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
460 assert(ud_info);
461
462 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
463 }
464
465 static void
466 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
467 uint32_t indirect_offset)
468 {
469 struct ac_userdata_info *ud_info =
470 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
471 assert(ud_info);
472
473 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
474 }
475
476 struct user_sgpr_info {
477 bool need_ring_offsets;
478 uint8_t sgpr_count;
479 bool indirect_all_descriptor_sets;
480 };
481
482 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
483 gl_shader_stage stage)
484 {
485 switch (stage) {
486 case MESA_SHADER_VERTEX:
487 if (ctx->shader_info->info.needs_multiview_view_index ||
488 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
489 return true;
490 break;
491 case MESA_SHADER_TESS_EVAL:
492 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
493 return true;
494 break;
495 case MESA_SHADER_GEOMETRY:
496 case MESA_SHADER_TESS_CTRL:
497 if (ctx->shader_info->info.needs_multiview_view_index)
498 return true;
499 break;
500 default:
501 break;
502 }
503 return false;
504 }
505
506 static uint8_t
507 count_vs_user_sgprs(struct radv_shader_context *ctx)
508 {
509 uint8_t count = 0;
510
511 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
512 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
513
514 return count;
515 }
516
517 static void allocate_user_sgprs(struct radv_shader_context *ctx,
518 gl_shader_stage stage,
519 bool has_previous_stage,
520 gl_shader_stage previous_stage,
521 bool needs_view_index,
522 struct user_sgpr_info *user_sgpr_info)
523 {
524 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
525
526 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
527 if (stage == MESA_SHADER_GEOMETRY ||
528 stage == MESA_SHADER_VERTEX ||
529 stage == MESA_SHADER_TESS_CTRL ||
530 stage == MESA_SHADER_TESS_EVAL ||
531 ctx->is_gs_copy_shader)
532 user_sgpr_info->need_ring_offsets = true;
533
534 if (stage == MESA_SHADER_FRAGMENT &&
535 ctx->shader_info->info.ps.needs_sample_positions)
536 user_sgpr_info->need_ring_offsets = true;
537
538 /* 2 user sgprs will nearly always be allocated for scratch/rings */
539 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
540 user_sgpr_info->sgpr_count += 2;
541 }
542
543 switch (stage) {
544 case MESA_SHADER_COMPUTE:
545 if (ctx->shader_info->info.cs.uses_grid_size)
546 user_sgpr_info->sgpr_count += 3;
547 break;
548 case MESA_SHADER_FRAGMENT:
549 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
550 break;
551 case MESA_SHADER_VERTEX:
552 if (!ctx->is_gs_copy_shader)
553 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
554 if (ctx->options->key.vs.as_ls)
555 user_sgpr_info->sgpr_count++;
556 break;
557 case MESA_SHADER_TESS_CTRL:
558 if (has_previous_stage) {
559 if (previous_stage == MESA_SHADER_VERTEX)
560 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
561 user_sgpr_info->sgpr_count++;
562 }
563 user_sgpr_info->sgpr_count += 4;
564 break;
565 case MESA_SHADER_TESS_EVAL:
566 user_sgpr_info->sgpr_count += 1;
567 break;
568 case MESA_SHADER_GEOMETRY:
569 if (has_previous_stage) {
570 if (previous_stage == MESA_SHADER_VERTEX) {
571 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
572 } else {
573 user_sgpr_info->sgpr_count++;
574 }
575 }
576 user_sgpr_info->sgpr_count += 2;
577 break;
578 default:
579 break;
580 }
581
582 if (needs_view_index)
583 user_sgpr_info->sgpr_count++;
584
585 if (ctx->shader_info->info.loads_push_constants)
586 user_sgpr_info->sgpr_count += 2;
587
588 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
589 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
590
591 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
592 user_sgpr_info->sgpr_count += 2;
593 user_sgpr_info->indirect_all_descriptor_sets = true;
594 } else {
595 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
596 }
597 }
598
599 static void
600 declare_global_input_sgprs(struct radv_shader_context *ctx,
601 gl_shader_stage stage,
602 bool has_previous_stage,
603 gl_shader_stage previous_stage,
604 const struct user_sgpr_info *user_sgpr_info,
605 struct arg_info *args,
606 LLVMValueRef *desc_sets)
607 {
608 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
609 unsigned num_sets = ctx->options->layout ?
610 ctx->options->layout->num_sets : 0;
611 unsigned stage_mask = 1 << stage;
612
613 if (has_previous_stage)
614 stage_mask |= 1 << previous_stage;
615
616 /* 1 for each descriptor set */
617 if (!user_sgpr_info->indirect_all_descriptor_sets) {
618 for (unsigned i = 0; i < num_sets; ++i) {
619 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
620 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
621 add_array_arg(args, type,
622 &ctx->descriptor_sets[i]);
623 }
624 }
625 } else {
626 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
627 }
628
629 if (ctx->shader_info->info.loads_push_constants) {
630 /* 1 for push constants and dynamic descriptors */
631 add_array_arg(args, type, &ctx->abi.push_constants);
632 }
633 }
634
635 static void
636 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
637 gl_shader_stage stage,
638 bool has_previous_stage,
639 gl_shader_stage previous_stage,
640 struct arg_info *args)
641 {
642 if (!ctx->is_gs_copy_shader &&
643 (stage == MESA_SHADER_VERTEX ||
644 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
645 if (ctx->shader_info->info.vs.has_vertex_buffers) {
646 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
647 &ctx->vertex_buffers);
648 }
649 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
650 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
651 if (ctx->shader_info->info.vs.needs_draw_id) {
652 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
653 }
654 }
655 }
656
657 static void
658 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
659 {
660 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
661 if (!ctx->is_gs_copy_shader) {
662 if (ctx->options->key.vs.as_ls) {
663 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
664 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
665 } else {
666 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
667 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
668 }
669 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
670 }
671 }
672
673 static void
674 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
675 {
676 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
677 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
678 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
679 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
680 }
681
682 static void
683 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
684 bool has_previous_stage, gl_shader_stage previous_stage,
685 const struct user_sgpr_info *user_sgpr_info,
686 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
687 {
688 unsigned num_sets = ctx->options->layout ?
689 ctx->options->layout->num_sets : 0;
690 unsigned stage_mask = 1 << stage;
691
692 if (has_previous_stage)
693 stage_mask |= 1 << previous_stage;
694
695 if (!user_sgpr_info->indirect_all_descriptor_sets) {
696 for (unsigned i = 0; i < num_sets; ++i) {
697 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
698 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
699 set_loc_desc(ctx, i, user_sgpr_idx, 0);
700 } else
701 ctx->descriptor_sets[i] = NULL;
702 }
703 } else {
704 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
705 user_sgpr_idx, 2);
706
707 for (unsigned i = 0; i < num_sets; ++i) {
708 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
709 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
710 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
711 ctx->descriptor_sets[i] =
712 ac_build_load_to_sgpr(&ctx->ac,
713 desc_sets,
714 LLVMConstInt(ctx->ac.i32, i, false));
715
716 } else
717 ctx->descriptor_sets[i] = NULL;
718 }
719 ctx->shader_info->need_indirect_descriptor_sets = true;
720 }
721
722 if (ctx->shader_info->info.loads_push_constants) {
723 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
724 }
725 }
726
727 static void
728 set_vs_specific_input_locs(struct radv_shader_context *ctx,
729 gl_shader_stage stage, bool has_previous_stage,
730 gl_shader_stage previous_stage,
731 uint8_t *user_sgpr_idx)
732 {
733 if (!ctx->is_gs_copy_shader &&
734 (stage == MESA_SHADER_VERTEX ||
735 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
736 if (ctx->shader_info->info.vs.has_vertex_buffers) {
737 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
738 user_sgpr_idx, 2);
739 }
740
741 unsigned vs_num = 2;
742 if (ctx->shader_info->info.vs.needs_draw_id)
743 vs_num++;
744
745 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
746 user_sgpr_idx, vs_num);
747 }
748 }
749
750 static void create_function(struct radv_shader_context *ctx,
751 gl_shader_stage stage,
752 bool has_previous_stage,
753 gl_shader_stage previous_stage)
754 {
755 uint8_t user_sgpr_idx;
756 struct user_sgpr_info user_sgpr_info;
757 struct arg_info args = {};
758 LLVMValueRef desc_sets;
759 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
760 allocate_user_sgprs(ctx, stage, has_previous_stage,
761 previous_stage, needs_view_index, &user_sgpr_info);
762
763 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
764 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
765 &ctx->ring_offsets);
766 }
767
768 switch (stage) {
769 case MESA_SHADER_COMPUTE:
770 declare_global_input_sgprs(ctx, stage, has_previous_stage,
771 previous_stage, &user_sgpr_info,
772 &args, &desc_sets);
773
774 if (ctx->shader_info->info.cs.uses_grid_size) {
775 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
776 &ctx->abi.num_work_groups);
777 }
778
779 for (int i = 0; i < 3; i++) {
780 ctx->abi.workgroup_ids[i] = NULL;
781 if (ctx->shader_info->info.cs.uses_block_id[i]) {
782 add_arg(&args, ARG_SGPR, ctx->ac.i32,
783 &ctx->abi.workgroup_ids[i]);
784 }
785 }
786
787 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
788 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
789 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
790 &ctx->abi.local_invocation_ids);
791 break;
792 case MESA_SHADER_VERTEX:
793 declare_global_input_sgprs(ctx, stage, has_previous_stage,
794 previous_stage, &user_sgpr_info,
795 &args, &desc_sets);
796 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
797 previous_stage, &args);
798
799 if (needs_view_index)
800 add_arg(&args, ARG_SGPR, ctx->ac.i32,
801 &ctx->abi.view_index);
802 if (ctx->options->key.vs.as_es)
803 add_arg(&args, ARG_SGPR, ctx->ac.i32,
804 &ctx->es2gs_offset);
805 else if (ctx->options->key.vs.as_ls)
806 add_arg(&args, ARG_SGPR, ctx->ac.i32,
807 &ctx->ls_out_layout);
808
809 declare_vs_input_vgprs(ctx, &args);
810 break;
811 case MESA_SHADER_TESS_CTRL:
812 if (has_previous_stage) {
813 // First 6 system regs
814 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
815 add_arg(&args, ARG_SGPR, ctx->ac.i32,
816 &ctx->merged_wave_info);
817 add_arg(&args, ARG_SGPR, ctx->ac.i32,
818 &ctx->tess_factor_offset);
819
820 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823
824 declare_global_input_sgprs(ctx, stage,
825 has_previous_stage,
826 previous_stage,
827 &user_sgpr_info, &args,
828 &desc_sets);
829 declare_vs_specific_input_sgprs(ctx, stage,
830 has_previous_stage,
831 previous_stage, &args);
832
833 add_arg(&args, ARG_SGPR, ctx->ac.i32,
834 &ctx->ls_out_layout);
835
836 add_arg(&args, ARG_SGPR, ctx->ac.i32,
837 &ctx->tcs_offchip_layout);
838 add_arg(&args, ARG_SGPR, ctx->ac.i32,
839 &ctx->tcs_out_offsets);
840 add_arg(&args, ARG_SGPR, ctx->ac.i32,
841 &ctx->tcs_out_layout);
842 add_arg(&args, ARG_SGPR, ctx->ac.i32,
843 &ctx->tcs_in_layout);
844 if (needs_view_index)
845 add_arg(&args, ARG_SGPR, ctx->ac.i32,
846 &ctx->abi.view_index);
847
848 add_arg(&args, ARG_VGPR, ctx->ac.i32,
849 &ctx->abi.tcs_patch_id);
850 add_arg(&args, ARG_VGPR, ctx->ac.i32,
851 &ctx->abi.tcs_rel_ids);
852
853 declare_vs_input_vgprs(ctx, &args);
854 } else {
855 declare_global_input_sgprs(ctx, stage,
856 has_previous_stage,
857 previous_stage,
858 &user_sgpr_info, &args,
859 &desc_sets);
860
861 add_arg(&args, ARG_SGPR, ctx->ac.i32,
862 &ctx->tcs_offchip_layout);
863 add_arg(&args, ARG_SGPR, ctx->ac.i32,
864 &ctx->tcs_out_offsets);
865 add_arg(&args, ARG_SGPR, ctx->ac.i32,
866 &ctx->tcs_out_layout);
867 add_arg(&args, ARG_SGPR, ctx->ac.i32,
868 &ctx->tcs_in_layout);
869 if (needs_view_index)
870 add_arg(&args, ARG_SGPR, ctx->ac.i32,
871 &ctx->abi.view_index);
872
873 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
874 add_arg(&args, ARG_SGPR, ctx->ac.i32,
875 &ctx->tess_factor_offset);
876 add_arg(&args, ARG_VGPR, ctx->ac.i32,
877 &ctx->abi.tcs_patch_id);
878 add_arg(&args, ARG_VGPR, ctx->ac.i32,
879 &ctx->abi.tcs_rel_ids);
880 }
881 break;
882 case MESA_SHADER_TESS_EVAL:
883 declare_global_input_sgprs(ctx, stage, has_previous_stage,
884 previous_stage, &user_sgpr_info,
885 &args, &desc_sets);
886
887 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
888 if (needs_view_index)
889 add_arg(&args, ARG_SGPR, ctx->ac.i32,
890 &ctx->abi.view_index);
891
892 if (ctx->options->key.tes.as_es) {
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32,
896 &ctx->es2gs_offset);
897 } else {
898 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
900 }
901 declare_tes_input_vgprs(ctx, &args);
902 break;
903 case MESA_SHADER_GEOMETRY:
904 if (has_previous_stage) {
905 // First 6 system regs
906 add_arg(&args, ARG_SGPR, ctx->ac.i32,
907 &ctx->gs2vs_offset);
908 add_arg(&args, ARG_SGPR, ctx->ac.i32,
909 &ctx->merged_wave_info);
910 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
911
912 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915
916 declare_global_input_sgprs(ctx, stage,
917 has_previous_stage,
918 previous_stage,
919 &user_sgpr_info, &args,
920 &desc_sets);
921
922 if (previous_stage == MESA_SHADER_TESS_EVAL) {
923 add_arg(&args, ARG_SGPR, ctx->ac.i32,
924 &ctx->tcs_offchip_layout);
925 } else {
926 declare_vs_specific_input_sgprs(ctx, stage,
927 has_previous_stage,
928 previous_stage,
929 &args);
930 }
931
932 add_arg(&args, ARG_SGPR, ctx->ac.i32,
933 &ctx->gsvs_ring_stride);
934 add_arg(&args, ARG_SGPR, ctx->ac.i32,
935 &ctx->gsvs_num_entries);
936 if (needs_view_index)
937 add_arg(&args, ARG_SGPR, ctx->ac.i32,
938 &ctx->abi.view_index);
939
940 add_arg(&args, ARG_VGPR, ctx->ac.i32,
941 &ctx->gs_vtx_offset[0]);
942 add_arg(&args, ARG_VGPR, ctx->ac.i32,
943 &ctx->gs_vtx_offset[2]);
944 add_arg(&args, ARG_VGPR, ctx->ac.i32,
945 &ctx->abi.gs_prim_id);
946 add_arg(&args, ARG_VGPR, ctx->ac.i32,
947 &ctx->abi.gs_invocation_id);
948 add_arg(&args, ARG_VGPR, ctx->ac.i32,
949 &ctx->gs_vtx_offset[4]);
950
951 if (previous_stage == MESA_SHADER_VERTEX) {
952 declare_vs_input_vgprs(ctx, &args);
953 } else {
954 declare_tes_input_vgprs(ctx, &args);
955 }
956 } else {
957 declare_global_input_sgprs(ctx, stage,
958 has_previous_stage,
959 previous_stage,
960 &user_sgpr_info, &args,
961 &desc_sets);
962
963 add_arg(&args, ARG_SGPR, ctx->ac.i32,
964 &ctx->gsvs_ring_stride);
965 add_arg(&args, ARG_SGPR, ctx->ac.i32,
966 &ctx->gsvs_num_entries);
967 if (needs_view_index)
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->abi.view_index);
970
971 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
973 add_arg(&args, ARG_VGPR, ctx->ac.i32,
974 &ctx->gs_vtx_offset[0]);
975 add_arg(&args, ARG_VGPR, ctx->ac.i32,
976 &ctx->gs_vtx_offset[1]);
977 add_arg(&args, ARG_VGPR, ctx->ac.i32,
978 &ctx->abi.gs_prim_id);
979 add_arg(&args, ARG_VGPR, ctx->ac.i32,
980 &ctx->gs_vtx_offset[2]);
981 add_arg(&args, ARG_VGPR, ctx->ac.i32,
982 &ctx->gs_vtx_offset[3]);
983 add_arg(&args, ARG_VGPR, ctx->ac.i32,
984 &ctx->gs_vtx_offset[4]);
985 add_arg(&args, ARG_VGPR, ctx->ac.i32,
986 &ctx->gs_vtx_offset[5]);
987 add_arg(&args, ARG_VGPR, ctx->ac.i32,
988 &ctx->abi.gs_invocation_id);
989 }
990 break;
991 case MESA_SHADER_FRAGMENT:
992 declare_global_input_sgprs(ctx, stage, has_previous_stage,
993 previous_stage, &user_sgpr_info,
994 &args, &desc_sets);
995
996 if (ctx->shader_info->info.ps.needs_sample_positions)
997 add_arg(&args, ARG_SGPR, ctx->ac.i32,
998 &ctx->sample_pos_offset);
999
1000 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1001 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1005 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1008 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1017 break;
1018 default:
1019 unreachable("Shader stage not implemented");
1020 }
1021
1022 ctx->main_function = create_llvm_function(
1023 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1024 ctx->max_workgroup_size,
1025 ctx->options->unsafe_math);
1026 set_llvm_calling_convention(ctx->main_function, stage);
1027
1028
1029 ctx->shader_info->num_input_vgprs = 0;
1030 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1031
1032 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1033
1034 if (ctx->stage != MESA_SHADER_FRAGMENT)
1035 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1036
1037 assign_arguments(ctx->main_function, &args);
1038
1039 user_sgpr_idx = 0;
1040
1041 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1042 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1043 &user_sgpr_idx, 2);
1044 if (ctx->options->supports_spill) {
1045 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1046 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1047 NULL, 0, AC_FUNC_ATTR_READNONE);
1048 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1049 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1050 }
1051 }
1052
1053 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1054 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1055 if (has_previous_stage)
1056 user_sgpr_idx = 0;
1057
1058 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1059 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1060
1061 switch (stage) {
1062 case MESA_SHADER_COMPUTE:
1063 if (ctx->shader_info->info.cs.uses_grid_size) {
1064 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1065 &user_sgpr_idx, 3);
1066 }
1067 break;
1068 case MESA_SHADER_VERTEX:
1069 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1070 previous_stage, &user_sgpr_idx);
1071 if (ctx->abi.view_index)
1072 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1073 if (ctx->options->key.vs.as_ls) {
1074 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1075 &user_sgpr_idx, 1);
1076 }
1077 break;
1078 case MESA_SHADER_TESS_CTRL:
1079 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1080 previous_stage, &user_sgpr_idx);
1081 if (has_previous_stage)
1082 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1083 &user_sgpr_idx, 1);
1084 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1085 if (ctx->abi.view_index)
1086 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1087 break;
1088 case MESA_SHADER_TESS_EVAL:
1089 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1090 if (ctx->abi.view_index)
1091 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1092 break;
1093 case MESA_SHADER_GEOMETRY:
1094 if (has_previous_stage) {
1095 if (previous_stage == MESA_SHADER_VERTEX)
1096 set_vs_specific_input_locs(ctx, stage,
1097 has_previous_stage,
1098 previous_stage,
1099 &user_sgpr_idx);
1100 else
1101 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1102 &user_sgpr_idx, 1);
1103 }
1104 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1105 &user_sgpr_idx, 2);
1106 if (ctx->abi.view_index)
1107 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1108 break;
1109 case MESA_SHADER_FRAGMENT:
1110 if (ctx->shader_info->info.ps.needs_sample_positions) {
1111 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1112 &user_sgpr_idx, 1);
1113 }
1114 break;
1115 default:
1116 unreachable("Shader stage not implemented");
1117 }
1118
1119 if (stage == MESA_SHADER_TESS_CTRL ||
1120 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1121 /* GFX9 has the ESGS ring buffer in LDS. */
1122 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1123 ac_declare_lds_as_pointer(&ctx->ac);
1124 }
1125
1126 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1127 }
1128
1129 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1130 LLVMValueRef value, unsigned count)
1131 {
1132 unsigned num_components = ac_get_llvm_num_components(value);
1133 if (count == num_components)
1134 return value;
1135
1136 LLVMValueRef masks[] = {
1137 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1138 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1139
1140 if (count == 1)
1141 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1142 "");
1143
1144 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1145 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1146 }
1147
1148 static void
1149 build_store_values_extended(struct ac_llvm_context *ac,
1150 LLVMValueRef *values,
1151 unsigned value_count,
1152 unsigned value_stride,
1153 LLVMValueRef vec)
1154 {
1155 LLVMBuilderRef builder = ac->builder;
1156 unsigned i;
1157
1158 for (i = 0; i < value_count; i++) {
1159 LLVMValueRef ptr = values[i * value_stride];
1160 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1161 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1162 LLVMBuildStore(builder, value, ptr);
1163 }
1164 }
1165
1166 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1167 const nir_ssa_def *def)
1168 {
1169 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1170 if (def->num_components > 1) {
1171 type = LLVMVectorType(type, def->num_components);
1172 }
1173 return type;
1174 }
1175
1176 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1177 {
1178 assert(src.is_ssa);
1179 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1180 return (LLVMValueRef)entry->data;
1181 }
1182
1183 static LLVMValueRef
1184 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1185 {
1186 LLVMValueRef ptr = get_src(ctx, src);
1187 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1188 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1189
1190 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1191 LLVMPointerType(ctx->ac.i32, addr_space), "");
1192 }
1193
1194 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1195 const struct nir_block *b)
1196 {
1197 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1198 return (LLVMBasicBlockRef)entry->data;
1199 }
1200
1201 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1202 nir_alu_src src,
1203 unsigned num_components)
1204 {
1205 LLVMValueRef value = get_src(ctx, src.src);
1206 bool need_swizzle = false;
1207
1208 assert(value);
1209 LLVMTypeRef type = LLVMTypeOf(value);
1210 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1211 ? LLVMGetVectorSize(type)
1212 : 1;
1213
1214 for (unsigned i = 0; i < num_components; ++i) {
1215 assert(src.swizzle[i] < src_components);
1216 if (src.swizzle[i] != i)
1217 need_swizzle = true;
1218 }
1219
1220 if (need_swizzle || num_components != src_components) {
1221 LLVMValueRef masks[] = {
1222 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1223 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1224 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1225 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1226
1227 if (src_components > 1 && num_components == 1) {
1228 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1229 masks[0], "");
1230 } else if (src_components == 1 && num_components > 1) {
1231 LLVMValueRef values[] = {value, value, value, value};
1232 value = ac_build_gather_values(&ctx->ac, values, num_components);
1233 } else {
1234 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1235 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1236 swizzle, "");
1237 }
1238 }
1239 assert(!src.negate);
1240 assert(!src.abs);
1241 return value;
1242 }
1243
1244 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1245 LLVMIntPredicate pred, LLVMValueRef src0,
1246 LLVMValueRef src1)
1247 {
1248 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1249 return LLVMBuildSelect(ctx->builder, result,
1250 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1251 ctx->i32_0, "");
1252 }
1253
1254 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1255 LLVMRealPredicate pred, LLVMValueRef src0,
1256 LLVMValueRef src1)
1257 {
1258 LLVMValueRef result;
1259 src0 = ac_to_float(ctx, src0);
1260 src1 = ac_to_float(ctx, src1);
1261 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1262 return LLVMBuildSelect(ctx->builder, result,
1263 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1264 ctx->i32_0, "");
1265 }
1266
1267 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1268 const char *intrin,
1269 LLVMTypeRef result_type,
1270 LLVMValueRef src0)
1271 {
1272 char name[64];
1273 LLVMValueRef params[] = {
1274 ac_to_float(ctx, src0),
1275 };
1276
1277 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1278 ac_get_elem_bits(ctx, result_type));
1279 assert(length < sizeof(name));
1280 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1281 }
1282
1283 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1284 const char *intrin,
1285 LLVMTypeRef result_type,
1286 LLVMValueRef src0, LLVMValueRef src1)
1287 {
1288 char name[64];
1289 LLVMValueRef params[] = {
1290 ac_to_float(ctx, src0),
1291 ac_to_float(ctx, src1),
1292 };
1293
1294 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1295 ac_get_elem_bits(ctx, result_type));
1296 assert(length < sizeof(name));
1297 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1298 }
1299
1300 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1301 const char *intrin,
1302 LLVMTypeRef result_type,
1303 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1304 {
1305 char name[64];
1306 LLVMValueRef params[] = {
1307 ac_to_float(ctx, src0),
1308 ac_to_float(ctx, src1),
1309 ac_to_float(ctx, src2),
1310 };
1311
1312 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1313 ac_get_elem_bits(ctx, result_type));
1314 assert(length < sizeof(name));
1315 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1316 }
1317
1318 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1319 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1320 {
1321 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1322 ctx->i32_0, "");
1323 return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
1324 ac_to_integer(ctx, src2), "");
1325 }
1326
1327 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1328 LLVMIntPredicate pred,
1329 LLVMValueRef src0, LLVMValueRef src1)
1330 {
1331 return LLVMBuildSelect(ctx->builder,
1332 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1333 src0,
1334 src1, "");
1335
1336 }
1337 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1338 LLVMValueRef src0)
1339 {
1340 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1341 LLVMBuildNeg(ctx->builder, src0, ""));
1342 }
1343
1344 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1345 LLVMValueRef src0,
1346 unsigned bitsize)
1347 {
1348 LLVMValueRef cmp, val, zero, one;
1349 LLVMTypeRef type;
1350
1351 if (bitsize == 32) {
1352 type = ctx->f32;
1353 zero = ctx->f32_0;
1354 one = ctx->f32_1;
1355 } else {
1356 type = ctx->f64;
1357 zero = ctx->f64_0;
1358 one = ctx->f64_1;
1359 }
1360
1361 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1362 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1363 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1364 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1365 return val;
1366 }
1367
1368 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1369 LLVMValueRef src0, unsigned bitsize)
1370 {
1371 LLVMValueRef cmp, val, zero, one;
1372 LLVMTypeRef type;
1373
1374 if (bitsize == 32) {
1375 type = ctx->i32;
1376 zero = ctx->i32_0;
1377 one = ctx->i32_1;
1378 } else {
1379 type = ctx->i64;
1380 zero = ctx->i64_0;
1381 one = ctx->i64_1;
1382 }
1383
1384 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1385 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1386 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1387 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1388 return val;
1389 }
1390
1391 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1392 LLVMValueRef src0, unsigned bitsize)
1393 {
1394 LLVMTypeRef type;
1395 char *intr;
1396
1397 if (bitsize == 32) {
1398 intr = "llvm.floor.f32";
1399 type = ctx->f32;
1400 } else {
1401 intr = "llvm.floor.f64";
1402 type = ctx->f64;
1403 }
1404
1405 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1406 LLVMValueRef params[] = {
1407 fsrc0,
1408 };
1409 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1410 AC_FUNC_ATTR_READNONE);
1411 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1412 }
1413
1414 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1415 const char *intrin,
1416 LLVMValueRef src0, LLVMValueRef src1)
1417 {
1418 LLVMTypeRef ret_type;
1419 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1420 LLVMValueRef res;
1421 LLVMValueRef params[] = { src0, src1 };
1422 ret_type = LLVMStructTypeInContext(ctx->context, types,
1423 2, true);
1424
1425 res = ac_build_intrinsic(ctx, intrin, ret_type,
1426 params, 2, AC_FUNC_ATTR_READNONE);
1427
1428 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1429 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1430 return res;
1431 }
1432
1433 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1434 LLVMValueRef src0)
1435 {
1436 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1437 }
1438
1439 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1440 LLVMValueRef src0)
1441 {
1442 src0 = ac_to_float(ctx, src0);
1443 return LLVMBuildSExt(ctx->builder,
1444 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1445 ctx->i32, "");
1446 }
1447
1448 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1449 LLVMValueRef src0,
1450 unsigned bitsize)
1451 {
1452 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1453
1454 if (bitsize == 32)
1455 return result;
1456
1457 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1458 }
1459
1460 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1461 LLVMValueRef src0)
1462 {
1463 return LLVMBuildSExt(ctx->builder,
1464 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1465 ctx->i32, "");
1466 }
1467
1468 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1469 LLVMValueRef src0)
1470 {
1471 LLVMValueRef result;
1472 LLVMValueRef cond = NULL;
1473
1474 src0 = ac_to_float(ctx, src0);
1475 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1476
1477 if (ctx->chip_class >= VI) {
1478 LLVMValueRef args[2];
1479 /* Check if the result is a denormal - and flush to 0 if so. */
1480 args[0] = result;
1481 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1482 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1483 }
1484
1485 /* need to convert back up to f32 */
1486 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1487
1488 if (ctx->chip_class >= VI)
1489 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1490 else {
1491 /* for SI/CIK */
1492 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1493 * so compare the result and flush to 0 if it's smaller.
1494 */
1495 LLVMValueRef temp, cond2;
1496 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1497 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1498 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1499 temp, "");
1500 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1501 temp, ctx->f32_0, "");
1502 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1503 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1504 }
1505 return result;
1506 }
1507
1508 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1509 LLVMValueRef src0, LLVMValueRef src1)
1510 {
1511 LLVMValueRef dst64, result;
1512 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1513 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1514
1515 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1516 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1517 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1518 return result;
1519 }
1520
1521 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1522 LLVMValueRef src0, LLVMValueRef src1)
1523 {
1524 LLVMValueRef dst64, result;
1525 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1526 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1527
1528 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1529 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1530 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1531 return result;
1532 }
1533
1534 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1535 bool is_signed,
1536 const LLVMValueRef srcs[3])
1537 {
1538 LLVMValueRef result;
1539 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1540
1541 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1542 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1543 return result;
1544 }
1545
1546 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1547 LLVMValueRef src0, LLVMValueRef src1,
1548 LLVMValueRef src2, LLVMValueRef src3)
1549 {
1550 LLVMValueRef bfi_args[3], result;
1551
1552 bfi_args[0] = LLVMBuildShl(ctx->builder,
1553 LLVMBuildSub(ctx->builder,
1554 LLVMBuildShl(ctx->builder,
1555 ctx->i32_1,
1556 src3, ""),
1557 ctx->i32_1, ""),
1558 src2, "");
1559 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1560 bfi_args[2] = src0;
1561
1562 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1563
1564 /* Calculate:
1565 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1566 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1567 */
1568 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1569 LLVMBuildAnd(ctx->builder, bfi_args[0],
1570 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1571
1572 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1573 return result;
1574 }
1575
1576 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1577 LLVMValueRef src0)
1578 {
1579 LLVMValueRef comp[2];
1580
1581 src0 = ac_to_float(ctx, src0);
1582 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1583 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1584
1585 return ac_build_cvt_pkrtz_f16(ctx, comp);
1586 }
1587
1588 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1589 LLVMValueRef src0)
1590 {
1591 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1592 LLVMValueRef temps[2], result, val;
1593 int i;
1594
1595 for (i = 0; i < 2; i++) {
1596 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1597 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1598 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1599 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1600 }
1601
1602 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1603 ctx->i32_0, "");
1604 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1605 ctx->i32_1, "");
1606 return result;
1607 }
1608
1609 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1610 nir_op op,
1611 LLVMValueRef src0)
1612 {
1613 unsigned mask;
1614 int idx;
1615 LLVMValueRef result;
1616
1617 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1618 mask = AC_TID_MASK_LEFT;
1619 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1620 mask = AC_TID_MASK_TOP;
1621 else
1622 mask = AC_TID_MASK_TOP_LEFT;
1623
1624 /* for DDX we want to next X pixel, DDY next Y pixel. */
1625 if (op == nir_op_fddx_fine ||
1626 op == nir_op_fddx_coarse ||
1627 op == nir_op_fddx)
1628 idx = 1;
1629 else
1630 idx = 2;
1631
1632 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1633 return result;
1634 }
1635
1636 /*
1637 * this takes an I,J coordinate pair,
1638 * and works out the X and Y derivatives.
1639 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1640 */
1641 static LLVMValueRef emit_ddxy_interp(
1642 struct ac_nir_context *ctx,
1643 LLVMValueRef interp_ij)
1644 {
1645 LLVMValueRef result[4], a;
1646 unsigned i;
1647
1648 for (i = 0; i < 2; i++) {
1649 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1650 LLVMConstInt(ctx->ac.i32, i, false), "");
1651 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1652 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1653 }
1654 return ac_build_gather_values(&ctx->ac, result, 4);
1655 }
1656
1657 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1658 {
1659 LLVMValueRef src[4], result = NULL;
1660 unsigned num_components = instr->dest.dest.ssa.num_components;
1661 unsigned src_components;
1662 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1663
1664 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1665 switch (instr->op) {
1666 case nir_op_vec2:
1667 case nir_op_vec3:
1668 case nir_op_vec4:
1669 src_components = 1;
1670 break;
1671 case nir_op_pack_half_2x16:
1672 src_components = 2;
1673 break;
1674 case nir_op_unpack_half_2x16:
1675 src_components = 1;
1676 break;
1677 default:
1678 src_components = num_components;
1679 break;
1680 }
1681 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1682 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1683
1684 switch (instr->op) {
1685 case nir_op_fmov:
1686 case nir_op_imov:
1687 result = src[0];
1688 break;
1689 case nir_op_fneg:
1690 src[0] = ac_to_float(&ctx->ac, src[0]);
1691 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1692 break;
1693 case nir_op_ineg:
1694 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1695 break;
1696 case nir_op_inot:
1697 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1698 break;
1699 case nir_op_iadd:
1700 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1701 break;
1702 case nir_op_fadd:
1703 src[0] = ac_to_float(&ctx->ac, src[0]);
1704 src[1] = ac_to_float(&ctx->ac, src[1]);
1705 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1706 break;
1707 case nir_op_fsub:
1708 src[0] = ac_to_float(&ctx->ac, src[0]);
1709 src[1] = ac_to_float(&ctx->ac, src[1]);
1710 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1711 break;
1712 case nir_op_isub:
1713 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1714 break;
1715 case nir_op_imul:
1716 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1717 break;
1718 case nir_op_imod:
1719 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1720 break;
1721 case nir_op_umod:
1722 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1723 break;
1724 case nir_op_fmod:
1725 src[0] = ac_to_float(&ctx->ac, src[0]);
1726 src[1] = ac_to_float(&ctx->ac, src[1]);
1727 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1728 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1729 ac_to_float_type(&ctx->ac, def_type), result);
1730 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1731 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1732 break;
1733 case nir_op_frem:
1734 src[0] = ac_to_float(&ctx->ac, src[0]);
1735 src[1] = ac_to_float(&ctx->ac, src[1]);
1736 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1737 break;
1738 case nir_op_irem:
1739 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1740 break;
1741 case nir_op_idiv:
1742 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1743 break;
1744 case nir_op_udiv:
1745 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1746 break;
1747 case nir_op_fmul:
1748 src[0] = ac_to_float(&ctx->ac, src[0]);
1749 src[1] = ac_to_float(&ctx->ac, src[1]);
1750 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1751 break;
1752 case nir_op_frcp:
1753 src[0] = ac_to_float(&ctx->ac, src[0]);
1754 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1755 src[0]);
1756 break;
1757 case nir_op_iand:
1758 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1759 break;
1760 case nir_op_ior:
1761 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1762 break;
1763 case nir_op_ixor:
1764 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1765 break;
1766 case nir_op_ishl:
1767 result = LLVMBuildShl(ctx->ac.builder, src[0],
1768 LLVMBuildZExt(ctx->ac.builder, src[1],
1769 LLVMTypeOf(src[0]), ""),
1770 "");
1771 break;
1772 case nir_op_ishr:
1773 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1774 LLVMBuildZExt(ctx->ac.builder, src[1],
1775 LLVMTypeOf(src[0]), ""),
1776 "");
1777 break;
1778 case nir_op_ushr:
1779 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1780 LLVMBuildZExt(ctx->ac.builder, src[1],
1781 LLVMTypeOf(src[0]), ""),
1782 "");
1783 break;
1784 case nir_op_ilt:
1785 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1786 break;
1787 case nir_op_ine:
1788 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1789 break;
1790 case nir_op_ieq:
1791 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1792 break;
1793 case nir_op_ige:
1794 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1795 break;
1796 case nir_op_ult:
1797 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1798 break;
1799 case nir_op_uge:
1800 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1801 break;
1802 case nir_op_feq:
1803 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1804 break;
1805 case nir_op_fne:
1806 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1807 break;
1808 case nir_op_flt:
1809 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1810 break;
1811 case nir_op_fge:
1812 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1813 break;
1814 case nir_op_fabs:
1815 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1816 ac_to_float_type(&ctx->ac, def_type), src[0]);
1817 break;
1818 case nir_op_iabs:
1819 result = emit_iabs(&ctx->ac, src[0]);
1820 break;
1821 case nir_op_imax:
1822 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1823 break;
1824 case nir_op_imin:
1825 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1826 break;
1827 case nir_op_umax:
1828 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1829 break;
1830 case nir_op_umin:
1831 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1832 break;
1833 case nir_op_isign:
1834 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1835 break;
1836 case nir_op_fsign:
1837 src[0] = ac_to_float(&ctx->ac, src[0]);
1838 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1839 break;
1840 case nir_op_ffloor:
1841 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1842 ac_to_float_type(&ctx->ac, def_type), src[0]);
1843 break;
1844 case nir_op_ftrunc:
1845 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1846 ac_to_float_type(&ctx->ac, def_type), src[0]);
1847 break;
1848 case nir_op_fceil:
1849 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1850 ac_to_float_type(&ctx->ac, def_type), src[0]);
1851 break;
1852 case nir_op_fround_even:
1853 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1854 ac_to_float_type(&ctx->ac, def_type),src[0]);
1855 break;
1856 case nir_op_ffract:
1857 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1858 break;
1859 case nir_op_fsin:
1860 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1861 ac_to_float_type(&ctx->ac, def_type), src[0]);
1862 break;
1863 case nir_op_fcos:
1864 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1865 ac_to_float_type(&ctx->ac, def_type), src[0]);
1866 break;
1867 case nir_op_fsqrt:
1868 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1869 ac_to_float_type(&ctx->ac, def_type), src[0]);
1870 break;
1871 case nir_op_fexp2:
1872 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1873 ac_to_float_type(&ctx->ac, def_type), src[0]);
1874 break;
1875 case nir_op_flog2:
1876 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1877 ac_to_float_type(&ctx->ac, def_type), src[0]);
1878 break;
1879 case nir_op_frsq:
1880 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1881 ac_to_float_type(&ctx->ac, def_type), src[0]);
1882 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1883 result);
1884 break;
1885 case nir_op_fpow:
1886 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1887 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1888 break;
1889 case nir_op_fmax:
1890 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1891 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1892 if (ctx->ac.chip_class < GFX9 &&
1893 instr->dest.dest.ssa.bit_size == 32) {
1894 /* Only pre-GFX9 chips do not flush denorms. */
1895 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1896 ac_to_float_type(&ctx->ac, def_type),
1897 result);
1898 }
1899 break;
1900 case nir_op_fmin:
1901 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1902 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1903 if (ctx->ac.chip_class < GFX9 &&
1904 instr->dest.dest.ssa.bit_size == 32) {
1905 /* Only pre-GFX9 chips do not flush denorms. */
1906 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1907 ac_to_float_type(&ctx->ac, def_type),
1908 result);
1909 }
1910 break;
1911 case nir_op_ffma:
1912 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1913 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1914 break;
1915 case nir_op_ibitfield_extract:
1916 result = emit_bitfield_extract(&ctx->ac, true, src);
1917 break;
1918 case nir_op_ubitfield_extract:
1919 result = emit_bitfield_extract(&ctx->ac, false, src);
1920 break;
1921 case nir_op_bitfield_insert:
1922 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1923 break;
1924 case nir_op_bitfield_reverse:
1925 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1926 break;
1927 case nir_op_bit_count:
1928 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1929 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1930 else {
1931 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1932 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1933 }
1934 break;
1935 case nir_op_vec2:
1936 case nir_op_vec3:
1937 case nir_op_vec4:
1938 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1939 src[i] = ac_to_integer(&ctx->ac, src[i]);
1940 result = ac_build_gather_values(&ctx->ac, src, num_components);
1941 break;
1942 case nir_op_f2i32:
1943 case nir_op_f2i64:
1944 src[0] = ac_to_float(&ctx->ac, src[0]);
1945 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1946 break;
1947 case nir_op_f2u32:
1948 case nir_op_f2u64:
1949 src[0] = ac_to_float(&ctx->ac, src[0]);
1950 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1951 break;
1952 case nir_op_i2f32:
1953 case nir_op_i2f64:
1954 src[0] = ac_to_integer(&ctx->ac, src[0]);
1955 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1956 break;
1957 case nir_op_u2f32:
1958 case nir_op_u2f64:
1959 src[0] = ac_to_integer(&ctx->ac, src[0]);
1960 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1961 break;
1962 case nir_op_f2f64:
1963 src[0] = ac_to_float(&ctx->ac, src[0]);
1964 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1965 break;
1966 case nir_op_f2f32:
1967 src[0] = ac_to_float(&ctx->ac, src[0]);
1968 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1969 break;
1970 case nir_op_u2u32:
1971 case nir_op_u2u64:
1972 src[0] = ac_to_integer(&ctx->ac, src[0]);
1973 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1974 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1975 else
1976 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1977 break;
1978 case nir_op_i2i32:
1979 case nir_op_i2i64:
1980 src[0] = ac_to_integer(&ctx->ac, src[0]);
1981 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1982 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1983 else
1984 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1985 break;
1986 case nir_op_bcsel:
1987 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1988 break;
1989 case nir_op_find_lsb:
1990 src[0] = ac_to_integer(&ctx->ac, src[0]);
1991 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1992 break;
1993 case nir_op_ufind_msb:
1994 src[0] = ac_to_integer(&ctx->ac, src[0]);
1995 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1996 break;
1997 case nir_op_ifind_msb:
1998 src[0] = ac_to_integer(&ctx->ac, src[0]);
1999 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
2000 break;
2001 case nir_op_uadd_carry:
2002 src[0] = ac_to_integer(&ctx->ac, src[0]);
2003 src[1] = ac_to_integer(&ctx->ac, src[1]);
2004 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
2005 break;
2006 case nir_op_usub_borrow:
2007 src[0] = ac_to_integer(&ctx->ac, src[0]);
2008 src[1] = ac_to_integer(&ctx->ac, src[1]);
2009 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2010 break;
2011 case nir_op_b2f:
2012 result = emit_b2f(&ctx->ac, src[0]);
2013 break;
2014 case nir_op_f2b:
2015 result = emit_f2b(&ctx->ac, src[0]);
2016 break;
2017 case nir_op_b2i:
2018 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2019 break;
2020 case nir_op_i2b:
2021 src[0] = ac_to_integer(&ctx->ac, src[0]);
2022 result = emit_i2b(&ctx->ac, src[0]);
2023 break;
2024 case nir_op_fquantize2f16:
2025 result = emit_f2f16(&ctx->ac, src[0]);
2026 break;
2027 case nir_op_umul_high:
2028 src[0] = ac_to_integer(&ctx->ac, src[0]);
2029 src[1] = ac_to_integer(&ctx->ac, src[1]);
2030 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2031 break;
2032 case nir_op_imul_high:
2033 src[0] = ac_to_integer(&ctx->ac, src[0]);
2034 src[1] = ac_to_integer(&ctx->ac, src[1]);
2035 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2036 break;
2037 case nir_op_pack_half_2x16:
2038 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2039 break;
2040 case nir_op_unpack_half_2x16:
2041 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2042 break;
2043 case nir_op_fddx:
2044 case nir_op_fddy:
2045 case nir_op_fddx_fine:
2046 case nir_op_fddy_fine:
2047 case nir_op_fddx_coarse:
2048 case nir_op_fddy_coarse:
2049 result = emit_ddxy(ctx, instr->op, src[0]);
2050 break;
2051
2052 case nir_op_unpack_64_2x32_split_x: {
2053 assert(ac_get_llvm_num_components(src[0]) == 1);
2054 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2055 ctx->ac.v2i32,
2056 "");
2057 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2058 ctx->ac.i32_0, "");
2059 break;
2060 }
2061
2062 case nir_op_unpack_64_2x32_split_y: {
2063 assert(ac_get_llvm_num_components(src[0]) == 1);
2064 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2065 ctx->ac.v2i32,
2066 "");
2067 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2068 ctx->ac.i32_1, "");
2069 break;
2070 }
2071
2072 case nir_op_pack_64_2x32_split: {
2073 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2074 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2075 src[0], ctx->ac.i32_0, "");
2076 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2077 src[1], ctx->ac.i32_1, "");
2078 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2079 break;
2080 }
2081
2082 default:
2083 fprintf(stderr, "Unknown NIR alu instr: ");
2084 nir_print_instr(&instr->instr, stderr);
2085 fprintf(stderr, "\n");
2086 abort();
2087 }
2088
2089 if (result) {
2090 assert(instr->dest.dest.is_ssa);
2091 result = ac_to_integer(&ctx->ac, result);
2092 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2093 result);
2094 }
2095 }
2096
2097 static void visit_load_const(struct ac_nir_context *ctx,
2098 const nir_load_const_instr *instr)
2099 {
2100 LLVMValueRef values[4], value = NULL;
2101 LLVMTypeRef element_type =
2102 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2103
2104 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2105 switch (instr->def.bit_size) {
2106 case 32:
2107 values[i] = LLVMConstInt(element_type,
2108 instr->value.u32[i], false);
2109 break;
2110 case 64:
2111 values[i] = LLVMConstInt(element_type,
2112 instr->value.u64[i], false);
2113 break;
2114 default:
2115 fprintf(stderr,
2116 "unsupported nir load_const bit_size: %d\n",
2117 instr->def.bit_size);
2118 abort();
2119 }
2120 }
2121 if (instr->def.num_components > 1) {
2122 value = LLVMConstVector(values, instr->def.num_components);
2123 } else
2124 value = values[0];
2125
2126 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2127 }
2128
2129 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2130 LLVMTypeRef type)
2131 {
2132 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2133 return LLVMBuildBitCast(ctx->builder, ptr,
2134 LLVMPointerType(type, addr_space), "");
2135 }
2136
2137 static LLVMValueRef
2138 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2139 {
2140 LLVMValueRef size =
2141 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2142 LLVMConstInt(ctx->ac.i32, 2, false), "");
2143
2144 /* VI only */
2145 if (ctx->ac.chip_class == VI && in_elements) {
2146 /* On VI, the descriptor contains the size in bytes,
2147 * but TXQ must return the size in elements.
2148 * The stride is always non-zero for resources using TXQ.
2149 */
2150 LLVMValueRef stride =
2151 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2152 ctx->ac.i32_1, "");
2153 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2154 LLVMConstInt(ctx->ac.i32, 16, false), "");
2155 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2156 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2157
2158 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2159 }
2160 return size;
2161 }
2162
2163 /**
2164 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2165 * intrinsic names).
2166 */
2167 static void build_int_type_name(
2168 LLVMTypeRef type,
2169 char *buf, unsigned bufsize)
2170 {
2171 assert(bufsize >= 6);
2172
2173 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2174 snprintf(buf, bufsize, "v%ui32",
2175 LLVMGetVectorSize(type));
2176 else
2177 strcpy(buf, "i32");
2178 }
2179
2180 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2181 struct ac_image_args *args,
2182 const nir_tex_instr *instr)
2183 {
2184 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2185 LLVMValueRef coord = args->addr;
2186 LLVMValueRef half_texel[2];
2187 LLVMValueRef compare_cube_wa = NULL;
2188 LLVMValueRef result;
2189 int c;
2190 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2191
2192 //TODO Rect
2193 {
2194 struct ac_image_args txq_args = { 0 };
2195
2196 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2197 txq_args.opcode = ac_image_get_resinfo;
2198 txq_args.dmask = 0xf;
2199 txq_args.addr = ctx->i32_0;
2200 txq_args.resource = args->resource;
2201 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2202
2203 for (c = 0; c < 2; c++) {
2204 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2205 LLVMConstInt(ctx->i32, c, false), "");
2206 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2207 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2208 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2209 LLVMConstReal(ctx->f32, -0.5), "");
2210 }
2211 }
2212
2213 LLVMValueRef orig_coords = args->addr;
2214
2215 for (c = 0; c < 2; c++) {
2216 LLVMValueRef tmp;
2217 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2218 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2219 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2220 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2221 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2222 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2223 }
2224
2225
2226 /*
2227 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2228 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2229 * workaround by sampling using a scaled type and converting.
2230 * This is taken from amdgpu-pro shaders.
2231 */
2232 /* NOTE this produces some ugly code compared to amdgpu-pro,
2233 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2234 * and then reads them back. -pro generates two selects,
2235 * one s_cmp for the descriptor rewriting
2236 * one v_cmp for the coordinate and result changes.
2237 */
2238 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2239 LLVMValueRef tmp, tmp2;
2240
2241 /* workaround 8/8/8/8 uint/sint cube gather bug */
2242 /* first detect it then change to a scaled read and f2i */
2243 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2244 tmp2 = tmp;
2245
2246 /* extract the DATA_FORMAT */
2247 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2248 LLVMConstInt(ctx->i32, 6, false), false);
2249
2250 /* is the DATA_FORMAT == 8_8_8_8 */
2251 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2252
2253 if (stype == GLSL_TYPE_UINT)
2254 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2255 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2256 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2257 else
2258 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2259 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2260 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2261
2262 /* replace the NUM FORMAT in the descriptor */
2263 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2264 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2265
2266 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2267
2268 /* don't modify the coordinates for this case */
2269 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2270 }
2271 args->addr = coord;
2272 result = ac_build_image_opcode(ctx, args);
2273
2274 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2275 LLVMValueRef tmp, tmp2;
2276
2277 /* if the cube workaround is in place, f2i the result. */
2278 for (c = 0; c < 4; c++) {
2279 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2280 if (stype == GLSL_TYPE_UINT)
2281 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2282 else
2283 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2284 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2285 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2286 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2287 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2288 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2289 }
2290 }
2291 return result;
2292 }
2293
2294 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2295 const nir_tex_instr *instr,
2296 bool lod_is_zero,
2297 struct ac_image_args *args)
2298 {
2299 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2300 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2301
2302 return ac_build_buffer_load_format(&ctx->ac,
2303 args->resource,
2304 args->addr,
2305 ctx->ac.i32_0,
2306 util_last_bit(mask),
2307 false, true);
2308 }
2309
2310 args->opcode = ac_image_sample;
2311 args->compare = instr->is_shadow;
2312
2313 switch (instr->op) {
2314 case nir_texop_txf:
2315 case nir_texop_txf_ms:
2316 case nir_texop_samples_identical:
2317 args->opcode = lod_is_zero ||
2318 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2319 ac_image_load : ac_image_load_mip;
2320 args->compare = false;
2321 args->offset = false;
2322 break;
2323 case nir_texop_txb:
2324 args->bias = true;
2325 break;
2326 case nir_texop_txl:
2327 if (lod_is_zero)
2328 args->level_zero = true;
2329 else
2330 args->lod = true;
2331 break;
2332 case nir_texop_txs:
2333 case nir_texop_query_levels:
2334 args->opcode = ac_image_get_resinfo;
2335 break;
2336 case nir_texop_tex:
2337 if (ctx->stage != MESA_SHADER_FRAGMENT)
2338 args->level_zero = true;
2339 break;
2340 case nir_texop_txd:
2341 args->deriv = true;
2342 break;
2343 case nir_texop_tg4:
2344 args->opcode = ac_image_gather4;
2345 args->level_zero = true;
2346 break;
2347 case nir_texop_lod:
2348 args->opcode = ac_image_get_lod;
2349 args->compare = false;
2350 args->offset = false;
2351 break;
2352 default:
2353 break;
2354 }
2355
2356 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2357 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2358 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2359 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2360 }
2361 }
2362 return ac_build_image_opcode(&ctx->ac, args);
2363 }
2364
2365 static LLVMValueRef
2366 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2367 unsigned desc_set, unsigned binding)
2368 {
2369 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2370 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2371 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2372 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2373 unsigned base_offset = layout->binding[binding].offset;
2374 LLVMValueRef offset, stride;
2375
2376 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2377 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2378 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2379 layout->binding[binding].dynamic_offset_offset;
2380 desc_ptr = ctx->abi.push_constants;
2381 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2382 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2383 } else
2384 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2385
2386 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2387 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2388 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2389
2390 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2391 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2392 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2393
2394 return desc_ptr;
2395 }
2396
2397 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2398 nir_intrinsic_instr *instr)
2399 {
2400 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2401 LLVMValueRef index = get_src(ctx, instr->src[1]);
2402
2403 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2404 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2405 return result;
2406 }
2407
2408 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2409 nir_intrinsic_instr *instr)
2410 {
2411 LLVMValueRef ptr, addr;
2412
2413 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2414 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2415 get_src(ctx, instr->src[0]), "");
2416
2417 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2418 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2419
2420 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2421 }
2422
2423 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2424 const nir_intrinsic_instr *instr)
2425 {
2426 LLVMValueRef index = get_src(ctx, instr->src[0]);
2427
2428 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2429 }
2430
2431 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2432 {
2433 uint32_t new_mask = 0;
2434 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2435 if (mask & (1u << i))
2436 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2437 return new_mask;
2438 }
2439
2440 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2441 unsigned start, unsigned count)
2442 {
2443 LLVMTypeRef type = LLVMTypeOf(src);
2444
2445 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2446 assert(start == 0);
2447 assert(count == 1);
2448 return src;
2449 }
2450
2451 unsigned src_elements = LLVMGetVectorSize(type);
2452 assert(start < src_elements);
2453 assert(start + count <= src_elements);
2454
2455 if (start == 0 && count == src_elements)
2456 return src;
2457
2458 if (count == 1)
2459 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2460
2461 assert(count <= 8);
2462 LLVMValueRef indices[8];
2463 for (unsigned i = 0; i < count; ++i)
2464 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2465
2466 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2467 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2468 }
2469
2470 static void visit_store_ssbo(struct ac_nir_context *ctx,
2471 nir_intrinsic_instr *instr)
2472 {
2473 const char *store_name;
2474 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2475 LLVMTypeRef data_type = ctx->ac.f32;
2476 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2477 int components_32bit = elem_size_mult * instr->num_components;
2478 unsigned writemask = nir_intrinsic_write_mask(instr);
2479 LLVMValueRef base_data, base_offset;
2480 LLVMValueRef params[6];
2481
2482 params[1] = ctx->abi->load_ssbo(ctx->abi,
2483 get_src(ctx, instr->src[1]), true);
2484 params[2] = ctx->ac.i32_0; /* vindex */
2485 params[4] = ctx->ac.i1false; /* glc */
2486 params[5] = ctx->ac.i1false; /* slc */
2487
2488 if (components_32bit > 1)
2489 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2490
2491 writemask = widen_mask(writemask, elem_size_mult);
2492
2493 base_data = ac_to_float(&ctx->ac, src_data);
2494 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2495 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2496 data_type, "");
2497 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2498 while (writemask) {
2499 int start, count;
2500 LLVMValueRef data;
2501 LLVMValueRef offset;
2502
2503 u_bit_scan_consecutive_range(&writemask, &start, &count);
2504
2505 /* Due to an LLVM limitation, split 3-element writes
2506 * into a 2-element and a 1-element write. */
2507 if (count == 3) {
2508 writemask |= 1 << (start + 2);
2509 count = 2;
2510 }
2511
2512 if (count > 4) {
2513 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2514 count = 4;
2515 }
2516
2517 if (count == 4) {
2518 store_name = "llvm.amdgcn.buffer.store.v4f32";
2519 } else if (count == 2) {
2520 store_name = "llvm.amdgcn.buffer.store.v2f32";
2521
2522 } else {
2523 assert(count == 1);
2524 store_name = "llvm.amdgcn.buffer.store.f32";
2525 }
2526 data = extract_vector_range(&ctx->ac, base_data, start, count);
2527
2528 offset = base_offset;
2529 if (start != 0) {
2530 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2531 }
2532 params[0] = data;
2533 params[3] = offset;
2534 ac_build_intrinsic(&ctx->ac, store_name,
2535 ctx->ac.voidt, params, 6, 0);
2536 }
2537 }
2538
2539 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2540 const nir_intrinsic_instr *instr)
2541 {
2542 const char *name;
2543 LLVMValueRef params[6];
2544 int arg_count = 0;
2545
2546 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2547 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2548 }
2549 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2550 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2551 get_src(ctx, instr->src[0]),
2552 true);
2553 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2554 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2555 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2556
2557 switch (instr->intrinsic) {
2558 case nir_intrinsic_ssbo_atomic_add:
2559 name = "llvm.amdgcn.buffer.atomic.add";
2560 break;
2561 case nir_intrinsic_ssbo_atomic_imin:
2562 name = "llvm.amdgcn.buffer.atomic.smin";
2563 break;
2564 case nir_intrinsic_ssbo_atomic_umin:
2565 name = "llvm.amdgcn.buffer.atomic.umin";
2566 break;
2567 case nir_intrinsic_ssbo_atomic_imax:
2568 name = "llvm.amdgcn.buffer.atomic.smax";
2569 break;
2570 case nir_intrinsic_ssbo_atomic_umax:
2571 name = "llvm.amdgcn.buffer.atomic.umax";
2572 break;
2573 case nir_intrinsic_ssbo_atomic_and:
2574 name = "llvm.amdgcn.buffer.atomic.and";
2575 break;
2576 case nir_intrinsic_ssbo_atomic_or:
2577 name = "llvm.amdgcn.buffer.atomic.or";
2578 break;
2579 case nir_intrinsic_ssbo_atomic_xor:
2580 name = "llvm.amdgcn.buffer.atomic.xor";
2581 break;
2582 case nir_intrinsic_ssbo_atomic_exchange:
2583 name = "llvm.amdgcn.buffer.atomic.swap";
2584 break;
2585 case nir_intrinsic_ssbo_atomic_comp_swap:
2586 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2587 break;
2588 default:
2589 abort();
2590 }
2591
2592 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2593 }
2594
2595 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2596 const nir_intrinsic_instr *instr)
2597 {
2598 LLVMValueRef results[2];
2599 int load_components;
2600 int num_components = instr->num_components;
2601 if (instr->dest.ssa.bit_size == 64)
2602 num_components *= 2;
2603
2604 for (int i = 0; i < num_components; i += load_components) {
2605 load_components = MIN2(num_components - i, 4);
2606 const char *load_name;
2607 LLVMTypeRef data_type = ctx->ac.f32;
2608 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2609 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2610
2611 if (load_components == 3)
2612 data_type = LLVMVectorType(ctx->ac.f32, 4);
2613 else if (load_components > 1)
2614 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2615
2616 if (load_components >= 3)
2617 load_name = "llvm.amdgcn.buffer.load.v4f32";
2618 else if (load_components == 2)
2619 load_name = "llvm.amdgcn.buffer.load.v2f32";
2620 else if (load_components == 1)
2621 load_name = "llvm.amdgcn.buffer.load.f32";
2622 else
2623 unreachable("unhandled number of components");
2624
2625 LLVMValueRef params[] = {
2626 ctx->abi->load_ssbo(ctx->abi,
2627 get_src(ctx, instr->src[0]),
2628 false),
2629 ctx->ac.i32_0,
2630 offset,
2631 ctx->ac.i1false,
2632 ctx->ac.i1false,
2633 };
2634
2635 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2636 }
2637
2638 assume(results[0]);
2639 LLVMValueRef ret = results[0];
2640 if (num_components > 4 || num_components == 3) {
2641 LLVMValueRef masks[] = {
2642 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2643 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2644 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2645 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2646 };
2647
2648 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2649 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2650 results[num_components > 4 ? 1 : 0], swizzle, "");
2651 }
2652
2653 return LLVMBuildBitCast(ctx->ac.builder, ret,
2654 get_def_type(ctx, &instr->dest.ssa), "");
2655 }
2656
2657 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2658 const nir_intrinsic_instr *instr)
2659 {
2660 LLVMValueRef ret;
2661 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2662 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2663 int num_components = instr->num_components;
2664
2665 if (ctx->abi->load_ubo)
2666 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2667
2668 if (instr->dest.ssa.bit_size == 64)
2669 num_components *= 2;
2670
2671 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2672 NULL, 0, false, false, true, true);
2673 ret = trim_vector(&ctx->ac, ret, num_components);
2674 return LLVMBuildBitCast(ctx->ac.builder, ret,
2675 get_def_type(ctx, &instr->dest.ssa), "");
2676 }
2677
2678 static void
2679 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2680 bool vs_in, unsigned *vertex_index_out,
2681 LLVMValueRef *vertex_index_ref,
2682 unsigned *const_out, LLVMValueRef *indir_out)
2683 {
2684 unsigned const_offset = 0;
2685 nir_deref *tail = &deref->deref;
2686 LLVMValueRef offset = NULL;
2687
2688 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2689 tail = tail->child;
2690 nir_deref_array *deref_array = nir_deref_as_array(tail);
2691 if (vertex_index_out)
2692 *vertex_index_out = deref_array->base_offset;
2693
2694 if (vertex_index_ref) {
2695 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2696 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2697 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2698 }
2699 *vertex_index_ref = vtx;
2700 }
2701 }
2702
2703 if (deref->var->data.compact) {
2704 assert(tail->child->deref_type == nir_deref_type_array);
2705 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2706 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2707 /* We always lower indirect dereferences for "compact" array vars. */
2708 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2709
2710 const_offset = deref_array->base_offset;
2711 goto out;
2712 }
2713
2714 while (tail->child != NULL) {
2715 const struct glsl_type *parent_type = tail->type;
2716 tail = tail->child;
2717
2718 if (tail->deref_type == nir_deref_type_array) {
2719 nir_deref_array *deref_array = nir_deref_as_array(tail);
2720 LLVMValueRef index, stride, local_offset;
2721 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2722
2723 const_offset += size * deref_array->base_offset;
2724 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2725 continue;
2726
2727 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2728 index = get_src(ctx, deref_array->indirect);
2729 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2730 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2731
2732 if (offset)
2733 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2734 else
2735 offset = local_offset;
2736 } else if (tail->deref_type == nir_deref_type_struct) {
2737 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2738
2739 for (unsigned i = 0; i < deref_struct->index; i++) {
2740 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2741 const_offset += glsl_count_attribute_slots(ft, vs_in);
2742 }
2743 } else
2744 unreachable("unsupported deref type");
2745
2746 }
2747 out:
2748 if (const_offset && offset)
2749 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2750 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2751 "");
2752
2753 *const_out = const_offset;
2754 *indir_out = offset;
2755 }
2756
2757
2758 /* The offchip buffer layout for TCS->TES is
2759 *
2760 * - attribute 0 of patch 0 vertex 0
2761 * - attribute 0 of patch 0 vertex 1
2762 * - attribute 0 of patch 0 vertex 2
2763 * ...
2764 * - attribute 0 of patch 1 vertex 0
2765 * - attribute 0 of patch 1 vertex 1
2766 * ...
2767 * - attribute 1 of patch 0 vertex 0
2768 * - attribute 1 of patch 0 vertex 1
2769 * ...
2770 * - per patch attribute 0 of patch 0
2771 * - per patch attribute 0 of patch 1
2772 * ...
2773 *
2774 * Note that every attribute has 4 components.
2775 */
2776 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2777 LLVMValueRef vertex_index,
2778 LLVMValueRef param_index)
2779 {
2780 LLVMValueRef base_addr, vertices_per_patch, num_patches;
2781 LLVMValueRef param_stride, constant16;
2782 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2783
2784 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2785 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2786
2787 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2788 if (vertex_index) {
2789 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2790 vertices_per_patch, "");
2791
2792 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2793 vertex_index, "");
2794
2795 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2796 num_patches, "");
2797 } else {
2798 base_addr = rel_patch_id;
2799 param_stride = num_patches;
2800 }
2801
2802 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2803 LLVMBuildMul(ctx->ac.builder, param_index,
2804 param_stride, ""), "");
2805
2806 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2807
2808 if (!vertex_index) {
2809 LLVMValueRef patch_data_offset =
2810 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2811
2812 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2813 patch_data_offset, "");
2814 }
2815 return base_addr;
2816 }
2817
2818 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2819 unsigned param,
2820 unsigned const_index,
2821 bool is_compact,
2822 LLVMValueRef vertex_index,
2823 LLVMValueRef indir_index)
2824 {
2825 LLVMValueRef param_index;
2826
2827 if (indir_index)
2828 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2829 indir_index, "");
2830 else {
2831 if (const_index && !is_compact)
2832 param += const_index;
2833 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2834 }
2835 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2836 }
2837
2838 static void
2839 mark_tess_output(struct radv_shader_context *ctx,
2840 bool is_patch, uint32_t param)
2841
2842 {
2843 if (is_patch) {
2844 ctx->tess_patch_outputs_written |= (1ull << param);
2845 } else
2846 ctx->tess_outputs_written |= (1ull << param);
2847 }
2848
2849 static LLVMValueRef
2850 get_dw_address(struct radv_shader_context *ctx,
2851 LLVMValueRef dw_addr,
2852 unsigned param,
2853 unsigned const_index,
2854 bool compact_const_index,
2855 LLVMValueRef vertex_index,
2856 LLVMValueRef stride,
2857 LLVMValueRef indir_index)
2858
2859 {
2860
2861 if (vertex_index) {
2862 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2863 LLVMBuildMul(ctx->ac.builder,
2864 vertex_index,
2865 stride, ""), "");
2866 }
2867
2868 if (indir_index)
2869 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2870 LLVMBuildMul(ctx->ac.builder, indir_index,
2871 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2872 else if (const_index && !compact_const_index)
2873 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2874 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2875
2876 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2877 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2878
2879 if (const_index && compact_const_index)
2880 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2881 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2882 return dw_addr;
2883 }
2884
2885 static LLVMValueRef
2886 load_tcs_varyings(struct ac_shader_abi *abi,
2887 LLVMValueRef vertex_index,
2888 LLVMValueRef indir_index,
2889 unsigned const_index,
2890 unsigned location,
2891 unsigned driver_location,
2892 unsigned component,
2893 unsigned num_components,
2894 bool is_patch,
2895 bool is_compact,
2896 bool load_input)
2897 {
2898 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2899 LLVMValueRef dw_addr, stride;
2900 LLVMValueRef value[4], result;
2901 unsigned param = shader_io_get_unique_index(location);
2902
2903 if (load_input) {
2904 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2905 dw_addr = get_tcs_in_current_patch_offset(ctx);
2906 } else {
2907 if (!is_patch) {
2908 stride = get_tcs_out_vertex_stride(ctx);
2909 dw_addr = get_tcs_out_current_patch_offset(ctx);
2910 } else {
2911 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2912 stride = NULL;
2913 }
2914 }
2915
2916 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2917 indir_index);
2918
2919 for (unsigned i = 0; i < num_components + component; i++) {
2920 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2921 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2922 ctx->ac.i32_1, "");
2923 }
2924 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2925 return result;
2926 }
2927
2928 static void
2929 store_tcs_output(struct ac_shader_abi *abi,
2930 LLVMValueRef vertex_index,
2931 LLVMValueRef param_index,
2932 unsigned const_index,
2933 unsigned location,
2934 unsigned driver_location,
2935 LLVMValueRef src,
2936 unsigned component,
2937 bool is_patch,
2938 bool is_compact,
2939 unsigned writemask)
2940 {
2941 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2942 LLVMValueRef dw_addr;
2943 LLVMValueRef stride = NULL;
2944 LLVMValueRef buf_addr = NULL;
2945 unsigned param;
2946 bool store_lds = true;
2947
2948 if (is_patch) {
2949 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2950 store_lds = false;
2951 } else {
2952 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2953 store_lds = false;
2954 }
2955
2956 param = shader_io_get_unique_index(location);
2957 if (location == VARYING_SLOT_CLIP_DIST0 &&
2958 is_compact && const_index > 3) {
2959 const_index -= 3;
2960 param++;
2961 }
2962
2963 if (!is_patch) {
2964 stride = get_tcs_out_vertex_stride(ctx);
2965 dw_addr = get_tcs_out_current_patch_offset(ctx);
2966 } else {
2967 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2968 }
2969
2970 mark_tess_output(ctx, is_patch, param);
2971
2972 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2973 param_index);
2974 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2975 vertex_index, param_index);
2976
2977 bool is_tess_factor = false;
2978 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2979 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2980 is_tess_factor = true;
2981
2982 unsigned base = is_compact ? const_index : 0;
2983 for (unsigned chan = 0; chan < 8; chan++) {
2984 if (!(writemask & (1 << chan)))
2985 continue;
2986 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2987
2988 if (store_lds || is_tess_factor) {
2989 LLVMValueRef dw_addr_chan =
2990 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2991 LLVMConstInt(ctx->ac.i32, chan, false), "");
2992 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2993 }
2994
2995 if (!is_tess_factor && writemask != 0xF)
2996 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2997 buf_addr, ctx->oc_lds,
2998 4 * (base + chan), 1, 0, true, false);
2999 }
3000
3001 if (writemask == 0xF) {
3002 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
3003 buf_addr, ctx->oc_lds,
3004 (base * 4), 1, 0, true, false);
3005 }
3006 }
3007
3008 static LLVMValueRef
3009 load_tes_input(struct ac_shader_abi *abi,
3010 LLVMValueRef vertex_index,
3011 LLVMValueRef param_index,
3012 unsigned const_index,
3013 unsigned location,
3014 unsigned driver_location,
3015 unsigned component,
3016 unsigned num_components,
3017 bool is_patch,
3018 bool is_compact,
3019 bool load_input)
3020 {
3021 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3022 LLVMValueRef buf_addr;
3023 LLVMValueRef result;
3024 unsigned param = shader_io_get_unique_index(location);
3025
3026 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3027 const_index -= 3;
3028 param++;
3029 }
3030
3031 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3032 is_compact, vertex_index, param_index);
3033
3034 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3035 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3036
3037 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3038 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3039 result = trim_vector(&ctx->ac, result, num_components);
3040 return result;
3041 }
3042
3043 static LLVMValueRef
3044 load_gs_input(struct ac_shader_abi *abi,
3045 unsigned location,
3046 unsigned driver_location,
3047 unsigned component,
3048 unsigned num_components,
3049 unsigned vertex_index,
3050 unsigned const_index,
3051 LLVMTypeRef type)
3052 {
3053 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3054 LLVMValueRef vtx_offset;
3055 unsigned param, vtx_offset_param;
3056 LLVMValueRef value[4], result;
3057
3058 vtx_offset_param = vertex_index;
3059 assert(vtx_offset_param < 6);
3060 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3061 LLVMConstInt(ctx->ac.i32, 4, false), "");
3062
3063 param = shader_io_get_unique_index(location);
3064
3065 for (unsigned i = component; i < num_components + component; i++) {
3066 if (ctx->ac.chip_class >= GFX9) {
3067 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3068 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3069 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3070 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3071 } else {
3072 LLVMValueRef soffset =
3073 LLVMConstInt(ctx->ac.i32,
3074 (param * 4 + i + const_index) * 256,
3075 false);
3076
3077 value[i] = ac_build_buffer_load(&ctx->ac,
3078 ctx->esgs_ring, 1,
3079 ctx->ac.i32_0,
3080 vtx_offset, soffset,
3081 0, 1, 0, true, false);
3082
3083 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3084 type, "");
3085 }
3086 }
3087 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3088 result = ac_to_integer(&ctx->ac, result);
3089 return result;
3090 }
3091
3092 static LLVMValueRef
3093 build_gep_for_deref(struct ac_nir_context *ctx,
3094 nir_deref_var *deref)
3095 {
3096 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3097 assert(entry->data);
3098 LLVMValueRef val = entry->data;
3099 nir_deref *tail = deref->deref.child;
3100 while (tail != NULL) {
3101 LLVMValueRef offset;
3102 switch (tail->deref_type) {
3103 case nir_deref_type_array: {
3104 nir_deref_array *array = nir_deref_as_array(tail);
3105 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3106 if (array->deref_array_type ==
3107 nir_deref_array_type_indirect) {
3108 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3109 get_src(ctx,
3110 array->indirect),
3111 "");
3112 }
3113 break;
3114 }
3115 case nir_deref_type_struct: {
3116 nir_deref_struct *deref_struct =
3117 nir_deref_as_struct(tail);
3118 offset = LLVMConstInt(ctx->ac.i32,
3119 deref_struct->index, 0);
3120 break;
3121 }
3122 default:
3123 unreachable("bad deref type");
3124 }
3125 val = ac_build_gep0(&ctx->ac, val, offset);
3126 tail = tail->child;
3127 }
3128 return val;
3129 }
3130
3131 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3132 nir_intrinsic_instr *instr,
3133 bool load_inputs)
3134 {
3135 LLVMValueRef result;
3136 LLVMValueRef vertex_index = NULL;
3137 LLVMValueRef indir_index = NULL;
3138 unsigned const_index = 0;
3139 unsigned location = instr->variables[0]->var->data.location;
3140 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3141 const bool is_patch = instr->variables[0]->var->data.patch;
3142 const bool is_compact = instr->variables[0]->var->data.compact;
3143
3144 get_deref_offset(ctx, instr->variables[0],
3145 false, NULL, is_patch ? NULL : &vertex_index,
3146 &const_index, &indir_index);
3147
3148 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3149 const_index, location, driver_location,
3150 instr->variables[0]->var->data.location_frac,
3151 instr->num_components,
3152 is_patch, is_compact, load_inputs);
3153 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3154 }
3155
3156 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3157 nir_intrinsic_instr *instr)
3158 {
3159 LLVMValueRef values[8];
3160 int idx = instr->variables[0]->var->data.driver_location;
3161 int ve = instr->dest.ssa.num_components;
3162 unsigned comp = instr->variables[0]->var->data.location_frac;
3163 LLVMValueRef indir_index;
3164 LLVMValueRef ret;
3165 unsigned const_index;
3166 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3167 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3168 instr->variables[0]->var->data.mode == nir_var_shader_in;
3169 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3170 &const_index, &indir_index);
3171
3172 if (instr->dest.ssa.bit_size == 64)
3173 ve *= 2;
3174
3175 switch (instr->variables[0]->var->data.mode) {
3176 case nir_var_shader_in:
3177 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3178 ctx->stage == MESA_SHADER_TESS_EVAL) {
3179 return load_tess_varyings(ctx, instr, true);
3180 }
3181
3182 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3183 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3184 LLVMValueRef indir_index;
3185 unsigned const_index, vertex_index;
3186 get_deref_offset(ctx, instr->variables[0],
3187 false, &vertex_index, NULL,
3188 &const_index, &indir_index);
3189
3190 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3191 instr->variables[0]->var->data.driver_location,
3192 instr->variables[0]->var->data.location_frac, ve,
3193 vertex_index, const_index, type);
3194 }
3195
3196 for (unsigned chan = comp; chan < ve + comp; chan++) {
3197 if (indir_index) {
3198 unsigned count = glsl_count_attribute_slots(
3199 instr->variables[0]->var->type,
3200 ctx->stage == MESA_SHADER_VERTEX);
3201 count -= chan / 4;
3202 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3203 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3204 stride, false, true);
3205
3206 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3207 tmp_vec,
3208 indir_index, "");
3209 } else
3210 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3211 }
3212 break;
3213 case nir_var_local:
3214 for (unsigned chan = 0; chan < ve; chan++) {
3215 if (indir_index) {
3216 unsigned count = glsl_count_attribute_slots(
3217 instr->variables[0]->var->type, false);
3218 count -= chan / 4;
3219 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3220 &ctx->ac, ctx->locals + idx + chan, count,
3221 stride, true, true);
3222
3223 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3224 tmp_vec,
3225 indir_index, "");
3226 } else {
3227 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3228 }
3229 }
3230 break;
3231 case nir_var_shared: {
3232 LLVMValueRef address = build_gep_for_deref(ctx,
3233 instr->variables[0]);
3234 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3235 return LLVMBuildBitCast(ctx->ac.builder, val,
3236 get_def_type(ctx, &instr->dest.ssa),
3237 "");
3238 }
3239 case nir_var_shader_out:
3240 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3241 return load_tess_varyings(ctx, instr, false);
3242 }
3243
3244 for (unsigned chan = comp; chan < ve + comp; chan++) {
3245 if (indir_index) {
3246 unsigned count = glsl_count_attribute_slots(
3247 instr->variables[0]->var->type, false);
3248 count -= chan / 4;
3249 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3250 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3251 stride, true, true);
3252
3253 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3254 tmp_vec,
3255 indir_index, "");
3256 } else {
3257 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3258 ctx->abi->outputs[idx + chan + const_index * stride],
3259 "");
3260 }
3261 }
3262 break;
3263 default:
3264 unreachable("unhandle variable mode");
3265 }
3266 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3267 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3268 }
3269
3270 static void
3271 visit_store_var(struct ac_nir_context *ctx,
3272 nir_intrinsic_instr *instr)
3273 {
3274 LLVMValueRef temp_ptr, value;
3275 int idx = instr->variables[0]->var->data.driver_location;
3276 unsigned comp = instr->variables[0]->var->data.location_frac;
3277 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3278 int writemask = instr->const_index[0] << comp;
3279 LLVMValueRef indir_index;
3280 unsigned const_index;
3281 get_deref_offset(ctx, instr->variables[0], false,
3282 NULL, NULL, &const_index, &indir_index);
3283
3284 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3285
3286 src = LLVMBuildBitCast(ctx->ac.builder, src,
3287 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3288 "");
3289
3290 writemask = widen_mask(writemask, 2);
3291 }
3292
3293 switch (instr->variables[0]->var->data.mode) {
3294 case nir_var_shader_out:
3295
3296 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3297 LLVMValueRef vertex_index = NULL;
3298 LLVMValueRef indir_index = NULL;
3299 unsigned const_index = 0;
3300 const unsigned location = instr->variables[0]->var->data.location;
3301 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3302 const unsigned comp = instr->variables[0]->var->data.location_frac;
3303 const bool is_patch = instr->variables[0]->var->data.patch;
3304 const bool is_compact = instr->variables[0]->var->data.compact;
3305
3306 get_deref_offset(ctx, instr->variables[0],
3307 false, NULL, is_patch ? NULL : &vertex_index,
3308 &const_index, &indir_index);
3309
3310 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3311 const_index, location, driver_location,
3312 src, comp, is_patch, is_compact, writemask);
3313 return;
3314 }
3315
3316 for (unsigned chan = 0; chan < 8; chan++) {
3317 int stride = 4;
3318 if (!(writemask & (1 << chan)))
3319 continue;
3320
3321 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3322
3323 if (instr->variables[0]->var->data.compact)
3324 stride = 1;
3325 if (indir_index) {
3326 unsigned count = glsl_count_attribute_slots(
3327 instr->variables[0]->var->type, false);
3328 count -= chan / 4;
3329 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3330 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3331 stride, true, true);
3332
3333 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3334 value, indir_index, "");
3335 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3336 count, stride, tmp_vec);
3337
3338 } else {
3339 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3340
3341 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3342 }
3343 }
3344 break;
3345 case nir_var_local:
3346 for (unsigned chan = 0; chan < 8; chan++) {
3347 if (!(writemask & (1 << chan)))
3348 continue;
3349
3350 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3351 if (indir_index) {
3352 unsigned count = glsl_count_attribute_slots(
3353 instr->variables[0]->var->type, false);
3354 count -= chan / 4;
3355 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3356 &ctx->ac, ctx->locals + idx + chan, count,
3357 4, true, true);
3358
3359 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3360 value, indir_index, "");
3361 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3362 count, 4, tmp_vec);
3363 } else {
3364 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3365
3366 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3367 }
3368 }
3369 break;
3370 case nir_var_shared: {
3371 int writemask = instr->const_index[0];
3372 LLVMValueRef address = build_gep_for_deref(ctx,
3373 instr->variables[0]);
3374 LLVMValueRef val = get_src(ctx, instr->src[0]);
3375 unsigned components =
3376 glsl_get_vector_elements(
3377 nir_deref_tail(&instr->variables[0]->deref)->type);
3378 if (writemask == (1 << components) - 1) {
3379 val = LLVMBuildBitCast(
3380 ctx->ac.builder, val,
3381 LLVMGetElementType(LLVMTypeOf(address)), "");
3382 LLVMBuildStore(ctx->ac.builder, val, address);
3383 } else {
3384 for (unsigned chan = 0; chan < 4; chan++) {
3385 if (!(writemask & (1 << chan)))
3386 continue;
3387 LLVMValueRef ptr =
3388 LLVMBuildStructGEP(ctx->ac.builder,
3389 address, chan, "");
3390 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3391 chan);
3392 src = LLVMBuildBitCast(
3393 ctx->ac.builder, src,
3394 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3395 LLVMBuildStore(ctx->ac.builder, src, ptr);
3396 }
3397 }
3398 break;
3399 }
3400 default:
3401 break;
3402 }
3403 }
3404
3405 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3406 {
3407 switch (dim) {
3408 case GLSL_SAMPLER_DIM_BUF:
3409 return 1;
3410 case GLSL_SAMPLER_DIM_1D:
3411 return array ? 2 : 1;
3412 case GLSL_SAMPLER_DIM_2D:
3413 return array ? 3 : 2;
3414 case GLSL_SAMPLER_DIM_MS:
3415 return array ? 4 : 3;
3416 case GLSL_SAMPLER_DIM_3D:
3417 case GLSL_SAMPLER_DIM_CUBE:
3418 return 3;
3419 case GLSL_SAMPLER_DIM_RECT:
3420 case GLSL_SAMPLER_DIM_SUBPASS:
3421 return 2;
3422 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3423 return 3;
3424 default:
3425 break;
3426 }
3427 return 0;
3428 }
3429
3430
3431
3432 /* Adjust the sample index according to FMASK.
3433 *
3434 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3435 * which is the identity mapping. Each nibble says which physical sample
3436 * should be fetched to get that sample.
3437 *
3438 * For example, 0x11111100 means there are only 2 samples stored and
3439 * the second sample covers 3/4 of the pixel. When reading samples 0
3440 * and 1, return physical sample 0 (determined by the first two 0s
3441 * in FMASK), otherwise return physical sample 1.
3442 *
3443 * The sample index should be adjusted as follows:
3444 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3445 */
3446 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3447 LLVMValueRef coord_x, LLVMValueRef coord_y,
3448 LLVMValueRef coord_z,
3449 LLVMValueRef sample_index,
3450 LLVMValueRef fmask_desc_ptr)
3451 {
3452 LLVMValueRef fmask_load_address[4];
3453 LLVMValueRef res;
3454
3455 fmask_load_address[0] = coord_x;
3456 fmask_load_address[1] = coord_y;
3457 if (coord_z) {
3458 fmask_load_address[2] = coord_z;
3459 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3460 }
3461
3462 struct ac_image_args args = {0};
3463
3464 args.opcode = ac_image_load;
3465 args.da = coord_z ? true : false;
3466 args.resource = fmask_desc_ptr;
3467 args.dmask = 0xf;
3468 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3469
3470 res = ac_build_image_opcode(ctx, &args);
3471
3472 res = ac_to_integer(ctx, res);
3473 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3474 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3475
3476 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3477 res,
3478 ctx->i32_0, "");
3479
3480 LLVMValueRef sample_index4 =
3481 LLVMBuildMul(ctx->builder, sample_index, four, "");
3482 LLVMValueRef shifted_fmask =
3483 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3484 LLVMValueRef final_sample =
3485 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3486
3487 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3488 * resource descriptor is 0 (invalid),
3489 */
3490 LLVMValueRef fmask_desc =
3491 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3492 ctx->v8i32, "");
3493
3494 LLVMValueRef fmask_word1 =
3495 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3496 ctx->i32_1, "");
3497
3498 LLVMValueRef word1_is_nonzero =
3499 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3500 fmask_word1, ctx->i32_0, "");
3501
3502 /* Replace the MSAA sample index. */
3503 sample_index =
3504 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3505 final_sample, sample_index, "");
3506 return sample_index;
3507 }
3508
3509 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3510 const nir_intrinsic_instr *instr)
3511 {
3512 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3513
3514 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3515 LLVMValueRef coords[4];
3516 LLVMValueRef masks[] = {
3517 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3518 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3519 };
3520 LLVMValueRef res;
3521 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3522
3523 int count;
3524 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3525 bool is_array = glsl_sampler_type_is_array(type);
3526 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3527 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3528 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3529 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3530 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3531 count = image_type_to_components_count(dim, is_array);
3532
3533 if (is_ms) {
3534 LLVMValueRef fmask_load_address[3];
3535 int chan;
3536
3537 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3538 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3539 if (is_array)
3540 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3541 else
3542 fmask_load_address[2] = NULL;
3543 if (add_frag_pos) {
3544 for (chan = 0; chan < 2; ++chan)
3545 fmask_load_address[chan] =
3546 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3547 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3548 ctx->ac.i32, ""), "");
3549 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3550 }
3551 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3552 fmask_load_address[0],
3553 fmask_load_address[1],
3554 fmask_load_address[2],
3555 sample_index,
3556 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3557 }
3558 if (count == 1 && !gfx9_1d) {
3559 if (instr->src[0].ssa->num_components)
3560 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3561 else
3562 res = src0;
3563 } else {
3564 int chan;
3565 if (is_ms)
3566 count--;
3567 for (chan = 0; chan < count; ++chan) {
3568 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3569 }
3570 if (add_frag_pos) {
3571 for (chan = 0; chan < 2; ++chan)
3572 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3573 ctx->ac.i32, ""), "");
3574 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3575 count++;
3576 }
3577
3578 if (gfx9_1d) {
3579 if (is_array) {
3580 coords[2] = coords[1];
3581 coords[1] = ctx->ac.i32_0;
3582 } else
3583 coords[1] = ctx->ac.i32_0;
3584 count++;
3585 }
3586
3587 if (is_ms) {
3588 coords[count] = sample_index;
3589 count++;
3590 }
3591
3592 if (count == 3) {
3593 coords[3] = LLVMGetUndef(ctx->ac.i32);
3594 count = 4;
3595 }
3596 res = ac_build_gather_values(&ctx->ac, coords, count);
3597 }
3598 return res;
3599 }
3600
3601 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3602 const nir_intrinsic_instr *instr)
3603 {
3604 LLVMValueRef params[7];
3605 LLVMValueRef res;
3606 char intrinsic_name[64];
3607 const nir_variable *var = instr->variables[0]->var;
3608 const struct glsl_type *type = var->type;
3609
3610 if(instr->variables[0]->deref.child)
3611 type = instr->variables[0]->deref.child->type;
3612
3613 type = glsl_without_array(type);
3614
3615 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3616 if (dim == GLSL_SAMPLER_DIM_BUF) {
3617 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3618 unsigned num_channels = util_last_bit(mask);
3619 LLVMValueRef rsrc, vindex;
3620
3621 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3622 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3623 ctx->ac.i32_0, "");
3624
3625 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3626 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3627 ctx->ac.i32_0, num_channels,
3628 false, false);
3629 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3630
3631 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3632 res = ac_to_integer(&ctx->ac, res);
3633 } else {
3634 bool is_da = glsl_sampler_type_is_array(type) ||
3635 dim == GLSL_SAMPLER_DIM_CUBE ||
3636 dim == GLSL_SAMPLER_DIM_3D ||
3637 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3638 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3639 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3640 LLVMValueRef glc = ctx->ac.i1false;
3641 LLVMValueRef slc = ctx->ac.i1false;
3642
3643 params[0] = get_image_coords(ctx, instr);
3644 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3645 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3646 params[3] = glc;
3647 params[4] = slc;
3648 params[5] = ctx->ac.i1false;
3649 params[6] = da;
3650
3651 ac_get_image_intr_name("llvm.amdgcn.image.load",
3652 ctx->ac.v4f32, /* vdata */
3653 LLVMTypeOf(params[0]), /* coords */
3654 LLVMTypeOf(params[1]), /* rsrc */
3655 intrinsic_name, sizeof(intrinsic_name));
3656
3657 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3658 params, 7, AC_FUNC_ATTR_READONLY);
3659 }
3660 return ac_to_integer(&ctx->ac, res);
3661 }
3662
3663 static void visit_image_store(struct ac_nir_context *ctx,
3664 nir_intrinsic_instr *instr)
3665 {
3666 LLVMValueRef params[8];
3667 char intrinsic_name[64];
3668 const nir_variable *var = instr->variables[0]->var;
3669 const struct glsl_type *type = glsl_without_array(var->type);
3670 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3671 LLVMValueRef glc = ctx->ac.i1false;
3672 bool force_glc = ctx->ac.chip_class == SI;
3673 if (force_glc)
3674 glc = ctx->ac.i1true;
3675
3676 if (dim == GLSL_SAMPLER_DIM_BUF) {
3677 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3678 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3679 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3680 ctx->ac.i32_0, ""); /* vindex */
3681 params[3] = ctx->ac.i32_0; /* voffset */
3682 params[4] = glc; /* glc */
3683 params[5] = ctx->ac.i1false; /* slc */
3684 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3685 params, 6, 0);
3686 } else {
3687 bool is_da = glsl_sampler_type_is_array(type) ||
3688 dim == GLSL_SAMPLER_DIM_CUBE ||
3689 dim == GLSL_SAMPLER_DIM_3D;
3690 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3691 LLVMValueRef slc = ctx->ac.i1false;
3692
3693 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3694 params[1] = get_image_coords(ctx, instr); /* coords */
3695 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3696 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3697 params[4] = glc;
3698 params[5] = slc;
3699 params[6] = ctx->ac.i1false;
3700 params[7] = da;
3701
3702 ac_get_image_intr_name("llvm.amdgcn.image.store",
3703 LLVMTypeOf(params[0]), /* vdata */
3704 LLVMTypeOf(params[1]), /* coords */
3705 LLVMTypeOf(params[2]), /* rsrc */
3706 intrinsic_name, sizeof(intrinsic_name));
3707
3708 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3709 params, 8, 0);
3710 }
3711
3712 }
3713
3714 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3715 const nir_intrinsic_instr *instr)
3716 {
3717 LLVMValueRef params[7];
3718 int param_count = 0;
3719 const nir_variable *var = instr->variables[0]->var;
3720
3721 const char *atomic_name;
3722 char intrinsic_name[41];
3723 const struct glsl_type *type = glsl_without_array(var->type);
3724 MAYBE_UNUSED int length;
3725
3726 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3727
3728 switch (instr->intrinsic) {
3729 case nir_intrinsic_image_atomic_add:
3730 atomic_name = "add";
3731 break;
3732 case nir_intrinsic_image_atomic_min:
3733 atomic_name = is_unsigned ? "umin" : "smin";
3734 break;
3735 case nir_intrinsic_image_atomic_max:
3736 atomic_name = is_unsigned ? "umax" : "smax";
3737 break;
3738 case nir_intrinsic_image_atomic_and:
3739 atomic_name = "and";
3740 break;
3741 case nir_intrinsic_image_atomic_or:
3742 atomic_name = "or";
3743 break;
3744 case nir_intrinsic_image_atomic_xor:
3745 atomic_name = "xor";
3746 break;
3747 case nir_intrinsic_image_atomic_exchange:
3748 atomic_name = "swap";
3749 break;
3750 case nir_intrinsic_image_atomic_comp_swap:
3751 atomic_name = "cmpswap";
3752 break;
3753 default:
3754 abort();
3755 }
3756
3757 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3758 params[param_count++] = get_src(ctx, instr->src[3]);
3759 params[param_count++] = get_src(ctx, instr->src[2]);
3760
3761 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3762 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3763 NULL, true, true);
3764 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3765 ctx->ac.i32_0, ""); /* vindex */
3766 params[param_count++] = ctx->ac.i32_0; /* voffset */
3767 params[param_count++] = ctx->ac.i1false; /* slc */
3768
3769 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3770 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3771 } else {
3772 char coords_type[8];
3773
3774 bool da = glsl_sampler_type_is_array(type) ||
3775 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3776
3777 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3778 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3779 NULL, true, true);
3780 params[param_count++] = ctx->ac.i1false; /* r128 */
3781 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3782 params[param_count++] = ctx->ac.i1false; /* slc */
3783
3784 build_int_type_name(LLVMTypeOf(coords),
3785 coords_type, sizeof(coords_type));
3786
3787 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3788 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3789 }
3790
3791 assert(length < sizeof(intrinsic_name));
3792 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3793 }
3794
3795 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3796 const nir_intrinsic_instr *instr)
3797 {
3798 const nir_variable *var = instr->variables[0]->var;
3799 const struct glsl_type *type = glsl_without_array(var->type);
3800 bool da = glsl_sampler_type_is_array(type) ||
3801 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3802 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3803
3804 struct ac_image_args args = { 0 };
3805 args.da = da;
3806 args.dmask = 0xf;
3807 args.resource = get_sampler_desc(ctx, instr->variables[0],
3808 AC_DESC_IMAGE, NULL, true, false);
3809 args.opcode = ac_image_get_resinfo;
3810 args.addr = ctx->ac.i32_0;
3811
3812 return ac_build_image_opcode(&ctx->ac, &args);
3813 }
3814
3815 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3816 const nir_intrinsic_instr *instr)
3817 {
3818 LLVMValueRef res;
3819 const nir_variable *var = instr->variables[0]->var;
3820 const struct glsl_type *type = glsl_without_array(var->type);
3821 bool da = glsl_sampler_type_is_array(type) ||
3822 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3823 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3824
3825 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3826 return get_buffer_size(ctx,
3827 get_sampler_desc(ctx, instr->variables[0],
3828 AC_DESC_BUFFER, NULL, true, false), true);
3829
3830 struct ac_image_args args = { 0 };
3831
3832 args.da = da;
3833 args.dmask = 0xf;
3834 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3835 args.opcode = ac_image_get_resinfo;
3836 args.addr = ctx->ac.i32_0;
3837
3838 res = ac_build_image_opcode(&ctx->ac, &args);
3839
3840 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3841
3842 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3843 glsl_sampler_type_is_array(type)) {
3844 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3845 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3846 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3847 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3848 }
3849 if (ctx->ac.chip_class >= GFX9 &&
3850 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3851 glsl_sampler_type_is_array(type)) {
3852 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3853 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3854 ctx->ac.i32_1, "");
3855
3856 }
3857 return res;
3858 }
3859
3860 #define NOOP_WAITCNT 0xf7f
3861 #define LGKM_CNT 0x07f
3862 #define VM_CNT 0xf70
3863
3864 static void emit_membar(struct ac_llvm_context *ac,
3865 const nir_intrinsic_instr *instr)
3866 {
3867 unsigned waitcnt = NOOP_WAITCNT;
3868
3869 switch (instr->intrinsic) {
3870 case nir_intrinsic_memory_barrier:
3871 case nir_intrinsic_group_memory_barrier:
3872 waitcnt &= VM_CNT & LGKM_CNT;
3873 break;
3874 case nir_intrinsic_memory_barrier_atomic_counter:
3875 case nir_intrinsic_memory_barrier_buffer:
3876 case nir_intrinsic_memory_barrier_image:
3877 waitcnt &= VM_CNT;
3878 break;
3879 case nir_intrinsic_memory_barrier_shared:
3880 waitcnt &= LGKM_CNT;
3881 break;
3882 default:
3883 break;
3884 }
3885 if (waitcnt != NOOP_WAITCNT)
3886 ac_build_waitcnt(ac, waitcnt);
3887 }
3888
3889 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3890 {
3891 /* SI only (thanks to a hw bug workaround):
3892 * The real barrier instruction isn’t needed, because an entire patch
3893 * always fits into a single wave.
3894 */
3895 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3896 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3897 return;
3898 }
3899 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3900 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3901 }
3902
3903 static void emit_discard(struct ac_nir_context *ctx,
3904 const nir_intrinsic_instr *instr)
3905 {
3906 LLVMValueRef cond;
3907
3908 if (instr->intrinsic == nir_intrinsic_discard_if) {
3909 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3910 get_src(ctx, instr->src[0]),
3911 ctx->ac.i32_0, "");
3912 } else {
3913 assert(instr->intrinsic == nir_intrinsic_discard);
3914 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3915 }
3916
3917 ac_build_kill_if_false(&ctx->ac, cond);
3918 }
3919
3920 static LLVMValueRef
3921 visit_load_helper_invocation(struct ac_nir_context *ctx)
3922 {
3923 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3924 "llvm.amdgcn.ps.live",
3925 ctx->ac.i1, NULL, 0,
3926 AC_FUNC_ATTR_READNONE);
3927 result = LLVMBuildNot(ctx->ac.builder, result, "");
3928 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3929 }
3930
3931 static LLVMValueRef
3932 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3933 {
3934 LLVMValueRef result;
3935 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3936 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3937 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3938
3939 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3940 }
3941
3942 static LLVMValueRef
3943 visit_load_shared(struct ac_nir_context *ctx,
3944 const nir_intrinsic_instr *instr)
3945 {
3946 LLVMValueRef values[4], derived_ptr, index, ret;
3947
3948 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3949
3950 for (int chan = 0; chan < instr->num_components; chan++) {
3951 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3952 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3953 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3954 }
3955
3956 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3957 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3958 }
3959
3960 static void
3961 visit_store_shared(struct ac_nir_context *ctx,
3962 const nir_intrinsic_instr *instr)
3963 {
3964 LLVMValueRef derived_ptr, data,index;
3965 LLVMBuilderRef builder = ctx->ac.builder;
3966
3967 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3968 LLVMValueRef src = get_src(ctx, instr->src[0]);
3969
3970 int writemask = nir_intrinsic_write_mask(instr);
3971 for (int chan = 0; chan < 4; chan++) {
3972 if (!(writemask & (1 << chan))) {
3973 continue;
3974 }
3975 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3976 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3977 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3978 LLVMBuildStore(builder, data, derived_ptr);
3979 }
3980 }
3981
3982 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3983 const nir_intrinsic_instr *instr,
3984 LLVMValueRef ptr)
3985 {
3986 LLVMValueRef result;
3987 LLVMValueRef src = get_src(ctx, instr->src[0]);
3988
3989 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3990 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3991 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3992 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3993 ptr, src, src1,
3994 LLVMAtomicOrderingSequentiallyConsistent,
3995 LLVMAtomicOrderingSequentiallyConsistent,
3996 false);
3997 } else {
3998 LLVMAtomicRMWBinOp op;
3999 switch (instr->intrinsic) {
4000 case nir_intrinsic_var_atomic_add:
4001 case nir_intrinsic_shared_atomic_add:
4002 op = LLVMAtomicRMWBinOpAdd;
4003 break;
4004 case nir_intrinsic_var_atomic_umin:
4005 case nir_intrinsic_shared_atomic_umin:
4006 op = LLVMAtomicRMWBinOpUMin;
4007 break;
4008 case nir_intrinsic_var_atomic_umax:
4009 case nir_intrinsic_shared_atomic_umax:
4010 op = LLVMAtomicRMWBinOpUMax;
4011 break;
4012 case nir_intrinsic_var_atomic_imin:
4013 case nir_intrinsic_shared_atomic_imin:
4014 op = LLVMAtomicRMWBinOpMin;
4015 break;
4016 case nir_intrinsic_var_atomic_imax:
4017 case nir_intrinsic_shared_atomic_imax:
4018 op = LLVMAtomicRMWBinOpMax;
4019 break;
4020 case nir_intrinsic_var_atomic_and:
4021 case nir_intrinsic_shared_atomic_and:
4022 op = LLVMAtomicRMWBinOpAnd;
4023 break;
4024 case nir_intrinsic_var_atomic_or:
4025 case nir_intrinsic_shared_atomic_or:
4026 op = LLVMAtomicRMWBinOpOr;
4027 break;
4028 case nir_intrinsic_var_atomic_xor:
4029 case nir_intrinsic_shared_atomic_xor:
4030 op = LLVMAtomicRMWBinOpXor;
4031 break;
4032 case nir_intrinsic_var_atomic_exchange:
4033 case nir_intrinsic_shared_atomic_exchange:
4034 op = LLVMAtomicRMWBinOpXchg;
4035 break;
4036 default:
4037 return NULL;
4038 }
4039
4040 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4041 LLVMAtomicOrderingSequentiallyConsistent,
4042 false);
4043 }
4044 return result;
4045 }
4046
4047 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4048 enum glsl_interp_mode interp, unsigned location)
4049 {
4050 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4051
4052 switch (interp) {
4053 case INTERP_MODE_FLAT:
4054 default:
4055 return NULL;
4056 case INTERP_MODE_SMOOTH:
4057 case INTERP_MODE_NONE:
4058 if (location == INTERP_CENTER)
4059 return ctx->persp_center;
4060 else if (location == INTERP_CENTROID)
4061 return ctx->persp_centroid;
4062 else if (location == INTERP_SAMPLE)
4063 return ctx->persp_sample;
4064 break;
4065 case INTERP_MODE_NOPERSPECTIVE:
4066 if (location == INTERP_CENTER)
4067 return ctx->linear_center;
4068 else if (location == INTERP_CENTROID)
4069 return ctx->linear_centroid;
4070 else if (location == INTERP_SAMPLE)
4071 return ctx->linear_sample;
4072 break;
4073 }
4074 return NULL;
4075 }
4076
4077 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4078 LLVMValueRef sample_id)
4079 {
4080 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4081
4082 LLVMValueRef result;
4083 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4084
4085 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4086 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4087
4088 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4089 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4090
4091 return result;
4092 }
4093
4094 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4095 {
4096 LLVMValueRef values[2];
4097
4098 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4099 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4100 return ac_build_gather_values(&ctx->ac, values, 2);
4101 }
4102
4103 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4104 {
4105 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4106 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4107 ctx->options->key.fs.log2_num_samples :
4108 ctx->options->key.fs.log2_ps_iter_samples;
4109
4110 /* The bit pattern matches that used by fixed function fragment
4111 * processing. */
4112 static const uint16_t ps_iter_masks[] = {
4113 0xffff, /* not used */
4114 0x5555,
4115 0x1111,
4116 0x0101,
4117 0x0001,
4118 };
4119 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4120
4121 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4122
4123 LLVMValueRef result, sample_id;
4124 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4125 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4126 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4127 return result;
4128 }
4129
4130 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4131 const nir_intrinsic_instr *instr)
4132 {
4133 LLVMValueRef result[4];
4134 LLVMValueRef interp_param, attr_number;
4135 unsigned location;
4136 unsigned chan;
4137 LLVMValueRef src_c0 = NULL;
4138 LLVMValueRef src_c1 = NULL;
4139 LLVMValueRef src0 = NULL;
4140 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4141 switch (instr->intrinsic) {
4142 case nir_intrinsic_interp_var_at_centroid:
4143 location = INTERP_CENTROID;
4144 break;
4145 case nir_intrinsic_interp_var_at_sample:
4146 case nir_intrinsic_interp_var_at_offset:
4147 location = INTERP_CENTER;
4148 src0 = get_src(ctx, instr->src[0]);
4149 break;
4150 default:
4151 break;
4152 }
4153
4154 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4155 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4156 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4157 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4158 LLVMValueRef sample_position;
4159 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4160
4161 /* fetch sample ID */
4162 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4163
4164 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4165 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4166 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4167 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4168 }
4169 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4170 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4171
4172 if (location == INTERP_CENTER) {
4173 LLVMValueRef ij_out[2];
4174 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4175
4176 /*
4177 * take the I then J parameters, and the DDX/Y for it, and
4178 * calculate the IJ inputs for the interpolator.
4179 * temp1 = ddx * offset/sample.x + I;
4180 * interp_param.I = ddy * offset/sample.y + temp1;
4181 * temp1 = ddx * offset/sample.x + J;
4182 * interp_param.J = ddy * offset/sample.y + temp1;
4183 */
4184 for (unsigned i = 0; i < 2; i++) {
4185 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4186 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4187 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4188 ddxy_out, ix_ll, "");
4189 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4190 ddxy_out, iy_ll, "");
4191 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4192 interp_param, ix_ll, "");
4193 LLVMValueRef temp1, temp2;
4194
4195 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4196 ctx->ac.f32, "");
4197
4198 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4199 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4200
4201 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4202 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4203
4204 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4205 temp2, ctx->ac.i32, "");
4206 }
4207 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4208
4209 }
4210
4211 for (chan = 0; chan < 4; chan++) {
4212 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4213
4214 if (interp_param) {
4215 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4216 interp_param, ctx->ac.v2f32, "");
4217 LLVMValueRef i = LLVMBuildExtractElement(
4218 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4219 LLVMValueRef j = LLVMBuildExtractElement(
4220 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4221
4222 result[chan] = ac_build_fs_interp(&ctx->ac,
4223 llvm_chan, attr_number,
4224 ctx->abi->prim_mask, i, j);
4225 } else {
4226 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4227 LLVMConstInt(ctx->ac.i32, 2, false),
4228 llvm_chan, attr_number,
4229 ctx->abi->prim_mask);
4230 }
4231 }
4232 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4233 instr->variables[0]->var->data.location_frac);
4234 }
4235
4236 static void
4237 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4238 {
4239 LLVMValueRef gs_next_vertex;
4240 LLVMValueRef can_emit;
4241 int idx;
4242 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4243
4244 assert(stream == 0);
4245
4246 /* Write vertex attribute values to GSVS ring */
4247 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4248 ctx->gs_next_vertex,
4249 "");
4250
4251 /* If this thread has already emitted the declared maximum number of
4252 * vertices, kill it: excessive vertex emissions are not supposed to
4253 * have any effect, and GS threads have no externally observable
4254 * effects other than emitting vertices.
4255 */
4256 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4257 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4258 ac_build_kill_if_false(&ctx->ac, can_emit);
4259
4260 /* loop num outputs */
4261 idx = 0;
4262 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4263 LLVMValueRef *out_ptr = &addrs[i * 4];
4264 int length = 4;
4265 int slot = idx;
4266 int slot_inc = 1;
4267
4268 if (!(ctx->output_mask & (1ull << i)))
4269 continue;
4270
4271 if (i == VARYING_SLOT_CLIP_DIST0) {
4272 /* pack clip and cull into a single set of slots */
4273 length = ctx->num_output_clips + ctx->num_output_culls;
4274 if (length > 4)
4275 slot_inc = 2;
4276 }
4277 for (unsigned j = 0; j < length; j++) {
4278 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4279 out_ptr[j], "");
4280 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4281 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4282 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4283
4284 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4285
4286 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4287 out_val, 1,
4288 voffset, ctx->gs2vs_offset, 0,
4289 1, 1, true, true);
4290 }
4291 idx += slot_inc;
4292 }
4293
4294 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4295 ctx->ac.i32_1, "");
4296 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4297
4298 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4299 }
4300
4301 static void
4302 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4303 {
4304 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4305 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4306 }
4307
4308 static LLVMValueRef
4309 load_tess_coord(struct ac_shader_abi *abi)
4310 {
4311 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4312
4313 LLVMValueRef coord[4] = {
4314 ctx->tes_u,
4315 ctx->tes_v,
4316 ctx->ac.f32_0,
4317 ctx->ac.f32_0,
4318 };
4319
4320 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4321 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4322 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4323
4324 return ac_build_gather_values(&ctx->ac, coord, 3);
4325 }
4326
4327 static LLVMValueRef
4328 load_patch_vertices_in(struct ac_shader_abi *abi)
4329 {
4330 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4331 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4332 }
4333
4334 static void visit_intrinsic(struct ac_nir_context *ctx,
4335 nir_intrinsic_instr *instr)
4336 {
4337 LLVMValueRef result = NULL;
4338
4339 switch (instr->intrinsic) {
4340 case nir_intrinsic_ballot:
4341 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4342 break;
4343 case nir_intrinsic_read_invocation:
4344 case nir_intrinsic_read_first_invocation: {
4345 LLVMValueRef args[2];
4346
4347 /* Value */
4348 args[0] = get_src(ctx, instr->src[0]);
4349
4350 unsigned num_args;
4351 const char *intr_name;
4352 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4353 num_args = 2;
4354 intr_name = "llvm.amdgcn.readlane";
4355
4356 /* Invocation */
4357 args[1] = get_src(ctx, instr->src[1]);
4358 } else {
4359 num_args = 1;
4360 intr_name = "llvm.amdgcn.readfirstlane";
4361 }
4362
4363 /* We currently have no other way to prevent LLVM from lifting the icmp
4364 * calls to a dominating basic block.
4365 */
4366 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4367
4368 result = ac_build_intrinsic(&ctx->ac, intr_name,
4369 ctx->ac.i32, args, num_args,
4370 AC_FUNC_ATTR_READNONE |
4371 AC_FUNC_ATTR_CONVERGENT);
4372 break;
4373 }
4374 case nir_intrinsic_load_subgroup_invocation:
4375 result = ac_get_thread_id(&ctx->ac);
4376 break;
4377 case nir_intrinsic_load_work_group_id: {
4378 LLVMValueRef values[3];
4379
4380 for (int i = 0; i < 3; i++) {
4381 values[i] = ctx->abi->workgroup_ids[i] ?
4382 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4383 }
4384
4385 result = ac_build_gather_values(&ctx->ac, values, 3);
4386 break;
4387 }
4388 case nir_intrinsic_load_base_vertex: {
4389 result = ctx->abi->base_vertex;
4390 break;
4391 }
4392 case nir_intrinsic_load_local_group_size:
4393 result = ctx->abi->load_local_group_size(ctx->abi);
4394 break;
4395 case nir_intrinsic_load_vertex_id_zero_base: {
4396 result = ctx->abi->vertex_id;
4397 break;
4398 }
4399 case nir_intrinsic_load_local_invocation_id: {
4400 result = ctx->abi->local_invocation_ids;
4401 break;
4402 }
4403 case nir_intrinsic_load_base_instance:
4404 result = ctx->abi->start_instance;
4405 break;
4406 case nir_intrinsic_load_draw_id:
4407 result = ctx->abi->draw_id;
4408 break;
4409 case nir_intrinsic_load_view_index:
4410 result = ctx->abi->view_index;
4411 break;
4412 case nir_intrinsic_load_invocation_id:
4413 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4414 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4415 else
4416 result = ctx->abi->gs_invocation_id;
4417 break;
4418 case nir_intrinsic_load_primitive_id:
4419 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4420 result = ctx->abi->gs_prim_id;
4421 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4422 result = ctx->abi->tcs_patch_id;
4423 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4424 result = ctx->abi->tes_patch_id;
4425 } else
4426 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4427 break;
4428 case nir_intrinsic_load_sample_id:
4429 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4430 break;
4431 case nir_intrinsic_load_sample_pos:
4432 result = load_sample_pos(ctx);
4433 break;
4434 case nir_intrinsic_load_sample_mask_in:
4435 result = ctx->abi->load_sample_mask_in(ctx->abi);
4436 break;
4437 case nir_intrinsic_load_frag_coord: {
4438 LLVMValueRef values[4] = {
4439 ctx->abi->frag_pos[0],
4440 ctx->abi->frag_pos[1],
4441 ctx->abi->frag_pos[2],
4442 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4443 };
4444 result = ac_build_gather_values(&ctx->ac, values, 4);
4445 break;
4446 }
4447 case nir_intrinsic_load_front_face:
4448 result = ctx->abi->front_face;
4449 break;
4450 case nir_intrinsic_load_helper_invocation:
4451 result = visit_load_helper_invocation(ctx);
4452 break;
4453 case nir_intrinsic_load_instance_id:
4454 result = ctx->abi->instance_id;
4455 break;
4456 case nir_intrinsic_load_num_work_groups:
4457 result = ctx->abi->num_work_groups;
4458 break;
4459 case nir_intrinsic_load_local_invocation_index:
4460 result = visit_load_local_invocation_index(ctx);
4461 break;
4462 case nir_intrinsic_load_push_constant:
4463 result = visit_load_push_constant(ctx, instr);
4464 break;
4465 case nir_intrinsic_vulkan_resource_index: {
4466 LLVMValueRef index = get_src(ctx, instr->src[0]);
4467 unsigned desc_set = nir_intrinsic_desc_set(instr);
4468 unsigned binding = nir_intrinsic_binding(instr);
4469
4470 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4471 binding);
4472 break;
4473 }
4474 case nir_intrinsic_vulkan_resource_reindex:
4475 result = visit_vulkan_resource_reindex(ctx, instr);
4476 break;
4477 case nir_intrinsic_store_ssbo:
4478 visit_store_ssbo(ctx, instr);
4479 break;
4480 case nir_intrinsic_load_ssbo:
4481 result = visit_load_buffer(ctx, instr);
4482 break;
4483 case nir_intrinsic_ssbo_atomic_add:
4484 case nir_intrinsic_ssbo_atomic_imin:
4485 case nir_intrinsic_ssbo_atomic_umin:
4486 case nir_intrinsic_ssbo_atomic_imax:
4487 case nir_intrinsic_ssbo_atomic_umax:
4488 case nir_intrinsic_ssbo_atomic_and:
4489 case nir_intrinsic_ssbo_atomic_or:
4490 case nir_intrinsic_ssbo_atomic_xor:
4491 case nir_intrinsic_ssbo_atomic_exchange:
4492 case nir_intrinsic_ssbo_atomic_comp_swap:
4493 result = visit_atomic_ssbo(ctx, instr);
4494 break;
4495 case nir_intrinsic_load_ubo:
4496 result = visit_load_ubo_buffer(ctx, instr);
4497 break;
4498 case nir_intrinsic_get_buffer_size:
4499 result = visit_get_buffer_size(ctx, instr);
4500 break;
4501 case nir_intrinsic_load_var:
4502 result = visit_load_var(ctx, instr);
4503 break;
4504 case nir_intrinsic_store_var:
4505 visit_store_var(ctx, instr);
4506 break;
4507 case nir_intrinsic_load_shared:
4508 result = visit_load_shared(ctx, instr);
4509 break;
4510 case nir_intrinsic_store_shared:
4511 visit_store_shared(ctx, instr);
4512 break;
4513 case nir_intrinsic_image_samples:
4514 result = visit_image_samples(ctx, instr);
4515 break;
4516 case nir_intrinsic_image_load:
4517 result = visit_image_load(ctx, instr);
4518 break;
4519 case nir_intrinsic_image_store:
4520 visit_image_store(ctx, instr);
4521 break;
4522 case nir_intrinsic_image_atomic_add:
4523 case nir_intrinsic_image_atomic_min:
4524 case nir_intrinsic_image_atomic_max:
4525 case nir_intrinsic_image_atomic_and:
4526 case nir_intrinsic_image_atomic_or:
4527 case nir_intrinsic_image_atomic_xor:
4528 case nir_intrinsic_image_atomic_exchange:
4529 case nir_intrinsic_image_atomic_comp_swap:
4530 result = visit_image_atomic(ctx, instr);
4531 break;
4532 case nir_intrinsic_image_size:
4533 result = visit_image_size(ctx, instr);
4534 break;
4535 case nir_intrinsic_shader_clock:
4536 result = ac_build_shader_clock(&ctx->ac);
4537 break;
4538 case nir_intrinsic_discard:
4539 case nir_intrinsic_discard_if:
4540 emit_discard(ctx, instr);
4541 break;
4542 case nir_intrinsic_memory_barrier:
4543 case nir_intrinsic_group_memory_barrier:
4544 case nir_intrinsic_memory_barrier_atomic_counter:
4545 case nir_intrinsic_memory_barrier_buffer:
4546 case nir_intrinsic_memory_barrier_image:
4547 case nir_intrinsic_memory_barrier_shared:
4548 emit_membar(&ctx->ac, instr);
4549 break;
4550 case nir_intrinsic_barrier:
4551 emit_barrier(&ctx->ac, ctx->stage);
4552 break;
4553 case nir_intrinsic_shared_atomic_add:
4554 case nir_intrinsic_shared_atomic_imin:
4555 case nir_intrinsic_shared_atomic_umin:
4556 case nir_intrinsic_shared_atomic_imax:
4557 case nir_intrinsic_shared_atomic_umax:
4558 case nir_intrinsic_shared_atomic_and:
4559 case nir_intrinsic_shared_atomic_or:
4560 case nir_intrinsic_shared_atomic_xor:
4561 case nir_intrinsic_shared_atomic_exchange:
4562 case nir_intrinsic_shared_atomic_comp_swap: {
4563 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
4564 result = visit_var_atomic(ctx, instr, ptr);
4565 break;
4566 }
4567 case nir_intrinsic_var_atomic_add:
4568 case nir_intrinsic_var_atomic_imin:
4569 case nir_intrinsic_var_atomic_umin:
4570 case nir_intrinsic_var_atomic_imax:
4571 case nir_intrinsic_var_atomic_umax:
4572 case nir_intrinsic_var_atomic_and:
4573 case nir_intrinsic_var_atomic_or:
4574 case nir_intrinsic_var_atomic_xor:
4575 case nir_intrinsic_var_atomic_exchange:
4576 case nir_intrinsic_var_atomic_comp_swap: {
4577 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4578 result = visit_var_atomic(ctx, instr, ptr);
4579 break;
4580 }
4581 case nir_intrinsic_interp_var_at_centroid:
4582 case nir_intrinsic_interp_var_at_sample:
4583 case nir_intrinsic_interp_var_at_offset:
4584 result = visit_interp(ctx, instr);
4585 break;
4586 case nir_intrinsic_emit_vertex:
4587 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4588 break;
4589 case nir_intrinsic_end_primitive:
4590 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4591 break;
4592 case nir_intrinsic_load_tess_coord:
4593 result = ctx->abi->load_tess_coord(ctx->abi);
4594 break;
4595 case nir_intrinsic_load_tess_level_outer:
4596 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4597 break;
4598 case nir_intrinsic_load_tess_level_inner:
4599 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4600 break;
4601 case nir_intrinsic_load_patch_vertices_in:
4602 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4603 break;
4604 case nir_intrinsic_vote_all: {
4605 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4606 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4607 break;
4608 }
4609 case nir_intrinsic_vote_any: {
4610 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4611 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4612 break;
4613 }
4614 case nir_intrinsic_vote_eq: {
4615 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4616 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4617 break;
4618 }
4619 default:
4620 fprintf(stderr, "Unknown intrinsic: ");
4621 nir_print_instr(&instr->instr, stderr);
4622 fprintf(stderr, "\n");
4623 break;
4624 }
4625 if (result) {
4626 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4627 }
4628 }
4629
4630 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4631 LLVMValueRef buffer_ptr, bool write)
4632 {
4633 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4634 LLVMValueRef result;
4635
4636 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4637
4638 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4639 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4640
4641 return result;
4642 }
4643
4644 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4645 {
4646 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4647 LLVMValueRef result;
4648
4649 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4650
4651 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4652 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4653
4654 return result;
4655 }
4656
4657 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4658 unsigned descriptor_set,
4659 unsigned base_index,
4660 unsigned constant_index,
4661 LLVMValueRef index,
4662 enum ac_descriptor_type desc_type,
4663 bool image, bool write)
4664 {
4665 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4666 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4667 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4668 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4669 unsigned offset = binding->offset;
4670 unsigned stride = binding->size;
4671 unsigned type_size;
4672 LLVMBuilderRef builder = ctx->ac.builder;
4673 LLVMTypeRef type;
4674
4675 assert(base_index < layout->binding_count);
4676
4677 switch (desc_type) {
4678 case AC_DESC_IMAGE:
4679 type = ctx->ac.v8i32;
4680 type_size = 32;
4681 break;
4682 case AC_DESC_FMASK:
4683 type = ctx->ac.v8i32;
4684 offset += 32;
4685 type_size = 32;
4686 break;
4687 case AC_DESC_SAMPLER:
4688 type = ctx->ac.v4i32;
4689 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4690 offset += 64;
4691
4692 type_size = 16;
4693 break;
4694 case AC_DESC_BUFFER:
4695 type = ctx->ac.v4i32;
4696 type_size = 16;
4697 break;
4698 default:
4699 unreachable("invalid desc_type\n");
4700 }
4701
4702 offset += constant_index * stride;
4703
4704 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4705 (!index || binding->immutable_samplers_equal)) {
4706 if (binding->immutable_samplers_equal)
4707 constant_index = 0;
4708
4709 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4710
4711 LLVMValueRef constants[] = {
4712 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4713 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4714 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4715 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4716 };
4717 return ac_build_gather_values(&ctx->ac, constants, 4);
4718 }
4719
4720 assert(stride % type_size == 0);
4721
4722 if (!index)
4723 index = ctx->ac.i32_0;
4724
4725 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4726
4727 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4728 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4729
4730 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4731 }
4732
4733 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4734 const nir_deref_var *deref,
4735 enum ac_descriptor_type desc_type,
4736 const nir_tex_instr *tex_instr,
4737 bool image, bool write)
4738 {
4739 LLVMValueRef index = NULL;
4740 unsigned constant_index = 0;
4741 unsigned descriptor_set;
4742 unsigned base_index;
4743
4744 if (!deref) {
4745 assert(tex_instr && !image);
4746 descriptor_set = 0;
4747 base_index = tex_instr->sampler_index;
4748 } else {
4749 const nir_deref *tail = &deref->deref;
4750 while (tail->child) {
4751 const nir_deref_array *child = nir_deref_as_array(tail->child);
4752 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4753
4754 if (!array_size)
4755 array_size = 1;
4756
4757 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4758
4759 if (child->deref_array_type == nir_deref_array_type_indirect) {
4760 LLVMValueRef indirect = get_src(ctx, child->indirect);
4761
4762 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4763 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4764
4765 if (!index)
4766 index = indirect;
4767 else
4768 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4769 }
4770
4771 constant_index += child->base_offset * array_size;
4772
4773 tail = &child->deref;
4774 }
4775 descriptor_set = deref->var->data.descriptor_set;
4776 base_index = deref->var->data.binding;
4777 }
4778
4779 return ctx->abi->load_sampler_desc(ctx->abi,
4780 descriptor_set,
4781 base_index,
4782 constant_index, index,
4783 desc_type, image, write);
4784 }
4785
4786 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4787 struct ac_image_args *args,
4788 const nir_tex_instr *instr,
4789 nir_texop op,
4790 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4791 LLVMValueRef *param, unsigned count,
4792 unsigned dmask)
4793 {
4794 unsigned is_rect = 0;
4795 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4796
4797 if (op == nir_texop_lod)
4798 da = false;
4799 /* Pad to power of two vector */
4800 while (count < util_next_power_of_two(count))
4801 param[count++] = LLVMGetUndef(ctx->i32);
4802
4803 if (count > 1)
4804 args->addr = ac_build_gather_values(ctx, param, count);
4805 else
4806 args->addr = param[0];
4807
4808 args->resource = res_ptr;
4809 args->sampler = samp_ptr;
4810
4811 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4812 args->addr = param[0];
4813 return;
4814 }
4815
4816 args->dmask = dmask;
4817 args->unorm = is_rect;
4818 args->da = da;
4819 }
4820
4821 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4822 *
4823 * SI-CI:
4824 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4825 * filtering manually. The driver sets img7 to a mask clearing
4826 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4827 * s_and_b32 samp0, samp0, img7
4828 *
4829 * VI:
4830 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4831 */
4832 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4833 LLVMValueRef res, LLVMValueRef samp)
4834 {
4835 LLVMBuilderRef builder = ctx->ac.builder;
4836 LLVMValueRef img7, samp0;
4837
4838 if (ctx->ac.chip_class >= VI)
4839 return samp;
4840
4841 img7 = LLVMBuildExtractElement(builder, res,
4842 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4843 samp0 = LLVMBuildExtractElement(builder, samp,
4844 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4845 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4846 return LLVMBuildInsertElement(builder, samp, samp0,
4847 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4848 }
4849
4850 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4851 nir_tex_instr *instr,
4852 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4853 LLVMValueRef *fmask_ptr)
4854 {
4855 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4856 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4857 else
4858 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4859 if (samp_ptr) {
4860 if (instr->sampler)
4861 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4862 else
4863 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4864 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4865 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4866 }
4867 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4868 instr->op == nir_texop_samples_identical))
4869 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4870 }
4871
4872 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4873 LLVMValueRef coord)
4874 {
4875 coord = ac_to_float(ctx, coord);
4876 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4877 coord = ac_to_integer(ctx, coord);
4878 return coord;
4879 }
4880
4881 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4882 {
4883 LLVMValueRef result = NULL;
4884 struct ac_image_args args = { 0 };
4885 unsigned dmask = 0xf;
4886 LLVMValueRef address[16];
4887 LLVMValueRef coords[5];
4888 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4889 LLVMValueRef bias = NULL, offsets = NULL;
4890 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4891 LLVMValueRef ddx = NULL, ddy = NULL;
4892 LLVMValueRef derivs[6];
4893 unsigned chan, count = 0;
4894 unsigned const_src = 0, num_deriv_comp = 0;
4895 bool lod_is_zero = false;
4896
4897 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4898
4899 for (unsigned i = 0; i < instr->num_srcs; i++) {
4900 switch (instr->src[i].src_type) {
4901 case nir_tex_src_coord:
4902 coord = get_src(ctx, instr->src[i].src);
4903 break;
4904 case nir_tex_src_projector:
4905 break;
4906 case nir_tex_src_comparator:
4907 comparator = get_src(ctx, instr->src[i].src);
4908 break;
4909 case nir_tex_src_offset:
4910 offsets = get_src(ctx, instr->src[i].src);
4911 const_src = i;
4912 break;
4913 case nir_tex_src_bias:
4914 bias = get_src(ctx, instr->src[i].src);
4915 break;
4916 case nir_tex_src_lod: {
4917 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4918
4919 if (val && val->i32[0] == 0)
4920 lod_is_zero = true;
4921 lod = get_src(ctx, instr->src[i].src);
4922 break;
4923 }
4924 case nir_tex_src_ms_index:
4925 sample_index = get_src(ctx, instr->src[i].src);
4926 break;
4927 case nir_tex_src_ms_mcs:
4928 break;
4929 case nir_tex_src_ddx:
4930 ddx = get_src(ctx, instr->src[i].src);
4931 num_deriv_comp = instr->src[i].src.ssa->num_components;
4932 break;
4933 case nir_tex_src_ddy:
4934 ddy = get_src(ctx, instr->src[i].src);
4935 break;
4936 case nir_tex_src_texture_offset:
4937 case nir_tex_src_sampler_offset:
4938 case nir_tex_src_plane:
4939 default:
4940 break;
4941 }
4942 }
4943
4944 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4945 result = get_buffer_size(ctx, res_ptr, true);
4946 goto write_result;
4947 }
4948
4949 if (instr->op == nir_texop_texture_samples) {
4950 LLVMValueRef res, samples, is_msaa;
4951 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4952 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4953 LLVMConstInt(ctx->ac.i32, 3, false), "");
4954 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4955 LLVMConstInt(ctx->ac.i32, 28, false), "");
4956 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4957 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4958 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4959 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4960
4961 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4962 LLVMConstInt(ctx->ac.i32, 16, false), "");
4963 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4964 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4965 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4966 samples, "");
4967 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4968 ctx->ac.i32_1, "");
4969 result = samples;
4970 goto write_result;
4971 }
4972
4973 if (coord)
4974 for (chan = 0; chan < instr->coord_components; chan++)
4975 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4976
4977 if (offsets && instr->op != nir_texop_txf) {
4978 LLVMValueRef offset[3], pack;
4979 for (chan = 0; chan < 3; ++chan)
4980 offset[chan] = ctx->ac.i32_0;
4981
4982 args.offset = true;
4983 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4984 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4985 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4986 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4987 if (chan)
4988 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4989 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4990 }
4991 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4992 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4993 address[count++] = pack;
4994
4995 }
4996 /* pack LOD bias value */
4997 if (instr->op == nir_texop_txb && bias) {
4998 address[count++] = bias;
4999 }
5000
5001 /* Pack depth comparison value */
5002 if (instr->is_shadow && comparator) {
5003 LLVMValueRef z = ac_to_float(&ctx->ac,
5004 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
5005
5006 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
5007 * so the depth comparison value isn't clamped for Z16 and
5008 * Z24 anymore. Do it manually here.
5009 *
5010 * It's unnecessary if the original texture format was
5011 * Z32_FLOAT, but we don't know that here.
5012 */
5013 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5014 z = ac_build_clamp(&ctx->ac, z);
5015
5016 address[count++] = z;
5017 }
5018
5019 /* pack derivatives */
5020 if (ddx || ddy) {
5021 int num_src_deriv_channels, num_dest_deriv_channels;
5022 switch (instr->sampler_dim) {
5023 case GLSL_SAMPLER_DIM_3D:
5024 case GLSL_SAMPLER_DIM_CUBE:
5025 num_deriv_comp = 3;
5026 num_src_deriv_channels = 3;
5027 num_dest_deriv_channels = 3;
5028 break;
5029 case GLSL_SAMPLER_DIM_2D:
5030 default:
5031 num_src_deriv_channels = 2;
5032 num_dest_deriv_channels = 2;
5033 num_deriv_comp = 2;
5034 break;
5035 case GLSL_SAMPLER_DIM_1D:
5036 num_src_deriv_channels = 1;
5037 if (ctx->ac.chip_class >= GFX9) {
5038 num_dest_deriv_channels = 2;
5039 num_deriv_comp = 2;
5040 } else {
5041 num_dest_deriv_channels = 1;
5042 num_deriv_comp = 1;
5043 }
5044 break;
5045 }
5046
5047 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5048 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5049 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5050 }
5051 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5052 derivs[i] = ctx->ac.f32_0;
5053 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5054 }
5055 }
5056
5057 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5058 for (chan = 0; chan < instr->coord_components; chan++)
5059 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5060 if (instr->coord_components == 3)
5061 coords[3] = LLVMGetUndef(ctx->ac.f32);
5062 ac_prepare_cube_coords(&ctx->ac,
5063 instr->op == nir_texop_txd, instr->is_array,
5064 instr->op == nir_texop_lod, coords, derivs);
5065 if (num_deriv_comp)
5066 num_deriv_comp--;
5067 }
5068
5069 if (ddx || ddy) {
5070 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5071 address[count++] = derivs[i];
5072 }
5073
5074 /* Pack texture coordinates */
5075 if (coord) {
5076 address[count++] = coords[0];
5077 if (instr->coord_components > 1) {
5078 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5079 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5080 }
5081 address[count++] = coords[1];
5082 }
5083 if (instr->coord_components > 2) {
5084 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5085 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
5086 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
5087 instr->op != nir_texop_txf) {
5088 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5089 }
5090 address[count++] = coords[2];
5091 }
5092
5093 if (ctx->ac.chip_class >= GFX9) {
5094 LLVMValueRef filler;
5095 if (instr->op == nir_texop_txf)
5096 filler = ctx->ac.i32_0;
5097 else
5098 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5099
5100 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5101 /* No nir_texop_lod, because it does not take a slice
5102 * even with array textures. */
5103 if (instr->is_array && instr->op != nir_texop_lod ) {
5104 address[count] = address[count - 1];
5105 address[count - 1] = filler;
5106 count++;
5107 } else
5108 address[count++] = filler;
5109 }
5110 }
5111 }
5112
5113 /* Pack LOD */
5114 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5115 instr->op == nir_texop_txf)) {
5116 address[count++] = lod;
5117 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5118 address[count++] = sample_index;
5119 } else if(instr->op == nir_texop_txs) {
5120 count = 0;
5121 if (lod)
5122 address[count++] = lod;
5123 else
5124 address[count++] = ctx->ac.i32_0;
5125 }
5126
5127 for (chan = 0; chan < count; chan++) {
5128 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5129 address[chan], ctx->ac.i32, "");
5130 }
5131
5132 if (instr->op == nir_texop_samples_identical) {
5133 LLVMValueRef txf_address[4];
5134 struct ac_image_args txf_args = { 0 };
5135 unsigned txf_count = count;
5136 memcpy(txf_address, address, sizeof(txf_address));
5137
5138 if (!instr->is_array)
5139 txf_address[2] = ctx->ac.i32_0;
5140 txf_address[3] = ctx->ac.i32_0;
5141
5142 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5143 fmask_ptr, NULL,
5144 txf_address, txf_count, 0xf);
5145
5146 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5147
5148 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5149 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5150 goto write_result;
5151 }
5152
5153 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5154 instr->op != nir_texop_txs) {
5155 unsigned sample_chan = instr->is_array ? 3 : 2;
5156 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5157 address[0],
5158 address[1],
5159 instr->is_array ? address[2] : NULL,
5160 address[sample_chan],
5161 fmask_ptr);
5162 }
5163
5164 if (offsets && instr->op == nir_texop_txf) {
5165 nir_const_value *const_offset =
5166 nir_src_as_const_value(instr->src[const_src].src);
5167 int num_offsets = instr->src[const_src].src.ssa->num_components;
5168 assert(const_offset);
5169 num_offsets = MIN2(num_offsets, instr->coord_components);
5170 if (num_offsets > 2)
5171 address[2] = LLVMBuildAdd(ctx->ac.builder,
5172 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5173 if (num_offsets > 1)
5174 address[1] = LLVMBuildAdd(ctx->ac.builder,
5175 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5176 address[0] = LLVMBuildAdd(ctx->ac.builder,
5177 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5178
5179 }
5180
5181 /* TODO TG4 support */
5182 if (instr->op == nir_texop_tg4) {
5183 if (instr->is_shadow)
5184 dmask = 1;
5185 else
5186 dmask = 1 << instr->component;
5187 }
5188 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5189 res_ptr, samp_ptr, address, count, dmask);
5190
5191 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5192
5193 if (instr->op == nir_texop_query_levels)
5194 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5195 else if (instr->is_shadow && instr->is_new_style_shadow &&
5196 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5197 instr->op != nir_texop_tg4)
5198 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5199 else if (instr->op == nir_texop_txs &&
5200 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5201 instr->is_array) {
5202 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5203 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5204 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5205 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5206 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5207 } else if (ctx->ac.chip_class >= GFX9 &&
5208 instr->op == nir_texop_txs &&
5209 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5210 instr->is_array) {
5211 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5212 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5213 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5214 ctx->ac.i32_1, "");
5215 } else if (instr->dest.ssa.num_components != 4)
5216 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5217
5218 write_result:
5219 if (result) {
5220 assert(instr->dest.is_ssa);
5221 result = ac_to_integer(&ctx->ac, result);
5222 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5223 }
5224 }
5225
5226
5227 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5228 {
5229 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5230 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5231
5232 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5233 _mesa_hash_table_insert(ctx->phis, instr, result);
5234 }
5235
5236 static void visit_post_phi(struct ac_nir_context *ctx,
5237 nir_phi_instr *instr,
5238 LLVMValueRef llvm_phi)
5239 {
5240 nir_foreach_phi_src(src, instr) {
5241 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5242 LLVMValueRef llvm_src = get_src(ctx, src->src);
5243
5244 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5245 }
5246 }
5247
5248 static void phi_post_pass(struct ac_nir_context *ctx)
5249 {
5250 struct hash_entry *entry;
5251 hash_table_foreach(ctx->phis, entry) {
5252 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5253 (LLVMValueRef)entry->data);
5254 }
5255 }
5256
5257
5258 static void visit_ssa_undef(struct ac_nir_context *ctx,
5259 const nir_ssa_undef_instr *instr)
5260 {
5261 unsigned num_components = instr->def.num_components;
5262 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5263 LLVMValueRef undef;
5264
5265 if (num_components == 1)
5266 undef = LLVMGetUndef(type);
5267 else {
5268 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5269 }
5270 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5271 }
5272
5273 static void visit_jump(struct ac_nir_context *ctx,
5274 const nir_jump_instr *instr)
5275 {
5276 switch (instr->type) {
5277 case nir_jump_break:
5278 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5279 LLVMClearInsertionPosition(ctx->ac.builder);
5280 break;
5281 case nir_jump_continue:
5282 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5283 LLVMClearInsertionPosition(ctx->ac.builder);
5284 break;
5285 default:
5286 fprintf(stderr, "Unknown NIR jump instr: ");
5287 nir_print_instr(&instr->instr, stderr);
5288 fprintf(stderr, "\n");
5289 abort();
5290 }
5291 }
5292
5293 static void visit_cf_list(struct ac_nir_context *ctx,
5294 struct exec_list *list);
5295
5296 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5297 {
5298 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5299 nir_foreach_instr(instr, block)
5300 {
5301 switch (instr->type) {
5302 case nir_instr_type_alu:
5303 visit_alu(ctx, nir_instr_as_alu(instr));
5304 break;
5305 case nir_instr_type_load_const:
5306 visit_load_const(ctx, nir_instr_as_load_const(instr));
5307 break;
5308 case nir_instr_type_intrinsic:
5309 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5310 break;
5311 case nir_instr_type_tex:
5312 visit_tex(ctx, nir_instr_as_tex(instr));
5313 break;
5314 case nir_instr_type_phi:
5315 visit_phi(ctx, nir_instr_as_phi(instr));
5316 break;
5317 case nir_instr_type_ssa_undef:
5318 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5319 break;
5320 case nir_instr_type_jump:
5321 visit_jump(ctx, nir_instr_as_jump(instr));
5322 break;
5323 default:
5324 fprintf(stderr, "Unknown NIR instr type: ");
5325 nir_print_instr(instr, stderr);
5326 fprintf(stderr, "\n");
5327 abort();
5328 }
5329 }
5330
5331 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5332 }
5333
5334 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5335 {
5336 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5337
5338 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5339 LLVMBasicBlockRef merge_block =
5340 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5341 LLVMBasicBlockRef if_block =
5342 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5343 LLVMBasicBlockRef else_block = merge_block;
5344 if (!exec_list_is_empty(&if_stmt->else_list))
5345 else_block = LLVMAppendBasicBlockInContext(
5346 ctx->ac.context, fn, "");
5347
5348 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5349 ctx->ac.i32_0, "");
5350 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5351
5352 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5353 visit_cf_list(ctx, &if_stmt->then_list);
5354 if (LLVMGetInsertBlock(ctx->ac.builder))
5355 LLVMBuildBr(ctx->ac.builder, merge_block);
5356
5357 if (!exec_list_is_empty(&if_stmt->else_list)) {
5358 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5359 visit_cf_list(ctx, &if_stmt->else_list);
5360 if (LLVMGetInsertBlock(ctx->ac.builder))
5361 LLVMBuildBr(ctx->ac.builder, merge_block);
5362 }
5363
5364 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5365 }
5366
5367 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5368 {
5369 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5370 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5371 LLVMBasicBlockRef break_parent = ctx->break_block;
5372
5373 ctx->continue_block =
5374 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5375 ctx->break_block =
5376 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5377
5378 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5379 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5380 visit_cf_list(ctx, &loop->body);
5381
5382 if (LLVMGetInsertBlock(ctx->ac.builder))
5383 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5384 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5385
5386 ctx->continue_block = continue_parent;
5387 ctx->break_block = break_parent;
5388 }
5389
5390 static void visit_cf_list(struct ac_nir_context *ctx,
5391 struct exec_list *list)
5392 {
5393 foreach_list_typed(nir_cf_node, node, node, list)
5394 {
5395 switch (node->type) {
5396 case nir_cf_node_block:
5397 visit_block(ctx, nir_cf_node_as_block(node));
5398 break;
5399
5400 case nir_cf_node_if:
5401 visit_if(ctx, nir_cf_node_as_if(node));
5402 break;
5403
5404 case nir_cf_node_loop:
5405 visit_loop(ctx, nir_cf_node_as_loop(node));
5406 break;
5407
5408 default:
5409 assert(0);
5410 }
5411 }
5412 }
5413
5414 static void
5415 handle_vs_input_decl(struct radv_shader_context *ctx,
5416 struct nir_variable *variable)
5417 {
5418 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5419 LLVMValueRef t_offset;
5420 LLVMValueRef t_list;
5421 LLVMValueRef input;
5422 LLVMValueRef buffer_index;
5423 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5424 int idx = variable->data.location;
5425 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5426 uint8_t input_usage_mask =
5427 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5428 unsigned num_channels = util_last_bit(input_usage_mask);
5429
5430 variable->data.driver_location = idx * 4;
5431
5432 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5433 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5434 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5435 ctx->abi.start_instance, "");
5436 if (ctx->options->key.vs.as_ls) {
5437 ctx->shader_info->vs.vgpr_comp_cnt =
5438 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5439 } else {
5440 ctx->shader_info->vs.vgpr_comp_cnt =
5441 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5442 }
5443 } else
5444 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5445 ctx->abi.base_vertex, "");
5446 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5447
5448 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5449
5450 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5451 buffer_index,
5452 ctx->ac.i32_0,
5453 num_channels, false, true);
5454
5455 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5456
5457 for (unsigned chan = 0; chan < 4; chan++) {
5458 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5459 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5460 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5461 input, llvm_chan, ""));
5462 }
5463 }
5464 }
5465
5466 static void interp_fs_input(struct radv_shader_context *ctx,
5467 unsigned attr,
5468 LLVMValueRef interp_param,
5469 LLVMValueRef prim_mask,
5470 LLVMValueRef result[4])
5471 {
5472 LLVMValueRef attr_number;
5473 unsigned chan;
5474 LLVMValueRef i, j;
5475 bool interp = interp_param != NULL;
5476
5477 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5478
5479 /* fs.constant returns the param from the middle vertex, so it's not
5480 * really useful for flat shading. It's meant to be used for custom
5481 * interpolation (but the intrinsic can't fetch from the other two
5482 * vertices).
5483 *
5484 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5485 * to do the right thing. The only reason we use fs.constant is that
5486 * fs.interp cannot be used on integers, because they can be equal
5487 * to NaN.
5488 */
5489 if (interp) {
5490 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5491 ctx->ac.v2f32, "");
5492
5493 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5494 ctx->ac.i32_0, "");
5495 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5496 ctx->ac.i32_1, "");
5497 }
5498
5499 for (chan = 0; chan < 4; chan++) {
5500 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5501
5502 if (interp) {
5503 result[chan] = ac_build_fs_interp(&ctx->ac,
5504 llvm_chan,
5505 attr_number,
5506 prim_mask, i, j);
5507 } else {
5508 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5509 LLVMConstInt(ctx->ac.i32, 2, false),
5510 llvm_chan,
5511 attr_number,
5512 prim_mask);
5513 }
5514 }
5515 }
5516
5517 static void
5518 handle_fs_input_decl(struct radv_shader_context *ctx,
5519 struct nir_variable *variable)
5520 {
5521 int idx = variable->data.location;
5522 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5523 LLVMValueRef interp;
5524
5525 variable->data.driver_location = idx * 4;
5526 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5527
5528 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5529 unsigned interp_type;
5530 if (variable->data.sample)
5531 interp_type = INTERP_SAMPLE;
5532 else if (variable->data.centroid)
5533 interp_type = INTERP_CENTROID;
5534 else
5535 interp_type = INTERP_CENTER;
5536
5537 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5538 } else
5539 interp = NULL;
5540
5541 for (unsigned i = 0; i < attrib_count; ++i)
5542 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5543
5544 }
5545
5546 static void
5547 handle_vs_inputs(struct radv_shader_context *ctx,
5548 struct nir_shader *nir) {
5549 nir_foreach_variable(variable, &nir->inputs)
5550 handle_vs_input_decl(ctx, variable);
5551 }
5552
5553 static void
5554 prepare_interp_optimize(struct radv_shader_context *ctx,
5555 struct nir_shader *nir)
5556 {
5557 if (!ctx->options->key.fs.multisample)
5558 return;
5559
5560 bool uses_center = false;
5561 bool uses_centroid = false;
5562 nir_foreach_variable(variable, &nir->inputs) {
5563 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5564 variable->data.sample)
5565 continue;
5566
5567 if (variable->data.centroid)
5568 uses_centroid = true;
5569 else
5570 uses_center = true;
5571 }
5572
5573 if (uses_center && uses_centroid) {
5574 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5575 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5576 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5577 }
5578 }
5579
5580 static void
5581 handle_fs_inputs(struct radv_shader_context *ctx,
5582 struct nir_shader *nir)
5583 {
5584 prepare_interp_optimize(ctx, nir);
5585
5586 nir_foreach_variable(variable, &nir->inputs)
5587 handle_fs_input_decl(ctx, variable);
5588
5589 unsigned index = 0;
5590
5591 if (ctx->shader_info->info.ps.uses_input_attachments ||
5592 ctx->shader_info->info.needs_multiview_view_index)
5593 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5594
5595 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5596 LLVMValueRef interp_param;
5597 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5598
5599 if (!(ctx->input_mask & (1ull << i)))
5600 continue;
5601
5602 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5603 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5604 interp_param = *inputs;
5605 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5606 inputs);
5607
5608 if (!interp_param)
5609 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5610 ++index;
5611 } else if (i == VARYING_SLOT_POS) {
5612 for(int i = 0; i < 3; ++i)
5613 inputs[i] = ctx->abi.frag_pos[i];
5614
5615 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5616 ctx->abi.frag_pos[3]);
5617 }
5618 }
5619 ctx->shader_info->fs.num_interp = index;
5620 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5621 ctx->shader_info->fs.has_pcoord = true;
5622 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5623 ctx->shader_info->fs.prim_id_input = true;
5624 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5625 ctx->shader_info->fs.layer_input = true;
5626 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5627
5628 if (ctx->shader_info->info.needs_multiview_view_index)
5629 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5630 }
5631
5632 static LLVMValueRef
5633 ac_build_alloca(struct ac_llvm_context *ac,
5634 LLVMTypeRef type,
5635 const char *name)
5636 {
5637 LLVMBuilderRef builder = ac->builder;
5638 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5639 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5640 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5641 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5642 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5643 LLVMValueRef res;
5644
5645 if (first_instr) {
5646 LLVMPositionBuilderBefore(first_builder, first_instr);
5647 } else {
5648 LLVMPositionBuilderAtEnd(first_builder, first_block);
5649 }
5650
5651 res = LLVMBuildAlloca(first_builder, type, name);
5652 LLVMBuildStore(builder, LLVMConstNull(type), res);
5653
5654 LLVMDisposeBuilder(first_builder);
5655
5656 return res;
5657 }
5658
5659 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5660 LLVMTypeRef type,
5661 const char *name)
5662 {
5663 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5664 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5665 return ptr;
5666 }
5667
5668 static void
5669 scan_shader_output_decl(struct radv_shader_context *ctx,
5670 struct nir_variable *variable,
5671 struct nir_shader *shader,
5672 gl_shader_stage stage)
5673 {
5674 int idx = variable->data.location + variable->data.index;
5675 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5676 uint64_t mask_attribs;
5677
5678 variable->data.driver_location = idx * 4;
5679
5680 /* tess ctrl has it's own load/store paths for outputs */
5681 if (stage == MESA_SHADER_TESS_CTRL)
5682 return;
5683
5684 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5685 if (stage == MESA_SHADER_VERTEX ||
5686 stage == MESA_SHADER_TESS_EVAL ||
5687 stage == MESA_SHADER_GEOMETRY) {
5688 if (idx == VARYING_SLOT_CLIP_DIST0) {
5689 int length = shader->info.clip_distance_array_size +
5690 shader->info.cull_distance_array_size;
5691 if (stage == MESA_SHADER_VERTEX) {
5692 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5693 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5694 }
5695 if (stage == MESA_SHADER_TESS_EVAL) {
5696 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5697 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5698 }
5699
5700 if (length > 4)
5701 attrib_count = 2;
5702 else
5703 attrib_count = 1;
5704 mask_attribs = 1ull << idx;
5705 }
5706 }
5707
5708 ctx->output_mask |= mask_attribs;
5709 }
5710
5711 static void
5712 handle_shader_output_decl(struct ac_nir_context *ctx,
5713 struct nir_shader *nir,
5714 struct nir_variable *variable)
5715 {
5716 unsigned output_loc = variable->data.driver_location / 4;
5717 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5718
5719 /* tess ctrl has it's own load/store paths for outputs */
5720 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5721 return;
5722
5723 if (ctx->stage == MESA_SHADER_VERTEX ||
5724 ctx->stage == MESA_SHADER_TESS_EVAL ||
5725 ctx->stage == MESA_SHADER_GEOMETRY) {
5726 int idx = variable->data.location + variable->data.index;
5727 if (idx == VARYING_SLOT_CLIP_DIST0) {
5728 int length = nir->info.clip_distance_array_size +
5729 nir->info.cull_distance_array_size;
5730
5731 if (length > 4)
5732 attrib_count = 2;
5733 else
5734 attrib_count = 1;
5735 }
5736 }
5737
5738 for (unsigned i = 0; i < attrib_count; ++i) {
5739 for (unsigned chan = 0; chan < 4; chan++) {
5740 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5741 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5742 }
5743 }
5744 }
5745
5746 static LLVMTypeRef
5747 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5748 enum glsl_base_type type)
5749 {
5750 switch (type) {
5751 case GLSL_TYPE_INT:
5752 case GLSL_TYPE_UINT:
5753 case GLSL_TYPE_BOOL:
5754 case GLSL_TYPE_SUBROUTINE:
5755 return ac->i32;
5756 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5757 return ac->f32;
5758 case GLSL_TYPE_INT64:
5759 case GLSL_TYPE_UINT64:
5760 return ac->i64;
5761 case GLSL_TYPE_DOUBLE:
5762 return ac->f64;
5763 default:
5764 unreachable("unknown GLSL type");
5765 }
5766 }
5767
5768 static LLVMTypeRef
5769 glsl_to_llvm_type(struct ac_llvm_context *ac,
5770 const struct glsl_type *type)
5771 {
5772 if (glsl_type_is_scalar(type)) {
5773 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5774 }
5775
5776 if (glsl_type_is_vector(type)) {
5777 return LLVMVectorType(
5778 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5779 glsl_get_vector_elements(type));
5780 }
5781
5782 if (glsl_type_is_matrix(type)) {
5783 return LLVMArrayType(
5784 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5785 glsl_get_matrix_columns(type));
5786 }
5787
5788 if (glsl_type_is_array(type)) {
5789 return LLVMArrayType(
5790 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5791 glsl_get_length(type));
5792 }
5793
5794 assert(glsl_type_is_struct(type));
5795
5796 LLVMTypeRef member_types[glsl_get_length(type)];
5797
5798 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5799 member_types[i] =
5800 glsl_to_llvm_type(ac,
5801 glsl_get_struct_field(type, i));
5802 }
5803
5804 return LLVMStructTypeInContext(ac->context, member_types,
5805 glsl_get_length(type), false);
5806 }
5807
5808 static void
5809 setup_locals(struct ac_nir_context *ctx,
5810 struct nir_function *func)
5811 {
5812 int i, j;
5813 ctx->num_locals = 0;
5814 nir_foreach_variable(variable, &func->impl->locals) {
5815 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5816 variable->data.driver_location = ctx->num_locals * 4;
5817 variable->data.location_frac = 0;
5818 ctx->num_locals += attrib_count;
5819 }
5820 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5821 if (!ctx->locals)
5822 return;
5823
5824 for (i = 0; i < ctx->num_locals; i++) {
5825 for (j = 0; j < 4; j++) {
5826 ctx->locals[i * 4 + j] =
5827 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5828 }
5829 }
5830 }
5831
5832 static void
5833 setup_shared(struct ac_nir_context *ctx,
5834 struct nir_shader *nir)
5835 {
5836 nir_foreach_variable(variable, &nir->shared) {
5837 LLVMValueRef shared =
5838 LLVMAddGlobalInAddressSpace(
5839 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5840 variable->name ? variable->name : "",
5841 AC_LOCAL_ADDR_SPACE);
5842 _mesa_hash_table_insert(ctx->vars, variable, shared);
5843 }
5844 }
5845
5846 /* Initialize arguments for the shader export intrinsic */
5847 static void
5848 si_llvm_init_export_args(struct radv_shader_context *ctx,
5849 LLVMValueRef *values,
5850 unsigned target,
5851 struct ac_export_args *args)
5852 {
5853 /* Default is 0xf. Adjusted below depending on the format. */
5854 args->enabled_channels = 0xf;
5855
5856 /* Specify whether the EXEC mask represents the valid mask */
5857 args->valid_mask = 0;
5858
5859 /* Specify whether this is the last export */
5860 args->done = 0;
5861
5862 /* Specify the target we are exporting */
5863 args->target = target;
5864
5865 args->compr = false;
5866 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5867 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5868 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5869 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5870
5871 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5872 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5873 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5874 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5875 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5876 unsigned chan;
5877
5878 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5879 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5880 unsigned bits, bool hi) = NULL;
5881
5882 switch(col_format) {
5883 case V_028714_SPI_SHADER_ZERO:
5884 args->enabled_channels = 0; /* writemask */
5885 args->target = V_008DFC_SQ_EXP_NULL;
5886 break;
5887
5888 case V_028714_SPI_SHADER_32_R:
5889 args->enabled_channels = 1;
5890 args->out[0] = values[0];
5891 break;
5892
5893 case V_028714_SPI_SHADER_32_GR:
5894 args->enabled_channels = 0x3;
5895 args->out[0] = values[0];
5896 args->out[1] = values[1];
5897 break;
5898
5899 case V_028714_SPI_SHADER_32_AR:
5900 args->enabled_channels = 0x9;
5901 args->out[0] = values[0];
5902 args->out[3] = values[3];
5903 break;
5904
5905 case V_028714_SPI_SHADER_FP16_ABGR:
5906 packf = ac_build_cvt_pkrtz_f16;
5907 break;
5908
5909 case V_028714_SPI_SHADER_UNORM16_ABGR:
5910 packf = ac_build_cvt_pknorm_u16;
5911 break;
5912
5913 case V_028714_SPI_SHADER_SNORM16_ABGR:
5914 packf = ac_build_cvt_pknorm_i16;
5915 break;
5916
5917 case V_028714_SPI_SHADER_UINT16_ABGR:
5918 packi = ac_build_cvt_pk_u16;
5919 break;
5920
5921 case V_028714_SPI_SHADER_SINT16_ABGR:
5922 packi = ac_build_cvt_pk_i16;
5923 break;
5924
5925 default:
5926 case V_028714_SPI_SHADER_32_ABGR:
5927 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5928 break;
5929 }
5930
5931 /* Pack f16 or norm_i16/u16. */
5932 if (packf) {
5933 for (chan = 0; chan < 2; chan++) {
5934 LLVMValueRef pack_args[2] = {
5935 values[2 * chan],
5936 values[2 * chan + 1]
5937 };
5938 LLVMValueRef packed;
5939
5940 packed = packf(&ctx->ac, pack_args);
5941 args->out[chan] = ac_to_float(&ctx->ac, packed);
5942 }
5943 args->compr = 1; /* COMPR flag */
5944 }
5945
5946 /* Pack i16/u16. */
5947 if (packi) {
5948 for (chan = 0; chan < 2; chan++) {
5949 LLVMValueRef pack_args[2] = {
5950 ac_to_integer(&ctx->ac, values[2 * chan]),
5951 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5952 };
5953 LLVMValueRef packed;
5954
5955 packed = packi(&ctx->ac, pack_args,
5956 is_int8 ? 8 : is_int10 ? 10 : 16,
5957 chan == 1);
5958 args->out[chan] = ac_to_float(&ctx->ac, packed);
5959 }
5960 args->compr = 1; /* COMPR flag */
5961 }
5962 return;
5963 }
5964
5965 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5966
5967 for (unsigned i = 0; i < 4; ++i)
5968 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5969 }
5970
5971 static void
5972 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5973 LLVMValueRef *values)
5974 {
5975 struct ac_export_args args;
5976
5977 si_llvm_init_export_args(ctx, values,
5978 V_008DFC_SQ_EXP_PARAM + index, &args);
5979 ac_build_export(&ctx->ac, &args);
5980 }
5981
5982 static LLVMValueRef
5983 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5984 {
5985 LLVMValueRef output =
5986 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5987
5988 return LLVMBuildLoad(ctx->ac.builder, output, "");
5989 }
5990
5991 static void
5992 handle_vs_outputs_post(struct radv_shader_context *ctx,
5993 bool export_prim_id,
5994 struct ac_vs_output_info *outinfo)
5995 {
5996 uint32_t param_count = 0;
5997 unsigned target;
5998 unsigned pos_idx, num_pos_exports = 0;
5999 struct ac_export_args args, pos_args[4] = {};
6000 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
6001 int i;
6002
6003 if (ctx->options->key.has_multiview_view_index) {
6004 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
6005 if(!*tmp_out) {
6006 for(unsigned i = 0; i < 4; ++i)
6007 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
6008 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
6009 }
6010
6011 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
6012 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
6013 }
6014
6015 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6016 sizeof(outinfo->vs_output_param_offset));
6017
6018 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
6019 LLVMValueRef slots[8];
6020 unsigned j;
6021
6022 if (outinfo->cull_dist_mask)
6023 outinfo->cull_dist_mask <<= ctx->num_output_clips;
6024
6025 i = VARYING_SLOT_CLIP_DIST0;
6026 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
6027 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6028
6029 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
6030 slots[i] = LLVMGetUndef(ctx->ac.f32);
6031
6032 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
6033 target = V_008DFC_SQ_EXP_POS + 3;
6034 si_llvm_init_export_args(ctx, &slots[4], target, &args);
6035 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6036 &args, sizeof(args));
6037 }
6038
6039 target = V_008DFC_SQ_EXP_POS + 2;
6040 si_llvm_init_export_args(ctx, &slots[0], target, &args);
6041 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6042 &args, sizeof(args));
6043
6044 }
6045
6046 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6047 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6048 for (unsigned j = 0; j < 4; j++)
6049 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6050 }
6051 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6052
6053 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6054 outinfo->writes_pointsize = true;
6055 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6056 }
6057
6058 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6059 outinfo->writes_layer = true;
6060 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6061 }
6062
6063 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6064 outinfo->writes_viewport_index = true;
6065 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6066 }
6067
6068 if (outinfo->writes_pointsize ||
6069 outinfo->writes_layer ||
6070 outinfo->writes_viewport_index) {
6071 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6072 (outinfo->writes_layer == true ? 4 : 0));
6073 pos_args[1].valid_mask = 0;
6074 pos_args[1].done = 0;
6075 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6076 pos_args[1].compr = 0;
6077 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6078 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6079 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6080 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6081
6082 if (outinfo->writes_pointsize == true)
6083 pos_args[1].out[0] = psize_value;
6084 if (outinfo->writes_layer == true)
6085 pos_args[1].out[2] = layer_value;
6086 if (outinfo->writes_viewport_index == true) {
6087 if (ctx->options->chip_class >= GFX9) {
6088 /* GFX9 has the layer in out.z[10:0] and the viewport
6089 * index in out.z[19:16].
6090 */
6091 LLVMValueRef v = viewport_index_value;
6092 v = ac_to_integer(&ctx->ac, v);
6093 v = LLVMBuildShl(ctx->ac.builder, v,
6094 LLVMConstInt(ctx->ac.i32, 16, false),
6095 "");
6096 v = LLVMBuildOr(ctx->ac.builder, v,
6097 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6098
6099 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6100 pos_args[1].enabled_channels |= 1 << 2;
6101 } else {
6102 pos_args[1].out[3] = viewport_index_value;
6103 pos_args[1].enabled_channels |= 1 << 3;
6104 }
6105 }
6106 }
6107 for (i = 0; i < 4; i++) {
6108 if (pos_args[i].out[0])
6109 num_pos_exports++;
6110 }
6111
6112 pos_idx = 0;
6113 for (i = 0; i < 4; i++) {
6114 if (!pos_args[i].out[0])
6115 continue;
6116
6117 /* Specify the target we are exporting */
6118 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6119 if (pos_idx == num_pos_exports)
6120 pos_args[i].done = 1;
6121 ac_build_export(&ctx->ac, &pos_args[i]);
6122 }
6123
6124 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6125 LLVMValueRef values[4];
6126 if (!(ctx->output_mask & (1ull << i)))
6127 continue;
6128
6129 if (i != VARYING_SLOT_LAYER &&
6130 i != VARYING_SLOT_PRIMITIVE_ID &&
6131 i < VARYING_SLOT_VAR0)
6132 continue;
6133
6134 for (unsigned j = 0; j < 4; j++)
6135 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6136
6137 radv_export_param(ctx, param_count, values);
6138
6139 outinfo->vs_output_param_offset[i] = param_count++;
6140 }
6141
6142 if (export_prim_id) {
6143 LLVMValueRef values[4];
6144
6145 values[0] = ctx->vs_prim_id;
6146 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6147 ctx->shader_info->vs.vgpr_comp_cnt);
6148 for (unsigned j = 1; j < 4; j++)
6149 values[j] = ctx->ac.f32_0;
6150
6151 radv_export_param(ctx, param_count, values);
6152
6153 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6154 outinfo->export_prim_id = true;
6155 }
6156
6157 outinfo->pos_exports = num_pos_exports;
6158 outinfo->param_exports = param_count;
6159 }
6160
6161 static void
6162 handle_es_outputs_post(struct radv_shader_context *ctx,
6163 struct ac_es_output_info *outinfo)
6164 {
6165 int j;
6166 uint64_t max_output_written = 0;
6167 LLVMValueRef lds_base = NULL;
6168
6169 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6170 int param_index;
6171 int length = 4;
6172
6173 if (!(ctx->output_mask & (1ull << i)))
6174 continue;
6175
6176 if (i == VARYING_SLOT_CLIP_DIST0)
6177 length = ctx->num_output_clips + ctx->num_output_culls;
6178
6179 param_index = shader_io_get_unique_index(i);
6180
6181 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6182 }
6183
6184 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6185
6186 if (ctx->ac.chip_class >= GFX9) {
6187 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6188 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6189 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6190 LLVMConstInt(ctx->ac.i32, 24, false),
6191 LLVMConstInt(ctx->ac.i32, 4, false), false);
6192 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6193 LLVMBuildMul(ctx->ac.builder, wave_idx,
6194 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6195 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6196 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6197 }
6198
6199 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6200 LLVMValueRef dw_addr = NULL;
6201 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6202 int param_index;
6203 int length = 4;
6204
6205 if (!(ctx->output_mask & (1ull << i)))
6206 continue;
6207
6208 if (i == VARYING_SLOT_CLIP_DIST0)
6209 length = ctx->num_output_clips + ctx->num_output_culls;
6210
6211 param_index = shader_io_get_unique_index(i);
6212
6213 if (lds_base) {
6214 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6215 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6216 "");
6217 }
6218 for (j = 0; j < length; j++) {
6219 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6220 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6221
6222 if (ctx->ac.chip_class >= GFX9) {
6223 ac_lds_store(&ctx->ac, dw_addr,
6224 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6225 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6226 } else {
6227 ac_build_buffer_store_dword(&ctx->ac,
6228 ctx->esgs_ring,
6229 out_val, 1,
6230 NULL, ctx->es2gs_offset,
6231 (4 * param_index + j) * 4,
6232 1, 1, true, true);
6233 }
6234 }
6235 }
6236 }
6237
6238 static void
6239 handle_ls_outputs_post(struct radv_shader_context *ctx)
6240 {
6241 LLVMValueRef vertex_id = ctx->rel_auto_id;
6242 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6243 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6244 vertex_dw_stride, "");
6245
6246 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6247 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6248 int length = 4;
6249
6250 if (!(ctx->output_mask & (1ull << i)))
6251 continue;
6252
6253 if (i == VARYING_SLOT_CLIP_DIST0)
6254 length = ctx->num_output_clips + ctx->num_output_culls;
6255 int param = shader_io_get_unique_index(i);
6256 mark_tess_output(ctx, false, param);
6257 if (length > 4)
6258 mark_tess_output(ctx, false, param + 1);
6259 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6260 LLVMConstInt(ctx->ac.i32, param * 4, false),
6261 "");
6262 for (unsigned j = 0; j < length; j++) {
6263 ac_lds_store(&ctx->ac, dw_addr,
6264 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6265 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6266 }
6267 }
6268 }
6269
6270 struct ac_build_if_state
6271 {
6272 struct radv_shader_context *ctx;
6273 LLVMValueRef condition;
6274 LLVMBasicBlockRef entry_block;
6275 LLVMBasicBlockRef true_block;
6276 LLVMBasicBlockRef false_block;
6277 LLVMBasicBlockRef merge_block;
6278 };
6279
6280 static LLVMBasicBlockRef
6281 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6282 {
6283 LLVMBasicBlockRef current_block;
6284 LLVMBasicBlockRef next_block;
6285 LLVMBasicBlockRef new_block;
6286
6287 /* get current basic block */
6288 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6289
6290 /* chqeck if there's another block after this one */
6291 next_block = LLVMGetNextBasicBlock(current_block);
6292 if (next_block) {
6293 /* insert the new block before the next block */
6294 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6295 }
6296 else {
6297 /* append new block after current block */
6298 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6299 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6300 }
6301 return new_block;
6302 }
6303
6304 static void
6305 ac_nir_build_if(struct ac_build_if_state *ifthen,
6306 struct radv_shader_context *ctx,
6307 LLVMValueRef condition)
6308 {
6309 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6310
6311 memset(ifthen, 0, sizeof *ifthen);
6312 ifthen->ctx = ctx;
6313 ifthen->condition = condition;
6314 ifthen->entry_block = block;
6315
6316 /* create endif/merge basic block for the phi functions */
6317 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6318
6319 /* create/insert true_block before merge_block */
6320 ifthen->true_block =
6321 LLVMInsertBasicBlockInContext(ctx->context,
6322 ifthen->merge_block,
6323 "if-true-block");
6324
6325 /* successive code goes into the true block */
6326 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6327 }
6328
6329 /**
6330 * End a conditional.
6331 */
6332 static void
6333 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6334 {
6335 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6336
6337 /* Insert branch to the merge block from current block */
6338 LLVMBuildBr(builder, ifthen->merge_block);
6339
6340 /*
6341 * Now patch in the various branch instructions.
6342 */
6343
6344 /* Insert the conditional branch instruction at the end of entry_block */
6345 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6346 if (ifthen->false_block) {
6347 /* we have an else clause */
6348 LLVMBuildCondBr(builder, ifthen->condition,
6349 ifthen->true_block, ifthen->false_block);
6350 }
6351 else {
6352 /* no else clause */
6353 LLVMBuildCondBr(builder, ifthen->condition,
6354 ifthen->true_block, ifthen->merge_block);
6355 }
6356
6357 /* Resume building code at end of the ifthen->merge_block */
6358 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6359 }
6360
6361 static void
6362 write_tess_factors(struct radv_shader_context *ctx)
6363 {
6364 unsigned stride, outer_comps, inner_comps;
6365 struct ac_build_if_state if_ctx, inner_if_ctx;
6366 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6367 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6368 unsigned tess_inner_index = 0, tess_outer_index;
6369 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
6370 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6371 int i;
6372 emit_barrier(&ctx->ac, ctx->stage);
6373
6374 switch (ctx->options->key.tcs.primitive_mode) {
6375 case GL_ISOLINES:
6376 stride = 2;
6377 outer_comps = 2;
6378 inner_comps = 0;
6379 break;
6380 case GL_TRIANGLES:
6381 stride = 4;
6382 outer_comps = 3;
6383 inner_comps = 1;
6384 break;
6385 case GL_QUADS:
6386 stride = 6;
6387 outer_comps = 4;
6388 inner_comps = 2;
6389 break;
6390 default:
6391 return;
6392 }
6393
6394 ac_nir_build_if(&if_ctx, ctx,
6395 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6396 invocation_id, ctx->ac.i32_0, ""));
6397
6398 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6399
6400 if (inner_comps) {
6401 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6402 mark_tess_output(ctx, true, tess_inner_index);
6403 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6404 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6405 }
6406
6407 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6408 mark_tess_output(ctx, true, tess_outer_index);
6409 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6410 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6411
6412 for (i = 0; i < 4; i++) {
6413 inner[i] = LLVMGetUndef(ctx->ac.i32);
6414 outer[i] = LLVMGetUndef(ctx->ac.i32);
6415 }
6416
6417 // LINES reverseal
6418 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6419 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6420 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6421 ctx->ac.i32_1, "");
6422 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6423 } else {
6424 for (i = 0; i < outer_comps; i++) {
6425 outer[i] = out[i] =
6426 ac_lds_load(&ctx->ac, lds_outer);
6427 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6428 ctx->ac.i32_1, "");
6429 }
6430 for (i = 0; i < inner_comps; i++) {
6431 inner[i] = out[outer_comps+i] =
6432 ac_lds_load(&ctx->ac, lds_inner);
6433 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6434 ctx->ac.i32_1, "");
6435 }
6436 }
6437
6438 /* Convert the outputs to vectors for stores. */
6439 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6440 vec1 = NULL;
6441
6442 if (stride > 4)
6443 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6444
6445
6446 buffer = ctx->hs_ring_tess_factor;
6447 tf_base = ctx->tess_factor_offset;
6448 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6449 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6450 unsigned tf_offset = 0;
6451
6452 if (ctx->options->chip_class <= VI) {
6453 ac_nir_build_if(&inner_if_ctx, ctx,
6454 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6455 rel_patch_id, ctx->ac.i32_0, ""));
6456
6457 /* Store the dynamic HS control word. */
6458 ac_build_buffer_store_dword(&ctx->ac, buffer,
6459 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6460 1, ctx->ac.i32_0, tf_base,
6461 0, 1, 0, true, false);
6462 tf_offset += 4;
6463
6464 ac_nir_build_endif(&inner_if_ctx);
6465 }
6466
6467 /* Store the tessellation factors. */
6468 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6469 MIN2(stride, 4), byteoffset, tf_base,
6470 tf_offset, 1, 0, true, false);
6471 if (vec1)
6472 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6473 stride - 4, byteoffset, tf_base,
6474 16 + tf_offset, 1, 0, true, false);
6475
6476 //store to offchip for TES to read - only if TES reads them
6477 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6478 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6479 LLVMValueRef tf_inner_offset;
6480 unsigned param_outer, param_inner;
6481
6482 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6483 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6484 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6485
6486 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6487 util_next_power_of_two(outer_comps));
6488
6489 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6490 outer_comps, tf_outer_offset,
6491 ctx->oc_lds, 0, 1, 0, true, false);
6492 if (inner_comps) {
6493 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6494 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6495 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6496
6497 inner_vec = inner_comps == 1 ? inner[0] :
6498 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6499 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6500 inner_comps, tf_inner_offset,
6501 ctx->oc_lds, 0, 1, 0, true, false);
6502 }
6503 }
6504 ac_nir_build_endif(&if_ctx);
6505 }
6506
6507 static void
6508 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6509 {
6510 write_tess_factors(ctx);
6511 }
6512
6513 static bool
6514 si_export_mrt_color(struct radv_shader_context *ctx,
6515 LLVMValueRef *color, unsigned index, bool is_last,
6516 struct ac_export_args *args)
6517 {
6518 /* Export */
6519 si_llvm_init_export_args(ctx, color,
6520 V_008DFC_SQ_EXP_MRT + index, args);
6521
6522 if (is_last) {
6523 args->valid_mask = 1; /* whether the EXEC mask is valid */
6524 args->done = 1; /* DONE bit */
6525 } else if (!args->enabled_channels)
6526 return false; /* unnecessary NULL export */
6527
6528 return true;
6529 }
6530
6531 static void
6532 radv_export_mrt_z(struct radv_shader_context *ctx,
6533 LLVMValueRef depth, LLVMValueRef stencil,
6534 LLVMValueRef samplemask)
6535 {
6536 struct ac_export_args args;
6537
6538 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6539
6540 ac_build_export(&ctx->ac, &args);
6541 }
6542
6543 static void
6544 handle_fs_outputs_post(struct radv_shader_context *ctx)
6545 {
6546 unsigned index = 0;
6547 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6548 struct ac_export_args color_args[8];
6549
6550 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6551 LLVMValueRef values[4];
6552 bool last = false;
6553
6554 if (!(ctx->output_mask & (1ull << i)))
6555 continue;
6556
6557 if (i < FRAG_RESULT_DATA0)
6558 continue;
6559
6560 for (unsigned j = 0; j < 4; j++)
6561 values[j] = ac_to_float(&ctx->ac,
6562 radv_load_output(ctx, i, j));
6563
6564 if (!ctx->shader_info->info.ps.writes_z &&
6565 !ctx->shader_info->info.ps.writes_stencil &&
6566 !ctx->shader_info->info.ps.writes_sample_mask)
6567 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6568
6569 bool ret = si_export_mrt_color(ctx, values,
6570 i - FRAG_RESULT_DATA0,
6571 last, &color_args[index]);
6572 if (ret)
6573 index++;
6574 }
6575
6576 /* Process depth, stencil, samplemask. */
6577 if (ctx->shader_info->info.ps.writes_z) {
6578 depth = ac_to_float(&ctx->ac,
6579 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6580 }
6581 if (ctx->shader_info->info.ps.writes_stencil) {
6582 stencil = ac_to_float(&ctx->ac,
6583 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6584 }
6585 if (ctx->shader_info->info.ps.writes_sample_mask) {
6586 samplemask = ac_to_float(&ctx->ac,
6587 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6588 }
6589
6590 /* Export PS outputs. */
6591 for (unsigned i = 0; i < index; i++)
6592 ac_build_export(&ctx->ac, &color_args[i]);
6593
6594 if (depth || stencil || samplemask)
6595 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6596 else if (!index)
6597 ac_build_export_null(&ctx->ac);
6598 }
6599
6600 static void
6601 emit_gs_epilogue(struct radv_shader_context *ctx)
6602 {
6603 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6604 }
6605
6606 static void
6607 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6608 LLVMValueRef *addrs)
6609 {
6610 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6611
6612 switch (ctx->stage) {
6613 case MESA_SHADER_VERTEX:
6614 if (ctx->options->key.vs.as_ls)
6615 handle_ls_outputs_post(ctx);
6616 else if (ctx->options->key.vs.as_es)
6617 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6618 else
6619 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6620 &ctx->shader_info->vs.outinfo);
6621 break;
6622 case MESA_SHADER_FRAGMENT:
6623 handle_fs_outputs_post(ctx);
6624 break;
6625 case MESA_SHADER_GEOMETRY:
6626 emit_gs_epilogue(ctx);
6627 break;
6628 case MESA_SHADER_TESS_CTRL:
6629 handle_tcs_outputs_post(ctx);
6630 break;
6631 case MESA_SHADER_TESS_EVAL:
6632 if (ctx->options->key.tes.as_es)
6633 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6634 else
6635 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6636 &ctx->shader_info->tes.outinfo);
6637 break;
6638 default:
6639 break;
6640 }
6641 }
6642
6643 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6644 {
6645 LLVMPassManagerRef passmgr;
6646 /* Create the pass manager */
6647 passmgr = LLVMCreateFunctionPassManagerForModule(
6648 ctx->ac.module);
6649
6650 /* This pass should eliminate all the load and store instructions */
6651 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6652
6653 /* Add some optimization passes */
6654 LLVMAddScalarReplAggregatesPass(passmgr);
6655 LLVMAddLICMPass(passmgr);
6656 LLVMAddAggressiveDCEPass(passmgr);
6657 LLVMAddCFGSimplificationPass(passmgr);
6658 LLVMAddInstructionCombiningPass(passmgr);
6659
6660 /* Run the pass */
6661 LLVMInitializeFunctionPassManager(passmgr);
6662 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6663 LLVMFinalizeFunctionPassManager(passmgr);
6664
6665 LLVMDisposeBuilder(ctx->ac.builder);
6666 LLVMDisposePassManager(passmgr);
6667 }
6668
6669 static void
6670 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6671 {
6672 struct ac_vs_output_info *outinfo;
6673
6674 switch (ctx->stage) {
6675 case MESA_SHADER_FRAGMENT:
6676 case MESA_SHADER_COMPUTE:
6677 case MESA_SHADER_TESS_CTRL:
6678 case MESA_SHADER_GEOMETRY:
6679 return;
6680 case MESA_SHADER_VERTEX:
6681 if (ctx->options->key.vs.as_ls ||
6682 ctx->options->key.vs.as_es)
6683 return;
6684 outinfo = &ctx->shader_info->vs.outinfo;
6685 break;
6686 case MESA_SHADER_TESS_EVAL:
6687 if (ctx->options->key.vs.as_es)
6688 return;
6689 outinfo = &ctx->shader_info->tes.outinfo;
6690 break;
6691 default:
6692 unreachable("Unhandled shader type");
6693 }
6694
6695 ac_optimize_vs_outputs(&ctx->ac,
6696 ctx->main_function,
6697 outinfo->vs_output_param_offset,
6698 VARYING_SLOT_MAX,
6699 &outinfo->param_exports);
6700 }
6701
6702 static void
6703 ac_setup_rings(struct radv_shader_context *ctx)
6704 {
6705 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6706 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6707 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6708 }
6709
6710 if (ctx->is_gs_copy_shader) {
6711 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6712 }
6713 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6714 LLVMValueRef tmp;
6715 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6716 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6717
6718 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6719
6720 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6721 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6722 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6723 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6724 }
6725
6726 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6727 ctx->stage == MESA_SHADER_TESS_EVAL) {
6728 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6729 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6730 }
6731 }
6732
6733 static unsigned
6734 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6735 const struct nir_shader *nir)
6736 {
6737 switch (nir->info.stage) {
6738 case MESA_SHADER_TESS_CTRL:
6739 return chip_class >= CIK ? 128 : 64;
6740 case MESA_SHADER_GEOMETRY:
6741 return chip_class >= GFX9 ? 128 : 64;
6742 case MESA_SHADER_COMPUTE:
6743 break;
6744 default:
6745 return 0;
6746 }
6747
6748 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6749 nir->info.cs.local_size[1] *
6750 nir->info.cs.local_size[2];
6751 return max_workgroup_size;
6752 }
6753
6754 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6755 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6756 {
6757 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6758 LLVMConstInt(ctx->ac.i32, 8, false),
6759 LLVMConstInt(ctx->ac.i32, 8, false), false);
6760 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6761 ctx->ac.i32_0, "");
6762 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6763 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6764 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6765 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6766 }
6767
6768 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6769 {
6770 for(int i = 5; i >= 0; --i) {
6771 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6772 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6773 LLVMConstInt(ctx->ac.i32, 16, false), false);
6774 }
6775
6776 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6777 LLVMConstInt(ctx->ac.i32, 16, false),
6778 LLVMConstInt(ctx->ac.i32, 8, false), false);
6779 }
6780
6781 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6782 struct nir_shader *nir)
6783 {
6784 struct ac_nir_context ctx = {};
6785 struct nir_function *func;
6786
6787 ctx.ac = *ac;
6788 ctx.abi = abi;
6789
6790 ctx.stage = nir->info.stage;
6791
6792 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6793
6794 nir_foreach_variable(variable, &nir->outputs)
6795 handle_shader_output_decl(&ctx, nir, variable);
6796
6797 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6798 _mesa_key_pointer_equal);
6799 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6800 _mesa_key_pointer_equal);
6801 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6802 _mesa_key_pointer_equal);
6803
6804 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6805
6806 setup_locals(&ctx, func);
6807
6808 if (nir->info.stage == MESA_SHADER_COMPUTE)
6809 setup_shared(&ctx, nir);
6810
6811 visit_cf_list(&ctx, &func->impl->body);
6812 phi_post_pass(&ctx);
6813
6814 if (nir->info.stage != MESA_SHADER_COMPUTE)
6815 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6816 ctx.abi->outputs);
6817
6818 free(ctx.locals);
6819 ralloc_free(ctx.defs);
6820 ralloc_free(ctx.phis);
6821 ralloc_free(ctx.vars);
6822 }
6823
6824 static
6825 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6826 struct nir_shader *const *shaders,
6827 int shader_count,
6828 struct ac_shader_variant_info *shader_info,
6829 const struct ac_nir_compiler_options *options)
6830 {
6831 struct radv_shader_context ctx = {0};
6832 unsigned i;
6833 ctx.options = options;
6834 ctx.shader_info = shader_info;
6835 ctx.context = LLVMContextCreate();
6836
6837 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6838 options->family);
6839 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6840 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6841
6842 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6843 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6844 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6845 LLVMDisposeTargetData(data_layout);
6846 LLVMDisposeMessage(data_layout_str);
6847
6848 enum ac_float_mode float_mode =
6849 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6850 AC_FLOAT_MODE_DEFAULT;
6851
6852 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6853
6854 memset(shader_info, 0, sizeof(*shader_info));
6855
6856 for(int i = 0; i < shader_count; ++i)
6857 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6858
6859 for (i = 0; i < AC_UD_MAX_SETS; i++)
6860 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6861 for (i = 0; i < AC_UD_MAX_UD; i++)
6862 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6863
6864 ctx.max_workgroup_size = 0;
6865 for (int i = 0; i < shader_count; ++i) {
6866 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6867 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6868 shaders[i]));
6869 }
6870
6871 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6872 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6873
6874 ctx.abi.inputs = &ctx.inputs[0];
6875 ctx.abi.emit_outputs = handle_shader_outputs_post;
6876 ctx.abi.emit_vertex = visit_emit_vertex;
6877 ctx.abi.load_ubo = radv_load_ubo;
6878 ctx.abi.load_ssbo = radv_load_ssbo;
6879 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6880 ctx.abi.load_resource = radv_load_resource;
6881 ctx.abi.clamp_shadow_reference = false;
6882
6883 if (shader_count >= 2)
6884 ac_init_exec_full_mask(&ctx.ac);
6885
6886 if (ctx.ac.chip_class == GFX9 &&
6887 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6888 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6889
6890 for(int i = 0; i < shader_count; ++i) {
6891 ctx.stage = shaders[i]->info.stage;
6892 ctx.output_mask = 0;
6893 ctx.tess_outputs_written = 0;
6894 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6895 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6896
6897 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6898 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6899 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6900 ctx.abi.load_inputs = load_gs_input;
6901 ctx.abi.emit_primitive = visit_end_primitive;
6902 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6903 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6904 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6905 ctx.abi.load_tess_varyings = load_tcs_varyings;
6906 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6907 ctx.abi.store_tcs_outputs = store_tcs_output;
6908 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6909 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6910 ctx.abi.load_tess_varyings = load_tes_input;
6911 ctx.abi.load_tess_coord = load_tess_coord;
6912 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6913 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6914 if (shader_info->info.vs.needs_instance_id) {
6915 if (ctx.options->key.vs.as_ls) {
6916 ctx.shader_info->vs.vgpr_comp_cnt =
6917 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6918 } else {
6919 ctx.shader_info->vs.vgpr_comp_cnt =
6920 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6921 }
6922 }
6923 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6924 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6925 ctx.abi.lookup_interp_param = lookup_interp_param;
6926 ctx.abi.load_sample_position = load_sample_position;
6927 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6928 }
6929
6930 if (i)
6931 emit_barrier(&ctx.ac, ctx.stage);
6932
6933 ac_setup_rings(&ctx);
6934
6935 LLVMBasicBlockRef merge_block;
6936 if (shader_count >= 2) {
6937 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6938 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6939 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6940
6941 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6942 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6943 LLVMConstInt(ctx.ac.i32, 8, false), false);
6944 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6945 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6946 thread_id, count, "");
6947 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6948
6949 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6950 }
6951
6952 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6953 handle_fs_inputs(&ctx, shaders[i]);
6954 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6955 handle_vs_inputs(&ctx, shaders[i]);
6956 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6957 prepare_gs_input_vgprs(&ctx);
6958
6959 nir_foreach_variable(variable, &shaders[i]->outputs)
6960 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6961
6962 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6963
6964 if (shader_count >= 2) {
6965 LLVMBuildBr(ctx.ac.builder, merge_block);
6966 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6967 }
6968
6969 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6970 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6971 shaders[i]->info.cull_distance_array_size > 4;
6972 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6973 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6974 shaders[i]->info.gs.vertices_out;
6975 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6976 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6977 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6978 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6979 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6980 }
6981 }
6982
6983 LLVMBuildRetVoid(ctx.ac.builder);
6984
6985 if (options->dump_preoptir)
6986 ac_dump_module(ctx.ac.module);
6987
6988 ac_llvm_finalize_module(&ctx);
6989
6990 if (shader_count == 1)
6991 ac_nir_eliminate_const_vs_outputs(&ctx);
6992
6993 return ctx.ac.module;
6994 }
6995
6996 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6997 {
6998 unsigned *retval = (unsigned *)context;
6999 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
7000 char *description = LLVMGetDiagInfoDescription(di);
7001
7002 if (severity == LLVMDSError) {
7003 *retval = 1;
7004 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
7005 description);
7006 }
7007
7008 LLVMDisposeMessage(description);
7009 }
7010
7011 static unsigned ac_llvm_compile(LLVMModuleRef M,
7012 struct ac_shader_binary *binary,
7013 LLVMTargetMachineRef tm)
7014 {
7015 unsigned retval = 0;
7016 char *err;
7017 LLVMContextRef llvm_ctx;
7018 LLVMMemoryBufferRef out_buffer;
7019 unsigned buffer_size;
7020 const char *buffer_data;
7021 LLVMBool mem_err;
7022
7023 /* Setup Diagnostic Handler*/
7024 llvm_ctx = LLVMGetModuleContext(M);
7025
7026 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
7027 &retval);
7028
7029 /* Compile IR*/
7030 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
7031 &err, &out_buffer);
7032
7033 /* Process Errors/Warnings */
7034 if (mem_err) {
7035 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7036 free(err);
7037 retval = 1;
7038 goto out;
7039 }
7040
7041 /* Extract Shader Code*/
7042 buffer_size = LLVMGetBufferSize(out_buffer);
7043 buffer_data = LLVMGetBufferStart(out_buffer);
7044
7045 ac_elf_read(buffer_data, buffer_size, binary);
7046
7047 /* Clean up */
7048 LLVMDisposeMemoryBuffer(out_buffer);
7049
7050 out:
7051 return retval;
7052 }
7053
7054 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7055 LLVMModuleRef llvm_module,
7056 struct ac_shader_binary *binary,
7057 struct ac_shader_config *config,
7058 struct ac_shader_variant_info *shader_info,
7059 gl_shader_stage stage,
7060 bool dump_shader, bool supports_spill)
7061 {
7062 if (dump_shader)
7063 ac_dump_module(llvm_module);
7064
7065 memset(binary, 0, sizeof(*binary));
7066 int v = ac_llvm_compile(llvm_module, binary, tm);
7067 if (v) {
7068 fprintf(stderr, "compile failed\n");
7069 }
7070
7071 if (dump_shader)
7072 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7073
7074 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7075
7076 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7077 LLVMDisposeModule(llvm_module);
7078 LLVMContextDispose(ctx);
7079
7080 if (stage == MESA_SHADER_FRAGMENT) {
7081 shader_info->num_input_vgprs = 0;
7082 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7083 shader_info->num_input_vgprs += 2;
7084 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7085 shader_info->num_input_vgprs += 2;
7086 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7087 shader_info->num_input_vgprs += 2;
7088 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7089 shader_info->num_input_vgprs += 3;
7090 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7091 shader_info->num_input_vgprs += 2;
7092 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7093 shader_info->num_input_vgprs += 2;
7094 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7095 shader_info->num_input_vgprs += 2;
7096 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7097 shader_info->num_input_vgprs += 1;
7098 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7099 shader_info->num_input_vgprs += 1;
7100 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7101 shader_info->num_input_vgprs += 1;
7102 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7103 shader_info->num_input_vgprs += 1;
7104 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7105 shader_info->num_input_vgprs += 1;
7106 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7107 shader_info->num_input_vgprs += 1;
7108 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7109 shader_info->num_input_vgprs += 1;
7110 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7111 shader_info->num_input_vgprs += 1;
7112 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7113 shader_info->num_input_vgprs += 1;
7114 }
7115 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7116
7117 /* +3 for scratch wave offset and VCC */
7118 config->num_sgprs = MAX2(config->num_sgprs,
7119 shader_info->num_input_sgprs + 3);
7120
7121 /* Enable 64-bit and 16-bit denormals, because there is no performance
7122 * cost.
7123 *
7124 * If denormals are enabled, all floating-point output modifiers are
7125 * ignored.
7126 *
7127 * Don't enable denormals for 32-bit floats, because:
7128 * - Floating-point output modifiers would be ignored by the hw.
7129 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7130 * have to stop using those.
7131 * - SI & CI would be very slow.
7132 */
7133 config->float_mode |= V_00B028_FP_64_DENORMS;
7134 }
7135
7136 static void
7137 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7138 {
7139 switch (nir->info.stage) {
7140 case MESA_SHADER_COMPUTE:
7141 for (int i = 0; i < 3; ++i)
7142 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7143 break;
7144 case MESA_SHADER_FRAGMENT:
7145 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7146 break;
7147 case MESA_SHADER_GEOMETRY:
7148 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7149 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7150 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7151 shader_info->gs.invocations = nir->info.gs.invocations;
7152 break;
7153 case MESA_SHADER_TESS_EVAL:
7154 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7155 shader_info->tes.spacing = nir->info.tess.spacing;
7156 shader_info->tes.ccw = nir->info.tess.ccw;
7157 shader_info->tes.point_mode = nir->info.tess.point_mode;
7158 shader_info->tes.as_es = options->key.tes.as_es;
7159 break;
7160 case MESA_SHADER_TESS_CTRL:
7161 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7162 break;
7163 case MESA_SHADER_VERTEX:
7164 shader_info->vs.as_es = options->key.vs.as_es;
7165 shader_info->vs.as_ls = options->key.vs.as_ls;
7166 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7167 if (options->key.vs.as_ls)
7168 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7169 break;
7170 default:
7171 break;
7172 }
7173 }
7174
7175 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7176 struct ac_shader_binary *binary,
7177 struct ac_shader_config *config,
7178 struct ac_shader_variant_info *shader_info,
7179 struct nir_shader *const *nir,
7180 int nir_count,
7181 const struct ac_nir_compiler_options *options,
7182 bool dump_shader)
7183 {
7184
7185 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7186 options);
7187
7188 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7189 for (int i = 0; i < nir_count; ++i)
7190 ac_fill_shader_info(shader_info, nir[i], options);
7191
7192 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7193 if (options->chip_class == GFX9) {
7194 if (nir_count == 2 &&
7195 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7196 shader_info->gs.es_type = nir[0]->info.stage;
7197 }
7198 }
7199 }
7200
7201 static void
7202 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7203 {
7204 LLVMValueRef vtx_offset =
7205 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7206 LLVMConstInt(ctx->ac.i32, 4, false), "");
7207 int idx = 0;
7208
7209 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7210 int length = 4;
7211 int slot = idx;
7212 int slot_inc = 1;
7213 if (!(ctx->output_mask & (1ull << i)))
7214 continue;
7215
7216 if (i == VARYING_SLOT_CLIP_DIST0) {
7217 /* unpack clip and cull from a single set of slots */
7218 length = ctx->num_output_clips + ctx->num_output_culls;
7219 if (length > 4)
7220 slot_inc = 2;
7221 }
7222
7223 for (unsigned j = 0; j < length; j++) {
7224 LLVMValueRef value, soffset;
7225
7226 soffset = LLVMConstInt(ctx->ac.i32,
7227 (slot * 4 + j) *
7228 ctx->gs_max_out_vertices * 16 * 4, false);
7229
7230 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7231 1, ctx->ac.i32_0,
7232 vtx_offset, soffset,
7233 0, 1, 1, true, false);
7234
7235 LLVMBuildStore(ctx->ac.builder,
7236 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7237 }
7238 idx += slot_inc;
7239 }
7240 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7241 }
7242
7243 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7244 struct nir_shader *geom_shader,
7245 struct ac_shader_binary *binary,
7246 struct ac_shader_config *config,
7247 struct ac_shader_variant_info *shader_info,
7248 const struct ac_nir_compiler_options *options,
7249 bool dump_shader)
7250 {
7251 struct radv_shader_context ctx = {0};
7252 ctx.context = LLVMContextCreate();
7253 ctx.options = options;
7254 ctx.shader_info = shader_info;
7255
7256 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7257 options->family);
7258 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7259
7260 ctx.is_gs_copy_shader = true;
7261 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7262
7263 enum ac_float_mode float_mode =
7264 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7265 AC_FLOAT_MODE_DEFAULT;
7266
7267 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7268 ctx.stage = MESA_SHADER_VERTEX;
7269
7270 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7271
7272 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7273 ac_setup_rings(&ctx);
7274
7275 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7276 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7277
7278 struct ac_nir_context nir_ctx = {};
7279 nir_ctx.ac = ctx.ac;
7280 nir_ctx.abi = &ctx.abi;
7281
7282 nir_foreach_variable(variable, &geom_shader->outputs) {
7283 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7284 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7285 }
7286
7287 ac_gs_copy_shader_emit(&ctx);
7288
7289 LLVMBuildRetVoid(ctx.ac.builder);
7290
7291 ac_llvm_finalize_module(&ctx);
7292
7293 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7294 MESA_SHADER_VERTEX,
7295 dump_shader, options->supports_spill);
7296 }