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ac/nir: assign argument param pointers in one place.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 #include "ac_exp_param.h"
35
36 enum radeon_llvm_calling_convention {
37 RADEON_LLVM_AMDGPU_VS = 87,
38 RADEON_LLVM_AMDGPU_GS = 88,
39 RADEON_LLVM_AMDGPU_PS = 89,
40 RADEON_LLVM_AMDGPU_CS = 90,
41 };
42
43 #define CONST_ADDR_SPACE 2
44 #define LOCAL_ADDR_SPACE 3
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 enum desc_type {
50 DESC_IMAGE,
51 DESC_FMASK,
52 DESC_SAMPLER,
53 DESC_BUFFER,
54 };
55
56 struct nir_to_llvm_context {
57 struct ac_llvm_context ac;
58 const struct ac_nir_compiler_options *options;
59 struct ac_shader_variant_info *shader_info;
60 unsigned max_workgroup_size;
61 LLVMContextRef context;
62 LLVMModuleRef module;
63 LLVMBuilderRef builder;
64 LLVMValueRef main_function;
65
66 struct hash_table *defs;
67 struct hash_table *phis;
68
69 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
70 LLVMValueRef ring_offsets;
71 LLVMValueRef push_constants;
72 LLVMValueRef num_work_groups;
73 LLVMValueRef workgroup_ids;
74 LLVMValueRef local_invocation_ids;
75 LLVMValueRef tg_size;
76
77 LLVMValueRef vertex_buffers;
78 LLVMValueRef base_vertex;
79 LLVMValueRef start_instance;
80 LLVMValueRef draw_index;
81 LLVMValueRef vertex_id;
82 LLVMValueRef rel_auto_id;
83 LLVMValueRef vs_prim_id;
84 LLVMValueRef instance_id;
85 LLVMValueRef ls_out_layout;
86 LLVMValueRef es2gs_offset;
87
88 LLVMValueRef tcs_offchip_layout;
89 LLVMValueRef tcs_out_offsets;
90 LLVMValueRef tcs_out_layout;
91 LLVMValueRef tcs_in_layout;
92 LLVMValueRef oc_lds;
93 LLVMValueRef tess_factor_offset;
94 LLVMValueRef tcs_patch_id;
95 LLVMValueRef tcs_rel_ids;
96 LLVMValueRef tes_rel_patch_id;
97 LLVMValueRef tes_patch_id;
98 LLVMValueRef tes_u;
99 LLVMValueRef tes_v;
100
101 LLVMValueRef gsvs_ring_stride;
102 LLVMValueRef gsvs_num_entries;
103 LLVMValueRef gs2vs_offset;
104 LLVMValueRef gs_wave_id;
105 LLVMValueRef gs_vtx_offset[6];
106 LLVMValueRef gs_prim_id, gs_invocation_id;
107
108 LLVMValueRef esgs_ring;
109 LLVMValueRef gsvs_ring;
110 LLVMValueRef hs_ring_tess_offchip;
111 LLVMValueRef hs_ring_tess_factor;
112
113 LLVMValueRef prim_mask;
114 LLVMValueRef sample_pos_offset;
115 LLVMValueRef persp_sample, persp_center, persp_centroid;
116 LLVMValueRef linear_sample, linear_center, linear_centroid;
117 LLVMValueRef front_face;
118 LLVMValueRef ancillary;
119 LLVMValueRef sample_coverage;
120 LLVMValueRef frag_pos[4];
121
122 LLVMBasicBlockRef continue_block;
123 LLVMBasicBlockRef break_block;
124
125 LLVMTypeRef i1;
126 LLVMTypeRef i8;
127 LLVMTypeRef i16;
128 LLVMTypeRef i32;
129 LLVMTypeRef i64;
130 LLVMTypeRef v2i32;
131 LLVMTypeRef v3i32;
132 LLVMTypeRef v4i32;
133 LLVMTypeRef v8i32;
134 LLVMTypeRef f64;
135 LLVMTypeRef f32;
136 LLVMTypeRef f16;
137 LLVMTypeRef v2f32;
138 LLVMTypeRef v4f32;
139 LLVMTypeRef v16i8;
140 LLVMTypeRef voidt;
141
142 LLVMValueRef i1true;
143 LLVMValueRef i1false;
144 LLVMValueRef i32zero;
145 LLVMValueRef i32one;
146 LLVMValueRef f32zero;
147 LLVMValueRef f32one;
148 LLVMValueRef v4f32empty;
149
150 unsigned uniform_md_kind;
151 LLVMValueRef empty_md;
152 gl_shader_stage stage;
153
154 LLVMValueRef lds;
155 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
156 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
157
158 LLVMValueRef shared_memory;
159 uint64_t input_mask;
160 uint64_t output_mask;
161 int num_locals;
162 LLVMValueRef *locals;
163 bool has_ddxy;
164 uint8_t num_output_clips;
165 uint8_t num_output_culls;
166
167 bool has_ds_bpermute;
168
169 bool is_gs_copy_shader;
170 LLVMValueRef gs_next_vertex;
171 unsigned gs_max_out_vertices;
172
173 unsigned tes_primitive_mode;
174 uint64_t tess_outputs_written;
175 uint64_t tess_patch_outputs_written;
176 };
177
178 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
179 nir_deref_var *deref,
180 enum desc_type desc_type);
181 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
182 {
183 return (index * 4) + chan;
184 }
185
186 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
187 {
188 /* handle patch indices separate */
189 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
190 return 0;
191 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
192 return 1;
193 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
194 return 2 + (slot - VARYING_SLOT_PATCH0);
195
196 if (slot == VARYING_SLOT_POS)
197 return 0;
198 if (slot == VARYING_SLOT_PSIZ)
199 return 1;
200 if (slot == VARYING_SLOT_CLIP_DIST0)
201 return 2;
202 /* 3 is reserved for clip dist as well */
203 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
204 return 4 + (slot - VARYING_SLOT_VAR0);
205 unreachable("illegal slot in get unique index\n");
206 }
207
208 static unsigned llvm_get_type_size(LLVMTypeRef type)
209 {
210 LLVMTypeKind kind = LLVMGetTypeKind(type);
211
212 switch (kind) {
213 case LLVMIntegerTypeKind:
214 return LLVMGetIntTypeWidth(type) / 8;
215 case LLVMFloatTypeKind:
216 return 4;
217 case LLVMPointerTypeKind:
218 return 8;
219 case LLVMVectorTypeKind:
220 return LLVMGetVectorSize(type) *
221 llvm_get_type_size(LLVMGetElementType(type));
222 default:
223 assert(0);
224 return 0;
225 }
226 }
227
228 static void set_llvm_calling_convention(LLVMValueRef func,
229 gl_shader_stage stage)
230 {
231 enum radeon_llvm_calling_convention calling_conv;
232
233 switch (stage) {
234 case MESA_SHADER_VERTEX:
235 case MESA_SHADER_TESS_CTRL:
236 case MESA_SHADER_TESS_EVAL:
237 calling_conv = RADEON_LLVM_AMDGPU_VS;
238 break;
239 case MESA_SHADER_GEOMETRY:
240 calling_conv = RADEON_LLVM_AMDGPU_GS;
241 break;
242 case MESA_SHADER_FRAGMENT:
243 calling_conv = RADEON_LLVM_AMDGPU_PS;
244 break;
245 case MESA_SHADER_COMPUTE:
246 calling_conv = RADEON_LLVM_AMDGPU_CS;
247 break;
248 default:
249 unreachable("Unhandle shader type");
250 }
251
252 LLVMSetFunctionCallConv(func, calling_conv);
253 }
254
255 #define MAX_ARGS 23
256 struct arg_info {
257 LLVMTypeRef types[MAX_ARGS];
258 LLVMValueRef *assign[MAX_ARGS];
259 unsigned array_params_mask;
260 uint8_t count;
261 uint8_t user_sgpr_count;
262 uint8_t sgpr_count;
263 };
264
265 static inline void
266 add_argument(struct arg_info *info,
267 LLVMTypeRef type, LLVMValueRef *param_ptr)
268 {
269 assert(info->count < MAX_ARGS);
270 info->assign[info->count] = param_ptr;
271 info->types[info->count] = type;
272 info->count++;
273 }
274
275 static inline void
276 add_sgpr_argument(struct arg_info *info,
277 LLVMTypeRef type, LLVMValueRef *param_ptr)
278 {
279 add_argument(info, type, param_ptr);
280 info->sgpr_count++;
281 }
282
283 static inline void
284 add_user_sgpr_argument(struct arg_info *info,
285 LLVMTypeRef type,
286 LLVMValueRef *param_ptr)
287 {
288 add_sgpr_argument(info, type, param_ptr);
289 info->user_sgpr_count++;
290 }
291
292 static inline void
293 add_vgpr_argument(struct arg_info *info,
294 LLVMTypeRef type,
295 LLVMValueRef *param_ptr)
296 {
297 add_argument(info, type, param_ptr);
298 }
299
300 static inline void
301 add_user_sgpr_array_argument(struct arg_info *info,
302 LLVMTypeRef type,
303 LLVMValueRef *param_ptr)
304 {
305 info->array_params_mask |= (1 << info->count);
306 add_user_sgpr_argument(info, type, param_ptr);
307 }
308
309 static void assign_arguments(LLVMValueRef main_function,
310 struct arg_info *info)
311 {
312 unsigned i;
313 for (i = 0; i < info->count; i++) {
314 if (info->assign[i])
315 *info->assign[i] = LLVMGetParam(main_function, i);
316 }
317 }
318
319 static LLVMValueRef
320 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
321 LLVMBuilderRef builder, LLVMTypeRef *return_types,
322 unsigned num_return_elems,
323 struct arg_info *args,
324 unsigned max_workgroup_size,
325 bool unsafe_math)
326 {
327 LLVMTypeRef main_function_type, ret_type;
328 LLVMBasicBlockRef main_function_body;
329
330 if (num_return_elems)
331 ret_type = LLVMStructTypeInContext(ctx, return_types,
332 num_return_elems, true);
333 else
334 ret_type = LLVMVoidTypeInContext(ctx);
335
336 /* Setup the function */
337 main_function_type =
338 LLVMFunctionType(ret_type, args->types, args->count, 0);
339 LLVMValueRef main_function =
340 LLVMAddFunction(module, "main", main_function_type);
341 main_function_body =
342 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
343 LLVMPositionBuilderAtEnd(builder, main_function_body);
344
345 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
346 for (unsigned i = 0; i < args->sgpr_count; ++i) {
347 if (args->array_params_mask & (1 << i)) {
348 LLVMValueRef P = LLVMGetParam(main_function, i);
349 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
350 ac_add_attr_dereferenceable(P, UINT64_MAX);
351 }
352 else {
353 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
354 }
355 }
356
357 if (max_workgroup_size) {
358 ac_llvm_add_target_dep_function_attr(main_function,
359 "amdgpu-max-work-group-size",
360 max_workgroup_size);
361 }
362 if (unsafe_math) {
363 /* These were copied from some LLVM test. */
364 LLVMAddTargetDependentFunctionAttr(main_function,
365 "less-precise-fpmad",
366 "true");
367 LLVMAddTargetDependentFunctionAttr(main_function,
368 "no-infs-fp-math",
369 "true");
370 LLVMAddTargetDependentFunctionAttr(main_function,
371 "no-nans-fp-math",
372 "true");
373 LLVMAddTargetDependentFunctionAttr(main_function,
374 "unsafe-fp-math",
375 "true");
376 }
377 return main_function;
378 }
379
380 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
381 {
382 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
383 CONST_ADDR_SPACE);
384 }
385
386 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
387 int idx,
388 LLVMTypeRef type)
389 {
390 LLVMValueRef offset;
391 LLVMValueRef ptr;
392 int addr_space;
393
394 offset = LLVMConstInt(ctx->i32, idx * 16, false);
395
396 ptr = ctx->shared_memory;
397 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
398 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
399 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
400 return ptr;
401 }
402
403 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
404 {
405 if (t == ctx->f16 || t == ctx->i16)
406 return ctx->i16;
407 else if (t == ctx->f32 || t == ctx->i32)
408 return ctx->i32;
409 else if (t == ctx->f64 || t == ctx->i64)
410 return ctx->i64;
411 else
412 unreachable("Unhandled integer size");
413 }
414
415 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
416 {
417 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
418 LLVMTypeRef elem_type = LLVMGetElementType(t);
419 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
420 LLVMGetVectorSize(t));
421 }
422 return to_integer_type_scalar(ctx, t);
423 }
424
425 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
426 {
427 LLVMTypeRef type = LLVMTypeOf(v);
428 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
429 }
430
431 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
432 {
433 if (t == ctx->i16 || t == ctx->f16)
434 return ctx->f16;
435 else if (t == ctx->i32 || t == ctx->f32)
436 return ctx->f32;
437 else if (t == ctx->i64 || t == ctx->f64)
438 return ctx->f64;
439 else
440 unreachable("Unhandled float size");
441 }
442
443 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
444 {
445 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
446 LLVMTypeRef elem_type = LLVMGetElementType(t);
447 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
448 LLVMGetVectorSize(t));
449 }
450 return to_float_type_scalar(ctx, t);
451 }
452
453 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
454 {
455 LLVMTypeRef type = LLVMTypeOf(v);
456 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
457 }
458
459 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
460 {
461 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
462 type = LLVMGetElementType(type);
463
464 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
465 return LLVMGetIntTypeWidth(type);
466
467 if (type == ctx->f16)
468 return 16;
469 if (type == ctx->f32)
470 return 32;
471 if (type == ctx->f64)
472 return 64;
473
474 unreachable("Unhandled type kind in get_elem_bits");
475 }
476
477 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
478 LLVMValueRef param, unsigned rshift,
479 unsigned bitwidth)
480 {
481 LLVMValueRef value = param;
482 if (rshift)
483 value = LLVMBuildLShr(ctx->builder, value,
484 LLVMConstInt(ctx->i32, rshift, false), "");
485
486 if (rshift + bitwidth < 32) {
487 unsigned mask = (1 << bitwidth) - 1;
488 value = LLVMBuildAnd(ctx->builder, value,
489 LLVMConstInt(ctx->i32, mask, false), "");
490 }
491 return value;
492 }
493
494 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
495 {
496 switch (ctx->stage) {
497 case MESA_SHADER_TESS_CTRL:
498 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
499 case MESA_SHADER_TESS_EVAL:
500 return ctx->tes_rel_patch_id;
501 break;
502 default:
503 unreachable("Illegal stage");
504 }
505 }
506
507 /* Tessellation shaders pass outputs to the next shader using LDS.
508 *
509 * LS outputs = TCS inputs
510 * TCS outputs = TES inputs
511 *
512 * The LDS layout is:
513 * - TCS inputs for patch 0
514 * - TCS inputs for patch 1
515 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
516 * - ...
517 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
518 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
519 * - TCS outputs for patch 1
520 * - Per-patch TCS outputs for patch 1
521 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
522 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
523 * - ...
524 *
525 * All three shaders VS(LS), TCS, TES share the same LDS space.
526 */
527 static LLVMValueRef
528 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
529 {
530 if (ctx->stage == MESA_SHADER_VERTEX)
531 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
532 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
533 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
534 else {
535 assert(0);
536 return NULL;
537 }
538 }
539
540 static LLVMValueRef
541 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
542 {
543 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
544 }
545
546 static LLVMValueRef
547 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
548 {
549 return LLVMBuildMul(ctx->builder,
550 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
551 LLVMConstInt(ctx->i32, 4, false), "");
552 }
553
554 static LLVMValueRef
555 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
556 {
557 return LLVMBuildMul(ctx->builder,
558 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
559 LLVMConstInt(ctx->i32, 4, false), "");
560 }
561
562 static LLVMValueRef
563 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
564 {
565 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
566 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
567
568 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
569 }
570
571 static LLVMValueRef
572 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
573 {
574 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
575 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
576 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
577
578 return LLVMBuildAdd(ctx->builder, patch0_offset,
579 LLVMBuildMul(ctx->builder, patch_stride,
580 rel_patch_id, ""),
581 "");
582 }
583
584 static LLVMValueRef
585 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
586 {
587 LLVMValueRef patch0_patch_data_offset =
588 get_tcs_out_patch0_patch_data_offset(ctx);
589 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
590 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
591
592 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
593 LLVMBuildMul(ctx->builder, patch_stride,
594 rel_patch_id, ""),
595 "");
596 }
597
598 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
599 {
600 ud_info->sgpr_idx = *sgpr_idx;
601 ud_info->num_sgprs = num_sgprs;
602 ud_info->indirect = false;
603 ud_info->indirect_offset = 0;
604 *sgpr_idx += num_sgprs;
605 }
606
607 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
608 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
609 {
610 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
611 }
612
613
614 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
615 uint32_t indirect_offset)
616 {
617 ud_info->sgpr_idx = sgpr_idx;
618 ud_info->num_sgprs = num_sgprs;
619 ud_info->indirect = true;
620 ud_info->indirect_offset = indirect_offset;
621 }
622
623 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
624 {
625 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
626 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
627 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
628 "tess_lds");
629 }
630
631 struct user_sgpr_info {
632 bool need_ring_offsets;
633 uint8_t sgpr_count;
634 bool indirect_all_descriptor_sets;
635 };
636
637 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
638 struct user_sgpr_info *user_sgpr_info)
639 {
640 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
641
642 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
643 if (ctx->stage == MESA_SHADER_GEOMETRY ||
644 ctx->stage == MESA_SHADER_VERTEX ||
645 ctx->stage == MESA_SHADER_TESS_CTRL ||
646 ctx->stage == MESA_SHADER_TESS_EVAL ||
647 ctx->is_gs_copy_shader)
648 user_sgpr_info->need_ring_offsets = true;
649
650 if (ctx->stage == MESA_SHADER_FRAGMENT &&
651 ctx->shader_info->info.ps.needs_sample_positions)
652 user_sgpr_info->need_ring_offsets = true;
653
654 /* 2 user sgprs will nearly always be allocated for scratch/rings */
655 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
656 user_sgpr_info->sgpr_count += 2;
657 }
658
659 switch (ctx->stage) {
660 case MESA_SHADER_COMPUTE:
661 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
662 break;
663 case MESA_SHADER_FRAGMENT:
664 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
665 break;
666 case MESA_SHADER_VERTEX:
667 if (!ctx->is_gs_copy_shader) {
668 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
669 if (ctx->shader_info->info.vs.needs_draw_id) {
670 user_sgpr_info->sgpr_count += 3;
671 } else {
672 user_sgpr_info->sgpr_count += 2;
673 }
674 }
675 if (ctx->options->key.vs.as_ls)
676 user_sgpr_info->sgpr_count++;
677 break;
678 case MESA_SHADER_TESS_CTRL:
679 user_sgpr_info->sgpr_count += 4;
680 break;
681 case MESA_SHADER_TESS_EVAL:
682 user_sgpr_info->sgpr_count += 1;
683 break;
684 case MESA_SHADER_GEOMETRY:
685 user_sgpr_info->sgpr_count += 2;
686 break;
687 default:
688 break;
689 }
690
691 if (ctx->shader_info->info.needs_push_constants)
692 user_sgpr_info->sgpr_count += 2;
693
694 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
695 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
696 user_sgpr_info->sgpr_count += 2;
697 user_sgpr_info->indirect_all_descriptor_sets = true;
698 } else {
699 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
700 }
701 }
702
703 static void create_function(struct nir_to_llvm_context *ctx)
704 {
705 unsigned i;
706 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
707 uint8_t user_sgpr_idx;
708 struct user_sgpr_info user_sgpr_info;
709 struct arg_info args = {};
710 LLVMValueRef desc_sets;
711
712 allocate_user_sgprs(ctx, &user_sgpr_info);
713 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
714 add_user_sgpr_argument(&args, const_array(ctx->v16i8, 16), &ctx->ring_offsets); /* address of rings */
715 }
716
717 /* 1 for each descriptor set */
718 if (!user_sgpr_info.indirect_all_descriptor_sets) {
719 for (unsigned i = 0; i < num_sets; ++i) {
720 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
721 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
722 }
723 }
724 } else
725 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
726
727 if (ctx->shader_info->info.needs_push_constants) {
728 /* 1 for push constants and dynamic descriptors */
729 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
730 }
731
732 switch (ctx->stage) {
733 case MESA_SHADER_COMPUTE:
734 if (ctx->shader_info->info.cs.grid_components_used)
735 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
736 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
737 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
738 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
739 break;
740 case MESA_SHADER_VERTEX:
741 if (!ctx->is_gs_copy_shader) {
742 if (ctx->shader_info->info.vs.has_vertex_buffers)
743 add_user_sgpr_argument(&args, const_array(ctx->v16i8, 16), &ctx->vertex_buffers); /* vertex buffers */
744 add_user_sgpr_argument(&args, ctx->i32, &ctx->base_vertex); // base vertex
745 add_user_sgpr_argument(&args, ctx->i32, &ctx->start_instance);// start instance
746 if (ctx->shader_info->info.vs.needs_draw_id)
747 add_user_sgpr_argument(&args, ctx->i32, &ctx->draw_index); // draw id
748 }
749 if (ctx->options->key.vs.as_es)
750 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
751 else if (ctx->options->key.vs.as_ls)
752 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
753 add_vgpr_argument(&args, ctx->i32, &ctx->vertex_id); // vertex id
754 if (!ctx->is_gs_copy_shader) {
755 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
756 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
757 add_vgpr_argument(&args, ctx->i32, &ctx->instance_id); // instance id
758 }
759 break;
760 case MESA_SHADER_TESS_CTRL:
761 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
762 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
763 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
764 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
765 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
766 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
767 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
768 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
769 break;
770 case MESA_SHADER_TESS_EVAL:
771 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
772 if (ctx->options->key.tes.as_es) {
773 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
774 add_sgpr_argument(&args, ctx->i32, NULL); //
775 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
776 } else {
777 add_sgpr_argument(&args, ctx->i32, NULL); //
778 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
779 }
780 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
781 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
782 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
783 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
784 break;
785 case MESA_SHADER_GEOMETRY:
786 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
787 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
788 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
789 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
790 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
791 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
792 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
793 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
796 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
797 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
798 break;
799 case MESA_SHADER_FRAGMENT:
800 if (ctx->shader_info->info.ps.needs_sample_positions)
801 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
802 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
803 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
804 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
805 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
806 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
807 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
808 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
809 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
810 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
811 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos x float */
812 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos y float */
813 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos z float */
814 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos w float */
815 add_vgpr_argument(&args, ctx->i32, &ctx->front_face); /* front face */
816 add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /* ancillary */
817 add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /* sample coverage */
818 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
819 break;
820 default:
821 unreachable("Shader stage not implemented");
822 }
823
824 ctx->main_function = create_llvm_function(
825 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
826 ctx->max_workgroup_size,
827 ctx->options->unsafe_math);
828 set_llvm_calling_convention(ctx->main_function, ctx->stage);
829
830 ctx->shader_info->num_input_sgprs = 0;
831 ctx->shader_info->num_input_vgprs = 0;
832
833 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
834 for (i = 0; i < args.user_sgpr_count; i++)
835 ctx->shader_info->num_user_sgprs += llvm_get_type_size(args.types[i]) / 4;
836
837 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
838 for (; i < args.sgpr_count; i++)
839 ctx->shader_info->num_input_sgprs += llvm_get_type_size(args.types[i]) / 4;
840
841 if (ctx->stage != MESA_SHADER_FRAGMENT)
842 for (; i < args.count; ++i)
843 ctx->shader_info->num_input_vgprs += llvm_get_type_size(args.types[i]) / 4;
844
845 assign_arguments(ctx->main_function, &args);
846
847 user_sgpr_idx = 0;
848
849 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
850 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
851 if (ctx->options->supports_spill) {
852 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
853 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
854 NULL, 0, AC_FUNC_ATTR_READNONE);
855 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
856 const_array(ctx->v16i8, 16), "");
857 }
858 }
859
860 if (!user_sgpr_info.indirect_all_descriptor_sets) {
861 for (unsigned i = 0; i < num_sets; ++i) {
862 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
863 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
864 } else
865 ctx->descriptor_sets[i] = NULL;
866 }
867 } else {
868 uint32_t desc_sgpr_idx = user_sgpr_idx;
869 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
870
871 for (unsigned i = 0; i < num_sets; ++i) {
872 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
873 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
874 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
875
876 } else
877 ctx->descriptor_sets[i] = NULL;
878 }
879 ctx->shader_info->need_indirect_descriptor_sets = true;
880 }
881
882 if (ctx->shader_info->info.needs_push_constants) {
883 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
884 }
885
886 switch (ctx->stage) {
887 case MESA_SHADER_COMPUTE:
888 if (ctx->shader_info->info.cs.grid_components_used) {
889 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
890 }
891 break;
892 case MESA_SHADER_VERTEX:
893 if (!ctx->is_gs_copy_shader) {
894 if (ctx->shader_info->info.vs.has_vertex_buffers) {
895 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
896 }
897 unsigned vs_num = 2;
898 if (ctx->shader_info->info.vs.needs_draw_id)
899 vs_num++;
900
901 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
902 }
903 if (ctx->options->key.vs.as_ls) {
904 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
905 }
906 if (ctx->options->key.vs.as_ls)
907 declare_tess_lds(ctx);
908 break;
909 case MESA_SHADER_TESS_CTRL:
910 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
911 declare_tess_lds(ctx);
912 break;
913 case MESA_SHADER_TESS_EVAL:
914 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
915 break;
916 case MESA_SHADER_GEOMETRY:
917 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
918 break;
919 case MESA_SHADER_FRAGMENT:
920 if (ctx->shader_info->info.ps.needs_sample_positions) {
921 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
922 }
923 break;
924 default:
925 unreachable("Shader stage not implemented");
926 }
927 }
928
929 static void setup_types(struct nir_to_llvm_context *ctx)
930 {
931 LLVMValueRef args[4];
932
933 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
934 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
935 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
936 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
937 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
938 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
939 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
940 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
941 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
942 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
943 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
944 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
945 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
946 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
947 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
948 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
949
950 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
951 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
952 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
953 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
954 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
955 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
956
957 args[0] = ctx->f32zero;
958 args[1] = ctx->f32zero;
959 args[2] = ctx->f32zero;
960 args[3] = ctx->f32one;
961 ctx->v4f32empty = LLVMConstVector(args, 4);
962
963 ctx->uniform_md_kind =
964 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
965 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
966
967 args[0] = LLVMConstReal(ctx->f32, 2.5);
968 }
969
970 static int get_llvm_num_components(LLVMValueRef value)
971 {
972 LLVMTypeRef type = LLVMTypeOf(value);
973 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
974 ? LLVMGetVectorSize(type)
975 : 1;
976 return num_components;
977 }
978
979 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
980 LLVMValueRef value,
981 int index)
982 {
983 int count = get_llvm_num_components(value);
984
985 assert(index < count);
986 if (count == 1)
987 return value;
988
989 return LLVMBuildExtractElement(ctx->builder, value,
990 LLVMConstInt(ctx->i32, index, false), "");
991 }
992
993 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
994 LLVMValueRef value, unsigned count)
995 {
996 unsigned num_components = get_llvm_num_components(value);
997 if (count == num_components)
998 return value;
999
1000 LLVMValueRef masks[] = {
1001 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1002 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1003
1004 if (count == 1)
1005 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1006 "");
1007
1008 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1009 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1010 }
1011
1012 static void
1013 build_store_values_extended(struct nir_to_llvm_context *ctx,
1014 LLVMValueRef *values,
1015 unsigned value_count,
1016 unsigned value_stride,
1017 LLVMValueRef vec)
1018 {
1019 LLVMBuilderRef builder = ctx->builder;
1020 unsigned i;
1021
1022 if (value_count == 1) {
1023 LLVMBuildStore(builder, vec, values[0]);
1024 return;
1025 }
1026
1027 for (i = 0; i < value_count; i++) {
1028 LLVMValueRef ptr = values[i * value_stride];
1029 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
1030 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1031 LLVMBuildStore(builder, value, ptr);
1032 }
1033 }
1034
1035 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
1036 nir_ssa_def *def)
1037 {
1038 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
1039 if (def->num_components > 1) {
1040 type = LLVMVectorType(type, def->num_components);
1041 }
1042 return type;
1043 }
1044
1045 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
1046 {
1047 assert(src.is_ssa);
1048 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1049 return (LLVMValueRef)entry->data;
1050 }
1051
1052
1053 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1054 struct nir_block *b)
1055 {
1056 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1057 return (LLVMBasicBlockRef)entry->data;
1058 }
1059
1060 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1061 nir_alu_src src,
1062 unsigned num_components)
1063 {
1064 LLVMValueRef value = get_src(ctx, src.src);
1065 bool need_swizzle = false;
1066
1067 assert(value);
1068 LLVMTypeRef type = LLVMTypeOf(value);
1069 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1070 ? LLVMGetVectorSize(type)
1071 : 1;
1072
1073 for (unsigned i = 0; i < num_components; ++i) {
1074 assert(src.swizzle[i] < src_components);
1075 if (src.swizzle[i] != i)
1076 need_swizzle = true;
1077 }
1078
1079 if (need_swizzle || num_components != src_components) {
1080 LLVMValueRef masks[] = {
1081 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1082 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1083 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1084 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1085
1086 if (src_components > 1 && num_components == 1) {
1087 value = LLVMBuildExtractElement(ctx->builder, value,
1088 masks[0], "");
1089 } else if (src_components == 1 && num_components > 1) {
1090 LLVMValueRef values[] = {value, value, value, value};
1091 value = ac_build_gather_values(&ctx->ac, values, num_components);
1092 } else {
1093 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1094 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1095 swizzle, "");
1096 }
1097 }
1098 assert(!src.negate);
1099 assert(!src.abs);
1100 return value;
1101 }
1102
1103 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
1104 LLVMIntPredicate pred, LLVMValueRef src0,
1105 LLVMValueRef src1)
1106 {
1107 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1108 return LLVMBuildSelect(ctx->builder, result,
1109 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1110 LLVMConstInt(ctx->i32, 0, false), "");
1111 }
1112
1113 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
1114 LLVMRealPredicate pred, LLVMValueRef src0,
1115 LLVMValueRef src1)
1116 {
1117 LLVMValueRef result;
1118 src0 = to_float(ctx, src0);
1119 src1 = to_float(ctx, src1);
1120 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1121 return LLVMBuildSelect(ctx->builder, result,
1122 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1123 LLVMConstInt(ctx->i32, 0, false), "");
1124 }
1125
1126 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
1127 const char *intrin,
1128 LLVMTypeRef result_type,
1129 LLVMValueRef src0)
1130 {
1131 char name[64];
1132 LLVMValueRef params[] = {
1133 to_float(ctx, src0),
1134 };
1135
1136 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1137 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1138 }
1139
1140 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
1141 const char *intrin,
1142 LLVMTypeRef result_type,
1143 LLVMValueRef src0, LLVMValueRef src1)
1144 {
1145 char name[64];
1146 LLVMValueRef params[] = {
1147 to_float(ctx, src0),
1148 to_float(ctx, src1),
1149 };
1150
1151 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1152 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1153 }
1154
1155 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
1156 const char *intrin,
1157 LLVMTypeRef result_type,
1158 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1159 {
1160 char name[64];
1161 LLVMValueRef params[] = {
1162 to_float(ctx, src0),
1163 to_float(ctx, src1),
1164 to_float(ctx, src2),
1165 };
1166
1167 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1168 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1169 }
1170
1171 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
1172 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1173 {
1174 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1175 ctx->i32zero, "");
1176 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1177 }
1178
1179 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1180 LLVMValueRef src0)
1181 {
1182 LLVMValueRef params[2] = {
1183 src0,
1184
1185 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1186 * add special code to check for x=0. The reason is that
1187 * the LLVM behavior for x=0 is different from what we
1188 * need here.
1189 *
1190 * The hardware already implements the correct behavior.
1191 */
1192 LLVMConstInt(ctx->i32, 1, false),
1193 };
1194 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1195 }
1196
1197 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1198 LLVMValueRef src0)
1199 {
1200 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1201 }
1202
1203 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1204 LLVMValueRef src0)
1205 {
1206 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1207 }
1208
1209 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1210 LLVMIntPredicate pred,
1211 LLVMValueRef src0, LLVMValueRef src1)
1212 {
1213 return LLVMBuildSelect(ctx->builder,
1214 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1215 src0,
1216 src1, "");
1217
1218 }
1219 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1220 LLVMValueRef src0)
1221 {
1222 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1223 LLVMBuildNeg(ctx->builder, src0, ""));
1224 }
1225
1226 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1227 LLVMValueRef src0)
1228 {
1229 LLVMValueRef cmp, val;
1230
1231 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1232 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1233 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1234 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1235 return val;
1236 }
1237
1238 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1239 LLVMValueRef src0)
1240 {
1241 LLVMValueRef cmp, val;
1242
1243 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1244 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1245 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1246 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1247 return val;
1248 }
1249
1250 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1251 LLVMValueRef src0)
1252 {
1253 const char *intr = "llvm.floor.f32";
1254 LLVMValueRef fsrc0 = to_float(ctx, src0);
1255 LLVMValueRef params[] = {
1256 fsrc0,
1257 };
1258 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1259 ctx->f32, params, 1,
1260 AC_FUNC_ATTR_READNONE);
1261 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1262 }
1263
1264 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1265 const char *intrin,
1266 LLVMValueRef src0, LLVMValueRef src1)
1267 {
1268 LLVMTypeRef ret_type;
1269 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1270 LLVMValueRef res;
1271 LLVMValueRef params[] = { src0, src1 };
1272 ret_type = LLVMStructTypeInContext(ctx->context, types,
1273 2, true);
1274
1275 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1276 params, 2, AC_FUNC_ATTR_READNONE);
1277
1278 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1279 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1280 return res;
1281 }
1282
1283 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1284 LLVMValueRef src0)
1285 {
1286 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1287 }
1288
1289 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1290 LLVMValueRef src0)
1291 {
1292 LLVMValueRef result;
1293 LLVMValueRef cond;
1294
1295 src0 = to_float(ctx, src0);
1296 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1297
1298 /* TODO SI/CIK options here */
1299 if (ctx->options->chip_class >= VI) {
1300 LLVMValueRef args[2];
1301 /* Check if the result is a denormal - and flush to 0 if so. */
1302 args[0] = result;
1303 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1304 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1305 }
1306
1307 /* need to convert back up to f32 */
1308 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1309
1310 if (ctx->options->chip_class >= VI)
1311 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1312
1313 return result;
1314 }
1315
1316 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1317 LLVMValueRef src0, LLVMValueRef src1)
1318 {
1319 LLVMValueRef dst64, result;
1320 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1321 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1322
1323 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1324 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1325 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1326 return result;
1327 }
1328
1329 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1330 LLVMValueRef src0, LLVMValueRef src1)
1331 {
1332 LLVMValueRef dst64, result;
1333 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1334 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1335
1336 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1337 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1338 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1339 return result;
1340 }
1341
1342 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1343 bool is_signed,
1344 LLVMValueRef srcs[3])
1345 {
1346 LLVMValueRef result;
1347 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1348
1349 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1350 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1351 return result;
1352 }
1353
1354 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1355 LLVMValueRef src0, LLVMValueRef src1,
1356 LLVMValueRef src2, LLVMValueRef src3)
1357 {
1358 LLVMValueRef bfi_args[3], result;
1359
1360 bfi_args[0] = LLVMBuildShl(ctx->builder,
1361 LLVMBuildSub(ctx->builder,
1362 LLVMBuildShl(ctx->builder,
1363 ctx->i32one,
1364 src3, ""),
1365 ctx->i32one, ""),
1366 src2, "");
1367 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1368 bfi_args[2] = src0;
1369
1370 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1371
1372 /* Calculate:
1373 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1374 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1375 */
1376 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1377 LLVMBuildAnd(ctx->builder, bfi_args[0],
1378 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1379
1380 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1381 return result;
1382 }
1383
1384 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1385 LLVMValueRef src0)
1386 {
1387 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1388 int i;
1389 LLVMValueRef comp[2];
1390
1391 src0 = to_float(ctx, src0);
1392 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1393 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1394 for (i = 0; i < 2; i++) {
1395 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1396 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1397 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1398 }
1399
1400 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1401 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1402
1403 return comp[0];
1404 }
1405
1406 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1407 LLVMValueRef src0)
1408 {
1409 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1410 LLVMValueRef temps[2], result, val;
1411 int i;
1412
1413 for (i = 0; i < 2; i++) {
1414 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1415 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1416 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1417 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1418 }
1419
1420 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1421 ctx->i32zero, "");
1422 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1423 ctx->i32one, "");
1424 return result;
1425 }
1426
1427 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1428 nir_op op,
1429 LLVMValueRef src0)
1430 {
1431 unsigned mask;
1432 int idx;
1433 LLVMValueRef result;
1434 ctx->has_ddxy = true;
1435
1436 if (!ctx->lds && !ctx->has_ds_bpermute)
1437 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1438 LLVMArrayType(ctx->i32, 64),
1439 "ddxy_lds", LOCAL_ADDR_SPACE);
1440
1441 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1442 mask = AC_TID_MASK_LEFT;
1443 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1444 mask = AC_TID_MASK_TOP;
1445 else
1446 mask = AC_TID_MASK_TOP_LEFT;
1447
1448 /* for DDX we want to next X pixel, DDY next Y pixel. */
1449 if (op == nir_op_fddx_fine ||
1450 op == nir_op_fddx_coarse ||
1451 op == nir_op_fddx)
1452 idx = 1;
1453 else
1454 idx = 2;
1455
1456 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1457 mask, idx, ctx->lds,
1458 src0);
1459 return result;
1460 }
1461
1462 /*
1463 * this takes an I,J coordinate pair,
1464 * and works out the X and Y derivatives.
1465 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1466 */
1467 static LLVMValueRef emit_ddxy_interp(
1468 struct nir_to_llvm_context *ctx,
1469 LLVMValueRef interp_ij)
1470 {
1471 LLVMValueRef result[4], a;
1472 unsigned i;
1473
1474 for (i = 0; i < 2; i++) {
1475 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1476 LLVMConstInt(ctx->i32, i, false), "");
1477 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1478 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1479 }
1480 return ac_build_gather_values(&ctx->ac, result, 4);
1481 }
1482
1483 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1484 {
1485 LLVMValueRef src[4], result = NULL;
1486 unsigned num_components = instr->dest.dest.ssa.num_components;
1487 unsigned src_components;
1488 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1489
1490 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1491 switch (instr->op) {
1492 case nir_op_vec2:
1493 case nir_op_vec3:
1494 case nir_op_vec4:
1495 src_components = 1;
1496 break;
1497 case nir_op_pack_half_2x16:
1498 src_components = 2;
1499 break;
1500 case nir_op_unpack_half_2x16:
1501 src_components = 1;
1502 break;
1503 default:
1504 src_components = num_components;
1505 break;
1506 }
1507 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1508 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1509
1510 switch (instr->op) {
1511 case nir_op_fmov:
1512 case nir_op_imov:
1513 result = src[0];
1514 break;
1515 case nir_op_fneg:
1516 src[0] = to_float(ctx, src[0]);
1517 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1518 break;
1519 case nir_op_ineg:
1520 result = LLVMBuildNeg(ctx->builder, src[0], "");
1521 break;
1522 case nir_op_inot:
1523 result = LLVMBuildNot(ctx->builder, src[0], "");
1524 break;
1525 case nir_op_iadd:
1526 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1527 break;
1528 case nir_op_fadd:
1529 src[0] = to_float(ctx, src[0]);
1530 src[1] = to_float(ctx, src[1]);
1531 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1532 break;
1533 case nir_op_fsub:
1534 src[0] = to_float(ctx, src[0]);
1535 src[1] = to_float(ctx, src[1]);
1536 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1537 break;
1538 case nir_op_isub:
1539 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1540 break;
1541 case nir_op_imul:
1542 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1543 break;
1544 case nir_op_imod:
1545 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1546 break;
1547 case nir_op_umod:
1548 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1549 break;
1550 case nir_op_fmod:
1551 src[0] = to_float(ctx, src[0]);
1552 src[1] = to_float(ctx, src[1]);
1553 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1554 result = emit_intrin_1f_param(ctx, "llvm.floor",
1555 to_float_type(ctx, def_type), result);
1556 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1557 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1558 break;
1559 case nir_op_frem:
1560 src[0] = to_float(ctx, src[0]);
1561 src[1] = to_float(ctx, src[1]);
1562 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1563 break;
1564 case nir_op_irem:
1565 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1566 break;
1567 case nir_op_idiv:
1568 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1569 break;
1570 case nir_op_udiv:
1571 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1572 break;
1573 case nir_op_fmul:
1574 src[0] = to_float(ctx, src[0]);
1575 src[1] = to_float(ctx, src[1]);
1576 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1577 break;
1578 case nir_op_fdiv:
1579 src[0] = to_float(ctx, src[0]);
1580 src[1] = to_float(ctx, src[1]);
1581 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1582 break;
1583 case nir_op_frcp:
1584 src[0] = to_float(ctx, src[0]);
1585 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1586 break;
1587 case nir_op_iand:
1588 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1589 break;
1590 case nir_op_ior:
1591 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1592 break;
1593 case nir_op_ixor:
1594 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1595 break;
1596 case nir_op_ishl:
1597 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1598 break;
1599 case nir_op_ishr:
1600 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1601 break;
1602 case nir_op_ushr:
1603 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1604 break;
1605 case nir_op_ilt:
1606 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1607 break;
1608 case nir_op_ine:
1609 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1610 break;
1611 case nir_op_ieq:
1612 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1613 break;
1614 case nir_op_ige:
1615 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1616 break;
1617 case nir_op_ult:
1618 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1619 break;
1620 case nir_op_uge:
1621 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1622 break;
1623 case nir_op_feq:
1624 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1625 break;
1626 case nir_op_fne:
1627 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1628 break;
1629 case nir_op_flt:
1630 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1631 break;
1632 case nir_op_fge:
1633 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1634 break;
1635 case nir_op_fabs:
1636 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1637 to_float_type(ctx, def_type), src[0]);
1638 break;
1639 case nir_op_iabs:
1640 result = emit_iabs(ctx, src[0]);
1641 break;
1642 case nir_op_imax:
1643 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1644 break;
1645 case nir_op_imin:
1646 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1647 break;
1648 case nir_op_umax:
1649 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1650 break;
1651 case nir_op_umin:
1652 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1653 break;
1654 case nir_op_isign:
1655 result = emit_isign(ctx, src[0]);
1656 break;
1657 case nir_op_fsign:
1658 src[0] = to_float(ctx, src[0]);
1659 result = emit_fsign(ctx, src[0]);
1660 break;
1661 case nir_op_ffloor:
1662 result = emit_intrin_1f_param(ctx, "llvm.floor",
1663 to_float_type(ctx, def_type), src[0]);
1664 break;
1665 case nir_op_ftrunc:
1666 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1667 to_float_type(ctx, def_type), src[0]);
1668 break;
1669 case nir_op_fceil:
1670 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1671 to_float_type(ctx, def_type), src[0]);
1672 break;
1673 case nir_op_fround_even:
1674 result = emit_intrin_1f_param(ctx, "llvm.rint",
1675 to_float_type(ctx, def_type),src[0]);
1676 break;
1677 case nir_op_ffract:
1678 result = emit_ffract(ctx, src[0]);
1679 break;
1680 case nir_op_fsin:
1681 result = emit_intrin_1f_param(ctx, "llvm.sin",
1682 to_float_type(ctx, def_type), src[0]);
1683 break;
1684 case nir_op_fcos:
1685 result = emit_intrin_1f_param(ctx, "llvm.cos",
1686 to_float_type(ctx, def_type), src[0]);
1687 break;
1688 case nir_op_fsqrt:
1689 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1690 to_float_type(ctx, def_type), src[0]);
1691 break;
1692 case nir_op_fexp2:
1693 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1694 to_float_type(ctx, def_type), src[0]);
1695 break;
1696 case nir_op_flog2:
1697 result = emit_intrin_1f_param(ctx, "llvm.log2",
1698 to_float_type(ctx, def_type), src[0]);
1699 break;
1700 case nir_op_frsq:
1701 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1702 to_float_type(ctx, def_type), src[0]);
1703 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1704 break;
1705 case nir_op_fpow:
1706 result = emit_intrin_2f_param(ctx, "llvm.pow",
1707 to_float_type(ctx, def_type), src[0], src[1]);
1708 break;
1709 case nir_op_fmax:
1710 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1711 to_float_type(ctx, def_type), src[0], src[1]);
1712 if (instr->dest.dest.ssa.bit_size == 32)
1713 result = emit_intrin_1f_param(ctx, "llvm.canonicalize",
1714 to_float_type(ctx, def_type),
1715 result);
1716 break;
1717 case nir_op_fmin:
1718 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1719 to_float_type(ctx, def_type), src[0], src[1]);
1720 if (instr->dest.dest.ssa.bit_size == 32)
1721 result = emit_intrin_1f_param(ctx, "llvm.canonicalize",
1722 to_float_type(ctx, def_type),
1723 result);
1724 break;
1725 case nir_op_ffma:
1726 result = emit_intrin_3f_param(ctx, "llvm.fma",
1727 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1728 break;
1729 case nir_op_ibitfield_extract:
1730 result = emit_bitfield_extract(ctx, true, src);
1731 break;
1732 case nir_op_ubitfield_extract:
1733 result = emit_bitfield_extract(ctx, false, src);
1734 break;
1735 case nir_op_bitfield_insert:
1736 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1737 break;
1738 case nir_op_bitfield_reverse:
1739 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1740 break;
1741 case nir_op_bit_count:
1742 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1743 break;
1744 case nir_op_vec2:
1745 case nir_op_vec3:
1746 case nir_op_vec4:
1747 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1748 src[i] = to_integer(ctx, src[i]);
1749 result = ac_build_gather_values(&ctx->ac, src, num_components);
1750 break;
1751 case nir_op_f2i32:
1752 case nir_op_f2i64:
1753 src[0] = to_float(ctx, src[0]);
1754 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1755 break;
1756 case nir_op_f2u32:
1757 case nir_op_f2u64:
1758 src[0] = to_float(ctx, src[0]);
1759 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1760 break;
1761 case nir_op_i2f32:
1762 case nir_op_i2f64:
1763 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1764 break;
1765 case nir_op_u2f32:
1766 case nir_op_u2f64:
1767 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1768 break;
1769 case nir_op_f2f64:
1770 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1771 break;
1772 case nir_op_f2f32:
1773 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1774 break;
1775 case nir_op_u2u32:
1776 case nir_op_u2u64:
1777 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1778 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1779 else
1780 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1781 break;
1782 case nir_op_i2i32:
1783 case nir_op_i2i64:
1784 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1785 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1786 else
1787 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1788 break;
1789 case nir_op_bcsel:
1790 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1791 break;
1792 case nir_op_find_lsb:
1793 result = emit_find_lsb(ctx, src[0]);
1794 break;
1795 case nir_op_ufind_msb:
1796 result = emit_ufind_msb(ctx, src[0]);
1797 break;
1798 case nir_op_ifind_msb:
1799 result = emit_ifind_msb(ctx, src[0]);
1800 break;
1801 case nir_op_uadd_carry:
1802 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1803 break;
1804 case nir_op_usub_borrow:
1805 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1806 break;
1807 case nir_op_b2f:
1808 result = emit_b2f(ctx, src[0]);
1809 break;
1810 case nir_op_fquantize2f16:
1811 result = emit_f2f16(ctx, src[0]);
1812 break;
1813 case nir_op_umul_high:
1814 result = emit_umul_high(ctx, src[0], src[1]);
1815 break;
1816 case nir_op_imul_high:
1817 result = emit_imul_high(ctx, src[0], src[1]);
1818 break;
1819 case nir_op_pack_half_2x16:
1820 result = emit_pack_half_2x16(ctx, src[0]);
1821 break;
1822 case nir_op_unpack_half_2x16:
1823 result = emit_unpack_half_2x16(ctx, src[0]);
1824 break;
1825 case nir_op_fddx:
1826 case nir_op_fddy:
1827 case nir_op_fddx_fine:
1828 case nir_op_fddy_fine:
1829 case nir_op_fddx_coarse:
1830 case nir_op_fddy_coarse:
1831 result = emit_ddxy(ctx, instr->op, src[0]);
1832 break;
1833 default:
1834 fprintf(stderr, "Unknown NIR alu instr: ");
1835 nir_print_instr(&instr->instr, stderr);
1836 fprintf(stderr, "\n");
1837 abort();
1838 }
1839
1840 if (result) {
1841 assert(instr->dest.dest.is_ssa);
1842 result = to_integer(ctx, result);
1843 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1844 result);
1845 }
1846 }
1847
1848 static void visit_load_const(struct nir_to_llvm_context *ctx,
1849 nir_load_const_instr *instr)
1850 {
1851 LLVMValueRef values[4], value = NULL;
1852 LLVMTypeRef element_type =
1853 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1854
1855 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1856 switch (instr->def.bit_size) {
1857 case 32:
1858 values[i] = LLVMConstInt(element_type,
1859 instr->value.u32[i], false);
1860 break;
1861 case 64:
1862 values[i] = LLVMConstInt(element_type,
1863 instr->value.u64[i], false);
1864 break;
1865 default:
1866 fprintf(stderr,
1867 "unsupported nir load_const bit_size: %d\n",
1868 instr->def.bit_size);
1869 abort();
1870 }
1871 }
1872 if (instr->def.num_components > 1) {
1873 value = LLVMConstVector(values, instr->def.num_components);
1874 } else
1875 value = values[0];
1876
1877 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1878 }
1879
1880 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1881 LLVMTypeRef type)
1882 {
1883 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1884 return LLVMBuildBitCast(ctx->builder, ptr,
1885 LLVMPointerType(type, addr_space), "");
1886 }
1887
1888 static LLVMValueRef
1889 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1890 {
1891 LLVMValueRef size =
1892 LLVMBuildExtractElement(ctx->builder, descriptor,
1893 LLVMConstInt(ctx->i32, 2, false), "");
1894
1895 /* VI only */
1896 if (ctx->options->chip_class >= VI && in_elements) {
1897 /* On VI, the descriptor contains the size in bytes,
1898 * but TXQ must return the size in elements.
1899 * The stride is always non-zero for resources using TXQ.
1900 */
1901 LLVMValueRef stride =
1902 LLVMBuildExtractElement(ctx->builder, descriptor,
1903 LLVMConstInt(ctx->i32, 1, false), "");
1904 stride = LLVMBuildLShr(ctx->builder, stride,
1905 LLVMConstInt(ctx->i32, 16, false), "");
1906 stride = LLVMBuildAnd(ctx->builder, stride,
1907 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1908
1909 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1910 }
1911 return size;
1912 }
1913
1914 /**
1915 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1916 * intrinsic names).
1917 */
1918 static void build_int_type_name(
1919 LLVMTypeRef type,
1920 char *buf, unsigned bufsize)
1921 {
1922 assert(bufsize >= 6);
1923
1924 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1925 snprintf(buf, bufsize, "v%ui32",
1926 LLVMGetVectorSize(type));
1927 else
1928 strcpy(buf, "i32");
1929 }
1930
1931 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1932 struct ac_image_args *args,
1933 nir_tex_instr *instr)
1934 {
1935 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1936 LLVMValueRef coord = args->addr;
1937 LLVMValueRef half_texel[2];
1938 LLVMValueRef compare_cube_wa;
1939 LLVMValueRef result;
1940 int c;
1941 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1942
1943 //TODO Rect
1944 {
1945 struct ac_image_args txq_args = { 0 };
1946
1947 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1948 txq_args.opcode = ac_image_get_resinfo;
1949 txq_args.dmask = 0xf;
1950 txq_args.addr = ctx->i32zero;
1951 txq_args.resource = args->resource;
1952 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1953
1954 for (c = 0; c < 2; c++) {
1955 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1956 LLVMConstInt(ctx->i32, c, false), "");
1957 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1958 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1959 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1960 LLVMConstReal(ctx->f32, -0.5), "");
1961 }
1962 }
1963
1964 LLVMValueRef orig_coords = args->addr;
1965
1966 for (c = 0; c < 2; c++) {
1967 LLVMValueRef tmp;
1968 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1969 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1970 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1971 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1972 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1973 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1974 }
1975
1976
1977 /*
1978 * Apparantly cube has issue with integer types that the workaround doesn't solve,
1979 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
1980 * workaround by sampling using a scaled type and converting.
1981 * This is taken from amdgpu-pro shaders.
1982 */
1983 /* NOTE this produces some ugly code compared to amdgpu-pro,
1984 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
1985 * and then reads them back. -pro generates two selects,
1986 * one s_cmp for the descriptor rewriting
1987 * one v_cmp for the coordinate and result changes.
1988 */
1989 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1990 LLVMValueRef tmp, tmp2;
1991
1992 /* workaround 8/8/8/8 uint/sint cube gather bug */
1993 /* first detect it then change to a scaled read and f2i */
1994 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
1995 tmp2 = tmp;
1996
1997 /* extract the DATA_FORMAT */
1998 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
1999 LLVMConstInt(ctx->i32, 6, false), false);
2000
2001 /* is the DATA_FORMAT == 8_8_8_8 */
2002 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2003
2004 if (stype == GLSL_TYPE_UINT)
2005 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2006 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2007 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2008 else
2009 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2010 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2011 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2012
2013 /* replace the NUM FORMAT in the descriptor */
2014 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2015 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2016
2017 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
2018
2019 /* don't modify the coordinates for this case */
2020 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2021 }
2022 args->addr = coord;
2023 result = ac_build_image_opcode(&ctx->ac, args);
2024
2025 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2026 LLVMValueRef tmp, tmp2;
2027
2028 /* if the cube workaround is in place, f2i the result. */
2029 for (c = 0; c < 4; c++) {
2030 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2031 if (stype == GLSL_TYPE_UINT)
2032 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2033 else
2034 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2035 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2036 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2037 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2038 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2039 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2040 }
2041 }
2042 return result;
2043 }
2044
2045 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
2046 nir_tex_instr *instr,
2047 bool lod_is_zero,
2048 struct ac_image_args *args)
2049 {
2050 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2051 return ac_build_buffer_load_format(&ctx->ac,
2052 args->resource,
2053 args->addr,
2054 LLVMConstInt(ctx->i32, 0, false),
2055 true);
2056 }
2057
2058 args->opcode = ac_image_sample;
2059 args->compare = instr->is_shadow;
2060
2061 switch (instr->op) {
2062 case nir_texop_txf:
2063 case nir_texop_txf_ms:
2064 case nir_texop_samples_identical:
2065 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2066 args->compare = false;
2067 args->offset = false;
2068 break;
2069 case nir_texop_txb:
2070 args->bias = true;
2071 break;
2072 case nir_texop_txl:
2073 if (lod_is_zero)
2074 args->level_zero = true;
2075 else
2076 args->lod = true;
2077 break;
2078 case nir_texop_txs:
2079 case nir_texop_query_levels:
2080 args->opcode = ac_image_get_resinfo;
2081 break;
2082 case nir_texop_tex:
2083 if (ctx->stage != MESA_SHADER_FRAGMENT)
2084 args->level_zero = true;
2085 break;
2086 case nir_texop_txd:
2087 args->deriv = true;
2088 break;
2089 case nir_texop_tg4:
2090 args->opcode = ac_image_gather4;
2091 args->level_zero = true;
2092 break;
2093 case nir_texop_lod:
2094 args->opcode = ac_image_get_lod;
2095 args->compare = false;
2096 args->offset = false;
2097 break;
2098 default:
2099 break;
2100 }
2101
2102 if (instr->op == nir_texop_tg4) {
2103 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2104 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2105 return radv_lower_gather4_integer(ctx, args, instr);
2106 }
2107 }
2108 return ac_build_image_opcode(&ctx->ac, args);
2109 }
2110
2111 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2112 nir_intrinsic_instr *instr)
2113 {
2114 LLVMValueRef index = get_src(ctx, instr->src[0]);
2115 unsigned desc_set = nir_intrinsic_desc_set(instr);
2116 unsigned binding = nir_intrinsic_binding(instr);
2117 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2118 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2119 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2120 unsigned base_offset = layout->binding[binding].offset;
2121 LLVMValueRef offset, stride;
2122
2123 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2124 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2125 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2126 layout->binding[binding].dynamic_offset_offset;
2127 desc_ptr = ctx->push_constants;
2128 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2129 stride = LLVMConstInt(ctx->i32, 16, false);
2130 } else
2131 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2132
2133 offset = LLVMConstInt(ctx->i32, base_offset, false);
2134 index = LLVMBuildMul(ctx->builder, index, stride, "");
2135 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2136
2137 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2138 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2139 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2140
2141 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2142 }
2143
2144 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2145 nir_intrinsic_instr *instr)
2146 {
2147 LLVMValueRef ptr, addr;
2148
2149 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2150 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2151
2152 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2153 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2154
2155 return LLVMBuildLoad(ctx->builder, ptr, "");
2156 }
2157
2158 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2159 nir_intrinsic_instr *instr)
2160 {
2161 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2162
2163 return get_buffer_size(ctx, desc, false);
2164 }
2165 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2166 nir_intrinsic_instr *instr)
2167 {
2168 const char *store_name;
2169 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2170 LLVMTypeRef data_type = ctx->f32;
2171 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2172 int components_32bit = elem_size_mult * instr->num_components;
2173 unsigned writemask = nir_intrinsic_write_mask(instr);
2174 LLVMValueRef base_data, base_offset;
2175 LLVMValueRef params[6];
2176
2177 if (ctx->stage == MESA_SHADER_FRAGMENT)
2178 ctx->shader_info->fs.writes_memory = true;
2179
2180 params[1] = get_src(ctx, instr->src[1]);
2181 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2182 params[4] = ctx->i1false; /* glc */
2183 params[5] = ctx->i1false; /* slc */
2184
2185 if (components_32bit > 1)
2186 data_type = LLVMVectorType(ctx->f32, components_32bit);
2187
2188 base_data = to_float(ctx, src_data);
2189 base_data = trim_vector(ctx, base_data, instr->num_components);
2190 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2191 data_type, "");
2192 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2193 while (writemask) {
2194 int start, count;
2195 LLVMValueRef data;
2196 LLVMValueRef offset;
2197 LLVMValueRef tmp;
2198 u_bit_scan_consecutive_range(&writemask, &start, &count);
2199
2200 /* Due to an LLVM limitation, split 3-element writes
2201 * into a 2-element and a 1-element write. */
2202 if (count == 3) {
2203 writemask |= 1 << (start + 2);
2204 count = 2;
2205 }
2206
2207 start *= elem_size_mult;
2208 count *= elem_size_mult;
2209
2210 if (count > 4) {
2211 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2212 count = 4;
2213 }
2214
2215 if (count == 4) {
2216 store_name = "llvm.amdgcn.buffer.store.v4f32";
2217 data = base_data;
2218 } else if (count == 2) {
2219 tmp = LLVMBuildExtractElement(ctx->builder,
2220 base_data, LLVMConstInt(ctx->i32, start, false), "");
2221 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2222 ctx->i32zero, "");
2223
2224 tmp = LLVMBuildExtractElement(ctx->builder,
2225 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2226 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2227 ctx->i32one, "");
2228 store_name = "llvm.amdgcn.buffer.store.v2f32";
2229
2230 } else {
2231 assert(count == 1);
2232 if (get_llvm_num_components(base_data) > 1)
2233 data = LLVMBuildExtractElement(ctx->builder, base_data,
2234 LLVMConstInt(ctx->i32, start, false), "");
2235 else
2236 data = base_data;
2237 store_name = "llvm.amdgcn.buffer.store.f32";
2238 }
2239
2240 offset = base_offset;
2241 if (start != 0) {
2242 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2243 }
2244 params[0] = data;
2245 params[3] = offset;
2246 ac_build_intrinsic(&ctx->ac, store_name,
2247 ctx->voidt, params, 6, 0);
2248 }
2249 }
2250
2251 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2252 nir_intrinsic_instr *instr)
2253 {
2254 const char *name;
2255 LLVMValueRef params[6];
2256 int arg_count = 0;
2257 if (ctx->stage == MESA_SHADER_FRAGMENT)
2258 ctx->shader_info->fs.writes_memory = true;
2259
2260 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2261 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2262 }
2263 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2264 params[arg_count++] = get_src(ctx, instr->src[0]);
2265 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2266 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2267 params[arg_count++] = ctx->i1false; /* slc */
2268
2269 switch (instr->intrinsic) {
2270 case nir_intrinsic_ssbo_atomic_add:
2271 name = "llvm.amdgcn.buffer.atomic.add";
2272 break;
2273 case nir_intrinsic_ssbo_atomic_imin:
2274 name = "llvm.amdgcn.buffer.atomic.smin";
2275 break;
2276 case nir_intrinsic_ssbo_atomic_umin:
2277 name = "llvm.amdgcn.buffer.atomic.umin";
2278 break;
2279 case nir_intrinsic_ssbo_atomic_imax:
2280 name = "llvm.amdgcn.buffer.atomic.smax";
2281 break;
2282 case nir_intrinsic_ssbo_atomic_umax:
2283 name = "llvm.amdgcn.buffer.atomic.umax";
2284 break;
2285 case nir_intrinsic_ssbo_atomic_and:
2286 name = "llvm.amdgcn.buffer.atomic.and";
2287 break;
2288 case nir_intrinsic_ssbo_atomic_or:
2289 name = "llvm.amdgcn.buffer.atomic.or";
2290 break;
2291 case nir_intrinsic_ssbo_atomic_xor:
2292 name = "llvm.amdgcn.buffer.atomic.xor";
2293 break;
2294 case nir_intrinsic_ssbo_atomic_exchange:
2295 name = "llvm.amdgcn.buffer.atomic.swap";
2296 break;
2297 case nir_intrinsic_ssbo_atomic_comp_swap:
2298 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2299 break;
2300 default:
2301 abort();
2302 }
2303
2304 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2305 }
2306
2307 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2308 nir_intrinsic_instr *instr)
2309 {
2310 LLVMValueRef results[2];
2311 int load_components;
2312 int num_components = instr->num_components;
2313 if (instr->dest.ssa.bit_size == 64)
2314 num_components *= 2;
2315
2316 for (int i = 0; i < num_components; i += load_components) {
2317 load_components = MIN2(num_components - i, 4);
2318 const char *load_name;
2319 LLVMTypeRef data_type = ctx->f32;
2320 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2321 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2322
2323 if (load_components == 3)
2324 data_type = LLVMVectorType(ctx->f32, 4);
2325 else if (load_components > 1)
2326 data_type = LLVMVectorType(ctx->f32, load_components);
2327
2328 if (load_components >= 3)
2329 load_name = "llvm.amdgcn.buffer.load.v4f32";
2330 else if (load_components == 2)
2331 load_name = "llvm.amdgcn.buffer.load.v2f32";
2332 else if (load_components == 1)
2333 load_name = "llvm.amdgcn.buffer.load.f32";
2334 else
2335 unreachable("unhandled number of components");
2336
2337 LLVMValueRef params[] = {
2338 get_src(ctx, instr->src[0]),
2339 LLVMConstInt(ctx->i32, 0, false),
2340 offset,
2341 ctx->i1false,
2342 ctx->i1false,
2343 };
2344
2345 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2346
2347 }
2348
2349 LLVMValueRef ret = results[0];
2350 if (num_components > 4 || num_components == 3) {
2351 LLVMValueRef masks[] = {
2352 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2353 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2354 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2355 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2356 };
2357
2358 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2359 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2360 results[num_components > 4 ? 1 : 0], swizzle, "");
2361 }
2362
2363 return LLVMBuildBitCast(ctx->builder, ret,
2364 get_def_type(ctx, &instr->dest.ssa), "");
2365 }
2366
2367 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2368 nir_intrinsic_instr *instr)
2369 {
2370 LLVMValueRef results[8], ret;
2371 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2372 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2373 int num_components = instr->num_components;
2374
2375 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2376
2377 if (instr->dest.ssa.bit_size == 64)
2378 num_components *= 2;
2379
2380 for (unsigned i = 0; i < num_components; ++i) {
2381 LLVMValueRef params[] = {
2382 rsrc,
2383 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2384 offset, "")
2385 };
2386 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2387 params, 2,
2388 AC_FUNC_ATTR_READNONE |
2389 AC_FUNC_ATTR_LEGACY);
2390 }
2391
2392
2393 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2394 return LLVMBuildBitCast(ctx->builder, ret,
2395 get_def_type(ctx, &instr->dest.ssa), "");
2396 }
2397
2398 static void
2399 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2400 bool vs_in, unsigned *vertex_index_out,
2401 LLVMValueRef *vertex_index_ref,
2402 unsigned *const_out, LLVMValueRef *indir_out)
2403 {
2404 unsigned const_offset = 0;
2405 nir_deref *tail = &deref->deref;
2406 LLVMValueRef offset = NULL;
2407
2408 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2409 tail = tail->child;
2410 nir_deref_array *deref_array = nir_deref_as_array(tail);
2411 if (vertex_index_out)
2412 *vertex_index_out = deref_array->base_offset;
2413
2414 if (vertex_index_ref) {
2415 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2416 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2417 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2418 }
2419 *vertex_index_ref = vtx;
2420 }
2421 }
2422
2423 if (deref->var->data.compact) {
2424 assert(tail->child->deref_type == nir_deref_type_array);
2425 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2426 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2427 /* We always lower indirect dereferences for "compact" array vars. */
2428 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2429
2430 const_offset = deref_array->base_offset;
2431 goto out;
2432 }
2433
2434 while (tail->child != NULL) {
2435 const struct glsl_type *parent_type = tail->type;
2436 tail = tail->child;
2437
2438 if (tail->deref_type == nir_deref_type_array) {
2439 nir_deref_array *deref_array = nir_deref_as_array(tail);
2440 LLVMValueRef index, stride, local_offset;
2441 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2442
2443 const_offset += size * deref_array->base_offset;
2444 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2445 continue;
2446
2447 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2448 index = get_src(ctx, deref_array->indirect);
2449 stride = LLVMConstInt(ctx->i32, size, 0);
2450 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2451
2452 if (offset)
2453 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2454 else
2455 offset = local_offset;
2456 } else if (tail->deref_type == nir_deref_type_struct) {
2457 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2458
2459 for (unsigned i = 0; i < deref_struct->index; i++) {
2460 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2461 const_offset += glsl_count_attribute_slots(ft, vs_in);
2462 }
2463 } else
2464 unreachable("unsupported deref type");
2465
2466 }
2467 out:
2468 if (const_offset && offset)
2469 offset = LLVMBuildAdd(ctx->builder, offset,
2470 LLVMConstInt(ctx->i32, const_offset, 0),
2471 "");
2472
2473 *const_out = const_offset;
2474 *indir_out = offset;
2475 }
2476
2477 static LLVMValueRef
2478 lds_load(struct nir_to_llvm_context *ctx,
2479 LLVMValueRef dw_addr)
2480 {
2481 LLVMValueRef value;
2482 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2483 return value;
2484 }
2485
2486 static void
2487 lds_store(struct nir_to_llvm_context *ctx,
2488 LLVMValueRef dw_addr, LLVMValueRef value)
2489 {
2490 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2491 ac_build_indexed_store(&ctx->ac, ctx->lds,
2492 dw_addr, value);
2493 }
2494
2495 /* The offchip buffer layout for TCS->TES is
2496 *
2497 * - attribute 0 of patch 0 vertex 0
2498 * - attribute 0 of patch 0 vertex 1
2499 * - attribute 0 of patch 0 vertex 2
2500 * ...
2501 * - attribute 0 of patch 1 vertex 0
2502 * - attribute 0 of patch 1 vertex 1
2503 * ...
2504 * - attribute 1 of patch 0 vertex 0
2505 * - attribute 1 of patch 0 vertex 1
2506 * ...
2507 * - per patch attribute 0 of patch 0
2508 * - per patch attribute 0 of patch 1
2509 * ...
2510 *
2511 * Note that every attribute has 4 components.
2512 */
2513 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2514 LLVMValueRef vertex_index,
2515 LLVMValueRef param_index)
2516 {
2517 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2518 LLVMValueRef param_stride, constant16;
2519 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2520
2521 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2522 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2523 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2524 num_patches, "");
2525
2526 constant16 = LLVMConstInt(ctx->i32, 16, false);
2527 if (vertex_index) {
2528 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2529 vertices_per_patch, "");
2530
2531 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2532 vertex_index, "");
2533
2534 param_stride = total_vertices;
2535 } else {
2536 base_addr = rel_patch_id;
2537 param_stride = num_patches;
2538 }
2539
2540 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2541 LLVMBuildMul(ctx->builder, param_index,
2542 param_stride, ""), "");
2543
2544 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2545
2546 if (!vertex_index) {
2547 LLVMValueRef patch_data_offset =
2548 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2549
2550 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2551 patch_data_offset, "");
2552 }
2553 return base_addr;
2554 }
2555
2556 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2557 unsigned param,
2558 unsigned const_index,
2559 bool is_compact,
2560 LLVMValueRef vertex_index,
2561 LLVMValueRef indir_index)
2562 {
2563 LLVMValueRef param_index;
2564
2565 if (indir_index)
2566 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2567 indir_index, "");
2568 else {
2569 if (const_index && !is_compact)
2570 param += const_index;
2571 param_index = LLVMConstInt(ctx->i32, param, false);
2572 }
2573 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2574 }
2575
2576 static void
2577 mark_tess_output(struct nir_to_llvm_context *ctx,
2578 bool is_patch, uint32_t param)
2579
2580 {
2581 if (is_patch) {
2582 ctx->tess_patch_outputs_written |= (1ull << param);
2583 } else
2584 ctx->tess_outputs_written |= (1ull << param);
2585 }
2586
2587 static LLVMValueRef
2588 get_dw_address(struct nir_to_llvm_context *ctx,
2589 LLVMValueRef dw_addr,
2590 unsigned param,
2591 unsigned const_index,
2592 bool compact_const_index,
2593 LLVMValueRef vertex_index,
2594 LLVMValueRef stride,
2595 LLVMValueRef indir_index)
2596
2597 {
2598
2599 if (vertex_index) {
2600 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2601 LLVMBuildMul(ctx->builder,
2602 vertex_index,
2603 stride, ""), "");
2604 }
2605
2606 if (indir_index)
2607 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2608 LLVMBuildMul(ctx->builder, indir_index,
2609 LLVMConstInt(ctx->i32, 4, false), ""), "");
2610 else if (const_index && !compact_const_index)
2611 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2612 LLVMConstInt(ctx->i32, const_index, false), "");
2613
2614 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2615 LLVMConstInt(ctx->i32, param * 4, false), "");
2616
2617 if (const_index && compact_const_index)
2618 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2619 LLVMConstInt(ctx->i32, const_index, false), "");
2620 return dw_addr;
2621 }
2622
2623 static LLVMValueRef
2624 load_tcs_input(struct nir_to_llvm_context *ctx,
2625 nir_intrinsic_instr *instr)
2626 {
2627 LLVMValueRef dw_addr, stride;
2628 unsigned const_index;
2629 LLVMValueRef vertex_index;
2630 LLVMValueRef indir_index;
2631 unsigned param;
2632 LLVMValueRef value[4], result;
2633 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2634 const bool is_compact = instr->variables[0]->var->data.compact;
2635 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2636 radv_get_deref_offset(ctx, instr->variables[0],
2637 false, NULL, per_vertex ? &vertex_index : NULL,
2638 &const_index, &indir_index);
2639
2640 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2641 dw_addr = get_tcs_in_current_patch_offset(ctx);
2642 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2643 indir_index);
2644
2645 for (unsigned i = 0; i < instr->num_components; i++) {
2646 value[i] = lds_load(ctx, dw_addr);
2647 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2648 ctx->i32one, "");
2649 }
2650 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2651 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2652 return result;
2653 }
2654
2655 static LLVMValueRef
2656 load_tcs_output(struct nir_to_llvm_context *ctx,
2657 nir_intrinsic_instr *instr)
2658 {
2659 LLVMValueRef dw_addr, stride;
2660 LLVMValueRef value[4], result;
2661 LLVMValueRef vertex_index = NULL;
2662 LLVMValueRef indir_index = NULL;
2663 unsigned const_index = 0;
2664 unsigned param;
2665 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2666 const bool is_compact = instr->variables[0]->var->data.compact;
2667 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2668 radv_get_deref_offset(ctx, instr->variables[0],
2669 false, NULL, per_vertex ? &vertex_index : NULL,
2670 &const_index, &indir_index);
2671
2672 if (!instr->variables[0]->var->data.patch) {
2673 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2674 dw_addr = get_tcs_out_current_patch_offset(ctx);
2675 } else {
2676 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2677 }
2678
2679 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2680 indir_index);
2681
2682 for (unsigned i = 0; i < instr->num_components; i++) {
2683 value[i] = lds_load(ctx, dw_addr);
2684 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2685 ctx->i32one, "");
2686 }
2687 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2688 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2689 return result;
2690 }
2691
2692 static void
2693 store_tcs_output(struct nir_to_llvm_context *ctx,
2694 nir_intrinsic_instr *instr,
2695 LLVMValueRef src,
2696 unsigned writemask)
2697 {
2698 LLVMValueRef stride, dw_addr;
2699 LLVMValueRef buf_addr = NULL;
2700 LLVMValueRef vertex_index = NULL;
2701 LLVMValueRef indir_index = NULL;
2702 unsigned const_index = 0;
2703 unsigned param;
2704 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2705 const bool is_compact = instr->variables[0]->var->data.compact;
2706
2707 radv_get_deref_offset(ctx, instr->variables[0],
2708 false, NULL, per_vertex ? &vertex_index : NULL,
2709 &const_index, &indir_index);
2710
2711 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2712 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2713 is_compact && const_index > 3) {
2714 const_index -= 3;
2715 param++;
2716 }
2717
2718 if (!instr->variables[0]->var->data.patch) {
2719 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2720 dw_addr = get_tcs_out_current_patch_offset(ctx);
2721 } else {
2722 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2723 }
2724
2725 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2726
2727 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2728 indir_index);
2729 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2730 vertex_index, indir_index);
2731
2732 unsigned base = is_compact ? const_index : 0;
2733 for (unsigned chan = 0; chan < 8; chan++) {
2734 bool is_tess_factor = false;
2735 if (!(writemask & (1 << chan)))
2736 continue;
2737 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2738
2739 lds_store(ctx, dw_addr, value);
2740
2741 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2742 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2743 is_tess_factor = true;
2744
2745 if (!is_tess_factor && writemask != 0xF)
2746 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2747 buf_addr, ctx->oc_lds,
2748 4 * (base + chan), 1, 0, true, false);
2749
2750 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2751 ctx->i32one, "");
2752 }
2753
2754 if (writemask == 0xF) {
2755 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2756 buf_addr, ctx->oc_lds,
2757 (base * 4), 1, 0, true, false);
2758 }
2759 }
2760
2761 static LLVMValueRef
2762 load_tes_input(struct nir_to_llvm_context *ctx,
2763 nir_intrinsic_instr *instr)
2764 {
2765 LLVMValueRef buf_addr;
2766 LLVMValueRef result;
2767 LLVMValueRef vertex_index = NULL;
2768 LLVMValueRef indir_index = NULL;
2769 unsigned const_index = 0;
2770 unsigned param;
2771 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2772 const bool is_compact = instr->variables[0]->var->data.compact;
2773
2774 radv_get_deref_offset(ctx, instr->variables[0],
2775 false, NULL, per_vertex ? &vertex_index : NULL,
2776 &const_index, &indir_index);
2777 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2778 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2779 is_compact && const_index > 3) {
2780 const_index -= 3;
2781 param++;
2782 }
2783 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2784 is_compact, vertex_index, indir_index);
2785
2786 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2787 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2788 result = trim_vector(ctx, result, instr->num_components);
2789 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2790 return result;
2791 }
2792
2793 static LLVMValueRef
2794 load_gs_input(struct nir_to_llvm_context *ctx,
2795 nir_intrinsic_instr *instr)
2796 {
2797 LLVMValueRef indir_index, vtx_offset;
2798 unsigned const_index;
2799 LLVMValueRef args[9];
2800 unsigned param, vtx_offset_param;
2801 LLVMValueRef value[4], result;
2802 unsigned vertex_index;
2803 radv_get_deref_offset(ctx, instr->variables[0],
2804 false, &vertex_index, NULL,
2805 &const_index, &indir_index);
2806 vtx_offset_param = vertex_index;
2807 assert(vtx_offset_param < 6);
2808 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2809 LLVMConstInt(ctx->i32, 4, false), "");
2810
2811 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2812 for (unsigned i = 0; i < instr->num_components; i++) {
2813
2814 args[0] = ctx->esgs_ring;
2815 args[1] = vtx_offset;
2816 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2817 args[3] = ctx->i32zero;
2818 args[4] = ctx->i32one; /* OFFEN */
2819 args[5] = ctx->i32zero; /* IDXEN */
2820 args[6] = ctx->i32one; /* GLC */
2821 args[7] = ctx->i32zero; /* SLC */
2822 args[8] = ctx->i32zero; /* TFE */
2823
2824 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2825 ctx->i32, args, 9,
2826 AC_FUNC_ATTR_READONLY |
2827 AC_FUNC_ATTR_LEGACY);
2828 }
2829 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2830
2831 return result;
2832 }
2833
2834 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2835 nir_intrinsic_instr *instr)
2836 {
2837 LLVMValueRef values[8];
2838 int idx = instr->variables[0]->var->data.driver_location;
2839 int ve = instr->dest.ssa.num_components;
2840 LLVMValueRef indir_index;
2841 LLVMValueRef ret;
2842 unsigned const_index;
2843 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2844 instr->variables[0]->var->data.mode == nir_var_shader_in;
2845 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2846 &const_index, &indir_index);
2847
2848 if (instr->dest.ssa.bit_size == 64)
2849 ve *= 2;
2850
2851 switch (instr->variables[0]->var->data.mode) {
2852 case nir_var_shader_in:
2853 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2854 return load_tcs_input(ctx, instr);
2855 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2856 return load_tes_input(ctx, instr);
2857 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2858 return load_gs_input(ctx, instr);
2859 }
2860 for (unsigned chan = 0; chan < ve; chan++) {
2861 if (indir_index) {
2862 unsigned count = glsl_count_attribute_slots(
2863 instr->variables[0]->var->type,
2864 ctx->stage == MESA_SHADER_VERTEX);
2865 count -= chan / 4;
2866 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2867 &ctx->ac, ctx->inputs + idx + chan, count,
2868 4, false);
2869
2870 values[chan] = LLVMBuildExtractElement(ctx->builder,
2871 tmp_vec,
2872 indir_index, "");
2873 } else
2874 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2875 }
2876 break;
2877 case nir_var_local:
2878 for (unsigned chan = 0; chan < ve; chan++) {
2879 if (indir_index) {
2880 unsigned count = glsl_count_attribute_slots(
2881 instr->variables[0]->var->type, false);
2882 count -= chan / 4;
2883 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2884 &ctx->ac, ctx->locals + idx + chan, count,
2885 4, true);
2886
2887 values[chan] = LLVMBuildExtractElement(ctx->builder,
2888 tmp_vec,
2889 indir_index, "");
2890 } else {
2891 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2892 }
2893 }
2894 break;
2895 case nir_var_shader_out:
2896 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2897 return load_tcs_output(ctx, instr);
2898 for (unsigned chan = 0; chan < ve; chan++) {
2899 if (indir_index) {
2900 unsigned count = glsl_count_attribute_slots(
2901 instr->variables[0]->var->type, false);
2902 count -= chan / 4;
2903 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2904 &ctx->ac, ctx->outputs + idx + chan, count,
2905 4, true);
2906
2907 values[chan] = LLVMBuildExtractElement(ctx->builder,
2908 tmp_vec,
2909 indir_index, "");
2910 } else {
2911 values[chan] = LLVMBuildLoad(ctx->builder,
2912 ctx->outputs[idx + chan + const_index * 4],
2913 "");
2914 }
2915 }
2916 break;
2917 case nir_var_shared: {
2918 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2919 LLVMValueRef derived_ptr;
2920
2921 if (indir_index)
2922 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2923
2924 for (unsigned chan = 0; chan < ve; chan++) {
2925 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2926 if (indir_index)
2927 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2928 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2929
2930 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2931 }
2932 break;
2933 }
2934 default:
2935 unreachable("unhandle variable mode");
2936 }
2937 ret = ac_build_gather_values(&ctx->ac, values, ve);
2938 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2939 }
2940
2941 static void
2942 visit_store_var(struct nir_to_llvm_context *ctx,
2943 nir_intrinsic_instr *instr)
2944 {
2945 LLVMValueRef temp_ptr, value;
2946 int idx = instr->variables[0]->var->data.driver_location;
2947 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2948 int writemask = instr->const_index[0];
2949 LLVMValueRef indir_index;
2950 unsigned const_index;
2951 radv_get_deref_offset(ctx, instr->variables[0], false,
2952 NULL, NULL, &const_index, &indir_index);
2953
2954 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2955 int old_writemask = writemask;
2956
2957 src = LLVMBuildBitCast(ctx->builder, src,
2958 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2959 "");
2960
2961 writemask = 0;
2962 for (unsigned chan = 0; chan < 4; chan++) {
2963 if (old_writemask & (1 << chan))
2964 writemask |= 3u << (2 * chan);
2965 }
2966 }
2967
2968 switch (instr->variables[0]->var->data.mode) {
2969 case nir_var_shader_out:
2970
2971 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
2972 store_tcs_output(ctx, instr, src, writemask);
2973 return;
2974 }
2975
2976 for (unsigned chan = 0; chan < 8; chan++) {
2977 int stride = 4;
2978 if (!(writemask & (1 << chan)))
2979 continue;
2980
2981 value = llvm_extract_elem(ctx, src, chan);
2982
2983 if (instr->variables[0]->var->data.compact)
2984 stride = 1;
2985 if (indir_index) {
2986 unsigned count = glsl_count_attribute_slots(
2987 instr->variables[0]->var->type, false);
2988 count -= chan / 4;
2989 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2990 &ctx->ac, ctx->outputs + idx + chan, count,
2991 stride, true);
2992
2993 if (get_llvm_num_components(tmp_vec) > 1) {
2994 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2995 value, indir_index, "");
2996 } else
2997 tmp_vec = value;
2998 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2999 count, stride, tmp_vec);
3000
3001 } else {
3002 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3003
3004 LLVMBuildStore(ctx->builder, value, temp_ptr);
3005 }
3006 }
3007 break;
3008 case nir_var_local:
3009 for (unsigned chan = 0; chan < 8; chan++) {
3010 if (!(writemask & (1 << chan)))
3011 continue;
3012
3013 value = llvm_extract_elem(ctx, src, chan);
3014 if (indir_index) {
3015 unsigned count = glsl_count_attribute_slots(
3016 instr->variables[0]->var->type, false);
3017 count -= chan / 4;
3018 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3019 &ctx->ac, ctx->locals + idx + chan, count,
3020 4, true);
3021
3022 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3023 value, indir_index, "");
3024 build_store_values_extended(ctx, ctx->locals + idx + chan,
3025 count, 4, tmp_vec);
3026 } else {
3027 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3028
3029 LLVMBuildStore(ctx->builder, value, temp_ptr);
3030 }
3031 }
3032 break;
3033 case nir_var_shared: {
3034 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3035
3036 if (indir_index)
3037 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
3038
3039 for (unsigned chan = 0; chan < 8; chan++) {
3040 if (!(writemask & (1 << chan)))
3041 continue;
3042 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
3043 LLVMValueRef derived_ptr;
3044
3045 if (indir_index)
3046 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
3047
3048 value = llvm_extract_elem(ctx, src, chan);
3049 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
3050 LLVMBuildStore(ctx->builder,
3051 to_integer(ctx, value), derived_ptr);
3052 }
3053 break;
3054 }
3055 default:
3056 break;
3057 }
3058 }
3059
3060 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3061 {
3062 switch (dim) {
3063 case GLSL_SAMPLER_DIM_BUF:
3064 return 1;
3065 case GLSL_SAMPLER_DIM_1D:
3066 return array ? 2 : 1;
3067 case GLSL_SAMPLER_DIM_2D:
3068 return array ? 3 : 2;
3069 case GLSL_SAMPLER_DIM_MS:
3070 return array ? 4 : 3;
3071 case GLSL_SAMPLER_DIM_3D:
3072 case GLSL_SAMPLER_DIM_CUBE:
3073 return 3;
3074 case GLSL_SAMPLER_DIM_RECT:
3075 case GLSL_SAMPLER_DIM_SUBPASS:
3076 return 2;
3077 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3078 return 3;
3079 default:
3080 break;
3081 }
3082 return 0;
3083 }
3084
3085
3086
3087 /* Adjust the sample index according to FMASK.
3088 *
3089 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3090 * which is the identity mapping. Each nibble says which physical sample
3091 * should be fetched to get that sample.
3092 *
3093 * For example, 0x11111100 means there are only 2 samples stored and
3094 * the second sample covers 3/4 of the pixel. When reading samples 0
3095 * and 1, return physical sample 0 (determined by the first two 0s
3096 * in FMASK), otherwise return physical sample 1.
3097 *
3098 * The sample index should be adjusted as follows:
3099 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3100 */
3101 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3102 LLVMValueRef coord_x, LLVMValueRef coord_y,
3103 LLVMValueRef coord_z,
3104 LLVMValueRef sample_index,
3105 LLVMValueRef fmask_desc_ptr)
3106 {
3107 LLVMValueRef fmask_load_address[4];
3108 LLVMValueRef res;
3109
3110 fmask_load_address[0] = coord_x;
3111 fmask_load_address[1] = coord_y;
3112 if (coord_z) {
3113 fmask_load_address[2] = coord_z;
3114 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3115 }
3116
3117 struct ac_image_args args = {0};
3118
3119 args.opcode = ac_image_load;
3120 args.da = coord_z ? true : false;
3121 args.resource = fmask_desc_ptr;
3122 args.dmask = 0xf;
3123 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3124
3125 res = ac_build_image_opcode(&ctx->ac, &args);
3126
3127 res = to_integer(ctx, res);
3128 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3129 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3130
3131 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3132 res,
3133 ctx->i32zero, "");
3134
3135 LLVMValueRef sample_index4 =
3136 LLVMBuildMul(ctx->builder, sample_index, four, "");
3137 LLVMValueRef shifted_fmask =
3138 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3139 LLVMValueRef final_sample =
3140 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3141
3142 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3143 * resource descriptor is 0 (invalid),
3144 */
3145 LLVMValueRef fmask_desc =
3146 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3147 ctx->v8i32, "");
3148
3149 LLVMValueRef fmask_word1 =
3150 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3151 ctx->i32one, "");
3152
3153 LLVMValueRef word1_is_nonzero =
3154 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3155 fmask_word1, ctx->i32zero, "");
3156
3157 /* Replace the MSAA sample index. */
3158 sample_index =
3159 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3160 final_sample, sample_index, "");
3161 return sample_index;
3162 }
3163
3164 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3165 nir_intrinsic_instr *instr)
3166 {
3167 const struct glsl_type *type = instr->variables[0]->var->type;
3168 if(instr->variables[0]->deref.child)
3169 type = instr->variables[0]->deref.child->type;
3170
3171 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3172 LLVMValueRef coords[4];
3173 LLVMValueRef masks[] = {
3174 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3175 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3176 };
3177 LLVMValueRef res;
3178 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3179
3180 int count;
3181 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3182 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3183 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3184 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3185 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3186
3187 count = image_type_to_components_count(dim,
3188 glsl_sampler_type_is_array(type));
3189
3190 if (is_ms) {
3191 LLVMValueRef fmask_load_address[3];
3192 int chan;
3193
3194 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3195 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3196 if (glsl_sampler_type_is_array(type))
3197 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3198 else
3199 fmask_load_address[2] = NULL;
3200 if (add_frag_pos) {
3201 for (chan = 0; chan < 2; ++chan)
3202 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3203 }
3204 sample_index = adjust_sample_index_using_fmask(ctx,
3205 fmask_load_address[0],
3206 fmask_load_address[1],
3207 fmask_load_address[2],
3208 sample_index,
3209 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3210 }
3211 if (count == 1) {
3212 if (instr->src[0].ssa->num_components)
3213 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3214 else
3215 res = src0;
3216 } else {
3217 int chan;
3218 if (is_ms)
3219 count--;
3220 for (chan = 0; chan < count; ++chan) {
3221 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3222 }
3223
3224 if (add_frag_pos) {
3225 for (chan = 0; chan < count; ++chan)
3226 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3227 }
3228 if (is_ms) {
3229 coords[count] = sample_index;
3230 count++;
3231 }
3232
3233 if (count == 3) {
3234 coords[3] = LLVMGetUndef(ctx->i32);
3235 count = 4;
3236 }
3237 res = ac_build_gather_values(&ctx->ac, coords, count);
3238 }
3239 return res;
3240 }
3241
3242 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3243 nir_intrinsic_instr *instr)
3244 {
3245 LLVMValueRef params[7];
3246 LLVMValueRef res;
3247 char intrinsic_name[64];
3248 const nir_variable *var = instr->variables[0]->var;
3249 const struct glsl_type *type = var->type;
3250 if(instr->variables[0]->deref.child)
3251 type = instr->variables[0]->deref.child->type;
3252
3253 type = glsl_without_array(type);
3254 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3255 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3256 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3257 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3258 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3259 params[3] = ctx->i1false; /* glc */
3260 params[4] = ctx->i1false; /* slc */
3261 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3262 params, 5, 0);
3263
3264 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3265 res = to_integer(ctx, res);
3266 } else {
3267 bool is_da = glsl_sampler_type_is_array(type) ||
3268 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3269 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3270 LLVMValueRef glc = ctx->i1false;
3271 LLVMValueRef slc = ctx->i1false;
3272
3273 params[0] = get_image_coords(ctx, instr);
3274 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3275 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3276 if (HAVE_LLVM <= 0x0309) {
3277 params[3] = ctx->i1false; /* r128 */
3278 params[4] = da;
3279 params[5] = glc;
3280 params[6] = slc;
3281 } else {
3282 LLVMValueRef lwe = ctx->i1false;
3283 params[3] = glc;
3284 params[4] = slc;
3285 params[5] = lwe;
3286 params[6] = da;
3287 }
3288
3289 ac_get_image_intr_name("llvm.amdgcn.image.load",
3290 ctx->v4f32, /* vdata */
3291 LLVMTypeOf(params[0]), /* coords */
3292 LLVMTypeOf(params[1]), /* rsrc */
3293 intrinsic_name, sizeof(intrinsic_name));
3294
3295 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3296 params, 7, AC_FUNC_ATTR_READONLY);
3297 }
3298 return to_integer(ctx, res);
3299 }
3300
3301 static void visit_image_store(struct nir_to_llvm_context *ctx,
3302 nir_intrinsic_instr *instr)
3303 {
3304 LLVMValueRef params[8];
3305 char intrinsic_name[64];
3306 const nir_variable *var = instr->variables[0]->var;
3307 const struct glsl_type *type = glsl_without_array(var->type);
3308
3309 if (ctx->stage == MESA_SHADER_FRAGMENT)
3310 ctx->shader_info->fs.writes_memory = true;
3311
3312 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3313 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
3314 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3315 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3316 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3317 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3318 params[4] = ctx->i1false; /* glc */
3319 params[5] = ctx->i1false; /* slc */
3320 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3321 params, 6, 0);
3322 } else {
3323 bool is_da = glsl_sampler_type_is_array(type) ||
3324 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3325 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3326 LLVMValueRef glc = ctx->i1false;
3327 LLVMValueRef slc = ctx->i1false;
3328
3329 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
3330 params[1] = get_image_coords(ctx, instr); /* coords */
3331 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3332 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3333 if (HAVE_LLVM <= 0x0309) {
3334 params[4] = ctx->i1false; /* r128 */
3335 params[5] = da;
3336 params[6] = glc;
3337 params[7] = slc;
3338 } else {
3339 LLVMValueRef lwe = ctx->i1false;
3340 params[4] = glc;
3341 params[5] = slc;
3342 params[6] = lwe;
3343 params[7] = da;
3344 }
3345
3346 ac_get_image_intr_name("llvm.amdgcn.image.store",
3347 LLVMTypeOf(params[0]), /* vdata */
3348 LLVMTypeOf(params[1]), /* coords */
3349 LLVMTypeOf(params[2]), /* rsrc */
3350 intrinsic_name, sizeof(intrinsic_name));
3351
3352 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3353 params, 8, 0);
3354 }
3355
3356 }
3357
3358 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3359 nir_intrinsic_instr *instr)
3360 {
3361 LLVMValueRef params[6];
3362 int param_count = 0;
3363 const nir_variable *var = instr->variables[0]->var;
3364
3365 const char *base_name = "llvm.amdgcn.image.atomic";
3366 const char *atomic_name;
3367 LLVMValueRef coords;
3368 char intrinsic_name[32], coords_type[8];
3369 const struct glsl_type *type = glsl_without_array(var->type);
3370
3371 if (ctx->stage == MESA_SHADER_FRAGMENT)
3372 ctx->shader_info->fs.writes_memory = true;
3373
3374 params[param_count++] = get_src(ctx, instr->src[2]);
3375 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3376 params[param_count++] = get_src(ctx, instr->src[3]);
3377
3378 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3379 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3380 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3381 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3382 params[param_count++] = ctx->i32zero; /* voffset */
3383 params[param_count++] = ctx->i1false; /* glc */
3384 params[param_count++] = ctx->i1false; /* slc */
3385 } else {
3386 bool da = glsl_sampler_type_is_array(type) ||
3387 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3388
3389 coords = params[param_count++] = get_image_coords(ctx, instr);
3390 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3391 params[param_count++] = ctx->i1false; /* r128 */
3392 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3393 params[param_count++] = ctx->i1false; /* slc */
3394 }
3395
3396 switch (instr->intrinsic) {
3397 case nir_intrinsic_image_atomic_add:
3398 atomic_name = "add";
3399 break;
3400 case nir_intrinsic_image_atomic_min:
3401 atomic_name = "smin";
3402 break;
3403 case nir_intrinsic_image_atomic_max:
3404 atomic_name = "smax";
3405 break;
3406 case nir_intrinsic_image_atomic_and:
3407 atomic_name = "and";
3408 break;
3409 case nir_intrinsic_image_atomic_or:
3410 atomic_name = "or";
3411 break;
3412 case nir_intrinsic_image_atomic_xor:
3413 atomic_name = "xor";
3414 break;
3415 case nir_intrinsic_image_atomic_exchange:
3416 atomic_name = "swap";
3417 break;
3418 case nir_intrinsic_image_atomic_comp_swap:
3419 atomic_name = "cmpswap";
3420 break;
3421 default:
3422 abort();
3423 }
3424 build_int_type_name(LLVMTypeOf(coords),
3425 coords_type, sizeof(coords_type));
3426
3427 snprintf(intrinsic_name, sizeof(intrinsic_name),
3428 "%s.%s.%s", base_name, atomic_name, coords_type);
3429 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3430 }
3431
3432 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3433 nir_intrinsic_instr *instr)
3434 {
3435 LLVMValueRef res;
3436 const nir_variable *var = instr->variables[0]->var;
3437 const struct glsl_type *type = instr->variables[0]->var->type;
3438 bool da = glsl_sampler_type_is_array(var->type) ||
3439 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3440 if(instr->variables[0]->deref.child)
3441 type = instr->variables[0]->deref.child->type;
3442
3443 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3444 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3445
3446 struct ac_image_args args = { 0 };
3447
3448 args.da = da;
3449 args.dmask = 0xf;
3450 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3451 args.opcode = ac_image_get_resinfo;
3452 args.addr = ctx->i32zero;
3453
3454 res = ac_build_image_opcode(&ctx->ac, &args);
3455
3456 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3457 glsl_sampler_type_is_array(type)) {
3458 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3459 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3460 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3461 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3462 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3463 }
3464 return res;
3465 }
3466
3467 #define NOOP_WAITCNT 0xf7f
3468 #define LGKM_CNT 0x07f
3469 #define VM_CNT 0xf70
3470
3471 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3472 unsigned simm16)
3473 {
3474 LLVMValueRef args[1] = {
3475 LLVMConstInt(ctx->i32, simm16, false),
3476 };
3477 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3478 ctx->voidt, args, 1, 0);
3479 }
3480
3481 static void emit_barrier(struct nir_to_llvm_context *ctx)
3482 {
3483 /* SI only (thanks to a hw bug workaround):
3484 * The real barrier instruction isn’t needed, because an entire patch
3485 * always fits into a single wave.
3486 */
3487 if (ctx->options->chip_class == SI &&
3488 ctx->stage == MESA_SHADER_TESS_CTRL) {
3489 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3490 return;
3491 }
3492 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3493 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3494 }
3495
3496 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3497 nir_intrinsic_instr *instr)
3498 {
3499 LLVMValueRef cond;
3500 ctx->shader_info->fs.can_discard = true;
3501
3502 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3503 get_src(ctx, instr->src[0]),
3504 ctx->i32zero, "");
3505
3506 cond = LLVMBuildSelect(ctx->builder, cond,
3507 LLVMConstReal(ctx->f32, -1.0f),
3508 ctx->f32zero, "");
3509 ac_build_kill(&ctx->ac, cond);
3510 }
3511
3512 static LLVMValueRef
3513 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3514 {
3515 LLVMValueRef result;
3516 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3517 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3518 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3519
3520 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3521 }
3522
3523 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3524 nir_intrinsic_instr *instr)
3525 {
3526 LLVMValueRef ptr, result;
3527 int idx = instr->variables[0]->var->data.driver_location;
3528 LLVMValueRef src = get_src(ctx, instr->src[0]);
3529 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3530
3531 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3532 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3533 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3534 ptr, src, src1,
3535 LLVMAtomicOrderingSequentiallyConsistent,
3536 LLVMAtomicOrderingSequentiallyConsistent,
3537 false);
3538 } else {
3539 LLVMAtomicRMWBinOp op;
3540 switch (instr->intrinsic) {
3541 case nir_intrinsic_var_atomic_add:
3542 op = LLVMAtomicRMWBinOpAdd;
3543 break;
3544 case nir_intrinsic_var_atomic_umin:
3545 op = LLVMAtomicRMWBinOpUMin;
3546 break;
3547 case nir_intrinsic_var_atomic_umax:
3548 op = LLVMAtomicRMWBinOpUMax;
3549 break;
3550 case nir_intrinsic_var_atomic_imin:
3551 op = LLVMAtomicRMWBinOpMin;
3552 break;
3553 case nir_intrinsic_var_atomic_imax:
3554 op = LLVMAtomicRMWBinOpMax;
3555 break;
3556 case nir_intrinsic_var_atomic_and:
3557 op = LLVMAtomicRMWBinOpAnd;
3558 break;
3559 case nir_intrinsic_var_atomic_or:
3560 op = LLVMAtomicRMWBinOpOr;
3561 break;
3562 case nir_intrinsic_var_atomic_xor:
3563 op = LLVMAtomicRMWBinOpXor;
3564 break;
3565 case nir_intrinsic_var_atomic_exchange:
3566 op = LLVMAtomicRMWBinOpXchg;
3567 break;
3568 default:
3569 return NULL;
3570 }
3571
3572 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3573 LLVMAtomicOrderingSequentiallyConsistent,
3574 false);
3575 }
3576 return result;
3577 }
3578
3579 #define INTERP_CENTER 0
3580 #define INTERP_CENTROID 1
3581 #define INTERP_SAMPLE 2
3582
3583 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3584 enum glsl_interp_mode interp, unsigned location)
3585 {
3586 switch (interp) {
3587 case INTERP_MODE_FLAT:
3588 default:
3589 return NULL;
3590 case INTERP_MODE_SMOOTH:
3591 case INTERP_MODE_NONE:
3592 if (location == INTERP_CENTER)
3593 return ctx->persp_center;
3594 else if (location == INTERP_CENTROID)
3595 return ctx->persp_centroid;
3596 else if (location == INTERP_SAMPLE)
3597 return ctx->persp_sample;
3598 break;
3599 case INTERP_MODE_NOPERSPECTIVE:
3600 if (location == INTERP_CENTER)
3601 return ctx->linear_center;
3602 else if (location == INTERP_CENTROID)
3603 return ctx->linear_centroid;
3604 else if (location == INTERP_SAMPLE)
3605 return ctx->linear_sample;
3606 break;
3607 }
3608 return NULL;
3609 }
3610
3611 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3612 LLVMValueRef sample_id)
3613 {
3614 LLVMValueRef result;
3615 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3616
3617 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3618 const_array(ctx->v2f32, 64), "");
3619
3620 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3621 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3622
3623 return result;
3624 }
3625
3626 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3627 {
3628 LLVMValueRef values[2];
3629
3630 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3631 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3632 return ac_build_gather_values(&ctx->ac, values, 2);
3633 }
3634
3635 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3636 nir_intrinsic_instr *instr)
3637 {
3638 LLVMValueRef result[2];
3639 LLVMValueRef interp_param, attr_number;
3640 unsigned location;
3641 unsigned chan;
3642 LLVMValueRef src_c0, src_c1;
3643 LLVMValueRef src0;
3644 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3645 switch (instr->intrinsic) {
3646 case nir_intrinsic_interp_var_at_centroid:
3647 location = INTERP_CENTROID;
3648 break;
3649 case nir_intrinsic_interp_var_at_sample:
3650 case nir_intrinsic_interp_var_at_offset:
3651 location = INTERP_CENTER;
3652 src0 = get_src(ctx, instr->src[0]);
3653 break;
3654 default:
3655 break;
3656 }
3657
3658 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3659 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3660 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3661 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3662 LLVMValueRef sample_position;
3663 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3664
3665 /* fetch sample ID */
3666 sample_position = load_sample_position(ctx, src0);
3667
3668 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3669 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3670 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3671 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3672 }
3673 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3674 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3675
3676 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3677 LLVMValueRef ij_out[2];
3678 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3679
3680 /*
3681 * take the I then J parameters, and the DDX/Y for it, and
3682 * calculate the IJ inputs for the interpolator.
3683 * temp1 = ddx * offset/sample.x + I;
3684 * interp_param.I = ddy * offset/sample.y + temp1;
3685 * temp1 = ddx * offset/sample.x + J;
3686 * interp_param.J = ddy * offset/sample.y + temp1;
3687 */
3688 for (unsigned i = 0; i < 2; i++) {
3689 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3690 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3691 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3692 ddxy_out, ix_ll, "");
3693 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3694 ddxy_out, iy_ll, "");
3695 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3696 interp_param, ix_ll, "");
3697 LLVMValueRef temp1, temp2;
3698
3699 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3700 ctx->f32, "");
3701
3702 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3703 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3704
3705 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3706 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3707
3708 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3709 temp2, ctx->i32, "");
3710 }
3711 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3712
3713 }
3714
3715 for (chan = 0; chan < 2; chan++) {
3716 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3717
3718 if (interp_param) {
3719 interp_param = LLVMBuildBitCast(ctx->builder,
3720 interp_param, LLVMVectorType(ctx->f32, 2), "");
3721 LLVMValueRef i = LLVMBuildExtractElement(
3722 ctx->builder, interp_param, ctx->i32zero, "");
3723 LLVMValueRef j = LLVMBuildExtractElement(
3724 ctx->builder, interp_param, ctx->i32one, "");
3725
3726 result[chan] = ac_build_fs_interp(&ctx->ac,
3727 llvm_chan, attr_number,
3728 ctx->prim_mask, i, j);
3729 } else {
3730 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3731 LLVMConstInt(ctx->i32, 2, false),
3732 llvm_chan, attr_number,
3733 ctx->prim_mask);
3734 }
3735 }
3736 return ac_build_gather_values(&ctx->ac, result, 2);
3737 }
3738
3739 static void
3740 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3741 nir_intrinsic_instr *instr)
3742 {
3743 LLVMValueRef gs_next_vertex;
3744 LLVMValueRef can_emit, kill;
3745 int idx;
3746
3747 assert(instr->const_index[0] == 0);
3748 /* Write vertex attribute values to GSVS ring */
3749 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3750 ctx->gs_next_vertex,
3751 "");
3752
3753 /* If this thread has already emitted the declared maximum number of
3754 * vertices, kill it: excessive vertex emissions are not supposed to
3755 * have any effect, and GS threads have no externally observable
3756 * effects other than emitting vertices.
3757 */
3758 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3759 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3760
3761 kill = LLVMBuildSelect(ctx->builder, can_emit,
3762 LLVMConstReal(ctx->f32, 1.0f),
3763 LLVMConstReal(ctx->f32, -1.0f), "");
3764 ac_build_kill(&ctx->ac, kill);
3765
3766 /* loop num outputs */
3767 idx = 0;
3768 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3769 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3770 int length = 4;
3771 int slot = idx;
3772 int slot_inc = 1;
3773
3774 if (!(ctx->output_mask & (1ull << i)))
3775 continue;
3776
3777 if (i == VARYING_SLOT_CLIP_DIST0) {
3778 /* pack clip and cull into a single set of slots */
3779 length = ctx->num_output_clips + ctx->num_output_culls;
3780 if (length > 4)
3781 slot_inc = 2;
3782 }
3783 for (unsigned j = 0; j < length; j++) {
3784 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3785 out_ptr[j], "");
3786 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3787 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3788 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3789
3790 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3791
3792 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3793 out_val, 1,
3794 voffset, ctx->gs2vs_offset, 0,
3795 1, 1, true, true);
3796 }
3797 idx += slot_inc;
3798 }
3799
3800 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3801 ctx->i32one, "");
3802 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3803
3804 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3805 }
3806
3807 static void
3808 visit_end_primitive(struct nir_to_llvm_context *ctx,
3809 nir_intrinsic_instr *instr)
3810 {
3811 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3812 }
3813
3814 static LLVMValueRef
3815 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3816 nir_intrinsic_instr *instr)
3817 {
3818 LLVMValueRef coord[4] = {
3819 ctx->tes_u,
3820 ctx->tes_v,
3821 ctx->f32zero,
3822 ctx->f32zero,
3823 };
3824
3825 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3826 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3827 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3828
3829 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3830 return LLVMBuildBitCast(ctx->builder, result,
3831 get_def_type(ctx, &instr->dest.ssa), "");
3832 }
3833
3834 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3835 nir_intrinsic_instr *instr)
3836 {
3837 LLVMValueRef result = NULL;
3838
3839 switch (instr->intrinsic) {
3840 case nir_intrinsic_load_work_group_id: {
3841 result = ctx->workgroup_ids;
3842 break;
3843 }
3844 case nir_intrinsic_load_base_vertex: {
3845 result = ctx->base_vertex;
3846 break;
3847 }
3848 case nir_intrinsic_load_vertex_id_zero_base: {
3849 result = ctx->vertex_id;
3850 break;
3851 }
3852 case nir_intrinsic_load_local_invocation_id: {
3853 result = ctx->local_invocation_ids;
3854 break;
3855 }
3856 case nir_intrinsic_load_base_instance:
3857 result = ctx->start_instance;
3858 break;
3859 case nir_intrinsic_load_draw_id:
3860 result = ctx->draw_index;
3861 break;
3862 case nir_intrinsic_load_invocation_id:
3863 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3864 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3865 else
3866 result = ctx->gs_invocation_id;
3867 break;
3868 case nir_intrinsic_load_primitive_id:
3869 if (ctx->stage == MESA_SHADER_GEOMETRY)
3870 result = ctx->gs_prim_id;
3871 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
3872 result = ctx->tcs_patch_id;
3873 else if (ctx->stage == MESA_SHADER_TESS_EVAL)
3874 result = ctx->tes_patch_id;
3875 else
3876 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3877 break;
3878 case nir_intrinsic_load_sample_id:
3879 ctx->shader_info->fs.force_persample = true;
3880 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3881 break;
3882 case nir_intrinsic_load_sample_pos:
3883 ctx->shader_info->fs.force_persample = true;
3884 result = load_sample_pos(ctx);
3885 break;
3886 case nir_intrinsic_load_sample_mask_in:
3887 result = ctx->sample_coverage;
3888 break;
3889 case nir_intrinsic_load_front_face:
3890 result = ctx->front_face;
3891 break;
3892 case nir_intrinsic_load_instance_id:
3893 result = ctx->instance_id;
3894 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3895 ctx->shader_info->vs.vgpr_comp_cnt);
3896 break;
3897 case nir_intrinsic_load_num_work_groups:
3898 result = ctx->num_work_groups;
3899 break;
3900 case nir_intrinsic_load_local_invocation_index:
3901 result = visit_load_local_invocation_index(ctx);
3902 break;
3903 case nir_intrinsic_load_push_constant:
3904 result = visit_load_push_constant(ctx, instr);
3905 break;
3906 case nir_intrinsic_vulkan_resource_index:
3907 result = visit_vulkan_resource_index(ctx, instr);
3908 break;
3909 case nir_intrinsic_store_ssbo:
3910 visit_store_ssbo(ctx, instr);
3911 break;
3912 case nir_intrinsic_load_ssbo:
3913 result = visit_load_buffer(ctx, instr);
3914 break;
3915 case nir_intrinsic_ssbo_atomic_add:
3916 case nir_intrinsic_ssbo_atomic_imin:
3917 case nir_intrinsic_ssbo_atomic_umin:
3918 case nir_intrinsic_ssbo_atomic_imax:
3919 case nir_intrinsic_ssbo_atomic_umax:
3920 case nir_intrinsic_ssbo_atomic_and:
3921 case nir_intrinsic_ssbo_atomic_or:
3922 case nir_intrinsic_ssbo_atomic_xor:
3923 case nir_intrinsic_ssbo_atomic_exchange:
3924 case nir_intrinsic_ssbo_atomic_comp_swap:
3925 result = visit_atomic_ssbo(ctx, instr);
3926 break;
3927 case nir_intrinsic_load_ubo:
3928 result = visit_load_ubo_buffer(ctx, instr);
3929 break;
3930 case nir_intrinsic_get_buffer_size:
3931 result = visit_get_buffer_size(ctx, instr);
3932 break;
3933 case nir_intrinsic_load_var:
3934 result = visit_load_var(ctx, instr);
3935 break;
3936 case nir_intrinsic_store_var:
3937 visit_store_var(ctx, instr);
3938 break;
3939 case nir_intrinsic_image_load:
3940 result = visit_image_load(ctx, instr);
3941 break;
3942 case nir_intrinsic_image_store:
3943 visit_image_store(ctx, instr);
3944 break;
3945 case nir_intrinsic_image_atomic_add:
3946 case nir_intrinsic_image_atomic_min:
3947 case nir_intrinsic_image_atomic_max:
3948 case nir_intrinsic_image_atomic_and:
3949 case nir_intrinsic_image_atomic_or:
3950 case nir_intrinsic_image_atomic_xor:
3951 case nir_intrinsic_image_atomic_exchange:
3952 case nir_intrinsic_image_atomic_comp_swap:
3953 result = visit_image_atomic(ctx, instr);
3954 break;
3955 case nir_intrinsic_image_size:
3956 result = visit_image_size(ctx, instr);
3957 break;
3958 case nir_intrinsic_discard:
3959 ctx->shader_info->fs.can_discard = true;
3960 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3961 ctx->voidt,
3962 NULL, 0, AC_FUNC_ATTR_LEGACY);
3963 break;
3964 case nir_intrinsic_discard_if:
3965 emit_discard_if(ctx, instr);
3966 break;
3967 case nir_intrinsic_memory_barrier:
3968 emit_waitcnt(ctx, VM_CNT);
3969 break;
3970 case nir_intrinsic_barrier:
3971 emit_barrier(ctx);
3972 break;
3973 case nir_intrinsic_var_atomic_add:
3974 case nir_intrinsic_var_atomic_imin:
3975 case nir_intrinsic_var_atomic_umin:
3976 case nir_intrinsic_var_atomic_imax:
3977 case nir_intrinsic_var_atomic_umax:
3978 case nir_intrinsic_var_atomic_and:
3979 case nir_intrinsic_var_atomic_or:
3980 case nir_intrinsic_var_atomic_xor:
3981 case nir_intrinsic_var_atomic_exchange:
3982 case nir_intrinsic_var_atomic_comp_swap:
3983 result = visit_var_atomic(ctx, instr);
3984 break;
3985 case nir_intrinsic_interp_var_at_centroid:
3986 case nir_intrinsic_interp_var_at_sample:
3987 case nir_intrinsic_interp_var_at_offset:
3988 result = visit_interp(ctx, instr);
3989 break;
3990 case nir_intrinsic_emit_vertex:
3991 visit_emit_vertex(ctx, instr);
3992 break;
3993 case nir_intrinsic_end_primitive:
3994 visit_end_primitive(ctx, instr);
3995 break;
3996 case nir_intrinsic_load_tess_coord:
3997 result = visit_load_tess_coord(ctx, instr);
3998 break;
3999 case nir_intrinsic_load_patch_vertices_in:
4000 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
4001 break;
4002 default:
4003 fprintf(stderr, "Unknown intrinsic: ");
4004 nir_print_instr(&instr->instr, stderr);
4005 fprintf(stderr, "\n");
4006 break;
4007 }
4008 if (result) {
4009 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4010 }
4011 }
4012
4013 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
4014 nir_deref_var *deref,
4015 enum desc_type desc_type)
4016 {
4017 unsigned desc_set = deref->var->data.descriptor_set;
4018 LLVMValueRef list = ctx->descriptor_sets[desc_set];
4019 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4020 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
4021 unsigned offset = binding->offset;
4022 unsigned stride = binding->size;
4023 unsigned type_size;
4024 LLVMBuilderRef builder = ctx->builder;
4025 LLVMTypeRef type;
4026 LLVMValueRef index = NULL;
4027 unsigned constant_index = 0;
4028
4029 assert(deref->var->data.binding < layout->binding_count);
4030
4031 switch (desc_type) {
4032 case DESC_IMAGE:
4033 type = ctx->v8i32;
4034 type_size = 32;
4035 break;
4036 case DESC_FMASK:
4037 type = ctx->v8i32;
4038 offset += 32;
4039 type_size = 32;
4040 break;
4041 case DESC_SAMPLER:
4042 type = ctx->v4i32;
4043 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4044 offset += 64;
4045
4046 type_size = 16;
4047 break;
4048 case DESC_BUFFER:
4049 type = ctx->v4i32;
4050 type_size = 16;
4051 break;
4052 default:
4053 unreachable("invalid desc_type\n");
4054 }
4055
4056 if (deref->deref.child) {
4057 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
4058
4059 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4060 offset += child->base_offset * stride;
4061 if (child->deref_array_type == nir_deref_array_type_indirect) {
4062 index = get_src(ctx, child->indirect);
4063 }
4064
4065 constant_index = child->base_offset;
4066 }
4067 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
4068 (!index || binding->immutable_samplers_equal)) {
4069 if (binding->immutable_samplers_equal)
4070 constant_index = 0;
4071
4072 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4073
4074 LLVMValueRef constants[] = {
4075 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4076 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4077 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4078 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4079 };
4080 return ac_build_gather_values(&ctx->ac, constants, 4);
4081 }
4082
4083 assert(stride % type_size == 0);
4084
4085 if (!index)
4086 index = ctx->i32zero;
4087
4088 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4089
4090 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4091 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4092
4093 return ac_build_indexed_load_const(&ctx->ac, list, index);
4094 }
4095
4096 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4097 struct ac_image_args *args,
4098 nir_tex_instr *instr,
4099 nir_texop op,
4100 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4101 LLVMValueRef *param, unsigned count,
4102 unsigned dmask)
4103 {
4104 unsigned is_rect = 0;
4105 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4106
4107 if (op == nir_texop_lod)
4108 da = false;
4109 /* Pad to power of two vector */
4110 while (count < util_next_power_of_two(count))
4111 param[count++] = LLVMGetUndef(ctx->i32);
4112
4113 if (count > 1)
4114 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4115 else
4116 args->addr = param[0];
4117
4118 args->resource = res_ptr;
4119 args->sampler = samp_ptr;
4120
4121 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4122 args->addr = param[0];
4123 return;
4124 }
4125
4126 args->dmask = dmask;
4127 args->unorm = is_rect;
4128 args->da = da;
4129 }
4130
4131 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4132 *
4133 * SI-CI:
4134 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4135 * filtering manually. The driver sets img7 to a mask clearing
4136 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4137 * s_and_b32 samp0, samp0, img7
4138 *
4139 * VI:
4140 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4141 */
4142 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4143 LLVMValueRef res, LLVMValueRef samp)
4144 {
4145 LLVMBuilderRef builder = ctx->builder;
4146 LLVMValueRef img7, samp0;
4147
4148 if (ctx->options->chip_class >= VI)
4149 return samp;
4150
4151 img7 = LLVMBuildExtractElement(builder, res,
4152 LLVMConstInt(ctx->i32, 7, 0), "");
4153 samp0 = LLVMBuildExtractElement(builder, samp,
4154 LLVMConstInt(ctx->i32, 0, 0), "");
4155 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4156 return LLVMBuildInsertElement(builder, samp, samp0,
4157 LLVMConstInt(ctx->i32, 0, 0), "");
4158 }
4159
4160 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4161 nir_tex_instr *instr,
4162 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4163 LLVMValueRef *fmask_ptr)
4164 {
4165 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4166 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4167 else
4168 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4169 if (samp_ptr) {
4170 if (instr->sampler)
4171 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4172 else
4173 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4174 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4175 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4176 }
4177 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4178 instr->op == nir_texop_samples_identical))
4179 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4180 }
4181
4182 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4183 LLVMValueRef coord)
4184 {
4185 coord = to_float(ctx, coord);
4186 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4187 coord = to_integer(ctx, coord);
4188 return coord;
4189 }
4190
4191 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4192 {
4193 LLVMValueRef result = NULL;
4194 struct ac_image_args args = { 0 };
4195 unsigned dmask = 0xf;
4196 LLVMValueRef address[16];
4197 LLVMValueRef coords[5];
4198 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4199 LLVMValueRef bias = NULL, offsets = NULL;
4200 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4201 LLVMValueRef ddx = NULL, ddy = NULL;
4202 LLVMValueRef derivs[6];
4203 unsigned chan, count = 0;
4204 unsigned const_src = 0, num_deriv_comp = 0;
4205 bool lod_is_zero = false;
4206 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4207
4208 for (unsigned i = 0; i < instr->num_srcs; i++) {
4209 switch (instr->src[i].src_type) {
4210 case nir_tex_src_coord:
4211 coord = get_src(ctx, instr->src[i].src);
4212 break;
4213 case nir_tex_src_projector:
4214 break;
4215 case nir_tex_src_comparator:
4216 comparator = get_src(ctx, instr->src[i].src);
4217 break;
4218 case nir_tex_src_offset:
4219 offsets = get_src(ctx, instr->src[i].src);
4220 const_src = i;
4221 break;
4222 case nir_tex_src_bias:
4223 bias = get_src(ctx, instr->src[i].src);
4224 break;
4225 case nir_tex_src_lod: {
4226 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4227
4228 if (val && val->i32[0] == 0)
4229 lod_is_zero = true;
4230 lod = get_src(ctx, instr->src[i].src);
4231 break;
4232 }
4233 case nir_tex_src_ms_index:
4234 sample_index = get_src(ctx, instr->src[i].src);
4235 break;
4236 case nir_tex_src_ms_mcs:
4237 break;
4238 case nir_tex_src_ddx:
4239 ddx = get_src(ctx, instr->src[i].src);
4240 num_deriv_comp = instr->src[i].src.ssa->num_components;
4241 break;
4242 case nir_tex_src_ddy:
4243 ddy = get_src(ctx, instr->src[i].src);
4244 break;
4245 case nir_tex_src_texture_offset:
4246 case nir_tex_src_sampler_offset:
4247 case nir_tex_src_plane:
4248 default:
4249 break;
4250 }
4251 }
4252
4253 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4254 result = get_buffer_size(ctx, res_ptr, true);
4255 goto write_result;
4256 }
4257
4258 if (instr->op == nir_texop_texture_samples) {
4259 LLVMValueRef res, samples, is_msaa;
4260 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4261 samples = LLVMBuildExtractElement(ctx->builder, res,
4262 LLVMConstInt(ctx->i32, 3, false), "");
4263 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4264 LLVMConstInt(ctx->i32, 28, false), "");
4265 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4266 LLVMConstInt(ctx->i32, 0xe, false), "");
4267 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4268 LLVMConstInt(ctx->i32, 0xe, false), "");
4269
4270 samples = LLVMBuildLShr(ctx->builder, samples,
4271 LLVMConstInt(ctx->i32, 16, false), "");
4272 samples = LLVMBuildAnd(ctx->builder, samples,
4273 LLVMConstInt(ctx->i32, 0xf, false), "");
4274 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4275 samples, "");
4276 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4277 ctx->i32one, "");
4278 result = samples;
4279 goto write_result;
4280 }
4281
4282 if (coord)
4283 for (chan = 0; chan < instr->coord_components; chan++)
4284 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4285
4286 if (offsets && instr->op != nir_texop_txf) {
4287 LLVMValueRef offset[3], pack;
4288 for (chan = 0; chan < 3; ++chan)
4289 offset[chan] = ctx->i32zero;
4290
4291 args.offset = true;
4292 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4293 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4294 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4295 LLVMConstInt(ctx->i32, 0x3f, false), "");
4296 if (chan)
4297 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4298 LLVMConstInt(ctx->i32, chan * 8, false), "");
4299 }
4300 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4301 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4302 address[count++] = pack;
4303
4304 }
4305 /* pack LOD bias value */
4306 if (instr->op == nir_texop_txb && bias) {
4307 address[count++] = bias;
4308 }
4309
4310 /* Pack depth comparison value */
4311 if (instr->is_shadow && comparator) {
4312 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4313 }
4314
4315 /* pack derivatives */
4316 if (ddx || ddy) {
4317 switch (instr->sampler_dim) {
4318 case GLSL_SAMPLER_DIM_3D:
4319 case GLSL_SAMPLER_DIM_CUBE:
4320 num_deriv_comp = 3;
4321 break;
4322 case GLSL_SAMPLER_DIM_2D:
4323 default:
4324 num_deriv_comp = 2;
4325 break;
4326 case GLSL_SAMPLER_DIM_1D:
4327 num_deriv_comp = 1;
4328 break;
4329 }
4330
4331 for (unsigned i = 0; i < num_deriv_comp; i++) {
4332 derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
4333 derivs[num_deriv_comp + i] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
4334 }
4335 }
4336
4337 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4338 if (instr->is_array && instr->op != nir_texop_lod)
4339 coords[3] = apply_round_slice(ctx, coords[3]);
4340 for (chan = 0; chan < instr->coord_components; chan++)
4341 coords[chan] = to_float(ctx, coords[chan]);
4342 if (instr->coord_components == 3)
4343 coords[3] = LLVMGetUndef(ctx->f32);
4344 ac_prepare_cube_coords(&ctx->ac,
4345 instr->op == nir_texop_txd, instr->is_array,
4346 coords, derivs);
4347 if (num_deriv_comp)
4348 num_deriv_comp--;
4349 }
4350
4351 if (ddx || ddy) {
4352 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4353 address[count++] = derivs[i];
4354 }
4355
4356 /* Pack texture coordinates */
4357 if (coord) {
4358 address[count++] = coords[0];
4359 if (instr->coord_components > 1) {
4360 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4361 coords[1] = apply_round_slice(ctx, coords[1]);
4362 }
4363 address[count++] = coords[1];
4364 }
4365 if (instr->coord_components > 2) {
4366 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4367 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4368 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4369 instr->op != nir_texop_txf) {
4370 coords[2] = apply_round_slice(ctx, coords[2]);
4371 }
4372 address[count++] = coords[2];
4373 }
4374 }
4375
4376 /* Pack LOD */
4377 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4378 instr->op == nir_texop_txf)) {
4379 address[count++] = lod;
4380 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4381 address[count++] = sample_index;
4382 } else if(instr->op == nir_texop_txs) {
4383 count = 0;
4384 if (lod)
4385 address[count++] = lod;
4386 else
4387 address[count++] = ctx->i32zero;
4388 }
4389
4390 for (chan = 0; chan < count; chan++) {
4391 address[chan] = LLVMBuildBitCast(ctx->builder,
4392 address[chan], ctx->i32, "");
4393 }
4394
4395 if (instr->op == nir_texop_samples_identical) {
4396 LLVMValueRef txf_address[4];
4397 struct ac_image_args txf_args = { 0 };
4398 unsigned txf_count = count;
4399 memcpy(txf_address, address, sizeof(txf_address));
4400
4401 if (!instr->is_array)
4402 txf_address[2] = ctx->i32zero;
4403 txf_address[3] = ctx->i32zero;
4404
4405 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4406 fmask_ptr, NULL,
4407 txf_address, txf_count, 0xf);
4408
4409 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4410
4411 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4412 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
4413 goto write_result;
4414 }
4415
4416 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4417 instr->op != nir_texop_txs) {
4418 unsigned sample_chan = instr->is_array ? 3 : 2;
4419 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4420 address[0],
4421 address[1],
4422 instr->is_array ? address[2] : NULL,
4423 address[sample_chan],
4424 fmask_ptr);
4425 }
4426
4427 if (offsets && instr->op == nir_texop_txf) {
4428 nir_const_value *const_offset =
4429 nir_src_as_const_value(instr->src[const_src].src);
4430 int num_offsets = instr->src[const_src].src.ssa->num_components;
4431 assert(const_offset);
4432 num_offsets = MIN2(num_offsets, instr->coord_components);
4433 if (num_offsets > 2)
4434 address[2] = LLVMBuildAdd(ctx->builder,
4435 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4436 if (num_offsets > 1)
4437 address[1] = LLVMBuildAdd(ctx->builder,
4438 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4439 address[0] = LLVMBuildAdd(ctx->builder,
4440 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4441
4442 }
4443
4444 /* TODO TG4 support */
4445 if (instr->op == nir_texop_tg4) {
4446 if (instr->is_shadow)
4447 dmask = 1;
4448 else
4449 dmask = 1 << instr->component;
4450 }
4451 set_tex_fetch_args(ctx, &args, instr, instr->op,
4452 res_ptr, samp_ptr, address, count, dmask);
4453
4454 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4455
4456 if (instr->op == nir_texop_query_levels)
4457 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4458 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4459 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4460 else if (instr->op == nir_texop_txs &&
4461 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4462 instr->is_array) {
4463 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4464 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4465 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4466 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4467 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4468 } else if (instr->dest.ssa.num_components != 4)
4469 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4470
4471 write_result:
4472 if (result) {
4473 assert(instr->dest.is_ssa);
4474 result = to_integer(ctx, result);
4475 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4476 }
4477 }
4478
4479
4480 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4481 {
4482 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4483 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4484
4485 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4486 _mesa_hash_table_insert(ctx->phis, instr, result);
4487 }
4488
4489 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4490 nir_phi_instr *instr,
4491 LLVMValueRef llvm_phi)
4492 {
4493 nir_foreach_phi_src(src, instr) {
4494 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4495 LLVMValueRef llvm_src = get_src(ctx, src->src);
4496
4497 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4498 }
4499 }
4500
4501 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4502 {
4503 struct hash_entry *entry;
4504 hash_table_foreach(ctx->phis, entry) {
4505 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4506 (LLVMValueRef)entry->data);
4507 }
4508 }
4509
4510
4511 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4512 nir_ssa_undef_instr *instr)
4513 {
4514 unsigned num_components = instr->def.num_components;
4515 LLVMValueRef undef;
4516
4517 if (num_components == 1)
4518 undef = LLVMGetUndef(ctx->i32);
4519 else {
4520 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4521 }
4522 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4523 }
4524
4525 static void visit_jump(struct nir_to_llvm_context *ctx,
4526 nir_jump_instr *instr)
4527 {
4528 switch (instr->type) {
4529 case nir_jump_break:
4530 LLVMBuildBr(ctx->builder, ctx->break_block);
4531 LLVMClearInsertionPosition(ctx->builder);
4532 break;
4533 case nir_jump_continue:
4534 LLVMBuildBr(ctx->builder, ctx->continue_block);
4535 LLVMClearInsertionPosition(ctx->builder);
4536 break;
4537 default:
4538 fprintf(stderr, "Unknown NIR jump instr: ");
4539 nir_print_instr(&instr->instr, stderr);
4540 fprintf(stderr, "\n");
4541 abort();
4542 }
4543 }
4544
4545 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4546 struct exec_list *list);
4547
4548 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4549 {
4550 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4551 nir_foreach_instr(instr, block)
4552 {
4553 switch (instr->type) {
4554 case nir_instr_type_alu:
4555 visit_alu(ctx, nir_instr_as_alu(instr));
4556 break;
4557 case nir_instr_type_load_const:
4558 visit_load_const(ctx, nir_instr_as_load_const(instr));
4559 break;
4560 case nir_instr_type_intrinsic:
4561 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4562 break;
4563 case nir_instr_type_tex:
4564 visit_tex(ctx, nir_instr_as_tex(instr));
4565 break;
4566 case nir_instr_type_phi:
4567 visit_phi(ctx, nir_instr_as_phi(instr));
4568 break;
4569 case nir_instr_type_ssa_undef:
4570 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4571 break;
4572 case nir_instr_type_jump:
4573 visit_jump(ctx, nir_instr_as_jump(instr));
4574 break;
4575 default:
4576 fprintf(stderr, "Unknown NIR instr type: ");
4577 nir_print_instr(instr, stderr);
4578 fprintf(stderr, "\n");
4579 abort();
4580 }
4581 }
4582
4583 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4584 }
4585
4586 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4587 {
4588 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4589
4590 LLVMBasicBlockRef merge_block =
4591 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4592 LLVMBasicBlockRef if_block =
4593 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4594 LLVMBasicBlockRef else_block = merge_block;
4595 if (!exec_list_is_empty(&if_stmt->else_list))
4596 else_block = LLVMAppendBasicBlockInContext(
4597 ctx->context, ctx->main_function, "");
4598
4599 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4600 LLVMConstInt(ctx->i32, 0, false), "");
4601 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4602
4603 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4604 visit_cf_list(ctx, &if_stmt->then_list);
4605 if (LLVMGetInsertBlock(ctx->builder))
4606 LLVMBuildBr(ctx->builder, merge_block);
4607
4608 if (!exec_list_is_empty(&if_stmt->else_list)) {
4609 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4610 visit_cf_list(ctx, &if_stmt->else_list);
4611 if (LLVMGetInsertBlock(ctx->builder))
4612 LLVMBuildBr(ctx->builder, merge_block);
4613 }
4614
4615 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4616 }
4617
4618 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4619 {
4620 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4621 LLVMBasicBlockRef break_parent = ctx->break_block;
4622
4623 ctx->continue_block =
4624 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4625 ctx->break_block =
4626 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4627
4628 LLVMBuildBr(ctx->builder, ctx->continue_block);
4629 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4630 visit_cf_list(ctx, &loop->body);
4631
4632 if (LLVMGetInsertBlock(ctx->builder))
4633 LLVMBuildBr(ctx->builder, ctx->continue_block);
4634 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4635
4636 ctx->continue_block = continue_parent;
4637 ctx->break_block = break_parent;
4638 }
4639
4640 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4641 struct exec_list *list)
4642 {
4643 foreach_list_typed(nir_cf_node, node, node, list)
4644 {
4645 switch (node->type) {
4646 case nir_cf_node_block:
4647 visit_block(ctx, nir_cf_node_as_block(node));
4648 break;
4649
4650 case nir_cf_node_if:
4651 visit_if(ctx, nir_cf_node_as_if(node));
4652 break;
4653
4654 case nir_cf_node_loop:
4655 visit_loop(ctx, nir_cf_node_as_loop(node));
4656 break;
4657
4658 default:
4659 assert(0);
4660 }
4661 }
4662 }
4663
4664 static void
4665 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4666 struct nir_variable *variable)
4667 {
4668 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4669 LLVMValueRef t_offset;
4670 LLVMValueRef t_list;
4671 LLVMValueRef input;
4672 LLVMValueRef buffer_index;
4673 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4674 int idx = variable->data.location;
4675 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4676
4677 variable->data.driver_location = idx * 4;
4678
4679 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4680 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4681 ctx->start_instance, "");
4682 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4683 ctx->shader_info->vs.vgpr_comp_cnt);
4684 } else
4685 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4686 ctx->base_vertex, "");
4687
4688 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4689 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4690
4691 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4692
4693 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4694 buffer_index,
4695 LLVMConstInt(ctx->i32, 0, false),
4696 true);
4697
4698 for (unsigned chan = 0; chan < 4; chan++) {
4699 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4700 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4701 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4702 input, llvm_chan, ""));
4703 }
4704 }
4705 }
4706
4707 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4708 unsigned attr,
4709 LLVMValueRef interp_param,
4710 LLVMValueRef prim_mask,
4711 LLVMValueRef result[4])
4712 {
4713 LLVMValueRef attr_number;
4714 unsigned chan;
4715 LLVMValueRef i, j;
4716 bool interp = interp_param != NULL;
4717
4718 attr_number = LLVMConstInt(ctx->i32, attr, false);
4719
4720 /* fs.constant returns the param from the middle vertex, so it's not
4721 * really useful for flat shading. It's meant to be used for custom
4722 * interpolation (but the intrinsic can't fetch from the other two
4723 * vertices).
4724 *
4725 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4726 * to do the right thing. The only reason we use fs.constant is that
4727 * fs.interp cannot be used on integers, because they can be equal
4728 * to NaN.
4729 */
4730 if (interp) {
4731 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4732 LLVMVectorType(ctx->f32, 2), "");
4733
4734 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4735 ctx->i32zero, "");
4736 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4737 ctx->i32one, "");
4738 }
4739
4740 for (chan = 0; chan < 4; chan++) {
4741 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4742
4743 if (interp) {
4744 result[chan] = ac_build_fs_interp(&ctx->ac,
4745 llvm_chan,
4746 attr_number,
4747 prim_mask, i, j);
4748 } else {
4749 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4750 LLVMConstInt(ctx->i32, 2, false),
4751 llvm_chan,
4752 attr_number,
4753 prim_mask);
4754 }
4755 }
4756 }
4757
4758 static void
4759 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4760 struct nir_variable *variable)
4761 {
4762 int idx = variable->data.location;
4763 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4764 LLVMValueRef interp;
4765
4766 variable->data.driver_location = idx * 4;
4767 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4768
4769 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4770 unsigned interp_type;
4771 if (variable->data.sample) {
4772 interp_type = INTERP_SAMPLE;
4773 ctx->shader_info->fs.force_persample = true;
4774 } else if (variable->data.centroid)
4775 interp_type = INTERP_CENTROID;
4776 else
4777 interp_type = INTERP_CENTER;
4778
4779 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4780 } else
4781 interp = NULL;
4782
4783 for (unsigned i = 0; i < attrib_count; ++i)
4784 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4785
4786 }
4787
4788 static void
4789 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4790 struct nir_variable *variable)
4791 {
4792 switch (ctx->stage) {
4793 case MESA_SHADER_VERTEX:
4794 handle_vs_input_decl(ctx, variable);
4795 break;
4796 case MESA_SHADER_FRAGMENT:
4797 handle_fs_input_decl(ctx, variable);
4798 break;
4799 default:
4800 break;
4801 }
4802
4803 }
4804
4805 static void
4806 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4807 struct nir_shader *nir)
4808 {
4809 unsigned index = 0;
4810 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4811 LLVMValueRef interp_param;
4812 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4813
4814 if (!(ctx->input_mask & (1ull << i)))
4815 continue;
4816
4817 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4818 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4819 interp_param = *inputs;
4820 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4821 inputs);
4822
4823 if (!interp_param)
4824 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4825 ++index;
4826 } else if (i == VARYING_SLOT_POS) {
4827 for(int i = 0; i < 3; ++i)
4828 inputs[i] = ctx->frag_pos[i];
4829
4830 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4831 }
4832 }
4833 ctx->shader_info->fs.num_interp = index;
4834 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4835 ctx->shader_info->fs.has_pcoord = true;
4836 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4837 ctx->shader_info->fs.prim_id_input = true;
4838 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4839 ctx->shader_info->fs.layer_input = true;
4840 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4841 }
4842
4843 static LLVMValueRef
4844 ac_build_alloca(struct nir_to_llvm_context *ctx,
4845 LLVMTypeRef type,
4846 const char *name)
4847 {
4848 LLVMBuilderRef builder = ctx->builder;
4849 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4850 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4851 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4852 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4853 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4854 LLVMValueRef res;
4855
4856 if (first_instr) {
4857 LLVMPositionBuilderBefore(first_builder, first_instr);
4858 } else {
4859 LLVMPositionBuilderAtEnd(first_builder, first_block);
4860 }
4861
4862 res = LLVMBuildAlloca(first_builder, type, name);
4863 LLVMBuildStore(builder, LLVMConstNull(type), res);
4864
4865 LLVMDisposeBuilder(first_builder);
4866
4867 return res;
4868 }
4869
4870 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4871 LLVMTypeRef type,
4872 const char *name)
4873 {
4874 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4875 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4876 return ptr;
4877 }
4878
4879 static void
4880 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4881 struct nir_variable *variable)
4882 {
4883 int idx = variable->data.location + variable->data.index;
4884 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4885 uint64_t mask_attribs;
4886 variable->data.driver_location = idx * 4;
4887
4888 /* tess ctrl has it's own load/store paths for outputs */
4889 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4890 return;
4891
4892 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4893 if (ctx->stage == MESA_SHADER_VERTEX ||
4894 ctx->stage == MESA_SHADER_TESS_EVAL ||
4895 ctx->stage == MESA_SHADER_GEOMETRY) {
4896 if (idx == VARYING_SLOT_CLIP_DIST0) {
4897 int length = ctx->num_output_clips + ctx->num_output_culls;
4898 if (ctx->stage == MESA_SHADER_VERTEX) {
4899 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4900 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4901 }
4902 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4903 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4904 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4905 }
4906
4907 if (length > 4)
4908 attrib_count = 2;
4909 else
4910 attrib_count = 1;
4911 mask_attribs = 1ull << idx;
4912 }
4913 }
4914
4915 for (unsigned i = 0; i < attrib_count; ++i) {
4916 for (unsigned chan = 0; chan < 4; chan++) {
4917 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4918 si_build_alloca_undef(ctx, ctx->f32, "");
4919 }
4920 }
4921 ctx->output_mask |= mask_attribs;
4922 }
4923
4924 static void
4925 setup_locals(struct nir_to_llvm_context *ctx,
4926 struct nir_function *func)
4927 {
4928 int i, j;
4929 ctx->num_locals = 0;
4930 nir_foreach_variable(variable, &func->impl->locals) {
4931 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4932 variable->data.driver_location = ctx->num_locals * 4;
4933 ctx->num_locals += attrib_count;
4934 }
4935 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4936 if (!ctx->locals)
4937 return;
4938
4939 for (i = 0; i < ctx->num_locals; i++) {
4940 for (j = 0; j < 4; j++) {
4941 ctx->locals[i * 4 + j] =
4942 si_build_alloca_undef(ctx, ctx->f32, "temp");
4943 }
4944 }
4945 }
4946
4947 static LLVMValueRef
4948 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4949 {
4950 v = to_float(ctx, v);
4951 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4952 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4953 }
4954
4955
4956 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4957 LLVMValueRef src0, LLVMValueRef src1)
4958 {
4959 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4960 LLVMValueRef comp[2];
4961
4962 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4963 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4964 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4965 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4966 }
4967
4968 /* Initialize arguments for the shader export intrinsic */
4969 static void
4970 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4971 LLVMValueRef *values,
4972 unsigned target,
4973 struct ac_export_args *args)
4974 {
4975 /* Default is 0xf. Adjusted below depending on the format. */
4976 args->enabled_channels = 0xf;
4977
4978 /* Specify whether the EXEC mask represents the valid mask */
4979 args->valid_mask = 0;
4980
4981 /* Specify whether this is the last export */
4982 args->done = 0;
4983
4984 /* Specify the target we are exporting */
4985 args->target = target;
4986
4987 args->compr = false;
4988 args->out[0] = LLVMGetUndef(ctx->f32);
4989 args->out[1] = LLVMGetUndef(ctx->f32);
4990 args->out[2] = LLVMGetUndef(ctx->f32);
4991 args->out[3] = LLVMGetUndef(ctx->f32);
4992
4993 if (!values)
4994 return;
4995
4996 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4997 LLVMValueRef val[4];
4998 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4999 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5000 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5001
5002 switch(col_format) {
5003 case V_028714_SPI_SHADER_ZERO:
5004 args->enabled_channels = 0; /* writemask */
5005 args->target = V_008DFC_SQ_EXP_NULL;
5006 break;
5007
5008 case V_028714_SPI_SHADER_32_R:
5009 args->enabled_channels = 1;
5010 args->out[0] = values[0];
5011 break;
5012
5013 case V_028714_SPI_SHADER_32_GR:
5014 args->enabled_channels = 0x3;
5015 args->out[0] = values[0];
5016 args->out[1] = values[1];
5017 break;
5018
5019 case V_028714_SPI_SHADER_32_AR:
5020 args->enabled_channels = 0x9;
5021 args->out[0] = values[0];
5022 args->out[3] = values[3];
5023 break;
5024
5025 case V_028714_SPI_SHADER_FP16_ABGR:
5026 args->compr = 1;
5027
5028 for (unsigned chan = 0; chan < 2; chan++) {
5029 LLVMValueRef pack_args[2] = {
5030 values[2 * chan],
5031 values[2 * chan + 1]
5032 };
5033 LLVMValueRef packed;
5034
5035 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5036 args->out[chan] = packed;
5037 }
5038 break;
5039
5040 case V_028714_SPI_SHADER_UNORM16_ABGR:
5041 for (unsigned chan = 0; chan < 4; chan++) {
5042 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5043 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5044 LLVMConstReal(ctx->f32, 65535), "");
5045 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5046 LLVMConstReal(ctx->f32, 0.5), "");
5047 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5048 ctx->i32, "");
5049 }
5050
5051 args->compr = 1;
5052 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5053 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5054 break;
5055
5056 case V_028714_SPI_SHADER_SNORM16_ABGR:
5057 for (unsigned chan = 0; chan < 4; chan++) {
5058 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
5059 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5060 LLVMConstReal(ctx->f32, 32767), "");
5061
5062 /* If positive, add 0.5, else add -0.5. */
5063 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5064 LLVMBuildSelect(ctx->builder,
5065 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5066 val[chan], ctx->f32zero, ""),
5067 LLVMConstReal(ctx->f32, 0.5),
5068 LLVMConstReal(ctx->f32, -0.5), ""), "");
5069 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5070 }
5071
5072 args->compr = 1;
5073 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5074 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5075 break;
5076
5077 case V_028714_SPI_SHADER_UINT16_ABGR: {
5078 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5079
5080 for (unsigned chan = 0; chan < 4; chan++) {
5081 val[chan] = to_integer(ctx, values[chan]);
5082 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
5083 }
5084
5085 args->compr = 1;
5086 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5087 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5088 break;
5089 }
5090
5091 case V_028714_SPI_SHADER_SINT16_ABGR: {
5092 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5093 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5094
5095 /* Clamp. */
5096 for (unsigned chan = 0; chan < 4; chan++) {
5097 val[chan] = to_integer(ctx, values[chan]);
5098 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
5099 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
5100 }
5101
5102 args->compr = 1;
5103 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5104 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5105 break;
5106 }
5107
5108 default:
5109 case V_028714_SPI_SHADER_32_ABGR:
5110 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5111 break;
5112 }
5113 } else
5114 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5115
5116 for (unsigned i = 0; i < 4; ++i)
5117 args->out[i] = to_float(ctx, args->out[i]);
5118 }
5119
5120 static void
5121 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5122 struct ac_vs_output_info *outinfo)
5123 {
5124 uint32_t param_count = 0;
5125 unsigned target;
5126 unsigned pos_idx, num_pos_exports = 0;
5127 struct ac_export_args args, pos_args[4] = {};
5128 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5129 int i;
5130
5131 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5132 sizeof(outinfo->vs_output_param_offset));
5133
5134 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5135 LLVMValueRef slots[8];
5136 unsigned j;
5137
5138 if (outinfo->cull_dist_mask)
5139 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5140
5141 i = VARYING_SLOT_CLIP_DIST0;
5142 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5143 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5144 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5145
5146 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5147 slots[i] = LLVMGetUndef(ctx->f32);
5148
5149 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5150 target = V_008DFC_SQ_EXP_POS + 3;
5151 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5152 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5153 &args, sizeof(args));
5154 }
5155
5156 target = V_008DFC_SQ_EXP_POS + 2;
5157 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5158 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5159 &args, sizeof(args));
5160
5161 }
5162
5163 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5164 LLVMValueRef values[4];
5165 if (!(ctx->output_mask & (1ull << i)))
5166 continue;
5167
5168 for (unsigned j = 0; j < 4; j++)
5169 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5170 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5171
5172 if (i == VARYING_SLOT_POS) {
5173 target = V_008DFC_SQ_EXP_POS;
5174 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5175 continue;
5176 } else if (i == VARYING_SLOT_PSIZ) {
5177 outinfo->writes_pointsize = true;
5178 psize_value = values[0];
5179 continue;
5180 } else if (i == VARYING_SLOT_LAYER) {
5181 outinfo->writes_layer = true;
5182 layer_value = values[0];
5183 target = V_008DFC_SQ_EXP_PARAM + param_count;
5184 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5185 param_count++;
5186 } else if (i == VARYING_SLOT_VIEWPORT) {
5187 outinfo->writes_viewport_index = true;
5188 viewport_index_value = values[0];
5189 continue;
5190 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5191 target = V_008DFC_SQ_EXP_PARAM + param_count;
5192 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5193 param_count++;
5194 } else if (i >= VARYING_SLOT_VAR0) {
5195 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5196 target = V_008DFC_SQ_EXP_PARAM + param_count;
5197 outinfo->vs_output_param_offset[i] = param_count;
5198 param_count++;
5199 }
5200
5201 si_llvm_init_export_args(ctx, values, target, &args);
5202
5203 if (target >= V_008DFC_SQ_EXP_POS &&
5204 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5205 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5206 &args, sizeof(args));
5207 } else {
5208 ac_build_export(&ctx->ac, &args);
5209 }
5210 }
5211
5212 /* We need to add the position output manually if it's missing. */
5213 if (!pos_args[0].out[0]) {
5214 pos_args[0].enabled_channels = 0xf;
5215 pos_args[0].valid_mask = 0;
5216 pos_args[0].done = 0;
5217 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5218 pos_args[0].compr = 0;
5219 pos_args[0].out[0] = ctx->f32zero; /* X */
5220 pos_args[0].out[1] = ctx->f32zero; /* Y */
5221 pos_args[0].out[2] = ctx->f32zero; /* Z */
5222 pos_args[0].out[3] = ctx->f32one; /* W */
5223 }
5224
5225 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5226 (outinfo->writes_layer == true ? 4 : 0) |
5227 (outinfo->writes_viewport_index == true ? 8 : 0));
5228 if (mask) {
5229 pos_args[1].enabled_channels = mask;
5230 pos_args[1].valid_mask = 0;
5231 pos_args[1].done = 0;
5232 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5233 pos_args[1].compr = 0;
5234 pos_args[1].out[0] = ctx->f32zero; /* X */
5235 pos_args[1].out[1] = ctx->f32zero; /* Y */
5236 pos_args[1].out[2] = ctx->f32zero; /* Z */
5237 pos_args[1].out[3] = ctx->f32zero; /* W */
5238
5239 if (outinfo->writes_pointsize == true)
5240 pos_args[1].out[0] = psize_value;
5241 if (outinfo->writes_layer == true)
5242 pos_args[1].out[2] = layer_value;
5243 if (outinfo->writes_viewport_index == true)
5244 pos_args[1].out[3] = viewport_index_value;
5245 }
5246 for (i = 0; i < 4; i++) {
5247 if (pos_args[i].out[0])
5248 num_pos_exports++;
5249 }
5250
5251 pos_idx = 0;
5252 for (i = 0; i < 4; i++) {
5253 if (!pos_args[i].out[0])
5254 continue;
5255
5256 /* Specify the target we are exporting */
5257 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5258 if (pos_idx == num_pos_exports)
5259 pos_args[i].done = 1;
5260 ac_build_export(&ctx->ac, &pos_args[i]);
5261 }
5262
5263 outinfo->pos_exports = num_pos_exports;
5264 outinfo->param_exports = param_count;
5265 }
5266
5267 static void
5268 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5269 struct ac_es_output_info *outinfo)
5270 {
5271 int j;
5272 uint64_t max_output_written = 0;
5273 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5274 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5275 int param_index;
5276 int length = 4;
5277
5278 if (!(ctx->output_mask & (1ull << i)))
5279 continue;
5280
5281 if (i == VARYING_SLOT_CLIP_DIST0)
5282 length = ctx->num_output_clips + ctx->num_output_culls;
5283
5284 param_index = shader_io_get_unique_index(i);
5285
5286 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5287
5288 for (j = 0; j < length; j++) {
5289 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5290 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5291
5292 ac_build_buffer_store_dword(&ctx->ac,
5293 ctx->esgs_ring,
5294 out_val, 1,
5295 NULL, ctx->es2gs_offset,
5296 (4 * param_index + j) * 4,
5297 1, 1, true, true);
5298 }
5299 }
5300 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5301 }
5302
5303 static void
5304 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5305 {
5306 LLVMValueRef vertex_id = ctx->rel_auto_id;
5307 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5308 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5309 vertex_dw_stride, "");
5310
5311 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5312 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5313 int length = 4;
5314
5315 if (!(ctx->output_mask & (1ull << i)))
5316 continue;
5317
5318 if (i == VARYING_SLOT_CLIP_DIST0)
5319 length = ctx->num_output_clips + ctx->num_output_culls;
5320 int param = shader_io_get_unique_index(i);
5321 mark_tess_output(ctx, false, param);
5322 if (length > 4)
5323 mark_tess_output(ctx, false, param + 1);
5324 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5325 LLVMConstInt(ctx->i32, param * 4, false),
5326 "");
5327 for (unsigned j = 0; j < length; j++) {
5328 lds_store(ctx, dw_addr,
5329 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5330 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5331 }
5332 }
5333 }
5334
5335 struct ac_build_if_state
5336 {
5337 struct nir_to_llvm_context *ctx;
5338 LLVMValueRef condition;
5339 LLVMBasicBlockRef entry_block;
5340 LLVMBasicBlockRef true_block;
5341 LLVMBasicBlockRef false_block;
5342 LLVMBasicBlockRef merge_block;
5343 };
5344
5345 static LLVMBasicBlockRef
5346 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5347 {
5348 LLVMBasicBlockRef current_block;
5349 LLVMBasicBlockRef next_block;
5350 LLVMBasicBlockRef new_block;
5351
5352 /* get current basic block */
5353 current_block = LLVMGetInsertBlock(ctx->builder);
5354
5355 /* chqeck if there's another block after this one */
5356 next_block = LLVMGetNextBasicBlock(current_block);
5357 if (next_block) {
5358 /* insert the new block before the next block */
5359 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5360 }
5361 else {
5362 /* append new block after current block */
5363 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5364 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5365 }
5366 return new_block;
5367 }
5368
5369 static void
5370 ac_nir_build_if(struct ac_build_if_state *ifthen,
5371 struct nir_to_llvm_context *ctx,
5372 LLVMValueRef condition)
5373 {
5374 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5375
5376 memset(ifthen, 0, sizeof *ifthen);
5377 ifthen->ctx = ctx;
5378 ifthen->condition = condition;
5379 ifthen->entry_block = block;
5380
5381 /* create endif/merge basic block for the phi functions */
5382 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5383
5384 /* create/insert true_block before merge_block */
5385 ifthen->true_block =
5386 LLVMInsertBasicBlockInContext(ctx->context,
5387 ifthen->merge_block,
5388 "if-true-block");
5389
5390 /* successive code goes into the true block */
5391 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5392 }
5393
5394 /**
5395 * End a conditional.
5396 */
5397 static void
5398 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5399 {
5400 LLVMBuilderRef builder = ifthen->ctx->builder;
5401
5402 /* Insert branch to the merge block from current block */
5403 LLVMBuildBr(builder, ifthen->merge_block);
5404
5405 /*
5406 * Now patch in the various branch instructions.
5407 */
5408
5409 /* Insert the conditional branch instruction at the end of entry_block */
5410 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5411 if (ifthen->false_block) {
5412 /* we have an else clause */
5413 LLVMBuildCondBr(builder, ifthen->condition,
5414 ifthen->true_block, ifthen->false_block);
5415 }
5416 else {
5417 /* no else clause */
5418 LLVMBuildCondBr(builder, ifthen->condition,
5419 ifthen->true_block, ifthen->merge_block);
5420 }
5421
5422 /* Resume building code at end of the ifthen->merge_block */
5423 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5424 }
5425
5426 static void
5427 write_tess_factors(struct nir_to_llvm_context *ctx)
5428 {
5429 unsigned stride, outer_comps, inner_comps;
5430 struct ac_build_if_state if_ctx, inner_if_ctx;
5431 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5432 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5433 unsigned tess_inner_index, tess_outer_index;
5434 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5435 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5436 int i;
5437 emit_barrier(ctx);
5438
5439 switch (ctx->options->key.tcs.primitive_mode) {
5440 case GL_ISOLINES:
5441 stride = 2;
5442 outer_comps = 2;
5443 inner_comps = 0;
5444 break;
5445 case GL_TRIANGLES:
5446 stride = 4;
5447 outer_comps = 3;
5448 inner_comps = 1;
5449 break;
5450 case GL_QUADS:
5451 stride = 6;
5452 outer_comps = 4;
5453 inner_comps = 2;
5454 break;
5455 default:
5456 return;
5457 }
5458
5459 ac_nir_build_if(&if_ctx, ctx,
5460 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5461 invocation_id, ctx->i32zero, ""));
5462
5463 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5464 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5465
5466 mark_tess_output(ctx, true, tess_inner_index);
5467 mark_tess_output(ctx, true, tess_outer_index);
5468 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5469 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5470 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5471 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5472 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5473
5474 for (i = 0; i < 4; i++) {
5475 inner[i] = LLVMGetUndef(ctx->i32);
5476 outer[i] = LLVMGetUndef(ctx->i32);
5477 }
5478
5479 // LINES reverseal
5480 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5481 outer[0] = out[1] = lds_load(ctx, lds_outer);
5482 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5483 LLVMConstInt(ctx->i32, 1, false), "");
5484 outer[1] = out[0] = lds_load(ctx, lds_outer);
5485 } else {
5486 for (i = 0; i < outer_comps; i++) {
5487 outer[i] = out[i] =
5488 lds_load(ctx, lds_outer);
5489 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5490 LLVMConstInt(ctx->i32, 1, false), "");
5491 }
5492 for (i = 0; i < inner_comps; i++) {
5493 inner[i] = out[outer_comps+i] =
5494 lds_load(ctx, lds_inner);
5495 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5496 LLVMConstInt(ctx->i32, 1, false), "");
5497 }
5498 }
5499
5500 /* Convert the outputs to vectors for stores. */
5501 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5502 vec1 = NULL;
5503
5504 if (stride > 4)
5505 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5506
5507
5508 buffer = ctx->hs_ring_tess_factor;
5509 tf_base = ctx->tess_factor_offset;
5510 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5511 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5512
5513 ac_nir_build_if(&inner_if_ctx, ctx,
5514 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5515 rel_patch_id, ctx->i32zero, ""));
5516
5517 /* Store the dynamic HS control word. */
5518 ac_build_buffer_store_dword(&ctx->ac, buffer,
5519 LLVMConstInt(ctx->i32, 0x80000000, false),
5520 1, ctx->i32zero, tf_base,
5521 0, 1, 0, true, false);
5522 ac_nir_build_endif(&inner_if_ctx);
5523
5524 /* Store the tessellation factors. */
5525 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5526 MIN2(stride, 4), byteoffset, tf_base,
5527 4, 1, 0, true, false);
5528 if (vec1)
5529 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5530 stride - 4, byteoffset, tf_base,
5531 20, 1, 0, true, false);
5532
5533 //TODO store to offchip for TES to read - only if TES reads them
5534 if (1) {
5535 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5536 LLVMValueRef tf_inner_offset;
5537 unsigned param_outer, param_inner;
5538
5539 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5540 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5541 LLVMConstInt(ctx->i32, param_outer, 0));
5542
5543 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5544 util_next_power_of_two(outer_comps));
5545
5546 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5547 outer_comps, tf_outer_offset,
5548 ctx->oc_lds, 0, 1, 0, true, false);
5549 if (inner_comps) {
5550 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5551 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5552 LLVMConstInt(ctx->i32, param_inner, 0));
5553
5554 inner_vec = inner_comps == 1 ? inner[0] :
5555 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5556 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5557 inner_comps, tf_inner_offset,
5558 ctx->oc_lds, 0, 1, 0, true, false);
5559 }
5560 }
5561 ac_nir_build_endif(&if_ctx);
5562 }
5563
5564 static void
5565 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5566 {
5567 write_tess_factors(ctx);
5568 }
5569
5570 static bool
5571 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5572 LLVMValueRef *color, unsigned param, bool is_last,
5573 struct ac_export_args *args)
5574 {
5575 /* Export */
5576 si_llvm_init_export_args(ctx, color, param,
5577 args);
5578
5579 if (is_last) {
5580 args->valid_mask = 1; /* whether the EXEC mask is valid */
5581 args->done = 1; /* DONE bit */
5582 } else if (!args->enabled_channels)
5583 return false; /* unnecessary NULL export */
5584
5585 return true;
5586 }
5587
5588 static void
5589 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5590 LLVMValueRef depth, LLVMValueRef stencil,
5591 LLVMValueRef samplemask)
5592 {
5593 struct ac_export_args args;
5594
5595 args.enabled_channels = 0;
5596 args.valid_mask = 1;
5597 args.done = 1;
5598 args.target = V_008DFC_SQ_EXP_MRTZ;
5599 args.compr = false;
5600
5601 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5602 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5603 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5604 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5605
5606 if (depth) {
5607 args.out[0] = depth;
5608 args.enabled_channels |= 0x1;
5609 }
5610
5611 if (stencil) {
5612 args.out[1] = stencil;
5613 args.enabled_channels |= 0x2;
5614 }
5615
5616 if (samplemask) {
5617 args.out[2] = samplemask;
5618 args.enabled_channels |= 0x4;
5619 }
5620
5621 /* SI (except OLAND) has a bug that it only looks
5622 * at the X writemask component. */
5623 if (ctx->options->chip_class == SI &&
5624 ctx->options->family != CHIP_OLAND)
5625 args.enabled_channels |= 0x1;
5626
5627 ac_build_export(&ctx->ac, &args);
5628 }
5629
5630 static void
5631 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5632 {
5633 unsigned index = 0;
5634 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5635 struct ac_export_args color_args[8];
5636
5637 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5638 LLVMValueRef values[4];
5639
5640 if (!(ctx->output_mask & (1ull << i)))
5641 continue;
5642
5643 if (i == FRAG_RESULT_DEPTH) {
5644 ctx->shader_info->fs.writes_z = true;
5645 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
5646 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5647 } else if (i == FRAG_RESULT_STENCIL) {
5648 ctx->shader_info->fs.writes_stencil = true;
5649 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
5650 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5651 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5652 ctx->shader_info->fs.writes_sample_mask = true;
5653 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
5654 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5655 } else {
5656 bool last = false;
5657 for (unsigned j = 0; j < 4; j++)
5658 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5659 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5660
5661 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5662 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5663
5664 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5665 if (ret)
5666 index++;
5667 }
5668 }
5669
5670 for (unsigned i = 0; i < index; i++)
5671 ac_build_export(&ctx->ac, &color_args[i]);
5672 if (depth || stencil || samplemask)
5673 si_export_mrt_z(ctx, depth, stencil, samplemask);
5674 else if (!index) {
5675 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5676 ac_build_export(&ctx->ac, &color_args[0]);
5677 }
5678
5679 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5680 }
5681
5682 static void
5683 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5684 {
5685 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5686 }
5687
5688 static void
5689 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5690 {
5691 switch (ctx->stage) {
5692 case MESA_SHADER_VERTEX:
5693 if (ctx->options->key.vs.as_ls)
5694 handle_ls_outputs_post(ctx);
5695 else if (ctx->options->key.vs.as_es)
5696 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5697 else
5698 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5699 break;
5700 case MESA_SHADER_FRAGMENT:
5701 handle_fs_outputs_post(ctx);
5702 break;
5703 case MESA_SHADER_GEOMETRY:
5704 emit_gs_epilogue(ctx);
5705 break;
5706 case MESA_SHADER_TESS_CTRL:
5707 handle_tcs_outputs_post(ctx);
5708 break;
5709 case MESA_SHADER_TESS_EVAL:
5710 if (ctx->options->key.tes.as_es)
5711 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5712 else
5713 handle_vs_outputs_post(ctx, &ctx->shader_info->tes.outinfo);
5714 break;
5715 default:
5716 break;
5717 }
5718 }
5719
5720 static void
5721 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5722 struct nir_variable *variable, uint32_t *offset, int idx)
5723 {
5724 unsigned size = glsl_count_attribute_slots(variable->type, false);
5725 variable->data.driver_location = *offset;
5726 *offset += size;
5727 }
5728
5729 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5730 {
5731 LLVMPassManagerRef passmgr;
5732 /* Create the pass manager */
5733 passmgr = LLVMCreateFunctionPassManagerForModule(
5734 ctx->module);
5735
5736 /* This pass should eliminate all the load and store instructions */
5737 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5738
5739 /* Add some optimization passes */
5740 LLVMAddScalarReplAggregatesPass(passmgr);
5741 LLVMAddLICMPass(passmgr);
5742 LLVMAddAggressiveDCEPass(passmgr);
5743 LLVMAddCFGSimplificationPass(passmgr);
5744 LLVMAddInstructionCombiningPass(passmgr);
5745
5746 /* Run the pass */
5747 LLVMInitializeFunctionPassManager(passmgr);
5748 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5749 LLVMFinalizeFunctionPassManager(passmgr);
5750
5751 LLVMDisposeBuilder(ctx->builder);
5752 LLVMDisposePassManager(passmgr);
5753 }
5754
5755 static void
5756 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
5757 {
5758 struct ac_vs_output_info *outinfo;
5759
5760 if (ctx->stage == MESA_SHADER_FRAGMENT ||
5761 ctx->stage == MESA_SHADER_COMPUTE ||
5762 ctx->stage == MESA_SHADER_TESS_CTRL ||
5763 ctx->stage == MESA_SHADER_GEOMETRY)
5764 return;
5765
5766 if (ctx->stage == MESA_SHADER_VERTEX) {
5767 if (ctx->options->key.vs.as_ls ||
5768 ctx->options->key.vs.as_es)
5769 return;
5770 outinfo = &ctx->shader_info->vs.outinfo;
5771 }
5772
5773 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5774 if (ctx->options->key.vs.as_es)
5775 return;
5776 outinfo = &ctx->shader_info->tes.outinfo;
5777 }
5778
5779 ac_optimize_vs_outputs(&ctx->ac,
5780 ctx->main_function,
5781 outinfo->vs_output_param_offset,
5782 VARYING_SLOT_MAX,
5783 &outinfo->param_exports);
5784 }
5785
5786 static void
5787 ac_setup_rings(struct nir_to_llvm_context *ctx)
5788 {
5789 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5790 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5791 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5792 }
5793
5794 if (ctx->is_gs_copy_shader) {
5795 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5796 }
5797 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5798 LLVMValueRef tmp;
5799 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5800 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5801
5802 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5803
5804 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5805 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5806 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5807 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5808
5809 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5810 }
5811
5812 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5813 ctx->stage == MESA_SHADER_TESS_EVAL) {
5814 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5815 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5816 }
5817 }
5818
5819 static unsigned
5820 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
5821 struct nir_shader *nir)
5822 {
5823 switch (nir->stage) {
5824 case MESA_SHADER_TESS_CTRL:
5825 return chip_class >= CIK ? 128 : 64;
5826 case MESA_SHADER_GEOMETRY:
5827 return 64;
5828 case MESA_SHADER_COMPUTE:
5829 break;
5830 default:
5831 return 0;
5832 }
5833
5834 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
5835 nir->info.cs.local_size[1] *
5836 nir->info.cs.local_size[2];
5837 return max_workgroup_size;
5838 }
5839
5840 static
5841 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5842 struct nir_shader *nir,
5843 struct ac_shader_variant_info *shader_info,
5844 const struct ac_nir_compiler_options *options)
5845 {
5846 struct nir_to_llvm_context ctx = {0};
5847 struct nir_function *func;
5848 unsigned i;
5849 ctx.options = options;
5850 ctx.shader_info = shader_info;
5851 ctx.context = LLVMContextCreate();
5852 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5853
5854 ac_llvm_context_init(&ctx.ac, ctx.context);
5855 ctx.ac.module = ctx.module;
5856
5857 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5858
5859 memset(shader_info, 0, sizeof(*shader_info));
5860
5861 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5862
5863 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5864
5865 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5866 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5867 LLVMSetDataLayout(ctx.module, data_layout_str);
5868 LLVMDisposeTargetData(data_layout);
5869 LLVMDisposeMessage(data_layout_str);
5870
5871 setup_types(&ctx);
5872
5873 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5874 ctx.ac.builder = ctx.builder;
5875 ctx.stage = nir->stage;
5876 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
5877
5878 for (i = 0; i < AC_UD_MAX_SETS; i++)
5879 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5880 for (i = 0; i < AC_UD_MAX_UD; i++)
5881 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5882
5883 create_function(&ctx);
5884
5885 if (nir->stage == MESA_SHADER_COMPUTE) {
5886 int num_shared = 0;
5887 nir_foreach_variable(variable, &nir->shared)
5888 num_shared++;
5889 if (num_shared) {
5890 int idx = 0;
5891 uint32_t shared_size = 0;
5892 LLVMValueRef var;
5893 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5894 nir_foreach_variable(variable, &nir->shared) {
5895 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5896 idx++;
5897 }
5898
5899 shared_size *= 16;
5900 var = LLVMAddGlobalInAddressSpace(ctx.module,
5901 LLVMArrayType(ctx.i8, shared_size),
5902 "compute_lds",
5903 LOCAL_ADDR_SPACE);
5904 LLVMSetAlignment(var, 4);
5905 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5906 }
5907 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5908 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5909
5910 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
5911 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5912 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
5913 }
5914
5915 ac_setup_rings(&ctx);
5916
5917 nir_foreach_variable(variable, &nir->inputs)
5918 handle_shader_input_decl(&ctx, variable);
5919
5920 if (nir->stage == MESA_SHADER_FRAGMENT)
5921 handle_fs_inputs_pre(&ctx, nir);
5922
5923 ctx.num_output_clips = nir->info.clip_distance_array_size;
5924 ctx.num_output_culls = nir->info.cull_distance_array_size;
5925
5926 nir_foreach_variable(variable, &nir->outputs)
5927 handle_shader_output_decl(&ctx, variable);
5928
5929 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5930 _mesa_key_pointer_equal);
5931 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5932 _mesa_key_pointer_equal);
5933
5934 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5935
5936 setup_locals(&ctx, func);
5937
5938 visit_cf_list(&ctx, &func->impl->body);
5939 phi_post_pass(&ctx);
5940
5941 handle_shader_outputs_post(&ctx);
5942 LLVMBuildRetVoid(ctx.builder);
5943
5944 ac_llvm_finalize_module(&ctx);
5945
5946 ac_nir_eliminate_const_vs_outputs(&ctx);
5947 free(ctx.locals);
5948 ralloc_free(ctx.defs);
5949 ralloc_free(ctx.phis);
5950
5951 if (nir->stage == MESA_SHADER_GEOMETRY) {
5952 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
5953 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
5954 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5955 nir->info.gs.vertices_out;
5956 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
5957 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
5958 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
5959 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
5960 shader_info->vs.outputs_written = ctx.tess_outputs_written;
5961 }
5962
5963 return ctx.module;
5964 }
5965
5966 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
5967 {
5968 unsigned *retval = (unsigned *)context;
5969 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5970 char *description = LLVMGetDiagInfoDescription(di);
5971
5972 if (severity == LLVMDSError) {
5973 *retval = 1;
5974 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5975 description);
5976 }
5977
5978 LLVMDisposeMessage(description);
5979 }
5980
5981 static unsigned ac_llvm_compile(LLVMModuleRef M,
5982 struct ac_shader_binary *binary,
5983 LLVMTargetMachineRef tm)
5984 {
5985 unsigned retval = 0;
5986 char *err;
5987 LLVMContextRef llvm_ctx;
5988 LLVMMemoryBufferRef out_buffer;
5989 unsigned buffer_size;
5990 const char *buffer_data;
5991 LLVMBool mem_err;
5992
5993 /* Setup Diagnostic Handler*/
5994 llvm_ctx = LLVMGetModuleContext(M);
5995
5996 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5997 &retval);
5998
5999 /* Compile IR*/
6000 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6001 &err, &out_buffer);
6002
6003 /* Process Errors/Warnings */
6004 if (mem_err) {
6005 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6006 free(err);
6007 retval = 1;
6008 goto out;
6009 }
6010
6011 /* Extract Shader Code*/
6012 buffer_size = LLVMGetBufferSize(out_buffer);
6013 buffer_data = LLVMGetBufferStart(out_buffer);
6014
6015 ac_elf_read(buffer_data, buffer_size, binary);
6016
6017 /* Clean up */
6018 LLVMDisposeMemoryBuffer(out_buffer);
6019
6020 out:
6021 return retval;
6022 }
6023
6024 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6025 LLVMModuleRef llvm_module,
6026 struct ac_shader_binary *binary,
6027 struct ac_shader_config *config,
6028 struct ac_shader_variant_info *shader_info,
6029 gl_shader_stage stage,
6030 bool dump_shader, bool supports_spill)
6031 {
6032 if (dump_shader)
6033 ac_dump_module(llvm_module);
6034
6035 memset(binary, 0, sizeof(*binary));
6036 int v = ac_llvm_compile(llvm_module, binary, tm);
6037 if (v) {
6038 fprintf(stderr, "compile failed\n");
6039 }
6040
6041 if (dump_shader)
6042 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6043
6044 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6045
6046 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6047 LLVMDisposeModule(llvm_module);
6048 LLVMContextDispose(ctx);
6049
6050 if (stage == MESA_SHADER_FRAGMENT) {
6051 shader_info->num_input_vgprs = 0;
6052 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6053 shader_info->num_input_vgprs += 2;
6054 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6055 shader_info->num_input_vgprs += 2;
6056 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6057 shader_info->num_input_vgprs += 2;
6058 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6059 shader_info->num_input_vgprs += 3;
6060 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6061 shader_info->num_input_vgprs += 2;
6062 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6063 shader_info->num_input_vgprs += 2;
6064 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6065 shader_info->num_input_vgprs += 2;
6066 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6067 shader_info->num_input_vgprs += 1;
6068 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6069 shader_info->num_input_vgprs += 1;
6070 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6071 shader_info->num_input_vgprs += 1;
6072 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6073 shader_info->num_input_vgprs += 1;
6074 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6075 shader_info->num_input_vgprs += 1;
6076 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6077 shader_info->num_input_vgprs += 1;
6078 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6079 shader_info->num_input_vgprs += 1;
6080 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6081 shader_info->num_input_vgprs += 1;
6082 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6083 shader_info->num_input_vgprs += 1;
6084 }
6085 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6086
6087 /* +3 for scratch wave offset and VCC */
6088 config->num_sgprs = MAX2(config->num_sgprs,
6089 shader_info->num_input_sgprs + 3);
6090 }
6091
6092 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6093 struct ac_shader_binary *binary,
6094 struct ac_shader_config *config,
6095 struct ac_shader_variant_info *shader_info,
6096 struct nir_shader *nir,
6097 const struct ac_nir_compiler_options *options,
6098 bool dump_shader)
6099 {
6100
6101 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6102 options);
6103
6104 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6105 switch (nir->stage) {
6106 case MESA_SHADER_COMPUTE:
6107 for (int i = 0; i < 3; ++i)
6108 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6109 break;
6110 case MESA_SHADER_FRAGMENT:
6111 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6112 break;
6113 case MESA_SHADER_GEOMETRY:
6114 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6115 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6116 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6117 shader_info->gs.invocations = nir->info.gs.invocations;
6118 break;
6119 case MESA_SHADER_TESS_EVAL:
6120 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6121 shader_info->tes.spacing = nir->info.tess.spacing;
6122 shader_info->tes.ccw = nir->info.tess.ccw;
6123 shader_info->tes.point_mode = nir->info.tess.point_mode;
6124 shader_info->tes.as_es = options->key.tes.as_es;
6125 break;
6126 case MESA_SHADER_TESS_CTRL:
6127 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6128 break;
6129 case MESA_SHADER_VERTEX:
6130 shader_info->vs.as_es = options->key.vs.as_es;
6131 shader_info->vs.as_ls = options->key.vs.as_ls;
6132 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6133 if (options->key.vs.as_ls)
6134 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6135 break;
6136 default:
6137 break;
6138 }
6139 }
6140
6141 static void
6142 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6143 {
6144 LLVMValueRef args[9];
6145 args[0] = ctx->gsvs_ring;
6146 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6147 args[3] = ctx->i32zero;
6148 args[4] = ctx->i32one; /* OFFEN */
6149 args[5] = ctx->i32zero; /* IDXEN */
6150 args[6] = ctx->i32one; /* GLC */
6151 args[7] = ctx->i32one; /* SLC */
6152 args[8] = ctx->i32zero; /* TFE */
6153
6154 int idx = 0;
6155
6156 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6157 int length = 4;
6158 int slot = idx;
6159 int slot_inc = 1;
6160 if (!(ctx->output_mask & (1ull << i)))
6161 continue;
6162
6163 if (i == VARYING_SLOT_CLIP_DIST0) {
6164 /* unpack clip and cull from a single set of slots */
6165 length = ctx->num_output_clips + ctx->num_output_culls;
6166 if (length > 4)
6167 slot_inc = 2;
6168 }
6169
6170 for (unsigned j = 0; j < length; j++) {
6171 LLVMValueRef value;
6172 args[2] = LLVMConstInt(ctx->i32,
6173 (slot * 4 + j) *
6174 ctx->gs_max_out_vertices * 16 * 4, false);
6175
6176 value = ac_build_intrinsic(&ctx->ac,
6177 "llvm.SI.buffer.load.dword.i32.i32",
6178 ctx->i32, args, 9,
6179 AC_FUNC_ATTR_READONLY |
6180 AC_FUNC_ATTR_LEGACY);
6181
6182 LLVMBuildStore(ctx->builder,
6183 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6184 }
6185 idx += slot_inc;
6186 }
6187 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
6188 }
6189
6190 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6191 struct nir_shader *geom_shader,
6192 struct ac_shader_binary *binary,
6193 struct ac_shader_config *config,
6194 struct ac_shader_variant_info *shader_info,
6195 const struct ac_nir_compiler_options *options,
6196 bool dump_shader)
6197 {
6198 struct nir_to_llvm_context ctx = {0};
6199 ctx.context = LLVMContextCreate();
6200 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6201 ctx.options = options;
6202 ctx.shader_info = shader_info;
6203
6204 ac_llvm_context_init(&ctx.ac, ctx.context);
6205 ctx.ac.module = ctx.module;
6206
6207 ctx.is_gs_copy_shader = true;
6208 LLVMSetTarget(ctx.module, "amdgcn--");
6209 setup_types(&ctx);
6210
6211 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6212 ctx.ac.builder = ctx.builder;
6213 ctx.stage = MESA_SHADER_VERTEX;
6214
6215 create_function(&ctx);
6216
6217 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6218 ac_setup_rings(&ctx);
6219
6220 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6221 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6222
6223 nir_foreach_variable(variable, &geom_shader->outputs)
6224 handle_shader_output_decl(&ctx, variable);
6225
6226 ac_gs_copy_shader_emit(&ctx);
6227
6228 LLVMBuildRetVoid(ctx.builder);
6229
6230 ac_llvm_finalize_module(&ctx);
6231
6232 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6233 MESA_SHADER_VERTEX,
6234 dump_shader, options->supports_spill);
6235 }