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ac/nir: fix translation of nir_op_frcp for doubles
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 gl_shader_stage stage;
135
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137
138 uint64_t input_mask;
139 uint64_t output_mask;
140 uint8_t num_output_clips;
141 uint8_t num_output_culls;
142
143 bool is_gs_copy_shader;
144 LLVMValueRef gs_next_vertex;
145 unsigned gs_max_out_vertices;
146
147 unsigned tes_primitive_mode;
148 uint64_t tess_outputs_written;
149 uint64_t tess_patch_outputs_written;
150
151 uint32_t tcs_patch_outputs_read;
152 uint64_t tcs_outputs_read;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMTypeRef
163 nir2llvmtype(struct ac_nir_context *ctx,
164 const struct glsl_type *type)
165 {
166 switch (glsl_get_base_type(glsl_without_array(type))) {
167 case GLSL_TYPE_UINT:
168 case GLSL_TYPE_INT:
169 return ctx->ac.i32;
170 case GLSL_TYPE_UINT64:
171 case GLSL_TYPE_INT64:
172 return ctx->ac.i64;
173 case GLSL_TYPE_DOUBLE:
174 return ctx->ac.f64;
175 case GLSL_TYPE_FLOAT:
176 return ctx->ac.f32;
177 default:
178 assert(!"Unsupported type in nir2llvmtype()");
179 break;
180 }
181 return 0;
182 }
183
184 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
185 const nir_deref_var *deref,
186 enum ac_descriptor_type desc_type,
187 const nir_tex_instr *instr,
188 bool image, bool write);
189
190 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
191 {
192 return (index * 4) + chan;
193 }
194
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
196 {
197 /* handle patch indices separate */
198 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
199 return 0;
200 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
201 return 1;
202 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
203 return 2 + (slot - VARYING_SLOT_PATCH0);
204
205 if (slot == VARYING_SLOT_POS)
206 return 0;
207 if (slot == VARYING_SLOT_PSIZ)
208 return 1;
209 if (slot == VARYING_SLOT_CLIP_DIST0)
210 return 2;
211 /* 3 is reserved for clip dist as well */
212 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
213 return 4 + (slot - VARYING_SLOT_VAR0);
214 unreachable("illegal slot in get unique index\n");
215 }
216
217 static void set_llvm_calling_convention(LLVMValueRef func,
218 gl_shader_stage stage)
219 {
220 enum radeon_llvm_calling_convention calling_conv;
221
222 switch (stage) {
223 case MESA_SHADER_VERTEX:
224 case MESA_SHADER_TESS_EVAL:
225 calling_conv = RADEON_LLVM_AMDGPU_VS;
226 break;
227 case MESA_SHADER_GEOMETRY:
228 calling_conv = RADEON_LLVM_AMDGPU_GS;
229 break;
230 case MESA_SHADER_TESS_CTRL:
231 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t sgpr_count;
253 uint8_t num_sgprs_used;
254 uint8_t num_vgprs_used;
255 };
256
257 enum ac_arg_regfile {
258 ARG_SGPR,
259 ARG_VGPR,
260 };
261
262 static void
263 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
264 LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271
272 if (regfile == ARG_SGPR) {
273 info->num_sgprs_used += ac_get_type_size(type) / 4;
274 info->sgpr_count++;
275 } else {
276 assert(regfile == ARG_VGPR);
277 info->num_vgprs_used += ac_get_type_size(type) / 4;
278 }
279 }
280
281 static inline void
282 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 info->array_params_mask |= (1 << info->count);
285 add_arg(info, ARG_SGPR, type, param_ptr);
286 }
287
288 static void assign_arguments(LLVMValueRef main_function,
289 struct arg_info *info)
290 {
291 unsigned i;
292 for (i = 0; i < info->count; i++) {
293 if (info->assign[i])
294 *info->assign[i] = LLVMGetParam(main_function, i);
295 }
296 }
297
298 static LLVMValueRef
299 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
300 LLVMBuilderRef builder, LLVMTypeRef *return_types,
301 unsigned num_return_elems,
302 struct arg_info *args,
303 unsigned max_workgroup_size,
304 bool unsafe_math)
305 {
306 LLVMTypeRef main_function_type, ret_type;
307 LLVMBasicBlockRef main_function_body;
308
309 if (num_return_elems)
310 ret_type = LLVMStructTypeInContext(ctx, return_types,
311 num_return_elems, true);
312 else
313 ret_type = LLVMVoidTypeInContext(ctx);
314
315 /* Setup the function */
316 main_function_type =
317 LLVMFunctionType(ret_type, args->types, args->count, 0);
318 LLVMValueRef main_function =
319 LLVMAddFunction(module, "main", main_function_type);
320 main_function_body =
321 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
322 LLVMPositionBuilderAtEnd(builder, main_function_body);
323
324 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
325 for (unsigned i = 0; i < args->sgpr_count; ++i) {
326 if (args->array_params_mask & (1 << i)) {
327 LLVMValueRef P = LLVMGetParam(main_function, i);
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
329 ac_add_attr_dereferenceable(P, UINT64_MAX);
330 }
331 else {
332 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
333 }
334 }
335
336 if (max_workgroup_size) {
337 ac_llvm_add_target_dep_function_attr(main_function,
338 "amdgpu-max-work-group-size",
339 max_workgroup_size);
340 }
341 if (unsafe_math) {
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function,
344 "less-precise-fpmad",
345 "true");
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "no-infs-fp-math",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-nans-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "unsafe-fp-math",
354 "true");
355 }
356 return main_function;
357 }
358
359 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
360 {
361 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
362 CONST_ADDR_SPACE);
363 }
364
365 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
401 {
402 switch (ctx->stage) {
403 case MESA_SHADER_TESS_CTRL:
404 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
405 case MESA_SHADER_TESS_EVAL:
406 return ctx->tes_rel_patch_id;
407 break;
408 default:
409 unreachable("Illegal stage");
410 }
411 }
412
413 /* Tessellation shaders pass outputs to the next shader using LDS.
414 *
415 * LS outputs = TCS inputs
416 * TCS outputs = TES inputs
417 *
418 * The LDS layout is:
419 * - TCS inputs for patch 0
420 * - TCS inputs for patch 1
421 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
422 * - ...
423 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
424 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
425 * - TCS outputs for patch 1
426 * - Per-patch TCS outputs for patch 1
427 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
428 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
429 * - ...
430 *
431 * All three shaders VS(LS), TCS, TES share the same LDS space.
432 */
433 static LLVMValueRef
434 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
435 {
436 if (ctx->stage == MESA_SHADER_VERTEX)
437 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
438 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
439 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
440 else {
441 assert(0);
442 return NULL;
443 }
444 }
445
446 static LLVMValueRef
447 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
448 {
449 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
450 }
451
452 static LLVMValueRef
453 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
454 {
455 return LLVMBuildMul(ctx->builder,
456 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
457 LLVMConstInt(ctx->ac.i32, 4, false), "");
458 }
459
460 static LLVMValueRef
461 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
462 {
463 return LLVMBuildMul(ctx->builder,
464 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
465 LLVMConstInt(ctx->ac.i32, 4, false), "");
466 }
467
468 static LLVMValueRef
469 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
470 {
471 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
472 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
473
474 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
475 }
476
477 static LLVMValueRef
478 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
479 {
480 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
481 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
482 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
483
484 return LLVMBuildAdd(ctx->builder, patch0_offset,
485 LLVMBuildMul(ctx->builder, patch_stride,
486 rel_patch_id, ""),
487 "");
488 }
489
490 static LLVMValueRef
491 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch0_patch_data_offset =
494 get_tcs_out_patch0_patch_data_offset(ctx);
495 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
496 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
497
498 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
499 LLVMBuildMul(ctx->builder, patch_stride,
500 rel_patch_id, ""),
501 "");
502 }
503
504 static void
505 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
506 uint32_t indirect_offset)
507 {
508 ud_info->sgpr_idx = *sgpr_idx;
509 ud_info->num_sgprs = num_sgprs;
510 ud_info->indirect = indirect_offset > 0;
511 ud_info->indirect_offset = indirect_offset;
512 *sgpr_idx += num_sgprs;
513 }
514
515 static void
516 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
517 uint8_t num_sgprs)
518 {
519 struct ac_userdata_info *ud_info =
520 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
521 assert(ud_info);
522
523 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
524 }
525
526 static void
527 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
528 uint32_t indirect_offset)
529 {
530 struct ac_userdata_info *ud_info =
531 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
532 assert(ud_info);
533
534 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
535 }
536
537 struct user_sgpr_info {
538 bool need_ring_offsets;
539 uint8_t sgpr_count;
540 bool indirect_all_descriptor_sets;
541 };
542
543 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
544 gl_shader_stage stage,
545 struct user_sgpr_info *user_sgpr_info)
546 {
547 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
548
549 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
550 if (stage == MESA_SHADER_GEOMETRY ||
551 stage == MESA_SHADER_VERTEX ||
552 stage == MESA_SHADER_TESS_CTRL ||
553 stage == MESA_SHADER_TESS_EVAL ||
554 ctx->is_gs_copy_shader)
555 user_sgpr_info->need_ring_offsets = true;
556
557 if (stage == MESA_SHADER_FRAGMENT &&
558 ctx->shader_info->info.ps.needs_sample_positions)
559 user_sgpr_info->need_ring_offsets = true;
560
561 /* 2 user sgprs will nearly always be allocated for scratch/rings */
562 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
563 user_sgpr_info->sgpr_count += 2;
564 }
565
566 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
567 switch (stage) {
568 case MESA_SHADER_COMPUTE:
569 if (ctx->shader_info->info.cs.uses_grid_size)
570 user_sgpr_info->sgpr_count += 3;
571 break;
572 case MESA_SHADER_FRAGMENT:
573 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
574 break;
575 case MESA_SHADER_VERTEX:
576 if (!ctx->is_gs_copy_shader) {
577 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
578 if (ctx->shader_info->info.vs.needs_draw_id) {
579 user_sgpr_info->sgpr_count += 3;
580 } else {
581 user_sgpr_info->sgpr_count += 2;
582 }
583 }
584 if (ctx->options->key.vs.as_ls)
585 user_sgpr_info->sgpr_count++;
586 break;
587 case MESA_SHADER_TESS_CTRL:
588 user_sgpr_info->sgpr_count += 4;
589 break;
590 case MESA_SHADER_TESS_EVAL:
591 user_sgpr_info->sgpr_count += 1;
592 break;
593 case MESA_SHADER_GEOMETRY:
594 user_sgpr_info->sgpr_count += 2;
595 break;
596 default:
597 break;
598 }
599
600 if (ctx->shader_info->info.loads_push_constants)
601 user_sgpr_info->sgpr_count += 2;
602
603 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
604 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
605
606 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
607 user_sgpr_info->sgpr_count += 2;
608 user_sgpr_info->indirect_all_descriptor_sets = true;
609 } else {
610 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
611 }
612 }
613
614 static void
615 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
616 gl_shader_stage stage,
617 bool has_previous_stage,
618 gl_shader_stage previous_stage,
619 const struct user_sgpr_info *user_sgpr_info,
620 struct arg_info *args,
621 LLVMValueRef *desc_sets)
622 {
623 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
624 unsigned num_sets = ctx->options->layout ?
625 ctx->options->layout->num_sets : 0;
626 unsigned stage_mask = 1 << stage;
627
628 if (has_previous_stage)
629 stage_mask |= 1 << previous_stage;
630
631 /* 1 for each descriptor set */
632 if (!user_sgpr_info->indirect_all_descriptor_sets) {
633 for (unsigned i = 0; i < num_sets; ++i) {
634 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
635 add_array_arg(args, type,
636 &ctx->descriptor_sets[i]);
637 }
638 }
639 } else {
640 add_array_arg(args, const_array(type, 32), desc_sets);
641 }
642
643 if (ctx->shader_info->info.loads_push_constants) {
644 /* 1 for push constants and dynamic descriptors */
645 add_array_arg(args, type, &ctx->push_constants);
646 }
647 }
648
649 static void
650 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
651 gl_shader_stage stage,
652 bool has_previous_stage,
653 gl_shader_stage previous_stage,
654 struct arg_info *args)
655 {
656 if (!ctx->is_gs_copy_shader &&
657 (stage == MESA_SHADER_VERTEX ||
658 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
659 if (ctx->shader_info->info.vs.has_vertex_buffers) {
660 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
661 &ctx->vertex_buffers);
662 }
663 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
664 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
665 if (ctx->shader_info->info.vs.needs_draw_id) {
666 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
667 }
668 }
669 }
670
671 static void
672 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
673 {
674 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
675 if (!ctx->is_gs_copy_shader) {
676 if (ctx->options->key.vs.as_ls) {
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
678 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
679 } else {
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
681 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
682 }
683 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
684 }
685 }
686
687 static void
688 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
689 {
690 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
691 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
692 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
693 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
694 }
695
696 static void
697 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
698 bool has_previous_stage, gl_shader_stage previous_stage,
699 const struct user_sgpr_info *user_sgpr_info,
700 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
701 {
702 unsigned num_sets = ctx->options->layout ?
703 ctx->options->layout->num_sets : 0;
704 unsigned stage_mask = 1 << stage;
705
706 if (has_previous_stage)
707 stage_mask |= 1 << previous_stage;
708
709 if (!user_sgpr_info->indirect_all_descriptor_sets) {
710 for (unsigned i = 0; i < num_sets; ++i) {
711 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
712 set_loc_desc(ctx, i, user_sgpr_idx, 0);
713 } else
714 ctx->descriptor_sets[i] = NULL;
715 }
716 } else {
717 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
718 user_sgpr_idx, 2);
719
720 for (unsigned i = 0; i < num_sets; ++i) {
721 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
722 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
723 ctx->descriptor_sets[i] =
724 ac_build_load_to_sgpr(&ctx->ac,
725 desc_sets,
726 LLVMConstInt(ctx->ac.i32, i, false));
727
728 } else
729 ctx->descriptor_sets[i] = NULL;
730 }
731 ctx->shader_info->need_indirect_descriptor_sets = true;
732 }
733
734 if (ctx->shader_info->info.loads_push_constants) {
735 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
736 }
737 }
738
739 static void
740 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
741 gl_shader_stage stage, bool has_previous_stage,
742 gl_shader_stage previous_stage,
743 uint8_t *user_sgpr_idx)
744 {
745 if (!ctx->is_gs_copy_shader &&
746 (stage == MESA_SHADER_VERTEX ||
747 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
748 if (ctx->shader_info->info.vs.has_vertex_buffers) {
749 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
750 user_sgpr_idx, 2);
751 }
752
753 unsigned vs_num = 2;
754 if (ctx->shader_info->info.vs.needs_draw_id)
755 vs_num++;
756
757 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
758 user_sgpr_idx, vs_num);
759 }
760 }
761
762 static void create_function(struct nir_to_llvm_context *ctx,
763 gl_shader_stage stage,
764 bool has_previous_stage,
765 gl_shader_stage previous_stage)
766 {
767 uint8_t user_sgpr_idx;
768 struct user_sgpr_info user_sgpr_info;
769 struct arg_info args = {};
770 LLVMValueRef desc_sets;
771
772 allocate_user_sgprs(ctx, stage, &user_sgpr_info);
773
774 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
775 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
776 &ctx->ring_offsets);
777 }
778
779 switch (stage) {
780 case MESA_SHADER_COMPUTE:
781 declare_global_input_sgprs(ctx, stage, has_previous_stage,
782 previous_stage, &user_sgpr_info,
783 &args, &desc_sets);
784
785 if (ctx->shader_info->info.cs.uses_grid_size) {
786 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
787 &ctx->num_work_groups);
788 }
789
790 for (int i = 0; i < 3; i++) {
791 ctx->workgroup_ids[i] = NULL;
792 if (ctx->shader_info->info.cs.uses_block_id[i]) {
793 add_arg(&args, ARG_SGPR, ctx->ac.i32,
794 &ctx->workgroup_ids[i]);
795 }
796 }
797
798 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
799 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
800 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
801 &ctx->local_invocation_ids);
802 break;
803 case MESA_SHADER_VERTEX:
804 declare_global_input_sgprs(ctx, stage, has_previous_stage,
805 previous_stage, &user_sgpr_info,
806 &args, &desc_sets);
807 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
808 previous_stage, &args);
809
810 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
811 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
812 if (ctx->options->key.vs.as_es)
813 add_arg(&args, ARG_SGPR, ctx->ac.i32,
814 &ctx->es2gs_offset);
815 else if (ctx->options->key.vs.as_ls)
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->ls_out_layout);
818
819 declare_vs_input_vgprs(ctx, &args);
820 break;
821 case MESA_SHADER_TESS_CTRL:
822 if (has_previous_stage) {
823 // First 6 system regs
824 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
825 add_arg(&args, ARG_SGPR, ctx->ac.i32,
826 &ctx->merged_wave_info);
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->tess_factor_offset);
829
830 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
831 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
832 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
833
834 declare_global_input_sgprs(ctx, stage,
835 has_previous_stage,
836 previous_stage,
837 &user_sgpr_info, &args,
838 &desc_sets);
839 declare_vs_specific_input_sgprs(ctx, stage,
840 has_previous_stage,
841 previous_stage, &args);
842
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->ls_out_layout);
845
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_offchip_layout);
848 add_arg(&args, ARG_SGPR, ctx->ac.i32,
849 &ctx->tcs_out_offsets);
850 add_arg(&args, ARG_SGPR, ctx->ac.i32,
851 &ctx->tcs_out_layout);
852 add_arg(&args, ARG_SGPR, ctx->ac.i32,
853 &ctx->tcs_in_layout);
854 if (ctx->shader_info->info.needs_multiview_view_index)
855 add_arg(&args, ARG_SGPR, ctx->ac.i32,
856 &ctx->view_index);
857
858 add_arg(&args, ARG_VGPR, ctx->ac.i32,
859 &ctx->abi.tcs_patch_id);
860 add_arg(&args, ARG_VGPR, ctx->ac.i32,
861 &ctx->abi.tcs_rel_ids);
862
863 declare_vs_input_vgprs(ctx, &args);
864 } else {
865 declare_global_input_sgprs(ctx, stage,
866 has_previous_stage,
867 previous_stage,
868 &user_sgpr_info, &args,
869 &desc_sets);
870
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_offchip_layout);
873 add_arg(&args, ARG_SGPR, ctx->ac.i32,
874 &ctx->tcs_out_offsets);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tcs_out_layout);
877 add_arg(&args, ARG_SGPR, ctx->ac.i32,
878 &ctx->tcs_in_layout);
879 if (ctx->shader_info->info.needs_multiview_view_index)
880 add_arg(&args, ARG_SGPR, ctx->ac.i32,
881 &ctx->view_index);
882
883 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
884 add_arg(&args, ARG_SGPR, ctx->ac.i32,
885 &ctx->tess_factor_offset);
886 add_arg(&args, ARG_VGPR, ctx->ac.i32,
887 &ctx->abi.tcs_patch_id);
888 add_arg(&args, ARG_VGPR, ctx->ac.i32,
889 &ctx->abi.tcs_rel_ids);
890 }
891 break;
892 case MESA_SHADER_TESS_EVAL:
893 declare_global_input_sgprs(ctx, stage, has_previous_stage,
894 previous_stage, &user_sgpr_info,
895 &args, &desc_sets);
896
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
898 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
900
901 if (ctx->options->key.tes.as_es) {
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
903 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
904 add_arg(&args, ARG_SGPR, ctx->ac.i32,
905 &ctx->es2gs_offset);
906 } else {
907 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
908 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
909 }
910 declare_tes_input_vgprs(ctx, &args);
911 break;
912 case MESA_SHADER_GEOMETRY:
913 if (has_previous_stage) {
914 // First 6 system regs
915 add_arg(&args, ARG_SGPR, ctx->ac.i32,
916 &ctx->gs2vs_offset);
917 add_arg(&args, ARG_SGPR, ctx->ac.i32,
918 &ctx->merged_wave_info);
919 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
920
921 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
922 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
923 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
924
925 declare_global_input_sgprs(ctx, stage,
926 has_previous_stage,
927 previous_stage,
928 &user_sgpr_info, &args,
929 &desc_sets);
930
931 if (previous_stage == MESA_SHADER_TESS_EVAL) {
932 add_arg(&args, ARG_SGPR, ctx->ac.i32,
933 &ctx->tcs_offchip_layout);
934 } else {
935 declare_vs_specific_input_sgprs(ctx, stage,
936 has_previous_stage,
937 previous_stage,
938 &args);
939 }
940
941 add_arg(&args, ARG_SGPR, ctx->ac.i32,
942 &ctx->gsvs_ring_stride);
943 add_arg(&args, ARG_SGPR, ctx->ac.i32,
944 &ctx->gsvs_num_entries);
945 if (ctx->shader_info->info.needs_multiview_view_index)
946 add_arg(&args, ARG_SGPR, ctx->ac.i32,
947 &ctx->view_index);
948
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[0]);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->gs_vtx_offset[2]);
953 add_arg(&args, ARG_VGPR, ctx->ac.i32,
954 &ctx->abi.gs_prim_id);
955 add_arg(&args, ARG_VGPR, ctx->ac.i32,
956 &ctx->abi.gs_invocation_id);
957 add_arg(&args, ARG_VGPR, ctx->ac.i32,
958 &ctx->gs_vtx_offset[4]);
959
960 if (previous_stage == MESA_SHADER_VERTEX) {
961 declare_vs_input_vgprs(ctx, &args);
962 } else {
963 declare_tes_input_vgprs(ctx, &args);
964 }
965 } else {
966 declare_global_input_sgprs(ctx, stage,
967 has_previous_stage,
968 previous_stage,
969 &user_sgpr_info, &args,
970 &desc_sets);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32,
973 &ctx->gsvs_ring_stride);
974 add_arg(&args, ARG_SGPR, ctx->ac.i32,
975 &ctx->gsvs_num_entries);
976 if (ctx->shader_info->info.needs_multiview_view_index)
977 add_arg(&args, ARG_SGPR, ctx->ac.i32,
978 &ctx->view_index);
979
980 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
981 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[0]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[1]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->abi.gs_prim_id);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[2]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->gs_vtx_offset[3]);
992 add_arg(&args, ARG_VGPR, ctx->ac.i32,
993 &ctx->gs_vtx_offset[4]);
994 add_arg(&args, ARG_VGPR, ctx->ac.i32,
995 &ctx->gs_vtx_offset[5]);
996 add_arg(&args, ARG_VGPR, ctx->ac.i32,
997 &ctx->abi.gs_invocation_id);
998 }
999 break;
1000 case MESA_SHADER_FRAGMENT:
1001 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1002 previous_stage, &user_sgpr_info,
1003 &args, &desc_sets);
1004
1005 if (ctx->shader_info->info.ps.needs_sample_positions)
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1007 &ctx->sample_pos_offset);
1008
1009 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1011 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1012 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1013 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1014 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1015 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1016 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1017 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1018 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1019 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1020 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1021 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1022 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1023 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1024 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1025 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1026 break;
1027 default:
1028 unreachable("Shader stage not implemented");
1029 }
1030
1031 ctx->main_function = create_llvm_function(
1032 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1033 ctx->max_workgroup_size,
1034 ctx->options->unsafe_math);
1035 set_llvm_calling_convention(ctx->main_function, stage);
1036
1037
1038 ctx->shader_info->num_input_vgprs = 0;
1039 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1040
1041 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1042
1043 if (ctx->stage != MESA_SHADER_FRAGMENT)
1044 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1045
1046 assign_arguments(ctx->main_function, &args);
1047
1048 user_sgpr_idx = 0;
1049
1050 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1051 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1052 &user_sgpr_idx, 2);
1053 if (ctx->options->supports_spill) {
1054 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1055 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1056 NULL, 0, AC_FUNC_ATTR_READNONE);
1057 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1058 const_array(ctx->ac.v4i32, 16), "");
1059 }
1060 }
1061
1062 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1063 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1064 if (has_previous_stage)
1065 user_sgpr_idx = 0;
1066
1067 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1068 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1069
1070 switch (stage) {
1071 case MESA_SHADER_COMPUTE:
1072 if (ctx->shader_info->info.cs.uses_grid_size) {
1073 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1074 &user_sgpr_idx, 3);
1075 }
1076 break;
1077 case MESA_SHADER_VERTEX:
1078 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1079 previous_stage, &user_sgpr_idx);
1080 if (ctx->view_index)
1081 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1082 if (ctx->options->key.vs.as_ls) {
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 }
1086 if (ctx->options->key.vs.as_ls)
1087 ac_declare_lds_as_pointer(&ctx->ac);
1088 break;
1089 case MESA_SHADER_TESS_CTRL:
1090 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1091 previous_stage, &user_sgpr_idx);
1092 if (has_previous_stage)
1093 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1094 &user_sgpr_idx, 1);
1095 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1096 if (ctx->view_index)
1097 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1098 ac_declare_lds_as_pointer(&ctx->ac);
1099 break;
1100 case MESA_SHADER_TESS_EVAL:
1101 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1102 if (ctx->view_index)
1103 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1104 break;
1105 case MESA_SHADER_GEOMETRY:
1106 if (has_previous_stage) {
1107 if (previous_stage == MESA_SHADER_VERTEX)
1108 set_vs_specific_input_locs(ctx, stage,
1109 has_previous_stage,
1110 previous_stage,
1111 &user_sgpr_idx);
1112 else
1113 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1114 &user_sgpr_idx, 1);
1115 }
1116 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1117 &user_sgpr_idx, 2);
1118 if (ctx->view_index)
1119 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1120 if (has_previous_stage)
1121 ac_declare_lds_as_pointer(&ctx->ac);
1122 break;
1123 case MESA_SHADER_FRAGMENT:
1124 if (ctx->shader_info->info.ps.needs_sample_positions) {
1125 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1126 &user_sgpr_idx, 1);
1127 }
1128 break;
1129 default:
1130 unreachable("Shader stage not implemented");
1131 }
1132
1133 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1134 }
1135
1136 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1137 LLVMValueRef value, unsigned count)
1138 {
1139 unsigned num_components = ac_get_llvm_num_components(value);
1140 if (count == num_components)
1141 return value;
1142
1143 LLVMValueRef masks[] = {
1144 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1145 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1146
1147 if (count == 1)
1148 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1149 "");
1150
1151 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1152 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1153 }
1154
1155 static void
1156 build_store_values_extended(struct ac_llvm_context *ac,
1157 LLVMValueRef *values,
1158 unsigned value_count,
1159 unsigned value_stride,
1160 LLVMValueRef vec)
1161 {
1162 LLVMBuilderRef builder = ac->builder;
1163 unsigned i;
1164
1165 for (i = 0; i < value_count; i++) {
1166 LLVMValueRef ptr = values[i * value_stride];
1167 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1168 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1169 LLVMBuildStore(builder, value, ptr);
1170 }
1171 }
1172
1173 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1174 const nir_ssa_def *def)
1175 {
1176 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1177 if (def->num_components > 1) {
1178 type = LLVMVectorType(type, def->num_components);
1179 }
1180 return type;
1181 }
1182
1183 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1184 {
1185 assert(src.is_ssa);
1186 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1187 return (LLVMValueRef)entry->data;
1188 }
1189
1190
1191 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1192 const struct nir_block *b)
1193 {
1194 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1195 return (LLVMBasicBlockRef)entry->data;
1196 }
1197
1198 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1199 nir_alu_src src,
1200 unsigned num_components)
1201 {
1202 LLVMValueRef value = get_src(ctx, src.src);
1203 bool need_swizzle = false;
1204
1205 assert(value);
1206 LLVMTypeRef type = LLVMTypeOf(value);
1207 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1208 ? LLVMGetVectorSize(type)
1209 : 1;
1210
1211 for (unsigned i = 0; i < num_components; ++i) {
1212 assert(src.swizzle[i] < src_components);
1213 if (src.swizzle[i] != i)
1214 need_swizzle = true;
1215 }
1216
1217 if (need_swizzle || num_components != src_components) {
1218 LLVMValueRef masks[] = {
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1220 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1221 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1222 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1223
1224 if (src_components > 1 && num_components == 1) {
1225 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1226 masks[0], "");
1227 } else if (src_components == 1 && num_components > 1) {
1228 LLVMValueRef values[] = {value, value, value, value};
1229 value = ac_build_gather_values(&ctx->ac, values, num_components);
1230 } else {
1231 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1232 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1233 swizzle, "");
1234 }
1235 }
1236 assert(!src.negate);
1237 assert(!src.abs);
1238 return value;
1239 }
1240
1241 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1242 LLVMIntPredicate pred, LLVMValueRef src0,
1243 LLVMValueRef src1)
1244 {
1245 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1246 return LLVMBuildSelect(ctx->builder, result,
1247 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1248 ctx->i32_0, "");
1249 }
1250
1251 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1252 LLVMRealPredicate pred, LLVMValueRef src0,
1253 LLVMValueRef src1)
1254 {
1255 LLVMValueRef result;
1256 src0 = ac_to_float(ctx, src0);
1257 src1 = ac_to_float(ctx, src1);
1258 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1259 return LLVMBuildSelect(ctx->builder, result,
1260 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1261 ctx->i32_0, "");
1262 }
1263
1264 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1265 const char *intrin,
1266 LLVMTypeRef result_type,
1267 LLVMValueRef src0)
1268 {
1269 char name[64];
1270 LLVMValueRef params[] = {
1271 ac_to_float(ctx, src0),
1272 };
1273
1274 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1275 get_elem_bits(ctx, result_type));
1276 assert(length < sizeof(name));
1277 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1278 }
1279
1280 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0, LLVMValueRef src1)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 ac_to_float(ctx, src1),
1289 };
1290
1291 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1292 get_elem_bits(ctx, result_type));
1293 assert(length < sizeof(name));
1294 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1295 }
1296
1297 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1298 const char *intrin,
1299 LLVMTypeRef result_type,
1300 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1301 {
1302 char name[64];
1303 LLVMValueRef params[] = {
1304 ac_to_float(ctx, src0),
1305 ac_to_float(ctx, src1),
1306 ac_to_float(ctx, src2),
1307 };
1308
1309 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1310 get_elem_bits(ctx, result_type));
1311 assert(length < sizeof(name));
1312 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1313 }
1314
1315 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1319 ctx->i32_0, "");
1320 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1321 }
1322
1323 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1324 LLVMIntPredicate pred,
1325 LLVMValueRef src0, LLVMValueRef src1)
1326 {
1327 return LLVMBuildSelect(ctx->builder,
1328 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1329 src0,
1330 src1, "");
1331
1332 }
1333 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1334 LLVMValueRef src0)
1335 {
1336 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1337 LLVMBuildNeg(ctx->builder, src0, ""));
1338 }
1339
1340 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1341 LLVMValueRef src0)
1342 {
1343 LLVMValueRef cmp, val;
1344
1345 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1346 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1347 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1348 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1349 return val;
1350 }
1351
1352 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1353 LLVMValueRef src0)
1354 {
1355 LLVMValueRef cmp, val;
1356
1357 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1358 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1359 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1360 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1361 return val;
1362 }
1363
1364 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1365 LLVMValueRef src0)
1366 {
1367 const char *intr = "llvm.floor.f32";
1368 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1369 LLVMValueRef params[] = {
1370 fsrc0,
1371 };
1372 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1373 ctx->f32, params, 1,
1374 AC_FUNC_ATTR_READNONE);
1375 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1376 }
1377
1378 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1379 const char *intrin,
1380 LLVMValueRef src0, LLVMValueRef src1)
1381 {
1382 LLVMTypeRef ret_type;
1383 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1384 LLVMValueRef res;
1385 LLVMValueRef params[] = { src0, src1 };
1386 ret_type = LLVMStructTypeInContext(ctx->context, types,
1387 2, true);
1388
1389 res = ac_build_intrinsic(ctx, intrin, ret_type,
1390 params, 2, AC_FUNC_ATTR_READNONE);
1391
1392 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1393 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1394 return res;
1395 }
1396
1397 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1398 LLVMValueRef src0)
1399 {
1400 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1401 }
1402
1403 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1404 LLVMValueRef src0)
1405 {
1406 src0 = ac_to_float(ctx, src0);
1407 return LLVMBuildSExt(ctx->builder,
1408 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1409 ctx->i32, "");
1410 }
1411
1412 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1413 LLVMValueRef src0)
1414 {
1415 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1416 }
1417
1418 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1419 LLVMValueRef src0)
1420 {
1421 return LLVMBuildSExt(ctx->builder,
1422 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1423 ctx->i32, "");
1424 }
1425
1426 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1427 LLVMValueRef src0)
1428 {
1429 LLVMValueRef result;
1430 LLVMValueRef cond = NULL;
1431
1432 src0 = ac_to_float(&ctx->ac, src0);
1433 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1434
1435 if (ctx->options->chip_class >= VI) {
1436 LLVMValueRef args[2];
1437 /* Check if the result is a denormal - and flush to 0 if so. */
1438 args[0] = result;
1439 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1440 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1441 }
1442
1443 /* need to convert back up to f32 */
1444 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1445
1446 if (ctx->options->chip_class >= VI)
1447 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1448 else {
1449 /* for SI/CIK */
1450 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1451 * so compare the result and flush to 0 if it's smaller.
1452 */
1453 LLVMValueRef temp, cond2;
1454 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1455 ctx->ac.f32, result);
1456 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1457 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1458 temp, "");
1459 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1460 temp, ctx->ac.f32_0, "");
1461 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1462 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1463 }
1464 return result;
1465 }
1466
1467 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1468 LLVMValueRef src0, LLVMValueRef src1)
1469 {
1470 LLVMValueRef dst64, result;
1471 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1472 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1473
1474 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1475 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1476 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1477 return result;
1478 }
1479
1480 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1481 LLVMValueRef src0, LLVMValueRef src1)
1482 {
1483 LLVMValueRef dst64, result;
1484 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1485 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1486
1487 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1488 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1489 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1490 return result;
1491 }
1492
1493 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1494 bool is_signed,
1495 const LLVMValueRef srcs[3])
1496 {
1497 LLVMValueRef result;
1498 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1499
1500 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1501 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1502 return result;
1503 }
1504
1505 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1506 LLVMValueRef src0, LLVMValueRef src1,
1507 LLVMValueRef src2, LLVMValueRef src3)
1508 {
1509 LLVMValueRef bfi_args[3], result;
1510
1511 bfi_args[0] = LLVMBuildShl(ctx->builder,
1512 LLVMBuildSub(ctx->builder,
1513 LLVMBuildShl(ctx->builder,
1514 ctx->i32_1,
1515 src3, ""),
1516 ctx->i32_1, ""),
1517 src2, "");
1518 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1519 bfi_args[2] = src0;
1520
1521 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1522
1523 /* Calculate:
1524 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1525 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1526 */
1527 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1528 LLVMBuildAnd(ctx->builder, bfi_args[0],
1529 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1530
1531 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1532 return result;
1533 }
1534
1535 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1536 LLVMValueRef src0)
1537 {
1538 LLVMValueRef comp[2];
1539
1540 src0 = ac_to_float(ctx, src0);
1541 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1542 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1543
1544 return ac_build_cvt_pkrtz_f16(ctx, comp);
1545 }
1546
1547 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1548 LLVMValueRef src0)
1549 {
1550 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1551 LLVMValueRef temps[2], result, val;
1552 int i;
1553
1554 for (i = 0; i < 2; i++) {
1555 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1556 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1557 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1558 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1559 }
1560
1561 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1562 ctx->i32_0, "");
1563 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1564 ctx->i32_1, "");
1565 return result;
1566 }
1567
1568 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1569 nir_op op,
1570 LLVMValueRef src0)
1571 {
1572 unsigned mask;
1573 int idx;
1574 LLVMValueRef result;
1575
1576 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1577 mask = AC_TID_MASK_LEFT;
1578 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1579 mask = AC_TID_MASK_TOP;
1580 else
1581 mask = AC_TID_MASK_TOP_LEFT;
1582
1583 /* for DDX we want to next X pixel, DDY next Y pixel. */
1584 if (op == nir_op_fddx_fine ||
1585 op == nir_op_fddx_coarse ||
1586 op == nir_op_fddx)
1587 idx = 1;
1588 else
1589 idx = 2;
1590
1591 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1592 return result;
1593 }
1594
1595 /*
1596 * this takes an I,J coordinate pair,
1597 * and works out the X and Y derivatives.
1598 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1599 */
1600 static LLVMValueRef emit_ddxy_interp(
1601 struct ac_nir_context *ctx,
1602 LLVMValueRef interp_ij)
1603 {
1604 LLVMValueRef result[4], a;
1605 unsigned i;
1606
1607 for (i = 0; i < 2; i++) {
1608 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1609 LLVMConstInt(ctx->ac.i32, i, false), "");
1610 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1611 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1612 }
1613 return ac_build_gather_values(&ctx->ac, result, 4);
1614 }
1615
1616 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1617 {
1618 LLVMValueRef src[4], result = NULL;
1619 unsigned num_components = instr->dest.dest.ssa.num_components;
1620 unsigned src_components;
1621 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1622
1623 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1624 switch (instr->op) {
1625 case nir_op_vec2:
1626 case nir_op_vec3:
1627 case nir_op_vec4:
1628 src_components = 1;
1629 break;
1630 case nir_op_pack_half_2x16:
1631 src_components = 2;
1632 break;
1633 case nir_op_unpack_half_2x16:
1634 src_components = 1;
1635 break;
1636 default:
1637 src_components = num_components;
1638 break;
1639 }
1640 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1641 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1642
1643 switch (instr->op) {
1644 case nir_op_fmov:
1645 case nir_op_imov:
1646 result = src[0];
1647 break;
1648 case nir_op_fneg:
1649 src[0] = ac_to_float(&ctx->ac, src[0]);
1650 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1651 break;
1652 case nir_op_ineg:
1653 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1654 break;
1655 case nir_op_inot:
1656 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1657 break;
1658 case nir_op_iadd:
1659 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1660 break;
1661 case nir_op_fadd:
1662 src[0] = ac_to_float(&ctx->ac, src[0]);
1663 src[1] = ac_to_float(&ctx->ac, src[1]);
1664 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1665 break;
1666 case nir_op_fsub:
1667 src[0] = ac_to_float(&ctx->ac, src[0]);
1668 src[1] = ac_to_float(&ctx->ac, src[1]);
1669 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1670 break;
1671 case nir_op_isub:
1672 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1673 break;
1674 case nir_op_imul:
1675 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1676 break;
1677 case nir_op_imod:
1678 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1679 break;
1680 case nir_op_umod:
1681 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1682 break;
1683 case nir_op_fmod:
1684 src[0] = ac_to_float(&ctx->ac, src[0]);
1685 src[1] = ac_to_float(&ctx->ac, src[1]);
1686 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1687 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1688 ac_to_float_type(&ctx->ac, def_type), result);
1689 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1690 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1691 break;
1692 case nir_op_frem:
1693 src[0] = ac_to_float(&ctx->ac, src[0]);
1694 src[1] = ac_to_float(&ctx->ac, src[1]);
1695 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1696 break;
1697 case nir_op_irem:
1698 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1699 break;
1700 case nir_op_idiv:
1701 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_udiv:
1704 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1705 break;
1706 case nir_op_fmul:
1707 src[0] = ac_to_float(&ctx->ac, src[0]);
1708 src[1] = ac_to_float(&ctx->ac, src[1]);
1709 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1710 break;
1711 case nir_op_fdiv:
1712 src[0] = ac_to_float(&ctx->ac, src[0]);
1713 src[1] = ac_to_float(&ctx->ac, src[1]);
1714 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1715 break;
1716 case nir_op_frcp:
1717 src[0] = ac_to_float(&ctx->ac, src[0]);
1718 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1719 src[0]);
1720 break;
1721 case nir_op_iand:
1722 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1723 break;
1724 case nir_op_ior:
1725 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1726 break;
1727 case nir_op_ixor:
1728 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1729 break;
1730 case nir_op_ishl:
1731 result = LLVMBuildShl(ctx->ac.builder, src[0],
1732 LLVMBuildZExt(ctx->ac.builder, src[1],
1733 LLVMTypeOf(src[0]), ""),
1734 "");
1735 break;
1736 case nir_op_ishr:
1737 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1738 LLVMBuildZExt(ctx->ac.builder, src[1],
1739 LLVMTypeOf(src[0]), ""),
1740 "");
1741 break;
1742 case nir_op_ushr:
1743 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1744 LLVMBuildZExt(ctx->ac.builder, src[1],
1745 LLVMTypeOf(src[0]), ""),
1746 "");
1747 break;
1748 case nir_op_ilt:
1749 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1750 break;
1751 case nir_op_ine:
1752 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1753 break;
1754 case nir_op_ieq:
1755 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1756 break;
1757 case nir_op_ige:
1758 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1759 break;
1760 case nir_op_ult:
1761 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1762 break;
1763 case nir_op_uge:
1764 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1765 break;
1766 case nir_op_feq:
1767 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1768 break;
1769 case nir_op_fne:
1770 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1771 break;
1772 case nir_op_flt:
1773 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1774 break;
1775 case nir_op_fge:
1776 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1777 break;
1778 case nir_op_fabs:
1779 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1780 ac_to_float_type(&ctx->ac, def_type), src[0]);
1781 break;
1782 case nir_op_iabs:
1783 result = emit_iabs(&ctx->ac, src[0]);
1784 break;
1785 case nir_op_imax:
1786 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1787 break;
1788 case nir_op_imin:
1789 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1790 break;
1791 case nir_op_umax:
1792 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1793 break;
1794 case nir_op_umin:
1795 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1796 break;
1797 case nir_op_isign:
1798 result = emit_isign(&ctx->ac, src[0]);
1799 break;
1800 case nir_op_fsign:
1801 src[0] = ac_to_float(&ctx->ac, src[0]);
1802 result = emit_fsign(&ctx->ac, src[0]);
1803 break;
1804 case nir_op_ffloor:
1805 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1806 ac_to_float_type(&ctx->ac, def_type), src[0]);
1807 break;
1808 case nir_op_ftrunc:
1809 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1810 ac_to_float_type(&ctx->ac, def_type), src[0]);
1811 break;
1812 case nir_op_fceil:
1813 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1814 ac_to_float_type(&ctx->ac, def_type), src[0]);
1815 break;
1816 case nir_op_fround_even:
1817 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1818 ac_to_float_type(&ctx->ac, def_type),src[0]);
1819 break;
1820 case nir_op_ffract:
1821 result = emit_ffract(&ctx->ac, src[0]);
1822 break;
1823 case nir_op_fsin:
1824 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1825 ac_to_float_type(&ctx->ac, def_type), src[0]);
1826 break;
1827 case nir_op_fcos:
1828 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1829 ac_to_float_type(&ctx->ac, def_type), src[0]);
1830 break;
1831 case nir_op_fsqrt:
1832 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1833 ac_to_float_type(&ctx->ac, def_type), src[0]);
1834 break;
1835 case nir_op_fexp2:
1836 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1837 ac_to_float_type(&ctx->ac, def_type), src[0]);
1838 break;
1839 case nir_op_flog2:
1840 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1841 ac_to_float_type(&ctx->ac, def_type), src[0]);
1842 break;
1843 case nir_op_frsq:
1844 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1845 ac_to_float_type(&ctx->ac, def_type), src[0]);
1846 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1847 result);
1848 break;
1849 case nir_op_fpow:
1850 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1851 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1852 break;
1853 case nir_op_fmax:
1854 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1855 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1856 if (instr->dest.dest.ssa.bit_size == 32)
1857 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1858 ac_to_float_type(&ctx->ac, def_type),
1859 result);
1860 break;
1861 case nir_op_fmin:
1862 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1863 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1864 if (instr->dest.dest.ssa.bit_size == 32)
1865 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1866 ac_to_float_type(&ctx->ac, def_type),
1867 result);
1868 break;
1869 case nir_op_ffma:
1870 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1871 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1872 break;
1873 case nir_op_ibitfield_extract:
1874 result = emit_bitfield_extract(&ctx->ac, true, src);
1875 break;
1876 case nir_op_ubitfield_extract:
1877 result = emit_bitfield_extract(&ctx->ac, false, src);
1878 break;
1879 case nir_op_bitfield_insert:
1880 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1881 break;
1882 case nir_op_bitfield_reverse:
1883 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1884 break;
1885 case nir_op_bit_count:
1886 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1887 break;
1888 case nir_op_vec2:
1889 case nir_op_vec3:
1890 case nir_op_vec4:
1891 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1892 src[i] = ac_to_integer(&ctx->ac, src[i]);
1893 result = ac_build_gather_values(&ctx->ac, src, num_components);
1894 break;
1895 case nir_op_f2i32:
1896 case nir_op_f2i64:
1897 src[0] = ac_to_float(&ctx->ac, src[0]);
1898 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1899 break;
1900 case nir_op_f2u32:
1901 case nir_op_f2u64:
1902 src[0] = ac_to_float(&ctx->ac, src[0]);
1903 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1904 break;
1905 case nir_op_i2f32:
1906 case nir_op_i2f64:
1907 src[0] = ac_to_integer(&ctx->ac, src[0]);
1908 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1909 break;
1910 case nir_op_u2f32:
1911 case nir_op_u2f64:
1912 src[0] = ac_to_integer(&ctx->ac, src[0]);
1913 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1914 break;
1915 case nir_op_f2f64:
1916 src[0] = ac_to_float(&ctx->ac, src[0]);
1917 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1918 break;
1919 case nir_op_f2f32:
1920 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1921 break;
1922 case nir_op_u2u32:
1923 case nir_op_u2u64:
1924 src[0] = ac_to_integer(&ctx->ac, src[0]);
1925 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1926 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1927 else
1928 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1929 break;
1930 case nir_op_i2i32:
1931 case nir_op_i2i64:
1932 src[0] = ac_to_integer(&ctx->ac, src[0]);
1933 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1934 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1935 else
1936 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1937 break;
1938 case nir_op_bcsel:
1939 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1940 break;
1941 case nir_op_find_lsb:
1942 src[0] = ac_to_integer(&ctx->ac, src[0]);
1943 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1944 break;
1945 case nir_op_ufind_msb:
1946 src[0] = ac_to_integer(&ctx->ac, src[0]);
1947 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1948 break;
1949 case nir_op_ifind_msb:
1950 src[0] = ac_to_integer(&ctx->ac, src[0]);
1951 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1952 break;
1953 case nir_op_uadd_carry:
1954 src[0] = ac_to_integer(&ctx->ac, src[0]);
1955 src[1] = ac_to_integer(&ctx->ac, src[1]);
1956 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1957 break;
1958 case nir_op_usub_borrow:
1959 src[0] = ac_to_integer(&ctx->ac, src[0]);
1960 src[1] = ac_to_integer(&ctx->ac, src[1]);
1961 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1962 break;
1963 case nir_op_b2f:
1964 result = emit_b2f(&ctx->ac, src[0]);
1965 break;
1966 case nir_op_f2b:
1967 result = emit_f2b(&ctx->ac, src[0]);
1968 break;
1969 case nir_op_b2i:
1970 result = emit_b2i(&ctx->ac, src[0]);
1971 break;
1972 case nir_op_i2b:
1973 src[0] = ac_to_integer(&ctx->ac, src[0]);
1974 result = emit_i2b(&ctx->ac, src[0]);
1975 break;
1976 case nir_op_fquantize2f16:
1977 result = emit_f2f16(ctx->nctx, src[0]);
1978 break;
1979 case nir_op_umul_high:
1980 src[0] = ac_to_integer(&ctx->ac, src[0]);
1981 src[1] = ac_to_integer(&ctx->ac, src[1]);
1982 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1983 break;
1984 case nir_op_imul_high:
1985 src[0] = ac_to_integer(&ctx->ac, src[0]);
1986 src[1] = ac_to_integer(&ctx->ac, src[1]);
1987 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1988 break;
1989 case nir_op_pack_half_2x16:
1990 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1991 break;
1992 case nir_op_unpack_half_2x16:
1993 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1994 break;
1995 case nir_op_fddx:
1996 case nir_op_fddy:
1997 case nir_op_fddx_fine:
1998 case nir_op_fddy_fine:
1999 case nir_op_fddx_coarse:
2000 case nir_op_fddy_coarse:
2001 result = emit_ddxy(ctx, instr->op, src[0]);
2002 break;
2003
2004 case nir_op_unpack_64_2x32_split_x: {
2005 assert(instr->src[0].src.ssa->num_components == 1);
2006 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2007 ctx->ac.v2i32,
2008 "");
2009 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2010 ctx->ac.i32_0, "");
2011 break;
2012 }
2013
2014 case nir_op_unpack_64_2x32_split_y: {
2015 assert(instr->src[0].src.ssa->num_components == 1);
2016 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2017 ctx->ac.v2i32,
2018 "");
2019 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2020 ctx->ac.i32_1, "");
2021 break;
2022 }
2023
2024 case nir_op_pack_64_2x32_split: {
2025 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2026 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2027 src[0], ctx->ac.i32_0, "");
2028 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2029 src[1], ctx->ac.i32_1, "");
2030 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2031 break;
2032 }
2033
2034 default:
2035 fprintf(stderr, "Unknown NIR alu instr: ");
2036 nir_print_instr(&instr->instr, stderr);
2037 fprintf(stderr, "\n");
2038 abort();
2039 }
2040
2041 if (result) {
2042 assert(instr->dest.dest.is_ssa);
2043 result = ac_to_integer(&ctx->ac, result);
2044 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2045 result);
2046 }
2047 }
2048
2049 static void visit_load_const(struct ac_nir_context *ctx,
2050 const nir_load_const_instr *instr)
2051 {
2052 LLVMValueRef values[4], value = NULL;
2053 LLVMTypeRef element_type =
2054 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2055
2056 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2057 switch (instr->def.bit_size) {
2058 case 32:
2059 values[i] = LLVMConstInt(element_type,
2060 instr->value.u32[i], false);
2061 break;
2062 case 64:
2063 values[i] = LLVMConstInt(element_type,
2064 instr->value.u64[i], false);
2065 break;
2066 default:
2067 fprintf(stderr,
2068 "unsupported nir load_const bit_size: %d\n",
2069 instr->def.bit_size);
2070 abort();
2071 }
2072 }
2073 if (instr->def.num_components > 1) {
2074 value = LLVMConstVector(values, instr->def.num_components);
2075 } else
2076 value = values[0];
2077
2078 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2079 }
2080
2081 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2082 LLVMTypeRef type)
2083 {
2084 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2085 return LLVMBuildBitCast(ctx->builder, ptr,
2086 LLVMPointerType(type, addr_space), "");
2087 }
2088
2089 static LLVMValueRef
2090 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2091 {
2092 LLVMValueRef size =
2093 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2094 LLVMConstInt(ctx->ac.i32, 2, false), "");
2095
2096 /* VI only */
2097 if (ctx->ac.chip_class == VI && in_elements) {
2098 /* On VI, the descriptor contains the size in bytes,
2099 * but TXQ must return the size in elements.
2100 * The stride is always non-zero for resources using TXQ.
2101 */
2102 LLVMValueRef stride =
2103 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2104 ctx->ac.i32_1, "");
2105 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2106 LLVMConstInt(ctx->ac.i32, 16, false), "");
2107 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2108 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2109
2110 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2111 }
2112 return size;
2113 }
2114
2115 /**
2116 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2117 * intrinsic names).
2118 */
2119 static void build_int_type_name(
2120 LLVMTypeRef type,
2121 char *buf, unsigned bufsize)
2122 {
2123 assert(bufsize >= 6);
2124
2125 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2126 snprintf(buf, bufsize, "v%ui32",
2127 LLVMGetVectorSize(type));
2128 else
2129 strcpy(buf, "i32");
2130 }
2131
2132 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2133 struct ac_image_args *args,
2134 const nir_tex_instr *instr)
2135 {
2136 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2137 LLVMValueRef coord = args->addr;
2138 LLVMValueRef half_texel[2];
2139 LLVMValueRef compare_cube_wa = NULL;
2140 LLVMValueRef result;
2141 int c;
2142 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2143
2144 //TODO Rect
2145 {
2146 struct ac_image_args txq_args = { 0 };
2147
2148 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2149 txq_args.opcode = ac_image_get_resinfo;
2150 txq_args.dmask = 0xf;
2151 txq_args.addr = ctx->i32_0;
2152 txq_args.resource = args->resource;
2153 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2154
2155 for (c = 0; c < 2; c++) {
2156 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2157 LLVMConstInt(ctx->i32, c, false), "");
2158 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2159 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2160 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2161 LLVMConstReal(ctx->f32, -0.5), "");
2162 }
2163 }
2164
2165 LLVMValueRef orig_coords = args->addr;
2166
2167 for (c = 0; c < 2; c++) {
2168 LLVMValueRef tmp;
2169 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2170 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2171 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2172 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2173 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2174 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2175 }
2176
2177
2178 /*
2179 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2180 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2181 * workaround by sampling using a scaled type and converting.
2182 * This is taken from amdgpu-pro shaders.
2183 */
2184 /* NOTE this produces some ugly code compared to amdgpu-pro,
2185 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2186 * and then reads them back. -pro generates two selects,
2187 * one s_cmp for the descriptor rewriting
2188 * one v_cmp for the coordinate and result changes.
2189 */
2190 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2191 LLVMValueRef tmp, tmp2;
2192
2193 /* workaround 8/8/8/8 uint/sint cube gather bug */
2194 /* first detect it then change to a scaled read and f2i */
2195 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2196 tmp2 = tmp;
2197
2198 /* extract the DATA_FORMAT */
2199 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2200 LLVMConstInt(ctx->i32, 6, false), false);
2201
2202 /* is the DATA_FORMAT == 8_8_8_8 */
2203 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2204
2205 if (stype == GLSL_TYPE_UINT)
2206 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2207 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2208 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2209 else
2210 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2211 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2212 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2213
2214 /* replace the NUM FORMAT in the descriptor */
2215 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2216 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2217
2218 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2219
2220 /* don't modify the coordinates for this case */
2221 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2222 }
2223 args->addr = coord;
2224 result = ac_build_image_opcode(ctx, args);
2225
2226 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2227 LLVMValueRef tmp, tmp2;
2228
2229 /* if the cube workaround is in place, f2i the result. */
2230 for (c = 0; c < 4; c++) {
2231 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2232 if (stype == GLSL_TYPE_UINT)
2233 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2234 else
2235 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2236 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2237 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2238 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2239 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2240 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2241 }
2242 }
2243 return result;
2244 }
2245
2246 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2247 const nir_tex_instr *instr,
2248 bool lod_is_zero,
2249 struct ac_image_args *args)
2250 {
2251 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2252 return ac_build_buffer_load_format(&ctx->ac,
2253 args->resource,
2254 args->addr,
2255 ctx->ac.i32_0,
2256 true);
2257 }
2258
2259 args->opcode = ac_image_sample;
2260 args->compare = instr->is_shadow;
2261
2262 switch (instr->op) {
2263 case nir_texop_txf:
2264 case nir_texop_txf_ms:
2265 case nir_texop_samples_identical:
2266 args->opcode = lod_is_zero ||
2267 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2268 ac_image_load : ac_image_load_mip;
2269 args->compare = false;
2270 args->offset = false;
2271 break;
2272 case nir_texop_txb:
2273 args->bias = true;
2274 break;
2275 case nir_texop_txl:
2276 if (lod_is_zero)
2277 args->level_zero = true;
2278 else
2279 args->lod = true;
2280 break;
2281 case nir_texop_txs:
2282 case nir_texop_query_levels:
2283 args->opcode = ac_image_get_resinfo;
2284 break;
2285 case nir_texop_tex:
2286 if (ctx->stage != MESA_SHADER_FRAGMENT)
2287 args->level_zero = true;
2288 break;
2289 case nir_texop_txd:
2290 args->deriv = true;
2291 break;
2292 case nir_texop_tg4:
2293 args->opcode = ac_image_gather4;
2294 args->level_zero = true;
2295 break;
2296 case nir_texop_lod:
2297 args->opcode = ac_image_get_lod;
2298 args->compare = false;
2299 args->offset = false;
2300 break;
2301 default:
2302 break;
2303 }
2304
2305 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2306 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2307 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2308 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2309 }
2310 }
2311 return ac_build_image_opcode(&ctx->ac, args);
2312 }
2313
2314 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2315 nir_intrinsic_instr *instr)
2316 {
2317 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2318 unsigned desc_set = nir_intrinsic_desc_set(instr);
2319 unsigned binding = nir_intrinsic_binding(instr);
2320 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2321 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2322 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2323 unsigned base_offset = layout->binding[binding].offset;
2324 LLVMValueRef offset, stride;
2325
2326 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2327 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2328 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2329 layout->binding[binding].dynamic_offset_offset;
2330 desc_ptr = ctx->push_constants;
2331 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2332 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2333 } else
2334 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2335
2336 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2337 index = LLVMBuildMul(ctx->builder, index, stride, "");
2338 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2339
2340 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2341 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2342 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2343
2344 return desc_ptr;
2345 }
2346
2347 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2348 nir_intrinsic_instr *instr)
2349 {
2350 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2351 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2352
2353 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2354 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2355 return result;
2356 }
2357
2358 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2359 nir_intrinsic_instr *instr)
2360 {
2361 LLVMValueRef ptr, addr;
2362
2363 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2364 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2365
2366 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2367 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2368
2369 return LLVMBuildLoad(ctx->builder, ptr, "");
2370 }
2371
2372 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2373 const nir_intrinsic_instr *instr)
2374 {
2375 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2376
2377 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2378 }
2379 static void visit_store_ssbo(struct ac_nir_context *ctx,
2380 nir_intrinsic_instr *instr)
2381 {
2382 const char *store_name;
2383 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2384 LLVMTypeRef data_type = ctx->ac.f32;
2385 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2386 int components_32bit = elem_size_mult * instr->num_components;
2387 unsigned writemask = nir_intrinsic_write_mask(instr);
2388 LLVMValueRef base_data, base_offset;
2389 LLVMValueRef params[6];
2390
2391 params[1] = ctx->abi->load_ssbo(ctx->abi,
2392 get_src(ctx, instr->src[1]), true);
2393 params[2] = ctx->ac.i32_0; /* vindex */
2394 params[4] = ctx->ac.i1false; /* glc */
2395 params[5] = ctx->ac.i1false; /* slc */
2396
2397 if (components_32bit > 1)
2398 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2399
2400 base_data = ac_to_float(&ctx->ac, src_data);
2401 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2402 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2403 data_type, "");
2404 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2405 while (writemask) {
2406 int start, count;
2407 LLVMValueRef data;
2408 LLVMValueRef offset;
2409 LLVMValueRef tmp;
2410 u_bit_scan_consecutive_range(&writemask, &start, &count);
2411
2412 /* Due to an LLVM limitation, split 3-element writes
2413 * into a 2-element and a 1-element write. */
2414 if (count == 3) {
2415 writemask |= 1 << (start + 2);
2416 count = 2;
2417 }
2418
2419 start *= elem_size_mult;
2420 count *= elem_size_mult;
2421
2422 if (count > 4) {
2423 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2424 count = 4;
2425 }
2426
2427 if (count == 4) {
2428 store_name = "llvm.amdgcn.buffer.store.v4f32";
2429 data = base_data;
2430 } else if (count == 2) {
2431 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2432 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2433 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2434 ctx->ac.i32_0, "");
2435
2436 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2437 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2438 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2439 ctx->ac.i32_1, "");
2440 store_name = "llvm.amdgcn.buffer.store.v2f32";
2441
2442 } else {
2443 assert(count == 1);
2444 if (ac_get_llvm_num_components(base_data) > 1)
2445 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2446 LLVMConstInt(ctx->ac.i32, start, false), "");
2447 else
2448 data = base_data;
2449 store_name = "llvm.amdgcn.buffer.store.f32";
2450 }
2451
2452 offset = base_offset;
2453 if (start != 0) {
2454 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2455 }
2456 params[0] = data;
2457 params[3] = offset;
2458 ac_build_intrinsic(&ctx->ac, store_name,
2459 ctx->ac.voidt, params, 6, 0);
2460 }
2461 }
2462
2463 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2464 const nir_intrinsic_instr *instr)
2465 {
2466 const char *name;
2467 LLVMValueRef params[6];
2468 int arg_count = 0;
2469
2470 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2471 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2472 }
2473 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2474 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2475 get_src(ctx, instr->src[0]),
2476 true);
2477 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2478 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2479 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2480
2481 switch (instr->intrinsic) {
2482 case nir_intrinsic_ssbo_atomic_add:
2483 name = "llvm.amdgcn.buffer.atomic.add";
2484 break;
2485 case nir_intrinsic_ssbo_atomic_imin:
2486 name = "llvm.amdgcn.buffer.atomic.smin";
2487 break;
2488 case nir_intrinsic_ssbo_atomic_umin:
2489 name = "llvm.amdgcn.buffer.atomic.umin";
2490 break;
2491 case nir_intrinsic_ssbo_atomic_imax:
2492 name = "llvm.amdgcn.buffer.atomic.smax";
2493 break;
2494 case nir_intrinsic_ssbo_atomic_umax:
2495 name = "llvm.amdgcn.buffer.atomic.umax";
2496 break;
2497 case nir_intrinsic_ssbo_atomic_and:
2498 name = "llvm.amdgcn.buffer.atomic.and";
2499 break;
2500 case nir_intrinsic_ssbo_atomic_or:
2501 name = "llvm.amdgcn.buffer.atomic.or";
2502 break;
2503 case nir_intrinsic_ssbo_atomic_xor:
2504 name = "llvm.amdgcn.buffer.atomic.xor";
2505 break;
2506 case nir_intrinsic_ssbo_atomic_exchange:
2507 name = "llvm.amdgcn.buffer.atomic.swap";
2508 break;
2509 case nir_intrinsic_ssbo_atomic_comp_swap:
2510 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2511 break;
2512 default:
2513 abort();
2514 }
2515
2516 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2517 }
2518
2519 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2520 const nir_intrinsic_instr *instr)
2521 {
2522 LLVMValueRef results[2];
2523 int load_components;
2524 int num_components = instr->num_components;
2525 if (instr->dest.ssa.bit_size == 64)
2526 num_components *= 2;
2527
2528 for (int i = 0; i < num_components; i += load_components) {
2529 load_components = MIN2(num_components - i, 4);
2530 const char *load_name;
2531 LLVMTypeRef data_type = ctx->ac.f32;
2532 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2533 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2534
2535 if (load_components == 3)
2536 data_type = LLVMVectorType(ctx->ac.f32, 4);
2537 else if (load_components > 1)
2538 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2539
2540 if (load_components >= 3)
2541 load_name = "llvm.amdgcn.buffer.load.v4f32";
2542 else if (load_components == 2)
2543 load_name = "llvm.amdgcn.buffer.load.v2f32";
2544 else if (load_components == 1)
2545 load_name = "llvm.amdgcn.buffer.load.f32";
2546 else
2547 unreachable("unhandled number of components");
2548
2549 LLVMValueRef params[] = {
2550 ctx->abi->load_ssbo(ctx->abi,
2551 get_src(ctx, instr->src[0]),
2552 false),
2553 ctx->ac.i32_0,
2554 offset,
2555 ctx->ac.i1false,
2556 ctx->ac.i1false,
2557 };
2558
2559 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2560
2561 }
2562
2563 assume(results[0]);
2564 LLVMValueRef ret = results[0];
2565 if (num_components > 4 || num_components == 3) {
2566 LLVMValueRef masks[] = {
2567 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2568 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2569 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2570 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2571 };
2572
2573 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2574 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2575 results[num_components > 4 ? 1 : 0], swizzle, "");
2576 }
2577
2578 return LLVMBuildBitCast(ctx->ac.builder, ret,
2579 get_def_type(ctx, &instr->dest.ssa), "");
2580 }
2581
2582 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2583 const nir_intrinsic_instr *instr)
2584 {
2585 LLVMValueRef ret;
2586 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2587 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2588 int num_components = instr->num_components;
2589
2590 if (ctx->abi->load_ubo)
2591 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2592
2593 if (instr->dest.ssa.bit_size == 64)
2594 num_components *= 2;
2595
2596 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2597 NULL, 0, false, false, true, true);
2598
2599 return LLVMBuildBitCast(ctx->ac.builder, ret,
2600 get_def_type(ctx, &instr->dest.ssa), "");
2601 }
2602
2603 static void
2604 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2605 bool vs_in, unsigned *vertex_index_out,
2606 LLVMValueRef *vertex_index_ref,
2607 unsigned *const_out, LLVMValueRef *indir_out)
2608 {
2609 unsigned const_offset = 0;
2610 nir_deref *tail = &deref->deref;
2611 LLVMValueRef offset = NULL;
2612
2613 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2614 tail = tail->child;
2615 nir_deref_array *deref_array = nir_deref_as_array(tail);
2616 if (vertex_index_out)
2617 *vertex_index_out = deref_array->base_offset;
2618
2619 if (vertex_index_ref) {
2620 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2621 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2622 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2623 }
2624 *vertex_index_ref = vtx;
2625 }
2626 }
2627
2628 if (deref->var->data.compact) {
2629 assert(tail->child->deref_type == nir_deref_type_array);
2630 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2631 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2632 /* We always lower indirect dereferences for "compact" array vars. */
2633 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2634
2635 const_offset = deref_array->base_offset;
2636 goto out;
2637 }
2638
2639 while (tail->child != NULL) {
2640 const struct glsl_type *parent_type = tail->type;
2641 tail = tail->child;
2642
2643 if (tail->deref_type == nir_deref_type_array) {
2644 nir_deref_array *deref_array = nir_deref_as_array(tail);
2645 LLVMValueRef index, stride, local_offset;
2646 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2647
2648 const_offset += size * deref_array->base_offset;
2649 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2650 continue;
2651
2652 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2653 index = get_src(ctx, deref_array->indirect);
2654 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2655 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2656
2657 if (offset)
2658 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2659 else
2660 offset = local_offset;
2661 } else if (tail->deref_type == nir_deref_type_struct) {
2662 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2663
2664 for (unsigned i = 0; i < deref_struct->index; i++) {
2665 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2666 const_offset += glsl_count_attribute_slots(ft, vs_in);
2667 }
2668 } else
2669 unreachable("unsupported deref type");
2670
2671 }
2672 out:
2673 if (const_offset && offset)
2674 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2675 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2676 "");
2677
2678 *const_out = const_offset;
2679 *indir_out = offset;
2680 }
2681
2682
2683 /* The offchip buffer layout for TCS->TES is
2684 *
2685 * - attribute 0 of patch 0 vertex 0
2686 * - attribute 0 of patch 0 vertex 1
2687 * - attribute 0 of patch 0 vertex 2
2688 * ...
2689 * - attribute 0 of patch 1 vertex 0
2690 * - attribute 0 of patch 1 vertex 1
2691 * ...
2692 * - attribute 1 of patch 0 vertex 0
2693 * - attribute 1 of patch 0 vertex 1
2694 * ...
2695 * - per patch attribute 0 of patch 0
2696 * - per patch attribute 0 of patch 1
2697 * ...
2698 *
2699 * Note that every attribute has 4 components.
2700 */
2701 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2702 LLVMValueRef vertex_index,
2703 LLVMValueRef param_index)
2704 {
2705 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2706 LLVMValueRef param_stride, constant16;
2707 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2708
2709 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2710 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2711 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2712 num_patches, "");
2713
2714 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2715 if (vertex_index) {
2716 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2717 vertices_per_patch, "");
2718
2719 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2720 vertex_index, "");
2721
2722 param_stride = total_vertices;
2723 } else {
2724 base_addr = rel_patch_id;
2725 param_stride = num_patches;
2726 }
2727
2728 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2729 LLVMBuildMul(ctx->builder, param_index,
2730 param_stride, ""), "");
2731
2732 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2733
2734 if (!vertex_index) {
2735 LLVMValueRef patch_data_offset =
2736 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2737
2738 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2739 patch_data_offset, "");
2740 }
2741 return base_addr;
2742 }
2743
2744 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2745 unsigned param,
2746 unsigned const_index,
2747 bool is_compact,
2748 LLVMValueRef vertex_index,
2749 LLVMValueRef indir_index)
2750 {
2751 LLVMValueRef param_index;
2752
2753 if (indir_index)
2754 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2755 indir_index, "");
2756 else {
2757 if (const_index && !is_compact)
2758 param += const_index;
2759 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2760 }
2761 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2762 }
2763
2764 static void
2765 mark_tess_output(struct nir_to_llvm_context *ctx,
2766 bool is_patch, uint32_t param)
2767
2768 {
2769 if (is_patch) {
2770 ctx->tess_patch_outputs_written |= (1ull << param);
2771 } else
2772 ctx->tess_outputs_written |= (1ull << param);
2773 }
2774
2775 static LLVMValueRef
2776 get_dw_address(struct nir_to_llvm_context *ctx,
2777 LLVMValueRef dw_addr,
2778 unsigned param,
2779 unsigned const_index,
2780 bool compact_const_index,
2781 LLVMValueRef vertex_index,
2782 LLVMValueRef stride,
2783 LLVMValueRef indir_index)
2784
2785 {
2786
2787 if (vertex_index) {
2788 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2789 LLVMBuildMul(ctx->builder,
2790 vertex_index,
2791 stride, ""), "");
2792 }
2793
2794 if (indir_index)
2795 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2796 LLVMBuildMul(ctx->builder, indir_index,
2797 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2798 else if (const_index && !compact_const_index)
2799 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2800 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2801
2802 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2803 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2804
2805 if (const_index && compact_const_index)
2806 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2807 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2808 return dw_addr;
2809 }
2810
2811 static LLVMValueRef
2812 load_tcs_input(struct ac_shader_abi *abi,
2813 LLVMValueRef vertex_index,
2814 LLVMValueRef indir_index,
2815 unsigned const_index,
2816 unsigned location,
2817 unsigned driver_location,
2818 unsigned component,
2819 unsigned num_components,
2820 bool is_patch,
2821 bool is_compact)
2822 {
2823 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2824 LLVMValueRef dw_addr, stride;
2825 LLVMValueRef value[4], result;
2826 unsigned param = shader_io_get_unique_index(location);
2827
2828 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2829 dw_addr = get_tcs_in_current_patch_offset(ctx);
2830 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2831 indir_index);
2832
2833 for (unsigned i = 0; i < num_components + component; i++) {
2834 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2835 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2836 ctx->ac.i32_1, "");
2837 }
2838 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2839 return result;
2840 }
2841
2842 static LLVMValueRef
2843 load_tcs_output(struct nir_to_llvm_context *ctx,
2844 nir_intrinsic_instr *instr)
2845 {
2846 LLVMValueRef dw_addr;
2847 LLVMValueRef stride = NULL;
2848 LLVMValueRef value[4], result;
2849 LLVMValueRef vertex_index = NULL;
2850 LLVMValueRef indir_index = NULL;
2851 unsigned const_index = 0;
2852 unsigned param;
2853 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2854 const bool is_compact = instr->variables[0]->var->data.compact;
2855 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2856 get_deref_offset(ctx->nir, instr->variables[0],
2857 false, NULL, per_vertex ? &vertex_index : NULL,
2858 &const_index, &indir_index);
2859
2860 if (!instr->variables[0]->var->data.patch) {
2861 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2862 dw_addr = get_tcs_out_current_patch_offset(ctx);
2863 } else {
2864 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2865 }
2866
2867 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2868 indir_index);
2869
2870 unsigned comp = instr->variables[0]->var->data.location_frac;
2871 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2872 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2873 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2874 ctx->ac.i32_1, "");
2875 }
2876 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2877 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2878 return result;
2879 }
2880
2881 static void
2882 store_tcs_output(struct ac_shader_abi *abi,
2883 LLVMValueRef vertex_index,
2884 LLVMValueRef param_index,
2885 unsigned const_index,
2886 unsigned location,
2887 unsigned driver_location,
2888 LLVMValueRef src,
2889 unsigned component,
2890 bool is_patch,
2891 bool is_compact,
2892 unsigned writemask)
2893 {
2894 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2895 LLVMValueRef dw_addr;
2896 LLVMValueRef stride = NULL;
2897 LLVMValueRef buf_addr = NULL;
2898 unsigned param;
2899 bool store_lds = true;
2900
2901 if (is_patch) {
2902 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2903 store_lds = false;
2904 } else {
2905 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2906 store_lds = false;
2907 }
2908
2909 param = shader_io_get_unique_index(location);
2910 if (location == VARYING_SLOT_CLIP_DIST0 &&
2911 is_compact && const_index > 3) {
2912 const_index -= 3;
2913 param++;
2914 }
2915
2916 if (!is_patch) {
2917 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2918 dw_addr = get_tcs_out_current_patch_offset(ctx);
2919 } else {
2920 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2921 }
2922
2923 mark_tess_output(ctx, is_patch, param);
2924
2925 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2926 param_index);
2927 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2928 vertex_index, param_index);
2929
2930 bool is_tess_factor = false;
2931 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2932 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2933 is_tess_factor = true;
2934
2935 unsigned base = is_compact ? const_index : 0;
2936 for (unsigned chan = 0; chan < 8; chan++) {
2937 if (!(writemask & (1 << chan)))
2938 continue;
2939 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2940
2941 if (store_lds || is_tess_factor)
2942 ac_lds_store(&ctx->ac, dw_addr, value);
2943
2944 if (!is_tess_factor && writemask != 0xF)
2945 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2946 buf_addr, ctx->oc_lds,
2947 4 * (base + chan), 1, 0, true, false);
2948
2949 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2950 ctx->ac.i32_1, "");
2951 }
2952
2953 if (writemask == 0xF) {
2954 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2955 buf_addr, ctx->oc_lds,
2956 (base * 4), 1, 0, true, false);
2957 }
2958 }
2959
2960 static LLVMValueRef
2961 load_tes_input(struct ac_shader_abi *abi,
2962 LLVMValueRef vertex_index,
2963 LLVMValueRef param_index,
2964 unsigned const_index,
2965 unsigned location,
2966 unsigned driver_location,
2967 unsigned component,
2968 unsigned num_components,
2969 bool is_patch,
2970 bool is_compact)
2971 {
2972 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2973 LLVMValueRef buf_addr;
2974 LLVMValueRef result;
2975 unsigned param = shader_io_get_unique_index(location);
2976
2977 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2978 const_index -= 3;
2979 param++;
2980 }
2981
2982 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2983 is_compact, vertex_index, param_index);
2984
2985 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
2986 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2987
2988 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
2989 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2990 result = trim_vector(&ctx->ac, result, num_components);
2991 return result;
2992 }
2993
2994 static LLVMValueRef
2995 load_gs_input(struct ac_shader_abi *abi,
2996 unsigned location,
2997 unsigned driver_location,
2998 unsigned component,
2999 unsigned num_components,
3000 unsigned vertex_index,
3001 unsigned const_index,
3002 LLVMTypeRef type)
3003 {
3004 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3005 LLVMValueRef vtx_offset;
3006 LLVMValueRef args[9];
3007 unsigned param, vtx_offset_param;
3008 LLVMValueRef value[4], result;
3009
3010 vtx_offset_param = vertex_index;
3011 assert(vtx_offset_param < 6);
3012 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3013 LLVMConstInt(ctx->ac.i32, 4, false), "");
3014
3015 param = shader_io_get_unique_index(location);
3016
3017 for (unsigned i = component; i < num_components + component; i++) {
3018 if (ctx->ac.chip_class >= GFX9) {
3019 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3020 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3021 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3022 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3023 } else {
3024 args[0] = ctx->esgs_ring;
3025 args[1] = vtx_offset;
3026 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3027 args[3] = ctx->ac.i32_0;
3028 args[4] = ctx->ac.i32_1; /* OFFEN */
3029 args[5] = ctx->ac.i32_0; /* IDXEN */
3030 args[6] = ctx->ac.i32_1; /* GLC */
3031 args[7] = ctx->ac.i32_0; /* SLC */
3032 args[8] = ctx->ac.i32_0; /* TFE */
3033
3034 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3035 ctx->ac.i32, args, 9,
3036 AC_FUNC_ATTR_READONLY |
3037 AC_FUNC_ATTR_LEGACY);
3038 }
3039 }
3040 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3041
3042 return result;
3043 }
3044
3045 static LLVMValueRef
3046 build_gep_for_deref(struct ac_nir_context *ctx,
3047 nir_deref_var *deref)
3048 {
3049 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3050 assert(entry->data);
3051 LLVMValueRef val = entry->data;
3052 nir_deref *tail = deref->deref.child;
3053 while (tail != NULL) {
3054 LLVMValueRef offset;
3055 switch (tail->deref_type) {
3056 case nir_deref_type_array: {
3057 nir_deref_array *array = nir_deref_as_array(tail);
3058 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3059 if (array->deref_array_type ==
3060 nir_deref_array_type_indirect) {
3061 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3062 get_src(ctx,
3063 array->indirect),
3064 "");
3065 }
3066 break;
3067 }
3068 case nir_deref_type_struct: {
3069 nir_deref_struct *deref_struct =
3070 nir_deref_as_struct(tail);
3071 offset = LLVMConstInt(ctx->ac.i32,
3072 deref_struct->index, 0);
3073 break;
3074 }
3075 default:
3076 unreachable("bad deref type");
3077 }
3078 val = ac_build_gep0(&ctx->ac, val, offset);
3079 tail = tail->child;
3080 }
3081 return val;
3082 }
3083
3084 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3085 nir_intrinsic_instr *instr)
3086 {
3087 LLVMValueRef values[8];
3088 int idx = instr->variables[0]->var->data.driver_location;
3089 int ve = instr->dest.ssa.num_components;
3090 unsigned comp = instr->variables[0]->var->data.location_frac;
3091 LLVMValueRef indir_index;
3092 LLVMValueRef ret;
3093 unsigned const_index;
3094 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3095 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3096 instr->variables[0]->var->data.mode == nir_var_shader_in;
3097 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3098 &const_index, &indir_index);
3099
3100 if (instr->dest.ssa.bit_size == 64)
3101 ve *= 2;
3102
3103 switch (instr->variables[0]->var->data.mode) {
3104 case nir_var_shader_in:
3105 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3106 ctx->stage == MESA_SHADER_TESS_EVAL) {
3107 LLVMValueRef result;
3108 LLVMValueRef vertex_index = NULL;
3109 LLVMValueRef indir_index = NULL;
3110 unsigned const_index = 0;
3111 unsigned location = instr->variables[0]->var->data.location;
3112 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3113 const bool is_patch = instr->variables[0]->var->data.patch;
3114 const bool is_compact = instr->variables[0]->var->data.compact;
3115
3116 get_deref_offset(ctx, instr->variables[0],
3117 false, NULL, is_patch ? NULL : &vertex_index,
3118 &const_index, &indir_index);
3119
3120 result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, indir_index,
3121 const_index, location, driver_location,
3122 instr->variables[0]->var->data.location_frac,
3123 instr->num_components,
3124 is_patch, is_compact);
3125 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3126 }
3127
3128 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3129 LLVMValueRef indir_index;
3130 unsigned const_index, vertex_index;
3131 get_deref_offset(ctx, instr->variables[0],
3132 false, &vertex_index, NULL,
3133 &const_index, &indir_index);
3134 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3135 instr->variables[0]->var->data.driver_location,
3136 instr->variables[0]->var->data.location_frac, ve,
3137 vertex_index, const_index,
3138 nir2llvmtype(ctx, instr->variables[0]->var->type));
3139 }
3140
3141 for (unsigned chan = comp; chan < ve + comp; chan++) {
3142 if (indir_index) {
3143 unsigned count = glsl_count_attribute_slots(
3144 instr->variables[0]->var->type,
3145 ctx->stage == MESA_SHADER_VERTEX);
3146 count -= chan / 4;
3147 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3148 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3149 stride, false, true);
3150
3151 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3152 tmp_vec,
3153 indir_index, "");
3154 } else
3155 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3156 }
3157 break;
3158 case nir_var_local:
3159 for (unsigned chan = 0; chan < ve; chan++) {
3160 if (indir_index) {
3161 unsigned count = glsl_count_attribute_slots(
3162 instr->variables[0]->var->type, false);
3163 count -= chan / 4;
3164 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3165 &ctx->ac, ctx->locals + idx + chan, count,
3166 stride, true, true);
3167
3168 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3169 tmp_vec,
3170 indir_index, "");
3171 } else {
3172 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3173 }
3174 }
3175 break;
3176 case nir_var_shared: {
3177 LLVMValueRef address = build_gep_for_deref(ctx,
3178 instr->variables[0]);
3179 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3180 return LLVMBuildBitCast(ctx->ac.builder, val,
3181 get_def_type(ctx, &instr->dest.ssa),
3182 "");
3183 }
3184 case nir_var_shader_out:
3185 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3186 return load_tcs_output(ctx->nctx, instr);
3187
3188 for (unsigned chan = comp; chan < ve + comp; chan++) {
3189 if (indir_index) {
3190 unsigned count = glsl_count_attribute_slots(
3191 instr->variables[0]->var->type, false);
3192 count -= chan / 4;
3193 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3194 &ctx->ac, ctx->outputs + idx + chan, count,
3195 stride, true, true);
3196
3197 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3198 tmp_vec,
3199 indir_index, "");
3200 } else {
3201 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3202 ctx->outputs[idx + chan + const_index * stride],
3203 "");
3204 }
3205 }
3206 break;
3207 default:
3208 unreachable("unhandle variable mode");
3209 }
3210 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3211 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3212 }
3213
3214 static void
3215 visit_store_var(struct ac_nir_context *ctx,
3216 nir_intrinsic_instr *instr)
3217 {
3218 LLVMValueRef temp_ptr, value;
3219 int idx = instr->variables[0]->var->data.driver_location;
3220 unsigned comp = instr->variables[0]->var->data.location_frac;
3221 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3222 int writemask = instr->const_index[0] << comp;
3223 LLVMValueRef indir_index;
3224 unsigned const_index;
3225 get_deref_offset(ctx, instr->variables[0], false,
3226 NULL, NULL, &const_index, &indir_index);
3227
3228 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3229 int old_writemask = writemask;
3230
3231 src = LLVMBuildBitCast(ctx->ac.builder, src,
3232 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3233 "");
3234
3235 writemask = 0;
3236 for (unsigned chan = 0; chan < 4; chan++) {
3237 if (old_writemask & (1 << chan))
3238 writemask |= 3u << (2 * chan);
3239 }
3240 }
3241
3242 switch (instr->variables[0]->var->data.mode) {
3243 case nir_var_shader_out:
3244
3245 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3246 LLVMValueRef vertex_index = NULL;
3247 LLVMValueRef indir_index = NULL;
3248 unsigned const_index = 0;
3249 const unsigned location = instr->variables[0]->var->data.location;
3250 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3251 const unsigned comp = instr->variables[0]->var->data.location_frac;
3252 const bool is_patch = instr->variables[0]->var->data.patch;
3253 const bool is_compact = instr->variables[0]->var->data.compact;
3254
3255 get_deref_offset(ctx, instr->variables[0],
3256 false, NULL, is_patch ? NULL : &vertex_index,
3257 &const_index, &indir_index);
3258
3259 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3260 const_index, location, driver_location,
3261 src, comp, is_patch, is_compact, writemask);
3262 return;
3263 }
3264
3265 for (unsigned chan = 0; chan < 8; chan++) {
3266 int stride = 4;
3267 if (!(writemask & (1 << chan)))
3268 continue;
3269
3270 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3271
3272 if (instr->variables[0]->var->data.compact)
3273 stride = 1;
3274 if (indir_index) {
3275 unsigned count = glsl_count_attribute_slots(
3276 instr->variables[0]->var->type, false);
3277 count -= chan / 4;
3278 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3279 &ctx->ac, ctx->outputs + idx + chan, count,
3280 stride, true, true);
3281
3282 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3283 value, indir_index, "");
3284 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3285 count, stride, tmp_vec);
3286
3287 } else {
3288 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3289
3290 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3291 }
3292 }
3293 break;
3294 case nir_var_local:
3295 for (unsigned chan = 0; chan < 8; chan++) {
3296 if (!(writemask & (1 << chan)))
3297 continue;
3298
3299 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3300 if (indir_index) {
3301 unsigned count = glsl_count_attribute_slots(
3302 instr->variables[0]->var->type, false);
3303 count -= chan / 4;
3304 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3305 &ctx->ac, ctx->locals + idx + chan, count,
3306 4, true, true);
3307
3308 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3309 value, indir_index, "");
3310 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3311 count, 4, tmp_vec);
3312 } else {
3313 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3314
3315 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3316 }
3317 }
3318 break;
3319 case nir_var_shared: {
3320 int writemask = instr->const_index[0];
3321 LLVMValueRef address = build_gep_for_deref(ctx,
3322 instr->variables[0]);
3323 LLVMValueRef val = get_src(ctx, instr->src[0]);
3324 unsigned components =
3325 glsl_get_vector_elements(
3326 nir_deref_tail(&instr->variables[0]->deref)->type);
3327 if (writemask == (1 << components) - 1) {
3328 val = LLVMBuildBitCast(
3329 ctx->ac.builder, val,
3330 LLVMGetElementType(LLVMTypeOf(address)), "");
3331 LLVMBuildStore(ctx->ac.builder, val, address);
3332 } else {
3333 for (unsigned chan = 0; chan < 4; chan++) {
3334 if (!(writemask & (1 << chan)))
3335 continue;
3336 LLVMValueRef ptr =
3337 LLVMBuildStructGEP(ctx->ac.builder,
3338 address, chan, "");
3339 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3340 chan);
3341 src = LLVMBuildBitCast(
3342 ctx->ac.builder, src,
3343 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3344 LLVMBuildStore(ctx->ac.builder, src, ptr);
3345 }
3346 }
3347 break;
3348 }
3349 default:
3350 break;
3351 }
3352 }
3353
3354 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3355 {
3356 switch (dim) {
3357 case GLSL_SAMPLER_DIM_BUF:
3358 return 1;
3359 case GLSL_SAMPLER_DIM_1D:
3360 return array ? 2 : 1;
3361 case GLSL_SAMPLER_DIM_2D:
3362 return array ? 3 : 2;
3363 case GLSL_SAMPLER_DIM_MS:
3364 return array ? 4 : 3;
3365 case GLSL_SAMPLER_DIM_3D:
3366 case GLSL_SAMPLER_DIM_CUBE:
3367 return 3;
3368 case GLSL_SAMPLER_DIM_RECT:
3369 case GLSL_SAMPLER_DIM_SUBPASS:
3370 return 2;
3371 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3372 return 3;
3373 default:
3374 break;
3375 }
3376 return 0;
3377 }
3378
3379
3380
3381 /* Adjust the sample index according to FMASK.
3382 *
3383 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3384 * which is the identity mapping. Each nibble says which physical sample
3385 * should be fetched to get that sample.
3386 *
3387 * For example, 0x11111100 means there are only 2 samples stored and
3388 * the second sample covers 3/4 of the pixel. When reading samples 0
3389 * and 1, return physical sample 0 (determined by the first two 0s
3390 * in FMASK), otherwise return physical sample 1.
3391 *
3392 * The sample index should be adjusted as follows:
3393 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3394 */
3395 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3396 LLVMValueRef coord_x, LLVMValueRef coord_y,
3397 LLVMValueRef coord_z,
3398 LLVMValueRef sample_index,
3399 LLVMValueRef fmask_desc_ptr)
3400 {
3401 LLVMValueRef fmask_load_address[4];
3402 LLVMValueRef res;
3403
3404 fmask_load_address[0] = coord_x;
3405 fmask_load_address[1] = coord_y;
3406 if (coord_z) {
3407 fmask_load_address[2] = coord_z;
3408 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3409 }
3410
3411 struct ac_image_args args = {0};
3412
3413 args.opcode = ac_image_load;
3414 args.da = coord_z ? true : false;
3415 args.resource = fmask_desc_ptr;
3416 args.dmask = 0xf;
3417 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3418
3419 res = ac_build_image_opcode(ctx, &args);
3420
3421 res = ac_to_integer(ctx, res);
3422 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3423 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3424
3425 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3426 res,
3427 ctx->i32_0, "");
3428
3429 LLVMValueRef sample_index4 =
3430 LLVMBuildMul(ctx->builder, sample_index, four, "");
3431 LLVMValueRef shifted_fmask =
3432 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3433 LLVMValueRef final_sample =
3434 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3435
3436 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3437 * resource descriptor is 0 (invalid),
3438 */
3439 LLVMValueRef fmask_desc =
3440 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3441 ctx->v8i32, "");
3442
3443 LLVMValueRef fmask_word1 =
3444 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3445 ctx->i32_1, "");
3446
3447 LLVMValueRef word1_is_nonzero =
3448 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3449 fmask_word1, ctx->i32_0, "");
3450
3451 /* Replace the MSAA sample index. */
3452 sample_index =
3453 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3454 final_sample, sample_index, "");
3455 return sample_index;
3456 }
3457
3458 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3459 const nir_intrinsic_instr *instr)
3460 {
3461 const struct glsl_type *type = instr->variables[0]->var->type;
3462 if(instr->variables[0]->deref.child)
3463 type = instr->variables[0]->deref.child->type;
3464
3465 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3466 LLVMValueRef coords[4];
3467 LLVMValueRef masks[] = {
3468 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3469 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3470 };
3471 LLVMValueRef res;
3472 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3473
3474 int count;
3475 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3476 bool is_array = glsl_sampler_type_is_array(type);
3477 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3478 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3479 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3480 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3481 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3482 count = image_type_to_components_count(dim, is_array);
3483
3484 if (is_ms) {
3485 LLVMValueRef fmask_load_address[3];
3486 int chan;
3487
3488 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3489 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3490 if (is_array)
3491 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3492 else
3493 fmask_load_address[2] = NULL;
3494 if (add_frag_pos) {
3495 for (chan = 0; chan < 2; ++chan)
3496 fmask_load_address[chan] =
3497 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3498 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3499 ctx->ac.i32, ""), "");
3500 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3501 }
3502 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3503 fmask_load_address[0],
3504 fmask_load_address[1],
3505 fmask_load_address[2],
3506 sample_index,
3507 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3508 }
3509 if (count == 1 && !gfx9_1d) {
3510 if (instr->src[0].ssa->num_components)
3511 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3512 else
3513 res = src0;
3514 } else {
3515 int chan;
3516 if (is_ms)
3517 count--;
3518 for (chan = 0; chan < count; ++chan) {
3519 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3520 }
3521 if (add_frag_pos) {
3522 for (chan = 0; chan < 2; ++chan)
3523 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3524 ctx->ac.i32, ""), "");
3525 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3526 count++;
3527 }
3528
3529 if (gfx9_1d) {
3530 if (is_array) {
3531 coords[2] = coords[1];
3532 coords[1] = ctx->ac.i32_0;
3533 } else
3534 coords[1] = ctx->ac.i32_0;
3535 count++;
3536 }
3537
3538 if (is_ms) {
3539 coords[count] = sample_index;
3540 count++;
3541 }
3542
3543 if (count == 3) {
3544 coords[3] = LLVMGetUndef(ctx->ac.i32);
3545 count = 4;
3546 }
3547 res = ac_build_gather_values(&ctx->ac, coords, count);
3548 }
3549 return res;
3550 }
3551
3552 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3553 const nir_intrinsic_instr *instr)
3554 {
3555 LLVMValueRef params[7];
3556 LLVMValueRef res;
3557 char intrinsic_name[64];
3558 const nir_variable *var = instr->variables[0]->var;
3559 const struct glsl_type *type = var->type;
3560
3561 if(instr->variables[0]->deref.child)
3562 type = instr->variables[0]->deref.child->type;
3563
3564 type = glsl_without_array(type);
3565 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3566 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3567 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3568 ctx->ac.i32_0, ""); /* vindex */
3569 params[2] = ctx->ac.i32_0; /* voffset */
3570 params[3] = ctx->ac.i1false; /* glc */
3571 params[4] = ctx->ac.i1false; /* slc */
3572 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3573 params, 5, 0);
3574
3575 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3576 res = ac_to_integer(&ctx->ac, res);
3577 } else {
3578 bool is_da = glsl_sampler_type_is_array(type) ||
3579 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3580 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3581 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3582 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3583 LLVMValueRef glc = ctx->ac.i1false;
3584 LLVMValueRef slc = ctx->ac.i1false;
3585
3586 params[0] = get_image_coords(ctx, instr);
3587 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3588 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3589 if (HAVE_LLVM <= 0x0309) {
3590 params[3] = ctx->ac.i1false; /* r128 */
3591 params[4] = da;
3592 params[5] = glc;
3593 params[6] = slc;
3594 } else {
3595 LLVMValueRef lwe = ctx->ac.i1false;
3596 params[3] = glc;
3597 params[4] = slc;
3598 params[5] = lwe;
3599 params[6] = da;
3600 }
3601
3602 ac_get_image_intr_name("llvm.amdgcn.image.load",
3603 ctx->ac.v4f32, /* vdata */
3604 LLVMTypeOf(params[0]), /* coords */
3605 LLVMTypeOf(params[1]), /* rsrc */
3606 intrinsic_name, sizeof(intrinsic_name));
3607
3608 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3609 params, 7, AC_FUNC_ATTR_READONLY);
3610 }
3611 return ac_to_integer(&ctx->ac, res);
3612 }
3613
3614 static void visit_image_store(struct ac_nir_context *ctx,
3615 nir_intrinsic_instr *instr)
3616 {
3617 LLVMValueRef params[8];
3618 char intrinsic_name[64];
3619 const nir_variable *var = instr->variables[0]->var;
3620 const struct glsl_type *type = glsl_without_array(var->type);
3621 LLVMValueRef glc = ctx->ac.i1false;
3622 bool force_glc = ctx->ac.chip_class == SI;
3623 if (force_glc)
3624 glc = ctx->ac.i1true;
3625
3626 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3627 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3628 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3629 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3630 ctx->ac.i32_0, ""); /* vindex */
3631 params[3] = ctx->ac.i32_0; /* voffset */
3632 params[4] = glc; /* glc */
3633 params[5] = ctx->ac.i1false; /* slc */
3634 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3635 params, 6, 0);
3636 } else {
3637 bool is_da = glsl_sampler_type_is_array(type) ||
3638 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3639 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3640 LLVMValueRef slc = ctx->ac.i1false;
3641
3642 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3643 params[1] = get_image_coords(ctx, instr); /* coords */
3644 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3645 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3646 if (HAVE_LLVM <= 0x0309) {
3647 params[4] = ctx->ac.i1false; /* r128 */
3648 params[5] = da;
3649 params[6] = glc;
3650 params[7] = slc;
3651 } else {
3652 LLVMValueRef lwe = ctx->ac.i1false;
3653 params[4] = glc;
3654 params[5] = slc;
3655 params[6] = lwe;
3656 params[7] = da;
3657 }
3658
3659 ac_get_image_intr_name("llvm.amdgcn.image.store",
3660 LLVMTypeOf(params[0]), /* vdata */
3661 LLVMTypeOf(params[1]), /* coords */
3662 LLVMTypeOf(params[2]), /* rsrc */
3663 intrinsic_name, sizeof(intrinsic_name));
3664
3665 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3666 params, 8, 0);
3667 }
3668
3669 }
3670
3671 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3672 const nir_intrinsic_instr *instr)
3673 {
3674 LLVMValueRef params[7];
3675 int param_count = 0;
3676 const nir_variable *var = instr->variables[0]->var;
3677
3678 const char *atomic_name;
3679 char intrinsic_name[41];
3680 const struct glsl_type *type = glsl_without_array(var->type);
3681 MAYBE_UNUSED int length;
3682
3683 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3684
3685 switch (instr->intrinsic) {
3686 case nir_intrinsic_image_atomic_add:
3687 atomic_name = "add";
3688 break;
3689 case nir_intrinsic_image_atomic_min:
3690 atomic_name = is_unsigned ? "umin" : "smin";
3691 break;
3692 case nir_intrinsic_image_atomic_max:
3693 atomic_name = is_unsigned ? "umax" : "smax";
3694 break;
3695 case nir_intrinsic_image_atomic_and:
3696 atomic_name = "and";
3697 break;
3698 case nir_intrinsic_image_atomic_or:
3699 atomic_name = "or";
3700 break;
3701 case nir_intrinsic_image_atomic_xor:
3702 atomic_name = "xor";
3703 break;
3704 case nir_intrinsic_image_atomic_exchange:
3705 atomic_name = "swap";
3706 break;
3707 case nir_intrinsic_image_atomic_comp_swap:
3708 atomic_name = "cmpswap";
3709 break;
3710 default:
3711 abort();
3712 }
3713
3714 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3715 params[param_count++] = get_src(ctx, instr->src[3]);
3716 params[param_count++] = get_src(ctx, instr->src[2]);
3717
3718 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3719 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3720 NULL, true, true);
3721 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3722 ctx->ac.i32_0, ""); /* vindex */
3723 params[param_count++] = ctx->ac.i32_0; /* voffset */
3724 params[param_count++] = ctx->ac.i1false; /* slc */
3725
3726 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3727 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3728 } else {
3729 char coords_type[8];
3730
3731 bool da = glsl_sampler_type_is_array(type) ||
3732 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3733
3734 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3735 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3736 NULL, true, true);
3737 params[param_count++] = ctx->ac.i1false; /* r128 */
3738 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3739 params[param_count++] = ctx->ac.i1false; /* slc */
3740
3741 build_int_type_name(LLVMTypeOf(coords),
3742 coords_type, sizeof(coords_type));
3743
3744 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3745 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3746 }
3747
3748 assert(length < sizeof(intrinsic_name));
3749 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3750 }
3751
3752 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3753 const nir_intrinsic_instr *instr)
3754 {
3755 LLVMValueRef res;
3756 const nir_variable *var = instr->variables[0]->var;
3757 const struct glsl_type *type = instr->variables[0]->var->type;
3758 bool da = glsl_sampler_type_is_array(var->type) ||
3759 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3760 if(instr->variables[0]->deref.child)
3761 type = instr->variables[0]->deref.child->type;
3762
3763 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3764 return get_buffer_size(ctx,
3765 get_sampler_desc(ctx, instr->variables[0],
3766 AC_DESC_BUFFER, NULL, true, false), true);
3767
3768 struct ac_image_args args = { 0 };
3769
3770 args.da = da;
3771 args.dmask = 0xf;
3772 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3773 args.opcode = ac_image_get_resinfo;
3774 args.addr = ctx->ac.i32_0;
3775
3776 res = ac_build_image_opcode(&ctx->ac, &args);
3777
3778 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3779
3780 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3781 glsl_sampler_type_is_array(type)) {
3782 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3783 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3784 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3785 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3786 }
3787 if (ctx->ac.chip_class >= GFX9 &&
3788 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3789 glsl_sampler_type_is_array(type)) {
3790 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3791 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3792 ctx->ac.i32_1, "");
3793
3794 }
3795 return res;
3796 }
3797
3798 #define NOOP_WAITCNT 0xf7f
3799 #define LGKM_CNT 0x07f
3800 #define VM_CNT 0xf70
3801
3802 static void emit_membar(struct nir_to_llvm_context *ctx,
3803 const nir_intrinsic_instr *instr)
3804 {
3805 unsigned waitcnt = NOOP_WAITCNT;
3806
3807 switch (instr->intrinsic) {
3808 case nir_intrinsic_memory_barrier:
3809 case nir_intrinsic_group_memory_barrier:
3810 waitcnt &= VM_CNT & LGKM_CNT;
3811 break;
3812 case nir_intrinsic_memory_barrier_atomic_counter:
3813 case nir_intrinsic_memory_barrier_buffer:
3814 case nir_intrinsic_memory_barrier_image:
3815 waitcnt &= VM_CNT;
3816 break;
3817 case nir_intrinsic_memory_barrier_shared:
3818 waitcnt &= LGKM_CNT;
3819 break;
3820 default:
3821 break;
3822 }
3823 if (waitcnt != NOOP_WAITCNT)
3824 ac_build_waitcnt(&ctx->ac, waitcnt);
3825 }
3826
3827 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3828 {
3829 /* SI only (thanks to a hw bug workaround):
3830 * The real barrier instruction isn’t needed, because an entire patch
3831 * always fits into a single wave.
3832 */
3833 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3834 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3835 return;
3836 }
3837 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3838 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3839 }
3840
3841 static void emit_discard_if(struct ac_nir_context *ctx,
3842 const nir_intrinsic_instr *instr)
3843 {
3844 LLVMValueRef cond;
3845
3846 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3847 get_src(ctx, instr->src[0]),
3848 ctx->ac.i32_0, "");
3849 ac_build_kill_if_false(&ctx->ac, cond);
3850 }
3851
3852 static LLVMValueRef
3853 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3854 {
3855 LLVMValueRef result;
3856 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3857 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3858 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3859
3860 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3861 }
3862
3863 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3864 const nir_intrinsic_instr *instr)
3865 {
3866 LLVMValueRef ptr, result;
3867 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3868 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3869
3870 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3871 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3872 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3873 ptr, src, src1,
3874 LLVMAtomicOrderingSequentiallyConsistent,
3875 LLVMAtomicOrderingSequentiallyConsistent,
3876 false);
3877 } else {
3878 LLVMAtomicRMWBinOp op;
3879 switch (instr->intrinsic) {
3880 case nir_intrinsic_var_atomic_add:
3881 op = LLVMAtomicRMWBinOpAdd;
3882 break;
3883 case nir_intrinsic_var_atomic_umin:
3884 op = LLVMAtomicRMWBinOpUMin;
3885 break;
3886 case nir_intrinsic_var_atomic_umax:
3887 op = LLVMAtomicRMWBinOpUMax;
3888 break;
3889 case nir_intrinsic_var_atomic_imin:
3890 op = LLVMAtomicRMWBinOpMin;
3891 break;
3892 case nir_intrinsic_var_atomic_imax:
3893 op = LLVMAtomicRMWBinOpMax;
3894 break;
3895 case nir_intrinsic_var_atomic_and:
3896 op = LLVMAtomicRMWBinOpAnd;
3897 break;
3898 case nir_intrinsic_var_atomic_or:
3899 op = LLVMAtomicRMWBinOpOr;
3900 break;
3901 case nir_intrinsic_var_atomic_xor:
3902 op = LLVMAtomicRMWBinOpXor;
3903 break;
3904 case nir_intrinsic_var_atomic_exchange:
3905 op = LLVMAtomicRMWBinOpXchg;
3906 break;
3907 default:
3908 return NULL;
3909 }
3910
3911 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3912 LLVMAtomicOrderingSequentiallyConsistent,
3913 false);
3914 }
3915 return result;
3916 }
3917
3918 #define INTERP_CENTER 0
3919 #define INTERP_CENTROID 1
3920 #define INTERP_SAMPLE 2
3921
3922 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3923 enum glsl_interp_mode interp, unsigned location)
3924 {
3925 switch (interp) {
3926 case INTERP_MODE_FLAT:
3927 default:
3928 return NULL;
3929 case INTERP_MODE_SMOOTH:
3930 case INTERP_MODE_NONE:
3931 if (location == INTERP_CENTER)
3932 return ctx->persp_center;
3933 else if (location == INTERP_CENTROID)
3934 return ctx->persp_centroid;
3935 else if (location == INTERP_SAMPLE)
3936 return ctx->persp_sample;
3937 break;
3938 case INTERP_MODE_NOPERSPECTIVE:
3939 if (location == INTERP_CENTER)
3940 return ctx->linear_center;
3941 else if (location == INTERP_CENTROID)
3942 return ctx->linear_centroid;
3943 else if (location == INTERP_SAMPLE)
3944 return ctx->linear_sample;
3945 break;
3946 }
3947 return NULL;
3948 }
3949
3950 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3951 LLVMValueRef sample_id)
3952 {
3953 LLVMValueRef result;
3954 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3955
3956 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3957 const_array(ctx->ac.v2f32, 64), "");
3958
3959 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3960 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3961
3962 return result;
3963 }
3964
3965 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3966 {
3967 LLVMValueRef values[2];
3968
3969 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3970 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3971 return ac_build_gather_values(&ctx->ac, values, 2);
3972 }
3973
3974 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3975 const nir_intrinsic_instr *instr)
3976 {
3977 LLVMValueRef result[4];
3978 LLVMValueRef interp_param, attr_number;
3979 unsigned location;
3980 unsigned chan;
3981 LLVMValueRef src_c0 = NULL;
3982 LLVMValueRef src_c1 = NULL;
3983 LLVMValueRef src0 = NULL;
3984 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3985 switch (instr->intrinsic) {
3986 case nir_intrinsic_interp_var_at_centroid:
3987 location = INTERP_CENTROID;
3988 break;
3989 case nir_intrinsic_interp_var_at_sample:
3990 case nir_intrinsic_interp_var_at_offset:
3991 location = INTERP_CENTER;
3992 src0 = get_src(ctx->nir, instr->src[0]);
3993 break;
3994 default:
3995 break;
3996 }
3997
3998 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3999 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4000 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4001 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4002 LLVMValueRef sample_position;
4003 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4004
4005 /* fetch sample ID */
4006 sample_position = load_sample_position(ctx, src0);
4007
4008 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4009 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4010 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4011 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4012 }
4013 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4014 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4015
4016 if (location == INTERP_CENTER) {
4017 LLVMValueRef ij_out[2];
4018 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4019
4020 /*
4021 * take the I then J parameters, and the DDX/Y for it, and
4022 * calculate the IJ inputs for the interpolator.
4023 * temp1 = ddx * offset/sample.x + I;
4024 * interp_param.I = ddy * offset/sample.y + temp1;
4025 * temp1 = ddx * offset/sample.x + J;
4026 * interp_param.J = ddy * offset/sample.y + temp1;
4027 */
4028 for (unsigned i = 0; i < 2; i++) {
4029 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4030 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4031 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4032 ddxy_out, ix_ll, "");
4033 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4034 ddxy_out, iy_ll, "");
4035 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4036 interp_param, ix_ll, "");
4037 LLVMValueRef temp1, temp2;
4038
4039 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4040 ctx->ac.f32, "");
4041
4042 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4043 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4044
4045 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4046 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4047
4048 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4049 temp2, ctx->ac.i32, "");
4050 }
4051 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4052
4053 }
4054
4055 for (chan = 0; chan < 4; chan++) {
4056 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4057
4058 if (interp_param) {
4059 interp_param = LLVMBuildBitCast(ctx->builder,
4060 interp_param, ctx->ac.v2f32, "");
4061 LLVMValueRef i = LLVMBuildExtractElement(
4062 ctx->builder, interp_param, ctx->ac.i32_0, "");
4063 LLVMValueRef j = LLVMBuildExtractElement(
4064 ctx->builder, interp_param, ctx->ac.i32_1, "");
4065
4066 result[chan] = ac_build_fs_interp(&ctx->ac,
4067 llvm_chan, attr_number,
4068 ctx->prim_mask, i, j);
4069 } else {
4070 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4071 LLVMConstInt(ctx->ac.i32, 2, false),
4072 llvm_chan, attr_number,
4073 ctx->prim_mask);
4074 }
4075 }
4076 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4077 instr->variables[0]->var->data.location_frac);
4078 }
4079
4080 static void
4081 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4082 {
4083 LLVMValueRef gs_next_vertex;
4084 LLVMValueRef can_emit;
4085 int idx;
4086 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4087
4088 /* Write vertex attribute values to GSVS ring */
4089 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4090 ctx->gs_next_vertex,
4091 "");
4092
4093 /* If this thread has already emitted the declared maximum number of
4094 * vertices, kill it: excessive vertex emissions are not supposed to
4095 * have any effect, and GS threads have no externally observable
4096 * effects other than emitting vertices.
4097 */
4098 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4099 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4100 ac_build_kill_if_false(&ctx->ac, can_emit);
4101
4102 /* loop num outputs */
4103 idx = 0;
4104 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4105 LLVMValueRef *out_ptr = &addrs[i * 4];
4106 int length = 4;
4107 int slot = idx;
4108 int slot_inc = 1;
4109
4110 if (!(ctx->output_mask & (1ull << i)))
4111 continue;
4112
4113 if (i == VARYING_SLOT_CLIP_DIST0) {
4114 /* pack clip and cull into a single set of slots */
4115 length = ctx->num_output_clips + ctx->num_output_culls;
4116 if (length > 4)
4117 slot_inc = 2;
4118 }
4119 for (unsigned j = 0; j < length; j++) {
4120 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4121 out_ptr[j], "");
4122 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4123 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4124 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4125
4126 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4127
4128 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4129 out_val, 1,
4130 voffset, ctx->gs2vs_offset, 0,
4131 1, 1, true, true);
4132 }
4133 idx += slot_inc;
4134 }
4135
4136 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4137 ctx->ac.i32_1, "");
4138 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4139
4140 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4141 }
4142
4143 static void
4144 visit_end_primitive(struct nir_to_llvm_context *ctx,
4145 const nir_intrinsic_instr *instr)
4146 {
4147 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4148 }
4149
4150 static LLVMValueRef
4151 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4152 unsigned num_components)
4153 {
4154 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4155
4156 LLVMValueRef coord[4] = {
4157 ctx->tes_u,
4158 ctx->tes_v,
4159 ctx->ac.f32_0,
4160 ctx->ac.f32_0,
4161 };
4162
4163 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4164 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4165 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4166
4167 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4168 return LLVMBuildBitCast(ctx->builder, result, type, "");
4169 }
4170
4171 static LLVMValueRef
4172 load_patch_vertices_in(struct ac_shader_abi *abi)
4173 {
4174 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4175 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4176 }
4177
4178 static void visit_intrinsic(struct ac_nir_context *ctx,
4179 nir_intrinsic_instr *instr)
4180 {
4181 LLVMValueRef result = NULL;
4182
4183 switch (instr->intrinsic) {
4184 case nir_intrinsic_load_work_group_id: {
4185 LLVMValueRef values[3];
4186
4187 for (int i = 0; i < 3; i++) {
4188 values[i] = ctx->nctx->workgroup_ids[i] ?
4189 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4190 }
4191
4192 result = ac_build_gather_values(&ctx->ac, values, 3);
4193 break;
4194 }
4195 case nir_intrinsic_load_base_vertex: {
4196 result = ctx->abi->base_vertex;
4197 break;
4198 }
4199 case nir_intrinsic_load_vertex_id_zero_base: {
4200 result = ctx->abi->vertex_id;
4201 break;
4202 }
4203 case nir_intrinsic_load_local_invocation_id: {
4204 result = ctx->nctx->local_invocation_ids;
4205 break;
4206 }
4207 case nir_intrinsic_load_base_instance:
4208 result = ctx->abi->start_instance;
4209 break;
4210 case nir_intrinsic_load_draw_id:
4211 result = ctx->abi->draw_id;
4212 break;
4213 case nir_intrinsic_load_view_index:
4214 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4215 break;
4216 case nir_intrinsic_load_invocation_id:
4217 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4218 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4219 else
4220 result = ctx->abi->gs_invocation_id;
4221 break;
4222 case nir_intrinsic_load_primitive_id:
4223 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4224 result = ctx->abi->gs_prim_id;
4225 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4226 result = ctx->abi->tcs_patch_id;
4227 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4228 result = ctx->abi->tes_patch_id;
4229 } else
4230 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4231 break;
4232 case nir_intrinsic_load_sample_id:
4233 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4234 break;
4235 case nir_intrinsic_load_sample_pos:
4236 result = load_sample_pos(ctx);
4237 break;
4238 case nir_intrinsic_load_sample_mask_in:
4239 result = ctx->abi->sample_coverage;
4240 break;
4241 case nir_intrinsic_load_frag_coord: {
4242 LLVMValueRef values[4] = {
4243 ctx->abi->frag_pos[0],
4244 ctx->abi->frag_pos[1],
4245 ctx->abi->frag_pos[2],
4246 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4247 };
4248 result = ac_build_gather_values(&ctx->ac, values, 4);
4249 break;
4250 }
4251 case nir_intrinsic_load_front_face:
4252 result = ctx->abi->front_face;
4253 break;
4254 case nir_intrinsic_load_instance_id:
4255 result = ctx->abi->instance_id;
4256 break;
4257 case nir_intrinsic_load_num_work_groups:
4258 result = ctx->nctx->num_work_groups;
4259 break;
4260 case nir_intrinsic_load_local_invocation_index:
4261 result = visit_load_local_invocation_index(ctx->nctx);
4262 break;
4263 case nir_intrinsic_load_push_constant:
4264 result = visit_load_push_constant(ctx->nctx, instr);
4265 break;
4266 case nir_intrinsic_vulkan_resource_index:
4267 result = visit_vulkan_resource_index(ctx->nctx, instr);
4268 break;
4269 case nir_intrinsic_vulkan_resource_reindex:
4270 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4271 break;
4272 case nir_intrinsic_store_ssbo:
4273 visit_store_ssbo(ctx, instr);
4274 break;
4275 case nir_intrinsic_load_ssbo:
4276 result = visit_load_buffer(ctx, instr);
4277 break;
4278 case nir_intrinsic_ssbo_atomic_add:
4279 case nir_intrinsic_ssbo_atomic_imin:
4280 case nir_intrinsic_ssbo_atomic_umin:
4281 case nir_intrinsic_ssbo_atomic_imax:
4282 case nir_intrinsic_ssbo_atomic_umax:
4283 case nir_intrinsic_ssbo_atomic_and:
4284 case nir_intrinsic_ssbo_atomic_or:
4285 case nir_intrinsic_ssbo_atomic_xor:
4286 case nir_intrinsic_ssbo_atomic_exchange:
4287 case nir_intrinsic_ssbo_atomic_comp_swap:
4288 result = visit_atomic_ssbo(ctx, instr);
4289 break;
4290 case nir_intrinsic_load_ubo:
4291 result = visit_load_ubo_buffer(ctx, instr);
4292 break;
4293 case nir_intrinsic_get_buffer_size:
4294 result = visit_get_buffer_size(ctx, instr);
4295 break;
4296 case nir_intrinsic_load_var:
4297 result = visit_load_var(ctx, instr);
4298 break;
4299 case nir_intrinsic_store_var:
4300 visit_store_var(ctx, instr);
4301 break;
4302 case nir_intrinsic_image_load:
4303 result = visit_image_load(ctx, instr);
4304 break;
4305 case nir_intrinsic_image_store:
4306 visit_image_store(ctx, instr);
4307 break;
4308 case nir_intrinsic_image_atomic_add:
4309 case nir_intrinsic_image_atomic_min:
4310 case nir_intrinsic_image_atomic_max:
4311 case nir_intrinsic_image_atomic_and:
4312 case nir_intrinsic_image_atomic_or:
4313 case nir_intrinsic_image_atomic_xor:
4314 case nir_intrinsic_image_atomic_exchange:
4315 case nir_intrinsic_image_atomic_comp_swap:
4316 result = visit_image_atomic(ctx, instr);
4317 break;
4318 case nir_intrinsic_image_size:
4319 result = visit_image_size(ctx, instr);
4320 break;
4321 case nir_intrinsic_discard:
4322 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4323 LLVMVoidTypeInContext(ctx->ac.context),
4324 NULL, 0, AC_FUNC_ATTR_LEGACY);
4325 break;
4326 case nir_intrinsic_discard_if:
4327 emit_discard_if(ctx, instr);
4328 break;
4329 case nir_intrinsic_memory_barrier:
4330 case nir_intrinsic_group_memory_barrier:
4331 case nir_intrinsic_memory_barrier_atomic_counter:
4332 case nir_intrinsic_memory_barrier_buffer:
4333 case nir_intrinsic_memory_barrier_image:
4334 case nir_intrinsic_memory_barrier_shared:
4335 emit_membar(ctx->nctx, instr);
4336 break;
4337 case nir_intrinsic_barrier:
4338 emit_barrier(&ctx->ac, ctx->stage);
4339 break;
4340 case nir_intrinsic_var_atomic_add:
4341 case nir_intrinsic_var_atomic_imin:
4342 case nir_intrinsic_var_atomic_umin:
4343 case nir_intrinsic_var_atomic_imax:
4344 case nir_intrinsic_var_atomic_umax:
4345 case nir_intrinsic_var_atomic_and:
4346 case nir_intrinsic_var_atomic_or:
4347 case nir_intrinsic_var_atomic_xor:
4348 case nir_intrinsic_var_atomic_exchange:
4349 case nir_intrinsic_var_atomic_comp_swap:
4350 result = visit_var_atomic(ctx->nctx, instr);
4351 break;
4352 case nir_intrinsic_interp_var_at_centroid:
4353 case nir_intrinsic_interp_var_at_sample:
4354 case nir_intrinsic_interp_var_at_offset:
4355 result = visit_interp(ctx->nctx, instr);
4356 break;
4357 case nir_intrinsic_emit_vertex:
4358 assert(instr->const_index[0] == 0);
4359 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4360 break;
4361 case nir_intrinsic_end_primitive:
4362 visit_end_primitive(ctx->nctx, instr);
4363 break;
4364 case nir_intrinsic_load_tess_coord: {
4365 LLVMTypeRef type = ctx->nctx ?
4366 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4367 NULL;
4368 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4369 break;
4370 }
4371 case nir_intrinsic_load_tess_level_outer:
4372 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4373 break;
4374 case nir_intrinsic_load_tess_level_inner:
4375 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4376 break;
4377 case nir_intrinsic_load_patch_vertices_in:
4378 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4379 break;
4380 default:
4381 fprintf(stderr, "Unknown intrinsic: ");
4382 nir_print_instr(&instr->instr, stderr);
4383 fprintf(stderr, "\n");
4384 break;
4385 }
4386 if (result) {
4387 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4388 }
4389 }
4390
4391 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4392 LLVMValueRef buffer_ptr, bool write)
4393 {
4394 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4395
4396 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4397 ctx->shader_info->fs.writes_memory = true;
4398
4399 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4400 }
4401
4402 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4403 {
4404 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4405
4406 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4407 }
4408
4409 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4410 unsigned descriptor_set,
4411 unsigned base_index,
4412 unsigned constant_index,
4413 LLVMValueRef index,
4414 enum ac_descriptor_type desc_type,
4415 bool image, bool write)
4416 {
4417 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4418 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4419 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4420 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4421 unsigned offset = binding->offset;
4422 unsigned stride = binding->size;
4423 unsigned type_size;
4424 LLVMBuilderRef builder = ctx->builder;
4425 LLVMTypeRef type;
4426
4427 assert(base_index < layout->binding_count);
4428
4429 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4430 ctx->shader_info->fs.writes_memory = true;
4431
4432 switch (desc_type) {
4433 case AC_DESC_IMAGE:
4434 type = ctx->ac.v8i32;
4435 type_size = 32;
4436 break;
4437 case AC_DESC_FMASK:
4438 type = ctx->ac.v8i32;
4439 offset += 32;
4440 type_size = 32;
4441 break;
4442 case AC_DESC_SAMPLER:
4443 type = ctx->ac.v4i32;
4444 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4445 offset += 64;
4446
4447 type_size = 16;
4448 break;
4449 case AC_DESC_BUFFER:
4450 type = ctx->ac.v4i32;
4451 type_size = 16;
4452 break;
4453 default:
4454 unreachable("invalid desc_type\n");
4455 }
4456
4457 offset += constant_index * stride;
4458
4459 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4460 (!index || binding->immutable_samplers_equal)) {
4461 if (binding->immutable_samplers_equal)
4462 constant_index = 0;
4463
4464 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4465
4466 LLVMValueRef constants[] = {
4467 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4468 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4469 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4470 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4471 };
4472 return ac_build_gather_values(&ctx->ac, constants, 4);
4473 }
4474
4475 assert(stride % type_size == 0);
4476
4477 if (!index)
4478 index = ctx->ac.i32_0;
4479
4480 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4481
4482 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4483 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4484
4485 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4486 }
4487
4488 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4489 const nir_deref_var *deref,
4490 enum ac_descriptor_type desc_type,
4491 const nir_tex_instr *tex_instr,
4492 bool image, bool write)
4493 {
4494 LLVMValueRef index = NULL;
4495 unsigned constant_index = 0;
4496 unsigned descriptor_set;
4497 unsigned base_index;
4498
4499 if (!deref) {
4500 assert(tex_instr && !image);
4501 descriptor_set = 0;
4502 base_index = tex_instr->sampler_index;
4503 } else {
4504 const nir_deref *tail = &deref->deref;
4505 while (tail->child) {
4506 const nir_deref_array *child = nir_deref_as_array(tail->child);
4507 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4508
4509 if (!array_size)
4510 array_size = 1;
4511
4512 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4513
4514 if (child->deref_array_type == nir_deref_array_type_indirect) {
4515 LLVMValueRef indirect = get_src(ctx, child->indirect);
4516
4517 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4518 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4519
4520 if (!index)
4521 index = indirect;
4522 else
4523 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4524 }
4525
4526 constant_index += child->base_offset * array_size;
4527
4528 tail = &child->deref;
4529 }
4530 descriptor_set = deref->var->data.descriptor_set;
4531 base_index = deref->var->data.binding;
4532 }
4533
4534 return ctx->abi->load_sampler_desc(ctx->abi,
4535 descriptor_set,
4536 base_index,
4537 constant_index, index,
4538 desc_type, image, write);
4539 }
4540
4541 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4542 struct ac_image_args *args,
4543 const nir_tex_instr *instr,
4544 nir_texop op,
4545 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4546 LLVMValueRef *param, unsigned count,
4547 unsigned dmask)
4548 {
4549 unsigned is_rect = 0;
4550 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4551
4552 if (op == nir_texop_lod)
4553 da = false;
4554 /* Pad to power of two vector */
4555 while (count < util_next_power_of_two(count))
4556 param[count++] = LLVMGetUndef(ctx->i32);
4557
4558 if (count > 1)
4559 args->addr = ac_build_gather_values(ctx, param, count);
4560 else
4561 args->addr = param[0];
4562
4563 args->resource = res_ptr;
4564 args->sampler = samp_ptr;
4565
4566 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4567 args->addr = param[0];
4568 return;
4569 }
4570
4571 args->dmask = dmask;
4572 args->unorm = is_rect;
4573 args->da = da;
4574 }
4575
4576 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4577 *
4578 * SI-CI:
4579 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4580 * filtering manually. The driver sets img7 to a mask clearing
4581 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4582 * s_and_b32 samp0, samp0, img7
4583 *
4584 * VI:
4585 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4586 */
4587 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4588 LLVMValueRef res, LLVMValueRef samp)
4589 {
4590 LLVMBuilderRef builder = ctx->ac.builder;
4591 LLVMValueRef img7, samp0;
4592
4593 if (ctx->ac.chip_class >= VI)
4594 return samp;
4595
4596 img7 = LLVMBuildExtractElement(builder, res,
4597 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4598 samp0 = LLVMBuildExtractElement(builder, samp,
4599 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4600 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4601 return LLVMBuildInsertElement(builder, samp, samp0,
4602 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4603 }
4604
4605 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4606 nir_tex_instr *instr,
4607 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4608 LLVMValueRef *fmask_ptr)
4609 {
4610 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4611 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4612 else
4613 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4614 if (samp_ptr) {
4615 if (instr->sampler)
4616 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4617 else
4618 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4619 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4620 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4621 }
4622 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4623 instr->op == nir_texop_samples_identical))
4624 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4625 }
4626
4627 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4628 LLVMValueRef coord)
4629 {
4630 coord = ac_to_float(ctx, coord);
4631 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4632 coord = ac_to_integer(ctx, coord);
4633 return coord;
4634 }
4635
4636 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4637 {
4638 LLVMValueRef result = NULL;
4639 struct ac_image_args args = { 0 };
4640 unsigned dmask = 0xf;
4641 LLVMValueRef address[16];
4642 LLVMValueRef coords[5];
4643 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4644 LLVMValueRef bias = NULL, offsets = NULL;
4645 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4646 LLVMValueRef ddx = NULL, ddy = NULL;
4647 LLVMValueRef derivs[6];
4648 unsigned chan, count = 0;
4649 unsigned const_src = 0, num_deriv_comp = 0;
4650 bool lod_is_zero = false;
4651
4652 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4653
4654 for (unsigned i = 0; i < instr->num_srcs; i++) {
4655 switch (instr->src[i].src_type) {
4656 case nir_tex_src_coord:
4657 coord = get_src(ctx, instr->src[i].src);
4658 break;
4659 case nir_tex_src_projector:
4660 break;
4661 case nir_tex_src_comparator:
4662 comparator = get_src(ctx, instr->src[i].src);
4663 break;
4664 case nir_tex_src_offset:
4665 offsets = get_src(ctx, instr->src[i].src);
4666 const_src = i;
4667 break;
4668 case nir_tex_src_bias:
4669 bias = get_src(ctx, instr->src[i].src);
4670 break;
4671 case nir_tex_src_lod: {
4672 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4673
4674 if (val && val->i32[0] == 0)
4675 lod_is_zero = true;
4676 lod = get_src(ctx, instr->src[i].src);
4677 break;
4678 }
4679 case nir_tex_src_ms_index:
4680 sample_index = get_src(ctx, instr->src[i].src);
4681 break;
4682 case nir_tex_src_ms_mcs:
4683 break;
4684 case nir_tex_src_ddx:
4685 ddx = get_src(ctx, instr->src[i].src);
4686 num_deriv_comp = instr->src[i].src.ssa->num_components;
4687 break;
4688 case nir_tex_src_ddy:
4689 ddy = get_src(ctx, instr->src[i].src);
4690 break;
4691 case nir_tex_src_texture_offset:
4692 case nir_tex_src_sampler_offset:
4693 case nir_tex_src_plane:
4694 default:
4695 break;
4696 }
4697 }
4698
4699 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4700 result = get_buffer_size(ctx, res_ptr, true);
4701 goto write_result;
4702 }
4703
4704 if (instr->op == nir_texop_texture_samples) {
4705 LLVMValueRef res, samples, is_msaa;
4706 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4707 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4708 LLVMConstInt(ctx->ac.i32, 3, false), "");
4709 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4710 LLVMConstInt(ctx->ac.i32, 28, false), "");
4711 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4712 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4713 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4714 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4715
4716 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4717 LLVMConstInt(ctx->ac.i32, 16, false), "");
4718 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4719 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4720 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4721 samples, "");
4722 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4723 ctx->ac.i32_1, "");
4724 result = samples;
4725 goto write_result;
4726 }
4727
4728 if (coord)
4729 for (chan = 0; chan < instr->coord_components; chan++)
4730 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4731
4732 if (offsets && instr->op != nir_texop_txf) {
4733 LLVMValueRef offset[3], pack;
4734 for (chan = 0; chan < 3; ++chan)
4735 offset[chan] = ctx->ac.i32_0;
4736
4737 args.offset = true;
4738 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4739 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4740 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4741 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4742 if (chan)
4743 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4744 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4745 }
4746 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4747 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4748 address[count++] = pack;
4749
4750 }
4751 /* pack LOD bias value */
4752 if (instr->op == nir_texop_txb && bias) {
4753 address[count++] = bias;
4754 }
4755
4756 /* Pack depth comparison value */
4757 if (instr->is_shadow && comparator) {
4758 LLVMValueRef z = ac_to_float(&ctx->ac,
4759 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4760
4761 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4762 * so the depth comparison value isn't clamped for Z16 and
4763 * Z24 anymore. Do it manually here.
4764 *
4765 * It's unnecessary if the original texture format was
4766 * Z32_FLOAT, but we don't know that here.
4767 */
4768 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4769 z = ac_build_clamp(&ctx->ac, z);
4770
4771 address[count++] = z;
4772 }
4773
4774 /* pack derivatives */
4775 if (ddx || ddy) {
4776 int num_src_deriv_channels, num_dest_deriv_channels;
4777 switch (instr->sampler_dim) {
4778 case GLSL_SAMPLER_DIM_3D:
4779 case GLSL_SAMPLER_DIM_CUBE:
4780 num_deriv_comp = 3;
4781 num_src_deriv_channels = 3;
4782 num_dest_deriv_channels = 3;
4783 break;
4784 case GLSL_SAMPLER_DIM_2D:
4785 default:
4786 num_src_deriv_channels = 2;
4787 num_dest_deriv_channels = 2;
4788 num_deriv_comp = 2;
4789 break;
4790 case GLSL_SAMPLER_DIM_1D:
4791 num_src_deriv_channels = 1;
4792 if (ctx->ac.chip_class >= GFX9) {
4793 num_dest_deriv_channels = 2;
4794 num_deriv_comp = 2;
4795 } else {
4796 num_dest_deriv_channels = 1;
4797 num_deriv_comp = 1;
4798 }
4799 break;
4800 }
4801
4802 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4803 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4804 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4805 }
4806 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4807 derivs[i] = ctx->ac.f32_0;
4808 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4809 }
4810 }
4811
4812 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4813 for (chan = 0; chan < instr->coord_components; chan++)
4814 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4815 if (instr->coord_components == 3)
4816 coords[3] = LLVMGetUndef(ctx->ac.f32);
4817 ac_prepare_cube_coords(&ctx->ac,
4818 instr->op == nir_texop_txd, instr->is_array,
4819 instr->op == nir_texop_lod, coords, derivs);
4820 if (num_deriv_comp)
4821 num_deriv_comp--;
4822 }
4823
4824 if (ddx || ddy) {
4825 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4826 address[count++] = derivs[i];
4827 }
4828
4829 /* Pack texture coordinates */
4830 if (coord) {
4831 address[count++] = coords[0];
4832 if (instr->coord_components > 1) {
4833 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4834 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4835 }
4836 address[count++] = coords[1];
4837 }
4838 if (instr->coord_components > 2) {
4839 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4840 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4841 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4842 instr->op != nir_texop_txf) {
4843 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4844 }
4845 address[count++] = coords[2];
4846 }
4847
4848 if (ctx->ac.chip_class >= GFX9) {
4849 LLVMValueRef filler;
4850 if (instr->op == nir_texop_txf)
4851 filler = ctx->ac.i32_0;
4852 else
4853 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4854
4855 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4856 /* No nir_texop_lod, because it does not take a slice
4857 * even with array textures. */
4858 if (instr->is_array && instr->op != nir_texop_lod ) {
4859 address[count] = address[count - 1];
4860 address[count - 1] = filler;
4861 count++;
4862 } else
4863 address[count++] = filler;
4864 }
4865 }
4866 }
4867
4868 /* Pack LOD */
4869 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4870 instr->op == nir_texop_txf)) {
4871 address[count++] = lod;
4872 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4873 address[count++] = sample_index;
4874 } else if(instr->op == nir_texop_txs) {
4875 count = 0;
4876 if (lod)
4877 address[count++] = lod;
4878 else
4879 address[count++] = ctx->ac.i32_0;
4880 }
4881
4882 for (chan = 0; chan < count; chan++) {
4883 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4884 address[chan], ctx->ac.i32, "");
4885 }
4886
4887 if (instr->op == nir_texop_samples_identical) {
4888 LLVMValueRef txf_address[4];
4889 struct ac_image_args txf_args = { 0 };
4890 unsigned txf_count = count;
4891 memcpy(txf_address, address, sizeof(txf_address));
4892
4893 if (!instr->is_array)
4894 txf_address[2] = ctx->ac.i32_0;
4895 txf_address[3] = ctx->ac.i32_0;
4896
4897 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4898 fmask_ptr, NULL,
4899 txf_address, txf_count, 0xf);
4900
4901 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4902
4903 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4904 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4905 goto write_result;
4906 }
4907
4908 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4909 instr->op != nir_texop_txs) {
4910 unsigned sample_chan = instr->is_array ? 3 : 2;
4911 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4912 address[0],
4913 address[1],
4914 instr->is_array ? address[2] : NULL,
4915 address[sample_chan],
4916 fmask_ptr);
4917 }
4918
4919 if (offsets && instr->op == nir_texop_txf) {
4920 nir_const_value *const_offset =
4921 nir_src_as_const_value(instr->src[const_src].src);
4922 int num_offsets = instr->src[const_src].src.ssa->num_components;
4923 assert(const_offset);
4924 num_offsets = MIN2(num_offsets, instr->coord_components);
4925 if (num_offsets > 2)
4926 address[2] = LLVMBuildAdd(ctx->ac.builder,
4927 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4928 if (num_offsets > 1)
4929 address[1] = LLVMBuildAdd(ctx->ac.builder,
4930 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4931 address[0] = LLVMBuildAdd(ctx->ac.builder,
4932 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4933
4934 }
4935
4936 /* TODO TG4 support */
4937 if (instr->op == nir_texop_tg4) {
4938 if (instr->is_shadow)
4939 dmask = 1;
4940 else
4941 dmask = 1 << instr->component;
4942 }
4943 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4944 res_ptr, samp_ptr, address, count, dmask);
4945
4946 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4947
4948 if (instr->op == nir_texop_query_levels)
4949 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4950 else if (instr->is_shadow && instr->is_new_style_shadow &&
4951 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4952 instr->op != nir_texop_tg4)
4953 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4954 else if (instr->op == nir_texop_txs &&
4955 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4956 instr->is_array) {
4957 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4958 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4959 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4960 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4961 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4962 } else if (ctx->ac.chip_class >= GFX9 &&
4963 instr->op == nir_texop_txs &&
4964 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4965 instr->is_array) {
4966 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4967 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4968 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4969 ctx->ac.i32_1, "");
4970 } else if (instr->dest.ssa.num_components != 4)
4971 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4972
4973 write_result:
4974 if (result) {
4975 assert(instr->dest.is_ssa);
4976 result = ac_to_integer(&ctx->ac, result);
4977 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4978 }
4979 }
4980
4981
4982 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4983 {
4984 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4985 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4986
4987 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4988 _mesa_hash_table_insert(ctx->phis, instr, result);
4989 }
4990
4991 static void visit_post_phi(struct ac_nir_context *ctx,
4992 nir_phi_instr *instr,
4993 LLVMValueRef llvm_phi)
4994 {
4995 nir_foreach_phi_src(src, instr) {
4996 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4997 LLVMValueRef llvm_src = get_src(ctx, src->src);
4998
4999 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5000 }
5001 }
5002
5003 static void phi_post_pass(struct ac_nir_context *ctx)
5004 {
5005 struct hash_entry *entry;
5006 hash_table_foreach(ctx->phis, entry) {
5007 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5008 (LLVMValueRef)entry->data);
5009 }
5010 }
5011
5012
5013 static void visit_ssa_undef(struct ac_nir_context *ctx,
5014 const nir_ssa_undef_instr *instr)
5015 {
5016 unsigned num_components = instr->def.num_components;
5017 LLVMValueRef undef;
5018
5019 if (num_components == 1)
5020 undef = LLVMGetUndef(ctx->ac.i32);
5021 else {
5022 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5023 }
5024 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5025 }
5026
5027 static void visit_jump(struct ac_nir_context *ctx,
5028 const nir_jump_instr *instr)
5029 {
5030 switch (instr->type) {
5031 case nir_jump_break:
5032 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5033 LLVMClearInsertionPosition(ctx->ac.builder);
5034 break;
5035 case nir_jump_continue:
5036 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5037 LLVMClearInsertionPosition(ctx->ac.builder);
5038 break;
5039 default:
5040 fprintf(stderr, "Unknown NIR jump instr: ");
5041 nir_print_instr(&instr->instr, stderr);
5042 fprintf(stderr, "\n");
5043 abort();
5044 }
5045 }
5046
5047 static void visit_cf_list(struct ac_nir_context *ctx,
5048 struct exec_list *list);
5049
5050 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5051 {
5052 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5053 nir_foreach_instr(instr, block)
5054 {
5055 switch (instr->type) {
5056 case nir_instr_type_alu:
5057 visit_alu(ctx, nir_instr_as_alu(instr));
5058 break;
5059 case nir_instr_type_load_const:
5060 visit_load_const(ctx, nir_instr_as_load_const(instr));
5061 break;
5062 case nir_instr_type_intrinsic:
5063 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5064 break;
5065 case nir_instr_type_tex:
5066 visit_tex(ctx, nir_instr_as_tex(instr));
5067 break;
5068 case nir_instr_type_phi:
5069 visit_phi(ctx, nir_instr_as_phi(instr));
5070 break;
5071 case nir_instr_type_ssa_undef:
5072 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5073 break;
5074 case nir_instr_type_jump:
5075 visit_jump(ctx, nir_instr_as_jump(instr));
5076 break;
5077 default:
5078 fprintf(stderr, "Unknown NIR instr type: ");
5079 nir_print_instr(instr, stderr);
5080 fprintf(stderr, "\n");
5081 abort();
5082 }
5083 }
5084
5085 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5086 }
5087
5088 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5089 {
5090 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5091
5092 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5093 LLVMBasicBlockRef merge_block =
5094 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5095 LLVMBasicBlockRef if_block =
5096 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5097 LLVMBasicBlockRef else_block = merge_block;
5098 if (!exec_list_is_empty(&if_stmt->else_list))
5099 else_block = LLVMAppendBasicBlockInContext(
5100 ctx->ac.context, fn, "");
5101
5102 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5103 ctx->ac.i32_0, "");
5104 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5105
5106 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5107 visit_cf_list(ctx, &if_stmt->then_list);
5108 if (LLVMGetInsertBlock(ctx->ac.builder))
5109 LLVMBuildBr(ctx->ac.builder, merge_block);
5110
5111 if (!exec_list_is_empty(&if_stmt->else_list)) {
5112 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5113 visit_cf_list(ctx, &if_stmt->else_list);
5114 if (LLVMGetInsertBlock(ctx->ac.builder))
5115 LLVMBuildBr(ctx->ac.builder, merge_block);
5116 }
5117
5118 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5119 }
5120
5121 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5122 {
5123 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5124 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5125 LLVMBasicBlockRef break_parent = ctx->break_block;
5126
5127 ctx->continue_block =
5128 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5129 ctx->break_block =
5130 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5131
5132 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5133 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5134 visit_cf_list(ctx, &loop->body);
5135
5136 if (LLVMGetInsertBlock(ctx->ac.builder))
5137 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5138 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5139
5140 ctx->continue_block = continue_parent;
5141 ctx->break_block = break_parent;
5142 }
5143
5144 static void visit_cf_list(struct ac_nir_context *ctx,
5145 struct exec_list *list)
5146 {
5147 foreach_list_typed(nir_cf_node, node, node, list)
5148 {
5149 switch (node->type) {
5150 case nir_cf_node_block:
5151 visit_block(ctx, nir_cf_node_as_block(node));
5152 break;
5153
5154 case nir_cf_node_if:
5155 visit_if(ctx, nir_cf_node_as_if(node));
5156 break;
5157
5158 case nir_cf_node_loop:
5159 visit_loop(ctx, nir_cf_node_as_loop(node));
5160 break;
5161
5162 default:
5163 assert(0);
5164 }
5165 }
5166 }
5167
5168 static void
5169 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5170 struct nir_variable *variable)
5171 {
5172 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5173 LLVMValueRef t_offset;
5174 LLVMValueRef t_list;
5175 LLVMValueRef input;
5176 LLVMValueRef buffer_index;
5177 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5178 int idx = variable->data.location;
5179 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5180
5181 variable->data.driver_location = idx * 4;
5182
5183 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5184 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5185 ctx->abi.start_instance, "");
5186 if (ctx->options->key.vs.as_ls) {
5187 ctx->shader_info->vs.vgpr_comp_cnt =
5188 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5189 } else {
5190 ctx->shader_info->vs.vgpr_comp_cnt =
5191 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5192 }
5193 } else
5194 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5195 ctx->abi.base_vertex, "");
5196
5197 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5198 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5199
5200 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5201
5202 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5203 buffer_index,
5204 ctx->ac.i32_0,
5205 true);
5206
5207 for (unsigned chan = 0; chan < 4; chan++) {
5208 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5209 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5210 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5211 input, llvm_chan, ""));
5212 }
5213 }
5214 }
5215
5216 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5217 unsigned attr,
5218 LLVMValueRef interp_param,
5219 LLVMValueRef prim_mask,
5220 LLVMValueRef result[4])
5221 {
5222 LLVMValueRef attr_number;
5223 unsigned chan;
5224 LLVMValueRef i, j;
5225 bool interp = interp_param != NULL;
5226
5227 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5228
5229 /* fs.constant returns the param from the middle vertex, so it's not
5230 * really useful for flat shading. It's meant to be used for custom
5231 * interpolation (but the intrinsic can't fetch from the other two
5232 * vertices).
5233 *
5234 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5235 * to do the right thing. The only reason we use fs.constant is that
5236 * fs.interp cannot be used on integers, because they can be equal
5237 * to NaN.
5238 */
5239 if (interp) {
5240 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5241 ctx->ac.v2f32, "");
5242
5243 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5244 ctx->ac.i32_0, "");
5245 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5246 ctx->ac.i32_1, "");
5247 }
5248
5249 for (chan = 0; chan < 4; chan++) {
5250 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5251
5252 if (interp) {
5253 result[chan] = ac_build_fs_interp(&ctx->ac,
5254 llvm_chan,
5255 attr_number,
5256 prim_mask, i, j);
5257 } else {
5258 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5259 LLVMConstInt(ctx->ac.i32, 2, false),
5260 llvm_chan,
5261 attr_number,
5262 prim_mask);
5263 }
5264 }
5265 }
5266
5267 static void
5268 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5269 struct nir_variable *variable)
5270 {
5271 int idx = variable->data.location;
5272 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5273 LLVMValueRef interp;
5274
5275 variable->data.driver_location = idx * 4;
5276 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5277
5278 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5279 unsigned interp_type;
5280 if (variable->data.sample) {
5281 interp_type = INTERP_SAMPLE;
5282 ctx->shader_info->info.ps.force_persample = true;
5283 } else if (variable->data.centroid)
5284 interp_type = INTERP_CENTROID;
5285 else
5286 interp_type = INTERP_CENTER;
5287
5288 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5289 } else
5290 interp = NULL;
5291
5292 for (unsigned i = 0; i < attrib_count; ++i)
5293 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5294
5295 }
5296
5297 static void
5298 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5299 struct nir_shader *nir) {
5300 nir_foreach_variable(variable, &nir->inputs)
5301 handle_vs_input_decl(ctx, variable);
5302 }
5303
5304 static void
5305 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5306 struct nir_shader *nir)
5307 {
5308 if (!ctx->options->key.fs.multisample)
5309 return;
5310
5311 bool uses_center = false;
5312 bool uses_centroid = false;
5313 nir_foreach_variable(variable, &nir->inputs) {
5314 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5315 variable->data.sample)
5316 continue;
5317
5318 if (variable->data.centroid)
5319 uses_centroid = true;
5320 else
5321 uses_center = true;
5322 }
5323
5324 if (uses_center && uses_centroid) {
5325 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5326 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5327 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5328 }
5329 }
5330
5331 static void
5332 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5333 struct nir_shader *nir)
5334 {
5335 prepare_interp_optimize(ctx, nir);
5336
5337 nir_foreach_variable(variable, &nir->inputs)
5338 handle_fs_input_decl(ctx, variable);
5339
5340 unsigned index = 0;
5341
5342 if (ctx->shader_info->info.ps.uses_input_attachments ||
5343 ctx->shader_info->info.needs_multiview_view_index)
5344 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5345
5346 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5347 LLVMValueRef interp_param;
5348 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5349
5350 if (!(ctx->input_mask & (1ull << i)))
5351 continue;
5352
5353 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5354 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5355 interp_param = *inputs;
5356 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5357 inputs);
5358
5359 if (!interp_param)
5360 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5361 ++index;
5362 } else if (i == VARYING_SLOT_POS) {
5363 for(int i = 0; i < 3; ++i)
5364 inputs[i] = ctx->abi.frag_pos[i];
5365
5366 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5367 ctx->abi.frag_pos[3]);
5368 }
5369 }
5370 ctx->shader_info->fs.num_interp = index;
5371 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5372 ctx->shader_info->fs.has_pcoord = true;
5373 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5374 ctx->shader_info->fs.prim_id_input = true;
5375 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5376 ctx->shader_info->fs.layer_input = true;
5377 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5378
5379 if (ctx->shader_info->info.needs_multiview_view_index)
5380 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5381 }
5382
5383 static LLVMValueRef
5384 ac_build_alloca(struct ac_llvm_context *ac,
5385 LLVMTypeRef type,
5386 const char *name)
5387 {
5388 LLVMBuilderRef builder = ac->builder;
5389 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5390 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5391 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5392 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5393 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5394 LLVMValueRef res;
5395
5396 if (first_instr) {
5397 LLVMPositionBuilderBefore(first_builder, first_instr);
5398 } else {
5399 LLVMPositionBuilderAtEnd(first_builder, first_block);
5400 }
5401
5402 res = LLVMBuildAlloca(first_builder, type, name);
5403 LLVMBuildStore(builder, LLVMConstNull(type), res);
5404
5405 LLVMDisposeBuilder(first_builder);
5406
5407 return res;
5408 }
5409
5410 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5411 LLVMTypeRef type,
5412 const char *name)
5413 {
5414 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5415 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5416 return ptr;
5417 }
5418
5419 static void
5420 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5421 struct nir_variable *variable,
5422 struct nir_shader *shader,
5423 gl_shader_stage stage)
5424 {
5425 int idx = variable->data.location + variable->data.index;
5426 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5427 uint64_t mask_attribs;
5428
5429 variable->data.driver_location = idx * 4;
5430
5431 /* tess ctrl has it's own load/store paths for outputs */
5432 if (stage == MESA_SHADER_TESS_CTRL)
5433 return;
5434
5435 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5436 if (stage == MESA_SHADER_VERTEX ||
5437 stage == MESA_SHADER_TESS_EVAL ||
5438 stage == MESA_SHADER_GEOMETRY) {
5439 if (idx == VARYING_SLOT_CLIP_DIST0) {
5440 int length = shader->info.clip_distance_array_size +
5441 shader->info.cull_distance_array_size;
5442 if (stage == MESA_SHADER_VERTEX) {
5443 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5444 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5445 }
5446 if (stage == MESA_SHADER_TESS_EVAL) {
5447 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5448 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5449 }
5450
5451 if (length > 4)
5452 attrib_count = 2;
5453 else
5454 attrib_count = 1;
5455 mask_attribs = 1ull << idx;
5456 }
5457 }
5458
5459 ctx->output_mask |= mask_attribs;
5460 }
5461
5462 static void
5463 handle_shader_output_decl(struct ac_nir_context *ctx,
5464 struct nir_shader *nir,
5465 struct nir_variable *variable)
5466 {
5467 unsigned output_loc = variable->data.driver_location / 4;
5468 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5469
5470 /* tess ctrl has it's own load/store paths for outputs */
5471 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5472 return;
5473
5474 if (ctx->stage == MESA_SHADER_VERTEX ||
5475 ctx->stage == MESA_SHADER_TESS_EVAL ||
5476 ctx->stage == MESA_SHADER_GEOMETRY) {
5477 int idx = variable->data.location + variable->data.index;
5478 if (idx == VARYING_SLOT_CLIP_DIST0) {
5479 int length = nir->info.clip_distance_array_size +
5480 nir->info.cull_distance_array_size;
5481
5482 if (length > 4)
5483 attrib_count = 2;
5484 else
5485 attrib_count = 1;
5486 }
5487 }
5488
5489 for (unsigned i = 0; i < attrib_count; ++i) {
5490 for (unsigned chan = 0; chan < 4; chan++) {
5491 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5492 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5493 }
5494 }
5495 }
5496
5497 static LLVMTypeRef
5498 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5499 enum glsl_base_type type)
5500 {
5501 switch (type) {
5502 case GLSL_TYPE_INT:
5503 case GLSL_TYPE_UINT:
5504 case GLSL_TYPE_BOOL:
5505 case GLSL_TYPE_SUBROUTINE:
5506 return ctx->ac.i32;
5507 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5508 return ctx->ac.f32;
5509 case GLSL_TYPE_INT64:
5510 case GLSL_TYPE_UINT64:
5511 return ctx->ac.i64;
5512 case GLSL_TYPE_DOUBLE:
5513 return ctx->ac.f64;
5514 default:
5515 unreachable("unknown GLSL type");
5516 }
5517 }
5518
5519 static LLVMTypeRef
5520 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5521 const struct glsl_type *type)
5522 {
5523 if (glsl_type_is_scalar(type)) {
5524 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5525 }
5526
5527 if (glsl_type_is_vector(type)) {
5528 return LLVMVectorType(
5529 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5530 glsl_get_vector_elements(type));
5531 }
5532
5533 if (glsl_type_is_matrix(type)) {
5534 return LLVMArrayType(
5535 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5536 glsl_get_matrix_columns(type));
5537 }
5538
5539 if (glsl_type_is_array(type)) {
5540 return LLVMArrayType(
5541 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5542 glsl_get_length(type));
5543 }
5544
5545 assert(glsl_type_is_struct(type));
5546
5547 LLVMTypeRef member_types[glsl_get_length(type)];
5548
5549 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5550 member_types[i] =
5551 glsl_to_llvm_type(ctx,
5552 glsl_get_struct_field(type, i));
5553 }
5554
5555 return LLVMStructTypeInContext(ctx->context, member_types,
5556 glsl_get_length(type), false);
5557 }
5558
5559 static void
5560 setup_locals(struct ac_nir_context *ctx,
5561 struct nir_function *func)
5562 {
5563 int i, j;
5564 ctx->num_locals = 0;
5565 nir_foreach_variable(variable, &func->impl->locals) {
5566 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5567 variable->data.driver_location = ctx->num_locals * 4;
5568 variable->data.location_frac = 0;
5569 ctx->num_locals += attrib_count;
5570 }
5571 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5572 if (!ctx->locals)
5573 return;
5574
5575 for (i = 0; i < ctx->num_locals; i++) {
5576 for (j = 0; j < 4; j++) {
5577 ctx->locals[i * 4 + j] =
5578 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5579 }
5580 }
5581 }
5582
5583 static void
5584 setup_shared(struct ac_nir_context *ctx,
5585 struct nir_shader *nir)
5586 {
5587 nir_foreach_variable(variable, &nir->shared) {
5588 LLVMValueRef shared =
5589 LLVMAddGlobalInAddressSpace(
5590 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5591 variable->name ? variable->name : "",
5592 LOCAL_ADDR_SPACE);
5593 _mesa_hash_table_insert(ctx->vars, variable, shared);
5594 }
5595 }
5596
5597 static LLVMValueRef
5598 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5599 {
5600 v = ac_to_float(ctx, v);
5601 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5602 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5603 }
5604
5605
5606 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5607 LLVMValueRef src0, LLVMValueRef src1)
5608 {
5609 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5610 LLVMValueRef comp[2];
5611
5612 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5613 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5614 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5615 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5616 }
5617
5618 /* Initialize arguments for the shader export intrinsic */
5619 static void
5620 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5621 LLVMValueRef *values,
5622 unsigned target,
5623 struct ac_export_args *args)
5624 {
5625 /* Default is 0xf. Adjusted below depending on the format. */
5626 args->enabled_channels = 0xf;
5627
5628 /* Specify whether the EXEC mask represents the valid mask */
5629 args->valid_mask = 0;
5630
5631 /* Specify whether this is the last export */
5632 args->done = 0;
5633
5634 /* Specify the target we are exporting */
5635 args->target = target;
5636
5637 args->compr = false;
5638 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5639 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5640 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5641 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5642
5643 if (!values)
5644 return;
5645
5646 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5647 LLVMValueRef val[4];
5648 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5649 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5650 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5651 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5652
5653 switch(col_format) {
5654 case V_028714_SPI_SHADER_ZERO:
5655 args->enabled_channels = 0; /* writemask */
5656 args->target = V_008DFC_SQ_EXP_NULL;
5657 break;
5658
5659 case V_028714_SPI_SHADER_32_R:
5660 args->enabled_channels = 1;
5661 args->out[0] = values[0];
5662 break;
5663
5664 case V_028714_SPI_SHADER_32_GR:
5665 args->enabled_channels = 0x3;
5666 args->out[0] = values[0];
5667 args->out[1] = values[1];
5668 break;
5669
5670 case V_028714_SPI_SHADER_32_AR:
5671 args->enabled_channels = 0x9;
5672 args->out[0] = values[0];
5673 args->out[3] = values[3];
5674 break;
5675
5676 case V_028714_SPI_SHADER_FP16_ABGR:
5677 args->compr = 1;
5678
5679 for (unsigned chan = 0; chan < 2; chan++) {
5680 LLVMValueRef pack_args[2] = {
5681 values[2 * chan],
5682 values[2 * chan + 1]
5683 };
5684 LLVMValueRef packed;
5685
5686 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5687 args->out[chan] = packed;
5688 }
5689 break;
5690
5691 case V_028714_SPI_SHADER_UNORM16_ABGR:
5692 for (unsigned chan = 0; chan < 4; chan++) {
5693 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5694 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5695 LLVMConstReal(ctx->ac.f32, 65535), "");
5696 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5697 LLVMConstReal(ctx->ac.f32, 0.5), "");
5698 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5699 ctx->ac.i32, "");
5700 }
5701
5702 args->compr = 1;
5703 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5704 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5705 break;
5706
5707 case V_028714_SPI_SHADER_SNORM16_ABGR:
5708 for (unsigned chan = 0; chan < 4; chan++) {
5709 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5710 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5711 LLVMConstReal(ctx->ac.f32, 32767), "");
5712
5713 /* If positive, add 0.5, else add -0.5. */
5714 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5715 LLVMBuildSelect(ctx->builder,
5716 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5717 val[chan], ctx->ac.f32_0, ""),
5718 LLVMConstReal(ctx->ac.f32, 0.5),
5719 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5720 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5721 }
5722
5723 args->compr = 1;
5724 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5725 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5726 break;
5727
5728 case V_028714_SPI_SHADER_UINT16_ABGR: {
5729 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5730 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5731 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5732
5733 for (unsigned chan = 0; chan < 4; chan++) {
5734 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5735 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5736 }
5737
5738 args->compr = 1;
5739 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5740 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5741 break;
5742 }
5743
5744 case V_028714_SPI_SHADER_SINT16_ABGR: {
5745 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5746 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5747 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5748 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5749 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5750 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5751
5752 /* Clamp. */
5753 for (unsigned chan = 0; chan < 4; chan++) {
5754 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5755 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5756 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5757 }
5758
5759 args->compr = 1;
5760 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5761 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5762 break;
5763 }
5764
5765 default:
5766 case V_028714_SPI_SHADER_32_ABGR:
5767 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5768 break;
5769 }
5770 } else
5771 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5772
5773 for (unsigned i = 0; i < 4; ++i)
5774 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5775 }
5776
5777 static void
5778 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5779 bool export_prim_id,
5780 struct ac_vs_output_info *outinfo)
5781 {
5782 uint32_t param_count = 0;
5783 unsigned target;
5784 unsigned pos_idx, num_pos_exports = 0;
5785 struct ac_export_args args, pos_args[4] = {};
5786 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5787 int i;
5788
5789 if (ctx->options->key.has_multiview_view_index) {
5790 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5791 if(!*tmp_out) {
5792 for(unsigned i = 0; i < 4; ++i)
5793 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5794 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5795 }
5796
5797 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5798 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5799 }
5800
5801 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5802 sizeof(outinfo->vs_output_param_offset));
5803
5804 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5805 LLVMValueRef slots[8];
5806 unsigned j;
5807
5808 if (outinfo->cull_dist_mask)
5809 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5810
5811 i = VARYING_SLOT_CLIP_DIST0;
5812 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5813 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5814 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5815
5816 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5817 slots[i] = LLVMGetUndef(ctx->ac.f32);
5818
5819 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5820 target = V_008DFC_SQ_EXP_POS + 3;
5821 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5822 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5823 &args, sizeof(args));
5824 }
5825
5826 target = V_008DFC_SQ_EXP_POS + 2;
5827 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5828 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5829 &args, sizeof(args));
5830
5831 }
5832
5833 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5834 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5835 for (unsigned j = 0; j < 4; j++)
5836 pos_values[j] = LLVMBuildLoad(ctx->builder,
5837 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5838 }
5839 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5840
5841 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5842 outinfo->writes_pointsize = true;
5843 psize_value = LLVMBuildLoad(ctx->builder,
5844 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5845 }
5846
5847 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5848 outinfo->writes_layer = true;
5849 layer_value = LLVMBuildLoad(ctx->builder,
5850 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5851 }
5852
5853 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5854 outinfo->writes_viewport_index = true;
5855 viewport_index_value = LLVMBuildLoad(ctx->builder,
5856 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5857 }
5858
5859 if (outinfo->writes_pointsize ||
5860 outinfo->writes_layer ||
5861 outinfo->writes_viewport_index) {
5862 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5863 (outinfo->writes_layer == true ? 4 : 0));
5864 pos_args[1].valid_mask = 0;
5865 pos_args[1].done = 0;
5866 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5867 pos_args[1].compr = 0;
5868 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5869 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5870 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5871 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5872
5873 if (outinfo->writes_pointsize == true)
5874 pos_args[1].out[0] = psize_value;
5875 if (outinfo->writes_layer == true)
5876 pos_args[1].out[2] = layer_value;
5877 if (outinfo->writes_viewport_index == true) {
5878 if (ctx->options->chip_class >= GFX9) {
5879 /* GFX9 has the layer in out.z[10:0] and the viewport
5880 * index in out.z[19:16].
5881 */
5882 LLVMValueRef v = viewport_index_value;
5883 v = ac_to_integer(&ctx->ac, v);
5884 v = LLVMBuildShl(ctx->builder, v,
5885 LLVMConstInt(ctx->ac.i32, 16, false),
5886 "");
5887 v = LLVMBuildOr(ctx->builder, v,
5888 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5889
5890 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5891 pos_args[1].enabled_channels |= 1 << 2;
5892 } else {
5893 pos_args[1].out[3] = viewport_index_value;
5894 pos_args[1].enabled_channels |= 1 << 3;
5895 }
5896 }
5897 }
5898 for (i = 0; i < 4; i++) {
5899 if (pos_args[i].out[0])
5900 num_pos_exports++;
5901 }
5902
5903 pos_idx = 0;
5904 for (i = 0; i < 4; i++) {
5905 if (!pos_args[i].out[0])
5906 continue;
5907
5908 /* Specify the target we are exporting */
5909 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5910 if (pos_idx == num_pos_exports)
5911 pos_args[i].done = 1;
5912 ac_build_export(&ctx->ac, &pos_args[i]);
5913 }
5914
5915 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5916 LLVMValueRef values[4];
5917 if (!(ctx->output_mask & (1ull << i)))
5918 continue;
5919
5920 for (unsigned j = 0; j < 4; j++)
5921 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5922 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5923
5924 if (i == VARYING_SLOT_LAYER) {
5925 target = V_008DFC_SQ_EXP_PARAM + param_count;
5926 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5927 param_count++;
5928 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5929 target = V_008DFC_SQ_EXP_PARAM + param_count;
5930 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5931 param_count++;
5932 } else if (i >= VARYING_SLOT_VAR0) {
5933 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5934 target = V_008DFC_SQ_EXP_PARAM + param_count;
5935 outinfo->vs_output_param_offset[i] = param_count;
5936 param_count++;
5937 } else
5938 continue;
5939
5940 si_llvm_init_export_args(ctx, values, target, &args);
5941
5942 if (target >= V_008DFC_SQ_EXP_POS &&
5943 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5944 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5945 &args, sizeof(args));
5946 } else {
5947 ac_build_export(&ctx->ac, &args);
5948 }
5949 }
5950
5951 if (export_prim_id) {
5952 LLVMValueRef values[4];
5953 target = V_008DFC_SQ_EXP_PARAM + param_count;
5954 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5955 param_count++;
5956
5957 values[0] = ctx->vs_prim_id;
5958 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5959 ctx->shader_info->vs.vgpr_comp_cnt);
5960 for (unsigned j = 1; j < 4; j++)
5961 values[j] = ctx->ac.f32_0;
5962 si_llvm_init_export_args(ctx, values, target, &args);
5963 ac_build_export(&ctx->ac, &args);
5964 outinfo->export_prim_id = true;
5965 }
5966
5967 outinfo->pos_exports = num_pos_exports;
5968 outinfo->param_exports = param_count;
5969 }
5970
5971 static void
5972 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5973 struct ac_es_output_info *outinfo)
5974 {
5975 int j;
5976 uint64_t max_output_written = 0;
5977 LLVMValueRef lds_base = NULL;
5978
5979 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5980 int param_index;
5981 int length = 4;
5982
5983 if (!(ctx->output_mask & (1ull << i)))
5984 continue;
5985
5986 if (i == VARYING_SLOT_CLIP_DIST0)
5987 length = ctx->num_output_clips + ctx->num_output_culls;
5988
5989 param_index = shader_io_get_unique_index(i);
5990
5991 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5992 }
5993
5994 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5995
5996 if (ctx->ac.chip_class >= GFX9) {
5997 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5998 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5999 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6000 LLVMConstInt(ctx->ac.i32, 24, false),
6001 LLVMConstInt(ctx->ac.i32, 4, false), false);
6002 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6003 LLVMBuildMul(ctx->ac.builder, wave_idx,
6004 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6005 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6006 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6007 }
6008
6009 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6010 LLVMValueRef dw_addr;
6011 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6012 int param_index;
6013 int length = 4;
6014
6015 if (!(ctx->output_mask & (1ull << i)))
6016 continue;
6017
6018 if (i == VARYING_SLOT_CLIP_DIST0)
6019 length = ctx->num_output_clips + ctx->num_output_culls;
6020
6021 param_index = shader_io_get_unique_index(i);
6022
6023 if (lds_base) {
6024 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6025 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6026 "");
6027 }
6028 for (j = 0; j < length; j++) {
6029 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6030 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6031
6032 if (ctx->ac.chip_class >= GFX9) {
6033 ac_lds_store(&ctx->ac, dw_addr,
6034 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6035 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6036 } else {
6037 ac_build_buffer_store_dword(&ctx->ac,
6038 ctx->esgs_ring,
6039 out_val, 1,
6040 NULL, ctx->es2gs_offset,
6041 (4 * param_index + j) * 4,
6042 1, 1, true, true);
6043 }
6044 }
6045 }
6046 }
6047
6048 static void
6049 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6050 {
6051 LLVMValueRef vertex_id = ctx->rel_auto_id;
6052 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6053 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6054 vertex_dw_stride, "");
6055
6056 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6057 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6058 int length = 4;
6059
6060 if (!(ctx->output_mask & (1ull << i)))
6061 continue;
6062
6063 if (i == VARYING_SLOT_CLIP_DIST0)
6064 length = ctx->num_output_clips + ctx->num_output_culls;
6065 int param = shader_io_get_unique_index(i);
6066 mark_tess_output(ctx, false, param);
6067 if (length > 4)
6068 mark_tess_output(ctx, false, param + 1);
6069 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6070 LLVMConstInt(ctx->ac.i32, param * 4, false),
6071 "");
6072 for (unsigned j = 0; j < length; j++) {
6073 ac_lds_store(&ctx->ac, dw_addr,
6074 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6075 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6076 }
6077 }
6078 }
6079
6080 struct ac_build_if_state
6081 {
6082 struct nir_to_llvm_context *ctx;
6083 LLVMValueRef condition;
6084 LLVMBasicBlockRef entry_block;
6085 LLVMBasicBlockRef true_block;
6086 LLVMBasicBlockRef false_block;
6087 LLVMBasicBlockRef merge_block;
6088 };
6089
6090 static LLVMBasicBlockRef
6091 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6092 {
6093 LLVMBasicBlockRef current_block;
6094 LLVMBasicBlockRef next_block;
6095 LLVMBasicBlockRef new_block;
6096
6097 /* get current basic block */
6098 current_block = LLVMGetInsertBlock(ctx->builder);
6099
6100 /* chqeck if there's another block after this one */
6101 next_block = LLVMGetNextBasicBlock(current_block);
6102 if (next_block) {
6103 /* insert the new block before the next block */
6104 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6105 }
6106 else {
6107 /* append new block after current block */
6108 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6109 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6110 }
6111 return new_block;
6112 }
6113
6114 static void
6115 ac_nir_build_if(struct ac_build_if_state *ifthen,
6116 struct nir_to_llvm_context *ctx,
6117 LLVMValueRef condition)
6118 {
6119 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6120
6121 memset(ifthen, 0, sizeof *ifthen);
6122 ifthen->ctx = ctx;
6123 ifthen->condition = condition;
6124 ifthen->entry_block = block;
6125
6126 /* create endif/merge basic block for the phi functions */
6127 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6128
6129 /* create/insert true_block before merge_block */
6130 ifthen->true_block =
6131 LLVMInsertBasicBlockInContext(ctx->context,
6132 ifthen->merge_block,
6133 "if-true-block");
6134
6135 /* successive code goes into the true block */
6136 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6137 }
6138
6139 /**
6140 * End a conditional.
6141 */
6142 static void
6143 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6144 {
6145 LLVMBuilderRef builder = ifthen->ctx->builder;
6146
6147 /* Insert branch to the merge block from current block */
6148 LLVMBuildBr(builder, ifthen->merge_block);
6149
6150 /*
6151 * Now patch in the various branch instructions.
6152 */
6153
6154 /* Insert the conditional branch instruction at the end of entry_block */
6155 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6156 if (ifthen->false_block) {
6157 /* we have an else clause */
6158 LLVMBuildCondBr(builder, ifthen->condition,
6159 ifthen->true_block, ifthen->false_block);
6160 }
6161 else {
6162 /* no else clause */
6163 LLVMBuildCondBr(builder, ifthen->condition,
6164 ifthen->true_block, ifthen->merge_block);
6165 }
6166
6167 /* Resume building code at end of the ifthen->merge_block */
6168 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6169 }
6170
6171 static void
6172 write_tess_factors(struct nir_to_llvm_context *ctx)
6173 {
6174 unsigned stride, outer_comps, inner_comps;
6175 struct ac_build_if_state if_ctx, inner_if_ctx;
6176 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6177 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6178 unsigned tess_inner_index, tess_outer_index;
6179 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6180 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6181 int i;
6182 emit_barrier(&ctx->ac, ctx->stage);
6183
6184 switch (ctx->options->key.tcs.primitive_mode) {
6185 case GL_ISOLINES:
6186 stride = 2;
6187 outer_comps = 2;
6188 inner_comps = 0;
6189 break;
6190 case GL_TRIANGLES:
6191 stride = 4;
6192 outer_comps = 3;
6193 inner_comps = 1;
6194 break;
6195 case GL_QUADS:
6196 stride = 6;
6197 outer_comps = 4;
6198 inner_comps = 2;
6199 break;
6200 default:
6201 return;
6202 }
6203
6204 ac_nir_build_if(&if_ctx, ctx,
6205 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6206 invocation_id, ctx->ac.i32_0, ""));
6207
6208 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6209 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6210
6211 mark_tess_output(ctx, true, tess_inner_index);
6212 mark_tess_output(ctx, true, tess_outer_index);
6213 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6214 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6215 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6216 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6217 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6218
6219 for (i = 0; i < 4; i++) {
6220 inner[i] = LLVMGetUndef(ctx->ac.i32);
6221 outer[i] = LLVMGetUndef(ctx->ac.i32);
6222 }
6223
6224 // LINES reverseal
6225 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6226 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6227 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6228 ctx->ac.i32_1, "");
6229 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6230 } else {
6231 for (i = 0; i < outer_comps; i++) {
6232 outer[i] = out[i] =
6233 ac_lds_load(&ctx->ac, lds_outer);
6234 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6235 ctx->ac.i32_1, "");
6236 }
6237 for (i = 0; i < inner_comps; i++) {
6238 inner[i] = out[outer_comps+i] =
6239 ac_lds_load(&ctx->ac, lds_inner);
6240 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6241 ctx->ac.i32_1, "");
6242 }
6243 }
6244
6245 /* Convert the outputs to vectors for stores. */
6246 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6247 vec1 = NULL;
6248
6249 if (stride > 4)
6250 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6251
6252
6253 buffer = ctx->hs_ring_tess_factor;
6254 tf_base = ctx->tess_factor_offset;
6255 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6256 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6257 unsigned tf_offset = 0;
6258
6259 if (ctx->options->chip_class <= VI) {
6260 ac_nir_build_if(&inner_if_ctx, ctx,
6261 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6262 rel_patch_id, ctx->ac.i32_0, ""));
6263
6264 /* Store the dynamic HS control word. */
6265 ac_build_buffer_store_dword(&ctx->ac, buffer,
6266 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6267 1, ctx->ac.i32_0, tf_base,
6268 0, 1, 0, true, false);
6269 tf_offset += 4;
6270
6271 ac_nir_build_endif(&inner_if_ctx);
6272 }
6273
6274 /* Store the tessellation factors. */
6275 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6276 MIN2(stride, 4), byteoffset, tf_base,
6277 tf_offset, 1, 0, true, false);
6278 if (vec1)
6279 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6280 stride - 4, byteoffset, tf_base,
6281 16 + tf_offset, 1, 0, true, false);
6282
6283 //store to offchip for TES to read - only if TES reads them
6284 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6285 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6286 LLVMValueRef tf_inner_offset;
6287 unsigned param_outer, param_inner;
6288
6289 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6290 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6291 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6292
6293 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6294 util_next_power_of_two(outer_comps));
6295
6296 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6297 outer_comps, tf_outer_offset,
6298 ctx->oc_lds, 0, 1, 0, true, false);
6299 if (inner_comps) {
6300 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6301 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6302 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6303
6304 inner_vec = inner_comps == 1 ? inner[0] :
6305 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6306 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6307 inner_comps, tf_inner_offset,
6308 ctx->oc_lds, 0, 1, 0, true, false);
6309 }
6310 }
6311 ac_nir_build_endif(&if_ctx);
6312 }
6313
6314 static void
6315 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6316 {
6317 write_tess_factors(ctx);
6318 }
6319
6320 static bool
6321 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6322 LLVMValueRef *color, unsigned param, bool is_last,
6323 struct ac_export_args *args)
6324 {
6325 /* Export */
6326 si_llvm_init_export_args(ctx, color, param,
6327 args);
6328
6329 if (is_last) {
6330 args->valid_mask = 1; /* whether the EXEC mask is valid */
6331 args->done = 1; /* DONE bit */
6332 } else if (!args->enabled_channels)
6333 return false; /* unnecessary NULL export */
6334
6335 return true;
6336 }
6337
6338 static void
6339 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6340 LLVMValueRef depth, LLVMValueRef stencil,
6341 LLVMValueRef samplemask)
6342 {
6343 struct ac_export_args args;
6344
6345 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6346
6347 ac_build_export(&ctx->ac, &args);
6348 }
6349
6350 static void
6351 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6352 {
6353 unsigned index = 0;
6354 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6355 struct ac_export_args color_args[8];
6356
6357 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6358 LLVMValueRef values[4];
6359
6360 if (!(ctx->output_mask & (1ull << i)))
6361 continue;
6362
6363 if (i == FRAG_RESULT_DEPTH) {
6364 ctx->shader_info->fs.writes_z = true;
6365 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6366 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6367 } else if (i == FRAG_RESULT_STENCIL) {
6368 ctx->shader_info->fs.writes_stencil = true;
6369 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6370 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6371 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6372 ctx->shader_info->fs.writes_sample_mask = true;
6373 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6374 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6375 } else {
6376 bool last = false;
6377 for (unsigned j = 0; j < 4; j++)
6378 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6379 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6380
6381 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6382 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6383
6384 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6385 if (ret)
6386 index++;
6387 }
6388 }
6389
6390 for (unsigned i = 0; i < index; i++)
6391 ac_build_export(&ctx->ac, &color_args[i]);
6392 if (depth || stencil || samplemask)
6393 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6394 else if (!index) {
6395 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6396 ac_build_export(&ctx->ac, &color_args[0]);
6397 }
6398
6399 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6400 }
6401
6402 static void
6403 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6404 {
6405 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6406 }
6407
6408 static void
6409 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6410 LLVMValueRef *addrs)
6411 {
6412 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6413
6414 switch (ctx->stage) {
6415 case MESA_SHADER_VERTEX:
6416 if (ctx->options->key.vs.as_ls)
6417 handle_ls_outputs_post(ctx);
6418 else if (ctx->options->key.vs.as_es)
6419 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6420 else
6421 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6422 &ctx->shader_info->vs.outinfo);
6423 break;
6424 case MESA_SHADER_FRAGMENT:
6425 handle_fs_outputs_post(ctx);
6426 break;
6427 case MESA_SHADER_GEOMETRY:
6428 emit_gs_epilogue(ctx);
6429 break;
6430 case MESA_SHADER_TESS_CTRL:
6431 handle_tcs_outputs_post(ctx);
6432 break;
6433 case MESA_SHADER_TESS_EVAL:
6434 if (ctx->options->key.tes.as_es)
6435 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6436 else
6437 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6438 &ctx->shader_info->tes.outinfo);
6439 break;
6440 default:
6441 break;
6442 }
6443 }
6444
6445 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6446 {
6447 LLVMPassManagerRef passmgr;
6448 /* Create the pass manager */
6449 passmgr = LLVMCreateFunctionPassManagerForModule(
6450 ctx->module);
6451
6452 /* This pass should eliminate all the load and store instructions */
6453 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6454
6455 /* Add some optimization passes */
6456 LLVMAddScalarReplAggregatesPass(passmgr);
6457 LLVMAddLICMPass(passmgr);
6458 LLVMAddAggressiveDCEPass(passmgr);
6459 LLVMAddCFGSimplificationPass(passmgr);
6460 LLVMAddInstructionCombiningPass(passmgr);
6461
6462 /* Run the pass */
6463 LLVMInitializeFunctionPassManager(passmgr);
6464 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6465 LLVMFinalizeFunctionPassManager(passmgr);
6466
6467 LLVMDisposeBuilder(ctx->builder);
6468 LLVMDisposePassManager(passmgr);
6469 }
6470
6471 static void
6472 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6473 {
6474 struct ac_vs_output_info *outinfo;
6475
6476 switch (ctx->stage) {
6477 case MESA_SHADER_FRAGMENT:
6478 case MESA_SHADER_COMPUTE:
6479 case MESA_SHADER_TESS_CTRL:
6480 case MESA_SHADER_GEOMETRY:
6481 return;
6482 case MESA_SHADER_VERTEX:
6483 if (ctx->options->key.vs.as_ls ||
6484 ctx->options->key.vs.as_es)
6485 return;
6486 outinfo = &ctx->shader_info->vs.outinfo;
6487 break;
6488 case MESA_SHADER_TESS_EVAL:
6489 if (ctx->options->key.vs.as_es)
6490 return;
6491 outinfo = &ctx->shader_info->tes.outinfo;
6492 break;
6493 default:
6494 unreachable("Unhandled shader type");
6495 }
6496
6497 ac_optimize_vs_outputs(&ctx->ac,
6498 ctx->main_function,
6499 outinfo->vs_output_param_offset,
6500 VARYING_SLOT_MAX,
6501 &outinfo->param_exports);
6502 }
6503
6504 static void
6505 ac_setup_rings(struct nir_to_llvm_context *ctx)
6506 {
6507 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6508 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6509 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6510 }
6511
6512 if (ctx->is_gs_copy_shader) {
6513 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6514 }
6515 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6516 LLVMValueRef tmp;
6517 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6518 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6519
6520 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6521
6522 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6523 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6524 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6525 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6526 }
6527
6528 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6529 ctx->stage == MESA_SHADER_TESS_EVAL) {
6530 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6531 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6532 }
6533 }
6534
6535 static unsigned
6536 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6537 const struct nir_shader *nir)
6538 {
6539 switch (nir->info.stage) {
6540 case MESA_SHADER_TESS_CTRL:
6541 return chip_class >= CIK ? 128 : 64;
6542 case MESA_SHADER_GEOMETRY:
6543 return chip_class >= GFX9 ? 128 : 64;
6544 case MESA_SHADER_COMPUTE:
6545 break;
6546 default:
6547 return 0;
6548 }
6549
6550 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6551 nir->info.cs.local_size[1] *
6552 nir->info.cs.local_size[2];
6553 return max_workgroup_size;
6554 }
6555
6556 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6557 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6558 {
6559 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6560 LLVMConstInt(ctx->ac.i32, 8, false),
6561 LLVMConstInt(ctx->ac.i32, 8, false), false);
6562 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6563 ctx->ac.i32_0, "");
6564 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6565 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6566 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6567 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6568 }
6569
6570 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6571 {
6572 for(int i = 5; i >= 0; --i) {
6573 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6574 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6575 LLVMConstInt(ctx->ac.i32, 16, false), false);
6576 }
6577
6578 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6579 LLVMConstInt(ctx->ac.i32, 16, false),
6580 LLVMConstInt(ctx->ac.i32, 8, false), false);
6581 }
6582
6583 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6584 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6585 {
6586 struct ac_nir_context ctx = {};
6587 struct nir_function *func;
6588
6589 ctx.ac = *ac;
6590 ctx.abi = abi;
6591
6592 ctx.nctx = nctx;
6593 if (nctx)
6594 nctx->nir = &ctx;
6595
6596 ctx.stage = nir->info.stage;
6597
6598 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6599
6600 nir_foreach_variable(variable, &nir->outputs)
6601 handle_shader_output_decl(&ctx, nir, variable);
6602
6603 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6604 _mesa_key_pointer_equal);
6605 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6606 _mesa_key_pointer_equal);
6607 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6608 _mesa_key_pointer_equal);
6609
6610 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6611
6612 setup_locals(&ctx, func);
6613
6614 if (nir->info.stage == MESA_SHADER_COMPUTE)
6615 setup_shared(&ctx, nir);
6616
6617 visit_cf_list(&ctx, &func->impl->body);
6618 phi_post_pass(&ctx);
6619
6620 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6621 ctx.outputs);
6622
6623 free(ctx.locals);
6624 ralloc_free(ctx.defs);
6625 ralloc_free(ctx.phis);
6626 ralloc_free(ctx.vars);
6627
6628 if (nctx)
6629 nctx->nir = NULL;
6630 }
6631
6632 static
6633 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6634 struct nir_shader *const *shaders,
6635 int shader_count,
6636 struct ac_shader_variant_info *shader_info,
6637 const struct ac_nir_compiler_options *options)
6638 {
6639 struct nir_to_llvm_context ctx = {0};
6640 unsigned i;
6641 ctx.options = options;
6642 ctx.shader_info = shader_info;
6643 ctx.context = LLVMContextCreate();
6644 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6645
6646 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6647 options->family);
6648 ctx.ac.module = ctx.module;
6649 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6650
6651 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6652 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6653 LLVMSetDataLayout(ctx.module, data_layout_str);
6654 LLVMDisposeTargetData(data_layout);
6655 LLVMDisposeMessage(data_layout_str);
6656
6657 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6658 ctx.ac.builder = ctx.builder;
6659
6660 memset(shader_info, 0, sizeof(*shader_info));
6661
6662 for(int i = 0; i < shader_count; ++i)
6663 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6664
6665 for (i = 0; i < AC_UD_MAX_SETS; i++)
6666 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6667 for (i = 0; i < AC_UD_MAX_UD; i++)
6668 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6669
6670 ctx.max_workgroup_size = 0;
6671 for (int i = 0; i < shader_count; ++i) {
6672 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6673 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6674 shaders[i]));
6675 }
6676
6677 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6678 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6679
6680 ctx.abi.inputs = &ctx.inputs[0];
6681 ctx.abi.emit_outputs = handle_shader_outputs_post;
6682 ctx.abi.emit_vertex = visit_emit_vertex;
6683 ctx.abi.load_ubo = radv_load_ubo;
6684 ctx.abi.load_ssbo = radv_load_ssbo;
6685 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6686 ctx.abi.clamp_shadow_reference = false;
6687
6688 if (shader_count >= 2)
6689 ac_init_exec_full_mask(&ctx.ac);
6690
6691 if (ctx.ac.chip_class == GFX9 &&
6692 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6693 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6694
6695 for(int i = 0; i < shader_count; ++i) {
6696 ctx.stage = shaders[i]->info.stage;
6697 ctx.output_mask = 0;
6698 ctx.tess_outputs_written = 0;
6699 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6700 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6701
6702 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6703 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6704 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6705 ctx.abi.load_inputs = load_gs_input;
6706 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6707 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6708 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6709 ctx.abi.load_tess_inputs = load_tcs_input;
6710 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6711 ctx.abi.store_tcs_outputs = store_tcs_output;
6712 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6713 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6714 ctx.abi.load_tess_inputs = load_tes_input;
6715 ctx.abi.load_tess_coord = load_tess_coord;
6716 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6717 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6718 if (shader_info->info.vs.needs_instance_id) {
6719 if (ctx.ac.chip_class == GFX9 &&
6720 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL) {
6721 ctx.shader_info->vs.vgpr_comp_cnt =
6722 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6723 } else {
6724 ctx.shader_info->vs.vgpr_comp_cnt =
6725 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6726 }
6727 }
6728 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6729 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6730 }
6731
6732 if (i)
6733 emit_barrier(&ctx.ac, ctx.stage);
6734
6735 ac_setup_rings(&ctx);
6736
6737 LLVMBasicBlockRef merge_block;
6738 if (shader_count >= 2) {
6739 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6740 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6741 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6742
6743 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6744 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6745 LLVMConstInt(ctx.ac.i32, 8, false), false);
6746 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6747 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6748 thread_id, count, "");
6749 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6750
6751 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6752 }
6753
6754 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6755 handle_fs_inputs(&ctx, shaders[i]);
6756 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6757 handle_vs_inputs(&ctx, shaders[i]);
6758 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6759 prepare_gs_input_vgprs(&ctx);
6760
6761 nir_foreach_variable(variable, &shaders[i]->outputs)
6762 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6763
6764 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6765
6766 if (shader_count >= 2) {
6767 LLVMBuildBr(ctx.ac.builder, merge_block);
6768 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6769 }
6770
6771 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6772 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6773 shaders[i]->info.cull_distance_array_size > 4;
6774 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6775 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6776 shaders[i]->info.gs.vertices_out;
6777 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6778 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6779 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6780 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6781 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6782 }
6783 }
6784
6785 LLVMBuildRetVoid(ctx.builder);
6786
6787 ac_llvm_finalize_module(&ctx);
6788
6789 if (shader_count == 1)
6790 ac_nir_eliminate_const_vs_outputs(&ctx);
6791
6792 return ctx.module;
6793 }
6794
6795 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6796 {
6797 unsigned *retval = (unsigned *)context;
6798 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6799 char *description = LLVMGetDiagInfoDescription(di);
6800
6801 if (severity == LLVMDSError) {
6802 *retval = 1;
6803 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6804 description);
6805 }
6806
6807 LLVMDisposeMessage(description);
6808 }
6809
6810 static unsigned ac_llvm_compile(LLVMModuleRef M,
6811 struct ac_shader_binary *binary,
6812 LLVMTargetMachineRef tm)
6813 {
6814 unsigned retval = 0;
6815 char *err;
6816 LLVMContextRef llvm_ctx;
6817 LLVMMemoryBufferRef out_buffer;
6818 unsigned buffer_size;
6819 const char *buffer_data;
6820 LLVMBool mem_err;
6821
6822 /* Setup Diagnostic Handler*/
6823 llvm_ctx = LLVMGetModuleContext(M);
6824
6825 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6826 &retval);
6827
6828 /* Compile IR*/
6829 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6830 &err, &out_buffer);
6831
6832 /* Process Errors/Warnings */
6833 if (mem_err) {
6834 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6835 free(err);
6836 retval = 1;
6837 goto out;
6838 }
6839
6840 /* Extract Shader Code*/
6841 buffer_size = LLVMGetBufferSize(out_buffer);
6842 buffer_data = LLVMGetBufferStart(out_buffer);
6843
6844 ac_elf_read(buffer_data, buffer_size, binary);
6845
6846 /* Clean up */
6847 LLVMDisposeMemoryBuffer(out_buffer);
6848
6849 out:
6850 return retval;
6851 }
6852
6853 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6854 LLVMModuleRef llvm_module,
6855 struct ac_shader_binary *binary,
6856 struct ac_shader_config *config,
6857 struct ac_shader_variant_info *shader_info,
6858 gl_shader_stage stage,
6859 bool dump_shader, bool supports_spill)
6860 {
6861 if (dump_shader)
6862 ac_dump_module(llvm_module);
6863
6864 memset(binary, 0, sizeof(*binary));
6865 int v = ac_llvm_compile(llvm_module, binary, tm);
6866 if (v) {
6867 fprintf(stderr, "compile failed\n");
6868 }
6869
6870 if (dump_shader)
6871 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6872
6873 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6874
6875 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6876 LLVMDisposeModule(llvm_module);
6877 LLVMContextDispose(ctx);
6878
6879 if (stage == MESA_SHADER_FRAGMENT) {
6880 shader_info->num_input_vgprs = 0;
6881 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6882 shader_info->num_input_vgprs += 2;
6883 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6884 shader_info->num_input_vgprs += 2;
6885 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6886 shader_info->num_input_vgprs += 2;
6887 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6888 shader_info->num_input_vgprs += 3;
6889 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6890 shader_info->num_input_vgprs += 2;
6891 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6892 shader_info->num_input_vgprs += 2;
6893 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6894 shader_info->num_input_vgprs += 2;
6895 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6896 shader_info->num_input_vgprs += 1;
6897 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6898 shader_info->num_input_vgprs += 1;
6899 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6900 shader_info->num_input_vgprs += 1;
6901 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6902 shader_info->num_input_vgprs += 1;
6903 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6904 shader_info->num_input_vgprs += 1;
6905 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6906 shader_info->num_input_vgprs += 1;
6907 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6908 shader_info->num_input_vgprs += 1;
6909 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6910 shader_info->num_input_vgprs += 1;
6911 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6912 shader_info->num_input_vgprs += 1;
6913 }
6914 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6915
6916 /* +3 for scratch wave offset and VCC */
6917 config->num_sgprs = MAX2(config->num_sgprs,
6918 shader_info->num_input_sgprs + 3);
6919
6920 /* Enable 64-bit and 16-bit denormals, because there is no performance
6921 * cost.
6922 *
6923 * If denormals are enabled, all floating-point output modifiers are
6924 * ignored.
6925 *
6926 * Don't enable denormals for 32-bit floats, because:
6927 * - Floating-point output modifiers would be ignored by the hw.
6928 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6929 * have to stop using those.
6930 * - SI & CI would be very slow.
6931 */
6932 config->float_mode |= V_00B028_FP_64_DENORMS;
6933 }
6934
6935 static void
6936 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6937 {
6938 switch (nir->info.stage) {
6939 case MESA_SHADER_COMPUTE:
6940 for (int i = 0; i < 3; ++i)
6941 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6942 break;
6943 case MESA_SHADER_FRAGMENT:
6944 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6945 break;
6946 case MESA_SHADER_GEOMETRY:
6947 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6948 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6949 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6950 shader_info->gs.invocations = nir->info.gs.invocations;
6951 break;
6952 case MESA_SHADER_TESS_EVAL:
6953 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6954 shader_info->tes.spacing = nir->info.tess.spacing;
6955 shader_info->tes.ccw = nir->info.tess.ccw;
6956 shader_info->tes.point_mode = nir->info.tess.point_mode;
6957 shader_info->tes.as_es = options->key.tes.as_es;
6958 break;
6959 case MESA_SHADER_TESS_CTRL:
6960 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6961 break;
6962 case MESA_SHADER_VERTEX:
6963 shader_info->vs.as_es = options->key.vs.as_es;
6964 shader_info->vs.as_ls = options->key.vs.as_ls;
6965 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
6966 if (options->key.vs.as_ls)
6967 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6968 break;
6969 default:
6970 break;
6971 }
6972 }
6973
6974 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6975 struct ac_shader_binary *binary,
6976 struct ac_shader_config *config,
6977 struct ac_shader_variant_info *shader_info,
6978 struct nir_shader *const *nir,
6979 int nir_count,
6980 const struct ac_nir_compiler_options *options,
6981 bool dump_shader)
6982 {
6983
6984 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6985 options);
6986
6987 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6988 for (int i = 0; i < nir_count; ++i)
6989 ac_fill_shader_info(shader_info, nir[i], options);
6990
6991 /* Determine the ES type (VS or TES) for the GS on GFX9. */
6992 if (options->chip_class == GFX9) {
6993 if (nir_count == 2 &&
6994 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
6995 shader_info->gs.es_type = nir[0]->info.stage;
6996 }
6997 }
6998 }
6999
7000 static void
7001 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7002 {
7003 LLVMValueRef args[9];
7004 args[0] = ctx->gsvs_ring;
7005 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
7006 args[3] = ctx->ac.i32_0;
7007 args[4] = ctx->ac.i32_1; /* OFFEN */
7008 args[5] = ctx->ac.i32_0; /* IDXEN */
7009 args[6] = ctx->ac.i32_1; /* GLC */
7010 args[7] = ctx->ac.i32_1; /* SLC */
7011 args[8] = ctx->ac.i32_0; /* TFE */
7012
7013 int idx = 0;
7014
7015 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7016 int length = 4;
7017 int slot = idx;
7018 int slot_inc = 1;
7019 if (!(ctx->output_mask & (1ull << i)))
7020 continue;
7021
7022 if (i == VARYING_SLOT_CLIP_DIST0) {
7023 /* unpack clip and cull from a single set of slots */
7024 length = ctx->num_output_clips + ctx->num_output_culls;
7025 if (length > 4)
7026 slot_inc = 2;
7027 }
7028
7029 for (unsigned j = 0; j < length; j++) {
7030 LLVMValueRef value;
7031 args[2] = LLVMConstInt(ctx->ac.i32,
7032 (slot * 4 + j) *
7033 ctx->gs_max_out_vertices * 16 * 4, false);
7034
7035 value = ac_build_intrinsic(&ctx->ac,
7036 "llvm.SI.buffer.load.dword.i32.i32",
7037 ctx->ac.i32, args, 9,
7038 AC_FUNC_ATTR_READONLY |
7039 AC_FUNC_ATTR_LEGACY);
7040
7041 LLVMBuildStore(ctx->builder,
7042 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7043 }
7044 idx += slot_inc;
7045 }
7046 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7047 }
7048
7049 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7050 struct nir_shader *geom_shader,
7051 struct ac_shader_binary *binary,
7052 struct ac_shader_config *config,
7053 struct ac_shader_variant_info *shader_info,
7054 const struct ac_nir_compiler_options *options,
7055 bool dump_shader)
7056 {
7057 struct nir_to_llvm_context ctx = {0};
7058 ctx.context = LLVMContextCreate();
7059 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7060 ctx.options = options;
7061 ctx.shader_info = shader_info;
7062
7063 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7064 options->family);
7065 ctx.ac.module = ctx.module;
7066
7067 ctx.is_gs_copy_shader = true;
7068 LLVMSetTarget(ctx.module, "amdgcn--");
7069
7070 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7071 ctx.ac.builder = ctx.builder;
7072 ctx.stage = MESA_SHADER_VERTEX;
7073
7074 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7075
7076 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7077 ac_setup_rings(&ctx);
7078
7079 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7080 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7081
7082 struct ac_nir_context nir_ctx = {};
7083 nir_ctx.ac = ctx.ac;
7084 nir_ctx.abi = &ctx.abi;
7085
7086 nir_ctx.nctx = &ctx;
7087 ctx.nir = &nir_ctx;
7088
7089 nir_foreach_variable(variable, &geom_shader->outputs) {
7090 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7091 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7092 }
7093
7094 ac_gs_copy_shader_emit(&ctx);
7095
7096 ctx.nir = NULL;
7097
7098 LLVMBuildRetVoid(ctx.builder);
7099
7100 ac_llvm_finalize_module(&ctx);
7101
7102 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7103 MESA_SHADER_VERTEX,
7104 dump_shader, options->supports_spill);
7105 }