projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv/ac: Add draw index support.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_util.h"
26 #include "ac_binary.h"
27 #include "sid.h"
28 #include "nir/nir.h"
29 #include "../vulkan/radv_descriptor_set.h"
30 #include "util/bitscan.h"
31 #include <llvm-c/Transforms/Scalar.h>
32
33 enum radeon_llvm_calling_convention {
34 RADEON_LLVM_AMDGPU_VS = 87,
35 RADEON_LLVM_AMDGPU_GS = 88,
36 RADEON_LLVM_AMDGPU_PS = 89,
37 RADEON_LLVM_AMDGPU_CS = 90,
38 };
39
40 #define CONST_ADDR_SPACE 2
41 #define LOCAL_ADDR_SPACE 3
42
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
44 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
45
46 #define SENDMSG_GS 2
47 #define SENDMSG_GS_DONE 3
48
49 #define SENDMSG_GS_OP_NOP (0 << 4)
50 #define SENDMSG_GS_OP_CUT (1 << 4)
51 #define SENDMSG_GS_OP_EMIT (2 << 4)
52 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
53
54 enum desc_type {
55 DESC_IMAGE,
56 DESC_FMASK,
57 DESC_SAMPLER,
58 DESC_BUFFER,
59 };
60
61 struct nir_to_llvm_context {
62 struct ac_llvm_context ac;
63 const struct ac_nir_compiler_options *options;
64 struct ac_shader_variant_info *shader_info;
65
66 LLVMContextRef context;
67 LLVMModuleRef module;
68 LLVMBuilderRef builder;
69 LLVMValueRef main_function;
70
71 struct hash_table *defs;
72 struct hash_table *phis;
73
74 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
75 LLVMValueRef ring_offsets;
76 LLVMValueRef push_constants;
77 LLVMValueRef num_work_groups;
78 LLVMValueRef workgroup_ids;
79 LLVMValueRef local_invocation_ids;
80 LLVMValueRef tg_size;
81
82 LLVMValueRef vertex_buffers;
83 LLVMValueRef base_vertex;
84 LLVMValueRef start_instance;
85 LLVMValueRef draw_index;
86 LLVMValueRef vertex_id;
87 LLVMValueRef rel_auto_id;
88 LLVMValueRef vs_prim_id;
89 LLVMValueRef instance_id;
90
91 LLVMValueRef es2gs_offset;
92
93 LLVMValueRef gsvs_ring_stride;
94 LLVMValueRef gsvs_num_entries;
95 LLVMValueRef gs2vs_offset;
96 LLVMValueRef gs_wave_id;
97 LLVMValueRef gs_vtx_offset[6];
98 LLVMValueRef gs_prim_id, gs_invocation_id;
99
100 LLVMValueRef esgs_ring;
101 LLVMValueRef gsvs_ring;
102
103 LLVMValueRef prim_mask;
104 LLVMValueRef sample_positions;
105 LLVMValueRef persp_sample, persp_center, persp_centroid;
106 LLVMValueRef linear_sample, linear_center, linear_centroid;
107 LLVMValueRef front_face;
108 LLVMValueRef ancillary;
109 LLVMValueRef frag_pos[4];
110
111 LLVMBasicBlockRef continue_block;
112 LLVMBasicBlockRef break_block;
113
114 LLVMTypeRef i1;
115 LLVMTypeRef i8;
116 LLVMTypeRef i16;
117 LLVMTypeRef i32;
118 LLVMTypeRef i64;
119 LLVMTypeRef v2i32;
120 LLVMTypeRef v3i32;
121 LLVMTypeRef v4i32;
122 LLVMTypeRef v8i32;
123 LLVMTypeRef f64;
124 LLVMTypeRef f32;
125 LLVMTypeRef f16;
126 LLVMTypeRef v2f32;
127 LLVMTypeRef v4f32;
128 LLVMTypeRef v16i8;
129 LLVMTypeRef voidt;
130
131 LLVMValueRef i32zero;
132 LLVMValueRef i32one;
133 LLVMValueRef f32zero;
134 LLVMValueRef f32one;
135 LLVMValueRef v4f32empty;
136
137 unsigned range_md_kind;
138 unsigned uniform_md_kind;
139 unsigned invariant_load_md_kind;
140 LLVMValueRef empty_md;
141 gl_shader_stage stage;
142
143 LLVMValueRef lds;
144 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
145 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
146
147 LLVMValueRef shared_memory;
148 uint64_t input_mask;
149 uint64_t output_mask;
150 int num_locals;
151 LLVMValueRef *locals;
152 bool has_ddxy;
153 unsigned num_clips;
154 unsigned num_culls;
155
156 bool has_ds_bpermute;
157
158 bool is_gs_copy_shader;
159 LLVMValueRef gs_next_vertex;
160 unsigned gs_max_out_vertices;
161 };
162
163 struct ac_tex_info {
164 LLVMValueRef args[12];
165 int arg_count;
166 LLVMTypeRef dst_type;
167 bool has_offset;
168 };
169
170 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
171 nir_deref_var *deref,
172 enum desc_type desc_type);
173 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
174 {
175 return (index * 4) + chan;
176 }
177
178 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
179 {
180 if (slot == VARYING_SLOT_POS)
181 return 0;
182 if (slot == VARYING_SLOT_PSIZ)
183 return 1;
184 if (slot == VARYING_SLOT_CLIP_DIST0)
185 return 2;
186 if (slot == VARYING_SLOT_CLIP_DIST1)
187 return 3;
188 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
189 return 4 + (slot - VARYING_SLOT_VAR0);
190 unreachable("illegal slot in get unique index\n");
191 }
192
193 static unsigned llvm_get_type_size(LLVMTypeRef type)
194 {
195 LLVMTypeKind kind = LLVMGetTypeKind(type);
196
197 switch (kind) {
198 case LLVMIntegerTypeKind:
199 return LLVMGetIntTypeWidth(type) / 8;
200 case LLVMFloatTypeKind:
201 return 4;
202 case LLVMPointerTypeKind:
203 return 8;
204 case LLVMVectorTypeKind:
205 return LLVMGetVectorSize(type) *
206 llvm_get_type_size(LLVMGetElementType(type));
207 default:
208 assert(0);
209 return 0;
210 }
211 }
212
213 static void set_llvm_calling_convention(LLVMValueRef func,
214 gl_shader_stage stage)
215 {
216 enum radeon_llvm_calling_convention calling_conv;
217
218 switch (stage) {
219 case MESA_SHADER_VERTEX:
220 case MESA_SHADER_TESS_CTRL:
221 case MESA_SHADER_TESS_EVAL:
222 calling_conv = RADEON_LLVM_AMDGPU_VS;
223 break;
224 case MESA_SHADER_GEOMETRY:
225 calling_conv = RADEON_LLVM_AMDGPU_GS;
226 break;
227 case MESA_SHADER_FRAGMENT:
228 calling_conv = RADEON_LLVM_AMDGPU_PS;
229 break;
230 case MESA_SHADER_COMPUTE:
231 calling_conv = RADEON_LLVM_AMDGPU_CS;
232 break;
233 default:
234 unreachable("Unhandle shader type");
235 }
236
237 LLVMSetFunctionCallConv(func, calling_conv);
238 }
239
240 static LLVMValueRef
241 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
242 LLVMBuilderRef builder, LLVMTypeRef *return_types,
243 unsigned num_return_elems, LLVMTypeRef *param_types,
244 unsigned param_count, unsigned array_params_mask,
245 unsigned sgpr_params, bool unsafe_math)
246 {
247 LLVMTypeRef main_function_type, ret_type;
248 LLVMBasicBlockRef main_function_body;
249
250 if (num_return_elems)
251 ret_type = LLVMStructTypeInContext(ctx, return_types,
252 num_return_elems, true);
253 else
254 ret_type = LLVMVoidTypeInContext(ctx);
255
256 /* Setup the function */
257 main_function_type =
258 LLVMFunctionType(ret_type, param_types, param_count, 0);
259 LLVMValueRef main_function =
260 LLVMAddFunction(module, "main", main_function_type);
261 main_function_body =
262 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
263 LLVMPositionBuilderAtEnd(builder, main_function_body);
264
265 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
266 for (unsigned i = 0; i < sgpr_params; ++i) {
267 if (array_params_mask & (1 << i)) {
268 LLVMValueRef P = LLVMGetParam(main_function, i);
269 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
270 ac_add_attr_dereferenceable(P, UINT64_MAX);
271 }
272 else {
273 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
274 }
275 }
276
277 if (unsafe_math) {
278 /* These were copied from some LLVM test. */
279 LLVMAddTargetDependentFunctionAttr(main_function,
280 "less-precise-fpmad",
281 "true");
282 LLVMAddTargetDependentFunctionAttr(main_function,
283 "no-infs-fp-math",
284 "true");
285 LLVMAddTargetDependentFunctionAttr(main_function,
286 "no-nans-fp-math",
287 "true");
288 LLVMAddTargetDependentFunctionAttr(main_function,
289 "unsafe-fp-math",
290 "true");
291 }
292 return main_function;
293 }
294
295 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
296 {
297 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
298 CONST_ADDR_SPACE);
299 }
300
301 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
302 int idx,
303 LLVMTypeRef type)
304 {
305 LLVMValueRef offset;
306 LLVMValueRef ptr;
307 int addr_space;
308
309 offset = LLVMConstInt(ctx->i32, idx, false);
310
311 ptr = ctx->shared_memory;
312 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
313 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
314 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
315 return ptr;
316 }
317
318 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
319 {
320 if (t == ctx->f16 || t == ctx->i16)
321 return ctx->i16;
322 else if (t == ctx->f32 || t == ctx->i32)
323 return ctx->i32;
324 else if (t == ctx->f64 || t == ctx->i64)
325 return ctx->i64;
326 else
327 unreachable("Unhandled integer size");
328 }
329
330 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
331 {
332 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
333 LLVMTypeRef elem_type = LLVMGetElementType(t);
334 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
335 LLVMGetVectorSize(t));
336 }
337 return to_integer_type_scalar(ctx, t);
338 }
339
340 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
341 {
342 LLVMTypeRef type = LLVMTypeOf(v);
343 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
344 }
345
346 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
347 {
348 if (t == ctx->i16 || t == ctx->f16)
349 return ctx->f16;
350 else if (t == ctx->i32 || t == ctx->f32)
351 return ctx->f32;
352 else if (t == ctx->i64 || t == ctx->f64)
353 return ctx->f64;
354 else
355 unreachable("Unhandled float size");
356 }
357
358 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
359 {
360 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
361 LLVMTypeRef elem_type = LLVMGetElementType(t);
362 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
363 LLVMGetVectorSize(t));
364 }
365 return to_float_type_scalar(ctx, t);
366 }
367
368 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
369 {
370 LLVMTypeRef type = LLVMTypeOf(v);
371 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
372 }
373
374 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
375 {
376 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
377 type = LLVMGetElementType(type);
378
379 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
380 return LLVMGetIntTypeWidth(type);
381
382 if (type == ctx->f16)
383 return 16;
384 if (type == ctx->f32)
385 return 32;
386 if (type == ctx->f64)
387 return 64;
388
389 unreachable("Unhandled type kind in get_elem_bits");
390 }
391
392 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
393 LLVMValueRef param, unsigned rshift,
394 unsigned bitwidth)
395 {
396 LLVMValueRef value = param;
397 if (rshift)
398 value = LLVMBuildLShr(ctx->builder, value,
399 LLVMConstInt(ctx->i32, rshift, false), "");
400
401 if (rshift + bitwidth < 32) {
402 unsigned mask = (1 << bitwidth) - 1;
403 value = LLVMBuildAnd(ctx->builder, value,
404 LLVMConstInt(ctx->i32, mask, false), "");
405 }
406 return value;
407 }
408
409 static LLVMValueRef build_gep0(struct nir_to_llvm_context *ctx,
410 LLVMValueRef base_ptr, LLVMValueRef index)
411 {
412 LLVMValueRef indices[2] = {
413 ctx->i32zero,
414 index,
415 };
416 return LLVMBuildGEP(ctx->builder, base_ptr,
417 indices, 2, "");
418 }
419
420 static LLVMValueRef build_indexed_load(struct nir_to_llvm_context *ctx,
421 LLVMValueRef base_ptr, LLVMValueRef index,
422 bool uniform)
423 {
424 LLVMValueRef pointer;
425 pointer = build_gep0(ctx, base_ptr, index);
426 if (uniform)
427 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
428 return LLVMBuildLoad(ctx->builder, pointer, "");
429 }
430
431 static LLVMValueRef build_indexed_load_const(struct nir_to_llvm_context *ctx,
432 LLVMValueRef base_ptr, LLVMValueRef index)
433 {
434 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
435 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
436 return result;
437 }
438
439 static void build_tbuffer_store(struct nir_to_llvm_context *ctx,
440 LLVMValueRef rsrc,
441 LLVMValueRef vdata,
442 unsigned num_channels,
443 LLVMValueRef vaddr,
444 LLVMValueRef soffset,
445 unsigned inst_offset,
446 unsigned dfmt,
447 unsigned nfmt,
448 unsigned offen,
449 unsigned idxen,
450 unsigned glc,
451 unsigned slc,
452 unsigned tfe)
453 {
454 LLVMValueRef args[] = {
455 rsrc,
456 vdata,
457 LLVMConstInt(ctx->i32, num_channels, 0),
458 vaddr,
459 soffset,
460 LLVMConstInt(ctx->i32, inst_offset, 0),
461 LLVMConstInt(ctx->i32, dfmt, 0),
462 LLVMConstInt(ctx->i32, nfmt, 0),
463 LLVMConstInt(ctx->i32, offen, 0),
464 LLVMConstInt(ctx->i32, idxen, 0),
465 LLVMConstInt(ctx->i32, glc, 0),
466 LLVMConstInt(ctx->i32, slc, 0),
467 LLVMConstInt(ctx->i32, tfe, 0)
468 };
469
470 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
471 unsigned func = CLAMP(num_channels, 1, 3) - 1;
472 const char *types[] = {"i32", "v2i32", "v4i32"};
473 char name[256];
474 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
475
476 ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->voidt,
477 args, ARRAY_SIZE(args), 0);
478
479 }
480
481 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
482 {
483 ud_info->sgpr_idx = sgpr_idx;
484 ud_info->num_sgprs = num_sgprs;
485 ud_info->indirect = false;
486 ud_info->indirect_offset = 0;
487 }
488
489 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
490 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
491 {
492 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
493 }
494
495 #if 0
496 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
497 uint32_t indirect_offset)
498 {
499 ud_info->sgpr_idx = sgpr_idx;
500 ud_info->num_sgprs = num_sgprs;
501 ud_info->indirect = true;
502 ud_info->indirect_offset = indirect_offset;
503 }
504 #endif
505
506 static void create_function(struct nir_to_llvm_context *ctx)
507 {
508 LLVMTypeRef arg_types[23];
509 unsigned arg_idx = 0;
510 unsigned array_params_mask = 0;
511 unsigned sgpr_count = 0, user_sgpr_count;
512 unsigned i;
513 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
514 unsigned user_sgpr_idx;
515 bool need_push_constants;
516 bool need_ring_offsets = false;
517
518 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
519 if (ctx->stage == MESA_SHADER_GEOMETRY ||
520 ctx->stage == MESA_SHADER_VERTEX ||
521 ctx->is_gs_copy_shader)
522 need_ring_offsets = true;
523
524 need_push_constants = true;
525 if (!ctx->options->layout)
526 need_push_constants = false;
527 else if (!ctx->options->layout->push_constant_size &&
528 !ctx->options->layout->dynamic_offset_count)
529 need_push_constants = false;
530
531 if (need_ring_offsets && !ctx->options->supports_spill) {
532 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
533 }
534
535 /* 1 for each descriptor set */
536 for (unsigned i = 0; i < num_sets; ++i) {
537 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
538 array_params_mask |= (1 << arg_idx);
539 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
540 }
541 }
542
543 if (need_push_constants) {
544 /* 1 for push constants and dynamic descriptors */
545 array_params_mask |= (1 << arg_idx);
546 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
547 }
548
549 switch (ctx->stage) {
550 case MESA_SHADER_COMPUTE:
551 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
552 user_sgpr_count = arg_idx;
553 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
554 arg_types[arg_idx++] = ctx->i32;
555 sgpr_count = arg_idx;
556
557 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
558 break;
559 case MESA_SHADER_VERTEX:
560 if (!ctx->is_gs_copy_shader) {
561 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
562 arg_types[arg_idx++] = ctx->i32; // base vertex
563 arg_types[arg_idx++] = ctx->i32; // start instance
564 arg_types[arg_idx++] = ctx->i32; // draw index
565 }
566 user_sgpr_count = arg_idx;
567 if (ctx->options->key.vs.as_es)
568 arg_types[arg_idx++] = ctx->i32; //es2gs offset
569 sgpr_count = arg_idx;
570 arg_types[arg_idx++] = ctx->i32; // vertex id
571 if (!ctx->is_gs_copy_shader) {
572 arg_types[arg_idx++] = ctx->i32; // rel auto id
573 arg_types[arg_idx++] = ctx->i32; // vs prim id
574 arg_types[arg_idx++] = ctx->i32; // instance id
575 }
576 break;
577 case MESA_SHADER_GEOMETRY:
578 arg_types[arg_idx++] = ctx->i32; // gsvs stride
579 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
580 user_sgpr_count = arg_idx;
581 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
582 arg_types[arg_idx++] = ctx->i32; // wave id
583 sgpr_count = arg_idx;
584 arg_types[arg_idx++] = ctx->i32; // vtx0
585 arg_types[arg_idx++] = ctx->i32; // vtx1
586 arg_types[arg_idx++] = ctx->i32; // prim id
587 arg_types[arg_idx++] = ctx->i32; // vtx2
588 arg_types[arg_idx++] = ctx->i32; // vtx3
589 arg_types[arg_idx++] = ctx->i32; // vtx4
590 arg_types[arg_idx++] = ctx->i32; // vtx5
591 arg_types[arg_idx++] = ctx->i32; // GS instance id
592 break;
593 case MESA_SHADER_FRAGMENT:
594 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
595 user_sgpr_count = arg_idx;
596 arg_types[arg_idx++] = ctx->i32; /* prim mask */
597 sgpr_count = arg_idx;
598 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
599 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
600 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
601 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
602 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
603 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
604 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
605 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
606 arg_types[arg_idx++] = ctx->f32; /* pos x float */
607 arg_types[arg_idx++] = ctx->f32; /* pos y float */
608 arg_types[arg_idx++] = ctx->f32; /* pos z float */
609 arg_types[arg_idx++] = ctx->f32; /* pos w float */
610 arg_types[arg_idx++] = ctx->i32; /* front face */
611 arg_types[arg_idx++] = ctx->i32; /* ancillary */
612 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
613 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
614 break;
615 default:
616 unreachable("Shader stage not implemented");
617 }
618
619 ctx->main_function = create_llvm_function(
620 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
621 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
622 set_llvm_calling_convention(ctx->main_function, ctx->stage);
623
624 ctx->shader_info->num_input_sgprs = 0;
625 ctx->shader_info->num_input_vgprs = 0;
626
627 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
628 for (i = 0; i < user_sgpr_count; i++)
629 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
630
631 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
632 for (; i < sgpr_count; i++)
633 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
634
635 if (ctx->stage != MESA_SHADER_FRAGMENT)
636 for (; i < arg_idx; ++i)
637 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
638
639 arg_idx = 0;
640 user_sgpr_idx = 0;
641
642 if (ctx->options->supports_spill || need_ring_offsets) {
643 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
644 user_sgpr_idx += 2;
645 if (ctx->options->supports_spill) {
646 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
647 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
648 NULL, 0, AC_FUNC_ATTR_READNONE);
649 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
650 const_array(ctx->v16i8, 8), "");
651 } else
652 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
653 }
654
655 for (unsigned i = 0; i < num_sets; ++i) {
656 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
657 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
658 user_sgpr_idx += 2;
659 ctx->descriptor_sets[i] =
660 LLVMGetParam(ctx->main_function, arg_idx++);
661 } else
662 ctx->descriptor_sets[i] = NULL;
663 }
664
665 if (need_push_constants) {
666 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
667 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
668 user_sgpr_idx += 2;
669 }
670
671 switch (ctx->stage) {
672 case MESA_SHADER_COMPUTE:
673 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
674 user_sgpr_idx += 3;
675 ctx->num_work_groups =
676 LLVMGetParam(ctx->main_function, arg_idx++);
677 ctx->workgroup_ids =
678 LLVMGetParam(ctx->main_function, arg_idx++);
679 ctx->tg_size =
680 LLVMGetParam(ctx->main_function, arg_idx++);
681 ctx->local_invocation_ids =
682 LLVMGetParam(ctx->main_function, arg_idx++);
683 break;
684 case MESA_SHADER_VERTEX:
685 if (!ctx->is_gs_copy_shader) {
686 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
687 user_sgpr_idx += 2;
688 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
689 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
690 user_sgpr_idx += 3;
691 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
692 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
693 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
694 }
695 if (ctx->options->key.vs.as_es)
696 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
697 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
698 if (!ctx->is_gs_copy_shader) {
699 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
700 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
701 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
702 }
703 break;
704 case MESA_SHADER_GEOMETRY:
705 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
706 user_sgpr_idx += 2;
707 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
708 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
709 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
710 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
711 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
712 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
713 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
714 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
715 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
716 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
717 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
718 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
719 break;
720 case MESA_SHADER_FRAGMENT:
721 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
722 user_sgpr_idx += 2;
723 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
724 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
725 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
726 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
727 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
728 arg_idx++;
729 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
730 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
731 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
732 arg_idx++; /* line stipple */
733 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
734 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
735 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
736 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
737 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
738 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
739 break;
740 default:
741 unreachable("Shader stage not implemented");
742 }
743 }
744
745 static void setup_types(struct nir_to_llvm_context *ctx)
746 {
747 LLVMValueRef args[4];
748
749 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
750 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
751 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
752 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
753 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
754 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
755 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
756 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
757 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
758 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
759 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
760 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
761 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
762 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
763 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
764 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
765
766 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
767 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
768 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
769 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
770
771 args[0] = ctx->f32zero;
772 args[1] = ctx->f32zero;
773 args[2] = ctx->f32zero;
774 args[3] = ctx->f32one;
775 ctx->v4f32empty = LLVMConstVector(args, 4);
776
777 ctx->range_md_kind = LLVMGetMDKindIDInContext(ctx->context,
778 "range", 5);
779 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(ctx->context,
780 "invariant.load", 14);
781 ctx->uniform_md_kind =
782 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
783 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
784
785 args[0] = LLVMConstReal(ctx->f32, 2.5);
786 }
787
788 static int get_llvm_num_components(LLVMValueRef value)
789 {
790 LLVMTypeRef type = LLVMTypeOf(value);
791 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
792 ? LLVMGetVectorSize(type)
793 : 1;
794 return num_components;
795 }
796
797 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
798 LLVMValueRef value,
799 int index)
800 {
801 int count = get_llvm_num_components(value);
802
803 assert(index < count);
804 if (count == 1)
805 return value;
806
807 return LLVMBuildExtractElement(ctx->builder, value,
808 LLVMConstInt(ctx->i32, index, false), "");
809 }
810
811 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
812 LLVMValueRef value, unsigned count)
813 {
814 unsigned num_components = get_llvm_num_components(value);
815 if (count == num_components)
816 return value;
817
818 LLVMValueRef masks[] = {
819 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
820 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
821
822 if (count == 1)
823 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
824 "");
825
826 LLVMValueRef swizzle = LLVMConstVector(masks, count);
827 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
828 }
829
830 static void
831 build_store_values_extended(struct nir_to_llvm_context *ctx,
832 LLVMValueRef *values,
833 unsigned value_count,
834 unsigned value_stride,
835 LLVMValueRef vec)
836 {
837 LLVMBuilderRef builder = ctx->builder;
838 unsigned i;
839
840 if (value_count == 1) {
841 LLVMBuildStore(builder, vec, values[0]);
842 return;
843 }
844
845 for (i = 0; i < value_count; i++) {
846 LLVMValueRef ptr = values[i * value_stride];
847 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
848 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
849 LLVMBuildStore(builder, value, ptr);
850 }
851 }
852
853 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
854 nir_ssa_def *def)
855 {
856 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
857 if (def->num_components > 1) {
858 type = LLVMVectorType(type, def->num_components);
859 }
860 return type;
861 }
862
863 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
864 {
865 assert(src.is_ssa);
866 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
867 return (LLVMValueRef)entry->data;
868 }
869
870
871 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
872 struct nir_block *b)
873 {
874 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
875 return (LLVMBasicBlockRef)entry->data;
876 }
877
878 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
879 nir_alu_src src,
880 unsigned num_components)
881 {
882 LLVMValueRef value = get_src(ctx, src.src);
883 bool need_swizzle = false;
884
885 assert(value);
886 LLVMTypeRef type = LLVMTypeOf(value);
887 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
888 ? LLVMGetVectorSize(type)
889 : 1;
890
891 for (unsigned i = 0; i < num_components; ++i) {
892 assert(src.swizzle[i] < src_components);
893 if (src.swizzle[i] != i)
894 need_swizzle = true;
895 }
896
897 if (need_swizzle || num_components != src_components) {
898 LLVMValueRef masks[] = {
899 LLVMConstInt(ctx->i32, src.swizzle[0], false),
900 LLVMConstInt(ctx->i32, src.swizzle[1], false),
901 LLVMConstInt(ctx->i32, src.swizzle[2], false),
902 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
903
904 if (src_components > 1 && num_components == 1) {
905 value = LLVMBuildExtractElement(ctx->builder, value,
906 masks[0], "");
907 } else if (src_components == 1 && num_components > 1) {
908 LLVMValueRef values[] = {value, value, value, value};
909 value = ac_build_gather_values(&ctx->ac, values, num_components);
910 } else {
911 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
912 value = LLVMBuildShuffleVector(ctx->builder, value, value,
913 swizzle, "");
914 }
915 }
916 assert(!src.negate);
917 assert(!src.abs);
918 return value;
919 }
920
921 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
922 LLVMIntPredicate pred, LLVMValueRef src0,
923 LLVMValueRef src1)
924 {
925 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
926 return LLVMBuildSelect(ctx->builder, result,
927 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
928 LLVMConstInt(ctx->i32, 0, false), "");
929 }
930
931 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
932 LLVMRealPredicate pred, LLVMValueRef src0,
933 LLVMValueRef src1)
934 {
935 LLVMValueRef result;
936 src0 = to_float(ctx, src0);
937 src1 = to_float(ctx, src1);
938 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
939 return LLVMBuildSelect(ctx->builder, result,
940 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
941 LLVMConstInt(ctx->i32, 0, false), "");
942 }
943
944 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
945 const char *intrin,
946 LLVMTypeRef result_type,
947 LLVMValueRef src0)
948 {
949 char name[64];
950 LLVMValueRef params[] = {
951 to_float(ctx, src0),
952 };
953
954 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
955 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
956 }
957
958 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
959 const char *intrin,
960 LLVMTypeRef result_type,
961 LLVMValueRef src0, LLVMValueRef src1)
962 {
963 char name[64];
964 LLVMValueRef params[] = {
965 to_float(ctx, src0),
966 to_float(ctx, src1),
967 };
968
969 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
970 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
971 }
972
973 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
974 const char *intrin,
975 LLVMTypeRef result_type,
976 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
977 {
978 char name[64];
979 LLVMValueRef params[] = {
980 to_float(ctx, src0),
981 to_float(ctx, src1),
982 to_float(ctx, src2),
983 };
984
985 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
986 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
987 }
988
989 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
990 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
991 {
992 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
993 ctx->i32zero, "");
994 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
995 }
996
997 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
998 LLVMValueRef src0)
999 {
1000 LLVMValueRef params[2] = {
1001 src0,
1002
1003 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1004 * add special code to check for x=0. The reason is that
1005 * the LLVM behavior for x=0 is different from what we
1006 * need here.
1007 *
1008 * The hardware already implements the correct behavior.
1009 */
1010 LLVMConstInt(ctx->i32, 1, false),
1011 };
1012 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1013 }
1014
1015 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1016 LLVMValueRef src0)
1017 {
1018 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.flbit.i32",
1019 ctx->i32, &src0, 1,
1020 AC_FUNC_ATTR_READNONE);
1021
1022 /* The HW returns the last bit index from MSB, but NIR wants
1023 * the index from LSB. Invert it by doing "31 - msb". */
1024 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
1025 msb, "");
1026
1027 LLVMValueRef all_ones = LLVMConstInt(ctx->i32, -1, true);
1028 LLVMValueRef cond = LLVMBuildOr(ctx->builder,
1029 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
1030 src0, ctx->i32zero, ""),
1031 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
1032 src0, all_ones, ""), "");
1033
1034 return LLVMBuildSelect(ctx->builder, cond, all_ones, msb, "");
1035 }
1036
1037 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1038 LLVMValueRef src0)
1039 {
1040 LLVMValueRef args[2] = {
1041 src0,
1042 ctx->i32one,
1043 };
1044 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctlz.i32",
1045 ctx->i32, args, ARRAY_SIZE(args),
1046 AC_FUNC_ATTR_READNONE);
1047
1048 /* The HW returns the last bit index from MSB, but NIR wants
1049 * the index from LSB. Invert it by doing "31 - msb". */
1050 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
1051 msb, "");
1052
1053 return LLVMBuildSelect(ctx->builder,
1054 LLVMBuildICmp(ctx->builder, LLVMIntEQ, src0,
1055 ctx->i32zero, ""),
1056 LLVMConstInt(ctx->i32, -1, true), msb, "");
1057 }
1058
1059 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1060 LLVMIntPredicate pred,
1061 LLVMValueRef src0, LLVMValueRef src1)
1062 {
1063 return LLVMBuildSelect(ctx->builder,
1064 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1065 src0,
1066 src1, "");
1067
1068 }
1069 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1070 LLVMValueRef src0)
1071 {
1072 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1073 LLVMBuildNeg(ctx->builder, src0, ""));
1074 }
1075
1076 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1077 LLVMValueRef src0)
1078 {
1079 LLVMValueRef cmp, val;
1080
1081 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1082 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1083 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1084 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1085 return val;
1086 }
1087
1088 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1089 LLVMValueRef src0)
1090 {
1091 LLVMValueRef cmp, val;
1092
1093 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1094 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1095 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1096 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1097 return val;
1098 }
1099
1100 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1101 LLVMValueRef src0)
1102 {
1103 const char *intr = "llvm.floor.f32";
1104 LLVMValueRef fsrc0 = to_float(ctx, src0);
1105 LLVMValueRef params[] = {
1106 fsrc0,
1107 };
1108 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
1109 ctx->f32, params, 1,
1110 AC_FUNC_ATTR_READNONE);
1111 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1112 }
1113
1114 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1115 const char *intrin,
1116 LLVMValueRef src0, LLVMValueRef src1)
1117 {
1118 LLVMTypeRef ret_type;
1119 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1120 LLVMValueRef res;
1121 LLVMValueRef params[] = { src0, src1 };
1122 ret_type = LLVMStructTypeInContext(ctx->context, types,
1123 2, true);
1124
1125 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1126 params, 2, AC_FUNC_ATTR_READNONE);
1127
1128 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1129 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1130 return res;
1131 }
1132
1133 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1134 LLVMValueRef src0)
1135 {
1136 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1137 }
1138
1139 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1140 LLVMValueRef src0, LLVMValueRef src1)
1141 {
1142 LLVMValueRef dst64, result;
1143 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1144 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1145
1146 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1147 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1148 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1149 return result;
1150 }
1151
1152 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1153 LLVMValueRef src0, LLVMValueRef src1)
1154 {
1155 LLVMValueRef dst64, result;
1156 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1157 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1158
1159 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1160 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1161 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1162 return result;
1163 }
1164
1165 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1166 const char *intrin,
1167 LLVMValueRef srcs[3])
1168 {
1169 LLVMValueRef result;
1170 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1171 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1172
1173 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1174 return result;
1175 }
1176
1177 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1178 LLVMValueRef src0, LLVMValueRef src1,
1179 LLVMValueRef src2, LLVMValueRef src3)
1180 {
1181 LLVMValueRef bfi_args[3], result;
1182
1183 bfi_args[0] = LLVMBuildShl(ctx->builder,
1184 LLVMBuildSub(ctx->builder,
1185 LLVMBuildShl(ctx->builder,
1186 ctx->i32one,
1187 src3, ""),
1188 ctx->i32one, ""),
1189 src2, "");
1190 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1191 bfi_args[2] = src0;
1192
1193 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1194
1195 /* Calculate:
1196 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1197 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1198 */
1199 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1200 LLVMBuildAnd(ctx->builder, bfi_args[0],
1201 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1202
1203 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1204 return result;
1205 }
1206
1207 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1208 LLVMValueRef src0)
1209 {
1210 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1211 int i;
1212 LLVMValueRef comp[2];
1213
1214 src0 = to_float(ctx, src0);
1215 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1216 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1217 for (i = 0; i < 2; i++) {
1218 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1219 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1220 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1221 }
1222
1223 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1224 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1225
1226 return comp[0];
1227 }
1228
1229 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1230 LLVMValueRef src0)
1231 {
1232 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1233 LLVMValueRef temps[2], result, val;
1234 int i;
1235
1236 for (i = 0; i < 2; i++) {
1237 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1238 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1239 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1240 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1241 }
1242
1243 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1244 ctx->i32zero, "");
1245 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1246 ctx->i32one, "");
1247 return result;
1248 }
1249
1250 /**
1251 * Set range metadata on an instruction. This can only be used on load and
1252 * call instructions. If you know an instruction can only produce the values
1253 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1254 * \p lo is the minimum value inclusive.
1255 * \p hi is the maximum value exclusive.
1256 */
1257 static void set_range_metadata(struct nir_to_llvm_context *ctx,
1258 LLVMValueRef value, unsigned lo, unsigned hi)
1259 {
1260 LLVMValueRef range_md, md_args[2];
1261 LLVMTypeRef type = LLVMTypeOf(value);
1262 LLVMContextRef context = LLVMGetTypeContext(type);
1263
1264 md_args[0] = LLVMConstInt(type, lo, false);
1265 md_args[1] = LLVMConstInt(type, hi, false);
1266 range_md = LLVMMDNodeInContext(context, md_args, 2);
1267 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1268 }
1269
1270 static LLVMValueRef get_thread_id(struct nir_to_llvm_context *ctx)
1271 {
1272 LLVMValueRef tid;
1273 LLVMValueRef tid_args[2];
1274 tid_args[0] = LLVMConstInt(ctx->i32, 0xffffffff, false);
1275 tid_args[1] = ctx->i32zero;
1276 tid_args[1] = ac_emit_llvm_intrinsic(&ctx->ac,
1277 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1278 tid_args, 2, AC_FUNC_ATTR_READNONE);
1279
1280 tid = ac_emit_llvm_intrinsic(&ctx->ac,
1281 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1282 tid_args, 2, AC_FUNC_ATTR_READNONE);
1283 set_range_metadata(ctx, tid, 0, 64);
1284 return tid;
1285 }
1286
1287 /*
1288 * SI implements derivatives using the local data store (LDS)
1289 * All writes to the LDS happen in all executing threads at
1290 * the same time. TID is the Thread ID for the current
1291 * thread and is a value between 0 and 63, representing
1292 * the thread's position in the wavefront.
1293 *
1294 * For the pixel shader threads are grouped into quads of four pixels.
1295 * The TIDs of the pixels of a quad are:
1296 *
1297 * +------+------+
1298 * |4n + 0|4n + 1|
1299 * +------+------+
1300 * |4n + 2|4n + 3|
1301 * +------+------+
1302 *
1303 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
1304 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
1305 * the current pixel's column, and masking with 0xfffffffe yields the TID
1306 * of the left pixel of the current pixel's row.
1307 *
1308 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
1309 * adding 2 yields the TID of the pixel below the top pixel.
1310 */
1311 /* masks for thread ID. */
1312 #define TID_MASK_TOP_LEFT 0xfffffffc
1313 #define TID_MASK_TOP 0xfffffffd
1314 #define TID_MASK_LEFT 0xfffffffe
1315 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1316 nir_op op,
1317 LLVMValueRef src0)
1318 {
1319 LLVMValueRef tl, trbl, result;
1320 LLVMValueRef tl_tid, trbl_tid;
1321 LLVMValueRef args[2];
1322 LLVMValueRef thread_id;
1323 unsigned mask;
1324 int idx;
1325 ctx->has_ddxy = true;
1326
1327 if (!ctx->lds && !ctx->has_ds_bpermute)
1328 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1329 LLVMArrayType(ctx->i32, 64),
1330 "ddxy_lds", LOCAL_ADDR_SPACE);
1331
1332 thread_id = get_thread_id(ctx);
1333 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1334 mask = TID_MASK_LEFT;
1335 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1336 mask = TID_MASK_TOP;
1337 else
1338 mask = TID_MASK_TOP_LEFT;
1339
1340 tl_tid = LLVMBuildAnd(ctx->builder, thread_id,
1341 LLVMConstInt(ctx->i32, mask, false), "");
1342 /* for DDX we want to next X pixel, DDY next Y pixel. */
1343 if (op == nir_op_fddx_fine ||
1344 op == nir_op_fddx_coarse ||
1345 op == nir_op_fddx)
1346 idx = 1;
1347 else
1348 idx = 2;
1349
1350 trbl_tid = LLVMBuildAdd(ctx->builder, tl_tid,
1351 LLVMConstInt(ctx->i32, idx, false), "");
1352
1353 if (ctx->has_ds_bpermute) {
1354 args[0] = LLVMBuildMul(ctx->builder, tl_tid,
1355 LLVMConstInt(ctx->i32, 4, false), "");
1356 args[1] = src0;
1357 tl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1358 ctx->i32, args, 2,
1359 AC_FUNC_ATTR_READNONE);
1360
1361 args[0] = LLVMBuildMul(ctx->builder, trbl_tid,
1362 LLVMConstInt(ctx->i32, 4, false), "");
1363 trbl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1364 ctx->i32, args, 2,
1365 AC_FUNC_ATTR_READNONE);
1366 } else {
1367 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1368
1369 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
1370 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
1371 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
1372
1373 LLVMBuildStore(ctx->builder, src0, store_ptr);
1374 tl = LLVMBuildLoad(ctx->builder, load_ptr0, "");
1375 trbl = LLVMBuildLoad(ctx->builder, load_ptr1, "");
1376 }
1377 tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
1378 trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
1379 result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
1380 return result;
1381 }
1382
1383 /*
1384 * this takes an I,J coordinate pair,
1385 * and works out the X and Y derivatives.
1386 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1387 */
1388 static LLVMValueRef emit_ddxy_interp(
1389 struct nir_to_llvm_context *ctx,
1390 LLVMValueRef interp_ij)
1391 {
1392 LLVMValueRef result[4], a;
1393 unsigned i;
1394
1395 for (i = 0; i < 2; i++) {
1396 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1397 LLVMConstInt(ctx->i32, i, false), "");
1398 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1399 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1400 }
1401 return ac_build_gather_values(&ctx->ac, result, 4);
1402 }
1403
1404 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1405 {
1406 LLVMValueRef src[4], result = NULL;
1407 unsigned num_components = instr->dest.dest.ssa.num_components;
1408 unsigned src_components;
1409 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1410
1411 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1412 switch (instr->op) {
1413 case nir_op_vec2:
1414 case nir_op_vec3:
1415 case nir_op_vec4:
1416 src_components = 1;
1417 break;
1418 case nir_op_pack_half_2x16:
1419 src_components = 2;
1420 break;
1421 case nir_op_unpack_half_2x16:
1422 src_components = 1;
1423 break;
1424 default:
1425 src_components = num_components;
1426 break;
1427 }
1428 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1429 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1430
1431 switch (instr->op) {
1432 case nir_op_fmov:
1433 case nir_op_imov:
1434 result = src[0];
1435 break;
1436 case nir_op_fneg:
1437 src[0] = to_float(ctx, src[0]);
1438 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1439 break;
1440 case nir_op_ineg:
1441 result = LLVMBuildNeg(ctx->builder, src[0], "");
1442 break;
1443 case nir_op_inot:
1444 result = LLVMBuildNot(ctx->builder, src[0], "");
1445 break;
1446 case nir_op_iadd:
1447 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1448 break;
1449 case nir_op_fadd:
1450 src[0] = to_float(ctx, src[0]);
1451 src[1] = to_float(ctx, src[1]);
1452 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1453 break;
1454 case nir_op_fsub:
1455 src[0] = to_float(ctx, src[0]);
1456 src[1] = to_float(ctx, src[1]);
1457 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1458 break;
1459 case nir_op_isub:
1460 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1461 break;
1462 case nir_op_imul:
1463 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1464 break;
1465 case nir_op_imod:
1466 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1467 break;
1468 case nir_op_umod:
1469 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1470 break;
1471 case nir_op_fmod:
1472 src[0] = to_float(ctx, src[0]);
1473 src[1] = to_float(ctx, src[1]);
1474 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1475 result = emit_intrin_1f_param(ctx, "llvm.floor",
1476 to_float_type(ctx, def_type), result);
1477 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1478 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1479 break;
1480 case nir_op_frem:
1481 src[0] = to_float(ctx, src[0]);
1482 src[1] = to_float(ctx, src[1]);
1483 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1484 break;
1485 case nir_op_irem:
1486 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1487 break;
1488 case nir_op_idiv:
1489 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1490 break;
1491 case nir_op_udiv:
1492 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1493 break;
1494 case nir_op_fmul:
1495 src[0] = to_float(ctx, src[0]);
1496 src[1] = to_float(ctx, src[1]);
1497 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1498 break;
1499 case nir_op_fdiv:
1500 src[0] = to_float(ctx, src[0]);
1501 src[1] = to_float(ctx, src[1]);
1502 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1503 break;
1504 case nir_op_frcp:
1505 src[0] = to_float(ctx, src[0]);
1506 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1507 break;
1508 case nir_op_iand:
1509 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1510 break;
1511 case nir_op_ior:
1512 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1513 break;
1514 case nir_op_ixor:
1515 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1516 break;
1517 case nir_op_ishl:
1518 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1519 break;
1520 case nir_op_ishr:
1521 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1522 break;
1523 case nir_op_ushr:
1524 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1525 break;
1526 case nir_op_ilt:
1527 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1528 break;
1529 case nir_op_ine:
1530 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1531 break;
1532 case nir_op_ieq:
1533 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1534 break;
1535 case nir_op_ige:
1536 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1537 break;
1538 case nir_op_ult:
1539 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1540 break;
1541 case nir_op_uge:
1542 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1543 break;
1544 case nir_op_feq:
1545 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1546 break;
1547 case nir_op_fne:
1548 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1549 break;
1550 case nir_op_flt:
1551 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1552 break;
1553 case nir_op_fge:
1554 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1555 break;
1556 case nir_op_fabs:
1557 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1558 to_float_type(ctx, def_type), src[0]);
1559 break;
1560 case nir_op_iabs:
1561 result = emit_iabs(ctx, src[0]);
1562 break;
1563 case nir_op_imax:
1564 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1565 break;
1566 case nir_op_imin:
1567 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1568 break;
1569 case nir_op_umax:
1570 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1571 break;
1572 case nir_op_umin:
1573 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1574 break;
1575 case nir_op_isign:
1576 result = emit_isign(ctx, src[0]);
1577 break;
1578 case nir_op_fsign:
1579 src[0] = to_float(ctx, src[0]);
1580 result = emit_fsign(ctx, src[0]);
1581 break;
1582 case nir_op_ffloor:
1583 result = emit_intrin_1f_param(ctx, "llvm.floor",
1584 to_float_type(ctx, def_type), src[0]);
1585 break;
1586 case nir_op_ftrunc:
1587 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1588 to_float_type(ctx, def_type), src[0]);
1589 break;
1590 case nir_op_fceil:
1591 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1592 to_float_type(ctx, def_type), src[0]);
1593 break;
1594 case nir_op_fround_even:
1595 result = emit_intrin_1f_param(ctx, "llvm.rint",
1596 to_float_type(ctx, def_type),src[0]);
1597 break;
1598 case nir_op_ffract:
1599 result = emit_ffract(ctx, src[0]);
1600 break;
1601 case nir_op_fsin:
1602 result = emit_intrin_1f_param(ctx, "llvm.sin",
1603 to_float_type(ctx, def_type), src[0]);
1604 break;
1605 case nir_op_fcos:
1606 result = emit_intrin_1f_param(ctx, "llvm.cos",
1607 to_float_type(ctx, def_type), src[0]);
1608 break;
1609 case nir_op_fsqrt:
1610 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1611 to_float_type(ctx, def_type), src[0]);
1612 break;
1613 case nir_op_fexp2:
1614 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1615 to_float_type(ctx, def_type), src[0]);
1616 break;
1617 case nir_op_flog2:
1618 result = emit_intrin_1f_param(ctx, "llvm.log2",
1619 to_float_type(ctx, def_type), src[0]);
1620 break;
1621 case nir_op_frsq:
1622 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1623 to_float_type(ctx, def_type), src[0]);
1624 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1625 break;
1626 case nir_op_fpow:
1627 result = emit_intrin_2f_param(ctx, "llvm.pow",
1628 to_float_type(ctx, def_type), src[0], src[1]);
1629 break;
1630 case nir_op_fmax:
1631 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1632 to_float_type(ctx, def_type), src[0], src[1]);
1633 break;
1634 case nir_op_fmin:
1635 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1636 to_float_type(ctx, def_type), src[0], src[1]);
1637 break;
1638 case nir_op_ffma:
1639 result = emit_intrin_3f_param(ctx, "llvm.fma",
1640 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1641 break;
1642 case nir_op_ibitfield_extract:
1643 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1644 break;
1645 case nir_op_ubitfield_extract:
1646 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1647 break;
1648 case nir_op_bitfield_insert:
1649 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1650 break;
1651 case nir_op_bitfield_reverse:
1652 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1653 break;
1654 case nir_op_bit_count:
1655 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1656 break;
1657 case nir_op_vec2:
1658 case nir_op_vec3:
1659 case nir_op_vec4:
1660 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1661 src[i] = to_integer(ctx, src[i]);
1662 result = ac_build_gather_values(&ctx->ac, src, num_components);
1663 break;
1664 case nir_op_d2i:
1665 case nir_op_f2i:
1666 src[0] = to_float(ctx, src[0]);
1667 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1668 break;
1669 case nir_op_d2u:
1670 case nir_op_f2u:
1671 src[0] = to_float(ctx, src[0]);
1672 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1673 break;
1674 case nir_op_i2d:
1675 case nir_op_i2f:
1676 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1677 break;
1678 case nir_op_u2d:
1679 case nir_op_u2f:
1680 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1681 break;
1682 case nir_op_f2d:
1683 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1684 break;
1685 case nir_op_d2f:
1686 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1687 break;
1688 case nir_op_bcsel:
1689 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1690 break;
1691 case nir_op_find_lsb:
1692 result = emit_find_lsb(ctx, src[0]);
1693 break;
1694 case nir_op_ufind_msb:
1695 result = emit_ufind_msb(ctx, src[0]);
1696 break;
1697 case nir_op_ifind_msb:
1698 result = emit_ifind_msb(ctx, src[0]);
1699 break;
1700 case nir_op_uadd_carry:
1701 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1702 break;
1703 case nir_op_usub_borrow:
1704 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1705 break;
1706 case nir_op_b2f:
1707 result = emit_b2f(ctx, src[0]);
1708 break;
1709 case nir_op_fquantize2f16:
1710 src[0] = to_float(ctx, src[0]);
1711 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1712 /* need to convert back up to f32 */
1713 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1714 break;
1715 case nir_op_umul_high:
1716 result = emit_umul_high(ctx, src[0], src[1]);
1717 break;
1718 case nir_op_imul_high:
1719 result = emit_imul_high(ctx, src[0], src[1]);
1720 break;
1721 case nir_op_pack_half_2x16:
1722 result = emit_pack_half_2x16(ctx, src[0]);
1723 break;
1724 case nir_op_unpack_half_2x16:
1725 result = emit_unpack_half_2x16(ctx, src[0]);
1726 break;
1727 case nir_op_fddx:
1728 case nir_op_fddy:
1729 case nir_op_fddx_fine:
1730 case nir_op_fddy_fine:
1731 case nir_op_fddx_coarse:
1732 case nir_op_fddy_coarse:
1733 result = emit_ddxy(ctx, instr->op, src[0]);
1734 break;
1735 default:
1736 fprintf(stderr, "Unknown NIR alu instr: ");
1737 nir_print_instr(&instr->instr, stderr);
1738 fprintf(stderr, "\n");
1739 abort();
1740 }
1741
1742 if (result) {
1743 assert(instr->dest.dest.is_ssa);
1744 result = to_integer(ctx, result);
1745 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1746 result);
1747 }
1748 }
1749
1750 static void visit_load_const(struct nir_to_llvm_context *ctx,
1751 nir_load_const_instr *instr)
1752 {
1753 LLVMValueRef values[4], value = NULL;
1754 LLVMTypeRef element_type =
1755 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1756
1757 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1758 switch (instr->def.bit_size) {
1759 case 32:
1760 values[i] = LLVMConstInt(element_type,
1761 instr->value.u32[i], false);
1762 break;
1763 case 64:
1764 values[i] = LLVMConstInt(element_type,
1765 instr->value.u64[i], false);
1766 break;
1767 default:
1768 fprintf(stderr,
1769 "unsupported nir load_const bit_size: %d\n",
1770 instr->def.bit_size);
1771 abort();
1772 }
1773 }
1774 if (instr->def.num_components > 1) {
1775 value = LLVMConstVector(values, instr->def.num_components);
1776 } else
1777 value = values[0];
1778
1779 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1780 }
1781
1782 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1783 LLVMTypeRef type)
1784 {
1785 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1786 return LLVMBuildBitCast(ctx->builder, ptr,
1787 LLVMPointerType(type, addr_space), "");
1788 }
1789
1790 static LLVMValueRef
1791 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1792 {
1793 LLVMValueRef size =
1794 LLVMBuildExtractElement(ctx->builder, descriptor,
1795 LLVMConstInt(ctx->i32, 2, false), "");
1796
1797 /* VI only */
1798 if (ctx->options->chip_class >= VI && in_elements) {
1799 /* On VI, the descriptor contains the size in bytes,
1800 * but TXQ must return the size in elements.
1801 * The stride is always non-zero for resources using TXQ.
1802 */
1803 LLVMValueRef stride =
1804 LLVMBuildExtractElement(ctx->builder, descriptor,
1805 LLVMConstInt(ctx->i32, 1, false), "");
1806 stride = LLVMBuildLShr(ctx->builder, stride,
1807 LLVMConstInt(ctx->i32, 16, false), "");
1808 stride = LLVMBuildAnd(ctx->builder, stride,
1809 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1810
1811 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1812 }
1813 return size;
1814 }
1815
1816 /**
1817 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1818 * intrinsic names).
1819 */
1820 static void build_int_type_name(
1821 LLVMTypeRef type,
1822 char *buf, unsigned bufsize)
1823 {
1824 assert(bufsize >= 6);
1825
1826 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1827 snprintf(buf, bufsize, "v%ui32",
1828 LLVMGetVectorSize(type));
1829 else
1830 strcpy(buf, "i32");
1831 }
1832
1833 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1834 struct ac_tex_info *tinfo,
1835 nir_tex_instr *instr,
1836 const char *intr_name,
1837 unsigned coord_vgpr_index)
1838 {
1839 LLVMValueRef coord = tinfo->args[0];
1840 LLVMValueRef half_texel[2];
1841 int c;
1842
1843 //TODO Rect
1844 {
1845 LLVMValueRef txq_args[10];
1846 int txq_arg_count = 0;
1847 LLVMValueRef size;
1848 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1849 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1850 txq_args[txq_arg_count++] = tinfo->args[1];
1851 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1852 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1853 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1854 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1855 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1856 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1857 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1858 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1859 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1860 txq_args, txq_arg_count,
1861 AC_FUNC_ATTR_READNONE);
1862
1863 for (c = 0; c < 2; c++) {
1864 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1865 LLVMConstInt(ctx->i32, c, false), "");
1866 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1867 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1868 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1869 LLVMConstReal(ctx->f32, -0.5), "");
1870 }
1871 }
1872
1873 for (c = 0; c < 2; c++) {
1874 LLVMValueRef tmp;
1875 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1876 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1877 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1878 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1879 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1880 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1881 }
1882
1883 tinfo->args[0] = coord;
1884 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1885 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1886
1887 }
1888
1889 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1890 nir_tex_instr *instr,
1891 struct ac_tex_info *tinfo)
1892 {
1893 const char *name = "llvm.SI.image.sample";
1894 const char *infix = "";
1895 char intr_name[127];
1896 char type[64];
1897 bool is_shadow = instr->is_shadow;
1898 bool has_offset = tinfo->has_offset;
1899 switch (instr->op) {
1900 case nir_texop_txf:
1901 case nir_texop_txf_ms:
1902 case nir_texop_samples_identical:
1903 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1904 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1905 "llvm.SI.image.load.mip";
1906 is_shadow = false;
1907 has_offset = false;
1908 break;
1909 case nir_texop_txb:
1910 infix = ".b";
1911 break;
1912 case nir_texop_txl:
1913 infix = ".l";
1914 break;
1915 case nir_texop_txs:
1916 name = "llvm.SI.getresinfo";
1917 break;
1918 case nir_texop_query_levels:
1919 name = "llvm.SI.getresinfo";
1920 break;
1921 case nir_texop_tex:
1922 if (ctx->stage != MESA_SHADER_FRAGMENT)
1923 infix = ".lz";
1924 break;
1925 case nir_texop_txd:
1926 infix = ".d";
1927 break;
1928 case nir_texop_tg4:
1929 name = "llvm.SI.gather4";
1930 infix = ".lz";
1931 break;
1932 case nir_texop_lod:
1933 name = "llvm.SI.getlod";
1934 is_shadow = false;
1935 has_offset = false;
1936 break;
1937 default:
1938 break;
1939 }
1940
1941 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1942 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1943 has_offset ? ".o" : "", type);
1944
1945 if (instr->op == nir_texop_tg4) {
1946 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1947 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1948 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1949 (int)has_offset + (int)is_shadow);
1950 }
1951 }
1952 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1953 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1954
1955 }
1956
1957 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1958 nir_intrinsic_instr *instr)
1959 {
1960 LLVMValueRef index = get_src(ctx, instr->src[0]);
1961 unsigned desc_set = nir_intrinsic_desc_set(instr);
1962 unsigned binding = nir_intrinsic_binding(instr);
1963 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1964 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1965 unsigned base_offset = layout->binding[binding].offset;
1966 LLVMValueRef offset, stride;
1967
1968 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1969 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1970 desc_ptr = ctx->push_constants;
1971 base_offset = ctx->options->layout->push_constant_size;
1972 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1973 stride = LLVMConstInt(ctx->i32, 16, false);
1974 } else
1975 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1976
1977 offset = LLVMConstInt(ctx->i32, base_offset, false);
1978 index = LLVMBuildMul(ctx->builder, index, stride, "");
1979 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1980
1981 desc_ptr = build_gep0(ctx, desc_ptr, offset);
1982 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1983 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1984
1985 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1986 }
1987
1988 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1989 nir_intrinsic_instr *instr)
1990 {
1991 LLVMValueRef ptr, addr;
1992
1993 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1994 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1995
1996 ptr = build_gep0(ctx, ctx->push_constants, addr);
1997 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1998
1999 return LLVMBuildLoad(ctx->builder, ptr, "");
2000 }
2001
2002 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2003 nir_intrinsic_instr *instr)
2004 {
2005 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2006
2007 return get_buffer_size(ctx, desc, false);
2008 }
2009 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2010 nir_intrinsic_instr *instr)
2011 {
2012 const char *store_name;
2013 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2014 LLVMTypeRef data_type = ctx->f32;
2015 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2016 int components_32bit = elem_size_mult * instr->num_components;
2017 unsigned writemask = nir_intrinsic_write_mask(instr);
2018 LLVMValueRef base_data, base_offset;
2019 LLVMValueRef params[6];
2020
2021 if (ctx->stage == MESA_SHADER_FRAGMENT)
2022 ctx->shader_info->fs.writes_memory = true;
2023
2024 params[1] = get_src(ctx, instr->src[1]);
2025 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2026 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2027 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2028
2029 if (components_32bit > 1)
2030 data_type = LLVMVectorType(ctx->f32, components_32bit);
2031
2032 base_data = to_float(ctx, src_data);
2033 base_data = trim_vector(ctx, base_data, instr->num_components);
2034 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2035 data_type, "");
2036 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2037 while (writemask) {
2038 int start, count;
2039 LLVMValueRef data;
2040 LLVMValueRef offset;
2041 LLVMValueRef tmp;
2042 u_bit_scan_consecutive_range(&writemask, &start, &count);
2043
2044 /* Due to an LLVM limitation, split 3-element writes
2045 * into a 2-element and a 1-element write. */
2046 if (count == 3) {
2047 writemask |= 1 << (start + 2);
2048 count = 2;
2049 }
2050
2051 start *= elem_size_mult;
2052 count *= elem_size_mult;
2053
2054 if (count > 4) {
2055 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2056 count = 4;
2057 }
2058
2059 if (count == 4) {
2060 store_name = "llvm.amdgcn.buffer.store.v4f32";
2061 data = base_data;
2062 } else if (count == 2) {
2063 tmp = LLVMBuildExtractElement(ctx->builder,
2064 base_data, LLVMConstInt(ctx->i32, start, false), "");
2065 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2066 ctx->i32zero, "");
2067
2068 tmp = LLVMBuildExtractElement(ctx->builder,
2069 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2070 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2071 ctx->i32one, "");
2072 store_name = "llvm.amdgcn.buffer.store.v2f32";
2073
2074 } else {
2075 assert(count == 1);
2076 if (get_llvm_num_components(base_data) > 1)
2077 data = LLVMBuildExtractElement(ctx->builder, base_data,
2078 LLVMConstInt(ctx->i32, start, false), "");
2079 else
2080 data = base_data;
2081 store_name = "llvm.amdgcn.buffer.store.f32";
2082 }
2083
2084 offset = base_offset;
2085 if (start != 0) {
2086 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2087 }
2088 params[0] = data;
2089 params[3] = offset;
2090 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
2091 ctx->voidt, params, 6, 0);
2092 }
2093 }
2094
2095 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2096 nir_intrinsic_instr *instr)
2097 {
2098 const char *name;
2099 LLVMValueRef params[6];
2100 int arg_count = 0;
2101 if (ctx->stage == MESA_SHADER_FRAGMENT)
2102 ctx->shader_info->fs.writes_memory = true;
2103
2104 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2105 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2106 }
2107 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2108 params[arg_count++] = get_src(ctx, instr->src[0]);
2109 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2110 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2111 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2112
2113 switch (instr->intrinsic) {
2114 case nir_intrinsic_ssbo_atomic_add:
2115 name = "llvm.amdgcn.buffer.atomic.add";
2116 break;
2117 case nir_intrinsic_ssbo_atomic_imin:
2118 name = "llvm.amdgcn.buffer.atomic.smin";
2119 break;
2120 case nir_intrinsic_ssbo_atomic_umin:
2121 name = "llvm.amdgcn.buffer.atomic.umin";
2122 break;
2123 case nir_intrinsic_ssbo_atomic_imax:
2124 name = "llvm.amdgcn.buffer.atomic.smax";
2125 break;
2126 case nir_intrinsic_ssbo_atomic_umax:
2127 name = "llvm.amdgcn.buffer.atomic.umax";
2128 break;
2129 case nir_intrinsic_ssbo_atomic_and:
2130 name = "llvm.amdgcn.buffer.atomic.and";
2131 break;
2132 case nir_intrinsic_ssbo_atomic_or:
2133 name = "llvm.amdgcn.buffer.atomic.or";
2134 break;
2135 case nir_intrinsic_ssbo_atomic_xor:
2136 name = "llvm.amdgcn.buffer.atomic.xor";
2137 break;
2138 case nir_intrinsic_ssbo_atomic_exchange:
2139 name = "llvm.amdgcn.buffer.atomic.swap";
2140 break;
2141 case nir_intrinsic_ssbo_atomic_comp_swap:
2142 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2143 break;
2144 default:
2145 abort();
2146 }
2147
2148 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2149 }
2150
2151 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2152 nir_intrinsic_instr *instr)
2153 {
2154 LLVMValueRef results[2];
2155 int load_components;
2156 int num_components = instr->num_components;
2157 if (instr->dest.ssa.bit_size == 64)
2158 num_components *= 2;
2159
2160 for (int i = 0; i < num_components; i += load_components) {
2161 load_components = MIN2(num_components - i, 4);
2162 const char *load_name;
2163 LLVMTypeRef data_type = ctx->f32;
2164 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2165 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2166
2167 if (load_components == 3)
2168 data_type = LLVMVectorType(ctx->f32, 4);
2169 else if (load_components > 1)
2170 data_type = LLVMVectorType(ctx->f32, load_components);
2171
2172 if (load_components >= 3)
2173 load_name = "llvm.amdgcn.buffer.load.v4f32";
2174 else if (load_components == 2)
2175 load_name = "llvm.amdgcn.buffer.load.v2f32";
2176 else if (load_components == 1)
2177 load_name = "llvm.amdgcn.buffer.load.f32";
2178 else
2179 unreachable("unhandled number of components");
2180
2181 LLVMValueRef params[] = {
2182 get_src(ctx, instr->src[0]),
2183 LLVMConstInt(ctx->i32, 0, false),
2184 offset,
2185 LLVMConstInt(ctx->i1, 0, false),
2186 LLVMConstInt(ctx->i1, 0, false),
2187 };
2188
2189 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2190
2191 }
2192
2193 LLVMValueRef ret = results[0];
2194 if (num_components > 4 || num_components == 3) {
2195 LLVMValueRef masks[] = {
2196 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2197 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2198 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2199 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2200 };
2201
2202 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2203 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2204 results[num_components > 4 ? 1 : 0], swizzle, "");
2205 }
2206
2207 return LLVMBuildBitCast(ctx->builder, ret,
2208 get_def_type(ctx, &instr->dest.ssa), "");
2209 }
2210
2211 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2212 nir_intrinsic_instr *instr)
2213 {
2214 LLVMValueRef results[8], ret;
2215 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2216 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2217 int num_components = instr->num_components;
2218
2219 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2220
2221 if (instr->dest.ssa.bit_size == 64)
2222 num_components *= 2;
2223
2224 for (unsigned i = 0; i < num_components; ++i) {
2225 LLVMValueRef params[] = {
2226 rsrc,
2227 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2228 offset, "")
2229 };
2230 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2231 params, 2, AC_FUNC_ATTR_READNONE);
2232 }
2233
2234
2235 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2236 return LLVMBuildBitCast(ctx->builder, ret,
2237 get_def_type(ctx, &instr->dest.ssa), "");
2238 }
2239
2240 static void
2241 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2242 bool vs_in, unsigned *vertex_index_out,
2243 unsigned *const_out, LLVMValueRef *indir_out)
2244 {
2245 unsigned const_offset = 0;
2246 LLVMValueRef offset = NULL;
2247
2248 if (vertex_index_out != NULL) {
2249 tail = tail->child;
2250 nir_deref_array *deref_array = nir_deref_as_array(tail);
2251 *vertex_index_out = deref_array->base_offset;
2252 }
2253
2254 while (tail->child != NULL) {
2255 const struct glsl_type *parent_type = tail->type;
2256 tail = tail->child;
2257
2258 if (tail->deref_type == nir_deref_type_array) {
2259 nir_deref_array *deref_array = nir_deref_as_array(tail);
2260 LLVMValueRef index, stride, local_offset;
2261 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2262
2263 const_offset += size * deref_array->base_offset;
2264 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2265 continue;
2266
2267 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2268 index = get_src(ctx, deref_array->indirect);
2269 stride = LLVMConstInt(ctx->i32, size, 0);
2270 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2271
2272 if (offset)
2273 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2274 else
2275 offset = local_offset;
2276 } else if (tail->deref_type == nir_deref_type_struct) {
2277 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2278
2279 for (unsigned i = 0; i < deref_struct->index; i++) {
2280 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2281 const_offset += glsl_count_attribute_slots(ft, vs_in);
2282 }
2283 } else
2284 unreachable("unsupported deref type");
2285
2286 }
2287
2288 if (const_offset && offset)
2289 offset = LLVMBuildAdd(ctx->builder, offset,
2290 LLVMConstInt(ctx->i32, const_offset, 0),
2291 "");
2292
2293 *const_out = const_offset;
2294 *indir_out = offset;
2295 }
2296
2297 static LLVMValueRef
2298 load_gs_input(struct nir_to_llvm_context *ctx,
2299 nir_intrinsic_instr *instr)
2300 {
2301 LLVMValueRef indir_index, vtx_offset;
2302 unsigned const_index;
2303 LLVMValueRef args[9];
2304 unsigned param, vtx_offset_param;
2305 LLVMValueRef value[4], result;
2306 unsigned vertex_index;
2307 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2308 false, &vertex_index,
2309 &const_index, &indir_index);
2310 vtx_offset_param = vertex_index;
2311 assert(vtx_offset_param < 6);
2312 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2313 LLVMConstInt(ctx->i32, 4, false), "");
2314
2315 for (unsigned i = 0; i < instr->num_components; i++) {
2316 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2317 args[0] = ctx->esgs_ring;
2318 args[1] = vtx_offset;
2319 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i) * 256, false);
2320 args[3] = ctx->i32zero;
2321 args[4] = ctx->i32one; /* OFFEN */
2322 args[5] = ctx->i32zero; /* IDXEN */
2323 args[6] = ctx->i32one; /* GLC */
2324 args[7] = ctx->i32zero; /* SLC */
2325 args[8] = ctx->i32zero; /* TFE */
2326
2327 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2328 ctx->i32, args, 9, AC_FUNC_ATTR_READONLY);
2329 }
2330 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2331
2332 return result;
2333 }
2334
2335 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2336 nir_intrinsic_instr *instr)
2337 {
2338 LLVMValueRef values[8];
2339 int idx = instr->variables[0]->var->data.driver_location;
2340 int ve = instr->dest.ssa.num_components;
2341 LLVMValueRef indir_index;
2342 LLVMValueRef ret;
2343 unsigned const_index;
2344 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2345 instr->variables[0]->var->data.mode == nir_var_shader_in;
2346 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2347 &const_index, &indir_index);
2348
2349 if (instr->dest.ssa.bit_size == 64)
2350 ve *= 2;
2351
2352 switch (instr->variables[0]->var->data.mode) {
2353 case nir_var_shader_in:
2354 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2355 return load_gs_input(ctx, instr);
2356 }
2357 for (unsigned chan = 0; chan < ve; chan++) {
2358 if (indir_index) {
2359 unsigned count = glsl_count_attribute_slots(
2360 instr->variables[0]->var->type,
2361 ctx->stage == MESA_SHADER_VERTEX);
2362 count -= chan / 4;
2363 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2364 &ctx->ac, ctx->inputs + idx + chan, count,
2365 4, false);
2366
2367 values[chan] = LLVMBuildExtractElement(ctx->builder,
2368 tmp_vec,
2369 indir_index, "");
2370 } else
2371 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2372 }
2373 break;
2374 case nir_var_local:
2375 for (unsigned chan = 0; chan < ve; chan++) {
2376 if (indir_index) {
2377 unsigned count = glsl_count_attribute_slots(
2378 instr->variables[0]->var->type, false);
2379 count -= chan / 4;
2380 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2381 &ctx->ac, ctx->locals + idx + chan, count,
2382 4, true);
2383
2384 values[chan] = LLVMBuildExtractElement(ctx->builder,
2385 tmp_vec,
2386 indir_index, "");
2387 } else {
2388 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2389 }
2390 }
2391 break;
2392 case nir_var_shader_out:
2393 for (unsigned chan = 0; chan < ve; chan++) {
2394 if (indir_index) {
2395 unsigned count = glsl_count_attribute_slots(
2396 instr->variables[0]->var->type, false);
2397 count -= chan / 4;
2398 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2399 &ctx->ac, ctx->outputs + idx + chan, count,
2400 4, true);
2401
2402 values[chan] = LLVMBuildExtractElement(ctx->builder,
2403 tmp_vec,
2404 indir_index, "");
2405 } else {
2406 values[chan] = LLVMBuildLoad(ctx->builder,
2407 ctx->outputs[idx + chan + const_index * 4],
2408 "");
2409 }
2410 }
2411 break;
2412 case nir_var_shared: {
2413 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2414 LLVMValueRef derived_ptr;
2415
2416 for (unsigned chan = 0; chan < ve; chan++) {
2417 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2418 if (indir_index)
2419 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2420 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2421
2422 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2423 }
2424 break;
2425 }
2426 default:
2427 unreachable("unhandle variable mode");
2428 }
2429 ret = ac_build_gather_values(&ctx->ac, values, ve);
2430 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2431 }
2432
2433 static void
2434 visit_store_var(struct nir_to_llvm_context *ctx,
2435 nir_intrinsic_instr *instr)
2436 {
2437 LLVMValueRef temp_ptr, value;
2438 int idx = instr->variables[0]->var->data.driver_location;
2439 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2440 int writemask = instr->const_index[0];
2441 LLVMValueRef indir_index;
2442 unsigned const_index;
2443 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2444 NULL, &const_index, &indir_index);
2445
2446 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2447 int old_writemask = writemask;
2448
2449 src = LLVMBuildBitCast(ctx->builder, src,
2450 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2451 "");
2452
2453 writemask = 0;
2454 for (unsigned chan = 0; chan < 4; chan++) {
2455 if (old_writemask & (1 << chan))
2456 writemask |= 3u << (2 * chan);
2457 }
2458 }
2459
2460 switch (instr->variables[0]->var->data.mode) {
2461 case nir_var_shader_out:
2462 for (unsigned chan = 0; chan < 8; chan++) {
2463 int stride = 4;
2464 if (!(writemask & (1 << chan)))
2465 continue;
2466
2467 value = llvm_extract_elem(ctx, src, chan);
2468
2469 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2470 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2471 stride = 1;
2472 if (indir_index) {
2473 unsigned count = glsl_count_attribute_slots(
2474 instr->variables[0]->var->type, false);
2475 count -= chan / 4;
2476 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2477 &ctx->ac, ctx->outputs + idx + chan, count,
2478 stride, true);
2479
2480 if (get_llvm_num_components(tmp_vec) > 1) {
2481 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2482 value, indir_index, "");
2483 } else
2484 tmp_vec = value;
2485 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2486 count, stride, tmp_vec);
2487
2488 } else {
2489 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2490
2491 LLVMBuildStore(ctx->builder, value, temp_ptr);
2492 }
2493 }
2494 break;
2495 case nir_var_local:
2496 for (unsigned chan = 0; chan < 8; chan++) {
2497 if (!(writemask & (1 << chan)))
2498 continue;
2499
2500 value = llvm_extract_elem(ctx, src, chan);
2501 if (indir_index) {
2502 unsigned count = glsl_count_attribute_slots(
2503 instr->variables[0]->var->type, false);
2504 count -= chan / 4;
2505 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2506 &ctx->ac, ctx->locals + idx + chan, count,
2507 4, true);
2508
2509 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2510 value, indir_index, "");
2511 build_store_values_extended(ctx, ctx->locals + idx + chan,
2512 count, 4, tmp_vec);
2513 } else {
2514 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2515
2516 LLVMBuildStore(ctx->builder, value, temp_ptr);
2517 }
2518 }
2519 break;
2520 case nir_var_shared: {
2521 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2522 for (unsigned chan = 0; chan < 8; chan++) {
2523 if (!(writemask & (1 << chan)))
2524 continue;
2525 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2526 LLVMValueRef derived_ptr;
2527
2528 if (indir_index)
2529 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2530 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2531 LLVMBuildStore(ctx->builder,
2532 to_integer(ctx, src), derived_ptr);
2533 }
2534 break;
2535 }
2536 default:
2537 break;
2538 }
2539 }
2540
2541 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2542 {
2543 switch (dim) {
2544 case GLSL_SAMPLER_DIM_BUF:
2545 return 1;
2546 case GLSL_SAMPLER_DIM_1D:
2547 return array ? 2 : 1;
2548 case GLSL_SAMPLER_DIM_2D:
2549 return array ? 3 : 2;
2550 case GLSL_SAMPLER_DIM_MS:
2551 return array ? 4 : 3;
2552 case GLSL_SAMPLER_DIM_3D:
2553 case GLSL_SAMPLER_DIM_CUBE:
2554 return 3;
2555 case GLSL_SAMPLER_DIM_RECT:
2556 case GLSL_SAMPLER_DIM_SUBPASS:
2557 return 2;
2558 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2559 return 3;
2560 default:
2561 break;
2562 }
2563 return 0;
2564 }
2565
2566 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2567 nir_intrinsic_instr *instr)
2568 {
2569 const struct glsl_type *type = instr->variables[0]->var->type;
2570 if(instr->variables[0]->deref.child)
2571 type = instr->variables[0]->deref.child->type;
2572
2573 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2574 LLVMValueRef coords[4];
2575 LLVMValueRef masks[] = {
2576 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2577 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2578 };
2579 LLVMValueRef res;
2580 int count;
2581 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2582 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2583 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2584 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2585 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2586
2587 count = image_type_to_components_count(dim,
2588 glsl_sampler_type_is_array(type));
2589
2590 if (count == 1) {
2591 if (instr->src[0].ssa->num_components)
2592 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2593 else
2594 res = src0;
2595 } else {
2596 int chan;
2597 if (is_ms)
2598 count--;
2599 for (chan = 0; chan < count; ++chan) {
2600 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2601 }
2602
2603 if (add_frag_pos) {
2604 for (chan = 0; chan < count; ++chan)
2605 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2606 }
2607 if (is_ms) {
2608 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2609 count++;
2610 }
2611
2612 if (count == 3) {
2613 coords[3] = LLVMGetUndef(ctx->i32);
2614 count = 4;
2615 }
2616 res = ac_build_gather_values(&ctx->ac, coords, count);
2617 }
2618 return res;
2619 }
2620
2621 static void build_type_name_for_intr(
2622 LLVMTypeRef type,
2623 char *buf, unsigned bufsize)
2624 {
2625 LLVMTypeRef elem_type = type;
2626
2627 assert(bufsize >= 8);
2628
2629 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2630 int ret = snprintf(buf, bufsize, "v%u",
2631 LLVMGetVectorSize(type));
2632 if (ret < 0) {
2633 char *type_name = LLVMPrintTypeToString(type);
2634 fprintf(stderr, "Error building type name for: %s\n",
2635 type_name);
2636 return;
2637 }
2638 elem_type = LLVMGetElementType(type);
2639 buf += ret;
2640 bufsize -= ret;
2641 }
2642 switch (LLVMGetTypeKind(elem_type)) {
2643 default: break;
2644 case LLVMIntegerTypeKind:
2645 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2646 break;
2647 case LLVMFloatTypeKind:
2648 snprintf(buf, bufsize, "f32");
2649 break;
2650 case LLVMDoubleTypeKind:
2651 snprintf(buf, bufsize, "f64");
2652 break;
2653 }
2654 }
2655
2656 static void get_image_intr_name(const char *base_name,
2657 LLVMTypeRef data_type,
2658 LLVMTypeRef coords_type,
2659 LLVMTypeRef rsrc_type,
2660 char *out_name, unsigned out_len)
2661 {
2662 char coords_type_name[8];
2663
2664 build_type_name_for_intr(coords_type, coords_type_name,
2665 sizeof(coords_type_name));
2666
2667 if (HAVE_LLVM <= 0x0309) {
2668 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2669 } else {
2670 char data_type_name[8];
2671 char rsrc_type_name[8];
2672
2673 build_type_name_for_intr(data_type, data_type_name,
2674 sizeof(data_type_name));
2675 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2676 sizeof(rsrc_type_name));
2677 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2678 data_type_name, coords_type_name, rsrc_type_name);
2679 }
2680 }
2681
2682 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2683 nir_intrinsic_instr *instr)
2684 {
2685 LLVMValueRef params[7];
2686 LLVMValueRef res;
2687 char intrinsic_name[64];
2688 const nir_variable *var = instr->variables[0]->var;
2689 const struct glsl_type *type = var->type;
2690 if(instr->variables[0]->deref.child)
2691 type = instr->variables[0]->deref.child->type;
2692
2693 type = glsl_without_array(type);
2694 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2695 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2696 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2697 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2698 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2699 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2700 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2701 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2702 params, 5, 0);
2703
2704 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2705 res = to_integer(ctx, res);
2706 } else {
2707 bool is_da = glsl_sampler_type_is_array(type) ||
2708 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2709 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2710 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2711 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2712
2713 params[0] = get_image_coords(ctx, instr);
2714 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2715 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2716 if (HAVE_LLVM <= 0x0309) {
2717 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2718 params[4] = da;
2719 params[5] = glc;
2720 params[6] = slc;
2721 } else {
2722 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2723 params[3] = glc;
2724 params[4] = slc;
2725 params[5] = lwe;
2726 params[6] = da;
2727 }
2728
2729 get_image_intr_name("llvm.amdgcn.image.load",
2730 ctx->v4f32, /* vdata */
2731 LLVMTypeOf(params[0]), /* coords */
2732 LLVMTypeOf(params[1]), /* rsrc */
2733 intrinsic_name, sizeof(intrinsic_name));
2734
2735 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2736 params, 7, AC_FUNC_ATTR_READONLY);
2737 }
2738 return to_integer(ctx, res);
2739 }
2740
2741 static void visit_image_store(struct nir_to_llvm_context *ctx,
2742 nir_intrinsic_instr *instr)
2743 {
2744 LLVMValueRef params[8];
2745 char intrinsic_name[64];
2746 const nir_variable *var = instr->variables[0]->var;
2747 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2748 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2749 const struct glsl_type *type = glsl_without_array(var->type);
2750
2751 if (ctx->stage == MESA_SHADER_FRAGMENT)
2752 ctx->shader_info->fs.writes_memory = true;
2753
2754 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2755 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2756 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2757 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2758 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2759 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2760 params[4] = i1false; /* glc */
2761 params[5] = i1false; /* slc */
2762 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2763 params, 6, 0);
2764 } else {
2765 bool is_da = glsl_sampler_type_is_array(type) ||
2766 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2767 LLVMValueRef da = is_da ? i1true : i1false;
2768 LLVMValueRef glc = i1false;
2769 LLVMValueRef slc = i1false;
2770
2771 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2772 params[1] = get_image_coords(ctx, instr); /* coords */
2773 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2774 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2775 if (HAVE_LLVM <= 0x0309) {
2776 params[4] = i1false; /* r128 */
2777 params[5] = da;
2778 params[6] = glc;
2779 params[7] = slc;
2780 } else {
2781 LLVMValueRef lwe = i1false;
2782 params[4] = glc;
2783 params[5] = slc;
2784 params[6] = lwe;
2785 params[7] = da;
2786 }
2787
2788 get_image_intr_name("llvm.amdgcn.image.store",
2789 LLVMTypeOf(params[0]), /* vdata */
2790 LLVMTypeOf(params[1]), /* coords */
2791 LLVMTypeOf(params[2]), /* rsrc */
2792 intrinsic_name, sizeof(intrinsic_name));
2793
2794 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2795 params, 8, 0);
2796 }
2797
2798 }
2799
2800 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2801 nir_intrinsic_instr *instr)
2802 {
2803 LLVMValueRef params[6];
2804 int param_count = 0;
2805 const nir_variable *var = instr->variables[0]->var;
2806 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2807 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2808 const char *base_name = "llvm.amdgcn.image.atomic";
2809 const char *atomic_name;
2810 LLVMValueRef coords;
2811 char intrinsic_name[32], coords_type[8];
2812 const struct glsl_type *type = glsl_without_array(var->type);
2813
2814 if (ctx->stage == MESA_SHADER_FRAGMENT)
2815 ctx->shader_info->fs.writes_memory = true;
2816
2817 params[param_count++] = get_src(ctx, instr->src[2]);
2818 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2819 params[param_count++] = get_src(ctx, instr->src[3]);
2820
2821 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2822 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2823 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2824 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2825 params[param_count++] = ctx->i32zero; /* voffset */
2826 params[param_count++] = i1false; /* glc */
2827 params[param_count++] = i1false; /* slc */
2828 } else {
2829 bool da = glsl_sampler_type_is_array(type) ||
2830 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2831
2832 coords = params[param_count++] = get_image_coords(ctx, instr);
2833 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2834 params[param_count++] = i1false; /* r128 */
2835 params[param_count++] = da ? i1true : i1false; /* da */
2836 params[param_count++] = i1false; /* slc */
2837 }
2838
2839 switch (instr->intrinsic) {
2840 case nir_intrinsic_image_atomic_add:
2841 atomic_name = "add";
2842 break;
2843 case nir_intrinsic_image_atomic_min:
2844 atomic_name = "smin";
2845 break;
2846 case nir_intrinsic_image_atomic_max:
2847 atomic_name = "smax";
2848 break;
2849 case nir_intrinsic_image_atomic_and:
2850 atomic_name = "and";
2851 break;
2852 case nir_intrinsic_image_atomic_or:
2853 atomic_name = "or";
2854 break;
2855 case nir_intrinsic_image_atomic_xor:
2856 atomic_name = "xor";
2857 break;
2858 case nir_intrinsic_image_atomic_exchange:
2859 atomic_name = "swap";
2860 break;
2861 case nir_intrinsic_image_atomic_comp_swap:
2862 atomic_name = "cmpswap";
2863 break;
2864 default:
2865 abort();
2866 }
2867 build_int_type_name(LLVMTypeOf(coords),
2868 coords_type, sizeof(coords_type));
2869
2870 snprintf(intrinsic_name, sizeof(intrinsic_name),
2871 "%s.%s.%s", base_name, atomic_name, coords_type);
2872 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2873 }
2874
2875 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2876 nir_intrinsic_instr *instr)
2877 {
2878 LLVMValueRef res;
2879 LLVMValueRef params[10];
2880 const nir_variable *var = instr->variables[0]->var;
2881 const struct glsl_type *type = instr->variables[0]->var->type;
2882 bool da = glsl_sampler_type_is_array(var->type) ||
2883 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2884 if(instr->variables[0]->deref.child)
2885 type = instr->variables[0]->deref.child->type;
2886
2887 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2888 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2889 params[0] = ctx->i32zero;
2890 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2891 params[2] = LLVMConstInt(ctx->i32, 15, false);
2892 params[3] = ctx->i32zero;
2893 params[4] = ctx->i32zero;
2894 params[5] = da ? ctx->i32one : ctx->i32zero;
2895 params[6] = ctx->i32zero;
2896 params[7] = ctx->i32zero;
2897 params[8] = ctx->i32zero;
2898 params[9] = ctx->i32zero;
2899
2900 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2901 params, 10, AC_FUNC_ATTR_READNONE);
2902
2903 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2904 glsl_sampler_type_is_array(type)) {
2905 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2906 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2907 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2908 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2909 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2910 }
2911 return res;
2912 }
2913
2914 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2915 {
2916 LLVMValueRef args[1] = {
2917 LLVMConstInt(ctx->i32, 0xf70, false),
2918 };
2919 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2920 ctx->voidt, args, 1, 0);
2921 }
2922
2923 static void emit_barrier(struct nir_to_llvm_context *ctx)
2924 {
2925 // TODO tess
2926 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2927 ctx->voidt, NULL, 0, 0);
2928 }
2929
2930 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2931 nir_intrinsic_instr *instr)
2932 {
2933 LLVMValueRef cond;
2934 ctx->shader_info->fs.can_discard = true;
2935
2936 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2937 get_src(ctx, instr->src[0]),
2938 ctx->i32zero, "");
2939
2940 cond = LLVMBuildSelect(ctx->builder, cond,
2941 LLVMConstReal(ctx->f32, -1.0f),
2942 ctx->f32zero, "");
2943 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2944 ctx->voidt,
2945 &cond, 1, 0);
2946 }
2947
2948 static LLVMValueRef
2949 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2950 {
2951 LLVMValueRef result;
2952 LLVMValueRef thread_id = get_thread_id(ctx);
2953 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2954 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2955
2956 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2957 }
2958
2959 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2960 nir_intrinsic_instr *instr)
2961 {
2962 LLVMValueRef ptr, result;
2963 int idx = instr->variables[0]->var->data.driver_location;
2964 LLVMValueRef src = get_src(ctx, instr->src[0]);
2965 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2966
2967 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2968 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2969 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2970 ptr, src, src1,
2971 LLVMAtomicOrderingSequentiallyConsistent,
2972 LLVMAtomicOrderingSequentiallyConsistent,
2973 false);
2974 } else {
2975 LLVMAtomicRMWBinOp op;
2976 switch (instr->intrinsic) {
2977 case nir_intrinsic_var_atomic_add:
2978 op = LLVMAtomicRMWBinOpAdd;
2979 break;
2980 case nir_intrinsic_var_atomic_umin:
2981 op = LLVMAtomicRMWBinOpUMin;
2982 break;
2983 case nir_intrinsic_var_atomic_umax:
2984 op = LLVMAtomicRMWBinOpUMax;
2985 break;
2986 case nir_intrinsic_var_atomic_imin:
2987 op = LLVMAtomicRMWBinOpMin;
2988 break;
2989 case nir_intrinsic_var_atomic_imax:
2990 op = LLVMAtomicRMWBinOpMax;
2991 break;
2992 case nir_intrinsic_var_atomic_and:
2993 op = LLVMAtomicRMWBinOpAnd;
2994 break;
2995 case nir_intrinsic_var_atomic_or:
2996 op = LLVMAtomicRMWBinOpOr;
2997 break;
2998 case nir_intrinsic_var_atomic_xor:
2999 op = LLVMAtomicRMWBinOpXor;
3000 break;
3001 case nir_intrinsic_var_atomic_exchange:
3002 op = LLVMAtomicRMWBinOpXchg;
3003 break;
3004 default:
3005 return NULL;
3006 }
3007
3008 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3009 LLVMAtomicOrderingSequentiallyConsistent,
3010 false);
3011 }
3012 return result;
3013 }
3014
3015 #define INTERP_CENTER 0
3016 #define INTERP_CENTROID 1
3017 #define INTERP_SAMPLE 2
3018
3019 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3020 enum glsl_interp_mode interp, unsigned location)
3021 {
3022 switch (interp) {
3023 case INTERP_MODE_FLAT:
3024 default:
3025 return NULL;
3026 case INTERP_MODE_SMOOTH:
3027 case INTERP_MODE_NONE:
3028 if (location == INTERP_CENTER)
3029 return ctx->persp_center;
3030 else if (location == INTERP_CENTROID)
3031 return ctx->persp_centroid;
3032 else if (location == INTERP_SAMPLE)
3033 return ctx->persp_sample;
3034 break;
3035 case INTERP_MODE_NOPERSPECTIVE:
3036 if (location == INTERP_CENTER)
3037 return ctx->linear_center;
3038 else if (location == INTERP_CENTROID)
3039 return ctx->linear_centroid;
3040 else if (location == INTERP_SAMPLE)
3041 return ctx->linear_sample;
3042 break;
3043 }
3044 return NULL;
3045 }
3046
3047 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3048 LLVMValueRef sample_id)
3049 {
3050 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
3051 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
3052 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
3053 LLVMValueRef result[2];
3054
3055 result[0] = build_indexed_load_const(ctx, ctx->sample_positions, offset0);
3056 result[1] = build_indexed_load_const(ctx, ctx->sample_positions, offset1);
3057
3058 return ac_build_gather_values(&ctx->ac, result, 2);
3059 }
3060
3061 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3062 {
3063 LLVMValueRef values[2];
3064
3065 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3066 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3067 return ac_build_gather_values(&ctx->ac, values, 2);
3068 }
3069
3070 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3071 nir_intrinsic_instr *instr)
3072 {
3073 LLVMValueRef result[2];
3074 LLVMValueRef interp_param, attr_number;
3075 unsigned location;
3076 unsigned chan;
3077 LLVMValueRef src_c0, src_c1;
3078 const char *intr_name;
3079 LLVMValueRef src0;
3080 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3081 switch (instr->intrinsic) {
3082 case nir_intrinsic_interp_var_at_centroid:
3083 location = INTERP_CENTROID;
3084 break;
3085 case nir_intrinsic_interp_var_at_sample:
3086 case nir_intrinsic_interp_var_at_offset:
3087 location = INTERP_SAMPLE;
3088 src0 = get_src(ctx, instr->src[0]);
3089 break;
3090 default:
3091 break;
3092 }
3093
3094 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3095 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3096 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3097 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3098 LLVMValueRef sample_position;
3099 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3100
3101 /* fetch sample ID */
3102 sample_position = load_sample_position(ctx, src0);
3103
3104 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3105 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3106 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3107 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3108 }
3109 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3110 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3111
3112 if (location == INTERP_SAMPLE) {
3113 LLVMValueRef ij_out[2];
3114 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3115
3116 /*
3117 * take the I then J parameters, and the DDX/Y for it, and
3118 * calculate the IJ inputs for the interpolator.
3119 * temp1 = ddx * offset/sample.x + I;
3120 * interp_param.I = ddy * offset/sample.y + temp1;
3121 * temp1 = ddx * offset/sample.x + J;
3122 * interp_param.J = ddy * offset/sample.y + temp1;
3123 */
3124 for (unsigned i = 0; i < 2; i++) {
3125 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3126 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3127 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3128 ddxy_out, ix_ll, "");
3129 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3130 ddxy_out, iy_ll, "");
3131 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3132 interp_param, ix_ll, "");
3133 LLVMValueRef temp1, temp2;
3134
3135 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3136 ctx->f32, "");
3137
3138 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3139 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3140
3141 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3142 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3143
3144 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3145 temp2, ctx->i32, "");
3146 }
3147 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3148
3149 }
3150 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3151 for (chan = 0; chan < 2; chan++) {
3152 LLVMValueRef args[4];
3153 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3154
3155 args[0] = llvm_chan;
3156 args[1] = attr_number;
3157 args[2] = ctx->prim_mask;
3158 args[3] = interp_param;
3159 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
3160 ctx->f32, args, args[3] ? 4 : 3,
3161 AC_FUNC_ATTR_READNONE);
3162 }
3163 return ac_build_gather_values(&ctx->ac, result, 2);
3164 }
3165
3166 static void
3167 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3168 nir_intrinsic_instr *instr)
3169 {
3170 LLVMValueRef gs_next_vertex;
3171 LLVMValueRef can_emit, kill;
3172 LLVMValueRef args[2];
3173 int idx;
3174
3175 assert(instr->const_index[0] == 0);
3176 /* Write vertex attribute values to GSVS ring */
3177 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3178 ctx->gs_next_vertex,
3179 "");
3180
3181 /* If this thread has already emitted the declared maximum number of
3182 * vertices, kill it: excessive vertex emissions are not supposed to
3183 * have any effect, and GS threads have no externally observable
3184 * effects other than emitting vertices.
3185 */
3186 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3187 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3188
3189 kill = LLVMBuildSelect(ctx->builder, can_emit,
3190 LLVMConstReal(ctx->f32, 1.0f),
3191 LLVMConstReal(ctx->f32, -1.0f), "");
3192 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3193 ctx->voidt, &kill, 1, 0);
3194
3195 /* loop num outputs */
3196 idx = 0;
3197 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3198 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3199 if (!(ctx->output_mask & (1ull << i)))
3200 continue;
3201
3202 for (unsigned j = 0; j < 4; j++) {
3203 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3204 out_ptr[j], "");
3205 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (idx * 4 + j) * ctx->gs_max_out_vertices, false);
3206 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3207 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3208
3209 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3210
3211 build_tbuffer_store(ctx, ctx->gsvs_ring,
3212 out_val, 1,
3213 voffset, ctx->gs2vs_offset, 0,
3214 V_008F0C_BUF_DATA_FORMAT_32,
3215 V_008F0C_BUF_NUM_FORMAT_UINT,
3216 1, 0, 1, 1, 0);
3217 }
3218 idx++;
3219 }
3220
3221 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3222 ctx->i32one, "");
3223 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3224 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (0 << 8), false);
3225 args[1] = ctx->gs_wave_id;
3226 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
3227 ctx->voidt, args, 2, 0);
3228 }
3229
3230 static void
3231 visit_end_primitive(struct nir_to_llvm_context *ctx,
3232 nir_intrinsic_instr *instr)
3233 {
3234 LLVMValueRef args[2];
3235
3236 assert(instr->const_index[0] == 0);
3237 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_CUT | SENDMSG_GS | (0 << 8), false);
3238 args[1] = ctx->gs_wave_id;
3239
3240 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg", ctx->voidt,
3241 args, 2, 0);
3242 }
3243
3244 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3245 nir_intrinsic_instr *instr)
3246 {
3247 LLVMValueRef result = NULL;
3248
3249 switch (instr->intrinsic) {
3250 case nir_intrinsic_load_work_group_id: {
3251 result = ctx->workgroup_ids;
3252 break;
3253 }
3254 case nir_intrinsic_load_base_vertex: {
3255 result = ctx->base_vertex;
3256 break;
3257 }
3258 case nir_intrinsic_load_vertex_id_zero_base: {
3259 result = ctx->vertex_id;
3260 break;
3261 }
3262 case nir_intrinsic_load_local_invocation_id: {
3263 result = ctx->local_invocation_ids;
3264 break;
3265 }
3266 case nir_intrinsic_load_base_instance:
3267 result = ctx->start_instance;
3268 break;
3269 case nir_intrinsic_load_draw_id:
3270 result = ctx->draw_index;
3271 break;
3272 case nir_intrinsic_load_invocation_id:
3273 result = ctx->gs_invocation_id;
3274 break;
3275 case nir_intrinsic_load_primitive_id:
3276 if (ctx->stage == MESA_SHADER_GEOMETRY)
3277 result = ctx->gs_prim_id;
3278 else
3279 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3280 break;
3281 case nir_intrinsic_load_sample_id:
3282 ctx->shader_info->fs.force_persample = true;
3283 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3284 break;
3285 case nir_intrinsic_load_sample_pos:
3286 ctx->shader_info->fs.force_persample = true;
3287 result = load_sample_pos(ctx);
3288 break;
3289 case nir_intrinsic_load_front_face:
3290 result = ctx->front_face;
3291 break;
3292 case nir_intrinsic_load_instance_id:
3293 result = ctx->instance_id;
3294 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3295 ctx->shader_info->vs.vgpr_comp_cnt);
3296 break;
3297 case nir_intrinsic_load_num_work_groups:
3298 result = ctx->num_work_groups;
3299 break;
3300 case nir_intrinsic_load_local_invocation_index:
3301 result = visit_load_local_invocation_index(ctx);
3302 break;
3303 case nir_intrinsic_load_push_constant:
3304 result = visit_load_push_constant(ctx, instr);
3305 break;
3306 case nir_intrinsic_vulkan_resource_index:
3307 result = visit_vulkan_resource_index(ctx, instr);
3308 break;
3309 case nir_intrinsic_store_ssbo:
3310 visit_store_ssbo(ctx, instr);
3311 break;
3312 case nir_intrinsic_load_ssbo:
3313 result = visit_load_buffer(ctx, instr);
3314 break;
3315 case nir_intrinsic_ssbo_atomic_add:
3316 case nir_intrinsic_ssbo_atomic_imin:
3317 case nir_intrinsic_ssbo_atomic_umin:
3318 case nir_intrinsic_ssbo_atomic_imax:
3319 case nir_intrinsic_ssbo_atomic_umax:
3320 case nir_intrinsic_ssbo_atomic_and:
3321 case nir_intrinsic_ssbo_atomic_or:
3322 case nir_intrinsic_ssbo_atomic_xor:
3323 case nir_intrinsic_ssbo_atomic_exchange:
3324 case nir_intrinsic_ssbo_atomic_comp_swap:
3325 result = visit_atomic_ssbo(ctx, instr);
3326 break;
3327 case nir_intrinsic_load_ubo:
3328 result = visit_load_ubo_buffer(ctx, instr);
3329 break;
3330 case nir_intrinsic_get_buffer_size:
3331 result = visit_get_buffer_size(ctx, instr);
3332 break;
3333 case nir_intrinsic_load_var:
3334 result = visit_load_var(ctx, instr);
3335 break;
3336 case nir_intrinsic_store_var:
3337 visit_store_var(ctx, instr);
3338 break;
3339 case nir_intrinsic_image_load:
3340 result = visit_image_load(ctx, instr);
3341 break;
3342 case nir_intrinsic_image_store:
3343 visit_image_store(ctx, instr);
3344 break;
3345 case nir_intrinsic_image_atomic_add:
3346 case nir_intrinsic_image_atomic_min:
3347 case nir_intrinsic_image_atomic_max:
3348 case nir_intrinsic_image_atomic_and:
3349 case nir_intrinsic_image_atomic_or:
3350 case nir_intrinsic_image_atomic_xor:
3351 case nir_intrinsic_image_atomic_exchange:
3352 case nir_intrinsic_image_atomic_comp_swap:
3353 result = visit_image_atomic(ctx, instr);
3354 break;
3355 case nir_intrinsic_image_size:
3356 result = visit_image_size(ctx, instr);
3357 break;
3358 case nir_intrinsic_discard:
3359 ctx->shader_info->fs.can_discard = true;
3360 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3361 ctx->voidt,
3362 NULL, 0, 0);
3363 break;
3364 case nir_intrinsic_discard_if:
3365 emit_discard_if(ctx, instr);
3366 break;
3367 case nir_intrinsic_memory_barrier:
3368 emit_waitcnt(ctx);
3369 break;
3370 case nir_intrinsic_barrier:
3371 emit_barrier(ctx);
3372 break;
3373 case nir_intrinsic_var_atomic_add:
3374 case nir_intrinsic_var_atomic_imin:
3375 case nir_intrinsic_var_atomic_umin:
3376 case nir_intrinsic_var_atomic_imax:
3377 case nir_intrinsic_var_atomic_umax:
3378 case nir_intrinsic_var_atomic_and:
3379 case nir_intrinsic_var_atomic_or:
3380 case nir_intrinsic_var_atomic_xor:
3381 case nir_intrinsic_var_atomic_exchange:
3382 case nir_intrinsic_var_atomic_comp_swap:
3383 result = visit_var_atomic(ctx, instr);
3384 break;
3385 case nir_intrinsic_interp_var_at_centroid:
3386 case nir_intrinsic_interp_var_at_sample:
3387 case nir_intrinsic_interp_var_at_offset:
3388 result = visit_interp(ctx, instr);
3389 break;
3390 case nir_intrinsic_emit_vertex:
3391 visit_emit_vertex(ctx, instr);
3392 break;
3393 case nir_intrinsic_end_primitive:
3394 visit_end_primitive(ctx, instr);
3395 break;
3396 default:
3397 fprintf(stderr, "Unknown intrinsic: ");
3398 nir_print_instr(&instr->instr, stderr);
3399 fprintf(stderr, "\n");
3400 break;
3401 }
3402 if (result) {
3403 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3404 }
3405 }
3406
3407 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3408 nir_deref_var *deref,
3409 enum desc_type desc_type)
3410 {
3411 unsigned desc_set = deref->var->data.descriptor_set;
3412 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3413 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3414 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3415 unsigned offset = binding->offset;
3416 unsigned stride = binding->size;
3417 unsigned type_size;
3418 LLVMBuilderRef builder = ctx->builder;
3419 LLVMTypeRef type;
3420 LLVMValueRef index = NULL;
3421
3422 assert(deref->var->data.binding < layout->binding_count);
3423
3424 switch (desc_type) {
3425 case DESC_IMAGE:
3426 type = ctx->v8i32;
3427 type_size = 32;
3428 break;
3429 case DESC_FMASK:
3430 type = ctx->v8i32;
3431 offset += 32;
3432 type_size = 32;
3433 break;
3434 case DESC_SAMPLER:
3435 type = ctx->v4i32;
3436 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3437 offset += 64;
3438
3439 type_size = 16;
3440 break;
3441 case DESC_BUFFER:
3442 type = ctx->v4i32;
3443 type_size = 16;
3444 break;
3445 default:
3446 unreachable("invalid desc_type\n");
3447 }
3448
3449 if (deref->deref.child) {
3450 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3451
3452 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3453 offset += child->base_offset * stride;
3454 if (child->deref_array_type == nir_deref_array_type_indirect) {
3455 index = get_src(ctx, child->indirect);
3456 }
3457 }
3458
3459 assert(stride % type_size == 0);
3460
3461 if (!index)
3462 index = ctx->i32zero;
3463
3464 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3465
3466 list = build_gep0(ctx, list, LLVMConstInt(ctx->i32, offset, 0));
3467 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3468
3469 return build_indexed_load_const(ctx, list, index);
3470 }
3471
3472 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3473 struct ac_tex_info *tinfo,
3474 nir_tex_instr *instr,
3475 nir_texop op,
3476 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3477 LLVMValueRef *param, unsigned count,
3478 unsigned dmask)
3479 {
3480 int num_args;
3481 unsigned is_rect = 0;
3482 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3483
3484 if (op == nir_texop_lod)
3485 da = false;
3486 /* Pad to power of two vector */
3487 while (count < util_next_power_of_two(count))
3488 param[count++] = LLVMGetUndef(ctx->i32);
3489
3490 if (count > 1)
3491 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3492 else
3493 tinfo->args[0] = param[0];
3494
3495 tinfo->args[1] = res_ptr;
3496 num_args = 2;
3497
3498 if (op == nir_texop_txf ||
3499 op == nir_texop_txf_ms ||
3500 op == nir_texop_query_levels ||
3501 op == nir_texop_texture_samples ||
3502 op == nir_texop_txs)
3503 tinfo->dst_type = ctx->v4i32;
3504 else {
3505 tinfo->dst_type = ctx->v4f32;
3506 tinfo->args[num_args++] = samp_ptr;
3507 }
3508
3509 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3510 tinfo->args[0] = res_ptr;
3511 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3512 tinfo->args[2] = param[0];
3513 tinfo->arg_count = 3;
3514 return;
3515 }
3516
3517 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3518 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3519 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3520 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3521 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3522 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3523 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3524 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3525
3526 tinfo->arg_count = num_args;
3527 }
3528
3529 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3530 *
3531 * SI-CI:
3532 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3533 * filtering manually. The driver sets img7 to a mask clearing
3534 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3535 * s_and_b32 samp0, samp0, img7
3536 *
3537 * VI:
3538 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3539 */
3540 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3541 LLVMValueRef res, LLVMValueRef samp)
3542 {
3543 LLVMBuilderRef builder = ctx->builder;
3544 LLVMValueRef img7, samp0;
3545
3546 if (ctx->options->chip_class >= VI)
3547 return samp;
3548
3549 img7 = LLVMBuildExtractElement(builder, res,
3550 LLVMConstInt(ctx->i32, 7, 0), "");
3551 samp0 = LLVMBuildExtractElement(builder, samp,
3552 LLVMConstInt(ctx->i32, 0, 0), "");
3553 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3554 return LLVMBuildInsertElement(builder, samp, samp0,
3555 LLVMConstInt(ctx->i32, 0, 0), "");
3556 }
3557
3558 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3559 nir_tex_instr *instr,
3560 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3561 LLVMValueRef *fmask_ptr)
3562 {
3563 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3564 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3565 else
3566 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3567 if (samp_ptr) {
3568 if (instr->sampler)
3569 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3570 else
3571 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3572 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3573 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3574 }
3575 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3576 instr->op == nir_texop_samples_identical))
3577 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3578 }
3579
3580 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3581 LLVMValueRef coord)
3582 {
3583 coord = to_float(ctx, coord);
3584 coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3585 coord = to_integer(ctx, coord);
3586 return coord;
3587 }
3588
3589 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3590 {
3591 LLVMValueRef result = NULL;
3592 struct ac_tex_info tinfo = { 0 };
3593 unsigned dmask = 0xf;
3594 LLVMValueRef address[16];
3595 LLVMValueRef coords[5];
3596 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3597 LLVMValueRef bias = NULL, offsets = NULL;
3598 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3599 LLVMValueRef ddx = NULL, ddy = NULL;
3600 LLVMValueRef derivs[6];
3601 unsigned chan, count = 0;
3602 unsigned const_src = 0, num_deriv_comp = 0;
3603
3604 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3605
3606 for (unsigned i = 0; i < instr->num_srcs; i++) {
3607 switch (instr->src[i].src_type) {
3608 case nir_tex_src_coord:
3609 coord = get_src(ctx, instr->src[i].src);
3610 break;
3611 case nir_tex_src_projector:
3612 break;
3613 case nir_tex_src_comparator:
3614 comparator = get_src(ctx, instr->src[i].src);
3615 break;
3616 case nir_tex_src_offset:
3617 offsets = get_src(ctx, instr->src[i].src);
3618 const_src = i;
3619 break;
3620 case nir_tex_src_bias:
3621 bias = get_src(ctx, instr->src[i].src);
3622 break;
3623 case nir_tex_src_lod:
3624 lod = get_src(ctx, instr->src[i].src);
3625 break;
3626 case nir_tex_src_ms_index:
3627 sample_index = get_src(ctx, instr->src[i].src);
3628 break;
3629 case nir_tex_src_ms_mcs:
3630 break;
3631 case nir_tex_src_ddx:
3632 ddx = get_src(ctx, instr->src[i].src);
3633 num_deriv_comp = instr->src[i].src.ssa->num_components;
3634 break;
3635 case nir_tex_src_ddy:
3636 ddy = get_src(ctx, instr->src[i].src);
3637 break;
3638 case nir_tex_src_texture_offset:
3639 case nir_tex_src_sampler_offset:
3640 case nir_tex_src_plane:
3641 default:
3642 break;
3643 }
3644 }
3645
3646 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3647 result = get_buffer_size(ctx, res_ptr, false);
3648 goto write_result;
3649 }
3650
3651 if (instr->op == nir_texop_texture_samples) {
3652 LLVMValueRef res, samples, is_msaa;
3653 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3654 samples = LLVMBuildExtractElement(ctx->builder, res,
3655 LLVMConstInt(ctx->i32, 3, false), "");
3656 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3657 LLVMConstInt(ctx->i32, 28, false), "");
3658 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3659 LLVMConstInt(ctx->i32, 0xe, false), "");
3660 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3661 LLVMConstInt(ctx->i32, 0xe, false), "");
3662
3663 samples = LLVMBuildLShr(ctx->builder, samples,
3664 LLVMConstInt(ctx->i32, 16, false), "");
3665 samples = LLVMBuildAnd(ctx->builder, samples,
3666 LLVMConstInt(ctx->i32, 0xf, false), "");
3667 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3668 samples, "");
3669 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3670 ctx->i32one, "");
3671 result = samples;
3672 goto write_result;
3673 }
3674
3675 if (coord)
3676 for (chan = 0; chan < instr->coord_components; chan++)
3677 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3678
3679 if (offsets && instr->op != nir_texop_txf) {
3680 LLVMValueRef offset[3], pack;
3681 for (chan = 0; chan < 3; ++chan)
3682 offset[chan] = ctx->i32zero;
3683
3684 tinfo.has_offset = true;
3685 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3686 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3687 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3688 LLVMConstInt(ctx->i32, 0x3f, false), "");
3689 if (chan)
3690 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3691 LLVMConstInt(ctx->i32, chan * 8, false), "");
3692 }
3693 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3694 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3695 address[count++] = pack;
3696
3697 }
3698 /* pack LOD bias value */
3699 if (instr->op == nir_texop_txb && bias) {
3700 address[count++] = bias;
3701 }
3702
3703 /* Pack depth comparison value */
3704 if (instr->is_shadow && comparator) {
3705 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3706 }
3707
3708 /* pack derivatives */
3709 if (ddx || ddy) {
3710 switch (instr->sampler_dim) {
3711 case GLSL_SAMPLER_DIM_3D:
3712 case GLSL_SAMPLER_DIM_CUBE:
3713 num_deriv_comp = 3;
3714 break;
3715 case GLSL_SAMPLER_DIM_2D:
3716 default:
3717 num_deriv_comp = 2;
3718 break;
3719 case GLSL_SAMPLER_DIM_1D:
3720 num_deriv_comp = 1;
3721 break;
3722 }
3723
3724 for (unsigned i = 0; i < num_deriv_comp; i++) {
3725 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3726 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3727 }
3728 }
3729
3730 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3731 for (chan = 0; chan < instr->coord_components; chan++)
3732 coords[chan] = to_float(ctx, coords[chan]);
3733 if (instr->coord_components == 3)
3734 coords[3] = LLVMGetUndef(ctx->f32);
3735 ac_prepare_cube_coords(&ctx->ac,
3736 instr->op == nir_texop_txd, instr->is_array,
3737 coords, derivs);
3738 if (num_deriv_comp)
3739 num_deriv_comp--;
3740 }
3741
3742 if (ddx || ddy) {
3743 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3744 address[count++] = derivs[i];
3745 }
3746
3747 /* Pack texture coordinates */
3748 if (coord) {
3749 address[count++] = coords[0];
3750 if (instr->coord_components > 1) {
3751 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3752 coords[1] = apply_round_slice(ctx, coords[1]);
3753 }
3754 address[count++] = coords[1];
3755 }
3756 if (instr->coord_components > 2) {
3757 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3758 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3759 coords[2] = apply_round_slice(ctx, coords[2]);
3760 }
3761 address[count++] = coords[2];
3762 }
3763 }
3764
3765 /* Pack LOD */
3766 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3767 address[count++] = lod;
3768 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3769 address[count++] = sample_index;
3770 } else if(instr->op == nir_texop_txs) {
3771 count = 0;
3772 if (lod)
3773 address[count++] = lod;
3774 else
3775 address[count++] = ctx->i32zero;
3776 }
3777
3778 for (chan = 0; chan < count; chan++) {
3779 address[chan] = LLVMBuildBitCast(ctx->builder,
3780 address[chan], ctx->i32, "");
3781 }
3782
3783 if (instr->op == nir_texop_samples_identical) {
3784 LLVMValueRef txf_address[4];
3785 struct ac_tex_info txf_info = { 0 };
3786 unsigned txf_count = count;
3787 memcpy(txf_address, address, sizeof(txf_address));
3788
3789 if (!instr->is_array)
3790 txf_address[2] = ctx->i32zero;
3791 txf_address[3] = ctx->i32zero;
3792
3793 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3794 fmask_ptr, NULL,
3795 txf_address, txf_count, 0xf);
3796
3797 result = build_tex_intrinsic(ctx, instr, &txf_info);
3798
3799 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3800 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3801 goto write_result;
3802 }
3803
3804 /* Adjust the sample index according to FMASK.
3805 *
3806 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3807 * which is the identity mapping. Each nibble says which physical sample
3808 * should be fetched to get that sample.
3809 *
3810 * For example, 0x11111100 means there are only 2 samples stored and
3811 * the second sample covers 3/4 of the pixel. When reading samples 0
3812 * and 1, return physical sample 0 (determined by the first two 0s
3813 * in FMASK), otherwise return physical sample 1.
3814 *
3815 * The sample index should be adjusted as follows:
3816 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3817 */
3818 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS) {
3819 LLVMValueRef txf_address[4];
3820 struct ac_tex_info txf_info = { 0 };
3821 unsigned txf_count = count;
3822 memcpy(txf_address, address, sizeof(txf_address));
3823
3824 if (!instr->is_array)
3825 txf_address[2] = ctx->i32zero;
3826 txf_address[3] = ctx->i32zero;
3827
3828 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3829 fmask_ptr, NULL,
3830 txf_address, txf_count, 0xf);
3831
3832 result = build_tex_intrinsic(ctx, instr, &txf_info);
3833 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3834 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3835
3836 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3837 result,
3838 ctx->i32zero, "");
3839
3840 unsigned sample_chan = instr->is_array ? 3 : 2;
3841
3842 LLVMValueRef sample_index4 =
3843 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3844 LLVMValueRef shifted_fmask =
3845 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3846 LLVMValueRef final_sample =
3847 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3848
3849 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3850 * resource descriptor is 0 (invalid),
3851 */
3852 LLVMValueRef fmask_desc =
3853 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3854 ctx->v8i32, "");
3855
3856 LLVMValueRef fmask_word1 =
3857 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3858 ctx->i32one, "");
3859
3860 LLVMValueRef word1_is_nonzero =
3861 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3862 fmask_word1, ctx->i32zero, "");
3863
3864 /* Replace the MSAA sample index. */
3865 address[sample_chan] =
3866 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3867 final_sample, address[sample_chan], "");
3868 }
3869
3870 if (offsets && instr->op == nir_texop_txf) {
3871 nir_const_value *const_offset =
3872 nir_src_as_const_value(instr->src[const_src].src);
3873 int num_offsets = instr->src[const_src].src.ssa->num_components;
3874 assert(const_offset);
3875 num_offsets = MIN2(num_offsets, instr->coord_components);
3876 if (num_offsets > 2)
3877 address[2] = LLVMBuildAdd(ctx->builder,
3878 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3879 if (num_offsets > 1)
3880 address[1] = LLVMBuildAdd(ctx->builder,
3881 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3882 address[0] = LLVMBuildAdd(ctx->builder,
3883 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3884
3885 }
3886
3887 /* TODO TG4 support */
3888 if (instr->op == nir_texop_tg4) {
3889 if (instr->is_shadow)
3890 dmask = 1;
3891 else
3892 dmask = 1 << instr->component;
3893 }
3894 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3895 res_ptr, samp_ptr, address, count, dmask);
3896
3897 result = build_tex_intrinsic(ctx, instr, &tinfo);
3898
3899 if (instr->op == nir_texop_query_levels)
3900 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3901 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3902 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3903 else if (instr->op == nir_texop_txs &&
3904 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3905 instr->is_array) {
3906 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3907 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3908 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3909 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3910 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3911 } else if (instr->dest.ssa.num_components != 4)
3912 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3913
3914 write_result:
3915 if (result) {
3916 assert(instr->dest.is_ssa);
3917 result = to_integer(ctx, result);
3918 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3919 }
3920 }
3921
3922
3923 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3924 {
3925 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3926 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3927
3928 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3929 _mesa_hash_table_insert(ctx->phis, instr, result);
3930 }
3931
3932 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3933 nir_phi_instr *instr,
3934 LLVMValueRef llvm_phi)
3935 {
3936 nir_foreach_phi_src(src, instr) {
3937 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3938 LLVMValueRef llvm_src = get_src(ctx, src->src);
3939
3940 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3941 }
3942 }
3943
3944 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3945 {
3946 struct hash_entry *entry;
3947 hash_table_foreach(ctx->phis, entry) {
3948 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3949 (LLVMValueRef)entry->data);
3950 }
3951 }
3952
3953
3954 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3955 nir_ssa_undef_instr *instr)
3956 {
3957 unsigned num_components = instr->def.num_components;
3958 LLVMValueRef undef;
3959
3960 if (num_components == 1)
3961 undef = LLVMGetUndef(ctx->i32);
3962 else {
3963 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3964 }
3965 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3966 }
3967
3968 static void visit_jump(struct nir_to_llvm_context *ctx,
3969 nir_jump_instr *instr)
3970 {
3971 switch (instr->type) {
3972 case nir_jump_break:
3973 LLVMBuildBr(ctx->builder, ctx->break_block);
3974 LLVMClearInsertionPosition(ctx->builder);
3975 break;
3976 case nir_jump_continue:
3977 LLVMBuildBr(ctx->builder, ctx->continue_block);
3978 LLVMClearInsertionPosition(ctx->builder);
3979 break;
3980 default:
3981 fprintf(stderr, "Unknown NIR jump instr: ");
3982 nir_print_instr(&instr->instr, stderr);
3983 fprintf(stderr, "\n");
3984 abort();
3985 }
3986 }
3987
3988 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3989 struct exec_list *list);
3990
3991 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3992 {
3993 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3994 nir_foreach_instr(instr, block)
3995 {
3996 switch (instr->type) {
3997 case nir_instr_type_alu:
3998 visit_alu(ctx, nir_instr_as_alu(instr));
3999 break;
4000 case nir_instr_type_load_const:
4001 visit_load_const(ctx, nir_instr_as_load_const(instr));
4002 break;
4003 case nir_instr_type_intrinsic:
4004 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4005 break;
4006 case nir_instr_type_tex:
4007 visit_tex(ctx, nir_instr_as_tex(instr));
4008 break;
4009 case nir_instr_type_phi:
4010 visit_phi(ctx, nir_instr_as_phi(instr));
4011 break;
4012 case nir_instr_type_ssa_undef:
4013 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4014 break;
4015 case nir_instr_type_jump:
4016 visit_jump(ctx, nir_instr_as_jump(instr));
4017 break;
4018 default:
4019 fprintf(stderr, "Unknown NIR instr type: ");
4020 nir_print_instr(instr, stderr);
4021 fprintf(stderr, "\n");
4022 abort();
4023 }
4024 }
4025
4026 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4027 }
4028
4029 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4030 {
4031 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4032
4033 LLVMBasicBlockRef merge_block =
4034 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4035 LLVMBasicBlockRef if_block =
4036 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4037 LLVMBasicBlockRef else_block = merge_block;
4038 if (!exec_list_is_empty(&if_stmt->else_list))
4039 else_block = LLVMAppendBasicBlockInContext(
4040 ctx->context, ctx->main_function, "");
4041
4042 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4043 LLVMConstInt(ctx->i32, 0, false), "");
4044 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4045
4046 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4047 visit_cf_list(ctx, &if_stmt->then_list);
4048 if (LLVMGetInsertBlock(ctx->builder))
4049 LLVMBuildBr(ctx->builder, merge_block);
4050
4051 if (!exec_list_is_empty(&if_stmt->else_list)) {
4052 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4053 visit_cf_list(ctx, &if_stmt->else_list);
4054 if (LLVMGetInsertBlock(ctx->builder))
4055 LLVMBuildBr(ctx->builder, merge_block);
4056 }
4057
4058 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4059 }
4060
4061 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4062 {
4063 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4064 LLVMBasicBlockRef break_parent = ctx->break_block;
4065
4066 ctx->continue_block =
4067 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4068 ctx->break_block =
4069 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4070
4071 LLVMBuildBr(ctx->builder, ctx->continue_block);
4072 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4073 visit_cf_list(ctx, &loop->body);
4074
4075 if (LLVMGetInsertBlock(ctx->builder))
4076 LLVMBuildBr(ctx->builder, ctx->continue_block);
4077 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4078
4079 ctx->continue_block = continue_parent;
4080 ctx->break_block = break_parent;
4081 }
4082
4083 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4084 struct exec_list *list)
4085 {
4086 foreach_list_typed(nir_cf_node, node, node, list)
4087 {
4088 switch (node->type) {
4089 case nir_cf_node_block:
4090 visit_block(ctx, nir_cf_node_as_block(node));
4091 break;
4092
4093 case nir_cf_node_if:
4094 visit_if(ctx, nir_cf_node_as_if(node));
4095 break;
4096
4097 case nir_cf_node_loop:
4098 visit_loop(ctx, nir_cf_node_as_loop(node));
4099 break;
4100
4101 default:
4102 assert(0);
4103 }
4104 }
4105 }
4106
4107 static void
4108 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4109 struct nir_variable *variable)
4110 {
4111 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4112 LLVMValueRef t_offset;
4113 LLVMValueRef t_list;
4114 LLVMValueRef args[3];
4115 LLVMValueRef input;
4116 LLVMValueRef buffer_index;
4117 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4118 int idx = variable->data.location;
4119 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4120
4121 variable->data.driver_location = idx * 4;
4122
4123 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4124 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4125 ctx->start_instance, "");
4126 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4127 ctx->shader_info->vs.vgpr_comp_cnt);
4128 } else
4129 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4130 ctx->base_vertex, "");
4131
4132 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4133 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4134
4135 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
4136 args[0] = t_list;
4137 args[1] = LLVMConstInt(ctx->i32, 0, false);
4138 args[2] = buffer_index;
4139 input = ac_emit_llvm_intrinsic(&ctx->ac,
4140 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
4141 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
4142
4143 for (unsigned chan = 0; chan < 4; chan++) {
4144 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4145 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4146 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4147 input, llvm_chan, ""));
4148 }
4149 }
4150 }
4151
4152
4153 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4154 unsigned attr,
4155 LLVMValueRef interp_param,
4156 LLVMValueRef prim_mask,
4157 LLVMValueRef result[4])
4158 {
4159 const char *intr_name;
4160 LLVMValueRef attr_number;
4161 unsigned chan;
4162
4163 attr_number = LLVMConstInt(ctx->i32, attr, false);
4164
4165 /* fs.constant returns the param from the middle vertex, so it's not
4166 * really useful for flat shading. It's meant to be used for custom
4167 * interpolation (but the intrinsic can't fetch from the other two
4168 * vertices).
4169 *
4170 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4171 * to do the right thing. The only reason we use fs.constant is that
4172 * fs.interp cannot be used on integers, because they can be equal
4173 * to NaN.
4174 */
4175 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
4176
4177 for (chan = 0; chan < 4; chan++) {
4178 LLVMValueRef args[4];
4179 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4180
4181 args[0] = llvm_chan;
4182 args[1] = attr_number;
4183 args[2] = prim_mask;
4184 args[3] = interp_param;
4185 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
4186 ctx->f32, args, args[3] ? 4 : 3,
4187 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
4188 }
4189 }
4190
4191 static void
4192 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4193 struct nir_variable *variable)
4194 {
4195 int idx = variable->data.location;
4196 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4197 LLVMValueRef interp;
4198
4199 variable->data.driver_location = idx * 4;
4200 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4201
4202 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4203 unsigned interp_type;
4204 if (variable->data.sample) {
4205 interp_type = INTERP_SAMPLE;
4206 ctx->shader_info->fs.force_persample = true;
4207 } else if (variable->data.centroid)
4208 interp_type = INTERP_CENTROID;
4209 else
4210 interp_type = INTERP_CENTER;
4211
4212 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4213 } else
4214 interp = NULL;
4215
4216 for (unsigned i = 0; i < attrib_count; ++i)
4217 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4218
4219 }
4220
4221 static void
4222 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4223 struct nir_variable *variable)
4224 {
4225 switch (ctx->stage) {
4226 case MESA_SHADER_VERTEX:
4227 handle_vs_input_decl(ctx, variable);
4228 break;
4229 case MESA_SHADER_FRAGMENT:
4230 handle_fs_input_decl(ctx, variable);
4231 break;
4232 default:
4233 break;
4234 }
4235
4236 }
4237
4238 static void
4239 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4240 struct nir_shader *nir)
4241 {
4242 unsigned index = 0;
4243 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4244 LLVMValueRef interp_param;
4245 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4246
4247 if (!(ctx->input_mask & (1ull << i)))
4248 continue;
4249
4250 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4251 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4252 interp_param = *inputs;
4253 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4254 inputs);
4255
4256 if (!interp_param)
4257 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4258 ++index;
4259 } else if (i == VARYING_SLOT_POS) {
4260 for(int i = 0; i < 3; ++i)
4261 inputs[i] = ctx->frag_pos[i];
4262
4263 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4264 }
4265 }
4266 ctx->shader_info->fs.num_interp = index;
4267 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4268 ctx->shader_info->fs.has_pcoord = true;
4269 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4270 ctx->shader_info->fs.prim_id_input = true;
4271 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4272 ctx->shader_info->fs.layer_input = true;
4273 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4274 }
4275
4276 static LLVMValueRef
4277 ac_build_alloca(struct nir_to_llvm_context *ctx,
4278 LLVMTypeRef type,
4279 const char *name)
4280 {
4281 LLVMBuilderRef builder = ctx->builder;
4282 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4283 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4284 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4285 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4286 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4287 LLVMValueRef res;
4288
4289 if (first_instr) {
4290 LLVMPositionBuilderBefore(first_builder, first_instr);
4291 } else {
4292 LLVMPositionBuilderAtEnd(first_builder, first_block);
4293 }
4294
4295 res = LLVMBuildAlloca(first_builder, type, name);
4296 LLVMBuildStore(builder, LLVMConstNull(type), res);
4297
4298 LLVMDisposeBuilder(first_builder);
4299
4300 return res;
4301 }
4302
4303 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4304 LLVMTypeRef type,
4305 const char *name)
4306 {
4307 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4308 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4309 return ptr;
4310 }
4311
4312 static void
4313 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4314 struct nir_variable *variable)
4315 {
4316 int idx = variable->data.location + variable->data.index;
4317 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4318
4319 variable->data.driver_location = idx * 4;
4320
4321 if (ctx->stage == MESA_SHADER_VERTEX) {
4322
4323 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4324 idx == VARYING_SLOT_CULL_DIST0) {
4325 int length = glsl_get_length(variable->type);
4326 if (idx == VARYING_SLOT_CLIP_DIST0) {
4327 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4328 ctx->num_clips = length;
4329 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4330 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4331 ctx->num_culls = length;
4332 }
4333 if (length > 4)
4334 attrib_count = 2;
4335 else
4336 attrib_count = 1;
4337 }
4338 }
4339
4340 for (unsigned i = 0; i < attrib_count; ++i) {
4341 for (unsigned chan = 0; chan < 4; chan++) {
4342 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4343 si_build_alloca_undef(ctx, ctx->f32, "");
4344 }
4345 }
4346 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4347 }
4348
4349 static void
4350 setup_locals(struct nir_to_llvm_context *ctx,
4351 struct nir_function *func)
4352 {
4353 int i, j;
4354 ctx->num_locals = 0;
4355 nir_foreach_variable(variable, &func->impl->locals) {
4356 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4357 variable->data.driver_location = ctx->num_locals * 4;
4358 ctx->num_locals += attrib_count;
4359 }
4360 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4361 if (!ctx->locals)
4362 return;
4363
4364 for (i = 0; i < ctx->num_locals; i++) {
4365 for (j = 0; j < 4; j++) {
4366 ctx->locals[i * 4 + j] =
4367 si_build_alloca_undef(ctx, ctx->f32, "temp");
4368 }
4369 }
4370 }
4371
4372 static LLVMValueRef
4373 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4374 {
4375 v = to_float(ctx, v);
4376 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4377 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4378 }
4379
4380
4381 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4382 LLVMValueRef src0, LLVMValueRef src1)
4383 {
4384 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4385 LLVMValueRef comp[2];
4386
4387 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4388 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4389 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4390 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4391 }
4392
4393 /* Initialize arguments for the shader export intrinsic */
4394 static void
4395 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4396 LLVMValueRef *values,
4397 unsigned target,
4398 LLVMValueRef *args)
4399 {
4400 /* Default is 0xf. Adjusted below depending on the format. */
4401 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4402 /* Specify whether the EXEC mask represents the valid mask */
4403 args[1] = LLVMConstInt(ctx->i32, 0, false);
4404
4405 /* Specify whether this is the last export */
4406 args[2] = LLVMConstInt(ctx->i32, 0, false);
4407 /* Specify the target we are exporting */
4408 args[3] = LLVMConstInt(ctx->i32, target, false);
4409
4410 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4411 args[5] = LLVMGetUndef(ctx->f32);
4412 args[6] = LLVMGetUndef(ctx->f32);
4413 args[7] = LLVMGetUndef(ctx->f32);
4414 args[8] = LLVMGetUndef(ctx->f32);
4415
4416 if (!values)
4417 return;
4418
4419 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4420 LLVMValueRef val[4];
4421 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4422 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4423 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4424
4425 switch(col_format) {
4426 case V_028714_SPI_SHADER_ZERO:
4427 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4428 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4429 break;
4430
4431 case V_028714_SPI_SHADER_32_R:
4432 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4433 args[5] = values[0];
4434 break;
4435
4436 case V_028714_SPI_SHADER_32_GR:
4437 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4438 args[5] = values[0];
4439 args[6] = values[1];
4440 break;
4441
4442 case V_028714_SPI_SHADER_32_AR:
4443 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4444 args[5] = values[0];
4445 args[8] = values[3];
4446 break;
4447
4448 case V_028714_SPI_SHADER_FP16_ABGR:
4449 args[4] = ctx->i32one;
4450
4451 for (unsigned chan = 0; chan < 2; chan++) {
4452 LLVMValueRef pack_args[2] = {
4453 values[2 * chan],
4454 values[2 * chan + 1]
4455 };
4456 LLVMValueRef packed;
4457
4458 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4459 ctx->i32, pack_args, 2,
4460 AC_FUNC_ATTR_READNONE);
4461 args[chan + 5] = packed;
4462 }
4463 break;
4464
4465 case V_028714_SPI_SHADER_UNORM16_ABGR:
4466 for (unsigned chan = 0; chan < 4; chan++) {
4467 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4468 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4469 LLVMConstReal(ctx->f32, 65535), "");
4470 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4471 LLVMConstReal(ctx->f32, 0.5), "");
4472 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4473 ctx->i32, "");
4474 }
4475
4476 args[4] = ctx->i32one;
4477 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4478 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4479 break;
4480
4481 case V_028714_SPI_SHADER_SNORM16_ABGR:
4482 for (unsigned chan = 0; chan < 4; chan++) {
4483 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4484 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4485 LLVMConstReal(ctx->f32, 32767), "");
4486
4487 /* If positive, add 0.5, else add -0.5. */
4488 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4489 LLVMBuildSelect(ctx->builder,
4490 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4491 val[chan], ctx->f32zero, ""),
4492 LLVMConstReal(ctx->f32, 0.5),
4493 LLVMConstReal(ctx->f32, -0.5), ""), "");
4494 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4495 }
4496
4497 args[4] = ctx->i32one;
4498 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4499 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4500 break;
4501
4502 case V_028714_SPI_SHADER_UINT16_ABGR: {
4503 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4504
4505 for (unsigned chan = 0; chan < 4; chan++) {
4506 val[chan] = to_integer(ctx, values[chan]);
4507 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4508 }
4509
4510 args[4] = ctx->i32one;
4511 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4512 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4513 break;
4514 }
4515
4516 case V_028714_SPI_SHADER_SINT16_ABGR: {
4517 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4518 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4519
4520 /* Clamp. */
4521 for (unsigned chan = 0; chan < 4; chan++) {
4522 val[chan] = to_integer(ctx, values[chan]);
4523 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4524 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4525 }
4526
4527 args[4] = ctx->i32one;
4528 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4529 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4530 break;
4531 }
4532
4533 default:
4534 case V_028714_SPI_SHADER_32_ABGR:
4535 memcpy(&args[5], values, sizeof(values[0]) * 4);
4536 break;
4537 }
4538 } else
4539 memcpy(&args[5], values, sizeof(values[0]) * 4);
4540
4541 for (unsigned i = 5; i < 9; ++i)
4542 args[i] = to_float(ctx, args[i]);
4543 }
4544
4545 static void
4546 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4547 {
4548 uint32_t param_count = 0;
4549 unsigned target;
4550 unsigned pos_idx, num_pos_exports = 0;
4551 LLVMValueRef args[9];
4552 LLVMValueRef pos_args[4][9] = { { 0 } };
4553 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4554 int i;
4555 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4556 (1ull << VARYING_SLOT_CLIP_DIST1) |
4557 (1ull << VARYING_SLOT_CULL_DIST0) |
4558 (1ull << VARYING_SLOT_CULL_DIST1));
4559
4560 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4561 ctx->shader_info->vs.layer_output = 0xffffffff;
4562 if (clip_mask) {
4563 LLVMValueRef slots[8];
4564 unsigned j;
4565
4566 if (ctx->shader_info->vs.cull_dist_mask)
4567 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_clips;
4568
4569 i = VARYING_SLOT_CLIP_DIST0;
4570 for (j = 0; j < ctx->num_clips; j++)
4571 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4572 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4573 i = VARYING_SLOT_CULL_DIST0;
4574 for (j = 0; j < ctx->num_culls; j++)
4575 slots[ctx->num_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4576 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4577
4578 for (i = ctx->num_clips + ctx->num_culls; i < 8; i++)
4579 slots[i] = LLVMGetUndef(ctx->f32);
4580
4581 if (ctx->num_clips + ctx->num_culls > 4) {
4582 target = V_008DFC_SQ_EXP_POS + 3;
4583 si_llvm_init_export_args(ctx, &slots[4], target, args);
4584 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4585 args, sizeof(args));
4586 }
4587
4588 target = V_008DFC_SQ_EXP_POS + 2;
4589 si_llvm_init_export_args(ctx, &slots[0], target, args);
4590 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4591 args, sizeof(args));
4592
4593 }
4594
4595 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4596 LLVMValueRef values[4];
4597 if (!(ctx->output_mask & (1ull << i)))
4598 continue;
4599
4600 for (unsigned j = 0; j < 4; j++)
4601 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4602 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4603
4604 if (i == VARYING_SLOT_POS) {
4605 target = V_008DFC_SQ_EXP_POS;
4606 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4607 i == VARYING_SLOT_CLIP_DIST1 ||
4608 i == VARYING_SLOT_CULL_DIST0 ||
4609 i == VARYING_SLOT_CULL_DIST1) {
4610 continue;
4611 } else if (i == VARYING_SLOT_PSIZ) {
4612 ctx->shader_info->vs.writes_pointsize = true;
4613 psize_value = values[0];
4614 continue;
4615 } else if (i == VARYING_SLOT_LAYER) {
4616 ctx->shader_info->vs.writes_layer = true;
4617 layer_value = values[0];
4618 ctx->shader_info->vs.layer_output = param_count;
4619 target = V_008DFC_SQ_EXP_PARAM + param_count;
4620 param_count++;
4621 } else if (i == VARYING_SLOT_VIEWPORT) {
4622 ctx->shader_info->vs.writes_viewport_index = true;
4623 viewport_index_value = values[0];
4624 continue;
4625 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4626 ctx->shader_info->vs.prim_id_output = param_count;
4627 target = V_008DFC_SQ_EXP_PARAM + param_count;
4628 param_count++;
4629 } else if (i >= VARYING_SLOT_VAR0) {
4630 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4631 target = V_008DFC_SQ_EXP_PARAM + param_count;
4632 param_count++;
4633 }
4634
4635 si_llvm_init_export_args(ctx, values, target, args);
4636
4637 if (target >= V_008DFC_SQ_EXP_POS &&
4638 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4639 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4640 args, sizeof(args));
4641 } else {
4642 ac_emit_llvm_intrinsic(&ctx->ac,
4643 "llvm.SI.export",
4644 ctx->voidt,
4645 args, 9, 0);
4646 }
4647 }
4648
4649 /* We need to add the position output manually if it's missing. */
4650 if (!pos_args[0][0]) {
4651 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4652 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4653 pos_args[0][2] = ctx->i32zero; /* last export? */
4654 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4655 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4656 pos_args[0][5] = ctx->f32zero; /* X */
4657 pos_args[0][6] = ctx->f32zero; /* Y */
4658 pos_args[0][7] = ctx->f32zero; /* Z */
4659 pos_args[0][8] = ctx->f32one; /* W */
4660 }
4661
4662 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4663 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4664 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4665 if (mask) {
4666 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4667 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4668 pos_args[1][2] = ctx->i32zero; /* last export? */
4669 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4670 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4671 pos_args[1][5] = ctx->f32zero; /* X */
4672 pos_args[1][6] = ctx->f32zero; /* Y */
4673 pos_args[1][7] = ctx->f32zero; /* Z */
4674 pos_args[1][8] = ctx->f32zero; /* W */
4675
4676 if (ctx->shader_info->vs.writes_pointsize == true)
4677 pos_args[1][5] = psize_value;
4678 if (ctx->shader_info->vs.writes_layer == true)
4679 pos_args[1][7] = layer_value;
4680 if (ctx->shader_info->vs.writes_viewport_index == true)
4681 pos_args[1][8] = viewport_index_value;
4682 }
4683 for (i = 0; i < 4; i++) {
4684 if (pos_args[i][0])
4685 num_pos_exports++;
4686 }
4687
4688 pos_idx = 0;
4689 for (i = 0; i < 4; i++) {
4690 if (!pos_args[i][0])
4691 continue;
4692
4693 /* Specify the target we are exporting */
4694 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4695 if (pos_idx == num_pos_exports)
4696 pos_args[i][2] = ctx->i32one;
4697 ac_emit_llvm_intrinsic(&ctx->ac,
4698 "llvm.SI.export",
4699 ctx->voidt,
4700 pos_args[i], 9, 0);
4701 }
4702
4703 ctx->shader_info->vs.pos_exports = num_pos_exports;
4704 ctx->shader_info->vs.param_exports = param_count;
4705 }
4706
4707 static void
4708 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4709 {
4710 int j;
4711 uint64_t max_output_written = 0;
4712 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4713 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4714 int param_index;
4715 if (!(ctx->output_mask & (1ull << i)))
4716 continue;
4717
4718 param_index = shader_io_get_unique_index(i);
4719
4720 if (param_index > max_output_written)
4721 max_output_written = param_index;
4722
4723 for (j = 0; j < 4; j++) {
4724 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4725 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4726
4727 build_tbuffer_store(ctx,
4728 ctx->esgs_ring,
4729 out_val, 1,
4730 LLVMGetUndef(ctx->i32), ctx->es2gs_offset,
4731 (4 * param_index + j) * 4,
4732 V_008F0C_BUF_DATA_FORMAT_32,
4733 V_008F0C_BUF_NUM_FORMAT_UINT,
4734 0, 0, 1, 1, 0);
4735 }
4736 }
4737 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4738 }
4739
4740 static void
4741 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4742 LLVMValueRef *color, unsigned param, bool is_last)
4743 {
4744 LLVMValueRef args[9];
4745 /* Export */
4746 si_llvm_init_export_args(ctx, color, param,
4747 args);
4748
4749 if (is_last) {
4750 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4751 args[2] = ctx->i32one; /* DONE bit */
4752 } else if (args[0] == ctx->i32zero)
4753 return; /* unnecessary NULL export */
4754
4755 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4756 ctx->voidt, args, 9, 0);
4757 }
4758
4759 static void
4760 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4761 LLVMValueRef depth, LLVMValueRef stencil,
4762 LLVMValueRef samplemask)
4763 {
4764 LLVMValueRef args[9];
4765 unsigned mask = 0;
4766 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4767 args[2] = ctx->i32one; /* DONE bit */
4768 /* Specify the target we are exporting */
4769 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4770
4771 args[4] = ctx->i32zero; /* COMP flag */
4772 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4773 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4774 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4775 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4776
4777 if (depth) {
4778 args[5] = depth;
4779 mask |= 0x1;
4780 }
4781
4782 if (stencil) {
4783 args[6] = stencil;
4784 mask |= 0x2;
4785 }
4786
4787 if (samplemask) {
4788 args[7] = samplemask;
4789 mask |= 0x04;
4790 }
4791
4792 /* SI (except OLAND) has a bug that it only looks
4793 * at the X writemask component. */
4794 if (ctx->options->chip_class == SI &&
4795 ctx->options->family != CHIP_OLAND)
4796 mask |= 0x01;
4797
4798 args[0] = LLVMConstInt(ctx->i32, mask, false);
4799 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4800 ctx->voidt, args, 9, 0);
4801 }
4802
4803 static void
4804 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4805 {
4806 unsigned index = 0;
4807 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4808
4809 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4810 LLVMValueRef values[4];
4811
4812 if (!(ctx->output_mask & (1ull << i)))
4813 continue;
4814
4815 if (i == FRAG_RESULT_DEPTH) {
4816 ctx->shader_info->fs.writes_z = true;
4817 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4818 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4819 } else if (i == FRAG_RESULT_STENCIL) {
4820 ctx->shader_info->fs.writes_stencil = true;
4821 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4822 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4823 } else {
4824 bool last = false;
4825 for (unsigned j = 0; j < 4; j++)
4826 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4827 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4828
4829 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4830 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4831
4832 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4833 index++;
4834 }
4835 }
4836
4837 if (depth || stencil)
4838 si_export_mrt_z(ctx, depth, stencil, samplemask);
4839 else if (!index)
4840 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4841
4842 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4843 }
4844
4845 static void
4846 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4847 {
4848 LLVMValueRef args[2];
4849
4850 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE, false);
4851 args[1] = ctx->gs_wave_id;
4852 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
4853 ctx->voidt, args, 2, 0);
4854 }
4855
4856 static void
4857 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4858 {
4859 switch (ctx->stage) {
4860 case MESA_SHADER_VERTEX:
4861 if (ctx->options->key.vs.as_es)
4862 handle_es_outputs_post(ctx);
4863 else
4864 handle_vs_outputs_post(ctx);
4865 break;
4866 case MESA_SHADER_FRAGMENT:
4867 handle_fs_outputs_post(ctx);
4868 break;
4869 case MESA_SHADER_GEOMETRY:
4870 emit_gs_epilogue(ctx);
4871 break;
4872 default:
4873 break;
4874 }
4875 }
4876
4877 static void
4878 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4879 struct nir_variable *variable, uint32_t *offset, int idx)
4880 {
4881 unsigned size = glsl_count_attribute_slots(variable->type, false);
4882 variable->data.driver_location = *offset;
4883 *offset += size;
4884 }
4885
4886 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4887 {
4888 LLVMPassManagerRef passmgr;
4889 /* Create the pass manager */
4890 passmgr = LLVMCreateFunctionPassManagerForModule(
4891 ctx->module);
4892
4893 /* This pass should eliminate all the load and store instructions */
4894 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4895
4896 /* Add some optimization passes */
4897 LLVMAddScalarReplAggregatesPass(passmgr);
4898 LLVMAddLICMPass(passmgr);
4899 LLVMAddAggressiveDCEPass(passmgr);
4900 LLVMAddCFGSimplificationPass(passmgr);
4901 LLVMAddInstructionCombiningPass(passmgr);
4902
4903 /* Run the pass */
4904 LLVMInitializeFunctionPassManager(passmgr);
4905 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4906 LLVMFinalizeFunctionPassManager(passmgr);
4907
4908 LLVMDisposeBuilder(ctx->builder);
4909 LLVMDisposePassManager(passmgr);
4910 }
4911
4912 static void
4913 ac_setup_rings(struct nir_to_llvm_context *ctx)
4914 {
4915 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4916 ctx->esgs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, ctx->i32one);
4917 }
4918
4919 if (ctx->is_gs_copy_shader) {
4920 ctx->gsvs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4921 }
4922 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4923 LLVMValueRef tmp;
4924 ctx->esgs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4925 ctx->gsvs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4926
4927 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4928
4929 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4930 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4931 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4932 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4933
4934 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4935 }
4936 }
4937
4938 static
4939 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4940 struct nir_shader *nir,
4941 struct ac_shader_variant_info *shader_info,
4942 const struct ac_nir_compiler_options *options)
4943 {
4944 struct nir_to_llvm_context ctx = {0};
4945 struct nir_function *func;
4946 unsigned i;
4947 ctx.options = options;
4948 ctx.shader_info = shader_info;
4949 ctx.context = LLVMContextCreate();
4950 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4951
4952 ac_llvm_context_init(&ctx.ac, ctx.context);
4953 ctx.ac.module = ctx.module;
4954
4955 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4956
4957 memset(shader_info, 0, sizeof(*shader_info));
4958
4959 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4960 setup_types(&ctx);
4961
4962 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4963 ctx.ac.builder = ctx.builder;
4964 ctx.stage = nir->stage;
4965
4966 for (i = 0; i < AC_UD_MAX_SETS; i++)
4967 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4968 for (i = 0; i < AC_UD_MAX_UD; i++)
4969 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4970
4971 create_function(&ctx);
4972
4973 if (nir->stage == MESA_SHADER_COMPUTE) {
4974 int num_shared = 0;
4975 nir_foreach_variable(variable, &nir->shared)
4976 num_shared++;
4977 if (num_shared) {
4978 int idx = 0;
4979 uint32_t shared_size = 0;
4980 LLVMValueRef var;
4981 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4982 nir_foreach_variable(variable, &nir->shared) {
4983 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4984 idx++;
4985 }
4986
4987 shared_size *= 4;
4988 var = LLVMAddGlobalInAddressSpace(ctx.module,
4989 LLVMArrayType(ctx.i8, shared_size),
4990 "compute_lds",
4991 LOCAL_ADDR_SPACE);
4992 LLVMSetAlignment(var, 4);
4993 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4994 }
4995 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4996 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4997
4998 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4999 }
5000
5001 ac_setup_rings(&ctx);
5002
5003 nir_foreach_variable(variable, &nir->inputs)
5004 handle_shader_input_decl(&ctx, variable);
5005
5006 if (nir->stage == MESA_SHADER_FRAGMENT)
5007 handle_fs_inputs_pre(&ctx, nir);
5008
5009 nir_foreach_variable(variable, &nir->outputs)
5010 handle_shader_output_decl(&ctx, variable);
5011
5012 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5013 _mesa_key_pointer_equal);
5014 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5015 _mesa_key_pointer_equal);
5016
5017 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5018
5019 setup_locals(&ctx, func);
5020
5021 visit_cf_list(&ctx, &func->impl->body);
5022 phi_post_pass(&ctx);
5023
5024 handle_shader_outputs_post(&ctx);
5025 LLVMBuildRetVoid(ctx.builder);
5026
5027 ac_llvm_finalize_module(&ctx);
5028 free(ctx.locals);
5029 ralloc_free(ctx.defs);
5030 ralloc_free(ctx.phis);
5031
5032 if (nir->stage == MESA_SHADER_GEOMETRY) {
5033 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
5034 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5035 nir->info->gs.vertices_out;
5036 }
5037 return ctx.module;
5038 }
5039
5040 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
5041 {
5042 unsigned *retval = (unsigned *)context;
5043 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5044 char *description = LLVMGetDiagInfoDescription(di);
5045
5046 if (severity == LLVMDSError) {
5047 *retval = 1;
5048 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5049 description);
5050 }
5051
5052 LLVMDisposeMessage(description);
5053 }
5054
5055 static unsigned ac_llvm_compile(LLVMModuleRef M,
5056 struct ac_shader_binary *binary,
5057 LLVMTargetMachineRef tm)
5058 {
5059 unsigned retval = 0;
5060 char *err;
5061 LLVMContextRef llvm_ctx;
5062 LLVMMemoryBufferRef out_buffer;
5063 unsigned buffer_size;
5064 const char *buffer_data;
5065 LLVMBool mem_err;
5066
5067 /* Setup Diagnostic Handler*/
5068 llvm_ctx = LLVMGetModuleContext(M);
5069
5070 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5071 &retval);
5072
5073 /* Compile IR*/
5074 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5075 &err, &out_buffer);
5076
5077 /* Process Errors/Warnings */
5078 if (mem_err) {
5079 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5080 free(err);
5081 retval = 1;
5082 goto out;
5083 }
5084
5085 /* Extract Shader Code*/
5086 buffer_size = LLVMGetBufferSize(out_buffer);
5087 buffer_data = LLVMGetBufferStart(out_buffer);
5088
5089 ac_elf_read(buffer_data, buffer_size, binary);
5090
5091 /* Clean up */
5092 LLVMDisposeMemoryBuffer(out_buffer);
5093
5094 out:
5095 return retval;
5096 }
5097
5098 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5099 LLVMModuleRef llvm_module,
5100 struct ac_shader_binary *binary,
5101 struct ac_shader_config *config,
5102 struct ac_shader_variant_info *shader_info,
5103 gl_shader_stage stage,
5104 bool dump_shader, bool supports_spill)
5105 {
5106 if (dump_shader)
5107 ac_dump_module(llvm_module);
5108
5109 memset(binary, 0, sizeof(*binary));
5110 int v = ac_llvm_compile(llvm_module, binary, tm);
5111 if (v) {
5112 fprintf(stderr, "compile failed\n");
5113 }
5114
5115 if (dump_shader)
5116 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5117
5118 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5119
5120 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5121 LLVMDisposeModule(llvm_module);
5122 LLVMContextDispose(ctx);
5123
5124 if (stage == MESA_SHADER_FRAGMENT) {
5125 shader_info->num_input_vgprs = 0;
5126 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5127 shader_info->num_input_vgprs += 2;
5128 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5129 shader_info->num_input_vgprs += 2;
5130 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5131 shader_info->num_input_vgprs += 2;
5132 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5133 shader_info->num_input_vgprs += 3;
5134 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5135 shader_info->num_input_vgprs += 2;
5136 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5137 shader_info->num_input_vgprs += 2;
5138 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5139 shader_info->num_input_vgprs += 2;
5140 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5141 shader_info->num_input_vgprs += 1;
5142 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5143 shader_info->num_input_vgprs += 1;
5144 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5145 shader_info->num_input_vgprs += 1;
5146 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5147 shader_info->num_input_vgprs += 1;
5148 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5149 shader_info->num_input_vgprs += 1;
5150 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5151 shader_info->num_input_vgprs += 1;
5152 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5153 shader_info->num_input_vgprs += 1;
5154 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5155 shader_info->num_input_vgprs += 1;
5156 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5157 shader_info->num_input_vgprs += 1;
5158 }
5159 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5160
5161 /* +3 for scratch wave offset and VCC */
5162 config->num_sgprs = MAX2(config->num_sgprs,
5163 shader_info->num_input_sgprs + 3);
5164 }
5165
5166 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5167 struct ac_shader_binary *binary,
5168 struct ac_shader_config *config,
5169 struct ac_shader_variant_info *shader_info,
5170 struct nir_shader *nir,
5171 const struct ac_nir_compiler_options *options,
5172 bool dump_shader)
5173 {
5174
5175 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5176 options);
5177
5178 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5179 switch (nir->stage) {
5180 case MESA_SHADER_COMPUTE:
5181 for (int i = 0; i < 3; ++i)
5182 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5183 break;
5184 case MESA_SHADER_FRAGMENT:
5185 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5186 break;
5187 case MESA_SHADER_GEOMETRY:
5188 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5189 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5190 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5191 shader_info->gs.invocations = nir->info->gs.invocations;
5192 break;
5193 case MESA_SHADER_VERTEX:
5194 shader_info->vs.as_es = options->key.vs.as_es;
5195 break;
5196 default:
5197 break;
5198 }
5199 }
5200
5201 static void
5202 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5203 {
5204 LLVMValueRef args[9];
5205 args[0] = ctx->gsvs_ring;
5206 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5207 args[3] = ctx->i32zero;
5208 args[4] = ctx->i32one; /* OFFEN */
5209 args[5] = ctx->i32zero; /* IDXEN */
5210 args[6] = ctx->i32one; /* GLC */
5211 args[7] = ctx->i32one; /* SLC */
5212 args[8] = ctx->i32zero; /* TFE */
5213
5214 int idx = 0;
5215 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5216 if (!(ctx->output_mask & (1ull << i)))
5217 continue;
5218
5219 for (unsigned j = 0; j < 4; j++) {
5220 LLVMValueRef value;
5221 args[2] = LLVMConstInt(ctx->i32,
5222 (idx * 4 + j) *
5223 ctx->gs_max_out_vertices * 16 * 4, false);
5224
5225 value = ac_emit_llvm_intrinsic(&ctx->ac,
5226 "llvm.SI.buffer.load.dword.i32.i32",
5227 ctx->i32, args, 9,
5228 AC_FUNC_ATTR_READONLY);
5229
5230 LLVMBuildStore(ctx->builder,
5231 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5232 }
5233 idx++;
5234 }
5235 handle_vs_outputs_post(ctx);
5236 }
5237
5238 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5239 struct nir_shader *geom_shader,
5240 struct ac_shader_binary *binary,
5241 struct ac_shader_config *config,
5242 struct ac_shader_variant_info *shader_info,
5243 const struct ac_nir_compiler_options *options,
5244 bool dump_shader)
5245 {
5246 struct nir_to_llvm_context ctx = {0};
5247 ctx.context = LLVMContextCreate();
5248 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5249 ctx.options = options;
5250 ctx.shader_info = shader_info;
5251
5252 ac_llvm_context_init(&ctx.ac, ctx.context);
5253 ctx.ac.module = ctx.module;
5254
5255 ctx.is_gs_copy_shader = true;
5256 LLVMSetTarget(ctx.module, "amdgcn--");
5257 setup_types(&ctx);
5258
5259 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5260 ctx.ac.builder = ctx.builder;
5261 ctx.stage = MESA_SHADER_VERTEX;
5262
5263 create_function(&ctx);
5264
5265 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5266 ac_setup_rings(&ctx);
5267
5268 nir_foreach_variable(variable, &geom_shader->outputs)
5269 handle_shader_output_decl(&ctx, variable);
5270
5271 ac_gs_copy_shader_emit(&ctx);
5272
5273 LLVMBuildRetVoid(ctx.builder);
5274
5275 ac_llvm_finalize_module(&ctx);
5276
5277 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5278 MESA_SHADER_VERTEX,
5279 dump_shader, options->supports_spill);
5280 }