2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
38 enum radeon_llvm_calling_convention
{
39 RADEON_LLVM_AMDGPU_VS
= 87,
40 RADEON_LLVM_AMDGPU_GS
= 88,
41 RADEON_LLVM_AMDGPU_PS
= 89,
42 RADEON_LLVM_AMDGPU_CS
= 90,
43 RADEON_LLVM_AMDGPU_HS
= 93,
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
52 struct nir_to_llvm_context
;
54 struct ac_nir_context
{
55 struct ac_llvm_context ac
;
56 struct ac_shader_abi
*abi
;
58 gl_shader_stage stage
;
60 struct hash_table
*defs
;
61 struct hash_table
*phis
;
62 struct hash_table
*vars
;
64 LLVMValueRef main_function
;
65 LLVMBasicBlockRef continue_block
;
66 LLVMBasicBlockRef break_block
;
68 LLVMValueRef outputs
[RADEON_LLVM_MAX_OUTPUTS
* 4];
73 struct nir_to_llvm_context
*nctx
; /* TODO get rid of this */
76 struct nir_to_llvm_context
{
77 struct ac_llvm_context ac
;
78 const struct ac_nir_compiler_options
*options
;
79 struct ac_shader_variant_info
*shader_info
;
80 struct ac_shader_abi abi
;
81 struct ac_nir_context
*nir
;
83 unsigned max_workgroup_size
;
84 LLVMContextRef context
;
86 LLVMBuilderRef builder
;
87 LLVMValueRef main_function
;
89 struct hash_table
*defs
;
90 struct hash_table
*phis
;
92 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
93 LLVMValueRef ring_offsets
;
94 LLVMValueRef push_constants
;
95 LLVMValueRef view_index
;
96 LLVMValueRef num_work_groups
;
97 LLVMValueRef workgroup_ids
;
98 LLVMValueRef local_invocation_ids
;
101 LLVMValueRef vertex_buffers
;
102 LLVMValueRef rel_auto_id
;
103 LLVMValueRef vs_prim_id
;
104 LLVMValueRef ls_out_layout
;
105 LLVMValueRef es2gs_offset
;
107 LLVMValueRef tcs_offchip_layout
;
108 LLVMValueRef tcs_out_offsets
;
109 LLVMValueRef tcs_out_layout
;
110 LLVMValueRef tcs_in_layout
;
112 LLVMValueRef merged_wave_info
;
113 LLVMValueRef tess_factor_offset
;
114 LLVMValueRef tcs_patch_id
;
115 LLVMValueRef tcs_rel_ids
;
116 LLVMValueRef tes_rel_patch_id
;
117 LLVMValueRef tes_patch_id
;
121 LLVMValueRef gsvs_ring_stride
;
122 LLVMValueRef gsvs_num_entries
;
123 LLVMValueRef gs2vs_offset
;
124 LLVMValueRef gs_wave_id
;
125 LLVMValueRef gs_vtx_offset
[6];
127 LLVMValueRef esgs_ring
;
128 LLVMValueRef gsvs_ring
;
129 LLVMValueRef hs_ring_tess_offchip
;
130 LLVMValueRef hs_ring_tess_factor
;
132 LLVMValueRef prim_mask
;
133 LLVMValueRef sample_pos_offset
;
134 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
135 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
137 gl_shader_stage stage
;
139 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
142 uint64_t output_mask
;
143 uint8_t num_output_clips
;
144 uint8_t num_output_culls
;
146 bool is_gs_copy_shader
;
147 LLVMValueRef gs_next_vertex
;
148 unsigned gs_max_out_vertices
;
150 unsigned tes_primitive_mode
;
151 uint64_t tess_outputs_written
;
152 uint64_t tess_patch_outputs_written
;
154 uint32_t tcs_patch_outputs_read
;
155 uint64_t tcs_outputs_read
;
158 static inline struct nir_to_llvm_context
*
159 nir_to_llvm_context_from_abi(struct ac_shader_abi
*abi
)
161 struct nir_to_llvm_context
*ctx
= NULL
;
162 return container_of(abi
, ctx
, abi
);
166 nir2llvmtype(struct ac_nir_context
*ctx
,
167 const struct glsl_type
*type
)
169 switch (glsl_get_base_type(glsl_without_array(type
))) {
173 case GLSL_TYPE_UINT64
:
174 case GLSL_TYPE_INT64
:
176 case GLSL_TYPE_DOUBLE
:
178 case GLSL_TYPE_FLOAT
:
181 assert(!"Unsupported type in nir2llvmtype()");
187 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
188 const nir_deref_var
*deref
,
189 enum ac_descriptor_type desc_type
,
190 const nir_tex_instr
*instr
,
191 bool image
, bool write
);
193 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
195 return (index
* 4) + chan
;
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
200 /* handle patch indices separate */
201 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
203 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
205 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
206 return 2 + (slot
- VARYING_SLOT_PATCH0
);
208 if (slot
== VARYING_SLOT_POS
)
210 if (slot
== VARYING_SLOT_PSIZ
)
212 if (slot
== VARYING_SLOT_CLIP_DIST0
)
214 /* 3 is reserved for clip dist as well */
215 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
216 return 4 + (slot
- VARYING_SLOT_VAR0
);
217 unreachable("illegal slot in get unique index\n");
220 static void set_llvm_calling_convention(LLVMValueRef func
,
221 gl_shader_stage stage
)
223 enum radeon_llvm_calling_convention calling_conv
;
226 case MESA_SHADER_VERTEX
:
227 case MESA_SHADER_TESS_EVAL
:
228 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
230 case MESA_SHADER_GEOMETRY
:
231 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
233 case MESA_SHADER_TESS_CTRL
:
234 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
236 case MESA_SHADER_FRAGMENT
:
237 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
239 case MESA_SHADER_COMPUTE
:
240 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
243 unreachable("Unhandle shader type");
246 LLVMSetFunctionCallConv(func
, calling_conv
);
251 LLVMTypeRef types
[MAX_ARGS
];
252 LLVMValueRef
*assign
[MAX_ARGS
];
253 unsigned array_params_mask
;
255 uint8_t user_sgpr_count
;
257 uint8_t num_user_sgprs_used
;
258 uint8_t num_sgprs_used
;
259 uint8_t num_vgprs_used
;
263 add_argument(struct arg_info
*info
,
264 LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
266 assert(info
->count
< MAX_ARGS
);
267 info
->assign
[info
->count
] = param_ptr
;
268 info
->types
[info
->count
] = type
;
273 add_sgpr_argument(struct arg_info
*info
,
274 LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
276 add_argument(info
, type
, param_ptr
);
277 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
282 add_user_sgpr_argument(struct arg_info
*info
,
284 LLVMValueRef
*param_ptr
)
286 add_sgpr_argument(info
, type
, param_ptr
);
287 info
->num_user_sgprs_used
+= ac_get_type_size(type
) / 4;
288 info
->user_sgpr_count
++;
292 add_vgpr_argument(struct arg_info
*info
,
294 LLVMValueRef
*param_ptr
)
296 add_argument(info
, type
, param_ptr
);
297 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
301 add_user_sgpr_array_argument(struct arg_info
*info
,
303 LLVMValueRef
*param_ptr
)
305 info
->array_params_mask
|= (1 << info
->count
);
306 add_user_sgpr_argument(info
, type
, param_ptr
);
309 static void assign_arguments(LLVMValueRef main_function
,
310 struct arg_info
*info
)
313 for (i
= 0; i
< info
->count
; i
++) {
315 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
320 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
321 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
322 unsigned num_return_elems
,
323 struct arg_info
*args
,
324 unsigned max_workgroup_size
,
327 LLVMTypeRef main_function_type
, ret_type
;
328 LLVMBasicBlockRef main_function_body
;
330 if (num_return_elems
)
331 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
332 num_return_elems
, true);
334 ret_type
= LLVMVoidTypeInContext(ctx
);
336 /* Setup the function */
338 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
339 LLVMValueRef main_function
=
340 LLVMAddFunction(module
, "main", main_function_type
);
342 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
343 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
345 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
346 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
347 if (args
->array_params_mask
& (1 << i
)) {
348 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
349 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_BYVAL
);
350 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
353 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
357 if (max_workgroup_size
) {
358 ac_llvm_add_target_dep_function_attr(main_function
,
359 "amdgpu-max-work-group-size",
363 /* These were copied from some LLVM test. */
364 LLVMAddTargetDependentFunctionAttr(main_function
,
365 "less-precise-fpmad",
367 LLVMAddTargetDependentFunctionAttr(main_function
,
370 LLVMAddTargetDependentFunctionAttr(main_function
,
373 LLVMAddTargetDependentFunctionAttr(main_function
,
377 return main_function
;
380 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
382 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
386 static int get_elem_bits(struct ac_llvm_context
*ctx
, LLVMTypeRef type
)
388 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
389 type
= LLVMGetElementType(type
);
391 if (LLVMGetTypeKind(type
) == LLVMIntegerTypeKind
)
392 return LLVMGetIntTypeWidth(type
);
394 if (type
== ctx
->f16
)
396 if (type
== ctx
->f32
)
398 if (type
== ctx
->f64
)
401 unreachable("Unhandled type kind in get_elem_bits");
404 static LLVMValueRef
unpack_param(struct ac_llvm_context
*ctx
,
405 LLVMValueRef param
, unsigned rshift
,
408 LLVMValueRef value
= param
;
410 value
= LLVMBuildLShr(ctx
->builder
, value
,
411 LLVMConstInt(ctx
->i32
, rshift
, false), "");
413 if (rshift
+ bitwidth
< 32) {
414 unsigned mask
= (1 << bitwidth
) - 1;
415 value
= LLVMBuildAnd(ctx
->builder
, value
,
416 LLVMConstInt(ctx
->i32
, mask
, false), "");
421 static LLVMValueRef
get_rel_patch_id(struct nir_to_llvm_context
*ctx
)
423 switch (ctx
->stage
) {
424 case MESA_SHADER_TESS_CTRL
:
425 return unpack_param(&ctx
->ac
, ctx
->tcs_rel_ids
, 0, 8);
426 case MESA_SHADER_TESS_EVAL
:
427 return ctx
->tes_rel_patch_id
;
430 unreachable("Illegal stage");
434 /* Tessellation shaders pass outputs to the next shader using LDS.
436 * LS outputs = TCS inputs
437 * TCS outputs = TES inputs
440 * - TCS inputs for patch 0
441 * - TCS inputs for patch 1
442 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
444 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
445 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
446 * - TCS outputs for patch 1
447 * - Per-patch TCS outputs for patch 1
448 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
449 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
452 * All three shaders VS(LS), TCS, TES share the same LDS space.
455 get_tcs_in_patch_stride(struct nir_to_llvm_context
*ctx
)
457 if (ctx
->stage
== MESA_SHADER_VERTEX
)
458 return unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
459 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
460 return unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
468 get_tcs_out_patch_stride(struct nir_to_llvm_context
*ctx
)
470 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
474 get_tcs_out_patch0_offset(struct nir_to_llvm_context
*ctx
)
476 return LLVMBuildMul(ctx
->builder
,
477 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
478 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
482 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context
*ctx
)
484 return LLVMBuildMul(ctx
->builder
,
485 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
486 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
490 get_tcs_in_current_patch_offset(struct nir_to_llvm_context
*ctx
)
492 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
493 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
495 return LLVMBuildMul(ctx
->builder
, patch_stride
, rel_patch_id
, "");
499 get_tcs_out_current_patch_offset(struct nir_to_llvm_context
*ctx
)
501 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
502 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
503 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
505 return LLVMBuildAdd(ctx
->builder
, patch0_offset
,
506 LLVMBuildMul(ctx
->builder
, patch_stride
,
512 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context
*ctx
)
514 LLVMValueRef patch0_patch_data_offset
=
515 get_tcs_out_patch0_patch_data_offset(ctx
);
516 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
517 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
519 return LLVMBuildAdd(ctx
->builder
, patch0_patch_data_offset
,
520 LLVMBuildMul(ctx
->builder
, patch_stride
,
525 static void set_userdata_location(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
)
527 ud_info
->sgpr_idx
= *sgpr_idx
;
528 ud_info
->num_sgprs
= num_sgprs
;
529 ud_info
->indirect
= false;
530 ud_info
->indirect_offset
= 0;
531 *sgpr_idx
+= num_sgprs
;
534 static void set_userdata_location_shader(struct nir_to_llvm_context
*ctx
,
535 int idx
, uint8_t *sgpr_idx
, uint8_t num_sgprs
)
537 set_userdata_location(&ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
], sgpr_idx
, num_sgprs
);
541 static void set_userdata_location_indirect(struct ac_userdata_info
*ud_info
, uint8_t sgpr_idx
, uint8_t num_sgprs
,
542 uint32_t indirect_offset
)
544 ud_info
->sgpr_idx
= sgpr_idx
;
545 ud_info
->num_sgprs
= num_sgprs
;
546 ud_info
->indirect
= true;
547 ud_info
->indirect_offset
= indirect_offset
;
550 struct user_sgpr_info
{
551 bool need_ring_offsets
;
553 bool indirect_all_descriptor_sets
;
556 static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx
,
557 struct user_sgpr_info
*user_sgpr_info
)
559 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
561 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
562 if (ctx
->stage
== MESA_SHADER_GEOMETRY
||
563 ctx
->stage
== MESA_SHADER_VERTEX
||
564 ctx
->stage
== MESA_SHADER_TESS_CTRL
||
565 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
566 ctx
->is_gs_copy_shader
)
567 user_sgpr_info
->need_ring_offsets
= true;
569 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&&
570 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
571 user_sgpr_info
->need_ring_offsets
= true;
573 /* 2 user sgprs will nearly always be allocated for scratch/rings */
574 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
575 user_sgpr_info
->sgpr_count
+= 2;
578 switch (ctx
->stage
) {
579 case MESA_SHADER_COMPUTE
:
580 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
581 user_sgpr_info
->sgpr_count
+= 3;
583 case MESA_SHADER_FRAGMENT
:
584 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
586 case MESA_SHADER_VERTEX
:
587 if (!ctx
->is_gs_copy_shader
) {
588 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
589 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
590 user_sgpr_info
->sgpr_count
+= 3;
592 user_sgpr_info
->sgpr_count
+= 2;
595 if (ctx
->options
->key
.vs
.as_ls
)
596 user_sgpr_info
->sgpr_count
++;
598 case MESA_SHADER_TESS_CTRL
:
599 user_sgpr_info
->sgpr_count
+= 4;
601 case MESA_SHADER_TESS_EVAL
:
602 user_sgpr_info
->sgpr_count
+= 1;
604 case MESA_SHADER_GEOMETRY
:
605 user_sgpr_info
->sgpr_count
+= 2;
611 if (ctx
->shader_info
->info
.needs_push_constants
)
612 user_sgpr_info
->sgpr_count
+= 2;
614 uint32_t remaining_sgprs
= 16 - user_sgpr_info
->sgpr_count
;
615 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
616 user_sgpr_info
->sgpr_count
+= 2;
617 user_sgpr_info
->indirect_all_descriptor_sets
= true;
619 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
624 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context
*ctx
,
625 gl_shader_stage stage
,
626 bool has_previous_stage
,
627 gl_shader_stage previous_stage
,
628 const struct user_sgpr_info
*user_sgpr_info
,
629 struct arg_info
*args
,
630 LLVMValueRef
*desc_sets
)
632 unsigned num_sets
= ctx
->options
->layout
? ctx
->options
->layout
->num_sets
: 0;
633 unsigned stage_mask
= 1 << stage
;
634 if (has_previous_stage
)
635 stage_mask
|= 1 << previous_stage
;
637 /* 1 for each descriptor set */
638 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
639 for (unsigned i
= 0; i
< num_sets
; ++i
) {
640 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
641 add_user_sgpr_array_argument(args
, const_array(ctx
->ac
.i8
, 1024 * 1024), &ctx
->descriptor_sets
[i
]);
645 add_user_sgpr_array_argument(args
, const_array(const_array(ctx
->ac
.i8
, 1024 * 1024), 32), desc_sets
);
647 if (ctx
->shader_info
->info
.needs_push_constants
) {
648 /* 1 for push constants and dynamic descriptors */
649 add_user_sgpr_array_argument(args
, const_array(ctx
->ac
.i8
, 1024 * 1024), &ctx
->push_constants
);
654 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context
*ctx
,
655 gl_shader_stage stage
,
656 bool has_previous_stage
,
657 gl_shader_stage previous_stage
,
658 const struct user_sgpr_info
*user_sgpr_info
,
659 LLVMValueRef desc_sets
,
660 uint8_t *user_sgpr_idx
)
662 unsigned num_sets
= ctx
->options
->layout
? ctx
->options
->layout
->num_sets
: 0;
663 unsigned stage_mask
= 1 << stage
;
664 if (has_previous_stage
)
665 stage_mask
|= 1 << previous_stage
;
667 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
668 for (unsigned i
= 0; i
< num_sets
; ++i
) {
669 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
670 set_userdata_location(&ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[i
], user_sgpr_idx
, 2);
672 ctx
->descriptor_sets
[i
] = NULL
;
675 uint32_t desc_sgpr_idx
= *user_sgpr_idx
;
676 set_userdata_location_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
, user_sgpr_idx
, 2);
678 for (unsigned i
= 0; i
< num_sets
; ++i
) {
679 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
680 set_userdata_location_indirect(&ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[i
], desc_sgpr_idx
, 2, i
* 8);
681 ctx
->descriptor_sets
[i
] = ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
, LLVMConstInt(ctx
->ac
.i32
, i
, false));
684 ctx
->descriptor_sets
[i
] = NULL
;
686 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
689 if (ctx
->shader_info
->info
.needs_push_constants
) {
690 set_userdata_location_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
695 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context
*ctx
,
696 gl_shader_stage stage
,
697 bool has_previous_stage
,
698 gl_shader_stage previous_stage
,
699 struct arg_info
*args
)
701 if (!ctx
->is_gs_copy_shader
&& (stage
== MESA_SHADER_VERTEX
|| (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
702 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
703 add_user_sgpr_argument(args
, const_array(ctx
->ac
.v4i32
, 16), &ctx
->vertex_buffers
); /* vertex buffers */
704 add_user_sgpr_argument(args
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
); // base vertex
705 add_user_sgpr_argument(args
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);// start instance
706 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
707 add_user_sgpr_argument(args
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
); // draw id
712 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context
*ctx
,
713 gl_shader_stage stage
,
714 bool has_previous_stage
,
715 gl_shader_stage previous_stage
,
716 uint8_t *user_sgpr_idx
)
718 if (!ctx
->is_gs_copy_shader
&& (stage
== MESA_SHADER_VERTEX
|| (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
719 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
720 set_userdata_location_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
, user_sgpr_idx
, 2);
723 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
726 set_userdata_location_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
, user_sgpr_idx
, vs_num
);
731 static void create_function(struct nir_to_llvm_context
*ctx
,
732 gl_shader_stage stage
,
733 bool has_previous_stage
,
734 gl_shader_stage previous_stage
)
736 uint8_t user_sgpr_idx
;
737 struct user_sgpr_info user_sgpr_info
;
738 struct arg_info args
= {};
739 LLVMValueRef desc_sets
;
741 allocate_user_sgprs(ctx
, &user_sgpr_info
);
743 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
744 add_user_sgpr_argument(&args
, const_array(ctx
->ac
.v4i32
, 16), &ctx
->ring_offsets
); /* address of rings */
748 case MESA_SHADER_COMPUTE
:
749 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
750 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
751 add_user_sgpr_argument(&args
, ctx
->ac
.v3i32
,
752 &ctx
->num_work_groups
);
754 add_sgpr_argument(&args
, ctx
->ac
.v3i32
, &ctx
->workgroup_ids
);
755 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
756 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tg_size
);
757 add_vgpr_argument(&args
, ctx
->ac
.v3i32
, &ctx
->local_invocation_ids
);
759 case MESA_SHADER_VERTEX
:
760 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
761 radv_define_vs_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &args
);
762 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
763 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->view_index
);
764 if (ctx
->options
->key
.vs
.as_es
)
765 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->es2gs_offset
); // es2gs offset
766 else if (ctx
->options
->key
.vs
.as_ls
)
767 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->ls_out_layout
); // ls out layout
768 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
); // vertex id
769 if (!ctx
->is_gs_copy_shader
) {
770 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->rel_auto_id
); // rel auto id
771 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->vs_prim_id
); // vs prim id
772 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
); // instance id
775 case MESA_SHADER_TESS_CTRL
:
776 if (has_previous_stage
) {
777 // First 6 system regs
778 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->oc_lds
); // param oc lds
779 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->merged_wave_info
); // merged wave info
780 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tess_factor_offset
); // tess factor offset
782 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); // scratch offset
783 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); // unknown
784 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); // unknown
786 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
787 radv_define_vs_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &args
);
788 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->ls_out_layout
); // ls out layout
790 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
791 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_out_offsets
); // tcs out offsets
792 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_out_layout
); // tcs out layout
793 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_in_layout
); // tcs in layout
794 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
795 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->view_index
);
797 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_patch_id
); // patch id
798 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_rel_ids
); // rel ids;
799 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
); // vertex id
800 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->rel_auto_id
); // rel auto id
801 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->vs_prim_id
); // vs prim id
802 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
); // instance id
804 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
805 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
806 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_out_offsets
); // tcs out offsets
807 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_out_layout
); // tcs out layout
808 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_in_layout
); // tcs in layout
809 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
810 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->view_index
);
811 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->oc_lds
); // param oc lds
812 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tess_factor_offset
); // tess factor offset
813 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_patch_id
); // patch id
814 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_rel_ids
); // rel ids;
817 case MESA_SHADER_TESS_EVAL
:
818 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
819 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
820 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
821 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->view_index
);
822 if (ctx
->options
->key
.tes
.as_es
) {
823 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->oc_lds
); // OC LDS
824 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); //
825 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->es2gs_offset
); // es2gs offset
827 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); //
828 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->oc_lds
); // OC LDS
830 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->tes_u
); // tes_u
831 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->tes_v
); // tes_v
832 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
); // tes rel patch id
833 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tes_patch_id
); // tes patch id
835 case MESA_SHADER_GEOMETRY
:
836 if (has_previous_stage
) {
837 // First 6 system regs
838 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
); // tess factor offset
839 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->merged_wave_info
); // merged wave info
840 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->oc_lds
); // param oc lds
842 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); // scratch offset
843 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); // unknown
844 add_sgpr_argument(&args
, ctx
->ac
.i32
, NULL
); // unknown
846 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
847 if (previous_stage
== MESA_SHADER_TESS_EVAL
)
848 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
850 radv_define_vs_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &args
);
851 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gsvs_ring_stride
); // gsvs stride
852 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gsvs_num_entries
); // gsvs num entires
853 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
854 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->view_index
);
856 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[0]); // vtx01
857 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[2]); // vtx23
858 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.gs_prim_id
); // prim id
859 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.gs_invocation_id
);
860 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[4]);
862 if (previous_stage
== MESA_SHADER_VERTEX
) {
863 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
); // vertex id
864 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->rel_auto_id
); // rel auto id
865 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->vs_prim_id
); // vs prim id
866 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
); // instance id
868 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->tes_u
); // tes_u
869 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->tes_v
); // tes_v
870 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
); // tes rel patch id
871 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->tes_patch_id
); // tes patch id
874 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
875 radv_define_vs_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &args
);
876 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gsvs_ring_stride
); // gsvs stride
877 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gsvs_num_entries
); // gsvs num entires
878 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
879 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->view_index
);
880 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
); // gs2vs offset
881 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_wave_id
); // wave id
882 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[0]); // vtx0
883 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[1]); // vtx1
884 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.gs_prim_id
); // prim id
885 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[2]);
886 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[3]);
887 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[4]);
888 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->gs_vtx_offset
[5]);
889 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.gs_invocation_id
);
892 case MESA_SHADER_FRAGMENT
:
893 radv_define_common_user_sgprs_phase1(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, &args
, &desc_sets
);
894 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
895 add_user_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->sample_pos_offset
); /* sample position offset */
896 add_sgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->prim_mask
); /* prim mask */
897 add_vgpr_argument(&args
, ctx
->ac
.v2i32
, &ctx
->persp_sample
); /* persp sample */
898 add_vgpr_argument(&args
, ctx
->ac
.v2i32
, &ctx
->persp_center
); /* persp center */
899 add_vgpr_argument(&args
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
); /* persp centroid */
900 add_vgpr_argument(&args
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
901 add_vgpr_argument(&args
, ctx
->ac
.v2i32
, &ctx
->linear_sample
); /* linear sample */
902 add_vgpr_argument(&args
, ctx
->ac
.v2i32
, &ctx
->linear_center
); /* linear center */
903 add_vgpr_argument(&args
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
); /* linear centroid */
904 add_vgpr_argument(&args
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
905 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]); /* pos x float */
906 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]); /* pos y float */
907 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]); /* pos z float */
908 add_vgpr_argument(&args
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]); /* pos w float */
909 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.front_face
); /* front face */
910 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
); /* ancillary */
911 add_vgpr_argument(&args
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
); /* sample coverage */
912 add_vgpr_argument(&args
, ctx
->ac
.i32
, NULL
); /* fixed pt */
915 unreachable("Shader stage not implemented");
918 ctx
->main_function
= create_llvm_function(
919 ctx
->context
, ctx
->module
, ctx
->builder
, NULL
, 0, &args
,
920 ctx
->max_workgroup_size
,
921 ctx
->options
->unsafe_math
);
922 set_llvm_calling_convention(ctx
->main_function
, stage
);
925 ctx
->shader_info
->num_input_vgprs
= 0;
926 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
928 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
930 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
931 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
933 assign_arguments(ctx
->main_function
, &args
);
937 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
938 set_userdata_location_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
, &user_sgpr_idx
, 2);
939 if (ctx
->options
->supports_spill
) {
940 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
941 LLVMPointerType(ctx
->ac
.i8
, CONST_ADDR_SPACE
),
942 NULL
, 0, AC_FUNC_ATTR_READNONE
);
943 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->builder
, ctx
->ring_offsets
,
944 const_array(ctx
->ac
.v4i32
, 16), "");
948 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
949 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
950 if (has_previous_stage
)
953 radv_define_common_user_sgprs_phase2(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
956 case MESA_SHADER_COMPUTE
:
957 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
958 set_userdata_location_shader(ctx
, AC_UD_CS_GRID_SIZE
,
962 case MESA_SHADER_VERTEX
:
963 radv_define_vs_user_sgprs_phase2(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_idx
);
965 set_userdata_location_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
966 if (ctx
->options
->key
.vs
.as_ls
) {
967 set_userdata_location_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
, &user_sgpr_idx
, 1);
969 if (ctx
->options
->key
.vs
.as_ls
)
970 ac_declare_lds_as_pointer(&ctx
->ac
);
972 case MESA_SHADER_TESS_CTRL
:
973 radv_define_vs_user_sgprs_phase2(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_idx
);
974 if (has_previous_stage
)
975 set_userdata_location_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
, &user_sgpr_idx
, 1);
976 set_userdata_location_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
978 set_userdata_location_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
979 ac_declare_lds_as_pointer(&ctx
->ac
);
981 case MESA_SHADER_TESS_EVAL
:
982 set_userdata_location_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
984 set_userdata_location_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
986 case MESA_SHADER_GEOMETRY
:
987 if (has_previous_stage
) {
988 if (previous_stage
== MESA_SHADER_VERTEX
)
989 radv_define_vs_user_sgprs_phase2(ctx
, stage
, has_previous_stage
, previous_stage
, &user_sgpr_idx
);
991 set_userdata_location_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
993 set_userdata_location_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
, &user_sgpr_idx
, 2);
995 set_userdata_location_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
996 if (has_previous_stage
)
997 ac_declare_lds_as_pointer(&ctx
->ac
);
999 case MESA_SHADER_FRAGMENT
:
1000 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1001 set_userdata_location_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
, &user_sgpr_idx
, 1);
1005 unreachable("Shader stage not implemented");
1008 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1011 static int get_llvm_num_components(LLVMValueRef value
)
1013 LLVMTypeRef type
= LLVMTypeOf(value
);
1014 unsigned num_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1015 ? LLVMGetVectorSize(type
)
1017 return num_components
;
1020 static LLVMValueRef
llvm_extract_elem(struct ac_llvm_context
*ac
,
1024 int count
= get_llvm_num_components(value
);
1029 return LLVMBuildExtractElement(ac
->builder
, value
,
1030 LLVMConstInt(ac
->i32
, index
, false), "");
1033 static LLVMValueRef
trim_vector(struct ac_llvm_context
*ctx
,
1034 LLVMValueRef value
, unsigned count
)
1036 unsigned num_components
= get_llvm_num_components(value
);
1037 if (count
== num_components
)
1040 LLVMValueRef masks
[] = {
1041 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1042 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1045 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1048 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1049 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1053 build_store_values_extended(struct ac_llvm_context
*ac
,
1054 LLVMValueRef
*values
,
1055 unsigned value_count
,
1056 unsigned value_stride
,
1059 LLVMBuilderRef builder
= ac
->builder
;
1062 for (i
= 0; i
< value_count
; i
++) {
1063 LLVMValueRef ptr
= values
[i
* value_stride
];
1064 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1065 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1066 LLVMBuildStore(builder
, value
, ptr
);
1070 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1071 const nir_ssa_def
*def
)
1073 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1074 if (def
->num_components
> 1) {
1075 type
= LLVMVectorType(type
, def
->num_components
);
1080 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1083 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1084 return (LLVMValueRef
)entry
->data
;
1088 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1089 const struct nir_block
*b
)
1091 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1092 return (LLVMBasicBlockRef
)entry
->data
;
1095 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1097 unsigned num_components
)
1099 LLVMValueRef value
= get_src(ctx
, src
.src
);
1100 bool need_swizzle
= false;
1103 LLVMTypeRef type
= LLVMTypeOf(value
);
1104 unsigned src_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1105 ? LLVMGetVectorSize(type
)
1108 for (unsigned i
= 0; i
< num_components
; ++i
) {
1109 assert(src
.swizzle
[i
] < src_components
);
1110 if (src
.swizzle
[i
] != i
)
1111 need_swizzle
= true;
1114 if (need_swizzle
|| num_components
!= src_components
) {
1115 LLVMValueRef masks
[] = {
1116 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1117 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1118 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1119 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1121 if (src_components
> 1 && num_components
== 1) {
1122 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1124 } else if (src_components
== 1 && num_components
> 1) {
1125 LLVMValueRef values
[] = {value
, value
, value
, value
};
1126 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1128 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1129 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1133 assert(!src
.negate
);
1138 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1139 LLVMIntPredicate pred
, LLVMValueRef src0
,
1142 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1143 return LLVMBuildSelect(ctx
->builder
, result
,
1144 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1145 LLVMConstInt(ctx
->i32
, 0, false), "");
1148 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1149 LLVMRealPredicate pred
, LLVMValueRef src0
,
1152 LLVMValueRef result
;
1153 src0
= ac_to_float(ctx
, src0
);
1154 src1
= ac_to_float(ctx
, src1
);
1155 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1156 return LLVMBuildSelect(ctx
->builder
, result
,
1157 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1158 LLVMConstInt(ctx
->i32
, 0, false), "");
1161 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1163 LLVMTypeRef result_type
,
1167 LLVMValueRef params
[] = {
1168 ac_to_float(ctx
, src0
),
1171 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1172 get_elem_bits(ctx
, result_type
));
1173 assert(length
< sizeof(name
));
1174 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1177 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1179 LLVMTypeRef result_type
,
1180 LLVMValueRef src0
, LLVMValueRef src1
)
1183 LLVMValueRef params
[] = {
1184 ac_to_float(ctx
, src0
),
1185 ac_to_float(ctx
, src1
),
1188 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1189 get_elem_bits(ctx
, result_type
));
1190 assert(length
< sizeof(name
));
1191 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1194 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1196 LLVMTypeRef result_type
,
1197 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1200 LLVMValueRef params
[] = {
1201 ac_to_float(ctx
, src0
),
1202 ac_to_float(ctx
, src1
),
1203 ac_to_float(ctx
, src2
),
1206 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1207 get_elem_bits(ctx
, result_type
));
1208 assert(length
< sizeof(name
));
1209 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1212 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1213 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1215 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1217 return LLVMBuildSelect(ctx
->builder
, v
, src1
, src2
, "");
1220 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1221 LLVMIntPredicate pred
,
1222 LLVMValueRef src0
, LLVMValueRef src1
)
1224 return LLVMBuildSelect(ctx
->builder
,
1225 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1230 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1233 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1234 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1237 static LLVMValueRef
emit_fsign(struct ac_llvm_context
*ctx
,
1240 LLVMValueRef cmp
, val
;
1242 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGT
, src0
, ctx
->f32_0
, "");
1243 val
= LLVMBuildSelect(ctx
->builder
, cmp
, ctx
->f32_1
, src0
, "");
1244 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
, val
, ctx
->f32_0
, "");
1245 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstReal(ctx
->f32
, -1.0), "");
1249 static LLVMValueRef
emit_isign(struct ac_llvm_context
*ctx
,
1252 LLVMValueRef cmp
, val
;
1254 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGT
, src0
, ctx
->i32_0
, "");
1255 val
= LLVMBuildSelect(ctx
->builder
, cmp
, ctx
->i32_1
, src0
, "");
1256 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGE
, val
, ctx
->i32_0
, "");
1257 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstInt(ctx
->i32
, -1, true), "");
1261 static LLVMValueRef
emit_ffract(struct ac_llvm_context
*ctx
,
1264 const char *intr
= "llvm.floor.f32";
1265 LLVMValueRef fsrc0
= ac_to_float(ctx
, src0
);
1266 LLVMValueRef params
[] = {
1269 LLVMValueRef floor
= ac_build_intrinsic(ctx
, intr
,
1270 ctx
->f32
, params
, 1,
1271 AC_FUNC_ATTR_READNONE
);
1272 return LLVMBuildFSub(ctx
->builder
, fsrc0
, floor
, "");
1275 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1277 LLVMValueRef src0
, LLVMValueRef src1
)
1279 LLVMTypeRef ret_type
;
1280 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1282 LLVMValueRef params
[] = { src0
, src1
};
1283 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1286 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1287 params
, 2, AC_FUNC_ATTR_READNONE
);
1289 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1290 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1294 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1297 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1300 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1303 src0
= ac_to_float(ctx
, src0
);
1304 return LLVMBuildSExt(ctx
->builder
,
1305 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, ctx
->f32_0
, ""),
1309 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1312 return LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1315 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1318 return LLVMBuildSExt(ctx
->builder
,
1319 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, ctx
->i32_0
, ""),
1323 static LLVMValueRef
emit_f2f16(struct nir_to_llvm_context
*ctx
,
1326 LLVMValueRef result
;
1327 LLVMValueRef cond
= NULL
;
1329 src0
= ac_to_float(&ctx
->ac
, src0
);
1330 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->ac
.f16
, "");
1332 if (ctx
->options
->chip_class
>= VI
) {
1333 LLVMValueRef args
[2];
1334 /* Check if the result is a denormal - and flush to 0 if so. */
1336 args
[1] = LLVMConstInt(ctx
->ac
.i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1337 cond
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.class.f16", ctx
->ac
.i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1340 /* need to convert back up to f32 */
1341 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->ac
.f32
, "");
1343 if (ctx
->options
->chip_class
>= VI
)
1344 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1347 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1348 * so compare the result and flush to 0 if it's smaller.
1350 LLVMValueRef temp
, cond2
;
1351 temp
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1352 ctx
->ac
.f32
, result
);
1353 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1354 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, 0x38800000, false), ctx
->ac
.f32
, ""),
1356 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1357 temp
, ctx
->ac
.f32_0
, "");
1358 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1359 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->ac
.f32_0
, result
, "");
1364 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1365 LLVMValueRef src0
, LLVMValueRef src1
)
1367 LLVMValueRef dst64
, result
;
1368 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1369 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1371 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1372 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1373 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1377 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1378 LLVMValueRef src0
, LLVMValueRef src1
)
1380 LLVMValueRef dst64
, result
;
1381 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1382 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1384 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1385 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1386 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1390 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1392 const LLVMValueRef srcs
[3])
1394 LLVMValueRef result
;
1395 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1397 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1398 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1402 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1403 LLVMValueRef src0
, LLVMValueRef src1
,
1404 LLVMValueRef src2
, LLVMValueRef src3
)
1406 LLVMValueRef bfi_args
[3], result
;
1408 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1409 LLVMBuildSub(ctx
->builder
,
1410 LLVMBuildShl(ctx
->builder
,
1415 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1418 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1421 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1422 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1424 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1425 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1426 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1428 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1432 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1435 LLVMValueRef comp
[2];
1437 src0
= ac_to_float(ctx
, src0
);
1438 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1439 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1441 return ac_build_cvt_pkrtz_f16(ctx
, comp
);
1444 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1447 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1448 LLVMValueRef temps
[2], result
, val
;
1451 for (i
= 0; i
< 2; i
++) {
1452 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1453 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1454 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1455 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1458 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), temps
[0],
1460 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1465 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1471 LLVMValueRef result
;
1473 if (op
== nir_op_fddx_fine
|| op
== nir_op_fddx
)
1474 mask
= AC_TID_MASK_LEFT
;
1475 else if (op
== nir_op_fddy_fine
|| op
== nir_op_fddy
)
1476 mask
= AC_TID_MASK_TOP
;
1478 mask
= AC_TID_MASK_TOP_LEFT
;
1480 /* for DDX we want to next X pixel, DDY next Y pixel. */
1481 if (op
== nir_op_fddx_fine
||
1482 op
== nir_op_fddx_coarse
||
1488 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1493 * this takes an I,J coordinate pair,
1494 * and works out the X and Y derivatives.
1495 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1497 static LLVMValueRef
emit_ddxy_interp(
1498 struct ac_nir_context
*ctx
,
1499 LLVMValueRef interp_ij
)
1501 LLVMValueRef result
[4], a
;
1504 for (i
= 0; i
< 2; i
++) {
1505 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1506 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1507 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1508 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1510 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1513 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1515 LLVMValueRef src
[4], result
= NULL
;
1516 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1517 unsigned src_components
;
1518 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1520 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1521 switch (instr
->op
) {
1527 case nir_op_pack_half_2x16
:
1530 case nir_op_unpack_half_2x16
:
1534 src_components
= num_components
;
1537 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1538 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1540 switch (instr
->op
) {
1546 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1547 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1550 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1553 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1556 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1559 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1560 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1561 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1564 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1565 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1566 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1569 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1572 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1575 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1578 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1581 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1582 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1583 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1584 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1585 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1586 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1587 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1590 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1591 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1592 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1595 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1598 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1601 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1604 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1605 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1606 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1609 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1610 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1611 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1614 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1615 result
= ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, src
[0]);
1618 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1621 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1624 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1627 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1628 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1629 LLVMTypeOf(src
[0]), ""),
1633 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1634 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1635 LLVMTypeOf(src
[0]), ""),
1639 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1640 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1641 LLVMTypeOf(src
[0]), ""),
1645 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1648 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1651 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1654 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1657 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1660 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1663 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUEQ
, src
[0], src
[1]);
1666 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1669 result
= emit_float_cmp(&ctx
->ac
, LLVMRealULT
, src
[0], src
[1]);
1672 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUGE
, src
[0], src
[1]);
1675 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1676 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1679 result
= emit_iabs(&ctx
->ac
, src
[0]);
1682 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1685 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1688 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1691 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1694 result
= emit_isign(&ctx
->ac
, src
[0]);
1697 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1698 result
= emit_fsign(&ctx
->ac
, src
[0]);
1701 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1702 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1705 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1706 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1709 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1710 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1712 case nir_op_fround_even
:
1713 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1714 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1717 result
= emit_ffract(&ctx
->ac
, src
[0]);
1720 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1721 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1724 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1725 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1728 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1729 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1732 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1733 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1736 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1737 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1740 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1741 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1742 result
= ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, result
);
1745 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.pow",
1746 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1749 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1750 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1751 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1752 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1753 ac_to_float_type(&ctx
->ac
, def_type
),
1757 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1758 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1759 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1760 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1761 ac_to_float_type(&ctx
->ac
, def_type
),
1765 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1766 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1768 case nir_op_ibitfield_extract
:
1769 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1771 case nir_op_ubitfield_extract
:
1772 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1774 case nir_op_bitfield_insert
:
1775 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1777 case nir_op_bitfield_reverse
:
1778 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1780 case nir_op_bit_count
:
1781 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1786 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1787 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1788 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1792 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1793 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1797 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1798 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1802 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1803 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1807 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1808 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1811 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1812 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1815 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1819 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1820 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1821 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1823 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1827 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1828 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1829 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1831 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1834 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1836 case nir_op_find_lsb
:
1837 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1838 result
= ac_find_lsb(&ctx
->ac
, ctx
->ac
.i32
, src
[0]);
1840 case nir_op_ufind_msb
:
1841 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1842 result
= ac_build_umsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1844 case nir_op_ifind_msb
:
1845 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1846 result
= ac_build_imsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1848 case nir_op_uadd_carry
:
1849 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1850 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1851 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
1853 case nir_op_usub_borrow
:
1854 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1855 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1856 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
1859 result
= emit_b2f(&ctx
->ac
, src
[0]);
1862 result
= emit_f2b(&ctx
->ac
, src
[0]);
1865 result
= emit_b2i(&ctx
->ac
, src
[0]);
1868 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1869 result
= emit_i2b(&ctx
->ac
, src
[0]);
1871 case nir_op_fquantize2f16
:
1872 result
= emit_f2f16(ctx
->nctx
, src
[0]);
1874 case nir_op_umul_high
:
1875 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1876 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1877 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
1879 case nir_op_imul_high
:
1880 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1881 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1882 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
1884 case nir_op_pack_half_2x16
:
1885 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
1887 case nir_op_unpack_half_2x16
:
1888 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
1892 case nir_op_fddx_fine
:
1893 case nir_op_fddy_fine
:
1894 case nir_op_fddx_coarse
:
1895 case nir_op_fddy_coarse
:
1896 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
1899 case nir_op_unpack_64_2x32_split_x
: {
1900 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
1901 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
1904 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
1909 case nir_op_unpack_64_2x32_split_y
: {
1910 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
1911 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
1914 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
1919 case nir_op_pack_64_2x32_split
: {
1920 LLVMValueRef tmp
= LLVMGetUndef(ctx
->ac
.v2i32
);
1921 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
1922 src
[0], ctx
->ac
.i32_0
, "");
1923 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
1924 src
[1], ctx
->ac
.i32_1
, "");
1925 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
1930 fprintf(stderr
, "Unknown NIR alu instr: ");
1931 nir_print_instr(&instr
->instr
, stderr
);
1932 fprintf(stderr
, "\n");
1937 assert(instr
->dest
.dest
.is_ssa
);
1938 result
= ac_to_integer(&ctx
->ac
, result
);
1939 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
1944 static void visit_load_const(struct ac_nir_context
*ctx
,
1945 const nir_load_const_instr
*instr
)
1947 LLVMValueRef values
[4], value
= NULL
;
1948 LLVMTypeRef element_type
=
1949 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
1951 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
1952 switch (instr
->def
.bit_size
) {
1954 values
[i
] = LLVMConstInt(element_type
,
1955 instr
->value
.u32
[i
], false);
1958 values
[i
] = LLVMConstInt(element_type
,
1959 instr
->value
.u64
[i
], false);
1963 "unsupported nir load_const bit_size: %d\n",
1964 instr
->def
.bit_size
);
1968 if (instr
->def
.num_components
> 1) {
1969 value
= LLVMConstVector(values
, instr
->def
.num_components
);
1973 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
1976 static LLVMValueRef
cast_ptr(struct nir_to_llvm_context
*ctx
, LLVMValueRef ptr
,
1979 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
1980 return LLVMBuildBitCast(ctx
->builder
, ptr
,
1981 LLVMPointerType(type
, addr_space
), "");
1985 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
1988 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
1989 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
1992 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
1993 /* On VI, the descriptor contains the size in bytes,
1994 * but TXQ must return the size in elements.
1995 * The stride is always non-zero for resources using TXQ.
1997 LLVMValueRef stride
=
1998 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
1999 LLVMConstInt(ctx
->ac
.i32
, 1, false), "");
2000 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2001 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2002 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2003 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2005 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2011 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2014 static void build_int_type_name(
2016 char *buf
, unsigned bufsize
)
2018 assert(bufsize
>= 6);
2020 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2021 snprintf(buf
, bufsize
, "v%ui32",
2022 LLVMGetVectorSize(type
));
2027 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2028 struct ac_image_args
*args
,
2029 const nir_tex_instr
*instr
)
2031 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2032 LLVMValueRef coord
= args
->addr
;
2033 LLVMValueRef half_texel
[2];
2034 LLVMValueRef compare_cube_wa
= NULL
;
2035 LLVMValueRef result
;
2037 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2041 struct ac_image_args txq_args
= { 0 };
2043 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2044 txq_args
.opcode
= ac_image_get_resinfo
;
2045 txq_args
.dmask
= 0xf;
2046 txq_args
.addr
= ctx
->i32_0
;
2047 txq_args
.resource
= args
->resource
;
2048 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2050 for (c
= 0; c
< 2; c
++) {
2051 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2052 LLVMConstInt(ctx
->i32
, c
, false), "");
2053 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2054 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2055 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2056 LLVMConstReal(ctx
->f32
, -0.5), "");
2060 LLVMValueRef orig_coords
= args
->addr
;
2062 for (c
= 0; c
< 2; c
++) {
2064 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2065 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2066 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2067 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2068 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2069 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2074 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2075 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2076 * workaround by sampling using a scaled type and converting.
2077 * This is taken from amdgpu-pro shaders.
2079 /* NOTE this produces some ugly code compared to amdgpu-pro,
2080 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2081 * and then reads them back. -pro generates two selects,
2082 * one s_cmp for the descriptor rewriting
2083 * one v_cmp for the coordinate and result changes.
2085 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2086 LLVMValueRef tmp
, tmp2
;
2088 /* workaround 8/8/8/8 uint/sint cube gather bug */
2089 /* first detect it then change to a scaled read and f2i */
2090 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2093 /* extract the DATA_FORMAT */
2094 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2095 LLVMConstInt(ctx
->i32
, 6, false), false);
2097 /* is the DATA_FORMAT == 8_8_8_8 */
2098 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2100 if (stype
== GLSL_TYPE_UINT
)
2101 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2102 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2103 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2105 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2106 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2107 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2109 /* replace the NUM FORMAT in the descriptor */
2110 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2111 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2113 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2115 /* don't modify the coordinates for this case */
2116 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2119 result
= ac_build_image_opcode(ctx
, args
);
2121 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2122 LLVMValueRef tmp
, tmp2
;
2124 /* if the cube workaround is in place, f2i the result. */
2125 for (c
= 0; c
< 4; c
++) {
2126 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2127 if (stype
== GLSL_TYPE_UINT
)
2128 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2130 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2131 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2132 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2133 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2134 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2135 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2141 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2142 const nir_tex_instr
*instr
,
2144 struct ac_image_args
*args
)
2146 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2147 return ac_build_buffer_load_format(&ctx
->ac
,
2150 LLVMConstInt(ctx
->ac
.i32
, 0, false),
2154 args
->opcode
= ac_image_sample
;
2155 args
->compare
= instr
->is_shadow
;
2157 switch (instr
->op
) {
2159 case nir_texop_txf_ms
:
2160 case nir_texop_samples_identical
:
2161 args
->opcode
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
? ac_image_load
: ac_image_load_mip
;
2162 args
->compare
= false;
2163 args
->offset
= false;
2170 args
->level_zero
= true;
2175 case nir_texop_query_levels
:
2176 args
->opcode
= ac_image_get_resinfo
;
2179 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2180 args
->level_zero
= true;
2186 args
->opcode
= ac_image_gather4
;
2187 args
->level_zero
= true;
2190 args
->opcode
= ac_image_get_lod
;
2191 args
->compare
= false;
2192 args
->offset
= false;
2198 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2199 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2200 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2201 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2204 return ac_build_image_opcode(&ctx
->ac
, args
);
2207 static LLVMValueRef
visit_vulkan_resource_index(struct nir_to_llvm_context
*ctx
,
2208 nir_intrinsic_instr
*instr
)
2210 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[0]);
2211 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
2212 unsigned binding
= nir_intrinsic_binding(instr
);
2213 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2214 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2215 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2216 unsigned base_offset
= layout
->binding
[binding
].offset
;
2217 LLVMValueRef offset
, stride
;
2219 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2220 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2221 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2222 layout
->binding
[binding
].dynamic_offset_offset
;
2223 desc_ptr
= ctx
->push_constants
;
2224 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2225 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2227 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
2229 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
2230 index
= LLVMBuildMul(ctx
->builder
, index
, stride
, "");
2231 offset
= LLVMBuildAdd(ctx
->builder
, offset
, index
, "");
2233 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2234 desc_ptr
= cast_ptr(ctx
, desc_ptr
, ctx
->ac
.v4i32
);
2235 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2240 static LLVMValueRef
visit_vulkan_resource_reindex(struct nir_to_llvm_context
*ctx
,
2241 nir_intrinsic_instr
*instr
)
2243 LLVMValueRef ptr
= get_src(ctx
->nir
, instr
->src
[0]);
2244 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[1]);
2246 LLVMValueRef result
= LLVMBuildGEP(ctx
->builder
, ptr
, &index
, 1, "");
2247 LLVMSetMetadata(result
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2251 static LLVMValueRef
visit_load_push_constant(struct nir_to_llvm_context
*ctx
,
2252 nir_intrinsic_instr
*instr
)
2254 LLVMValueRef ptr
, addr
;
2256 addr
= LLVMConstInt(ctx
->ac
.i32
, nir_intrinsic_base(instr
), 0);
2257 addr
= LLVMBuildAdd(ctx
->builder
, addr
, get_src(ctx
->nir
, instr
->src
[0]), "");
2259 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->push_constants
, addr
);
2260 ptr
= cast_ptr(ctx
, ptr
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
));
2262 return LLVMBuildLoad(ctx
->builder
, ptr
, "");
2265 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2266 const nir_intrinsic_instr
*instr
)
2268 LLVMValueRef ptr
= get_src(ctx
, instr
->src
[0]);
2270 return get_buffer_size(ctx
, LLVMBuildLoad(ctx
->ac
.builder
, ptr
, ""), false);
2272 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2273 nir_intrinsic_instr
*instr
)
2275 const char *store_name
;
2276 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2277 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2278 int elem_size_mult
= get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2279 int components_32bit
= elem_size_mult
* instr
->num_components
;
2280 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2281 LLVMValueRef base_data
, base_offset
;
2282 LLVMValueRef params
[6];
2284 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2285 get_src(ctx
, instr
->src
[1]), true);
2286 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 0, false); /* vindex */
2287 params
[4] = ctx
->ac
.i1false
; /* glc */
2288 params
[5] = ctx
->ac
.i1false
; /* slc */
2290 if (components_32bit
> 1)
2291 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2293 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2294 base_data
= trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2295 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2297 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2301 LLVMValueRef offset
;
2303 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2305 /* Due to an LLVM limitation, split 3-element writes
2306 * into a 2-element and a 1-element write. */
2308 writemask
|= 1 << (start
+ 2);
2312 start
*= elem_size_mult
;
2313 count
*= elem_size_mult
;
2316 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2321 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2323 } else if (count
== 2) {
2324 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
2325 base_data
, LLVMConstInt(ctx
->ac
.i32
, start
, false), "");
2326 data
= LLVMBuildInsertElement(ctx
->ac
.builder
, LLVMGetUndef(ctx
->ac
.v2f32
), tmp
,
2329 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
2330 base_data
, LLVMConstInt(ctx
->ac
.i32
, start
+ 1, false), "");
2331 data
= LLVMBuildInsertElement(ctx
->ac
.builder
, data
, tmp
,
2333 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2337 if (get_llvm_num_components(base_data
) > 1)
2338 data
= LLVMBuildExtractElement(ctx
->ac
.builder
, base_data
,
2339 LLVMConstInt(ctx
->ac
.i32
, start
, false), "");
2342 store_name
= "llvm.amdgcn.buffer.store.f32";
2345 offset
= base_offset
;
2347 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2351 ac_build_intrinsic(&ctx
->ac
, store_name
,
2352 ctx
->ac
.voidt
, params
, 6, 0);
2356 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2357 const nir_intrinsic_instr
*instr
)
2360 LLVMValueRef params
[6];
2363 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2364 params
[arg_count
++] = llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2366 params
[arg_count
++] = llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2367 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2368 get_src(ctx
, instr
->src
[0]),
2370 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i32
, 0, false); /* vindex */
2371 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2372 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2374 switch (instr
->intrinsic
) {
2375 case nir_intrinsic_ssbo_atomic_add
:
2376 name
= "llvm.amdgcn.buffer.atomic.add";
2378 case nir_intrinsic_ssbo_atomic_imin
:
2379 name
= "llvm.amdgcn.buffer.atomic.smin";
2381 case nir_intrinsic_ssbo_atomic_umin
:
2382 name
= "llvm.amdgcn.buffer.atomic.umin";
2384 case nir_intrinsic_ssbo_atomic_imax
:
2385 name
= "llvm.amdgcn.buffer.atomic.smax";
2387 case nir_intrinsic_ssbo_atomic_umax
:
2388 name
= "llvm.amdgcn.buffer.atomic.umax";
2390 case nir_intrinsic_ssbo_atomic_and
:
2391 name
= "llvm.amdgcn.buffer.atomic.and";
2393 case nir_intrinsic_ssbo_atomic_or
:
2394 name
= "llvm.amdgcn.buffer.atomic.or";
2396 case nir_intrinsic_ssbo_atomic_xor
:
2397 name
= "llvm.amdgcn.buffer.atomic.xor";
2399 case nir_intrinsic_ssbo_atomic_exchange
:
2400 name
= "llvm.amdgcn.buffer.atomic.swap";
2402 case nir_intrinsic_ssbo_atomic_comp_swap
:
2403 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2409 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2412 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2413 const nir_intrinsic_instr
*instr
)
2415 LLVMValueRef results
[2];
2416 int load_components
;
2417 int num_components
= instr
->num_components
;
2418 if (instr
->dest
.ssa
.bit_size
== 64)
2419 num_components
*= 2;
2421 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2422 load_components
= MIN2(num_components
- i
, 4);
2423 const char *load_name
;
2424 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2425 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2426 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2428 if (load_components
== 3)
2429 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2430 else if (load_components
> 1)
2431 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2433 if (load_components
>= 3)
2434 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2435 else if (load_components
== 2)
2436 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2437 else if (load_components
== 1)
2438 load_name
= "llvm.amdgcn.buffer.load.f32";
2440 unreachable("unhandled number of components");
2442 LLVMValueRef params
[] = {
2443 ctx
->abi
->load_ssbo(ctx
->abi
,
2444 get_src(ctx
, instr
->src
[0]),
2446 LLVMConstInt(ctx
->ac
.i32
, 0, false),
2452 results
[i
] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2457 LLVMValueRef ret
= results
[0];
2458 if (num_components
> 4 || num_components
== 3) {
2459 LLVMValueRef masks
[] = {
2460 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2461 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2462 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2463 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2466 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2467 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2468 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2471 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2472 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2475 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2476 const nir_intrinsic_instr
*instr
)
2478 LLVMValueRef results
[8], ret
;
2479 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2480 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2481 int num_components
= instr
->num_components
;
2483 if (ctx
->abi
->load_ubo
)
2484 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2486 if (instr
->dest
.ssa
.bit_size
== 64)
2487 num_components
*= 2;
2489 for (unsigned i
= 0; i
< num_components
; ++i
) {
2490 LLVMValueRef params
[] = {
2492 LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, 4 * i
, 0),
2495 results
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.load.const.v4i32", ctx
->ac
.f32
,
2497 AC_FUNC_ATTR_READNONE
|
2498 AC_FUNC_ATTR_LEGACY
);
2502 ret
= ac_build_gather_values(&ctx
->ac
, results
, num_components
);
2503 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2504 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2508 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2509 bool vs_in
, unsigned *vertex_index_out
,
2510 LLVMValueRef
*vertex_index_ref
,
2511 unsigned *const_out
, LLVMValueRef
*indir_out
)
2513 unsigned const_offset
= 0;
2514 nir_deref
*tail
= &deref
->deref
;
2515 LLVMValueRef offset
= NULL
;
2517 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2519 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2520 if (vertex_index_out
)
2521 *vertex_index_out
= deref_array
->base_offset
;
2523 if (vertex_index_ref
) {
2524 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2525 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2526 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2528 *vertex_index_ref
= vtx
;
2532 if (deref
->var
->data
.compact
) {
2533 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2534 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2535 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2536 /* We always lower indirect dereferences for "compact" array vars. */
2537 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2539 const_offset
= deref_array
->base_offset
;
2543 while (tail
->child
!= NULL
) {
2544 const struct glsl_type
*parent_type
= tail
->type
;
2547 if (tail
->deref_type
== nir_deref_type_array
) {
2548 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2549 LLVMValueRef index
, stride
, local_offset
;
2550 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2552 const_offset
+= size
* deref_array
->base_offset
;
2553 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2556 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2557 index
= get_src(ctx
, deref_array
->indirect
);
2558 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2559 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2562 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2564 offset
= local_offset
;
2565 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2566 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2568 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2569 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2570 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2573 unreachable("unsupported deref type");
2577 if (const_offset
&& offset
)
2578 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2579 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2582 *const_out
= const_offset
;
2583 *indir_out
= offset
;
2587 /* The offchip buffer layout for TCS->TES is
2589 * - attribute 0 of patch 0 vertex 0
2590 * - attribute 0 of patch 0 vertex 1
2591 * - attribute 0 of patch 0 vertex 2
2593 * - attribute 0 of patch 1 vertex 0
2594 * - attribute 0 of patch 1 vertex 1
2596 * - attribute 1 of patch 0 vertex 0
2597 * - attribute 1 of patch 0 vertex 1
2599 * - per patch attribute 0 of patch 0
2600 * - per patch attribute 0 of patch 1
2603 * Note that every attribute has 4 components.
2605 static LLVMValueRef
get_tcs_tes_buffer_address(struct nir_to_llvm_context
*ctx
,
2606 LLVMValueRef vertex_index
,
2607 LLVMValueRef param_index
)
2609 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
2610 LLVMValueRef param_stride
, constant16
;
2611 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2613 vertices_per_patch
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 9, 6);
2614 num_patches
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2615 total_vertices
= LLVMBuildMul(ctx
->builder
, vertices_per_patch
,
2618 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2620 base_addr
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
2621 vertices_per_patch
, "");
2623 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2626 param_stride
= total_vertices
;
2628 base_addr
= rel_patch_id
;
2629 param_stride
= num_patches
;
2632 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2633 LLVMBuildMul(ctx
->builder
, param_index
,
2634 param_stride
, ""), "");
2636 base_addr
= LLVMBuildMul(ctx
->builder
, base_addr
, constant16
, "");
2638 if (!vertex_index
) {
2639 LLVMValueRef patch_data_offset
=
2640 unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2642 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2643 patch_data_offset
, "");
2648 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct nir_to_llvm_context
*ctx
,
2650 unsigned const_index
,
2652 LLVMValueRef vertex_index
,
2653 LLVMValueRef indir_index
)
2655 LLVMValueRef param_index
;
2658 param_index
= LLVMBuildAdd(ctx
->builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
2661 if (const_index
&& !is_compact
)
2662 param
+= const_index
;
2663 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
2665 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2669 mark_tess_output(struct nir_to_llvm_context
*ctx
,
2670 bool is_patch
, uint32_t param
)
2674 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2676 ctx
->tess_outputs_written
|= (1ull << param
);
2680 get_dw_address(struct nir_to_llvm_context
*ctx
,
2681 LLVMValueRef dw_addr
,
2683 unsigned const_index
,
2684 bool compact_const_index
,
2685 LLVMValueRef vertex_index
,
2686 LLVMValueRef stride
,
2687 LLVMValueRef indir_index
)
2692 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2693 LLVMBuildMul(ctx
->builder
,
2699 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2700 LLVMBuildMul(ctx
->builder
, indir_index
,
2701 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
2702 else if (const_index
&& !compact_const_index
)
2703 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2704 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2706 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2707 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
2709 if (const_index
&& compact_const_index
)
2710 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2711 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2716 load_tcs_input(struct nir_to_llvm_context
*ctx
,
2717 nir_intrinsic_instr
*instr
)
2719 LLVMValueRef dw_addr
, stride
;
2720 unsigned const_index
;
2721 LLVMValueRef vertex_index
;
2722 LLVMValueRef indir_index
;
2724 LLVMValueRef value
[4], result
;
2725 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2726 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2727 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2728 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2729 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2730 &const_index
, &indir_index
);
2732 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2733 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2734 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2737 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
2738 for (unsigned i
= 0; i
< instr
->num_components
+ comp
; i
++) {
2739 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2740 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2743 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, instr
->num_components
, comp
);
2744 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2749 load_tcs_output(struct nir_to_llvm_context
*ctx
,
2750 nir_intrinsic_instr
*instr
)
2752 LLVMValueRef dw_addr
;
2753 LLVMValueRef stride
= NULL
;
2754 LLVMValueRef value
[4], result
;
2755 LLVMValueRef vertex_index
= NULL
;
2756 LLVMValueRef indir_index
= NULL
;
2757 unsigned const_index
= 0;
2759 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2760 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2761 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2762 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2763 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2764 &const_index
, &indir_index
);
2766 if (!instr
->variables
[0]->var
->data
.patch
) {
2767 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2768 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2770 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2773 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2776 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
2777 for (unsigned i
= comp
; i
< instr
->num_components
+ comp
; i
++) {
2778 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2779 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2782 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, instr
->num_components
, comp
);
2783 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2788 store_tcs_output(struct nir_to_llvm_context
*ctx
,
2789 nir_intrinsic_instr
*instr
,
2793 LLVMValueRef dw_addr
;
2794 LLVMValueRef stride
= NULL
;
2795 LLVMValueRef buf_addr
= NULL
;
2796 LLVMValueRef vertex_index
= NULL
;
2797 LLVMValueRef indir_index
= NULL
;
2798 unsigned const_index
= 0;
2800 const unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
2801 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2802 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2803 bool store_lds
= true;
2805 if (instr
->variables
[0]->var
->data
.patch
) {
2806 if (!(ctx
->tcs_patch_outputs_read
& (1U << instr
->variables
[0]->var
->data
.location
)))
2809 if (!(ctx
->tcs_outputs_read
& (1ULL << instr
->variables
[0]->var
->data
.location
)))
2812 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2813 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2814 &const_index
, &indir_index
);
2816 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2817 if (instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_CLIP_DIST0
&&
2818 is_compact
&& const_index
> 3) {
2823 if (!instr
->variables
[0]->var
->data
.patch
) {
2824 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
2825 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2827 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2830 mark_tess_output(ctx
, instr
->variables
[0]->var
->data
.patch
, param
);
2832 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2834 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2835 vertex_index
, indir_index
);
2837 bool is_tess_factor
= false;
2838 if (instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2839 instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2840 is_tess_factor
= true;
2842 unsigned base
= is_compact
? const_index
: 0;
2843 for (unsigned chan
= 0; chan
< 8; chan
++) {
2844 if (!(writemask
& (1 << chan
)))
2846 LLVMValueRef value
= llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
2848 if (store_lds
|| is_tess_factor
)
2849 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2851 if (!is_tess_factor
&& writemask
!= 0xF)
2852 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
2853 buf_addr
, ctx
->oc_lds
,
2854 4 * (base
+ chan
), 1, 0, true, false);
2856 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2860 if (writemask
== 0xF) {
2861 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
2862 buf_addr
, ctx
->oc_lds
,
2863 (base
* 4), 1, 0, true, false);
2868 load_tes_input(struct nir_to_llvm_context
*ctx
,
2869 const nir_intrinsic_instr
*instr
)
2871 LLVMValueRef buf_addr
;
2872 LLVMValueRef result
;
2873 LLVMValueRef vertex_index
= NULL
;
2874 LLVMValueRef indir_index
= NULL
;
2875 unsigned const_index
= 0;
2877 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2878 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2880 get_deref_offset(ctx
->nir
, instr
->variables
[0],
2881 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2882 &const_index
, &indir_index
);
2883 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2884 if (instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_CLIP_DIST0
&&
2885 is_compact
&& const_index
> 3) {
2890 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
2891 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
2892 is_compact
, vertex_index
, indir_index
);
2894 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, comp
* 4, false);
2895 buf_addr
= LLVMBuildAdd(ctx
->builder
, buf_addr
, comp_offset
, "");
2897 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, instr
->num_components
, NULL
,
2898 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
2899 result
= trim_vector(&ctx
->ac
, result
, instr
->num_components
);
2900 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2905 load_gs_input(struct ac_shader_abi
*abi
,
2907 unsigned driver_location
,
2909 unsigned num_components
,
2910 unsigned vertex_index
,
2911 unsigned const_index
,
2914 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
2915 LLVMValueRef vtx_offset
;
2916 LLVMValueRef args
[9];
2917 unsigned param
, vtx_offset_param
;
2918 LLVMValueRef value
[4], result
;
2920 vtx_offset_param
= vertex_index
;
2921 assert(vtx_offset_param
< 6);
2922 vtx_offset
= LLVMBuildMul(ctx
->builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
2923 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2925 param
= shader_io_get_unique_index(location
);
2927 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
2928 if (ctx
->ac
.chip_class
>= GFX9
) {
2929 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
2930 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2931 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
2932 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2934 args
[0] = ctx
->esgs_ring
;
2935 args
[1] = vtx_offset
;
2936 args
[2] = LLVMConstInt(ctx
->ac
.i32
, (param
* 4 + i
+ const_index
) * 256, false);
2937 args
[3] = ctx
->ac
.i32_0
;
2938 args
[4] = ctx
->ac
.i32_1
; /* OFFEN */
2939 args
[5] = ctx
->ac
.i32_0
; /* IDXEN */
2940 args
[6] = ctx
->ac
.i32_1
; /* GLC */
2941 args
[7] = ctx
->ac
.i32_0
; /* SLC */
2942 args
[8] = ctx
->ac
.i32_0
; /* TFE */
2944 value
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.buffer.load.dword.i32.i32",
2945 ctx
->ac
.i32
, args
, 9,
2946 AC_FUNC_ATTR_READONLY
|
2947 AC_FUNC_ATTR_LEGACY
);
2950 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
2956 build_gep_for_deref(struct ac_nir_context
*ctx
,
2957 nir_deref_var
*deref
)
2959 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
2960 assert(entry
->data
);
2961 LLVMValueRef val
= entry
->data
;
2962 nir_deref
*tail
= deref
->deref
.child
;
2963 while (tail
!= NULL
) {
2964 LLVMValueRef offset
;
2965 switch (tail
->deref_type
) {
2966 case nir_deref_type_array
: {
2967 nir_deref_array
*array
= nir_deref_as_array(tail
);
2968 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
2969 if (array
->deref_array_type
==
2970 nir_deref_array_type_indirect
) {
2971 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2978 case nir_deref_type_struct
: {
2979 nir_deref_struct
*deref_struct
=
2980 nir_deref_as_struct(tail
);
2981 offset
= LLVMConstInt(ctx
->ac
.i32
,
2982 deref_struct
->index
, 0);
2986 unreachable("bad deref type");
2988 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
2994 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
2995 nir_intrinsic_instr
*instr
)
2997 LLVMValueRef values
[8];
2998 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
2999 int ve
= instr
->dest
.ssa
.num_components
;
3000 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3001 LLVMValueRef indir_index
;
3003 unsigned const_index
;
3004 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3005 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3006 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3007 &const_index
, &indir_index
);
3009 if (instr
->dest
.ssa
.bit_size
== 64)
3012 switch (instr
->variables
[0]->var
->data
.mode
) {
3013 case nir_var_shader_in
:
3014 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
3015 return load_tcs_input(ctx
->nctx
, instr
);
3016 if (ctx
->stage
== MESA_SHADER_TESS_EVAL
)
3017 return load_tes_input(ctx
->nctx
, instr
);
3018 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3019 LLVMValueRef indir_index
;
3020 unsigned const_index
, vertex_index
;
3021 get_deref_offset(ctx
, instr
->variables
[0],
3022 false, &vertex_index
, NULL
,
3023 &const_index
, &indir_index
);
3024 return ctx
->abi
->load_inputs(ctx
->abi
, instr
->variables
[0]->var
->data
.location
,
3025 instr
->variables
[0]->var
->data
.driver_location
,
3026 instr
->variables
[0]->var
->data
.location_frac
, ve
,
3027 vertex_index
, const_index
,
3028 nir2llvmtype(ctx
, instr
->variables
[0]->var
->type
));
3031 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3033 unsigned count
= glsl_count_attribute_slots(
3034 instr
->variables
[0]->var
->type
,
3035 ctx
->stage
== MESA_SHADER_VERTEX
);
3037 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3038 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3041 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3045 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* 4];
3049 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3051 unsigned count
= glsl_count_attribute_slots(
3052 instr
->variables
[0]->var
->type
, false);
3054 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3055 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3058 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3062 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* 4], "");
3066 case nir_var_shared
: {
3067 LLVMValueRef address
= build_gep_for_deref(ctx
,
3068 instr
->variables
[0]);
3069 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3070 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3071 get_def_type(ctx
, &instr
->dest
.ssa
),
3074 case nir_var_shader_out
:
3075 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
3076 return load_tcs_output(ctx
->nctx
, instr
);
3078 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3080 unsigned count
= glsl_count_attribute_slots(
3081 instr
->variables
[0]->var
->type
, false);
3083 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3084 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3087 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3091 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3092 ctx
->outputs
[idx
+ chan
+ const_index
* 4],
3098 unreachable("unhandle variable mode");
3100 ret
= ac_build_varying_gather_values(&ctx
->ac
, values
, ve
, comp
);
3101 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3105 visit_store_var(struct ac_nir_context
*ctx
,
3106 nir_intrinsic_instr
*instr
)
3108 LLVMValueRef temp_ptr
, value
;
3109 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3110 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3111 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3112 int writemask
= instr
->const_index
[0] << comp
;
3113 LLVMValueRef indir_index
;
3114 unsigned const_index
;
3115 get_deref_offset(ctx
, instr
->variables
[0], false,
3116 NULL
, NULL
, &const_index
, &indir_index
);
3118 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3119 int old_writemask
= writemask
;
3121 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3122 LLVMVectorType(ctx
->ac
.f32
, get_llvm_num_components(src
) * 2),
3126 for (unsigned chan
= 0; chan
< 4; chan
++) {
3127 if (old_writemask
& (1 << chan
))
3128 writemask
|= 3u << (2 * chan
);
3132 switch (instr
->variables
[0]->var
->data
.mode
) {
3133 case nir_var_shader_out
:
3135 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3136 store_tcs_output(ctx
->nctx
, instr
, src
, writemask
);
3140 for (unsigned chan
= 0; chan
< 8; chan
++) {
3142 if (!(writemask
& (1 << chan
)))
3145 value
= llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
3147 if (instr
->variables
[0]->var
->data
.compact
)
3150 unsigned count
= glsl_count_attribute_slots(
3151 instr
->variables
[0]->var
->type
, false);
3153 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3154 &ctx
->ac
, ctx
->outputs
+ idx
+ chan
, count
,
3155 stride
, true, true);
3157 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3158 value
, indir_index
, "");
3159 build_store_values_extended(&ctx
->ac
, ctx
->outputs
+ idx
+ chan
,
3160 count
, stride
, tmp_vec
);
3163 temp_ptr
= ctx
->outputs
[idx
+ chan
+ const_index
* stride
];
3165 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3170 for (unsigned chan
= 0; chan
< 8; chan
++) {
3171 if (!(writemask
& (1 << chan
)))
3174 value
= llvm_extract_elem(&ctx
->ac
, src
, chan
);
3176 unsigned count
= glsl_count_attribute_slots(
3177 instr
->variables
[0]->var
->type
, false);
3179 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3180 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3183 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3184 value
, indir_index
, "");
3185 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3188 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3190 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3194 case nir_var_shared
: {
3195 int writemask
= instr
->const_index
[0];
3196 LLVMValueRef address
= build_gep_for_deref(ctx
,
3197 instr
->variables
[0]);
3198 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3199 unsigned components
=
3200 glsl_get_vector_elements(
3201 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3202 if (writemask
== (1 << components
) - 1) {
3203 val
= LLVMBuildBitCast(
3204 ctx
->ac
.builder
, val
,
3205 LLVMGetElementType(LLVMTypeOf(address
)), "");
3206 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3208 for (unsigned chan
= 0; chan
< 4; chan
++) {
3209 if (!(writemask
& (1 << chan
)))
3212 LLVMBuildStructGEP(ctx
->ac
.builder
,
3214 LLVMValueRef src
= llvm_extract_elem(&ctx
->ac
, val
,
3216 src
= LLVMBuildBitCast(
3217 ctx
->ac
.builder
, src
,
3218 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3219 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3229 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3232 case GLSL_SAMPLER_DIM_BUF
:
3234 case GLSL_SAMPLER_DIM_1D
:
3235 return array
? 2 : 1;
3236 case GLSL_SAMPLER_DIM_2D
:
3237 return array
? 3 : 2;
3238 case GLSL_SAMPLER_DIM_MS
:
3239 return array
? 4 : 3;
3240 case GLSL_SAMPLER_DIM_3D
:
3241 case GLSL_SAMPLER_DIM_CUBE
:
3243 case GLSL_SAMPLER_DIM_RECT
:
3244 case GLSL_SAMPLER_DIM_SUBPASS
:
3246 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3256 /* Adjust the sample index according to FMASK.
3258 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3259 * which is the identity mapping. Each nibble says which physical sample
3260 * should be fetched to get that sample.
3262 * For example, 0x11111100 means there are only 2 samples stored and
3263 * the second sample covers 3/4 of the pixel. When reading samples 0
3264 * and 1, return physical sample 0 (determined by the first two 0s
3265 * in FMASK), otherwise return physical sample 1.
3267 * The sample index should be adjusted as follows:
3268 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3270 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3271 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3272 LLVMValueRef coord_z
,
3273 LLVMValueRef sample_index
,
3274 LLVMValueRef fmask_desc_ptr
)
3276 LLVMValueRef fmask_load_address
[4];
3279 fmask_load_address
[0] = coord_x
;
3280 fmask_load_address
[1] = coord_y
;
3282 fmask_load_address
[2] = coord_z
;
3283 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3286 struct ac_image_args args
= {0};
3288 args
.opcode
= ac_image_load
;
3289 args
.da
= coord_z
? true : false;
3290 args
.resource
= fmask_desc_ptr
;
3292 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3294 res
= ac_build_image_opcode(ctx
, &args
);
3296 res
= ac_to_integer(ctx
, res
);
3297 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3298 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3300 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3304 LLVMValueRef sample_index4
=
3305 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3306 LLVMValueRef shifted_fmask
=
3307 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3308 LLVMValueRef final_sample
=
3309 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3311 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3312 * resource descriptor is 0 (invalid),
3314 LLVMValueRef fmask_desc
=
3315 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3318 LLVMValueRef fmask_word1
=
3319 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3322 LLVMValueRef word1_is_nonzero
=
3323 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3324 fmask_word1
, ctx
->i32_0
, "");
3326 /* Replace the MSAA sample index. */
3328 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3329 final_sample
, sample_index
, "");
3330 return sample_index
;
3333 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3334 const nir_intrinsic_instr
*instr
)
3336 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3337 if(instr
->variables
[0]->deref
.child
)
3338 type
= instr
->variables
[0]->deref
.child
->type
;
3340 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3341 LLVMValueRef coords
[4];
3342 LLVMValueRef masks
[] = {
3343 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3344 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3347 LLVMValueRef sample_index
= llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3350 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3351 bool is_array
= glsl_sampler_type_is_array(type
);
3352 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3353 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3354 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3355 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3356 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3357 count
= image_type_to_components_count(dim
, is_array
);
3360 LLVMValueRef fmask_load_address
[3];
3363 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3364 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3366 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3368 fmask_load_address
[2] = NULL
;
3370 for (chan
= 0; chan
< 2; ++chan
)
3371 fmask_load_address
[chan
] =
3372 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3373 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3374 ctx
->ac
.i32
, ""), "");
3375 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3377 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3378 fmask_load_address
[0],
3379 fmask_load_address
[1],
3380 fmask_load_address
[2],
3382 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, NULL
, true, false));
3384 if (count
== 1 && !gfx9_1d
) {
3385 if (instr
->src
[0].ssa
->num_components
)
3386 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3393 for (chan
= 0; chan
< count
; ++chan
) {
3394 coords
[chan
] = llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3397 for (chan
= 0; chan
< 2; ++chan
)
3398 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3399 ctx
->ac
.i32
, ""), "");
3400 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3406 coords
[2] = coords
[1];
3407 coords
[1] = ctx
->ac
.i32_0
;
3409 coords
[1] = ctx
->ac
.i32_0
;
3414 coords
[count
] = sample_index
;
3419 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3422 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3427 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3428 const nir_intrinsic_instr
*instr
)
3430 LLVMValueRef params
[7];
3432 char intrinsic_name
[64];
3433 const nir_variable
*var
= instr
->variables
[0]->var
;
3434 const struct glsl_type
*type
= var
->type
;
3436 if(instr
->variables
[0]->deref
.child
)
3437 type
= instr
->variables
[0]->deref
.child
->type
;
3439 type
= glsl_without_array(type
);
3440 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3441 params
[0] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, false);
3442 params
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3443 ctx
->ac
.i32_0
, ""); /* vindex */
3444 params
[2] = ctx
->ac
.i32_0
; /* voffset */
3445 params
[3] = ctx
->ac
.i1false
; /* glc */
3446 params
[4] = ctx
->ac
.i1false
; /* slc */
3447 res
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.load.format.v4f32", ctx
->ac
.v4f32
,
3450 res
= trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3451 res
= ac_to_integer(&ctx
->ac
, res
);
3453 bool is_da
= glsl_sampler_type_is_array(type
) ||
3454 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
||
3455 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_SUBPASS
||
3456 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_SUBPASS_MS
;
3457 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3458 LLVMValueRef glc
= ctx
->ac
.i1false
;
3459 LLVMValueRef slc
= ctx
->ac
.i1false
;
3461 params
[0] = get_image_coords(ctx
, instr
);
3462 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3463 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3464 if (HAVE_LLVM
<= 0x0309) {
3465 params
[3] = ctx
->ac
.i1false
; /* r128 */
3470 LLVMValueRef lwe
= ctx
->ac
.i1false
;
3477 ac_get_image_intr_name("llvm.amdgcn.image.load",
3478 ctx
->ac
.v4f32
, /* vdata */
3479 LLVMTypeOf(params
[0]), /* coords */
3480 LLVMTypeOf(params
[1]), /* rsrc */
3481 intrinsic_name
, sizeof(intrinsic_name
));
3483 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3484 params
, 7, AC_FUNC_ATTR_READONLY
);
3486 return ac_to_integer(&ctx
->ac
, res
);
3489 static void visit_image_store(struct ac_nir_context
*ctx
,
3490 nir_intrinsic_instr
*instr
)
3492 LLVMValueRef params
[8];
3493 char intrinsic_name
[64];
3494 const nir_variable
*var
= instr
->variables
[0]->var
;
3495 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3496 LLVMValueRef glc
= ctx
->ac
.i1false
;
3497 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3499 glc
= ctx
->ac
.i1true
;
3501 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3502 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3503 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, true);
3504 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3505 ctx
->ac
.i32_0
, ""); /* vindex */
3506 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3507 params
[4] = glc
; /* glc */
3508 params
[5] = ctx
->ac
.i1false
; /* slc */
3509 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3512 bool is_da
= glsl_sampler_type_is_array(type
) ||
3513 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3514 LLVMValueRef da
= is_da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3515 LLVMValueRef slc
= ctx
->ac
.i1false
;
3517 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3518 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3519 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, true);
3520 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3521 if (HAVE_LLVM
<= 0x0309) {
3522 params
[4] = ctx
->ac
.i1false
; /* r128 */
3527 LLVMValueRef lwe
= ctx
->ac
.i1false
;
3534 ac_get_image_intr_name("llvm.amdgcn.image.store",
3535 LLVMTypeOf(params
[0]), /* vdata */
3536 LLVMTypeOf(params
[1]), /* coords */
3537 LLVMTypeOf(params
[2]), /* rsrc */
3538 intrinsic_name
, sizeof(intrinsic_name
));
3540 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3546 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3547 const nir_intrinsic_instr
*instr
)
3549 LLVMValueRef params
[7];
3550 int param_count
= 0;
3551 const nir_variable
*var
= instr
->variables
[0]->var
;
3553 const char *atomic_name
;
3554 char intrinsic_name
[41];
3555 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3556 MAYBE_UNUSED
int length
;
3558 bool is_unsigned
= glsl_get_sampler_result_type(type
) == GLSL_TYPE_UINT
;
3560 switch (instr
->intrinsic
) {
3561 case nir_intrinsic_image_atomic_add
:
3562 atomic_name
= "add";
3564 case nir_intrinsic_image_atomic_min
:
3565 atomic_name
= is_unsigned
? "umin" : "smin";
3567 case nir_intrinsic_image_atomic_max
:
3568 atomic_name
= is_unsigned
? "umax" : "smax";
3570 case nir_intrinsic_image_atomic_and
:
3571 atomic_name
= "and";
3573 case nir_intrinsic_image_atomic_or
:
3576 case nir_intrinsic_image_atomic_xor
:
3577 atomic_name
= "xor";
3579 case nir_intrinsic_image_atomic_exchange
:
3580 atomic_name
= "swap";
3582 case nir_intrinsic_image_atomic_comp_swap
:
3583 atomic_name
= "cmpswap";
3589 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3590 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3591 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3593 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3594 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3596 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3597 ctx
->ac
.i32_0
, ""); /* vindex */
3598 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3599 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3601 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3602 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3604 char coords_type
[8];
3606 bool da
= glsl_sampler_type_is_array(type
) ||
3607 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3609 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3610 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3612 params
[param_count
++] = ctx
->ac
.i1false
; /* r128 */
3613 params
[param_count
++] = da
? ctx
->ac
.i1true
: ctx
->ac
.i1false
; /* da */
3614 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3616 build_int_type_name(LLVMTypeOf(coords
),
3617 coords_type
, sizeof(coords_type
));
3619 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3620 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3623 assert(length
< sizeof(intrinsic_name
));
3624 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3627 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3628 const nir_intrinsic_instr
*instr
)
3631 const nir_variable
*var
= instr
->variables
[0]->var
;
3632 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3633 bool da
= glsl_sampler_type_is_array(var
->type
) ||
3634 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_CUBE
;
3635 if(instr
->variables
[0]->deref
.child
)
3636 type
= instr
->variables
[0]->deref
.child
->type
;
3638 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3639 return get_buffer_size(ctx
,
3640 get_sampler_desc(ctx
, instr
->variables
[0],
3641 AC_DESC_BUFFER
, NULL
, true, false), true);
3643 struct ac_image_args args
= { 0 };
3647 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3648 args
.opcode
= ac_image_get_resinfo
;
3649 args
.addr
= ctx
->ac
.i32_0
;
3651 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3653 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3655 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3656 glsl_sampler_type_is_array(type
)) {
3657 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3658 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3659 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3660 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3662 if (ctx
->ac
.chip_class
>= GFX9
&&
3663 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3664 glsl_sampler_type_is_array(type
)) {
3665 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3666 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3673 #define NOOP_WAITCNT 0xf7f
3674 #define LGKM_CNT 0x07f
3675 #define VM_CNT 0xf70
3677 static void emit_waitcnt(struct nir_to_llvm_context
*ctx
,
3680 LLVMValueRef args
[1] = {
3681 LLVMConstInt(ctx
->ac
.i32
, simm16
, false),
3683 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.s.waitcnt",
3684 ctx
->ac
.voidt
, args
, 1, 0);
3687 static void emit_membar(struct nir_to_llvm_context
*ctx
,
3688 const nir_intrinsic_instr
*instr
)
3690 unsigned waitcnt
= NOOP_WAITCNT
;
3692 switch (instr
->intrinsic
) {
3693 case nir_intrinsic_memory_barrier
:
3694 case nir_intrinsic_group_memory_barrier
:
3695 waitcnt
&= VM_CNT
& LGKM_CNT
;
3697 case nir_intrinsic_memory_barrier_atomic_counter
:
3698 case nir_intrinsic_memory_barrier_buffer
:
3699 case nir_intrinsic_memory_barrier_image
:
3702 case nir_intrinsic_memory_barrier_shared
:
3703 waitcnt
&= LGKM_CNT
;
3708 if (waitcnt
!= NOOP_WAITCNT
)
3709 emit_waitcnt(ctx
, waitcnt
);
3712 static void emit_barrier(struct nir_to_llvm_context
*ctx
)
3714 /* SI only (thanks to a hw bug workaround):
3715 * The real barrier instruction isn’t needed, because an entire patch
3716 * always fits into a single wave.
3718 if (ctx
->options
->chip_class
== SI
&&
3719 ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3720 emit_waitcnt(ctx
, LGKM_CNT
& VM_CNT
);
3723 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.s.barrier",
3724 ctx
->ac
.voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3727 static void emit_discard_if(struct ac_nir_context
*ctx
,
3728 const nir_intrinsic_instr
*instr
)
3732 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3733 get_src(ctx
, instr
->src
[0]),
3735 ac_build_kill_if_false(&ctx
->ac
, cond
);
3739 visit_load_local_invocation_index(struct nir_to_llvm_context
*ctx
)
3741 LLVMValueRef result
;
3742 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3743 result
= LLVMBuildAnd(ctx
->builder
, ctx
->tg_size
,
3744 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3746 return LLVMBuildAdd(ctx
->builder
, result
, thread_id
, "");
3749 static LLVMValueRef
visit_var_atomic(struct nir_to_llvm_context
*ctx
,
3750 const nir_intrinsic_instr
*instr
)
3752 LLVMValueRef ptr
, result
;
3753 LLVMValueRef src
= get_src(ctx
->nir
, instr
->src
[0]);
3754 ptr
= build_gep_for_deref(ctx
->nir
, instr
->variables
[0]);
3756 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
) {
3757 LLVMValueRef src1
= get_src(ctx
->nir
, instr
->src
[1]);
3758 result
= LLVMBuildAtomicCmpXchg(ctx
->builder
,
3760 LLVMAtomicOrderingSequentiallyConsistent
,
3761 LLVMAtomicOrderingSequentiallyConsistent
,
3764 LLVMAtomicRMWBinOp op
;
3765 switch (instr
->intrinsic
) {
3766 case nir_intrinsic_var_atomic_add
:
3767 op
= LLVMAtomicRMWBinOpAdd
;
3769 case nir_intrinsic_var_atomic_umin
:
3770 op
= LLVMAtomicRMWBinOpUMin
;
3772 case nir_intrinsic_var_atomic_umax
:
3773 op
= LLVMAtomicRMWBinOpUMax
;
3775 case nir_intrinsic_var_atomic_imin
:
3776 op
= LLVMAtomicRMWBinOpMin
;
3778 case nir_intrinsic_var_atomic_imax
:
3779 op
= LLVMAtomicRMWBinOpMax
;
3781 case nir_intrinsic_var_atomic_and
:
3782 op
= LLVMAtomicRMWBinOpAnd
;
3784 case nir_intrinsic_var_atomic_or
:
3785 op
= LLVMAtomicRMWBinOpOr
;
3787 case nir_intrinsic_var_atomic_xor
:
3788 op
= LLVMAtomicRMWBinOpXor
;
3790 case nir_intrinsic_var_atomic_exchange
:
3791 op
= LLVMAtomicRMWBinOpXchg
;
3797 result
= LLVMBuildAtomicRMW(ctx
->builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
3798 LLVMAtomicOrderingSequentiallyConsistent
,
3804 #define INTERP_CENTER 0
3805 #define INTERP_CENTROID 1
3806 #define INTERP_SAMPLE 2
3808 static LLVMValueRef
lookup_interp_param(struct nir_to_llvm_context
*ctx
,
3809 enum glsl_interp_mode interp
, unsigned location
)
3812 case INTERP_MODE_FLAT
:
3815 case INTERP_MODE_SMOOTH
:
3816 case INTERP_MODE_NONE
:
3817 if (location
== INTERP_CENTER
)
3818 return ctx
->persp_center
;
3819 else if (location
== INTERP_CENTROID
)
3820 return ctx
->persp_centroid
;
3821 else if (location
== INTERP_SAMPLE
)
3822 return ctx
->persp_sample
;
3824 case INTERP_MODE_NOPERSPECTIVE
:
3825 if (location
== INTERP_CENTER
)
3826 return ctx
->linear_center
;
3827 else if (location
== INTERP_CENTROID
)
3828 return ctx
->linear_centroid
;
3829 else if (location
== INTERP_SAMPLE
)
3830 return ctx
->linear_sample
;
3836 static LLVMValueRef
load_sample_position(struct nir_to_llvm_context
*ctx
,
3837 LLVMValueRef sample_id
)
3839 LLVMValueRef result
;
3840 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
3842 ptr
= LLVMBuildBitCast(ctx
->builder
, ptr
,
3843 const_array(ctx
->ac
.v2f32
, 64), "");
3845 sample_id
= LLVMBuildAdd(ctx
->builder
, sample_id
, ctx
->sample_pos_offset
, "");
3846 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
3851 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
3853 LLVMValueRef values
[2];
3855 values
[0] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[0]);
3856 values
[1] = emit_ffract(&ctx
->ac
, ctx
->abi
->frag_pos
[1]);
3857 return ac_build_gather_values(&ctx
->ac
, values
, 2);
3860 static LLVMValueRef
visit_interp(struct nir_to_llvm_context
*ctx
,
3861 const nir_intrinsic_instr
*instr
)
3863 LLVMValueRef result
[4];
3864 LLVMValueRef interp_param
, attr_number
;
3867 LLVMValueRef src_c0
= NULL
;
3868 LLVMValueRef src_c1
= NULL
;
3869 LLVMValueRef src0
= NULL
;
3870 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
3871 switch (instr
->intrinsic
) {
3872 case nir_intrinsic_interp_var_at_centroid
:
3873 location
= INTERP_CENTROID
;
3875 case nir_intrinsic_interp_var_at_sample
:
3876 case nir_intrinsic_interp_var_at_offset
:
3877 location
= INTERP_CENTER
;
3878 src0
= get_src(ctx
->nir
, instr
->src
[0]);
3884 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
3885 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->ac
.i32_0
, ""));
3886 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->ac
.i32_1
, ""));
3887 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
3888 LLVMValueRef sample_position
;
3889 LLVMValueRef halfval
= LLVMConstReal(ctx
->ac
.f32
, 0.5f
);
3891 /* fetch sample ID */
3892 sample_position
= load_sample_position(ctx
, src0
);
3894 src_c0
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->ac
.i32_0
, "");
3895 src_c0
= LLVMBuildFSub(ctx
->builder
, src_c0
, halfval
, "");
3896 src_c1
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->ac
.i32_1
, "");
3897 src_c1
= LLVMBuildFSub(ctx
->builder
, src_c1
, halfval
, "");
3899 interp_param
= lookup_interp_param(ctx
, instr
->variables
[0]->var
->data
.interpolation
, location
);
3900 attr_number
= LLVMConstInt(ctx
->ac
.i32
, input_index
, false);
3902 if (location
== INTERP_CENTER
) {
3903 LLVMValueRef ij_out
[2];
3904 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
->nir
, interp_param
);
3907 * take the I then J parameters, and the DDX/Y for it, and
3908 * calculate the IJ inputs for the interpolator.
3909 * temp1 = ddx * offset/sample.x + I;
3910 * interp_param.I = ddy * offset/sample.y + temp1;
3911 * temp1 = ddx * offset/sample.x + J;
3912 * interp_param.J = ddy * offset/sample.y + temp1;
3914 for (unsigned i
= 0; i
< 2; i
++) {
3915 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->ac
.i32
, i
, false);
3916 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->ac
.i32
, i
+ 2, false);
3917 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->builder
,
3918 ddxy_out
, ix_ll
, "");
3919 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->builder
,
3920 ddxy_out
, iy_ll
, "");
3921 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->builder
,
3922 interp_param
, ix_ll
, "");
3923 LLVMValueRef temp1
, temp2
;
3925 interp_el
= LLVMBuildBitCast(ctx
->builder
, interp_el
,
3928 temp1
= LLVMBuildFMul(ctx
->builder
, ddx_el
, src_c0
, "");
3929 temp1
= LLVMBuildFAdd(ctx
->builder
, temp1
, interp_el
, "");
3931 temp2
= LLVMBuildFMul(ctx
->builder
, ddy_el
, src_c1
, "");
3932 temp2
= LLVMBuildFAdd(ctx
->builder
, temp2
, temp1
, "");
3934 ij_out
[i
] = LLVMBuildBitCast(ctx
->builder
,
3935 temp2
, ctx
->ac
.i32
, "");
3937 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
3941 for (chan
= 0; chan
< 4; chan
++) {
3942 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
3945 interp_param
= LLVMBuildBitCast(ctx
->builder
,
3946 interp_param
, ctx
->ac
.v2f32
, "");
3947 LLVMValueRef i
= LLVMBuildExtractElement(
3948 ctx
->builder
, interp_param
, ctx
->ac
.i32_0
, "");
3949 LLVMValueRef j
= LLVMBuildExtractElement(
3950 ctx
->builder
, interp_param
, ctx
->ac
.i32_1
, "");
3952 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
3953 llvm_chan
, attr_number
,
3954 ctx
->prim_mask
, i
, j
);
3956 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
3957 LLVMConstInt(ctx
->ac
.i32
, 2, false),
3958 llvm_chan
, attr_number
,
3962 return ac_build_varying_gather_values(&ctx
->ac
, result
, instr
->num_components
,
3963 instr
->variables
[0]->var
->data
.location_frac
);
3967 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
3969 LLVMValueRef gs_next_vertex
;
3970 LLVMValueRef can_emit
;
3972 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
3974 /* Write vertex attribute values to GSVS ring */
3975 gs_next_vertex
= LLVMBuildLoad(ctx
->builder
,
3976 ctx
->gs_next_vertex
,
3979 /* If this thread has already emitted the declared maximum number of
3980 * vertices, kill it: excessive vertex emissions are not supposed to
3981 * have any effect, and GS threads have no externally observable
3982 * effects other than emitting vertices.
3984 can_emit
= LLVMBuildICmp(ctx
->builder
, LLVMIntULT
, gs_next_vertex
,
3985 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
3986 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
3988 /* loop num outputs */
3990 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
3991 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
3996 if (!(ctx
->output_mask
& (1ull << i
)))
3999 if (i
== VARYING_SLOT_CLIP_DIST0
) {
4000 /* pack clip and cull into a single set of slots */
4001 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4005 for (unsigned j
= 0; j
< length
; j
++) {
4006 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
,
4008 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4009 voffset
= LLVMBuildAdd(ctx
->builder
, voffset
, gs_next_vertex
, "");
4010 voffset
= LLVMBuildMul(ctx
->builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4012 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
4014 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4016 voffset
, ctx
->gs2vs_offset
, 0,
4022 gs_next_vertex
= LLVMBuildAdd(ctx
->builder
, gs_next_vertex
,
4024 LLVMBuildStore(ctx
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4026 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4030 visit_end_primitive(struct nir_to_llvm_context
*ctx
,
4031 const nir_intrinsic_instr
*instr
)
4033 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4037 visit_load_tess_coord(struct nir_to_llvm_context
*ctx
,
4038 const nir_intrinsic_instr
*instr
)
4040 LLVMValueRef coord
[4] = {
4047 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4048 coord
[2] = LLVMBuildFSub(ctx
->builder
, ctx
->ac
.f32_1
,
4049 LLVMBuildFAdd(ctx
->builder
, coord
[0], coord
[1], ""), "");
4051 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, coord
, instr
->num_components
);
4052 return LLVMBuildBitCast(ctx
->builder
, result
,
4053 get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
4056 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4057 nir_intrinsic_instr
*instr
)
4059 LLVMValueRef result
= NULL
;
4061 switch (instr
->intrinsic
) {
4062 case nir_intrinsic_load_work_group_id
: {
4063 result
= ctx
->nctx
->workgroup_ids
;
4066 case nir_intrinsic_load_base_vertex
: {
4067 result
= ctx
->abi
->base_vertex
;
4070 case nir_intrinsic_load_vertex_id_zero_base
: {
4071 result
= ctx
->abi
->vertex_id
;
4074 case nir_intrinsic_load_local_invocation_id
: {
4075 result
= ctx
->nctx
->local_invocation_ids
;
4078 case nir_intrinsic_load_base_instance
:
4079 result
= ctx
->abi
->start_instance
;
4081 case nir_intrinsic_load_draw_id
:
4082 result
= ctx
->abi
->draw_id
;
4084 case nir_intrinsic_load_view_index
:
4085 result
= ctx
->nctx
->view_index
? ctx
->nctx
->view_index
: ctx
->ac
.i32_0
;
4087 case nir_intrinsic_load_invocation_id
:
4088 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4089 result
= unpack_param(&ctx
->ac
, ctx
->nctx
->tcs_rel_ids
, 8, 5);
4091 result
= ctx
->abi
->gs_invocation_id
;
4093 case nir_intrinsic_load_primitive_id
:
4094 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4096 ctx
->nctx
->shader_info
->gs
.uses_prim_id
= true;
4097 result
= ctx
->abi
->gs_prim_id
;
4098 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4099 ctx
->nctx
->shader_info
->tcs
.uses_prim_id
= true;
4100 result
= ctx
->nctx
->tcs_patch_id
;
4101 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4102 ctx
->nctx
->shader_info
->tcs
.uses_prim_id
= true;
4103 result
= ctx
->nctx
->tes_patch_id
;
4105 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4107 case nir_intrinsic_load_sample_id
:
4108 result
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4110 case nir_intrinsic_load_sample_pos
:
4111 result
= load_sample_pos(ctx
);
4113 case nir_intrinsic_load_sample_mask_in
:
4114 result
= ctx
->abi
->sample_coverage
;
4116 case nir_intrinsic_load_frag_coord
: {
4117 LLVMValueRef values
[4] = {
4118 ctx
->abi
->frag_pos
[0],
4119 ctx
->abi
->frag_pos
[1],
4120 ctx
->abi
->frag_pos
[2],
4121 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4123 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4126 case nir_intrinsic_load_front_face
:
4127 result
= ctx
->abi
->front_face
;
4129 case nir_intrinsic_load_instance_id
:
4130 result
= ctx
->abi
->instance_id
;
4132 case nir_intrinsic_load_num_work_groups
:
4133 result
= ctx
->nctx
->num_work_groups
;
4135 case nir_intrinsic_load_local_invocation_index
:
4136 result
= visit_load_local_invocation_index(ctx
->nctx
);
4138 case nir_intrinsic_load_push_constant
:
4139 result
= visit_load_push_constant(ctx
->nctx
, instr
);
4141 case nir_intrinsic_vulkan_resource_index
:
4142 result
= visit_vulkan_resource_index(ctx
->nctx
, instr
);
4144 case nir_intrinsic_vulkan_resource_reindex
:
4145 result
= visit_vulkan_resource_reindex(ctx
->nctx
, instr
);
4147 case nir_intrinsic_store_ssbo
:
4148 visit_store_ssbo(ctx
, instr
);
4150 case nir_intrinsic_load_ssbo
:
4151 result
= visit_load_buffer(ctx
, instr
);
4153 case nir_intrinsic_ssbo_atomic_add
:
4154 case nir_intrinsic_ssbo_atomic_imin
:
4155 case nir_intrinsic_ssbo_atomic_umin
:
4156 case nir_intrinsic_ssbo_atomic_imax
:
4157 case nir_intrinsic_ssbo_atomic_umax
:
4158 case nir_intrinsic_ssbo_atomic_and
:
4159 case nir_intrinsic_ssbo_atomic_or
:
4160 case nir_intrinsic_ssbo_atomic_xor
:
4161 case nir_intrinsic_ssbo_atomic_exchange
:
4162 case nir_intrinsic_ssbo_atomic_comp_swap
:
4163 result
= visit_atomic_ssbo(ctx
, instr
);
4165 case nir_intrinsic_load_ubo
:
4166 result
= visit_load_ubo_buffer(ctx
, instr
);
4168 case nir_intrinsic_get_buffer_size
:
4169 result
= visit_get_buffer_size(ctx
, instr
);
4171 case nir_intrinsic_load_var
:
4172 result
= visit_load_var(ctx
, instr
);
4174 case nir_intrinsic_store_var
:
4175 visit_store_var(ctx
, instr
);
4177 case nir_intrinsic_image_load
:
4178 result
= visit_image_load(ctx
, instr
);
4180 case nir_intrinsic_image_store
:
4181 visit_image_store(ctx
, instr
);
4183 case nir_intrinsic_image_atomic_add
:
4184 case nir_intrinsic_image_atomic_min
:
4185 case nir_intrinsic_image_atomic_max
:
4186 case nir_intrinsic_image_atomic_and
:
4187 case nir_intrinsic_image_atomic_or
:
4188 case nir_intrinsic_image_atomic_xor
:
4189 case nir_intrinsic_image_atomic_exchange
:
4190 case nir_intrinsic_image_atomic_comp_swap
:
4191 result
= visit_image_atomic(ctx
, instr
);
4193 case nir_intrinsic_image_size
:
4194 result
= visit_image_size(ctx
, instr
);
4196 case nir_intrinsic_discard
:
4197 ac_build_intrinsic(&ctx
->ac
, "llvm.AMDGPU.kilp",
4198 LLVMVoidTypeInContext(ctx
->ac
.context
),
4199 NULL
, 0, AC_FUNC_ATTR_LEGACY
);
4201 case nir_intrinsic_discard_if
:
4202 emit_discard_if(ctx
, instr
);
4204 case nir_intrinsic_memory_barrier
:
4205 case nir_intrinsic_group_memory_barrier
:
4206 case nir_intrinsic_memory_barrier_atomic_counter
:
4207 case nir_intrinsic_memory_barrier_buffer
:
4208 case nir_intrinsic_memory_barrier_image
:
4209 case nir_intrinsic_memory_barrier_shared
:
4210 emit_membar(ctx
->nctx
, instr
);
4212 case nir_intrinsic_barrier
:
4213 emit_barrier(ctx
->nctx
);
4215 case nir_intrinsic_var_atomic_add
:
4216 case nir_intrinsic_var_atomic_imin
:
4217 case nir_intrinsic_var_atomic_umin
:
4218 case nir_intrinsic_var_atomic_imax
:
4219 case nir_intrinsic_var_atomic_umax
:
4220 case nir_intrinsic_var_atomic_and
:
4221 case nir_intrinsic_var_atomic_or
:
4222 case nir_intrinsic_var_atomic_xor
:
4223 case nir_intrinsic_var_atomic_exchange
:
4224 case nir_intrinsic_var_atomic_comp_swap
:
4225 result
= visit_var_atomic(ctx
->nctx
, instr
);
4227 case nir_intrinsic_interp_var_at_centroid
:
4228 case nir_intrinsic_interp_var_at_sample
:
4229 case nir_intrinsic_interp_var_at_offset
:
4230 result
= visit_interp(ctx
->nctx
, instr
);
4232 case nir_intrinsic_emit_vertex
:
4233 assert(instr
->const_index
[0] == 0);
4234 ctx
->abi
->emit_vertex(ctx
->abi
, 0, ctx
->outputs
);
4236 case nir_intrinsic_end_primitive
:
4237 visit_end_primitive(ctx
->nctx
, instr
);
4239 case nir_intrinsic_load_tess_coord
:
4240 result
= visit_load_tess_coord(ctx
->nctx
, instr
);
4242 case nir_intrinsic_load_patch_vertices_in
:
4243 result
= LLVMConstInt(ctx
->ac
.i32
, ctx
->nctx
->options
->key
.tcs
.input_vertices
, false);
4246 fprintf(stderr
, "Unknown intrinsic: ");
4247 nir_print_instr(&instr
->instr
, stderr
);
4248 fprintf(stderr
, "\n");
4252 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4256 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4257 LLVMValueRef buffer_ptr
, bool write
)
4259 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4261 if (write
&& ctx
->stage
== MESA_SHADER_FRAGMENT
)
4262 ctx
->shader_info
->fs
.writes_memory
= true;
4264 return LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4267 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
4269 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4271 return LLVMBuildLoad(ctx
->builder
, buffer_ptr
, "");
4274 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4275 unsigned descriptor_set
,
4276 unsigned base_index
,
4277 unsigned constant_index
,
4279 enum ac_descriptor_type desc_type
,
4280 bool image
, bool write
)
4282 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
4283 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4284 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4285 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4286 unsigned offset
= binding
->offset
;
4287 unsigned stride
= binding
->size
;
4289 LLVMBuilderRef builder
= ctx
->builder
;
4292 assert(base_index
< layout
->binding_count
);
4294 if (write
&& ctx
->stage
== MESA_SHADER_FRAGMENT
)
4295 ctx
->shader_info
->fs
.writes_memory
= true;
4297 switch (desc_type
) {
4299 type
= ctx
->ac
.v8i32
;
4303 type
= ctx
->ac
.v8i32
;
4307 case AC_DESC_SAMPLER
:
4308 type
= ctx
->ac
.v4i32
;
4309 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4314 case AC_DESC_BUFFER
:
4315 type
= ctx
->ac
.v4i32
;
4319 unreachable("invalid desc_type\n");
4322 offset
+= constant_index
* stride
;
4324 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4325 (!index
|| binding
->immutable_samplers_equal
)) {
4326 if (binding
->immutable_samplers_equal
)
4329 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4331 LLVMValueRef constants
[] = {
4332 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
4333 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
4334 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
4335 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
4337 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4340 assert(stride
% type_size
== 0);
4343 index
= ctx
->ac
.i32_0
;
4345 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
4347 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
4348 list
= LLVMBuildPointerCast(builder
, list
, const_array(type
, 0), "");
4350 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4353 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4354 const nir_deref_var
*deref
,
4355 enum ac_descriptor_type desc_type
,
4356 const nir_tex_instr
*tex_instr
,
4357 bool image
, bool write
)
4359 LLVMValueRef index
= NULL
;
4360 unsigned constant_index
= 0;
4361 unsigned descriptor_set
;
4362 unsigned base_index
;
4365 assert(tex_instr
&& !image
);
4367 base_index
= tex_instr
->sampler_index
;
4369 const nir_deref
*tail
= &deref
->deref
;
4370 while (tail
->child
) {
4371 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4372 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4377 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4379 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4380 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4382 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4383 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4388 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4391 constant_index
+= child
->base_offset
* array_size
;
4393 tail
= &child
->deref
;
4395 descriptor_set
= deref
->var
->data
.descriptor_set
;
4396 base_index
= deref
->var
->data
.binding
;
4399 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4402 constant_index
, index
,
4403 desc_type
, image
, write
);
4406 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4407 struct ac_image_args
*args
,
4408 const nir_tex_instr
*instr
,
4410 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4411 LLVMValueRef
*param
, unsigned count
,
4414 unsigned is_rect
= 0;
4415 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4417 if (op
== nir_texop_lod
)
4419 /* Pad to power of two vector */
4420 while (count
< util_next_power_of_two(count
))
4421 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4424 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4426 args
->addr
= param
[0];
4428 args
->resource
= res_ptr
;
4429 args
->sampler
= samp_ptr
;
4431 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4432 args
->addr
= param
[0];
4436 args
->dmask
= dmask
;
4437 args
->unorm
= is_rect
;
4441 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4444 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4445 * filtering manually. The driver sets img7 to a mask clearing
4446 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4447 * s_and_b32 samp0, samp0, img7
4450 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4452 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4453 LLVMValueRef res
, LLVMValueRef samp
)
4455 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4456 LLVMValueRef img7
, samp0
;
4458 if (ctx
->ac
.chip_class
>= VI
)
4461 img7
= LLVMBuildExtractElement(builder
, res
,
4462 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4463 samp0
= LLVMBuildExtractElement(builder
, samp
,
4464 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4465 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4466 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4467 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4470 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4471 nir_tex_instr
*instr
,
4472 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4473 LLVMValueRef
*fmask_ptr
)
4475 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4476 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, instr
, false, false);
4478 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, instr
, false, false);
4481 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, instr
, false, false);
4483 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, instr
, false, false);
4484 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4485 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4487 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4488 instr
->op
== nir_texop_samples_identical
))
4489 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, instr
, false, false);
4492 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4495 coord
= ac_to_float(ctx
, coord
);
4496 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4497 coord
= ac_to_integer(ctx
, coord
);
4501 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4503 LLVMValueRef result
= NULL
;
4504 struct ac_image_args args
= { 0 };
4505 unsigned dmask
= 0xf;
4506 LLVMValueRef address
[16];
4507 LLVMValueRef coords
[5];
4508 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4509 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4510 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4511 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4512 LLVMValueRef derivs
[6];
4513 unsigned chan
, count
= 0;
4514 unsigned const_src
= 0, num_deriv_comp
= 0;
4515 bool lod_is_zero
= false;
4517 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4519 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4520 switch (instr
->src
[i
].src_type
) {
4521 case nir_tex_src_coord
:
4522 coord
= get_src(ctx
, instr
->src
[i
].src
);
4524 case nir_tex_src_projector
:
4526 case nir_tex_src_comparator
:
4527 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4529 case nir_tex_src_offset
:
4530 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4533 case nir_tex_src_bias
:
4534 bias
= get_src(ctx
, instr
->src
[i
].src
);
4536 case nir_tex_src_lod
: {
4537 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4539 if (val
&& val
->i32
[0] == 0)
4541 lod
= get_src(ctx
, instr
->src
[i
].src
);
4544 case nir_tex_src_ms_index
:
4545 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4547 case nir_tex_src_ms_mcs
:
4549 case nir_tex_src_ddx
:
4550 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4551 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4553 case nir_tex_src_ddy
:
4554 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4556 case nir_tex_src_texture_offset
:
4557 case nir_tex_src_sampler_offset
:
4558 case nir_tex_src_plane
:
4564 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4565 result
= get_buffer_size(ctx
, res_ptr
, true);
4569 if (instr
->op
== nir_texop_texture_samples
) {
4570 LLVMValueRef res
, samples
, is_msaa
;
4571 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4572 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4573 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4574 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4575 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4576 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4577 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4578 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4579 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4581 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4582 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4583 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4584 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
4585 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
4587 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
4594 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4595 coords
[chan
] = llvm_extract_elem(&ctx
->ac
, coord
, chan
);
4597 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4598 LLVMValueRef offset
[3], pack
;
4599 for (chan
= 0; chan
< 3; ++chan
)
4600 offset
[chan
] = ctx
->ac
.i32_0
;
4603 for (chan
= 0; chan
< get_llvm_num_components(offsets
); chan
++) {
4604 offset
[chan
] = llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
4605 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
4606 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
4608 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
4609 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
4611 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
4612 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
4613 address
[count
++] = pack
;
4616 /* pack LOD bias value */
4617 if (instr
->op
== nir_texop_txb
&& bias
) {
4618 address
[count
++] = bias
;
4621 /* Pack depth comparison value */
4622 if (instr
->is_shadow
&& comparator
) {
4623 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
4624 llvm_extract_elem(&ctx
->ac
, comparator
, 0));
4626 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4627 * so the depth comparison value isn't clamped for Z16 and
4628 * Z24 anymore. Do it manually here.
4630 * It's unnecessary if the original texture format was
4631 * Z32_FLOAT, but we don't know that here.
4633 if (ctx
->ac
.chip_class
== VI
&& ctx
->abi
->clamp_shadow_reference
)
4634 z
= ac_build_clamp(&ctx
->ac
, z
);
4636 address
[count
++] = z
;
4639 /* pack derivatives */
4641 int num_src_deriv_channels
, num_dest_deriv_channels
;
4642 switch (instr
->sampler_dim
) {
4643 case GLSL_SAMPLER_DIM_3D
:
4644 case GLSL_SAMPLER_DIM_CUBE
:
4646 num_src_deriv_channels
= 3;
4647 num_dest_deriv_channels
= 3;
4649 case GLSL_SAMPLER_DIM_2D
:
4651 num_src_deriv_channels
= 2;
4652 num_dest_deriv_channels
= 2;
4655 case GLSL_SAMPLER_DIM_1D
:
4656 num_src_deriv_channels
= 1;
4657 if (ctx
->ac
.chip_class
>= GFX9
) {
4658 num_dest_deriv_channels
= 2;
4661 num_dest_deriv_channels
= 1;
4667 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
4668 derivs
[i
] = ac_to_float(&ctx
->ac
, llvm_extract_elem(&ctx
->ac
, ddx
, i
));
4669 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, llvm_extract_elem(&ctx
->ac
, ddy
, i
));
4671 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
4672 derivs
[i
] = ctx
->ac
.f32_0
;
4673 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
4677 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
4678 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4679 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
4680 if (instr
->coord_components
== 3)
4681 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
4682 ac_prepare_cube_coords(&ctx
->ac
,
4683 instr
->op
== nir_texop_txd
, instr
->is_array
,
4684 instr
->op
== nir_texop_lod
, coords
, derivs
);
4690 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
4691 address
[count
++] = derivs
[i
];
4694 /* Pack texture coordinates */
4696 address
[count
++] = coords
[0];
4697 if (instr
->coord_components
> 1) {
4698 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
4699 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
4701 address
[count
++] = coords
[1];
4703 if (instr
->coord_components
> 2) {
4704 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4705 if (instr
->sampler_dim
!= GLSL_SAMPLER_DIM_3D
&&
4706 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_CUBE
&&
4707 instr
->op
!= nir_texop_txf
) {
4708 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
4710 address
[count
++] = coords
[2];
4713 if (ctx
->ac
.chip_class
>= GFX9
) {
4714 LLVMValueRef filler
;
4715 if (instr
->op
== nir_texop_txf
)
4716 filler
= ctx
->ac
.i32_0
;
4718 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
4720 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
4721 /* No nir_texop_lod, because it does not take a slice
4722 * even with array textures. */
4723 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
4724 address
[count
] = address
[count
- 1];
4725 address
[count
- 1] = filler
;
4728 address
[count
++] = filler
;
4734 if (lod
&& ((instr
->op
== nir_texop_txl
&& !lod_is_zero
) ||
4735 instr
->op
== nir_texop_txf
)) {
4736 address
[count
++] = lod
;
4737 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
4738 address
[count
++] = sample_index
;
4739 } else if(instr
->op
== nir_texop_txs
) {
4742 address
[count
++] = lod
;
4744 address
[count
++] = ctx
->ac
.i32_0
;
4747 for (chan
= 0; chan
< count
; chan
++) {
4748 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
4749 address
[chan
], ctx
->ac
.i32
, "");
4752 if (instr
->op
== nir_texop_samples_identical
) {
4753 LLVMValueRef txf_address
[4];
4754 struct ac_image_args txf_args
= { 0 };
4755 unsigned txf_count
= count
;
4756 memcpy(txf_address
, address
, sizeof(txf_address
));
4758 if (!instr
->is_array
)
4759 txf_address
[2] = ctx
->ac
.i32_0
;
4760 txf_address
[3] = ctx
->ac
.i32_0
;
4762 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
4764 txf_address
, txf_count
, 0xf);
4766 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
4768 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
4769 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
4773 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
4774 instr
->op
!= nir_texop_txs
) {
4775 unsigned sample_chan
= instr
->is_array
? 3 : 2;
4776 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
4779 instr
->is_array
? address
[2] : NULL
,
4780 address
[sample_chan
],
4784 if (offsets
&& instr
->op
== nir_texop_txf
) {
4785 nir_const_value
*const_offset
=
4786 nir_src_as_const_value(instr
->src
[const_src
].src
);
4787 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
4788 assert(const_offset
);
4789 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
4790 if (num_offsets
> 2)
4791 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
4792 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
4793 if (num_offsets
> 1)
4794 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
4795 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
4796 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
4797 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
4801 /* TODO TG4 support */
4802 if (instr
->op
== nir_texop_tg4
) {
4803 if (instr
->is_shadow
)
4806 dmask
= 1 << instr
->component
;
4808 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
4809 res_ptr
, samp_ptr
, address
, count
, dmask
);
4811 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
4813 if (instr
->op
== nir_texop_query_levels
)
4814 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4815 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
4816 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
4817 instr
->op
!= nir_texop_tg4
)
4818 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
4819 else if (instr
->op
== nir_texop_txs
&&
4820 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
4822 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
4823 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
4824 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
4825 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
4826 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
4827 } else if (ctx
->ac
.chip_class
>= GFX9
&&
4828 instr
->op
== nir_texop_txs
&&
4829 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
4831 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
4832 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
4833 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
4835 } else if (instr
->dest
.ssa
.num_components
!= 4)
4836 result
= trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
4840 assert(instr
->dest
.is_ssa
);
4841 result
= ac_to_integer(&ctx
->ac
, result
);
4842 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4847 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
4849 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
4850 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
4852 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4853 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
4856 static void visit_post_phi(struct ac_nir_context
*ctx
,
4857 nir_phi_instr
*instr
,
4858 LLVMValueRef llvm_phi
)
4860 nir_foreach_phi_src(src
, instr
) {
4861 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
4862 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
4864 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
4868 static void phi_post_pass(struct ac_nir_context
*ctx
)
4870 struct hash_entry
*entry
;
4871 hash_table_foreach(ctx
->phis
, entry
) {
4872 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
4873 (LLVMValueRef
)entry
->data
);
4878 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
4879 const nir_ssa_undef_instr
*instr
)
4881 unsigned num_components
= instr
->def
.num_components
;
4884 if (num_components
== 1)
4885 undef
= LLVMGetUndef(ctx
->ac
.i32
);
4887 undef
= LLVMGetUndef(LLVMVectorType(ctx
->ac
.i32
, num_components
));
4889 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
4892 static void visit_jump(struct ac_nir_context
*ctx
,
4893 const nir_jump_instr
*instr
)
4895 switch (instr
->type
) {
4896 case nir_jump_break
:
4897 LLVMBuildBr(ctx
->ac
.builder
, ctx
->break_block
);
4898 LLVMClearInsertionPosition(ctx
->ac
.builder
);
4900 case nir_jump_continue
:
4901 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
4902 LLVMClearInsertionPosition(ctx
->ac
.builder
);
4905 fprintf(stderr
, "Unknown NIR jump instr: ");
4906 nir_print_instr(&instr
->instr
, stderr
);
4907 fprintf(stderr
, "\n");
4912 static void visit_cf_list(struct ac_nir_context
*ctx
,
4913 struct exec_list
*list
);
4915 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
4917 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
4918 nir_foreach_instr(instr
, block
)
4920 switch (instr
->type
) {
4921 case nir_instr_type_alu
:
4922 visit_alu(ctx
, nir_instr_as_alu(instr
));
4924 case nir_instr_type_load_const
:
4925 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
4927 case nir_instr_type_intrinsic
:
4928 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
4930 case nir_instr_type_tex
:
4931 visit_tex(ctx
, nir_instr_as_tex(instr
));
4933 case nir_instr_type_phi
:
4934 visit_phi(ctx
, nir_instr_as_phi(instr
));
4936 case nir_instr_type_ssa_undef
:
4937 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
4939 case nir_instr_type_jump
:
4940 visit_jump(ctx
, nir_instr_as_jump(instr
));
4943 fprintf(stderr
, "Unknown NIR instr type: ");
4944 nir_print_instr(instr
, stderr
);
4945 fprintf(stderr
, "\n");
4950 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
4953 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
4955 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
4957 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
4958 LLVMBasicBlockRef merge_block
=
4959 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
4960 LLVMBasicBlockRef if_block
=
4961 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
4962 LLVMBasicBlockRef else_block
= merge_block
;
4963 if (!exec_list_is_empty(&if_stmt
->else_list
))
4964 else_block
= LLVMAppendBasicBlockInContext(
4965 ctx
->ac
.context
, fn
, "");
4967 LLVMValueRef cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
, value
,
4968 LLVMConstInt(ctx
->ac
.i32
, 0, false), "");
4969 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, if_block
, else_block
);
4971 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, if_block
);
4972 visit_cf_list(ctx
, &if_stmt
->then_list
);
4973 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
4974 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
4976 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
4977 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, else_block
);
4978 visit_cf_list(ctx
, &if_stmt
->else_list
);
4979 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
4980 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
4983 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
4986 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
4988 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
4989 LLVMBasicBlockRef continue_parent
= ctx
->continue_block
;
4990 LLVMBasicBlockRef break_parent
= ctx
->break_block
;
4992 ctx
->continue_block
=
4993 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
4995 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
4997 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
4998 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->continue_block
);
4999 visit_cf_list(ctx
, &loop
->body
);
5001 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5002 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5003 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->break_block
);
5005 ctx
->continue_block
= continue_parent
;
5006 ctx
->break_block
= break_parent
;
5009 static void visit_cf_list(struct ac_nir_context
*ctx
,
5010 struct exec_list
*list
)
5012 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5014 switch (node
->type
) {
5015 case nir_cf_node_block
:
5016 visit_block(ctx
, nir_cf_node_as_block(node
));
5019 case nir_cf_node_if
:
5020 visit_if(ctx
, nir_cf_node_as_if(node
));
5023 case nir_cf_node_loop
:
5024 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5034 handle_vs_input_decl(struct nir_to_llvm_context
*ctx
,
5035 struct nir_variable
*variable
)
5037 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5038 LLVMValueRef t_offset
;
5039 LLVMValueRef t_list
;
5041 LLVMValueRef buffer_index
;
5042 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5043 int idx
= variable
->data
.location
;
5044 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5046 variable
->data
.driver_location
= idx
* 4;
5048 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << index
)) {
5049 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.instance_id
,
5050 ctx
->abi
.start_instance
, "");
5051 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(3,
5052 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5054 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.vertex_id
,
5055 ctx
->abi
.base_vertex
, "");
5057 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5058 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
5060 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5062 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5064 LLVMConstInt(ctx
->ac
.i32
, 0, false),
5067 for (unsigned chan
= 0; chan
< 4; chan
++) {
5068 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5069 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5070 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
,
5071 input
, llvm_chan
, ""));
5076 static void interp_fs_input(struct nir_to_llvm_context
*ctx
,
5078 LLVMValueRef interp_param
,
5079 LLVMValueRef prim_mask
,
5080 LLVMValueRef result
[4])
5082 LLVMValueRef attr_number
;
5085 bool interp
= interp_param
!= NULL
;
5087 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
5089 /* fs.constant returns the param from the middle vertex, so it's not
5090 * really useful for flat shading. It's meant to be used for custom
5091 * interpolation (but the intrinsic can't fetch from the other two
5094 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5095 * to do the right thing. The only reason we use fs.constant is that
5096 * fs.interp cannot be used on integers, because they can be equal
5100 interp_param
= LLVMBuildBitCast(ctx
->builder
, interp_param
,
5103 i
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5105 j
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
5109 for (chan
= 0; chan
< 4; chan
++) {
5110 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5113 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5118 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5119 LLVMConstInt(ctx
->ac
.i32
, 2, false),
5128 handle_fs_input_decl(struct nir_to_llvm_context
*ctx
,
5129 struct nir_variable
*variable
)
5131 int idx
= variable
->data
.location
;
5132 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5133 LLVMValueRef interp
;
5135 variable
->data
.driver_location
= idx
* 4;
5136 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5138 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5139 unsigned interp_type
;
5140 if (variable
->data
.sample
) {
5141 interp_type
= INTERP_SAMPLE
;
5142 ctx
->shader_info
->info
.ps
.force_persample
= true;
5143 } else if (variable
->data
.centroid
)
5144 interp_type
= INTERP_CENTROID
;
5146 interp_type
= INTERP_CENTER
;
5148 interp
= lookup_interp_param(ctx
, variable
->data
.interpolation
, interp_type
);
5152 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5153 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5158 handle_vs_inputs(struct nir_to_llvm_context
*ctx
,
5159 struct nir_shader
*nir
) {
5160 nir_foreach_variable(variable
, &nir
->inputs
)
5161 handle_vs_input_decl(ctx
, variable
);
5165 prepare_interp_optimize(struct nir_to_llvm_context
*ctx
,
5166 struct nir_shader
*nir
)
5168 if (!ctx
->options
->key
.fs
.multisample
)
5171 bool uses_center
= false;
5172 bool uses_centroid
= false;
5173 nir_foreach_variable(variable
, &nir
->inputs
) {
5174 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5175 variable
->data
.sample
)
5178 if (variable
->data
.centroid
)
5179 uses_centroid
= true;
5184 if (uses_center
&& uses_centroid
) {
5185 LLVMValueRef sel
= LLVMBuildICmp(ctx
->builder
, LLVMIntSLT
, ctx
->prim_mask
, ctx
->ac
.i32_0
, "");
5186 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5187 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5192 handle_fs_inputs(struct nir_to_llvm_context
*ctx
,
5193 struct nir_shader
*nir
)
5195 prepare_interp_optimize(ctx
, nir
);
5197 nir_foreach_variable(variable
, &nir
->inputs
)
5198 handle_fs_input_decl(ctx
, variable
);
5202 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5203 ctx
->shader_info
->info
.needs_multiview_view_index
)
5204 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5206 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5207 LLVMValueRef interp_param
;
5208 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5210 if (!(ctx
->input_mask
& (1ull << i
)))
5213 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5214 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5215 interp_param
= *inputs
;
5216 interp_fs_input(ctx
, index
, interp_param
, ctx
->prim_mask
,
5220 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5222 } else if (i
== VARYING_SLOT_POS
) {
5223 for(int i
= 0; i
< 3; ++i
)
5224 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5226 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
5227 ctx
->abi
.frag_pos
[3]);
5230 ctx
->shader_info
->fs
.num_interp
= index
;
5231 if (ctx
->input_mask
& (1 << VARYING_SLOT_PNTC
))
5232 ctx
->shader_info
->fs
.has_pcoord
= true;
5233 if (ctx
->input_mask
& (1 << VARYING_SLOT_PRIMITIVE_ID
))
5234 ctx
->shader_info
->fs
.prim_id_input
= true;
5235 if (ctx
->input_mask
& (1 << VARYING_SLOT_LAYER
))
5236 ctx
->shader_info
->fs
.layer_input
= true;
5237 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5239 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5240 ctx
->view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5244 ac_build_alloca(struct ac_llvm_context
*ac
,
5248 LLVMBuilderRef builder
= ac
->builder
;
5249 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
5250 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5251 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
5252 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
5253 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
5257 LLVMPositionBuilderBefore(first_builder
, first_instr
);
5259 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
5262 res
= LLVMBuildAlloca(first_builder
, type
, name
);
5263 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
5265 LLVMDisposeBuilder(first_builder
);
5270 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5274 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5275 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5280 scan_shader_output_decl(struct nir_to_llvm_context
*ctx
,
5281 struct nir_variable
*variable
,
5282 struct nir_shader
*shader
,
5283 gl_shader_stage stage
)
5285 int idx
= variable
->data
.location
+ variable
->data
.index
;
5286 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5287 uint64_t mask_attribs
;
5289 variable
->data
.driver_location
= idx
* 4;
5291 /* tess ctrl has it's own load/store paths for outputs */
5292 if (stage
== MESA_SHADER_TESS_CTRL
)
5295 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5296 if (stage
== MESA_SHADER_VERTEX
||
5297 stage
== MESA_SHADER_TESS_EVAL
||
5298 stage
== MESA_SHADER_GEOMETRY
) {
5299 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5300 int length
= shader
->info
.clip_distance_array_size
+
5301 shader
->info
.cull_distance_array_size
;
5302 if (stage
== MESA_SHADER_VERTEX
) {
5303 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5304 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5306 if (stage
== MESA_SHADER_TESS_EVAL
) {
5307 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5308 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5315 mask_attribs
= 1ull << idx
;
5319 ctx
->output_mask
|= mask_attribs
;
5323 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5324 struct nir_shader
*nir
,
5325 struct nir_variable
*variable
)
5327 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5328 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5330 /* tess ctrl has it's own load/store paths for outputs */
5331 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5334 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5335 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5336 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5337 int idx
= variable
->data
.location
+ variable
->data
.index
;
5338 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5339 int length
= nir
->info
.clip_distance_array_size
+
5340 nir
->info
.cull_distance_array_size
;
5349 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5350 for (unsigned chan
= 0; chan
< 4; chan
++) {
5351 ctx
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5352 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5358 glsl_base_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5359 enum glsl_base_type type
)
5363 case GLSL_TYPE_UINT
:
5364 case GLSL_TYPE_BOOL
:
5365 case GLSL_TYPE_SUBROUTINE
:
5367 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5369 case GLSL_TYPE_INT64
:
5370 case GLSL_TYPE_UINT64
:
5372 case GLSL_TYPE_DOUBLE
:
5375 unreachable("unknown GLSL type");
5380 glsl_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5381 const struct glsl_type
*type
)
5383 if (glsl_type_is_scalar(type
)) {
5384 return glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
));
5387 if (glsl_type_is_vector(type
)) {
5388 return LLVMVectorType(
5389 glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
)),
5390 glsl_get_vector_elements(type
));
5393 if (glsl_type_is_matrix(type
)) {
5394 return LLVMArrayType(
5395 glsl_to_llvm_type(ctx
, glsl_get_column_type(type
)),
5396 glsl_get_matrix_columns(type
));
5399 if (glsl_type_is_array(type
)) {
5400 return LLVMArrayType(
5401 glsl_to_llvm_type(ctx
, glsl_get_array_element(type
)),
5402 glsl_get_length(type
));
5405 assert(glsl_type_is_struct(type
));
5407 LLVMTypeRef member_types
[glsl_get_length(type
)];
5409 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5411 glsl_to_llvm_type(ctx
,
5412 glsl_get_struct_field(type
, i
));
5415 return LLVMStructTypeInContext(ctx
->context
, member_types
,
5416 glsl_get_length(type
), false);
5420 setup_locals(struct ac_nir_context
*ctx
,
5421 struct nir_function
*func
)
5424 ctx
->num_locals
= 0;
5425 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5426 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5427 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5428 ctx
->num_locals
+= attrib_count
;
5430 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5434 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5435 for (j
= 0; j
< 4; j
++) {
5436 ctx
->locals
[i
* 4 + j
] =
5437 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5443 setup_shared(struct ac_nir_context
*ctx
,
5444 struct nir_shader
*nir
)
5446 nir_foreach_variable(variable
, &nir
->shared
) {
5447 LLVMValueRef shared
=
5448 LLVMAddGlobalInAddressSpace(
5449 ctx
->ac
.module
, glsl_to_llvm_type(ctx
->nctx
, variable
->type
),
5450 variable
->name
? variable
->name
: "",
5452 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5457 emit_float_saturate(struct ac_llvm_context
*ctx
, LLVMValueRef v
, float lo
, float hi
)
5459 v
= ac_to_float(ctx
, v
);
5460 v
= emit_intrin_2f_param(ctx
, "llvm.maxnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, lo
));
5461 return emit_intrin_2f_param(ctx
, "llvm.minnum", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, hi
));
5465 static LLVMValueRef
emit_pack_int16(struct nir_to_llvm_context
*ctx
,
5466 LLVMValueRef src0
, LLVMValueRef src1
)
5468 LLVMValueRef const16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
5469 LLVMValueRef comp
[2];
5471 comp
[0] = LLVMBuildAnd(ctx
->builder
, src0
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5472 comp
[1] = LLVMBuildAnd(ctx
->builder
, src1
, LLVMConstInt(ctx
->ac
.i32
, 65535, 0), "");
5473 comp
[1] = LLVMBuildShl(ctx
->builder
, comp
[1], const16
, "");
5474 return LLVMBuildOr(ctx
->builder
, comp
[0], comp
[1], "");
5477 /* Initialize arguments for the shader export intrinsic */
5479 si_llvm_init_export_args(struct nir_to_llvm_context
*ctx
,
5480 LLVMValueRef
*values
,
5482 struct ac_export_args
*args
)
5484 /* Default is 0xf. Adjusted below depending on the format. */
5485 args
->enabled_channels
= 0xf;
5487 /* Specify whether the EXEC mask represents the valid mask */
5488 args
->valid_mask
= 0;
5490 /* Specify whether this is the last export */
5493 /* Specify the target we are exporting */
5494 args
->target
= target
;
5496 args
->compr
= false;
5497 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
5498 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
5499 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
5500 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5505 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5506 LLVMValueRef val
[4];
5507 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5508 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5509 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5510 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5512 switch(col_format
) {
5513 case V_028714_SPI_SHADER_ZERO
:
5514 args
->enabled_channels
= 0; /* writemask */
5515 args
->target
= V_008DFC_SQ_EXP_NULL
;
5518 case V_028714_SPI_SHADER_32_R
:
5519 args
->enabled_channels
= 1;
5520 args
->out
[0] = values
[0];
5523 case V_028714_SPI_SHADER_32_GR
:
5524 args
->enabled_channels
= 0x3;
5525 args
->out
[0] = values
[0];
5526 args
->out
[1] = values
[1];
5529 case V_028714_SPI_SHADER_32_AR
:
5530 args
->enabled_channels
= 0x9;
5531 args
->out
[0] = values
[0];
5532 args
->out
[3] = values
[3];
5535 case V_028714_SPI_SHADER_FP16_ABGR
:
5538 for (unsigned chan
= 0; chan
< 2; chan
++) {
5539 LLVMValueRef pack_args
[2] = {
5541 values
[2 * chan
+ 1]
5543 LLVMValueRef packed
;
5545 packed
= ac_build_cvt_pkrtz_f16(&ctx
->ac
, pack_args
);
5546 args
->out
[chan
] = packed
;
5550 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5551 for (unsigned chan
= 0; chan
< 4; chan
++) {
5552 val
[chan
] = ac_build_clamp(&ctx
->ac
, values
[chan
]);
5553 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5554 LLVMConstReal(ctx
->ac
.f32
, 65535), "");
5555 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5556 LLVMConstReal(ctx
->ac
.f32
, 0.5), "");
5557 val
[chan
] = LLVMBuildFPToUI(ctx
->builder
, val
[chan
],
5562 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5563 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5566 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5567 for (unsigned chan
= 0; chan
< 4; chan
++) {
5568 val
[chan
] = emit_float_saturate(&ctx
->ac
, values
[chan
], -1, 1);
5569 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5570 LLVMConstReal(ctx
->ac
.f32
, 32767), "");
5572 /* If positive, add 0.5, else add -0.5. */
5573 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5574 LLVMBuildSelect(ctx
->builder
,
5575 LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
,
5576 val
[chan
], ctx
->ac
.f32_0
, ""),
5577 LLVMConstReal(ctx
->ac
.f32
, 0.5),
5578 LLVMConstReal(ctx
->ac
.f32
, -0.5), ""), "");
5579 val
[chan
] = LLVMBuildFPToSI(ctx
->builder
, val
[chan
], ctx
->ac
.i32
, "");
5583 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5584 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5587 case V_028714_SPI_SHADER_UINT16_ABGR
: {
5588 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5589 is_int8
? 255 : is_int10
? 1023 : 65535, 0);
5590 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: LLVMConstInt(ctx
->ac
.i32
, 3, 0);
5592 for (unsigned chan
= 0; chan
< 4; chan
++) {
5593 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5594 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntULT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5598 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5599 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5603 case V_028714_SPI_SHADER_SINT16_ABGR
: {
5604 LLVMValueRef max_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5605 is_int8
? 127 : is_int10
? 511 : 32767, 0);
5606 LLVMValueRef min_rgb
= LLVMConstInt(ctx
->ac
.i32
,
5607 is_int8
? -128 : is_int10
? -512 : -32768, 0);
5608 LLVMValueRef max_alpha
= !is_int10
? max_rgb
: ctx
->ac
.i32_1
;
5609 LLVMValueRef min_alpha
= !is_int10
? min_rgb
: LLVMConstInt(ctx
->ac
.i32
, -2, 0);
5612 for (unsigned chan
= 0; chan
< 4; chan
++) {
5613 val
[chan
] = ac_to_integer(&ctx
->ac
, values
[chan
]);
5614 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, val
[chan
], chan
== 3 ? max_alpha
: max_rgb
);
5615 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, val
[chan
], chan
== 3 ? min_alpha
: min_rgb
);
5619 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5620 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5625 case V_028714_SPI_SHADER_32_ABGR
:
5626 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5630 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5632 for (unsigned i
= 0; i
< 4; ++i
)
5633 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5637 handle_vs_outputs_post(struct nir_to_llvm_context
*ctx
,
5638 bool export_prim_id
,
5639 struct ac_vs_output_info
*outinfo
)
5641 uint32_t param_count
= 0;
5643 unsigned pos_idx
, num_pos_exports
= 0;
5644 struct ac_export_args args
, pos_args
[4] = {};
5645 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
5648 if (ctx
->options
->key
.has_multiview_view_index
) {
5649 LLVMValueRef
* tmp_out
= &ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5651 for(unsigned i
= 0; i
< 4; ++i
)
5652 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
5653 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5656 LLVMBuildStore(ctx
->builder
, ac_to_float(&ctx
->ac
, ctx
->view_index
), *tmp_out
);
5657 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
5660 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
5661 sizeof(outinfo
->vs_output_param_offset
));
5663 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
5664 LLVMValueRef slots
[8];
5667 if (outinfo
->cull_dist_mask
)
5668 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
5670 i
= VARYING_SLOT_CLIP_DIST0
;
5671 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
5672 slots
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5673 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5675 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
5676 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
5678 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
5679 target
= V_008DFC_SQ_EXP_POS
+ 3;
5680 si_llvm_init_export_args(ctx
, &slots
[4], target
, &args
);
5681 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5682 &args
, sizeof(args
));
5685 target
= V_008DFC_SQ_EXP_POS
+ 2;
5686 si_llvm_init_export_args(ctx
, &slots
[0], target
, &args
);
5687 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5688 &args
, sizeof(args
));
5692 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
5693 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
5694 for (unsigned j
= 0; j
< 4; j
++)
5695 pos_values
[j
] = LLVMBuildLoad(ctx
->builder
,
5696 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_POS
, j
)], "");
5698 si_llvm_init_export_args(ctx
, pos_values
, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
5700 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
5701 outinfo
->writes_pointsize
= true;
5702 psize_value
= LLVMBuildLoad(ctx
->builder
,
5703 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ
, 0)], "");
5706 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
5707 outinfo
->writes_layer
= true;
5708 layer_value
= LLVMBuildLoad(ctx
->builder
,
5709 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)], "");
5712 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
5713 outinfo
->writes_viewport_index
= true;
5714 viewport_index_value
= LLVMBuildLoad(ctx
->builder
,
5715 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT
, 0)], "");
5718 if (outinfo
->writes_pointsize
||
5719 outinfo
->writes_layer
||
5720 outinfo
->writes_viewport_index
) {
5721 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
5722 (outinfo
->writes_layer
== true ? 4 : 0));
5723 pos_args
[1].valid_mask
= 0;
5724 pos_args
[1].done
= 0;
5725 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
5726 pos_args
[1].compr
= 0;
5727 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
5728 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
5729 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
5730 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
5732 if (outinfo
->writes_pointsize
== true)
5733 pos_args
[1].out
[0] = psize_value
;
5734 if (outinfo
->writes_layer
== true)
5735 pos_args
[1].out
[2] = layer_value
;
5736 if (outinfo
->writes_viewport_index
== true) {
5737 if (ctx
->options
->chip_class
>= GFX9
) {
5738 /* GFX9 has the layer in out.z[10:0] and the viewport
5739 * index in out.z[19:16].
5741 LLVMValueRef v
= viewport_index_value
;
5742 v
= ac_to_integer(&ctx
->ac
, v
);
5743 v
= LLVMBuildShl(ctx
->builder
, v
,
5744 LLVMConstInt(ctx
->ac
.i32
, 16, false),
5746 v
= LLVMBuildOr(ctx
->builder
, v
,
5747 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
5749 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
5750 pos_args
[1].enabled_channels
|= 1 << 2;
5752 pos_args
[1].out
[3] = viewport_index_value
;
5753 pos_args
[1].enabled_channels
|= 1 << 3;
5757 for (i
= 0; i
< 4; i
++) {
5758 if (pos_args
[i
].out
[0])
5763 for (i
= 0; i
< 4; i
++) {
5764 if (!pos_args
[i
].out
[0])
5767 /* Specify the target we are exporting */
5768 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
5769 if (pos_idx
== num_pos_exports
)
5770 pos_args
[i
].done
= 1;
5771 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
5774 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5775 LLVMValueRef values
[4];
5776 if (!(ctx
->output_mask
& (1ull << i
)))
5779 for (unsigned j
= 0; j
< 4; j
++)
5780 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5781 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5783 if (i
== VARYING_SLOT_LAYER
) {
5784 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5785 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
;
5787 } else if (i
== VARYING_SLOT_PRIMITIVE_ID
) {
5788 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5789 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
5791 } else if (i
>= VARYING_SLOT_VAR0
) {
5792 outinfo
->export_mask
|= 1u << (i
- VARYING_SLOT_VAR0
);
5793 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5794 outinfo
->vs_output_param_offset
[i
] = param_count
;
5799 si_llvm_init_export_args(ctx
, values
, target
, &args
);
5801 if (target
>= V_008DFC_SQ_EXP_POS
&&
5802 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
5803 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5804 &args
, sizeof(args
));
5806 ac_build_export(&ctx
->ac
, &args
);
5810 if (export_prim_id
) {
5811 LLVMValueRef values
[4];
5812 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5813 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
5816 values
[0] = ctx
->vs_prim_id
;
5817 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
5818 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5819 for (unsigned j
= 1; j
< 4; j
++)
5820 values
[j
] = ctx
->ac
.f32_0
;
5821 si_llvm_init_export_args(ctx
, values
, target
, &args
);
5822 ac_build_export(&ctx
->ac
, &args
);
5823 outinfo
->export_prim_id
= true;
5826 outinfo
->pos_exports
= num_pos_exports
;
5827 outinfo
->param_exports
= param_count
;
5831 handle_es_outputs_post(struct nir_to_llvm_context
*ctx
,
5832 struct ac_es_output_info
*outinfo
)
5835 uint64_t max_output_written
= 0;
5836 LLVMValueRef lds_base
= NULL
;
5838 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5842 if (!(ctx
->output_mask
& (1ull << i
)))
5845 if (i
== VARYING_SLOT_CLIP_DIST0
)
5846 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5848 param_index
= shader_io_get_unique_index(i
);
5850 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
5853 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
5855 if (ctx
->ac
.chip_class
>= GFX9
) {
5856 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
5857 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
5858 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
5859 LLVMConstInt(ctx
->ac
.i32
, 24, false),
5860 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
5861 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
5862 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
5863 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
5864 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
5865 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
5868 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5869 LLVMValueRef dw_addr
;
5870 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
5874 if (!(ctx
->output_mask
& (1ull << i
)))
5877 if (i
== VARYING_SLOT_CLIP_DIST0
)
5878 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5880 param_index
= shader_io_get_unique_index(i
);
5883 dw_addr
= LLVMBuildAdd(ctx
->builder
, lds_base
,
5884 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
5887 for (j
= 0; j
< length
; j
++) {
5888 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], "");
5889 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->ac
.i32
, "");
5891 if (ctx
->ac
.chip_class
>= GFX9
) {
5892 ac_lds_store(&ctx
->ac
, dw_addr
,
5893 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
5894 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
5896 ac_build_buffer_store_dword(&ctx
->ac
,
5899 NULL
, ctx
->es2gs_offset
,
5900 (4 * param_index
+ j
) * 4,
5908 handle_ls_outputs_post(struct nir_to_llvm_context
*ctx
)
5910 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
5911 LLVMValueRef vertex_dw_stride
= unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
5912 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->builder
, vertex_id
,
5913 vertex_dw_stride
, "");
5915 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5916 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
5919 if (!(ctx
->output_mask
& (1ull << i
)))
5922 if (i
== VARYING_SLOT_CLIP_DIST0
)
5923 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5924 int param
= shader_io_get_unique_index(i
);
5925 mark_tess_output(ctx
, false, param
);
5927 mark_tess_output(ctx
, false, param
+ 1);
5928 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->builder
, base_dw_addr
,
5929 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
5931 for (unsigned j
= 0; j
< length
; j
++) {
5932 ac_lds_store(&ctx
->ac
, dw_addr
,
5933 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
5934 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->ac
.i32_1
, "");
5939 struct ac_build_if_state
5941 struct nir_to_llvm_context
*ctx
;
5942 LLVMValueRef condition
;
5943 LLVMBasicBlockRef entry_block
;
5944 LLVMBasicBlockRef true_block
;
5945 LLVMBasicBlockRef false_block
;
5946 LLVMBasicBlockRef merge_block
;
5949 static LLVMBasicBlockRef
5950 ac_build_insert_new_block(struct nir_to_llvm_context
*ctx
, const char *name
)
5952 LLVMBasicBlockRef current_block
;
5953 LLVMBasicBlockRef next_block
;
5954 LLVMBasicBlockRef new_block
;
5956 /* get current basic block */
5957 current_block
= LLVMGetInsertBlock(ctx
->builder
);
5959 /* chqeck if there's another block after this one */
5960 next_block
= LLVMGetNextBasicBlock(current_block
);
5962 /* insert the new block before the next block */
5963 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
5966 /* append new block after current block */
5967 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5968 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
5974 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
5975 struct nir_to_llvm_context
*ctx
,
5976 LLVMValueRef condition
)
5978 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->builder
);
5980 memset(ifthen
, 0, sizeof *ifthen
);
5982 ifthen
->condition
= condition
;
5983 ifthen
->entry_block
= block
;
5985 /* create endif/merge basic block for the phi functions */
5986 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
5988 /* create/insert true_block before merge_block */
5989 ifthen
->true_block
=
5990 LLVMInsertBasicBlockInContext(ctx
->context
,
5991 ifthen
->merge_block
,
5994 /* successive code goes into the true block */
5995 LLVMPositionBuilderAtEnd(ctx
->builder
, ifthen
->true_block
);
5999 * End a conditional.
6002 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6004 LLVMBuilderRef builder
= ifthen
->ctx
->builder
;
6006 /* Insert branch to the merge block from current block */
6007 LLVMBuildBr(builder
, ifthen
->merge_block
);
6010 * Now patch in the various branch instructions.
6013 /* Insert the conditional branch instruction at the end of entry_block */
6014 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6015 if (ifthen
->false_block
) {
6016 /* we have an else clause */
6017 LLVMBuildCondBr(builder
, ifthen
->condition
,
6018 ifthen
->true_block
, ifthen
->false_block
);
6021 /* no else clause */
6022 LLVMBuildCondBr(builder
, ifthen
->condition
,
6023 ifthen
->true_block
, ifthen
->merge_block
);
6026 /* Resume building code at end of the ifthen->merge_block */
6027 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6031 write_tess_factors(struct nir_to_llvm_context
*ctx
)
6033 unsigned stride
, outer_comps
, inner_comps
;
6034 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6035 LLVMValueRef invocation_id
= unpack_param(&ctx
->ac
, ctx
->tcs_rel_ids
, 8, 5);
6036 LLVMValueRef rel_patch_id
= unpack_param(&ctx
->ac
, ctx
->tcs_rel_ids
, 0, 8);
6037 unsigned tess_inner_index
, tess_outer_index
;
6038 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
6039 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6043 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6063 ac_nir_build_if(&if_ctx
, ctx
,
6064 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6065 invocation_id
, ctx
->ac
.i32_0
, ""));
6067 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6068 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6070 mark_tess_output(ctx
, true, tess_inner_index
);
6071 mark_tess_output(ctx
, true, tess_outer_index
);
6072 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6073 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6074 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
6075 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_base
,
6076 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
6078 for (i
= 0; i
< 4; i
++) {
6079 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6080 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6084 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6085 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
6086 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6087 LLVMConstInt(ctx
->ac
.i32
, 1, false), "");
6088 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
6090 for (i
= 0; i
< outer_comps
; i
++) {
6092 ac_lds_load(&ctx
->ac
, lds_outer
);
6093 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
6094 LLVMConstInt(ctx
->ac
.i32
, 1, false), "");
6096 for (i
= 0; i
< inner_comps
; i
++) {
6097 inner
[i
] = out
[outer_comps
+i
] =
6098 ac_lds_load(&ctx
->ac
, lds_inner
);
6099 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_inner
,
6100 LLVMConstInt(ctx
->ac
.i32
, 1, false), "");
6104 /* Convert the outputs to vectors for stores. */
6105 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6109 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6112 buffer
= ctx
->hs_ring_tess_factor
;
6113 tf_base
= ctx
->tess_factor_offset
;
6114 byteoffset
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
6115 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
6116 unsigned tf_offset
= 0;
6118 if (ctx
->options
->chip_class
<= VI
) {
6119 ac_nir_build_if(&inner_if_ctx
, ctx
,
6120 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
6121 rel_patch_id
, ctx
->ac
.i32_0
, ""));
6123 /* Store the dynamic HS control word. */
6124 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6125 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
6126 1, ctx
->ac
.i32_0
, tf_base
,
6127 0, 1, 0, true, false);
6130 ac_nir_build_endif(&inner_if_ctx
);
6133 /* Store the tessellation factors. */
6134 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6135 MIN2(stride
, 4), byteoffset
, tf_base
,
6136 tf_offset
, 1, 0, true, false);
6138 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6139 stride
- 4, byteoffset
, tf_base
,
6140 16 + tf_offset
, 1, 0, true, false);
6142 //store to offchip for TES to read - only if TES reads them
6143 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6144 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6145 LLVMValueRef tf_inner_offset
;
6146 unsigned param_outer
, param_inner
;
6148 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6149 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6150 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
6152 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6153 util_next_power_of_two(outer_comps
));
6155 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6156 outer_comps
, tf_outer_offset
,
6157 ctx
->oc_lds
, 0, 1, 0, true, false);
6159 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6160 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6161 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
6163 inner_vec
= inner_comps
== 1 ? inner
[0] :
6164 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6165 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6166 inner_comps
, tf_inner_offset
,
6167 ctx
->oc_lds
, 0, 1, 0, true, false);
6170 ac_nir_build_endif(&if_ctx
);
6174 handle_tcs_outputs_post(struct nir_to_llvm_context
*ctx
)
6176 write_tess_factors(ctx
);
6180 si_export_mrt_color(struct nir_to_llvm_context
*ctx
,
6181 LLVMValueRef
*color
, unsigned param
, bool is_last
,
6182 struct ac_export_args
*args
)
6185 si_llvm_init_export_args(ctx
, color
, param
,
6189 args
->valid_mask
= 1; /* whether the EXEC mask is valid */
6190 args
->done
= 1; /* DONE bit */
6191 } else if (!args
->enabled_channels
)
6192 return false; /* unnecessary NULL export */
6198 si_export_mrt_z(struct nir_to_llvm_context
*ctx
,
6199 LLVMValueRef depth
, LLVMValueRef stencil
,
6200 LLVMValueRef samplemask
)
6202 struct ac_export_args args
;
6204 args
.enabled_channels
= 0;
6205 args
.valid_mask
= 1;
6207 args
.target
= V_008DFC_SQ_EXP_MRTZ
;
6210 args
.out
[0] = LLVMGetUndef(ctx
->ac
.f32
); /* R, depth */
6211 args
.out
[1] = LLVMGetUndef(ctx
->ac
.f32
); /* G, stencil test val[0:7], stencil op val[8:15] */
6212 args
.out
[2] = LLVMGetUndef(ctx
->ac
.f32
); /* B, sample mask */
6213 args
.out
[3] = LLVMGetUndef(ctx
->ac
.f32
); /* A, alpha to mask */
6215 unsigned format
= ac_get_spi_shader_z_format(depth
!= NULL
,
6217 samplemask
!= NULL
);
6219 if (format
== V_028710_SPI_SHADER_UINT16_ABGR
) {
6221 args
.compr
= 1; /* COMPR flag */
6224 /* Stencil should be in X[23:16]. */
6225 stencil
= ac_to_integer(&ctx
->ac
, stencil
);
6226 stencil
= LLVMBuildShl(ctx
->builder
, stencil
,
6227 LLVMConstInt(ctx
->ac
.i32
, 16, 0), "");
6228 args
.out
[0] = ac_to_float(&ctx
->ac
, stencil
);
6229 args
.enabled_channels
|= 0x3;
6232 /* SampleMask should be in Y[15:0]. */
6233 args
.out
[1] = samplemask
;
6234 args
.enabled_channels
|= 0xc;
6238 args
.out
[0] = depth
;
6239 args
.enabled_channels
|= 0x1;
6243 args
.out
[1] = stencil
;
6244 args
.enabled_channels
|= 0x2;
6248 args
.out
[2] = samplemask
;
6249 args
.enabled_channels
|= 0x4;
6253 /* SI (except OLAND and HAINAN) has a bug that it only looks
6254 * at the X writemask component. */
6255 if (ctx
->options
->chip_class
== SI
&&
6256 ctx
->options
->family
!= CHIP_OLAND
&&
6257 ctx
->options
->family
!= CHIP_HAINAN
)
6258 args
.enabled_channels
|= 0x1;
6260 ac_build_export(&ctx
->ac
, &args
);
6264 handle_fs_outputs_post(struct nir_to_llvm_context
*ctx
)
6267 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6268 struct ac_export_args color_args
[8];
6270 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6271 LLVMValueRef values
[4];
6273 if (!(ctx
->output_mask
& (1ull << i
)))
6276 if (i
== FRAG_RESULT_DEPTH
) {
6277 ctx
->shader_info
->fs
.writes_z
= true;
6278 depth
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6279 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6280 } else if (i
== FRAG_RESULT_STENCIL
) {
6281 ctx
->shader_info
->fs
.writes_stencil
= true;
6282 stencil
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6283 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6284 } else if (i
== FRAG_RESULT_SAMPLE_MASK
) {
6285 ctx
->shader_info
->fs
.writes_sample_mask
= true;
6286 samplemask
= ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6287 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
6290 for (unsigned j
= 0; j
< 4; j
++)
6291 values
[j
] = ac_to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
6292 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
6294 if (!ctx
->shader_info
->fs
.writes_z
&& !ctx
->shader_info
->fs
.writes_stencil
&& !ctx
->shader_info
->fs
.writes_sample_mask
)
6295 last
= ctx
->output_mask
<= ((1ull << (i
+ 1)) - 1);
6297 bool ret
= si_export_mrt_color(ctx
, values
, V_008DFC_SQ_EXP_MRT
+ (i
- FRAG_RESULT_DATA0
), last
, &color_args
[index
]);
6303 for (unsigned i
= 0; i
< index
; i
++)
6304 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6305 if (depth
|| stencil
|| samplemask
)
6306 si_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6308 si_export_mrt_color(ctx
, NULL
, V_008DFC_SQ_EXP_NULL
, true, &color_args
[0]);
6309 ac_build_export(&ctx
->ac
, &color_args
[0]);
6312 ctx
->shader_info
->fs
.output_mask
= index
? ((1ull << index
) - 1) : 0;
6316 emit_gs_epilogue(struct nir_to_llvm_context
*ctx
)
6318 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6322 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6323 LLVMValueRef
*addrs
)
6325 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
6327 switch (ctx
->stage
) {
6328 case MESA_SHADER_VERTEX
:
6329 if (ctx
->options
->key
.vs
.as_ls
)
6330 handle_ls_outputs_post(ctx
);
6331 else if (ctx
->options
->key
.vs
.as_es
)
6332 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6334 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6335 &ctx
->shader_info
->vs
.outinfo
);
6337 case MESA_SHADER_FRAGMENT
:
6338 handle_fs_outputs_post(ctx
);
6340 case MESA_SHADER_GEOMETRY
:
6341 emit_gs_epilogue(ctx
);
6343 case MESA_SHADER_TESS_CTRL
:
6344 handle_tcs_outputs_post(ctx
);
6346 case MESA_SHADER_TESS_EVAL
:
6347 if (ctx
->options
->key
.tes
.as_es
)
6348 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6350 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6351 &ctx
->shader_info
->tes
.outinfo
);
6358 static void ac_llvm_finalize_module(struct nir_to_llvm_context
* ctx
)
6360 LLVMPassManagerRef passmgr
;
6361 /* Create the pass manager */
6362 passmgr
= LLVMCreateFunctionPassManagerForModule(
6365 /* This pass should eliminate all the load and store instructions */
6366 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6368 /* Add some optimization passes */
6369 LLVMAddScalarReplAggregatesPass(passmgr
);
6370 LLVMAddLICMPass(passmgr
);
6371 LLVMAddAggressiveDCEPass(passmgr
);
6372 LLVMAddCFGSimplificationPass(passmgr
);
6373 LLVMAddInstructionCombiningPass(passmgr
);
6376 LLVMInitializeFunctionPassManager(passmgr
);
6377 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6378 LLVMFinalizeFunctionPassManager(passmgr
);
6380 LLVMDisposeBuilder(ctx
->builder
);
6381 LLVMDisposePassManager(passmgr
);
6385 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context
*ctx
)
6387 struct ac_vs_output_info
*outinfo
;
6389 switch (ctx
->stage
) {
6390 case MESA_SHADER_FRAGMENT
:
6391 case MESA_SHADER_COMPUTE
:
6392 case MESA_SHADER_TESS_CTRL
:
6393 case MESA_SHADER_GEOMETRY
:
6395 case MESA_SHADER_VERTEX
:
6396 if (ctx
->options
->key
.vs
.as_ls
||
6397 ctx
->options
->key
.vs
.as_es
)
6399 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6401 case MESA_SHADER_TESS_EVAL
:
6402 if (ctx
->options
->key
.vs
.as_es
)
6404 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6407 unreachable("Unhandled shader type");
6410 ac_optimize_vs_outputs(&ctx
->ac
,
6412 outinfo
->vs_output_param_offset
,
6414 &outinfo
->param_exports
);
6418 ac_setup_rings(struct nir_to_llvm_context
*ctx
)
6420 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6421 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6422 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
6425 if (ctx
->is_gs_copy_shader
) {
6426 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
6428 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6430 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
6431 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
6433 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
6435 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
6436 tmp
= LLVMBuildExtractElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
6437 tmp
= LLVMBuildOr(ctx
->builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6438 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
6441 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6442 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6443 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
6444 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
6449 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6450 const struct nir_shader
*nir
)
6452 switch (nir
->info
.stage
) {
6453 case MESA_SHADER_TESS_CTRL
:
6454 return chip_class
>= CIK
? 128 : 64;
6455 case MESA_SHADER_GEOMETRY
:
6456 return chip_class
>= GFX9
? 128 : 64;
6457 case MESA_SHADER_COMPUTE
:
6463 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6464 nir
->info
.cs
.local_size
[1] *
6465 nir
->info
.cs
.local_size
[2];
6466 return max_workgroup_size
;
6469 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6470 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6472 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6473 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6474 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6475 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6476 LLVMConstInt(ctx
->ac
.i32
, 0, false), "");
6477 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6478 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6479 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->tcs_rel_ids
, ctx
->rel_auto_id
, "");
6480 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6483 static void prepare_gs_input_vgprs(struct nir_to_llvm_context
*ctx
)
6485 for(int i
= 5; i
>= 0; --i
) {
6486 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6487 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6488 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6491 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6492 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6493 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6496 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6497 struct nir_shader
*nir
, struct nir_to_llvm_context
*nctx
)
6499 struct ac_nir_context ctx
= {};
6500 struct nir_function
*func
;
6509 ctx
.stage
= nir
->info
.stage
;
6511 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6513 nir_foreach_variable(variable
, &nir
->outputs
)
6514 handle_shader_output_decl(&ctx
, nir
, variable
);
6516 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6517 _mesa_key_pointer_equal
);
6518 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6519 _mesa_key_pointer_equal
);
6520 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6521 _mesa_key_pointer_equal
);
6523 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6525 setup_locals(&ctx
, func
);
6527 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6528 setup_shared(&ctx
, nir
);
6530 visit_cf_list(&ctx
, &func
->impl
->body
);
6531 phi_post_pass(&ctx
);
6533 ctx
.abi
->emit_outputs(ctx
.abi
, RADEON_LLVM_MAX_OUTPUTS
,
6537 ralloc_free(ctx
.defs
);
6538 ralloc_free(ctx
.phis
);
6539 ralloc_free(ctx
.vars
);
6546 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6547 struct nir_shader
*const *shaders
,
6549 struct ac_shader_variant_info
*shader_info
,
6550 const struct ac_nir_compiler_options
*options
)
6552 struct nir_to_llvm_context ctx
= {0};
6554 ctx
.options
= options
;
6555 ctx
.shader_info
= shader_info
;
6556 ctx
.context
= LLVMContextCreate();
6557 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6559 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
);
6560 ctx
.ac
.module
= ctx
.module
;
6561 LLVMSetTarget(ctx
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6563 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6564 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6565 LLVMSetDataLayout(ctx
.module
, data_layout_str
);
6566 LLVMDisposeTargetData(data_layout
);
6567 LLVMDisposeMessage(data_layout_str
);
6569 ctx
.builder
= LLVMCreateBuilderInContext(ctx
.context
);
6570 ctx
.ac
.builder
= ctx
.builder
;
6572 memset(shader_info
, 0, sizeof(*shader_info
));
6574 for(int i
= 0; i
< shader_count
; ++i
)
6575 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6577 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6578 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6579 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6580 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6582 ctx
.max_workgroup_size
= 0;
6583 for (int i
= 0; i
< shader_count
; ++i
) {
6584 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6585 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6589 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6590 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6592 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6593 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6594 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
6595 ctx
.abi
.load_ubo
= radv_load_ubo
;
6596 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6597 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6598 ctx
.abi
.clamp_shadow_reference
= false;
6600 if (shader_count
>= 2)
6601 ac_init_exec_full_mask(&ctx
.ac
);
6603 if (ctx
.ac
.chip_class
== GFX9
&&
6604 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6605 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6607 for(int i
= 0; i
< shader_count
; ++i
) {
6608 ctx
.stage
= shaders
[i
]->info
.stage
;
6609 ctx
.output_mask
= 0;
6610 ctx
.tess_outputs_written
= 0;
6611 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6612 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6614 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6615 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
6616 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6617 ctx
.abi
.load_inputs
= load_gs_input
;
6618 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6619 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
6620 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
6621 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6622 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6623 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6624 if (shader_info
->info
.vs
.needs_instance_id
) {
6625 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6626 MAX2(3, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6628 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6629 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6635 ac_setup_rings(&ctx
);
6637 LLVMBasicBlockRef merge_block
;
6638 if (shader_count
>= 2) {
6639 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6640 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6641 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6643 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6644 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6645 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6646 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6647 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6648 thread_id
, count
, "");
6649 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6651 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6654 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6655 handle_fs_inputs(&ctx
, shaders
[i
]);
6656 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
6657 handle_vs_inputs(&ctx
, shaders
[i
]);
6658 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
6659 prepare_gs_input_vgprs(&ctx
);
6661 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
6662 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
6664 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
], &ctx
);
6666 if (shader_count
>= 2) {
6667 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
6668 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
6671 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6672 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
6673 shaders
[i
]->info
.cull_distance_array_size
> 4;
6674 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6675 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6676 shaders
[i
]->info
.gs
.vertices_out
;
6677 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6678 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6679 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6680 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6681 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6685 LLVMBuildRetVoid(ctx
.builder
);
6687 ac_llvm_finalize_module(&ctx
);
6689 if (shader_count
== 1)
6690 ac_nir_eliminate_const_vs_outputs(&ctx
);
6695 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
6697 unsigned *retval
= (unsigned *)context
;
6698 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
6699 char *description
= LLVMGetDiagInfoDescription(di
);
6701 if (severity
== LLVMDSError
) {
6703 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
6707 LLVMDisposeMessage(description
);
6710 static unsigned ac_llvm_compile(LLVMModuleRef M
,
6711 struct ac_shader_binary
*binary
,
6712 LLVMTargetMachineRef tm
)
6714 unsigned retval
= 0;
6716 LLVMContextRef llvm_ctx
;
6717 LLVMMemoryBufferRef out_buffer
;
6718 unsigned buffer_size
;
6719 const char *buffer_data
;
6722 /* Setup Diagnostic Handler*/
6723 llvm_ctx
= LLVMGetModuleContext(M
);
6725 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
6729 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
6732 /* Process Errors/Warnings */
6734 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
6740 /* Extract Shader Code*/
6741 buffer_size
= LLVMGetBufferSize(out_buffer
);
6742 buffer_data
= LLVMGetBufferStart(out_buffer
);
6744 ac_elf_read(buffer_data
, buffer_size
, binary
);
6747 LLVMDisposeMemoryBuffer(out_buffer
);
6753 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
6754 LLVMModuleRef llvm_module
,
6755 struct ac_shader_binary
*binary
,
6756 struct ac_shader_config
*config
,
6757 struct ac_shader_variant_info
*shader_info
,
6758 gl_shader_stage stage
,
6759 bool dump_shader
, bool supports_spill
)
6762 ac_dump_module(llvm_module
);
6764 memset(binary
, 0, sizeof(*binary
));
6765 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
6767 fprintf(stderr
, "compile failed\n");
6771 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
6773 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
6775 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
6776 LLVMDisposeModule(llvm_module
);
6777 LLVMContextDispose(ctx
);
6779 if (stage
== MESA_SHADER_FRAGMENT
) {
6780 shader_info
->num_input_vgprs
= 0;
6781 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
6782 shader_info
->num_input_vgprs
+= 2;
6783 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
6784 shader_info
->num_input_vgprs
+= 2;
6785 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
6786 shader_info
->num_input_vgprs
+= 2;
6787 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
6788 shader_info
->num_input_vgprs
+= 3;
6789 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
6790 shader_info
->num_input_vgprs
+= 2;
6791 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
6792 shader_info
->num_input_vgprs
+= 2;
6793 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
6794 shader_info
->num_input_vgprs
+= 2;
6795 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
6796 shader_info
->num_input_vgprs
+= 1;
6797 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
6798 shader_info
->num_input_vgprs
+= 1;
6799 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
6800 shader_info
->num_input_vgprs
+= 1;
6801 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
6802 shader_info
->num_input_vgprs
+= 1;
6803 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
6804 shader_info
->num_input_vgprs
+= 1;
6805 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
6806 shader_info
->num_input_vgprs
+= 1;
6807 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
6808 shader_info
->num_input_vgprs
+= 1;
6809 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
6810 shader_info
->num_input_vgprs
+= 1;
6811 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
6812 shader_info
->num_input_vgprs
+= 1;
6814 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
6816 /* +3 for scratch wave offset and VCC */
6817 config
->num_sgprs
= MAX2(config
->num_sgprs
,
6818 shader_info
->num_input_sgprs
+ 3);
6822 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
6824 switch (nir
->info
.stage
) {
6825 case MESA_SHADER_COMPUTE
:
6826 for (int i
= 0; i
< 3; ++i
)
6827 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
6829 case MESA_SHADER_FRAGMENT
:
6830 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
6832 case MESA_SHADER_GEOMETRY
:
6833 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
6834 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
6835 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
6836 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
6838 case MESA_SHADER_TESS_EVAL
:
6839 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
6840 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
6841 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
6842 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
6843 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
6845 case MESA_SHADER_TESS_CTRL
:
6846 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
6848 case MESA_SHADER_VERTEX
:
6849 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
6850 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
6851 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6852 if (options
->key
.vs
.as_ls
)
6853 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
6860 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
6861 struct ac_shader_binary
*binary
,
6862 struct ac_shader_config
*config
,
6863 struct ac_shader_variant_info
*shader_info
,
6864 struct nir_shader
*const *nir
,
6866 const struct ac_nir_compiler_options
*options
,
6870 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
6873 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
6874 for (int i
= 0; i
< nir_count
; ++i
)
6875 ac_fill_shader_info(shader_info
, nir
[i
], options
);
6879 ac_gs_copy_shader_emit(struct nir_to_llvm_context
*ctx
)
6881 LLVMValueRef args
[9];
6882 args
[0] = ctx
->gsvs_ring
;
6883 args
[1] = LLVMBuildMul(ctx
->builder
, ctx
->abi
.vertex_id
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
6884 args
[3] = ctx
->ac
.i32_0
;
6885 args
[4] = ctx
->ac
.i32_1
; /* OFFEN */
6886 args
[5] = ctx
->ac
.i32_0
; /* IDXEN */
6887 args
[6] = ctx
->ac
.i32_1
; /* GLC */
6888 args
[7] = ctx
->ac
.i32_1
; /* SLC */
6889 args
[8] = ctx
->ac
.i32_0
; /* TFE */
6893 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6897 if (!(ctx
->output_mask
& (1ull << i
)))
6900 if (i
== VARYING_SLOT_CLIP_DIST0
) {
6901 /* unpack clip and cull from a single set of slots */
6902 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6907 for (unsigned j
= 0; j
< length
; j
++) {
6909 args
[2] = LLVMConstInt(ctx
->ac
.i32
,
6911 ctx
->gs_max_out_vertices
* 16 * 4, false);
6913 value
= ac_build_intrinsic(&ctx
->ac
,
6914 "llvm.SI.buffer.load.dword.i32.i32",
6915 ctx
->ac
.i32
, args
, 9,
6916 AC_FUNC_ATTR_READONLY
|
6917 AC_FUNC_ATTR_LEGACY
);
6919 LLVMBuildStore(ctx
->builder
,
6920 ac_to_float(&ctx
->ac
, value
), ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
6924 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
6927 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
6928 struct nir_shader
*geom_shader
,
6929 struct ac_shader_binary
*binary
,
6930 struct ac_shader_config
*config
,
6931 struct ac_shader_variant_info
*shader_info
,
6932 const struct ac_nir_compiler_options
*options
,
6935 struct nir_to_llvm_context ctx
= {0};
6936 ctx
.context
= LLVMContextCreate();
6937 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6938 ctx
.options
= options
;
6939 ctx
.shader_info
= shader_info
;
6941 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
);
6942 ctx
.ac
.module
= ctx
.module
;
6944 ctx
.is_gs_copy_shader
= true;
6945 LLVMSetTarget(ctx
.module
, "amdgcn--");
6947 ctx
.builder
= LLVMCreateBuilderInContext(ctx
.context
);
6948 ctx
.ac
.builder
= ctx
.builder
;
6949 ctx
.stage
= MESA_SHADER_VERTEX
;
6951 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
6953 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
6954 ac_setup_rings(&ctx
);
6956 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
6957 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
6959 struct ac_nir_context nir_ctx
= {};
6960 nir_ctx
.ac
= ctx
.ac
;
6961 nir_ctx
.abi
= &ctx
.abi
;
6963 nir_ctx
.nctx
= &ctx
;
6966 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
6967 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
6968 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
6971 ac_gs_copy_shader_emit(&ctx
);
6975 LLVMBuildRetVoid(ctx
.builder
);
6977 ac_llvm_finalize_module(&ctx
);
6979 ac_compile_llvm_module(tm
, ctx
.module
, binary
, config
, shader_info
,
6981 dump_shader
, options
->supports_spill
);