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ac/nir: move cast_ptr() to ac_llvm_build.c
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 uint32_t tcs_vertices_per_patch;
131 };
132
133 static inline struct radv_shader_context *
134 radv_shader_context_from_abi(struct ac_shader_abi *abi)
135 {
136 struct radv_shader_context *ctx = NULL;
137 return container_of(abi, ctx, abi);
138 }
139
140 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
141 const nir_deref_var *deref,
142 enum ac_descriptor_type desc_type,
143 const nir_tex_instr *instr,
144 bool image, bool write);
145
146 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
147 {
148 return (index * 4) + chan;
149 }
150
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
152 {
153 /* handle patch indices separate */
154 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
155 return 0;
156 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
157 return 1;
158 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
159 return 2 + (slot - VARYING_SLOT_PATCH0);
160
161 if (slot == VARYING_SLOT_POS)
162 return 0;
163 if (slot == VARYING_SLOT_PSIZ)
164 return 1;
165 if (slot == VARYING_SLOT_CLIP_DIST0)
166 return 2;
167 /* 3 is reserved for clip dist as well */
168 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
169 return 4 + (slot - VARYING_SLOT_VAR0);
170 unreachable("illegal slot in get unique index\n");
171 }
172
173 static void set_llvm_calling_convention(LLVMValueRef func,
174 gl_shader_stage stage)
175 {
176 enum radeon_llvm_calling_convention calling_conv;
177
178 switch (stage) {
179 case MESA_SHADER_VERTEX:
180 case MESA_SHADER_TESS_EVAL:
181 calling_conv = RADEON_LLVM_AMDGPU_VS;
182 break;
183 case MESA_SHADER_GEOMETRY:
184 calling_conv = RADEON_LLVM_AMDGPU_GS;
185 break;
186 case MESA_SHADER_TESS_CTRL:
187 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
188 break;
189 case MESA_SHADER_FRAGMENT:
190 calling_conv = RADEON_LLVM_AMDGPU_PS;
191 break;
192 case MESA_SHADER_COMPUTE:
193 calling_conv = RADEON_LLVM_AMDGPU_CS;
194 break;
195 default:
196 unreachable("Unhandle shader type");
197 }
198
199 LLVMSetFunctionCallConv(func, calling_conv);
200 }
201
202 #define MAX_ARGS 23
203 struct arg_info {
204 LLVMTypeRef types[MAX_ARGS];
205 LLVMValueRef *assign[MAX_ARGS];
206 unsigned array_params_mask;
207 uint8_t count;
208 uint8_t sgpr_count;
209 uint8_t num_sgprs_used;
210 uint8_t num_vgprs_used;
211 };
212
213 enum ac_arg_regfile {
214 ARG_SGPR,
215 ARG_VGPR,
216 };
217
218 static void
219 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
220 LLVMValueRef *param_ptr)
221 {
222 assert(info->count < MAX_ARGS);
223
224 info->assign[info->count] = param_ptr;
225 info->types[info->count] = type;
226 info->count++;
227
228 if (regfile == ARG_SGPR) {
229 info->num_sgprs_used += ac_get_type_size(type) / 4;
230 info->sgpr_count++;
231 } else {
232 assert(regfile == ARG_VGPR);
233 info->num_vgprs_used += ac_get_type_size(type) / 4;
234 }
235 }
236
237 static inline void
238 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
239 {
240 info->array_params_mask |= (1 << info->count);
241 add_arg(info, ARG_SGPR, type, param_ptr);
242 }
243
244 static void assign_arguments(LLVMValueRef main_function,
245 struct arg_info *info)
246 {
247 unsigned i;
248 for (i = 0; i < info->count; i++) {
249 if (info->assign[i])
250 *info->assign[i] = LLVMGetParam(main_function, i);
251 }
252 }
253
254 static LLVMValueRef
255 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
256 LLVMBuilderRef builder, LLVMTypeRef *return_types,
257 unsigned num_return_elems,
258 struct arg_info *args,
259 unsigned max_workgroup_size,
260 bool unsafe_math)
261 {
262 LLVMTypeRef main_function_type, ret_type;
263 LLVMBasicBlockRef main_function_body;
264
265 if (num_return_elems)
266 ret_type = LLVMStructTypeInContext(ctx, return_types,
267 num_return_elems, true);
268 else
269 ret_type = LLVMVoidTypeInContext(ctx);
270
271 /* Setup the function */
272 main_function_type =
273 LLVMFunctionType(ret_type, args->types, args->count, 0);
274 LLVMValueRef main_function =
275 LLVMAddFunction(module, "main", main_function_type);
276 main_function_body =
277 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
278 LLVMPositionBuilderAtEnd(builder, main_function_body);
279
280 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
281 for (unsigned i = 0; i < args->sgpr_count; ++i) {
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
283
284 if (args->array_params_mask & (1 << i)) {
285 LLVMValueRef P = LLVMGetParam(main_function, i);
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
287 ac_add_attr_dereferenceable(P, UINT64_MAX);
288 }
289 }
290
291 if (max_workgroup_size) {
292 ac_llvm_add_target_dep_function_attr(main_function,
293 "amdgpu-max-work-group-size",
294 max_workgroup_size);
295 }
296 if (unsafe_math) {
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "less-precise-fpmad",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "no-infs-fp-math",
303 "true");
304 LLVMAddTargetDependentFunctionAttr(main_function,
305 "no-nans-fp-math",
306 "true");
307 LLVMAddTargetDependentFunctionAttr(main_function,
308 "unsafe-fp-math",
309 "true");
310 LLVMAddTargetDependentFunctionAttr(main_function,
311 "no-signed-zeros-fp-math",
312 "true");
313 }
314 return main_function;
315 }
316
317 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
318 LLVMValueRef param, unsigned rshift,
319 unsigned bitwidth)
320 {
321 LLVMValueRef value = param;
322 if (rshift)
323 value = LLVMBuildLShr(ctx->builder, value,
324 LLVMConstInt(ctx->i32, rshift, false), "");
325
326 if (rshift + bitwidth < 32) {
327 unsigned mask = (1 << bitwidth) - 1;
328 value = LLVMBuildAnd(ctx->builder, value,
329 LLVMConstInt(ctx->i32, mask, false), "");
330 }
331 return value;
332 }
333
334 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
335 {
336 switch (ctx->stage) {
337 case MESA_SHADER_TESS_CTRL:
338 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
339 case MESA_SHADER_TESS_EVAL:
340 return ctx->tes_rel_patch_id;
341 break;
342 default:
343 unreachable("Illegal stage");
344 }
345 }
346
347 /* Tessellation shaders pass outputs to the next shader using LDS.
348 *
349 * LS outputs = TCS inputs
350 * TCS outputs = TES inputs
351 *
352 * The LDS layout is:
353 * - TCS inputs for patch 0
354 * - TCS inputs for patch 1
355 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
356 * - ...
357 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
358 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
359 * - TCS outputs for patch 1
360 * - Per-patch TCS outputs for patch 1
361 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
362 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
363 * - ...
364 *
365 * All three shaders VS(LS), TCS, TES share the same LDS space.
366 */
367 static LLVMValueRef
368 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
369 {
370 if (ctx->stage == MESA_SHADER_VERTEX)
371 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
372 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
373 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
374 else {
375 assert(0);
376 return NULL;
377 }
378 }
379
380 static LLVMValueRef
381 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
382 {
383 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
384 }
385
386 static LLVMValueRef
387 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
388 {
389 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
390 }
391
392 static LLVMValueRef
393 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
394 {
395 return LLVMBuildMul(ctx->ac.builder,
396 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
397 LLVMConstInt(ctx->ac.i32, 4, false), "");
398 }
399
400 static LLVMValueRef
401 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
402 {
403 return LLVMBuildMul(ctx->ac.builder,
404 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
405 LLVMConstInt(ctx->ac.i32, 4, false), "");
406 }
407
408 static LLVMValueRef
409 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
410 {
411 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
412 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
413
414 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
415 }
416
417 static LLVMValueRef
418 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
419 {
420 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
421 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
422 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
423
424 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
425 LLVMBuildMul(ctx->ac.builder, patch_stride,
426 rel_patch_id, ""),
427 "");
428 }
429
430 static LLVMValueRef
431 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
432 {
433 LLVMValueRef patch0_patch_data_offset =
434 get_tcs_out_patch0_patch_data_offset(ctx);
435 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
436 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
437
438 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
439 LLVMBuildMul(ctx->ac.builder, patch_stride,
440 rel_patch_id, ""),
441 "");
442 }
443
444 static void
445 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
446 uint32_t indirect_offset)
447 {
448 ud_info->sgpr_idx = *sgpr_idx;
449 ud_info->num_sgprs = num_sgprs;
450 ud_info->indirect = indirect_offset > 0;
451 ud_info->indirect_offset = indirect_offset;
452 *sgpr_idx += num_sgprs;
453 }
454
455 static void
456 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
457 uint8_t num_sgprs)
458 {
459 struct ac_userdata_info *ud_info =
460 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
461 assert(ud_info);
462
463 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
464 }
465
466 static void
467 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
468 uint32_t indirect_offset)
469 {
470 struct ac_userdata_info *ud_info =
471 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
472 assert(ud_info);
473
474 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
475 }
476
477 struct user_sgpr_info {
478 bool need_ring_offsets;
479 uint8_t sgpr_count;
480 bool indirect_all_descriptor_sets;
481 };
482
483 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
484 gl_shader_stage stage)
485 {
486 switch (stage) {
487 case MESA_SHADER_VERTEX:
488 if (ctx->shader_info->info.needs_multiview_view_index ||
489 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
490 return true;
491 break;
492 case MESA_SHADER_TESS_EVAL:
493 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
494 return true;
495 break;
496 case MESA_SHADER_GEOMETRY:
497 case MESA_SHADER_TESS_CTRL:
498 if (ctx->shader_info->info.needs_multiview_view_index)
499 return true;
500 break;
501 default:
502 break;
503 }
504 return false;
505 }
506
507 static uint8_t
508 count_vs_user_sgprs(struct radv_shader_context *ctx)
509 {
510 uint8_t count = 0;
511
512 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
513 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
514
515 return count;
516 }
517
518 static void allocate_user_sgprs(struct radv_shader_context *ctx,
519 gl_shader_stage stage,
520 bool has_previous_stage,
521 gl_shader_stage previous_stage,
522 bool needs_view_index,
523 struct user_sgpr_info *user_sgpr_info)
524 {
525 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
526
527 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
528 if (stage == MESA_SHADER_GEOMETRY ||
529 stage == MESA_SHADER_VERTEX ||
530 stage == MESA_SHADER_TESS_CTRL ||
531 stage == MESA_SHADER_TESS_EVAL ||
532 ctx->is_gs_copy_shader)
533 user_sgpr_info->need_ring_offsets = true;
534
535 if (stage == MESA_SHADER_FRAGMENT &&
536 ctx->shader_info->info.ps.needs_sample_positions)
537 user_sgpr_info->need_ring_offsets = true;
538
539 /* 2 user sgprs will nearly always be allocated for scratch/rings */
540 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
541 user_sgpr_info->sgpr_count += 2;
542 }
543
544 switch (stage) {
545 case MESA_SHADER_COMPUTE:
546 if (ctx->shader_info->info.cs.uses_grid_size)
547 user_sgpr_info->sgpr_count += 3;
548 break;
549 case MESA_SHADER_FRAGMENT:
550 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
551 break;
552 case MESA_SHADER_VERTEX:
553 if (!ctx->is_gs_copy_shader)
554 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
555 if (ctx->options->key.vs.as_ls)
556 user_sgpr_info->sgpr_count++;
557 break;
558 case MESA_SHADER_TESS_CTRL:
559 if (has_previous_stage) {
560 if (previous_stage == MESA_SHADER_VERTEX)
561 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
562 user_sgpr_info->sgpr_count++;
563 }
564 user_sgpr_info->sgpr_count += 4;
565 break;
566 case MESA_SHADER_TESS_EVAL:
567 user_sgpr_info->sgpr_count += 1;
568 break;
569 case MESA_SHADER_GEOMETRY:
570 if (has_previous_stage) {
571 if (previous_stage == MESA_SHADER_VERTEX) {
572 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
573 } else {
574 user_sgpr_info->sgpr_count++;
575 }
576 }
577 user_sgpr_info->sgpr_count += 2;
578 break;
579 default:
580 break;
581 }
582
583 if (needs_view_index)
584 user_sgpr_info->sgpr_count++;
585
586 if (ctx->shader_info->info.loads_push_constants)
587 user_sgpr_info->sgpr_count += 2;
588
589 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
590 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
591
592 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
593 user_sgpr_info->sgpr_count += 2;
594 user_sgpr_info->indirect_all_descriptor_sets = true;
595 } else {
596 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
597 }
598 }
599
600 static void
601 declare_global_input_sgprs(struct radv_shader_context *ctx,
602 gl_shader_stage stage,
603 bool has_previous_stage,
604 gl_shader_stage previous_stage,
605 const struct user_sgpr_info *user_sgpr_info,
606 struct arg_info *args,
607 LLVMValueRef *desc_sets)
608 {
609 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
610 unsigned num_sets = ctx->options->layout ?
611 ctx->options->layout->num_sets : 0;
612 unsigned stage_mask = 1 << stage;
613
614 if (has_previous_stage)
615 stage_mask |= 1 << previous_stage;
616
617 /* 1 for each descriptor set */
618 if (!user_sgpr_info->indirect_all_descriptor_sets) {
619 for (unsigned i = 0; i < num_sets; ++i) {
620 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
621 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
622 add_array_arg(args, type,
623 &ctx->descriptor_sets[i]);
624 }
625 }
626 } else {
627 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
628 }
629
630 if (ctx->shader_info->info.loads_push_constants) {
631 /* 1 for push constants and dynamic descriptors */
632 add_array_arg(args, type, &ctx->abi.push_constants);
633 }
634 }
635
636 static void
637 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
638 gl_shader_stage stage,
639 bool has_previous_stage,
640 gl_shader_stage previous_stage,
641 struct arg_info *args)
642 {
643 if (!ctx->is_gs_copy_shader &&
644 (stage == MESA_SHADER_VERTEX ||
645 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
646 if (ctx->shader_info->info.vs.has_vertex_buffers) {
647 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
648 &ctx->vertex_buffers);
649 }
650 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
651 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
652 if (ctx->shader_info->info.vs.needs_draw_id) {
653 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
654 }
655 }
656 }
657
658 static void
659 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
660 {
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
662 if (!ctx->is_gs_copy_shader) {
663 if (ctx->options->key.vs.as_ls) {
664 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
665 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
666 } else {
667 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
668 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
669 }
670 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
671 }
672 }
673
674 static void
675 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
676 {
677 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
678 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
679 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
681 }
682
683 static void
684 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
685 bool has_previous_stage, gl_shader_stage previous_stage,
686 const struct user_sgpr_info *user_sgpr_info,
687 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
688 {
689 unsigned num_sets = ctx->options->layout ?
690 ctx->options->layout->num_sets : 0;
691 unsigned stage_mask = 1 << stage;
692
693 if (has_previous_stage)
694 stage_mask |= 1 << previous_stage;
695
696 if (!user_sgpr_info->indirect_all_descriptor_sets) {
697 for (unsigned i = 0; i < num_sets; ++i) {
698 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
699 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
700 set_loc_desc(ctx, i, user_sgpr_idx, 0);
701 } else
702 ctx->descriptor_sets[i] = NULL;
703 }
704 } else {
705 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
706 user_sgpr_idx, 2);
707
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
710 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
712 ctx->descriptor_sets[i] =
713 ac_build_load_to_sgpr(&ctx->ac,
714 desc_sets,
715 LLVMConstInt(ctx->ac.i32, i, false));
716
717 } else
718 ctx->descriptor_sets[i] = NULL;
719 }
720 ctx->shader_info->need_indirect_descriptor_sets = true;
721 }
722
723 if (ctx->shader_info->info.loads_push_constants) {
724 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
725 }
726 }
727
728 static void
729 set_vs_specific_input_locs(struct radv_shader_context *ctx,
730 gl_shader_stage stage, bool has_previous_stage,
731 gl_shader_stage previous_stage,
732 uint8_t *user_sgpr_idx)
733 {
734 if (!ctx->is_gs_copy_shader &&
735 (stage == MESA_SHADER_VERTEX ||
736 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
737 if (ctx->shader_info->info.vs.has_vertex_buffers) {
738 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
739 user_sgpr_idx, 2);
740 }
741
742 unsigned vs_num = 2;
743 if (ctx->shader_info->info.vs.needs_draw_id)
744 vs_num++;
745
746 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
747 user_sgpr_idx, vs_num);
748 }
749 }
750
751 static void create_function(struct radv_shader_context *ctx,
752 gl_shader_stage stage,
753 bool has_previous_stage,
754 gl_shader_stage previous_stage)
755 {
756 uint8_t user_sgpr_idx;
757 struct user_sgpr_info user_sgpr_info;
758 struct arg_info args = {};
759 LLVMValueRef desc_sets;
760 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
761 allocate_user_sgprs(ctx, stage, has_previous_stage,
762 previous_stage, needs_view_index, &user_sgpr_info);
763
764 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
765 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
766 &ctx->ring_offsets);
767 }
768
769 switch (stage) {
770 case MESA_SHADER_COMPUTE:
771 declare_global_input_sgprs(ctx, stage, has_previous_stage,
772 previous_stage, &user_sgpr_info,
773 &args, &desc_sets);
774
775 if (ctx->shader_info->info.cs.uses_grid_size) {
776 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
777 &ctx->abi.num_work_groups);
778 }
779
780 for (int i = 0; i < 3; i++) {
781 ctx->abi.workgroup_ids[i] = NULL;
782 if (ctx->shader_info->info.cs.uses_block_id[i]) {
783 add_arg(&args, ARG_SGPR, ctx->ac.i32,
784 &ctx->abi.workgroup_ids[i]);
785 }
786 }
787
788 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
789 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
790 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
791 &ctx->abi.local_invocation_ids);
792 break;
793 case MESA_SHADER_VERTEX:
794 declare_global_input_sgprs(ctx, stage, has_previous_stage,
795 previous_stage, &user_sgpr_info,
796 &args, &desc_sets);
797 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &args);
799
800 if (needs_view_index)
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->abi.view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (needs_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->abi.view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->abi.tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (needs_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->abi.view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->abi.tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (needs_view_index)
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->abi.view_index);
892
893 if (ctx->options->key.tes.as_es) {
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->es2gs_offset);
898 } else {
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 }
902 declare_tes_input_vgprs(ctx, &args);
903 break;
904 case MESA_SHADER_GEOMETRY:
905 if (has_previous_stage) {
906 // First 6 system regs
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->gs2vs_offset);
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->merged_wave_info);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
912
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
916
917 declare_global_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &user_sgpr_info, &args,
921 &desc_sets);
922
923 if (previous_stage == MESA_SHADER_TESS_EVAL) {
924 add_arg(&args, ARG_SGPR, ctx->ac.i32,
925 &ctx->tcs_offchip_layout);
926 } else {
927 declare_vs_specific_input_sgprs(ctx, stage,
928 has_previous_stage,
929 previous_stage,
930 &args);
931 }
932
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->gsvs_ring_stride);
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_num_entries);
937 if (needs_view_index)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->abi.view_index);
940
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->gs_vtx_offset[0]);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[2]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->abi.gs_prim_id);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_invocation_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[4]);
951
952 if (previous_stage == MESA_SHADER_VERTEX) {
953 declare_vs_input_vgprs(ctx, &args);
954 } else {
955 declare_tes_input_vgprs(ctx, &args);
956 }
957 } else {
958 declare_global_input_sgprs(ctx, stage,
959 has_previous_stage,
960 previous_stage,
961 &user_sgpr_info, &args,
962 &desc_sets);
963
964 add_arg(&args, ARG_SGPR, ctx->ac.i32,
965 &ctx->gsvs_ring_stride);
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_num_entries);
968 if (needs_view_index)
969 add_arg(&args, ARG_SGPR, ctx->ac.i32,
970 &ctx->abi.view_index);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
973 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[0]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[1]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->abi.gs_prim_id);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[2]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[3]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[4]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[5]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->abi.gs_invocation_id);
990 }
991 break;
992 case MESA_SHADER_FRAGMENT:
993 declare_global_input_sgprs(ctx, stage, has_previous_stage,
994 previous_stage, &user_sgpr_info,
995 &args, &desc_sets);
996
997 if (ctx->shader_info->info.ps.needs_sample_positions)
998 add_arg(&args, ARG_SGPR, ctx->ac.i32,
999 &ctx->sample_pos_offset);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1018 break;
1019 default:
1020 unreachable("Shader stage not implemented");
1021 }
1022
1023 ctx->main_function = create_llvm_function(
1024 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1025 ctx->max_workgroup_size,
1026 ctx->options->unsafe_math);
1027 set_llvm_calling_convention(ctx->main_function, stage);
1028
1029
1030 ctx->shader_info->num_input_vgprs = 0;
1031 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1032
1033 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1034
1035 if (ctx->stage != MESA_SHADER_FRAGMENT)
1036 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1037
1038 assign_arguments(ctx->main_function, &args);
1039
1040 user_sgpr_idx = 0;
1041
1042 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1043 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1044 &user_sgpr_idx, 2);
1045 if (ctx->options->supports_spill) {
1046 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1048 NULL, 0, AC_FUNC_ATTR_READNONE);
1049 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1050 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1051 }
1052 }
1053
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage)
1057 user_sgpr_idx = 0;
1058
1059 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1060 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1061
1062 switch (stage) {
1063 case MESA_SHADER_COMPUTE:
1064 if (ctx->shader_info->info.cs.uses_grid_size) {
1065 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1066 &user_sgpr_idx, 3);
1067 }
1068 break;
1069 case MESA_SHADER_VERTEX:
1070 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1071 previous_stage, &user_sgpr_idx);
1072 if (ctx->abi.view_index)
1073 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1074 if (ctx->options->key.vs.as_ls) {
1075 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1076 &user_sgpr_idx, 1);
1077 }
1078 break;
1079 case MESA_SHADER_TESS_CTRL:
1080 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1081 previous_stage, &user_sgpr_idx);
1082 if (has_previous_stage)
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1086 if (ctx->abi.view_index)
1087 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1088 break;
1089 case MESA_SHADER_TESS_EVAL:
1090 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1091 if (ctx->abi.view_index)
1092 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1093 break;
1094 case MESA_SHADER_GEOMETRY:
1095 if (has_previous_stage) {
1096 if (previous_stage == MESA_SHADER_VERTEX)
1097 set_vs_specific_input_locs(ctx, stage,
1098 has_previous_stage,
1099 previous_stage,
1100 &user_sgpr_idx);
1101 else
1102 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1103 &user_sgpr_idx, 1);
1104 }
1105 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1106 &user_sgpr_idx, 2);
1107 if (ctx->abi.view_index)
1108 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1109 break;
1110 case MESA_SHADER_FRAGMENT:
1111 if (ctx->shader_info->info.ps.needs_sample_positions) {
1112 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1113 &user_sgpr_idx, 1);
1114 }
1115 break;
1116 default:
1117 unreachable("Shader stage not implemented");
1118 }
1119
1120 if (stage == MESA_SHADER_TESS_CTRL ||
1121 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1122 /* GFX9 has the ESGS ring buffer in LDS. */
1123 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1124 ac_declare_lds_as_pointer(&ctx->ac);
1125 }
1126
1127 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1128 }
1129
1130 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1131 LLVMValueRef value, unsigned count)
1132 {
1133 unsigned num_components = ac_get_llvm_num_components(value);
1134 if (count == num_components)
1135 return value;
1136
1137 LLVMValueRef masks[] = {
1138 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1139 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1140
1141 if (count == 1)
1142 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1143 "");
1144
1145 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1146 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1147 }
1148
1149 static void
1150 build_store_values_extended(struct ac_llvm_context *ac,
1151 LLVMValueRef *values,
1152 unsigned value_count,
1153 unsigned value_stride,
1154 LLVMValueRef vec)
1155 {
1156 LLVMBuilderRef builder = ac->builder;
1157 unsigned i;
1158
1159 for (i = 0; i < value_count; i++) {
1160 LLVMValueRef ptr = values[i * value_stride];
1161 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1162 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1163 LLVMBuildStore(builder, value, ptr);
1164 }
1165 }
1166
1167 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1168 const nir_ssa_def *def)
1169 {
1170 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1171 if (def->num_components > 1) {
1172 type = LLVMVectorType(type, def->num_components);
1173 }
1174 return type;
1175 }
1176
1177 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1178 {
1179 assert(src.is_ssa);
1180 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1181 return (LLVMValueRef)entry->data;
1182 }
1183
1184 static LLVMValueRef
1185 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1186 {
1187 LLVMValueRef ptr = get_src(ctx, src);
1188 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1189 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1190
1191 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1192 LLVMPointerType(ctx->ac.i32, addr_space), "");
1193 }
1194
1195 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1196 const struct nir_block *b)
1197 {
1198 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1199 return (LLVMBasicBlockRef)entry->data;
1200 }
1201
1202 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1203 nir_alu_src src,
1204 unsigned num_components)
1205 {
1206 LLVMValueRef value = get_src(ctx, src.src);
1207 bool need_swizzle = false;
1208
1209 assert(value);
1210 unsigned src_components = ac_get_llvm_num_components(value);
1211 for (unsigned i = 0; i < num_components; ++i) {
1212 assert(src.swizzle[i] < src_components);
1213 if (src.swizzle[i] != i)
1214 need_swizzle = true;
1215 }
1216
1217 if (need_swizzle || num_components != src_components) {
1218 LLVMValueRef masks[] = {
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1220 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1221 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1222 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1223
1224 if (src_components > 1 && num_components == 1) {
1225 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1226 masks[0], "");
1227 } else if (src_components == 1 && num_components > 1) {
1228 LLVMValueRef values[] = {value, value, value, value};
1229 value = ac_build_gather_values(&ctx->ac, values, num_components);
1230 } else {
1231 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1232 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1233 swizzle, "");
1234 }
1235 }
1236 assert(!src.negate);
1237 assert(!src.abs);
1238 return value;
1239 }
1240
1241 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1242 LLVMIntPredicate pred, LLVMValueRef src0,
1243 LLVMValueRef src1)
1244 {
1245 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1246 return LLVMBuildSelect(ctx->builder, result,
1247 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1248 ctx->i32_0, "");
1249 }
1250
1251 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1252 LLVMRealPredicate pred, LLVMValueRef src0,
1253 LLVMValueRef src1)
1254 {
1255 LLVMValueRef result;
1256 src0 = ac_to_float(ctx, src0);
1257 src1 = ac_to_float(ctx, src1);
1258 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1259 return LLVMBuildSelect(ctx->builder, result,
1260 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1261 ctx->i32_0, "");
1262 }
1263
1264 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1265 const char *intrin,
1266 LLVMTypeRef result_type,
1267 LLVMValueRef src0)
1268 {
1269 char name[64];
1270 LLVMValueRef params[] = {
1271 ac_to_float(ctx, src0),
1272 };
1273
1274 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1275 ac_get_elem_bits(ctx, result_type));
1276 assert(length < sizeof(name));
1277 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1278 }
1279
1280 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0, LLVMValueRef src1)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 ac_to_float(ctx, src1),
1289 };
1290
1291 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1292 ac_get_elem_bits(ctx, result_type));
1293 assert(length < sizeof(name));
1294 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1295 }
1296
1297 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1298 const char *intrin,
1299 LLVMTypeRef result_type,
1300 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1301 {
1302 char name[64];
1303 LLVMValueRef params[] = {
1304 ac_to_float(ctx, src0),
1305 ac_to_float(ctx, src1),
1306 ac_to_float(ctx, src2),
1307 };
1308
1309 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1310 ac_get_elem_bits(ctx, result_type));
1311 assert(length < sizeof(name));
1312 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1313 }
1314
1315 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1319 ctx->i32_0, "");
1320 return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
1321 ac_to_integer(ctx, src2), "");
1322 }
1323
1324 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1325 LLVMIntPredicate pred,
1326 LLVMValueRef src0, LLVMValueRef src1)
1327 {
1328 return LLVMBuildSelect(ctx->builder,
1329 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1330 src0,
1331 src1, "");
1332
1333 }
1334 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1335 LLVMValueRef src0)
1336 {
1337 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1338 LLVMBuildNeg(ctx->builder, src0, ""));
1339 }
1340
1341 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1342 const char *intrin,
1343 LLVMValueRef src0, LLVMValueRef src1)
1344 {
1345 LLVMTypeRef ret_type;
1346 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1347 LLVMValueRef res;
1348 LLVMValueRef params[] = { src0, src1 };
1349 ret_type = LLVMStructTypeInContext(ctx->context, types,
1350 2, true);
1351
1352 res = ac_build_intrinsic(ctx, intrin, ret_type,
1353 params, 2, AC_FUNC_ATTR_READNONE);
1354
1355 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1356 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1357 return res;
1358 }
1359
1360 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1361 LLVMValueRef src0)
1362 {
1363 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1364 }
1365
1366 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1367 LLVMValueRef src0)
1368 {
1369 src0 = ac_to_float(ctx, src0);
1370 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
1371 return LLVMBuildSExt(ctx->builder,
1372 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, zero, ""),
1373 ctx->i32, "");
1374 }
1375
1376 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1377 LLVMValueRef src0,
1378 unsigned bitsize)
1379 {
1380 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1381
1382 if (bitsize == 32)
1383 return result;
1384
1385 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1386 }
1387
1388 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1389 LLVMValueRef src0)
1390 {
1391 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
1392 return LLVMBuildSExt(ctx->builder,
1393 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, zero, ""),
1394 ctx->i32, "");
1395 }
1396
1397 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1398 LLVMValueRef src0)
1399 {
1400 LLVMValueRef result;
1401 LLVMValueRef cond = NULL;
1402
1403 src0 = ac_to_float(ctx, src0);
1404 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1405
1406 if (ctx->chip_class >= VI) {
1407 LLVMValueRef args[2];
1408 /* Check if the result is a denormal - and flush to 0 if so. */
1409 args[0] = result;
1410 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1411 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1412 }
1413
1414 /* need to convert back up to f32 */
1415 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1416
1417 if (ctx->chip_class >= VI)
1418 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1419 else {
1420 /* for SI/CIK */
1421 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1422 * so compare the result and flush to 0 if it's smaller.
1423 */
1424 LLVMValueRef temp, cond2;
1425 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1426 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1427 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1428 temp, "");
1429 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1430 temp, ctx->f32_0, "");
1431 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1432 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1433 }
1434 return result;
1435 }
1436
1437 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1438 LLVMValueRef src0, LLVMValueRef src1)
1439 {
1440 LLVMValueRef dst64, result;
1441 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1442 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1443
1444 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1445 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1446 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1447 return result;
1448 }
1449
1450 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1451 LLVMValueRef src0, LLVMValueRef src1)
1452 {
1453 LLVMValueRef dst64, result;
1454 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1455 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1456
1457 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1458 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1459 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1460 return result;
1461 }
1462
1463 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1464 bool is_signed,
1465 const LLVMValueRef srcs[3])
1466 {
1467 LLVMValueRef result;
1468 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1469
1470 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1471 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1472 return result;
1473 }
1474
1475 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1476 LLVMValueRef src0, LLVMValueRef src1,
1477 LLVMValueRef src2, LLVMValueRef src3)
1478 {
1479 LLVMValueRef bfi_args[3], result;
1480
1481 bfi_args[0] = LLVMBuildShl(ctx->builder,
1482 LLVMBuildSub(ctx->builder,
1483 LLVMBuildShl(ctx->builder,
1484 ctx->i32_1,
1485 src3, ""),
1486 ctx->i32_1, ""),
1487 src2, "");
1488 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1489 bfi_args[2] = src0;
1490
1491 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1492
1493 /* Calculate:
1494 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1495 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1496 */
1497 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1498 LLVMBuildAnd(ctx->builder, bfi_args[0],
1499 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1500
1501 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1502 return result;
1503 }
1504
1505 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1506 LLVMValueRef src0)
1507 {
1508 LLVMValueRef comp[2];
1509
1510 src0 = ac_to_float(ctx, src0);
1511 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1512 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1513
1514 return ac_build_cvt_pkrtz_f16(ctx, comp);
1515 }
1516
1517 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1518 LLVMValueRef src0)
1519 {
1520 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1521 LLVMValueRef temps[2], result, val;
1522 int i;
1523
1524 for (i = 0; i < 2; i++) {
1525 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1526 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1527 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1528 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1529 }
1530
1531 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1532 ctx->i32_0, "");
1533 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1534 ctx->i32_1, "");
1535 return result;
1536 }
1537
1538 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1539 nir_op op,
1540 LLVMValueRef src0)
1541 {
1542 unsigned mask;
1543 int idx;
1544 LLVMValueRef result;
1545
1546 if (op == nir_op_fddx_fine)
1547 mask = AC_TID_MASK_LEFT;
1548 else if (op == nir_op_fddy_fine)
1549 mask = AC_TID_MASK_TOP;
1550 else
1551 mask = AC_TID_MASK_TOP_LEFT;
1552
1553 /* for DDX we want to next X pixel, DDY next Y pixel. */
1554 if (op == nir_op_fddx_fine ||
1555 op == nir_op_fddx_coarse ||
1556 op == nir_op_fddx)
1557 idx = 1;
1558 else
1559 idx = 2;
1560
1561 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1562 return result;
1563 }
1564
1565 /*
1566 * this takes an I,J coordinate pair,
1567 * and works out the X and Y derivatives.
1568 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1569 */
1570 static LLVMValueRef emit_ddxy_interp(
1571 struct ac_nir_context *ctx,
1572 LLVMValueRef interp_ij)
1573 {
1574 LLVMValueRef result[4], a;
1575 unsigned i;
1576
1577 for (i = 0; i < 2; i++) {
1578 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1579 LLVMConstInt(ctx->ac.i32, i, false), "");
1580 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1581 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1582 }
1583 return ac_build_gather_values(&ctx->ac, result, 4);
1584 }
1585
1586 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1587 {
1588 LLVMValueRef src[4], result = NULL;
1589 unsigned num_components = instr->dest.dest.ssa.num_components;
1590 unsigned src_components;
1591 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1592
1593 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1594 switch (instr->op) {
1595 case nir_op_vec2:
1596 case nir_op_vec3:
1597 case nir_op_vec4:
1598 src_components = 1;
1599 break;
1600 case nir_op_pack_half_2x16:
1601 src_components = 2;
1602 break;
1603 case nir_op_unpack_half_2x16:
1604 src_components = 1;
1605 break;
1606 case nir_op_cube_face_coord:
1607 case nir_op_cube_face_index:
1608 src_components = 3;
1609 break;
1610 default:
1611 src_components = num_components;
1612 break;
1613 }
1614 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1615 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1616
1617 switch (instr->op) {
1618 case nir_op_fmov:
1619 case nir_op_imov:
1620 result = src[0];
1621 break;
1622 case nir_op_fneg:
1623 src[0] = ac_to_float(&ctx->ac, src[0]);
1624 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1625 break;
1626 case nir_op_ineg:
1627 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1628 break;
1629 case nir_op_inot:
1630 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1631 break;
1632 case nir_op_iadd:
1633 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1634 break;
1635 case nir_op_fadd:
1636 src[0] = ac_to_float(&ctx->ac, src[0]);
1637 src[1] = ac_to_float(&ctx->ac, src[1]);
1638 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1639 break;
1640 case nir_op_fsub:
1641 src[0] = ac_to_float(&ctx->ac, src[0]);
1642 src[1] = ac_to_float(&ctx->ac, src[1]);
1643 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1644 break;
1645 case nir_op_isub:
1646 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1647 break;
1648 case nir_op_imul:
1649 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1650 break;
1651 case nir_op_imod:
1652 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1653 break;
1654 case nir_op_umod:
1655 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1656 break;
1657 case nir_op_fmod:
1658 src[0] = ac_to_float(&ctx->ac, src[0]);
1659 src[1] = ac_to_float(&ctx->ac, src[1]);
1660 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1661 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1662 ac_to_float_type(&ctx->ac, def_type), result);
1663 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1664 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1665 break;
1666 case nir_op_frem:
1667 src[0] = ac_to_float(&ctx->ac, src[0]);
1668 src[1] = ac_to_float(&ctx->ac, src[1]);
1669 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1670 break;
1671 case nir_op_irem:
1672 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1673 break;
1674 case nir_op_idiv:
1675 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1676 break;
1677 case nir_op_udiv:
1678 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1679 break;
1680 case nir_op_fmul:
1681 src[0] = ac_to_float(&ctx->ac, src[0]);
1682 src[1] = ac_to_float(&ctx->ac, src[1]);
1683 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1684 break;
1685 case nir_op_frcp:
1686 src[0] = ac_to_float(&ctx->ac, src[0]);
1687 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1688 src[0]);
1689 break;
1690 case nir_op_iand:
1691 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1692 break;
1693 case nir_op_ior:
1694 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_ixor:
1697 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1698 break;
1699 case nir_op_ishl:
1700 result = LLVMBuildShl(ctx->ac.builder, src[0],
1701 LLVMBuildZExt(ctx->ac.builder, src[1],
1702 LLVMTypeOf(src[0]), ""),
1703 "");
1704 break;
1705 case nir_op_ishr:
1706 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1707 LLVMBuildZExt(ctx->ac.builder, src[1],
1708 LLVMTypeOf(src[0]), ""),
1709 "");
1710 break;
1711 case nir_op_ushr:
1712 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1713 LLVMBuildZExt(ctx->ac.builder, src[1],
1714 LLVMTypeOf(src[0]), ""),
1715 "");
1716 break;
1717 case nir_op_ilt:
1718 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1719 break;
1720 case nir_op_ine:
1721 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1722 break;
1723 case nir_op_ieq:
1724 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1725 break;
1726 case nir_op_ige:
1727 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1728 break;
1729 case nir_op_ult:
1730 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1731 break;
1732 case nir_op_uge:
1733 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1734 break;
1735 case nir_op_feq:
1736 result = emit_float_cmp(&ctx->ac, LLVMRealOEQ, src[0], src[1]);
1737 break;
1738 case nir_op_fne:
1739 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1740 break;
1741 case nir_op_flt:
1742 result = emit_float_cmp(&ctx->ac, LLVMRealOLT, src[0], src[1]);
1743 break;
1744 case nir_op_fge:
1745 result = emit_float_cmp(&ctx->ac, LLVMRealOGE, src[0], src[1]);
1746 break;
1747 case nir_op_fabs:
1748 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1749 ac_to_float_type(&ctx->ac, def_type), src[0]);
1750 break;
1751 case nir_op_iabs:
1752 result = emit_iabs(&ctx->ac, src[0]);
1753 break;
1754 case nir_op_imax:
1755 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1756 break;
1757 case nir_op_imin:
1758 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1759 break;
1760 case nir_op_umax:
1761 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1762 break;
1763 case nir_op_umin:
1764 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1765 break;
1766 case nir_op_isign:
1767 result = ac_build_isign(&ctx->ac, src[0],
1768 instr->dest.dest.ssa.bit_size);
1769 break;
1770 case nir_op_fsign:
1771 src[0] = ac_to_float(&ctx->ac, src[0]);
1772 result = ac_build_fsign(&ctx->ac, src[0],
1773 instr->dest.dest.ssa.bit_size);
1774 break;
1775 case nir_op_ffloor:
1776 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1777 ac_to_float_type(&ctx->ac, def_type), src[0]);
1778 break;
1779 case nir_op_ftrunc:
1780 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1781 ac_to_float_type(&ctx->ac, def_type), src[0]);
1782 break;
1783 case nir_op_fceil:
1784 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1785 ac_to_float_type(&ctx->ac, def_type), src[0]);
1786 break;
1787 case nir_op_fround_even:
1788 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1789 ac_to_float_type(&ctx->ac, def_type),src[0]);
1790 break;
1791 case nir_op_ffract:
1792 src[0] = ac_to_float(&ctx->ac, src[0]);
1793 result = ac_build_fract(&ctx->ac, src[0],
1794 instr->dest.dest.ssa.bit_size);
1795 break;
1796 case nir_op_fsin:
1797 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1798 ac_to_float_type(&ctx->ac, def_type), src[0]);
1799 break;
1800 case nir_op_fcos:
1801 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1802 ac_to_float_type(&ctx->ac, def_type), src[0]);
1803 break;
1804 case nir_op_fsqrt:
1805 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1806 ac_to_float_type(&ctx->ac, def_type), src[0]);
1807 break;
1808 case nir_op_fexp2:
1809 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1810 ac_to_float_type(&ctx->ac, def_type), src[0]);
1811 break;
1812 case nir_op_flog2:
1813 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1814 ac_to_float_type(&ctx->ac, def_type), src[0]);
1815 break;
1816 case nir_op_frsq:
1817 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1818 ac_to_float_type(&ctx->ac, def_type), src[0]);
1819 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1820 result);
1821 break;
1822 case nir_op_fmax:
1823 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1824 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1825 if (ctx->ac.chip_class < GFX9 &&
1826 instr->dest.dest.ssa.bit_size == 32) {
1827 /* Only pre-GFX9 chips do not flush denorms. */
1828 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1829 ac_to_float_type(&ctx->ac, def_type),
1830 result);
1831 }
1832 break;
1833 case nir_op_fmin:
1834 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1835 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1836 if (ctx->ac.chip_class < GFX9 &&
1837 instr->dest.dest.ssa.bit_size == 32) {
1838 /* Only pre-GFX9 chips do not flush denorms. */
1839 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1840 ac_to_float_type(&ctx->ac, def_type),
1841 result);
1842 }
1843 break;
1844 case nir_op_ffma:
1845 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1846 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1847 break;
1848 case nir_op_ldexp:
1849 src[0] = ac_to_float(&ctx->ac, src[0]);
1850 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1851 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f32", ctx->ac.f32, src, 2, AC_FUNC_ATTR_READNONE);
1852 else
1853 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f64", ctx->ac.f64, src, 2, AC_FUNC_ATTR_READNONE);
1854 break;
1855 case nir_op_ibitfield_extract:
1856 result = emit_bitfield_extract(&ctx->ac, true, src);
1857 break;
1858 case nir_op_ubitfield_extract:
1859 result = emit_bitfield_extract(&ctx->ac, false, src);
1860 break;
1861 case nir_op_bitfield_insert:
1862 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1863 break;
1864 case nir_op_bitfield_reverse:
1865 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1866 break;
1867 case nir_op_bit_count:
1868 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1869 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1870 else {
1871 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1872 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1873 }
1874 break;
1875 case nir_op_vec2:
1876 case nir_op_vec3:
1877 case nir_op_vec4:
1878 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1879 src[i] = ac_to_integer(&ctx->ac, src[i]);
1880 result = ac_build_gather_values(&ctx->ac, src, num_components);
1881 break;
1882 case nir_op_f2i32:
1883 case nir_op_f2i64:
1884 src[0] = ac_to_float(&ctx->ac, src[0]);
1885 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1886 break;
1887 case nir_op_f2u32:
1888 case nir_op_f2u64:
1889 src[0] = ac_to_float(&ctx->ac, src[0]);
1890 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1891 break;
1892 case nir_op_i2f32:
1893 case nir_op_i2f64:
1894 src[0] = ac_to_integer(&ctx->ac, src[0]);
1895 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1896 break;
1897 case nir_op_u2f32:
1898 case nir_op_u2f64:
1899 src[0] = ac_to_integer(&ctx->ac, src[0]);
1900 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1901 break;
1902 case nir_op_f2f64:
1903 src[0] = ac_to_float(&ctx->ac, src[0]);
1904 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1905 break;
1906 case nir_op_f2f32:
1907 src[0] = ac_to_float(&ctx->ac, src[0]);
1908 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1909 break;
1910 case nir_op_u2u32:
1911 case nir_op_u2u64:
1912 src[0] = ac_to_integer(&ctx->ac, src[0]);
1913 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1914 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1915 else
1916 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1917 break;
1918 case nir_op_i2i32:
1919 case nir_op_i2i64:
1920 src[0] = ac_to_integer(&ctx->ac, src[0]);
1921 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1922 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1923 else
1924 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1925 break;
1926 case nir_op_bcsel:
1927 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1928 break;
1929 case nir_op_find_lsb:
1930 src[0] = ac_to_integer(&ctx->ac, src[0]);
1931 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1932 break;
1933 case nir_op_ufind_msb:
1934 src[0] = ac_to_integer(&ctx->ac, src[0]);
1935 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1936 break;
1937 case nir_op_ifind_msb:
1938 src[0] = ac_to_integer(&ctx->ac, src[0]);
1939 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1940 break;
1941 case nir_op_uadd_carry:
1942 src[0] = ac_to_integer(&ctx->ac, src[0]);
1943 src[1] = ac_to_integer(&ctx->ac, src[1]);
1944 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1945 break;
1946 case nir_op_usub_borrow:
1947 src[0] = ac_to_integer(&ctx->ac, src[0]);
1948 src[1] = ac_to_integer(&ctx->ac, src[1]);
1949 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1950 break;
1951 case nir_op_b2f:
1952 result = emit_b2f(&ctx->ac, src[0]);
1953 break;
1954 case nir_op_f2b:
1955 result = emit_f2b(&ctx->ac, src[0]);
1956 break;
1957 case nir_op_b2i:
1958 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1959 break;
1960 case nir_op_i2b:
1961 src[0] = ac_to_integer(&ctx->ac, src[0]);
1962 result = emit_i2b(&ctx->ac, src[0]);
1963 break;
1964 case nir_op_fquantize2f16:
1965 result = emit_f2f16(&ctx->ac, src[0]);
1966 break;
1967 case nir_op_umul_high:
1968 src[0] = ac_to_integer(&ctx->ac, src[0]);
1969 src[1] = ac_to_integer(&ctx->ac, src[1]);
1970 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1971 break;
1972 case nir_op_imul_high:
1973 src[0] = ac_to_integer(&ctx->ac, src[0]);
1974 src[1] = ac_to_integer(&ctx->ac, src[1]);
1975 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1976 break;
1977 case nir_op_pack_half_2x16:
1978 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1979 break;
1980 case nir_op_unpack_half_2x16:
1981 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1982 break;
1983 case nir_op_fddx:
1984 case nir_op_fddy:
1985 case nir_op_fddx_fine:
1986 case nir_op_fddy_fine:
1987 case nir_op_fddx_coarse:
1988 case nir_op_fddy_coarse:
1989 result = emit_ddxy(ctx, instr->op, src[0]);
1990 break;
1991
1992 case nir_op_unpack_64_2x32_split_x: {
1993 assert(ac_get_llvm_num_components(src[0]) == 1);
1994 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1995 ctx->ac.v2i32,
1996 "");
1997 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1998 ctx->ac.i32_0, "");
1999 break;
2000 }
2001
2002 case nir_op_unpack_64_2x32_split_y: {
2003 assert(ac_get_llvm_num_components(src[0]) == 1);
2004 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2005 ctx->ac.v2i32,
2006 "");
2007 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2008 ctx->ac.i32_1, "");
2009 break;
2010 }
2011
2012 case nir_op_pack_64_2x32_split: {
2013 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2014 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2015 src[0], ctx->ac.i32_0, "");
2016 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2017 src[1], ctx->ac.i32_1, "");
2018 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2019 break;
2020 }
2021
2022 case nir_op_cube_face_coord: {
2023 src[0] = ac_to_float(&ctx->ac, src[0]);
2024 LLVMValueRef results[2];
2025 LLVMValueRef in[3];
2026 for (unsigned chan = 0; chan < 3; chan++)
2027 in[chan] = ac_llvm_extract_elem(&ctx->ac, src[0], chan);
2028 results[0] = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubetc",
2029 ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
2030 results[1] = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubesc",
2031 ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
2032 result = ac_build_gather_values(&ctx->ac, results, 2);
2033 break;
2034 }
2035
2036 case nir_op_cube_face_index: {
2037 src[0] = ac_to_float(&ctx->ac, src[0]);
2038 LLVMValueRef in[3];
2039 for (unsigned chan = 0; chan < 3; chan++)
2040 in[chan] = ac_llvm_extract_elem(&ctx->ac, src[0], chan);
2041 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubeid",
2042 ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
2043 break;
2044 }
2045
2046 default:
2047 fprintf(stderr, "Unknown NIR alu instr: ");
2048 nir_print_instr(&instr->instr, stderr);
2049 fprintf(stderr, "\n");
2050 abort();
2051 }
2052
2053 if (result) {
2054 assert(instr->dest.dest.is_ssa);
2055 result = ac_to_integer(&ctx->ac, result);
2056 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2057 result);
2058 }
2059 }
2060
2061 static void visit_load_const(struct ac_nir_context *ctx,
2062 const nir_load_const_instr *instr)
2063 {
2064 LLVMValueRef values[4], value = NULL;
2065 LLVMTypeRef element_type =
2066 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2067
2068 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2069 switch (instr->def.bit_size) {
2070 case 32:
2071 values[i] = LLVMConstInt(element_type,
2072 instr->value.u32[i], false);
2073 break;
2074 case 64:
2075 values[i] = LLVMConstInt(element_type,
2076 instr->value.u64[i], false);
2077 break;
2078 default:
2079 fprintf(stderr,
2080 "unsupported nir load_const bit_size: %d\n",
2081 instr->def.bit_size);
2082 abort();
2083 }
2084 }
2085 if (instr->def.num_components > 1) {
2086 value = LLVMConstVector(values, instr->def.num_components);
2087 } else
2088 value = values[0];
2089
2090 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2091 }
2092
2093 static LLVMValueRef
2094 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2095 {
2096 LLVMValueRef size =
2097 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2098 LLVMConstInt(ctx->ac.i32, 2, false), "");
2099
2100 /* VI only */
2101 if (ctx->ac.chip_class == VI && in_elements) {
2102 /* On VI, the descriptor contains the size in bytes,
2103 * but TXQ must return the size in elements.
2104 * The stride is always non-zero for resources using TXQ.
2105 */
2106 LLVMValueRef stride =
2107 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2108 ctx->ac.i32_1, "");
2109 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2110 LLVMConstInt(ctx->ac.i32, 16, false), "");
2111 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2112 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2113
2114 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2115 }
2116 return size;
2117 }
2118
2119 /**
2120 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2121 * intrinsic names).
2122 */
2123 static void build_int_type_name(
2124 LLVMTypeRef type,
2125 char *buf, unsigned bufsize)
2126 {
2127 assert(bufsize >= 6);
2128
2129 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2130 snprintf(buf, bufsize, "v%ui32",
2131 LLVMGetVectorSize(type));
2132 else
2133 strcpy(buf, "i32");
2134 }
2135
2136 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2137 struct ac_image_args *args,
2138 const nir_tex_instr *instr)
2139 {
2140 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2141 LLVMValueRef coord = args->addr;
2142 LLVMValueRef half_texel[2];
2143 LLVMValueRef compare_cube_wa = NULL;
2144 LLVMValueRef result;
2145 int c;
2146 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2147
2148 //TODO Rect
2149 {
2150 struct ac_image_args txq_args = { 0 };
2151
2152 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2153 txq_args.opcode = ac_image_get_resinfo;
2154 txq_args.dmask = 0xf;
2155 txq_args.addr = ctx->i32_0;
2156 txq_args.resource = args->resource;
2157 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2158
2159 for (c = 0; c < 2; c++) {
2160 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2161 LLVMConstInt(ctx->i32, c, false), "");
2162 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2163 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2164 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2165 LLVMConstReal(ctx->f32, -0.5), "");
2166 }
2167 }
2168
2169 LLVMValueRef orig_coords = args->addr;
2170
2171 for (c = 0; c < 2; c++) {
2172 LLVMValueRef tmp;
2173 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2174 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2175 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2176 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2177 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2178 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2179 }
2180
2181
2182 /*
2183 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2184 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2185 * workaround by sampling using a scaled type and converting.
2186 * This is taken from amdgpu-pro shaders.
2187 */
2188 /* NOTE this produces some ugly code compared to amdgpu-pro,
2189 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2190 * and then reads them back. -pro generates two selects,
2191 * one s_cmp for the descriptor rewriting
2192 * one v_cmp for the coordinate and result changes.
2193 */
2194 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2195 LLVMValueRef tmp, tmp2;
2196
2197 /* workaround 8/8/8/8 uint/sint cube gather bug */
2198 /* first detect it then change to a scaled read and f2i */
2199 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2200 tmp2 = tmp;
2201
2202 /* extract the DATA_FORMAT */
2203 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2204 LLVMConstInt(ctx->i32, 6, false), false);
2205
2206 /* is the DATA_FORMAT == 8_8_8_8 */
2207 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2208
2209 if (stype == GLSL_TYPE_UINT)
2210 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2211 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2212 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2213 else
2214 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2215 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2216 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2217
2218 /* replace the NUM FORMAT in the descriptor */
2219 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2220 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2221
2222 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2223
2224 /* don't modify the coordinates for this case */
2225 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2226 }
2227 args->addr = coord;
2228 result = ac_build_image_opcode(ctx, args);
2229
2230 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2231 LLVMValueRef tmp, tmp2;
2232
2233 /* if the cube workaround is in place, f2i the result. */
2234 for (c = 0; c < 4; c++) {
2235 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2236 if (stype == GLSL_TYPE_UINT)
2237 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2238 else
2239 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2240 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2241 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2242 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2243 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2244 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2245 }
2246 }
2247 return result;
2248 }
2249
2250 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2251 const nir_tex_instr *instr,
2252 bool lod_is_zero,
2253 struct ac_image_args *args)
2254 {
2255 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2256 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2257
2258 return ac_build_buffer_load_format(&ctx->ac,
2259 args->resource,
2260 args->addr,
2261 ctx->ac.i32_0,
2262 util_last_bit(mask),
2263 false, true);
2264 }
2265
2266 args->opcode = ac_image_sample;
2267 args->compare = instr->is_shadow;
2268
2269 switch (instr->op) {
2270 case nir_texop_txf:
2271 case nir_texop_txf_ms:
2272 case nir_texop_samples_identical:
2273 args->opcode = lod_is_zero ||
2274 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2275 ac_image_load : ac_image_load_mip;
2276 args->compare = false;
2277 args->offset = false;
2278 break;
2279 case nir_texop_txb:
2280 args->bias = true;
2281 break;
2282 case nir_texop_txl:
2283 if (lod_is_zero)
2284 args->level_zero = true;
2285 else
2286 args->lod = true;
2287 break;
2288 case nir_texop_txs:
2289 case nir_texop_query_levels:
2290 args->opcode = ac_image_get_resinfo;
2291 break;
2292 case nir_texop_tex:
2293 if (ctx->stage != MESA_SHADER_FRAGMENT)
2294 args->level_zero = true;
2295 break;
2296 case nir_texop_txd:
2297 args->deriv = true;
2298 break;
2299 case nir_texop_tg4:
2300 args->opcode = ac_image_gather4;
2301 args->level_zero = true;
2302 break;
2303 case nir_texop_lod:
2304 args->opcode = ac_image_get_lod;
2305 args->compare = false;
2306 args->offset = false;
2307 break;
2308 default:
2309 break;
2310 }
2311
2312 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2313 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2314 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2315 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2316 }
2317 }
2318 return ac_build_image_opcode(&ctx->ac, args);
2319 }
2320
2321 static LLVMValueRef
2322 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2323 unsigned desc_set, unsigned binding)
2324 {
2325 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2326 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2327 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2328 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2329 unsigned base_offset = layout->binding[binding].offset;
2330 LLVMValueRef offset, stride;
2331
2332 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2333 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2334 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2335 layout->binding[binding].dynamic_offset_offset;
2336 desc_ptr = ctx->abi.push_constants;
2337 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2338 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2339 } else
2340 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2341
2342 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2343 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2344 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2345
2346 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2347 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2348 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2349
2350 return desc_ptr;
2351 }
2352
2353 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2354 nir_intrinsic_instr *instr)
2355 {
2356 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2357 LLVMValueRef index = get_src(ctx, instr->src[1]);
2358
2359 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2360 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2361 return result;
2362 }
2363
2364 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2365 nir_intrinsic_instr *instr)
2366 {
2367 LLVMValueRef ptr, addr;
2368
2369 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2370 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2371 get_src(ctx, instr->src[0]), "");
2372
2373 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2374 ptr = ac_cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2375
2376 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2377 }
2378
2379 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2380 const nir_intrinsic_instr *instr)
2381 {
2382 LLVMValueRef index = get_src(ctx, instr->src[0]);
2383
2384 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2385 }
2386
2387 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2388 {
2389 uint32_t new_mask = 0;
2390 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2391 if (mask & (1u << i))
2392 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2393 return new_mask;
2394 }
2395
2396 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2397 unsigned start, unsigned count)
2398 {
2399 LLVMTypeRef type = LLVMTypeOf(src);
2400
2401 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2402 assert(start == 0);
2403 assert(count == 1);
2404 return src;
2405 }
2406
2407 unsigned src_elements = LLVMGetVectorSize(type);
2408 assert(start < src_elements);
2409 assert(start + count <= src_elements);
2410
2411 if (start == 0 && count == src_elements)
2412 return src;
2413
2414 if (count == 1)
2415 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2416
2417 assert(count <= 8);
2418 LLVMValueRef indices[8];
2419 for (unsigned i = 0; i < count; ++i)
2420 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2421
2422 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2423 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2424 }
2425
2426 static void visit_store_ssbo(struct ac_nir_context *ctx,
2427 nir_intrinsic_instr *instr)
2428 {
2429 const char *store_name;
2430 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2431 LLVMTypeRef data_type = ctx->ac.f32;
2432 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2433 int components_32bit = elem_size_mult * instr->num_components;
2434 unsigned writemask = nir_intrinsic_write_mask(instr);
2435 LLVMValueRef base_data, base_offset;
2436 LLVMValueRef params[6];
2437
2438 params[1] = ctx->abi->load_ssbo(ctx->abi,
2439 get_src(ctx, instr->src[1]), true);
2440 params[2] = ctx->ac.i32_0; /* vindex */
2441 params[4] = ctx->ac.i1false; /* glc */
2442 params[5] = ctx->ac.i1false; /* slc */
2443
2444 if (components_32bit > 1)
2445 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2446
2447 writemask = widen_mask(writemask, elem_size_mult);
2448
2449 base_data = ac_to_float(&ctx->ac, src_data);
2450 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2451 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2452 data_type, "");
2453 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2454 while (writemask) {
2455 int start, count;
2456 LLVMValueRef data;
2457 LLVMValueRef offset;
2458
2459 u_bit_scan_consecutive_range(&writemask, &start, &count);
2460
2461 /* Due to an LLVM limitation, split 3-element writes
2462 * into a 2-element and a 1-element write. */
2463 if (count == 3) {
2464 writemask |= 1 << (start + 2);
2465 count = 2;
2466 }
2467
2468 if (count > 4) {
2469 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2470 count = 4;
2471 }
2472
2473 if (count == 4) {
2474 store_name = "llvm.amdgcn.buffer.store.v4f32";
2475 } else if (count == 2) {
2476 store_name = "llvm.amdgcn.buffer.store.v2f32";
2477
2478 } else {
2479 assert(count == 1);
2480 store_name = "llvm.amdgcn.buffer.store.f32";
2481 }
2482 data = extract_vector_range(&ctx->ac, base_data, start, count);
2483
2484 offset = base_offset;
2485 if (start != 0) {
2486 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2487 }
2488 params[0] = data;
2489 params[3] = offset;
2490 ac_build_intrinsic(&ctx->ac, store_name,
2491 ctx->ac.voidt, params, 6, 0);
2492 }
2493 }
2494
2495 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2496 const nir_intrinsic_instr *instr)
2497 {
2498 const char *name;
2499 LLVMValueRef params[6];
2500 int arg_count = 0;
2501
2502 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2503 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2504 }
2505 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2506 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2507 get_src(ctx, instr->src[0]),
2508 true);
2509 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2510 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2511 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2512
2513 switch (instr->intrinsic) {
2514 case nir_intrinsic_ssbo_atomic_add:
2515 name = "llvm.amdgcn.buffer.atomic.add";
2516 break;
2517 case nir_intrinsic_ssbo_atomic_imin:
2518 name = "llvm.amdgcn.buffer.atomic.smin";
2519 break;
2520 case nir_intrinsic_ssbo_atomic_umin:
2521 name = "llvm.amdgcn.buffer.atomic.umin";
2522 break;
2523 case nir_intrinsic_ssbo_atomic_imax:
2524 name = "llvm.amdgcn.buffer.atomic.smax";
2525 break;
2526 case nir_intrinsic_ssbo_atomic_umax:
2527 name = "llvm.amdgcn.buffer.atomic.umax";
2528 break;
2529 case nir_intrinsic_ssbo_atomic_and:
2530 name = "llvm.amdgcn.buffer.atomic.and";
2531 break;
2532 case nir_intrinsic_ssbo_atomic_or:
2533 name = "llvm.amdgcn.buffer.atomic.or";
2534 break;
2535 case nir_intrinsic_ssbo_atomic_xor:
2536 name = "llvm.amdgcn.buffer.atomic.xor";
2537 break;
2538 case nir_intrinsic_ssbo_atomic_exchange:
2539 name = "llvm.amdgcn.buffer.atomic.swap";
2540 break;
2541 case nir_intrinsic_ssbo_atomic_comp_swap:
2542 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2543 break;
2544 default:
2545 abort();
2546 }
2547
2548 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2549 }
2550
2551 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2552 const nir_intrinsic_instr *instr)
2553 {
2554 LLVMValueRef results[2];
2555 int load_components;
2556 int num_components = instr->num_components;
2557 if (instr->dest.ssa.bit_size == 64)
2558 num_components *= 2;
2559
2560 for (int i = 0; i < num_components; i += load_components) {
2561 load_components = MIN2(num_components - i, 4);
2562 const char *load_name;
2563 LLVMTypeRef data_type = ctx->ac.f32;
2564 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2565 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2566
2567 if (load_components == 3)
2568 data_type = LLVMVectorType(ctx->ac.f32, 4);
2569 else if (load_components > 1)
2570 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2571
2572 if (load_components >= 3)
2573 load_name = "llvm.amdgcn.buffer.load.v4f32";
2574 else if (load_components == 2)
2575 load_name = "llvm.amdgcn.buffer.load.v2f32";
2576 else if (load_components == 1)
2577 load_name = "llvm.amdgcn.buffer.load.f32";
2578 else
2579 unreachable("unhandled number of components");
2580
2581 LLVMValueRef params[] = {
2582 ctx->abi->load_ssbo(ctx->abi,
2583 get_src(ctx, instr->src[0]),
2584 false),
2585 ctx->ac.i32_0,
2586 offset,
2587 ctx->ac.i1false,
2588 ctx->ac.i1false,
2589 };
2590
2591 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2592 }
2593
2594 assume(results[0]);
2595 LLVMValueRef ret = results[0];
2596 if (num_components > 4 || num_components == 3) {
2597 LLVMValueRef masks[] = {
2598 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2599 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2600 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2601 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2602 };
2603
2604 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2605 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2606 results[num_components > 4 ? 1 : 0], swizzle, "");
2607 }
2608
2609 return LLVMBuildBitCast(ctx->ac.builder, ret,
2610 get_def_type(ctx, &instr->dest.ssa), "");
2611 }
2612
2613 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2614 const nir_intrinsic_instr *instr)
2615 {
2616 LLVMValueRef ret;
2617 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2618 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2619 int num_components = instr->num_components;
2620
2621 if (ctx->abi->load_ubo)
2622 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2623
2624 if (instr->dest.ssa.bit_size == 64)
2625 num_components *= 2;
2626
2627 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2628 NULL, 0, false, false, true, true);
2629 ret = trim_vector(&ctx->ac, ret, num_components);
2630 return LLVMBuildBitCast(ctx->ac.builder, ret,
2631 get_def_type(ctx, &instr->dest.ssa), "");
2632 }
2633
2634 static void
2635 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2636 bool vs_in, unsigned *vertex_index_out,
2637 LLVMValueRef *vertex_index_ref,
2638 unsigned *const_out, LLVMValueRef *indir_out)
2639 {
2640 unsigned const_offset = 0;
2641 nir_deref *tail = &deref->deref;
2642 LLVMValueRef offset = NULL;
2643
2644 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2645 tail = tail->child;
2646 nir_deref_array *deref_array = nir_deref_as_array(tail);
2647 if (vertex_index_out)
2648 *vertex_index_out = deref_array->base_offset;
2649
2650 if (vertex_index_ref) {
2651 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2652 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2653 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2654 }
2655 *vertex_index_ref = vtx;
2656 }
2657 }
2658
2659 if (deref->var->data.compact) {
2660 assert(tail->child->deref_type == nir_deref_type_array);
2661 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2662 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2663 /* We always lower indirect dereferences for "compact" array vars. */
2664 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2665
2666 const_offset = deref_array->base_offset;
2667 goto out;
2668 }
2669
2670 while (tail->child != NULL) {
2671 const struct glsl_type *parent_type = tail->type;
2672 tail = tail->child;
2673
2674 if (tail->deref_type == nir_deref_type_array) {
2675 nir_deref_array *deref_array = nir_deref_as_array(tail);
2676 LLVMValueRef index, stride, local_offset;
2677 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2678
2679 const_offset += size * deref_array->base_offset;
2680 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2681 continue;
2682
2683 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2684 index = get_src(ctx, deref_array->indirect);
2685 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2686 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2687
2688 if (offset)
2689 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2690 else
2691 offset = local_offset;
2692 } else if (tail->deref_type == nir_deref_type_struct) {
2693 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2694
2695 for (unsigned i = 0; i < deref_struct->index; i++) {
2696 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2697 const_offset += glsl_count_attribute_slots(ft, vs_in);
2698 }
2699 } else
2700 unreachable("unsupported deref type");
2701
2702 }
2703 out:
2704 if (const_offset && offset)
2705 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2706 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2707 "");
2708
2709 *const_out = const_offset;
2710 *indir_out = offset;
2711 }
2712
2713
2714 /* The offchip buffer layout for TCS->TES is
2715 *
2716 * - attribute 0 of patch 0 vertex 0
2717 * - attribute 0 of patch 0 vertex 1
2718 * - attribute 0 of patch 0 vertex 2
2719 * ...
2720 * - attribute 0 of patch 1 vertex 0
2721 * - attribute 0 of patch 1 vertex 1
2722 * ...
2723 * - attribute 1 of patch 0 vertex 0
2724 * - attribute 1 of patch 0 vertex 1
2725 * ...
2726 * - per patch attribute 0 of patch 0
2727 * - per patch attribute 0 of patch 1
2728 * ...
2729 *
2730 * Note that every attribute has 4 components.
2731 */
2732 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2733 LLVMValueRef vertex_index,
2734 LLVMValueRef param_index)
2735 {
2736 LLVMValueRef base_addr, vertices_per_patch, num_patches;
2737 LLVMValueRef param_stride, constant16;
2738 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2739
2740 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
2741 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2742
2743 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2744 if (vertex_index) {
2745 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2746 vertices_per_patch, "");
2747
2748 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2749 vertex_index, "");
2750
2751 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2752 num_patches, "");
2753 } else {
2754 base_addr = rel_patch_id;
2755 param_stride = num_patches;
2756 }
2757
2758 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2759 LLVMBuildMul(ctx->ac.builder, param_index,
2760 param_stride, ""), "");
2761
2762 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2763
2764 if (!vertex_index) {
2765 LLVMValueRef patch_data_offset =
2766 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2767
2768 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2769 patch_data_offset, "");
2770 }
2771 return base_addr;
2772 }
2773
2774 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2775 unsigned param,
2776 unsigned const_index,
2777 bool is_compact,
2778 LLVMValueRef vertex_index,
2779 LLVMValueRef indir_index)
2780 {
2781 LLVMValueRef param_index;
2782
2783 if (indir_index)
2784 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2785 indir_index, "");
2786 else {
2787 if (const_index && !is_compact)
2788 param += const_index;
2789 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2790 }
2791 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2792 }
2793
2794 static void
2795 mark_tess_output(struct radv_shader_context *ctx,
2796 bool is_patch, uint32_t param)
2797
2798 {
2799 if (is_patch) {
2800 ctx->tess_patch_outputs_written |= (1ull << param);
2801 } else
2802 ctx->tess_outputs_written |= (1ull << param);
2803 }
2804
2805 static LLVMValueRef
2806 get_dw_address(struct radv_shader_context *ctx,
2807 LLVMValueRef dw_addr,
2808 unsigned param,
2809 unsigned const_index,
2810 bool compact_const_index,
2811 LLVMValueRef vertex_index,
2812 LLVMValueRef stride,
2813 LLVMValueRef indir_index)
2814
2815 {
2816
2817 if (vertex_index) {
2818 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2819 LLVMBuildMul(ctx->ac.builder,
2820 vertex_index,
2821 stride, ""), "");
2822 }
2823
2824 if (indir_index)
2825 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2826 LLVMBuildMul(ctx->ac.builder, indir_index,
2827 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2828 else if (const_index && !compact_const_index)
2829 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2830 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2831
2832 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2833 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2834
2835 if (const_index && compact_const_index)
2836 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2837 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2838 return dw_addr;
2839 }
2840
2841 static LLVMValueRef
2842 load_tcs_varyings(struct ac_shader_abi *abi,
2843 LLVMTypeRef type,
2844 LLVMValueRef vertex_index,
2845 LLVMValueRef indir_index,
2846 unsigned const_index,
2847 unsigned location,
2848 unsigned driver_location,
2849 unsigned component,
2850 unsigned num_components,
2851 bool is_patch,
2852 bool is_compact,
2853 bool load_input)
2854 {
2855 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2856 LLVMValueRef dw_addr, stride;
2857 LLVMValueRef value[4], result;
2858 unsigned param = shader_io_get_unique_index(location);
2859
2860 if (load_input) {
2861 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2862 dw_addr = get_tcs_in_current_patch_offset(ctx);
2863 } else {
2864 if (!is_patch) {
2865 stride = get_tcs_out_vertex_stride(ctx);
2866 dw_addr = get_tcs_out_current_patch_offset(ctx);
2867 } else {
2868 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2869 stride = NULL;
2870 }
2871 }
2872
2873 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2874 indir_index);
2875
2876 for (unsigned i = 0; i < num_components + component; i++) {
2877 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2878 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2879 ctx->ac.i32_1, "");
2880 }
2881 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2882 return result;
2883 }
2884
2885 static void
2886 store_tcs_output(struct ac_shader_abi *abi,
2887 LLVMValueRef vertex_index,
2888 LLVMValueRef param_index,
2889 unsigned const_index,
2890 unsigned location,
2891 unsigned driver_location,
2892 LLVMValueRef src,
2893 unsigned component,
2894 bool is_patch,
2895 bool is_compact,
2896 unsigned writemask)
2897 {
2898 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2899 LLVMValueRef dw_addr;
2900 LLVMValueRef stride = NULL;
2901 LLVMValueRef buf_addr = NULL;
2902 unsigned param;
2903 bool store_lds = true;
2904
2905 if (is_patch) {
2906 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2907 store_lds = false;
2908 } else {
2909 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2910 store_lds = false;
2911 }
2912
2913 param = shader_io_get_unique_index(location);
2914 if (location == VARYING_SLOT_CLIP_DIST0 &&
2915 is_compact && const_index > 3) {
2916 const_index -= 3;
2917 param++;
2918 }
2919
2920 if (!is_patch) {
2921 stride = get_tcs_out_vertex_stride(ctx);
2922 dw_addr = get_tcs_out_current_patch_offset(ctx);
2923 } else {
2924 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2925 }
2926
2927 mark_tess_output(ctx, is_patch, param);
2928
2929 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2930 param_index);
2931 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2932 vertex_index, param_index);
2933
2934 bool is_tess_factor = false;
2935 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2936 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2937 is_tess_factor = true;
2938
2939 unsigned base = is_compact ? const_index : 0;
2940 for (unsigned chan = 0; chan < 8; chan++) {
2941 if (!(writemask & (1 << chan)))
2942 continue;
2943 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2944
2945 if (store_lds || is_tess_factor) {
2946 LLVMValueRef dw_addr_chan =
2947 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2948 LLVMConstInt(ctx->ac.i32, chan, false), "");
2949 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2950 }
2951
2952 if (!is_tess_factor && writemask != 0xF)
2953 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2954 buf_addr, ctx->oc_lds,
2955 4 * (base + chan), 1, 0, true, false);
2956 }
2957
2958 if (writemask == 0xF) {
2959 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2960 buf_addr, ctx->oc_lds,
2961 (base * 4), 1, 0, true, false);
2962 }
2963 }
2964
2965 static LLVMValueRef
2966 load_tes_input(struct ac_shader_abi *abi,
2967 LLVMTypeRef type,
2968 LLVMValueRef vertex_index,
2969 LLVMValueRef param_index,
2970 unsigned const_index,
2971 unsigned location,
2972 unsigned driver_location,
2973 unsigned component,
2974 unsigned num_components,
2975 bool is_patch,
2976 bool is_compact,
2977 bool load_input)
2978 {
2979 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2980 LLVMValueRef buf_addr;
2981 LLVMValueRef result;
2982 unsigned param = shader_io_get_unique_index(location);
2983
2984 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2985 const_index -= 3;
2986 param++;
2987 }
2988
2989 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2990 is_compact, vertex_index, param_index);
2991
2992 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
2993 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
2994
2995 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
2996 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2997 result = trim_vector(&ctx->ac, result, num_components);
2998 return result;
2999 }
3000
3001 static LLVMValueRef
3002 load_gs_input(struct ac_shader_abi *abi,
3003 unsigned location,
3004 unsigned driver_location,
3005 unsigned component,
3006 unsigned num_components,
3007 unsigned vertex_index,
3008 unsigned const_index,
3009 LLVMTypeRef type)
3010 {
3011 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3012 LLVMValueRef vtx_offset;
3013 unsigned param, vtx_offset_param;
3014 LLVMValueRef value[4], result;
3015
3016 vtx_offset_param = vertex_index;
3017 assert(vtx_offset_param < 6);
3018 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3019 LLVMConstInt(ctx->ac.i32, 4, false), "");
3020
3021 param = shader_io_get_unique_index(location);
3022
3023 for (unsigned i = component; i < num_components + component; i++) {
3024 if (ctx->ac.chip_class >= GFX9) {
3025 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3026 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3027 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3028 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3029 } else {
3030 LLVMValueRef soffset =
3031 LLVMConstInt(ctx->ac.i32,
3032 (param * 4 + i + const_index) * 256,
3033 false);
3034
3035 value[i] = ac_build_buffer_load(&ctx->ac,
3036 ctx->esgs_ring, 1,
3037 ctx->ac.i32_0,
3038 vtx_offset, soffset,
3039 0, 1, 0, true, false);
3040
3041 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3042 type, "");
3043 }
3044 }
3045 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3046 result = ac_to_integer(&ctx->ac, result);
3047 return result;
3048 }
3049
3050 static LLVMValueRef
3051 build_gep_for_deref(struct ac_nir_context *ctx,
3052 nir_deref_var *deref)
3053 {
3054 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3055 assert(entry->data);
3056 LLVMValueRef val = entry->data;
3057 nir_deref *tail = deref->deref.child;
3058 while (tail != NULL) {
3059 LLVMValueRef offset;
3060 switch (tail->deref_type) {
3061 case nir_deref_type_array: {
3062 nir_deref_array *array = nir_deref_as_array(tail);
3063 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3064 if (array->deref_array_type ==
3065 nir_deref_array_type_indirect) {
3066 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3067 get_src(ctx,
3068 array->indirect),
3069 "");
3070 }
3071 break;
3072 }
3073 case nir_deref_type_struct: {
3074 nir_deref_struct *deref_struct =
3075 nir_deref_as_struct(tail);
3076 offset = LLVMConstInt(ctx->ac.i32,
3077 deref_struct->index, 0);
3078 break;
3079 }
3080 default:
3081 unreachable("bad deref type");
3082 }
3083 val = ac_build_gep0(&ctx->ac, val, offset);
3084 tail = tail->child;
3085 }
3086 return val;
3087 }
3088
3089 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3090 nir_intrinsic_instr *instr,
3091 bool load_inputs)
3092 {
3093 LLVMValueRef result;
3094 LLVMValueRef vertex_index = NULL;
3095 LLVMValueRef indir_index = NULL;
3096 unsigned const_index = 0;
3097 unsigned location = instr->variables[0]->var->data.location;
3098 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3099 const bool is_patch = instr->variables[0]->var->data.patch;
3100 const bool is_compact = instr->variables[0]->var->data.compact;
3101
3102 get_deref_offset(ctx, instr->variables[0],
3103 false, NULL, is_patch ? NULL : &vertex_index,
3104 &const_index, &indir_index);
3105
3106 LLVMTypeRef dest_type = get_def_type(ctx, &instr->dest.ssa);
3107
3108 LLVMTypeRef src_component_type;
3109 if (LLVMGetTypeKind(dest_type) == LLVMVectorTypeKind)
3110 src_component_type = LLVMGetElementType(dest_type);
3111 else
3112 src_component_type = dest_type;
3113
3114 result = ctx->abi->load_tess_varyings(ctx->abi, src_component_type,
3115 vertex_index, indir_index,
3116 const_index, location, driver_location,
3117 instr->variables[0]->var->data.location_frac,
3118 instr->num_components,
3119 is_patch, is_compact, load_inputs);
3120 return LLVMBuildBitCast(ctx->ac.builder, result, dest_type, "");
3121 }
3122
3123 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3124 nir_intrinsic_instr *instr)
3125 {
3126 LLVMValueRef values[8];
3127 int idx = instr->variables[0]->var->data.driver_location;
3128 int ve = instr->dest.ssa.num_components;
3129 unsigned comp = instr->variables[0]->var->data.location_frac;
3130 LLVMValueRef indir_index;
3131 LLVMValueRef ret;
3132 unsigned const_index;
3133 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3134 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3135 instr->variables[0]->var->data.mode == nir_var_shader_in;
3136 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3137 &const_index, &indir_index);
3138
3139 if (instr->dest.ssa.bit_size == 64)
3140 ve *= 2;
3141
3142 switch (instr->variables[0]->var->data.mode) {
3143 case nir_var_shader_in:
3144 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3145 ctx->stage == MESA_SHADER_TESS_EVAL) {
3146 return load_tess_varyings(ctx, instr, true);
3147 }
3148
3149 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3150 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3151 LLVMValueRef indir_index;
3152 unsigned const_index, vertex_index;
3153 get_deref_offset(ctx, instr->variables[0],
3154 false, &vertex_index, NULL,
3155 &const_index, &indir_index);
3156
3157 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3158 instr->variables[0]->var->data.driver_location,
3159 instr->variables[0]->var->data.location_frac,
3160 instr->num_components, vertex_index, const_index, type);
3161 }
3162
3163 for (unsigned chan = comp; chan < ve + comp; chan++) {
3164 if (indir_index) {
3165 unsigned count = glsl_count_attribute_slots(
3166 instr->variables[0]->var->type,
3167 ctx->stage == MESA_SHADER_VERTEX);
3168 count -= chan / 4;
3169 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3170 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3171 stride, false, true);
3172
3173 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3174 tmp_vec,
3175 indir_index, "");
3176 } else
3177 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3178 }
3179 break;
3180 case nir_var_local:
3181 for (unsigned chan = 0; chan < ve; chan++) {
3182 if (indir_index) {
3183 unsigned count = glsl_count_attribute_slots(
3184 instr->variables[0]->var->type, false);
3185 count -= chan / 4;
3186 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3187 &ctx->ac, ctx->locals + idx + chan, count,
3188 stride, true, true);
3189
3190 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3191 tmp_vec,
3192 indir_index, "");
3193 } else {
3194 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3195 }
3196 }
3197 break;
3198 case nir_var_shared: {
3199 LLVMValueRef address = build_gep_for_deref(ctx,
3200 instr->variables[0]);
3201 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3202 return LLVMBuildBitCast(ctx->ac.builder, val,
3203 get_def_type(ctx, &instr->dest.ssa),
3204 "");
3205 }
3206 case nir_var_shader_out:
3207 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3208 return load_tess_varyings(ctx, instr, false);
3209 }
3210
3211 for (unsigned chan = comp; chan < ve + comp; chan++) {
3212 if (indir_index) {
3213 unsigned count = glsl_count_attribute_slots(
3214 instr->variables[0]->var->type, false);
3215 count -= chan / 4;
3216 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3217 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3218 stride, true, true);
3219
3220 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3221 tmp_vec,
3222 indir_index, "");
3223 } else {
3224 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3225 ctx->abi->outputs[idx + chan + const_index * stride],
3226 "");
3227 }
3228 }
3229 break;
3230 default:
3231 unreachable("unhandle variable mode");
3232 }
3233 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3234 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3235 }
3236
3237 static void
3238 visit_store_var(struct ac_nir_context *ctx,
3239 nir_intrinsic_instr *instr)
3240 {
3241 LLVMValueRef temp_ptr, value;
3242 int idx = instr->variables[0]->var->data.driver_location;
3243 unsigned comp = instr->variables[0]->var->data.location_frac;
3244 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3245 int writemask = instr->const_index[0] << comp;
3246 LLVMValueRef indir_index;
3247 unsigned const_index;
3248 get_deref_offset(ctx, instr->variables[0], false,
3249 NULL, NULL, &const_index, &indir_index);
3250
3251 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3252
3253 src = LLVMBuildBitCast(ctx->ac.builder, src,
3254 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3255 "");
3256
3257 writemask = widen_mask(writemask, 2);
3258 }
3259
3260 switch (instr->variables[0]->var->data.mode) {
3261 case nir_var_shader_out:
3262
3263 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3264 LLVMValueRef vertex_index = NULL;
3265 LLVMValueRef indir_index = NULL;
3266 unsigned const_index = 0;
3267 const unsigned location = instr->variables[0]->var->data.location;
3268 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3269 const unsigned comp = instr->variables[0]->var->data.location_frac;
3270 const bool is_patch = instr->variables[0]->var->data.patch;
3271 const bool is_compact = instr->variables[0]->var->data.compact;
3272
3273 get_deref_offset(ctx, instr->variables[0],
3274 false, NULL, is_patch ? NULL : &vertex_index,
3275 &const_index, &indir_index);
3276
3277 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3278 const_index, location, driver_location,
3279 src, comp, is_patch, is_compact, writemask);
3280 return;
3281 }
3282
3283 for (unsigned chan = 0; chan < 8; chan++) {
3284 int stride = 4;
3285 if (!(writemask & (1 << chan)))
3286 continue;
3287
3288 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3289
3290 if (instr->variables[0]->var->data.compact)
3291 stride = 1;
3292 if (indir_index) {
3293 unsigned count = glsl_count_attribute_slots(
3294 instr->variables[0]->var->type, false);
3295 count -= chan / 4;
3296 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3297 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3298 stride, true, true);
3299
3300 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3301 value, indir_index, "");
3302 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3303 count, stride, tmp_vec);
3304
3305 } else {
3306 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3307
3308 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3309 }
3310 }
3311 break;
3312 case nir_var_local:
3313 for (unsigned chan = 0; chan < 8; chan++) {
3314 if (!(writemask & (1 << chan)))
3315 continue;
3316
3317 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3318 if (indir_index) {
3319 unsigned count = glsl_count_attribute_slots(
3320 instr->variables[0]->var->type, false);
3321 count -= chan / 4;
3322 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3323 &ctx->ac, ctx->locals + idx + chan, count,
3324 4, true, true);
3325
3326 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3327 value, indir_index, "");
3328 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3329 count, 4, tmp_vec);
3330 } else {
3331 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3332
3333 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3334 }
3335 }
3336 break;
3337 case nir_var_shared: {
3338 int writemask = instr->const_index[0];
3339 LLVMValueRef address = build_gep_for_deref(ctx,
3340 instr->variables[0]);
3341 LLVMValueRef val = get_src(ctx, instr->src[0]);
3342 unsigned components =
3343 glsl_get_vector_elements(
3344 nir_deref_tail(&instr->variables[0]->deref)->type);
3345 if (writemask == (1 << components) - 1) {
3346 val = LLVMBuildBitCast(
3347 ctx->ac.builder, val,
3348 LLVMGetElementType(LLVMTypeOf(address)), "");
3349 LLVMBuildStore(ctx->ac.builder, val, address);
3350 } else {
3351 for (unsigned chan = 0; chan < 4; chan++) {
3352 if (!(writemask & (1 << chan)))
3353 continue;
3354 LLVMValueRef ptr =
3355 LLVMBuildStructGEP(ctx->ac.builder,
3356 address, chan, "");
3357 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3358 chan);
3359 src = LLVMBuildBitCast(
3360 ctx->ac.builder, src,
3361 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3362 LLVMBuildStore(ctx->ac.builder, src, ptr);
3363 }
3364 }
3365 break;
3366 }
3367 default:
3368 break;
3369 }
3370 }
3371
3372 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3373 {
3374 switch (dim) {
3375 case GLSL_SAMPLER_DIM_BUF:
3376 return 1;
3377 case GLSL_SAMPLER_DIM_1D:
3378 return array ? 2 : 1;
3379 case GLSL_SAMPLER_DIM_2D:
3380 return array ? 3 : 2;
3381 case GLSL_SAMPLER_DIM_MS:
3382 return array ? 4 : 3;
3383 case GLSL_SAMPLER_DIM_3D:
3384 case GLSL_SAMPLER_DIM_CUBE:
3385 return 3;
3386 case GLSL_SAMPLER_DIM_RECT:
3387 case GLSL_SAMPLER_DIM_SUBPASS:
3388 return 2;
3389 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3390 return 3;
3391 default:
3392 break;
3393 }
3394 return 0;
3395 }
3396
3397 static bool
3398 glsl_is_array_image(const struct glsl_type *type)
3399 {
3400 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3401
3402 if (glsl_sampler_type_is_array(type))
3403 return true;
3404
3405 return dim == GLSL_SAMPLER_DIM_CUBE ||
3406 dim == GLSL_SAMPLER_DIM_3D ||
3407 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3408 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3409 }
3410
3411
3412 /* Adjust the sample index according to FMASK.
3413 *
3414 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3415 * which is the identity mapping. Each nibble says which physical sample
3416 * should be fetched to get that sample.
3417 *
3418 * For example, 0x11111100 means there are only 2 samples stored and
3419 * the second sample covers 3/4 of the pixel. When reading samples 0
3420 * and 1, return physical sample 0 (determined by the first two 0s
3421 * in FMASK), otherwise return physical sample 1.
3422 *
3423 * The sample index should be adjusted as follows:
3424 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3425 */
3426 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3427 LLVMValueRef coord_x, LLVMValueRef coord_y,
3428 LLVMValueRef coord_z,
3429 LLVMValueRef sample_index,
3430 LLVMValueRef fmask_desc_ptr)
3431 {
3432 LLVMValueRef fmask_load_address[4];
3433 LLVMValueRef res;
3434
3435 fmask_load_address[0] = coord_x;
3436 fmask_load_address[1] = coord_y;
3437 if (coord_z) {
3438 fmask_load_address[2] = coord_z;
3439 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3440 }
3441
3442 struct ac_image_args args = {0};
3443
3444 args.opcode = ac_image_load;
3445 args.da = coord_z ? true : false;
3446 args.resource = fmask_desc_ptr;
3447 args.dmask = 0xf;
3448 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3449
3450 res = ac_build_image_opcode(ctx, &args);
3451
3452 res = ac_to_integer(ctx, res);
3453 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3454 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3455
3456 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3457 res,
3458 ctx->i32_0, "");
3459
3460 LLVMValueRef sample_index4 =
3461 LLVMBuildMul(ctx->builder, sample_index, four, "");
3462 LLVMValueRef shifted_fmask =
3463 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3464 LLVMValueRef final_sample =
3465 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3466
3467 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3468 * resource descriptor is 0 (invalid),
3469 */
3470 LLVMValueRef fmask_desc =
3471 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3472 ctx->v8i32, "");
3473
3474 LLVMValueRef fmask_word1 =
3475 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3476 ctx->i32_1, "");
3477
3478 LLVMValueRef word1_is_nonzero =
3479 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3480 fmask_word1, ctx->i32_0, "");
3481
3482 /* Replace the MSAA sample index. */
3483 sample_index =
3484 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3485 final_sample, sample_index, "");
3486 return sample_index;
3487 }
3488
3489 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3490 const nir_intrinsic_instr *instr)
3491 {
3492 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3493
3494 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3495 LLVMValueRef coords[4];
3496 LLVMValueRef masks[] = {
3497 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3498 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3499 };
3500 LLVMValueRef res;
3501 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3502
3503 int count;
3504 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3505 bool is_array = glsl_sampler_type_is_array(type);
3506 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3507 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3508 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3509 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3510 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3511 count = image_type_to_components_count(dim, is_array);
3512
3513 if (is_ms) {
3514 LLVMValueRef fmask_load_address[3];
3515 int chan;
3516
3517 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3518 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3519 if (is_array)
3520 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3521 else
3522 fmask_load_address[2] = NULL;
3523 if (add_frag_pos) {
3524 for (chan = 0; chan < 2; ++chan)
3525 fmask_load_address[chan] =
3526 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3527 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3528 ctx->ac.i32, ""), "");
3529 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3530 }
3531 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3532 fmask_load_address[0],
3533 fmask_load_address[1],
3534 fmask_load_address[2],
3535 sample_index,
3536 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3537 }
3538 if (count == 1 && !gfx9_1d) {
3539 if (instr->src[0].ssa->num_components)
3540 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3541 else
3542 res = src0;
3543 } else {
3544 int chan;
3545 if (is_ms)
3546 count--;
3547 for (chan = 0; chan < count; ++chan) {
3548 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3549 }
3550 if (add_frag_pos) {
3551 for (chan = 0; chan < 2; ++chan)
3552 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3553 ctx->ac.i32, ""), "");
3554 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3555 count++;
3556 }
3557
3558 if (gfx9_1d) {
3559 if (is_array) {
3560 coords[2] = coords[1];
3561 coords[1] = ctx->ac.i32_0;
3562 } else
3563 coords[1] = ctx->ac.i32_0;
3564 count++;
3565 }
3566
3567 if (is_ms) {
3568 coords[count] = sample_index;
3569 count++;
3570 }
3571
3572 if (count == 3) {
3573 coords[3] = LLVMGetUndef(ctx->ac.i32);
3574 count = 4;
3575 }
3576 res = ac_build_gather_values(&ctx->ac, coords, count);
3577 }
3578 return res;
3579 }
3580
3581 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3582 const nir_intrinsic_instr *instr)
3583 {
3584 LLVMValueRef params[7];
3585 LLVMValueRef res;
3586 char intrinsic_name[64];
3587 const nir_variable *var = instr->variables[0]->var;
3588 const struct glsl_type *type = var->type;
3589
3590 if(instr->variables[0]->deref.child)
3591 type = instr->variables[0]->deref.child->type;
3592
3593 type = glsl_without_array(type);
3594
3595 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3596 if (dim == GLSL_SAMPLER_DIM_BUF) {
3597 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3598 unsigned num_channels = util_last_bit(mask);
3599 LLVMValueRef rsrc, vindex;
3600
3601 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3602 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3603 ctx->ac.i32_0, "");
3604
3605 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3606 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3607 ctx->ac.i32_0, num_channels,
3608 false, false);
3609 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3610
3611 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3612 res = ac_to_integer(&ctx->ac, res);
3613 } else {
3614 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3615 LLVMValueRef slc = ctx->ac.i1false;
3616
3617 params[0] = get_image_coords(ctx, instr);
3618 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3619 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3620 params[3] = (var->data.image._volatile || var->data.image.coherent) ?
3621 ctx->ac.i1true : ctx->ac.i1false;
3622 params[4] = slc;
3623 params[5] = ctx->ac.i1false;
3624 params[6] = da;
3625
3626 ac_get_image_intr_name("llvm.amdgcn.image.load",
3627 ctx->ac.v4f32, /* vdata */
3628 LLVMTypeOf(params[0]), /* coords */
3629 LLVMTypeOf(params[1]), /* rsrc */
3630 intrinsic_name, sizeof(intrinsic_name));
3631
3632 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3633 params, 7, AC_FUNC_ATTR_READONLY);
3634 }
3635 return ac_to_integer(&ctx->ac, res);
3636 }
3637
3638 static void visit_image_store(struct ac_nir_context *ctx,
3639 nir_intrinsic_instr *instr)
3640 {
3641 LLVMValueRef params[8];
3642 char intrinsic_name[64];
3643 const nir_variable *var = instr->variables[0]->var;
3644 const struct glsl_type *type = glsl_without_array(var->type);
3645 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3646 LLVMValueRef glc = ctx->ac.i1false;
3647 bool force_glc = ctx->ac.chip_class == SI;
3648 if (force_glc)
3649 glc = ctx->ac.i1true;
3650
3651 if (dim == GLSL_SAMPLER_DIM_BUF) {
3652 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3653 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3654 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3655 ctx->ac.i32_0, ""); /* vindex */
3656 params[3] = ctx->ac.i32_0; /* voffset */
3657 params[4] = glc; /* glc */
3658 params[5] = ctx->ac.i1false; /* slc */
3659 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3660 params, 6, 0);
3661 } else {
3662 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3663 LLVMValueRef slc = ctx->ac.i1false;
3664
3665 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3666 params[1] = get_image_coords(ctx, instr); /* coords */
3667 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3668 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3669 params[4] = (force_glc || var->data.image._volatile || var->data.image.coherent) ?
3670 ctx->ac.i1true : ctx->ac.i1false;
3671 params[5] = slc;
3672 params[6] = ctx->ac.i1false;
3673 params[7] = da;
3674
3675 ac_get_image_intr_name("llvm.amdgcn.image.store",
3676 LLVMTypeOf(params[0]), /* vdata */
3677 LLVMTypeOf(params[1]), /* coords */
3678 LLVMTypeOf(params[2]), /* rsrc */
3679 intrinsic_name, sizeof(intrinsic_name));
3680
3681 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3682 params, 8, 0);
3683 }
3684
3685 }
3686
3687 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3688 const nir_intrinsic_instr *instr)
3689 {
3690 LLVMValueRef params[7];
3691 int param_count = 0;
3692 const nir_variable *var = instr->variables[0]->var;
3693
3694 const char *atomic_name;
3695 char intrinsic_name[41];
3696 const struct glsl_type *type = glsl_without_array(var->type);
3697 MAYBE_UNUSED int length;
3698
3699 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3700
3701 switch (instr->intrinsic) {
3702 case nir_intrinsic_image_atomic_add:
3703 atomic_name = "add";
3704 break;
3705 case nir_intrinsic_image_atomic_min:
3706 atomic_name = is_unsigned ? "umin" : "smin";
3707 break;
3708 case nir_intrinsic_image_atomic_max:
3709 atomic_name = is_unsigned ? "umax" : "smax";
3710 break;
3711 case nir_intrinsic_image_atomic_and:
3712 atomic_name = "and";
3713 break;
3714 case nir_intrinsic_image_atomic_or:
3715 atomic_name = "or";
3716 break;
3717 case nir_intrinsic_image_atomic_xor:
3718 atomic_name = "xor";
3719 break;
3720 case nir_intrinsic_image_atomic_exchange:
3721 atomic_name = "swap";
3722 break;
3723 case nir_intrinsic_image_atomic_comp_swap:
3724 atomic_name = "cmpswap";
3725 break;
3726 default:
3727 abort();
3728 }
3729
3730 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3731 params[param_count++] = get_src(ctx, instr->src[3]);
3732 params[param_count++] = get_src(ctx, instr->src[2]);
3733
3734 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3735 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3736 NULL, true, true);
3737 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3738 ctx->ac.i32_0, ""); /* vindex */
3739 params[param_count++] = ctx->ac.i32_0; /* voffset */
3740 params[param_count++] = ctx->ac.i1false; /* slc */
3741
3742 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3743 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3744 } else {
3745 char coords_type[8];
3746
3747 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3748 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3749 NULL, true, true);
3750 params[param_count++] = ctx->ac.i1false; /* r128 */
3751 params[param_count++] = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3752 params[param_count++] = ctx->ac.i1false; /* slc */
3753
3754 build_int_type_name(LLVMTypeOf(coords),
3755 coords_type, sizeof(coords_type));
3756
3757 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3758 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3759 }
3760
3761 assert(length < sizeof(intrinsic_name));
3762 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3763 }
3764
3765 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3766 const nir_intrinsic_instr *instr)
3767 {
3768 const nir_variable *var = instr->variables[0]->var;
3769 const struct glsl_type *type = glsl_without_array(var->type);
3770
3771 struct ac_image_args args = { 0 };
3772 args.da = glsl_is_array_image(type);
3773 args.dmask = 0xf;
3774 args.resource = get_sampler_desc(ctx, instr->variables[0],
3775 AC_DESC_IMAGE, NULL, true, false);
3776 args.opcode = ac_image_get_resinfo;
3777 args.addr = ctx->ac.i32_0;
3778
3779 return ac_build_image_opcode(&ctx->ac, &args);
3780 }
3781
3782 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3783 const nir_intrinsic_instr *instr)
3784 {
3785 LLVMValueRef res;
3786 const nir_variable *var = instr->variables[0]->var;
3787 const struct glsl_type *type = glsl_without_array(var->type);
3788
3789 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3790 return get_buffer_size(ctx,
3791 get_sampler_desc(ctx, instr->variables[0],
3792 AC_DESC_BUFFER, NULL, true, false), true);
3793
3794 struct ac_image_args args = { 0 };
3795
3796 args.da = glsl_is_array_image(type);
3797 args.dmask = 0xf;
3798 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3799 args.opcode = ac_image_get_resinfo;
3800 args.addr = ctx->ac.i32_0;
3801
3802 res = ac_build_image_opcode(&ctx->ac, &args);
3803
3804 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3805
3806 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3807 glsl_sampler_type_is_array(type)) {
3808 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3809 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3810 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3811 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3812 }
3813 if (ctx->ac.chip_class >= GFX9 &&
3814 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3815 glsl_sampler_type_is_array(type)) {
3816 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3817 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3818 ctx->ac.i32_1, "");
3819
3820 }
3821 return res;
3822 }
3823
3824 #define NOOP_WAITCNT 0xf7f
3825 #define LGKM_CNT 0x07f
3826 #define VM_CNT 0xf70
3827
3828 static void emit_membar(struct ac_llvm_context *ac,
3829 const nir_intrinsic_instr *instr)
3830 {
3831 unsigned waitcnt = NOOP_WAITCNT;
3832
3833 switch (instr->intrinsic) {
3834 case nir_intrinsic_memory_barrier:
3835 case nir_intrinsic_group_memory_barrier:
3836 waitcnt &= VM_CNT & LGKM_CNT;
3837 break;
3838 case nir_intrinsic_memory_barrier_atomic_counter:
3839 case nir_intrinsic_memory_barrier_buffer:
3840 case nir_intrinsic_memory_barrier_image:
3841 waitcnt &= VM_CNT;
3842 break;
3843 case nir_intrinsic_memory_barrier_shared:
3844 waitcnt &= LGKM_CNT;
3845 break;
3846 default:
3847 break;
3848 }
3849 if (waitcnt != NOOP_WAITCNT)
3850 ac_build_waitcnt(ac, waitcnt);
3851 }
3852
3853 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3854 {
3855 /* SI only (thanks to a hw bug workaround):
3856 * The real barrier instruction isn’t needed, because an entire patch
3857 * always fits into a single wave.
3858 */
3859 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3860 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3861 return;
3862 }
3863 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3864 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3865 }
3866
3867 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
3868 {
3869 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3870 ac_build_kill_if_false(&ctx->ac, visible);
3871 }
3872
3873 static void emit_discard(struct ac_nir_context *ctx,
3874 const nir_intrinsic_instr *instr)
3875 {
3876 LLVMValueRef cond;
3877
3878 if (instr->intrinsic == nir_intrinsic_discard_if) {
3879 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3880 get_src(ctx, instr->src[0]),
3881 ctx->ac.i32_0, "");
3882 } else {
3883 assert(instr->intrinsic == nir_intrinsic_discard);
3884 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3885 }
3886
3887 ctx->abi->emit_kill(ctx->abi, cond);
3888 }
3889
3890 static LLVMValueRef
3891 visit_load_helper_invocation(struct ac_nir_context *ctx)
3892 {
3893 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3894 "llvm.amdgcn.ps.live",
3895 ctx->ac.i1, NULL, 0,
3896 AC_FUNC_ATTR_READNONE);
3897 result = LLVMBuildNot(ctx->ac.builder, result, "");
3898 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3899 }
3900
3901 static LLVMValueRef
3902 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3903 {
3904 LLVMValueRef result;
3905 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3906 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3907 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3908
3909 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3910 }
3911
3912 static LLVMValueRef
3913 visit_load_subgroup_id(struct ac_nir_context *ctx)
3914 {
3915 if (ctx->stage == MESA_SHADER_COMPUTE) {
3916 LLVMValueRef result;
3917 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3918 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3919 return LLVMBuildLShr(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 6, false), "");
3920 } else {
3921 return LLVMConstInt(ctx->ac.i32, 0, false);
3922 }
3923 }
3924
3925 static LLVMValueRef
3926 visit_load_num_subgroups(struct ac_nir_context *ctx)
3927 {
3928 if (ctx->stage == MESA_SHADER_COMPUTE) {
3929 return LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3930 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
3931 } else {
3932 return LLVMConstInt(ctx->ac.i32, 1, false);
3933 }
3934 }
3935
3936 static LLVMValueRef
3937 visit_first_invocation(struct ac_nir_context *ctx)
3938 {
3939 LLVMValueRef active_set = ac_build_ballot(&ctx->ac, ctx->ac.i32_1);
3940
3941 /* The second argument is whether cttz(0) should be defined, but we do not care. */
3942 LLVMValueRef args[] = {active_set, LLVMConstInt(ctx->ac.i1, 0, false)};
3943 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3944 "llvm.cttz.i64",
3945 ctx->ac.i64, args, 2,
3946 AC_FUNC_ATTR_NOUNWIND |
3947 AC_FUNC_ATTR_READNONE);
3948
3949 return LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
3950 }
3951
3952 static LLVMValueRef
3953 visit_load_shared(struct ac_nir_context *ctx,
3954 const nir_intrinsic_instr *instr)
3955 {
3956 LLVMValueRef values[4], derived_ptr, index, ret;
3957
3958 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3959
3960 for (int chan = 0; chan < instr->num_components; chan++) {
3961 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3962 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3963 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3964 }
3965
3966 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3967 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3968 }
3969
3970 static void
3971 visit_store_shared(struct ac_nir_context *ctx,
3972 const nir_intrinsic_instr *instr)
3973 {
3974 LLVMValueRef derived_ptr, data,index;
3975 LLVMBuilderRef builder = ctx->ac.builder;
3976
3977 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3978 LLVMValueRef src = get_src(ctx, instr->src[0]);
3979
3980 int writemask = nir_intrinsic_write_mask(instr);
3981 for (int chan = 0; chan < 4; chan++) {
3982 if (!(writemask & (1 << chan))) {
3983 continue;
3984 }
3985 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3986 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3987 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3988 LLVMBuildStore(builder, data, derived_ptr);
3989 }
3990 }
3991
3992 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3993 const nir_intrinsic_instr *instr,
3994 LLVMValueRef ptr, int src_idx)
3995 {
3996 LLVMValueRef result;
3997 LLVMValueRef src = get_src(ctx, instr->src[src_idx]);
3998
3999 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
4000 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
4001 LLVMValueRef src1 = get_src(ctx, instr->src[src_idx + 1]);
4002 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
4003 ptr, src, src1,
4004 LLVMAtomicOrderingSequentiallyConsistent,
4005 LLVMAtomicOrderingSequentiallyConsistent,
4006 false);
4007 } else {
4008 LLVMAtomicRMWBinOp op;
4009 switch (instr->intrinsic) {
4010 case nir_intrinsic_var_atomic_add:
4011 case nir_intrinsic_shared_atomic_add:
4012 op = LLVMAtomicRMWBinOpAdd;
4013 break;
4014 case nir_intrinsic_var_atomic_umin:
4015 case nir_intrinsic_shared_atomic_umin:
4016 op = LLVMAtomicRMWBinOpUMin;
4017 break;
4018 case nir_intrinsic_var_atomic_umax:
4019 case nir_intrinsic_shared_atomic_umax:
4020 op = LLVMAtomicRMWBinOpUMax;
4021 break;
4022 case nir_intrinsic_var_atomic_imin:
4023 case nir_intrinsic_shared_atomic_imin:
4024 op = LLVMAtomicRMWBinOpMin;
4025 break;
4026 case nir_intrinsic_var_atomic_imax:
4027 case nir_intrinsic_shared_atomic_imax:
4028 op = LLVMAtomicRMWBinOpMax;
4029 break;
4030 case nir_intrinsic_var_atomic_and:
4031 case nir_intrinsic_shared_atomic_and:
4032 op = LLVMAtomicRMWBinOpAnd;
4033 break;
4034 case nir_intrinsic_var_atomic_or:
4035 case nir_intrinsic_shared_atomic_or:
4036 op = LLVMAtomicRMWBinOpOr;
4037 break;
4038 case nir_intrinsic_var_atomic_xor:
4039 case nir_intrinsic_shared_atomic_xor:
4040 op = LLVMAtomicRMWBinOpXor;
4041 break;
4042 case nir_intrinsic_var_atomic_exchange:
4043 case nir_intrinsic_shared_atomic_exchange:
4044 op = LLVMAtomicRMWBinOpXchg;
4045 break;
4046 default:
4047 return NULL;
4048 }
4049
4050 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4051 LLVMAtomicOrderingSequentiallyConsistent,
4052 false);
4053 }
4054 return result;
4055 }
4056
4057 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4058 enum glsl_interp_mode interp, unsigned location)
4059 {
4060 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4061
4062 switch (interp) {
4063 case INTERP_MODE_FLAT:
4064 default:
4065 return NULL;
4066 case INTERP_MODE_SMOOTH:
4067 case INTERP_MODE_NONE:
4068 if (location == INTERP_CENTER)
4069 return ctx->persp_center;
4070 else if (location == INTERP_CENTROID)
4071 return ctx->persp_centroid;
4072 else if (location == INTERP_SAMPLE)
4073 return ctx->persp_sample;
4074 break;
4075 case INTERP_MODE_NOPERSPECTIVE:
4076 if (location == INTERP_CENTER)
4077 return ctx->linear_center;
4078 else if (location == INTERP_CENTROID)
4079 return ctx->linear_centroid;
4080 else if (location == INTERP_SAMPLE)
4081 return ctx->linear_sample;
4082 break;
4083 }
4084 return NULL;
4085 }
4086
4087 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4088 LLVMValueRef sample_id)
4089 {
4090 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4091
4092 LLVMValueRef result;
4093 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4094
4095 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4096 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4097
4098 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4099 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4100
4101 return result;
4102 }
4103
4104 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4105 {
4106 LLVMValueRef values[2];
4107 LLVMValueRef pos[2];
4108
4109 pos[0] = ac_to_float(&ctx->ac, ctx->abi->frag_pos[0]);
4110 pos[1] = ac_to_float(&ctx->ac, ctx->abi->frag_pos[1]);
4111
4112 values[0] = ac_build_fract(&ctx->ac, pos[0], 32);
4113 values[1] = ac_build_fract(&ctx->ac, pos[1], 32);
4114 return ac_build_gather_values(&ctx->ac, values, 2);
4115 }
4116
4117 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4118 {
4119 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4120 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4121 ctx->options->key.fs.log2_num_samples :
4122 ctx->options->key.fs.log2_ps_iter_samples;
4123
4124 /* The bit pattern matches that used by fixed function fragment
4125 * processing. */
4126 static const uint16_t ps_iter_masks[] = {
4127 0xffff, /* not used */
4128 0x5555,
4129 0x1111,
4130 0x0101,
4131 0x0001,
4132 };
4133 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4134
4135 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4136
4137 LLVMValueRef result, sample_id;
4138 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4139 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4140 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4141 return result;
4142 }
4143
4144 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4145 const nir_intrinsic_instr *instr)
4146 {
4147 LLVMValueRef result[4];
4148 LLVMValueRef interp_param, attr_number;
4149 unsigned location;
4150 unsigned chan;
4151 LLVMValueRef src_c0 = NULL;
4152 LLVMValueRef src_c1 = NULL;
4153 LLVMValueRef src0 = NULL;
4154 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4155 switch (instr->intrinsic) {
4156 case nir_intrinsic_interp_var_at_centroid:
4157 location = INTERP_CENTROID;
4158 break;
4159 case nir_intrinsic_interp_var_at_sample:
4160 case nir_intrinsic_interp_var_at_offset:
4161 location = INTERP_CENTER;
4162 src0 = get_src(ctx, instr->src[0]);
4163 break;
4164 default:
4165 break;
4166 }
4167
4168 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4169 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4170 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4171 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4172 LLVMValueRef sample_position;
4173 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4174
4175 /* fetch sample ID */
4176 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4177
4178 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4179 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4180 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4181 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4182 }
4183 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4184 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4185
4186 if (location == INTERP_CENTER) {
4187 LLVMValueRef ij_out[2];
4188 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4189
4190 /*
4191 * take the I then J parameters, and the DDX/Y for it, and
4192 * calculate the IJ inputs for the interpolator.
4193 * temp1 = ddx * offset/sample.x + I;
4194 * interp_param.I = ddy * offset/sample.y + temp1;
4195 * temp1 = ddx * offset/sample.x + J;
4196 * interp_param.J = ddy * offset/sample.y + temp1;
4197 */
4198 for (unsigned i = 0; i < 2; i++) {
4199 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4200 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4201 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4202 ddxy_out, ix_ll, "");
4203 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4204 ddxy_out, iy_ll, "");
4205 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4206 interp_param, ix_ll, "");
4207 LLVMValueRef temp1, temp2;
4208
4209 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4210 ctx->ac.f32, "");
4211
4212 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4213 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4214
4215 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4216 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4217
4218 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4219 temp2, ctx->ac.i32, "");
4220 }
4221 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4222
4223 }
4224
4225 for (chan = 0; chan < 4; chan++) {
4226 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4227
4228 if (interp_param) {
4229 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4230 interp_param, ctx->ac.v2f32, "");
4231 LLVMValueRef i = LLVMBuildExtractElement(
4232 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4233 LLVMValueRef j = LLVMBuildExtractElement(
4234 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4235
4236 result[chan] = ac_build_fs_interp(&ctx->ac,
4237 llvm_chan, attr_number,
4238 ctx->abi->prim_mask, i, j);
4239 } else {
4240 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4241 LLVMConstInt(ctx->ac.i32, 2, false),
4242 llvm_chan, attr_number,
4243 ctx->abi->prim_mask);
4244 }
4245 }
4246 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4247 instr->variables[0]->var->data.location_frac);
4248 }
4249
4250 static void
4251 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4252 {
4253 LLVMValueRef gs_next_vertex;
4254 LLVMValueRef can_emit;
4255 int idx;
4256 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4257
4258 assert(stream == 0);
4259
4260 /* Write vertex attribute values to GSVS ring */
4261 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4262 ctx->gs_next_vertex,
4263 "");
4264
4265 /* If this thread has already emitted the declared maximum number of
4266 * vertices, kill it: excessive vertex emissions are not supposed to
4267 * have any effect, and GS threads have no externally observable
4268 * effects other than emitting vertices.
4269 */
4270 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4271 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4272 ac_build_kill_if_false(&ctx->ac, can_emit);
4273
4274 /* loop num outputs */
4275 idx = 0;
4276 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4277 LLVMValueRef *out_ptr = &addrs[i * 4];
4278 int length = 4;
4279 int slot = idx;
4280 int slot_inc = 1;
4281
4282 if (!(ctx->output_mask & (1ull << i)))
4283 continue;
4284
4285 if (i == VARYING_SLOT_CLIP_DIST0) {
4286 /* pack clip and cull into a single set of slots */
4287 length = ctx->num_output_clips + ctx->num_output_culls;
4288 if (length > 4)
4289 slot_inc = 2;
4290 }
4291 for (unsigned j = 0; j < length; j++) {
4292 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4293 out_ptr[j], "");
4294 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4295 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4296 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4297
4298 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4299
4300 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4301 out_val, 1,
4302 voffset, ctx->gs2vs_offset, 0,
4303 1, 1, true, true);
4304 }
4305 idx += slot_inc;
4306 }
4307
4308 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4309 ctx->ac.i32_1, "");
4310 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4311
4312 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4313 }
4314
4315 static void
4316 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4317 {
4318 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4319 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4320 }
4321
4322 static LLVMValueRef
4323 load_tess_coord(struct ac_shader_abi *abi)
4324 {
4325 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4326
4327 LLVMValueRef coord[4] = {
4328 ctx->tes_u,
4329 ctx->tes_v,
4330 ctx->ac.f32_0,
4331 ctx->ac.f32_0,
4332 };
4333
4334 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4335 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4336 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4337
4338 return ac_build_gather_values(&ctx->ac, coord, 3);
4339 }
4340
4341 static LLVMValueRef
4342 load_patch_vertices_in(struct ac_shader_abi *abi)
4343 {
4344 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4345 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4346 }
4347
4348 static void visit_intrinsic(struct ac_nir_context *ctx,
4349 nir_intrinsic_instr *instr)
4350 {
4351 LLVMValueRef result = NULL;
4352
4353 switch (instr->intrinsic) {
4354 case nir_intrinsic_ballot:
4355 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4356 break;
4357 case nir_intrinsic_read_invocation:
4358 case nir_intrinsic_read_first_invocation: {
4359 LLVMValueRef args[2];
4360
4361 /* Value */
4362 args[0] = get_src(ctx, instr->src[0]);
4363
4364 unsigned num_args;
4365 const char *intr_name;
4366 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4367 num_args = 2;
4368 intr_name = "llvm.amdgcn.readlane";
4369
4370 /* Invocation */
4371 args[1] = get_src(ctx, instr->src[1]);
4372 } else {
4373 num_args = 1;
4374 intr_name = "llvm.amdgcn.readfirstlane";
4375 }
4376
4377 /* We currently have no other way to prevent LLVM from lifting the icmp
4378 * calls to a dominating basic block.
4379 */
4380 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4381
4382 result = ac_build_intrinsic(&ctx->ac, intr_name,
4383 ctx->ac.i32, args, num_args,
4384 AC_FUNC_ATTR_READNONE |
4385 AC_FUNC_ATTR_CONVERGENT);
4386 break;
4387 }
4388 case nir_intrinsic_load_subgroup_invocation:
4389 result = ac_get_thread_id(&ctx->ac);
4390 break;
4391 case nir_intrinsic_load_work_group_id: {
4392 LLVMValueRef values[3];
4393
4394 for (int i = 0; i < 3; i++) {
4395 values[i] = ctx->abi->workgroup_ids[i] ?
4396 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4397 }
4398
4399 result = ac_build_gather_values(&ctx->ac, values, 3);
4400 break;
4401 }
4402 case nir_intrinsic_load_base_vertex: {
4403 result = ctx->abi->load_base_vertex(ctx->abi);
4404 break;
4405 }
4406 case nir_intrinsic_load_local_group_size:
4407 result = ctx->abi->load_local_group_size(ctx->abi);
4408 break;
4409 case nir_intrinsic_load_vertex_id:
4410 result = LLVMBuildAdd(ctx->ac.builder, ctx->abi->vertex_id,
4411 ctx->abi->base_vertex, "");
4412 break;
4413 case nir_intrinsic_load_vertex_id_zero_base: {
4414 result = ctx->abi->vertex_id;
4415 break;
4416 }
4417 case nir_intrinsic_load_local_invocation_id: {
4418 result = ctx->abi->local_invocation_ids;
4419 break;
4420 }
4421 case nir_intrinsic_load_base_instance:
4422 result = ctx->abi->start_instance;
4423 break;
4424 case nir_intrinsic_load_draw_id:
4425 result = ctx->abi->draw_id;
4426 break;
4427 case nir_intrinsic_load_view_index:
4428 result = ctx->abi->view_index;
4429 break;
4430 case nir_intrinsic_load_invocation_id:
4431 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4432 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4433 else
4434 result = ctx->abi->gs_invocation_id;
4435 break;
4436 case nir_intrinsic_load_primitive_id:
4437 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4438 result = ctx->abi->gs_prim_id;
4439 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4440 result = ctx->abi->tcs_patch_id;
4441 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4442 result = ctx->abi->tes_patch_id;
4443 } else
4444 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4445 break;
4446 case nir_intrinsic_load_sample_id:
4447 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4448 break;
4449 case nir_intrinsic_load_sample_pos:
4450 result = load_sample_pos(ctx);
4451 break;
4452 case nir_intrinsic_load_sample_mask_in:
4453 result = ctx->abi->load_sample_mask_in(ctx->abi);
4454 break;
4455 case nir_intrinsic_load_frag_coord: {
4456 LLVMValueRef values[4] = {
4457 ctx->abi->frag_pos[0],
4458 ctx->abi->frag_pos[1],
4459 ctx->abi->frag_pos[2],
4460 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4461 };
4462 result = ac_build_gather_values(&ctx->ac, values, 4);
4463 break;
4464 }
4465 case nir_intrinsic_load_front_face:
4466 result = ctx->abi->front_face;
4467 break;
4468 case nir_intrinsic_load_helper_invocation:
4469 result = visit_load_helper_invocation(ctx);
4470 break;
4471 case nir_intrinsic_load_instance_id:
4472 result = ctx->abi->instance_id;
4473 break;
4474 case nir_intrinsic_load_num_work_groups:
4475 result = ctx->abi->num_work_groups;
4476 break;
4477 case nir_intrinsic_load_local_invocation_index:
4478 result = visit_load_local_invocation_index(ctx);
4479 break;
4480 case nir_intrinsic_load_subgroup_id:
4481 result = visit_load_subgroup_id(ctx);
4482 break;
4483 case nir_intrinsic_load_num_subgroups:
4484 result = visit_load_num_subgroups(ctx);
4485 break;
4486 case nir_intrinsic_first_invocation:
4487 result = visit_first_invocation(ctx);
4488 break;
4489 case nir_intrinsic_load_push_constant:
4490 result = visit_load_push_constant(ctx, instr);
4491 break;
4492 case nir_intrinsic_vulkan_resource_index: {
4493 LLVMValueRef index = get_src(ctx, instr->src[0]);
4494 unsigned desc_set = nir_intrinsic_desc_set(instr);
4495 unsigned binding = nir_intrinsic_binding(instr);
4496
4497 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4498 binding);
4499 break;
4500 }
4501 case nir_intrinsic_vulkan_resource_reindex:
4502 result = visit_vulkan_resource_reindex(ctx, instr);
4503 break;
4504 case nir_intrinsic_store_ssbo:
4505 visit_store_ssbo(ctx, instr);
4506 break;
4507 case nir_intrinsic_load_ssbo:
4508 result = visit_load_buffer(ctx, instr);
4509 break;
4510 case nir_intrinsic_ssbo_atomic_add:
4511 case nir_intrinsic_ssbo_atomic_imin:
4512 case nir_intrinsic_ssbo_atomic_umin:
4513 case nir_intrinsic_ssbo_atomic_imax:
4514 case nir_intrinsic_ssbo_atomic_umax:
4515 case nir_intrinsic_ssbo_atomic_and:
4516 case nir_intrinsic_ssbo_atomic_or:
4517 case nir_intrinsic_ssbo_atomic_xor:
4518 case nir_intrinsic_ssbo_atomic_exchange:
4519 case nir_intrinsic_ssbo_atomic_comp_swap:
4520 result = visit_atomic_ssbo(ctx, instr);
4521 break;
4522 case nir_intrinsic_load_ubo:
4523 result = visit_load_ubo_buffer(ctx, instr);
4524 break;
4525 case nir_intrinsic_get_buffer_size:
4526 result = visit_get_buffer_size(ctx, instr);
4527 break;
4528 case nir_intrinsic_load_var:
4529 result = visit_load_var(ctx, instr);
4530 break;
4531 case nir_intrinsic_store_var:
4532 visit_store_var(ctx, instr);
4533 break;
4534 case nir_intrinsic_load_shared:
4535 result = visit_load_shared(ctx, instr);
4536 break;
4537 case nir_intrinsic_store_shared:
4538 visit_store_shared(ctx, instr);
4539 break;
4540 case nir_intrinsic_image_samples:
4541 result = visit_image_samples(ctx, instr);
4542 break;
4543 case nir_intrinsic_image_load:
4544 result = visit_image_load(ctx, instr);
4545 break;
4546 case nir_intrinsic_image_store:
4547 visit_image_store(ctx, instr);
4548 break;
4549 case nir_intrinsic_image_atomic_add:
4550 case nir_intrinsic_image_atomic_min:
4551 case nir_intrinsic_image_atomic_max:
4552 case nir_intrinsic_image_atomic_and:
4553 case nir_intrinsic_image_atomic_or:
4554 case nir_intrinsic_image_atomic_xor:
4555 case nir_intrinsic_image_atomic_exchange:
4556 case nir_intrinsic_image_atomic_comp_swap:
4557 result = visit_image_atomic(ctx, instr);
4558 break;
4559 case nir_intrinsic_image_size:
4560 result = visit_image_size(ctx, instr);
4561 break;
4562 case nir_intrinsic_shader_clock:
4563 result = ac_build_shader_clock(&ctx->ac);
4564 break;
4565 case nir_intrinsic_discard:
4566 case nir_intrinsic_discard_if:
4567 emit_discard(ctx, instr);
4568 break;
4569 case nir_intrinsic_memory_barrier:
4570 case nir_intrinsic_group_memory_barrier:
4571 case nir_intrinsic_memory_barrier_atomic_counter:
4572 case nir_intrinsic_memory_barrier_buffer:
4573 case nir_intrinsic_memory_barrier_image:
4574 case nir_intrinsic_memory_barrier_shared:
4575 emit_membar(&ctx->ac, instr);
4576 break;
4577 case nir_intrinsic_barrier:
4578 emit_barrier(&ctx->ac, ctx->stage);
4579 break;
4580 case nir_intrinsic_shared_atomic_add:
4581 case nir_intrinsic_shared_atomic_imin:
4582 case nir_intrinsic_shared_atomic_umin:
4583 case nir_intrinsic_shared_atomic_imax:
4584 case nir_intrinsic_shared_atomic_umax:
4585 case nir_intrinsic_shared_atomic_and:
4586 case nir_intrinsic_shared_atomic_or:
4587 case nir_intrinsic_shared_atomic_xor:
4588 case nir_intrinsic_shared_atomic_exchange:
4589 case nir_intrinsic_shared_atomic_comp_swap: {
4590 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
4591 result = visit_var_atomic(ctx, instr, ptr, 1);
4592 break;
4593 }
4594 case nir_intrinsic_var_atomic_add:
4595 case nir_intrinsic_var_atomic_imin:
4596 case nir_intrinsic_var_atomic_umin:
4597 case nir_intrinsic_var_atomic_imax:
4598 case nir_intrinsic_var_atomic_umax:
4599 case nir_intrinsic_var_atomic_and:
4600 case nir_intrinsic_var_atomic_or:
4601 case nir_intrinsic_var_atomic_xor:
4602 case nir_intrinsic_var_atomic_exchange:
4603 case nir_intrinsic_var_atomic_comp_swap: {
4604 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4605 result = visit_var_atomic(ctx, instr, ptr, 0);
4606 break;
4607 }
4608 case nir_intrinsic_interp_var_at_centroid:
4609 case nir_intrinsic_interp_var_at_sample:
4610 case nir_intrinsic_interp_var_at_offset:
4611 result = visit_interp(ctx, instr);
4612 break;
4613 case nir_intrinsic_emit_vertex:
4614 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4615 break;
4616 case nir_intrinsic_end_primitive:
4617 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4618 break;
4619 case nir_intrinsic_load_tess_coord:
4620 result = ctx->abi->load_tess_coord(ctx->abi);
4621 break;
4622 case nir_intrinsic_load_tess_level_outer:
4623 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4624 break;
4625 case nir_intrinsic_load_tess_level_inner:
4626 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4627 break;
4628 case nir_intrinsic_load_patch_vertices_in:
4629 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4630 break;
4631 case nir_intrinsic_vote_all: {
4632 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4633 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4634 break;
4635 }
4636 case nir_intrinsic_vote_any: {
4637 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4638 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4639 break;
4640 }
4641 default:
4642 fprintf(stderr, "Unknown intrinsic: ");
4643 nir_print_instr(&instr->instr, stderr);
4644 fprintf(stderr, "\n");
4645 break;
4646 }
4647 if (result) {
4648 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4649 }
4650 }
4651
4652 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
4653 {
4654 return abi->base_vertex;
4655 }
4656
4657 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4658 LLVMValueRef buffer_ptr, bool write)
4659 {
4660 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4661 LLVMValueRef result;
4662
4663 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4664
4665 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4666 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4667
4668 return result;
4669 }
4670
4671 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4672 {
4673 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4674 LLVMValueRef result;
4675
4676 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4677
4678 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4679 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4680
4681 return result;
4682 }
4683
4684 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4685 unsigned descriptor_set,
4686 unsigned base_index,
4687 unsigned constant_index,
4688 LLVMValueRef index,
4689 enum ac_descriptor_type desc_type,
4690 bool image, bool write)
4691 {
4692 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4693 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4694 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4695 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4696 unsigned offset = binding->offset;
4697 unsigned stride = binding->size;
4698 unsigned type_size;
4699 LLVMBuilderRef builder = ctx->ac.builder;
4700 LLVMTypeRef type;
4701
4702 assert(base_index < layout->binding_count);
4703
4704 switch (desc_type) {
4705 case AC_DESC_IMAGE:
4706 type = ctx->ac.v8i32;
4707 type_size = 32;
4708 break;
4709 case AC_DESC_FMASK:
4710 type = ctx->ac.v8i32;
4711 offset += 32;
4712 type_size = 32;
4713 break;
4714 case AC_DESC_SAMPLER:
4715 type = ctx->ac.v4i32;
4716 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4717 offset += 64;
4718
4719 type_size = 16;
4720 break;
4721 case AC_DESC_BUFFER:
4722 type = ctx->ac.v4i32;
4723 type_size = 16;
4724 break;
4725 default:
4726 unreachable("invalid desc_type\n");
4727 }
4728
4729 offset += constant_index * stride;
4730
4731 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4732 (!index || binding->immutable_samplers_equal)) {
4733 if (binding->immutable_samplers_equal)
4734 constant_index = 0;
4735
4736 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4737
4738 LLVMValueRef constants[] = {
4739 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4740 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4741 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4742 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4743 };
4744 return ac_build_gather_values(&ctx->ac, constants, 4);
4745 }
4746
4747 assert(stride % type_size == 0);
4748
4749 if (!index)
4750 index = ctx->ac.i32_0;
4751
4752 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4753
4754 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4755 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4756
4757 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4758 }
4759
4760 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4761 const nir_deref_var *deref,
4762 enum ac_descriptor_type desc_type,
4763 const nir_tex_instr *tex_instr,
4764 bool image, bool write)
4765 {
4766 LLVMValueRef index = NULL;
4767 unsigned constant_index = 0;
4768 unsigned descriptor_set;
4769 unsigned base_index;
4770
4771 if (!deref) {
4772 assert(tex_instr && !image);
4773 descriptor_set = 0;
4774 base_index = tex_instr->sampler_index;
4775 } else {
4776 const nir_deref *tail = &deref->deref;
4777 while (tail->child) {
4778 const nir_deref_array *child = nir_deref_as_array(tail->child);
4779 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4780
4781 if (!array_size)
4782 array_size = 1;
4783
4784 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4785
4786 if (child->deref_array_type == nir_deref_array_type_indirect) {
4787 LLVMValueRef indirect = get_src(ctx, child->indirect);
4788
4789 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4790 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4791
4792 if (!index)
4793 index = indirect;
4794 else
4795 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4796 }
4797
4798 constant_index += child->base_offset * array_size;
4799
4800 tail = &child->deref;
4801 }
4802 descriptor_set = deref->var->data.descriptor_set;
4803 base_index = deref->var->data.binding;
4804 }
4805
4806 return ctx->abi->load_sampler_desc(ctx->abi,
4807 descriptor_set,
4808 base_index,
4809 constant_index, index,
4810 desc_type, image, write);
4811 }
4812
4813 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4814 struct ac_image_args *args,
4815 const nir_tex_instr *instr,
4816 nir_texop op,
4817 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4818 LLVMValueRef *param, unsigned count,
4819 unsigned dmask)
4820 {
4821 unsigned is_rect = 0;
4822 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4823
4824 if (op == nir_texop_lod)
4825 da = false;
4826 /* Pad to power of two vector */
4827 while (count < util_next_power_of_two(count))
4828 param[count++] = LLVMGetUndef(ctx->i32);
4829
4830 if (count > 1)
4831 args->addr = ac_build_gather_values(ctx, param, count);
4832 else
4833 args->addr = param[0];
4834
4835 args->resource = res_ptr;
4836 args->sampler = samp_ptr;
4837
4838 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4839 args->addr = param[0];
4840 return;
4841 }
4842
4843 args->dmask = dmask;
4844 args->unorm = is_rect;
4845 args->da = da;
4846 }
4847
4848 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4849 *
4850 * SI-CI:
4851 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4852 * filtering manually. The driver sets img7 to a mask clearing
4853 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4854 * s_and_b32 samp0, samp0, img7
4855 *
4856 * VI:
4857 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4858 */
4859 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4860 LLVMValueRef res, LLVMValueRef samp)
4861 {
4862 LLVMBuilderRef builder = ctx->ac.builder;
4863 LLVMValueRef img7, samp0;
4864
4865 if (ctx->ac.chip_class >= VI)
4866 return samp;
4867
4868 img7 = LLVMBuildExtractElement(builder, res,
4869 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4870 samp0 = LLVMBuildExtractElement(builder, samp,
4871 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4872 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4873 return LLVMBuildInsertElement(builder, samp, samp0,
4874 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4875 }
4876
4877 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4878 nir_tex_instr *instr,
4879 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4880 LLVMValueRef *fmask_ptr)
4881 {
4882 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4883 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4884 else
4885 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4886 if (samp_ptr) {
4887 if (instr->sampler)
4888 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4889 else
4890 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4891 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4892 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4893 }
4894 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4895 instr->op == nir_texop_samples_identical))
4896 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4897 }
4898
4899 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4900 LLVMValueRef coord)
4901 {
4902 coord = ac_to_float(ctx, coord);
4903 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4904 coord = ac_to_integer(ctx, coord);
4905 return coord;
4906 }
4907
4908 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4909 {
4910 LLVMValueRef result = NULL;
4911 struct ac_image_args args = { 0 };
4912 unsigned dmask = 0xf;
4913 LLVMValueRef address[16];
4914 LLVMValueRef coords[5];
4915 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4916 LLVMValueRef bias = NULL, offsets = NULL;
4917 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4918 LLVMValueRef ddx = NULL, ddy = NULL;
4919 LLVMValueRef derivs[6];
4920 unsigned chan, count = 0;
4921 unsigned const_src = 0, num_deriv_comp = 0;
4922 bool lod_is_zero = false;
4923
4924 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4925
4926 for (unsigned i = 0; i < instr->num_srcs; i++) {
4927 switch (instr->src[i].src_type) {
4928 case nir_tex_src_coord:
4929 coord = get_src(ctx, instr->src[i].src);
4930 break;
4931 case nir_tex_src_projector:
4932 break;
4933 case nir_tex_src_comparator:
4934 comparator = get_src(ctx, instr->src[i].src);
4935 break;
4936 case nir_tex_src_offset:
4937 offsets = get_src(ctx, instr->src[i].src);
4938 const_src = i;
4939 break;
4940 case nir_tex_src_bias:
4941 bias = get_src(ctx, instr->src[i].src);
4942 break;
4943 case nir_tex_src_lod: {
4944 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4945
4946 if (val && val->i32[0] == 0)
4947 lod_is_zero = true;
4948 lod = get_src(ctx, instr->src[i].src);
4949 break;
4950 }
4951 case nir_tex_src_ms_index:
4952 sample_index = get_src(ctx, instr->src[i].src);
4953 break;
4954 case nir_tex_src_ms_mcs:
4955 break;
4956 case nir_tex_src_ddx:
4957 ddx = get_src(ctx, instr->src[i].src);
4958 num_deriv_comp = instr->src[i].src.ssa->num_components;
4959 break;
4960 case nir_tex_src_ddy:
4961 ddy = get_src(ctx, instr->src[i].src);
4962 break;
4963 case nir_tex_src_texture_offset:
4964 case nir_tex_src_sampler_offset:
4965 case nir_tex_src_plane:
4966 default:
4967 break;
4968 }
4969 }
4970
4971 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4972 result = get_buffer_size(ctx, res_ptr, true);
4973 goto write_result;
4974 }
4975
4976 if (instr->op == nir_texop_texture_samples) {
4977 LLVMValueRef res, samples, is_msaa;
4978 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4979 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4980 LLVMConstInt(ctx->ac.i32, 3, false), "");
4981 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4982 LLVMConstInt(ctx->ac.i32, 28, false), "");
4983 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4984 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4985 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4986 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4987
4988 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4989 LLVMConstInt(ctx->ac.i32, 16, false), "");
4990 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4991 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4992 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4993 samples, "");
4994 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4995 ctx->ac.i32_1, "");
4996 result = samples;
4997 goto write_result;
4998 }
4999
5000 if (coord)
5001 for (chan = 0; chan < instr->coord_components; chan++)
5002 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
5003
5004 if (offsets && instr->op != nir_texop_txf) {
5005 LLVMValueRef offset[3], pack;
5006 for (chan = 0; chan < 3; ++chan)
5007 offset[chan] = ctx->ac.i32_0;
5008
5009 args.offset = true;
5010 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
5011 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
5012 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
5013 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
5014 if (chan)
5015 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
5016 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
5017 }
5018 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
5019 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
5020 address[count++] = pack;
5021
5022 }
5023 /* pack LOD bias value */
5024 if (instr->op == nir_texop_txb && bias) {
5025 address[count++] = bias;
5026 }
5027
5028 /* Pack depth comparison value */
5029 if (instr->is_shadow && comparator) {
5030 LLVMValueRef z = ac_to_float(&ctx->ac,
5031 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
5032
5033 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
5034 * so the depth comparison value isn't clamped for Z16 and
5035 * Z24 anymore. Do it manually here.
5036 *
5037 * It's unnecessary if the original texture format was
5038 * Z32_FLOAT, but we don't know that here.
5039 */
5040 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5041 z = ac_build_clamp(&ctx->ac, z);
5042
5043 address[count++] = z;
5044 }
5045
5046 /* pack derivatives */
5047 if (ddx || ddy) {
5048 int num_src_deriv_channels, num_dest_deriv_channels;
5049 switch (instr->sampler_dim) {
5050 case GLSL_SAMPLER_DIM_3D:
5051 case GLSL_SAMPLER_DIM_CUBE:
5052 num_deriv_comp = 3;
5053 num_src_deriv_channels = 3;
5054 num_dest_deriv_channels = 3;
5055 break;
5056 case GLSL_SAMPLER_DIM_2D:
5057 default:
5058 num_src_deriv_channels = 2;
5059 num_dest_deriv_channels = 2;
5060 num_deriv_comp = 2;
5061 break;
5062 case GLSL_SAMPLER_DIM_1D:
5063 num_src_deriv_channels = 1;
5064 if (ctx->ac.chip_class >= GFX9) {
5065 num_dest_deriv_channels = 2;
5066 num_deriv_comp = 2;
5067 } else {
5068 num_dest_deriv_channels = 1;
5069 num_deriv_comp = 1;
5070 }
5071 break;
5072 }
5073
5074 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5075 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5076 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5077 }
5078 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5079 derivs[i] = ctx->ac.f32_0;
5080 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5081 }
5082 }
5083
5084 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5085 for (chan = 0; chan < instr->coord_components; chan++)
5086 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5087 if (instr->coord_components == 3)
5088 coords[3] = LLVMGetUndef(ctx->ac.f32);
5089 ac_prepare_cube_coords(&ctx->ac,
5090 instr->op == nir_texop_txd, instr->is_array,
5091 instr->op == nir_texop_lod, coords, derivs);
5092 if (num_deriv_comp)
5093 num_deriv_comp--;
5094 }
5095
5096 if (ddx || ddy) {
5097 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5098 address[count++] = derivs[i];
5099 }
5100
5101 /* Pack texture coordinates */
5102 if (coord) {
5103 address[count++] = coords[0];
5104 if (instr->coord_components > 1) {
5105 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5106 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5107 }
5108 address[count++] = coords[1];
5109 }
5110 if (instr->coord_components > 2) {
5111 if ((instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
5112 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
5113 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
5114 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
5115 instr->is_array &&
5116 instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
5117 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5118 }
5119 address[count++] = coords[2];
5120 }
5121
5122 if (ctx->ac.chip_class >= GFX9) {
5123 LLVMValueRef filler;
5124 if (instr->op == nir_texop_txf)
5125 filler = ctx->ac.i32_0;
5126 else
5127 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5128
5129 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5130 /* No nir_texop_lod, because it does not take a slice
5131 * even with array textures. */
5132 if (instr->is_array && instr->op != nir_texop_lod ) {
5133 address[count] = address[count - 1];
5134 address[count - 1] = filler;
5135 count++;
5136 } else
5137 address[count++] = filler;
5138 }
5139 }
5140 }
5141
5142 /* Pack LOD */
5143 if (lod && ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && !lod_is_zero)) {
5144 address[count++] = lod;
5145 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5146 address[count++] = sample_index;
5147 } else if(instr->op == nir_texop_txs) {
5148 count = 0;
5149 if (lod)
5150 address[count++] = lod;
5151 else
5152 address[count++] = ctx->ac.i32_0;
5153 }
5154
5155 for (chan = 0; chan < count; chan++) {
5156 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5157 address[chan], ctx->ac.i32, "");
5158 }
5159
5160 if (instr->op == nir_texop_samples_identical) {
5161 LLVMValueRef txf_address[4];
5162 struct ac_image_args txf_args = { 0 };
5163 unsigned txf_count = count;
5164 memcpy(txf_address, address, sizeof(txf_address));
5165
5166 if (!instr->is_array)
5167 txf_address[2] = ctx->ac.i32_0;
5168 txf_address[3] = ctx->ac.i32_0;
5169
5170 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5171 fmask_ptr, NULL,
5172 txf_address, txf_count, 0xf);
5173
5174 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5175
5176 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5177 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5178 goto write_result;
5179 }
5180
5181 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5182 instr->op != nir_texop_txs) {
5183 unsigned sample_chan = instr->is_array ? 3 : 2;
5184 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5185 address[0],
5186 address[1],
5187 instr->is_array ? address[2] : NULL,
5188 address[sample_chan],
5189 fmask_ptr);
5190 }
5191
5192 if (offsets && instr->op == nir_texop_txf) {
5193 nir_const_value *const_offset =
5194 nir_src_as_const_value(instr->src[const_src].src);
5195 int num_offsets = instr->src[const_src].src.ssa->num_components;
5196 assert(const_offset);
5197 num_offsets = MIN2(num_offsets, instr->coord_components);
5198 if (num_offsets > 2)
5199 address[2] = LLVMBuildAdd(ctx->ac.builder,
5200 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5201 if (num_offsets > 1)
5202 address[1] = LLVMBuildAdd(ctx->ac.builder,
5203 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5204 address[0] = LLVMBuildAdd(ctx->ac.builder,
5205 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5206
5207 }
5208
5209 /* TODO TG4 support */
5210 if (instr->op == nir_texop_tg4) {
5211 if (instr->is_shadow)
5212 dmask = 1;
5213 else
5214 dmask = 1 << instr->component;
5215 }
5216 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5217 res_ptr, samp_ptr, address, count, dmask);
5218
5219 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5220
5221 if (instr->op == nir_texop_query_levels)
5222 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5223 else if (instr->is_shadow && instr->is_new_style_shadow &&
5224 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5225 instr->op != nir_texop_tg4)
5226 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5227 else if (instr->op == nir_texop_txs &&
5228 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5229 instr->is_array) {
5230 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5231 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5232 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5233 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5234 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5235 } else if (ctx->ac.chip_class >= GFX9 &&
5236 instr->op == nir_texop_txs &&
5237 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5238 instr->is_array) {
5239 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5240 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5241 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5242 ctx->ac.i32_1, "");
5243 } else if (instr->dest.ssa.num_components != 4)
5244 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5245
5246 write_result:
5247 if (result) {
5248 assert(instr->dest.is_ssa);
5249 result = ac_to_integer(&ctx->ac, result);
5250 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5251 }
5252 }
5253
5254
5255 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5256 {
5257 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5258 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5259
5260 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5261 _mesa_hash_table_insert(ctx->phis, instr, result);
5262 }
5263
5264 static void visit_post_phi(struct ac_nir_context *ctx,
5265 nir_phi_instr *instr,
5266 LLVMValueRef llvm_phi)
5267 {
5268 nir_foreach_phi_src(src, instr) {
5269 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5270 LLVMValueRef llvm_src = get_src(ctx, src->src);
5271
5272 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5273 }
5274 }
5275
5276 static void phi_post_pass(struct ac_nir_context *ctx)
5277 {
5278 struct hash_entry *entry;
5279 hash_table_foreach(ctx->phis, entry) {
5280 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5281 (LLVMValueRef)entry->data);
5282 }
5283 }
5284
5285
5286 static void visit_ssa_undef(struct ac_nir_context *ctx,
5287 const nir_ssa_undef_instr *instr)
5288 {
5289 unsigned num_components = instr->def.num_components;
5290 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5291 LLVMValueRef undef;
5292
5293 if (num_components == 1)
5294 undef = LLVMGetUndef(type);
5295 else {
5296 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5297 }
5298 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5299 }
5300
5301 static void visit_jump(struct ac_llvm_context *ctx,
5302 const nir_jump_instr *instr)
5303 {
5304 switch (instr->type) {
5305 case nir_jump_break:
5306 ac_build_break(ctx);
5307 break;
5308 case nir_jump_continue:
5309 ac_build_continue(ctx);
5310 break;
5311 default:
5312 fprintf(stderr, "Unknown NIR jump instr: ");
5313 nir_print_instr(&instr->instr, stderr);
5314 fprintf(stderr, "\n");
5315 abort();
5316 }
5317 }
5318
5319 static void visit_cf_list(struct ac_nir_context *ctx,
5320 struct exec_list *list);
5321
5322 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5323 {
5324 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5325 nir_foreach_instr(instr, block)
5326 {
5327 switch (instr->type) {
5328 case nir_instr_type_alu:
5329 visit_alu(ctx, nir_instr_as_alu(instr));
5330 break;
5331 case nir_instr_type_load_const:
5332 visit_load_const(ctx, nir_instr_as_load_const(instr));
5333 break;
5334 case nir_instr_type_intrinsic:
5335 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5336 break;
5337 case nir_instr_type_tex:
5338 visit_tex(ctx, nir_instr_as_tex(instr));
5339 break;
5340 case nir_instr_type_phi:
5341 visit_phi(ctx, nir_instr_as_phi(instr));
5342 break;
5343 case nir_instr_type_ssa_undef:
5344 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5345 break;
5346 case nir_instr_type_jump:
5347 visit_jump(&ctx->ac, nir_instr_as_jump(instr));
5348 break;
5349 default:
5350 fprintf(stderr, "Unknown NIR instr type: ");
5351 nir_print_instr(instr, stderr);
5352 fprintf(stderr, "\n");
5353 abort();
5354 }
5355 }
5356
5357 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5358 }
5359
5360 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5361 {
5362 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5363
5364 nir_block *then_block =
5365 (nir_block *) exec_list_get_head(&if_stmt->then_list);
5366
5367 ac_build_uif(&ctx->ac, value, then_block->index);
5368
5369 visit_cf_list(ctx, &if_stmt->then_list);
5370
5371 if (!exec_list_is_empty(&if_stmt->else_list)) {
5372 nir_block *else_block =
5373 (nir_block *) exec_list_get_head(&if_stmt->else_list);
5374
5375 ac_build_else(&ctx->ac, else_block->index);
5376 visit_cf_list(ctx, &if_stmt->else_list);
5377 }
5378
5379 ac_build_endif(&ctx->ac, then_block->index);
5380 }
5381
5382 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5383 {
5384 nir_block *first_loop_block =
5385 (nir_block *) exec_list_get_head(&loop->body);
5386
5387 ac_build_bgnloop(&ctx->ac, first_loop_block->index);
5388
5389 visit_cf_list(ctx, &loop->body);
5390
5391 ac_build_endloop(&ctx->ac, first_loop_block->index);
5392 }
5393
5394 static void visit_cf_list(struct ac_nir_context *ctx,
5395 struct exec_list *list)
5396 {
5397 foreach_list_typed(nir_cf_node, node, node, list)
5398 {
5399 switch (node->type) {
5400 case nir_cf_node_block:
5401 visit_block(ctx, nir_cf_node_as_block(node));
5402 break;
5403
5404 case nir_cf_node_if:
5405 visit_if(ctx, nir_cf_node_as_if(node));
5406 break;
5407
5408 case nir_cf_node_loop:
5409 visit_loop(ctx, nir_cf_node_as_loop(node));
5410 break;
5411
5412 default:
5413 assert(0);
5414 }
5415 }
5416 }
5417
5418 static void
5419 handle_vs_input_decl(struct radv_shader_context *ctx,
5420 struct nir_variable *variable)
5421 {
5422 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5423 LLVMValueRef t_offset;
5424 LLVMValueRef t_list;
5425 LLVMValueRef input;
5426 LLVMValueRef buffer_index;
5427 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5428 int idx = variable->data.location;
5429 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5430 uint8_t input_usage_mask =
5431 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5432 unsigned num_channels = util_last_bit(input_usage_mask);
5433
5434 variable->data.driver_location = idx * 4;
5435
5436 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5437 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5438 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5439 ctx->abi.start_instance, "");
5440 if (ctx->options->key.vs.as_ls) {
5441 ctx->shader_info->vs.vgpr_comp_cnt =
5442 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5443 } else {
5444 ctx->shader_info->vs.vgpr_comp_cnt =
5445 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5446 }
5447 } else
5448 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5449 ctx->abi.base_vertex, "");
5450 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5451
5452 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5453
5454 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5455 buffer_index,
5456 ctx->ac.i32_0,
5457 num_channels, false, true);
5458
5459 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5460
5461 for (unsigned chan = 0; chan < 4; chan++) {
5462 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5463 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5464 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5465 input, llvm_chan, ""));
5466 }
5467 }
5468 }
5469
5470 static void interp_fs_input(struct radv_shader_context *ctx,
5471 unsigned attr,
5472 LLVMValueRef interp_param,
5473 LLVMValueRef prim_mask,
5474 LLVMValueRef result[4])
5475 {
5476 LLVMValueRef attr_number;
5477 unsigned chan;
5478 LLVMValueRef i, j;
5479 bool interp = interp_param != NULL;
5480
5481 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5482
5483 /* fs.constant returns the param from the middle vertex, so it's not
5484 * really useful for flat shading. It's meant to be used for custom
5485 * interpolation (but the intrinsic can't fetch from the other two
5486 * vertices).
5487 *
5488 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5489 * to do the right thing. The only reason we use fs.constant is that
5490 * fs.interp cannot be used on integers, because they can be equal
5491 * to NaN.
5492 */
5493 if (interp) {
5494 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5495 ctx->ac.v2f32, "");
5496
5497 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5498 ctx->ac.i32_0, "");
5499 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5500 ctx->ac.i32_1, "");
5501 }
5502
5503 for (chan = 0; chan < 4; chan++) {
5504 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5505
5506 if (interp) {
5507 result[chan] = ac_build_fs_interp(&ctx->ac,
5508 llvm_chan,
5509 attr_number,
5510 prim_mask, i, j);
5511 } else {
5512 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5513 LLVMConstInt(ctx->ac.i32, 2, false),
5514 llvm_chan,
5515 attr_number,
5516 prim_mask);
5517 }
5518 }
5519 }
5520
5521 static void
5522 handle_fs_input_decl(struct radv_shader_context *ctx,
5523 struct nir_variable *variable)
5524 {
5525 int idx = variable->data.location;
5526 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5527 LLVMValueRef interp;
5528
5529 variable->data.driver_location = idx * 4;
5530 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5531
5532 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5533 unsigned interp_type;
5534 if (variable->data.sample)
5535 interp_type = INTERP_SAMPLE;
5536 else if (variable->data.centroid)
5537 interp_type = INTERP_CENTROID;
5538 else
5539 interp_type = INTERP_CENTER;
5540
5541 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5542 } else
5543 interp = NULL;
5544
5545 for (unsigned i = 0; i < attrib_count; ++i)
5546 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5547
5548 }
5549
5550 static void
5551 handle_vs_inputs(struct radv_shader_context *ctx,
5552 struct nir_shader *nir) {
5553 nir_foreach_variable(variable, &nir->inputs)
5554 handle_vs_input_decl(ctx, variable);
5555 }
5556
5557 static void
5558 prepare_interp_optimize(struct radv_shader_context *ctx,
5559 struct nir_shader *nir)
5560 {
5561 if (!ctx->options->key.fs.multisample)
5562 return;
5563
5564 bool uses_center = false;
5565 bool uses_centroid = false;
5566 nir_foreach_variable(variable, &nir->inputs) {
5567 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5568 variable->data.sample)
5569 continue;
5570
5571 if (variable->data.centroid)
5572 uses_centroid = true;
5573 else
5574 uses_center = true;
5575 }
5576
5577 if (uses_center && uses_centroid) {
5578 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5579 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5580 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5581 }
5582 }
5583
5584 static void
5585 handle_fs_inputs(struct radv_shader_context *ctx,
5586 struct nir_shader *nir)
5587 {
5588 prepare_interp_optimize(ctx, nir);
5589
5590 nir_foreach_variable(variable, &nir->inputs)
5591 handle_fs_input_decl(ctx, variable);
5592
5593 unsigned index = 0;
5594
5595 if (ctx->shader_info->info.ps.uses_input_attachments ||
5596 ctx->shader_info->info.needs_multiview_view_index)
5597 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5598
5599 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5600 LLVMValueRef interp_param;
5601 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5602
5603 if (!(ctx->input_mask & (1ull << i)))
5604 continue;
5605
5606 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5607 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5608 interp_param = *inputs;
5609 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5610 inputs);
5611
5612 if (!interp_param)
5613 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5614 ++index;
5615 } else if (i == VARYING_SLOT_POS) {
5616 for(int i = 0; i < 3; ++i)
5617 inputs[i] = ctx->abi.frag_pos[i];
5618
5619 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5620 ctx->abi.frag_pos[3]);
5621 }
5622 }
5623 ctx->shader_info->fs.num_interp = index;
5624 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5625
5626 if (ctx->shader_info->info.needs_multiview_view_index)
5627 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5628 }
5629
5630 static void
5631 scan_shader_output_decl(struct radv_shader_context *ctx,
5632 struct nir_variable *variable,
5633 struct nir_shader *shader,
5634 gl_shader_stage stage)
5635 {
5636 int idx = variable->data.location + variable->data.index;
5637 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5638 uint64_t mask_attribs;
5639
5640 variable->data.driver_location = idx * 4;
5641
5642 /* tess ctrl has it's own load/store paths for outputs */
5643 if (stage == MESA_SHADER_TESS_CTRL)
5644 return;
5645
5646 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5647 if (stage == MESA_SHADER_VERTEX ||
5648 stage == MESA_SHADER_TESS_EVAL ||
5649 stage == MESA_SHADER_GEOMETRY) {
5650 if (idx == VARYING_SLOT_CLIP_DIST0) {
5651 int length = shader->info.clip_distance_array_size +
5652 shader->info.cull_distance_array_size;
5653 if (stage == MESA_SHADER_VERTEX) {
5654 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5655 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5656 }
5657 if (stage == MESA_SHADER_TESS_EVAL) {
5658 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5659 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5660 }
5661
5662 if (length > 4)
5663 attrib_count = 2;
5664 else
5665 attrib_count = 1;
5666 mask_attribs = 1ull << idx;
5667 }
5668 }
5669
5670 ctx->output_mask |= mask_attribs;
5671 }
5672
5673 static void
5674 handle_shader_output_decl(struct ac_nir_context *ctx,
5675 struct nir_shader *nir,
5676 struct nir_variable *variable)
5677 {
5678 unsigned output_loc = variable->data.driver_location / 4;
5679 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5680
5681 /* tess ctrl has it's own load/store paths for outputs */
5682 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5683 return;
5684
5685 if (ctx->stage == MESA_SHADER_VERTEX ||
5686 ctx->stage == MESA_SHADER_TESS_EVAL ||
5687 ctx->stage == MESA_SHADER_GEOMETRY) {
5688 int idx = variable->data.location + variable->data.index;
5689 if (idx == VARYING_SLOT_CLIP_DIST0) {
5690 int length = nir->info.clip_distance_array_size +
5691 nir->info.cull_distance_array_size;
5692
5693 if (length > 4)
5694 attrib_count = 2;
5695 else
5696 attrib_count = 1;
5697 }
5698 }
5699
5700 for (unsigned i = 0; i < attrib_count; ++i) {
5701 for (unsigned chan = 0; chan < 4; chan++) {
5702 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5703 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5704 }
5705 }
5706 }
5707
5708 static LLVMTypeRef
5709 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5710 enum glsl_base_type type)
5711 {
5712 switch (type) {
5713 case GLSL_TYPE_INT:
5714 case GLSL_TYPE_UINT:
5715 case GLSL_TYPE_BOOL:
5716 case GLSL_TYPE_SUBROUTINE:
5717 return ac->i32;
5718 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5719 return ac->f32;
5720 case GLSL_TYPE_INT64:
5721 case GLSL_TYPE_UINT64:
5722 return ac->i64;
5723 case GLSL_TYPE_DOUBLE:
5724 return ac->f64;
5725 default:
5726 unreachable("unknown GLSL type");
5727 }
5728 }
5729
5730 static LLVMTypeRef
5731 glsl_to_llvm_type(struct ac_llvm_context *ac,
5732 const struct glsl_type *type)
5733 {
5734 if (glsl_type_is_scalar(type)) {
5735 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5736 }
5737
5738 if (glsl_type_is_vector(type)) {
5739 return LLVMVectorType(
5740 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5741 glsl_get_vector_elements(type));
5742 }
5743
5744 if (glsl_type_is_matrix(type)) {
5745 return LLVMArrayType(
5746 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5747 glsl_get_matrix_columns(type));
5748 }
5749
5750 if (glsl_type_is_array(type)) {
5751 return LLVMArrayType(
5752 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5753 glsl_get_length(type));
5754 }
5755
5756 assert(glsl_type_is_struct(type));
5757
5758 LLVMTypeRef member_types[glsl_get_length(type)];
5759
5760 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5761 member_types[i] =
5762 glsl_to_llvm_type(ac,
5763 glsl_get_struct_field(type, i));
5764 }
5765
5766 return LLVMStructTypeInContext(ac->context, member_types,
5767 glsl_get_length(type), false);
5768 }
5769
5770 static void
5771 setup_locals(struct ac_nir_context *ctx,
5772 struct nir_function *func)
5773 {
5774 int i, j;
5775 ctx->num_locals = 0;
5776 nir_foreach_variable(variable, &func->impl->locals) {
5777 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5778 variable->data.driver_location = ctx->num_locals * 4;
5779 variable->data.location_frac = 0;
5780 ctx->num_locals += attrib_count;
5781 }
5782 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5783 if (!ctx->locals)
5784 return;
5785
5786 for (i = 0; i < ctx->num_locals; i++) {
5787 for (j = 0; j < 4; j++) {
5788 ctx->locals[i * 4 + j] =
5789 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5790 }
5791 }
5792 }
5793
5794 static void
5795 setup_shared(struct ac_nir_context *ctx,
5796 struct nir_shader *nir)
5797 {
5798 nir_foreach_variable(variable, &nir->shared) {
5799 LLVMValueRef shared =
5800 LLVMAddGlobalInAddressSpace(
5801 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5802 variable->name ? variable->name : "",
5803 AC_LOCAL_ADDR_SPACE);
5804 _mesa_hash_table_insert(ctx->vars, variable, shared);
5805 }
5806 }
5807
5808 /* Initialize arguments for the shader export intrinsic */
5809 static void
5810 si_llvm_init_export_args(struct radv_shader_context *ctx,
5811 LLVMValueRef *values,
5812 unsigned enabled_channels,
5813 unsigned target,
5814 struct ac_export_args *args)
5815 {
5816 /* Specify the channels that are enabled. */
5817 args->enabled_channels = enabled_channels;
5818
5819 /* Specify whether the EXEC mask represents the valid mask */
5820 args->valid_mask = 0;
5821
5822 /* Specify whether this is the last export */
5823 args->done = 0;
5824
5825 /* Specify the target we are exporting */
5826 args->target = target;
5827
5828 args->compr = false;
5829 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5830 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5831 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5832 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5833
5834 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5835 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5836 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5837 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5838 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5839 unsigned chan;
5840
5841 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5842 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5843 unsigned bits, bool hi) = NULL;
5844
5845 switch(col_format) {
5846 case V_028714_SPI_SHADER_ZERO:
5847 args->enabled_channels = 0; /* writemask */
5848 args->target = V_008DFC_SQ_EXP_NULL;
5849 break;
5850
5851 case V_028714_SPI_SHADER_32_R:
5852 args->enabled_channels = 1;
5853 args->out[0] = values[0];
5854 break;
5855
5856 case V_028714_SPI_SHADER_32_GR:
5857 args->enabled_channels = 0x3;
5858 args->out[0] = values[0];
5859 args->out[1] = values[1];
5860 break;
5861
5862 case V_028714_SPI_SHADER_32_AR:
5863 args->enabled_channels = 0x9;
5864 args->out[0] = values[0];
5865 args->out[3] = values[3];
5866 break;
5867
5868 case V_028714_SPI_SHADER_FP16_ABGR:
5869 args->enabled_channels = 0x5;
5870 packf = ac_build_cvt_pkrtz_f16;
5871 break;
5872
5873 case V_028714_SPI_SHADER_UNORM16_ABGR:
5874 args->enabled_channels = 0x5;
5875 packf = ac_build_cvt_pknorm_u16;
5876 break;
5877
5878 case V_028714_SPI_SHADER_SNORM16_ABGR:
5879 args->enabled_channels = 0x5;
5880 packf = ac_build_cvt_pknorm_i16;
5881 break;
5882
5883 case V_028714_SPI_SHADER_UINT16_ABGR:
5884 args->enabled_channels = 0x5;
5885 packi = ac_build_cvt_pk_u16;
5886 break;
5887
5888 case V_028714_SPI_SHADER_SINT16_ABGR:
5889 args->enabled_channels = 0x5;
5890 packi = ac_build_cvt_pk_i16;
5891 break;
5892
5893 default:
5894 case V_028714_SPI_SHADER_32_ABGR:
5895 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5896 break;
5897 }
5898
5899 /* Pack f16 or norm_i16/u16. */
5900 if (packf) {
5901 for (chan = 0; chan < 2; chan++) {
5902 LLVMValueRef pack_args[2] = {
5903 values[2 * chan],
5904 values[2 * chan + 1]
5905 };
5906 LLVMValueRef packed;
5907
5908 packed = packf(&ctx->ac, pack_args);
5909 args->out[chan] = ac_to_float(&ctx->ac, packed);
5910 }
5911 args->compr = 1; /* COMPR flag */
5912 }
5913
5914 /* Pack i16/u16. */
5915 if (packi) {
5916 for (chan = 0; chan < 2; chan++) {
5917 LLVMValueRef pack_args[2] = {
5918 ac_to_integer(&ctx->ac, values[2 * chan]),
5919 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5920 };
5921 LLVMValueRef packed;
5922
5923 packed = packi(&ctx->ac, pack_args,
5924 is_int8 ? 8 : is_int10 ? 10 : 16,
5925 chan == 1);
5926 args->out[chan] = ac_to_float(&ctx->ac, packed);
5927 }
5928 args->compr = 1; /* COMPR flag */
5929 }
5930 return;
5931 }
5932
5933 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5934
5935 for (unsigned i = 0; i < 4; ++i) {
5936 if (!(args->enabled_channels & (1 << i)))
5937 continue;
5938
5939 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5940 }
5941 }
5942
5943 static void
5944 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5945 LLVMValueRef *values, unsigned enabled_channels)
5946 {
5947 struct ac_export_args args;
5948
5949 si_llvm_init_export_args(ctx, values, enabled_channels,
5950 V_008DFC_SQ_EXP_PARAM + index, &args);
5951 ac_build_export(&ctx->ac, &args);
5952 }
5953
5954 static LLVMValueRef
5955 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5956 {
5957 LLVMValueRef output =
5958 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5959
5960 return LLVMBuildLoad(ctx->ac.builder, output, "");
5961 }
5962
5963 static void
5964 handle_vs_outputs_post(struct radv_shader_context *ctx,
5965 bool export_prim_id,
5966 struct ac_vs_output_info *outinfo)
5967 {
5968 uint32_t param_count = 0;
5969 unsigned target;
5970 unsigned pos_idx, num_pos_exports = 0;
5971 struct ac_export_args args, pos_args[4] = {};
5972 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5973 int i;
5974
5975 if (ctx->options->key.has_multiview_view_index) {
5976 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5977 if(!*tmp_out) {
5978 for(unsigned i = 0; i < 4; ++i)
5979 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5980 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5981 }
5982
5983 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
5984 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5985 }
5986
5987 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5988 sizeof(outinfo->vs_output_param_offset));
5989
5990 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5991 LLVMValueRef slots[8];
5992 unsigned j;
5993
5994 if (outinfo->cull_dist_mask)
5995 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5996
5997 i = VARYING_SLOT_CLIP_DIST0;
5998 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5999 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6000
6001 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
6002 slots[i] = LLVMGetUndef(ctx->ac.f32);
6003
6004 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
6005 target = V_008DFC_SQ_EXP_POS + 3;
6006 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
6007 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6008 &args, sizeof(args));
6009 }
6010
6011 target = V_008DFC_SQ_EXP_POS + 2;
6012 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
6013 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6014 &args, sizeof(args));
6015
6016 }
6017
6018 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6019 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6020 for (unsigned j = 0; j < 4; j++)
6021 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6022 }
6023 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6024
6025 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6026 outinfo->writes_pointsize = true;
6027 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6028 }
6029
6030 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6031 outinfo->writes_layer = true;
6032 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6033 }
6034
6035 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6036 outinfo->writes_viewport_index = true;
6037 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6038 }
6039
6040 if (outinfo->writes_pointsize ||
6041 outinfo->writes_layer ||
6042 outinfo->writes_viewport_index) {
6043 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6044 (outinfo->writes_layer == true ? 4 : 0));
6045 pos_args[1].valid_mask = 0;
6046 pos_args[1].done = 0;
6047 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6048 pos_args[1].compr = 0;
6049 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6050 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6051 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6052 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6053
6054 if (outinfo->writes_pointsize == true)
6055 pos_args[1].out[0] = psize_value;
6056 if (outinfo->writes_layer == true)
6057 pos_args[1].out[2] = layer_value;
6058 if (outinfo->writes_viewport_index == true) {
6059 if (ctx->options->chip_class >= GFX9) {
6060 /* GFX9 has the layer in out.z[10:0] and the viewport
6061 * index in out.z[19:16].
6062 */
6063 LLVMValueRef v = viewport_index_value;
6064 v = ac_to_integer(&ctx->ac, v);
6065 v = LLVMBuildShl(ctx->ac.builder, v,
6066 LLVMConstInt(ctx->ac.i32, 16, false),
6067 "");
6068 v = LLVMBuildOr(ctx->ac.builder, v,
6069 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6070
6071 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6072 pos_args[1].enabled_channels |= 1 << 2;
6073 } else {
6074 pos_args[1].out[3] = viewport_index_value;
6075 pos_args[1].enabled_channels |= 1 << 3;
6076 }
6077 }
6078 }
6079 for (i = 0; i < 4; i++) {
6080 if (pos_args[i].out[0])
6081 num_pos_exports++;
6082 }
6083
6084 pos_idx = 0;
6085 for (i = 0; i < 4; i++) {
6086 if (!pos_args[i].out[0])
6087 continue;
6088
6089 /* Specify the target we are exporting */
6090 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6091 if (pos_idx == num_pos_exports)
6092 pos_args[i].done = 1;
6093 ac_build_export(&ctx->ac, &pos_args[i]);
6094 }
6095
6096 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6097 LLVMValueRef values[4];
6098 if (!(ctx->output_mask & (1ull << i)))
6099 continue;
6100
6101 if (i != VARYING_SLOT_LAYER &&
6102 i != VARYING_SLOT_PRIMITIVE_ID &&
6103 i < VARYING_SLOT_VAR0)
6104 continue;
6105
6106 for (unsigned j = 0; j < 4; j++)
6107 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6108
6109 unsigned output_usage_mask;
6110
6111 if (ctx->stage == MESA_SHADER_VERTEX &&
6112 !ctx->is_gs_copy_shader) {
6113 output_usage_mask =
6114 ctx->shader_info->info.vs.output_usage_mask[i];
6115 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
6116 output_usage_mask =
6117 ctx->shader_info->info.tes.output_usage_mask[i];
6118 } else {
6119 /* Enable all channels for the GS copy shader because
6120 * we don't know the output usage mask currently.
6121 */
6122 output_usage_mask = 0xf;
6123 }
6124
6125 radv_export_param(ctx, param_count, values, output_usage_mask);
6126
6127 outinfo->vs_output_param_offset[i] = param_count++;
6128 }
6129
6130 if (export_prim_id) {
6131 LLVMValueRef values[4];
6132
6133 values[0] = ctx->vs_prim_id;
6134 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6135 ctx->shader_info->vs.vgpr_comp_cnt);
6136 for (unsigned j = 1; j < 4; j++)
6137 values[j] = ctx->ac.f32_0;
6138
6139 radv_export_param(ctx, param_count, values, 0xf);
6140
6141 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6142 outinfo->export_prim_id = true;
6143 }
6144
6145 outinfo->pos_exports = num_pos_exports;
6146 outinfo->param_exports = param_count;
6147 }
6148
6149 static void
6150 handle_es_outputs_post(struct radv_shader_context *ctx,
6151 struct ac_es_output_info *outinfo)
6152 {
6153 int j;
6154 uint64_t max_output_written = 0;
6155 LLVMValueRef lds_base = NULL;
6156
6157 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6158 int param_index;
6159 int length = 4;
6160
6161 if (!(ctx->output_mask & (1ull << i)))
6162 continue;
6163
6164 if (i == VARYING_SLOT_CLIP_DIST0)
6165 length = ctx->num_output_clips + ctx->num_output_culls;
6166
6167 param_index = shader_io_get_unique_index(i);
6168
6169 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6170 }
6171
6172 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6173
6174 if (ctx->ac.chip_class >= GFX9) {
6175 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6176 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6177 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6178 LLVMConstInt(ctx->ac.i32, 24, false),
6179 LLVMConstInt(ctx->ac.i32, 4, false), false);
6180 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6181 LLVMBuildMul(ctx->ac.builder, wave_idx,
6182 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6183 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6184 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6185 }
6186
6187 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6188 LLVMValueRef dw_addr = NULL;
6189 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6190 int param_index;
6191 int length = 4;
6192
6193 if (!(ctx->output_mask & (1ull << i)))
6194 continue;
6195
6196 if (i == VARYING_SLOT_CLIP_DIST0)
6197 length = ctx->num_output_clips + ctx->num_output_culls;
6198
6199 param_index = shader_io_get_unique_index(i);
6200
6201 if (lds_base) {
6202 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6203 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6204 "");
6205 }
6206 for (j = 0; j < length; j++) {
6207 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6208 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6209
6210 if (ctx->ac.chip_class >= GFX9) {
6211 ac_lds_store(&ctx->ac, dw_addr,
6212 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6213 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6214 } else {
6215 ac_build_buffer_store_dword(&ctx->ac,
6216 ctx->esgs_ring,
6217 out_val, 1,
6218 NULL, ctx->es2gs_offset,
6219 (4 * param_index + j) * 4,
6220 1, 1, true, true);
6221 }
6222 }
6223 }
6224 }
6225
6226 static void
6227 handle_ls_outputs_post(struct radv_shader_context *ctx)
6228 {
6229 LLVMValueRef vertex_id = ctx->rel_auto_id;
6230 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6231 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6232 vertex_dw_stride, "");
6233
6234 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6235 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6236 int length = 4;
6237
6238 if (!(ctx->output_mask & (1ull << i)))
6239 continue;
6240
6241 if (i == VARYING_SLOT_CLIP_DIST0)
6242 length = ctx->num_output_clips + ctx->num_output_culls;
6243 int param = shader_io_get_unique_index(i);
6244 mark_tess_output(ctx, false, param);
6245 if (length > 4)
6246 mark_tess_output(ctx, false, param + 1);
6247 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6248 LLVMConstInt(ctx->ac.i32, param * 4, false),
6249 "");
6250 for (unsigned j = 0; j < length; j++) {
6251 ac_lds_store(&ctx->ac, dw_addr,
6252 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6253 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6254 }
6255 }
6256 }
6257
6258 struct ac_build_if_state
6259 {
6260 struct radv_shader_context *ctx;
6261 LLVMValueRef condition;
6262 LLVMBasicBlockRef entry_block;
6263 LLVMBasicBlockRef true_block;
6264 LLVMBasicBlockRef false_block;
6265 LLVMBasicBlockRef merge_block;
6266 };
6267
6268 static LLVMBasicBlockRef
6269 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6270 {
6271 LLVMBasicBlockRef current_block;
6272 LLVMBasicBlockRef next_block;
6273 LLVMBasicBlockRef new_block;
6274
6275 /* get current basic block */
6276 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6277
6278 /* chqeck if there's another block after this one */
6279 next_block = LLVMGetNextBasicBlock(current_block);
6280 if (next_block) {
6281 /* insert the new block before the next block */
6282 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6283 }
6284 else {
6285 /* append new block after current block */
6286 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6287 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6288 }
6289 return new_block;
6290 }
6291
6292 static void
6293 ac_nir_build_if(struct ac_build_if_state *ifthen,
6294 struct radv_shader_context *ctx,
6295 LLVMValueRef condition)
6296 {
6297 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6298
6299 memset(ifthen, 0, sizeof *ifthen);
6300 ifthen->ctx = ctx;
6301 ifthen->condition = condition;
6302 ifthen->entry_block = block;
6303
6304 /* create endif/merge basic block for the phi functions */
6305 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6306
6307 /* create/insert true_block before merge_block */
6308 ifthen->true_block =
6309 LLVMInsertBasicBlockInContext(ctx->context,
6310 ifthen->merge_block,
6311 "if-true-block");
6312
6313 /* successive code goes into the true block */
6314 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6315 }
6316
6317 /**
6318 * End a conditional.
6319 */
6320 static void
6321 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6322 {
6323 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6324
6325 /* Insert branch to the merge block from current block */
6326 LLVMBuildBr(builder, ifthen->merge_block);
6327
6328 /*
6329 * Now patch in the various branch instructions.
6330 */
6331
6332 /* Insert the conditional branch instruction at the end of entry_block */
6333 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6334 if (ifthen->false_block) {
6335 /* we have an else clause */
6336 LLVMBuildCondBr(builder, ifthen->condition,
6337 ifthen->true_block, ifthen->false_block);
6338 }
6339 else {
6340 /* no else clause */
6341 LLVMBuildCondBr(builder, ifthen->condition,
6342 ifthen->true_block, ifthen->merge_block);
6343 }
6344
6345 /* Resume building code at end of the ifthen->merge_block */
6346 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6347 }
6348
6349 static void
6350 write_tess_factors(struct radv_shader_context *ctx)
6351 {
6352 unsigned stride, outer_comps, inner_comps;
6353 struct ac_build_if_state if_ctx, inner_if_ctx;
6354 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6355 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6356 unsigned tess_inner_index = 0, tess_outer_index;
6357 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
6358 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6359 int i;
6360 emit_barrier(&ctx->ac, ctx->stage);
6361
6362 switch (ctx->options->key.tcs.primitive_mode) {
6363 case GL_ISOLINES:
6364 stride = 2;
6365 outer_comps = 2;
6366 inner_comps = 0;
6367 break;
6368 case GL_TRIANGLES:
6369 stride = 4;
6370 outer_comps = 3;
6371 inner_comps = 1;
6372 break;
6373 case GL_QUADS:
6374 stride = 6;
6375 outer_comps = 4;
6376 inner_comps = 2;
6377 break;
6378 default:
6379 return;
6380 }
6381
6382 ac_nir_build_if(&if_ctx, ctx,
6383 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6384 invocation_id, ctx->ac.i32_0, ""));
6385
6386 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6387
6388 if (inner_comps) {
6389 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6390 mark_tess_output(ctx, true, tess_inner_index);
6391 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6392 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6393 }
6394
6395 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6396 mark_tess_output(ctx, true, tess_outer_index);
6397 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6398 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6399
6400 for (i = 0; i < 4; i++) {
6401 inner[i] = LLVMGetUndef(ctx->ac.i32);
6402 outer[i] = LLVMGetUndef(ctx->ac.i32);
6403 }
6404
6405 // LINES reverseal
6406 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6407 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6408 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6409 ctx->ac.i32_1, "");
6410 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6411 } else {
6412 for (i = 0; i < outer_comps; i++) {
6413 outer[i] = out[i] =
6414 ac_lds_load(&ctx->ac, lds_outer);
6415 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6416 ctx->ac.i32_1, "");
6417 }
6418 for (i = 0; i < inner_comps; i++) {
6419 inner[i] = out[outer_comps+i] =
6420 ac_lds_load(&ctx->ac, lds_inner);
6421 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6422 ctx->ac.i32_1, "");
6423 }
6424 }
6425
6426 /* Convert the outputs to vectors for stores. */
6427 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6428 vec1 = NULL;
6429
6430 if (stride > 4)
6431 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6432
6433
6434 buffer = ctx->hs_ring_tess_factor;
6435 tf_base = ctx->tess_factor_offset;
6436 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6437 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6438 unsigned tf_offset = 0;
6439
6440 if (ctx->options->chip_class <= VI) {
6441 ac_nir_build_if(&inner_if_ctx, ctx,
6442 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6443 rel_patch_id, ctx->ac.i32_0, ""));
6444
6445 /* Store the dynamic HS control word. */
6446 ac_build_buffer_store_dword(&ctx->ac, buffer,
6447 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6448 1, ctx->ac.i32_0, tf_base,
6449 0, 1, 0, true, false);
6450 tf_offset += 4;
6451
6452 ac_nir_build_endif(&inner_if_ctx);
6453 }
6454
6455 /* Store the tessellation factors. */
6456 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6457 MIN2(stride, 4), byteoffset, tf_base,
6458 tf_offset, 1, 0, true, false);
6459 if (vec1)
6460 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6461 stride - 4, byteoffset, tf_base,
6462 16 + tf_offset, 1, 0, true, false);
6463
6464 //store to offchip for TES to read - only if TES reads them
6465 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6466 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6467 LLVMValueRef tf_inner_offset;
6468 unsigned param_outer, param_inner;
6469
6470 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6471 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6472 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6473
6474 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6475 util_next_power_of_two(outer_comps));
6476
6477 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6478 outer_comps, tf_outer_offset,
6479 ctx->oc_lds, 0, 1, 0, true, false);
6480 if (inner_comps) {
6481 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6482 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6483 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6484
6485 inner_vec = inner_comps == 1 ? inner[0] :
6486 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6487 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6488 inner_comps, tf_inner_offset,
6489 ctx->oc_lds, 0, 1, 0, true, false);
6490 }
6491 }
6492 ac_nir_build_endif(&if_ctx);
6493 }
6494
6495 static void
6496 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6497 {
6498 write_tess_factors(ctx);
6499 }
6500
6501 static bool
6502 si_export_mrt_color(struct radv_shader_context *ctx,
6503 LLVMValueRef *color, unsigned index,
6504 struct ac_export_args *args)
6505 {
6506 /* Export */
6507 si_llvm_init_export_args(ctx, color, 0xf,
6508 V_008DFC_SQ_EXP_MRT + index, args);
6509 if (!args->enabled_channels)
6510 return false; /* unnecessary NULL export */
6511
6512 return true;
6513 }
6514
6515 static void
6516 radv_export_mrt_z(struct radv_shader_context *ctx,
6517 LLVMValueRef depth, LLVMValueRef stencil,
6518 LLVMValueRef samplemask)
6519 {
6520 struct ac_export_args args;
6521
6522 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6523
6524 ac_build_export(&ctx->ac, &args);
6525 }
6526
6527 static void
6528 handle_fs_outputs_post(struct radv_shader_context *ctx)
6529 {
6530 unsigned index = 0;
6531 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6532 struct ac_export_args color_args[8];
6533
6534 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6535 LLVMValueRef values[4];
6536
6537 if (!(ctx->output_mask & (1ull << i)))
6538 continue;
6539
6540 if (i < FRAG_RESULT_DATA0)
6541 continue;
6542
6543 for (unsigned j = 0; j < 4; j++)
6544 values[j] = ac_to_float(&ctx->ac,
6545 radv_load_output(ctx, i, j));
6546
6547 bool ret = si_export_mrt_color(ctx, values,
6548 i - FRAG_RESULT_DATA0,
6549 &color_args[index]);
6550 if (ret)
6551 index++;
6552 }
6553
6554 /* Process depth, stencil, samplemask. */
6555 if (ctx->shader_info->info.ps.writes_z) {
6556 depth = ac_to_float(&ctx->ac,
6557 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6558 }
6559 if (ctx->shader_info->info.ps.writes_stencil) {
6560 stencil = ac_to_float(&ctx->ac,
6561 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6562 }
6563 if (ctx->shader_info->info.ps.writes_sample_mask) {
6564 samplemask = ac_to_float(&ctx->ac,
6565 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6566 }
6567
6568 /* Set the DONE bit on last non-null color export only if Z isn't
6569 * exported.
6570 */
6571 if (index > 0 &&
6572 !ctx->shader_info->info.ps.writes_z &&
6573 !ctx->shader_info->info.ps.writes_stencil &&
6574 !ctx->shader_info->info.ps.writes_sample_mask) {
6575 unsigned last = index - 1;
6576
6577 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
6578 color_args[last].done = 1; /* DONE bit */
6579 }
6580
6581 /* Export PS outputs. */
6582 for (unsigned i = 0; i < index; i++)
6583 ac_build_export(&ctx->ac, &color_args[i]);
6584
6585 if (depth || stencil || samplemask)
6586 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6587 else if (!index)
6588 ac_build_export_null(&ctx->ac);
6589 }
6590
6591 static void
6592 emit_gs_epilogue(struct radv_shader_context *ctx)
6593 {
6594 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6595 }
6596
6597 static void
6598 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6599 LLVMValueRef *addrs)
6600 {
6601 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6602
6603 switch (ctx->stage) {
6604 case MESA_SHADER_VERTEX:
6605 if (ctx->options->key.vs.as_ls)
6606 handle_ls_outputs_post(ctx);
6607 else if (ctx->options->key.vs.as_es)
6608 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6609 else
6610 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6611 &ctx->shader_info->vs.outinfo);
6612 break;
6613 case MESA_SHADER_FRAGMENT:
6614 handle_fs_outputs_post(ctx);
6615 break;
6616 case MESA_SHADER_GEOMETRY:
6617 emit_gs_epilogue(ctx);
6618 break;
6619 case MESA_SHADER_TESS_CTRL:
6620 handle_tcs_outputs_post(ctx);
6621 break;
6622 case MESA_SHADER_TESS_EVAL:
6623 if (ctx->options->key.tes.as_es)
6624 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6625 else
6626 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6627 &ctx->shader_info->tes.outinfo);
6628 break;
6629 default:
6630 break;
6631 }
6632 }
6633
6634 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6635 {
6636 LLVMPassManagerRef passmgr;
6637 /* Create the pass manager */
6638 passmgr = LLVMCreateFunctionPassManagerForModule(
6639 ctx->ac.module);
6640
6641 /* This pass should eliminate all the load and store instructions */
6642 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6643
6644 /* Add some optimization passes */
6645 LLVMAddScalarReplAggregatesPass(passmgr);
6646 LLVMAddLICMPass(passmgr);
6647 LLVMAddAggressiveDCEPass(passmgr);
6648 LLVMAddCFGSimplificationPass(passmgr);
6649 LLVMAddInstructionCombiningPass(passmgr);
6650
6651 /* Run the pass */
6652 LLVMInitializeFunctionPassManager(passmgr);
6653 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6654 LLVMFinalizeFunctionPassManager(passmgr);
6655
6656 LLVMDisposeBuilder(ctx->ac.builder);
6657 LLVMDisposePassManager(passmgr);
6658
6659 ac_llvm_context_dispose(&ctx->ac);
6660 }
6661
6662 static void
6663 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6664 {
6665 struct ac_vs_output_info *outinfo;
6666
6667 switch (ctx->stage) {
6668 case MESA_SHADER_FRAGMENT:
6669 case MESA_SHADER_COMPUTE:
6670 case MESA_SHADER_TESS_CTRL:
6671 case MESA_SHADER_GEOMETRY:
6672 return;
6673 case MESA_SHADER_VERTEX:
6674 if (ctx->options->key.vs.as_ls ||
6675 ctx->options->key.vs.as_es)
6676 return;
6677 outinfo = &ctx->shader_info->vs.outinfo;
6678 break;
6679 case MESA_SHADER_TESS_EVAL:
6680 if (ctx->options->key.vs.as_es)
6681 return;
6682 outinfo = &ctx->shader_info->tes.outinfo;
6683 break;
6684 default:
6685 unreachable("Unhandled shader type");
6686 }
6687
6688 ac_optimize_vs_outputs(&ctx->ac,
6689 ctx->main_function,
6690 outinfo->vs_output_param_offset,
6691 VARYING_SLOT_MAX,
6692 &outinfo->param_exports);
6693 }
6694
6695 static void
6696 ac_setup_rings(struct radv_shader_context *ctx)
6697 {
6698 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6699 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6700 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6701 }
6702
6703 if (ctx->is_gs_copy_shader) {
6704 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6705 }
6706 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6707 LLVMValueRef tmp;
6708 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6709 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6710
6711 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6712
6713 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6714 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6715 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6716 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6717 }
6718
6719 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6720 ctx->stage == MESA_SHADER_TESS_EVAL) {
6721 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6722 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6723 }
6724 }
6725
6726 static unsigned
6727 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6728 const struct nir_shader *nir)
6729 {
6730 switch (nir->info.stage) {
6731 case MESA_SHADER_TESS_CTRL:
6732 return chip_class >= CIK ? 128 : 64;
6733 case MESA_SHADER_GEOMETRY:
6734 return chip_class >= GFX9 ? 128 : 64;
6735 case MESA_SHADER_COMPUTE:
6736 break;
6737 default:
6738 return 0;
6739 }
6740
6741 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6742 nir->info.cs.local_size[1] *
6743 nir->info.cs.local_size[2];
6744 return max_workgroup_size;
6745 }
6746
6747 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6748 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6749 {
6750 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6751 LLVMConstInt(ctx->ac.i32, 8, false),
6752 LLVMConstInt(ctx->ac.i32, 8, false), false);
6753 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6754 ctx->ac.i32_0, "");
6755 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6756 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6757 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6758 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6759 }
6760
6761 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6762 {
6763 for(int i = 5; i >= 0; --i) {
6764 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6765 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6766 LLVMConstInt(ctx->ac.i32, 16, false), false);
6767 }
6768
6769 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6770 LLVMConstInt(ctx->ac.i32, 16, false),
6771 LLVMConstInt(ctx->ac.i32, 8, false), false);
6772 }
6773
6774 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6775 struct nir_shader *nir)
6776 {
6777 struct ac_nir_context ctx = {};
6778 struct nir_function *func;
6779
6780 /* Last minute passes for both radv & radeonsi */
6781 ac_lower_subgroups(nir);
6782
6783 ctx.ac = *ac;
6784 ctx.abi = abi;
6785
6786 ctx.stage = nir->info.stage;
6787
6788 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6789
6790 nir_foreach_variable(variable, &nir->outputs)
6791 handle_shader_output_decl(&ctx, nir, variable);
6792
6793 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6794 _mesa_key_pointer_equal);
6795 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6796 _mesa_key_pointer_equal);
6797 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6798 _mesa_key_pointer_equal);
6799
6800 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6801
6802 setup_locals(&ctx, func);
6803
6804 if (nir->info.stage == MESA_SHADER_COMPUTE)
6805 setup_shared(&ctx, nir);
6806
6807 visit_cf_list(&ctx, &func->impl->body);
6808 phi_post_pass(&ctx);
6809
6810 if (nir->info.stage != MESA_SHADER_COMPUTE)
6811 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6812 ctx.abi->outputs);
6813
6814 free(ctx.locals);
6815 ralloc_free(ctx.defs);
6816 ralloc_free(ctx.phis);
6817 ralloc_free(ctx.vars);
6818 }
6819
6820 static
6821 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6822 struct nir_shader *const *shaders,
6823 int shader_count,
6824 struct ac_shader_variant_info *shader_info,
6825 const struct ac_nir_compiler_options *options,
6826 bool dump_shader)
6827 {
6828 struct radv_shader_context ctx = {0};
6829 unsigned i;
6830 ctx.options = options;
6831 ctx.shader_info = shader_info;
6832 ctx.context = LLVMContextCreate();
6833
6834 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6835 options->family);
6836 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6837 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6838
6839 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6840 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6841 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6842 LLVMDisposeTargetData(data_layout);
6843 LLVMDisposeMessage(data_layout_str);
6844
6845 enum ac_float_mode float_mode =
6846 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6847 AC_FLOAT_MODE_DEFAULT;
6848
6849 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6850
6851 memset(shader_info, 0, sizeof(*shader_info));
6852
6853 for(int i = 0; i < shader_count; ++i)
6854 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6855
6856 for (i = 0; i < AC_UD_MAX_SETS; i++)
6857 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6858 for (i = 0; i < AC_UD_MAX_UD; i++)
6859 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6860
6861 ctx.max_workgroup_size = 0;
6862 for (int i = 0; i < shader_count; ++i) {
6863 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6864 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6865 shaders[i]));
6866 }
6867
6868 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6869 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6870
6871 ctx.abi.inputs = &ctx.inputs[0];
6872 ctx.abi.emit_outputs = handle_shader_outputs_post;
6873 ctx.abi.emit_vertex = visit_emit_vertex;
6874 ctx.abi.load_ubo = radv_load_ubo;
6875 ctx.abi.load_ssbo = radv_load_ssbo;
6876 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6877 ctx.abi.load_resource = radv_load_resource;
6878 ctx.abi.clamp_shadow_reference = false;
6879
6880 if (shader_count >= 2)
6881 ac_init_exec_full_mask(&ctx.ac);
6882
6883 if (ctx.ac.chip_class == GFX9 &&
6884 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6885 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6886
6887 for(int i = 0; i < shader_count; ++i) {
6888 ctx.stage = shaders[i]->info.stage;
6889 ctx.output_mask = 0;
6890 ctx.tess_outputs_written = 0;
6891 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6892 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6893
6894 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6895 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6896 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6897 ctx.abi.load_inputs = load_gs_input;
6898 ctx.abi.emit_primitive = visit_end_primitive;
6899 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6900 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6901 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6902 ctx.abi.load_tess_varyings = load_tcs_varyings;
6903 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6904 ctx.abi.store_tcs_outputs = store_tcs_output;
6905 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6906 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6907 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6908 ctx.abi.load_tess_varyings = load_tes_input;
6909 ctx.abi.load_tess_coord = load_tess_coord;
6910 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6911 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6912 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6913 if (shader_info->info.vs.needs_instance_id) {
6914 if (ctx.options->key.vs.as_ls) {
6915 ctx.shader_info->vs.vgpr_comp_cnt =
6916 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6917 } else {
6918 ctx.shader_info->vs.vgpr_comp_cnt =
6919 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6920 }
6921 }
6922 ctx.abi.load_base_vertex = radv_load_base_vertex;
6923 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6924 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6925 ctx.abi.lookup_interp_param = lookup_interp_param;
6926 ctx.abi.load_sample_position = load_sample_position;
6927 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6928 ctx.abi.emit_kill = radv_emit_kill;
6929 }
6930
6931 if (i)
6932 emit_barrier(&ctx.ac, ctx.stage);
6933
6934 ac_setup_rings(&ctx);
6935
6936 LLVMBasicBlockRef merge_block;
6937 if (shader_count >= 2) {
6938 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6939 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6940 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6941
6942 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6943 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6944 LLVMConstInt(ctx.ac.i32, 8, false), false);
6945 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6946 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6947 thread_id, count, "");
6948 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6949
6950 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6951 }
6952
6953 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6954 handle_fs_inputs(&ctx, shaders[i]);
6955 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6956 handle_vs_inputs(&ctx, shaders[i]);
6957 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6958 prepare_gs_input_vgprs(&ctx);
6959
6960 nir_foreach_variable(variable, &shaders[i]->outputs)
6961 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6962
6963 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6964
6965 if (shader_count >= 2) {
6966 LLVMBuildBr(ctx.ac.builder, merge_block);
6967 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6968 }
6969
6970 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6971 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6972 shaders[i]->info.cull_distance_array_size > 4;
6973 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6974 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6975 shaders[i]->info.gs.vertices_out;
6976 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6977 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6978 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6979 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6980 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6981 }
6982 }
6983
6984 LLVMBuildRetVoid(ctx.ac.builder);
6985
6986 if (options->dump_preoptir)
6987 ac_dump_module(ctx.ac.module);
6988
6989 ac_llvm_finalize_module(&ctx);
6990
6991 if (shader_count == 1)
6992 ac_nir_eliminate_const_vs_outputs(&ctx);
6993
6994 if (dump_shader) {
6995 ctx.shader_info->private_mem_vgprs =
6996 ac_count_scratch_private_memory(ctx.main_function);
6997 }
6998
6999 return ctx.ac.module;
7000 }
7001
7002 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
7003 {
7004 unsigned *retval = (unsigned *)context;
7005 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
7006 char *description = LLVMGetDiagInfoDescription(di);
7007
7008 if (severity == LLVMDSError) {
7009 *retval = 1;
7010 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
7011 description);
7012 }
7013
7014 LLVMDisposeMessage(description);
7015 }
7016
7017 static unsigned ac_llvm_compile(LLVMModuleRef M,
7018 struct ac_shader_binary *binary,
7019 LLVMTargetMachineRef tm)
7020 {
7021 unsigned retval = 0;
7022 char *err;
7023 LLVMContextRef llvm_ctx;
7024 LLVMMemoryBufferRef out_buffer;
7025 unsigned buffer_size;
7026 const char *buffer_data;
7027 LLVMBool mem_err;
7028
7029 /* Setup Diagnostic Handler*/
7030 llvm_ctx = LLVMGetModuleContext(M);
7031
7032 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
7033 &retval);
7034
7035 /* Compile IR*/
7036 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
7037 &err, &out_buffer);
7038
7039 /* Process Errors/Warnings */
7040 if (mem_err) {
7041 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7042 free(err);
7043 retval = 1;
7044 goto out;
7045 }
7046
7047 /* Extract Shader Code*/
7048 buffer_size = LLVMGetBufferSize(out_buffer);
7049 buffer_data = LLVMGetBufferStart(out_buffer);
7050
7051 ac_elf_read(buffer_data, buffer_size, binary);
7052
7053 /* Clean up */
7054 LLVMDisposeMemoryBuffer(out_buffer);
7055
7056 out:
7057 return retval;
7058 }
7059
7060 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7061 LLVMModuleRef llvm_module,
7062 struct ac_shader_binary *binary,
7063 struct ac_shader_config *config,
7064 struct ac_shader_variant_info *shader_info,
7065 gl_shader_stage stage,
7066 bool dump_shader, bool supports_spill)
7067 {
7068 if (dump_shader)
7069 ac_dump_module(llvm_module);
7070
7071 memset(binary, 0, sizeof(*binary));
7072 int v = ac_llvm_compile(llvm_module, binary, tm);
7073 if (v) {
7074 fprintf(stderr, "compile failed\n");
7075 }
7076
7077 if (dump_shader)
7078 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7079
7080 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7081
7082 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7083 LLVMDisposeModule(llvm_module);
7084 LLVMContextDispose(ctx);
7085
7086 if (stage == MESA_SHADER_FRAGMENT) {
7087 shader_info->num_input_vgprs = 0;
7088 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7089 shader_info->num_input_vgprs += 2;
7090 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7091 shader_info->num_input_vgprs += 2;
7092 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7093 shader_info->num_input_vgprs += 2;
7094 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7095 shader_info->num_input_vgprs += 3;
7096 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7097 shader_info->num_input_vgprs += 2;
7098 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7099 shader_info->num_input_vgprs += 2;
7100 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7101 shader_info->num_input_vgprs += 2;
7102 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7103 shader_info->num_input_vgprs += 1;
7104 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7105 shader_info->num_input_vgprs += 1;
7106 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7107 shader_info->num_input_vgprs += 1;
7108 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7109 shader_info->num_input_vgprs += 1;
7110 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7111 shader_info->num_input_vgprs += 1;
7112 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7113 shader_info->num_input_vgprs += 1;
7114 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7115 shader_info->num_input_vgprs += 1;
7116 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7117 shader_info->num_input_vgprs += 1;
7118 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7119 shader_info->num_input_vgprs += 1;
7120 }
7121 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7122
7123 /* +3 for scratch wave offset and VCC */
7124 config->num_sgprs = MAX2(config->num_sgprs,
7125 shader_info->num_input_sgprs + 3);
7126
7127 /* Enable 64-bit and 16-bit denormals, because there is no performance
7128 * cost.
7129 *
7130 * If denormals are enabled, all floating-point output modifiers are
7131 * ignored.
7132 *
7133 * Don't enable denormals for 32-bit floats, because:
7134 * - Floating-point output modifiers would be ignored by the hw.
7135 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7136 * have to stop using those.
7137 * - SI & CI would be very slow.
7138 */
7139 config->float_mode |= V_00B028_FP_64_DENORMS;
7140 }
7141
7142 static void
7143 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7144 {
7145 switch (nir->info.stage) {
7146 case MESA_SHADER_COMPUTE:
7147 for (int i = 0; i < 3; ++i)
7148 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7149 break;
7150 case MESA_SHADER_FRAGMENT:
7151 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7152 break;
7153 case MESA_SHADER_GEOMETRY:
7154 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7155 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7156 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7157 shader_info->gs.invocations = nir->info.gs.invocations;
7158 break;
7159 case MESA_SHADER_TESS_EVAL:
7160 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7161 shader_info->tes.spacing = nir->info.tess.spacing;
7162 shader_info->tes.ccw = nir->info.tess.ccw;
7163 shader_info->tes.point_mode = nir->info.tess.point_mode;
7164 shader_info->tes.as_es = options->key.tes.as_es;
7165 break;
7166 case MESA_SHADER_TESS_CTRL:
7167 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7168 break;
7169 case MESA_SHADER_VERTEX:
7170 shader_info->vs.as_es = options->key.vs.as_es;
7171 shader_info->vs.as_ls = options->key.vs.as_ls;
7172 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7173 if (options->key.vs.as_ls)
7174 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7175 break;
7176 default:
7177 break;
7178 }
7179 }
7180
7181 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7182 struct ac_shader_binary *binary,
7183 struct ac_shader_config *config,
7184 struct ac_shader_variant_info *shader_info,
7185 struct nir_shader *const *nir,
7186 int nir_count,
7187 const struct ac_nir_compiler_options *options,
7188 bool dump_shader)
7189 {
7190
7191 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7192 options, dump_shader);
7193
7194 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7195 for (int i = 0; i < nir_count; ++i)
7196 ac_fill_shader_info(shader_info, nir[i], options);
7197
7198 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7199 if (options->chip_class == GFX9) {
7200 if (nir_count == 2 &&
7201 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7202 shader_info->gs.es_type = nir[0]->info.stage;
7203 }
7204 }
7205 }
7206
7207 static void
7208 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7209 {
7210 LLVMValueRef vtx_offset =
7211 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7212 LLVMConstInt(ctx->ac.i32, 4, false), "");
7213 int idx = 0;
7214
7215 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7216 int length = 4;
7217 int slot = idx;
7218 int slot_inc = 1;
7219 if (!(ctx->output_mask & (1ull << i)))
7220 continue;
7221
7222 if (i == VARYING_SLOT_CLIP_DIST0) {
7223 /* unpack clip and cull from a single set of slots */
7224 length = ctx->num_output_clips + ctx->num_output_culls;
7225 if (length > 4)
7226 slot_inc = 2;
7227 }
7228
7229 for (unsigned j = 0; j < length; j++) {
7230 LLVMValueRef value, soffset;
7231
7232 soffset = LLVMConstInt(ctx->ac.i32,
7233 (slot * 4 + j) *
7234 ctx->gs_max_out_vertices * 16 * 4, false);
7235
7236 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7237 1, ctx->ac.i32_0,
7238 vtx_offset, soffset,
7239 0, 1, 1, true, false);
7240
7241 LLVMBuildStore(ctx->ac.builder,
7242 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7243 }
7244 idx += slot_inc;
7245 }
7246 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7247 }
7248
7249 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7250 struct nir_shader *geom_shader,
7251 struct ac_shader_binary *binary,
7252 struct ac_shader_config *config,
7253 struct ac_shader_variant_info *shader_info,
7254 const struct ac_nir_compiler_options *options,
7255 bool dump_shader)
7256 {
7257 struct radv_shader_context ctx = {0};
7258 ctx.context = LLVMContextCreate();
7259 ctx.options = options;
7260 ctx.shader_info = shader_info;
7261
7262 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7263 options->family);
7264 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7265
7266 ctx.is_gs_copy_shader = true;
7267 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7268
7269 enum ac_float_mode float_mode =
7270 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7271 AC_FLOAT_MODE_DEFAULT;
7272
7273 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7274 ctx.stage = MESA_SHADER_VERTEX;
7275
7276 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7277
7278 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7279 ac_setup_rings(&ctx);
7280
7281 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7282 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7283
7284 struct ac_nir_context nir_ctx = {};
7285 nir_ctx.ac = ctx.ac;
7286 nir_ctx.abi = &ctx.abi;
7287
7288 nir_foreach_variable(variable, &geom_shader->outputs) {
7289 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7290 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7291 }
7292
7293 ac_gs_copy_shader_emit(&ctx);
7294
7295 LLVMBuildRetVoid(ctx.ac.builder);
7296
7297 ac_llvm_finalize_module(&ctx);
7298
7299 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7300 MESA_SHADER_VERTEX,
7301 dump_shader, options->supports_spill);
7302 }
7303
7304 void
7305 ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class chip_class)
7306 {
7307 /* While it would be nice not to have this flag, we are constrained
7308 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
7309 * on GFX9.
7310 */
7311 bool llvm_has_working_vgpr_indexing = chip_class <= VI;
7312
7313 /* TODO: Indirect indexing of GS inputs is unimplemented.
7314 *
7315 * TCS and TES load inputs directly from LDS or offchip memory, so
7316 * indirect indexing is trivial.
7317 */
7318 nir_variable_mode indirect_mask = 0;
7319 if (nir->info.stage == MESA_SHADER_GEOMETRY ||
7320 (nir->info.stage != MESA_SHADER_TESS_CTRL &&
7321 nir->info.stage != MESA_SHADER_TESS_EVAL &&
7322 !llvm_has_working_vgpr_indexing)) {
7323 indirect_mask |= nir_var_shader_in;
7324 }
7325 if (!llvm_has_working_vgpr_indexing &&
7326 nir->info.stage != MESA_SHADER_TESS_CTRL)
7327 indirect_mask |= nir_var_shader_out;
7328
7329 /* TODO: We shouldn't need to do this, however LLVM isn't currently
7330 * smart enough to handle indirects without causing excess spilling
7331 * causing the gpu to hang.
7332 *
7333 * See the following thread for more details of the problem:
7334 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
7335 */
7336 indirect_mask |= nir_var_local;
7337
7338 nir_lower_indirect_derefs(nir, indirect_mask);
7339 }