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radv: do not load the local invocation index when it's unused
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef merged_wave_info;
112 LLVMValueRef tess_factor_offset;
113 LLVMValueRef tcs_patch_id;
114 LLVMValueRef tcs_rel_ids;
115 LLVMValueRef tes_rel_patch_id;
116 LLVMValueRef tes_patch_id;
117 LLVMValueRef tes_u;
118 LLVMValueRef tes_v;
119
120 LLVMValueRef gsvs_ring_stride;
121 LLVMValueRef gsvs_num_entries;
122 LLVMValueRef gs2vs_offset;
123 LLVMValueRef gs_wave_id;
124 LLVMValueRef gs_vtx_offset[6];
125
126 LLVMValueRef esgs_ring;
127 LLVMValueRef gsvs_ring;
128 LLVMValueRef hs_ring_tess_offchip;
129 LLVMValueRef hs_ring_tess_factor;
130
131 LLVMValueRef prim_mask;
132 LLVMValueRef sample_pos_offset;
133 LLVMValueRef persp_sample, persp_center, persp_centroid;
134 LLVMValueRef linear_sample, linear_center, linear_centroid;
135
136 gl_shader_stage stage;
137
138 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
139
140 uint64_t input_mask;
141 uint64_t output_mask;
142 uint8_t num_output_clips;
143 uint8_t num_output_culls;
144
145 bool is_gs_copy_shader;
146 LLVMValueRef gs_next_vertex;
147 unsigned gs_max_out_vertices;
148
149 unsigned tes_primitive_mode;
150 uint64_t tess_outputs_written;
151 uint64_t tess_patch_outputs_written;
152
153 uint32_t tcs_patch_outputs_read;
154 uint64_t tcs_outputs_read;
155 };
156
157 static inline struct nir_to_llvm_context *
158 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
159 {
160 struct nir_to_llvm_context *ctx = NULL;
161 return container_of(abi, ctx, abi);
162 }
163
164 static LLVMTypeRef
165 nir2llvmtype(struct ac_nir_context *ctx,
166 const struct glsl_type *type)
167 {
168 switch (glsl_get_base_type(glsl_without_array(type))) {
169 case GLSL_TYPE_UINT:
170 case GLSL_TYPE_INT:
171 return ctx->ac.i32;
172 case GLSL_TYPE_UINT64:
173 case GLSL_TYPE_INT64:
174 return ctx->ac.i64;
175 case GLSL_TYPE_DOUBLE:
176 return ctx->ac.f64;
177 case GLSL_TYPE_FLOAT:
178 return ctx->ac.f32;
179 default:
180 assert(!"Unsupported type in nir2llvmtype()");
181 break;
182 }
183 return 0;
184 }
185
186 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
187 const nir_deref_var *deref,
188 enum ac_descriptor_type desc_type,
189 const nir_tex_instr *instr,
190 bool image, bool write);
191
192 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
193 {
194 return (index * 4) + chan;
195 }
196
197 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
198 {
199 /* handle patch indices separate */
200 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
201 return 0;
202 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
203 return 1;
204 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
205 return 2 + (slot - VARYING_SLOT_PATCH0);
206
207 if (slot == VARYING_SLOT_POS)
208 return 0;
209 if (slot == VARYING_SLOT_PSIZ)
210 return 1;
211 if (slot == VARYING_SLOT_CLIP_DIST0)
212 return 2;
213 /* 3 is reserved for clip dist as well */
214 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
215 return 4 + (slot - VARYING_SLOT_VAR0);
216 unreachable("illegal slot in get unique index\n");
217 }
218
219 static void set_llvm_calling_convention(LLVMValueRef func,
220 gl_shader_stage stage)
221 {
222 enum radeon_llvm_calling_convention calling_conv;
223
224 switch (stage) {
225 case MESA_SHADER_VERTEX:
226 case MESA_SHADER_TESS_EVAL:
227 calling_conv = RADEON_LLVM_AMDGPU_VS;
228 break;
229 case MESA_SHADER_GEOMETRY:
230 calling_conv = RADEON_LLVM_AMDGPU_GS;
231 break;
232 case MESA_SHADER_TESS_CTRL:
233 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
234 break;
235 case MESA_SHADER_FRAGMENT:
236 calling_conv = RADEON_LLVM_AMDGPU_PS;
237 break;
238 case MESA_SHADER_COMPUTE:
239 calling_conv = RADEON_LLVM_AMDGPU_CS;
240 break;
241 default:
242 unreachable("Unhandle shader type");
243 }
244
245 LLVMSetFunctionCallConv(func, calling_conv);
246 }
247
248 #define MAX_ARGS 23
249 struct arg_info {
250 LLVMTypeRef types[MAX_ARGS];
251 LLVMValueRef *assign[MAX_ARGS];
252 unsigned array_params_mask;
253 uint8_t count;
254 uint8_t user_sgpr_count;
255 uint8_t sgpr_count;
256 uint8_t num_user_sgprs_used;
257 uint8_t num_sgprs_used;
258 uint8_t num_vgprs_used;
259 };
260
261 static inline void
262 add_argument(struct arg_info *info,
263 LLVMTypeRef type, LLVMValueRef *param_ptr)
264 {
265 assert(info->count < MAX_ARGS);
266 info->assign[info->count] = param_ptr;
267 info->types[info->count] = type;
268 info->count++;
269 }
270
271 static inline void
272 add_sgpr_argument(struct arg_info *info,
273 LLVMTypeRef type, LLVMValueRef *param_ptr)
274 {
275 add_argument(info, type, param_ptr);
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 }
279
280 static inline void
281 add_user_sgpr_argument(struct arg_info *info,
282 LLVMTypeRef type,
283 LLVMValueRef *param_ptr)
284 {
285 add_sgpr_argument(info, type, param_ptr);
286 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
287 info->user_sgpr_count++;
288 }
289
290 static inline void
291 add_vgpr_argument(struct arg_info *info,
292 LLVMTypeRef type,
293 LLVMValueRef *param_ptr)
294 {
295 add_argument(info, type, param_ptr);
296 info->num_vgprs_used += ac_get_type_size(type) / 4;
297 }
298
299 static inline void
300 add_user_sgpr_array_argument(struct arg_info *info,
301 LLVMTypeRef type,
302 LLVMValueRef *param_ptr)
303 {
304 info->array_params_mask |= (1 << info->count);
305 add_user_sgpr_argument(info, type, param_ptr);
306 }
307
308 static void assign_arguments(LLVMValueRef main_function,
309 struct arg_info *info)
310 {
311 unsigned i;
312 for (i = 0; i < info->count; i++) {
313 if (info->assign[i])
314 *info->assign[i] = LLVMGetParam(main_function, i);
315 }
316 }
317
318 static LLVMValueRef
319 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
320 LLVMBuilderRef builder, LLVMTypeRef *return_types,
321 unsigned num_return_elems,
322 struct arg_info *args,
323 unsigned max_workgroup_size,
324 bool unsafe_math)
325 {
326 LLVMTypeRef main_function_type, ret_type;
327 LLVMBasicBlockRef main_function_body;
328
329 if (num_return_elems)
330 ret_type = LLVMStructTypeInContext(ctx, return_types,
331 num_return_elems, true);
332 else
333 ret_type = LLVMVoidTypeInContext(ctx);
334
335 /* Setup the function */
336 main_function_type =
337 LLVMFunctionType(ret_type, args->types, args->count, 0);
338 LLVMValueRef main_function =
339 LLVMAddFunction(module, "main", main_function_type);
340 main_function_body =
341 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
342 LLVMPositionBuilderAtEnd(builder, main_function_body);
343
344 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
345 for (unsigned i = 0; i < args->sgpr_count; ++i) {
346 if (args->array_params_mask & (1 << i)) {
347 LLVMValueRef P = LLVMGetParam(main_function, i);
348 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
349 ac_add_attr_dereferenceable(P, UINT64_MAX);
350 }
351 else {
352 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
353 }
354 }
355
356 if (max_workgroup_size) {
357 ac_llvm_add_target_dep_function_attr(main_function,
358 "amdgpu-max-work-group-size",
359 max_workgroup_size);
360 }
361 if (unsafe_math) {
362 /* These were copied from some LLVM test. */
363 LLVMAddTargetDependentFunctionAttr(main_function,
364 "less-precise-fpmad",
365 "true");
366 LLVMAddTargetDependentFunctionAttr(main_function,
367 "no-infs-fp-math",
368 "true");
369 LLVMAddTargetDependentFunctionAttr(main_function,
370 "no-nans-fp-math",
371 "true");
372 LLVMAddTargetDependentFunctionAttr(main_function,
373 "unsafe-fp-math",
374 "true");
375 }
376 return main_function;
377 }
378
379 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
380 {
381 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
382 CONST_ADDR_SPACE);
383 }
384
385 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
386 {
387 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
388 type = LLVMGetElementType(type);
389
390 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
391 return LLVMGetIntTypeWidth(type);
392
393 if (type == ctx->f16)
394 return 16;
395 if (type == ctx->f32)
396 return 32;
397 if (type == ctx->f64)
398 return 64;
399
400 unreachable("Unhandled type kind in get_elem_bits");
401 }
402
403 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
404 LLVMValueRef param, unsigned rshift,
405 unsigned bitwidth)
406 {
407 LLVMValueRef value = param;
408 if (rshift)
409 value = LLVMBuildLShr(ctx->builder, value,
410 LLVMConstInt(ctx->i32, rshift, false), "");
411
412 if (rshift + bitwidth < 32) {
413 unsigned mask = (1 << bitwidth) - 1;
414 value = LLVMBuildAnd(ctx->builder, value,
415 LLVMConstInt(ctx->i32, mask, false), "");
416 }
417 return value;
418 }
419
420 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
421 {
422 switch (ctx->stage) {
423 case MESA_SHADER_TESS_CTRL:
424 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
425 case MESA_SHADER_TESS_EVAL:
426 return ctx->tes_rel_patch_id;
427 break;
428 default:
429 unreachable("Illegal stage");
430 }
431 }
432
433 /* Tessellation shaders pass outputs to the next shader using LDS.
434 *
435 * LS outputs = TCS inputs
436 * TCS outputs = TES inputs
437 *
438 * The LDS layout is:
439 * - TCS inputs for patch 0
440 * - TCS inputs for patch 1
441 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
442 * - ...
443 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
444 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
445 * - TCS outputs for patch 1
446 * - Per-patch TCS outputs for patch 1
447 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
448 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
449 * - ...
450 *
451 * All three shaders VS(LS), TCS, TES share the same LDS space.
452 */
453 static LLVMValueRef
454 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
455 {
456 if (ctx->stage == MESA_SHADER_VERTEX)
457 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
458 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
459 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
460 else {
461 assert(0);
462 return NULL;
463 }
464 }
465
466 static LLVMValueRef
467 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
468 {
469 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
470 }
471
472 static LLVMValueRef
473 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
474 {
475 return LLVMBuildMul(ctx->builder,
476 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
477 LLVMConstInt(ctx->ac.i32, 4, false), "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
482 {
483 return LLVMBuildMul(ctx->builder,
484 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
485 LLVMConstInt(ctx->ac.i32, 4, false), "");
486 }
487
488 static LLVMValueRef
489 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
490 {
491 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
492 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
493
494 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
495 }
496
497 static LLVMValueRef
498 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
499 {
500 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
501 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
502 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
503
504 return LLVMBuildAdd(ctx->builder, patch0_offset,
505 LLVMBuildMul(ctx->builder, patch_stride,
506 rel_patch_id, ""),
507 "");
508 }
509
510 static LLVMValueRef
511 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
512 {
513 LLVMValueRef patch0_patch_data_offset =
514 get_tcs_out_patch0_patch_data_offset(ctx);
515 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
516 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
517
518 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
519 LLVMBuildMul(ctx->builder, patch_stride,
520 rel_patch_id, ""),
521 "");
522 }
523
524 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
525 {
526 ud_info->sgpr_idx = *sgpr_idx;
527 ud_info->num_sgprs = num_sgprs;
528 ud_info->indirect = false;
529 ud_info->indirect_offset = 0;
530 *sgpr_idx += num_sgprs;
531 }
532
533 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
534 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
535 {
536 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
537 }
538
539
540 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
541 uint32_t indirect_offset)
542 {
543 ud_info->sgpr_idx = sgpr_idx;
544 ud_info->num_sgprs = num_sgprs;
545 ud_info->indirect = true;
546 ud_info->indirect_offset = indirect_offset;
547 }
548
549 struct user_sgpr_info {
550 bool need_ring_offsets;
551 uint8_t sgpr_count;
552 bool indirect_all_descriptor_sets;
553 };
554
555 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
556 struct user_sgpr_info *user_sgpr_info)
557 {
558 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
559
560 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
561 if (ctx->stage == MESA_SHADER_GEOMETRY ||
562 ctx->stage == MESA_SHADER_VERTEX ||
563 ctx->stage == MESA_SHADER_TESS_CTRL ||
564 ctx->stage == MESA_SHADER_TESS_EVAL ||
565 ctx->is_gs_copy_shader)
566 user_sgpr_info->need_ring_offsets = true;
567
568 if (ctx->stage == MESA_SHADER_FRAGMENT &&
569 ctx->shader_info->info.ps.needs_sample_positions)
570 user_sgpr_info->need_ring_offsets = true;
571
572 /* 2 user sgprs will nearly always be allocated for scratch/rings */
573 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
574 user_sgpr_info->sgpr_count += 2;
575 }
576
577 switch (ctx->stage) {
578 case MESA_SHADER_COMPUTE:
579 if (ctx->shader_info->info.cs.uses_grid_size)
580 user_sgpr_info->sgpr_count += 3;
581 break;
582 case MESA_SHADER_FRAGMENT:
583 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
584 break;
585 case MESA_SHADER_VERTEX:
586 if (!ctx->is_gs_copy_shader) {
587 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
588 if (ctx->shader_info->info.vs.needs_draw_id) {
589 user_sgpr_info->sgpr_count += 3;
590 } else {
591 user_sgpr_info->sgpr_count += 2;
592 }
593 }
594 if (ctx->options->key.vs.as_ls)
595 user_sgpr_info->sgpr_count++;
596 break;
597 case MESA_SHADER_TESS_CTRL:
598 user_sgpr_info->sgpr_count += 4;
599 break;
600 case MESA_SHADER_TESS_EVAL:
601 user_sgpr_info->sgpr_count += 1;
602 break;
603 case MESA_SHADER_GEOMETRY:
604 user_sgpr_info->sgpr_count += 2;
605 break;
606 default:
607 break;
608 }
609
610 if (ctx->shader_info->info.needs_push_constants)
611 user_sgpr_info->sgpr_count += 2;
612
613 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
614 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
615 user_sgpr_info->sgpr_count += 2;
616 user_sgpr_info->indirect_all_descriptor_sets = true;
617 } else {
618 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
619 }
620 }
621
622 static void
623 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
624 gl_shader_stage stage,
625 bool has_previous_stage,
626 gl_shader_stage previous_stage,
627 const struct user_sgpr_info *user_sgpr_info,
628 struct arg_info *args,
629 LLVMValueRef *desc_sets)
630 {
631 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
632 unsigned stage_mask = 1 << stage;
633 if (has_previous_stage)
634 stage_mask |= 1 << previous_stage;
635
636 /* 1 for each descriptor set */
637 if (!user_sgpr_info->indirect_all_descriptor_sets) {
638 for (unsigned i = 0; i < num_sets; ++i) {
639 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
640 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->descriptor_sets[i]);
641 }
642 }
643 } else
644 add_user_sgpr_array_argument(args, const_array(const_array(ctx->ac.i8, 1024 * 1024), 32), desc_sets);
645
646 if (ctx->shader_info->info.needs_push_constants) {
647 /* 1 for push constants and dynamic descriptors */
648 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->push_constants);
649 }
650 }
651
652 static void
653 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
654 gl_shader_stage stage,
655 bool has_previous_stage,
656 gl_shader_stage previous_stage,
657 const struct user_sgpr_info *user_sgpr_info,
658 LLVMValueRef desc_sets,
659 uint8_t *user_sgpr_idx)
660 {
661 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
662 unsigned stage_mask = 1 << stage;
663 if (has_previous_stage)
664 stage_mask |= 1 << previous_stage;
665
666 if (!user_sgpr_info->indirect_all_descriptor_sets) {
667 for (unsigned i = 0; i < num_sets; ++i) {
668 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
669 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
670 } else
671 ctx->descriptor_sets[i] = NULL;
672 }
673 } else {
674 uint32_t desc_sgpr_idx = *user_sgpr_idx;
675 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
676
677 for (unsigned i = 0; i < num_sets; ++i) {
678 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
679 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
680 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
681
682 } else
683 ctx->descriptor_sets[i] = NULL;
684 }
685 ctx->shader_info->need_indirect_descriptor_sets = true;
686 }
687
688 if (ctx->shader_info->info.needs_push_constants) {
689 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
690 }
691 }
692
693 static void
694 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
695 gl_shader_stage stage,
696 bool has_previous_stage,
697 gl_shader_stage previous_stage,
698 struct arg_info *args)
699 {
700 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
701 if (ctx->shader_info->info.vs.has_vertex_buffers)
702 add_user_sgpr_argument(args, const_array(ctx->ac.v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
703 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.base_vertex); // base vertex
704 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.start_instance);// start instance
705 if (ctx->shader_info->info.vs.needs_draw_id)
706 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.draw_id); // draw id
707 }
708 }
709
710 static void
711 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
712 gl_shader_stage stage,
713 bool has_previous_stage,
714 gl_shader_stage previous_stage,
715 uint8_t *user_sgpr_idx)
716 {
717 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
718 if (ctx->shader_info->info.vs.has_vertex_buffers) {
719 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
720 }
721 unsigned vs_num = 2;
722 if (ctx->shader_info->info.vs.needs_draw_id)
723 vs_num++;
724
725 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
726 }
727 }
728
729
730 static void create_function(struct nir_to_llvm_context *ctx,
731 gl_shader_stage stage,
732 bool has_previous_stage,
733 gl_shader_stage previous_stage)
734 {
735 uint8_t user_sgpr_idx;
736 struct user_sgpr_info user_sgpr_info;
737 struct arg_info args = {};
738 LLVMValueRef desc_sets;
739
740 allocate_user_sgprs(ctx, &user_sgpr_info);
741
742 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
743 add_user_sgpr_argument(&args, const_array(ctx->ac.v4i32, 16), &ctx->ring_offsets); /* address of rings */
744 }
745
746 switch (stage) {
747 case MESA_SHADER_COMPUTE:
748 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
749 if (ctx->shader_info->info.cs.uses_grid_size) {
750 add_user_sgpr_argument(&args, ctx->ac.v3i32,
751 &ctx->num_work_groups);
752 }
753 add_sgpr_argument(&args, ctx->ac.v3i32, &ctx->workgroup_ids);
754 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
755 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
756 add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
757 break;
758 case MESA_SHADER_VERTEX:
759 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
760 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
761 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
762 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
763 if (ctx->options->key.vs.as_es)
764 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
765 else if (ctx->options->key.vs.as_ls)
766 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
767 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
768 if (!ctx->is_gs_copy_shader) {
769 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
770 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
771 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
772 }
773 break;
774 case MESA_SHADER_TESS_CTRL:
775 if (has_previous_stage) {
776 // First 6 system regs
777 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
778 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
779 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
780
781 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
782 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
783 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
784
785 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
786 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
787 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
788
789 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
790 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
791 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
792 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
793 if (ctx->shader_info->info.needs_multiview_view_index)
794 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
795
796 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
797 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
798 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
799 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
800 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
801 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
802 } else {
803 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
804 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
805 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
806 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
807 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
808 if (ctx->shader_info->info.needs_multiview_view_index)
809 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
810 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
811 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
812 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
813 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
814 }
815 break;
816 case MESA_SHADER_TESS_EVAL:
817 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
818 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
819 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
820 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
821 if (ctx->options->key.tes.as_es) {
822 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
823 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
824 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
825 } else {
826 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
827 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
828 }
829 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
830 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
831 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
832 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
833 break;
834 case MESA_SHADER_GEOMETRY:
835 if (has_previous_stage) {
836 // First 6 system regs
837 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
838 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
839 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
840
841 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
842 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
843 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
844
845 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
846 if (previous_stage == MESA_SHADER_TESS_EVAL)
847 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
848 else
849 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
850 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
851 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
852 if (ctx->shader_info->info.needs_multiview_view_index)
853 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
854
855 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx01
856 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]); // vtx23
857 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
858 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
859 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
860
861 if (previous_stage == MESA_SHADER_VERTEX) {
862 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
863 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
864 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
865 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
866 } else {
867 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_u); // tes_u
868 add_vgpr_argument(&args, ctx->ac.f32, &ctx->tes_v); // tes_v
869 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
870 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
871 }
872 } else {
873 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
874 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
875 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
876 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
877 if (ctx->shader_info->info.needs_multiview_view_index)
878 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
879 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
880 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
881 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx0
882 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[1]); // vtx1
883 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_prim_id); // prim id
884 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]);
885 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[3]);
886 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
887 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[5]);
888 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.gs_invocation_id);
889 }
890 break;
891 case MESA_SHADER_FRAGMENT:
892 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
893 if (ctx->shader_info->info.ps.needs_sample_positions)
894 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */
895 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
896 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /* persp sample */
897 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /* persp center */
898 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid); /* persp centroid */
899 add_vgpr_argument(&args, ctx->ac.v3i32, NULL); /* persp pull model */
900 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_sample); /* linear sample */
901 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_center); /* linear center */
902 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_centroid); /* linear centroid */
903 add_vgpr_argument(&args, ctx->ac.f32, NULL); /* line stipple tex */
904 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[0]); /* pos x float */
905 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[1]); /* pos y float */
906 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[2]); /* pos z float */
907 add_vgpr_argument(&args, ctx->ac.f32, &ctx->abi.frag_pos[3]); /* pos w float */
908 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */
909 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */
910 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.sample_coverage); /* sample coverage */
911 add_vgpr_argument(&args, ctx->ac.i32, NULL); /* fixed pt */
912 break;
913 default:
914 unreachable("Shader stage not implemented");
915 }
916
917 ctx->main_function = create_llvm_function(
918 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
919 ctx->max_workgroup_size,
920 ctx->options->unsafe_math);
921 set_llvm_calling_convention(ctx->main_function, stage);
922
923
924 ctx->shader_info->num_input_vgprs = 0;
925 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
926
927 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
928
929 if (ctx->stage != MESA_SHADER_FRAGMENT)
930 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
931
932 assign_arguments(ctx->main_function, &args);
933
934 user_sgpr_idx = 0;
935
936 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
937 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
938 if (ctx->options->supports_spill) {
939 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
940 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
941 NULL, 0, AC_FUNC_ATTR_READNONE);
942 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
943 const_array(ctx->ac.v4i32, 16), "");
944 }
945 }
946
947 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
948 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
949 if (has_previous_stage)
950 user_sgpr_idx = 0;
951
952 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
953
954 switch (stage) {
955 case MESA_SHADER_COMPUTE:
956 if (ctx->shader_info->info.cs.uses_grid_size) {
957 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE,
958 &user_sgpr_idx, 3);
959 }
960 break;
961 case MESA_SHADER_VERTEX:
962 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
963 if (ctx->view_index)
964 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
965 if (ctx->options->key.vs.as_ls) {
966 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
967 }
968 if (ctx->options->key.vs.as_ls)
969 ac_declare_lds_as_pointer(&ctx->ac);
970 break;
971 case MESA_SHADER_TESS_CTRL:
972 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
973 if (has_previous_stage)
974 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
975 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
976 if (ctx->view_index)
977 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
978 ac_declare_lds_as_pointer(&ctx->ac);
979 break;
980 case MESA_SHADER_TESS_EVAL:
981 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
982 if (ctx->view_index)
983 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
984 break;
985 case MESA_SHADER_GEOMETRY:
986 if (has_previous_stage) {
987 if (previous_stage == MESA_SHADER_VERTEX)
988 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
989 else
990 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
991 }
992 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
993 if (ctx->view_index)
994 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
995 if (has_previous_stage)
996 ac_declare_lds_as_pointer(&ctx->ac);
997 break;
998 case MESA_SHADER_FRAGMENT:
999 if (ctx->shader_info->info.ps.needs_sample_positions) {
1000 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
1001 }
1002 break;
1003 default:
1004 unreachable("Shader stage not implemented");
1005 }
1006
1007 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1008 }
1009
1010 static int get_llvm_num_components(LLVMValueRef value)
1011 {
1012 LLVMTypeRef type = LLVMTypeOf(value);
1013 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1014 ? LLVMGetVectorSize(type)
1015 : 1;
1016 return num_components;
1017 }
1018
1019 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1020 LLVMValueRef value,
1021 int index)
1022 {
1023 int count = get_llvm_num_components(value);
1024
1025 if (count == 1)
1026 return value;
1027
1028 return LLVMBuildExtractElement(ac->builder, value,
1029 LLVMConstInt(ac->i32, index, false), "");
1030 }
1031
1032 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1033 LLVMValueRef value, unsigned count)
1034 {
1035 unsigned num_components = get_llvm_num_components(value);
1036 if (count == num_components)
1037 return value;
1038
1039 LLVMValueRef masks[] = {
1040 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1041 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1042
1043 if (count == 1)
1044 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1045 "");
1046
1047 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1048 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1049 }
1050
1051 static void
1052 build_store_values_extended(struct ac_llvm_context *ac,
1053 LLVMValueRef *values,
1054 unsigned value_count,
1055 unsigned value_stride,
1056 LLVMValueRef vec)
1057 {
1058 LLVMBuilderRef builder = ac->builder;
1059 unsigned i;
1060
1061 for (i = 0; i < value_count; i++) {
1062 LLVMValueRef ptr = values[i * value_stride];
1063 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1064 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1065 LLVMBuildStore(builder, value, ptr);
1066 }
1067 }
1068
1069 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1070 const nir_ssa_def *def)
1071 {
1072 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1073 if (def->num_components > 1) {
1074 type = LLVMVectorType(type, def->num_components);
1075 }
1076 return type;
1077 }
1078
1079 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1080 {
1081 assert(src.is_ssa);
1082 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1083 return (LLVMValueRef)entry->data;
1084 }
1085
1086
1087 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1088 const struct nir_block *b)
1089 {
1090 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1091 return (LLVMBasicBlockRef)entry->data;
1092 }
1093
1094 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1095 nir_alu_src src,
1096 unsigned num_components)
1097 {
1098 LLVMValueRef value = get_src(ctx, src.src);
1099 bool need_swizzle = false;
1100
1101 assert(value);
1102 LLVMTypeRef type = LLVMTypeOf(value);
1103 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1104 ? LLVMGetVectorSize(type)
1105 : 1;
1106
1107 for (unsigned i = 0; i < num_components; ++i) {
1108 assert(src.swizzle[i] < src_components);
1109 if (src.swizzle[i] != i)
1110 need_swizzle = true;
1111 }
1112
1113 if (need_swizzle || num_components != src_components) {
1114 LLVMValueRef masks[] = {
1115 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1116 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1117 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1118 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1119
1120 if (src_components > 1 && num_components == 1) {
1121 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1122 masks[0], "");
1123 } else if (src_components == 1 && num_components > 1) {
1124 LLVMValueRef values[] = {value, value, value, value};
1125 value = ac_build_gather_values(&ctx->ac, values, num_components);
1126 } else {
1127 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1128 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1129 swizzle, "");
1130 }
1131 }
1132 assert(!src.negate);
1133 assert(!src.abs);
1134 return value;
1135 }
1136
1137 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1138 LLVMIntPredicate pred, LLVMValueRef src0,
1139 LLVMValueRef src1)
1140 {
1141 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1142 return LLVMBuildSelect(ctx->builder, result,
1143 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1144 LLVMConstInt(ctx->i32, 0, false), "");
1145 }
1146
1147 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1148 LLVMRealPredicate pred, LLVMValueRef src0,
1149 LLVMValueRef src1)
1150 {
1151 LLVMValueRef result;
1152 src0 = ac_to_float(ctx, src0);
1153 src1 = ac_to_float(ctx, src1);
1154 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1155 return LLVMBuildSelect(ctx->builder, result,
1156 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1157 LLVMConstInt(ctx->i32, 0, false), "");
1158 }
1159
1160 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1161 const char *intrin,
1162 LLVMTypeRef result_type,
1163 LLVMValueRef src0)
1164 {
1165 char name[64];
1166 LLVMValueRef params[] = {
1167 ac_to_float(ctx, src0),
1168 };
1169
1170 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1171 get_elem_bits(ctx, result_type));
1172 assert(length < sizeof(name));
1173 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1174 }
1175
1176 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1177 const char *intrin,
1178 LLVMTypeRef result_type,
1179 LLVMValueRef src0, LLVMValueRef src1)
1180 {
1181 char name[64];
1182 LLVMValueRef params[] = {
1183 ac_to_float(ctx, src0),
1184 ac_to_float(ctx, src1),
1185 };
1186
1187 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1188 get_elem_bits(ctx, result_type));
1189 assert(length < sizeof(name));
1190 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1191 }
1192
1193 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1194 const char *intrin,
1195 LLVMTypeRef result_type,
1196 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1197 {
1198 char name[64];
1199 LLVMValueRef params[] = {
1200 ac_to_float(ctx, src0),
1201 ac_to_float(ctx, src1),
1202 ac_to_float(ctx, src2),
1203 };
1204
1205 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1206 get_elem_bits(ctx, result_type));
1207 assert(length < sizeof(name));
1208 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1209 }
1210
1211 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1212 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1213 {
1214 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1215 ctx->i32_0, "");
1216 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1217 }
1218
1219 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1220 LLVMIntPredicate pred,
1221 LLVMValueRef src0, LLVMValueRef src1)
1222 {
1223 return LLVMBuildSelect(ctx->builder,
1224 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1225 src0,
1226 src1, "");
1227
1228 }
1229 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1230 LLVMValueRef src0)
1231 {
1232 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1233 LLVMBuildNeg(ctx->builder, src0, ""));
1234 }
1235
1236 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1237 LLVMValueRef src0)
1238 {
1239 LLVMValueRef cmp, val;
1240
1241 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1242 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1243 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1244 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1245 return val;
1246 }
1247
1248 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1249 LLVMValueRef src0)
1250 {
1251 LLVMValueRef cmp, val;
1252
1253 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1254 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1255 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1256 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1257 return val;
1258 }
1259
1260 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1261 LLVMValueRef src0)
1262 {
1263 const char *intr = "llvm.floor.f32";
1264 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1265 LLVMValueRef params[] = {
1266 fsrc0,
1267 };
1268 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1269 ctx->f32, params, 1,
1270 AC_FUNC_ATTR_READNONE);
1271 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1272 }
1273
1274 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1275 const char *intrin,
1276 LLVMValueRef src0, LLVMValueRef src1)
1277 {
1278 LLVMTypeRef ret_type;
1279 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1280 LLVMValueRef res;
1281 LLVMValueRef params[] = { src0, src1 };
1282 ret_type = LLVMStructTypeInContext(ctx->context, types,
1283 2, true);
1284
1285 res = ac_build_intrinsic(ctx, intrin, ret_type,
1286 params, 2, AC_FUNC_ATTR_READNONE);
1287
1288 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1289 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1290 return res;
1291 }
1292
1293 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1294 LLVMValueRef src0)
1295 {
1296 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1297 }
1298
1299 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1300 LLVMValueRef src0)
1301 {
1302 src0 = ac_to_float(ctx, src0);
1303 return LLVMBuildSExt(ctx->builder,
1304 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1305 ctx->i32, "");
1306 }
1307
1308 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1309 LLVMValueRef src0)
1310 {
1311 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1312 }
1313
1314 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1315 LLVMValueRef src0)
1316 {
1317 return LLVMBuildSExt(ctx->builder,
1318 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1319 ctx->i32, "");
1320 }
1321
1322 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1323 LLVMValueRef src0)
1324 {
1325 LLVMValueRef result;
1326 LLVMValueRef cond = NULL;
1327
1328 src0 = ac_to_float(&ctx->ac, src0);
1329 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1330
1331 if (ctx->options->chip_class >= VI) {
1332 LLVMValueRef args[2];
1333 /* Check if the result is a denormal - and flush to 0 if so. */
1334 args[0] = result;
1335 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1336 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1337 }
1338
1339 /* need to convert back up to f32 */
1340 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1341
1342 if (ctx->options->chip_class >= VI)
1343 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1344 else {
1345 /* for SI/CIK */
1346 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1347 * so compare the result and flush to 0 if it's smaller.
1348 */
1349 LLVMValueRef temp, cond2;
1350 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1351 ctx->ac.f32, result);
1352 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1353 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1354 temp, "");
1355 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1356 temp, ctx->ac.f32_0, "");
1357 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1358 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1359 }
1360 return result;
1361 }
1362
1363 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1364 LLVMValueRef src0, LLVMValueRef src1)
1365 {
1366 LLVMValueRef dst64, result;
1367 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1368 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1369
1370 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1371 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1372 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1373 return result;
1374 }
1375
1376 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1377 LLVMValueRef src0, LLVMValueRef src1)
1378 {
1379 LLVMValueRef dst64, result;
1380 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1381 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1382
1383 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1384 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1385 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1386 return result;
1387 }
1388
1389 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1390 bool is_signed,
1391 const LLVMValueRef srcs[3])
1392 {
1393 LLVMValueRef result;
1394 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1395
1396 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1397 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1398 return result;
1399 }
1400
1401 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1402 LLVMValueRef src0, LLVMValueRef src1,
1403 LLVMValueRef src2, LLVMValueRef src3)
1404 {
1405 LLVMValueRef bfi_args[3], result;
1406
1407 bfi_args[0] = LLVMBuildShl(ctx->builder,
1408 LLVMBuildSub(ctx->builder,
1409 LLVMBuildShl(ctx->builder,
1410 ctx->i32_1,
1411 src3, ""),
1412 ctx->i32_1, ""),
1413 src2, "");
1414 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1415 bfi_args[2] = src0;
1416
1417 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1418
1419 /* Calculate:
1420 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1421 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1422 */
1423 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1424 LLVMBuildAnd(ctx->builder, bfi_args[0],
1425 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1426
1427 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1428 return result;
1429 }
1430
1431 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1432 LLVMValueRef src0)
1433 {
1434 LLVMValueRef comp[2];
1435
1436 src0 = ac_to_float(ctx, src0);
1437 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1438 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1439
1440 return ac_build_cvt_pkrtz_f16(ctx, comp);
1441 }
1442
1443 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1444 LLVMValueRef src0)
1445 {
1446 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1447 LLVMValueRef temps[2], result, val;
1448 int i;
1449
1450 for (i = 0; i < 2; i++) {
1451 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1452 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1453 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1454 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1455 }
1456
1457 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1458 ctx->i32_0, "");
1459 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1460 ctx->i32_1, "");
1461 return result;
1462 }
1463
1464 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1465 nir_op op,
1466 LLVMValueRef src0)
1467 {
1468 unsigned mask;
1469 int idx;
1470 LLVMValueRef result;
1471
1472 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1473 mask = AC_TID_MASK_LEFT;
1474 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1475 mask = AC_TID_MASK_TOP;
1476 else
1477 mask = AC_TID_MASK_TOP_LEFT;
1478
1479 /* for DDX we want to next X pixel, DDY next Y pixel. */
1480 if (op == nir_op_fddx_fine ||
1481 op == nir_op_fddx_coarse ||
1482 op == nir_op_fddx)
1483 idx = 1;
1484 else
1485 idx = 2;
1486
1487 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1488 return result;
1489 }
1490
1491 /*
1492 * this takes an I,J coordinate pair,
1493 * and works out the X and Y derivatives.
1494 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1495 */
1496 static LLVMValueRef emit_ddxy_interp(
1497 struct ac_nir_context *ctx,
1498 LLVMValueRef interp_ij)
1499 {
1500 LLVMValueRef result[4], a;
1501 unsigned i;
1502
1503 for (i = 0; i < 2; i++) {
1504 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1505 LLVMConstInt(ctx->ac.i32, i, false), "");
1506 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1507 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1508 }
1509 return ac_build_gather_values(&ctx->ac, result, 4);
1510 }
1511
1512 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1513 {
1514 LLVMValueRef src[4], result = NULL;
1515 unsigned num_components = instr->dest.dest.ssa.num_components;
1516 unsigned src_components;
1517 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1518
1519 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1520 switch (instr->op) {
1521 case nir_op_vec2:
1522 case nir_op_vec3:
1523 case nir_op_vec4:
1524 src_components = 1;
1525 break;
1526 case nir_op_pack_half_2x16:
1527 src_components = 2;
1528 break;
1529 case nir_op_unpack_half_2x16:
1530 src_components = 1;
1531 break;
1532 default:
1533 src_components = num_components;
1534 break;
1535 }
1536 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1537 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1538
1539 switch (instr->op) {
1540 case nir_op_fmov:
1541 case nir_op_imov:
1542 result = src[0];
1543 break;
1544 case nir_op_fneg:
1545 src[0] = ac_to_float(&ctx->ac, src[0]);
1546 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1547 break;
1548 case nir_op_ineg:
1549 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1550 break;
1551 case nir_op_inot:
1552 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1553 break;
1554 case nir_op_iadd:
1555 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1556 break;
1557 case nir_op_fadd:
1558 src[0] = ac_to_float(&ctx->ac, src[0]);
1559 src[1] = ac_to_float(&ctx->ac, src[1]);
1560 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1561 break;
1562 case nir_op_fsub:
1563 src[0] = ac_to_float(&ctx->ac, src[0]);
1564 src[1] = ac_to_float(&ctx->ac, src[1]);
1565 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1566 break;
1567 case nir_op_isub:
1568 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1569 break;
1570 case nir_op_imul:
1571 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1572 break;
1573 case nir_op_imod:
1574 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1575 break;
1576 case nir_op_umod:
1577 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1578 break;
1579 case nir_op_fmod:
1580 src[0] = ac_to_float(&ctx->ac, src[0]);
1581 src[1] = ac_to_float(&ctx->ac, src[1]);
1582 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1583 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1584 ac_to_float_type(&ctx->ac, def_type), result);
1585 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1586 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1587 break;
1588 case nir_op_frem:
1589 src[0] = ac_to_float(&ctx->ac, src[0]);
1590 src[1] = ac_to_float(&ctx->ac, src[1]);
1591 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1592 break;
1593 case nir_op_irem:
1594 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1595 break;
1596 case nir_op_idiv:
1597 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1598 break;
1599 case nir_op_udiv:
1600 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1601 break;
1602 case nir_op_fmul:
1603 src[0] = ac_to_float(&ctx->ac, src[0]);
1604 src[1] = ac_to_float(&ctx->ac, src[1]);
1605 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1606 break;
1607 case nir_op_fdiv:
1608 src[0] = ac_to_float(&ctx->ac, src[0]);
1609 src[1] = ac_to_float(&ctx->ac, src[1]);
1610 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1611 break;
1612 case nir_op_frcp:
1613 src[0] = ac_to_float(&ctx->ac, src[0]);
1614 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1615 break;
1616 case nir_op_iand:
1617 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1618 break;
1619 case nir_op_ior:
1620 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1621 break;
1622 case nir_op_ixor:
1623 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1624 break;
1625 case nir_op_ishl:
1626 result = LLVMBuildShl(ctx->ac.builder, src[0],
1627 LLVMBuildZExt(ctx->ac.builder, src[1],
1628 LLVMTypeOf(src[0]), ""),
1629 "");
1630 break;
1631 case nir_op_ishr:
1632 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1633 LLVMBuildZExt(ctx->ac.builder, src[1],
1634 LLVMTypeOf(src[0]), ""),
1635 "");
1636 break;
1637 case nir_op_ushr:
1638 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1639 LLVMBuildZExt(ctx->ac.builder, src[1],
1640 LLVMTypeOf(src[0]), ""),
1641 "");
1642 break;
1643 case nir_op_ilt:
1644 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1645 break;
1646 case nir_op_ine:
1647 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1648 break;
1649 case nir_op_ieq:
1650 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1651 break;
1652 case nir_op_ige:
1653 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1654 break;
1655 case nir_op_ult:
1656 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1657 break;
1658 case nir_op_uge:
1659 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1660 break;
1661 case nir_op_feq:
1662 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1663 break;
1664 case nir_op_fne:
1665 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1666 break;
1667 case nir_op_flt:
1668 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1669 break;
1670 case nir_op_fge:
1671 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1672 break;
1673 case nir_op_fabs:
1674 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1675 ac_to_float_type(&ctx->ac, def_type), src[0]);
1676 break;
1677 case nir_op_iabs:
1678 result = emit_iabs(&ctx->ac, src[0]);
1679 break;
1680 case nir_op_imax:
1681 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1682 break;
1683 case nir_op_imin:
1684 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1685 break;
1686 case nir_op_umax:
1687 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1688 break;
1689 case nir_op_umin:
1690 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1691 break;
1692 case nir_op_isign:
1693 result = emit_isign(&ctx->ac, src[0]);
1694 break;
1695 case nir_op_fsign:
1696 src[0] = ac_to_float(&ctx->ac, src[0]);
1697 result = emit_fsign(&ctx->ac, src[0]);
1698 break;
1699 case nir_op_ffloor:
1700 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1701 ac_to_float_type(&ctx->ac, def_type), src[0]);
1702 break;
1703 case nir_op_ftrunc:
1704 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1705 ac_to_float_type(&ctx->ac, def_type), src[0]);
1706 break;
1707 case nir_op_fceil:
1708 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1709 ac_to_float_type(&ctx->ac, def_type), src[0]);
1710 break;
1711 case nir_op_fround_even:
1712 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1713 ac_to_float_type(&ctx->ac, def_type),src[0]);
1714 break;
1715 case nir_op_ffract:
1716 result = emit_ffract(&ctx->ac, src[0]);
1717 break;
1718 case nir_op_fsin:
1719 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1720 ac_to_float_type(&ctx->ac, def_type), src[0]);
1721 break;
1722 case nir_op_fcos:
1723 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1724 ac_to_float_type(&ctx->ac, def_type), src[0]);
1725 break;
1726 case nir_op_fsqrt:
1727 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1728 ac_to_float_type(&ctx->ac, def_type), src[0]);
1729 break;
1730 case nir_op_fexp2:
1731 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1732 ac_to_float_type(&ctx->ac, def_type), src[0]);
1733 break;
1734 case nir_op_flog2:
1735 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1736 ac_to_float_type(&ctx->ac, def_type), src[0]);
1737 break;
1738 case nir_op_frsq:
1739 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1740 ac_to_float_type(&ctx->ac, def_type), src[0]);
1741 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1742 break;
1743 case nir_op_fpow:
1744 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1745 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1746 break;
1747 case nir_op_fmax:
1748 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1749 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1750 if (instr->dest.dest.ssa.bit_size == 32)
1751 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1752 ac_to_float_type(&ctx->ac, def_type),
1753 result);
1754 break;
1755 case nir_op_fmin:
1756 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1757 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1758 if (instr->dest.dest.ssa.bit_size == 32)
1759 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1760 ac_to_float_type(&ctx->ac, def_type),
1761 result);
1762 break;
1763 case nir_op_ffma:
1764 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1765 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1766 break;
1767 case nir_op_ibitfield_extract:
1768 result = emit_bitfield_extract(&ctx->ac, true, src);
1769 break;
1770 case nir_op_ubitfield_extract:
1771 result = emit_bitfield_extract(&ctx->ac, false, src);
1772 break;
1773 case nir_op_bitfield_insert:
1774 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1775 break;
1776 case nir_op_bitfield_reverse:
1777 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1778 break;
1779 case nir_op_bit_count:
1780 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1781 break;
1782 case nir_op_vec2:
1783 case nir_op_vec3:
1784 case nir_op_vec4:
1785 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1786 src[i] = ac_to_integer(&ctx->ac, src[i]);
1787 result = ac_build_gather_values(&ctx->ac, src, num_components);
1788 break;
1789 case nir_op_f2i32:
1790 case nir_op_f2i64:
1791 src[0] = ac_to_float(&ctx->ac, src[0]);
1792 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1793 break;
1794 case nir_op_f2u32:
1795 case nir_op_f2u64:
1796 src[0] = ac_to_float(&ctx->ac, src[0]);
1797 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1798 break;
1799 case nir_op_i2f32:
1800 case nir_op_i2f64:
1801 src[0] = ac_to_integer(&ctx->ac, src[0]);
1802 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1803 break;
1804 case nir_op_u2f32:
1805 case nir_op_u2f64:
1806 src[0] = ac_to_integer(&ctx->ac, src[0]);
1807 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1808 break;
1809 case nir_op_f2f64:
1810 src[0] = ac_to_float(&ctx->ac, src[0]);
1811 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1812 break;
1813 case nir_op_f2f32:
1814 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1815 break;
1816 case nir_op_u2u32:
1817 case nir_op_u2u64:
1818 src[0] = ac_to_integer(&ctx->ac, src[0]);
1819 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1820 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1821 else
1822 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1823 break;
1824 case nir_op_i2i32:
1825 case nir_op_i2i64:
1826 src[0] = ac_to_integer(&ctx->ac, src[0]);
1827 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1828 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1829 else
1830 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1831 break;
1832 case nir_op_bcsel:
1833 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1834 break;
1835 case nir_op_find_lsb:
1836 src[0] = ac_to_integer(&ctx->ac, src[0]);
1837 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1838 break;
1839 case nir_op_ufind_msb:
1840 src[0] = ac_to_integer(&ctx->ac, src[0]);
1841 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1842 break;
1843 case nir_op_ifind_msb:
1844 src[0] = ac_to_integer(&ctx->ac, src[0]);
1845 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1846 break;
1847 case nir_op_uadd_carry:
1848 src[0] = ac_to_integer(&ctx->ac, src[0]);
1849 src[1] = ac_to_integer(&ctx->ac, src[1]);
1850 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1851 break;
1852 case nir_op_usub_borrow:
1853 src[0] = ac_to_integer(&ctx->ac, src[0]);
1854 src[1] = ac_to_integer(&ctx->ac, src[1]);
1855 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1856 break;
1857 case nir_op_b2f:
1858 result = emit_b2f(&ctx->ac, src[0]);
1859 break;
1860 case nir_op_f2b:
1861 result = emit_f2b(&ctx->ac, src[0]);
1862 break;
1863 case nir_op_b2i:
1864 result = emit_b2i(&ctx->ac, src[0]);
1865 break;
1866 case nir_op_i2b:
1867 src[0] = ac_to_integer(&ctx->ac, src[0]);
1868 result = emit_i2b(&ctx->ac, src[0]);
1869 break;
1870 case nir_op_fquantize2f16:
1871 result = emit_f2f16(ctx->nctx, src[0]);
1872 break;
1873 case nir_op_umul_high:
1874 src[0] = ac_to_integer(&ctx->ac, src[0]);
1875 src[1] = ac_to_integer(&ctx->ac, src[1]);
1876 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1877 break;
1878 case nir_op_imul_high:
1879 src[0] = ac_to_integer(&ctx->ac, src[0]);
1880 src[1] = ac_to_integer(&ctx->ac, src[1]);
1881 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1882 break;
1883 case nir_op_pack_half_2x16:
1884 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1885 break;
1886 case nir_op_unpack_half_2x16:
1887 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1888 break;
1889 case nir_op_fddx:
1890 case nir_op_fddy:
1891 case nir_op_fddx_fine:
1892 case nir_op_fddy_fine:
1893 case nir_op_fddx_coarse:
1894 case nir_op_fddy_coarse:
1895 result = emit_ddxy(ctx, instr->op, src[0]);
1896 break;
1897
1898 case nir_op_unpack_64_2x32_split_x: {
1899 assert(instr->src[0].src.ssa->num_components == 1);
1900 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1901 ctx->ac.v2i32,
1902 "");
1903 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1904 ctx->ac.i32_0, "");
1905 break;
1906 }
1907
1908 case nir_op_unpack_64_2x32_split_y: {
1909 assert(instr->src[0].src.ssa->num_components == 1);
1910 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1911 ctx->ac.v2i32,
1912 "");
1913 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1914 ctx->ac.i32_1, "");
1915 break;
1916 }
1917
1918 case nir_op_pack_64_2x32_split: {
1919 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1920 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1921 src[0], ctx->ac.i32_0, "");
1922 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1923 src[1], ctx->ac.i32_1, "");
1924 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1925 break;
1926 }
1927
1928 default:
1929 fprintf(stderr, "Unknown NIR alu instr: ");
1930 nir_print_instr(&instr->instr, stderr);
1931 fprintf(stderr, "\n");
1932 abort();
1933 }
1934
1935 if (result) {
1936 assert(instr->dest.dest.is_ssa);
1937 result = ac_to_integer(&ctx->ac, result);
1938 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1939 result);
1940 }
1941 }
1942
1943 static void visit_load_const(struct ac_nir_context *ctx,
1944 const nir_load_const_instr *instr)
1945 {
1946 LLVMValueRef values[4], value = NULL;
1947 LLVMTypeRef element_type =
1948 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1949
1950 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1951 switch (instr->def.bit_size) {
1952 case 32:
1953 values[i] = LLVMConstInt(element_type,
1954 instr->value.u32[i], false);
1955 break;
1956 case 64:
1957 values[i] = LLVMConstInt(element_type,
1958 instr->value.u64[i], false);
1959 break;
1960 default:
1961 fprintf(stderr,
1962 "unsupported nir load_const bit_size: %d\n",
1963 instr->def.bit_size);
1964 abort();
1965 }
1966 }
1967 if (instr->def.num_components > 1) {
1968 value = LLVMConstVector(values, instr->def.num_components);
1969 } else
1970 value = values[0];
1971
1972 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1973 }
1974
1975 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1976 LLVMTypeRef type)
1977 {
1978 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1979 return LLVMBuildBitCast(ctx->builder, ptr,
1980 LLVMPointerType(type, addr_space), "");
1981 }
1982
1983 static LLVMValueRef
1984 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1985 {
1986 LLVMValueRef size =
1987 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1988 LLVMConstInt(ctx->ac.i32, 2, false), "");
1989
1990 /* VI only */
1991 if (ctx->ac.chip_class == VI && in_elements) {
1992 /* On VI, the descriptor contains the size in bytes,
1993 * but TXQ must return the size in elements.
1994 * The stride is always non-zero for resources using TXQ.
1995 */
1996 LLVMValueRef stride =
1997 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1998 LLVMConstInt(ctx->ac.i32, 1, false), "");
1999 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2000 LLVMConstInt(ctx->ac.i32, 16, false), "");
2001 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2002 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2003
2004 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2005 }
2006 return size;
2007 }
2008
2009 /**
2010 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2011 * intrinsic names).
2012 */
2013 static void build_int_type_name(
2014 LLVMTypeRef type,
2015 char *buf, unsigned bufsize)
2016 {
2017 assert(bufsize >= 6);
2018
2019 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2020 snprintf(buf, bufsize, "v%ui32",
2021 LLVMGetVectorSize(type));
2022 else
2023 strcpy(buf, "i32");
2024 }
2025
2026 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2027 struct ac_image_args *args,
2028 const nir_tex_instr *instr)
2029 {
2030 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2031 LLVMValueRef coord = args->addr;
2032 LLVMValueRef half_texel[2];
2033 LLVMValueRef compare_cube_wa = NULL;
2034 LLVMValueRef result;
2035 int c;
2036 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2037
2038 //TODO Rect
2039 {
2040 struct ac_image_args txq_args = { 0 };
2041
2042 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2043 txq_args.opcode = ac_image_get_resinfo;
2044 txq_args.dmask = 0xf;
2045 txq_args.addr = ctx->i32_0;
2046 txq_args.resource = args->resource;
2047 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2048
2049 for (c = 0; c < 2; c++) {
2050 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2051 LLVMConstInt(ctx->i32, c, false), "");
2052 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2053 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2054 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2055 LLVMConstReal(ctx->f32, -0.5), "");
2056 }
2057 }
2058
2059 LLVMValueRef orig_coords = args->addr;
2060
2061 for (c = 0; c < 2; c++) {
2062 LLVMValueRef tmp;
2063 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2064 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2065 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2066 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2067 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2068 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2069 }
2070
2071
2072 /*
2073 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2074 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2075 * workaround by sampling using a scaled type and converting.
2076 * This is taken from amdgpu-pro shaders.
2077 */
2078 /* NOTE this produces some ugly code compared to amdgpu-pro,
2079 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2080 * and then reads them back. -pro generates two selects,
2081 * one s_cmp for the descriptor rewriting
2082 * one v_cmp for the coordinate and result changes.
2083 */
2084 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2085 LLVMValueRef tmp, tmp2;
2086
2087 /* workaround 8/8/8/8 uint/sint cube gather bug */
2088 /* first detect it then change to a scaled read and f2i */
2089 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2090 tmp2 = tmp;
2091
2092 /* extract the DATA_FORMAT */
2093 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2094 LLVMConstInt(ctx->i32, 6, false), false);
2095
2096 /* is the DATA_FORMAT == 8_8_8_8 */
2097 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2098
2099 if (stype == GLSL_TYPE_UINT)
2100 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2101 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2102 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2103 else
2104 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2105 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2106 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2107
2108 /* replace the NUM FORMAT in the descriptor */
2109 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2110 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2111
2112 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2113
2114 /* don't modify the coordinates for this case */
2115 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2116 }
2117 args->addr = coord;
2118 result = ac_build_image_opcode(ctx, args);
2119
2120 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2121 LLVMValueRef tmp, tmp2;
2122
2123 /* if the cube workaround is in place, f2i the result. */
2124 for (c = 0; c < 4; c++) {
2125 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2126 if (stype == GLSL_TYPE_UINT)
2127 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2128 else
2129 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2130 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2131 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2132 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2133 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2134 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2135 }
2136 }
2137 return result;
2138 }
2139
2140 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2141 const nir_tex_instr *instr,
2142 bool lod_is_zero,
2143 struct ac_image_args *args)
2144 {
2145 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2146 return ac_build_buffer_load_format(&ctx->ac,
2147 args->resource,
2148 args->addr,
2149 LLVMConstInt(ctx->ac.i32, 0, false),
2150 true);
2151 }
2152
2153 args->opcode = ac_image_sample;
2154 args->compare = instr->is_shadow;
2155
2156 switch (instr->op) {
2157 case nir_texop_txf:
2158 case nir_texop_txf_ms:
2159 case nir_texop_samples_identical:
2160 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2161 args->compare = false;
2162 args->offset = false;
2163 break;
2164 case nir_texop_txb:
2165 args->bias = true;
2166 break;
2167 case nir_texop_txl:
2168 if (lod_is_zero)
2169 args->level_zero = true;
2170 else
2171 args->lod = true;
2172 break;
2173 case nir_texop_txs:
2174 case nir_texop_query_levels:
2175 args->opcode = ac_image_get_resinfo;
2176 break;
2177 case nir_texop_tex:
2178 if (ctx->stage != MESA_SHADER_FRAGMENT)
2179 args->level_zero = true;
2180 break;
2181 case nir_texop_txd:
2182 args->deriv = true;
2183 break;
2184 case nir_texop_tg4:
2185 args->opcode = ac_image_gather4;
2186 args->level_zero = true;
2187 break;
2188 case nir_texop_lod:
2189 args->opcode = ac_image_get_lod;
2190 args->compare = false;
2191 args->offset = false;
2192 break;
2193 default:
2194 break;
2195 }
2196
2197 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2198 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2199 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2200 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2201 }
2202 }
2203 return ac_build_image_opcode(&ctx->ac, args);
2204 }
2205
2206 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2207 nir_intrinsic_instr *instr)
2208 {
2209 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2210 unsigned desc_set = nir_intrinsic_desc_set(instr);
2211 unsigned binding = nir_intrinsic_binding(instr);
2212 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2213 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2214 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2215 unsigned base_offset = layout->binding[binding].offset;
2216 LLVMValueRef offset, stride;
2217
2218 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2219 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2220 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2221 layout->binding[binding].dynamic_offset_offset;
2222 desc_ptr = ctx->push_constants;
2223 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2224 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2225 } else
2226 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2227
2228 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2229 index = LLVMBuildMul(ctx->builder, index, stride, "");
2230 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2231
2232 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2233 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2234 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2235
2236 return desc_ptr;
2237 }
2238
2239 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2240 nir_intrinsic_instr *instr)
2241 {
2242 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2243 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2244
2245 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2246 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2247 return result;
2248 }
2249
2250 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2251 nir_intrinsic_instr *instr)
2252 {
2253 LLVMValueRef ptr, addr;
2254
2255 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2256 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2257
2258 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2259 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2260
2261 return LLVMBuildLoad(ctx->builder, ptr, "");
2262 }
2263
2264 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2265 const nir_intrinsic_instr *instr)
2266 {
2267 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2268
2269 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2270 }
2271 static void visit_store_ssbo(struct ac_nir_context *ctx,
2272 nir_intrinsic_instr *instr)
2273 {
2274 const char *store_name;
2275 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2276 LLVMTypeRef data_type = ctx->ac.f32;
2277 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2278 int components_32bit = elem_size_mult * instr->num_components;
2279 unsigned writemask = nir_intrinsic_write_mask(instr);
2280 LLVMValueRef base_data, base_offset;
2281 LLVMValueRef params[6];
2282
2283 params[1] = ctx->abi->load_ssbo(ctx->abi,
2284 get_src(ctx, instr->src[1]), true);
2285 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2286 params[4] = ctx->ac.i1false; /* glc */
2287 params[5] = ctx->ac.i1false; /* slc */
2288
2289 if (components_32bit > 1)
2290 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2291
2292 base_data = ac_to_float(&ctx->ac, src_data);
2293 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2294 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2295 data_type, "");
2296 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2297 while (writemask) {
2298 int start, count;
2299 LLVMValueRef data;
2300 LLVMValueRef offset;
2301 LLVMValueRef tmp;
2302 u_bit_scan_consecutive_range(&writemask, &start, &count);
2303
2304 /* Due to an LLVM limitation, split 3-element writes
2305 * into a 2-element and a 1-element write. */
2306 if (count == 3) {
2307 writemask |= 1 << (start + 2);
2308 count = 2;
2309 }
2310
2311 start *= elem_size_mult;
2312 count *= elem_size_mult;
2313
2314 if (count > 4) {
2315 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2316 count = 4;
2317 }
2318
2319 if (count == 4) {
2320 store_name = "llvm.amdgcn.buffer.store.v4f32";
2321 data = base_data;
2322 } else if (count == 2) {
2323 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2324 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2325 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2326 ctx->ac.i32_0, "");
2327
2328 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2329 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2330 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2331 ctx->ac.i32_1, "");
2332 store_name = "llvm.amdgcn.buffer.store.v2f32";
2333
2334 } else {
2335 assert(count == 1);
2336 if (get_llvm_num_components(base_data) > 1)
2337 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2338 LLVMConstInt(ctx->ac.i32, start, false), "");
2339 else
2340 data = base_data;
2341 store_name = "llvm.amdgcn.buffer.store.f32";
2342 }
2343
2344 offset = base_offset;
2345 if (start != 0) {
2346 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2347 }
2348 params[0] = data;
2349 params[3] = offset;
2350 ac_build_intrinsic(&ctx->ac, store_name,
2351 ctx->ac.voidt, params, 6, 0);
2352 }
2353 }
2354
2355 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2356 const nir_intrinsic_instr *instr)
2357 {
2358 const char *name;
2359 LLVMValueRef params[6];
2360 int arg_count = 0;
2361
2362 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2363 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2364 }
2365 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2366 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2367 get_src(ctx, instr->src[0]),
2368 true);
2369 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2370 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2371 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2372
2373 switch (instr->intrinsic) {
2374 case nir_intrinsic_ssbo_atomic_add:
2375 name = "llvm.amdgcn.buffer.atomic.add";
2376 break;
2377 case nir_intrinsic_ssbo_atomic_imin:
2378 name = "llvm.amdgcn.buffer.atomic.smin";
2379 break;
2380 case nir_intrinsic_ssbo_atomic_umin:
2381 name = "llvm.amdgcn.buffer.atomic.umin";
2382 break;
2383 case nir_intrinsic_ssbo_atomic_imax:
2384 name = "llvm.amdgcn.buffer.atomic.smax";
2385 break;
2386 case nir_intrinsic_ssbo_atomic_umax:
2387 name = "llvm.amdgcn.buffer.atomic.umax";
2388 break;
2389 case nir_intrinsic_ssbo_atomic_and:
2390 name = "llvm.amdgcn.buffer.atomic.and";
2391 break;
2392 case nir_intrinsic_ssbo_atomic_or:
2393 name = "llvm.amdgcn.buffer.atomic.or";
2394 break;
2395 case nir_intrinsic_ssbo_atomic_xor:
2396 name = "llvm.amdgcn.buffer.atomic.xor";
2397 break;
2398 case nir_intrinsic_ssbo_atomic_exchange:
2399 name = "llvm.amdgcn.buffer.atomic.swap";
2400 break;
2401 case nir_intrinsic_ssbo_atomic_comp_swap:
2402 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2403 break;
2404 default:
2405 abort();
2406 }
2407
2408 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2409 }
2410
2411 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2412 const nir_intrinsic_instr *instr)
2413 {
2414 LLVMValueRef results[2];
2415 int load_components;
2416 int num_components = instr->num_components;
2417 if (instr->dest.ssa.bit_size == 64)
2418 num_components *= 2;
2419
2420 for (int i = 0; i < num_components; i += load_components) {
2421 load_components = MIN2(num_components - i, 4);
2422 const char *load_name;
2423 LLVMTypeRef data_type = ctx->ac.f32;
2424 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2425 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2426
2427 if (load_components == 3)
2428 data_type = LLVMVectorType(ctx->ac.f32, 4);
2429 else if (load_components > 1)
2430 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2431
2432 if (load_components >= 3)
2433 load_name = "llvm.amdgcn.buffer.load.v4f32";
2434 else if (load_components == 2)
2435 load_name = "llvm.amdgcn.buffer.load.v2f32";
2436 else if (load_components == 1)
2437 load_name = "llvm.amdgcn.buffer.load.f32";
2438 else
2439 unreachable("unhandled number of components");
2440
2441 LLVMValueRef params[] = {
2442 ctx->abi->load_ssbo(ctx->abi,
2443 get_src(ctx, instr->src[0]),
2444 false),
2445 LLVMConstInt(ctx->ac.i32, 0, false),
2446 offset,
2447 ctx->ac.i1false,
2448 ctx->ac.i1false,
2449 };
2450
2451 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2452
2453 }
2454
2455 assume(results[0]);
2456 LLVMValueRef ret = results[0];
2457 if (num_components > 4 || num_components == 3) {
2458 LLVMValueRef masks[] = {
2459 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2460 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2461 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2462 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2463 };
2464
2465 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2466 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2467 results[num_components > 4 ? 1 : 0], swizzle, "");
2468 }
2469
2470 return LLVMBuildBitCast(ctx->ac.builder, ret,
2471 get_def_type(ctx, &instr->dest.ssa), "");
2472 }
2473
2474 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2475 const nir_intrinsic_instr *instr)
2476 {
2477 LLVMValueRef results[8], ret;
2478 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2479 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2480 int num_components = instr->num_components;
2481
2482 if (ctx->abi->load_ubo)
2483 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2484
2485 if (instr->dest.ssa.bit_size == 64)
2486 num_components *= 2;
2487
2488 for (unsigned i = 0; i < num_components; ++i) {
2489 LLVMValueRef params[] = {
2490 rsrc,
2491 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2492 offset, "")
2493 };
2494 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2495 params, 2,
2496 AC_FUNC_ATTR_READNONE |
2497 AC_FUNC_ATTR_LEGACY);
2498 }
2499
2500
2501 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2502 return LLVMBuildBitCast(ctx->ac.builder, ret,
2503 get_def_type(ctx, &instr->dest.ssa), "");
2504 }
2505
2506 static void
2507 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2508 bool vs_in, unsigned *vertex_index_out,
2509 LLVMValueRef *vertex_index_ref,
2510 unsigned *const_out, LLVMValueRef *indir_out)
2511 {
2512 unsigned const_offset = 0;
2513 nir_deref *tail = &deref->deref;
2514 LLVMValueRef offset = NULL;
2515
2516 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2517 tail = tail->child;
2518 nir_deref_array *deref_array = nir_deref_as_array(tail);
2519 if (vertex_index_out)
2520 *vertex_index_out = deref_array->base_offset;
2521
2522 if (vertex_index_ref) {
2523 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2524 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2525 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2526 }
2527 *vertex_index_ref = vtx;
2528 }
2529 }
2530
2531 if (deref->var->data.compact) {
2532 assert(tail->child->deref_type == nir_deref_type_array);
2533 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2534 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2535 /* We always lower indirect dereferences for "compact" array vars. */
2536 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2537
2538 const_offset = deref_array->base_offset;
2539 goto out;
2540 }
2541
2542 while (tail->child != NULL) {
2543 const struct glsl_type *parent_type = tail->type;
2544 tail = tail->child;
2545
2546 if (tail->deref_type == nir_deref_type_array) {
2547 nir_deref_array *deref_array = nir_deref_as_array(tail);
2548 LLVMValueRef index, stride, local_offset;
2549 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2550
2551 const_offset += size * deref_array->base_offset;
2552 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2553 continue;
2554
2555 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2556 index = get_src(ctx, deref_array->indirect);
2557 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2558 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2559
2560 if (offset)
2561 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2562 else
2563 offset = local_offset;
2564 } else if (tail->deref_type == nir_deref_type_struct) {
2565 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2566
2567 for (unsigned i = 0; i < deref_struct->index; i++) {
2568 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2569 const_offset += glsl_count_attribute_slots(ft, vs_in);
2570 }
2571 } else
2572 unreachable("unsupported deref type");
2573
2574 }
2575 out:
2576 if (const_offset && offset)
2577 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2578 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2579 "");
2580
2581 *const_out = const_offset;
2582 *indir_out = offset;
2583 }
2584
2585
2586 /* The offchip buffer layout for TCS->TES is
2587 *
2588 * - attribute 0 of patch 0 vertex 0
2589 * - attribute 0 of patch 0 vertex 1
2590 * - attribute 0 of patch 0 vertex 2
2591 * ...
2592 * - attribute 0 of patch 1 vertex 0
2593 * - attribute 0 of patch 1 vertex 1
2594 * ...
2595 * - attribute 1 of patch 0 vertex 0
2596 * - attribute 1 of patch 0 vertex 1
2597 * ...
2598 * - per patch attribute 0 of patch 0
2599 * - per patch attribute 0 of patch 1
2600 * ...
2601 *
2602 * Note that every attribute has 4 components.
2603 */
2604 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2605 LLVMValueRef vertex_index,
2606 LLVMValueRef param_index)
2607 {
2608 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2609 LLVMValueRef param_stride, constant16;
2610 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2611
2612 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2613 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2614 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2615 num_patches, "");
2616
2617 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2618 if (vertex_index) {
2619 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2620 vertices_per_patch, "");
2621
2622 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2623 vertex_index, "");
2624
2625 param_stride = total_vertices;
2626 } else {
2627 base_addr = rel_patch_id;
2628 param_stride = num_patches;
2629 }
2630
2631 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2632 LLVMBuildMul(ctx->builder, param_index,
2633 param_stride, ""), "");
2634
2635 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2636
2637 if (!vertex_index) {
2638 LLVMValueRef patch_data_offset =
2639 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2640
2641 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2642 patch_data_offset, "");
2643 }
2644 return base_addr;
2645 }
2646
2647 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2648 unsigned param,
2649 unsigned const_index,
2650 bool is_compact,
2651 LLVMValueRef vertex_index,
2652 LLVMValueRef indir_index)
2653 {
2654 LLVMValueRef param_index;
2655
2656 if (indir_index)
2657 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2658 indir_index, "");
2659 else {
2660 if (const_index && !is_compact)
2661 param += const_index;
2662 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2663 }
2664 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2665 }
2666
2667 static void
2668 mark_tess_output(struct nir_to_llvm_context *ctx,
2669 bool is_patch, uint32_t param)
2670
2671 {
2672 if (is_patch) {
2673 ctx->tess_patch_outputs_written |= (1ull << param);
2674 } else
2675 ctx->tess_outputs_written |= (1ull << param);
2676 }
2677
2678 static LLVMValueRef
2679 get_dw_address(struct nir_to_llvm_context *ctx,
2680 LLVMValueRef dw_addr,
2681 unsigned param,
2682 unsigned const_index,
2683 bool compact_const_index,
2684 LLVMValueRef vertex_index,
2685 LLVMValueRef stride,
2686 LLVMValueRef indir_index)
2687
2688 {
2689
2690 if (vertex_index) {
2691 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2692 LLVMBuildMul(ctx->builder,
2693 vertex_index,
2694 stride, ""), "");
2695 }
2696
2697 if (indir_index)
2698 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2699 LLVMBuildMul(ctx->builder, indir_index,
2700 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2701 else if (const_index && !compact_const_index)
2702 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2703 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2704
2705 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2706 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2707
2708 if (const_index && compact_const_index)
2709 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2710 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2711 return dw_addr;
2712 }
2713
2714 static LLVMValueRef
2715 load_tcs_input(struct nir_to_llvm_context *ctx,
2716 nir_intrinsic_instr *instr)
2717 {
2718 LLVMValueRef dw_addr, stride;
2719 unsigned const_index;
2720 LLVMValueRef vertex_index;
2721 LLVMValueRef indir_index;
2722 unsigned param;
2723 LLVMValueRef value[4], result;
2724 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2725 const bool is_compact = instr->variables[0]->var->data.compact;
2726 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2727 get_deref_offset(ctx->nir, instr->variables[0],
2728 false, NULL, per_vertex ? &vertex_index : NULL,
2729 &const_index, &indir_index);
2730
2731 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2732 dw_addr = get_tcs_in_current_patch_offset(ctx);
2733 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2734 indir_index);
2735
2736 unsigned comp = instr->variables[0]->var->data.location_frac;
2737 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2738 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2739 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2740 ctx->ac.i32_1, "");
2741 }
2742 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2743 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2744 return result;
2745 }
2746
2747 static LLVMValueRef
2748 load_tcs_output(struct nir_to_llvm_context *ctx,
2749 nir_intrinsic_instr *instr)
2750 {
2751 LLVMValueRef dw_addr;
2752 LLVMValueRef stride = NULL;
2753 LLVMValueRef value[4], result;
2754 LLVMValueRef vertex_index = NULL;
2755 LLVMValueRef indir_index = NULL;
2756 unsigned const_index = 0;
2757 unsigned param;
2758 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2759 const bool is_compact = instr->variables[0]->var->data.compact;
2760 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2761 get_deref_offset(ctx->nir, instr->variables[0],
2762 false, NULL, per_vertex ? &vertex_index : NULL,
2763 &const_index, &indir_index);
2764
2765 if (!instr->variables[0]->var->data.patch) {
2766 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2767 dw_addr = get_tcs_out_current_patch_offset(ctx);
2768 } else {
2769 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2770 }
2771
2772 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2773 indir_index);
2774
2775 unsigned comp = instr->variables[0]->var->data.location_frac;
2776 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2777 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2778 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2779 ctx->ac.i32_1, "");
2780 }
2781 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2782 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2783 return result;
2784 }
2785
2786 static void
2787 store_tcs_output(struct nir_to_llvm_context *ctx,
2788 nir_intrinsic_instr *instr,
2789 LLVMValueRef src,
2790 unsigned writemask)
2791 {
2792 LLVMValueRef dw_addr;
2793 LLVMValueRef stride = NULL;
2794 LLVMValueRef buf_addr = NULL;
2795 LLVMValueRef vertex_index = NULL;
2796 LLVMValueRef indir_index = NULL;
2797 unsigned const_index = 0;
2798 unsigned param;
2799 const unsigned comp = instr->variables[0]->var->data.location_frac;
2800 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2801 const bool is_compact = instr->variables[0]->var->data.compact;
2802 bool store_lds = true;
2803
2804 if (instr->variables[0]->var->data.patch) {
2805 if (!(ctx->tcs_patch_outputs_read & (1U << instr->variables[0]->var->data.location)))
2806 store_lds = false;
2807 } else {
2808 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2809 store_lds = false;
2810 }
2811 get_deref_offset(ctx->nir, instr->variables[0],
2812 false, NULL, per_vertex ? &vertex_index : NULL,
2813 &const_index, &indir_index);
2814
2815 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2816 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2817 is_compact && const_index > 3) {
2818 const_index -= 3;
2819 param++;
2820 }
2821
2822 if (!instr->variables[0]->var->data.patch) {
2823 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2824 dw_addr = get_tcs_out_current_patch_offset(ctx);
2825 } else {
2826 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2827 }
2828
2829 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2830
2831 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2832 indir_index);
2833 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2834 vertex_index, indir_index);
2835
2836 bool is_tess_factor = false;
2837 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2838 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2839 is_tess_factor = true;
2840
2841 unsigned base = is_compact ? const_index : 0;
2842 for (unsigned chan = 0; chan < 8; chan++) {
2843 if (!(writemask & (1 << chan)))
2844 continue;
2845 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2846
2847 if (store_lds || is_tess_factor)
2848 ac_lds_store(&ctx->ac, dw_addr, value);
2849
2850 if (!is_tess_factor && writemask != 0xF)
2851 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2852 buf_addr, ctx->oc_lds,
2853 4 * (base + chan), 1, 0, true, false);
2854
2855 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2856 ctx->ac.i32_1, "");
2857 }
2858
2859 if (writemask == 0xF) {
2860 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2861 buf_addr, ctx->oc_lds,
2862 (base * 4), 1, 0, true, false);
2863 }
2864 }
2865
2866 static LLVMValueRef
2867 load_tes_input(struct nir_to_llvm_context *ctx,
2868 const nir_intrinsic_instr *instr)
2869 {
2870 LLVMValueRef buf_addr;
2871 LLVMValueRef result;
2872 LLVMValueRef vertex_index = NULL;
2873 LLVMValueRef indir_index = NULL;
2874 unsigned const_index = 0;
2875 unsigned param;
2876 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2877 const bool is_compact = instr->variables[0]->var->data.compact;
2878
2879 get_deref_offset(ctx->nir, instr->variables[0],
2880 false, NULL, per_vertex ? &vertex_index : NULL,
2881 &const_index, &indir_index);
2882 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2883 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2884 is_compact && const_index > 3) {
2885 const_index -= 3;
2886 param++;
2887 }
2888
2889 unsigned comp = instr->variables[0]->var->data.location_frac;
2890 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2891 is_compact, vertex_index, indir_index);
2892
2893 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2894 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2895
2896 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2897 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2898 result = trim_vector(&ctx->ac, result, instr->num_components);
2899 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2900 return result;
2901 }
2902
2903 static LLVMValueRef
2904 load_gs_input(struct ac_shader_abi *abi,
2905 unsigned location,
2906 unsigned driver_location,
2907 unsigned component,
2908 unsigned num_components,
2909 unsigned vertex_index,
2910 unsigned const_index,
2911 LLVMTypeRef type)
2912 {
2913 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2914 LLVMValueRef vtx_offset;
2915 LLVMValueRef args[9];
2916 unsigned param, vtx_offset_param;
2917 LLVMValueRef value[4], result;
2918
2919 vtx_offset_param = vertex_index;
2920 assert(vtx_offset_param < 6);
2921 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2922 LLVMConstInt(ctx->ac.i32, 4, false), "");
2923
2924 param = shader_io_get_unique_index(location);
2925
2926 for (unsigned i = component; i < num_components + component; i++) {
2927 if (ctx->ac.chip_class >= GFX9) {
2928 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2929 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2930 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2931 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2932 } else {
2933 args[0] = ctx->esgs_ring;
2934 args[1] = vtx_offset;
2935 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
2936 args[3] = ctx->ac.i32_0;
2937 args[4] = ctx->ac.i32_1; /* OFFEN */
2938 args[5] = ctx->ac.i32_0; /* IDXEN */
2939 args[6] = ctx->ac.i32_1; /* GLC */
2940 args[7] = ctx->ac.i32_0; /* SLC */
2941 args[8] = ctx->ac.i32_0; /* TFE */
2942
2943 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2944 ctx->ac.i32, args, 9,
2945 AC_FUNC_ATTR_READONLY |
2946 AC_FUNC_ATTR_LEGACY);
2947 }
2948 }
2949 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2950
2951 return result;
2952 }
2953
2954 static LLVMValueRef
2955 build_gep_for_deref(struct ac_nir_context *ctx,
2956 nir_deref_var *deref)
2957 {
2958 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2959 assert(entry->data);
2960 LLVMValueRef val = entry->data;
2961 nir_deref *tail = deref->deref.child;
2962 while (tail != NULL) {
2963 LLVMValueRef offset;
2964 switch (tail->deref_type) {
2965 case nir_deref_type_array: {
2966 nir_deref_array *array = nir_deref_as_array(tail);
2967 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2968 if (array->deref_array_type ==
2969 nir_deref_array_type_indirect) {
2970 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2971 get_src(ctx,
2972 array->indirect),
2973 "");
2974 }
2975 break;
2976 }
2977 case nir_deref_type_struct: {
2978 nir_deref_struct *deref_struct =
2979 nir_deref_as_struct(tail);
2980 offset = LLVMConstInt(ctx->ac.i32,
2981 deref_struct->index, 0);
2982 break;
2983 }
2984 default:
2985 unreachable("bad deref type");
2986 }
2987 val = ac_build_gep0(&ctx->ac, val, offset);
2988 tail = tail->child;
2989 }
2990 return val;
2991 }
2992
2993 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2994 nir_intrinsic_instr *instr)
2995 {
2996 LLVMValueRef values[8];
2997 int idx = instr->variables[0]->var->data.driver_location;
2998 int ve = instr->dest.ssa.num_components;
2999 unsigned comp = instr->variables[0]->var->data.location_frac;
3000 LLVMValueRef indir_index;
3001 LLVMValueRef ret;
3002 unsigned const_index;
3003 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3004 instr->variables[0]->var->data.mode == nir_var_shader_in;
3005 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3006 &const_index, &indir_index);
3007
3008 if (instr->dest.ssa.bit_size == 64)
3009 ve *= 2;
3010
3011 switch (instr->variables[0]->var->data.mode) {
3012 case nir_var_shader_in:
3013 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3014 return load_tcs_input(ctx->nctx, instr);
3015 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3016 return load_tes_input(ctx->nctx, instr);
3017 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3018 LLVMValueRef indir_index;
3019 unsigned const_index, vertex_index;
3020 get_deref_offset(ctx, instr->variables[0],
3021 false, &vertex_index, NULL,
3022 &const_index, &indir_index);
3023 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3024 instr->variables[0]->var->data.driver_location,
3025 instr->variables[0]->var->data.location_frac, ve,
3026 vertex_index, const_index,
3027 nir2llvmtype(ctx, instr->variables[0]->var->type));
3028 }
3029
3030 for (unsigned chan = comp; chan < ve + comp; chan++) {
3031 if (indir_index) {
3032 unsigned count = glsl_count_attribute_slots(
3033 instr->variables[0]->var->type,
3034 ctx->stage == MESA_SHADER_VERTEX);
3035 count -= chan / 4;
3036 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3037 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3038 4, false, true);
3039
3040 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3041 tmp_vec,
3042 indir_index, "");
3043 } else
3044 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3045 }
3046 break;
3047 case nir_var_local:
3048 for (unsigned chan = 0; chan < ve; chan++) {
3049 if (indir_index) {
3050 unsigned count = glsl_count_attribute_slots(
3051 instr->variables[0]->var->type, false);
3052 count -= chan / 4;
3053 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3054 &ctx->ac, ctx->locals + idx + chan, count,
3055 4, true, true);
3056
3057 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3058 tmp_vec,
3059 indir_index, "");
3060 } else {
3061 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3062 }
3063 }
3064 break;
3065 case nir_var_shared: {
3066 LLVMValueRef address = build_gep_for_deref(ctx,
3067 instr->variables[0]);
3068 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3069 return LLVMBuildBitCast(ctx->ac.builder, val,
3070 get_def_type(ctx, &instr->dest.ssa),
3071 "");
3072 }
3073 case nir_var_shader_out:
3074 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3075 return load_tcs_output(ctx->nctx, instr);
3076
3077 for (unsigned chan = comp; chan < ve + comp; chan++) {
3078 if (indir_index) {
3079 unsigned count = glsl_count_attribute_slots(
3080 instr->variables[0]->var->type, false);
3081 count -= chan / 4;
3082 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3083 &ctx->ac, ctx->outputs + idx + chan, count,
3084 4, true, true);
3085
3086 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3087 tmp_vec,
3088 indir_index, "");
3089 } else {
3090 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3091 ctx->outputs[idx + chan + const_index * 4],
3092 "");
3093 }
3094 }
3095 break;
3096 default:
3097 unreachable("unhandle variable mode");
3098 }
3099 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3100 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3101 }
3102
3103 static void
3104 visit_store_var(struct ac_nir_context *ctx,
3105 nir_intrinsic_instr *instr)
3106 {
3107 LLVMValueRef temp_ptr, value;
3108 int idx = instr->variables[0]->var->data.driver_location;
3109 unsigned comp = instr->variables[0]->var->data.location_frac;
3110 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3111 int writemask = instr->const_index[0] << comp;
3112 LLVMValueRef indir_index;
3113 unsigned const_index;
3114 get_deref_offset(ctx, instr->variables[0], false,
3115 NULL, NULL, &const_index, &indir_index);
3116
3117 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3118 int old_writemask = writemask;
3119
3120 src = LLVMBuildBitCast(ctx->ac.builder, src,
3121 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3122 "");
3123
3124 writemask = 0;
3125 for (unsigned chan = 0; chan < 4; chan++) {
3126 if (old_writemask & (1 << chan))
3127 writemask |= 3u << (2 * chan);
3128 }
3129 }
3130
3131 switch (instr->variables[0]->var->data.mode) {
3132 case nir_var_shader_out:
3133
3134 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3135 store_tcs_output(ctx->nctx, instr, src, writemask);
3136 return;
3137 }
3138
3139 for (unsigned chan = 0; chan < 8; chan++) {
3140 int stride = 4;
3141 if (!(writemask & (1 << chan)))
3142 continue;
3143
3144 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3145
3146 if (instr->variables[0]->var->data.compact)
3147 stride = 1;
3148 if (indir_index) {
3149 unsigned count = glsl_count_attribute_slots(
3150 instr->variables[0]->var->type, false);
3151 count -= chan / 4;
3152 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3153 &ctx->ac, ctx->outputs + idx + chan, count,
3154 stride, true, true);
3155
3156 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3157 value, indir_index, "");
3158 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3159 count, stride, tmp_vec);
3160
3161 } else {
3162 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3163
3164 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3165 }
3166 }
3167 break;
3168 case nir_var_local:
3169 for (unsigned chan = 0; chan < 8; chan++) {
3170 if (!(writemask & (1 << chan)))
3171 continue;
3172
3173 value = llvm_extract_elem(&ctx->ac, src, chan);
3174 if (indir_index) {
3175 unsigned count = glsl_count_attribute_slots(
3176 instr->variables[0]->var->type, false);
3177 count -= chan / 4;
3178 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3179 &ctx->ac, ctx->locals + idx + chan, count,
3180 4, true, true);
3181
3182 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3183 value, indir_index, "");
3184 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3185 count, 4, tmp_vec);
3186 } else {
3187 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3188
3189 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3190 }
3191 }
3192 break;
3193 case nir_var_shared: {
3194 int writemask = instr->const_index[0];
3195 LLVMValueRef address = build_gep_for_deref(ctx,
3196 instr->variables[0]);
3197 LLVMValueRef val = get_src(ctx, instr->src[0]);
3198 unsigned components =
3199 glsl_get_vector_elements(
3200 nir_deref_tail(&instr->variables[0]->deref)->type);
3201 if (writemask == (1 << components) - 1) {
3202 val = LLVMBuildBitCast(
3203 ctx->ac.builder, val,
3204 LLVMGetElementType(LLVMTypeOf(address)), "");
3205 LLVMBuildStore(ctx->ac.builder, val, address);
3206 } else {
3207 for (unsigned chan = 0; chan < 4; chan++) {
3208 if (!(writemask & (1 << chan)))
3209 continue;
3210 LLVMValueRef ptr =
3211 LLVMBuildStructGEP(ctx->ac.builder,
3212 address, chan, "");
3213 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3214 chan);
3215 src = LLVMBuildBitCast(
3216 ctx->ac.builder, src,
3217 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3218 LLVMBuildStore(ctx->ac.builder, src, ptr);
3219 }
3220 }
3221 break;
3222 }
3223 default:
3224 break;
3225 }
3226 }
3227
3228 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3229 {
3230 switch (dim) {
3231 case GLSL_SAMPLER_DIM_BUF:
3232 return 1;
3233 case GLSL_SAMPLER_DIM_1D:
3234 return array ? 2 : 1;
3235 case GLSL_SAMPLER_DIM_2D:
3236 return array ? 3 : 2;
3237 case GLSL_SAMPLER_DIM_MS:
3238 return array ? 4 : 3;
3239 case GLSL_SAMPLER_DIM_3D:
3240 case GLSL_SAMPLER_DIM_CUBE:
3241 return 3;
3242 case GLSL_SAMPLER_DIM_RECT:
3243 case GLSL_SAMPLER_DIM_SUBPASS:
3244 return 2;
3245 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3246 return 3;
3247 default:
3248 break;
3249 }
3250 return 0;
3251 }
3252
3253
3254
3255 /* Adjust the sample index according to FMASK.
3256 *
3257 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3258 * which is the identity mapping. Each nibble says which physical sample
3259 * should be fetched to get that sample.
3260 *
3261 * For example, 0x11111100 means there are only 2 samples stored and
3262 * the second sample covers 3/4 of the pixel. When reading samples 0
3263 * and 1, return physical sample 0 (determined by the first two 0s
3264 * in FMASK), otherwise return physical sample 1.
3265 *
3266 * The sample index should be adjusted as follows:
3267 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3268 */
3269 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3270 LLVMValueRef coord_x, LLVMValueRef coord_y,
3271 LLVMValueRef coord_z,
3272 LLVMValueRef sample_index,
3273 LLVMValueRef fmask_desc_ptr)
3274 {
3275 LLVMValueRef fmask_load_address[4];
3276 LLVMValueRef res;
3277
3278 fmask_load_address[0] = coord_x;
3279 fmask_load_address[1] = coord_y;
3280 if (coord_z) {
3281 fmask_load_address[2] = coord_z;
3282 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3283 }
3284
3285 struct ac_image_args args = {0};
3286
3287 args.opcode = ac_image_load;
3288 args.da = coord_z ? true : false;
3289 args.resource = fmask_desc_ptr;
3290 args.dmask = 0xf;
3291 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3292
3293 res = ac_build_image_opcode(ctx, &args);
3294
3295 res = ac_to_integer(ctx, res);
3296 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3297 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3298
3299 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3300 res,
3301 ctx->i32_0, "");
3302
3303 LLVMValueRef sample_index4 =
3304 LLVMBuildMul(ctx->builder, sample_index, four, "");
3305 LLVMValueRef shifted_fmask =
3306 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3307 LLVMValueRef final_sample =
3308 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3309
3310 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3311 * resource descriptor is 0 (invalid),
3312 */
3313 LLVMValueRef fmask_desc =
3314 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3315 ctx->v8i32, "");
3316
3317 LLVMValueRef fmask_word1 =
3318 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3319 ctx->i32_1, "");
3320
3321 LLVMValueRef word1_is_nonzero =
3322 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3323 fmask_word1, ctx->i32_0, "");
3324
3325 /* Replace the MSAA sample index. */
3326 sample_index =
3327 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3328 final_sample, sample_index, "");
3329 return sample_index;
3330 }
3331
3332 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3333 const nir_intrinsic_instr *instr)
3334 {
3335 const struct glsl_type *type = instr->variables[0]->var->type;
3336 if(instr->variables[0]->deref.child)
3337 type = instr->variables[0]->deref.child->type;
3338
3339 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3340 LLVMValueRef coords[4];
3341 LLVMValueRef masks[] = {
3342 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3343 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3344 };
3345 LLVMValueRef res;
3346 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3347
3348 int count;
3349 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3350 bool is_array = glsl_sampler_type_is_array(type);
3351 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3352 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3353 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3354 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3355 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3356 count = image_type_to_components_count(dim, is_array);
3357
3358 if (is_ms) {
3359 LLVMValueRef fmask_load_address[3];
3360 int chan;
3361
3362 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3363 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3364 if (is_array)
3365 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3366 else
3367 fmask_load_address[2] = NULL;
3368 if (add_frag_pos) {
3369 for (chan = 0; chan < 2; ++chan)
3370 fmask_load_address[chan] =
3371 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3372 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3373 ctx->ac.i32, ""), "");
3374 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3375 }
3376 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3377 fmask_load_address[0],
3378 fmask_load_address[1],
3379 fmask_load_address[2],
3380 sample_index,
3381 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3382 }
3383 if (count == 1 && !gfx9_1d) {
3384 if (instr->src[0].ssa->num_components)
3385 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3386 else
3387 res = src0;
3388 } else {
3389 int chan;
3390 if (is_ms)
3391 count--;
3392 for (chan = 0; chan < count; ++chan) {
3393 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3394 }
3395 if (add_frag_pos) {
3396 for (chan = 0; chan < 2; ++chan)
3397 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3398 ctx->ac.i32, ""), "");
3399 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3400 count++;
3401 }
3402
3403 if (gfx9_1d) {
3404 if (is_array) {
3405 coords[2] = coords[1];
3406 coords[1] = ctx->ac.i32_0;
3407 } else
3408 coords[1] = ctx->ac.i32_0;
3409 count++;
3410 }
3411
3412 if (is_ms) {
3413 coords[count] = sample_index;
3414 count++;
3415 }
3416
3417 if (count == 3) {
3418 coords[3] = LLVMGetUndef(ctx->ac.i32);
3419 count = 4;
3420 }
3421 res = ac_build_gather_values(&ctx->ac, coords, count);
3422 }
3423 return res;
3424 }
3425
3426 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3427 const nir_intrinsic_instr *instr)
3428 {
3429 LLVMValueRef params[7];
3430 LLVMValueRef res;
3431 char intrinsic_name[64];
3432 const nir_variable *var = instr->variables[0]->var;
3433 const struct glsl_type *type = var->type;
3434
3435 if(instr->variables[0]->deref.child)
3436 type = instr->variables[0]->deref.child->type;
3437
3438 type = glsl_without_array(type);
3439 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3440 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3441 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3442 ctx->ac.i32_0, ""); /* vindex */
3443 params[2] = ctx->ac.i32_0; /* voffset */
3444 params[3] = ctx->ac.i1false; /* glc */
3445 params[4] = ctx->ac.i1false; /* slc */
3446 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3447 params, 5, 0);
3448
3449 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3450 res = ac_to_integer(&ctx->ac, res);
3451 } else {
3452 bool is_da = glsl_sampler_type_is_array(type) ||
3453 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3454 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3455 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3456 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3457 LLVMValueRef glc = ctx->ac.i1false;
3458 LLVMValueRef slc = ctx->ac.i1false;
3459
3460 params[0] = get_image_coords(ctx, instr);
3461 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3462 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3463 if (HAVE_LLVM <= 0x0309) {
3464 params[3] = ctx->ac.i1false; /* r128 */
3465 params[4] = da;
3466 params[5] = glc;
3467 params[6] = slc;
3468 } else {
3469 LLVMValueRef lwe = ctx->ac.i1false;
3470 params[3] = glc;
3471 params[4] = slc;
3472 params[5] = lwe;
3473 params[6] = da;
3474 }
3475
3476 ac_get_image_intr_name("llvm.amdgcn.image.load",
3477 ctx->ac.v4f32, /* vdata */
3478 LLVMTypeOf(params[0]), /* coords */
3479 LLVMTypeOf(params[1]), /* rsrc */
3480 intrinsic_name, sizeof(intrinsic_name));
3481
3482 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3483 params, 7, AC_FUNC_ATTR_READONLY);
3484 }
3485 return ac_to_integer(&ctx->ac, res);
3486 }
3487
3488 static void visit_image_store(struct ac_nir_context *ctx,
3489 nir_intrinsic_instr *instr)
3490 {
3491 LLVMValueRef params[8];
3492 char intrinsic_name[64];
3493 const nir_variable *var = instr->variables[0]->var;
3494 const struct glsl_type *type = glsl_without_array(var->type);
3495 LLVMValueRef glc = ctx->ac.i1false;
3496 bool force_glc = ctx->ac.chip_class == SI;
3497 if (force_glc)
3498 glc = ctx->ac.i1true;
3499
3500 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3501 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3502 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3503 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3504 ctx->ac.i32_0, ""); /* vindex */
3505 params[3] = ctx->ac.i32_0; /* voffset */
3506 params[4] = glc; /* glc */
3507 params[5] = ctx->ac.i1false; /* slc */
3508 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3509 params, 6, 0);
3510 } else {
3511 bool is_da = glsl_sampler_type_is_array(type) ||
3512 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3513 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3514 LLVMValueRef slc = ctx->ac.i1false;
3515
3516 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3517 params[1] = get_image_coords(ctx, instr); /* coords */
3518 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3519 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3520 if (HAVE_LLVM <= 0x0309) {
3521 params[4] = ctx->ac.i1false; /* r128 */
3522 params[5] = da;
3523 params[6] = glc;
3524 params[7] = slc;
3525 } else {
3526 LLVMValueRef lwe = ctx->ac.i1false;
3527 params[4] = glc;
3528 params[5] = slc;
3529 params[6] = lwe;
3530 params[7] = da;
3531 }
3532
3533 ac_get_image_intr_name("llvm.amdgcn.image.store",
3534 LLVMTypeOf(params[0]), /* vdata */
3535 LLVMTypeOf(params[1]), /* coords */
3536 LLVMTypeOf(params[2]), /* rsrc */
3537 intrinsic_name, sizeof(intrinsic_name));
3538
3539 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3540 params, 8, 0);
3541 }
3542
3543 }
3544
3545 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3546 const nir_intrinsic_instr *instr)
3547 {
3548 LLVMValueRef params[7];
3549 int param_count = 0;
3550 const nir_variable *var = instr->variables[0]->var;
3551
3552 const char *atomic_name;
3553 char intrinsic_name[41];
3554 const struct glsl_type *type = glsl_without_array(var->type);
3555 MAYBE_UNUSED int length;
3556
3557 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3558
3559 switch (instr->intrinsic) {
3560 case nir_intrinsic_image_atomic_add:
3561 atomic_name = "add";
3562 break;
3563 case nir_intrinsic_image_atomic_min:
3564 atomic_name = is_unsigned ? "umin" : "smin";
3565 break;
3566 case nir_intrinsic_image_atomic_max:
3567 atomic_name = is_unsigned ? "umax" : "smax";
3568 break;
3569 case nir_intrinsic_image_atomic_and:
3570 atomic_name = "and";
3571 break;
3572 case nir_intrinsic_image_atomic_or:
3573 atomic_name = "or";
3574 break;
3575 case nir_intrinsic_image_atomic_xor:
3576 atomic_name = "xor";
3577 break;
3578 case nir_intrinsic_image_atomic_exchange:
3579 atomic_name = "swap";
3580 break;
3581 case nir_intrinsic_image_atomic_comp_swap:
3582 atomic_name = "cmpswap";
3583 break;
3584 default:
3585 abort();
3586 }
3587
3588 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3589 params[param_count++] = get_src(ctx, instr->src[3]);
3590 params[param_count++] = get_src(ctx, instr->src[2]);
3591
3592 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3593 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3594 NULL, true, true);
3595 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3596 ctx->ac.i32_0, ""); /* vindex */
3597 params[param_count++] = ctx->ac.i32_0; /* voffset */
3598 params[param_count++] = ctx->ac.i1false; /* slc */
3599
3600 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3601 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3602 } else {
3603 char coords_type[8];
3604
3605 bool da = glsl_sampler_type_is_array(type) ||
3606 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3607
3608 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3609 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3610 NULL, true, true);
3611 params[param_count++] = ctx->ac.i1false; /* r128 */
3612 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3613 params[param_count++] = ctx->ac.i1false; /* slc */
3614
3615 build_int_type_name(LLVMTypeOf(coords),
3616 coords_type, sizeof(coords_type));
3617
3618 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3619 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3620 }
3621
3622 assert(length < sizeof(intrinsic_name));
3623 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3624 }
3625
3626 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3627 const nir_intrinsic_instr *instr)
3628 {
3629 LLVMValueRef res;
3630 const nir_variable *var = instr->variables[0]->var;
3631 const struct glsl_type *type = instr->variables[0]->var->type;
3632 bool da = glsl_sampler_type_is_array(var->type) ||
3633 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3634 if(instr->variables[0]->deref.child)
3635 type = instr->variables[0]->deref.child->type;
3636
3637 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3638 return get_buffer_size(ctx,
3639 get_sampler_desc(ctx, instr->variables[0],
3640 AC_DESC_BUFFER, NULL, true, false), true);
3641
3642 struct ac_image_args args = { 0 };
3643
3644 args.da = da;
3645 args.dmask = 0xf;
3646 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3647 args.opcode = ac_image_get_resinfo;
3648 args.addr = ctx->ac.i32_0;
3649
3650 res = ac_build_image_opcode(&ctx->ac, &args);
3651
3652 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3653
3654 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3655 glsl_sampler_type_is_array(type)) {
3656 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3657 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3658 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3659 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3660 }
3661 if (ctx->ac.chip_class >= GFX9 &&
3662 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3663 glsl_sampler_type_is_array(type)) {
3664 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3665 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3666 ctx->ac.i32_1, "");
3667
3668 }
3669 return res;
3670 }
3671
3672 #define NOOP_WAITCNT 0xf7f
3673 #define LGKM_CNT 0x07f
3674 #define VM_CNT 0xf70
3675
3676 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3677 unsigned simm16)
3678 {
3679 LLVMValueRef args[1] = {
3680 LLVMConstInt(ctx->ac.i32, simm16, false),
3681 };
3682 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3683 ctx->ac.voidt, args, 1, 0);
3684 }
3685
3686 static void emit_membar(struct nir_to_llvm_context *ctx,
3687 const nir_intrinsic_instr *instr)
3688 {
3689 unsigned waitcnt = NOOP_WAITCNT;
3690
3691 switch (instr->intrinsic) {
3692 case nir_intrinsic_memory_barrier:
3693 case nir_intrinsic_group_memory_barrier:
3694 waitcnt &= VM_CNT & LGKM_CNT;
3695 break;
3696 case nir_intrinsic_memory_barrier_atomic_counter:
3697 case nir_intrinsic_memory_barrier_buffer:
3698 case nir_intrinsic_memory_barrier_image:
3699 waitcnt &= VM_CNT;
3700 break;
3701 case nir_intrinsic_memory_barrier_shared:
3702 waitcnt &= LGKM_CNT;
3703 break;
3704 default:
3705 break;
3706 }
3707 if (waitcnt != NOOP_WAITCNT)
3708 emit_waitcnt(ctx, waitcnt);
3709 }
3710
3711 static void emit_barrier(struct nir_to_llvm_context *ctx)
3712 {
3713 /* SI only (thanks to a hw bug workaround):
3714 * The real barrier instruction isn’t needed, because an entire patch
3715 * always fits into a single wave.
3716 */
3717 if (ctx->options->chip_class == SI &&
3718 ctx->stage == MESA_SHADER_TESS_CTRL) {
3719 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3720 return;
3721 }
3722 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3723 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3724 }
3725
3726 static void emit_discard_if(struct ac_nir_context *ctx,
3727 const nir_intrinsic_instr *instr)
3728 {
3729 LLVMValueRef cond;
3730
3731 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3732 get_src(ctx, instr->src[0]),
3733 ctx->ac.i32_0, "");
3734 ac_build_kill_if_false(&ctx->ac, cond);
3735 }
3736
3737 static LLVMValueRef
3738 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3739 {
3740 LLVMValueRef result;
3741 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3742 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3743 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3744
3745 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3746 }
3747
3748 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3749 const nir_intrinsic_instr *instr)
3750 {
3751 LLVMValueRef ptr, result;
3752 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3753 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3754
3755 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3756 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3757 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3758 ptr, src, src1,
3759 LLVMAtomicOrderingSequentiallyConsistent,
3760 LLVMAtomicOrderingSequentiallyConsistent,
3761 false);
3762 } else {
3763 LLVMAtomicRMWBinOp op;
3764 switch (instr->intrinsic) {
3765 case nir_intrinsic_var_atomic_add:
3766 op = LLVMAtomicRMWBinOpAdd;
3767 break;
3768 case nir_intrinsic_var_atomic_umin:
3769 op = LLVMAtomicRMWBinOpUMin;
3770 break;
3771 case nir_intrinsic_var_atomic_umax:
3772 op = LLVMAtomicRMWBinOpUMax;
3773 break;
3774 case nir_intrinsic_var_atomic_imin:
3775 op = LLVMAtomicRMWBinOpMin;
3776 break;
3777 case nir_intrinsic_var_atomic_imax:
3778 op = LLVMAtomicRMWBinOpMax;
3779 break;
3780 case nir_intrinsic_var_atomic_and:
3781 op = LLVMAtomicRMWBinOpAnd;
3782 break;
3783 case nir_intrinsic_var_atomic_or:
3784 op = LLVMAtomicRMWBinOpOr;
3785 break;
3786 case nir_intrinsic_var_atomic_xor:
3787 op = LLVMAtomicRMWBinOpXor;
3788 break;
3789 case nir_intrinsic_var_atomic_exchange:
3790 op = LLVMAtomicRMWBinOpXchg;
3791 break;
3792 default:
3793 return NULL;
3794 }
3795
3796 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3797 LLVMAtomicOrderingSequentiallyConsistent,
3798 false);
3799 }
3800 return result;
3801 }
3802
3803 #define INTERP_CENTER 0
3804 #define INTERP_CENTROID 1
3805 #define INTERP_SAMPLE 2
3806
3807 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3808 enum glsl_interp_mode interp, unsigned location)
3809 {
3810 switch (interp) {
3811 case INTERP_MODE_FLAT:
3812 default:
3813 return NULL;
3814 case INTERP_MODE_SMOOTH:
3815 case INTERP_MODE_NONE:
3816 if (location == INTERP_CENTER)
3817 return ctx->persp_center;
3818 else if (location == INTERP_CENTROID)
3819 return ctx->persp_centroid;
3820 else if (location == INTERP_SAMPLE)
3821 return ctx->persp_sample;
3822 break;
3823 case INTERP_MODE_NOPERSPECTIVE:
3824 if (location == INTERP_CENTER)
3825 return ctx->linear_center;
3826 else if (location == INTERP_CENTROID)
3827 return ctx->linear_centroid;
3828 else if (location == INTERP_SAMPLE)
3829 return ctx->linear_sample;
3830 break;
3831 }
3832 return NULL;
3833 }
3834
3835 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3836 LLVMValueRef sample_id)
3837 {
3838 LLVMValueRef result;
3839 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3840
3841 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3842 const_array(ctx->ac.v2f32, 64), "");
3843
3844 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3845 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3846
3847 return result;
3848 }
3849
3850 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3851 {
3852 LLVMValueRef values[2];
3853
3854 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3855 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3856 return ac_build_gather_values(&ctx->ac, values, 2);
3857 }
3858
3859 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3860 const nir_intrinsic_instr *instr)
3861 {
3862 LLVMValueRef result[4];
3863 LLVMValueRef interp_param, attr_number;
3864 unsigned location;
3865 unsigned chan;
3866 LLVMValueRef src_c0 = NULL;
3867 LLVMValueRef src_c1 = NULL;
3868 LLVMValueRef src0 = NULL;
3869 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3870 switch (instr->intrinsic) {
3871 case nir_intrinsic_interp_var_at_centroid:
3872 location = INTERP_CENTROID;
3873 break;
3874 case nir_intrinsic_interp_var_at_sample:
3875 case nir_intrinsic_interp_var_at_offset:
3876 location = INTERP_CENTER;
3877 src0 = get_src(ctx->nir, instr->src[0]);
3878 break;
3879 default:
3880 break;
3881 }
3882
3883 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3884 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3885 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3886 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3887 LLVMValueRef sample_position;
3888 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3889
3890 /* fetch sample ID */
3891 sample_position = load_sample_position(ctx, src0);
3892
3893 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3894 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3895 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3896 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3897 }
3898 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3899 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3900
3901 if (location == INTERP_CENTER) {
3902 LLVMValueRef ij_out[2];
3903 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3904
3905 /*
3906 * take the I then J parameters, and the DDX/Y for it, and
3907 * calculate the IJ inputs for the interpolator.
3908 * temp1 = ddx * offset/sample.x + I;
3909 * interp_param.I = ddy * offset/sample.y + temp1;
3910 * temp1 = ddx * offset/sample.x + J;
3911 * interp_param.J = ddy * offset/sample.y + temp1;
3912 */
3913 for (unsigned i = 0; i < 2; i++) {
3914 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
3915 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
3916 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3917 ddxy_out, ix_ll, "");
3918 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3919 ddxy_out, iy_ll, "");
3920 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3921 interp_param, ix_ll, "");
3922 LLVMValueRef temp1, temp2;
3923
3924 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3925 ctx->ac.f32, "");
3926
3927 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3928 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3929
3930 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3931 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3932
3933 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3934 temp2, ctx->ac.i32, "");
3935 }
3936 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3937
3938 }
3939
3940 for (chan = 0; chan < 4; chan++) {
3941 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
3942
3943 if (interp_param) {
3944 interp_param = LLVMBuildBitCast(ctx->builder,
3945 interp_param, ctx->ac.v2f32, "");
3946 LLVMValueRef i = LLVMBuildExtractElement(
3947 ctx->builder, interp_param, ctx->ac.i32_0, "");
3948 LLVMValueRef j = LLVMBuildExtractElement(
3949 ctx->builder, interp_param, ctx->ac.i32_1, "");
3950
3951 result[chan] = ac_build_fs_interp(&ctx->ac,
3952 llvm_chan, attr_number,
3953 ctx->prim_mask, i, j);
3954 } else {
3955 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3956 LLVMConstInt(ctx->ac.i32, 2, false),
3957 llvm_chan, attr_number,
3958 ctx->prim_mask);
3959 }
3960 }
3961 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
3962 instr->variables[0]->var->data.location_frac);
3963 }
3964
3965 static void
3966 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
3967 {
3968 LLVMValueRef gs_next_vertex;
3969 LLVMValueRef can_emit;
3970 int idx;
3971 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3972
3973 /* Write vertex attribute values to GSVS ring */
3974 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3975 ctx->gs_next_vertex,
3976 "");
3977
3978 /* If this thread has already emitted the declared maximum number of
3979 * vertices, kill it: excessive vertex emissions are not supposed to
3980 * have any effect, and GS threads have no externally observable
3981 * effects other than emitting vertices.
3982 */
3983 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3984 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
3985 ac_build_kill_if_false(&ctx->ac, can_emit);
3986
3987 /* loop num outputs */
3988 idx = 0;
3989 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3990 LLVMValueRef *out_ptr = &addrs[i * 4];
3991 int length = 4;
3992 int slot = idx;
3993 int slot_inc = 1;
3994
3995 if (!(ctx->output_mask & (1ull << i)))
3996 continue;
3997
3998 if (i == VARYING_SLOT_CLIP_DIST0) {
3999 /* pack clip and cull into a single set of slots */
4000 length = ctx->num_output_clips + ctx->num_output_culls;
4001 if (length > 4)
4002 slot_inc = 2;
4003 }
4004 for (unsigned j = 0; j < length; j++) {
4005 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4006 out_ptr[j], "");
4007 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4008 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4009 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4010
4011 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4012
4013 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4014 out_val, 1,
4015 voffset, ctx->gs2vs_offset, 0,
4016 1, 1, true, true);
4017 }
4018 idx += slot_inc;
4019 }
4020
4021 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4022 ctx->ac.i32_1, "");
4023 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4024
4025 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4026 }
4027
4028 static void
4029 visit_end_primitive(struct nir_to_llvm_context *ctx,
4030 const nir_intrinsic_instr *instr)
4031 {
4032 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4033 }
4034
4035 static LLVMValueRef
4036 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4037 const nir_intrinsic_instr *instr)
4038 {
4039 LLVMValueRef coord[4] = {
4040 ctx->tes_u,
4041 ctx->tes_v,
4042 ctx->ac.f32_0,
4043 ctx->ac.f32_0,
4044 };
4045
4046 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4047 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4048 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4049
4050 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4051 return LLVMBuildBitCast(ctx->builder, result,
4052 get_def_type(ctx->nir, &instr->dest.ssa), "");
4053 }
4054
4055 static void visit_intrinsic(struct ac_nir_context *ctx,
4056 nir_intrinsic_instr *instr)
4057 {
4058 LLVMValueRef result = NULL;
4059
4060 switch (instr->intrinsic) {
4061 case nir_intrinsic_load_work_group_id: {
4062 result = ctx->nctx->workgroup_ids;
4063 break;
4064 }
4065 case nir_intrinsic_load_base_vertex: {
4066 result = ctx->abi->base_vertex;
4067 break;
4068 }
4069 case nir_intrinsic_load_vertex_id_zero_base: {
4070 result = ctx->abi->vertex_id;
4071 break;
4072 }
4073 case nir_intrinsic_load_local_invocation_id: {
4074 result = ctx->nctx->local_invocation_ids;
4075 break;
4076 }
4077 case nir_intrinsic_load_base_instance:
4078 result = ctx->abi->start_instance;
4079 break;
4080 case nir_intrinsic_load_draw_id:
4081 result = ctx->abi->draw_id;
4082 break;
4083 case nir_intrinsic_load_view_index:
4084 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4085 break;
4086 case nir_intrinsic_load_invocation_id:
4087 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4088 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4089 else
4090 result = ctx->abi->gs_invocation_id;
4091 break;
4092 case nir_intrinsic_load_primitive_id:
4093 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4094 if (ctx->nctx)
4095 ctx->nctx->shader_info->gs.uses_prim_id = true;
4096 result = ctx->abi->gs_prim_id;
4097 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4098 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4099 result = ctx->nctx->tcs_patch_id;
4100 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4101 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4102 result = ctx->nctx->tes_patch_id;
4103 } else
4104 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4105 break;
4106 case nir_intrinsic_load_sample_id:
4107 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4108 break;
4109 case nir_intrinsic_load_sample_pos:
4110 result = load_sample_pos(ctx);
4111 break;
4112 case nir_intrinsic_load_sample_mask_in:
4113 result = ctx->abi->sample_coverage;
4114 break;
4115 case nir_intrinsic_load_frag_coord: {
4116 LLVMValueRef values[4] = {
4117 ctx->abi->frag_pos[0],
4118 ctx->abi->frag_pos[1],
4119 ctx->abi->frag_pos[2],
4120 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4121 };
4122 result = ac_build_gather_values(&ctx->ac, values, 4);
4123 break;
4124 }
4125 case nir_intrinsic_load_front_face:
4126 result = ctx->abi->front_face;
4127 break;
4128 case nir_intrinsic_load_instance_id:
4129 result = ctx->abi->instance_id;
4130 break;
4131 case nir_intrinsic_load_num_work_groups:
4132 result = ctx->nctx->num_work_groups;
4133 break;
4134 case nir_intrinsic_load_local_invocation_index:
4135 result = visit_load_local_invocation_index(ctx->nctx);
4136 break;
4137 case nir_intrinsic_load_push_constant:
4138 result = visit_load_push_constant(ctx->nctx, instr);
4139 break;
4140 case nir_intrinsic_vulkan_resource_index:
4141 result = visit_vulkan_resource_index(ctx->nctx, instr);
4142 break;
4143 case nir_intrinsic_vulkan_resource_reindex:
4144 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4145 break;
4146 case nir_intrinsic_store_ssbo:
4147 visit_store_ssbo(ctx, instr);
4148 break;
4149 case nir_intrinsic_load_ssbo:
4150 result = visit_load_buffer(ctx, instr);
4151 break;
4152 case nir_intrinsic_ssbo_atomic_add:
4153 case nir_intrinsic_ssbo_atomic_imin:
4154 case nir_intrinsic_ssbo_atomic_umin:
4155 case nir_intrinsic_ssbo_atomic_imax:
4156 case nir_intrinsic_ssbo_atomic_umax:
4157 case nir_intrinsic_ssbo_atomic_and:
4158 case nir_intrinsic_ssbo_atomic_or:
4159 case nir_intrinsic_ssbo_atomic_xor:
4160 case nir_intrinsic_ssbo_atomic_exchange:
4161 case nir_intrinsic_ssbo_atomic_comp_swap:
4162 result = visit_atomic_ssbo(ctx, instr);
4163 break;
4164 case nir_intrinsic_load_ubo:
4165 result = visit_load_ubo_buffer(ctx, instr);
4166 break;
4167 case nir_intrinsic_get_buffer_size:
4168 result = visit_get_buffer_size(ctx, instr);
4169 break;
4170 case nir_intrinsic_load_var:
4171 result = visit_load_var(ctx, instr);
4172 break;
4173 case nir_intrinsic_store_var:
4174 visit_store_var(ctx, instr);
4175 break;
4176 case nir_intrinsic_image_load:
4177 result = visit_image_load(ctx, instr);
4178 break;
4179 case nir_intrinsic_image_store:
4180 visit_image_store(ctx, instr);
4181 break;
4182 case nir_intrinsic_image_atomic_add:
4183 case nir_intrinsic_image_atomic_min:
4184 case nir_intrinsic_image_atomic_max:
4185 case nir_intrinsic_image_atomic_and:
4186 case nir_intrinsic_image_atomic_or:
4187 case nir_intrinsic_image_atomic_xor:
4188 case nir_intrinsic_image_atomic_exchange:
4189 case nir_intrinsic_image_atomic_comp_swap:
4190 result = visit_image_atomic(ctx, instr);
4191 break;
4192 case nir_intrinsic_image_size:
4193 result = visit_image_size(ctx, instr);
4194 break;
4195 case nir_intrinsic_discard:
4196 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4197 LLVMVoidTypeInContext(ctx->ac.context),
4198 NULL, 0, AC_FUNC_ATTR_LEGACY);
4199 break;
4200 case nir_intrinsic_discard_if:
4201 emit_discard_if(ctx, instr);
4202 break;
4203 case nir_intrinsic_memory_barrier:
4204 case nir_intrinsic_group_memory_barrier:
4205 case nir_intrinsic_memory_barrier_atomic_counter:
4206 case nir_intrinsic_memory_barrier_buffer:
4207 case nir_intrinsic_memory_barrier_image:
4208 case nir_intrinsic_memory_barrier_shared:
4209 emit_membar(ctx->nctx, instr);
4210 break;
4211 case nir_intrinsic_barrier:
4212 emit_barrier(ctx->nctx);
4213 break;
4214 case nir_intrinsic_var_atomic_add:
4215 case nir_intrinsic_var_atomic_imin:
4216 case nir_intrinsic_var_atomic_umin:
4217 case nir_intrinsic_var_atomic_imax:
4218 case nir_intrinsic_var_atomic_umax:
4219 case nir_intrinsic_var_atomic_and:
4220 case nir_intrinsic_var_atomic_or:
4221 case nir_intrinsic_var_atomic_xor:
4222 case nir_intrinsic_var_atomic_exchange:
4223 case nir_intrinsic_var_atomic_comp_swap:
4224 result = visit_var_atomic(ctx->nctx, instr);
4225 break;
4226 case nir_intrinsic_interp_var_at_centroid:
4227 case nir_intrinsic_interp_var_at_sample:
4228 case nir_intrinsic_interp_var_at_offset:
4229 result = visit_interp(ctx->nctx, instr);
4230 break;
4231 case nir_intrinsic_emit_vertex:
4232 assert(instr->const_index[0] == 0);
4233 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4234 break;
4235 case nir_intrinsic_end_primitive:
4236 visit_end_primitive(ctx->nctx, instr);
4237 break;
4238 case nir_intrinsic_load_tess_coord:
4239 result = visit_load_tess_coord(ctx->nctx, instr);
4240 break;
4241 case nir_intrinsic_load_patch_vertices_in:
4242 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4243 break;
4244 default:
4245 fprintf(stderr, "Unknown intrinsic: ");
4246 nir_print_instr(&instr->instr, stderr);
4247 fprintf(stderr, "\n");
4248 break;
4249 }
4250 if (result) {
4251 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4252 }
4253 }
4254
4255 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4256 LLVMValueRef buffer_ptr, bool write)
4257 {
4258 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4259
4260 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4261 ctx->shader_info->fs.writes_memory = true;
4262
4263 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4264 }
4265
4266 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4267 {
4268 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4269
4270 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4271 }
4272
4273 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4274 unsigned descriptor_set,
4275 unsigned base_index,
4276 unsigned constant_index,
4277 LLVMValueRef index,
4278 enum ac_descriptor_type desc_type,
4279 bool image, bool write)
4280 {
4281 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4282 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4283 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4284 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4285 unsigned offset = binding->offset;
4286 unsigned stride = binding->size;
4287 unsigned type_size;
4288 LLVMBuilderRef builder = ctx->builder;
4289 LLVMTypeRef type;
4290
4291 assert(base_index < layout->binding_count);
4292
4293 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4294 ctx->shader_info->fs.writes_memory = true;
4295
4296 switch (desc_type) {
4297 case AC_DESC_IMAGE:
4298 type = ctx->ac.v8i32;
4299 type_size = 32;
4300 break;
4301 case AC_DESC_FMASK:
4302 type = ctx->ac.v8i32;
4303 offset += 32;
4304 type_size = 32;
4305 break;
4306 case AC_DESC_SAMPLER:
4307 type = ctx->ac.v4i32;
4308 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4309 offset += 64;
4310
4311 type_size = 16;
4312 break;
4313 case AC_DESC_BUFFER:
4314 type = ctx->ac.v4i32;
4315 type_size = 16;
4316 break;
4317 default:
4318 unreachable("invalid desc_type\n");
4319 }
4320
4321 offset += constant_index * stride;
4322
4323 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4324 (!index || binding->immutable_samplers_equal)) {
4325 if (binding->immutable_samplers_equal)
4326 constant_index = 0;
4327
4328 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4329
4330 LLVMValueRef constants[] = {
4331 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4332 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4333 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4334 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4335 };
4336 return ac_build_gather_values(&ctx->ac, constants, 4);
4337 }
4338
4339 assert(stride % type_size == 0);
4340
4341 if (!index)
4342 index = ctx->ac.i32_0;
4343
4344 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4345
4346 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4347 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4348
4349 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4350 }
4351
4352 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4353 const nir_deref_var *deref,
4354 enum ac_descriptor_type desc_type,
4355 const nir_tex_instr *tex_instr,
4356 bool image, bool write)
4357 {
4358 LLVMValueRef index = NULL;
4359 unsigned constant_index = 0;
4360 unsigned descriptor_set;
4361 unsigned base_index;
4362
4363 if (!deref) {
4364 assert(tex_instr && !image);
4365 descriptor_set = 0;
4366 base_index = tex_instr->sampler_index;
4367 } else {
4368 const nir_deref *tail = &deref->deref;
4369 while (tail->child) {
4370 const nir_deref_array *child = nir_deref_as_array(tail->child);
4371 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4372
4373 if (!array_size)
4374 array_size = 1;
4375
4376 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4377
4378 if (child->deref_array_type == nir_deref_array_type_indirect) {
4379 LLVMValueRef indirect = get_src(ctx, child->indirect);
4380
4381 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4382 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4383
4384 if (!index)
4385 index = indirect;
4386 else
4387 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4388 }
4389
4390 constant_index += child->base_offset * array_size;
4391
4392 tail = &child->deref;
4393 }
4394 descriptor_set = deref->var->data.descriptor_set;
4395 base_index = deref->var->data.binding;
4396 }
4397
4398 return ctx->abi->load_sampler_desc(ctx->abi,
4399 descriptor_set,
4400 base_index,
4401 constant_index, index,
4402 desc_type, image, write);
4403 }
4404
4405 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4406 struct ac_image_args *args,
4407 const nir_tex_instr *instr,
4408 nir_texop op,
4409 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4410 LLVMValueRef *param, unsigned count,
4411 unsigned dmask)
4412 {
4413 unsigned is_rect = 0;
4414 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4415
4416 if (op == nir_texop_lod)
4417 da = false;
4418 /* Pad to power of two vector */
4419 while (count < util_next_power_of_two(count))
4420 param[count++] = LLVMGetUndef(ctx->i32);
4421
4422 if (count > 1)
4423 args->addr = ac_build_gather_values(ctx, param, count);
4424 else
4425 args->addr = param[0];
4426
4427 args->resource = res_ptr;
4428 args->sampler = samp_ptr;
4429
4430 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4431 args->addr = param[0];
4432 return;
4433 }
4434
4435 args->dmask = dmask;
4436 args->unorm = is_rect;
4437 args->da = da;
4438 }
4439
4440 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4441 *
4442 * SI-CI:
4443 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4444 * filtering manually. The driver sets img7 to a mask clearing
4445 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4446 * s_and_b32 samp0, samp0, img7
4447 *
4448 * VI:
4449 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4450 */
4451 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4452 LLVMValueRef res, LLVMValueRef samp)
4453 {
4454 LLVMBuilderRef builder = ctx->ac.builder;
4455 LLVMValueRef img7, samp0;
4456
4457 if (ctx->ac.chip_class >= VI)
4458 return samp;
4459
4460 img7 = LLVMBuildExtractElement(builder, res,
4461 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4462 samp0 = LLVMBuildExtractElement(builder, samp,
4463 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4464 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4465 return LLVMBuildInsertElement(builder, samp, samp0,
4466 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4467 }
4468
4469 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4470 nir_tex_instr *instr,
4471 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4472 LLVMValueRef *fmask_ptr)
4473 {
4474 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4475 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4476 else
4477 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4478 if (samp_ptr) {
4479 if (instr->sampler)
4480 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4481 else
4482 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4483 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4484 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4485 }
4486 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4487 instr->op == nir_texop_samples_identical))
4488 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4489 }
4490
4491 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4492 LLVMValueRef coord)
4493 {
4494 coord = ac_to_float(ctx, coord);
4495 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4496 coord = ac_to_integer(ctx, coord);
4497 return coord;
4498 }
4499
4500 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4501 {
4502 LLVMValueRef result = NULL;
4503 struct ac_image_args args = { 0 };
4504 unsigned dmask = 0xf;
4505 LLVMValueRef address[16];
4506 LLVMValueRef coords[5];
4507 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4508 LLVMValueRef bias = NULL, offsets = NULL;
4509 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4510 LLVMValueRef ddx = NULL, ddy = NULL;
4511 LLVMValueRef derivs[6];
4512 unsigned chan, count = 0;
4513 unsigned const_src = 0, num_deriv_comp = 0;
4514 bool lod_is_zero = false;
4515
4516 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4517
4518 for (unsigned i = 0; i < instr->num_srcs; i++) {
4519 switch (instr->src[i].src_type) {
4520 case nir_tex_src_coord:
4521 coord = get_src(ctx, instr->src[i].src);
4522 break;
4523 case nir_tex_src_projector:
4524 break;
4525 case nir_tex_src_comparator:
4526 comparator = get_src(ctx, instr->src[i].src);
4527 break;
4528 case nir_tex_src_offset:
4529 offsets = get_src(ctx, instr->src[i].src);
4530 const_src = i;
4531 break;
4532 case nir_tex_src_bias:
4533 bias = get_src(ctx, instr->src[i].src);
4534 break;
4535 case nir_tex_src_lod: {
4536 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4537
4538 if (val && val->i32[0] == 0)
4539 lod_is_zero = true;
4540 lod = get_src(ctx, instr->src[i].src);
4541 break;
4542 }
4543 case nir_tex_src_ms_index:
4544 sample_index = get_src(ctx, instr->src[i].src);
4545 break;
4546 case nir_tex_src_ms_mcs:
4547 break;
4548 case nir_tex_src_ddx:
4549 ddx = get_src(ctx, instr->src[i].src);
4550 num_deriv_comp = instr->src[i].src.ssa->num_components;
4551 break;
4552 case nir_tex_src_ddy:
4553 ddy = get_src(ctx, instr->src[i].src);
4554 break;
4555 case nir_tex_src_texture_offset:
4556 case nir_tex_src_sampler_offset:
4557 case nir_tex_src_plane:
4558 default:
4559 break;
4560 }
4561 }
4562
4563 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4564 result = get_buffer_size(ctx, res_ptr, true);
4565 goto write_result;
4566 }
4567
4568 if (instr->op == nir_texop_texture_samples) {
4569 LLVMValueRef res, samples, is_msaa;
4570 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4571 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4572 LLVMConstInt(ctx->ac.i32, 3, false), "");
4573 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4574 LLVMConstInt(ctx->ac.i32, 28, false), "");
4575 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4576 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4577 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4578 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4579
4580 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4581 LLVMConstInt(ctx->ac.i32, 16, false), "");
4582 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4583 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4584 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4585 samples, "");
4586 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4587 ctx->ac.i32_1, "");
4588 result = samples;
4589 goto write_result;
4590 }
4591
4592 if (coord)
4593 for (chan = 0; chan < instr->coord_components; chan++)
4594 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4595
4596 if (offsets && instr->op != nir_texop_txf) {
4597 LLVMValueRef offset[3], pack;
4598 for (chan = 0; chan < 3; ++chan)
4599 offset[chan] = ctx->ac.i32_0;
4600
4601 args.offset = true;
4602 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4603 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4604 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4605 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4606 if (chan)
4607 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4608 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4609 }
4610 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4611 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4612 address[count++] = pack;
4613
4614 }
4615 /* pack LOD bias value */
4616 if (instr->op == nir_texop_txb && bias) {
4617 address[count++] = bias;
4618 }
4619
4620 /* Pack depth comparison value */
4621 if (instr->is_shadow && comparator) {
4622 LLVMValueRef z = ac_to_float(&ctx->ac,
4623 llvm_extract_elem(&ctx->ac, comparator, 0));
4624
4625 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4626 * so the depth comparison value isn't clamped for Z16 and
4627 * Z24 anymore. Do it manually here.
4628 *
4629 * It's unnecessary if the original texture format was
4630 * Z32_FLOAT, but we don't know that here.
4631 */
4632 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4633 z = ac_build_clamp(&ctx->ac, z);
4634
4635 address[count++] = z;
4636 }
4637
4638 /* pack derivatives */
4639 if (ddx || ddy) {
4640 int num_src_deriv_channels, num_dest_deriv_channels;
4641 switch (instr->sampler_dim) {
4642 case GLSL_SAMPLER_DIM_3D:
4643 case GLSL_SAMPLER_DIM_CUBE:
4644 num_deriv_comp = 3;
4645 num_src_deriv_channels = 3;
4646 num_dest_deriv_channels = 3;
4647 break;
4648 case GLSL_SAMPLER_DIM_2D:
4649 default:
4650 num_src_deriv_channels = 2;
4651 num_dest_deriv_channels = 2;
4652 num_deriv_comp = 2;
4653 break;
4654 case GLSL_SAMPLER_DIM_1D:
4655 num_src_deriv_channels = 1;
4656 if (ctx->ac.chip_class >= GFX9) {
4657 num_dest_deriv_channels = 2;
4658 num_deriv_comp = 2;
4659 } else {
4660 num_dest_deriv_channels = 1;
4661 num_deriv_comp = 1;
4662 }
4663 break;
4664 }
4665
4666 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4667 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4668 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4669 }
4670 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4671 derivs[i] = ctx->ac.f32_0;
4672 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4673 }
4674 }
4675
4676 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4677 for (chan = 0; chan < instr->coord_components; chan++)
4678 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4679 if (instr->coord_components == 3)
4680 coords[3] = LLVMGetUndef(ctx->ac.f32);
4681 ac_prepare_cube_coords(&ctx->ac,
4682 instr->op == nir_texop_txd, instr->is_array,
4683 instr->op == nir_texop_lod, coords, derivs);
4684 if (num_deriv_comp)
4685 num_deriv_comp--;
4686 }
4687
4688 if (ddx || ddy) {
4689 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4690 address[count++] = derivs[i];
4691 }
4692
4693 /* Pack texture coordinates */
4694 if (coord) {
4695 address[count++] = coords[0];
4696 if (instr->coord_components > 1) {
4697 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4698 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4699 }
4700 address[count++] = coords[1];
4701 }
4702 if (instr->coord_components > 2) {
4703 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4704 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4705 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4706 instr->op != nir_texop_txf) {
4707 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4708 }
4709 address[count++] = coords[2];
4710 }
4711
4712 if (ctx->ac.chip_class >= GFX9) {
4713 LLVMValueRef filler;
4714 if (instr->op == nir_texop_txf)
4715 filler = ctx->ac.i32_0;
4716 else
4717 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4718
4719 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4720 /* No nir_texop_lod, because it does not take a slice
4721 * even with array textures. */
4722 if (instr->is_array && instr->op != nir_texop_lod ) {
4723 address[count] = address[count - 1];
4724 address[count - 1] = filler;
4725 count++;
4726 } else
4727 address[count++] = filler;
4728 }
4729 }
4730 }
4731
4732 /* Pack LOD */
4733 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4734 instr->op == nir_texop_txf)) {
4735 address[count++] = lod;
4736 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4737 address[count++] = sample_index;
4738 } else if(instr->op == nir_texop_txs) {
4739 count = 0;
4740 if (lod)
4741 address[count++] = lod;
4742 else
4743 address[count++] = ctx->ac.i32_0;
4744 }
4745
4746 for (chan = 0; chan < count; chan++) {
4747 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4748 address[chan], ctx->ac.i32, "");
4749 }
4750
4751 if (instr->op == nir_texop_samples_identical) {
4752 LLVMValueRef txf_address[4];
4753 struct ac_image_args txf_args = { 0 };
4754 unsigned txf_count = count;
4755 memcpy(txf_address, address, sizeof(txf_address));
4756
4757 if (!instr->is_array)
4758 txf_address[2] = ctx->ac.i32_0;
4759 txf_address[3] = ctx->ac.i32_0;
4760
4761 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4762 fmask_ptr, NULL,
4763 txf_address, txf_count, 0xf);
4764
4765 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4766
4767 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4768 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4769 goto write_result;
4770 }
4771
4772 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4773 instr->op != nir_texop_txs) {
4774 unsigned sample_chan = instr->is_array ? 3 : 2;
4775 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4776 address[0],
4777 address[1],
4778 instr->is_array ? address[2] : NULL,
4779 address[sample_chan],
4780 fmask_ptr);
4781 }
4782
4783 if (offsets && instr->op == nir_texop_txf) {
4784 nir_const_value *const_offset =
4785 nir_src_as_const_value(instr->src[const_src].src);
4786 int num_offsets = instr->src[const_src].src.ssa->num_components;
4787 assert(const_offset);
4788 num_offsets = MIN2(num_offsets, instr->coord_components);
4789 if (num_offsets > 2)
4790 address[2] = LLVMBuildAdd(ctx->ac.builder,
4791 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4792 if (num_offsets > 1)
4793 address[1] = LLVMBuildAdd(ctx->ac.builder,
4794 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4795 address[0] = LLVMBuildAdd(ctx->ac.builder,
4796 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4797
4798 }
4799
4800 /* TODO TG4 support */
4801 if (instr->op == nir_texop_tg4) {
4802 if (instr->is_shadow)
4803 dmask = 1;
4804 else
4805 dmask = 1 << instr->component;
4806 }
4807 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4808 res_ptr, samp_ptr, address, count, dmask);
4809
4810 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4811
4812 if (instr->op == nir_texop_query_levels)
4813 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4814 else if (instr->is_shadow && instr->is_new_style_shadow &&
4815 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4816 instr->op != nir_texop_tg4)
4817 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4818 else if (instr->op == nir_texop_txs &&
4819 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4820 instr->is_array) {
4821 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4822 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4823 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4824 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4825 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4826 } else if (ctx->ac.chip_class >= GFX9 &&
4827 instr->op == nir_texop_txs &&
4828 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4829 instr->is_array) {
4830 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4831 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4832 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4833 ctx->ac.i32_1, "");
4834 } else if (instr->dest.ssa.num_components != 4)
4835 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4836
4837 write_result:
4838 if (result) {
4839 assert(instr->dest.is_ssa);
4840 result = ac_to_integer(&ctx->ac, result);
4841 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4842 }
4843 }
4844
4845
4846 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4847 {
4848 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4849 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4850
4851 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4852 _mesa_hash_table_insert(ctx->phis, instr, result);
4853 }
4854
4855 static void visit_post_phi(struct ac_nir_context *ctx,
4856 nir_phi_instr *instr,
4857 LLVMValueRef llvm_phi)
4858 {
4859 nir_foreach_phi_src(src, instr) {
4860 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4861 LLVMValueRef llvm_src = get_src(ctx, src->src);
4862
4863 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4864 }
4865 }
4866
4867 static void phi_post_pass(struct ac_nir_context *ctx)
4868 {
4869 struct hash_entry *entry;
4870 hash_table_foreach(ctx->phis, entry) {
4871 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4872 (LLVMValueRef)entry->data);
4873 }
4874 }
4875
4876
4877 static void visit_ssa_undef(struct ac_nir_context *ctx,
4878 const nir_ssa_undef_instr *instr)
4879 {
4880 unsigned num_components = instr->def.num_components;
4881 LLVMValueRef undef;
4882
4883 if (num_components == 1)
4884 undef = LLVMGetUndef(ctx->ac.i32);
4885 else {
4886 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4887 }
4888 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4889 }
4890
4891 static void visit_jump(struct ac_nir_context *ctx,
4892 const nir_jump_instr *instr)
4893 {
4894 switch (instr->type) {
4895 case nir_jump_break:
4896 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4897 LLVMClearInsertionPosition(ctx->ac.builder);
4898 break;
4899 case nir_jump_continue:
4900 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4901 LLVMClearInsertionPosition(ctx->ac.builder);
4902 break;
4903 default:
4904 fprintf(stderr, "Unknown NIR jump instr: ");
4905 nir_print_instr(&instr->instr, stderr);
4906 fprintf(stderr, "\n");
4907 abort();
4908 }
4909 }
4910
4911 static void visit_cf_list(struct ac_nir_context *ctx,
4912 struct exec_list *list);
4913
4914 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4915 {
4916 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4917 nir_foreach_instr(instr, block)
4918 {
4919 switch (instr->type) {
4920 case nir_instr_type_alu:
4921 visit_alu(ctx, nir_instr_as_alu(instr));
4922 break;
4923 case nir_instr_type_load_const:
4924 visit_load_const(ctx, nir_instr_as_load_const(instr));
4925 break;
4926 case nir_instr_type_intrinsic:
4927 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4928 break;
4929 case nir_instr_type_tex:
4930 visit_tex(ctx, nir_instr_as_tex(instr));
4931 break;
4932 case nir_instr_type_phi:
4933 visit_phi(ctx, nir_instr_as_phi(instr));
4934 break;
4935 case nir_instr_type_ssa_undef:
4936 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4937 break;
4938 case nir_instr_type_jump:
4939 visit_jump(ctx, nir_instr_as_jump(instr));
4940 break;
4941 default:
4942 fprintf(stderr, "Unknown NIR instr type: ");
4943 nir_print_instr(instr, stderr);
4944 fprintf(stderr, "\n");
4945 abort();
4946 }
4947 }
4948
4949 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4950 }
4951
4952 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4953 {
4954 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4955
4956 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4957 LLVMBasicBlockRef merge_block =
4958 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4959 LLVMBasicBlockRef if_block =
4960 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4961 LLVMBasicBlockRef else_block = merge_block;
4962 if (!exec_list_is_empty(&if_stmt->else_list))
4963 else_block = LLVMAppendBasicBlockInContext(
4964 ctx->ac.context, fn, "");
4965
4966 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4967 LLVMConstInt(ctx->ac.i32, 0, false), "");
4968 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4969
4970 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4971 visit_cf_list(ctx, &if_stmt->then_list);
4972 if (LLVMGetInsertBlock(ctx->ac.builder))
4973 LLVMBuildBr(ctx->ac.builder, merge_block);
4974
4975 if (!exec_list_is_empty(&if_stmt->else_list)) {
4976 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4977 visit_cf_list(ctx, &if_stmt->else_list);
4978 if (LLVMGetInsertBlock(ctx->ac.builder))
4979 LLVMBuildBr(ctx->ac.builder, merge_block);
4980 }
4981
4982 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4983 }
4984
4985 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4986 {
4987 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4988 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4989 LLVMBasicBlockRef break_parent = ctx->break_block;
4990
4991 ctx->continue_block =
4992 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4993 ctx->break_block =
4994 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4995
4996 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4997 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4998 visit_cf_list(ctx, &loop->body);
4999
5000 if (LLVMGetInsertBlock(ctx->ac.builder))
5001 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5002 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5003
5004 ctx->continue_block = continue_parent;
5005 ctx->break_block = break_parent;
5006 }
5007
5008 static void visit_cf_list(struct ac_nir_context *ctx,
5009 struct exec_list *list)
5010 {
5011 foreach_list_typed(nir_cf_node, node, node, list)
5012 {
5013 switch (node->type) {
5014 case nir_cf_node_block:
5015 visit_block(ctx, nir_cf_node_as_block(node));
5016 break;
5017
5018 case nir_cf_node_if:
5019 visit_if(ctx, nir_cf_node_as_if(node));
5020 break;
5021
5022 case nir_cf_node_loop:
5023 visit_loop(ctx, nir_cf_node_as_loop(node));
5024 break;
5025
5026 default:
5027 assert(0);
5028 }
5029 }
5030 }
5031
5032 static void
5033 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5034 struct nir_variable *variable)
5035 {
5036 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5037 LLVMValueRef t_offset;
5038 LLVMValueRef t_list;
5039 LLVMValueRef input;
5040 LLVMValueRef buffer_index;
5041 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5042 int idx = variable->data.location;
5043 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5044
5045 variable->data.driver_location = idx * 4;
5046
5047 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5048 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5049 ctx->abi.start_instance, "");
5050 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5051 ctx->shader_info->vs.vgpr_comp_cnt);
5052 } else
5053 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5054 ctx->abi.base_vertex, "");
5055
5056 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5057 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5058
5059 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5060
5061 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5062 buffer_index,
5063 LLVMConstInt(ctx->ac.i32, 0, false),
5064 true);
5065
5066 for (unsigned chan = 0; chan < 4; chan++) {
5067 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5068 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5069 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5070 input, llvm_chan, ""));
5071 }
5072 }
5073 }
5074
5075 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5076 unsigned attr,
5077 LLVMValueRef interp_param,
5078 LLVMValueRef prim_mask,
5079 LLVMValueRef result[4])
5080 {
5081 LLVMValueRef attr_number;
5082 unsigned chan;
5083 LLVMValueRef i, j;
5084 bool interp = interp_param != NULL;
5085
5086 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5087
5088 /* fs.constant returns the param from the middle vertex, so it's not
5089 * really useful for flat shading. It's meant to be used for custom
5090 * interpolation (but the intrinsic can't fetch from the other two
5091 * vertices).
5092 *
5093 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5094 * to do the right thing. The only reason we use fs.constant is that
5095 * fs.interp cannot be used on integers, because they can be equal
5096 * to NaN.
5097 */
5098 if (interp) {
5099 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5100 ctx->ac.v2f32, "");
5101
5102 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5103 ctx->ac.i32_0, "");
5104 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5105 ctx->ac.i32_1, "");
5106 }
5107
5108 for (chan = 0; chan < 4; chan++) {
5109 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5110
5111 if (interp) {
5112 result[chan] = ac_build_fs_interp(&ctx->ac,
5113 llvm_chan,
5114 attr_number,
5115 prim_mask, i, j);
5116 } else {
5117 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5118 LLVMConstInt(ctx->ac.i32, 2, false),
5119 llvm_chan,
5120 attr_number,
5121 prim_mask);
5122 }
5123 }
5124 }
5125
5126 static void
5127 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5128 struct nir_variable *variable)
5129 {
5130 int idx = variable->data.location;
5131 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5132 LLVMValueRef interp;
5133
5134 variable->data.driver_location = idx * 4;
5135 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5136
5137 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5138 unsigned interp_type;
5139 if (variable->data.sample) {
5140 interp_type = INTERP_SAMPLE;
5141 ctx->shader_info->info.ps.force_persample = true;
5142 } else if (variable->data.centroid)
5143 interp_type = INTERP_CENTROID;
5144 else
5145 interp_type = INTERP_CENTER;
5146
5147 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5148 } else
5149 interp = NULL;
5150
5151 for (unsigned i = 0; i < attrib_count; ++i)
5152 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5153
5154 }
5155
5156 static void
5157 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5158 struct nir_shader *nir) {
5159 nir_foreach_variable(variable, &nir->inputs)
5160 handle_vs_input_decl(ctx, variable);
5161 }
5162
5163 static void
5164 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5165 struct nir_shader *nir)
5166 {
5167 if (!ctx->options->key.fs.multisample)
5168 return;
5169
5170 bool uses_center = false;
5171 bool uses_centroid = false;
5172 nir_foreach_variable(variable, &nir->inputs) {
5173 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5174 variable->data.sample)
5175 continue;
5176
5177 if (variable->data.centroid)
5178 uses_centroid = true;
5179 else
5180 uses_center = true;
5181 }
5182
5183 if (uses_center && uses_centroid) {
5184 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5185 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5186 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5187 }
5188 }
5189
5190 static void
5191 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5192 struct nir_shader *nir)
5193 {
5194 prepare_interp_optimize(ctx, nir);
5195
5196 nir_foreach_variable(variable, &nir->inputs)
5197 handle_fs_input_decl(ctx, variable);
5198
5199 unsigned index = 0;
5200
5201 if (ctx->shader_info->info.ps.uses_input_attachments ||
5202 ctx->shader_info->info.needs_multiview_view_index)
5203 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5204
5205 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5206 LLVMValueRef interp_param;
5207 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5208
5209 if (!(ctx->input_mask & (1ull << i)))
5210 continue;
5211
5212 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5213 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5214 interp_param = *inputs;
5215 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5216 inputs);
5217
5218 if (!interp_param)
5219 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5220 ++index;
5221 } else if (i == VARYING_SLOT_POS) {
5222 for(int i = 0; i < 3; ++i)
5223 inputs[i] = ctx->abi.frag_pos[i];
5224
5225 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5226 ctx->abi.frag_pos[3]);
5227 }
5228 }
5229 ctx->shader_info->fs.num_interp = index;
5230 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5231 ctx->shader_info->fs.has_pcoord = true;
5232 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5233 ctx->shader_info->fs.prim_id_input = true;
5234 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5235 ctx->shader_info->fs.layer_input = true;
5236 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5237
5238 if (ctx->shader_info->info.needs_multiview_view_index)
5239 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5240 }
5241
5242 static LLVMValueRef
5243 ac_build_alloca(struct ac_llvm_context *ac,
5244 LLVMTypeRef type,
5245 const char *name)
5246 {
5247 LLVMBuilderRef builder = ac->builder;
5248 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5249 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5250 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5251 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5252 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5253 LLVMValueRef res;
5254
5255 if (first_instr) {
5256 LLVMPositionBuilderBefore(first_builder, first_instr);
5257 } else {
5258 LLVMPositionBuilderAtEnd(first_builder, first_block);
5259 }
5260
5261 res = LLVMBuildAlloca(first_builder, type, name);
5262 LLVMBuildStore(builder, LLVMConstNull(type), res);
5263
5264 LLVMDisposeBuilder(first_builder);
5265
5266 return res;
5267 }
5268
5269 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5270 LLVMTypeRef type,
5271 const char *name)
5272 {
5273 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5274 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5275 return ptr;
5276 }
5277
5278 static void
5279 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5280 struct nir_variable *variable,
5281 struct nir_shader *shader,
5282 gl_shader_stage stage)
5283 {
5284 int idx = variable->data.location + variable->data.index;
5285 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5286 uint64_t mask_attribs;
5287
5288 variable->data.driver_location = idx * 4;
5289
5290 /* tess ctrl has it's own load/store paths for outputs */
5291 if (stage == MESA_SHADER_TESS_CTRL)
5292 return;
5293
5294 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5295 if (stage == MESA_SHADER_VERTEX ||
5296 stage == MESA_SHADER_TESS_EVAL ||
5297 stage == MESA_SHADER_GEOMETRY) {
5298 if (idx == VARYING_SLOT_CLIP_DIST0) {
5299 int length = shader->info.clip_distance_array_size +
5300 shader->info.cull_distance_array_size;
5301 if (stage == MESA_SHADER_VERTEX) {
5302 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5303 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5304 }
5305 if (stage == MESA_SHADER_TESS_EVAL) {
5306 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5307 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5308 }
5309
5310 if (length > 4)
5311 attrib_count = 2;
5312 else
5313 attrib_count = 1;
5314 mask_attribs = 1ull << idx;
5315 }
5316 }
5317
5318 ctx->output_mask |= mask_attribs;
5319 }
5320
5321 static void
5322 handle_shader_output_decl(struct ac_nir_context *ctx,
5323 struct nir_shader *nir,
5324 struct nir_variable *variable)
5325 {
5326 unsigned output_loc = variable->data.driver_location / 4;
5327 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5328
5329 /* tess ctrl has it's own load/store paths for outputs */
5330 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5331 return;
5332
5333 if (ctx->stage == MESA_SHADER_VERTEX ||
5334 ctx->stage == MESA_SHADER_TESS_EVAL ||
5335 ctx->stage == MESA_SHADER_GEOMETRY) {
5336 int idx = variable->data.location + variable->data.index;
5337 if (idx == VARYING_SLOT_CLIP_DIST0) {
5338 int length = nir->info.clip_distance_array_size +
5339 nir->info.cull_distance_array_size;
5340
5341 if (length > 4)
5342 attrib_count = 2;
5343 else
5344 attrib_count = 1;
5345 }
5346 }
5347
5348 for (unsigned i = 0; i < attrib_count; ++i) {
5349 for (unsigned chan = 0; chan < 4; chan++) {
5350 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5351 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5352 }
5353 }
5354 }
5355
5356 static LLVMTypeRef
5357 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5358 enum glsl_base_type type)
5359 {
5360 switch (type) {
5361 case GLSL_TYPE_INT:
5362 case GLSL_TYPE_UINT:
5363 case GLSL_TYPE_BOOL:
5364 case GLSL_TYPE_SUBROUTINE:
5365 return ctx->ac.i32;
5366 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5367 return ctx->ac.f32;
5368 case GLSL_TYPE_INT64:
5369 case GLSL_TYPE_UINT64:
5370 return ctx->ac.i64;
5371 case GLSL_TYPE_DOUBLE:
5372 return ctx->ac.f64;
5373 default:
5374 unreachable("unknown GLSL type");
5375 }
5376 }
5377
5378 static LLVMTypeRef
5379 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5380 const struct glsl_type *type)
5381 {
5382 if (glsl_type_is_scalar(type)) {
5383 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5384 }
5385
5386 if (glsl_type_is_vector(type)) {
5387 return LLVMVectorType(
5388 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5389 glsl_get_vector_elements(type));
5390 }
5391
5392 if (glsl_type_is_matrix(type)) {
5393 return LLVMArrayType(
5394 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5395 glsl_get_matrix_columns(type));
5396 }
5397
5398 if (glsl_type_is_array(type)) {
5399 return LLVMArrayType(
5400 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5401 glsl_get_length(type));
5402 }
5403
5404 assert(glsl_type_is_struct(type));
5405
5406 LLVMTypeRef member_types[glsl_get_length(type)];
5407
5408 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5409 member_types[i] =
5410 glsl_to_llvm_type(ctx,
5411 glsl_get_struct_field(type, i));
5412 }
5413
5414 return LLVMStructTypeInContext(ctx->context, member_types,
5415 glsl_get_length(type), false);
5416 }
5417
5418 static void
5419 setup_locals(struct ac_nir_context *ctx,
5420 struct nir_function *func)
5421 {
5422 int i, j;
5423 ctx->num_locals = 0;
5424 nir_foreach_variable(variable, &func->impl->locals) {
5425 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5426 variable->data.driver_location = ctx->num_locals * 4;
5427 ctx->num_locals += attrib_count;
5428 }
5429 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5430 if (!ctx->locals)
5431 return;
5432
5433 for (i = 0; i < ctx->num_locals; i++) {
5434 for (j = 0; j < 4; j++) {
5435 ctx->locals[i * 4 + j] =
5436 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5437 }
5438 }
5439 }
5440
5441 static void
5442 setup_shared(struct ac_nir_context *ctx,
5443 struct nir_shader *nir)
5444 {
5445 nir_foreach_variable(variable, &nir->shared) {
5446 LLVMValueRef shared =
5447 LLVMAddGlobalInAddressSpace(
5448 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5449 variable->name ? variable->name : "",
5450 LOCAL_ADDR_SPACE);
5451 _mesa_hash_table_insert(ctx->vars, variable, shared);
5452 }
5453 }
5454
5455 static LLVMValueRef
5456 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5457 {
5458 v = ac_to_float(ctx, v);
5459 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5460 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5461 }
5462
5463
5464 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5465 LLVMValueRef src0, LLVMValueRef src1)
5466 {
5467 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5468 LLVMValueRef comp[2];
5469
5470 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5471 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5472 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5473 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5474 }
5475
5476 /* Initialize arguments for the shader export intrinsic */
5477 static void
5478 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5479 LLVMValueRef *values,
5480 unsigned target,
5481 struct ac_export_args *args)
5482 {
5483 /* Default is 0xf. Adjusted below depending on the format. */
5484 args->enabled_channels = 0xf;
5485
5486 /* Specify whether the EXEC mask represents the valid mask */
5487 args->valid_mask = 0;
5488
5489 /* Specify whether this is the last export */
5490 args->done = 0;
5491
5492 /* Specify the target we are exporting */
5493 args->target = target;
5494
5495 args->compr = false;
5496 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5497 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5498 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5499 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5500
5501 if (!values)
5502 return;
5503
5504 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5505 LLVMValueRef val[4];
5506 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5507 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5508 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5509 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5510
5511 switch(col_format) {
5512 case V_028714_SPI_SHADER_ZERO:
5513 args->enabled_channels = 0; /* writemask */
5514 args->target = V_008DFC_SQ_EXP_NULL;
5515 break;
5516
5517 case V_028714_SPI_SHADER_32_R:
5518 args->enabled_channels = 1;
5519 args->out[0] = values[0];
5520 break;
5521
5522 case V_028714_SPI_SHADER_32_GR:
5523 args->enabled_channels = 0x3;
5524 args->out[0] = values[0];
5525 args->out[1] = values[1];
5526 break;
5527
5528 case V_028714_SPI_SHADER_32_AR:
5529 args->enabled_channels = 0x9;
5530 args->out[0] = values[0];
5531 args->out[3] = values[3];
5532 break;
5533
5534 case V_028714_SPI_SHADER_FP16_ABGR:
5535 args->compr = 1;
5536
5537 for (unsigned chan = 0; chan < 2; chan++) {
5538 LLVMValueRef pack_args[2] = {
5539 values[2 * chan],
5540 values[2 * chan + 1]
5541 };
5542 LLVMValueRef packed;
5543
5544 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5545 args->out[chan] = packed;
5546 }
5547 break;
5548
5549 case V_028714_SPI_SHADER_UNORM16_ABGR:
5550 for (unsigned chan = 0; chan < 4; chan++) {
5551 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5552 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5553 LLVMConstReal(ctx->ac.f32, 65535), "");
5554 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5555 LLVMConstReal(ctx->ac.f32, 0.5), "");
5556 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5557 ctx->ac.i32, "");
5558 }
5559
5560 args->compr = 1;
5561 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5562 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5563 break;
5564
5565 case V_028714_SPI_SHADER_SNORM16_ABGR:
5566 for (unsigned chan = 0; chan < 4; chan++) {
5567 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5568 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5569 LLVMConstReal(ctx->ac.f32, 32767), "");
5570
5571 /* If positive, add 0.5, else add -0.5. */
5572 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5573 LLVMBuildSelect(ctx->builder,
5574 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5575 val[chan], ctx->ac.f32_0, ""),
5576 LLVMConstReal(ctx->ac.f32, 0.5),
5577 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5578 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5579 }
5580
5581 args->compr = 1;
5582 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5583 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5584 break;
5585
5586 case V_028714_SPI_SHADER_UINT16_ABGR: {
5587 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5588 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5589 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5590
5591 for (unsigned chan = 0; chan < 4; chan++) {
5592 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5593 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5594 }
5595
5596 args->compr = 1;
5597 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5598 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5599 break;
5600 }
5601
5602 case V_028714_SPI_SHADER_SINT16_ABGR: {
5603 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5604 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5605 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5606 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5607 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5608 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5609
5610 /* Clamp. */
5611 for (unsigned chan = 0; chan < 4; chan++) {
5612 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5613 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5614 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5615 }
5616
5617 args->compr = 1;
5618 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5619 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5620 break;
5621 }
5622
5623 default:
5624 case V_028714_SPI_SHADER_32_ABGR:
5625 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5626 break;
5627 }
5628 } else
5629 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5630
5631 for (unsigned i = 0; i < 4; ++i)
5632 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5633 }
5634
5635 static void
5636 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5637 bool export_prim_id,
5638 struct ac_vs_output_info *outinfo)
5639 {
5640 uint32_t param_count = 0;
5641 unsigned target;
5642 unsigned pos_idx, num_pos_exports = 0;
5643 struct ac_export_args args, pos_args[4] = {};
5644 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5645 int i;
5646
5647 if (ctx->options->key.has_multiview_view_index) {
5648 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5649 if(!*tmp_out) {
5650 for(unsigned i = 0; i < 4; ++i)
5651 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5652 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5653 }
5654
5655 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5656 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5657 }
5658
5659 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5660 sizeof(outinfo->vs_output_param_offset));
5661
5662 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5663 LLVMValueRef slots[8];
5664 unsigned j;
5665
5666 if (outinfo->cull_dist_mask)
5667 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5668
5669 i = VARYING_SLOT_CLIP_DIST0;
5670 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5671 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5672 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5673
5674 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5675 slots[i] = LLVMGetUndef(ctx->ac.f32);
5676
5677 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5678 target = V_008DFC_SQ_EXP_POS + 3;
5679 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5680 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5681 &args, sizeof(args));
5682 }
5683
5684 target = V_008DFC_SQ_EXP_POS + 2;
5685 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5686 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5687 &args, sizeof(args));
5688
5689 }
5690
5691 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5692 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5693 for (unsigned j = 0; j < 4; j++)
5694 pos_values[j] = LLVMBuildLoad(ctx->builder,
5695 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5696 }
5697 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5698
5699 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5700 outinfo->writes_pointsize = true;
5701 psize_value = LLVMBuildLoad(ctx->builder,
5702 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5703 }
5704
5705 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5706 outinfo->writes_layer = true;
5707 layer_value = LLVMBuildLoad(ctx->builder,
5708 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5709 }
5710
5711 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5712 outinfo->writes_viewport_index = true;
5713 viewport_index_value = LLVMBuildLoad(ctx->builder,
5714 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5715 }
5716
5717 if (outinfo->writes_pointsize ||
5718 outinfo->writes_layer ||
5719 outinfo->writes_viewport_index) {
5720 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5721 (outinfo->writes_layer == true ? 4 : 0));
5722 pos_args[1].valid_mask = 0;
5723 pos_args[1].done = 0;
5724 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5725 pos_args[1].compr = 0;
5726 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5727 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5728 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5729 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5730
5731 if (outinfo->writes_pointsize == true)
5732 pos_args[1].out[0] = psize_value;
5733 if (outinfo->writes_layer == true)
5734 pos_args[1].out[2] = layer_value;
5735 if (outinfo->writes_viewport_index == true) {
5736 if (ctx->options->chip_class >= GFX9) {
5737 /* GFX9 has the layer in out.z[10:0] and the viewport
5738 * index in out.z[19:16].
5739 */
5740 LLVMValueRef v = viewport_index_value;
5741 v = ac_to_integer(&ctx->ac, v);
5742 v = LLVMBuildShl(ctx->builder, v,
5743 LLVMConstInt(ctx->ac.i32, 16, false),
5744 "");
5745 v = LLVMBuildOr(ctx->builder, v,
5746 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5747
5748 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5749 pos_args[1].enabled_channels |= 1 << 2;
5750 } else {
5751 pos_args[1].out[3] = viewport_index_value;
5752 pos_args[1].enabled_channels |= 1 << 3;
5753 }
5754 }
5755 }
5756 for (i = 0; i < 4; i++) {
5757 if (pos_args[i].out[0])
5758 num_pos_exports++;
5759 }
5760
5761 pos_idx = 0;
5762 for (i = 0; i < 4; i++) {
5763 if (!pos_args[i].out[0])
5764 continue;
5765
5766 /* Specify the target we are exporting */
5767 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5768 if (pos_idx == num_pos_exports)
5769 pos_args[i].done = 1;
5770 ac_build_export(&ctx->ac, &pos_args[i]);
5771 }
5772
5773 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5774 LLVMValueRef values[4];
5775 if (!(ctx->output_mask & (1ull << i)))
5776 continue;
5777
5778 for (unsigned j = 0; j < 4; j++)
5779 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5780 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5781
5782 if (i == VARYING_SLOT_LAYER) {
5783 target = V_008DFC_SQ_EXP_PARAM + param_count;
5784 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5785 param_count++;
5786 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5787 target = V_008DFC_SQ_EXP_PARAM + param_count;
5788 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5789 param_count++;
5790 } else if (i >= VARYING_SLOT_VAR0) {
5791 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5792 target = V_008DFC_SQ_EXP_PARAM + param_count;
5793 outinfo->vs_output_param_offset[i] = param_count;
5794 param_count++;
5795 } else
5796 continue;
5797
5798 si_llvm_init_export_args(ctx, values, target, &args);
5799
5800 if (target >= V_008DFC_SQ_EXP_POS &&
5801 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5802 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5803 &args, sizeof(args));
5804 } else {
5805 ac_build_export(&ctx->ac, &args);
5806 }
5807 }
5808
5809 if (export_prim_id) {
5810 LLVMValueRef values[4];
5811 target = V_008DFC_SQ_EXP_PARAM + param_count;
5812 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5813 param_count++;
5814
5815 values[0] = ctx->vs_prim_id;
5816 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5817 ctx->shader_info->vs.vgpr_comp_cnt);
5818 for (unsigned j = 1; j < 4; j++)
5819 values[j] = ctx->ac.f32_0;
5820 si_llvm_init_export_args(ctx, values, target, &args);
5821 ac_build_export(&ctx->ac, &args);
5822 outinfo->export_prim_id = true;
5823 }
5824
5825 outinfo->pos_exports = num_pos_exports;
5826 outinfo->param_exports = param_count;
5827 }
5828
5829 static void
5830 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5831 struct ac_es_output_info *outinfo)
5832 {
5833 int j;
5834 uint64_t max_output_written = 0;
5835 LLVMValueRef lds_base = NULL;
5836
5837 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5838 int param_index;
5839 int length = 4;
5840
5841 if (!(ctx->output_mask & (1ull << i)))
5842 continue;
5843
5844 if (i == VARYING_SLOT_CLIP_DIST0)
5845 length = ctx->num_output_clips + ctx->num_output_culls;
5846
5847 param_index = shader_io_get_unique_index(i);
5848
5849 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5850 }
5851
5852 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5853
5854 if (ctx->ac.chip_class >= GFX9) {
5855 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5856 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5857 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5858 LLVMConstInt(ctx->ac.i32, 24, false),
5859 LLVMConstInt(ctx->ac.i32, 4, false), false);
5860 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5861 LLVMBuildMul(ctx->ac.builder, wave_idx,
5862 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5863 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5864 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5865 }
5866
5867 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5868 LLVMValueRef dw_addr;
5869 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5870 int param_index;
5871 int length = 4;
5872
5873 if (!(ctx->output_mask & (1ull << i)))
5874 continue;
5875
5876 if (i == VARYING_SLOT_CLIP_DIST0)
5877 length = ctx->num_output_clips + ctx->num_output_culls;
5878
5879 param_index = shader_io_get_unique_index(i);
5880
5881 if (lds_base) {
5882 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5883 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5884 "");
5885 }
5886 for (j = 0; j < length; j++) {
5887 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5888 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5889
5890 if (ctx->ac.chip_class >= GFX9) {
5891 ac_lds_store(&ctx->ac, dw_addr,
5892 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5893 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5894 } else {
5895 ac_build_buffer_store_dword(&ctx->ac,
5896 ctx->esgs_ring,
5897 out_val, 1,
5898 NULL, ctx->es2gs_offset,
5899 (4 * param_index + j) * 4,
5900 1, 1, true, true);
5901 }
5902 }
5903 }
5904 }
5905
5906 static void
5907 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5908 {
5909 LLVMValueRef vertex_id = ctx->rel_auto_id;
5910 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5911 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5912 vertex_dw_stride, "");
5913
5914 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5915 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5916 int length = 4;
5917
5918 if (!(ctx->output_mask & (1ull << i)))
5919 continue;
5920
5921 if (i == VARYING_SLOT_CLIP_DIST0)
5922 length = ctx->num_output_clips + ctx->num_output_culls;
5923 int param = shader_io_get_unique_index(i);
5924 mark_tess_output(ctx, false, param);
5925 if (length > 4)
5926 mark_tess_output(ctx, false, param + 1);
5927 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5928 LLVMConstInt(ctx->ac.i32, param * 4, false),
5929 "");
5930 for (unsigned j = 0; j < length; j++) {
5931 ac_lds_store(&ctx->ac, dw_addr,
5932 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5933 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5934 }
5935 }
5936 }
5937
5938 struct ac_build_if_state
5939 {
5940 struct nir_to_llvm_context *ctx;
5941 LLVMValueRef condition;
5942 LLVMBasicBlockRef entry_block;
5943 LLVMBasicBlockRef true_block;
5944 LLVMBasicBlockRef false_block;
5945 LLVMBasicBlockRef merge_block;
5946 };
5947
5948 static LLVMBasicBlockRef
5949 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5950 {
5951 LLVMBasicBlockRef current_block;
5952 LLVMBasicBlockRef next_block;
5953 LLVMBasicBlockRef new_block;
5954
5955 /* get current basic block */
5956 current_block = LLVMGetInsertBlock(ctx->builder);
5957
5958 /* chqeck if there's another block after this one */
5959 next_block = LLVMGetNextBasicBlock(current_block);
5960 if (next_block) {
5961 /* insert the new block before the next block */
5962 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5963 }
5964 else {
5965 /* append new block after current block */
5966 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5967 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5968 }
5969 return new_block;
5970 }
5971
5972 static void
5973 ac_nir_build_if(struct ac_build_if_state *ifthen,
5974 struct nir_to_llvm_context *ctx,
5975 LLVMValueRef condition)
5976 {
5977 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5978
5979 memset(ifthen, 0, sizeof *ifthen);
5980 ifthen->ctx = ctx;
5981 ifthen->condition = condition;
5982 ifthen->entry_block = block;
5983
5984 /* create endif/merge basic block for the phi functions */
5985 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5986
5987 /* create/insert true_block before merge_block */
5988 ifthen->true_block =
5989 LLVMInsertBasicBlockInContext(ctx->context,
5990 ifthen->merge_block,
5991 "if-true-block");
5992
5993 /* successive code goes into the true block */
5994 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5995 }
5996
5997 /**
5998 * End a conditional.
5999 */
6000 static void
6001 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6002 {
6003 LLVMBuilderRef builder = ifthen->ctx->builder;
6004
6005 /* Insert branch to the merge block from current block */
6006 LLVMBuildBr(builder, ifthen->merge_block);
6007
6008 /*
6009 * Now patch in the various branch instructions.
6010 */
6011
6012 /* Insert the conditional branch instruction at the end of entry_block */
6013 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6014 if (ifthen->false_block) {
6015 /* we have an else clause */
6016 LLVMBuildCondBr(builder, ifthen->condition,
6017 ifthen->true_block, ifthen->false_block);
6018 }
6019 else {
6020 /* no else clause */
6021 LLVMBuildCondBr(builder, ifthen->condition,
6022 ifthen->true_block, ifthen->merge_block);
6023 }
6024
6025 /* Resume building code at end of the ifthen->merge_block */
6026 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6027 }
6028
6029 static void
6030 write_tess_factors(struct nir_to_llvm_context *ctx)
6031 {
6032 unsigned stride, outer_comps, inner_comps;
6033 struct ac_build_if_state if_ctx, inner_if_ctx;
6034 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6035 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6036 unsigned tess_inner_index, tess_outer_index;
6037 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6038 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6039 int i;
6040 emit_barrier(ctx);
6041
6042 switch (ctx->options->key.tcs.primitive_mode) {
6043 case GL_ISOLINES:
6044 stride = 2;
6045 outer_comps = 2;
6046 inner_comps = 0;
6047 break;
6048 case GL_TRIANGLES:
6049 stride = 4;
6050 outer_comps = 3;
6051 inner_comps = 1;
6052 break;
6053 case GL_QUADS:
6054 stride = 6;
6055 outer_comps = 4;
6056 inner_comps = 2;
6057 break;
6058 default:
6059 return;
6060 }
6061
6062 ac_nir_build_if(&if_ctx, ctx,
6063 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6064 invocation_id, ctx->ac.i32_0, ""));
6065
6066 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6067 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6068
6069 mark_tess_output(ctx, true, tess_inner_index);
6070 mark_tess_output(ctx, true, tess_outer_index);
6071 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6072 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6073 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6074 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6075 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6076
6077 for (i = 0; i < 4; i++) {
6078 inner[i] = LLVMGetUndef(ctx->ac.i32);
6079 outer[i] = LLVMGetUndef(ctx->ac.i32);
6080 }
6081
6082 // LINES reverseal
6083 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6084 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6085 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6086 LLVMConstInt(ctx->ac.i32, 1, false), "");
6087 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6088 } else {
6089 for (i = 0; i < outer_comps; i++) {
6090 outer[i] = out[i] =
6091 ac_lds_load(&ctx->ac, lds_outer);
6092 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6093 LLVMConstInt(ctx->ac.i32, 1, false), "");
6094 }
6095 for (i = 0; i < inner_comps; i++) {
6096 inner[i] = out[outer_comps+i] =
6097 ac_lds_load(&ctx->ac, lds_inner);
6098 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6099 LLVMConstInt(ctx->ac.i32, 1, false), "");
6100 }
6101 }
6102
6103 /* Convert the outputs to vectors for stores. */
6104 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6105 vec1 = NULL;
6106
6107 if (stride > 4)
6108 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6109
6110
6111 buffer = ctx->hs_ring_tess_factor;
6112 tf_base = ctx->tess_factor_offset;
6113 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6114 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6115 unsigned tf_offset = 0;
6116
6117 if (ctx->options->chip_class <= VI) {
6118 ac_nir_build_if(&inner_if_ctx, ctx,
6119 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6120 rel_patch_id, ctx->ac.i32_0, ""));
6121
6122 /* Store the dynamic HS control word. */
6123 ac_build_buffer_store_dword(&ctx->ac, buffer,
6124 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6125 1, ctx->ac.i32_0, tf_base,
6126 0, 1, 0, true, false);
6127 tf_offset += 4;
6128
6129 ac_nir_build_endif(&inner_if_ctx);
6130 }
6131
6132 /* Store the tessellation factors. */
6133 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6134 MIN2(stride, 4), byteoffset, tf_base,
6135 tf_offset, 1, 0, true, false);
6136 if (vec1)
6137 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6138 stride - 4, byteoffset, tf_base,
6139 16 + tf_offset, 1, 0, true, false);
6140
6141 //store to offchip for TES to read - only if TES reads them
6142 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6143 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6144 LLVMValueRef tf_inner_offset;
6145 unsigned param_outer, param_inner;
6146
6147 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6148 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6149 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6150
6151 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6152 util_next_power_of_two(outer_comps));
6153
6154 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6155 outer_comps, tf_outer_offset,
6156 ctx->oc_lds, 0, 1, 0, true, false);
6157 if (inner_comps) {
6158 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6159 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6160 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6161
6162 inner_vec = inner_comps == 1 ? inner[0] :
6163 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6164 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6165 inner_comps, tf_inner_offset,
6166 ctx->oc_lds, 0, 1, 0, true, false);
6167 }
6168 }
6169 ac_nir_build_endif(&if_ctx);
6170 }
6171
6172 static void
6173 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6174 {
6175 write_tess_factors(ctx);
6176 }
6177
6178 static bool
6179 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6180 LLVMValueRef *color, unsigned param, bool is_last,
6181 struct ac_export_args *args)
6182 {
6183 /* Export */
6184 si_llvm_init_export_args(ctx, color, param,
6185 args);
6186
6187 if (is_last) {
6188 args->valid_mask = 1; /* whether the EXEC mask is valid */
6189 args->done = 1; /* DONE bit */
6190 } else if (!args->enabled_channels)
6191 return false; /* unnecessary NULL export */
6192
6193 return true;
6194 }
6195
6196 static void
6197 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6198 LLVMValueRef depth, LLVMValueRef stencil,
6199 LLVMValueRef samplemask)
6200 {
6201 struct ac_export_args args;
6202
6203 args.enabled_channels = 0;
6204 args.valid_mask = 1;
6205 args.done = 1;
6206 args.target = V_008DFC_SQ_EXP_MRTZ;
6207 args.compr = false;
6208
6209 args.out[0] = LLVMGetUndef(ctx->ac.f32); /* R, depth */
6210 args.out[1] = LLVMGetUndef(ctx->ac.f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6211 args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */
6212 args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */
6213
6214 if (depth) {
6215 args.out[0] = depth;
6216 args.enabled_channels |= 0x1;
6217 }
6218
6219 if (stencil) {
6220 args.out[1] = stencil;
6221 args.enabled_channels |= 0x2;
6222 }
6223
6224 if (samplemask) {
6225 args.out[2] = samplemask;
6226 args.enabled_channels |= 0x4;
6227 }
6228
6229 /* SI (except OLAND and HAINAN) has a bug that it only looks
6230 * at the X writemask component. */
6231 if (ctx->options->chip_class == SI &&
6232 ctx->options->family != CHIP_OLAND &&
6233 ctx->options->family != CHIP_HAINAN)
6234 args.enabled_channels |= 0x1;
6235
6236 ac_build_export(&ctx->ac, &args);
6237 }
6238
6239 static void
6240 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6241 {
6242 unsigned index = 0;
6243 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6244 struct ac_export_args color_args[8];
6245
6246 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6247 LLVMValueRef values[4];
6248
6249 if (!(ctx->output_mask & (1ull << i)))
6250 continue;
6251
6252 if (i == FRAG_RESULT_DEPTH) {
6253 ctx->shader_info->fs.writes_z = true;
6254 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6255 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6256 } else if (i == FRAG_RESULT_STENCIL) {
6257 ctx->shader_info->fs.writes_stencil = true;
6258 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6259 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6260 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6261 ctx->shader_info->fs.writes_sample_mask = true;
6262 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6263 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6264 } else {
6265 bool last = false;
6266 for (unsigned j = 0; j < 4; j++)
6267 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6268 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6269
6270 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6271 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6272
6273 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6274 if (ret)
6275 index++;
6276 }
6277 }
6278
6279 for (unsigned i = 0; i < index; i++)
6280 ac_build_export(&ctx->ac, &color_args[i]);
6281 if (depth || stencil || samplemask)
6282 si_export_mrt_z(ctx, depth, stencil, samplemask);
6283 else if (!index) {
6284 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6285 ac_build_export(&ctx->ac, &color_args[0]);
6286 }
6287
6288 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6289 }
6290
6291 static void
6292 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6293 {
6294 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6295 }
6296
6297 static void
6298 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6299 LLVMValueRef *addrs)
6300 {
6301 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6302
6303 switch (ctx->stage) {
6304 case MESA_SHADER_VERTEX:
6305 if (ctx->options->key.vs.as_ls)
6306 handle_ls_outputs_post(ctx);
6307 else if (ctx->options->key.vs.as_es)
6308 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6309 else
6310 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6311 &ctx->shader_info->vs.outinfo);
6312 break;
6313 case MESA_SHADER_FRAGMENT:
6314 handle_fs_outputs_post(ctx);
6315 break;
6316 case MESA_SHADER_GEOMETRY:
6317 emit_gs_epilogue(ctx);
6318 break;
6319 case MESA_SHADER_TESS_CTRL:
6320 handle_tcs_outputs_post(ctx);
6321 break;
6322 case MESA_SHADER_TESS_EVAL:
6323 if (ctx->options->key.tes.as_es)
6324 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6325 else
6326 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6327 &ctx->shader_info->tes.outinfo);
6328 break;
6329 default:
6330 break;
6331 }
6332 }
6333
6334 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6335 {
6336 LLVMPassManagerRef passmgr;
6337 /* Create the pass manager */
6338 passmgr = LLVMCreateFunctionPassManagerForModule(
6339 ctx->module);
6340
6341 /* This pass should eliminate all the load and store instructions */
6342 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6343
6344 /* Add some optimization passes */
6345 LLVMAddScalarReplAggregatesPass(passmgr);
6346 LLVMAddLICMPass(passmgr);
6347 LLVMAddAggressiveDCEPass(passmgr);
6348 LLVMAddCFGSimplificationPass(passmgr);
6349 LLVMAddInstructionCombiningPass(passmgr);
6350
6351 /* Run the pass */
6352 LLVMInitializeFunctionPassManager(passmgr);
6353 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6354 LLVMFinalizeFunctionPassManager(passmgr);
6355
6356 LLVMDisposeBuilder(ctx->builder);
6357 LLVMDisposePassManager(passmgr);
6358 }
6359
6360 static void
6361 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6362 {
6363 struct ac_vs_output_info *outinfo;
6364
6365 switch (ctx->stage) {
6366 case MESA_SHADER_FRAGMENT:
6367 case MESA_SHADER_COMPUTE:
6368 case MESA_SHADER_TESS_CTRL:
6369 case MESA_SHADER_GEOMETRY:
6370 return;
6371 case MESA_SHADER_VERTEX:
6372 if (ctx->options->key.vs.as_ls ||
6373 ctx->options->key.vs.as_es)
6374 return;
6375 outinfo = &ctx->shader_info->vs.outinfo;
6376 break;
6377 case MESA_SHADER_TESS_EVAL:
6378 if (ctx->options->key.vs.as_es)
6379 return;
6380 outinfo = &ctx->shader_info->tes.outinfo;
6381 break;
6382 default:
6383 unreachable("Unhandled shader type");
6384 }
6385
6386 ac_optimize_vs_outputs(&ctx->ac,
6387 ctx->main_function,
6388 outinfo->vs_output_param_offset,
6389 VARYING_SLOT_MAX,
6390 &outinfo->param_exports);
6391 }
6392
6393 static void
6394 ac_setup_rings(struct nir_to_llvm_context *ctx)
6395 {
6396 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6397 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6398 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6399 }
6400
6401 if (ctx->is_gs_copy_shader) {
6402 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6403 }
6404 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6405 LLVMValueRef tmp;
6406 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6407 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6408
6409 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6410
6411 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6412 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6413 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6414 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6415 }
6416
6417 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6418 ctx->stage == MESA_SHADER_TESS_EVAL) {
6419 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6420 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6421 }
6422 }
6423
6424 static unsigned
6425 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6426 const struct nir_shader *nir)
6427 {
6428 switch (nir->info.stage) {
6429 case MESA_SHADER_TESS_CTRL:
6430 return chip_class >= CIK ? 128 : 64;
6431 case MESA_SHADER_GEOMETRY:
6432 return chip_class >= GFX9 ? 128 : 64;
6433 case MESA_SHADER_COMPUTE:
6434 break;
6435 default:
6436 return 0;
6437 }
6438
6439 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6440 nir->info.cs.local_size[1] *
6441 nir->info.cs.local_size[2];
6442 return max_workgroup_size;
6443 }
6444
6445 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6446 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6447 {
6448 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6449 LLVMConstInt(ctx->ac.i32, 8, false),
6450 LLVMConstInt(ctx->ac.i32, 8, false), false);
6451 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6452 LLVMConstInt(ctx->ac.i32, 0, false), "");
6453 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6454 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6455 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6456 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6457 }
6458
6459 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6460 {
6461 for(int i = 5; i >= 0; --i) {
6462 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6463 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6464 LLVMConstInt(ctx->ac.i32, 16, false), false);
6465 }
6466
6467 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6468 LLVMConstInt(ctx->ac.i32, 16, false),
6469 LLVMConstInt(ctx->ac.i32, 8, false), false);
6470 }
6471
6472 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6473 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6474 {
6475 struct ac_nir_context ctx = {};
6476 struct nir_function *func;
6477
6478 ctx.ac = *ac;
6479 ctx.abi = abi;
6480
6481 ctx.nctx = nctx;
6482 if (nctx)
6483 nctx->nir = &ctx;
6484
6485 ctx.stage = nir->info.stage;
6486
6487 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6488
6489 nir_foreach_variable(variable, &nir->outputs)
6490 handle_shader_output_decl(&ctx, nir, variable);
6491
6492 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6493 _mesa_key_pointer_equal);
6494 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6495 _mesa_key_pointer_equal);
6496 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6497 _mesa_key_pointer_equal);
6498
6499 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6500
6501 setup_locals(&ctx, func);
6502
6503 if (nir->info.stage == MESA_SHADER_COMPUTE)
6504 setup_shared(&ctx, nir);
6505
6506 visit_cf_list(&ctx, &func->impl->body);
6507 phi_post_pass(&ctx);
6508
6509 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6510 ctx.outputs);
6511
6512 free(ctx.locals);
6513 ralloc_free(ctx.defs);
6514 ralloc_free(ctx.phis);
6515 ralloc_free(ctx.vars);
6516
6517 if (nctx)
6518 nctx->nir = NULL;
6519 }
6520
6521 static
6522 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6523 struct nir_shader *const *shaders,
6524 int shader_count,
6525 struct ac_shader_variant_info *shader_info,
6526 const struct ac_nir_compiler_options *options)
6527 {
6528 struct nir_to_llvm_context ctx = {0};
6529 unsigned i;
6530 ctx.options = options;
6531 ctx.shader_info = shader_info;
6532 ctx.context = LLVMContextCreate();
6533 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6534
6535 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6536 ctx.ac.module = ctx.module;
6537 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6538
6539 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6540 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6541 LLVMSetDataLayout(ctx.module, data_layout_str);
6542 LLVMDisposeTargetData(data_layout);
6543 LLVMDisposeMessage(data_layout_str);
6544
6545 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6546 ctx.ac.builder = ctx.builder;
6547
6548 memset(shader_info, 0, sizeof(*shader_info));
6549
6550 for(int i = 0; i < shader_count; ++i)
6551 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6552
6553 for (i = 0; i < AC_UD_MAX_SETS; i++)
6554 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6555 for (i = 0; i < AC_UD_MAX_UD; i++)
6556 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6557
6558 ctx.max_workgroup_size = 0;
6559 for (int i = 0; i < shader_count; ++i) {
6560 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6561 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6562 shaders[i]));
6563 }
6564
6565 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6566 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6567
6568 ctx.abi.inputs = &ctx.inputs[0];
6569 ctx.abi.emit_outputs = handle_shader_outputs_post;
6570 ctx.abi.emit_vertex = visit_emit_vertex;
6571 ctx.abi.load_ubo = radv_load_ubo;
6572 ctx.abi.load_ssbo = radv_load_ssbo;
6573 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6574 ctx.abi.clamp_shadow_reference = false;
6575
6576 if (shader_count >= 2)
6577 ac_init_exec_full_mask(&ctx.ac);
6578
6579 if (ctx.ac.chip_class == GFX9 &&
6580 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6581 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6582
6583 for(int i = 0; i < shader_count; ++i) {
6584 ctx.stage = shaders[i]->info.stage;
6585 ctx.output_mask = 0;
6586 ctx.tess_outputs_written = 0;
6587 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6588 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6589
6590 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6591 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6592 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6593 ctx.abi.load_inputs = load_gs_input;
6594 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6595 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6596 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6597 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6598 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6599 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6600 if (shader_info->info.vs.needs_instance_id) {
6601 ctx.shader_info->vs.vgpr_comp_cnt =
6602 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6603 }
6604 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6605 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6606 }
6607
6608 if (i)
6609 emit_barrier(&ctx);
6610
6611 ac_setup_rings(&ctx);
6612
6613 LLVMBasicBlockRef merge_block;
6614 if (shader_count >= 2) {
6615 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6616 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6617 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6618
6619 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6620 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6621 LLVMConstInt(ctx.ac.i32, 8, false), false);
6622 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6623 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6624 thread_id, count, "");
6625 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6626
6627 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6628 }
6629
6630 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6631 handle_fs_inputs(&ctx, shaders[i]);
6632 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6633 handle_vs_inputs(&ctx, shaders[i]);
6634 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6635 prepare_gs_input_vgprs(&ctx);
6636
6637 nir_foreach_variable(variable, &shaders[i]->outputs)
6638 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6639
6640 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6641
6642 if (shader_count >= 2) {
6643 LLVMBuildBr(ctx.ac.builder, merge_block);
6644 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6645 }
6646
6647 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6648 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6649 shaders[i]->info.cull_distance_array_size > 4;
6650 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6651 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6652 shaders[i]->info.gs.vertices_out;
6653 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6654 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6655 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6656 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6657 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6658 }
6659 }
6660
6661 LLVMBuildRetVoid(ctx.builder);
6662
6663 ac_llvm_finalize_module(&ctx);
6664
6665 if (shader_count == 1)
6666 ac_nir_eliminate_const_vs_outputs(&ctx);
6667
6668 return ctx.module;
6669 }
6670
6671 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6672 {
6673 unsigned *retval = (unsigned *)context;
6674 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6675 char *description = LLVMGetDiagInfoDescription(di);
6676
6677 if (severity == LLVMDSError) {
6678 *retval = 1;
6679 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6680 description);
6681 }
6682
6683 LLVMDisposeMessage(description);
6684 }
6685
6686 static unsigned ac_llvm_compile(LLVMModuleRef M,
6687 struct ac_shader_binary *binary,
6688 LLVMTargetMachineRef tm)
6689 {
6690 unsigned retval = 0;
6691 char *err;
6692 LLVMContextRef llvm_ctx;
6693 LLVMMemoryBufferRef out_buffer;
6694 unsigned buffer_size;
6695 const char *buffer_data;
6696 LLVMBool mem_err;
6697
6698 /* Setup Diagnostic Handler*/
6699 llvm_ctx = LLVMGetModuleContext(M);
6700
6701 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6702 &retval);
6703
6704 /* Compile IR*/
6705 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6706 &err, &out_buffer);
6707
6708 /* Process Errors/Warnings */
6709 if (mem_err) {
6710 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6711 free(err);
6712 retval = 1;
6713 goto out;
6714 }
6715
6716 /* Extract Shader Code*/
6717 buffer_size = LLVMGetBufferSize(out_buffer);
6718 buffer_data = LLVMGetBufferStart(out_buffer);
6719
6720 ac_elf_read(buffer_data, buffer_size, binary);
6721
6722 /* Clean up */
6723 LLVMDisposeMemoryBuffer(out_buffer);
6724
6725 out:
6726 return retval;
6727 }
6728
6729 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6730 LLVMModuleRef llvm_module,
6731 struct ac_shader_binary *binary,
6732 struct ac_shader_config *config,
6733 struct ac_shader_variant_info *shader_info,
6734 gl_shader_stage stage,
6735 bool dump_shader, bool supports_spill)
6736 {
6737 if (dump_shader)
6738 ac_dump_module(llvm_module);
6739
6740 memset(binary, 0, sizeof(*binary));
6741 int v = ac_llvm_compile(llvm_module, binary, tm);
6742 if (v) {
6743 fprintf(stderr, "compile failed\n");
6744 }
6745
6746 if (dump_shader)
6747 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6748
6749 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6750
6751 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6752 LLVMDisposeModule(llvm_module);
6753 LLVMContextDispose(ctx);
6754
6755 if (stage == MESA_SHADER_FRAGMENT) {
6756 shader_info->num_input_vgprs = 0;
6757 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6758 shader_info->num_input_vgprs += 2;
6759 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6760 shader_info->num_input_vgprs += 2;
6761 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6762 shader_info->num_input_vgprs += 2;
6763 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6764 shader_info->num_input_vgprs += 3;
6765 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6766 shader_info->num_input_vgprs += 2;
6767 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6768 shader_info->num_input_vgprs += 2;
6769 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6770 shader_info->num_input_vgprs += 2;
6771 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6772 shader_info->num_input_vgprs += 1;
6773 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6774 shader_info->num_input_vgprs += 1;
6775 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6776 shader_info->num_input_vgprs += 1;
6777 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6778 shader_info->num_input_vgprs += 1;
6779 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6780 shader_info->num_input_vgprs += 1;
6781 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6782 shader_info->num_input_vgprs += 1;
6783 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6784 shader_info->num_input_vgprs += 1;
6785 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6786 shader_info->num_input_vgprs += 1;
6787 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6788 shader_info->num_input_vgprs += 1;
6789 }
6790 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6791
6792 /* +3 for scratch wave offset and VCC */
6793 config->num_sgprs = MAX2(config->num_sgprs,
6794 shader_info->num_input_sgprs + 3);
6795 }
6796
6797 static void
6798 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6799 {
6800 switch (nir->info.stage) {
6801 case MESA_SHADER_COMPUTE:
6802 for (int i = 0; i < 3; ++i)
6803 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6804 break;
6805 case MESA_SHADER_FRAGMENT:
6806 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6807 break;
6808 case MESA_SHADER_GEOMETRY:
6809 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6810 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6811 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6812 shader_info->gs.invocations = nir->info.gs.invocations;
6813 break;
6814 case MESA_SHADER_TESS_EVAL:
6815 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6816 shader_info->tes.spacing = nir->info.tess.spacing;
6817 shader_info->tes.ccw = nir->info.tess.ccw;
6818 shader_info->tes.point_mode = nir->info.tess.point_mode;
6819 shader_info->tes.as_es = options->key.tes.as_es;
6820 break;
6821 case MESA_SHADER_TESS_CTRL:
6822 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6823 break;
6824 case MESA_SHADER_VERTEX:
6825 shader_info->vs.as_es = options->key.vs.as_es;
6826 shader_info->vs.as_ls = options->key.vs.as_ls;
6827 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6828 if (options->key.vs.as_ls)
6829 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6830 break;
6831 default:
6832 break;
6833 }
6834 }
6835
6836 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6837 struct ac_shader_binary *binary,
6838 struct ac_shader_config *config,
6839 struct ac_shader_variant_info *shader_info,
6840 struct nir_shader *const *nir,
6841 int nir_count,
6842 const struct ac_nir_compiler_options *options,
6843 bool dump_shader)
6844 {
6845
6846 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6847 options);
6848
6849 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6850 for (int i = 0; i < nir_count; ++i)
6851 ac_fill_shader_info(shader_info, nir[i], options);
6852 }
6853
6854 static void
6855 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6856 {
6857 LLVMValueRef args[9];
6858 args[0] = ctx->gsvs_ring;
6859 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6860 args[3] = ctx->ac.i32_0;
6861 args[4] = ctx->ac.i32_1; /* OFFEN */
6862 args[5] = ctx->ac.i32_0; /* IDXEN */
6863 args[6] = ctx->ac.i32_1; /* GLC */
6864 args[7] = ctx->ac.i32_1; /* SLC */
6865 args[8] = ctx->ac.i32_0; /* TFE */
6866
6867 int idx = 0;
6868
6869 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6870 int length = 4;
6871 int slot = idx;
6872 int slot_inc = 1;
6873 if (!(ctx->output_mask & (1ull << i)))
6874 continue;
6875
6876 if (i == VARYING_SLOT_CLIP_DIST0) {
6877 /* unpack clip and cull from a single set of slots */
6878 length = ctx->num_output_clips + ctx->num_output_culls;
6879 if (length > 4)
6880 slot_inc = 2;
6881 }
6882
6883 for (unsigned j = 0; j < length; j++) {
6884 LLVMValueRef value;
6885 args[2] = LLVMConstInt(ctx->ac.i32,
6886 (slot * 4 + j) *
6887 ctx->gs_max_out_vertices * 16 * 4, false);
6888
6889 value = ac_build_intrinsic(&ctx->ac,
6890 "llvm.SI.buffer.load.dword.i32.i32",
6891 ctx->ac.i32, args, 9,
6892 AC_FUNC_ATTR_READONLY |
6893 AC_FUNC_ATTR_LEGACY);
6894
6895 LLVMBuildStore(ctx->builder,
6896 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6897 }
6898 idx += slot_inc;
6899 }
6900 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6901 }
6902
6903 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6904 struct nir_shader *geom_shader,
6905 struct ac_shader_binary *binary,
6906 struct ac_shader_config *config,
6907 struct ac_shader_variant_info *shader_info,
6908 const struct ac_nir_compiler_options *options,
6909 bool dump_shader)
6910 {
6911 struct nir_to_llvm_context ctx = {0};
6912 ctx.context = LLVMContextCreate();
6913 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6914 ctx.options = options;
6915 ctx.shader_info = shader_info;
6916
6917 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6918 ctx.ac.module = ctx.module;
6919
6920 ctx.is_gs_copy_shader = true;
6921 LLVMSetTarget(ctx.module, "amdgcn--");
6922
6923 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6924 ctx.ac.builder = ctx.builder;
6925 ctx.stage = MESA_SHADER_VERTEX;
6926
6927 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6928
6929 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6930 ac_setup_rings(&ctx);
6931
6932 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6933 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6934
6935 struct ac_nir_context nir_ctx = {};
6936 nir_ctx.ac = ctx.ac;
6937 nir_ctx.abi = &ctx.abi;
6938
6939 nir_ctx.nctx = &ctx;
6940 ctx.nir = &nir_ctx;
6941
6942 nir_foreach_variable(variable, &geom_shader->outputs) {
6943 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6944 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6945 }
6946
6947 ac_gs_copy_shader_emit(&ctx);
6948
6949 ctx.nir = NULL;
6950
6951 LLVMBuildRetVoid(ctx.builder);
6952
6953 ac_llvm_finalize_module(&ctx);
6954
6955 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6956 MESA_SHADER_VERTEX,
6957 dump_shader, options->supports_spill);
6958 }