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radv/ac: Implement Float64 SSBO stores.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_util.h"
26 #include "ac_binary.h"
27 #include "sid.h"
28 #include "nir/nir.h"
29 #include "../vulkan/radv_descriptor_set.h"
30 #include "util/bitscan.h"
31 #include <llvm-c/Transforms/Scalar.h>
32
33 enum radeon_llvm_calling_convention {
34 RADEON_LLVM_AMDGPU_VS = 87,
35 RADEON_LLVM_AMDGPU_GS = 88,
36 RADEON_LLVM_AMDGPU_PS = 89,
37 RADEON_LLVM_AMDGPU_CS = 90,
38 };
39
40 #define CONST_ADDR_SPACE 2
41 #define LOCAL_ADDR_SPACE 3
42
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
44 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
45
46 #define SENDMSG_GS 2
47 #define SENDMSG_GS_DONE 3
48
49 #define SENDMSG_GS_OP_NOP (0 << 4)
50 #define SENDMSG_GS_OP_CUT (1 << 4)
51 #define SENDMSG_GS_OP_EMIT (2 << 4)
52 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
53
54 enum desc_type {
55 DESC_IMAGE,
56 DESC_FMASK,
57 DESC_SAMPLER,
58 DESC_BUFFER,
59 };
60
61 struct nir_to_llvm_context {
62 struct ac_llvm_context ac;
63 const struct ac_nir_compiler_options *options;
64 struct ac_shader_variant_info *shader_info;
65
66 LLVMContextRef context;
67 LLVMModuleRef module;
68 LLVMBuilderRef builder;
69 LLVMValueRef main_function;
70
71 struct hash_table *defs;
72 struct hash_table *phis;
73
74 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
75 LLVMValueRef ring_offsets;
76 LLVMValueRef push_constants;
77 LLVMValueRef num_work_groups;
78 LLVMValueRef workgroup_ids;
79 LLVMValueRef local_invocation_ids;
80 LLVMValueRef tg_size;
81
82 LLVMValueRef vertex_buffers;
83 LLVMValueRef base_vertex;
84 LLVMValueRef start_instance;
85 LLVMValueRef vertex_id;
86 LLVMValueRef rel_auto_id;
87 LLVMValueRef vs_prim_id;
88 LLVMValueRef instance_id;
89
90 LLVMValueRef es2gs_offset;
91
92 LLVMValueRef gsvs_ring_stride;
93 LLVMValueRef gsvs_num_entries;
94 LLVMValueRef gs2vs_offset;
95 LLVMValueRef gs_wave_id;
96 LLVMValueRef gs_vtx_offset[6];
97 LLVMValueRef gs_prim_id, gs_invocation_id;
98
99 LLVMValueRef esgs_ring;
100 LLVMValueRef gsvs_ring;
101
102 LLVMValueRef prim_mask;
103 LLVMValueRef sample_positions;
104 LLVMValueRef persp_sample, persp_center, persp_centroid;
105 LLVMValueRef linear_sample, linear_center, linear_centroid;
106 LLVMValueRef front_face;
107 LLVMValueRef ancillary;
108 LLVMValueRef frag_pos[4];
109
110 LLVMBasicBlockRef continue_block;
111 LLVMBasicBlockRef break_block;
112
113 LLVMTypeRef i1;
114 LLVMTypeRef i8;
115 LLVMTypeRef i16;
116 LLVMTypeRef i32;
117 LLVMTypeRef i64;
118 LLVMTypeRef v2i32;
119 LLVMTypeRef v3i32;
120 LLVMTypeRef v4i32;
121 LLVMTypeRef v8i32;
122 LLVMTypeRef f64;
123 LLVMTypeRef f32;
124 LLVMTypeRef f16;
125 LLVMTypeRef v2f32;
126 LLVMTypeRef v4f32;
127 LLVMTypeRef v16i8;
128 LLVMTypeRef voidt;
129
130 LLVMValueRef i32zero;
131 LLVMValueRef i32one;
132 LLVMValueRef f32zero;
133 LLVMValueRef f32one;
134 LLVMValueRef v4f32empty;
135
136 unsigned range_md_kind;
137 unsigned uniform_md_kind;
138 unsigned invariant_load_md_kind;
139 LLVMValueRef empty_md;
140 gl_shader_stage stage;
141
142 LLVMValueRef lds;
143 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
144 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
145
146 LLVMValueRef shared_memory;
147 uint64_t input_mask;
148 uint64_t output_mask;
149 int num_locals;
150 LLVMValueRef *locals;
151 bool has_ddxy;
152 unsigned num_clips;
153 unsigned num_culls;
154
155 bool has_ds_bpermute;
156
157 bool is_gs_copy_shader;
158 LLVMValueRef gs_next_vertex;
159 unsigned gs_max_out_vertices;
160 };
161
162 struct ac_tex_info {
163 LLVMValueRef args[12];
164 int arg_count;
165 LLVMTypeRef dst_type;
166 bool has_offset;
167 };
168
169 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
170 nir_deref_var *deref,
171 enum desc_type desc_type);
172 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
173 {
174 return (index * 4) + chan;
175 }
176
177 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
178 {
179 if (slot == VARYING_SLOT_POS)
180 return 0;
181 if (slot == VARYING_SLOT_PSIZ)
182 return 1;
183 if (slot == VARYING_SLOT_CLIP_DIST0)
184 return 2;
185 if (slot == VARYING_SLOT_CLIP_DIST1)
186 return 3;
187 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
188 return 4 + (slot - VARYING_SLOT_VAR0);
189 unreachable("illegal slot in get unique index\n");
190 }
191
192 static unsigned llvm_get_type_size(LLVMTypeRef type)
193 {
194 LLVMTypeKind kind = LLVMGetTypeKind(type);
195
196 switch (kind) {
197 case LLVMIntegerTypeKind:
198 return LLVMGetIntTypeWidth(type) / 8;
199 case LLVMFloatTypeKind:
200 return 4;
201 case LLVMPointerTypeKind:
202 return 8;
203 case LLVMVectorTypeKind:
204 return LLVMGetVectorSize(type) *
205 llvm_get_type_size(LLVMGetElementType(type));
206 default:
207 assert(0);
208 return 0;
209 }
210 }
211
212 static void set_llvm_calling_convention(LLVMValueRef func,
213 gl_shader_stage stage)
214 {
215 enum radeon_llvm_calling_convention calling_conv;
216
217 switch (stage) {
218 case MESA_SHADER_VERTEX:
219 case MESA_SHADER_TESS_CTRL:
220 case MESA_SHADER_TESS_EVAL:
221 calling_conv = RADEON_LLVM_AMDGPU_VS;
222 break;
223 case MESA_SHADER_GEOMETRY:
224 calling_conv = RADEON_LLVM_AMDGPU_GS;
225 break;
226 case MESA_SHADER_FRAGMENT:
227 calling_conv = RADEON_LLVM_AMDGPU_PS;
228 break;
229 case MESA_SHADER_COMPUTE:
230 calling_conv = RADEON_LLVM_AMDGPU_CS;
231 break;
232 default:
233 unreachable("Unhandle shader type");
234 }
235
236 LLVMSetFunctionCallConv(func, calling_conv);
237 }
238
239 static LLVMValueRef
240 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
241 LLVMBuilderRef builder, LLVMTypeRef *return_types,
242 unsigned num_return_elems, LLVMTypeRef *param_types,
243 unsigned param_count, unsigned array_params_mask,
244 unsigned sgpr_params, bool unsafe_math)
245 {
246 LLVMTypeRef main_function_type, ret_type;
247 LLVMBasicBlockRef main_function_body;
248
249 if (num_return_elems)
250 ret_type = LLVMStructTypeInContext(ctx, return_types,
251 num_return_elems, true);
252 else
253 ret_type = LLVMVoidTypeInContext(ctx);
254
255 /* Setup the function */
256 main_function_type =
257 LLVMFunctionType(ret_type, param_types, param_count, 0);
258 LLVMValueRef main_function =
259 LLVMAddFunction(module, "main", main_function_type);
260 main_function_body =
261 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
262 LLVMPositionBuilderAtEnd(builder, main_function_body);
263
264 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
265 for (unsigned i = 0; i < sgpr_params; ++i) {
266 if (array_params_mask & (1 << i)) {
267 LLVMValueRef P = LLVMGetParam(main_function, i);
268 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
269 ac_add_attr_dereferenceable(P, UINT64_MAX);
270 }
271 else {
272 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
273 }
274 }
275
276 if (unsafe_math) {
277 /* These were copied from some LLVM test. */
278 LLVMAddTargetDependentFunctionAttr(main_function,
279 "less-precise-fpmad",
280 "true");
281 LLVMAddTargetDependentFunctionAttr(main_function,
282 "no-infs-fp-math",
283 "true");
284 LLVMAddTargetDependentFunctionAttr(main_function,
285 "no-nans-fp-math",
286 "true");
287 LLVMAddTargetDependentFunctionAttr(main_function,
288 "unsafe-fp-math",
289 "true");
290 }
291 return main_function;
292 }
293
294 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
295 {
296 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
297 CONST_ADDR_SPACE);
298 }
299
300 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
301 int idx,
302 LLVMTypeRef type)
303 {
304 LLVMValueRef offset;
305 LLVMValueRef ptr;
306 int addr_space;
307
308 offset = LLVMConstInt(ctx->i32, idx, false);
309
310 ptr = ctx->shared_memory;
311 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
312 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
313 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
314 return ptr;
315 }
316
317 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
318 {
319 if (t == ctx->f16 || t == ctx->i16)
320 return ctx->i16;
321 else if (t == ctx->f32 || t == ctx->i32)
322 return ctx->i32;
323 else if (t == ctx->f64 || t == ctx->i64)
324 return ctx->i64;
325 else
326 unreachable("Unhandled integer size");
327 }
328
329 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
330 {
331 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
332 LLVMTypeRef elem_type = LLVMGetElementType(t);
333 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
334 LLVMGetVectorSize(t));
335 }
336 return to_integer_type_scalar(ctx, t);
337 }
338
339 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
340 {
341 LLVMTypeRef type = LLVMTypeOf(v);
342 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
343 }
344
345 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
346 {
347 if (t == ctx->i16 || t == ctx->f16)
348 return ctx->f16;
349 else if (t == ctx->i32 || t == ctx->f32)
350 return ctx->f32;
351 else if (t == ctx->i64 || t == ctx->f64)
352 return ctx->f64;
353 else
354 unreachable("Unhandled float size");
355 }
356
357 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
358 {
359 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
360 LLVMTypeRef elem_type = LLVMGetElementType(t);
361 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
362 LLVMGetVectorSize(t));
363 }
364 return to_float_type_scalar(ctx, t);
365 }
366
367 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
368 {
369 LLVMTypeRef type = LLVMTypeOf(v);
370 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
371 }
372
373 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
374 {
375 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
376 type = LLVMGetElementType(type);
377
378 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
379 return LLVMGetIntTypeWidth(type);
380
381 if (type == ctx->f16)
382 return 16;
383 if (type == ctx->f32)
384 return 32;
385 if (type == ctx->f64)
386 return 64;
387
388 unreachable("Unhandled type kind in get_elem_bits");
389 }
390
391 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
392 LLVMValueRef param, unsigned rshift,
393 unsigned bitwidth)
394 {
395 LLVMValueRef value = param;
396 if (rshift)
397 value = LLVMBuildLShr(ctx->builder, value,
398 LLVMConstInt(ctx->i32, rshift, false), "");
399
400 if (rshift + bitwidth < 32) {
401 unsigned mask = (1 << bitwidth) - 1;
402 value = LLVMBuildAnd(ctx->builder, value,
403 LLVMConstInt(ctx->i32, mask, false), "");
404 }
405 return value;
406 }
407
408 static LLVMValueRef build_gep0(struct nir_to_llvm_context *ctx,
409 LLVMValueRef base_ptr, LLVMValueRef index)
410 {
411 LLVMValueRef indices[2] = {
412 ctx->i32zero,
413 index,
414 };
415 return LLVMBuildGEP(ctx->builder, base_ptr,
416 indices, 2, "");
417 }
418
419 static LLVMValueRef build_indexed_load(struct nir_to_llvm_context *ctx,
420 LLVMValueRef base_ptr, LLVMValueRef index,
421 bool uniform)
422 {
423 LLVMValueRef pointer;
424 pointer = build_gep0(ctx, base_ptr, index);
425 if (uniform)
426 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
427 return LLVMBuildLoad(ctx->builder, pointer, "");
428 }
429
430 static LLVMValueRef build_indexed_load_const(struct nir_to_llvm_context *ctx,
431 LLVMValueRef base_ptr, LLVMValueRef index)
432 {
433 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
434 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
435 return result;
436 }
437
438 static void build_tbuffer_store(struct nir_to_llvm_context *ctx,
439 LLVMValueRef rsrc,
440 LLVMValueRef vdata,
441 unsigned num_channels,
442 LLVMValueRef vaddr,
443 LLVMValueRef soffset,
444 unsigned inst_offset,
445 unsigned dfmt,
446 unsigned nfmt,
447 unsigned offen,
448 unsigned idxen,
449 unsigned glc,
450 unsigned slc,
451 unsigned tfe)
452 {
453 LLVMValueRef args[] = {
454 rsrc,
455 vdata,
456 LLVMConstInt(ctx->i32, num_channels, 0),
457 vaddr,
458 soffset,
459 LLVMConstInt(ctx->i32, inst_offset, 0),
460 LLVMConstInt(ctx->i32, dfmt, 0),
461 LLVMConstInt(ctx->i32, nfmt, 0),
462 LLVMConstInt(ctx->i32, offen, 0),
463 LLVMConstInt(ctx->i32, idxen, 0),
464 LLVMConstInt(ctx->i32, glc, 0),
465 LLVMConstInt(ctx->i32, slc, 0),
466 LLVMConstInt(ctx->i32, tfe, 0)
467 };
468
469 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
470 unsigned func = CLAMP(num_channels, 1, 3) - 1;
471 const char *types[] = {"i32", "v2i32", "v4i32"};
472 char name[256];
473 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
474
475 ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->voidt,
476 args, ARRAY_SIZE(args), 0);
477
478 }
479
480 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
481 {
482 ud_info->sgpr_idx = sgpr_idx;
483 ud_info->num_sgprs = num_sgprs;
484 ud_info->indirect = false;
485 ud_info->indirect_offset = 0;
486 }
487
488 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
489 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
490 {
491 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
492 }
493
494 #if 0
495 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
496 uint32_t indirect_offset)
497 {
498 ud_info->sgpr_idx = sgpr_idx;
499 ud_info->num_sgprs = num_sgprs;
500 ud_info->indirect = true;
501 ud_info->indirect_offset = indirect_offset;
502 }
503 #endif
504
505 static void create_function(struct nir_to_llvm_context *ctx)
506 {
507 LLVMTypeRef arg_types[23];
508 unsigned arg_idx = 0;
509 unsigned array_params_mask = 0;
510 unsigned sgpr_count = 0, user_sgpr_count;
511 unsigned i;
512 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
513 unsigned user_sgpr_idx;
514 bool need_push_constants;
515 bool need_ring_offsets = false;
516
517 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
518 if (ctx->stage == MESA_SHADER_GEOMETRY ||
519 ctx->stage == MESA_SHADER_VERTEX ||
520 ctx->is_gs_copy_shader)
521 need_ring_offsets = true;
522
523 need_push_constants = true;
524 if (!ctx->options->layout)
525 need_push_constants = false;
526 else if (!ctx->options->layout->push_constant_size &&
527 !ctx->options->layout->dynamic_offset_count)
528 need_push_constants = false;
529
530 if (need_ring_offsets && !ctx->options->supports_spill) {
531 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
532 }
533
534 /* 1 for each descriptor set */
535 for (unsigned i = 0; i < num_sets; ++i) {
536 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
537 array_params_mask |= (1 << arg_idx);
538 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
539 }
540 }
541
542 if (need_push_constants) {
543 /* 1 for push constants and dynamic descriptors */
544 array_params_mask |= (1 << arg_idx);
545 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
546 }
547
548 switch (ctx->stage) {
549 case MESA_SHADER_COMPUTE:
550 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
551 user_sgpr_count = arg_idx;
552 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
553 arg_types[arg_idx++] = ctx->i32;
554 sgpr_count = arg_idx;
555
556 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
557 break;
558 case MESA_SHADER_VERTEX:
559 if (!ctx->is_gs_copy_shader) {
560 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
561 arg_types[arg_idx++] = ctx->i32; // base vertex
562 arg_types[arg_idx++] = ctx->i32; // start instance
563 }
564 user_sgpr_count = arg_idx;
565 if (ctx->options->key.vs.as_es)
566 arg_types[arg_idx++] = ctx->i32; //es2gs offset
567 sgpr_count = arg_idx;
568 arg_types[arg_idx++] = ctx->i32; // vertex id
569 if (!ctx->is_gs_copy_shader) {
570 arg_types[arg_idx++] = ctx->i32; // rel auto id
571 arg_types[arg_idx++] = ctx->i32; // vs prim id
572 arg_types[arg_idx++] = ctx->i32; // instance id
573 }
574 break;
575 case MESA_SHADER_GEOMETRY:
576 arg_types[arg_idx++] = ctx->i32; // gsvs stride
577 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
578 user_sgpr_count = arg_idx;
579 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
580 arg_types[arg_idx++] = ctx->i32; // wave id
581 sgpr_count = arg_idx;
582 arg_types[arg_idx++] = ctx->i32; // vtx0
583 arg_types[arg_idx++] = ctx->i32; // vtx1
584 arg_types[arg_idx++] = ctx->i32; // prim id
585 arg_types[arg_idx++] = ctx->i32; // vtx2
586 arg_types[arg_idx++] = ctx->i32; // vtx3
587 arg_types[arg_idx++] = ctx->i32; // vtx4
588 arg_types[arg_idx++] = ctx->i32; // vtx5
589 arg_types[arg_idx++] = ctx->i32; // GS instance id
590 break;
591 case MESA_SHADER_FRAGMENT:
592 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
593 user_sgpr_count = arg_idx;
594 arg_types[arg_idx++] = ctx->i32; /* prim mask */
595 sgpr_count = arg_idx;
596 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
597 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
598 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
599 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
600 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
601 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
602 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
603 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
604 arg_types[arg_idx++] = ctx->f32; /* pos x float */
605 arg_types[arg_idx++] = ctx->f32; /* pos y float */
606 arg_types[arg_idx++] = ctx->f32; /* pos z float */
607 arg_types[arg_idx++] = ctx->f32; /* pos w float */
608 arg_types[arg_idx++] = ctx->i32; /* front face */
609 arg_types[arg_idx++] = ctx->i32; /* ancillary */
610 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
611 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
612 break;
613 default:
614 unreachable("Shader stage not implemented");
615 }
616
617 ctx->main_function = create_llvm_function(
618 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
619 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
620 set_llvm_calling_convention(ctx->main_function, ctx->stage);
621
622 ctx->shader_info->num_input_sgprs = 0;
623 ctx->shader_info->num_input_vgprs = 0;
624
625 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
626 for (i = 0; i < user_sgpr_count; i++)
627 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
628
629 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
630 for (; i < sgpr_count; i++)
631 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
632
633 if (ctx->stage != MESA_SHADER_FRAGMENT)
634 for (; i < arg_idx; ++i)
635 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
636
637 arg_idx = 0;
638 user_sgpr_idx = 0;
639
640 if (ctx->options->supports_spill || need_ring_offsets) {
641 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
642 user_sgpr_idx += 2;
643 if (ctx->options->supports_spill) {
644 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
645 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
646 NULL, 0, AC_FUNC_ATTR_READNONE);
647 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
648 const_array(ctx->v16i8, 8), "");
649 } else
650 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
651 }
652
653 for (unsigned i = 0; i < num_sets; ++i) {
654 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
655 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
656 user_sgpr_idx += 2;
657 ctx->descriptor_sets[i] =
658 LLVMGetParam(ctx->main_function, arg_idx++);
659 } else
660 ctx->descriptor_sets[i] = NULL;
661 }
662
663 if (need_push_constants) {
664 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
665 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
666 user_sgpr_idx += 2;
667 }
668
669 switch (ctx->stage) {
670 case MESA_SHADER_COMPUTE:
671 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
672 user_sgpr_idx += 3;
673 ctx->num_work_groups =
674 LLVMGetParam(ctx->main_function, arg_idx++);
675 ctx->workgroup_ids =
676 LLVMGetParam(ctx->main_function, arg_idx++);
677 ctx->tg_size =
678 LLVMGetParam(ctx->main_function, arg_idx++);
679 ctx->local_invocation_ids =
680 LLVMGetParam(ctx->main_function, arg_idx++);
681 break;
682 case MESA_SHADER_VERTEX:
683 if (!ctx->is_gs_copy_shader) {
684 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
685 user_sgpr_idx += 2;
686 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
687 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 2);
688 user_sgpr_idx += 2;
689 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
690 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
691 }
692 if (ctx->options->key.vs.as_es)
693 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
694 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
695 if (!ctx->is_gs_copy_shader) {
696 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
697 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
698 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
699 }
700 break;
701 case MESA_SHADER_GEOMETRY:
702 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
703 user_sgpr_idx += 2;
704 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
705 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
706 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
707 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
708 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
709 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
710 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
711 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
712 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
713 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
714 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
715 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
716 break;
717 case MESA_SHADER_FRAGMENT:
718 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
719 user_sgpr_idx += 2;
720 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
721 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
722 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
723 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
724 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
725 arg_idx++;
726 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
727 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
728 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
729 arg_idx++; /* line stipple */
730 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
731 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
732 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
733 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
734 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
735 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
736 break;
737 default:
738 unreachable("Shader stage not implemented");
739 }
740 }
741
742 static void setup_types(struct nir_to_llvm_context *ctx)
743 {
744 LLVMValueRef args[4];
745
746 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
747 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
748 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
749 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
750 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
751 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
752 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
753 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
754 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
755 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
756 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
757 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
758 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
759 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
760 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
761 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
762
763 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
764 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
765 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
766 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
767
768 args[0] = ctx->f32zero;
769 args[1] = ctx->f32zero;
770 args[2] = ctx->f32zero;
771 args[3] = ctx->f32one;
772 ctx->v4f32empty = LLVMConstVector(args, 4);
773
774 ctx->range_md_kind = LLVMGetMDKindIDInContext(ctx->context,
775 "range", 5);
776 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(ctx->context,
777 "invariant.load", 14);
778 ctx->uniform_md_kind =
779 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
780 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
781
782 args[0] = LLVMConstReal(ctx->f32, 2.5);
783 }
784
785 static int get_llvm_num_components(LLVMValueRef value)
786 {
787 LLVMTypeRef type = LLVMTypeOf(value);
788 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
789 ? LLVMGetVectorSize(type)
790 : 1;
791 return num_components;
792 }
793
794 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
795 LLVMValueRef value,
796 int index)
797 {
798 int count = get_llvm_num_components(value);
799
800 assert(index < count);
801 if (count == 1)
802 return value;
803
804 return LLVMBuildExtractElement(ctx->builder, value,
805 LLVMConstInt(ctx->i32, index, false), "");
806 }
807
808 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
809 LLVMValueRef value, unsigned count)
810 {
811 unsigned num_components = get_llvm_num_components(value);
812 if (count == num_components)
813 return value;
814
815 LLVMValueRef masks[] = {
816 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
817 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
818
819 if (count == 1)
820 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
821 "");
822
823 LLVMValueRef swizzle = LLVMConstVector(masks, count);
824 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
825 }
826
827 static void
828 build_store_values_extended(struct nir_to_llvm_context *ctx,
829 LLVMValueRef *values,
830 unsigned value_count,
831 unsigned value_stride,
832 LLVMValueRef vec)
833 {
834 LLVMBuilderRef builder = ctx->builder;
835 unsigned i;
836
837 if (value_count == 1) {
838 LLVMBuildStore(builder, vec, values[0]);
839 return;
840 }
841
842 for (i = 0; i < value_count; i++) {
843 LLVMValueRef ptr = values[i * value_stride];
844 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
845 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
846 LLVMBuildStore(builder, value, ptr);
847 }
848 }
849
850 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
851 nir_ssa_def *def)
852 {
853 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
854 if (def->num_components > 1) {
855 type = LLVMVectorType(type, def->num_components);
856 }
857 return type;
858 }
859
860 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
861 {
862 assert(src.is_ssa);
863 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
864 return (LLVMValueRef)entry->data;
865 }
866
867
868 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
869 struct nir_block *b)
870 {
871 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
872 return (LLVMBasicBlockRef)entry->data;
873 }
874
875 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
876 nir_alu_src src,
877 unsigned num_components)
878 {
879 LLVMValueRef value = get_src(ctx, src.src);
880 bool need_swizzle = false;
881
882 assert(value);
883 LLVMTypeRef type = LLVMTypeOf(value);
884 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
885 ? LLVMGetVectorSize(type)
886 : 1;
887
888 for (unsigned i = 0; i < num_components; ++i) {
889 assert(src.swizzle[i] < src_components);
890 if (src.swizzle[i] != i)
891 need_swizzle = true;
892 }
893
894 if (need_swizzle || num_components != src_components) {
895 LLVMValueRef masks[] = {
896 LLVMConstInt(ctx->i32, src.swizzle[0], false),
897 LLVMConstInt(ctx->i32, src.swizzle[1], false),
898 LLVMConstInt(ctx->i32, src.swizzle[2], false),
899 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
900
901 if (src_components > 1 && num_components == 1) {
902 value = LLVMBuildExtractElement(ctx->builder, value,
903 masks[0], "");
904 } else if (src_components == 1 && num_components > 1) {
905 LLVMValueRef values[] = {value, value, value, value};
906 value = ac_build_gather_values(&ctx->ac, values, num_components);
907 } else {
908 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
909 value = LLVMBuildShuffleVector(ctx->builder, value, value,
910 swizzle, "");
911 }
912 }
913 assert(!src.negate);
914 assert(!src.abs);
915 return value;
916 }
917
918 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
919 LLVMIntPredicate pred, LLVMValueRef src0,
920 LLVMValueRef src1)
921 {
922 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
923 return LLVMBuildSelect(ctx->builder, result,
924 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
925 LLVMConstInt(ctx->i32, 0, false), "");
926 }
927
928 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
929 LLVMRealPredicate pred, LLVMValueRef src0,
930 LLVMValueRef src1)
931 {
932 LLVMValueRef result;
933 src0 = to_float(ctx, src0);
934 src1 = to_float(ctx, src1);
935 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
936 return LLVMBuildSelect(ctx->builder, result,
937 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
938 LLVMConstInt(ctx->i32, 0, false), "");
939 }
940
941 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
942 const char *intrin,
943 LLVMTypeRef result_type,
944 LLVMValueRef src0)
945 {
946 char name[64];
947 LLVMValueRef params[] = {
948 to_float(ctx, src0),
949 };
950
951 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
952 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
953 }
954
955 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
956 const char *intrin,
957 LLVMTypeRef result_type,
958 LLVMValueRef src0, LLVMValueRef src1)
959 {
960 char name[64];
961 LLVMValueRef params[] = {
962 to_float(ctx, src0),
963 to_float(ctx, src1),
964 };
965
966 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
967 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
968 }
969
970 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
971 const char *intrin,
972 LLVMTypeRef result_type,
973 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
974 {
975 char name[64];
976 LLVMValueRef params[] = {
977 to_float(ctx, src0),
978 to_float(ctx, src1),
979 to_float(ctx, src2),
980 };
981
982 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
983 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
984 }
985
986 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
987 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
988 {
989 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
990 ctx->i32zero, "");
991 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
992 }
993
994 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
995 LLVMValueRef src0)
996 {
997 LLVMValueRef params[2] = {
998 src0,
999
1000 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1001 * add special code to check for x=0. The reason is that
1002 * the LLVM behavior for x=0 is different from what we
1003 * need here.
1004 *
1005 * The hardware already implements the correct behavior.
1006 */
1007 LLVMConstInt(ctx->i32, 1, false),
1008 };
1009 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1010 }
1011
1012 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1013 LLVMValueRef src0)
1014 {
1015 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.flbit.i32",
1016 ctx->i32, &src0, 1,
1017 AC_FUNC_ATTR_READNONE);
1018
1019 /* The HW returns the last bit index from MSB, but NIR wants
1020 * the index from LSB. Invert it by doing "31 - msb". */
1021 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
1022 msb, "");
1023
1024 LLVMValueRef all_ones = LLVMConstInt(ctx->i32, -1, true);
1025 LLVMValueRef cond = LLVMBuildOr(ctx->builder,
1026 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
1027 src0, ctx->i32zero, ""),
1028 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
1029 src0, all_ones, ""), "");
1030
1031 return LLVMBuildSelect(ctx->builder, cond, all_ones, msb, "");
1032 }
1033
1034 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1035 LLVMValueRef src0)
1036 {
1037 LLVMValueRef args[2] = {
1038 src0,
1039 ctx->i32one,
1040 };
1041 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctlz.i32",
1042 ctx->i32, args, ARRAY_SIZE(args),
1043 AC_FUNC_ATTR_READNONE);
1044
1045 /* The HW returns the last bit index from MSB, but NIR wants
1046 * the index from LSB. Invert it by doing "31 - msb". */
1047 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
1048 msb, "");
1049
1050 return LLVMBuildSelect(ctx->builder,
1051 LLVMBuildICmp(ctx->builder, LLVMIntEQ, src0,
1052 ctx->i32zero, ""),
1053 LLVMConstInt(ctx->i32, -1, true), msb, "");
1054 }
1055
1056 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1057 LLVMIntPredicate pred,
1058 LLVMValueRef src0, LLVMValueRef src1)
1059 {
1060 return LLVMBuildSelect(ctx->builder,
1061 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1062 src0,
1063 src1, "");
1064
1065 }
1066 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1067 LLVMValueRef src0)
1068 {
1069 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1070 LLVMBuildNeg(ctx->builder, src0, ""));
1071 }
1072
1073 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1074 LLVMValueRef src0)
1075 {
1076 LLVMValueRef cmp, val;
1077
1078 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1079 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1080 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1081 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1082 return val;
1083 }
1084
1085 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1086 LLVMValueRef src0)
1087 {
1088 LLVMValueRef cmp, val;
1089
1090 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1091 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1092 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1093 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1094 return val;
1095 }
1096
1097 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1098 LLVMValueRef src0)
1099 {
1100 const char *intr = "llvm.floor.f32";
1101 LLVMValueRef fsrc0 = to_float(ctx, src0);
1102 LLVMValueRef params[] = {
1103 fsrc0,
1104 };
1105 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
1106 ctx->f32, params, 1,
1107 AC_FUNC_ATTR_READNONE);
1108 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1109 }
1110
1111 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1112 const char *intrin,
1113 LLVMValueRef src0, LLVMValueRef src1)
1114 {
1115 LLVMTypeRef ret_type;
1116 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1117 LLVMValueRef res;
1118 LLVMValueRef params[] = { src0, src1 };
1119 ret_type = LLVMStructTypeInContext(ctx->context, types,
1120 2, true);
1121
1122 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1123 params, 2, AC_FUNC_ATTR_READNONE);
1124
1125 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1126 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1127 return res;
1128 }
1129
1130 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1131 LLVMValueRef src0)
1132 {
1133 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1134 }
1135
1136 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1137 LLVMValueRef src0, LLVMValueRef src1)
1138 {
1139 LLVMValueRef dst64, result;
1140 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1141 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1142
1143 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1144 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1145 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1146 return result;
1147 }
1148
1149 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1150 LLVMValueRef src0, LLVMValueRef src1)
1151 {
1152 LLVMValueRef dst64, result;
1153 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1154 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1155
1156 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1157 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1158 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1159 return result;
1160 }
1161
1162 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1163 const char *intrin,
1164 LLVMValueRef srcs[3])
1165 {
1166 LLVMValueRef result;
1167 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1168 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1169
1170 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1171 return result;
1172 }
1173
1174 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1175 LLVMValueRef src0, LLVMValueRef src1,
1176 LLVMValueRef src2, LLVMValueRef src3)
1177 {
1178 LLVMValueRef bfi_args[3], result;
1179
1180 bfi_args[0] = LLVMBuildShl(ctx->builder,
1181 LLVMBuildSub(ctx->builder,
1182 LLVMBuildShl(ctx->builder,
1183 ctx->i32one,
1184 src3, ""),
1185 ctx->i32one, ""),
1186 src2, "");
1187 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1188 bfi_args[2] = src0;
1189
1190 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1191
1192 /* Calculate:
1193 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1194 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1195 */
1196 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1197 LLVMBuildAnd(ctx->builder, bfi_args[0],
1198 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1199
1200 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1201 return result;
1202 }
1203
1204 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1205 LLVMValueRef src0)
1206 {
1207 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1208 int i;
1209 LLVMValueRef comp[2];
1210
1211 src0 = to_float(ctx, src0);
1212 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1213 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1214 for (i = 0; i < 2; i++) {
1215 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1216 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1217 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1218 }
1219
1220 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1221 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1222
1223 return comp[0];
1224 }
1225
1226 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1227 LLVMValueRef src0)
1228 {
1229 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1230 LLVMValueRef temps[2], result, val;
1231 int i;
1232
1233 for (i = 0; i < 2; i++) {
1234 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1235 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1236 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1237 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1238 }
1239
1240 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1241 ctx->i32zero, "");
1242 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1243 ctx->i32one, "");
1244 return result;
1245 }
1246
1247 /**
1248 * Set range metadata on an instruction. This can only be used on load and
1249 * call instructions. If you know an instruction can only produce the values
1250 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1251 * \p lo is the minimum value inclusive.
1252 * \p hi is the maximum value exclusive.
1253 */
1254 static void set_range_metadata(struct nir_to_llvm_context *ctx,
1255 LLVMValueRef value, unsigned lo, unsigned hi)
1256 {
1257 LLVMValueRef range_md, md_args[2];
1258 LLVMTypeRef type = LLVMTypeOf(value);
1259 LLVMContextRef context = LLVMGetTypeContext(type);
1260
1261 md_args[0] = LLVMConstInt(type, lo, false);
1262 md_args[1] = LLVMConstInt(type, hi, false);
1263 range_md = LLVMMDNodeInContext(context, md_args, 2);
1264 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1265 }
1266
1267 static LLVMValueRef get_thread_id(struct nir_to_llvm_context *ctx)
1268 {
1269 LLVMValueRef tid;
1270 LLVMValueRef tid_args[2];
1271 tid_args[0] = LLVMConstInt(ctx->i32, 0xffffffff, false);
1272 tid_args[1] = ctx->i32zero;
1273 tid_args[1] = ac_emit_llvm_intrinsic(&ctx->ac,
1274 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1275 tid_args, 2, AC_FUNC_ATTR_READNONE);
1276
1277 tid = ac_emit_llvm_intrinsic(&ctx->ac,
1278 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1279 tid_args, 2, AC_FUNC_ATTR_READNONE);
1280 set_range_metadata(ctx, tid, 0, 64);
1281 return tid;
1282 }
1283
1284 /*
1285 * SI implements derivatives using the local data store (LDS)
1286 * All writes to the LDS happen in all executing threads at
1287 * the same time. TID is the Thread ID for the current
1288 * thread and is a value between 0 and 63, representing
1289 * the thread's position in the wavefront.
1290 *
1291 * For the pixel shader threads are grouped into quads of four pixels.
1292 * The TIDs of the pixels of a quad are:
1293 *
1294 * +------+------+
1295 * |4n + 0|4n + 1|
1296 * +------+------+
1297 * |4n + 2|4n + 3|
1298 * +------+------+
1299 *
1300 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
1301 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
1302 * the current pixel's column, and masking with 0xfffffffe yields the TID
1303 * of the left pixel of the current pixel's row.
1304 *
1305 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
1306 * adding 2 yields the TID of the pixel below the top pixel.
1307 */
1308 /* masks for thread ID. */
1309 #define TID_MASK_TOP_LEFT 0xfffffffc
1310 #define TID_MASK_TOP 0xfffffffd
1311 #define TID_MASK_LEFT 0xfffffffe
1312 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1313 nir_op op,
1314 LLVMValueRef src0)
1315 {
1316 LLVMValueRef tl, trbl, result;
1317 LLVMValueRef tl_tid, trbl_tid;
1318 LLVMValueRef args[2];
1319 LLVMValueRef thread_id;
1320 unsigned mask;
1321 int idx;
1322 ctx->has_ddxy = true;
1323
1324 if (!ctx->lds && !ctx->has_ds_bpermute)
1325 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1326 LLVMArrayType(ctx->i32, 64),
1327 "ddxy_lds", LOCAL_ADDR_SPACE);
1328
1329 thread_id = get_thread_id(ctx);
1330 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1331 mask = TID_MASK_LEFT;
1332 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1333 mask = TID_MASK_TOP;
1334 else
1335 mask = TID_MASK_TOP_LEFT;
1336
1337 tl_tid = LLVMBuildAnd(ctx->builder, thread_id,
1338 LLVMConstInt(ctx->i32, mask, false), "");
1339 /* for DDX we want to next X pixel, DDY next Y pixel. */
1340 if (op == nir_op_fddx_fine ||
1341 op == nir_op_fddx_coarse ||
1342 op == nir_op_fddx)
1343 idx = 1;
1344 else
1345 idx = 2;
1346
1347 trbl_tid = LLVMBuildAdd(ctx->builder, tl_tid,
1348 LLVMConstInt(ctx->i32, idx, false), "");
1349
1350 if (ctx->has_ds_bpermute) {
1351 args[0] = LLVMBuildMul(ctx->builder, tl_tid,
1352 LLVMConstInt(ctx->i32, 4, false), "");
1353 args[1] = src0;
1354 tl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1355 ctx->i32, args, 2,
1356 AC_FUNC_ATTR_READNONE);
1357
1358 args[0] = LLVMBuildMul(ctx->builder, trbl_tid,
1359 LLVMConstInt(ctx->i32, 4, false), "");
1360 trbl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1361 ctx->i32, args, 2,
1362 AC_FUNC_ATTR_READNONE);
1363 } else {
1364 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1365
1366 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
1367 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
1368 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
1369
1370 LLVMBuildStore(ctx->builder, src0, store_ptr);
1371 tl = LLVMBuildLoad(ctx->builder, load_ptr0, "");
1372 trbl = LLVMBuildLoad(ctx->builder, load_ptr1, "");
1373 }
1374 tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
1375 trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
1376 result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
1377 return result;
1378 }
1379
1380 /*
1381 * this takes an I,J coordinate pair,
1382 * and works out the X and Y derivatives.
1383 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1384 */
1385 static LLVMValueRef emit_ddxy_interp(
1386 struct nir_to_llvm_context *ctx,
1387 LLVMValueRef interp_ij)
1388 {
1389 LLVMValueRef result[4], a;
1390 unsigned i;
1391
1392 for (i = 0; i < 2; i++) {
1393 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1394 LLVMConstInt(ctx->i32, i, false), "");
1395 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1396 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1397 }
1398 return ac_build_gather_values(&ctx->ac, result, 4);
1399 }
1400
1401 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1402 {
1403 LLVMValueRef src[4], result = NULL;
1404 unsigned num_components = instr->dest.dest.ssa.num_components;
1405 unsigned src_components;
1406 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1407
1408 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1409 switch (instr->op) {
1410 case nir_op_vec2:
1411 case nir_op_vec3:
1412 case nir_op_vec4:
1413 src_components = 1;
1414 break;
1415 case nir_op_pack_half_2x16:
1416 src_components = 2;
1417 break;
1418 case nir_op_unpack_half_2x16:
1419 src_components = 1;
1420 break;
1421 default:
1422 src_components = num_components;
1423 break;
1424 }
1425 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1426 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1427
1428 switch (instr->op) {
1429 case nir_op_fmov:
1430 case nir_op_imov:
1431 result = src[0];
1432 break;
1433 case nir_op_fneg:
1434 src[0] = to_float(ctx, src[0]);
1435 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1436 break;
1437 case nir_op_ineg:
1438 result = LLVMBuildNeg(ctx->builder, src[0], "");
1439 break;
1440 case nir_op_inot:
1441 result = LLVMBuildNot(ctx->builder, src[0], "");
1442 break;
1443 case nir_op_iadd:
1444 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1445 break;
1446 case nir_op_fadd:
1447 src[0] = to_float(ctx, src[0]);
1448 src[1] = to_float(ctx, src[1]);
1449 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1450 break;
1451 case nir_op_fsub:
1452 src[0] = to_float(ctx, src[0]);
1453 src[1] = to_float(ctx, src[1]);
1454 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1455 break;
1456 case nir_op_isub:
1457 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1458 break;
1459 case nir_op_imul:
1460 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1461 break;
1462 case nir_op_imod:
1463 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1464 break;
1465 case nir_op_umod:
1466 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1467 break;
1468 case nir_op_fmod:
1469 src[0] = to_float(ctx, src[0]);
1470 src[1] = to_float(ctx, src[1]);
1471 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1472 result = emit_intrin_1f_param(ctx, "llvm.floor",
1473 to_float_type(ctx, def_type), result);
1474 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1475 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1476 break;
1477 case nir_op_frem:
1478 src[0] = to_float(ctx, src[0]);
1479 src[1] = to_float(ctx, src[1]);
1480 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1481 break;
1482 case nir_op_irem:
1483 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1484 break;
1485 case nir_op_idiv:
1486 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1487 break;
1488 case nir_op_udiv:
1489 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1490 break;
1491 case nir_op_fmul:
1492 src[0] = to_float(ctx, src[0]);
1493 src[1] = to_float(ctx, src[1]);
1494 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1495 break;
1496 case nir_op_fdiv:
1497 src[0] = to_float(ctx, src[0]);
1498 src[1] = to_float(ctx, src[1]);
1499 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1500 break;
1501 case nir_op_frcp:
1502 src[0] = to_float(ctx, src[0]);
1503 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1504 break;
1505 case nir_op_iand:
1506 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1507 break;
1508 case nir_op_ior:
1509 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1510 break;
1511 case nir_op_ixor:
1512 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1513 break;
1514 case nir_op_ishl:
1515 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1516 break;
1517 case nir_op_ishr:
1518 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1519 break;
1520 case nir_op_ushr:
1521 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1522 break;
1523 case nir_op_ilt:
1524 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1525 break;
1526 case nir_op_ine:
1527 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1528 break;
1529 case nir_op_ieq:
1530 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1531 break;
1532 case nir_op_ige:
1533 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1534 break;
1535 case nir_op_ult:
1536 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1537 break;
1538 case nir_op_uge:
1539 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1540 break;
1541 case nir_op_feq:
1542 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1543 break;
1544 case nir_op_fne:
1545 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1546 break;
1547 case nir_op_flt:
1548 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1549 break;
1550 case nir_op_fge:
1551 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1552 break;
1553 case nir_op_fabs:
1554 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1555 to_float_type(ctx, def_type), src[0]);
1556 break;
1557 case nir_op_iabs:
1558 result = emit_iabs(ctx, src[0]);
1559 break;
1560 case nir_op_imax:
1561 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1562 break;
1563 case nir_op_imin:
1564 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1565 break;
1566 case nir_op_umax:
1567 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1568 break;
1569 case nir_op_umin:
1570 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1571 break;
1572 case nir_op_isign:
1573 result = emit_isign(ctx, src[0]);
1574 break;
1575 case nir_op_fsign:
1576 src[0] = to_float(ctx, src[0]);
1577 result = emit_fsign(ctx, src[0]);
1578 break;
1579 case nir_op_ffloor:
1580 result = emit_intrin_1f_param(ctx, "llvm.floor",
1581 to_float_type(ctx, def_type), src[0]);
1582 break;
1583 case nir_op_ftrunc:
1584 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1585 to_float_type(ctx, def_type), src[0]);
1586 break;
1587 case nir_op_fceil:
1588 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1589 to_float_type(ctx, def_type), src[0]);
1590 break;
1591 case nir_op_fround_even:
1592 result = emit_intrin_1f_param(ctx, "llvm.rint",
1593 to_float_type(ctx, def_type),src[0]);
1594 break;
1595 case nir_op_ffract:
1596 result = emit_ffract(ctx, src[0]);
1597 break;
1598 case nir_op_fsin:
1599 result = emit_intrin_1f_param(ctx, "llvm.sin",
1600 to_float_type(ctx, def_type), src[0]);
1601 break;
1602 case nir_op_fcos:
1603 result = emit_intrin_1f_param(ctx, "llvm.cos",
1604 to_float_type(ctx, def_type), src[0]);
1605 break;
1606 case nir_op_fsqrt:
1607 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1608 to_float_type(ctx, def_type), src[0]);
1609 break;
1610 case nir_op_fexp2:
1611 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1612 to_float_type(ctx, def_type), src[0]);
1613 break;
1614 case nir_op_flog2:
1615 result = emit_intrin_1f_param(ctx, "llvm.log2",
1616 to_float_type(ctx, def_type), src[0]);
1617 break;
1618 case nir_op_frsq:
1619 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1620 to_float_type(ctx, def_type), src[0]);
1621 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1622 break;
1623 case nir_op_fpow:
1624 result = emit_intrin_2f_param(ctx, "llvm.pow",
1625 to_float_type(ctx, def_type), src[0], src[1]);
1626 break;
1627 case nir_op_fmax:
1628 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1629 to_float_type(ctx, def_type), src[0], src[1]);
1630 break;
1631 case nir_op_fmin:
1632 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1633 to_float_type(ctx, def_type), src[0], src[1]);
1634 break;
1635 case nir_op_ffma:
1636 result = emit_intrin_3f_param(ctx, "llvm.fma",
1637 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1638 break;
1639 case nir_op_ibitfield_extract:
1640 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1641 break;
1642 case nir_op_ubitfield_extract:
1643 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1644 break;
1645 case nir_op_bitfield_insert:
1646 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1647 break;
1648 case nir_op_bitfield_reverse:
1649 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1650 break;
1651 case nir_op_bit_count:
1652 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1653 break;
1654 case nir_op_vec2:
1655 case nir_op_vec3:
1656 case nir_op_vec4:
1657 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1658 src[i] = to_integer(ctx, src[i]);
1659 result = ac_build_gather_values(&ctx->ac, src, num_components);
1660 break;
1661 case nir_op_d2i:
1662 case nir_op_f2i:
1663 src[0] = to_float(ctx, src[0]);
1664 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1665 break;
1666 case nir_op_d2u:
1667 case nir_op_f2u:
1668 src[0] = to_float(ctx, src[0]);
1669 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1670 break;
1671 case nir_op_i2d:
1672 case nir_op_i2f:
1673 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1674 break;
1675 case nir_op_u2d:
1676 case nir_op_u2f:
1677 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1678 break;
1679 case nir_op_f2d:
1680 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1681 break;
1682 case nir_op_d2f:
1683 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1684 break;
1685 case nir_op_bcsel:
1686 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1687 break;
1688 case nir_op_find_lsb:
1689 result = emit_find_lsb(ctx, src[0]);
1690 break;
1691 case nir_op_ufind_msb:
1692 result = emit_ufind_msb(ctx, src[0]);
1693 break;
1694 case nir_op_ifind_msb:
1695 result = emit_ifind_msb(ctx, src[0]);
1696 break;
1697 case nir_op_uadd_carry:
1698 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1699 break;
1700 case nir_op_usub_borrow:
1701 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1702 break;
1703 case nir_op_b2f:
1704 result = emit_b2f(ctx, src[0]);
1705 break;
1706 case nir_op_fquantize2f16:
1707 src[0] = to_float(ctx, src[0]);
1708 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1709 /* need to convert back up to f32 */
1710 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1711 break;
1712 case nir_op_umul_high:
1713 result = emit_umul_high(ctx, src[0], src[1]);
1714 break;
1715 case nir_op_imul_high:
1716 result = emit_imul_high(ctx, src[0], src[1]);
1717 break;
1718 case nir_op_pack_half_2x16:
1719 result = emit_pack_half_2x16(ctx, src[0]);
1720 break;
1721 case nir_op_unpack_half_2x16:
1722 result = emit_unpack_half_2x16(ctx, src[0]);
1723 break;
1724 case nir_op_fddx:
1725 case nir_op_fddy:
1726 case nir_op_fddx_fine:
1727 case nir_op_fddy_fine:
1728 case nir_op_fddx_coarse:
1729 case nir_op_fddy_coarse:
1730 result = emit_ddxy(ctx, instr->op, src[0]);
1731 break;
1732 default:
1733 fprintf(stderr, "Unknown NIR alu instr: ");
1734 nir_print_instr(&instr->instr, stderr);
1735 fprintf(stderr, "\n");
1736 abort();
1737 }
1738
1739 if (result) {
1740 assert(instr->dest.dest.is_ssa);
1741 result = to_integer(ctx, result);
1742 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1743 result);
1744 }
1745 }
1746
1747 static void visit_load_const(struct nir_to_llvm_context *ctx,
1748 nir_load_const_instr *instr)
1749 {
1750 LLVMValueRef values[4], value = NULL;
1751 LLVMTypeRef element_type =
1752 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1753
1754 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1755 switch (instr->def.bit_size) {
1756 case 32:
1757 values[i] = LLVMConstInt(element_type,
1758 instr->value.u32[i], false);
1759 break;
1760 case 64:
1761 values[i] = LLVMConstInt(element_type,
1762 instr->value.u64[i], false);
1763 break;
1764 default:
1765 fprintf(stderr,
1766 "unsupported nir load_const bit_size: %d\n",
1767 instr->def.bit_size);
1768 abort();
1769 }
1770 }
1771 if (instr->def.num_components > 1) {
1772 value = LLVMConstVector(values, instr->def.num_components);
1773 } else
1774 value = values[0];
1775
1776 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1777 }
1778
1779 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1780 LLVMTypeRef type)
1781 {
1782 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1783 return LLVMBuildBitCast(ctx->builder, ptr,
1784 LLVMPointerType(type, addr_space), "");
1785 }
1786
1787 static LLVMValueRef
1788 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1789 {
1790 LLVMValueRef size =
1791 LLVMBuildExtractElement(ctx->builder, descriptor,
1792 LLVMConstInt(ctx->i32, 2, false), "");
1793
1794 /* VI only */
1795 if (ctx->options->chip_class >= VI && in_elements) {
1796 /* On VI, the descriptor contains the size in bytes,
1797 * but TXQ must return the size in elements.
1798 * The stride is always non-zero for resources using TXQ.
1799 */
1800 LLVMValueRef stride =
1801 LLVMBuildExtractElement(ctx->builder, descriptor,
1802 LLVMConstInt(ctx->i32, 1, false), "");
1803 stride = LLVMBuildLShr(ctx->builder, stride,
1804 LLVMConstInt(ctx->i32, 16, false), "");
1805 stride = LLVMBuildAnd(ctx->builder, stride,
1806 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1807
1808 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1809 }
1810 return size;
1811 }
1812
1813 /**
1814 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1815 * intrinsic names).
1816 */
1817 static void build_int_type_name(
1818 LLVMTypeRef type,
1819 char *buf, unsigned bufsize)
1820 {
1821 assert(bufsize >= 6);
1822
1823 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1824 snprintf(buf, bufsize, "v%ui32",
1825 LLVMGetVectorSize(type));
1826 else
1827 strcpy(buf, "i32");
1828 }
1829
1830 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1831 struct ac_tex_info *tinfo,
1832 nir_tex_instr *instr,
1833 const char *intr_name,
1834 unsigned coord_vgpr_index)
1835 {
1836 LLVMValueRef coord = tinfo->args[0];
1837 LLVMValueRef half_texel[2];
1838 int c;
1839
1840 //TODO Rect
1841 {
1842 LLVMValueRef txq_args[10];
1843 int txq_arg_count = 0;
1844 LLVMValueRef size;
1845 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1846 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1847 txq_args[txq_arg_count++] = tinfo->args[1];
1848 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1849 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1850 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1851 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1852 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1853 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1854 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1855 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1856 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1857 txq_args, txq_arg_count,
1858 AC_FUNC_ATTR_READNONE);
1859
1860 for (c = 0; c < 2; c++) {
1861 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1862 LLVMConstInt(ctx->i32, c, false), "");
1863 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1864 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1865 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1866 LLVMConstReal(ctx->f32, -0.5), "");
1867 }
1868 }
1869
1870 for (c = 0; c < 2; c++) {
1871 LLVMValueRef tmp;
1872 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1873 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1874 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1875 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1876 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1877 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1878 }
1879
1880 tinfo->args[0] = coord;
1881 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1882 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1883
1884 }
1885
1886 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1887 nir_tex_instr *instr,
1888 struct ac_tex_info *tinfo)
1889 {
1890 const char *name = "llvm.SI.image.sample";
1891 const char *infix = "";
1892 char intr_name[127];
1893 char type[64];
1894 bool is_shadow = instr->is_shadow;
1895 bool has_offset = tinfo->has_offset;
1896 switch (instr->op) {
1897 case nir_texop_txf:
1898 case nir_texop_txf_ms:
1899 case nir_texop_samples_identical:
1900 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1901 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1902 "llvm.SI.image.load.mip";
1903 is_shadow = false;
1904 has_offset = false;
1905 break;
1906 case nir_texop_txb:
1907 infix = ".b";
1908 break;
1909 case nir_texop_txl:
1910 infix = ".l";
1911 break;
1912 case nir_texop_txs:
1913 name = "llvm.SI.getresinfo";
1914 break;
1915 case nir_texop_query_levels:
1916 name = "llvm.SI.getresinfo";
1917 break;
1918 case nir_texop_tex:
1919 if (ctx->stage != MESA_SHADER_FRAGMENT)
1920 infix = ".lz";
1921 break;
1922 case nir_texop_txd:
1923 infix = ".d";
1924 break;
1925 case nir_texop_tg4:
1926 name = "llvm.SI.gather4";
1927 infix = ".lz";
1928 break;
1929 case nir_texop_lod:
1930 name = "llvm.SI.getlod";
1931 is_shadow = false;
1932 has_offset = false;
1933 break;
1934 default:
1935 break;
1936 }
1937
1938 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1939 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1940 has_offset ? ".o" : "", type);
1941
1942 if (instr->op == nir_texop_tg4) {
1943 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1944 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1945 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1946 (int)has_offset + (int)is_shadow);
1947 }
1948 }
1949 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1950 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1951
1952 }
1953
1954 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1955 nir_intrinsic_instr *instr)
1956 {
1957 LLVMValueRef index = get_src(ctx, instr->src[0]);
1958 unsigned desc_set = nir_intrinsic_desc_set(instr);
1959 unsigned binding = nir_intrinsic_binding(instr);
1960 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1961 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1962 unsigned base_offset = layout->binding[binding].offset;
1963 LLVMValueRef offset, stride;
1964
1965 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1966 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1967 desc_ptr = ctx->push_constants;
1968 base_offset = ctx->options->layout->push_constant_size;
1969 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1970 stride = LLVMConstInt(ctx->i32, 16, false);
1971 } else
1972 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1973
1974 offset = LLVMConstInt(ctx->i32, base_offset, false);
1975 index = LLVMBuildMul(ctx->builder, index, stride, "");
1976 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1977
1978 desc_ptr = build_gep0(ctx, desc_ptr, offset);
1979 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1980 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1981
1982 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1983 }
1984
1985 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1986 nir_intrinsic_instr *instr)
1987 {
1988 LLVMValueRef ptr, addr;
1989
1990 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1991 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1992
1993 ptr = build_gep0(ctx, ctx->push_constants, addr);
1994 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1995
1996 return LLVMBuildLoad(ctx->builder, ptr, "");
1997 }
1998
1999 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2000 nir_intrinsic_instr *instr)
2001 {
2002 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2003
2004 return get_buffer_size(ctx, desc, false);
2005 }
2006 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2007 nir_intrinsic_instr *instr)
2008 {
2009 const char *store_name;
2010 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2011 LLVMTypeRef data_type = ctx->f32;
2012 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2013 int components_32bit = elem_size_mult * instr->num_components;
2014 unsigned writemask = nir_intrinsic_write_mask(instr);
2015 LLVMValueRef base_data, base_offset;
2016 LLVMValueRef params[6];
2017
2018 if (ctx->stage == MESA_SHADER_FRAGMENT)
2019 ctx->shader_info->fs.writes_memory = true;
2020
2021 params[1] = get_src(ctx, instr->src[1]);
2022 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2023 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2024 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2025
2026 if (components_32bit > 1)
2027 data_type = LLVMVectorType(ctx->f32, components_32bit);
2028
2029 base_data = to_float(ctx, src_data);
2030 base_data = trim_vector(ctx, base_data, instr->num_components);
2031 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2032 data_type, "");
2033 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2034 while (writemask) {
2035 int start, count;
2036 LLVMValueRef data;
2037 LLVMValueRef offset;
2038 LLVMValueRef tmp;
2039 u_bit_scan_consecutive_range(&writemask, &start, &count);
2040
2041 /* Due to an LLVM limitation, split 3-element writes
2042 * into a 2-element and a 1-element write. */
2043 if (count == 3) {
2044 writemask |= 1 << (start + 2);
2045 count = 2;
2046 }
2047
2048 start *= elem_size_mult;
2049 count *= elem_size_mult;
2050
2051 if (count > 4) {
2052 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2053 count = 4;
2054 }
2055
2056 if (count == 4) {
2057 store_name = "llvm.amdgcn.buffer.store.v4f32";
2058 data = base_data;
2059 } else if (count == 2) {
2060 tmp = LLVMBuildExtractElement(ctx->builder,
2061 base_data, LLVMConstInt(ctx->i32, start, false), "");
2062 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2063 ctx->i32zero, "");
2064
2065 tmp = LLVMBuildExtractElement(ctx->builder,
2066 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2067 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2068 ctx->i32one, "");
2069 store_name = "llvm.amdgcn.buffer.store.v2f32";
2070
2071 } else {
2072 assert(count == 1);
2073 if (get_llvm_num_components(base_data) > 1)
2074 data = LLVMBuildExtractElement(ctx->builder, base_data,
2075 LLVMConstInt(ctx->i32, start, false), "");
2076 else
2077 data = base_data;
2078 store_name = "llvm.amdgcn.buffer.store.f32";
2079 }
2080
2081 offset = base_offset;
2082 if (start != 0) {
2083 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2084 }
2085 params[0] = data;
2086 params[3] = offset;
2087 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
2088 ctx->voidt, params, 6, 0);
2089 }
2090 }
2091
2092 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2093 nir_intrinsic_instr *instr)
2094 {
2095 const char *name;
2096 LLVMValueRef params[6];
2097 int arg_count = 0;
2098 if (ctx->stage == MESA_SHADER_FRAGMENT)
2099 ctx->shader_info->fs.writes_memory = true;
2100
2101 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2102 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2103 }
2104 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2105 params[arg_count++] = get_src(ctx, instr->src[0]);
2106 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2107 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2108 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2109
2110 switch (instr->intrinsic) {
2111 case nir_intrinsic_ssbo_atomic_add:
2112 name = "llvm.amdgcn.buffer.atomic.add";
2113 break;
2114 case nir_intrinsic_ssbo_atomic_imin:
2115 name = "llvm.amdgcn.buffer.atomic.smin";
2116 break;
2117 case nir_intrinsic_ssbo_atomic_umin:
2118 name = "llvm.amdgcn.buffer.atomic.umin";
2119 break;
2120 case nir_intrinsic_ssbo_atomic_imax:
2121 name = "llvm.amdgcn.buffer.atomic.smax";
2122 break;
2123 case nir_intrinsic_ssbo_atomic_umax:
2124 name = "llvm.amdgcn.buffer.atomic.umax";
2125 break;
2126 case nir_intrinsic_ssbo_atomic_and:
2127 name = "llvm.amdgcn.buffer.atomic.and";
2128 break;
2129 case nir_intrinsic_ssbo_atomic_or:
2130 name = "llvm.amdgcn.buffer.atomic.or";
2131 break;
2132 case nir_intrinsic_ssbo_atomic_xor:
2133 name = "llvm.amdgcn.buffer.atomic.xor";
2134 break;
2135 case nir_intrinsic_ssbo_atomic_exchange:
2136 name = "llvm.amdgcn.buffer.atomic.swap";
2137 break;
2138 case nir_intrinsic_ssbo_atomic_comp_swap:
2139 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2140 break;
2141 default:
2142 abort();
2143 }
2144
2145 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2146 }
2147
2148 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2149 nir_intrinsic_instr *instr)
2150 {
2151 const char *load_name;
2152 LLVMTypeRef data_type = ctx->f32;
2153 if (instr->num_components == 3)
2154 data_type = LLVMVectorType(ctx->f32, 4);
2155 else if (instr->num_components > 1)
2156 data_type = LLVMVectorType(ctx->f32, instr->num_components);
2157
2158 if (instr->num_components == 4 || instr->num_components == 3)
2159 load_name = "llvm.amdgcn.buffer.load.v4f32";
2160 else if (instr->num_components == 2)
2161 load_name = "llvm.amdgcn.buffer.load.v2f32";
2162 else if (instr->num_components == 1)
2163 load_name = "llvm.amdgcn.buffer.load.f32";
2164 else
2165 abort();
2166
2167 LLVMValueRef params[] = {
2168 get_src(ctx, instr->src[0]),
2169 LLVMConstInt(ctx->i32, 0, false),
2170 get_src(ctx, instr->src[1]),
2171 LLVMConstInt(ctx->i1, 0, false),
2172 LLVMConstInt(ctx->i1, 0, false),
2173 };
2174
2175 LLVMValueRef ret =
2176 ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2177
2178 if (instr->num_components == 3)
2179 ret = trim_vector(ctx, ret, 3);
2180
2181 return LLVMBuildBitCast(ctx->builder, ret,
2182 get_def_type(ctx, &instr->dest.ssa), "");
2183 }
2184
2185 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2186 nir_intrinsic_instr *instr)
2187 {
2188 LLVMValueRef results[4], ret;
2189 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2190 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2191
2192 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2193
2194 for (unsigned i = 0; i < instr->num_components; ++i) {
2195 LLVMValueRef params[] = {
2196 rsrc,
2197 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2198 offset, "")
2199 };
2200 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2201 params, 2, AC_FUNC_ATTR_READNONE);
2202 }
2203
2204
2205 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2206 return LLVMBuildBitCast(ctx->builder, ret,
2207 get_def_type(ctx, &instr->dest.ssa), "");
2208 }
2209
2210 static void
2211 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2212 bool vs_in, unsigned *vertex_index_out,
2213 unsigned *const_out, LLVMValueRef *indir_out)
2214 {
2215 unsigned const_offset = 0;
2216 LLVMValueRef offset = NULL;
2217
2218 if (vertex_index_out != NULL) {
2219 tail = tail->child;
2220 nir_deref_array *deref_array = nir_deref_as_array(tail);
2221 *vertex_index_out = deref_array->base_offset;
2222 }
2223
2224 while (tail->child != NULL) {
2225 const struct glsl_type *parent_type = tail->type;
2226 tail = tail->child;
2227
2228 if (tail->deref_type == nir_deref_type_array) {
2229 nir_deref_array *deref_array = nir_deref_as_array(tail);
2230 LLVMValueRef index, stride, local_offset;
2231 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2232
2233 const_offset += size * deref_array->base_offset;
2234 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2235 continue;
2236
2237 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2238 index = get_src(ctx, deref_array->indirect);
2239 stride = LLVMConstInt(ctx->i32, size, 0);
2240 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2241
2242 if (offset)
2243 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2244 else
2245 offset = local_offset;
2246 } else if (tail->deref_type == nir_deref_type_struct) {
2247 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2248
2249 for (unsigned i = 0; i < deref_struct->index; i++) {
2250 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2251 const_offset += glsl_count_attribute_slots(ft, vs_in);
2252 }
2253 } else
2254 unreachable("unsupported deref type");
2255
2256 }
2257
2258 if (const_offset && offset)
2259 offset = LLVMBuildAdd(ctx->builder, offset,
2260 LLVMConstInt(ctx->i32, const_offset, 0),
2261 "");
2262
2263 *const_out = const_offset;
2264 *indir_out = offset;
2265 }
2266
2267 static LLVMValueRef
2268 load_gs_input(struct nir_to_llvm_context *ctx,
2269 nir_intrinsic_instr *instr)
2270 {
2271 LLVMValueRef indir_index, vtx_offset;
2272 unsigned const_index;
2273 LLVMValueRef args[9];
2274 unsigned param, vtx_offset_param;
2275 LLVMValueRef value[4], result;
2276 unsigned vertex_index;
2277 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2278 false, &vertex_index,
2279 &const_index, &indir_index);
2280 vtx_offset_param = vertex_index;
2281 assert(vtx_offset_param < 6);
2282 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2283 LLVMConstInt(ctx->i32, 4, false), "");
2284
2285 for (unsigned i = 0; i < instr->num_components; i++) {
2286 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2287 args[0] = ctx->esgs_ring;
2288 args[1] = vtx_offset;
2289 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i) * 256, false);
2290 args[3] = ctx->i32zero;
2291 args[4] = ctx->i32one; /* OFFEN */
2292 args[5] = ctx->i32zero; /* IDXEN */
2293 args[6] = ctx->i32one; /* GLC */
2294 args[7] = ctx->i32zero; /* SLC */
2295 args[8] = ctx->i32zero; /* TFE */
2296
2297 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2298 ctx->i32, args, 9, AC_FUNC_ATTR_READONLY);
2299 }
2300 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2301
2302 return result;
2303 }
2304
2305 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2306 nir_intrinsic_instr *instr)
2307 {
2308 LLVMValueRef values[4];
2309 int idx = instr->variables[0]->var->data.driver_location;
2310 int ve = instr->dest.ssa.num_components;
2311 LLVMValueRef indir_index;
2312 unsigned const_index;
2313 switch (instr->variables[0]->var->data.mode) {
2314 case nir_var_shader_in:
2315 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2316 return load_gs_input(ctx, instr);
2317 }
2318 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2319 ctx->stage == MESA_SHADER_VERTEX, NULL,
2320 &const_index, &indir_index);
2321 for (unsigned chan = 0; chan < ve; chan++) {
2322 if (indir_index) {
2323 unsigned count = glsl_count_attribute_slots(
2324 instr->variables[0]->var->type,
2325 ctx->stage == MESA_SHADER_VERTEX);
2326 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2327 &ctx->ac, ctx->inputs + idx + chan, count,
2328 4, false);
2329
2330 values[chan] = LLVMBuildExtractElement(ctx->builder,
2331 tmp_vec,
2332 indir_index, "");
2333 } else
2334 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2335 }
2336 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2337 break;
2338 case nir_var_local:
2339 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2340 NULL, &const_index, &indir_index);
2341 for (unsigned chan = 0; chan < ve; chan++) {
2342 if (indir_index) {
2343 unsigned count = glsl_count_attribute_slots(
2344 instr->variables[0]->var->type, false);
2345 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2346 &ctx->ac, ctx->locals + idx + chan, count,
2347 4, true);
2348
2349 values[chan] = LLVMBuildExtractElement(ctx->builder,
2350 tmp_vec,
2351 indir_index, "");
2352 } else {
2353 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2354 }
2355 }
2356 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2357 case nir_var_shader_out:
2358 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2359 NULL, &const_index, &indir_index);
2360 for (unsigned chan = 0; chan < ve; chan++) {
2361 if (indir_index) {
2362 unsigned count = glsl_count_attribute_slots(
2363 instr->variables[0]->var->type, false);
2364 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2365 &ctx->ac, ctx->outputs + idx + chan, count,
2366 4, true);
2367
2368 values[chan] = LLVMBuildExtractElement(ctx->builder,
2369 tmp_vec,
2370 indir_index, "");
2371 } else {
2372 values[chan] = LLVMBuildLoad(ctx->builder,
2373 ctx->outputs[idx + chan + const_index * 4],
2374 "");
2375 }
2376 }
2377 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2378 case nir_var_shared: {
2379 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2380 NULL, &const_index, &indir_index);
2381 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2382 LLVMValueRef derived_ptr;
2383
2384 for (unsigned chan = 0; chan < ve; chan++) {
2385 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2386 if (indir_index)
2387 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2388 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2389 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2390 }
2391 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2392 }
2393 default:
2394 break;
2395 }
2396 return NULL;
2397 }
2398
2399 static void
2400 visit_store_var(struct nir_to_llvm_context *ctx,
2401 nir_intrinsic_instr *instr)
2402 {
2403 LLVMValueRef temp_ptr, value;
2404 int idx = instr->variables[0]->var->data.driver_location;
2405 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2406 int writemask = instr->const_index[0];
2407 LLVMValueRef indir_index;
2408 unsigned const_index;
2409 switch (instr->variables[0]->var->data.mode) {
2410 case nir_var_shader_out:
2411 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2412 NULL, &const_index, &indir_index);
2413 for (unsigned chan = 0; chan < 4; chan++) {
2414 int stride = 4;
2415 if (!(writemask & (1 << chan)))
2416 continue;
2417 if (get_llvm_num_components(src) == 1)
2418 value = src;
2419 else
2420 value = LLVMBuildExtractElement(ctx->builder, src,
2421 LLVMConstInt(ctx->i32,
2422 chan, false),
2423 "");
2424
2425 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2426 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2427 stride = 1;
2428 if (indir_index) {
2429 unsigned count = glsl_count_attribute_slots(
2430 instr->variables[0]->var->type, false);
2431 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2432 &ctx->ac, ctx->outputs + idx + chan, count,
2433 stride, true);
2434
2435 if (get_llvm_num_components(tmp_vec) > 1) {
2436 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2437 value, indir_index, "");
2438 } else
2439 tmp_vec = value;
2440 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2441 count, stride, tmp_vec);
2442
2443 } else {
2444 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2445
2446 LLVMBuildStore(ctx->builder, value, temp_ptr);
2447 }
2448 }
2449 break;
2450 case nir_var_local:
2451 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2452 NULL, &const_index, &indir_index);
2453 for (unsigned chan = 0; chan < 4; chan++) {
2454 if (!(writemask & (1 << chan)))
2455 continue;
2456
2457 if (get_llvm_num_components(src) == 1)
2458 value = src;
2459 else
2460 value = LLVMBuildExtractElement(ctx->builder, src,
2461 LLVMConstInt(ctx->i32, chan, false), "");
2462 if (indir_index) {
2463 unsigned count = glsl_count_attribute_slots(
2464 instr->variables[0]->var->type, false);
2465 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2466 &ctx->ac, ctx->locals + idx + chan, count,
2467 4, true);
2468
2469 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2470 value, indir_index, "");
2471 build_store_values_extended(ctx, ctx->locals + idx + chan,
2472 count, 4, tmp_vec);
2473 } else {
2474 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2475
2476 LLVMBuildStore(ctx->builder, value, temp_ptr);
2477 }
2478 }
2479 break;
2480 case nir_var_shared: {
2481 LLVMValueRef ptr;
2482 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2483 NULL, &const_index, &indir_index);
2484
2485 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2486 LLVMValueRef derived_ptr;
2487
2488 for (unsigned chan = 0; chan < 4; chan++) {
2489 if (!(writemask & (1 << chan)))
2490 continue;
2491
2492 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2493
2494 if (get_llvm_num_components(src) == 1)
2495 value = src;
2496 else
2497 value = LLVMBuildExtractElement(ctx->builder, src,
2498 LLVMConstInt(ctx->i32,
2499 chan, false),
2500 "");
2501
2502 if (indir_index)
2503 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2504
2505 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2506 LLVMBuildStore(ctx->builder,
2507 to_integer(ctx, value), derived_ptr);
2508 }
2509 break;
2510 }
2511 default:
2512 break;
2513 }
2514 }
2515
2516 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2517 {
2518 switch (dim) {
2519 case GLSL_SAMPLER_DIM_BUF:
2520 return 1;
2521 case GLSL_SAMPLER_DIM_1D:
2522 return array ? 2 : 1;
2523 case GLSL_SAMPLER_DIM_2D:
2524 return array ? 3 : 2;
2525 case GLSL_SAMPLER_DIM_MS:
2526 return array ? 4 : 3;
2527 case GLSL_SAMPLER_DIM_3D:
2528 case GLSL_SAMPLER_DIM_CUBE:
2529 return 3;
2530 case GLSL_SAMPLER_DIM_RECT:
2531 case GLSL_SAMPLER_DIM_SUBPASS:
2532 return 2;
2533 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2534 return 3;
2535 default:
2536 break;
2537 }
2538 return 0;
2539 }
2540
2541 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2542 nir_intrinsic_instr *instr)
2543 {
2544 const struct glsl_type *type = instr->variables[0]->var->type;
2545 if(instr->variables[0]->deref.child)
2546 type = instr->variables[0]->deref.child->type;
2547
2548 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2549 LLVMValueRef coords[4];
2550 LLVMValueRef masks[] = {
2551 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2552 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2553 };
2554 LLVMValueRef res;
2555 int count;
2556 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2557 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2558 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2559 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2560 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2561
2562 count = image_type_to_components_count(dim,
2563 glsl_sampler_type_is_array(type));
2564
2565 if (count == 1) {
2566 if (instr->src[0].ssa->num_components)
2567 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2568 else
2569 res = src0;
2570 } else {
2571 int chan;
2572 if (is_ms)
2573 count--;
2574 for (chan = 0; chan < count; ++chan) {
2575 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2576 }
2577
2578 if (add_frag_pos) {
2579 for (chan = 0; chan < count; ++chan)
2580 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2581 }
2582 if (is_ms) {
2583 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2584 count++;
2585 }
2586
2587 if (count == 3) {
2588 coords[3] = LLVMGetUndef(ctx->i32);
2589 count = 4;
2590 }
2591 res = ac_build_gather_values(&ctx->ac, coords, count);
2592 }
2593 return res;
2594 }
2595
2596 static void build_type_name_for_intr(
2597 LLVMTypeRef type,
2598 char *buf, unsigned bufsize)
2599 {
2600 LLVMTypeRef elem_type = type;
2601
2602 assert(bufsize >= 8);
2603
2604 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2605 int ret = snprintf(buf, bufsize, "v%u",
2606 LLVMGetVectorSize(type));
2607 if (ret < 0) {
2608 char *type_name = LLVMPrintTypeToString(type);
2609 fprintf(stderr, "Error building type name for: %s\n",
2610 type_name);
2611 return;
2612 }
2613 elem_type = LLVMGetElementType(type);
2614 buf += ret;
2615 bufsize -= ret;
2616 }
2617 switch (LLVMGetTypeKind(elem_type)) {
2618 default: break;
2619 case LLVMIntegerTypeKind:
2620 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2621 break;
2622 case LLVMFloatTypeKind:
2623 snprintf(buf, bufsize, "f32");
2624 break;
2625 case LLVMDoubleTypeKind:
2626 snprintf(buf, bufsize, "f64");
2627 break;
2628 }
2629 }
2630
2631 static void get_image_intr_name(const char *base_name,
2632 LLVMTypeRef data_type,
2633 LLVMTypeRef coords_type,
2634 LLVMTypeRef rsrc_type,
2635 char *out_name, unsigned out_len)
2636 {
2637 char coords_type_name[8];
2638
2639 build_type_name_for_intr(coords_type, coords_type_name,
2640 sizeof(coords_type_name));
2641
2642 if (HAVE_LLVM <= 0x0309) {
2643 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2644 } else {
2645 char data_type_name[8];
2646 char rsrc_type_name[8];
2647
2648 build_type_name_for_intr(data_type, data_type_name,
2649 sizeof(data_type_name));
2650 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2651 sizeof(rsrc_type_name));
2652 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2653 data_type_name, coords_type_name, rsrc_type_name);
2654 }
2655 }
2656
2657 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2658 nir_intrinsic_instr *instr)
2659 {
2660 LLVMValueRef params[7];
2661 LLVMValueRef res;
2662 char intrinsic_name[64];
2663 const nir_variable *var = instr->variables[0]->var;
2664 const struct glsl_type *type = var->type;
2665 if(instr->variables[0]->deref.child)
2666 type = instr->variables[0]->deref.child->type;
2667
2668 type = glsl_without_array(type);
2669 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2670 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2671 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2672 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2673 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2674 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2675 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2676 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2677 params, 5, 0);
2678
2679 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2680 res = to_integer(ctx, res);
2681 } else {
2682 bool is_da = glsl_sampler_type_is_array(type) ||
2683 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2684 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2685 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2686 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2687
2688 params[0] = get_image_coords(ctx, instr);
2689 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2690 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2691 if (HAVE_LLVM <= 0x0309) {
2692 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2693 params[4] = da;
2694 params[5] = glc;
2695 params[6] = slc;
2696 } else {
2697 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2698 params[3] = glc;
2699 params[4] = slc;
2700 params[5] = lwe;
2701 params[6] = da;
2702 }
2703
2704 get_image_intr_name("llvm.amdgcn.image.load",
2705 ctx->v4f32, /* vdata */
2706 LLVMTypeOf(params[0]), /* coords */
2707 LLVMTypeOf(params[1]), /* rsrc */
2708 intrinsic_name, sizeof(intrinsic_name));
2709
2710 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2711 params, 7, AC_FUNC_ATTR_READONLY);
2712 }
2713 return to_integer(ctx, res);
2714 }
2715
2716 static void visit_image_store(struct nir_to_llvm_context *ctx,
2717 nir_intrinsic_instr *instr)
2718 {
2719 LLVMValueRef params[8];
2720 char intrinsic_name[64];
2721 const nir_variable *var = instr->variables[0]->var;
2722 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2723 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2724 const struct glsl_type *type = glsl_without_array(var->type);
2725
2726 if (ctx->stage == MESA_SHADER_FRAGMENT)
2727 ctx->shader_info->fs.writes_memory = true;
2728
2729 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2730 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2731 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2732 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2733 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2734 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2735 params[4] = i1false; /* glc */
2736 params[5] = i1false; /* slc */
2737 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2738 params, 6, 0);
2739 } else {
2740 bool is_da = glsl_sampler_type_is_array(type) ||
2741 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2742 LLVMValueRef da = is_da ? i1true : i1false;
2743 LLVMValueRef glc = i1false;
2744 LLVMValueRef slc = i1false;
2745
2746 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2747 params[1] = get_image_coords(ctx, instr); /* coords */
2748 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2749 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2750 if (HAVE_LLVM <= 0x0309) {
2751 params[4] = i1false; /* r128 */
2752 params[5] = da;
2753 params[6] = glc;
2754 params[7] = slc;
2755 } else {
2756 LLVMValueRef lwe = i1false;
2757 params[4] = glc;
2758 params[5] = slc;
2759 params[6] = lwe;
2760 params[7] = da;
2761 }
2762
2763 get_image_intr_name("llvm.amdgcn.image.store",
2764 LLVMTypeOf(params[0]), /* vdata */
2765 LLVMTypeOf(params[1]), /* coords */
2766 LLVMTypeOf(params[2]), /* rsrc */
2767 intrinsic_name, sizeof(intrinsic_name));
2768
2769 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2770 params, 8, 0);
2771 }
2772
2773 }
2774
2775 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2776 nir_intrinsic_instr *instr)
2777 {
2778 LLVMValueRef params[6];
2779 int param_count = 0;
2780 const nir_variable *var = instr->variables[0]->var;
2781 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2782 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2783 const char *base_name = "llvm.amdgcn.image.atomic";
2784 const char *atomic_name;
2785 LLVMValueRef coords;
2786 char intrinsic_name[32], coords_type[8];
2787 const struct glsl_type *type = glsl_without_array(var->type);
2788
2789 if (ctx->stage == MESA_SHADER_FRAGMENT)
2790 ctx->shader_info->fs.writes_memory = true;
2791
2792 params[param_count++] = get_src(ctx, instr->src[2]);
2793 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2794 params[param_count++] = get_src(ctx, instr->src[3]);
2795
2796 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2797 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2798 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2799 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2800 params[param_count++] = ctx->i32zero; /* voffset */
2801 params[param_count++] = i1false; /* glc */
2802 params[param_count++] = i1false; /* slc */
2803 } else {
2804 bool da = glsl_sampler_type_is_array(type) ||
2805 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2806
2807 coords = params[param_count++] = get_image_coords(ctx, instr);
2808 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2809 params[param_count++] = i1false; /* r128 */
2810 params[param_count++] = da ? i1true : i1false; /* da */
2811 params[param_count++] = i1false; /* slc */
2812 }
2813
2814 switch (instr->intrinsic) {
2815 case nir_intrinsic_image_atomic_add:
2816 atomic_name = "add";
2817 break;
2818 case nir_intrinsic_image_atomic_min:
2819 atomic_name = "smin";
2820 break;
2821 case nir_intrinsic_image_atomic_max:
2822 atomic_name = "smax";
2823 break;
2824 case nir_intrinsic_image_atomic_and:
2825 atomic_name = "and";
2826 break;
2827 case nir_intrinsic_image_atomic_or:
2828 atomic_name = "or";
2829 break;
2830 case nir_intrinsic_image_atomic_xor:
2831 atomic_name = "xor";
2832 break;
2833 case nir_intrinsic_image_atomic_exchange:
2834 atomic_name = "swap";
2835 break;
2836 case nir_intrinsic_image_atomic_comp_swap:
2837 atomic_name = "cmpswap";
2838 break;
2839 default:
2840 abort();
2841 }
2842 build_int_type_name(LLVMTypeOf(coords),
2843 coords_type, sizeof(coords_type));
2844
2845 snprintf(intrinsic_name, sizeof(intrinsic_name),
2846 "%s.%s.%s", base_name, atomic_name, coords_type);
2847 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2848 }
2849
2850 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2851 nir_intrinsic_instr *instr)
2852 {
2853 LLVMValueRef res;
2854 LLVMValueRef params[10];
2855 const nir_variable *var = instr->variables[0]->var;
2856 const struct glsl_type *type = instr->variables[0]->var->type;
2857 bool da = glsl_sampler_type_is_array(var->type) ||
2858 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2859 if(instr->variables[0]->deref.child)
2860 type = instr->variables[0]->deref.child->type;
2861
2862 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2863 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2864 params[0] = ctx->i32zero;
2865 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2866 params[2] = LLVMConstInt(ctx->i32, 15, false);
2867 params[3] = ctx->i32zero;
2868 params[4] = ctx->i32zero;
2869 params[5] = da ? ctx->i32one : ctx->i32zero;
2870 params[6] = ctx->i32zero;
2871 params[7] = ctx->i32zero;
2872 params[8] = ctx->i32zero;
2873 params[9] = ctx->i32zero;
2874
2875 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2876 params, 10, AC_FUNC_ATTR_READNONE);
2877
2878 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2879 glsl_sampler_type_is_array(type)) {
2880 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2881 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2882 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2883 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2884 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2885 }
2886 return res;
2887 }
2888
2889 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2890 {
2891 LLVMValueRef args[1] = {
2892 LLVMConstInt(ctx->i32, 0xf70, false),
2893 };
2894 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2895 ctx->voidt, args, 1, 0);
2896 }
2897
2898 static void emit_barrier(struct nir_to_llvm_context *ctx)
2899 {
2900 // TODO tess
2901 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2902 ctx->voidt, NULL, 0, 0);
2903 }
2904
2905 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2906 nir_intrinsic_instr *instr)
2907 {
2908 LLVMValueRef cond;
2909 ctx->shader_info->fs.can_discard = true;
2910
2911 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2912 get_src(ctx, instr->src[0]),
2913 ctx->i32zero, "");
2914
2915 cond = LLVMBuildSelect(ctx->builder, cond,
2916 LLVMConstReal(ctx->f32, -1.0f),
2917 ctx->f32zero, "");
2918 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2919 ctx->voidt,
2920 &cond, 1, 0);
2921 }
2922
2923 static LLVMValueRef
2924 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2925 {
2926 LLVMValueRef result;
2927 LLVMValueRef thread_id = get_thread_id(ctx);
2928 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2929 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2930
2931 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2932 }
2933
2934 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2935 nir_intrinsic_instr *instr)
2936 {
2937 LLVMValueRef ptr, result;
2938 int idx = instr->variables[0]->var->data.driver_location;
2939 LLVMValueRef src = get_src(ctx, instr->src[0]);
2940 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2941
2942 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2943 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2944 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2945 ptr, src, src1,
2946 LLVMAtomicOrderingSequentiallyConsistent,
2947 LLVMAtomicOrderingSequentiallyConsistent,
2948 false);
2949 } else {
2950 LLVMAtomicRMWBinOp op;
2951 switch (instr->intrinsic) {
2952 case nir_intrinsic_var_atomic_add:
2953 op = LLVMAtomicRMWBinOpAdd;
2954 break;
2955 case nir_intrinsic_var_atomic_umin:
2956 op = LLVMAtomicRMWBinOpUMin;
2957 break;
2958 case nir_intrinsic_var_atomic_umax:
2959 op = LLVMAtomicRMWBinOpUMax;
2960 break;
2961 case nir_intrinsic_var_atomic_imin:
2962 op = LLVMAtomicRMWBinOpMin;
2963 break;
2964 case nir_intrinsic_var_atomic_imax:
2965 op = LLVMAtomicRMWBinOpMax;
2966 break;
2967 case nir_intrinsic_var_atomic_and:
2968 op = LLVMAtomicRMWBinOpAnd;
2969 break;
2970 case nir_intrinsic_var_atomic_or:
2971 op = LLVMAtomicRMWBinOpOr;
2972 break;
2973 case nir_intrinsic_var_atomic_xor:
2974 op = LLVMAtomicRMWBinOpXor;
2975 break;
2976 case nir_intrinsic_var_atomic_exchange:
2977 op = LLVMAtomicRMWBinOpXchg;
2978 break;
2979 default:
2980 return NULL;
2981 }
2982
2983 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2984 LLVMAtomicOrderingSequentiallyConsistent,
2985 false);
2986 }
2987 return result;
2988 }
2989
2990 #define INTERP_CENTER 0
2991 #define INTERP_CENTROID 1
2992 #define INTERP_SAMPLE 2
2993
2994 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2995 enum glsl_interp_mode interp, unsigned location)
2996 {
2997 switch (interp) {
2998 case INTERP_MODE_FLAT:
2999 default:
3000 return NULL;
3001 case INTERP_MODE_SMOOTH:
3002 case INTERP_MODE_NONE:
3003 if (location == INTERP_CENTER)
3004 return ctx->persp_center;
3005 else if (location == INTERP_CENTROID)
3006 return ctx->persp_centroid;
3007 else if (location == INTERP_SAMPLE)
3008 return ctx->persp_sample;
3009 break;
3010 case INTERP_MODE_NOPERSPECTIVE:
3011 if (location == INTERP_CENTER)
3012 return ctx->linear_center;
3013 else if (location == INTERP_CENTROID)
3014 return ctx->linear_centroid;
3015 else if (location == INTERP_SAMPLE)
3016 return ctx->linear_sample;
3017 break;
3018 }
3019 return NULL;
3020 }
3021
3022 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3023 LLVMValueRef sample_id)
3024 {
3025 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
3026 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
3027 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
3028 LLVMValueRef result[2];
3029
3030 result[0] = build_indexed_load_const(ctx, ctx->sample_positions, offset0);
3031 result[1] = build_indexed_load_const(ctx, ctx->sample_positions, offset1);
3032
3033 return ac_build_gather_values(&ctx->ac, result, 2);
3034 }
3035
3036 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3037 {
3038 LLVMValueRef values[2];
3039
3040 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3041 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3042 return ac_build_gather_values(&ctx->ac, values, 2);
3043 }
3044
3045 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3046 nir_intrinsic_instr *instr)
3047 {
3048 LLVMValueRef result[2];
3049 LLVMValueRef interp_param, attr_number;
3050 unsigned location;
3051 unsigned chan;
3052 LLVMValueRef src_c0, src_c1;
3053 const char *intr_name;
3054 LLVMValueRef src0;
3055 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3056 switch (instr->intrinsic) {
3057 case nir_intrinsic_interp_var_at_centroid:
3058 location = INTERP_CENTROID;
3059 break;
3060 case nir_intrinsic_interp_var_at_sample:
3061 case nir_intrinsic_interp_var_at_offset:
3062 location = INTERP_SAMPLE;
3063 src0 = get_src(ctx, instr->src[0]);
3064 break;
3065 default:
3066 break;
3067 }
3068
3069 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3070 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3071 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3072 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3073 LLVMValueRef sample_position;
3074 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3075
3076 /* fetch sample ID */
3077 sample_position = load_sample_position(ctx, src0);
3078
3079 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3080 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3081 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3082 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3083 }
3084 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3085 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3086
3087 if (location == INTERP_SAMPLE) {
3088 LLVMValueRef ij_out[2];
3089 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3090
3091 /*
3092 * take the I then J parameters, and the DDX/Y for it, and
3093 * calculate the IJ inputs for the interpolator.
3094 * temp1 = ddx * offset/sample.x + I;
3095 * interp_param.I = ddy * offset/sample.y + temp1;
3096 * temp1 = ddx * offset/sample.x + J;
3097 * interp_param.J = ddy * offset/sample.y + temp1;
3098 */
3099 for (unsigned i = 0; i < 2; i++) {
3100 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3101 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3102 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3103 ddxy_out, ix_ll, "");
3104 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3105 ddxy_out, iy_ll, "");
3106 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3107 interp_param, ix_ll, "");
3108 LLVMValueRef temp1, temp2;
3109
3110 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3111 ctx->f32, "");
3112
3113 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3114 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3115
3116 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3117 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3118
3119 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3120 temp2, ctx->i32, "");
3121 }
3122 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3123
3124 }
3125 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3126 for (chan = 0; chan < 2; chan++) {
3127 LLVMValueRef args[4];
3128 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3129
3130 args[0] = llvm_chan;
3131 args[1] = attr_number;
3132 args[2] = ctx->prim_mask;
3133 args[3] = interp_param;
3134 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
3135 ctx->f32, args, args[3] ? 4 : 3,
3136 AC_FUNC_ATTR_READNONE);
3137 }
3138 return ac_build_gather_values(&ctx->ac, result, 2);
3139 }
3140
3141 static void
3142 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3143 nir_intrinsic_instr *instr)
3144 {
3145 LLVMValueRef gs_next_vertex;
3146 LLVMValueRef can_emit, kill;
3147 LLVMValueRef args[2];
3148 int idx;
3149
3150 assert(instr->const_index[0] == 0);
3151 /* Write vertex attribute values to GSVS ring */
3152 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3153 ctx->gs_next_vertex,
3154 "");
3155
3156 /* If this thread has already emitted the declared maximum number of
3157 * vertices, kill it: excessive vertex emissions are not supposed to
3158 * have any effect, and GS threads have no externally observable
3159 * effects other than emitting vertices.
3160 */
3161 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3162 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3163
3164 kill = LLVMBuildSelect(ctx->builder, can_emit,
3165 LLVMConstReal(ctx->f32, 1.0f),
3166 LLVMConstReal(ctx->f32, -1.0f), "");
3167 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3168 ctx->voidt, &kill, 1, 0);
3169
3170 /* loop num outputs */
3171 idx = 0;
3172 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3173 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3174 if (!(ctx->output_mask & (1ull << i)))
3175 continue;
3176
3177 for (unsigned j = 0; j < 4; j++) {
3178 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3179 out_ptr[j], "");
3180 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (idx * 4 + j) * ctx->gs_max_out_vertices, false);
3181 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3182 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3183
3184 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3185
3186 build_tbuffer_store(ctx, ctx->gsvs_ring,
3187 out_val, 1,
3188 voffset, ctx->gs2vs_offset, 0,
3189 V_008F0C_BUF_DATA_FORMAT_32,
3190 V_008F0C_BUF_NUM_FORMAT_UINT,
3191 1, 0, 1, 1, 0);
3192 }
3193 idx++;
3194 }
3195
3196 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3197 ctx->i32one, "");
3198 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3199 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (0 << 8), false);
3200 args[1] = ctx->gs_wave_id;
3201 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
3202 ctx->voidt, args, 2, 0);
3203 }
3204
3205 static void
3206 visit_end_primitive(struct nir_to_llvm_context *ctx,
3207 nir_intrinsic_instr *instr)
3208 {
3209 LLVMValueRef args[2];
3210
3211 assert(instr->const_index[0] == 0);
3212 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_CUT | SENDMSG_GS | (0 << 8), false);
3213 args[1] = ctx->gs_wave_id;
3214
3215 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg", ctx->voidt,
3216 args, 2, 0);
3217 }
3218
3219 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3220 nir_intrinsic_instr *instr)
3221 {
3222 LLVMValueRef result = NULL;
3223
3224 switch (instr->intrinsic) {
3225 case nir_intrinsic_load_work_group_id: {
3226 result = ctx->workgroup_ids;
3227 break;
3228 }
3229 case nir_intrinsic_load_base_vertex: {
3230 result = ctx->base_vertex;
3231 break;
3232 }
3233 case nir_intrinsic_load_vertex_id_zero_base: {
3234 result = ctx->vertex_id;
3235 break;
3236 }
3237 case nir_intrinsic_load_local_invocation_id: {
3238 result = ctx->local_invocation_ids;
3239 break;
3240 }
3241 case nir_intrinsic_load_base_instance:
3242 result = ctx->start_instance;
3243 break;
3244 case nir_intrinsic_load_invocation_id:
3245 result = ctx->gs_invocation_id;
3246 break;
3247 case nir_intrinsic_load_primitive_id:
3248 if (ctx->stage == MESA_SHADER_GEOMETRY)
3249 result = ctx->gs_prim_id;
3250 else
3251 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3252 break;
3253 case nir_intrinsic_load_sample_id:
3254 ctx->shader_info->fs.force_persample = true;
3255 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3256 break;
3257 case nir_intrinsic_load_sample_pos:
3258 ctx->shader_info->fs.force_persample = true;
3259 result = load_sample_pos(ctx);
3260 break;
3261 case nir_intrinsic_load_front_face:
3262 result = ctx->front_face;
3263 break;
3264 case nir_intrinsic_load_instance_id:
3265 result = ctx->instance_id;
3266 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3267 ctx->shader_info->vs.vgpr_comp_cnt);
3268 break;
3269 case nir_intrinsic_load_num_work_groups:
3270 result = ctx->num_work_groups;
3271 break;
3272 case nir_intrinsic_load_local_invocation_index:
3273 result = visit_load_local_invocation_index(ctx);
3274 break;
3275 case nir_intrinsic_load_push_constant:
3276 result = visit_load_push_constant(ctx, instr);
3277 break;
3278 case nir_intrinsic_vulkan_resource_index:
3279 result = visit_vulkan_resource_index(ctx, instr);
3280 break;
3281 case nir_intrinsic_store_ssbo:
3282 visit_store_ssbo(ctx, instr);
3283 break;
3284 case nir_intrinsic_load_ssbo:
3285 result = visit_load_buffer(ctx, instr);
3286 break;
3287 case nir_intrinsic_ssbo_atomic_add:
3288 case nir_intrinsic_ssbo_atomic_imin:
3289 case nir_intrinsic_ssbo_atomic_umin:
3290 case nir_intrinsic_ssbo_atomic_imax:
3291 case nir_intrinsic_ssbo_atomic_umax:
3292 case nir_intrinsic_ssbo_atomic_and:
3293 case nir_intrinsic_ssbo_atomic_or:
3294 case nir_intrinsic_ssbo_atomic_xor:
3295 case nir_intrinsic_ssbo_atomic_exchange:
3296 case nir_intrinsic_ssbo_atomic_comp_swap:
3297 result = visit_atomic_ssbo(ctx, instr);
3298 break;
3299 case nir_intrinsic_load_ubo:
3300 result = visit_load_ubo_buffer(ctx, instr);
3301 break;
3302 case nir_intrinsic_get_buffer_size:
3303 result = visit_get_buffer_size(ctx, instr);
3304 break;
3305 case nir_intrinsic_load_var:
3306 result = visit_load_var(ctx, instr);
3307 break;
3308 case nir_intrinsic_store_var:
3309 visit_store_var(ctx, instr);
3310 break;
3311 case nir_intrinsic_image_load:
3312 result = visit_image_load(ctx, instr);
3313 break;
3314 case nir_intrinsic_image_store:
3315 visit_image_store(ctx, instr);
3316 break;
3317 case nir_intrinsic_image_atomic_add:
3318 case nir_intrinsic_image_atomic_min:
3319 case nir_intrinsic_image_atomic_max:
3320 case nir_intrinsic_image_atomic_and:
3321 case nir_intrinsic_image_atomic_or:
3322 case nir_intrinsic_image_atomic_xor:
3323 case nir_intrinsic_image_atomic_exchange:
3324 case nir_intrinsic_image_atomic_comp_swap:
3325 result = visit_image_atomic(ctx, instr);
3326 break;
3327 case nir_intrinsic_image_size:
3328 result = visit_image_size(ctx, instr);
3329 break;
3330 case nir_intrinsic_discard:
3331 ctx->shader_info->fs.can_discard = true;
3332 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3333 ctx->voidt,
3334 NULL, 0, 0);
3335 break;
3336 case nir_intrinsic_discard_if:
3337 emit_discard_if(ctx, instr);
3338 break;
3339 case nir_intrinsic_memory_barrier:
3340 emit_waitcnt(ctx);
3341 break;
3342 case nir_intrinsic_barrier:
3343 emit_barrier(ctx);
3344 break;
3345 case nir_intrinsic_var_atomic_add:
3346 case nir_intrinsic_var_atomic_imin:
3347 case nir_intrinsic_var_atomic_umin:
3348 case nir_intrinsic_var_atomic_imax:
3349 case nir_intrinsic_var_atomic_umax:
3350 case nir_intrinsic_var_atomic_and:
3351 case nir_intrinsic_var_atomic_or:
3352 case nir_intrinsic_var_atomic_xor:
3353 case nir_intrinsic_var_atomic_exchange:
3354 case nir_intrinsic_var_atomic_comp_swap:
3355 result = visit_var_atomic(ctx, instr);
3356 break;
3357 case nir_intrinsic_interp_var_at_centroid:
3358 case nir_intrinsic_interp_var_at_sample:
3359 case nir_intrinsic_interp_var_at_offset:
3360 result = visit_interp(ctx, instr);
3361 break;
3362 case nir_intrinsic_emit_vertex:
3363 visit_emit_vertex(ctx, instr);
3364 break;
3365 case nir_intrinsic_end_primitive:
3366 visit_end_primitive(ctx, instr);
3367 break;
3368 default:
3369 fprintf(stderr, "Unknown intrinsic: ");
3370 nir_print_instr(&instr->instr, stderr);
3371 fprintf(stderr, "\n");
3372 break;
3373 }
3374 if (result) {
3375 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3376 }
3377 }
3378
3379 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3380 nir_deref_var *deref,
3381 enum desc_type desc_type)
3382 {
3383 unsigned desc_set = deref->var->data.descriptor_set;
3384 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3385 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3386 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3387 unsigned offset = binding->offset;
3388 unsigned stride = binding->size;
3389 unsigned type_size;
3390 LLVMBuilderRef builder = ctx->builder;
3391 LLVMTypeRef type;
3392 LLVMValueRef index = NULL;
3393
3394 assert(deref->var->data.binding < layout->binding_count);
3395
3396 switch (desc_type) {
3397 case DESC_IMAGE:
3398 type = ctx->v8i32;
3399 type_size = 32;
3400 break;
3401 case DESC_FMASK:
3402 type = ctx->v8i32;
3403 offset += 32;
3404 type_size = 32;
3405 break;
3406 case DESC_SAMPLER:
3407 type = ctx->v4i32;
3408 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3409 offset += 64;
3410
3411 type_size = 16;
3412 break;
3413 case DESC_BUFFER:
3414 type = ctx->v4i32;
3415 type_size = 16;
3416 break;
3417 default:
3418 unreachable("invalid desc_type\n");
3419 }
3420
3421 if (deref->deref.child) {
3422 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3423
3424 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3425 offset += child->base_offset * stride;
3426 if (child->deref_array_type == nir_deref_array_type_indirect) {
3427 index = get_src(ctx, child->indirect);
3428 }
3429 }
3430
3431 assert(stride % type_size == 0);
3432
3433 if (!index)
3434 index = ctx->i32zero;
3435
3436 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3437
3438 list = build_gep0(ctx, list, LLVMConstInt(ctx->i32, offset, 0));
3439 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3440
3441 return build_indexed_load_const(ctx, list, index);
3442 }
3443
3444 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3445 struct ac_tex_info *tinfo,
3446 nir_tex_instr *instr,
3447 nir_texop op,
3448 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3449 LLVMValueRef *param, unsigned count,
3450 unsigned dmask)
3451 {
3452 int num_args;
3453 unsigned is_rect = 0;
3454 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3455
3456 if (op == nir_texop_lod)
3457 da = false;
3458 /* Pad to power of two vector */
3459 while (count < util_next_power_of_two(count))
3460 param[count++] = LLVMGetUndef(ctx->i32);
3461
3462 if (count > 1)
3463 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3464 else
3465 tinfo->args[0] = param[0];
3466
3467 tinfo->args[1] = res_ptr;
3468 num_args = 2;
3469
3470 if (op == nir_texop_txf ||
3471 op == nir_texop_txf_ms ||
3472 op == nir_texop_query_levels ||
3473 op == nir_texop_texture_samples ||
3474 op == nir_texop_txs)
3475 tinfo->dst_type = ctx->v4i32;
3476 else {
3477 tinfo->dst_type = ctx->v4f32;
3478 tinfo->args[num_args++] = samp_ptr;
3479 }
3480
3481 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3482 tinfo->args[0] = res_ptr;
3483 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3484 tinfo->args[2] = param[0];
3485 tinfo->arg_count = 3;
3486 return;
3487 }
3488
3489 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3490 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3491 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3492 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3493 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3494 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3495 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3496 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3497
3498 tinfo->arg_count = num_args;
3499 }
3500
3501 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3502 *
3503 * SI-CI:
3504 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3505 * filtering manually. The driver sets img7 to a mask clearing
3506 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3507 * s_and_b32 samp0, samp0, img7
3508 *
3509 * VI:
3510 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3511 */
3512 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3513 LLVMValueRef res, LLVMValueRef samp)
3514 {
3515 LLVMBuilderRef builder = ctx->builder;
3516 LLVMValueRef img7, samp0;
3517
3518 if (ctx->options->chip_class >= VI)
3519 return samp;
3520
3521 img7 = LLVMBuildExtractElement(builder, res,
3522 LLVMConstInt(ctx->i32, 7, 0), "");
3523 samp0 = LLVMBuildExtractElement(builder, samp,
3524 LLVMConstInt(ctx->i32, 0, 0), "");
3525 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3526 return LLVMBuildInsertElement(builder, samp, samp0,
3527 LLVMConstInt(ctx->i32, 0, 0), "");
3528 }
3529
3530 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3531 nir_tex_instr *instr,
3532 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3533 LLVMValueRef *fmask_ptr)
3534 {
3535 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3536 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3537 else
3538 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3539 if (samp_ptr) {
3540 if (instr->sampler)
3541 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3542 else
3543 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3544 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3545 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3546 }
3547 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3548 instr->op == nir_texop_samples_identical))
3549 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3550 }
3551
3552 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3553 LLVMValueRef coord)
3554 {
3555 coord = to_float(ctx, coord);
3556 coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3557 coord = to_integer(ctx, coord);
3558 return coord;
3559 }
3560
3561 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3562 {
3563 LLVMValueRef result = NULL;
3564 struct ac_tex_info tinfo = { 0 };
3565 unsigned dmask = 0xf;
3566 LLVMValueRef address[16];
3567 LLVMValueRef coords[5];
3568 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3569 LLVMValueRef bias = NULL, offsets = NULL;
3570 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3571 LLVMValueRef ddx = NULL, ddy = NULL;
3572 LLVMValueRef derivs[6];
3573 unsigned chan, count = 0;
3574 unsigned const_src = 0, num_deriv_comp = 0;
3575
3576 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3577
3578 for (unsigned i = 0; i < instr->num_srcs; i++) {
3579 switch (instr->src[i].src_type) {
3580 case nir_tex_src_coord:
3581 coord = get_src(ctx, instr->src[i].src);
3582 break;
3583 case nir_tex_src_projector:
3584 break;
3585 case nir_tex_src_comparator:
3586 comparator = get_src(ctx, instr->src[i].src);
3587 break;
3588 case nir_tex_src_offset:
3589 offsets = get_src(ctx, instr->src[i].src);
3590 const_src = i;
3591 break;
3592 case nir_tex_src_bias:
3593 bias = get_src(ctx, instr->src[i].src);
3594 break;
3595 case nir_tex_src_lod:
3596 lod = get_src(ctx, instr->src[i].src);
3597 break;
3598 case nir_tex_src_ms_index:
3599 sample_index = get_src(ctx, instr->src[i].src);
3600 break;
3601 case nir_tex_src_ms_mcs:
3602 break;
3603 case nir_tex_src_ddx:
3604 ddx = get_src(ctx, instr->src[i].src);
3605 num_deriv_comp = instr->src[i].src.ssa->num_components;
3606 break;
3607 case nir_tex_src_ddy:
3608 ddy = get_src(ctx, instr->src[i].src);
3609 break;
3610 case nir_tex_src_texture_offset:
3611 case nir_tex_src_sampler_offset:
3612 case nir_tex_src_plane:
3613 default:
3614 break;
3615 }
3616 }
3617
3618 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3619 result = get_buffer_size(ctx, res_ptr, false);
3620 goto write_result;
3621 }
3622
3623 if (instr->op == nir_texop_texture_samples) {
3624 LLVMValueRef res, samples, is_msaa;
3625 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3626 samples = LLVMBuildExtractElement(ctx->builder, res,
3627 LLVMConstInt(ctx->i32, 3, false), "");
3628 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3629 LLVMConstInt(ctx->i32, 28, false), "");
3630 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3631 LLVMConstInt(ctx->i32, 0xe, false), "");
3632 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3633 LLVMConstInt(ctx->i32, 0xe, false), "");
3634
3635 samples = LLVMBuildLShr(ctx->builder, samples,
3636 LLVMConstInt(ctx->i32, 16, false), "");
3637 samples = LLVMBuildAnd(ctx->builder, samples,
3638 LLVMConstInt(ctx->i32, 0xf, false), "");
3639 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3640 samples, "");
3641 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3642 ctx->i32one, "");
3643 result = samples;
3644 goto write_result;
3645 }
3646
3647 if (coord)
3648 for (chan = 0; chan < instr->coord_components; chan++)
3649 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3650
3651 if (offsets && instr->op != nir_texop_txf) {
3652 LLVMValueRef offset[3], pack;
3653 for (chan = 0; chan < 3; ++chan)
3654 offset[chan] = ctx->i32zero;
3655
3656 tinfo.has_offset = true;
3657 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3658 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3659 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3660 LLVMConstInt(ctx->i32, 0x3f, false), "");
3661 if (chan)
3662 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3663 LLVMConstInt(ctx->i32, chan * 8, false), "");
3664 }
3665 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3666 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3667 address[count++] = pack;
3668
3669 }
3670 /* pack LOD bias value */
3671 if (instr->op == nir_texop_txb && bias) {
3672 address[count++] = bias;
3673 }
3674
3675 /* Pack depth comparison value */
3676 if (instr->is_shadow && comparator) {
3677 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3678 }
3679
3680 /* pack derivatives */
3681 if (ddx || ddy) {
3682 switch (instr->sampler_dim) {
3683 case GLSL_SAMPLER_DIM_3D:
3684 case GLSL_SAMPLER_DIM_CUBE:
3685 num_deriv_comp = 3;
3686 break;
3687 case GLSL_SAMPLER_DIM_2D:
3688 default:
3689 num_deriv_comp = 2;
3690 break;
3691 case GLSL_SAMPLER_DIM_1D:
3692 num_deriv_comp = 1;
3693 break;
3694 }
3695
3696 for (unsigned i = 0; i < num_deriv_comp; i++) {
3697 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3698 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3699 }
3700 }
3701
3702 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3703 for (chan = 0; chan < instr->coord_components; chan++)
3704 coords[chan] = to_float(ctx, coords[chan]);
3705 if (instr->coord_components == 3)
3706 coords[3] = LLVMGetUndef(ctx->f32);
3707 ac_prepare_cube_coords(&ctx->ac,
3708 instr->op == nir_texop_txd, instr->is_array,
3709 coords, derivs);
3710 if (num_deriv_comp)
3711 num_deriv_comp--;
3712 }
3713
3714 if (ddx || ddy) {
3715 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3716 address[count++] = derivs[i];
3717 }
3718
3719 /* Pack texture coordinates */
3720 if (coord) {
3721 address[count++] = coords[0];
3722 if (instr->coord_components > 1) {
3723 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3724 coords[1] = apply_round_slice(ctx, coords[1]);
3725 }
3726 address[count++] = coords[1];
3727 }
3728 if (instr->coord_components > 2) {
3729 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3730 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3731 coords[2] = apply_round_slice(ctx, coords[2]);
3732 }
3733 address[count++] = coords[2];
3734 }
3735 }
3736
3737 /* Pack LOD */
3738 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3739 address[count++] = lod;
3740 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3741 address[count++] = sample_index;
3742 } else if(instr->op == nir_texop_txs) {
3743 count = 0;
3744 if (lod)
3745 address[count++] = lod;
3746 else
3747 address[count++] = ctx->i32zero;
3748 }
3749
3750 for (chan = 0; chan < count; chan++) {
3751 address[chan] = LLVMBuildBitCast(ctx->builder,
3752 address[chan], ctx->i32, "");
3753 }
3754
3755 if (instr->op == nir_texop_samples_identical) {
3756 LLVMValueRef txf_address[4];
3757 struct ac_tex_info txf_info = { 0 };
3758 unsigned txf_count = count;
3759 memcpy(txf_address, address, sizeof(txf_address));
3760
3761 if (!instr->is_array)
3762 txf_address[2] = ctx->i32zero;
3763 txf_address[3] = ctx->i32zero;
3764
3765 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3766 fmask_ptr, NULL,
3767 txf_address, txf_count, 0xf);
3768
3769 result = build_tex_intrinsic(ctx, instr, &txf_info);
3770
3771 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3772 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3773 goto write_result;
3774 }
3775
3776 /* Adjust the sample index according to FMASK.
3777 *
3778 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3779 * which is the identity mapping. Each nibble says which physical sample
3780 * should be fetched to get that sample.
3781 *
3782 * For example, 0x11111100 means there are only 2 samples stored and
3783 * the second sample covers 3/4 of the pixel. When reading samples 0
3784 * and 1, return physical sample 0 (determined by the first two 0s
3785 * in FMASK), otherwise return physical sample 1.
3786 *
3787 * The sample index should be adjusted as follows:
3788 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3789 */
3790 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS) {
3791 LLVMValueRef txf_address[4];
3792 struct ac_tex_info txf_info = { 0 };
3793 unsigned txf_count = count;
3794 memcpy(txf_address, address, sizeof(txf_address));
3795
3796 if (!instr->is_array)
3797 txf_address[2] = ctx->i32zero;
3798 txf_address[3] = ctx->i32zero;
3799
3800 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3801 fmask_ptr, NULL,
3802 txf_address, txf_count, 0xf);
3803
3804 result = build_tex_intrinsic(ctx, instr, &txf_info);
3805 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3806 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3807
3808 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3809 result,
3810 ctx->i32zero, "");
3811
3812 unsigned sample_chan = instr->is_array ? 3 : 2;
3813
3814 LLVMValueRef sample_index4 =
3815 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3816 LLVMValueRef shifted_fmask =
3817 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3818 LLVMValueRef final_sample =
3819 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3820
3821 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3822 * resource descriptor is 0 (invalid),
3823 */
3824 LLVMValueRef fmask_desc =
3825 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3826 ctx->v8i32, "");
3827
3828 LLVMValueRef fmask_word1 =
3829 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3830 ctx->i32one, "");
3831
3832 LLVMValueRef word1_is_nonzero =
3833 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3834 fmask_word1, ctx->i32zero, "");
3835
3836 /* Replace the MSAA sample index. */
3837 address[sample_chan] =
3838 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3839 final_sample, address[sample_chan], "");
3840 }
3841
3842 if (offsets && instr->op == nir_texop_txf) {
3843 nir_const_value *const_offset =
3844 nir_src_as_const_value(instr->src[const_src].src);
3845 int num_offsets = instr->src[const_src].src.ssa->num_components;
3846 assert(const_offset);
3847 num_offsets = MIN2(num_offsets, instr->coord_components);
3848 if (num_offsets > 2)
3849 address[2] = LLVMBuildAdd(ctx->builder,
3850 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3851 if (num_offsets > 1)
3852 address[1] = LLVMBuildAdd(ctx->builder,
3853 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3854 address[0] = LLVMBuildAdd(ctx->builder,
3855 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3856
3857 }
3858
3859 /* TODO TG4 support */
3860 if (instr->op == nir_texop_tg4) {
3861 if (instr->is_shadow)
3862 dmask = 1;
3863 else
3864 dmask = 1 << instr->component;
3865 }
3866 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3867 res_ptr, samp_ptr, address, count, dmask);
3868
3869 result = build_tex_intrinsic(ctx, instr, &tinfo);
3870
3871 if (instr->op == nir_texop_query_levels)
3872 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3873 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3874 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3875 else if (instr->op == nir_texop_txs &&
3876 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3877 instr->is_array) {
3878 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3879 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3880 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3881 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3882 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3883 } else if (instr->dest.ssa.num_components != 4)
3884 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3885
3886 write_result:
3887 if (result) {
3888 assert(instr->dest.is_ssa);
3889 result = to_integer(ctx, result);
3890 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3891 }
3892 }
3893
3894
3895 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3896 {
3897 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3898 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3899
3900 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3901 _mesa_hash_table_insert(ctx->phis, instr, result);
3902 }
3903
3904 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3905 nir_phi_instr *instr,
3906 LLVMValueRef llvm_phi)
3907 {
3908 nir_foreach_phi_src(src, instr) {
3909 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3910 LLVMValueRef llvm_src = get_src(ctx, src->src);
3911
3912 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3913 }
3914 }
3915
3916 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3917 {
3918 struct hash_entry *entry;
3919 hash_table_foreach(ctx->phis, entry) {
3920 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3921 (LLVMValueRef)entry->data);
3922 }
3923 }
3924
3925
3926 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3927 nir_ssa_undef_instr *instr)
3928 {
3929 unsigned num_components = instr->def.num_components;
3930 LLVMValueRef undef;
3931
3932 if (num_components == 1)
3933 undef = LLVMGetUndef(ctx->i32);
3934 else {
3935 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3936 }
3937 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3938 }
3939
3940 static void visit_jump(struct nir_to_llvm_context *ctx,
3941 nir_jump_instr *instr)
3942 {
3943 switch (instr->type) {
3944 case nir_jump_break:
3945 LLVMBuildBr(ctx->builder, ctx->break_block);
3946 LLVMClearInsertionPosition(ctx->builder);
3947 break;
3948 case nir_jump_continue:
3949 LLVMBuildBr(ctx->builder, ctx->continue_block);
3950 LLVMClearInsertionPosition(ctx->builder);
3951 break;
3952 default:
3953 fprintf(stderr, "Unknown NIR jump instr: ");
3954 nir_print_instr(&instr->instr, stderr);
3955 fprintf(stderr, "\n");
3956 abort();
3957 }
3958 }
3959
3960 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3961 struct exec_list *list);
3962
3963 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3964 {
3965 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3966 nir_foreach_instr(instr, block)
3967 {
3968 switch (instr->type) {
3969 case nir_instr_type_alu:
3970 visit_alu(ctx, nir_instr_as_alu(instr));
3971 break;
3972 case nir_instr_type_load_const:
3973 visit_load_const(ctx, nir_instr_as_load_const(instr));
3974 break;
3975 case nir_instr_type_intrinsic:
3976 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3977 break;
3978 case nir_instr_type_tex:
3979 visit_tex(ctx, nir_instr_as_tex(instr));
3980 break;
3981 case nir_instr_type_phi:
3982 visit_phi(ctx, nir_instr_as_phi(instr));
3983 break;
3984 case nir_instr_type_ssa_undef:
3985 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3986 break;
3987 case nir_instr_type_jump:
3988 visit_jump(ctx, nir_instr_as_jump(instr));
3989 break;
3990 default:
3991 fprintf(stderr, "Unknown NIR instr type: ");
3992 nir_print_instr(instr, stderr);
3993 fprintf(stderr, "\n");
3994 abort();
3995 }
3996 }
3997
3998 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3999 }
4000
4001 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4002 {
4003 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4004
4005 LLVMBasicBlockRef merge_block =
4006 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4007 LLVMBasicBlockRef if_block =
4008 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4009 LLVMBasicBlockRef else_block = merge_block;
4010 if (!exec_list_is_empty(&if_stmt->else_list))
4011 else_block = LLVMAppendBasicBlockInContext(
4012 ctx->context, ctx->main_function, "");
4013
4014 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4015 LLVMConstInt(ctx->i32, 0, false), "");
4016 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4017
4018 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4019 visit_cf_list(ctx, &if_stmt->then_list);
4020 if (LLVMGetInsertBlock(ctx->builder))
4021 LLVMBuildBr(ctx->builder, merge_block);
4022
4023 if (!exec_list_is_empty(&if_stmt->else_list)) {
4024 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4025 visit_cf_list(ctx, &if_stmt->else_list);
4026 if (LLVMGetInsertBlock(ctx->builder))
4027 LLVMBuildBr(ctx->builder, merge_block);
4028 }
4029
4030 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4031 }
4032
4033 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4034 {
4035 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4036 LLVMBasicBlockRef break_parent = ctx->break_block;
4037
4038 ctx->continue_block =
4039 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4040 ctx->break_block =
4041 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4042
4043 LLVMBuildBr(ctx->builder, ctx->continue_block);
4044 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4045 visit_cf_list(ctx, &loop->body);
4046
4047 if (LLVMGetInsertBlock(ctx->builder))
4048 LLVMBuildBr(ctx->builder, ctx->continue_block);
4049 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4050
4051 ctx->continue_block = continue_parent;
4052 ctx->break_block = break_parent;
4053 }
4054
4055 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4056 struct exec_list *list)
4057 {
4058 foreach_list_typed(nir_cf_node, node, node, list)
4059 {
4060 switch (node->type) {
4061 case nir_cf_node_block:
4062 visit_block(ctx, nir_cf_node_as_block(node));
4063 break;
4064
4065 case nir_cf_node_if:
4066 visit_if(ctx, nir_cf_node_as_if(node));
4067 break;
4068
4069 case nir_cf_node_loop:
4070 visit_loop(ctx, nir_cf_node_as_loop(node));
4071 break;
4072
4073 default:
4074 assert(0);
4075 }
4076 }
4077 }
4078
4079 static void
4080 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4081 struct nir_variable *variable)
4082 {
4083 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4084 LLVMValueRef t_offset;
4085 LLVMValueRef t_list;
4086 LLVMValueRef args[3];
4087 LLVMValueRef input;
4088 LLVMValueRef buffer_index;
4089 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4090 int idx = variable->data.location;
4091 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4092
4093 variable->data.driver_location = idx * 4;
4094
4095 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4096 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4097 ctx->start_instance, "");
4098 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4099 ctx->shader_info->vs.vgpr_comp_cnt);
4100 } else
4101 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4102 ctx->base_vertex, "");
4103
4104 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4105 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4106
4107 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
4108 args[0] = t_list;
4109 args[1] = LLVMConstInt(ctx->i32, 0, false);
4110 args[2] = buffer_index;
4111 input = ac_emit_llvm_intrinsic(&ctx->ac,
4112 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
4113 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
4114
4115 for (unsigned chan = 0; chan < 4; chan++) {
4116 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4117 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4118 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4119 input, llvm_chan, ""));
4120 }
4121 }
4122 }
4123
4124
4125 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4126 unsigned attr,
4127 LLVMValueRef interp_param,
4128 LLVMValueRef prim_mask,
4129 LLVMValueRef result[4])
4130 {
4131 const char *intr_name;
4132 LLVMValueRef attr_number;
4133 unsigned chan;
4134
4135 attr_number = LLVMConstInt(ctx->i32, attr, false);
4136
4137 /* fs.constant returns the param from the middle vertex, so it's not
4138 * really useful for flat shading. It's meant to be used for custom
4139 * interpolation (but the intrinsic can't fetch from the other two
4140 * vertices).
4141 *
4142 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4143 * to do the right thing. The only reason we use fs.constant is that
4144 * fs.interp cannot be used on integers, because they can be equal
4145 * to NaN.
4146 */
4147 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
4148
4149 for (chan = 0; chan < 4; chan++) {
4150 LLVMValueRef args[4];
4151 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4152
4153 args[0] = llvm_chan;
4154 args[1] = attr_number;
4155 args[2] = prim_mask;
4156 args[3] = interp_param;
4157 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
4158 ctx->f32, args, args[3] ? 4 : 3,
4159 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
4160 }
4161 }
4162
4163 static void
4164 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4165 struct nir_variable *variable)
4166 {
4167 int idx = variable->data.location;
4168 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4169 LLVMValueRef interp;
4170
4171 variable->data.driver_location = idx * 4;
4172 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4173
4174 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4175 unsigned interp_type;
4176 if (variable->data.sample) {
4177 interp_type = INTERP_SAMPLE;
4178 ctx->shader_info->fs.force_persample = true;
4179 } else if (variable->data.centroid)
4180 interp_type = INTERP_CENTROID;
4181 else
4182 interp_type = INTERP_CENTER;
4183
4184 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4185 } else
4186 interp = NULL;
4187
4188 for (unsigned i = 0; i < attrib_count; ++i)
4189 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4190
4191 }
4192
4193 static void
4194 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4195 struct nir_variable *variable)
4196 {
4197 switch (ctx->stage) {
4198 case MESA_SHADER_VERTEX:
4199 handle_vs_input_decl(ctx, variable);
4200 break;
4201 case MESA_SHADER_FRAGMENT:
4202 handle_fs_input_decl(ctx, variable);
4203 break;
4204 default:
4205 break;
4206 }
4207
4208 }
4209
4210 static void
4211 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4212 struct nir_shader *nir)
4213 {
4214 unsigned index = 0;
4215 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4216 LLVMValueRef interp_param;
4217 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4218
4219 if (!(ctx->input_mask & (1ull << i)))
4220 continue;
4221
4222 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4223 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4224 interp_param = *inputs;
4225 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4226 inputs);
4227
4228 if (!interp_param)
4229 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4230 ++index;
4231 } else if (i == VARYING_SLOT_POS) {
4232 for(int i = 0; i < 3; ++i)
4233 inputs[i] = ctx->frag_pos[i];
4234
4235 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4236 }
4237 }
4238 ctx->shader_info->fs.num_interp = index;
4239 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4240 ctx->shader_info->fs.has_pcoord = true;
4241 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4242 ctx->shader_info->fs.prim_id_input = true;
4243 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4244 ctx->shader_info->fs.layer_input = true;
4245 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4246 }
4247
4248 static LLVMValueRef
4249 ac_build_alloca(struct nir_to_llvm_context *ctx,
4250 LLVMTypeRef type,
4251 const char *name)
4252 {
4253 LLVMBuilderRef builder = ctx->builder;
4254 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4255 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4256 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4257 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4258 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4259 LLVMValueRef res;
4260
4261 if (first_instr) {
4262 LLVMPositionBuilderBefore(first_builder, first_instr);
4263 } else {
4264 LLVMPositionBuilderAtEnd(first_builder, first_block);
4265 }
4266
4267 res = LLVMBuildAlloca(first_builder, type, name);
4268 LLVMBuildStore(builder, LLVMConstNull(type), res);
4269
4270 LLVMDisposeBuilder(first_builder);
4271
4272 return res;
4273 }
4274
4275 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4276 LLVMTypeRef type,
4277 const char *name)
4278 {
4279 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4280 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4281 return ptr;
4282 }
4283
4284 static void
4285 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4286 struct nir_variable *variable)
4287 {
4288 int idx = variable->data.location + variable->data.index;
4289 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4290
4291 variable->data.driver_location = idx * 4;
4292
4293 if (ctx->stage == MESA_SHADER_VERTEX) {
4294
4295 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4296 idx == VARYING_SLOT_CULL_DIST0) {
4297 int length = glsl_get_length(variable->type);
4298 if (idx == VARYING_SLOT_CLIP_DIST0) {
4299 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4300 ctx->num_clips = length;
4301 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4302 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4303 ctx->num_culls = length;
4304 }
4305 if (length > 4)
4306 attrib_count = 2;
4307 else
4308 attrib_count = 1;
4309 }
4310 }
4311
4312 for (unsigned i = 0; i < attrib_count; ++i) {
4313 for (unsigned chan = 0; chan < 4; chan++) {
4314 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4315 si_build_alloca_undef(ctx, ctx->f32, "");
4316 }
4317 }
4318 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4319 }
4320
4321 static void
4322 setup_locals(struct nir_to_llvm_context *ctx,
4323 struct nir_function *func)
4324 {
4325 int i, j;
4326 ctx->num_locals = 0;
4327 nir_foreach_variable(variable, &func->impl->locals) {
4328 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4329 variable->data.driver_location = ctx->num_locals * 4;
4330 ctx->num_locals += attrib_count;
4331 }
4332 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4333 if (!ctx->locals)
4334 return;
4335
4336 for (i = 0; i < ctx->num_locals; i++) {
4337 for (j = 0; j < 4; j++) {
4338 ctx->locals[i * 4 + j] =
4339 si_build_alloca_undef(ctx, ctx->f32, "temp");
4340 }
4341 }
4342 }
4343
4344 static LLVMValueRef
4345 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4346 {
4347 v = to_float(ctx, v);
4348 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4349 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4350 }
4351
4352
4353 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4354 LLVMValueRef src0, LLVMValueRef src1)
4355 {
4356 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4357 LLVMValueRef comp[2];
4358
4359 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4360 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4361 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4362 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4363 }
4364
4365 /* Initialize arguments for the shader export intrinsic */
4366 static void
4367 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4368 LLVMValueRef *values,
4369 unsigned target,
4370 LLVMValueRef *args)
4371 {
4372 /* Default is 0xf. Adjusted below depending on the format. */
4373 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4374 /* Specify whether the EXEC mask represents the valid mask */
4375 args[1] = LLVMConstInt(ctx->i32, 0, false);
4376
4377 /* Specify whether this is the last export */
4378 args[2] = LLVMConstInt(ctx->i32, 0, false);
4379 /* Specify the target we are exporting */
4380 args[3] = LLVMConstInt(ctx->i32, target, false);
4381
4382 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4383 args[5] = LLVMGetUndef(ctx->f32);
4384 args[6] = LLVMGetUndef(ctx->f32);
4385 args[7] = LLVMGetUndef(ctx->f32);
4386 args[8] = LLVMGetUndef(ctx->f32);
4387
4388 if (!values)
4389 return;
4390
4391 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4392 LLVMValueRef val[4];
4393 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4394 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4395 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4396
4397 switch(col_format) {
4398 case V_028714_SPI_SHADER_ZERO:
4399 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4400 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4401 break;
4402
4403 case V_028714_SPI_SHADER_32_R:
4404 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4405 args[5] = values[0];
4406 break;
4407
4408 case V_028714_SPI_SHADER_32_GR:
4409 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4410 args[5] = values[0];
4411 args[6] = values[1];
4412 break;
4413
4414 case V_028714_SPI_SHADER_32_AR:
4415 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4416 args[5] = values[0];
4417 args[8] = values[3];
4418 break;
4419
4420 case V_028714_SPI_SHADER_FP16_ABGR:
4421 args[4] = ctx->i32one;
4422
4423 for (unsigned chan = 0; chan < 2; chan++) {
4424 LLVMValueRef pack_args[2] = {
4425 values[2 * chan],
4426 values[2 * chan + 1]
4427 };
4428 LLVMValueRef packed;
4429
4430 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4431 ctx->i32, pack_args, 2,
4432 AC_FUNC_ATTR_READNONE);
4433 args[chan + 5] = packed;
4434 }
4435 break;
4436
4437 case V_028714_SPI_SHADER_UNORM16_ABGR:
4438 for (unsigned chan = 0; chan < 4; chan++) {
4439 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4440 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4441 LLVMConstReal(ctx->f32, 65535), "");
4442 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4443 LLVMConstReal(ctx->f32, 0.5), "");
4444 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4445 ctx->i32, "");
4446 }
4447
4448 args[4] = ctx->i32one;
4449 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4450 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4451 break;
4452
4453 case V_028714_SPI_SHADER_SNORM16_ABGR:
4454 for (unsigned chan = 0; chan < 4; chan++) {
4455 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4456 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4457 LLVMConstReal(ctx->f32, 32767), "");
4458
4459 /* If positive, add 0.5, else add -0.5. */
4460 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4461 LLVMBuildSelect(ctx->builder,
4462 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4463 val[chan], ctx->f32zero, ""),
4464 LLVMConstReal(ctx->f32, 0.5),
4465 LLVMConstReal(ctx->f32, -0.5), ""), "");
4466 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4467 }
4468
4469 args[4] = ctx->i32one;
4470 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4471 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4472 break;
4473
4474 case V_028714_SPI_SHADER_UINT16_ABGR: {
4475 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4476
4477 for (unsigned chan = 0; chan < 4; chan++) {
4478 val[chan] = to_integer(ctx, values[chan]);
4479 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4480 }
4481
4482 args[4] = ctx->i32one;
4483 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4484 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4485 break;
4486 }
4487
4488 case V_028714_SPI_SHADER_SINT16_ABGR: {
4489 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4490 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4491
4492 /* Clamp. */
4493 for (unsigned chan = 0; chan < 4; chan++) {
4494 val[chan] = to_integer(ctx, values[chan]);
4495 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4496 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4497 }
4498
4499 args[4] = ctx->i32one;
4500 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4501 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4502 break;
4503 }
4504
4505 default:
4506 case V_028714_SPI_SHADER_32_ABGR:
4507 memcpy(&args[5], values, sizeof(values[0]) * 4);
4508 break;
4509 }
4510 } else
4511 memcpy(&args[5], values, sizeof(values[0]) * 4);
4512
4513 for (unsigned i = 5; i < 9; ++i)
4514 args[i] = to_float(ctx, args[i]);
4515 }
4516
4517 static void
4518 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4519 {
4520 uint32_t param_count = 0;
4521 unsigned target;
4522 unsigned pos_idx, num_pos_exports = 0;
4523 LLVMValueRef args[9];
4524 LLVMValueRef pos_args[4][9] = { { 0 } };
4525 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4526 int i;
4527 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4528 (1ull << VARYING_SLOT_CLIP_DIST1) |
4529 (1ull << VARYING_SLOT_CULL_DIST0) |
4530 (1ull << VARYING_SLOT_CULL_DIST1));
4531
4532 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4533 ctx->shader_info->vs.layer_output = 0xffffffff;
4534 if (clip_mask) {
4535 LLVMValueRef slots[8];
4536 unsigned j;
4537
4538 if (ctx->shader_info->vs.cull_dist_mask)
4539 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_clips;
4540
4541 i = VARYING_SLOT_CLIP_DIST0;
4542 for (j = 0; j < ctx->num_clips; j++)
4543 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4544 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4545 i = VARYING_SLOT_CULL_DIST0;
4546 for (j = 0; j < ctx->num_culls; j++)
4547 slots[ctx->num_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4548 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4549
4550 for (i = ctx->num_clips + ctx->num_culls; i < 8; i++)
4551 slots[i] = LLVMGetUndef(ctx->f32);
4552
4553 if (ctx->num_clips + ctx->num_culls > 4) {
4554 target = V_008DFC_SQ_EXP_POS + 3;
4555 si_llvm_init_export_args(ctx, &slots[4], target, args);
4556 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4557 args, sizeof(args));
4558 }
4559
4560 target = V_008DFC_SQ_EXP_POS + 2;
4561 si_llvm_init_export_args(ctx, &slots[0], target, args);
4562 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4563 args, sizeof(args));
4564
4565 }
4566
4567 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4568 LLVMValueRef values[4];
4569 if (!(ctx->output_mask & (1ull << i)))
4570 continue;
4571
4572 for (unsigned j = 0; j < 4; j++)
4573 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4574 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4575
4576 if (i == VARYING_SLOT_POS) {
4577 target = V_008DFC_SQ_EXP_POS;
4578 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4579 i == VARYING_SLOT_CLIP_DIST1 ||
4580 i == VARYING_SLOT_CULL_DIST0 ||
4581 i == VARYING_SLOT_CULL_DIST1) {
4582 continue;
4583 } else if (i == VARYING_SLOT_PSIZ) {
4584 ctx->shader_info->vs.writes_pointsize = true;
4585 psize_value = values[0];
4586 continue;
4587 } else if (i == VARYING_SLOT_LAYER) {
4588 ctx->shader_info->vs.writes_layer = true;
4589 layer_value = values[0];
4590 ctx->shader_info->vs.layer_output = param_count;
4591 target = V_008DFC_SQ_EXP_PARAM + param_count;
4592 param_count++;
4593 } else if (i == VARYING_SLOT_VIEWPORT) {
4594 ctx->shader_info->vs.writes_viewport_index = true;
4595 viewport_index_value = values[0];
4596 continue;
4597 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4598 ctx->shader_info->vs.prim_id_output = param_count;
4599 target = V_008DFC_SQ_EXP_PARAM + param_count;
4600 param_count++;
4601 } else if (i >= VARYING_SLOT_VAR0) {
4602 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4603 target = V_008DFC_SQ_EXP_PARAM + param_count;
4604 param_count++;
4605 }
4606
4607 si_llvm_init_export_args(ctx, values, target, args);
4608
4609 if (target >= V_008DFC_SQ_EXP_POS &&
4610 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4611 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4612 args, sizeof(args));
4613 } else {
4614 ac_emit_llvm_intrinsic(&ctx->ac,
4615 "llvm.SI.export",
4616 ctx->voidt,
4617 args, 9, 0);
4618 }
4619 }
4620
4621 /* We need to add the position output manually if it's missing. */
4622 if (!pos_args[0][0]) {
4623 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4624 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4625 pos_args[0][2] = ctx->i32zero; /* last export? */
4626 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4627 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4628 pos_args[0][5] = ctx->f32zero; /* X */
4629 pos_args[0][6] = ctx->f32zero; /* Y */
4630 pos_args[0][7] = ctx->f32zero; /* Z */
4631 pos_args[0][8] = ctx->f32one; /* W */
4632 }
4633
4634 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4635 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4636 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4637 if (mask) {
4638 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4639 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4640 pos_args[1][2] = ctx->i32zero; /* last export? */
4641 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4642 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4643 pos_args[1][5] = ctx->f32zero; /* X */
4644 pos_args[1][6] = ctx->f32zero; /* Y */
4645 pos_args[1][7] = ctx->f32zero; /* Z */
4646 pos_args[1][8] = ctx->f32zero; /* W */
4647
4648 if (ctx->shader_info->vs.writes_pointsize == true)
4649 pos_args[1][5] = psize_value;
4650 if (ctx->shader_info->vs.writes_layer == true)
4651 pos_args[1][7] = layer_value;
4652 if (ctx->shader_info->vs.writes_viewport_index == true)
4653 pos_args[1][8] = viewport_index_value;
4654 }
4655 for (i = 0; i < 4; i++) {
4656 if (pos_args[i][0])
4657 num_pos_exports++;
4658 }
4659
4660 pos_idx = 0;
4661 for (i = 0; i < 4; i++) {
4662 if (!pos_args[i][0])
4663 continue;
4664
4665 /* Specify the target we are exporting */
4666 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4667 if (pos_idx == num_pos_exports)
4668 pos_args[i][2] = ctx->i32one;
4669 ac_emit_llvm_intrinsic(&ctx->ac,
4670 "llvm.SI.export",
4671 ctx->voidt,
4672 pos_args[i], 9, 0);
4673 }
4674
4675 ctx->shader_info->vs.pos_exports = num_pos_exports;
4676 ctx->shader_info->vs.param_exports = param_count;
4677 }
4678
4679 static void
4680 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4681 {
4682 int j;
4683 uint64_t max_output_written = 0;
4684 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4685 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4686 int param_index;
4687 if (!(ctx->output_mask & (1ull << i)))
4688 continue;
4689
4690 param_index = shader_io_get_unique_index(i);
4691
4692 if (param_index > max_output_written)
4693 max_output_written = param_index;
4694
4695 for (j = 0; j < 4; j++) {
4696 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4697 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4698
4699 build_tbuffer_store(ctx,
4700 ctx->esgs_ring,
4701 out_val, 1,
4702 LLVMGetUndef(ctx->i32), ctx->es2gs_offset,
4703 (4 * param_index + j) * 4,
4704 V_008F0C_BUF_DATA_FORMAT_32,
4705 V_008F0C_BUF_NUM_FORMAT_UINT,
4706 0, 0, 1, 1, 0);
4707 }
4708 }
4709 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4710 }
4711
4712 static void
4713 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4714 LLVMValueRef *color, unsigned param, bool is_last)
4715 {
4716 LLVMValueRef args[9];
4717 /* Export */
4718 si_llvm_init_export_args(ctx, color, param,
4719 args);
4720
4721 if (is_last) {
4722 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4723 args[2] = ctx->i32one; /* DONE bit */
4724 } else if (args[0] == ctx->i32zero)
4725 return; /* unnecessary NULL export */
4726
4727 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4728 ctx->voidt, args, 9, 0);
4729 }
4730
4731 static void
4732 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4733 LLVMValueRef depth, LLVMValueRef stencil,
4734 LLVMValueRef samplemask)
4735 {
4736 LLVMValueRef args[9];
4737 unsigned mask = 0;
4738 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4739 args[2] = ctx->i32one; /* DONE bit */
4740 /* Specify the target we are exporting */
4741 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4742
4743 args[4] = ctx->i32zero; /* COMP flag */
4744 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4745 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4746 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4747 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4748
4749 if (depth) {
4750 args[5] = depth;
4751 mask |= 0x1;
4752 }
4753
4754 if (stencil) {
4755 args[6] = stencil;
4756 mask |= 0x2;
4757 }
4758
4759 if (samplemask) {
4760 args[7] = samplemask;
4761 mask |= 0x04;
4762 }
4763
4764 /* SI (except OLAND) has a bug that it only looks
4765 * at the X writemask component. */
4766 if (ctx->options->chip_class == SI &&
4767 ctx->options->family != CHIP_OLAND)
4768 mask |= 0x01;
4769
4770 args[0] = LLVMConstInt(ctx->i32, mask, false);
4771 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4772 ctx->voidt, args, 9, 0);
4773 }
4774
4775 static void
4776 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4777 {
4778 unsigned index = 0;
4779 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4780
4781 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4782 LLVMValueRef values[4];
4783
4784 if (!(ctx->output_mask & (1ull << i)))
4785 continue;
4786
4787 if (i == FRAG_RESULT_DEPTH) {
4788 ctx->shader_info->fs.writes_z = true;
4789 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4790 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4791 } else if (i == FRAG_RESULT_STENCIL) {
4792 ctx->shader_info->fs.writes_stencil = true;
4793 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4794 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4795 } else {
4796 bool last = false;
4797 for (unsigned j = 0; j < 4; j++)
4798 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4799 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4800
4801 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4802 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4803
4804 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4805 index++;
4806 }
4807 }
4808
4809 if (depth || stencil)
4810 si_export_mrt_z(ctx, depth, stencil, samplemask);
4811 else if (!index)
4812 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4813
4814 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4815 }
4816
4817 static void
4818 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4819 {
4820 LLVMValueRef args[2];
4821
4822 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE, false);
4823 args[1] = ctx->gs_wave_id;
4824 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
4825 ctx->voidt, args, 2, 0);
4826 }
4827
4828 static void
4829 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4830 {
4831 switch (ctx->stage) {
4832 case MESA_SHADER_VERTEX:
4833 if (ctx->options->key.vs.as_es)
4834 handle_es_outputs_post(ctx);
4835 else
4836 handle_vs_outputs_post(ctx);
4837 break;
4838 case MESA_SHADER_FRAGMENT:
4839 handle_fs_outputs_post(ctx);
4840 break;
4841 case MESA_SHADER_GEOMETRY:
4842 emit_gs_epilogue(ctx);
4843 break;
4844 default:
4845 break;
4846 }
4847 }
4848
4849 static void
4850 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4851 struct nir_variable *variable, uint32_t *offset, int idx)
4852 {
4853 unsigned size = glsl_count_attribute_slots(variable->type, false);
4854 variable->data.driver_location = *offset;
4855 *offset += size;
4856 }
4857
4858 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4859 {
4860 LLVMPassManagerRef passmgr;
4861 /* Create the pass manager */
4862 passmgr = LLVMCreateFunctionPassManagerForModule(
4863 ctx->module);
4864
4865 /* This pass should eliminate all the load and store instructions */
4866 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4867
4868 /* Add some optimization passes */
4869 LLVMAddScalarReplAggregatesPass(passmgr);
4870 LLVMAddLICMPass(passmgr);
4871 LLVMAddAggressiveDCEPass(passmgr);
4872 LLVMAddCFGSimplificationPass(passmgr);
4873 LLVMAddInstructionCombiningPass(passmgr);
4874
4875 /* Run the pass */
4876 LLVMInitializeFunctionPassManager(passmgr);
4877 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4878 LLVMFinalizeFunctionPassManager(passmgr);
4879
4880 LLVMDisposeBuilder(ctx->builder);
4881 LLVMDisposePassManager(passmgr);
4882 }
4883
4884 static void
4885 ac_setup_rings(struct nir_to_llvm_context *ctx)
4886 {
4887 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4888 ctx->esgs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, ctx->i32one);
4889 }
4890
4891 if (ctx->is_gs_copy_shader) {
4892 ctx->gsvs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4893 }
4894 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4895 LLVMValueRef tmp;
4896 ctx->esgs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4897 ctx->gsvs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4898
4899 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4900
4901 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4902 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4903 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4904 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4905
4906 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4907 }
4908 }
4909
4910 static
4911 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4912 struct nir_shader *nir,
4913 struct ac_shader_variant_info *shader_info,
4914 const struct ac_nir_compiler_options *options)
4915 {
4916 struct nir_to_llvm_context ctx = {0};
4917 struct nir_function *func;
4918 unsigned i;
4919 ctx.options = options;
4920 ctx.shader_info = shader_info;
4921 ctx.context = LLVMContextCreate();
4922 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4923
4924 ac_llvm_context_init(&ctx.ac, ctx.context);
4925 ctx.ac.module = ctx.module;
4926
4927 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4928
4929 memset(shader_info, 0, sizeof(*shader_info));
4930
4931 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4932 setup_types(&ctx);
4933
4934 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4935 ctx.ac.builder = ctx.builder;
4936 ctx.stage = nir->stage;
4937
4938 for (i = 0; i < AC_UD_MAX_SETS; i++)
4939 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4940 for (i = 0; i < AC_UD_MAX_UD; i++)
4941 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4942
4943 create_function(&ctx);
4944
4945 if (nir->stage == MESA_SHADER_COMPUTE) {
4946 int num_shared = 0;
4947 nir_foreach_variable(variable, &nir->shared)
4948 num_shared++;
4949 if (num_shared) {
4950 int idx = 0;
4951 uint32_t shared_size = 0;
4952 LLVMValueRef var;
4953 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4954 nir_foreach_variable(variable, &nir->shared) {
4955 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4956 idx++;
4957 }
4958
4959 shared_size *= 4;
4960 var = LLVMAddGlobalInAddressSpace(ctx.module,
4961 LLVMArrayType(ctx.i8, shared_size),
4962 "compute_lds",
4963 LOCAL_ADDR_SPACE);
4964 LLVMSetAlignment(var, 4);
4965 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4966 }
4967 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4968 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4969
4970 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4971 }
4972
4973 ac_setup_rings(&ctx);
4974
4975 nir_foreach_variable(variable, &nir->inputs)
4976 handle_shader_input_decl(&ctx, variable);
4977
4978 if (nir->stage == MESA_SHADER_FRAGMENT)
4979 handle_fs_inputs_pre(&ctx, nir);
4980
4981 nir_foreach_variable(variable, &nir->outputs)
4982 handle_shader_output_decl(&ctx, variable);
4983
4984 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4985 _mesa_key_pointer_equal);
4986 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4987 _mesa_key_pointer_equal);
4988
4989 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4990
4991 setup_locals(&ctx, func);
4992
4993 visit_cf_list(&ctx, &func->impl->body);
4994 phi_post_pass(&ctx);
4995
4996 handle_shader_outputs_post(&ctx);
4997 LLVMBuildRetVoid(ctx.builder);
4998
4999 ac_llvm_finalize_module(&ctx);
5000 free(ctx.locals);
5001 ralloc_free(ctx.defs);
5002 ralloc_free(ctx.phis);
5003
5004 if (nir->stage == MESA_SHADER_GEOMETRY) {
5005 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
5006 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5007 nir->info->gs.vertices_out;
5008 }
5009 return ctx.module;
5010 }
5011
5012 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
5013 {
5014 unsigned *retval = (unsigned *)context;
5015 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5016 char *description = LLVMGetDiagInfoDescription(di);
5017
5018 if (severity == LLVMDSError) {
5019 *retval = 1;
5020 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5021 description);
5022 }
5023
5024 LLVMDisposeMessage(description);
5025 }
5026
5027 static unsigned ac_llvm_compile(LLVMModuleRef M,
5028 struct ac_shader_binary *binary,
5029 LLVMTargetMachineRef tm)
5030 {
5031 unsigned retval = 0;
5032 char *err;
5033 LLVMContextRef llvm_ctx;
5034 LLVMMemoryBufferRef out_buffer;
5035 unsigned buffer_size;
5036 const char *buffer_data;
5037 LLVMBool mem_err;
5038
5039 /* Setup Diagnostic Handler*/
5040 llvm_ctx = LLVMGetModuleContext(M);
5041
5042 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5043 &retval);
5044
5045 /* Compile IR*/
5046 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5047 &err, &out_buffer);
5048
5049 /* Process Errors/Warnings */
5050 if (mem_err) {
5051 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5052 free(err);
5053 retval = 1;
5054 goto out;
5055 }
5056
5057 /* Extract Shader Code*/
5058 buffer_size = LLVMGetBufferSize(out_buffer);
5059 buffer_data = LLVMGetBufferStart(out_buffer);
5060
5061 ac_elf_read(buffer_data, buffer_size, binary);
5062
5063 /* Clean up */
5064 LLVMDisposeMemoryBuffer(out_buffer);
5065
5066 out:
5067 return retval;
5068 }
5069
5070 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5071 LLVMModuleRef llvm_module,
5072 struct ac_shader_binary *binary,
5073 struct ac_shader_config *config,
5074 struct ac_shader_variant_info *shader_info,
5075 gl_shader_stage stage,
5076 bool dump_shader, bool supports_spill)
5077 {
5078 if (dump_shader)
5079 ac_dump_module(llvm_module);
5080
5081 memset(binary, 0, sizeof(*binary));
5082 int v = ac_llvm_compile(llvm_module, binary, tm);
5083 if (v) {
5084 fprintf(stderr, "compile failed\n");
5085 }
5086
5087 if (dump_shader)
5088 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5089
5090 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5091
5092 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5093 LLVMDisposeModule(llvm_module);
5094 LLVMContextDispose(ctx);
5095
5096 if (stage == MESA_SHADER_FRAGMENT) {
5097 shader_info->num_input_vgprs = 0;
5098 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5099 shader_info->num_input_vgprs += 2;
5100 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5101 shader_info->num_input_vgprs += 2;
5102 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5103 shader_info->num_input_vgprs += 2;
5104 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5105 shader_info->num_input_vgprs += 3;
5106 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5107 shader_info->num_input_vgprs += 2;
5108 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5109 shader_info->num_input_vgprs += 2;
5110 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5111 shader_info->num_input_vgprs += 2;
5112 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5113 shader_info->num_input_vgprs += 1;
5114 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5115 shader_info->num_input_vgprs += 1;
5116 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5117 shader_info->num_input_vgprs += 1;
5118 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5119 shader_info->num_input_vgprs += 1;
5120 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5121 shader_info->num_input_vgprs += 1;
5122 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5123 shader_info->num_input_vgprs += 1;
5124 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5125 shader_info->num_input_vgprs += 1;
5126 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5127 shader_info->num_input_vgprs += 1;
5128 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5129 shader_info->num_input_vgprs += 1;
5130 }
5131 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5132
5133 /* +3 for scratch wave offset and VCC */
5134 config->num_sgprs = MAX2(config->num_sgprs,
5135 shader_info->num_input_sgprs + 3);
5136 }
5137
5138 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5139 struct ac_shader_binary *binary,
5140 struct ac_shader_config *config,
5141 struct ac_shader_variant_info *shader_info,
5142 struct nir_shader *nir,
5143 const struct ac_nir_compiler_options *options,
5144 bool dump_shader)
5145 {
5146
5147 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5148 options);
5149
5150 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5151 switch (nir->stage) {
5152 case MESA_SHADER_COMPUTE:
5153 for (int i = 0; i < 3; ++i)
5154 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5155 break;
5156 case MESA_SHADER_FRAGMENT:
5157 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5158 break;
5159 case MESA_SHADER_GEOMETRY:
5160 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5161 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5162 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5163 shader_info->gs.invocations = nir->info->gs.invocations;
5164 break;
5165 case MESA_SHADER_VERTEX:
5166 shader_info->vs.as_es = options->key.vs.as_es;
5167 break;
5168 default:
5169 break;
5170 }
5171 }
5172
5173 static void
5174 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5175 {
5176 LLVMValueRef args[9];
5177 args[0] = ctx->gsvs_ring;
5178 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5179 args[3] = ctx->i32zero;
5180 args[4] = ctx->i32one; /* OFFEN */
5181 args[5] = ctx->i32zero; /* IDXEN */
5182 args[6] = ctx->i32one; /* GLC */
5183 args[7] = ctx->i32one; /* SLC */
5184 args[8] = ctx->i32zero; /* TFE */
5185
5186 int idx = 0;
5187 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5188 if (!(ctx->output_mask & (1ull << i)))
5189 continue;
5190
5191 for (unsigned j = 0; j < 4; j++) {
5192 LLVMValueRef value;
5193 args[2] = LLVMConstInt(ctx->i32,
5194 (idx * 4 + j) *
5195 ctx->gs_max_out_vertices * 16 * 4, false);
5196
5197 value = ac_emit_llvm_intrinsic(&ctx->ac,
5198 "llvm.SI.buffer.load.dword.i32.i32",
5199 ctx->i32, args, 9,
5200 AC_FUNC_ATTR_READONLY);
5201
5202 LLVMBuildStore(ctx->builder,
5203 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5204 }
5205 idx++;
5206 }
5207 handle_vs_outputs_post(ctx);
5208 }
5209
5210 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5211 struct nir_shader *geom_shader,
5212 struct ac_shader_binary *binary,
5213 struct ac_shader_config *config,
5214 struct ac_shader_variant_info *shader_info,
5215 const struct ac_nir_compiler_options *options,
5216 bool dump_shader)
5217 {
5218 struct nir_to_llvm_context ctx = {0};
5219 ctx.context = LLVMContextCreate();
5220 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5221 ctx.options = options;
5222 ctx.shader_info = shader_info;
5223
5224 ac_llvm_context_init(&ctx.ac, ctx.context);
5225 ctx.ac.module = ctx.module;
5226
5227 ctx.is_gs_copy_shader = true;
5228 LLVMSetTarget(ctx.module, "amdgcn--");
5229 setup_types(&ctx);
5230
5231 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5232 ctx.ac.builder = ctx.builder;
5233 ctx.stage = MESA_SHADER_VERTEX;
5234
5235 create_function(&ctx);
5236
5237 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5238 ac_setup_rings(&ctx);
5239
5240 nir_foreach_variable(variable, &geom_shader->outputs)
5241 handle_shader_output_decl(&ctx, variable);
5242
5243 ac_gs_copy_shader_emit(&ctx);
5244
5245 LLVMBuildRetVoid(ctx.builder);
5246
5247 ac_llvm_finalize_module(&ctx);
5248
5249 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5250 MESA_SHADER_VERTEX,
5251 dump_shader, options->supports_spill);
5252 }