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ac: implement nir_intrinsic_image_samples
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 };
131
132 static inline struct radv_shader_context *
133 radv_shader_context_from_abi(struct ac_shader_abi *abi)
134 {
135 struct radv_shader_context *ctx = NULL;
136 return container_of(abi, ctx, abi);
137 }
138
139 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
140 const nir_deref_var *deref,
141 enum ac_descriptor_type desc_type,
142 const nir_tex_instr *instr,
143 bool image, bool write);
144
145 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
146 {
147 return (index * 4) + chan;
148 }
149
150 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
151 {
152 /* handle patch indices separate */
153 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
154 return 0;
155 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
156 return 1;
157 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
158 return 2 + (slot - VARYING_SLOT_PATCH0);
159
160 if (slot == VARYING_SLOT_POS)
161 return 0;
162 if (slot == VARYING_SLOT_PSIZ)
163 return 1;
164 if (slot == VARYING_SLOT_CLIP_DIST0)
165 return 2;
166 /* 3 is reserved for clip dist as well */
167 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
168 return 4 + (slot - VARYING_SLOT_VAR0);
169 unreachable("illegal slot in get unique index\n");
170 }
171
172 static void set_llvm_calling_convention(LLVMValueRef func,
173 gl_shader_stage stage)
174 {
175 enum radeon_llvm_calling_convention calling_conv;
176
177 switch (stage) {
178 case MESA_SHADER_VERTEX:
179 case MESA_SHADER_TESS_EVAL:
180 calling_conv = RADEON_LLVM_AMDGPU_VS;
181 break;
182 case MESA_SHADER_GEOMETRY:
183 calling_conv = RADEON_LLVM_AMDGPU_GS;
184 break;
185 case MESA_SHADER_TESS_CTRL:
186 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
187 break;
188 case MESA_SHADER_FRAGMENT:
189 calling_conv = RADEON_LLVM_AMDGPU_PS;
190 break;
191 case MESA_SHADER_COMPUTE:
192 calling_conv = RADEON_LLVM_AMDGPU_CS;
193 break;
194 default:
195 unreachable("Unhandle shader type");
196 }
197
198 LLVMSetFunctionCallConv(func, calling_conv);
199 }
200
201 #define MAX_ARGS 23
202 struct arg_info {
203 LLVMTypeRef types[MAX_ARGS];
204 LLVMValueRef *assign[MAX_ARGS];
205 unsigned array_params_mask;
206 uint8_t count;
207 uint8_t sgpr_count;
208 uint8_t num_sgprs_used;
209 uint8_t num_vgprs_used;
210 };
211
212 enum ac_arg_regfile {
213 ARG_SGPR,
214 ARG_VGPR,
215 };
216
217 static void
218 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
219 LLVMValueRef *param_ptr)
220 {
221 assert(info->count < MAX_ARGS);
222
223 info->assign[info->count] = param_ptr;
224 info->types[info->count] = type;
225 info->count++;
226
227 if (regfile == ARG_SGPR) {
228 info->num_sgprs_used += ac_get_type_size(type) / 4;
229 info->sgpr_count++;
230 } else {
231 assert(regfile == ARG_VGPR);
232 info->num_vgprs_used += ac_get_type_size(type) / 4;
233 }
234 }
235
236 static inline void
237 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
238 {
239 info->array_params_mask |= (1 << info->count);
240 add_arg(info, ARG_SGPR, type, param_ptr);
241 }
242
243 static void assign_arguments(LLVMValueRef main_function,
244 struct arg_info *info)
245 {
246 unsigned i;
247 for (i = 0; i < info->count; i++) {
248 if (info->assign[i])
249 *info->assign[i] = LLVMGetParam(main_function, i);
250 }
251 }
252
253 static LLVMValueRef
254 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
255 LLVMBuilderRef builder, LLVMTypeRef *return_types,
256 unsigned num_return_elems,
257 struct arg_info *args,
258 unsigned max_workgroup_size,
259 bool unsafe_math)
260 {
261 LLVMTypeRef main_function_type, ret_type;
262 LLVMBasicBlockRef main_function_body;
263
264 if (num_return_elems)
265 ret_type = LLVMStructTypeInContext(ctx, return_types,
266 num_return_elems, true);
267 else
268 ret_type = LLVMVoidTypeInContext(ctx);
269
270 /* Setup the function */
271 main_function_type =
272 LLVMFunctionType(ret_type, args->types, args->count, 0);
273 LLVMValueRef main_function =
274 LLVMAddFunction(module, "main", main_function_type);
275 main_function_body =
276 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
277 LLVMPositionBuilderAtEnd(builder, main_function_body);
278
279 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
280 for (unsigned i = 0; i < args->sgpr_count; ++i) {
281 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
282
283 if (args->array_params_mask & (1 << i)) {
284 LLVMValueRef P = LLVMGetParam(main_function, i);
285 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
286 ac_add_attr_dereferenceable(P, UINT64_MAX);
287 }
288 }
289
290 if (max_workgroup_size) {
291 ac_llvm_add_target_dep_function_attr(main_function,
292 "amdgpu-max-work-group-size",
293 max_workgroup_size);
294 }
295 if (unsafe_math) {
296 /* These were copied from some LLVM test. */
297 LLVMAddTargetDependentFunctionAttr(main_function,
298 "less-precise-fpmad",
299 "true");
300 LLVMAddTargetDependentFunctionAttr(main_function,
301 "no-infs-fp-math",
302 "true");
303 LLVMAddTargetDependentFunctionAttr(main_function,
304 "no-nans-fp-math",
305 "true");
306 LLVMAddTargetDependentFunctionAttr(main_function,
307 "unsafe-fp-math",
308 "true");
309 LLVMAddTargetDependentFunctionAttr(main_function,
310 "no-signed-zeros-fp-math",
311 "true");
312 }
313 return main_function;
314 }
315
316 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
317 LLVMValueRef param, unsigned rshift,
318 unsigned bitwidth)
319 {
320 LLVMValueRef value = param;
321 if (rshift)
322 value = LLVMBuildLShr(ctx->builder, value,
323 LLVMConstInt(ctx->i32, rshift, false), "");
324
325 if (rshift + bitwidth < 32) {
326 unsigned mask = (1 << bitwidth) - 1;
327 value = LLVMBuildAnd(ctx->builder, value,
328 LLVMConstInt(ctx->i32, mask, false), "");
329 }
330 return value;
331 }
332
333 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
334 {
335 switch (ctx->stage) {
336 case MESA_SHADER_TESS_CTRL:
337 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
338 case MESA_SHADER_TESS_EVAL:
339 return ctx->tes_rel_patch_id;
340 break;
341 default:
342 unreachable("Illegal stage");
343 }
344 }
345
346 /* Tessellation shaders pass outputs to the next shader using LDS.
347 *
348 * LS outputs = TCS inputs
349 * TCS outputs = TES inputs
350 *
351 * The LDS layout is:
352 * - TCS inputs for patch 0
353 * - TCS inputs for patch 1
354 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
355 * - ...
356 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
357 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
358 * - TCS outputs for patch 1
359 * - Per-patch TCS outputs for patch 1
360 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
361 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
362 * - ...
363 *
364 * All three shaders VS(LS), TCS, TES share the same LDS space.
365 */
366 static LLVMValueRef
367 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
368 {
369 if (ctx->stage == MESA_SHADER_VERTEX)
370 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
371 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
372 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
373 else {
374 assert(0);
375 return NULL;
376 }
377 }
378
379 static LLVMValueRef
380 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
381 {
382 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
383 }
384
385 static LLVMValueRef
386 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
387 {
388 return LLVMBuildMul(ctx->ac.builder,
389 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
390 LLVMConstInt(ctx->ac.i32, 4, false), "");
391 }
392
393 static LLVMValueRef
394 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
395 {
396 return LLVMBuildMul(ctx->ac.builder,
397 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
398 LLVMConstInt(ctx->ac.i32, 4, false), "");
399 }
400
401 static LLVMValueRef
402 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
403 {
404 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
405 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
406
407 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
408 }
409
410 static LLVMValueRef
411 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
412 {
413 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
414 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
415 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
416
417 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
418 LLVMBuildMul(ctx->ac.builder, patch_stride,
419 rel_patch_id, ""),
420 "");
421 }
422
423 static LLVMValueRef
424 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
425 {
426 LLVMValueRef patch0_patch_data_offset =
427 get_tcs_out_patch0_patch_data_offset(ctx);
428 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
429 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
430
431 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
432 LLVMBuildMul(ctx->ac.builder, patch_stride,
433 rel_patch_id, ""),
434 "");
435 }
436
437 static void
438 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
439 uint32_t indirect_offset)
440 {
441 ud_info->sgpr_idx = *sgpr_idx;
442 ud_info->num_sgprs = num_sgprs;
443 ud_info->indirect = indirect_offset > 0;
444 ud_info->indirect_offset = indirect_offset;
445 *sgpr_idx += num_sgprs;
446 }
447
448 static void
449 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
450 uint8_t num_sgprs)
451 {
452 struct ac_userdata_info *ud_info =
453 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
454 assert(ud_info);
455
456 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
457 }
458
459 static void
460 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
461 uint32_t indirect_offset)
462 {
463 struct ac_userdata_info *ud_info =
464 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
465 assert(ud_info);
466
467 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
468 }
469
470 struct user_sgpr_info {
471 bool need_ring_offsets;
472 uint8_t sgpr_count;
473 bool indirect_all_descriptor_sets;
474 };
475
476 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
477 gl_shader_stage stage)
478 {
479 switch (stage) {
480 case MESA_SHADER_VERTEX:
481 if (ctx->shader_info->info.needs_multiview_view_index ||
482 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
483 return true;
484 break;
485 case MESA_SHADER_TESS_EVAL:
486 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
487 return true;
488 break;
489 case MESA_SHADER_GEOMETRY:
490 case MESA_SHADER_TESS_CTRL:
491 if (ctx->shader_info->info.needs_multiview_view_index)
492 return true;
493 break;
494 default:
495 break;
496 }
497 return false;
498 }
499
500 static uint8_t
501 count_vs_user_sgprs(struct radv_shader_context *ctx)
502 {
503 uint8_t count = 0;
504
505 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
506 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
507
508 return count;
509 }
510
511 static void allocate_user_sgprs(struct radv_shader_context *ctx,
512 gl_shader_stage stage,
513 bool has_previous_stage,
514 gl_shader_stage previous_stage,
515 bool needs_view_index,
516 struct user_sgpr_info *user_sgpr_info)
517 {
518 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
519
520 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
521 if (stage == MESA_SHADER_GEOMETRY ||
522 stage == MESA_SHADER_VERTEX ||
523 stage == MESA_SHADER_TESS_CTRL ||
524 stage == MESA_SHADER_TESS_EVAL ||
525 ctx->is_gs_copy_shader)
526 user_sgpr_info->need_ring_offsets = true;
527
528 if (stage == MESA_SHADER_FRAGMENT &&
529 ctx->shader_info->info.ps.needs_sample_positions)
530 user_sgpr_info->need_ring_offsets = true;
531
532 /* 2 user sgprs will nearly always be allocated for scratch/rings */
533 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
534 user_sgpr_info->sgpr_count += 2;
535 }
536
537 switch (stage) {
538 case MESA_SHADER_COMPUTE:
539 if (ctx->shader_info->info.cs.uses_grid_size)
540 user_sgpr_info->sgpr_count += 3;
541 break;
542 case MESA_SHADER_FRAGMENT:
543 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
544 break;
545 case MESA_SHADER_VERTEX:
546 if (!ctx->is_gs_copy_shader)
547 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
548 if (ctx->options->key.vs.as_ls)
549 user_sgpr_info->sgpr_count++;
550 break;
551 case MESA_SHADER_TESS_CTRL:
552 if (has_previous_stage) {
553 if (previous_stage == MESA_SHADER_VERTEX)
554 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
555 user_sgpr_info->sgpr_count++;
556 }
557 user_sgpr_info->sgpr_count += 4;
558 break;
559 case MESA_SHADER_TESS_EVAL:
560 user_sgpr_info->sgpr_count += 1;
561 break;
562 case MESA_SHADER_GEOMETRY:
563 if (has_previous_stage) {
564 if (previous_stage == MESA_SHADER_VERTEX) {
565 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
566 } else {
567 user_sgpr_info->sgpr_count++;
568 }
569 }
570 user_sgpr_info->sgpr_count += 2;
571 break;
572 default:
573 break;
574 }
575
576 if (needs_view_index)
577 user_sgpr_info->sgpr_count++;
578
579 if (ctx->shader_info->info.loads_push_constants)
580 user_sgpr_info->sgpr_count += 2;
581
582 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
583 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
584
585 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
586 user_sgpr_info->sgpr_count += 2;
587 user_sgpr_info->indirect_all_descriptor_sets = true;
588 } else {
589 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
590 }
591 }
592
593 static void
594 declare_global_input_sgprs(struct radv_shader_context *ctx,
595 gl_shader_stage stage,
596 bool has_previous_stage,
597 gl_shader_stage previous_stage,
598 const struct user_sgpr_info *user_sgpr_info,
599 struct arg_info *args,
600 LLVMValueRef *desc_sets)
601 {
602 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
603 unsigned num_sets = ctx->options->layout ?
604 ctx->options->layout->num_sets : 0;
605 unsigned stage_mask = 1 << stage;
606
607 if (has_previous_stage)
608 stage_mask |= 1 << previous_stage;
609
610 /* 1 for each descriptor set */
611 if (!user_sgpr_info->indirect_all_descriptor_sets) {
612 for (unsigned i = 0; i < num_sets; ++i) {
613 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
614 add_array_arg(args, type,
615 &ctx->descriptor_sets[i]);
616 }
617 }
618 } else {
619 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
620 }
621
622 if (ctx->shader_info->info.loads_push_constants) {
623 /* 1 for push constants and dynamic descriptors */
624 add_array_arg(args, type, &ctx->abi.push_constants);
625 }
626 }
627
628 static void
629 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
630 gl_shader_stage stage,
631 bool has_previous_stage,
632 gl_shader_stage previous_stage,
633 struct arg_info *args)
634 {
635 if (!ctx->is_gs_copy_shader &&
636 (stage == MESA_SHADER_VERTEX ||
637 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
638 if (ctx->shader_info->info.vs.has_vertex_buffers) {
639 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
640 &ctx->vertex_buffers);
641 }
642 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
643 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
644 if (ctx->shader_info->info.vs.needs_draw_id) {
645 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
646 }
647 }
648 }
649
650 static void
651 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
652 {
653 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
654 if (!ctx->is_gs_copy_shader) {
655 if (ctx->options->key.vs.as_ls) {
656 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
657 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
658 } else {
659 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
660 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
661 }
662 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
663 }
664 }
665
666 static void
667 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
668 {
669 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
670 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
671 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
672 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
673 }
674
675 static void
676 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
677 bool has_previous_stage, gl_shader_stage previous_stage,
678 const struct user_sgpr_info *user_sgpr_info,
679 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
680 {
681 unsigned num_sets = ctx->options->layout ?
682 ctx->options->layout->num_sets : 0;
683 unsigned stage_mask = 1 << stage;
684
685 if (has_previous_stage)
686 stage_mask |= 1 << previous_stage;
687
688 if (!user_sgpr_info->indirect_all_descriptor_sets) {
689 for (unsigned i = 0; i < num_sets; ++i) {
690 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
691 set_loc_desc(ctx, i, user_sgpr_idx, 0);
692 } else
693 ctx->descriptor_sets[i] = NULL;
694 }
695 } else {
696 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
697 user_sgpr_idx, 2);
698
699 for (unsigned i = 0; i < num_sets; ++i) {
700 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
701 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
702 ctx->descriptor_sets[i] =
703 ac_build_load_to_sgpr(&ctx->ac,
704 desc_sets,
705 LLVMConstInt(ctx->ac.i32, i, false));
706
707 } else
708 ctx->descriptor_sets[i] = NULL;
709 }
710 ctx->shader_info->need_indirect_descriptor_sets = true;
711 }
712
713 if (ctx->shader_info->info.loads_push_constants) {
714 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
715 }
716 }
717
718 static void
719 set_vs_specific_input_locs(struct radv_shader_context *ctx,
720 gl_shader_stage stage, bool has_previous_stage,
721 gl_shader_stage previous_stage,
722 uint8_t *user_sgpr_idx)
723 {
724 if (!ctx->is_gs_copy_shader &&
725 (stage == MESA_SHADER_VERTEX ||
726 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
727 if (ctx->shader_info->info.vs.has_vertex_buffers) {
728 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
729 user_sgpr_idx, 2);
730 }
731
732 unsigned vs_num = 2;
733 if (ctx->shader_info->info.vs.needs_draw_id)
734 vs_num++;
735
736 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
737 user_sgpr_idx, vs_num);
738 }
739 }
740
741 static void create_function(struct radv_shader_context *ctx,
742 gl_shader_stage stage,
743 bool has_previous_stage,
744 gl_shader_stage previous_stage)
745 {
746 uint8_t user_sgpr_idx;
747 struct user_sgpr_info user_sgpr_info;
748 struct arg_info args = {};
749 LLVMValueRef desc_sets;
750 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
751 allocate_user_sgprs(ctx, stage, has_previous_stage,
752 previous_stage, needs_view_index, &user_sgpr_info);
753
754 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
755 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
756 &ctx->ring_offsets);
757 }
758
759 switch (stage) {
760 case MESA_SHADER_COMPUTE:
761 declare_global_input_sgprs(ctx, stage, has_previous_stage,
762 previous_stage, &user_sgpr_info,
763 &args, &desc_sets);
764
765 if (ctx->shader_info->info.cs.uses_grid_size) {
766 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
767 &ctx->abi.num_work_groups);
768 }
769
770 for (int i = 0; i < 3; i++) {
771 ctx->abi.workgroup_ids[i] = NULL;
772 if (ctx->shader_info->info.cs.uses_block_id[i]) {
773 add_arg(&args, ARG_SGPR, ctx->ac.i32,
774 &ctx->abi.workgroup_ids[i]);
775 }
776 }
777
778 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
779 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
780 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
781 &ctx->abi.local_invocation_ids);
782 break;
783 case MESA_SHADER_VERTEX:
784 declare_global_input_sgprs(ctx, stage, has_previous_stage,
785 previous_stage, &user_sgpr_info,
786 &args, &desc_sets);
787 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
788 previous_stage, &args);
789
790 if (needs_view_index)
791 add_arg(&args, ARG_SGPR, ctx->ac.i32,
792 &ctx->abi.view_index);
793 if (ctx->options->key.vs.as_es)
794 add_arg(&args, ARG_SGPR, ctx->ac.i32,
795 &ctx->es2gs_offset);
796 else if (ctx->options->key.vs.as_ls)
797 add_arg(&args, ARG_SGPR, ctx->ac.i32,
798 &ctx->ls_out_layout);
799
800 declare_vs_input_vgprs(ctx, &args);
801 break;
802 case MESA_SHADER_TESS_CTRL:
803 if (has_previous_stage) {
804 // First 6 system regs
805 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
806 add_arg(&args, ARG_SGPR, ctx->ac.i32,
807 &ctx->merged_wave_info);
808 add_arg(&args, ARG_SGPR, ctx->ac.i32,
809 &ctx->tess_factor_offset);
810
811 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
812 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
813 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
814
815 declare_global_input_sgprs(ctx, stage,
816 has_previous_stage,
817 previous_stage,
818 &user_sgpr_info, &args,
819 &desc_sets);
820 declare_vs_specific_input_sgprs(ctx, stage,
821 has_previous_stage,
822 previous_stage, &args);
823
824 add_arg(&args, ARG_SGPR, ctx->ac.i32,
825 &ctx->ls_out_layout);
826
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->tcs_offchip_layout);
829 add_arg(&args, ARG_SGPR, ctx->ac.i32,
830 &ctx->tcs_out_offsets);
831 add_arg(&args, ARG_SGPR, ctx->ac.i32,
832 &ctx->tcs_out_layout);
833 add_arg(&args, ARG_SGPR, ctx->ac.i32,
834 &ctx->tcs_in_layout);
835 if (needs_view_index)
836 add_arg(&args, ARG_SGPR, ctx->ac.i32,
837 &ctx->abi.view_index);
838
839 add_arg(&args, ARG_VGPR, ctx->ac.i32,
840 &ctx->abi.tcs_patch_id);
841 add_arg(&args, ARG_VGPR, ctx->ac.i32,
842 &ctx->abi.tcs_rel_ids);
843
844 declare_vs_input_vgprs(ctx, &args);
845 } else {
846 declare_global_input_sgprs(ctx, stage,
847 has_previous_stage,
848 previous_stage,
849 &user_sgpr_info, &args,
850 &desc_sets);
851
852 add_arg(&args, ARG_SGPR, ctx->ac.i32,
853 &ctx->tcs_offchip_layout);
854 add_arg(&args, ARG_SGPR, ctx->ac.i32,
855 &ctx->tcs_out_offsets);
856 add_arg(&args, ARG_SGPR, ctx->ac.i32,
857 &ctx->tcs_out_layout);
858 add_arg(&args, ARG_SGPR, ctx->ac.i32,
859 &ctx->tcs_in_layout);
860 if (needs_view_index)
861 add_arg(&args, ARG_SGPR, ctx->ac.i32,
862 &ctx->abi.view_index);
863
864 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
865 add_arg(&args, ARG_SGPR, ctx->ac.i32,
866 &ctx->tess_factor_offset);
867 add_arg(&args, ARG_VGPR, ctx->ac.i32,
868 &ctx->abi.tcs_patch_id);
869 add_arg(&args, ARG_VGPR, ctx->ac.i32,
870 &ctx->abi.tcs_rel_ids);
871 }
872 break;
873 case MESA_SHADER_TESS_EVAL:
874 declare_global_input_sgprs(ctx, stage, has_previous_stage,
875 previous_stage, &user_sgpr_info,
876 &args, &desc_sets);
877
878 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
879 if (needs_view_index)
880 add_arg(&args, ARG_SGPR, ctx->ac.i32,
881 &ctx->abi.view_index);
882
883 if (ctx->options->key.tes.as_es) {
884 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
885 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
886 add_arg(&args, ARG_SGPR, ctx->ac.i32,
887 &ctx->es2gs_offset);
888 } else {
889 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
890 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
891 }
892 declare_tes_input_vgprs(ctx, &args);
893 break;
894 case MESA_SHADER_GEOMETRY:
895 if (has_previous_stage) {
896 // First 6 system regs
897 add_arg(&args, ARG_SGPR, ctx->ac.i32,
898 &ctx->gs2vs_offset);
899 add_arg(&args, ARG_SGPR, ctx->ac.i32,
900 &ctx->merged_wave_info);
901 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
902
903 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
904 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
905 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
906
907 declare_global_input_sgprs(ctx, stage,
908 has_previous_stage,
909 previous_stage,
910 &user_sgpr_info, &args,
911 &desc_sets);
912
913 if (previous_stage == MESA_SHADER_TESS_EVAL) {
914 add_arg(&args, ARG_SGPR, ctx->ac.i32,
915 &ctx->tcs_offchip_layout);
916 } else {
917 declare_vs_specific_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &args);
921 }
922
923 add_arg(&args, ARG_SGPR, ctx->ac.i32,
924 &ctx->gsvs_ring_stride);
925 add_arg(&args, ARG_SGPR, ctx->ac.i32,
926 &ctx->gsvs_num_entries);
927 if (needs_view_index)
928 add_arg(&args, ARG_SGPR, ctx->ac.i32,
929 &ctx->abi.view_index);
930
931 add_arg(&args, ARG_VGPR, ctx->ac.i32,
932 &ctx->gs_vtx_offset[0]);
933 add_arg(&args, ARG_VGPR, ctx->ac.i32,
934 &ctx->gs_vtx_offset[2]);
935 add_arg(&args, ARG_VGPR, ctx->ac.i32,
936 &ctx->abi.gs_prim_id);
937 add_arg(&args, ARG_VGPR, ctx->ac.i32,
938 &ctx->abi.gs_invocation_id);
939 add_arg(&args, ARG_VGPR, ctx->ac.i32,
940 &ctx->gs_vtx_offset[4]);
941
942 if (previous_stage == MESA_SHADER_VERTEX) {
943 declare_vs_input_vgprs(ctx, &args);
944 } else {
945 declare_tes_input_vgprs(ctx, &args);
946 }
947 } else {
948 declare_global_input_sgprs(ctx, stage,
949 has_previous_stage,
950 previous_stage,
951 &user_sgpr_info, &args,
952 &desc_sets);
953
954 add_arg(&args, ARG_SGPR, ctx->ac.i32,
955 &ctx->gsvs_ring_stride);
956 add_arg(&args, ARG_SGPR, ctx->ac.i32,
957 &ctx->gsvs_num_entries);
958 if (needs_view_index)
959 add_arg(&args, ARG_SGPR, ctx->ac.i32,
960 &ctx->abi.view_index);
961
962 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
963 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
964 add_arg(&args, ARG_VGPR, ctx->ac.i32,
965 &ctx->gs_vtx_offset[0]);
966 add_arg(&args, ARG_VGPR, ctx->ac.i32,
967 &ctx->gs_vtx_offset[1]);
968 add_arg(&args, ARG_VGPR, ctx->ac.i32,
969 &ctx->abi.gs_prim_id);
970 add_arg(&args, ARG_VGPR, ctx->ac.i32,
971 &ctx->gs_vtx_offset[2]);
972 add_arg(&args, ARG_VGPR, ctx->ac.i32,
973 &ctx->gs_vtx_offset[3]);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[4]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[5]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->abi.gs_invocation_id);
980 }
981 break;
982 case MESA_SHADER_FRAGMENT:
983 declare_global_input_sgprs(ctx, stage, has_previous_stage,
984 previous_stage, &user_sgpr_info,
985 &args, &desc_sets);
986
987 if (ctx->shader_info->info.ps.needs_sample_positions)
988 add_arg(&args, ARG_SGPR, ctx->ac.i32,
989 &ctx->sample_pos_offset);
990
991 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
992 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
993 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
994 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
995 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
996 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
997 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
998 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
999 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1000 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1001 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1002 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1003 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1004 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1005 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1006 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1007 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1008 break;
1009 default:
1010 unreachable("Shader stage not implemented");
1011 }
1012
1013 ctx->main_function = create_llvm_function(
1014 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1015 ctx->max_workgroup_size,
1016 ctx->options->unsafe_math);
1017 set_llvm_calling_convention(ctx->main_function, stage);
1018
1019
1020 ctx->shader_info->num_input_vgprs = 0;
1021 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1022
1023 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1024
1025 if (ctx->stage != MESA_SHADER_FRAGMENT)
1026 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1027
1028 assign_arguments(ctx->main_function, &args);
1029
1030 user_sgpr_idx = 0;
1031
1032 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1033 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1034 &user_sgpr_idx, 2);
1035 if (ctx->options->supports_spill) {
1036 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1037 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1038 NULL, 0, AC_FUNC_ATTR_READNONE);
1039 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1040 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1041 }
1042 }
1043
1044 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1045 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1046 if (has_previous_stage)
1047 user_sgpr_idx = 0;
1048
1049 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1050 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1051
1052 switch (stage) {
1053 case MESA_SHADER_COMPUTE:
1054 if (ctx->shader_info->info.cs.uses_grid_size) {
1055 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1056 &user_sgpr_idx, 3);
1057 }
1058 break;
1059 case MESA_SHADER_VERTEX:
1060 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1061 previous_stage, &user_sgpr_idx);
1062 if (ctx->abi.view_index)
1063 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1064 if (ctx->options->key.vs.as_ls) {
1065 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1066 &user_sgpr_idx, 1);
1067 }
1068 if (ctx->options->key.vs.as_ls)
1069 ac_declare_lds_as_pointer(&ctx->ac);
1070 break;
1071 case MESA_SHADER_TESS_CTRL:
1072 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1073 previous_stage, &user_sgpr_idx);
1074 if (has_previous_stage)
1075 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1076 &user_sgpr_idx, 1);
1077 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1078 if (ctx->abi.view_index)
1079 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1080 ac_declare_lds_as_pointer(&ctx->ac);
1081 break;
1082 case MESA_SHADER_TESS_EVAL:
1083 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1084 if (ctx->abi.view_index)
1085 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1086 break;
1087 case MESA_SHADER_GEOMETRY:
1088 if (has_previous_stage) {
1089 if (previous_stage == MESA_SHADER_VERTEX)
1090 set_vs_specific_input_locs(ctx, stage,
1091 has_previous_stage,
1092 previous_stage,
1093 &user_sgpr_idx);
1094 else
1095 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1096 &user_sgpr_idx, 1);
1097 }
1098 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1099 &user_sgpr_idx, 2);
1100 if (ctx->abi.view_index)
1101 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1102 if (has_previous_stage)
1103 ac_declare_lds_as_pointer(&ctx->ac);
1104 break;
1105 case MESA_SHADER_FRAGMENT:
1106 if (ctx->shader_info->info.ps.needs_sample_positions) {
1107 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1108 &user_sgpr_idx, 1);
1109 }
1110 break;
1111 default:
1112 unreachable("Shader stage not implemented");
1113 }
1114
1115 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1116 }
1117
1118 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1119 LLVMValueRef value, unsigned count)
1120 {
1121 unsigned num_components = ac_get_llvm_num_components(value);
1122 if (count == num_components)
1123 return value;
1124
1125 LLVMValueRef masks[] = {
1126 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1127 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1128
1129 if (count == 1)
1130 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1131 "");
1132
1133 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1134 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1135 }
1136
1137 static void
1138 build_store_values_extended(struct ac_llvm_context *ac,
1139 LLVMValueRef *values,
1140 unsigned value_count,
1141 unsigned value_stride,
1142 LLVMValueRef vec)
1143 {
1144 LLVMBuilderRef builder = ac->builder;
1145 unsigned i;
1146
1147 for (i = 0; i < value_count; i++) {
1148 LLVMValueRef ptr = values[i * value_stride];
1149 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1150 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1151 LLVMBuildStore(builder, value, ptr);
1152 }
1153 }
1154
1155 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1156 const nir_ssa_def *def)
1157 {
1158 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1159 if (def->num_components > 1) {
1160 type = LLVMVectorType(type, def->num_components);
1161 }
1162 return type;
1163 }
1164
1165 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1166 {
1167 assert(src.is_ssa);
1168 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1169 return (LLVMValueRef)entry->data;
1170 }
1171
1172 static LLVMValueRef
1173 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1174 {
1175 LLVMValueRef ptr = get_src(ctx, src);
1176 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1177 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1178
1179 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1180 LLVMPointerType(ctx->ac.i32, addr_space), "");
1181 }
1182
1183 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1184 const struct nir_block *b)
1185 {
1186 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1187 return (LLVMBasicBlockRef)entry->data;
1188 }
1189
1190 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1191 nir_alu_src src,
1192 unsigned num_components)
1193 {
1194 LLVMValueRef value = get_src(ctx, src.src);
1195 bool need_swizzle = false;
1196
1197 assert(value);
1198 LLVMTypeRef type = LLVMTypeOf(value);
1199 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1200 ? LLVMGetVectorSize(type)
1201 : 1;
1202
1203 for (unsigned i = 0; i < num_components; ++i) {
1204 assert(src.swizzle[i] < src_components);
1205 if (src.swizzle[i] != i)
1206 need_swizzle = true;
1207 }
1208
1209 if (need_swizzle || num_components != src_components) {
1210 LLVMValueRef masks[] = {
1211 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1212 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1213 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1214 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1215
1216 if (src_components > 1 && num_components == 1) {
1217 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1218 masks[0], "");
1219 } else if (src_components == 1 && num_components > 1) {
1220 LLVMValueRef values[] = {value, value, value, value};
1221 value = ac_build_gather_values(&ctx->ac, values, num_components);
1222 } else {
1223 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1224 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1225 swizzle, "");
1226 }
1227 }
1228 assert(!src.negate);
1229 assert(!src.abs);
1230 return value;
1231 }
1232
1233 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1234 LLVMIntPredicate pred, LLVMValueRef src0,
1235 LLVMValueRef src1)
1236 {
1237 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1238 return LLVMBuildSelect(ctx->builder, result,
1239 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1240 ctx->i32_0, "");
1241 }
1242
1243 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1244 LLVMRealPredicate pred, LLVMValueRef src0,
1245 LLVMValueRef src1)
1246 {
1247 LLVMValueRef result;
1248 src0 = ac_to_float(ctx, src0);
1249 src1 = ac_to_float(ctx, src1);
1250 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1251 return LLVMBuildSelect(ctx->builder, result,
1252 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1253 ctx->i32_0, "");
1254 }
1255
1256 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1257 const char *intrin,
1258 LLVMTypeRef result_type,
1259 LLVMValueRef src0)
1260 {
1261 char name[64];
1262 LLVMValueRef params[] = {
1263 ac_to_float(ctx, src0),
1264 };
1265
1266 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1267 ac_get_elem_bits(ctx, result_type));
1268 assert(length < sizeof(name));
1269 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1270 }
1271
1272 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1273 const char *intrin,
1274 LLVMTypeRef result_type,
1275 LLVMValueRef src0, LLVMValueRef src1)
1276 {
1277 char name[64];
1278 LLVMValueRef params[] = {
1279 ac_to_float(ctx, src0),
1280 ac_to_float(ctx, src1),
1281 };
1282
1283 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1284 ac_get_elem_bits(ctx, result_type));
1285 assert(length < sizeof(name));
1286 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1287 }
1288
1289 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1290 const char *intrin,
1291 LLVMTypeRef result_type,
1292 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1293 {
1294 char name[64];
1295 LLVMValueRef params[] = {
1296 ac_to_float(ctx, src0),
1297 ac_to_float(ctx, src1),
1298 ac_to_float(ctx, src2),
1299 };
1300
1301 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1302 ac_get_elem_bits(ctx, result_type));
1303 assert(length < sizeof(name));
1304 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1305 }
1306
1307 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1308 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1309 {
1310 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1311 ctx->i32_0, "");
1312 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1313 }
1314
1315 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1316 LLVMIntPredicate pred,
1317 LLVMValueRef src0, LLVMValueRef src1)
1318 {
1319 return LLVMBuildSelect(ctx->builder,
1320 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1321 src0,
1322 src1, "");
1323
1324 }
1325 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1326 LLVMValueRef src0)
1327 {
1328 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1329 LLVMBuildNeg(ctx->builder, src0, ""));
1330 }
1331
1332 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1333 LLVMValueRef src0,
1334 unsigned bitsize)
1335 {
1336 LLVMValueRef cmp, val, zero, one;
1337 LLVMTypeRef type;
1338
1339 if (bitsize == 32) {
1340 type = ctx->f32;
1341 zero = ctx->f32_0;
1342 one = ctx->f32_1;
1343 } else {
1344 type = ctx->f64;
1345 zero = ctx->f64_0;
1346 one = ctx->f64_1;
1347 }
1348
1349 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1350 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1351 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1352 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1353 return val;
1354 }
1355
1356 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0, unsigned bitsize)
1358 {
1359 LLVMValueRef cmp, val, zero, one;
1360 LLVMTypeRef type;
1361
1362 if (bitsize == 32) {
1363 type = ctx->i32;
1364 zero = ctx->i32_0;
1365 one = ctx->i32_1;
1366 } else {
1367 type = ctx->i64;
1368 zero = ctx->i64_0;
1369 one = ctx->i64_1;
1370 }
1371
1372 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1373 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1374 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1375 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1376 return val;
1377 }
1378
1379 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1380 LLVMValueRef src0, unsigned bitsize)
1381 {
1382 LLVMTypeRef type;
1383 char *intr;
1384
1385 if (bitsize == 32) {
1386 intr = "llvm.floor.f32";
1387 type = ctx->f32;
1388 } else {
1389 intr = "llvm.floor.f64";
1390 type = ctx->f64;
1391 }
1392
1393 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1394 LLVMValueRef params[] = {
1395 fsrc0,
1396 };
1397 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1398 AC_FUNC_ATTR_READNONE);
1399 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1400 }
1401
1402 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1403 const char *intrin,
1404 LLVMValueRef src0, LLVMValueRef src1)
1405 {
1406 LLVMTypeRef ret_type;
1407 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1408 LLVMValueRef res;
1409 LLVMValueRef params[] = { src0, src1 };
1410 ret_type = LLVMStructTypeInContext(ctx->context, types,
1411 2, true);
1412
1413 res = ac_build_intrinsic(ctx, intrin, ret_type,
1414 params, 2, AC_FUNC_ATTR_READNONE);
1415
1416 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1417 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1418 return res;
1419 }
1420
1421 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1422 LLVMValueRef src0)
1423 {
1424 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1425 }
1426
1427 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1428 LLVMValueRef src0)
1429 {
1430 src0 = ac_to_float(ctx, src0);
1431 return LLVMBuildSExt(ctx->builder,
1432 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1433 ctx->i32, "");
1434 }
1435
1436 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1437 LLVMValueRef src0,
1438 unsigned bitsize)
1439 {
1440 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1441
1442 if (bitsize == 32)
1443 return result;
1444
1445 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1446 }
1447
1448 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1449 LLVMValueRef src0)
1450 {
1451 return LLVMBuildSExt(ctx->builder,
1452 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1453 ctx->i32, "");
1454 }
1455
1456 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1457 LLVMValueRef src0)
1458 {
1459 LLVMValueRef result;
1460 LLVMValueRef cond = NULL;
1461
1462 src0 = ac_to_float(ctx, src0);
1463 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1464
1465 if (ctx->chip_class >= VI) {
1466 LLVMValueRef args[2];
1467 /* Check if the result is a denormal - and flush to 0 if so. */
1468 args[0] = result;
1469 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1470 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1471 }
1472
1473 /* need to convert back up to f32 */
1474 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1475
1476 if (ctx->chip_class >= VI)
1477 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1478 else {
1479 /* for SI/CIK */
1480 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1481 * so compare the result and flush to 0 if it's smaller.
1482 */
1483 LLVMValueRef temp, cond2;
1484 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1485 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1486 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1487 temp, "");
1488 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1489 temp, ctx->f32_0, "");
1490 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1491 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1492 }
1493 return result;
1494 }
1495
1496 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1497 LLVMValueRef src0, LLVMValueRef src1)
1498 {
1499 LLVMValueRef dst64, result;
1500 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1501 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1502
1503 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1504 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1505 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1510 LLVMValueRef src0, LLVMValueRef src1)
1511 {
1512 LLVMValueRef dst64, result;
1513 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1514 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1515
1516 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1517 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1518 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1519 return result;
1520 }
1521
1522 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1523 bool is_signed,
1524 const LLVMValueRef srcs[3])
1525 {
1526 LLVMValueRef result;
1527 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1528
1529 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1530 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1531 return result;
1532 }
1533
1534 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1535 LLVMValueRef src0, LLVMValueRef src1,
1536 LLVMValueRef src2, LLVMValueRef src3)
1537 {
1538 LLVMValueRef bfi_args[3], result;
1539
1540 bfi_args[0] = LLVMBuildShl(ctx->builder,
1541 LLVMBuildSub(ctx->builder,
1542 LLVMBuildShl(ctx->builder,
1543 ctx->i32_1,
1544 src3, ""),
1545 ctx->i32_1, ""),
1546 src2, "");
1547 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1548 bfi_args[2] = src0;
1549
1550 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1551
1552 /* Calculate:
1553 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1554 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1555 */
1556 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1557 LLVMBuildAnd(ctx->builder, bfi_args[0],
1558 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1559
1560 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1561 return result;
1562 }
1563
1564 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1565 LLVMValueRef src0)
1566 {
1567 LLVMValueRef comp[2];
1568
1569 src0 = ac_to_float(ctx, src0);
1570 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1571 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1572
1573 return ac_build_cvt_pkrtz_f16(ctx, comp);
1574 }
1575
1576 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1577 LLVMValueRef src0)
1578 {
1579 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1580 LLVMValueRef temps[2], result, val;
1581 int i;
1582
1583 for (i = 0; i < 2; i++) {
1584 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1585 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1586 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1587 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1588 }
1589
1590 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1591 ctx->i32_0, "");
1592 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1593 ctx->i32_1, "");
1594 return result;
1595 }
1596
1597 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1598 nir_op op,
1599 LLVMValueRef src0)
1600 {
1601 unsigned mask;
1602 int idx;
1603 LLVMValueRef result;
1604
1605 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1606 mask = AC_TID_MASK_LEFT;
1607 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1608 mask = AC_TID_MASK_TOP;
1609 else
1610 mask = AC_TID_MASK_TOP_LEFT;
1611
1612 /* for DDX we want to next X pixel, DDY next Y pixel. */
1613 if (op == nir_op_fddx_fine ||
1614 op == nir_op_fddx_coarse ||
1615 op == nir_op_fddx)
1616 idx = 1;
1617 else
1618 idx = 2;
1619
1620 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1621 return result;
1622 }
1623
1624 /*
1625 * this takes an I,J coordinate pair,
1626 * and works out the X and Y derivatives.
1627 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1628 */
1629 static LLVMValueRef emit_ddxy_interp(
1630 struct ac_nir_context *ctx,
1631 LLVMValueRef interp_ij)
1632 {
1633 LLVMValueRef result[4], a;
1634 unsigned i;
1635
1636 for (i = 0; i < 2; i++) {
1637 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1638 LLVMConstInt(ctx->ac.i32, i, false), "");
1639 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1640 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1641 }
1642 return ac_build_gather_values(&ctx->ac, result, 4);
1643 }
1644
1645 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1646 {
1647 LLVMValueRef src[4], result = NULL;
1648 unsigned num_components = instr->dest.dest.ssa.num_components;
1649 unsigned src_components;
1650 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1651
1652 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1653 switch (instr->op) {
1654 case nir_op_vec2:
1655 case nir_op_vec3:
1656 case nir_op_vec4:
1657 src_components = 1;
1658 break;
1659 case nir_op_pack_half_2x16:
1660 src_components = 2;
1661 break;
1662 case nir_op_unpack_half_2x16:
1663 src_components = 1;
1664 break;
1665 default:
1666 src_components = num_components;
1667 break;
1668 }
1669 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1670 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1671
1672 switch (instr->op) {
1673 case nir_op_fmov:
1674 case nir_op_imov:
1675 result = src[0];
1676 break;
1677 case nir_op_fneg:
1678 src[0] = ac_to_float(&ctx->ac, src[0]);
1679 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1680 break;
1681 case nir_op_ineg:
1682 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1683 break;
1684 case nir_op_inot:
1685 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1686 break;
1687 case nir_op_iadd:
1688 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_fadd:
1691 src[0] = ac_to_float(&ctx->ac, src[0]);
1692 src[1] = ac_to_float(&ctx->ac, src[1]);
1693 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1694 break;
1695 case nir_op_fsub:
1696 src[0] = ac_to_float(&ctx->ac, src[0]);
1697 src[1] = ac_to_float(&ctx->ac, src[1]);
1698 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1699 break;
1700 case nir_op_isub:
1701 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_imul:
1704 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1705 break;
1706 case nir_op_imod:
1707 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1708 break;
1709 case nir_op_umod:
1710 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1711 break;
1712 case nir_op_fmod:
1713 src[0] = ac_to_float(&ctx->ac, src[0]);
1714 src[1] = ac_to_float(&ctx->ac, src[1]);
1715 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1716 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1717 ac_to_float_type(&ctx->ac, def_type), result);
1718 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1719 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1720 break;
1721 case nir_op_frem:
1722 src[0] = ac_to_float(&ctx->ac, src[0]);
1723 src[1] = ac_to_float(&ctx->ac, src[1]);
1724 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1725 break;
1726 case nir_op_irem:
1727 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1728 break;
1729 case nir_op_idiv:
1730 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1731 break;
1732 case nir_op_udiv:
1733 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1734 break;
1735 case nir_op_fmul:
1736 src[0] = ac_to_float(&ctx->ac, src[0]);
1737 src[1] = ac_to_float(&ctx->ac, src[1]);
1738 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1739 break;
1740 case nir_op_frcp:
1741 src[0] = ac_to_float(&ctx->ac, src[0]);
1742 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1743 src[0]);
1744 break;
1745 case nir_op_iand:
1746 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1747 break;
1748 case nir_op_ior:
1749 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1750 break;
1751 case nir_op_ixor:
1752 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1753 break;
1754 case nir_op_ishl:
1755 result = LLVMBuildShl(ctx->ac.builder, src[0],
1756 LLVMBuildZExt(ctx->ac.builder, src[1],
1757 LLVMTypeOf(src[0]), ""),
1758 "");
1759 break;
1760 case nir_op_ishr:
1761 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1762 LLVMBuildZExt(ctx->ac.builder, src[1],
1763 LLVMTypeOf(src[0]), ""),
1764 "");
1765 break;
1766 case nir_op_ushr:
1767 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1768 LLVMBuildZExt(ctx->ac.builder, src[1],
1769 LLVMTypeOf(src[0]), ""),
1770 "");
1771 break;
1772 case nir_op_ilt:
1773 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1774 break;
1775 case nir_op_ine:
1776 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1777 break;
1778 case nir_op_ieq:
1779 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1780 break;
1781 case nir_op_ige:
1782 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1783 break;
1784 case nir_op_ult:
1785 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1786 break;
1787 case nir_op_uge:
1788 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1789 break;
1790 case nir_op_feq:
1791 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1792 break;
1793 case nir_op_fne:
1794 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1795 break;
1796 case nir_op_flt:
1797 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1798 break;
1799 case nir_op_fge:
1800 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1801 break;
1802 case nir_op_fabs:
1803 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1804 ac_to_float_type(&ctx->ac, def_type), src[0]);
1805 break;
1806 case nir_op_iabs:
1807 result = emit_iabs(&ctx->ac, src[0]);
1808 break;
1809 case nir_op_imax:
1810 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1811 break;
1812 case nir_op_imin:
1813 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1814 break;
1815 case nir_op_umax:
1816 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1817 break;
1818 case nir_op_umin:
1819 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1820 break;
1821 case nir_op_isign:
1822 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1823 break;
1824 case nir_op_fsign:
1825 src[0] = ac_to_float(&ctx->ac, src[0]);
1826 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1827 break;
1828 case nir_op_ffloor:
1829 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1830 ac_to_float_type(&ctx->ac, def_type), src[0]);
1831 break;
1832 case nir_op_ftrunc:
1833 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1834 ac_to_float_type(&ctx->ac, def_type), src[0]);
1835 break;
1836 case nir_op_fceil:
1837 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1838 ac_to_float_type(&ctx->ac, def_type), src[0]);
1839 break;
1840 case nir_op_fround_even:
1841 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1842 ac_to_float_type(&ctx->ac, def_type),src[0]);
1843 break;
1844 case nir_op_ffract:
1845 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1846 break;
1847 case nir_op_fsin:
1848 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1849 ac_to_float_type(&ctx->ac, def_type), src[0]);
1850 break;
1851 case nir_op_fcos:
1852 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1853 ac_to_float_type(&ctx->ac, def_type), src[0]);
1854 break;
1855 case nir_op_fsqrt:
1856 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1857 ac_to_float_type(&ctx->ac, def_type), src[0]);
1858 break;
1859 case nir_op_fexp2:
1860 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1861 ac_to_float_type(&ctx->ac, def_type), src[0]);
1862 break;
1863 case nir_op_flog2:
1864 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1865 ac_to_float_type(&ctx->ac, def_type), src[0]);
1866 break;
1867 case nir_op_frsq:
1868 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1869 ac_to_float_type(&ctx->ac, def_type), src[0]);
1870 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1871 result);
1872 break;
1873 case nir_op_fpow:
1874 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1875 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1876 break;
1877 case nir_op_fmax:
1878 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1879 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1880 if (ctx->ac.chip_class < GFX9 &&
1881 instr->dest.dest.ssa.bit_size == 32) {
1882 /* Only pre-GFX9 chips do not flush denorms. */
1883 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1884 ac_to_float_type(&ctx->ac, def_type),
1885 result);
1886 }
1887 break;
1888 case nir_op_fmin:
1889 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1890 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1891 if (ctx->ac.chip_class < GFX9 &&
1892 instr->dest.dest.ssa.bit_size == 32) {
1893 /* Only pre-GFX9 chips do not flush denorms. */
1894 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1895 ac_to_float_type(&ctx->ac, def_type),
1896 result);
1897 }
1898 break;
1899 case nir_op_ffma:
1900 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1901 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1902 break;
1903 case nir_op_ibitfield_extract:
1904 result = emit_bitfield_extract(&ctx->ac, true, src);
1905 break;
1906 case nir_op_ubitfield_extract:
1907 result = emit_bitfield_extract(&ctx->ac, false, src);
1908 break;
1909 case nir_op_bitfield_insert:
1910 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1911 break;
1912 case nir_op_bitfield_reverse:
1913 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1914 break;
1915 case nir_op_bit_count:
1916 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1917 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1918 else {
1919 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1920 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1921 }
1922 break;
1923 case nir_op_vec2:
1924 case nir_op_vec3:
1925 case nir_op_vec4:
1926 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1927 src[i] = ac_to_integer(&ctx->ac, src[i]);
1928 result = ac_build_gather_values(&ctx->ac, src, num_components);
1929 break;
1930 case nir_op_f2i32:
1931 case nir_op_f2i64:
1932 src[0] = ac_to_float(&ctx->ac, src[0]);
1933 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1934 break;
1935 case nir_op_f2u32:
1936 case nir_op_f2u64:
1937 src[0] = ac_to_float(&ctx->ac, src[0]);
1938 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1939 break;
1940 case nir_op_i2f32:
1941 case nir_op_i2f64:
1942 src[0] = ac_to_integer(&ctx->ac, src[0]);
1943 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1944 break;
1945 case nir_op_u2f32:
1946 case nir_op_u2f64:
1947 src[0] = ac_to_integer(&ctx->ac, src[0]);
1948 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1949 break;
1950 case nir_op_f2f64:
1951 src[0] = ac_to_float(&ctx->ac, src[0]);
1952 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1953 break;
1954 case nir_op_f2f32:
1955 src[0] = ac_to_float(&ctx->ac, src[0]);
1956 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1957 break;
1958 case nir_op_u2u32:
1959 case nir_op_u2u64:
1960 src[0] = ac_to_integer(&ctx->ac, src[0]);
1961 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1962 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1963 else
1964 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1965 break;
1966 case nir_op_i2i32:
1967 case nir_op_i2i64:
1968 src[0] = ac_to_integer(&ctx->ac, src[0]);
1969 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1970 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1971 else
1972 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1973 break;
1974 case nir_op_bcsel:
1975 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1976 break;
1977 case nir_op_find_lsb:
1978 src[0] = ac_to_integer(&ctx->ac, src[0]);
1979 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1980 break;
1981 case nir_op_ufind_msb:
1982 src[0] = ac_to_integer(&ctx->ac, src[0]);
1983 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1984 break;
1985 case nir_op_ifind_msb:
1986 src[0] = ac_to_integer(&ctx->ac, src[0]);
1987 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1988 break;
1989 case nir_op_uadd_carry:
1990 src[0] = ac_to_integer(&ctx->ac, src[0]);
1991 src[1] = ac_to_integer(&ctx->ac, src[1]);
1992 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1993 break;
1994 case nir_op_usub_borrow:
1995 src[0] = ac_to_integer(&ctx->ac, src[0]);
1996 src[1] = ac_to_integer(&ctx->ac, src[1]);
1997 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1998 break;
1999 case nir_op_b2f:
2000 result = emit_b2f(&ctx->ac, src[0]);
2001 break;
2002 case nir_op_f2b:
2003 result = emit_f2b(&ctx->ac, src[0]);
2004 break;
2005 case nir_op_b2i:
2006 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2007 break;
2008 case nir_op_i2b:
2009 src[0] = ac_to_integer(&ctx->ac, src[0]);
2010 result = emit_i2b(&ctx->ac, src[0]);
2011 break;
2012 case nir_op_fquantize2f16:
2013 result = emit_f2f16(&ctx->ac, src[0]);
2014 break;
2015 case nir_op_umul_high:
2016 src[0] = ac_to_integer(&ctx->ac, src[0]);
2017 src[1] = ac_to_integer(&ctx->ac, src[1]);
2018 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2019 break;
2020 case nir_op_imul_high:
2021 src[0] = ac_to_integer(&ctx->ac, src[0]);
2022 src[1] = ac_to_integer(&ctx->ac, src[1]);
2023 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2024 break;
2025 case nir_op_pack_half_2x16:
2026 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2027 break;
2028 case nir_op_unpack_half_2x16:
2029 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2030 break;
2031 case nir_op_fddx:
2032 case nir_op_fddy:
2033 case nir_op_fddx_fine:
2034 case nir_op_fddy_fine:
2035 case nir_op_fddx_coarse:
2036 case nir_op_fddy_coarse:
2037 result = emit_ddxy(ctx, instr->op, src[0]);
2038 break;
2039
2040 case nir_op_unpack_64_2x32_split_x: {
2041 assert(ac_get_llvm_num_components(src[0]) == 1);
2042 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2043 ctx->ac.v2i32,
2044 "");
2045 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2046 ctx->ac.i32_0, "");
2047 break;
2048 }
2049
2050 case nir_op_unpack_64_2x32_split_y: {
2051 assert(ac_get_llvm_num_components(src[0]) == 1);
2052 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2053 ctx->ac.v2i32,
2054 "");
2055 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2056 ctx->ac.i32_1, "");
2057 break;
2058 }
2059
2060 case nir_op_pack_64_2x32_split: {
2061 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2062 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2063 src[0], ctx->ac.i32_0, "");
2064 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2065 src[1], ctx->ac.i32_1, "");
2066 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2067 break;
2068 }
2069
2070 default:
2071 fprintf(stderr, "Unknown NIR alu instr: ");
2072 nir_print_instr(&instr->instr, stderr);
2073 fprintf(stderr, "\n");
2074 abort();
2075 }
2076
2077 if (result) {
2078 assert(instr->dest.dest.is_ssa);
2079 result = ac_to_integer(&ctx->ac, result);
2080 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2081 result);
2082 }
2083 }
2084
2085 static void visit_load_const(struct ac_nir_context *ctx,
2086 const nir_load_const_instr *instr)
2087 {
2088 LLVMValueRef values[4], value = NULL;
2089 LLVMTypeRef element_type =
2090 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2091
2092 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2093 switch (instr->def.bit_size) {
2094 case 32:
2095 values[i] = LLVMConstInt(element_type,
2096 instr->value.u32[i], false);
2097 break;
2098 case 64:
2099 values[i] = LLVMConstInt(element_type,
2100 instr->value.u64[i], false);
2101 break;
2102 default:
2103 fprintf(stderr,
2104 "unsupported nir load_const bit_size: %d\n",
2105 instr->def.bit_size);
2106 abort();
2107 }
2108 }
2109 if (instr->def.num_components > 1) {
2110 value = LLVMConstVector(values, instr->def.num_components);
2111 } else
2112 value = values[0];
2113
2114 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2115 }
2116
2117 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2118 LLVMTypeRef type)
2119 {
2120 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2121 return LLVMBuildBitCast(ctx->builder, ptr,
2122 LLVMPointerType(type, addr_space), "");
2123 }
2124
2125 static LLVMValueRef
2126 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2127 {
2128 LLVMValueRef size =
2129 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2130 LLVMConstInt(ctx->ac.i32, 2, false), "");
2131
2132 /* VI only */
2133 if (ctx->ac.chip_class == VI && in_elements) {
2134 /* On VI, the descriptor contains the size in bytes,
2135 * but TXQ must return the size in elements.
2136 * The stride is always non-zero for resources using TXQ.
2137 */
2138 LLVMValueRef stride =
2139 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2140 ctx->ac.i32_1, "");
2141 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2142 LLVMConstInt(ctx->ac.i32, 16, false), "");
2143 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2144 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2145
2146 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2147 }
2148 return size;
2149 }
2150
2151 /**
2152 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2153 * intrinsic names).
2154 */
2155 static void build_int_type_name(
2156 LLVMTypeRef type,
2157 char *buf, unsigned bufsize)
2158 {
2159 assert(bufsize >= 6);
2160
2161 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2162 snprintf(buf, bufsize, "v%ui32",
2163 LLVMGetVectorSize(type));
2164 else
2165 strcpy(buf, "i32");
2166 }
2167
2168 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2169 struct ac_image_args *args,
2170 const nir_tex_instr *instr)
2171 {
2172 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2173 LLVMValueRef coord = args->addr;
2174 LLVMValueRef half_texel[2];
2175 LLVMValueRef compare_cube_wa = NULL;
2176 LLVMValueRef result;
2177 int c;
2178 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2179
2180 //TODO Rect
2181 {
2182 struct ac_image_args txq_args = { 0 };
2183
2184 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2185 txq_args.opcode = ac_image_get_resinfo;
2186 txq_args.dmask = 0xf;
2187 txq_args.addr = ctx->i32_0;
2188 txq_args.resource = args->resource;
2189 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2190
2191 for (c = 0; c < 2; c++) {
2192 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2193 LLVMConstInt(ctx->i32, c, false), "");
2194 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2195 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2196 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2197 LLVMConstReal(ctx->f32, -0.5), "");
2198 }
2199 }
2200
2201 LLVMValueRef orig_coords = args->addr;
2202
2203 for (c = 0; c < 2; c++) {
2204 LLVMValueRef tmp;
2205 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2206 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2207 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2208 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2209 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2210 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2211 }
2212
2213
2214 /*
2215 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2216 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2217 * workaround by sampling using a scaled type and converting.
2218 * This is taken from amdgpu-pro shaders.
2219 */
2220 /* NOTE this produces some ugly code compared to amdgpu-pro,
2221 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2222 * and then reads them back. -pro generates two selects,
2223 * one s_cmp for the descriptor rewriting
2224 * one v_cmp for the coordinate and result changes.
2225 */
2226 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2227 LLVMValueRef tmp, tmp2;
2228
2229 /* workaround 8/8/8/8 uint/sint cube gather bug */
2230 /* first detect it then change to a scaled read and f2i */
2231 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2232 tmp2 = tmp;
2233
2234 /* extract the DATA_FORMAT */
2235 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2236 LLVMConstInt(ctx->i32, 6, false), false);
2237
2238 /* is the DATA_FORMAT == 8_8_8_8 */
2239 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2240
2241 if (stype == GLSL_TYPE_UINT)
2242 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2243 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2244 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2245 else
2246 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2247 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2248 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2249
2250 /* replace the NUM FORMAT in the descriptor */
2251 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2252 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2253
2254 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2255
2256 /* don't modify the coordinates for this case */
2257 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2258 }
2259 args->addr = coord;
2260 result = ac_build_image_opcode(ctx, args);
2261
2262 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2263 LLVMValueRef tmp, tmp2;
2264
2265 /* if the cube workaround is in place, f2i the result. */
2266 for (c = 0; c < 4; c++) {
2267 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2268 if (stype == GLSL_TYPE_UINT)
2269 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2270 else
2271 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2272 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2273 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2274 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2275 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2276 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2277 }
2278 }
2279 return result;
2280 }
2281
2282 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2283 const nir_tex_instr *instr,
2284 bool lod_is_zero,
2285 struct ac_image_args *args)
2286 {
2287 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2288 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2289
2290 return ac_build_buffer_load_format(&ctx->ac,
2291 args->resource,
2292 args->addr,
2293 ctx->ac.i32_0,
2294 util_last_bit(mask),
2295 false, true);
2296 }
2297
2298 args->opcode = ac_image_sample;
2299 args->compare = instr->is_shadow;
2300
2301 switch (instr->op) {
2302 case nir_texop_txf:
2303 case nir_texop_txf_ms:
2304 case nir_texop_samples_identical:
2305 args->opcode = lod_is_zero ||
2306 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2307 ac_image_load : ac_image_load_mip;
2308 args->compare = false;
2309 args->offset = false;
2310 break;
2311 case nir_texop_txb:
2312 args->bias = true;
2313 break;
2314 case nir_texop_txl:
2315 if (lod_is_zero)
2316 args->level_zero = true;
2317 else
2318 args->lod = true;
2319 break;
2320 case nir_texop_txs:
2321 case nir_texop_query_levels:
2322 args->opcode = ac_image_get_resinfo;
2323 break;
2324 case nir_texop_tex:
2325 if (ctx->stage != MESA_SHADER_FRAGMENT)
2326 args->level_zero = true;
2327 break;
2328 case nir_texop_txd:
2329 args->deriv = true;
2330 break;
2331 case nir_texop_tg4:
2332 args->opcode = ac_image_gather4;
2333 args->level_zero = true;
2334 break;
2335 case nir_texop_lod:
2336 args->opcode = ac_image_get_lod;
2337 args->compare = false;
2338 args->offset = false;
2339 break;
2340 default:
2341 break;
2342 }
2343
2344 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2345 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2346 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2347 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2348 }
2349 }
2350 return ac_build_image_opcode(&ctx->ac, args);
2351 }
2352
2353 static LLVMValueRef
2354 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2355 unsigned desc_set, unsigned binding)
2356 {
2357 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2358 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2359 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2360 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2361 unsigned base_offset = layout->binding[binding].offset;
2362 LLVMValueRef offset, stride;
2363
2364 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2365 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2366 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2367 layout->binding[binding].dynamic_offset_offset;
2368 desc_ptr = ctx->abi.push_constants;
2369 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2370 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2371 } else
2372 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2373
2374 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2375 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2376 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2377
2378 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2379 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2380 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2381
2382 return desc_ptr;
2383 }
2384
2385 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2386 nir_intrinsic_instr *instr)
2387 {
2388 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2389 LLVMValueRef index = get_src(ctx, instr->src[1]);
2390
2391 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2392 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2393 return result;
2394 }
2395
2396 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2397 nir_intrinsic_instr *instr)
2398 {
2399 LLVMValueRef ptr, addr;
2400
2401 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2402 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2403 get_src(ctx, instr->src[0]), "");
2404
2405 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2406 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2407
2408 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2409 }
2410
2411 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2412 const nir_intrinsic_instr *instr)
2413 {
2414 LLVMValueRef index = get_src(ctx, instr->src[0]);
2415
2416 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2417 }
2418
2419 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2420 {
2421 uint32_t new_mask = 0;
2422 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2423 if (mask & (1u << i))
2424 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2425 return new_mask;
2426 }
2427
2428 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2429 unsigned start, unsigned count)
2430 {
2431 LLVMTypeRef type = LLVMTypeOf(src);
2432
2433 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2434 assert(start == 0);
2435 assert(count == 1);
2436 return src;
2437 }
2438
2439 unsigned src_elements = LLVMGetVectorSize(type);
2440 assert(start < src_elements);
2441 assert(start + count <= src_elements);
2442
2443 if (start == 0 && count == src_elements)
2444 return src;
2445
2446 if (count == 1)
2447 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2448
2449 assert(count <= 8);
2450 LLVMValueRef indices[8];
2451 for (unsigned i = 0; i < count; ++i)
2452 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2453
2454 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2455 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2456 }
2457
2458 static void visit_store_ssbo(struct ac_nir_context *ctx,
2459 nir_intrinsic_instr *instr)
2460 {
2461 const char *store_name;
2462 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2463 LLVMTypeRef data_type = ctx->ac.f32;
2464 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2465 int components_32bit = elem_size_mult * instr->num_components;
2466 unsigned writemask = nir_intrinsic_write_mask(instr);
2467 LLVMValueRef base_data, base_offset;
2468 LLVMValueRef params[6];
2469
2470 params[1] = ctx->abi->load_ssbo(ctx->abi,
2471 get_src(ctx, instr->src[1]), true);
2472 params[2] = ctx->ac.i32_0; /* vindex */
2473 params[4] = ctx->ac.i1false; /* glc */
2474 params[5] = ctx->ac.i1false; /* slc */
2475
2476 if (components_32bit > 1)
2477 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2478
2479 writemask = widen_mask(writemask, elem_size_mult);
2480
2481 base_data = ac_to_float(&ctx->ac, src_data);
2482 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2483 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2484 data_type, "");
2485 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2486 while (writemask) {
2487 int start, count;
2488 LLVMValueRef data;
2489 LLVMValueRef offset;
2490
2491 u_bit_scan_consecutive_range(&writemask, &start, &count);
2492
2493 /* Due to an LLVM limitation, split 3-element writes
2494 * into a 2-element and a 1-element write. */
2495 if (count == 3) {
2496 writemask |= 1 << (start + 2);
2497 count = 2;
2498 }
2499
2500 if (count > 4) {
2501 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2502 count = 4;
2503 }
2504
2505 if (count == 4) {
2506 store_name = "llvm.amdgcn.buffer.store.v4f32";
2507 } else if (count == 2) {
2508 store_name = "llvm.amdgcn.buffer.store.v2f32";
2509
2510 } else {
2511 assert(count == 1);
2512 store_name = "llvm.amdgcn.buffer.store.f32";
2513 }
2514 data = extract_vector_range(&ctx->ac, base_data, start, count);
2515
2516 offset = base_offset;
2517 if (start != 0) {
2518 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2519 }
2520 params[0] = data;
2521 params[3] = offset;
2522 ac_build_intrinsic(&ctx->ac, store_name,
2523 ctx->ac.voidt, params, 6, 0);
2524 }
2525 }
2526
2527 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2528 const nir_intrinsic_instr *instr)
2529 {
2530 const char *name;
2531 LLVMValueRef params[6];
2532 int arg_count = 0;
2533
2534 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2535 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2536 }
2537 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2538 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2539 get_src(ctx, instr->src[0]),
2540 true);
2541 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2542 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2543 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2544
2545 switch (instr->intrinsic) {
2546 case nir_intrinsic_ssbo_atomic_add:
2547 name = "llvm.amdgcn.buffer.atomic.add";
2548 break;
2549 case nir_intrinsic_ssbo_atomic_imin:
2550 name = "llvm.amdgcn.buffer.atomic.smin";
2551 break;
2552 case nir_intrinsic_ssbo_atomic_umin:
2553 name = "llvm.amdgcn.buffer.atomic.umin";
2554 break;
2555 case nir_intrinsic_ssbo_atomic_imax:
2556 name = "llvm.amdgcn.buffer.atomic.smax";
2557 break;
2558 case nir_intrinsic_ssbo_atomic_umax:
2559 name = "llvm.amdgcn.buffer.atomic.umax";
2560 break;
2561 case nir_intrinsic_ssbo_atomic_and:
2562 name = "llvm.amdgcn.buffer.atomic.and";
2563 break;
2564 case nir_intrinsic_ssbo_atomic_or:
2565 name = "llvm.amdgcn.buffer.atomic.or";
2566 break;
2567 case nir_intrinsic_ssbo_atomic_xor:
2568 name = "llvm.amdgcn.buffer.atomic.xor";
2569 break;
2570 case nir_intrinsic_ssbo_atomic_exchange:
2571 name = "llvm.amdgcn.buffer.atomic.swap";
2572 break;
2573 case nir_intrinsic_ssbo_atomic_comp_swap:
2574 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2575 break;
2576 default:
2577 abort();
2578 }
2579
2580 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2581 }
2582
2583 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2584 const nir_intrinsic_instr *instr)
2585 {
2586 LLVMValueRef results[2];
2587 int load_components;
2588 int num_components = instr->num_components;
2589 if (instr->dest.ssa.bit_size == 64)
2590 num_components *= 2;
2591
2592 for (int i = 0; i < num_components; i += load_components) {
2593 load_components = MIN2(num_components - i, 4);
2594 const char *load_name;
2595 LLVMTypeRef data_type = ctx->ac.f32;
2596 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2597 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2598
2599 if (load_components == 3)
2600 data_type = LLVMVectorType(ctx->ac.f32, 4);
2601 else if (load_components > 1)
2602 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2603
2604 if (load_components >= 3)
2605 load_name = "llvm.amdgcn.buffer.load.v4f32";
2606 else if (load_components == 2)
2607 load_name = "llvm.amdgcn.buffer.load.v2f32";
2608 else if (load_components == 1)
2609 load_name = "llvm.amdgcn.buffer.load.f32";
2610 else
2611 unreachable("unhandled number of components");
2612
2613 LLVMValueRef params[] = {
2614 ctx->abi->load_ssbo(ctx->abi,
2615 get_src(ctx, instr->src[0]),
2616 false),
2617 ctx->ac.i32_0,
2618 offset,
2619 ctx->ac.i1false,
2620 ctx->ac.i1false,
2621 };
2622
2623 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2624 }
2625
2626 assume(results[0]);
2627 LLVMValueRef ret = results[0];
2628 if (num_components > 4 || num_components == 3) {
2629 LLVMValueRef masks[] = {
2630 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2631 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2632 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2633 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2634 };
2635
2636 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2637 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2638 results[num_components > 4 ? 1 : 0], swizzle, "");
2639 }
2640
2641 return LLVMBuildBitCast(ctx->ac.builder, ret,
2642 get_def_type(ctx, &instr->dest.ssa), "");
2643 }
2644
2645 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2646 const nir_intrinsic_instr *instr)
2647 {
2648 LLVMValueRef ret;
2649 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2650 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2651 int num_components = instr->num_components;
2652
2653 if (ctx->abi->load_ubo)
2654 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2655
2656 if (instr->dest.ssa.bit_size == 64)
2657 num_components *= 2;
2658
2659 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2660 NULL, 0, false, false, true, true);
2661 ret = trim_vector(&ctx->ac, ret, num_components);
2662 return LLVMBuildBitCast(ctx->ac.builder, ret,
2663 get_def_type(ctx, &instr->dest.ssa), "");
2664 }
2665
2666 static void
2667 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2668 bool vs_in, unsigned *vertex_index_out,
2669 LLVMValueRef *vertex_index_ref,
2670 unsigned *const_out, LLVMValueRef *indir_out)
2671 {
2672 unsigned const_offset = 0;
2673 nir_deref *tail = &deref->deref;
2674 LLVMValueRef offset = NULL;
2675
2676 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2677 tail = tail->child;
2678 nir_deref_array *deref_array = nir_deref_as_array(tail);
2679 if (vertex_index_out)
2680 *vertex_index_out = deref_array->base_offset;
2681
2682 if (vertex_index_ref) {
2683 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2684 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2685 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2686 }
2687 *vertex_index_ref = vtx;
2688 }
2689 }
2690
2691 if (deref->var->data.compact) {
2692 assert(tail->child->deref_type == nir_deref_type_array);
2693 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2694 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2695 /* We always lower indirect dereferences for "compact" array vars. */
2696 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2697
2698 const_offset = deref_array->base_offset;
2699 goto out;
2700 }
2701
2702 while (tail->child != NULL) {
2703 const struct glsl_type *parent_type = tail->type;
2704 tail = tail->child;
2705
2706 if (tail->deref_type == nir_deref_type_array) {
2707 nir_deref_array *deref_array = nir_deref_as_array(tail);
2708 LLVMValueRef index, stride, local_offset;
2709 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2710
2711 const_offset += size * deref_array->base_offset;
2712 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2713 continue;
2714
2715 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2716 index = get_src(ctx, deref_array->indirect);
2717 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2718 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2719
2720 if (offset)
2721 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2722 else
2723 offset = local_offset;
2724 } else if (tail->deref_type == nir_deref_type_struct) {
2725 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2726
2727 for (unsigned i = 0; i < deref_struct->index; i++) {
2728 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2729 const_offset += glsl_count_attribute_slots(ft, vs_in);
2730 }
2731 } else
2732 unreachable("unsupported deref type");
2733
2734 }
2735 out:
2736 if (const_offset && offset)
2737 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2738 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2739 "");
2740
2741 *const_out = const_offset;
2742 *indir_out = offset;
2743 }
2744
2745
2746 /* The offchip buffer layout for TCS->TES is
2747 *
2748 * - attribute 0 of patch 0 vertex 0
2749 * - attribute 0 of patch 0 vertex 1
2750 * - attribute 0 of patch 0 vertex 2
2751 * ...
2752 * - attribute 0 of patch 1 vertex 0
2753 * - attribute 0 of patch 1 vertex 1
2754 * ...
2755 * - attribute 1 of patch 0 vertex 0
2756 * - attribute 1 of patch 0 vertex 1
2757 * ...
2758 * - per patch attribute 0 of patch 0
2759 * - per patch attribute 0 of patch 1
2760 * ...
2761 *
2762 * Note that every attribute has 4 components.
2763 */
2764 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2765 LLVMValueRef vertex_index,
2766 LLVMValueRef param_index)
2767 {
2768 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2769 LLVMValueRef param_stride, constant16;
2770 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2771
2772 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2773 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2774 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2775 num_patches, "");
2776
2777 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2778 if (vertex_index) {
2779 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2780 vertices_per_patch, "");
2781
2782 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2783 vertex_index, "");
2784
2785 param_stride = total_vertices;
2786 } else {
2787 base_addr = rel_patch_id;
2788 param_stride = num_patches;
2789 }
2790
2791 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2792 LLVMBuildMul(ctx->ac.builder, param_index,
2793 param_stride, ""), "");
2794
2795 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2796
2797 if (!vertex_index) {
2798 LLVMValueRef patch_data_offset =
2799 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2800
2801 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2802 patch_data_offset, "");
2803 }
2804 return base_addr;
2805 }
2806
2807 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2808 unsigned param,
2809 unsigned const_index,
2810 bool is_compact,
2811 LLVMValueRef vertex_index,
2812 LLVMValueRef indir_index)
2813 {
2814 LLVMValueRef param_index;
2815
2816 if (indir_index)
2817 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2818 indir_index, "");
2819 else {
2820 if (const_index && !is_compact)
2821 param += const_index;
2822 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2823 }
2824 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2825 }
2826
2827 static void
2828 mark_tess_output(struct radv_shader_context *ctx,
2829 bool is_patch, uint32_t param)
2830
2831 {
2832 if (is_patch) {
2833 ctx->tess_patch_outputs_written |= (1ull << param);
2834 } else
2835 ctx->tess_outputs_written |= (1ull << param);
2836 }
2837
2838 static LLVMValueRef
2839 get_dw_address(struct radv_shader_context *ctx,
2840 LLVMValueRef dw_addr,
2841 unsigned param,
2842 unsigned const_index,
2843 bool compact_const_index,
2844 LLVMValueRef vertex_index,
2845 LLVMValueRef stride,
2846 LLVMValueRef indir_index)
2847
2848 {
2849
2850 if (vertex_index) {
2851 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2852 LLVMBuildMul(ctx->ac.builder,
2853 vertex_index,
2854 stride, ""), "");
2855 }
2856
2857 if (indir_index)
2858 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2859 LLVMBuildMul(ctx->ac.builder, indir_index,
2860 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2861 else if (const_index && !compact_const_index)
2862 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2863 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2864
2865 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2866 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2867
2868 if (const_index && compact_const_index)
2869 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2870 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2871 return dw_addr;
2872 }
2873
2874 static LLVMValueRef
2875 load_tcs_varyings(struct ac_shader_abi *abi,
2876 LLVMValueRef vertex_index,
2877 LLVMValueRef indir_index,
2878 unsigned const_index,
2879 unsigned location,
2880 unsigned driver_location,
2881 unsigned component,
2882 unsigned num_components,
2883 bool is_patch,
2884 bool is_compact,
2885 bool load_input)
2886 {
2887 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2888 LLVMValueRef dw_addr, stride;
2889 LLVMValueRef value[4], result;
2890 unsigned param = shader_io_get_unique_index(location);
2891
2892 if (load_input) {
2893 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2894 dw_addr = get_tcs_in_current_patch_offset(ctx);
2895 } else {
2896 if (!is_patch) {
2897 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2898 dw_addr = get_tcs_out_current_patch_offset(ctx);
2899 } else {
2900 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2901 stride = NULL;
2902 }
2903 }
2904
2905 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2906 indir_index);
2907
2908 for (unsigned i = 0; i < num_components + component; i++) {
2909 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2910 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2911 ctx->ac.i32_1, "");
2912 }
2913 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2914 return result;
2915 }
2916
2917 static void
2918 store_tcs_output(struct ac_shader_abi *abi,
2919 LLVMValueRef vertex_index,
2920 LLVMValueRef param_index,
2921 unsigned const_index,
2922 unsigned location,
2923 unsigned driver_location,
2924 LLVMValueRef src,
2925 unsigned component,
2926 bool is_patch,
2927 bool is_compact,
2928 unsigned writemask)
2929 {
2930 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2931 LLVMValueRef dw_addr;
2932 LLVMValueRef stride = NULL;
2933 LLVMValueRef buf_addr = NULL;
2934 unsigned param;
2935 bool store_lds = true;
2936
2937 if (is_patch) {
2938 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2939 store_lds = false;
2940 } else {
2941 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2942 store_lds = false;
2943 }
2944
2945 param = shader_io_get_unique_index(location);
2946 if (location == VARYING_SLOT_CLIP_DIST0 &&
2947 is_compact && const_index > 3) {
2948 const_index -= 3;
2949 param++;
2950 }
2951
2952 if (!is_patch) {
2953 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2954 dw_addr = get_tcs_out_current_patch_offset(ctx);
2955 } else {
2956 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2957 }
2958
2959 mark_tess_output(ctx, is_patch, param);
2960
2961 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2962 param_index);
2963 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2964 vertex_index, param_index);
2965
2966 bool is_tess_factor = false;
2967 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2968 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2969 is_tess_factor = true;
2970
2971 unsigned base = is_compact ? const_index : 0;
2972 for (unsigned chan = 0; chan < 8; chan++) {
2973 if (!(writemask & (1 << chan)))
2974 continue;
2975 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2976
2977 if (store_lds || is_tess_factor) {
2978 LLVMValueRef dw_addr_chan =
2979 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2980 LLVMConstInt(ctx->ac.i32, chan, false), "");
2981 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2982 }
2983
2984 if (!is_tess_factor && writemask != 0xF)
2985 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2986 buf_addr, ctx->oc_lds,
2987 4 * (base + chan), 1, 0, true, false);
2988 }
2989
2990 if (writemask == 0xF) {
2991 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2992 buf_addr, ctx->oc_lds,
2993 (base * 4), 1, 0, true, false);
2994 }
2995 }
2996
2997 static LLVMValueRef
2998 load_tes_input(struct ac_shader_abi *abi,
2999 LLVMValueRef vertex_index,
3000 LLVMValueRef param_index,
3001 unsigned const_index,
3002 unsigned location,
3003 unsigned driver_location,
3004 unsigned component,
3005 unsigned num_components,
3006 bool is_patch,
3007 bool is_compact,
3008 bool load_input)
3009 {
3010 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3011 LLVMValueRef buf_addr;
3012 LLVMValueRef result;
3013 unsigned param = shader_io_get_unique_index(location);
3014
3015 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3016 const_index -= 3;
3017 param++;
3018 }
3019
3020 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3021 is_compact, vertex_index, param_index);
3022
3023 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3024 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3025
3026 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3027 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3028 result = trim_vector(&ctx->ac, result, num_components);
3029 return result;
3030 }
3031
3032 static LLVMValueRef
3033 load_gs_input(struct ac_shader_abi *abi,
3034 unsigned location,
3035 unsigned driver_location,
3036 unsigned component,
3037 unsigned num_components,
3038 unsigned vertex_index,
3039 unsigned const_index,
3040 LLVMTypeRef type)
3041 {
3042 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3043 LLVMValueRef vtx_offset;
3044 unsigned param, vtx_offset_param;
3045 LLVMValueRef value[4], result;
3046
3047 vtx_offset_param = vertex_index;
3048 assert(vtx_offset_param < 6);
3049 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3050 LLVMConstInt(ctx->ac.i32, 4, false), "");
3051
3052 param = shader_io_get_unique_index(location);
3053
3054 for (unsigned i = component; i < num_components + component; i++) {
3055 if (ctx->ac.chip_class >= GFX9) {
3056 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3057 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3058 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3059 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3060 } else {
3061 LLVMValueRef soffset =
3062 LLVMConstInt(ctx->ac.i32,
3063 (param * 4 + i + const_index) * 256,
3064 false);
3065
3066 value[i] = ac_build_buffer_load(&ctx->ac,
3067 ctx->esgs_ring, 1,
3068 ctx->ac.i32_0,
3069 vtx_offset, soffset,
3070 0, 1, 0, true, false);
3071
3072 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3073 type, "");
3074 }
3075 }
3076 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3077 result = ac_to_integer(&ctx->ac, result);
3078 return result;
3079 }
3080
3081 static LLVMValueRef
3082 build_gep_for_deref(struct ac_nir_context *ctx,
3083 nir_deref_var *deref)
3084 {
3085 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3086 assert(entry->data);
3087 LLVMValueRef val = entry->data;
3088 nir_deref *tail = deref->deref.child;
3089 while (tail != NULL) {
3090 LLVMValueRef offset;
3091 switch (tail->deref_type) {
3092 case nir_deref_type_array: {
3093 nir_deref_array *array = nir_deref_as_array(tail);
3094 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3095 if (array->deref_array_type ==
3096 nir_deref_array_type_indirect) {
3097 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3098 get_src(ctx,
3099 array->indirect),
3100 "");
3101 }
3102 break;
3103 }
3104 case nir_deref_type_struct: {
3105 nir_deref_struct *deref_struct =
3106 nir_deref_as_struct(tail);
3107 offset = LLVMConstInt(ctx->ac.i32,
3108 deref_struct->index, 0);
3109 break;
3110 }
3111 default:
3112 unreachable("bad deref type");
3113 }
3114 val = ac_build_gep0(&ctx->ac, val, offset);
3115 tail = tail->child;
3116 }
3117 return val;
3118 }
3119
3120 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3121 nir_intrinsic_instr *instr,
3122 bool load_inputs)
3123 {
3124 LLVMValueRef result;
3125 LLVMValueRef vertex_index = NULL;
3126 LLVMValueRef indir_index = NULL;
3127 unsigned const_index = 0;
3128 unsigned location = instr->variables[0]->var->data.location;
3129 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3130 const bool is_patch = instr->variables[0]->var->data.patch;
3131 const bool is_compact = instr->variables[0]->var->data.compact;
3132
3133 get_deref_offset(ctx, instr->variables[0],
3134 false, NULL, is_patch ? NULL : &vertex_index,
3135 &const_index, &indir_index);
3136
3137 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3138 const_index, location, driver_location,
3139 instr->variables[0]->var->data.location_frac,
3140 instr->num_components,
3141 is_patch, is_compact, load_inputs);
3142 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3143 }
3144
3145 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3146 nir_intrinsic_instr *instr)
3147 {
3148 LLVMValueRef values[8];
3149 int idx = instr->variables[0]->var->data.driver_location;
3150 int ve = instr->dest.ssa.num_components;
3151 unsigned comp = instr->variables[0]->var->data.location_frac;
3152 LLVMValueRef indir_index;
3153 LLVMValueRef ret;
3154 unsigned const_index;
3155 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3156 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3157 instr->variables[0]->var->data.mode == nir_var_shader_in;
3158 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3159 &const_index, &indir_index);
3160
3161 if (instr->dest.ssa.bit_size == 64)
3162 ve *= 2;
3163
3164 switch (instr->variables[0]->var->data.mode) {
3165 case nir_var_shader_in:
3166 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3167 ctx->stage == MESA_SHADER_TESS_EVAL) {
3168 return load_tess_varyings(ctx, instr, true);
3169 }
3170
3171 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3172 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3173 LLVMValueRef indir_index;
3174 unsigned const_index, vertex_index;
3175 get_deref_offset(ctx, instr->variables[0],
3176 false, &vertex_index, NULL,
3177 &const_index, &indir_index);
3178
3179 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3180 instr->variables[0]->var->data.driver_location,
3181 instr->variables[0]->var->data.location_frac, ve,
3182 vertex_index, const_index, type);
3183 }
3184
3185 for (unsigned chan = comp; chan < ve + comp; chan++) {
3186 if (indir_index) {
3187 unsigned count = glsl_count_attribute_slots(
3188 instr->variables[0]->var->type,
3189 ctx->stage == MESA_SHADER_VERTEX);
3190 count -= chan / 4;
3191 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3192 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3193 stride, false, true);
3194
3195 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3196 tmp_vec,
3197 indir_index, "");
3198 } else
3199 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3200 }
3201 break;
3202 case nir_var_local:
3203 for (unsigned chan = 0; chan < ve; chan++) {
3204 if (indir_index) {
3205 unsigned count = glsl_count_attribute_slots(
3206 instr->variables[0]->var->type, false);
3207 count -= chan / 4;
3208 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3209 &ctx->ac, ctx->locals + idx + chan, count,
3210 stride, true, true);
3211
3212 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3213 tmp_vec,
3214 indir_index, "");
3215 } else {
3216 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3217 }
3218 }
3219 break;
3220 case nir_var_shared: {
3221 LLVMValueRef address = build_gep_for_deref(ctx,
3222 instr->variables[0]);
3223 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3224 return LLVMBuildBitCast(ctx->ac.builder, val,
3225 get_def_type(ctx, &instr->dest.ssa),
3226 "");
3227 }
3228 case nir_var_shader_out:
3229 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3230 return load_tess_varyings(ctx, instr, false);
3231 }
3232
3233 for (unsigned chan = comp; chan < ve + comp; chan++) {
3234 if (indir_index) {
3235 unsigned count = glsl_count_attribute_slots(
3236 instr->variables[0]->var->type, false);
3237 count -= chan / 4;
3238 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3239 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3240 stride, true, true);
3241
3242 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3243 tmp_vec,
3244 indir_index, "");
3245 } else {
3246 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3247 ctx->abi->outputs[idx + chan + const_index * stride],
3248 "");
3249 }
3250 }
3251 break;
3252 default:
3253 unreachable("unhandle variable mode");
3254 }
3255 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3256 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3257 }
3258
3259 static void
3260 visit_store_var(struct ac_nir_context *ctx,
3261 nir_intrinsic_instr *instr)
3262 {
3263 LLVMValueRef temp_ptr, value;
3264 int idx = instr->variables[0]->var->data.driver_location;
3265 unsigned comp = instr->variables[0]->var->data.location_frac;
3266 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3267 int writemask = instr->const_index[0] << comp;
3268 LLVMValueRef indir_index;
3269 unsigned const_index;
3270 get_deref_offset(ctx, instr->variables[0], false,
3271 NULL, NULL, &const_index, &indir_index);
3272
3273 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3274
3275 src = LLVMBuildBitCast(ctx->ac.builder, src,
3276 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3277 "");
3278
3279 writemask = widen_mask(writemask, 2);
3280 }
3281
3282 switch (instr->variables[0]->var->data.mode) {
3283 case nir_var_shader_out:
3284
3285 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3286 LLVMValueRef vertex_index = NULL;
3287 LLVMValueRef indir_index = NULL;
3288 unsigned const_index = 0;
3289 const unsigned location = instr->variables[0]->var->data.location;
3290 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3291 const unsigned comp = instr->variables[0]->var->data.location_frac;
3292 const bool is_patch = instr->variables[0]->var->data.patch;
3293 const bool is_compact = instr->variables[0]->var->data.compact;
3294
3295 get_deref_offset(ctx, instr->variables[0],
3296 false, NULL, is_patch ? NULL : &vertex_index,
3297 &const_index, &indir_index);
3298
3299 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3300 const_index, location, driver_location,
3301 src, comp, is_patch, is_compact, writemask);
3302 return;
3303 }
3304
3305 for (unsigned chan = 0; chan < 8; chan++) {
3306 int stride = 4;
3307 if (!(writemask & (1 << chan)))
3308 continue;
3309
3310 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3311
3312 if (instr->variables[0]->var->data.compact)
3313 stride = 1;
3314 if (indir_index) {
3315 unsigned count = glsl_count_attribute_slots(
3316 instr->variables[0]->var->type, false);
3317 count -= chan / 4;
3318 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3319 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3320 stride, true, true);
3321
3322 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3323 value, indir_index, "");
3324 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3325 count, stride, tmp_vec);
3326
3327 } else {
3328 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3329
3330 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3331 }
3332 }
3333 break;
3334 case nir_var_local:
3335 for (unsigned chan = 0; chan < 8; chan++) {
3336 if (!(writemask & (1 << chan)))
3337 continue;
3338
3339 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3340 if (indir_index) {
3341 unsigned count = glsl_count_attribute_slots(
3342 instr->variables[0]->var->type, false);
3343 count -= chan / 4;
3344 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3345 &ctx->ac, ctx->locals + idx + chan, count,
3346 4, true, true);
3347
3348 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3349 value, indir_index, "");
3350 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3351 count, 4, tmp_vec);
3352 } else {
3353 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3354
3355 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3356 }
3357 }
3358 break;
3359 case nir_var_shared: {
3360 int writemask = instr->const_index[0];
3361 LLVMValueRef address = build_gep_for_deref(ctx,
3362 instr->variables[0]);
3363 LLVMValueRef val = get_src(ctx, instr->src[0]);
3364 unsigned components =
3365 glsl_get_vector_elements(
3366 nir_deref_tail(&instr->variables[0]->deref)->type);
3367 if (writemask == (1 << components) - 1) {
3368 val = LLVMBuildBitCast(
3369 ctx->ac.builder, val,
3370 LLVMGetElementType(LLVMTypeOf(address)), "");
3371 LLVMBuildStore(ctx->ac.builder, val, address);
3372 } else {
3373 for (unsigned chan = 0; chan < 4; chan++) {
3374 if (!(writemask & (1 << chan)))
3375 continue;
3376 LLVMValueRef ptr =
3377 LLVMBuildStructGEP(ctx->ac.builder,
3378 address, chan, "");
3379 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3380 chan);
3381 src = LLVMBuildBitCast(
3382 ctx->ac.builder, src,
3383 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3384 LLVMBuildStore(ctx->ac.builder, src, ptr);
3385 }
3386 }
3387 break;
3388 }
3389 default:
3390 break;
3391 }
3392 }
3393
3394 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3395 {
3396 switch (dim) {
3397 case GLSL_SAMPLER_DIM_BUF:
3398 return 1;
3399 case GLSL_SAMPLER_DIM_1D:
3400 return array ? 2 : 1;
3401 case GLSL_SAMPLER_DIM_2D:
3402 return array ? 3 : 2;
3403 case GLSL_SAMPLER_DIM_MS:
3404 return array ? 4 : 3;
3405 case GLSL_SAMPLER_DIM_3D:
3406 case GLSL_SAMPLER_DIM_CUBE:
3407 return 3;
3408 case GLSL_SAMPLER_DIM_RECT:
3409 case GLSL_SAMPLER_DIM_SUBPASS:
3410 return 2;
3411 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3412 return 3;
3413 default:
3414 break;
3415 }
3416 return 0;
3417 }
3418
3419
3420
3421 /* Adjust the sample index according to FMASK.
3422 *
3423 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3424 * which is the identity mapping. Each nibble says which physical sample
3425 * should be fetched to get that sample.
3426 *
3427 * For example, 0x11111100 means there are only 2 samples stored and
3428 * the second sample covers 3/4 of the pixel. When reading samples 0
3429 * and 1, return physical sample 0 (determined by the first two 0s
3430 * in FMASK), otherwise return physical sample 1.
3431 *
3432 * The sample index should be adjusted as follows:
3433 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3434 */
3435 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3436 LLVMValueRef coord_x, LLVMValueRef coord_y,
3437 LLVMValueRef coord_z,
3438 LLVMValueRef sample_index,
3439 LLVMValueRef fmask_desc_ptr)
3440 {
3441 LLVMValueRef fmask_load_address[4];
3442 LLVMValueRef res;
3443
3444 fmask_load_address[0] = coord_x;
3445 fmask_load_address[1] = coord_y;
3446 if (coord_z) {
3447 fmask_load_address[2] = coord_z;
3448 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3449 }
3450
3451 struct ac_image_args args = {0};
3452
3453 args.opcode = ac_image_load;
3454 args.da = coord_z ? true : false;
3455 args.resource = fmask_desc_ptr;
3456 args.dmask = 0xf;
3457 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3458
3459 res = ac_build_image_opcode(ctx, &args);
3460
3461 res = ac_to_integer(ctx, res);
3462 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3463 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3464
3465 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3466 res,
3467 ctx->i32_0, "");
3468
3469 LLVMValueRef sample_index4 =
3470 LLVMBuildMul(ctx->builder, sample_index, four, "");
3471 LLVMValueRef shifted_fmask =
3472 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3473 LLVMValueRef final_sample =
3474 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3475
3476 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3477 * resource descriptor is 0 (invalid),
3478 */
3479 LLVMValueRef fmask_desc =
3480 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3481 ctx->v8i32, "");
3482
3483 LLVMValueRef fmask_word1 =
3484 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3485 ctx->i32_1, "");
3486
3487 LLVMValueRef word1_is_nonzero =
3488 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3489 fmask_word1, ctx->i32_0, "");
3490
3491 /* Replace the MSAA sample index. */
3492 sample_index =
3493 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3494 final_sample, sample_index, "");
3495 return sample_index;
3496 }
3497
3498 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3499 const nir_intrinsic_instr *instr)
3500 {
3501 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3502
3503 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3504 LLVMValueRef coords[4];
3505 LLVMValueRef masks[] = {
3506 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3507 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3508 };
3509 LLVMValueRef res;
3510 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3511
3512 int count;
3513 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3514 bool is_array = glsl_sampler_type_is_array(type);
3515 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3516 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3517 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3518 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3519 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3520 count = image_type_to_components_count(dim, is_array);
3521
3522 if (is_ms) {
3523 LLVMValueRef fmask_load_address[3];
3524 int chan;
3525
3526 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3527 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3528 if (is_array)
3529 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3530 else
3531 fmask_load_address[2] = NULL;
3532 if (add_frag_pos) {
3533 for (chan = 0; chan < 2; ++chan)
3534 fmask_load_address[chan] =
3535 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3536 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3537 ctx->ac.i32, ""), "");
3538 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3539 }
3540 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3541 fmask_load_address[0],
3542 fmask_load_address[1],
3543 fmask_load_address[2],
3544 sample_index,
3545 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3546 }
3547 if (count == 1 && !gfx9_1d) {
3548 if (instr->src[0].ssa->num_components)
3549 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3550 else
3551 res = src0;
3552 } else {
3553 int chan;
3554 if (is_ms)
3555 count--;
3556 for (chan = 0; chan < count; ++chan) {
3557 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3558 }
3559 if (add_frag_pos) {
3560 for (chan = 0; chan < 2; ++chan)
3561 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3562 ctx->ac.i32, ""), "");
3563 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3564 count++;
3565 }
3566
3567 if (gfx9_1d) {
3568 if (is_array) {
3569 coords[2] = coords[1];
3570 coords[1] = ctx->ac.i32_0;
3571 } else
3572 coords[1] = ctx->ac.i32_0;
3573 count++;
3574 }
3575
3576 if (is_ms) {
3577 coords[count] = sample_index;
3578 count++;
3579 }
3580
3581 if (count == 3) {
3582 coords[3] = LLVMGetUndef(ctx->ac.i32);
3583 count = 4;
3584 }
3585 res = ac_build_gather_values(&ctx->ac, coords, count);
3586 }
3587 return res;
3588 }
3589
3590 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3591 const nir_intrinsic_instr *instr)
3592 {
3593 LLVMValueRef params[7];
3594 LLVMValueRef res;
3595 char intrinsic_name[64];
3596 const nir_variable *var = instr->variables[0]->var;
3597 const struct glsl_type *type = var->type;
3598
3599 if(instr->variables[0]->deref.child)
3600 type = instr->variables[0]->deref.child->type;
3601
3602 type = glsl_without_array(type);
3603
3604 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3605 if (dim == GLSL_SAMPLER_DIM_BUF) {
3606 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3607 unsigned num_channels = util_last_bit(mask);
3608 LLVMValueRef rsrc, vindex;
3609
3610 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3611 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3612 ctx->ac.i32_0, "");
3613
3614 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3615 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3616 ctx->ac.i32_0, num_channels,
3617 false, false);
3618 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3619
3620 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3621 res = ac_to_integer(&ctx->ac, res);
3622 } else {
3623 bool is_da = glsl_sampler_type_is_array(type) ||
3624 dim == GLSL_SAMPLER_DIM_CUBE ||
3625 dim == GLSL_SAMPLER_DIM_3D ||
3626 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3627 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3628 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3629 LLVMValueRef glc = ctx->ac.i1false;
3630 LLVMValueRef slc = ctx->ac.i1false;
3631
3632 params[0] = get_image_coords(ctx, instr);
3633 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3634 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3635 params[3] = glc;
3636 params[4] = slc;
3637 params[5] = ctx->ac.i1false;
3638 params[6] = da;
3639
3640 ac_get_image_intr_name("llvm.amdgcn.image.load",
3641 ctx->ac.v4f32, /* vdata */
3642 LLVMTypeOf(params[0]), /* coords */
3643 LLVMTypeOf(params[1]), /* rsrc */
3644 intrinsic_name, sizeof(intrinsic_name));
3645
3646 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3647 params, 7, AC_FUNC_ATTR_READONLY);
3648 }
3649 return ac_to_integer(&ctx->ac, res);
3650 }
3651
3652 static void visit_image_store(struct ac_nir_context *ctx,
3653 nir_intrinsic_instr *instr)
3654 {
3655 LLVMValueRef params[8];
3656 char intrinsic_name[64];
3657 const nir_variable *var = instr->variables[0]->var;
3658 const struct glsl_type *type = glsl_without_array(var->type);
3659 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3660 LLVMValueRef glc = ctx->ac.i1false;
3661 bool force_glc = ctx->ac.chip_class == SI;
3662 if (force_glc)
3663 glc = ctx->ac.i1true;
3664
3665 if (dim == GLSL_SAMPLER_DIM_BUF) {
3666 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3667 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3668 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3669 ctx->ac.i32_0, ""); /* vindex */
3670 params[3] = ctx->ac.i32_0; /* voffset */
3671 params[4] = glc; /* glc */
3672 params[5] = ctx->ac.i1false; /* slc */
3673 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3674 params, 6, 0);
3675 } else {
3676 bool is_da = glsl_sampler_type_is_array(type) ||
3677 dim == GLSL_SAMPLER_DIM_CUBE ||
3678 dim == GLSL_SAMPLER_DIM_3D;
3679 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3680 LLVMValueRef slc = ctx->ac.i1false;
3681
3682 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3683 params[1] = get_image_coords(ctx, instr); /* coords */
3684 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3685 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3686 params[4] = glc;
3687 params[5] = slc;
3688 params[6] = ctx->ac.i1false;
3689 params[7] = da;
3690
3691 ac_get_image_intr_name("llvm.amdgcn.image.store",
3692 LLVMTypeOf(params[0]), /* vdata */
3693 LLVMTypeOf(params[1]), /* coords */
3694 LLVMTypeOf(params[2]), /* rsrc */
3695 intrinsic_name, sizeof(intrinsic_name));
3696
3697 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3698 params, 8, 0);
3699 }
3700
3701 }
3702
3703 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3704 const nir_intrinsic_instr *instr)
3705 {
3706 LLVMValueRef params[7];
3707 int param_count = 0;
3708 const nir_variable *var = instr->variables[0]->var;
3709
3710 const char *atomic_name;
3711 char intrinsic_name[41];
3712 const struct glsl_type *type = glsl_without_array(var->type);
3713 MAYBE_UNUSED int length;
3714
3715 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3716
3717 switch (instr->intrinsic) {
3718 case nir_intrinsic_image_atomic_add:
3719 atomic_name = "add";
3720 break;
3721 case nir_intrinsic_image_atomic_min:
3722 atomic_name = is_unsigned ? "umin" : "smin";
3723 break;
3724 case nir_intrinsic_image_atomic_max:
3725 atomic_name = is_unsigned ? "umax" : "smax";
3726 break;
3727 case nir_intrinsic_image_atomic_and:
3728 atomic_name = "and";
3729 break;
3730 case nir_intrinsic_image_atomic_or:
3731 atomic_name = "or";
3732 break;
3733 case nir_intrinsic_image_atomic_xor:
3734 atomic_name = "xor";
3735 break;
3736 case nir_intrinsic_image_atomic_exchange:
3737 atomic_name = "swap";
3738 break;
3739 case nir_intrinsic_image_atomic_comp_swap:
3740 atomic_name = "cmpswap";
3741 break;
3742 default:
3743 abort();
3744 }
3745
3746 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3747 params[param_count++] = get_src(ctx, instr->src[3]);
3748 params[param_count++] = get_src(ctx, instr->src[2]);
3749
3750 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3751 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3752 NULL, true, true);
3753 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3754 ctx->ac.i32_0, ""); /* vindex */
3755 params[param_count++] = ctx->ac.i32_0; /* voffset */
3756 params[param_count++] = ctx->ac.i1false; /* slc */
3757
3758 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3759 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3760 } else {
3761 char coords_type[8];
3762
3763 bool da = glsl_sampler_type_is_array(type) ||
3764 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3765
3766 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3767 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3768 NULL, true, true);
3769 params[param_count++] = ctx->ac.i1false; /* r128 */
3770 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3771 params[param_count++] = ctx->ac.i1false; /* slc */
3772
3773 build_int_type_name(LLVMTypeOf(coords),
3774 coords_type, sizeof(coords_type));
3775
3776 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3777 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3778 }
3779
3780 assert(length < sizeof(intrinsic_name));
3781 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3782 }
3783
3784 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3785 const nir_intrinsic_instr *instr)
3786 {
3787 const nir_variable *var = instr->variables[0]->var;
3788 const struct glsl_type *type = glsl_without_array(var->type);
3789 bool da = glsl_sampler_type_is_array(type) ||
3790 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3791 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3792
3793 struct ac_image_args args = { 0 };
3794 args.da = da;
3795 args.dmask = 0xf;
3796 args.resource = get_sampler_desc(ctx, instr->variables[0],
3797 AC_DESC_IMAGE, NULL, true, false);
3798 args.opcode = ac_image_get_resinfo;
3799 args.addr = ctx->ac.i32_0;
3800
3801 return ac_build_image_opcode(&ctx->ac, &args);
3802 }
3803
3804 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3805 const nir_intrinsic_instr *instr)
3806 {
3807 LLVMValueRef res;
3808 const nir_variable *var = instr->variables[0]->var;
3809 const struct glsl_type *type = glsl_without_array(var->type);
3810 bool da = glsl_sampler_type_is_array(type) ||
3811 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3812 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3813
3814 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3815 return get_buffer_size(ctx,
3816 get_sampler_desc(ctx, instr->variables[0],
3817 AC_DESC_BUFFER, NULL, true, false), true);
3818
3819 struct ac_image_args args = { 0 };
3820
3821 args.da = da;
3822 args.dmask = 0xf;
3823 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3824 args.opcode = ac_image_get_resinfo;
3825 args.addr = ctx->ac.i32_0;
3826
3827 res = ac_build_image_opcode(&ctx->ac, &args);
3828
3829 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3830
3831 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3832 glsl_sampler_type_is_array(type)) {
3833 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3834 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3835 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3836 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3837 }
3838 if (ctx->ac.chip_class >= GFX9 &&
3839 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3840 glsl_sampler_type_is_array(type)) {
3841 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3842 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3843 ctx->ac.i32_1, "");
3844
3845 }
3846 return res;
3847 }
3848
3849 #define NOOP_WAITCNT 0xf7f
3850 #define LGKM_CNT 0x07f
3851 #define VM_CNT 0xf70
3852
3853 static void emit_membar(struct ac_llvm_context *ac,
3854 const nir_intrinsic_instr *instr)
3855 {
3856 unsigned waitcnt = NOOP_WAITCNT;
3857
3858 switch (instr->intrinsic) {
3859 case nir_intrinsic_memory_barrier:
3860 case nir_intrinsic_group_memory_barrier:
3861 waitcnt &= VM_CNT & LGKM_CNT;
3862 break;
3863 case nir_intrinsic_memory_barrier_atomic_counter:
3864 case nir_intrinsic_memory_barrier_buffer:
3865 case nir_intrinsic_memory_barrier_image:
3866 waitcnt &= VM_CNT;
3867 break;
3868 case nir_intrinsic_memory_barrier_shared:
3869 waitcnt &= LGKM_CNT;
3870 break;
3871 default:
3872 break;
3873 }
3874 if (waitcnt != NOOP_WAITCNT)
3875 ac_build_waitcnt(ac, waitcnt);
3876 }
3877
3878 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3879 {
3880 /* SI only (thanks to a hw bug workaround):
3881 * The real barrier instruction isn’t needed, because an entire patch
3882 * always fits into a single wave.
3883 */
3884 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3885 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3886 return;
3887 }
3888 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3889 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3890 }
3891
3892 static void emit_discard(struct ac_nir_context *ctx,
3893 const nir_intrinsic_instr *instr)
3894 {
3895 LLVMValueRef cond;
3896
3897 if (instr->intrinsic == nir_intrinsic_discard_if) {
3898 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3899 get_src(ctx, instr->src[0]),
3900 ctx->ac.i32_0, "");
3901 } else {
3902 assert(instr->intrinsic == nir_intrinsic_discard);
3903 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3904 }
3905
3906 ac_build_kill_if_false(&ctx->ac, cond);
3907 }
3908
3909 static LLVMValueRef
3910 visit_load_helper_invocation(struct ac_nir_context *ctx)
3911 {
3912 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3913 "llvm.amdgcn.ps.live",
3914 ctx->ac.i1, NULL, 0,
3915 AC_FUNC_ATTR_READNONE);
3916 result = LLVMBuildNot(ctx->ac.builder, result, "");
3917 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3918 }
3919
3920 static LLVMValueRef
3921 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3922 {
3923 LLVMValueRef result;
3924 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3925 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3926 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3927
3928 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3929 }
3930
3931 static LLVMValueRef
3932 visit_load_shared(struct ac_nir_context *ctx,
3933 const nir_intrinsic_instr *instr)
3934 {
3935 LLVMValueRef values[4], derived_ptr, index, ret;
3936
3937 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3938
3939 for (int chan = 0; chan < instr->num_components; chan++) {
3940 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3941 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3942 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3943 }
3944
3945 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3946 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3947 }
3948
3949 static void
3950 visit_store_shared(struct ac_nir_context *ctx,
3951 const nir_intrinsic_instr *instr)
3952 {
3953 LLVMValueRef derived_ptr, data,index;
3954 LLVMBuilderRef builder = ctx->ac.builder;
3955
3956 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3957 LLVMValueRef src = get_src(ctx, instr->src[0]);
3958
3959 int writemask = nir_intrinsic_write_mask(instr);
3960 for (int chan = 0; chan < 4; chan++) {
3961 if (!(writemask & (1 << chan))) {
3962 continue;
3963 }
3964 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3965 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3966 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3967 LLVMBuildStore(builder, data, derived_ptr);
3968 }
3969 }
3970
3971 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3972 const nir_intrinsic_instr *instr,
3973 LLVMValueRef ptr)
3974 {
3975 LLVMValueRef result;
3976 LLVMValueRef src = get_src(ctx, instr->src[0]);
3977
3978 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3979 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3980 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3981 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3982 ptr, src, src1,
3983 LLVMAtomicOrderingSequentiallyConsistent,
3984 LLVMAtomicOrderingSequentiallyConsistent,
3985 false);
3986 } else {
3987 LLVMAtomicRMWBinOp op;
3988 switch (instr->intrinsic) {
3989 case nir_intrinsic_var_atomic_add:
3990 case nir_intrinsic_shared_atomic_add:
3991 op = LLVMAtomicRMWBinOpAdd;
3992 break;
3993 case nir_intrinsic_var_atomic_umin:
3994 case nir_intrinsic_shared_atomic_umin:
3995 op = LLVMAtomicRMWBinOpUMin;
3996 break;
3997 case nir_intrinsic_var_atomic_umax:
3998 case nir_intrinsic_shared_atomic_umax:
3999 op = LLVMAtomicRMWBinOpUMax;
4000 break;
4001 case nir_intrinsic_var_atomic_imin:
4002 case nir_intrinsic_shared_atomic_imin:
4003 op = LLVMAtomicRMWBinOpMin;
4004 break;
4005 case nir_intrinsic_var_atomic_imax:
4006 case nir_intrinsic_shared_atomic_imax:
4007 op = LLVMAtomicRMWBinOpMax;
4008 break;
4009 case nir_intrinsic_var_atomic_and:
4010 case nir_intrinsic_shared_atomic_and:
4011 op = LLVMAtomicRMWBinOpAnd;
4012 break;
4013 case nir_intrinsic_var_atomic_or:
4014 case nir_intrinsic_shared_atomic_or:
4015 op = LLVMAtomicRMWBinOpOr;
4016 break;
4017 case nir_intrinsic_var_atomic_xor:
4018 case nir_intrinsic_shared_atomic_xor:
4019 op = LLVMAtomicRMWBinOpXor;
4020 break;
4021 case nir_intrinsic_var_atomic_exchange:
4022 case nir_intrinsic_shared_atomic_exchange:
4023 op = LLVMAtomicRMWBinOpXchg;
4024 break;
4025 default:
4026 return NULL;
4027 }
4028
4029 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4030 LLVMAtomicOrderingSequentiallyConsistent,
4031 false);
4032 }
4033 return result;
4034 }
4035
4036 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4037 enum glsl_interp_mode interp, unsigned location)
4038 {
4039 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4040
4041 switch (interp) {
4042 case INTERP_MODE_FLAT:
4043 default:
4044 return NULL;
4045 case INTERP_MODE_SMOOTH:
4046 case INTERP_MODE_NONE:
4047 if (location == INTERP_CENTER)
4048 return ctx->persp_center;
4049 else if (location == INTERP_CENTROID)
4050 return ctx->persp_centroid;
4051 else if (location == INTERP_SAMPLE)
4052 return ctx->persp_sample;
4053 break;
4054 case INTERP_MODE_NOPERSPECTIVE:
4055 if (location == INTERP_CENTER)
4056 return ctx->linear_center;
4057 else if (location == INTERP_CENTROID)
4058 return ctx->linear_centroid;
4059 else if (location == INTERP_SAMPLE)
4060 return ctx->linear_sample;
4061 break;
4062 }
4063 return NULL;
4064 }
4065
4066 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4067 LLVMValueRef sample_id)
4068 {
4069 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4070
4071 LLVMValueRef result;
4072 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4073
4074 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4075 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4076
4077 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4078 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4079
4080 return result;
4081 }
4082
4083 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4084 {
4085 LLVMValueRef values[2];
4086
4087 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4088 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4089 return ac_build_gather_values(&ctx->ac, values, 2);
4090 }
4091
4092 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4093 {
4094 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4095 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4096 ctx->options->key.fs.log2_num_samples :
4097 ctx->options->key.fs.log2_ps_iter_samples;
4098
4099 /* The bit pattern matches that used by fixed function fragment
4100 * processing. */
4101 static const uint16_t ps_iter_masks[] = {
4102 0xffff, /* not used */
4103 0x5555,
4104 0x1111,
4105 0x0101,
4106 0x0001,
4107 };
4108 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4109
4110 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4111
4112 LLVMValueRef result, sample_id;
4113 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4114 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4115 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4116 return result;
4117 }
4118
4119 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4120 const nir_intrinsic_instr *instr)
4121 {
4122 LLVMValueRef result[4];
4123 LLVMValueRef interp_param, attr_number;
4124 unsigned location;
4125 unsigned chan;
4126 LLVMValueRef src_c0 = NULL;
4127 LLVMValueRef src_c1 = NULL;
4128 LLVMValueRef src0 = NULL;
4129 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4130 switch (instr->intrinsic) {
4131 case nir_intrinsic_interp_var_at_centroid:
4132 location = INTERP_CENTROID;
4133 break;
4134 case nir_intrinsic_interp_var_at_sample:
4135 case nir_intrinsic_interp_var_at_offset:
4136 location = INTERP_CENTER;
4137 src0 = get_src(ctx, instr->src[0]);
4138 break;
4139 default:
4140 break;
4141 }
4142
4143 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4144 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4145 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4146 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4147 LLVMValueRef sample_position;
4148 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4149
4150 /* fetch sample ID */
4151 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4152
4153 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4154 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4155 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4156 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4157 }
4158 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4159 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4160
4161 if (location == INTERP_CENTER) {
4162 LLVMValueRef ij_out[2];
4163 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4164
4165 /*
4166 * take the I then J parameters, and the DDX/Y for it, and
4167 * calculate the IJ inputs for the interpolator.
4168 * temp1 = ddx * offset/sample.x + I;
4169 * interp_param.I = ddy * offset/sample.y + temp1;
4170 * temp1 = ddx * offset/sample.x + J;
4171 * interp_param.J = ddy * offset/sample.y + temp1;
4172 */
4173 for (unsigned i = 0; i < 2; i++) {
4174 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4175 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4176 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4177 ddxy_out, ix_ll, "");
4178 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4179 ddxy_out, iy_ll, "");
4180 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4181 interp_param, ix_ll, "");
4182 LLVMValueRef temp1, temp2;
4183
4184 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4185 ctx->ac.f32, "");
4186
4187 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4188 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4189
4190 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4191 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4192
4193 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4194 temp2, ctx->ac.i32, "");
4195 }
4196 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4197
4198 }
4199
4200 for (chan = 0; chan < 4; chan++) {
4201 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4202
4203 if (interp_param) {
4204 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4205 interp_param, ctx->ac.v2f32, "");
4206 LLVMValueRef i = LLVMBuildExtractElement(
4207 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4208 LLVMValueRef j = LLVMBuildExtractElement(
4209 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4210
4211 result[chan] = ac_build_fs_interp(&ctx->ac,
4212 llvm_chan, attr_number,
4213 ctx->abi->prim_mask, i, j);
4214 } else {
4215 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4216 LLVMConstInt(ctx->ac.i32, 2, false),
4217 llvm_chan, attr_number,
4218 ctx->abi->prim_mask);
4219 }
4220 }
4221 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4222 instr->variables[0]->var->data.location_frac);
4223 }
4224
4225 static void
4226 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4227 {
4228 LLVMValueRef gs_next_vertex;
4229 LLVMValueRef can_emit;
4230 int idx;
4231 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4232
4233 assert(stream == 0);
4234
4235 /* Write vertex attribute values to GSVS ring */
4236 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4237 ctx->gs_next_vertex,
4238 "");
4239
4240 /* If this thread has already emitted the declared maximum number of
4241 * vertices, kill it: excessive vertex emissions are not supposed to
4242 * have any effect, and GS threads have no externally observable
4243 * effects other than emitting vertices.
4244 */
4245 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4246 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4247 ac_build_kill_if_false(&ctx->ac, can_emit);
4248
4249 /* loop num outputs */
4250 idx = 0;
4251 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4252 LLVMValueRef *out_ptr = &addrs[i * 4];
4253 int length = 4;
4254 int slot = idx;
4255 int slot_inc = 1;
4256
4257 if (!(ctx->output_mask & (1ull << i)))
4258 continue;
4259
4260 if (i == VARYING_SLOT_CLIP_DIST0) {
4261 /* pack clip and cull into a single set of slots */
4262 length = ctx->num_output_clips + ctx->num_output_culls;
4263 if (length > 4)
4264 slot_inc = 2;
4265 }
4266 for (unsigned j = 0; j < length; j++) {
4267 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4268 out_ptr[j], "");
4269 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4270 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4271 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4272
4273 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4274
4275 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4276 out_val, 1,
4277 voffset, ctx->gs2vs_offset, 0,
4278 1, 1, true, true);
4279 }
4280 idx += slot_inc;
4281 }
4282
4283 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4284 ctx->ac.i32_1, "");
4285 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4286
4287 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4288 }
4289
4290 static void
4291 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4292 {
4293 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4294 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4295 }
4296
4297 static LLVMValueRef
4298 load_tess_coord(struct ac_shader_abi *abi)
4299 {
4300 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4301
4302 LLVMValueRef coord[4] = {
4303 ctx->tes_u,
4304 ctx->tes_v,
4305 ctx->ac.f32_0,
4306 ctx->ac.f32_0,
4307 };
4308
4309 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4310 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4311 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4312
4313 return ac_build_gather_values(&ctx->ac, coord, 3);
4314 }
4315
4316 static LLVMValueRef
4317 load_patch_vertices_in(struct ac_shader_abi *abi)
4318 {
4319 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4320 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4321 }
4322
4323 static void visit_intrinsic(struct ac_nir_context *ctx,
4324 nir_intrinsic_instr *instr)
4325 {
4326 LLVMValueRef result = NULL;
4327
4328 switch (instr->intrinsic) {
4329 case nir_intrinsic_ballot:
4330 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4331 break;
4332 case nir_intrinsic_read_invocation:
4333 case nir_intrinsic_read_first_invocation: {
4334 LLVMValueRef args[2];
4335
4336 /* Value */
4337 args[0] = get_src(ctx, instr->src[0]);
4338
4339 unsigned num_args;
4340 const char *intr_name;
4341 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4342 num_args = 2;
4343 intr_name = "llvm.amdgcn.readlane";
4344
4345 /* Invocation */
4346 args[1] = get_src(ctx, instr->src[1]);
4347 } else {
4348 num_args = 1;
4349 intr_name = "llvm.amdgcn.readfirstlane";
4350 }
4351
4352 /* We currently have no other way to prevent LLVM from lifting the icmp
4353 * calls to a dominating basic block.
4354 */
4355 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4356
4357 result = ac_build_intrinsic(&ctx->ac, intr_name,
4358 ctx->ac.i32, args, num_args,
4359 AC_FUNC_ATTR_READNONE |
4360 AC_FUNC_ATTR_CONVERGENT);
4361 break;
4362 }
4363 case nir_intrinsic_load_subgroup_invocation:
4364 result = ac_get_thread_id(&ctx->ac);
4365 break;
4366 case nir_intrinsic_load_work_group_id: {
4367 LLVMValueRef values[3];
4368
4369 for (int i = 0; i < 3; i++) {
4370 values[i] = ctx->abi->workgroup_ids[i] ?
4371 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4372 }
4373
4374 result = ac_build_gather_values(&ctx->ac, values, 3);
4375 break;
4376 }
4377 case nir_intrinsic_load_base_vertex: {
4378 result = ctx->abi->base_vertex;
4379 break;
4380 }
4381 case nir_intrinsic_load_local_group_size:
4382 result = ctx->abi->load_local_group_size(ctx->abi);
4383 break;
4384 case nir_intrinsic_load_vertex_id_zero_base: {
4385 result = ctx->abi->vertex_id;
4386 break;
4387 }
4388 case nir_intrinsic_load_local_invocation_id: {
4389 result = ctx->abi->local_invocation_ids;
4390 break;
4391 }
4392 case nir_intrinsic_load_base_instance:
4393 result = ctx->abi->start_instance;
4394 break;
4395 case nir_intrinsic_load_draw_id:
4396 result = ctx->abi->draw_id;
4397 break;
4398 case nir_intrinsic_load_view_index:
4399 result = ctx->abi->view_index;
4400 break;
4401 case nir_intrinsic_load_invocation_id:
4402 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4403 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4404 else
4405 result = ctx->abi->gs_invocation_id;
4406 break;
4407 case nir_intrinsic_load_primitive_id:
4408 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4409 result = ctx->abi->gs_prim_id;
4410 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4411 result = ctx->abi->tcs_patch_id;
4412 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4413 result = ctx->abi->tes_patch_id;
4414 } else
4415 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4416 break;
4417 case nir_intrinsic_load_sample_id:
4418 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4419 break;
4420 case nir_intrinsic_load_sample_pos:
4421 result = load_sample_pos(ctx);
4422 break;
4423 case nir_intrinsic_load_sample_mask_in:
4424 result = ctx->abi->load_sample_mask_in(ctx->abi);
4425 break;
4426 case nir_intrinsic_load_frag_coord: {
4427 LLVMValueRef values[4] = {
4428 ctx->abi->frag_pos[0],
4429 ctx->abi->frag_pos[1],
4430 ctx->abi->frag_pos[2],
4431 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4432 };
4433 result = ac_build_gather_values(&ctx->ac, values, 4);
4434 break;
4435 }
4436 case nir_intrinsic_load_front_face:
4437 result = ctx->abi->front_face;
4438 break;
4439 case nir_intrinsic_load_helper_invocation:
4440 result = visit_load_helper_invocation(ctx);
4441 break;
4442 case nir_intrinsic_load_instance_id:
4443 result = ctx->abi->instance_id;
4444 break;
4445 case nir_intrinsic_load_num_work_groups:
4446 result = ctx->abi->num_work_groups;
4447 break;
4448 case nir_intrinsic_load_local_invocation_index:
4449 result = visit_load_local_invocation_index(ctx);
4450 break;
4451 case nir_intrinsic_load_push_constant:
4452 result = visit_load_push_constant(ctx, instr);
4453 break;
4454 case nir_intrinsic_vulkan_resource_index: {
4455 LLVMValueRef index = get_src(ctx, instr->src[0]);
4456 unsigned desc_set = nir_intrinsic_desc_set(instr);
4457 unsigned binding = nir_intrinsic_binding(instr);
4458
4459 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4460 binding);
4461 break;
4462 }
4463 case nir_intrinsic_vulkan_resource_reindex:
4464 result = visit_vulkan_resource_reindex(ctx, instr);
4465 break;
4466 case nir_intrinsic_store_ssbo:
4467 visit_store_ssbo(ctx, instr);
4468 break;
4469 case nir_intrinsic_load_ssbo:
4470 result = visit_load_buffer(ctx, instr);
4471 break;
4472 case nir_intrinsic_ssbo_atomic_add:
4473 case nir_intrinsic_ssbo_atomic_imin:
4474 case nir_intrinsic_ssbo_atomic_umin:
4475 case nir_intrinsic_ssbo_atomic_imax:
4476 case nir_intrinsic_ssbo_atomic_umax:
4477 case nir_intrinsic_ssbo_atomic_and:
4478 case nir_intrinsic_ssbo_atomic_or:
4479 case nir_intrinsic_ssbo_atomic_xor:
4480 case nir_intrinsic_ssbo_atomic_exchange:
4481 case nir_intrinsic_ssbo_atomic_comp_swap:
4482 result = visit_atomic_ssbo(ctx, instr);
4483 break;
4484 case nir_intrinsic_load_ubo:
4485 result = visit_load_ubo_buffer(ctx, instr);
4486 break;
4487 case nir_intrinsic_get_buffer_size:
4488 result = visit_get_buffer_size(ctx, instr);
4489 break;
4490 case nir_intrinsic_load_var:
4491 result = visit_load_var(ctx, instr);
4492 break;
4493 case nir_intrinsic_store_var:
4494 visit_store_var(ctx, instr);
4495 break;
4496 case nir_intrinsic_load_shared:
4497 result = visit_load_shared(ctx, instr);
4498 break;
4499 case nir_intrinsic_store_shared:
4500 visit_store_shared(ctx, instr);
4501 break;
4502 case nir_intrinsic_image_samples:
4503 result = visit_image_samples(ctx, instr);
4504 break;
4505 case nir_intrinsic_image_load:
4506 result = visit_image_load(ctx, instr);
4507 break;
4508 case nir_intrinsic_image_store:
4509 visit_image_store(ctx, instr);
4510 break;
4511 case nir_intrinsic_image_atomic_add:
4512 case nir_intrinsic_image_atomic_min:
4513 case nir_intrinsic_image_atomic_max:
4514 case nir_intrinsic_image_atomic_and:
4515 case nir_intrinsic_image_atomic_or:
4516 case nir_intrinsic_image_atomic_xor:
4517 case nir_intrinsic_image_atomic_exchange:
4518 case nir_intrinsic_image_atomic_comp_swap:
4519 result = visit_image_atomic(ctx, instr);
4520 break;
4521 case nir_intrinsic_image_size:
4522 result = visit_image_size(ctx, instr);
4523 break;
4524 case nir_intrinsic_shader_clock:
4525 result = ac_build_shader_clock(&ctx->ac);
4526 break;
4527 case nir_intrinsic_discard:
4528 case nir_intrinsic_discard_if:
4529 emit_discard(ctx, instr);
4530 break;
4531 case nir_intrinsic_memory_barrier:
4532 case nir_intrinsic_group_memory_barrier:
4533 case nir_intrinsic_memory_barrier_atomic_counter:
4534 case nir_intrinsic_memory_barrier_buffer:
4535 case nir_intrinsic_memory_barrier_image:
4536 case nir_intrinsic_memory_barrier_shared:
4537 emit_membar(&ctx->ac, instr);
4538 break;
4539 case nir_intrinsic_barrier:
4540 emit_barrier(&ctx->ac, ctx->stage);
4541 break;
4542 case nir_intrinsic_shared_atomic_add:
4543 case nir_intrinsic_shared_atomic_imin:
4544 case nir_intrinsic_shared_atomic_umin:
4545 case nir_intrinsic_shared_atomic_imax:
4546 case nir_intrinsic_shared_atomic_umax:
4547 case nir_intrinsic_shared_atomic_and:
4548 case nir_intrinsic_shared_atomic_or:
4549 case nir_intrinsic_shared_atomic_xor:
4550 case nir_intrinsic_shared_atomic_exchange:
4551 case nir_intrinsic_shared_atomic_comp_swap: {
4552 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
4553 result = visit_var_atomic(ctx, instr, ptr);
4554 break;
4555 }
4556 case nir_intrinsic_var_atomic_add:
4557 case nir_intrinsic_var_atomic_imin:
4558 case nir_intrinsic_var_atomic_umin:
4559 case nir_intrinsic_var_atomic_imax:
4560 case nir_intrinsic_var_atomic_umax:
4561 case nir_intrinsic_var_atomic_and:
4562 case nir_intrinsic_var_atomic_or:
4563 case nir_intrinsic_var_atomic_xor:
4564 case nir_intrinsic_var_atomic_exchange:
4565 case nir_intrinsic_var_atomic_comp_swap: {
4566 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4567 result = visit_var_atomic(ctx, instr, ptr);
4568 break;
4569 }
4570 case nir_intrinsic_interp_var_at_centroid:
4571 case nir_intrinsic_interp_var_at_sample:
4572 case nir_intrinsic_interp_var_at_offset:
4573 result = visit_interp(ctx, instr);
4574 break;
4575 case nir_intrinsic_emit_vertex:
4576 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4577 break;
4578 case nir_intrinsic_end_primitive:
4579 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4580 break;
4581 case nir_intrinsic_load_tess_coord:
4582 result = ctx->abi->load_tess_coord(ctx->abi);
4583 break;
4584 case nir_intrinsic_load_tess_level_outer:
4585 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4586 break;
4587 case nir_intrinsic_load_tess_level_inner:
4588 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4589 break;
4590 case nir_intrinsic_load_patch_vertices_in:
4591 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4592 break;
4593 case nir_intrinsic_vote_all: {
4594 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4595 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4596 break;
4597 }
4598 case nir_intrinsic_vote_any: {
4599 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4600 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4601 break;
4602 }
4603 case nir_intrinsic_vote_eq: {
4604 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4605 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4606 break;
4607 }
4608 default:
4609 fprintf(stderr, "Unknown intrinsic: ");
4610 nir_print_instr(&instr->instr, stderr);
4611 fprintf(stderr, "\n");
4612 break;
4613 }
4614 if (result) {
4615 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4616 }
4617 }
4618
4619 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4620 LLVMValueRef buffer_ptr, bool write)
4621 {
4622 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4623 LLVMValueRef result;
4624
4625 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4626
4627 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4628 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4629
4630 return result;
4631 }
4632
4633 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4634 {
4635 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4636 LLVMValueRef result;
4637
4638 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4639
4640 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4641 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4642
4643 return result;
4644 }
4645
4646 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4647 unsigned descriptor_set,
4648 unsigned base_index,
4649 unsigned constant_index,
4650 LLVMValueRef index,
4651 enum ac_descriptor_type desc_type,
4652 bool image, bool write)
4653 {
4654 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4655 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4656 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4657 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4658 unsigned offset = binding->offset;
4659 unsigned stride = binding->size;
4660 unsigned type_size;
4661 LLVMBuilderRef builder = ctx->ac.builder;
4662 LLVMTypeRef type;
4663
4664 assert(base_index < layout->binding_count);
4665
4666 switch (desc_type) {
4667 case AC_DESC_IMAGE:
4668 type = ctx->ac.v8i32;
4669 type_size = 32;
4670 break;
4671 case AC_DESC_FMASK:
4672 type = ctx->ac.v8i32;
4673 offset += 32;
4674 type_size = 32;
4675 break;
4676 case AC_DESC_SAMPLER:
4677 type = ctx->ac.v4i32;
4678 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4679 offset += 64;
4680
4681 type_size = 16;
4682 break;
4683 case AC_DESC_BUFFER:
4684 type = ctx->ac.v4i32;
4685 type_size = 16;
4686 break;
4687 default:
4688 unreachable("invalid desc_type\n");
4689 }
4690
4691 offset += constant_index * stride;
4692
4693 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4694 (!index || binding->immutable_samplers_equal)) {
4695 if (binding->immutable_samplers_equal)
4696 constant_index = 0;
4697
4698 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4699
4700 LLVMValueRef constants[] = {
4701 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4702 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4703 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4704 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4705 };
4706 return ac_build_gather_values(&ctx->ac, constants, 4);
4707 }
4708
4709 assert(stride % type_size == 0);
4710
4711 if (!index)
4712 index = ctx->ac.i32_0;
4713
4714 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4715
4716 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4717 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4718
4719 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4720 }
4721
4722 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4723 const nir_deref_var *deref,
4724 enum ac_descriptor_type desc_type,
4725 const nir_tex_instr *tex_instr,
4726 bool image, bool write)
4727 {
4728 LLVMValueRef index = NULL;
4729 unsigned constant_index = 0;
4730 unsigned descriptor_set;
4731 unsigned base_index;
4732
4733 if (!deref) {
4734 assert(tex_instr && !image);
4735 descriptor_set = 0;
4736 base_index = tex_instr->sampler_index;
4737 } else {
4738 const nir_deref *tail = &deref->deref;
4739 while (tail->child) {
4740 const nir_deref_array *child = nir_deref_as_array(tail->child);
4741 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4742
4743 if (!array_size)
4744 array_size = 1;
4745
4746 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4747
4748 if (child->deref_array_type == nir_deref_array_type_indirect) {
4749 LLVMValueRef indirect = get_src(ctx, child->indirect);
4750
4751 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4752 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4753
4754 if (!index)
4755 index = indirect;
4756 else
4757 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4758 }
4759
4760 constant_index += child->base_offset * array_size;
4761
4762 tail = &child->deref;
4763 }
4764 descriptor_set = deref->var->data.descriptor_set;
4765 base_index = deref->var->data.binding;
4766 }
4767
4768 return ctx->abi->load_sampler_desc(ctx->abi,
4769 descriptor_set,
4770 base_index,
4771 constant_index, index,
4772 desc_type, image, write);
4773 }
4774
4775 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4776 struct ac_image_args *args,
4777 const nir_tex_instr *instr,
4778 nir_texop op,
4779 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4780 LLVMValueRef *param, unsigned count,
4781 unsigned dmask)
4782 {
4783 unsigned is_rect = 0;
4784 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4785
4786 if (op == nir_texop_lod)
4787 da = false;
4788 /* Pad to power of two vector */
4789 while (count < util_next_power_of_two(count))
4790 param[count++] = LLVMGetUndef(ctx->i32);
4791
4792 if (count > 1)
4793 args->addr = ac_build_gather_values(ctx, param, count);
4794 else
4795 args->addr = param[0];
4796
4797 args->resource = res_ptr;
4798 args->sampler = samp_ptr;
4799
4800 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4801 args->addr = param[0];
4802 return;
4803 }
4804
4805 args->dmask = dmask;
4806 args->unorm = is_rect;
4807 args->da = da;
4808 }
4809
4810 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4811 *
4812 * SI-CI:
4813 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4814 * filtering manually. The driver sets img7 to a mask clearing
4815 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4816 * s_and_b32 samp0, samp0, img7
4817 *
4818 * VI:
4819 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4820 */
4821 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4822 LLVMValueRef res, LLVMValueRef samp)
4823 {
4824 LLVMBuilderRef builder = ctx->ac.builder;
4825 LLVMValueRef img7, samp0;
4826
4827 if (ctx->ac.chip_class >= VI)
4828 return samp;
4829
4830 img7 = LLVMBuildExtractElement(builder, res,
4831 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4832 samp0 = LLVMBuildExtractElement(builder, samp,
4833 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4834 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4835 return LLVMBuildInsertElement(builder, samp, samp0,
4836 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4837 }
4838
4839 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4840 nir_tex_instr *instr,
4841 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4842 LLVMValueRef *fmask_ptr)
4843 {
4844 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4845 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4846 else
4847 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4848 if (samp_ptr) {
4849 if (instr->sampler)
4850 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4851 else
4852 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4853 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4854 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4855 }
4856 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4857 instr->op == nir_texop_samples_identical))
4858 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4859 }
4860
4861 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4862 LLVMValueRef coord)
4863 {
4864 coord = ac_to_float(ctx, coord);
4865 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4866 coord = ac_to_integer(ctx, coord);
4867 return coord;
4868 }
4869
4870 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4871 {
4872 LLVMValueRef result = NULL;
4873 struct ac_image_args args = { 0 };
4874 unsigned dmask = 0xf;
4875 LLVMValueRef address[16];
4876 LLVMValueRef coords[5];
4877 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4878 LLVMValueRef bias = NULL, offsets = NULL;
4879 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4880 LLVMValueRef ddx = NULL, ddy = NULL;
4881 LLVMValueRef derivs[6];
4882 unsigned chan, count = 0;
4883 unsigned const_src = 0, num_deriv_comp = 0;
4884 bool lod_is_zero = false;
4885
4886 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4887
4888 for (unsigned i = 0; i < instr->num_srcs; i++) {
4889 switch (instr->src[i].src_type) {
4890 case nir_tex_src_coord:
4891 coord = get_src(ctx, instr->src[i].src);
4892 break;
4893 case nir_tex_src_projector:
4894 break;
4895 case nir_tex_src_comparator:
4896 comparator = get_src(ctx, instr->src[i].src);
4897 break;
4898 case nir_tex_src_offset:
4899 offsets = get_src(ctx, instr->src[i].src);
4900 const_src = i;
4901 break;
4902 case nir_tex_src_bias:
4903 bias = get_src(ctx, instr->src[i].src);
4904 break;
4905 case nir_tex_src_lod: {
4906 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4907
4908 if (val && val->i32[0] == 0)
4909 lod_is_zero = true;
4910 lod = get_src(ctx, instr->src[i].src);
4911 break;
4912 }
4913 case nir_tex_src_ms_index:
4914 sample_index = get_src(ctx, instr->src[i].src);
4915 break;
4916 case nir_tex_src_ms_mcs:
4917 break;
4918 case nir_tex_src_ddx:
4919 ddx = get_src(ctx, instr->src[i].src);
4920 num_deriv_comp = instr->src[i].src.ssa->num_components;
4921 break;
4922 case nir_tex_src_ddy:
4923 ddy = get_src(ctx, instr->src[i].src);
4924 break;
4925 case nir_tex_src_texture_offset:
4926 case nir_tex_src_sampler_offset:
4927 case nir_tex_src_plane:
4928 default:
4929 break;
4930 }
4931 }
4932
4933 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4934 result = get_buffer_size(ctx, res_ptr, true);
4935 goto write_result;
4936 }
4937
4938 if (instr->op == nir_texop_texture_samples) {
4939 LLVMValueRef res, samples, is_msaa;
4940 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4941 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4942 LLVMConstInt(ctx->ac.i32, 3, false), "");
4943 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4944 LLVMConstInt(ctx->ac.i32, 28, false), "");
4945 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4946 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4947 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4948 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4949
4950 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4951 LLVMConstInt(ctx->ac.i32, 16, false), "");
4952 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4953 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4954 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4955 samples, "");
4956 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4957 ctx->ac.i32_1, "");
4958 result = samples;
4959 goto write_result;
4960 }
4961
4962 if (coord)
4963 for (chan = 0; chan < instr->coord_components; chan++)
4964 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4965
4966 if (offsets && instr->op != nir_texop_txf) {
4967 LLVMValueRef offset[3], pack;
4968 for (chan = 0; chan < 3; ++chan)
4969 offset[chan] = ctx->ac.i32_0;
4970
4971 args.offset = true;
4972 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4973 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4974 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4975 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4976 if (chan)
4977 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4978 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4979 }
4980 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4981 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4982 address[count++] = pack;
4983
4984 }
4985 /* pack LOD bias value */
4986 if (instr->op == nir_texop_txb && bias) {
4987 address[count++] = bias;
4988 }
4989
4990 /* Pack depth comparison value */
4991 if (instr->is_shadow && comparator) {
4992 LLVMValueRef z = ac_to_float(&ctx->ac,
4993 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4994
4995 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4996 * so the depth comparison value isn't clamped for Z16 and
4997 * Z24 anymore. Do it manually here.
4998 *
4999 * It's unnecessary if the original texture format was
5000 * Z32_FLOAT, but we don't know that here.
5001 */
5002 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5003 z = ac_build_clamp(&ctx->ac, z);
5004
5005 address[count++] = z;
5006 }
5007
5008 /* pack derivatives */
5009 if (ddx || ddy) {
5010 int num_src_deriv_channels, num_dest_deriv_channels;
5011 switch (instr->sampler_dim) {
5012 case GLSL_SAMPLER_DIM_3D:
5013 case GLSL_SAMPLER_DIM_CUBE:
5014 num_deriv_comp = 3;
5015 num_src_deriv_channels = 3;
5016 num_dest_deriv_channels = 3;
5017 break;
5018 case GLSL_SAMPLER_DIM_2D:
5019 default:
5020 num_src_deriv_channels = 2;
5021 num_dest_deriv_channels = 2;
5022 num_deriv_comp = 2;
5023 break;
5024 case GLSL_SAMPLER_DIM_1D:
5025 num_src_deriv_channels = 1;
5026 if (ctx->ac.chip_class >= GFX9) {
5027 num_dest_deriv_channels = 2;
5028 num_deriv_comp = 2;
5029 } else {
5030 num_dest_deriv_channels = 1;
5031 num_deriv_comp = 1;
5032 }
5033 break;
5034 }
5035
5036 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5037 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5038 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5039 }
5040 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5041 derivs[i] = ctx->ac.f32_0;
5042 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5043 }
5044 }
5045
5046 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5047 for (chan = 0; chan < instr->coord_components; chan++)
5048 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5049 if (instr->coord_components == 3)
5050 coords[3] = LLVMGetUndef(ctx->ac.f32);
5051 ac_prepare_cube_coords(&ctx->ac,
5052 instr->op == nir_texop_txd, instr->is_array,
5053 instr->op == nir_texop_lod, coords, derivs);
5054 if (num_deriv_comp)
5055 num_deriv_comp--;
5056 }
5057
5058 if (ddx || ddy) {
5059 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5060 address[count++] = derivs[i];
5061 }
5062
5063 /* Pack texture coordinates */
5064 if (coord) {
5065 address[count++] = coords[0];
5066 if (instr->coord_components > 1) {
5067 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5068 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5069 }
5070 address[count++] = coords[1];
5071 }
5072 if (instr->coord_components > 2) {
5073 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5074 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
5075 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
5076 instr->op != nir_texop_txf) {
5077 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5078 }
5079 address[count++] = coords[2];
5080 }
5081
5082 if (ctx->ac.chip_class >= GFX9) {
5083 LLVMValueRef filler;
5084 if (instr->op == nir_texop_txf)
5085 filler = ctx->ac.i32_0;
5086 else
5087 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5088
5089 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5090 /* No nir_texop_lod, because it does not take a slice
5091 * even with array textures. */
5092 if (instr->is_array && instr->op != nir_texop_lod ) {
5093 address[count] = address[count - 1];
5094 address[count - 1] = filler;
5095 count++;
5096 } else
5097 address[count++] = filler;
5098 }
5099 }
5100 }
5101
5102 /* Pack LOD */
5103 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5104 instr->op == nir_texop_txf)) {
5105 address[count++] = lod;
5106 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5107 address[count++] = sample_index;
5108 } else if(instr->op == nir_texop_txs) {
5109 count = 0;
5110 if (lod)
5111 address[count++] = lod;
5112 else
5113 address[count++] = ctx->ac.i32_0;
5114 }
5115
5116 for (chan = 0; chan < count; chan++) {
5117 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5118 address[chan], ctx->ac.i32, "");
5119 }
5120
5121 if (instr->op == nir_texop_samples_identical) {
5122 LLVMValueRef txf_address[4];
5123 struct ac_image_args txf_args = { 0 };
5124 unsigned txf_count = count;
5125 memcpy(txf_address, address, sizeof(txf_address));
5126
5127 if (!instr->is_array)
5128 txf_address[2] = ctx->ac.i32_0;
5129 txf_address[3] = ctx->ac.i32_0;
5130
5131 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5132 fmask_ptr, NULL,
5133 txf_address, txf_count, 0xf);
5134
5135 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5136
5137 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5138 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5139 goto write_result;
5140 }
5141
5142 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5143 instr->op != nir_texop_txs) {
5144 unsigned sample_chan = instr->is_array ? 3 : 2;
5145 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5146 address[0],
5147 address[1],
5148 instr->is_array ? address[2] : NULL,
5149 address[sample_chan],
5150 fmask_ptr);
5151 }
5152
5153 if (offsets && instr->op == nir_texop_txf) {
5154 nir_const_value *const_offset =
5155 nir_src_as_const_value(instr->src[const_src].src);
5156 int num_offsets = instr->src[const_src].src.ssa->num_components;
5157 assert(const_offset);
5158 num_offsets = MIN2(num_offsets, instr->coord_components);
5159 if (num_offsets > 2)
5160 address[2] = LLVMBuildAdd(ctx->ac.builder,
5161 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5162 if (num_offsets > 1)
5163 address[1] = LLVMBuildAdd(ctx->ac.builder,
5164 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5165 address[0] = LLVMBuildAdd(ctx->ac.builder,
5166 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5167
5168 }
5169
5170 /* TODO TG4 support */
5171 if (instr->op == nir_texop_tg4) {
5172 if (instr->is_shadow)
5173 dmask = 1;
5174 else
5175 dmask = 1 << instr->component;
5176 }
5177 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5178 res_ptr, samp_ptr, address, count, dmask);
5179
5180 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5181
5182 if (instr->op == nir_texop_query_levels)
5183 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5184 else if (instr->is_shadow && instr->is_new_style_shadow &&
5185 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5186 instr->op != nir_texop_tg4)
5187 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5188 else if (instr->op == nir_texop_txs &&
5189 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5190 instr->is_array) {
5191 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5192 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5193 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5194 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5195 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5196 } else if (ctx->ac.chip_class >= GFX9 &&
5197 instr->op == nir_texop_txs &&
5198 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5199 instr->is_array) {
5200 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5201 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5202 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5203 ctx->ac.i32_1, "");
5204 } else if (instr->dest.ssa.num_components != 4)
5205 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5206
5207 write_result:
5208 if (result) {
5209 assert(instr->dest.is_ssa);
5210 result = ac_to_integer(&ctx->ac, result);
5211 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5212 }
5213 }
5214
5215
5216 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5217 {
5218 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5219 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5220
5221 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5222 _mesa_hash_table_insert(ctx->phis, instr, result);
5223 }
5224
5225 static void visit_post_phi(struct ac_nir_context *ctx,
5226 nir_phi_instr *instr,
5227 LLVMValueRef llvm_phi)
5228 {
5229 nir_foreach_phi_src(src, instr) {
5230 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5231 LLVMValueRef llvm_src = get_src(ctx, src->src);
5232
5233 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5234 }
5235 }
5236
5237 static void phi_post_pass(struct ac_nir_context *ctx)
5238 {
5239 struct hash_entry *entry;
5240 hash_table_foreach(ctx->phis, entry) {
5241 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5242 (LLVMValueRef)entry->data);
5243 }
5244 }
5245
5246
5247 static void visit_ssa_undef(struct ac_nir_context *ctx,
5248 const nir_ssa_undef_instr *instr)
5249 {
5250 unsigned num_components = instr->def.num_components;
5251 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5252 LLVMValueRef undef;
5253
5254 if (num_components == 1)
5255 undef = LLVMGetUndef(type);
5256 else {
5257 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5258 }
5259 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5260 }
5261
5262 static void visit_jump(struct ac_nir_context *ctx,
5263 const nir_jump_instr *instr)
5264 {
5265 switch (instr->type) {
5266 case nir_jump_break:
5267 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5268 LLVMClearInsertionPosition(ctx->ac.builder);
5269 break;
5270 case nir_jump_continue:
5271 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5272 LLVMClearInsertionPosition(ctx->ac.builder);
5273 break;
5274 default:
5275 fprintf(stderr, "Unknown NIR jump instr: ");
5276 nir_print_instr(&instr->instr, stderr);
5277 fprintf(stderr, "\n");
5278 abort();
5279 }
5280 }
5281
5282 static void visit_cf_list(struct ac_nir_context *ctx,
5283 struct exec_list *list);
5284
5285 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5286 {
5287 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5288 nir_foreach_instr(instr, block)
5289 {
5290 switch (instr->type) {
5291 case nir_instr_type_alu:
5292 visit_alu(ctx, nir_instr_as_alu(instr));
5293 break;
5294 case nir_instr_type_load_const:
5295 visit_load_const(ctx, nir_instr_as_load_const(instr));
5296 break;
5297 case nir_instr_type_intrinsic:
5298 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5299 break;
5300 case nir_instr_type_tex:
5301 visit_tex(ctx, nir_instr_as_tex(instr));
5302 break;
5303 case nir_instr_type_phi:
5304 visit_phi(ctx, nir_instr_as_phi(instr));
5305 break;
5306 case nir_instr_type_ssa_undef:
5307 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5308 break;
5309 case nir_instr_type_jump:
5310 visit_jump(ctx, nir_instr_as_jump(instr));
5311 break;
5312 default:
5313 fprintf(stderr, "Unknown NIR instr type: ");
5314 nir_print_instr(instr, stderr);
5315 fprintf(stderr, "\n");
5316 abort();
5317 }
5318 }
5319
5320 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5321 }
5322
5323 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5324 {
5325 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5326
5327 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5328 LLVMBasicBlockRef merge_block =
5329 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5330 LLVMBasicBlockRef if_block =
5331 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5332 LLVMBasicBlockRef else_block = merge_block;
5333 if (!exec_list_is_empty(&if_stmt->else_list))
5334 else_block = LLVMAppendBasicBlockInContext(
5335 ctx->ac.context, fn, "");
5336
5337 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5338 ctx->ac.i32_0, "");
5339 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5340
5341 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5342 visit_cf_list(ctx, &if_stmt->then_list);
5343 if (LLVMGetInsertBlock(ctx->ac.builder))
5344 LLVMBuildBr(ctx->ac.builder, merge_block);
5345
5346 if (!exec_list_is_empty(&if_stmt->else_list)) {
5347 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5348 visit_cf_list(ctx, &if_stmt->else_list);
5349 if (LLVMGetInsertBlock(ctx->ac.builder))
5350 LLVMBuildBr(ctx->ac.builder, merge_block);
5351 }
5352
5353 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5354 }
5355
5356 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5357 {
5358 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5359 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5360 LLVMBasicBlockRef break_parent = ctx->break_block;
5361
5362 ctx->continue_block =
5363 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5364 ctx->break_block =
5365 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5366
5367 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5368 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5369 visit_cf_list(ctx, &loop->body);
5370
5371 if (LLVMGetInsertBlock(ctx->ac.builder))
5372 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5373 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5374
5375 ctx->continue_block = continue_parent;
5376 ctx->break_block = break_parent;
5377 }
5378
5379 static void visit_cf_list(struct ac_nir_context *ctx,
5380 struct exec_list *list)
5381 {
5382 foreach_list_typed(nir_cf_node, node, node, list)
5383 {
5384 switch (node->type) {
5385 case nir_cf_node_block:
5386 visit_block(ctx, nir_cf_node_as_block(node));
5387 break;
5388
5389 case nir_cf_node_if:
5390 visit_if(ctx, nir_cf_node_as_if(node));
5391 break;
5392
5393 case nir_cf_node_loop:
5394 visit_loop(ctx, nir_cf_node_as_loop(node));
5395 break;
5396
5397 default:
5398 assert(0);
5399 }
5400 }
5401 }
5402
5403 static void
5404 handle_vs_input_decl(struct radv_shader_context *ctx,
5405 struct nir_variable *variable)
5406 {
5407 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5408 LLVMValueRef t_offset;
5409 LLVMValueRef t_list;
5410 LLVMValueRef input;
5411 LLVMValueRef buffer_index;
5412 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5413 int idx = variable->data.location;
5414 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5415 uint8_t input_usage_mask =
5416 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5417 unsigned num_channels = util_last_bit(input_usage_mask);
5418
5419 variable->data.driver_location = idx * 4;
5420
5421 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5422 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5423 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5424 ctx->abi.start_instance, "");
5425 if (ctx->options->key.vs.as_ls) {
5426 ctx->shader_info->vs.vgpr_comp_cnt =
5427 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5428 } else {
5429 ctx->shader_info->vs.vgpr_comp_cnt =
5430 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5431 }
5432 } else
5433 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5434 ctx->abi.base_vertex, "");
5435 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5436
5437 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5438
5439 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5440 buffer_index,
5441 ctx->ac.i32_0,
5442 num_channels, false, true);
5443
5444 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5445
5446 for (unsigned chan = 0; chan < 4; chan++) {
5447 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5448 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5449 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5450 input, llvm_chan, ""));
5451 }
5452 }
5453 }
5454
5455 static void interp_fs_input(struct radv_shader_context *ctx,
5456 unsigned attr,
5457 LLVMValueRef interp_param,
5458 LLVMValueRef prim_mask,
5459 LLVMValueRef result[4])
5460 {
5461 LLVMValueRef attr_number;
5462 unsigned chan;
5463 LLVMValueRef i, j;
5464 bool interp = interp_param != NULL;
5465
5466 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5467
5468 /* fs.constant returns the param from the middle vertex, so it's not
5469 * really useful for flat shading. It's meant to be used for custom
5470 * interpolation (but the intrinsic can't fetch from the other two
5471 * vertices).
5472 *
5473 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5474 * to do the right thing. The only reason we use fs.constant is that
5475 * fs.interp cannot be used on integers, because they can be equal
5476 * to NaN.
5477 */
5478 if (interp) {
5479 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5480 ctx->ac.v2f32, "");
5481
5482 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5483 ctx->ac.i32_0, "");
5484 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5485 ctx->ac.i32_1, "");
5486 }
5487
5488 for (chan = 0; chan < 4; chan++) {
5489 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5490
5491 if (interp) {
5492 result[chan] = ac_build_fs_interp(&ctx->ac,
5493 llvm_chan,
5494 attr_number,
5495 prim_mask, i, j);
5496 } else {
5497 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5498 LLVMConstInt(ctx->ac.i32, 2, false),
5499 llvm_chan,
5500 attr_number,
5501 prim_mask);
5502 }
5503 }
5504 }
5505
5506 static void
5507 handle_fs_input_decl(struct radv_shader_context *ctx,
5508 struct nir_variable *variable)
5509 {
5510 int idx = variable->data.location;
5511 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5512 LLVMValueRef interp;
5513
5514 variable->data.driver_location = idx * 4;
5515 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5516
5517 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5518 unsigned interp_type;
5519 if (variable->data.sample)
5520 interp_type = INTERP_SAMPLE;
5521 else if (variable->data.centroid)
5522 interp_type = INTERP_CENTROID;
5523 else
5524 interp_type = INTERP_CENTER;
5525
5526 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5527 } else
5528 interp = NULL;
5529
5530 for (unsigned i = 0; i < attrib_count; ++i)
5531 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5532
5533 }
5534
5535 static void
5536 handle_vs_inputs(struct radv_shader_context *ctx,
5537 struct nir_shader *nir) {
5538 nir_foreach_variable(variable, &nir->inputs)
5539 handle_vs_input_decl(ctx, variable);
5540 }
5541
5542 static void
5543 prepare_interp_optimize(struct radv_shader_context *ctx,
5544 struct nir_shader *nir)
5545 {
5546 if (!ctx->options->key.fs.multisample)
5547 return;
5548
5549 bool uses_center = false;
5550 bool uses_centroid = false;
5551 nir_foreach_variable(variable, &nir->inputs) {
5552 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5553 variable->data.sample)
5554 continue;
5555
5556 if (variable->data.centroid)
5557 uses_centroid = true;
5558 else
5559 uses_center = true;
5560 }
5561
5562 if (uses_center && uses_centroid) {
5563 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5564 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5565 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5566 }
5567 }
5568
5569 static void
5570 handle_fs_inputs(struct radv_shader_context *ctx,
5571 struct nir_shader *nir)
5572 {
5573 prepare_interp_optimize(ctx, nir);
5574
5575 nir_foreach_variable(variable, &nir->inputs)
5576 handle_fs_input_decl(ctx, variable);
5577
5578 unsigned index = 0;
5579
5580 if (ctx->shader_info->info.ps.uses_input_attachments ||
5581 ctx->shader_info->info.needs_multiview_view_index)
5582 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5583
5584 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5585 LLVMValueRef interp_param;
5586 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5587
5588 if (!(ctx->input_mask & (1ull << i)))
5589 continue;
5590
5591 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5592 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5593 interp_param = *inputs;
5594 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5595 inputs);
5596
5597 if (!interp_param)
5598 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5599 ++index;
5600 } else if (i == VARYING_SLOT_POS) {
5601 for(int i = 0; i < 3; ++i)
5602 inputs[i] = ctx->abi.frag_pos[i];
5603
5604 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5605 ctx->abi.frag_pos[3]);
5606 }
5607 }
5608 ctx->shader_info->fs.num_interp = index;
5609 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5610 ctx->shader_info->fs.has_pcoord = true;
5611 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5612 ctx->shader_info->fs.prim_id_input = true;
5613 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5614 ctx->shader_info->fs.layer_input = true;
5615 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5616
5617 if (ctx->shader_info->info.needs_multiview_view_index)
5618 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5619 }
5620
5621 static LLVMValueRef
5622 ac_build_alloca(struct ac_llvm_context *ac,
5623 LLVMTypeRef type,
5624 const char *name)
5625 {
5626 LLVMBuilderRef builder = ac->builder;
5627 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5628 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5629 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5630 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5631 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5632 LLVMValueRef res;
5633
5634 if (first_instr) {
5635 LLVMPositionBuilderBefore(first_builder, first_instr);
5636 } else {
5637 LLVMPositionBuilderAtEnd(first_builder, first_block);
5638 }
5639
5640 res = LLVMBuildAlloca(first_builder, type, name);
5641 LLVMBuildStore(builder, LLVMConstNull(type), res);
5642
5643 LLVMDisposeBuilder(first_builder);
5644
5645 return res;
5646 }
5647
5648 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5649 LLVMTypeRef type,
5650 const char *name)
5651 {
5652 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5653 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5654 return ptr;
5655 }
5656
5657 static void
5658 scan_shader_output_decl(struct radv_shader_context *ctx,
5659 struct nir_variable *variable,
5660 struct nir_shader *shader,
5661 gl_shader_stage stage)
5662 {
5663 int idx = variable->data.location + variable->data.index;
5664 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5665 uint64_t mask_attribs;
5666
5667 variable->data.driver_location = idx * 4;
5668
5669 /* tess ctrl has it's own load/store paths for outputs */
5670 if (stage == MESA_SHADER_TESS_CTRL)
5671 return;
5672
5673 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5674 if (stage == MESA_SHADER_VERTEX ||
5675 stage == MESA_SHADER_TESS_EVAL ||
5676 stage == MESA_SHADER_GEOMETRY) {
5677 if (idx == VARYING_SLOT_CLIP_DIST0) {
5678 int length = shader->info.clip_distance_array_size +
5679 shader->info.cull_distance_array_size;
5680 if (stage == MESA_SHADER_VERTEX) {
5681 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5682 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5683 }
5684 if (stage == MESA_SHADER_TESS_EVAL) {
5685 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5686 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5687 }
5688
5689 if (length > 4)
5690 attrib_count = 2;
5691 else
5692 attrib_count = 1;
5693 mask_attribs = 1ull << idx;
5694 }
5695 }
5696
5697 ctx->output_mask |= mask_attribs;
5698 }
5699
5700 static void
5701 handle_shader_output_decl(struct ac_nir_context *ctx,
5702 struct nir_shader *nir,
5703 struct nir_variable *variable)
5704 {
5705 unsigned output_loc = variable->data.driver_location / 4;
5706 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5707
5708 /* tess ctrl has it's own load/store paths for outputs */
5709 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5710 return;
5711
5712 if (ctx->stage == MESA_SHADER_VERTEX ||
5713 ctx->stage == MESA_SHADER_TESS_EVAL ||
5714 ctx->stage == MESA_SHADER_GEOMETRY) {
5715 int idx = variable->data.location + variable->data.index;
5716 if (idx == VARYING_SLOT_CLIP_DIST0) {
5717 int length = nir->info.clip_distance_array_size +
5718 nir->info.cull_distance_array_size;
5719
5720 if (length > 4)
5721 attrib_count = 2;
5722 else
5723 attrib_count = 1;
5724 }
5725 }
5726
5727 for (unsigned i = 0; i < attrib_count; ++i) {
5728 for (unsigned chan = 0; chan < 4; chan++) {
5729 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5730 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5731 }
5732 }
5733 }
5734
5735 static LLVMTypeRef
5736 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5737 enum glsl_base_type type)
5738 {
5739 switch (type) {
5740 case GLSL_TYPE_INT:
5741 case GLSL_TYPE_UINT:
5742 case GLSL_TYPE_BOOL:
5743 case GLSL_TYPE_SUBROUTINE:
5744 return ac->i32;
5745 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5746 return ac->f32;
5747 case GLSL_TYPE_INT64:
5748 case GLSL_TYPE_UINT64:
5749 return ac->i64;
5750 case GLSL_TYPE_DOUBLE:
5751 return ac->f64;
5752 default:
5753 unreachable("unknown GLSL type");
5754 }
5755 }
5756
5757 static LLVMTypeRef
5758 glsl_to_llvm_type(struct ac_llvm_context *ac,
5759 const struct glsl_type *type)
5760 {
5761 if (glsl_type_is_scalar(type)) {
5762 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5763 }
5764
5765 if (glsl_type_is_vector(type)) {
5766 return LLVMVectorType(
5767 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5768 glsl_get_vector_elements(type));
5769 }
5770
5771 if (glsl_type_is_matrix(type)) {
5772 return LLVMArrayType(
5773 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5774 glsl_get_matrix_columns(type));
5775 }
5776
5777 if (glsl_type_is_array(type)) {
5778 return LLVMArrayType(
5779 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5780 glsl_get_length(type));
5781 }
5782
5783 assert(glsl_type_is_struct(type));
5784
5785 LLVMTypeRef member_types[glsl_get_length(type)];
5786
5787 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5788 member_types[i] =
5789 glsl_to_llvm_type(ac,
5790 glsl_get_struct_field(type, i));
5791 }
5792
5793 return LLVMStructTypeInContext(ac->context, member_types,
5794 glsl_get_length(type), false);
5795 }
5796
5797 static void
5798 setup_locals(struct ac_nir_context *ctx,
5799 struct nir_function *func)
5800 {
5801 int i, j;
5802 ctx->num_locals = 0;
5803 nir_foreach_variable(variable, &func->impl->locals) {
5804 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5805 variable->data.driver_location = ctx->num_locals * 4;
5806 variable->data.location_frac = 0;
5807 ctx->num_locals += attrib_count;
5808 }
5809 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5810 if (!ctx->locals)
5811 return;
5812
5813 for (i = 0; i < ctx->num_locals; i++) {
5814 for (j = 0; j < 4; j++) {
5815 ctx->locals[i * 4 + j] =
5816 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5817 }
5818 }
5819 }
5820
5821 static void
5822 setup_shared(struct ac_nir_context *ctx,
5823 struct nir_shader *nir)
5824 {
5825 nir_foreach_variable(variable, &nir->shared) {
5826 LLVMValueRef shared =
5827 LLVMAddGlobalInAddressSpace(
5828 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5829 variable->name ? variable->name : "",
5830 AC_LOCAL_ADDR_SPACE);
5831 _mesa_hash_table_insert(ctx->vars, variable, shared);
5832 }
5833 }
5834
5835 /* Initialize arguments for the shader export intrinsic */
5836 static void
5837 si_llvm_init_export_args(struct radv_shader_context *ctx,
5838 LLVMValueRef *values,
5839 unsigned target,
5840 struct ac_export_args *args)
5841 {
5842 /* Default is 0xf. Adjusted below depending on the format. */
5843 args->enabled_channels = 0xf;
5844
5845 /* Specify whether the EXEC mask represents the valid mask */
5846 args->valid_mask = 0;
5847
5848 /* Specify whether this is the last export */
5849 args->done = 0;
5850
5851 /* Specify the target we are exporting */
5852 args->target = target;
5853
5854 args->compr = false;
5855 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5856 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5857 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5858 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5859
5860 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5861 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5862 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5863 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5864 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5865 unsigned chan;
5866
5867 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5868 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5869 unsigned bits, bool hi) = NULL;
5870
5871 switch(col_format) {
5872 case V_028714_SPI_SHADER_ZERO:
5873 args->enabled_channels = 0; /* writemask */
5874 args->target = V_008DFC_SQ_EXP_NULL;
5875 break;
5876
5877 case V_028714_SPI_SHADER_32_R:
5878 args->enabled_channels = 1;
5879 args->out[0] = values[0];
5880 break;
5881
5882 case V_028714_SPI_SHADER_32_GR:
5883 args->enabled_channels = 0x3;
5884 args->out[0] = values[0];
5885 args->out[1] = values[1];
5886 break;
5887
5888 case V_028714_SPI_SHADER_32_AR:
5889 args->enabled_channels = 0x9;
5890 args->out[0] = values[0];
5891 args->out[3] = values[3];
5892 break;
5893
5894 case V_028714_SPI_SHADER_FP16_ABGR:
5895 packf = ac_build_cvt_pkrtz_f16;
5896 break;
5897
5898 case V_028714_SPI_SHADER_UNORM16_ABGR:
5899 packf = ac_build_cvt_pknorm_u16;
5900 break;
5901
5902 case V_028714_SPI_SHADER_SNORM16_ABGR:
5903 packf = ac_build_cvt_pknorm_i16;
5904 break;
5905
5906 case V_028714_SPI_SHADER_UINT16_ABGR:
5907 packi = ac_build_cvt_pk_u16;
5908 break;
5909
5910 case V_028714_SPI_SHADER_SINT16_ABGR:
5911 packi = ac_build_cvt_pk_i16;
5912 break;
5913
5914 default:
5915 case V_028714_SPI_SHADER_32_ABGR:
5916 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5917 break;
5918 }
5919
5920 /* Pack f16 or norm_i16/u16. */
5921 if (packf) {
5922 for (chan = 0; chan < 2; chan++) {
5923 LLVMValueRef pack_args[2] = {
5924 values[2 * chan],
5925 values[2 * chan + 1]
5926 };
5927 LLVMValueRef packed;
5928
5929 packed = packf(&ctx->ac, pack_args);
5930 args->out[chan] = ac_to_float(&ctx->ac, packed);
5931 }
5932 args->compr = 1; /* COMPR flag */
5933 }
5934
5935 /* Pack i16/u16. */
5936 if (packi) {
5937 for (chan = 0; chan < 2; chan++) {
5938 LLVMValueRef pack_args[2] = {
5939 ac_to_integer(&ctx->ac, values[2 * chan]),
5940 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5941 };
5942 LLVMValueRef packed;
5943
5944 packed = packi(&ctx->ac, pack_args,
5945 is_int8 ? 8 : is_int10 ? 10 : 16,
5946 chan == 1);
5947 args->out[chan] = ac_to_float(&ctx->ac, packed);
5948 }
5949 args->compr = 1; /* COMPR flag */
5950 }
5951 return;
5952 }
5953
5954 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5955
5956 for (unsigned i = 0; i < 4; ++i)
5957 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5958 }
5959
5960 static void
5961 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5962 LLVMValueRef *values)
5963 {
5964 struct ac_export_args args;
5965
5966 si_llvm_init_export_args(ctx, values,
5967 V_008DFC_SQ_EXP_PARAM + index, &args);
5968 ac_build_export(&ctx->ac, &args);
5969 }
5970
5971 static LLVMValueRef
5972 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5973 {
5974 LLVMValueRef output =
5975 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5976
5977 return LLVMBuildLoad(ctx->ac.builder, output, "");
5978 }
5979
5980 static void
5981 handle_vs_outputs_post(struct radv_shader_context *ctx,
5982 bool export_prim_id,
5983 struct ac_vs_output_info *outinfo)
5984 {
5985 uint32_t param_count = 0;
5986 unsigned target;
5987 unsigned pos_idx, num_pos_exports = 0;
5988 struct ac_export_args args, pos_args[4] = {};
5989 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5990 int i;
5991
5992 if (ctx->options->key.has_multiview_view_index) {
5993 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5994 if(!*tmp_out) {
5995 for(unsigned i = 0; i < 4; ++i)
5996 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5997 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5998 }
5999
6000 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
6001 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
6002 }
6003
6004 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6005 sizeof(outinfo->vs_output_param_offset));
6006
6007 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
6008 LLVMValueRef slots[8];
6009 unsigned j;
6010
6011 if (outinfo->cull_dist_mask)
6012 outinfo->cull_dist_mask <<= ctx->num_output_clips;
6013
6014 i = VARYING_SLOT_CLIP_DIST0;
6015 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
6016 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6017
6018 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
6019 slots[i] = LLVMGetUndef(ctx->ac.f32);
6020
6021 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
6022 target = V_008DFC_SQ_EXP_POS + 3;
6023 si_llvm_init_export_args(ctx, &slots[4], target, &args);
6024 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6025 &args, sizeof(args));
6026 }
6027
6028 target = V_008DFC_SQ_EXP_POS + 2;
6029 si_llvm_init_export_args(ctx, &slots[0], target, &args);
6030 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6031 &args, sizeof(args));
6032
6033 }
6034
6035 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6036 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6037 for (unsigned j = 0; j < 4; j++)
6038 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6039 }
6040 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6041
6042 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6043 outinfo->writes_pointsize = true;
6044 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6045 }
6046
6047 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6048 outinfo->writes_layer = true;
6049 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6050 }
6051
6052 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6053 outinfo->writes_viewport_index = true;
6054 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6055 }
6056
6057 if (outinfo->writes_pointsize ||
6058 outinfo->writes_layer ||
6059 outinfo->writes_viewport_index) {
6060 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6061 (outinfo->writes_layer == true ? 4 : 0));
6062 pos_args[1].valid_mask = 0;
6063 pos_args[1].done = 0;
6064 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6065 pos_args[1].compr = 0;
6066 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6067 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6068 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6069 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6070
6071 if (outinfo->writes_pointsize == true)
6072 pos_args[1].out[0] = psize_value;
6073 if (outinfo->writes_layer == true)
6074 pos_args[1].out[2] = layer_value;
6075 if (outinfo->writes_viewport_index == true) {
6076 if (ctx->options->chip_class >= GFX9) {
6077 /* GFX9 has the layer in out.z[10:0] and the viewport
6078 * index in out.z[19:16].
6079 */
6080 LLVMValueRef v = viewport_index_value;
6081 v = ac_to_integer(&ctx->ac, v);
6082 v = LLVMBuildShl(ctx->ac.builder, v,
6083 LLVMConstInt(ctx->ac.i32, 16, false),
6084 "");
6085 v = LLVMBuildOr(ctx->ac.builder, v,
6086 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6087
6088 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6089 pos_args[1].enabled_channels |= 1 << 2;
6090 } else {
6091 pos_args[1].out[3] = viewport_index_value;
6092 pos_args[1].enabled_channels |= 1 << 3;
6093 }
6094 }
6095 }
6096 for (i = 0; i < 4; i++) {
6097 if (pos_args[i].out[0])
6098 num_pos_exports++;
6099 }
6100
6101 pos_idx = 0;
6102 for (i = 0; i < 4; i++) {
6103 if (!pos_args[i].out[0])
6104 continue;
6105
6106 /* Specify the target we are exporting */
6107 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6108 if (pos_idx == num_pos_exports)
6109 pos_args[i].done = 1;
6110 ac_build_export(&ctx->ac, &pos_args[i]);
6111 }
6112
6113 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6114 LLVMValueRef values[4];
6115 if (!(ctx->output_mask & (1ull << i)))
6116 continue;
6117
6118 if (i != VARYING_SLOT_LAYER &&
6119 i != VARYING_SLOT_PRIMITIVE_ID &&
6120 i < VARYING_SLOT_VAR0)
6121 continue;
6122
6123 for (unsigned j = 0; j < 4; j++)
6124 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6125
6126 radv_export_param(ctx, param_count, values);
6127
6128 outinfo->vs_output_param_offset[i] = param_count++;
6129 }
6130
6131 if (export_prim_id) {
6132 LLVMValueRef values[4];
6133
6134 values[0] = ctx->vs_prim_id;
6135 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6136 ctx->shader_info->vs.vgpr_comp_cnt);
6137 for (unsigned j = 1; j < 4; j++)
6138 values[j] = ctx->ac.f32_0;
6139
6140 radv_export_param(ctx, param_count, values);
6141
6142 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6143 outinfo->export_prim_id = true;
6144 }
6145
6146 outinfo->pos_exports = num_pos_exports;
6147 outinfo->param_exports = param_count;
6148 }
6149
6150 static void
6151 handle_es_outputs_post(struct radv_shader_context *ctx,
6152 struct ac_es_output_info *outinfo)
6153 {
6154 int j;
6155 uint64_t max_output_written = 0;
6156 LLVMValueRef lds_base = NULL;
6157
6158 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6159 int param_index;
6160 int length = 4;
6161
6162 if (!(ctx->output_mask & (1ull << i)))
6163 continue;
6164
6165 if (i == VARYING_SLOT_CLIP_DIST0)
6166 length = ctx->num_output_clips + ctx->num_output_culls;
6167
6168 param_index = shader_io_get_unique_index(i);
6169
6170 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6171 }
6172
6173 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6174
6175 if (ctx->ac.chip_class >= GFX9) {
6176 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6177 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6178 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6179 LLVMConstInt(ctx->ac.i32, 24, false),
6180 LLVMConstInt(ctx->ac.i32, 4, false), false);
6181 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6182 LLVMBuildMul(ctx->ac.builder, wave_idx,
6183 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6184 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6185 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6186 }
6187
6188 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6189 LLVMValueRef dw_addr = NULL;
6190 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6191 int param_index;
6192 int length = 4;
6193
6194 if (!(ctx->output_mask & (1ull << i)))
6195 continue;
6196
6197 if (i == VARYING_SLOT_CLIP_DIST0)
6198 length = ctx->num_output_clips + ctx->num_output_culls;
6199
6200 param_index = shader_io_get_unique_index(i);
6201
6202 if (lds_base) {
6203 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6204 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6205 "");
6206 }
6207 for (j = 0; j < length; j++) {
6208 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6209 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6210
6211 if (ctx->ac.chip_class >= GFX9) {
6212 ac_lds_store(&ctx->ac, dw_addr,
6213 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6214 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6215 } else {
6216 ac_build_buffer_store_dword(&ctx->ac,
6217 ctx->esgs_ring,
6218 out_val, 1,
6219 NULL, ctx->es2gs_offset,
6220 (4 * param_index + j) * 4,
6221 1, 1, true, true);
6222 }
6223 }
6224 }
6225 }
6226
6227 static void
6228 handle_ls_outputs_post(struct radv_shader_context *ctx)
6229 {
6230 LLVMValueRef vertex_id = ctx->rel_auto_id;
6231 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6232 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6233 vertex_dw_stride, "");
6234
6235 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6236 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6237 int length = 4;
6238
6239 if (!(ctx->output_mask & (1ull << i)))
6240 continue;
6241
6242 if (i == VARYING_SLOT_CLIP_DIST0)
6243 length = ctx->num_output_clips + ctx->num_output_culls;
6244 int param = shader_io_get_unique_index(i);
6245 mark_tess_output(ctx, false, param);
6246 if (length > 4)
6247 mark_tess_output(ctx, false, param + 1);
6248 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6249 LLVMConstInt(ctx->ac.i32, param * 4, false),
6250 "");
6251 for (unsigned j = 0; j < length; j++) {
6252 ac_lds_store(&ctx->ac, dw_addr,
6253 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6254 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6255 }
6256 }
6257 }
6258
6259 struct ac_build_if_state
6260 {
6261 struct radv_shader_context *ctx;
6262 LLVMValueRef condition;
6263 LLVMBasicBlockRef entry_block;
6264 LLVMBasicBlockRef true_block;
6265 LLVMBasicBlockRef false_block;
6266 LLVMBasicBlockRef merge_block;
6267 };
6268
6269 static LLVMBasicBlockRef
6270 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6271 {
6272 LLVMBasicBlockRef current_block;
6273 LLVMBasicBlockRef next_block;
6274 LLVMBasicBlockRef new_block;
6275
6276 /* get current basic block */
6277 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6278
6279 /* chqeck if there's another block after this one */
6280 next_block = LLVMGetNextBasicBlock(current_block);
6281 if (next_block) {
6282 /* insert the new block before the next block */
6283 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6284 }
6285 else {
6286 /* append new block after current block */
6287 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6288 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6289 }
6290 return new_block;
6291 }
6292
6293 static void
6294 ac_nir_build_if(struct ac_build_if_state *ifthen,
6295 struct radv_shader_context *ctx,
6296 LLVMValueRef condition)
6297 {
6298 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6299
6300 memset(ifthen, 0, sizeof *ifthen);
6301 ifthen->ctx = ctx;
6302 ifthen->condition = condition;
6303 ifthen->entry_block = block;
6304
6305 /* create endif/merge basic block for the phi functions */
6306 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6307
6308 /* create/insert true_block before merge_block */
6309 ifthen->true_block =
6310 LLVMInsertBasicBlockInContext(ctx->context,
6311 ifthen->merge_block,
6312 "if-true-block");
6313
6314 /* successive code goes into the true block */
6315 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6316 }
6317
6318 /**
6319 * End a conditional.
6320 */
6321 static void
6322 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6323 {
6324 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6325
6326 /* Insert branch to the merge block from current block */
6327 LLVMBuildBr(builder, ifthen->merge_block);
6328
6329 /*
6330 * Now patch in the various branch instructions.
6331 */
6332
6333 /* Insert the conditional branch instruction at the end of entry_block */
6334 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6335 if (ifthen->false_block) {
6336 /* we have an else clause */
6337 LLVMBuildCondBr(builder, ifthen->condition,
6338 ifthen->true_block, ifthen->false_block);
6339 }
6340 else {
6341 /* no else clause */
6342 LLVMBuildCondBr(builder, ifthen->condition,
6343 ifthen->true_block, ifthen->merge_block);
6344 }
6345
6346 /* Resume building code at end of the ifthen->merge_block */
6347 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6348 }
6349
6350 static void
6351 write_tess_factors(struct radv_shader_context *ctx)
6352 {
6353 unsigned stride, outer_comps, inner_comps;
6354 struct ac_build_if_state if_ctx, inner_if_ctx;
6355 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6356 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6357 unsigned tess_inner_index, tess_outer_index;
6358 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6359 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6360 int i;
6361 emit_barrier(&ctx->ac, ctx->stage);
6362
6363 switch (ctx->options->key.tcs.primitive_mode) {
6364 case GL_ISOLINES:
6365 stride = 2;
6366 outer_comps = 2;
6367 inner_comps = 0;
6368 break;
6369 case GL_TRIANGLES:
6370 stride = 4;
6371 outer_comps = 3;
6372 inner_comps = 1;
6373 break;
6374 case GL_QUADS:
6375 stride = 6;
6376 outer_comps = 4;
6377 inner_comps = 2;
6378 break;
6379 default:
6380 return;
6381 }
6382
6383 ac_nir_build_if(&if_ctx, ctx,
6384 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6385 invocation_id, ctx->ac.i32_0, ""));
6386
6387 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6388 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6389
6390 mark_tess_output(ctx, true, tess_inner_index);
6391 mark_tess_output(ctx, true, tess_outer_index);
6392 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6393 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6394 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6395 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6396 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6397
6398 for (i = 0; i < 4; i++) {
6399 inner[i] = LLVMGetUndef(ctx->ac.i32);
6400 outer[i] = LLVMGetUndef(ctx->ac.i32);
6401 }
6402
6403 // LINES reverseal
6404 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6405 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6406 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6407 ctx->ac.i32_1, "");
6408 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6409 } else {
6410 for (i = 0; i < outer_comps; i++) {
6411 outer[i] = out[i] =
6412 ac_lds_load(&ctx->ac, lds_outer);
6413 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6414 ctx->ac.i32_1, "");
6415 }
6416 for (i = 0; i < inner_comps; i++) {
6417 inner[i] = out[outer_comps+i] =
6418 ac_lds_load(&ctx->ac, lds_inner);
6419 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6420 ctx->ac.i32_1, "");
6421 }
6422 }
6423
6424 /* Convert the outputs to vectors for stores. */
6425 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6426 vec1 = NULL;
6427
6428 if (stride > 4)
6429 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6430
6431
6432 buffer = ctx->hs_ring_tess_factor;
6433 tf_base = ctx->tess_factor_offset;
6434 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6435 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6436 unsigned tf_offset = 0;
6437
6438 if (ctx->options->chip_class <= VI) {
6439 ac_nir_build_if(&inner_if_ctx, ctx,
6440 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6441 rel_patch_id, ctx->ac.i32_0, ""));
6442
6443 /* Store the dynamic HS control word. */
6444 ac_build_buffer_store_dword(&ctx->ac, buffer,
6445 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6446 1, ctx->ac.i32_0, tf_base,
6447 0, 1, 0, true, false);
6448 tf_offset += 4;
6449
6450 ac_nir_build_endif(&inner_if_ctx);
6451 }
6452
6453 /* Store the tessellation factors. */
6454 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6455 MIN2(stride, 4), byteoffset, tf_base,
6456 tf_offset, 1, 0, true, false);
6457 if (vec1)
6458 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6459 stride - 4, byteoffset, tf_base,
6460 16 + tf_offset, 1, 0, true, false);
6461
6462 //store to offchip for TES to read - only if TES reads them
6463 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6464 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6465 LLVMValueRef tf_inner_offset;
6466 unsigned param_outer, param_inner;
6467
6468 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6469 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6470 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6471
6472 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6473 util_next_power_of_two(outer_comps));
6474
6475 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6476 outer_comps, tf_outer_offset,
6477 ctx->oc_lds, 0, 1, 0, true, false);
6478 if (inner_comps) {
6479 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6480 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6481 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6482
6483 inner_vec = inner_comps == 1 ? inner[0] :
6484 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6485 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6486 inner_comps, tf_inner_offset,
6487 ctx->oc_lds, 0, 1, 0, true, false);
6488 }
6489 }
6490 ac_nir_build_endif(&if_ctx);
6491 }
6492
6493 static void
6494 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6495 {
6496 write_tess_factors(ctx);
6497 }
6498
6499 static bool
6500 si_export_mrt_color(struct radv_shader_context *ctx,
6501 LLVMValueRef *color, unsigned index, bool is_last,
6502 struct ac_export_args *args)
6503 {
6504 /* Export */
6505 si_llvm_init_export_args(ctx, color,
6506 V_008DFC_SQ_EXP_MRT + index, args);
6507
6508 if (is_last) {
6509 args->valid_mask = 1; /* whether the EXEC mask is valid */
6510 args->done = 1; /* DONE bit */
6511 } else if (!args->enabled_channels)
6512 return false; /* unnecessary NULL export */
6513
6514 return true;
6515 }
6516
6517 static void
6518 radv_export_mrt_z(struct radv_shader_context *ctx,
6519 LLVMValueRef depth, LLVMValueRef stencil,
6520 LLVMValueRef samplemask)
6521 {
6522 struct ac_export_args args;
6523
6524 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6525
6526 ac_build_export(&ctx->ac, &args);
6527 }
6528
6529 static void
6530 handle_fs_outputs_post(struct radv_shader_context *ctx)
6531 {
6532 unsigned index = 0;
6533 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6534 struct ac_export_args color_args[8];
6535
6536 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6537 LLVMValueRef values[4];
6538 bool last = false;
6539
6540 if (!(ctx->output_mask & (1ull << i)))
6541 continue;
6542
6543 if (i < FRAG_RESULT_DATA0)
6544 continue;
6545
6546 for (unsigned j = 0; j < 4; j++)
6547 values[j] = ac_to_float(&ctx->ac,
6548 radv_load_output(ctx, i, j));
6549
6550 if (!ctx->shader_info->info.ps.writes_z &&
6551 !ctx->shader_info->info.ps.writes_stencil &&
6552 !ctx->shader_info->info.ps.writes_sample_mask)
6553 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6554
6555 bool ret = si_export_mrt_color(ctx, values,
6556 i - FRAG_RESULT_DATA0,
6557 last, &color_args[index]);
6558 if (ret)
6559 index++;
6560 }
6561
6562 /* Process depth, stencil, samplemask. */
6563 if (ctx->shader_info->info.ps.writes_z) {
6564 depth = ac_to_float(&ctx->ac,
6565 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6566 }
6567 if (ctx->shader_info->info.ps.writes_stencil) {
6568 stencil = ac_to_float(&ctx->ac,
6569 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6570 }
6571 if (ctx->shader_info->info.ps.writes_sample_mask) {
6572 samplemask = ac_to_float(&ctx->ac,
6573 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6574 }
6575
6576 /* Export PS outputs. */
6577 for (unsigned i = 0; i < index; i++)
6578 ac_build_export(&ctx->ac, &color_args[i]);
6579
6580 if (depth || stencil || samplemask)
6581 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6582 else if (!index)
6583 ac_build_export_null(&ctx->ac);
6584 }
6585
6586 static void
6587 emit_gs_epilogue(struct radv_shader_context *ctx)
6588 {
6589 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6590 }
6591
6592 static void
6593 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6594 LLVMValueRef *addrs)
6595 {
6596 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6597
6598 switch (ctx->stage) {
6599 case MESA_SHADER_VERTEX:
6600 if (ctx->options->key.vs.as_ls)
6601 handle_ls_outputs_post(ctx);
6602 else if (ctx->options->key.vs.as_es)
6603 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6604 else
6605 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6606 &ctx->shader_info->vs.outinfo);
6607 break;
6608 case MESA_SHADER_FRAGMENT:
6609 handle_fs_outputs_post(ctx);
6610 break;
6611 case MESA_SHADER_GEOMETRY:
6612 emit_gs_epilogue(ctx);
6613 break;
6614 case MESA_SHADER_TESS_CTRL:
6615 handle_tcs_outputs_post(ctx);
6616 break;
6617 case MESA_SHADER_TESS_EVAL:
6618 if (ctx->options->key.tes.as_es)
6619 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6620 else
6621 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6622 &ctx->shader_info->tes.outinfo);
6623 break;
6624 default:
6625 break;
6626 }
6627 }
6628
6629 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6630 {
6631 LLVMPassManagerRef passmgr;
6632 /* Create the pass manager */
6633 passmgr = LLVMCreateFunctionPassManagerForModule(
6634 ctx->ac.module);
6635
6636 /* This pass should eliminate all the load and store instructions */
6637 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6638
6639 /* Add some optimization passes */
6640 LLVMAddScalarReplAggregatesPass(passmgr);
6641 LLVMAddLICMPass(passmgr);
6642 LLVMAddAggressiveDCEPass(passmgr);
6643 LLVMAddCFGSimplificationPass(passmgr);
6644 LLVMAddInstructionCombiningPass(passmgr);
6645
6646 /* Run the pass */
6647 LLVMInitializeFunctionPassManager(passmgr);
6648 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6649 LLVMFinalizeFunctionPassManager(passmgr);
6650
6651 LLVMDisposeBuilder(ctx->ac.builder);
6652 LLVMDisposePassManager(passmgr);
6653 }
6654
6655 static void
6656 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6657 {
6658 struct ac_vs_output_info *outinfo;
6659
6660 switch (ctx->stage) {
6661 case MESA_SHADER_FRAGMENT:
6662 case MESA_SHADER_COMPUTE:
6663 case MESA_SHADER_TESS_CTRL:
6664 case MESA_SHADER_GEOMETRY:
6665 return;
6666 case MESA_SHADER_VERTEX:
6667 if (ctx->options->key.vs.as_ls ||
6668 ctx->options->key.vs.as_es)
6669 return;
6670 outinfo = &ctx->shader_info->vs.outinfo;
6671 break;
6672 case MESA_SHADER_TESS_EVAL:
6673 if (ctx->options->key.vs.as_es)
6674 return;
6675 outinfo = &ctx->shader_info->tes.outinfo;
6676 break;
6677 default:
6678 unreachable("Unhandled shader type");
6679 }
6680
6681 ac_optimize_vs_outputs(&ctx->ac,
6682 ctx->main_function,
6683 outinfo->vs_output_param_offset,
6684 VARYING_SLOT_MAX,
6685 &outinfo->param_exports);
6686 }
6687
6688 static void
6689 ac_setup_rings(struct radv_shader_context *ctx)
6690 {
6691 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6692 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6693 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6694 }
6695
6696 if (ctx->is_gs_copy_shader) {
6697 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6698 }
6699 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6700 LLVMValueRef tmp;
6701 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6702 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6703
6704 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6705
6706 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6707 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6708 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6709 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6710 }
6711
6712 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6713 ctx->stage == MESA_SHADER_TESS_EVAL) {
6714 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6715 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6716 }
6717 }
6718
6719 static unsigned
6720 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6721 const struct nir_shader *nir)
6722 {
6723 switch (nir->info.stage) {
6724 case MESA_SHADER_TESS_CTRL:
6725 return chip_class >= CIK ? 128 : 64;
6726 case MESA_SHADER_GEOMETRY:
6727 return chip_class >= GFX9 ? 128 : 64;
6728 case MESA_SHADER_COMPUTE:
6729 break;
6730 default:
6731 return 0;
6732 }
6733
6734 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6735 nir->info.cs.local_size[1] *
6736 nir->info.cs.local_size[2];
6737 return max_workgroup_size;
6738 }
6739
6740 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6741 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6742 {
6743 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6744 LLVMConstInt(ctx->ac.i32, 8, false),
6745 LLVMConstInt(ctx->ac.i32, 8, false), false);
6746 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6747 ctx->ac.i32_0, "");
6748 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6749 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6750 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6751 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6752 }
6753
6754 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6755 {
6756 for(int i = 5; i >= 0; --i) {
6757 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6758 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6759 LLVMConstInt(ctx->ac.i32, 16, false), false);
6760 }
6761
6762 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6763 LLVMConstInt(ctx->ac.i32, 16, false),
6764 LLVMConstInt(ctx->ac.i32, 8, false), false);
6765 }
6766
6767 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6768 struct nir_shader *nir)
6769 {
6770 struct ac_nir_context ctx = {};
6771 struct nir_function *func;
6772
6773 ctx.ac = *ac;
6774 ctx.abi = abi;
6775
6776 ctx.stage = nir->info.stage;
6777
6778 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6779
6780 nir_foreach_variable(variable, &nir->outputs)
6781 handle_shader_output_decl(&ctx, nir, variable);
6782
6783 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6784 _mesa_key_pointer_equal);
6785 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6786 _mesa_key_pointer_equal);
6787 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6788 _mesa_key_pointer_equal);
6789
6790 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6791
6792 setup_locals(&ctx, func);
6793
6794 if (nir->info.stage == MESA_SHADER_COMPUTE)
6795 setup_shared(&ctx, nir);
6796
6797 visit_cf_list(&ctx, &func->impl->body);
6798 phi_post_pass(&ctx);
6799
6800 if (nir->info.stage != MESA_SHADER_COMPUTE)
6801 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6802 ctx.abi->outputs);
6803
6804 free(ctx.locals);
6805 ralloc_free(ctx.defs);
6806 ralloc_free(ctx.phis);
6807 ralloc_free(ctx.vars);
6808 }
6809
6810 static
6811 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6812 struct nir_shader *const *shaders,
6813 int shader_count,
6814 struct ac_shader_variant_info *shader_info,
6815 const struct ac_nir_compiler_options *options)
6816 {
6817 struct radv_shader_context ctx = {0};
6818 unsigned i;
6819 ctx.options = options;
6820 ctx.shader_info = shader_info;
6821 ctx.context = LLVMContextCreate();
6822
6823 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6824 options->family);
6825 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6826 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6827
6828 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6829 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6830 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6831 LLVMDisposeTargetData(data_layout);
6832 LLVMDisposeMessage(data_layout_str);
6833
6834 enum ac_float_mode float_mode =
6835 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6836 AC_FLOAT_MODE_DEFAULT;
6837
6838 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6839
6840 memset(shader_info, 0, sizeof(*shader_info));
6841
6842 for(int i = 0; i < shader_count; ++i)
6843 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6844
6845 for (i = 0; i < AC_UD_MAX_SETS; i++)
6846 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6847 for (i = 0; i < AC_UD_MAX_UD; i++)
6848 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6849
6850 ctx.max_workgroup_size = 0;
6851 for (int i = 0; i < shader_count; ++i) {
6852 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6853 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6854 shaders[i]));
6855 }
6856
6857 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6858 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6859
6860 ctx.abi.inputs = &ctx.inputs[0];
6861 ctx.abi.emit_outputs = handle_shader_outputs_post;
6862 ctx.abi.emit_vertex = visit_emit_vertex;
6863 ctx.abi.load_ubo = radv_load_ubo;
6864 ctx.abi.load_ssbo = radv_load_ssbo;
6865 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6866 ctx.abi.load_resource = radv_load_resource;
6867 ctx.abi.clamp_shadow_reference = false;
6868
6869 if (shader_count >= 2)
6870 ac_init_exec_full_mask(&ctx.ac);
6871
6872 if (ctx.ac.chip_class == GFX9 &&
6873 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6874 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6875
6876 for(int i = 0; i < shader_count; ++i) {
6877 ctx.stage = shaders[i]->info.stage;
6878 ctx.output_mask = 0;
6879 ctx.tess_outputs_written = 0;
6880 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6881 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6882
6883 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6884 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6885 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6886 ctx.abi.load_inputs = load_gs_input;
6887 ctx.abi.emit_primitive = visit_end_primitive;
6888 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6889 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6890 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6891 ctx.abi.load_tess_varyings = load_tcs_varyings;
6892 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6893 ctx.abi.store_tcs_outputs = store_tcs_output;
6894 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6895 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6896 ctx.abi.load_tess_varyings = load_tes_input;
6897 ctx.abi.load_tess_coord = load_tess_coord;
6898 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6899 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6900 if (shader_info->info.vs.needs_instance_id) {
6901 if (ctx.options->key.vs.as_ls) {
6902 ctx.shader_info->vs.vgpr_comp_cnt =
6903 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6904 } else {
6905 ctx.shader_info->vs.vgpr_comp_cnt =
6906 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6907 }
6908 }
6909 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6910 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6911 ctx.abi.lookup_interp_param = lookup_interp_param;
6912 ctx.abi.load_sample_position = load_sample_position;
6913 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6914 }
6915
6916 if (i)
6917 emit_barrier(&ctx.ac, ctx.stage);
6918
6919 ac_setup_rings(&ctx);
6920
6921 LLVMBasicBlockRef merge_block;
6922 if (shader_count >= 2) {
6923 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6924 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6925 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6926
6927 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6928 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6929 LLVMConstInt(ctx.ac.i32, 8, false), false);
6930 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6931 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6932 thread_id, count, "");
6933 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6934
6935 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6936 }
6937
6938 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6939 handle_fs_inputs(&ctx, shaders[i]);
6940 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6941 handle_vs_inputs(&ctx, shaders[i]);
6942 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6943 prepare_gs_input_vgprs(&ctx);
6944
6945 nir_foreach_variable(variable, &shaders[i]->outputs)
6946 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6947
6948 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6949
6950 if (shader_count >= 2) {
6951 LLVMBuildBr(ctx.ac.builder, merge_block);
6952 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6953 }
6954
6955 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6956 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6957 shaders[i]->info.cull_distance_array_size > 4;
6958 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6959 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6960 shaders[i]->info.gs.vertices_out;
6961 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6962 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6963 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6964 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6965 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6966 }
6967 }
6968
6969 LLVMBuildRetVoid(ctx.ac.builder);
6970
6971 if (options->dump_preoptir)
6972 ac_dump_module(ctx.ac.module);
6973
6974 ac_llvm_finalize_module(&ctx);
6975
6976 if (shader_count == 1)
6977 ac_nir_eliminate_const_vs_outputs(&ctx);
6978
6979 return ctx.ac.module;
6980 }
6981
6982 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6983 {
6984 unsigned *retval = (unsigned *)context;
6985 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6986 char *description = LLVMGetDiagInfoDescription(di);
6987
6988 if (severity == LLVMDSError) {
6989 *retval = 1;
6990 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6991 description);
6992 }
6993
6994 LLVMDisposeMessage(description);
6995 }
6996
6997 static unsigned ac_llvm_compile(LLVMModuleRef M,
6998 struct ac_shader_binary *binary,
6999 LLVMTargetMachineRef tm)
7000 {
7001 unsigned retval = 0;
7002 char *err;
7003 LLVMContextRef llvm_ctx;
7004 LLVMMemoryBufferRef out_buffer;
7005 unsigned buffer_size;
7006 const char *buffer_data;
7007 LLVMBool mem_err;
7008
7009 /* Setup Diagnostic Handler*/
7010 llvm_ctx = LLVMGetModuleContext(M);
7011
7012 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
7013 &retval);
7014
7015 /* Compile IR*/
7016 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
7017 &err, &out_buffer);
7018
7019 /* Process Errors/Warnings */
7020 if (mem_err) {
7021 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7022 free(err);
7023 retval = 1;
7024 goto out;
7025 }
7026
7027 /* Extract Shader Code*/
7028 buffer_size = LLVMGetBufferSize(out_buffer);
7029 buffer_data = LLVMGetBufferStart(out_buffer);
7030
7031 ac_elf_read(buffer_data, buffer_size, binary);
7032
7033 /* Clean up */
7034 LLVMDisposeMemoryBuffer(out_buffer);
7035
7036 out:
7037 return retval;
7038 }
7039
7040 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7041 LLVMModuleRef llvm_module,
7042 struct ac_shader_binary *binary,
7043 struct ac_shader_config *config,
7044 struct ac_shader_variant_info *shader_info,
7045 gl_shader_stage stage,
7046 bool dump_shader, bool supports_spill)
7047 {
7048 if (dump_shader)
7049 ac_dump_module(llvm_module);
7050
7051 memset(binary, 0, sizeof(*binary));
7052 int v = ac_llvm_compile(llvm_module, binary, tm);
7053 if (v) {
7054 fprintf(stderr, "compile failed\n");
7055 }
7056
7057 if (dump_shader)
7058 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7059
7060 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7061
7062 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7063 LLVMDisposeModule(llvm_module);
7064 LLVMContextDispose(ctx);
7065
7066 if (stage == MESA_SHADER_FRAGMENT) {
7067 shader_info->num_input_vgprs = 0;
7068 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7069 shader_info->num_input_vgprs += 2;
7070 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7071 shader_info->num_input_vgprs += 2;
7072 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7073 shader_info->num_input_vgprs += 2;
7074 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7075 shader_info->num_input_vgprs += 3;
7076 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7077 shader_info->num_input_vgprs += 2;
7078 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7079 shader_info->num_input_vgprs += 2;
7080 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7081 shader_info->num_input_vgprs += 2;
7082 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7083 shader_info->num_input_vgprs += 1;
7084 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7085 shader_info->num_input_vgprs += 1;
7086 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7087 shader_info->num_input_vgprs += 1;
7088 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7089 shader_info->num_input_vgprs += 1;
7090 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7091 shader_info->num_input_vgprs += 1;
7092 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7093 shader_info->num_input_vgprs += 1;
7094 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7095 shader_info->num_input_vgprs += 1;
7096 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7097 shader_info->num_input_vgprs += 1;
7098 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7099 shader_info->num_input_vgprs += 1;
7100 }
7101 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7102
7103 /* +3 for scratch wave offset and VCC */
7104 config->num_sgprs = MAX2(config->num_sgprs,
7105 shader_info->num_input_sgprs + 3);
7106
7107 /* Enable 64-bit and 16-bit denormals, because there is no performance
7108 * cost.
7109 *
7110 * If denormals are enabled, all floating-point output modifiers are
7111 * ignored.
7112 *
7113 * Don't enable denormals for 32-bit floats, because:
7114 * - Floating-point output modifiers would be ignored by the hw.
7115 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7116 * have to stop using those.
7117 * - SI & CI would be very slow.
7118 */
7119 config->float_mode |= V_00B028_FP_64_DENORMS;
7120 }
7121
7122 static void
7123 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7124 {
7125 switch (nir->info.stage) {
7126 case MESA_SHADER_COMPUTE:
7127 for (int i = 0; i < 3; ++i)
7128 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7129 break;
7130 case MESA_SHADER_FRAGMENT:
7131 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7132 break;
7133 case MESA_SHADER_GEOMETRY:
7134 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7135 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7136 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7137 shader_info->gs.invocations = nir->info.gs.invocations;
7138 break;
7139 case MESA_SHADER_TESS_EVAL:
7140 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7141 shader_info->tes.spacing = nir->info.tess.spacing;
7142 shader_info->tes.ccw = nir->info.tess.ccw;
7143 shader_info->tes.point_mode = nir->info.tess.point_mode;
7144 shader_info->tes.as_es = options->key.tes.as_es;
7145 break;
7146 case MESA_SHADER_TESS_CTRL:
7147 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7148 break;
7149 case MESA_SHADER_VERTEX:
7150 shader_info->vs.as_es = options->key.vs.as_es;
7151 shader_info->vs.as_ls = options->key.vs.as_ls;
7152 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7153 if (options->key.vs.as_ls)
7154 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7155 break;
7156 default:
7157 break;
7158 }
7159 }
7160
7161 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7162 struct ac_shader_binary *binary,
7163 struct ac_shader_config *config,
7164 struct ac_shader_variant_info *shader_info,
7165 struct nir_shader *const *nir,
7166 int nir_count,
7167 const struct ac_nir_compiler_options *options,
7168 bool dump_shader)
7169 {
7170
7171 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7172 options);
7173
7174 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7175 for (int i = 0; i < nir_count; ++i)
7176 ac_fill_shader_info(shader_info, nir[i], options);
7177
7178 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7179 if (options->chip_class == GFX9) {
7180 if (nir_count == 2 &&
7181 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7182 shader_info->gs.es_type = nir[0]->info.stage;
7183 }
7184 }
7185 }
7186
7187 static void
7188 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7189 {
7190 LLVMValueRef vtx_offset =
7191 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7192 LLVMConstInt(ctx->ac.i32, 4, false), "");
7193 int idx = 0;
7194
7195 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7196 int length = 4;
7197 int slot = idx;
7198 int slot_inc = 1;
7199 if (!(ctx->output_mask & (1ull << i)))
7200 continue;
7201
7202 if (i == VARYING_SLOT_CLIP_DIST0) {
7203 /* unpack clip and cull from a single set of slots */
7204 length = ctx->num_output_clips + ctx->num_output_culls;
7205 if (length > 4)
7206 slot_inc = 2;
7207 }
7208
7209 for (unsigned j = 0; j < length; j++) {
7210 LLVMValueRef value, soffset;
7211
7212 soffset = LLVMConstInt(ctx->ac.i32,
7213 (slot * 4 + j) *
7214 ctx->gs_max_out_vertices * 16 * 4, false);
7215
7216 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7217 1, ctx->ac.i32_0,
7218 vtx_offset, soffset,
7219 0, 1, 1, true, false);
7220
7221 LLVMBuildStore(ctx->ac.builder,
7222 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7223 }
7224 idx += slot_inc;
7225 }
7226 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7227 }
7228
7229 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7230 struct nir_shader *geom_shader,
7231 struct ac_shader_binary *binary,
7232 struct ac_shader_config *config,
7233 struct ac_shader_variant_info *shader_info,
7234 const struct ac_nir_compiler_options *options,
7235 bool dump_shader)
7236 {
7237 struct radv_shader_context ctx = {0};
7238 ctx.context = LLVMContextCreate();
7239 ctx.options = options;
7240 ctx.shader_info = shader_info;
7241
7242 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7243 options->family);
7244 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7245
7246 ctx.is_gs_copy_shader = true;
7247 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7248
7249 enum ac_float_mode float_mode =
7250 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7251 AC_FLOAT_MODE_DEFAULT;
7252
7253 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7254 ctx.stage = MESA_SHADER_VERTEX;
7255
7256 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7257
7258 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7259 ac_setup_rings(&ctx);
7260
7261 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7262 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7263
7264 struct ac_nir_context nir_ctx = {};
7265 nir_ctx.ac = ctx.ac;
7266 nir_ctx.abi = &ctx.abi;
7267
7268 nir_foreach_variable(variable, &geom_shader->outputs) {
7269 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7270 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7271 }
7272
7273 ac_gs_copy_shader_emit(&ctx);
7274
7275 LLVMBuildRetVoid(ctx.ac.builder);
7276
7277 ac_llvm_finalize_module(&ctx);
7278
7279 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7280 MESA_SHADER_VERTEX,
7281 dump_shader, options->supports_spill);
7282 }