2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
38 enum radeon_llvm_calling_convention
{
39 RADEON_LLVM_AMDGPU_VS
= 87,
40 RADEON_LLVM_AMDGPU_GS
= 88,
41 RADEON_LLVM_AMDGPU_PS
= 89,
42 RADEON_LLVM_AMDGPU_CS
= 90,
43 RADEON_LLVM_AMDGPU_HS
= 93,
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 struct ac_nir_context
{
49 struct ac_llvm_context ac
;
50 struct ac_shader_abi
*abi
;
52 gl_shader_stage stage
;
54 struct hash_table
*defs
;
55 struct hash_table
*phis
;
56 struct hash_table
*vars
;
58 LLVMValueRef main_function
;
59 LLVMBasicBlockRef continue_block
;
60 LLVMBasicBlockRef break_block
;
66 struct radv_shader_context
{
67 struct ac_llvm_context ac
;
68 const struct ac_nir_compiler_options
*options
;
69 struct ac_shader_variant_info
*shader_info
;
70 struct ac_shader_abi abi
;
72 unsigned max_workgroup_size
;
73 LLVMContextRef context
;
74 LLVMValueRef main_function
;
76 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
77 LLVMValueRef ring_offsets
;
79 LLVMValueRef vertex_buffers
;
80 LLVMValueRef rel_auto_id
;
81 LLVMValueRef vs_prim_id
;
82 LLVMValueRef ls_out_layout
;
83 LLVMValueRef es2gs_offset
;
85 LLVMValueRef tcs_offchip_layout
;
86 LLVMValueRef tcs_out_offsets
;
87 LLVMValueRef tcs_out_layout
;
88 LLVMValueRef tcs_in_layout
;
90 LLVMValueRef merged_wave_info
;
91 LLVMValueRef tess_factor_offset
;
92 LLVMValueRef tes_rel_patch_id
;
96 LLVMValueRef gsvs_ring_stride
;
97 LLVMValueRef gsvs_num_entries
;
98 LLVMValueRef gs2vs_offset
;
99 LLVMValueRef gs_wave_id
;
100 LLVMValueRef gs_vtx_offset
[6];
102 LLVMValueRef esgs_ring
;
103 LLVMValueRef gsvs_ring
;
104 LLVMValueRef hs_ring_tess_offchip
;
105 LLVMValueRef hs_ring_tess_factor
;
107 LLVMValueRef sample_pos_offset
;
108 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
109 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
111 gl_shader_stage stage
;
113 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
116 uint64_t output_mask
;
117 uint8_t num_output_clips
;
118 uint8_t num_output_culls
;
120 bool is_gs_copy_shader
;
121 LLVMValueRef gs_next_vertex
;
122 unsigned gs_max_out_vertices
;
124 unsigned tes_primitive_mode
;
125 uint64_t tess_outputs_written
;
126 uint64_t tess_patch_outputs_written
;
128 uint32_t tcs_patch_outputs_read
;
129 uint64_t tcs_outputs_read
;
130 uint32_t tcs_vertices_per_patch
;
133 static inline struct radv_shader_context
*
134 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
136 struct radv_shader_context
*ctx
= NULL
;
137 return container_of(abi
, ctx
, abi
);
140 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
141 const nir_deref_var
*deref
,
142 enum ac_descriptor_type desc_type
,
143 const nir_tex_instr
*instr
,
144 bool image
, bool write
);
146 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
148 return (index
* 4) + chan
;
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
153 /* handle patch indices separate */
154 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
156 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
158 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
159 return 2 + (slot
- VARYING_SLOT_PATCH0
);
161 if (slot
== VARYING_SLOT_POS
)
163 if (slot
== VARYING_SLOT_PSIZ
)
165 if (slot
== VARYING_SLOT_CLIP_DIST0
)
167 /* 3 is reserved for clip dist as well */
168 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
169 return 4 + (slot
- VARYING_SLOT_VAR0
);
170 unreachable("illegal slot in get unique index\n");
173 static void set_llvm_calling_convention(LLVMValueRef func
,
174 gl_shader_stage stage
)
176 enum radeon_llvm_calling_convention calling_conv
;
179 case MESA_SHADER_VERTEX
:
180 case MESA_SHADER_TESS_EVAL
:
181 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
183 case MESA_SHADER_GEOMETRY
:
184 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
186 case MESA_SHADER_TESS_CTRL
:
187 calling_conv
= HAVE_LLVM
>= 0x0500 ? RADEON_LLVM_AMDGPU_HS
: RADEON_LLVM_AMDGPU_VS
;
189 case MESA_SHADER_FRAGMENT
:
190 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
192 case MESA_SHADER_COMPUTE
:
193 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
196 unreachable("Unhandle shader type");
199 LLVMSetFunctionCallConv(func
, calling_conv
);
204 LLVMTypeRef types
[MAX_ARGS
];
205 LLVMValueRef
*assign
[MAX_ARGS
];
206 unsigned array_params_mask
;
209 uint8_t num_sgprs_used
;
210 uint8_t num_vgprs_used
;
213 enum ac_arg_regfile
{
219 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
220 LLVMValueRef
*param_ptr
)
222 assert(info
->count
< MAX_ARGS
);
224 info
->assign
[info
->count
] = param_ptr
;
225 info
->types
[info
->count
] = type
;
228 if (regfile
== ARG_SGPR
) {
229 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
232 assert(regfile
== ARG_VGPR
);
233 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
238 add_array_arg(struct arg_info
*info
, LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
240 info
->array_params_mask
|= (1 << info
->count
);
241 add_arg(info
, ARG_SGPR
, type
, param_ptr
);
244 static void assign_arguments(LLVMValueRef main_function
,
245 struct arg_info
*info
)
248 for (i
= 0; i
< info
->count
; i
++) {
250 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
255 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
256 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
257 unsigned num_return_elems
,
258 struct arg_info
*args
,
259 unsigned max_workgroup_size
,
262 LLVMTypeRef main_function_type
, ret_type
;
263 LLVMBasicBlockRef main_function_body
;
265 if (num_return_elems
)
266 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
267 num_return_elems
, true);
269 ret_type
= LLVMVoidTypeInContext(ctx
);
271 /* Setup the function */
273 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
274 LLVMValueRef main_function
=
275 LLVMAddFunction(module
, "main", main_function_type
);
277 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
278 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
280 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
281 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
282 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
284 if (args
->array_params_mask
& (1 << i
)) {
285 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
286 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
287 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
291 if (max_workgroup_size
) {
292 ac_llvm_add_target_dep_function_attr(main_function
,
293 "amdgpu-max-work-group-size",
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function
,
299 "less-precise-fpmad",
301 LLVMAddTargetDependentFunctionAttr(main_function
,
304 LLVMAddTargetDependentFunctionAttr(main_function
,
307 LLVMAddTargetDependentFunctionAttr(main_function
,
310 LLVMAddTargetDependentFunctionAttr(main_function
,
311 "no-signed-zeros-fp-math",
314 return main_function
;
317 static LLVMValueRef
unpack_param(struct ac_llvm_context
*ctx
,
318 LLVMValueRef param
, unsigned rshift
,
321 LLVMValueRef value
= param
;
323 value
= LLVMBuildLShr(ctx
->builder
, value
,
324 LLVMConstInt(ctx
->i32
, rshift
, false), "");
326 if (rshift
+ bitwidth
< 32) {
327 unsigned mask
= (1 << bitwidth
) - 1;
328 value
= LLVMBuildAnd(ctx
->builder
, value
,
329 LLVMConstInt(ctx
->i32
, mask
, false), "");
334 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
336 switch (ctx
->stage
) {
337 case MESA_SHADER_TESS_CTRL
:
338 return unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
339 case MESA_SHADER_TESS_EVAL
:
340 return ctx
->tes_rel_patch_id
;
343 unreachable("Illegal stage");
347 /* Tessellation shaders pass outputs to the next shader using LDS.
349 * LS outputs = TCS inputs
350 * TCS outputs = TES inputs
353 * - TCS inputs for patch 0
354 * - TCS inputs for patch 1
355 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
357 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
358 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
359 * - TCS outputs for patch 1
360 * - Per-patch TCS outputs for patch 1
361 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
362 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
365 * All three shaders VS(LS), TCS, TES share the same LDS space.
368 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
370 if (ctx
->stage
== MESA_SHADER_VERTEX
)
371 return unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 0, 13);
372 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
373 return unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 0, 13);
381 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
383 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 0, 13);
387 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
389 return unpack_param(&ctx
->ac
, ctx
->tcs_out_layout
, 13, 8);
393 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
395 return LLVMBuildMul(ctx
->ac
.builder
,
396 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 0, 16),
397 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
401 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
403 return LLVMBuildMul(ctx
->ac
.builder
,
404 unpack_param(&ctx
->ac
, ctx
->tcs_out_offsets
, 16, 16),
405 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
409 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
411 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
412 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
414 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
418 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
420 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
421 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
422 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
424 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_offset
,
425 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
431 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
433 LLVMValueRef patch0_patch_data_offset
=
434 get_tcs_out_patch0_patch_data_offset(ctx
);
435 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
436 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
438 return LLVMBuildAdd(ctx
->ac
.builder
, patch0_patch_data_offset
,
439 LLVMBuildMul(ctx
->ac
.builder
, patch_stride
,
445 set_loc(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
,
446 uint32_t indirect_offset
)
448 ud_info
->sgpr_idx
= *sgpr_idx
;
449 ud_info
->num_sgprs
= num_sgprs
;
450 ud_info
->indirect
= indirect_offset
> 0;
451 ud_info
->indirect_offset
= indirect_offset
;
452 *sgpr_idx
+= num_sgprs
;
456 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
459 struct ac_userdata_info
*ud_info
=
460 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
463 set_loc(ud_info
, sgpr_idx
, num_sgprs
, 0);
467 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
468 uint32_t indirect_offset
)
470 struct ac_userdata_info
*ud_info
=
471 &ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[idx
];
474 set_loc(ud_info
, sgpr_idx
, 2, indirect_offset
);
477 struct user_sgpr_info
{
478 bool need_ring_offsets
;
480 bool indirect_all_descriptor_sets
;
483 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
484 gl_shader_stage stage
)
487 case MESA_SHADER_VERTEX
:
488 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
489 (!ctx
->options
->key
.vs
.as_es
&& !ctx
->options
->key
.vs
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
492 case MESA_SHADER_TESS_EVAL
:
493 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.tes
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
496 case MESA_SHADER_GEOMETRY
:
497 case MESA_SHADER_TESS_CTRL
:
498 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
508 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
512 count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
513 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
518 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
519 gl_shader_stage stage
,
520 bool has_previous_stage
,
521 gl_shader_stage previous_stage
,
522 bool needs_view_index
,
523 struct user_sgpr_info
*user_sgpr_info
)
525 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
527 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
528 if (stage
== MESA_SHADER_GEOMETRY
||
529 stage
== MESA_SHADER_VERTEX
||
530 stage
== MESA_SHADER_TESS_CTRL
||
531 stage
== MESA_SHADER_TESS_EVAL
||
532 ctx
->is_gs_copy_shader
)
533 user_sgpr_info
->need_ring_offsets
= true;
535 if (stage
== MESA_SHADER_FRAGMENT
&&
536 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
537 user_sgpr_info
->need_ring_offsets
= true;
539 /* 2 user sgprs will nearly always be allocated for scratch/rings */
540 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
541 user_sgpr_info
->sgpr_count
+= 2;
545 case MESA_SHADER_COMPUTE
:
546 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
547 user_sgpr_info
->sgpr_count
+= 3;
549 case MESA_SHADER_FRAGMENT
:
550 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
552 case MESA_SHADER_VERTEX
:
553 if (!ctx
->is_gs_copy_shader
)
554 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
555 if (ctx
->options
->key
.vs
.as_ls
)
556 user_sgpr_info
->sgpr_count
++;
558 case MESA_SHADER_TESS_CTRL
:
559 if (has_previous_stage
) {
560 if (previous_stage
== MESA_SHADER_VERTEX
)
561 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
562 user_sgpr_info
->sgpr_count
++;
564 user_sgpr_info
->sgpr_count
+= 4;
566 case MESA_SHADER_TESS_EVAL
:
567 user_sgpr_info
->sgpr_count
+= 1;
569 case MESA_SHADER_GEOMETRY
:
570 if (has_previous_stage
) {
571 if (previous_stage
== MESA_SHADER_VERTEX
) {
572 user_sgpr_info
->sgpr_count
+= count_vs_user_sgprs(ctx
);
574 user_sgpr_info
->sgpr_count
++;
577 user_sgpr_info
->sgpr_count
+= 2;
583 if (needs_view_index
)
584 user_sgpr_info
->sgpr_count
++;
586 if (ctx
->shader_info
->info
.loads_push_constants
)
587 user_sgpr_info
->sgpr_count
+= 2;
589 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
? 32 : 16;
590 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_info
->sgpr_count
;
592 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
593 user_sgpr_info
->sgpr_count
+= 2;
594 user_sgpr_info
->indirect_all_descriptor_sets
= true;
596 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
601 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
602 gl_shader_stage stage
,
603 bool has_previous_stage
,
604 gl_shader_stage previous_stage
,
605 const struct user_sgpr_info
*user_sgpr_info
,
606 struct arg_info
*args
,
607 LLVMValueRef
*desc_sets
)
609 LLVMTypeRef type
= ac_array_in_const_addr_space(ctx
->ac
.i8
);
610 unsigned num_sets
= ctx
->options
->layout
?
611 ctx
->options
->layout
->num_sets
: 0;
612 unsigned stage_mask
= 1 << stage
;
614 if (has_previous_stage
)
615 stage_mask
|= 1 << previous_stage
;
617 /* 1 for each descriptor set */
618 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
619 for (unsigned i
= 0; i
< num_sets
; ++i
) {
620 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
621 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
622 add_array_arg(args
, type
,
623 &ctx
->descriptor_sets
[i
]);
627 add_array_arg(args
, ac_array_in_const_addr_space(type
), desc_sets
);
630 if (ctx
->shader_info
->info
.loads_push_constants
) {
631 /* 1 for push constants and dynamic descriptors */
632 add_array_arg(args
, type
, &ctx
->abi
.push_constants
);
637 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
638 gl_shader_stage stage
,
639 bool has_previous_stage
,
640 gl_shader_stage previous_stage
,
641 struct arg_info
*args
)
643 if (!ctx
->is_gs_copy_shader
&&
644 (stage
== MESA_SHADER_VERTEX
||
645 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
646 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
647 add_arg(args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
648 &ctx
->vertex_buffers
);
650 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
651 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
652 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
653 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
659 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
661 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
662 if (!ctx
->is_gs_copy_shader
) {
663 if (ctx
->options
->key
.vs
.as_ls
) {
664 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
665 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
667 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
668 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
670 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
675 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
677 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
678 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
679 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
680 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
684 set_global_input_locs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
685 bool has_previous_stage
, gl_shader_stage previous_stage
,
686 const struct user_sgpr_info
*user_sgpr_info
,
687 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
689 unsigned num_sets
= ctx
->options
->layout
?
690 ctx
->options
->layout
->num_sets
: 0;
691 unsigned stage_mask
= 1 << stage
;
693 if (has_previous_stage
)
694 stage_mask
|= 1 << previous_stage
;
696 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
697 for (unsigned i
= 0; i
< num_sets
; ++i
) {
698 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
699 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
700 set_loc_desc(ctx
, i
, user_sgpr_idx
, 0);
702 ctx
->descriptor_sets
[i
] = NULL
;
705 set_loc_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
708 for (unsigned i
= 0; i
< num_sets
; ++i
) {
709 if ((ctx
->shader_info
->info
.desc_set_used_mask
& (1 << i
)) &&
710 ctx
->options
->layout
->set
[i
].layout
->shader_stages
& stage_mask
) {
711 set_loc_desc(ctx
, i
, user_sgpr_idx
, i
* 8);
712 ctx
->descriptor_sets
[i
] =
713 ac_build_load_to_sgpr(&ctx
->ac
,
715 LLVMConstInt(ctx
->ac
.i32
, i
, false));
718 ctx
->descriptor_sets
[i
] = NULL
;
720 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
723 if (ctx
->shader_info
->info
.loads_push_constants
) {
724 set_loc_shader(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
, 2);
729 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
730 gl_shader_stage stage
, bool has_previous_stage
,
731 gl_shader_stage previous_stage
,
732 uint8_t *user_sgpr_idx
)
734 if (!ctx
->is_gs_copy_shader
&&
735 (stage
== MESA_SHADER_VERTEX
||
736 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
737 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
738 set_loc_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
743 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
746 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
747 user_sgpr_idx
, vs_num
);
751 static void create_function(struct radv_shader_context
*ctx
,
752 gl_shader_stage stage
,
753 bool has_previous_stage
,
754 gl_shader_stage previous_stage
)
756 uint8_t user_sgpr_idx
;
757 struct user_sgpr_info user_sgpr_info
;
758 struct arg_info args
= {};
759 LLVMValueRef desc_sets
;
760 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
761 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
762 previous_stage
, needs_view_index
, &user_sgpr_info
);
764 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
765 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
770 case MESA_SHADER_COMPUTE
:
771 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
772 previous_stage
, &user_sgpr_info
,
775 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
776 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
777 &ctx
->abi
.num_work_groups
);
780 for (int i
= 0; i
< 3; i
++) {
781 ctx
->abi
.workgroup_ids
[i
] = NULL
;
782 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
783 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
784 &ctx
->abi
.workgroup_ids
[i
]);
788 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
789 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
790 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
791 &ctx
->abi
.local_invocation_ids
);
793 case MESA_SHADER_VERTEX
:
794 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
795 previous_stage
, &user_sgpr_info
,
797 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
798 previous_stage
, &args
);
800 if (needs_view_index
)
801 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
802 &ctx
->abi
.view_index
);
803 if (ctx
->options
->key
.vs
.as_es
)
804 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
806 else if (ctx
->options
->key
.vs
.as_ls
)
807 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
808 &ctx
->ls_out_layout
);
810 declare_vs_input_vgprs(ctx
, &args
);
812 case MESA_SHADER_TESS_CTRL
:
813 if (has_previous_stage
) {
814 // First 6 system regs
815 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
816 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
817 &ctx
->merged_wave_info
);
818 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
819 &ctx
->tess_factor_offset
);
821 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
822 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
823 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
825 declare_global_input_sgprs(ctx
, stage
,
828 &user_sgpr_info
, &args
,
830 declare_vs_specific_input_sgprs(ctx
, stage
,
832 previous_stage
, &args
);
834 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
835 &ctx
->ls_out_layout
);
837 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
838 &ctx
->tcs_offchip_layout
);
839 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
840 &ctx
->tcs_out_offsets
);
841 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
842 &ctx
->tcs_out_layout
);
843 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
844 &ctx
->tcs_in_layout
);
845 if (needs_view_index
)
846 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
847 &ctx
->abi
.view_index
);
849 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
850 &ctx
->abi
.tcs_patch_id
);
851 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
852 &ctx
->abi
.tcs_rel_ids
);
854 declare_vs_input_vgprs(ctx
, &args
);
856 declare_global_input_sgprs(ctx
, stage
,
859 &user_sgpr_info
, &args
,
862 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
863 &ctx
->tcs_offchip_layout
);
864 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
865 &ctx
->tcs_out_offsets
);
866 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
867 &ctx
->tcs_out_layout
);
868 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
869 &ctx
->tcs_in_layout
);
870 if (needs_view_index
)
871 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
872 &ctx
->abi
.view_index
);
874 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
875 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
876 &ctx
->tess_factor_offset
);
877 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
878 &ctx
->abi
.tcs_patch_id
);
879 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
880 &ctx
->abi
.tcs_rel_ids
);
883 case MESA_SHADER_TESS_EVAL
:
884 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
885 previous_stage
, &user_sgpr_info
,
888 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->tcs_offchip_layout
);
889 if (needs_view_index
)
890 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
891 &ctx
->abi
.view_index
);
893 if (ctx
->options
->key
.tes
.as_es
) {
894 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
895 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
896 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
899 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
900 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
902 declare_tes_input_vgprs(ctx
, &args
);
904 case MESA_SHADER_GEOMETRY
:
905 if (has_previous_stage
) {
906 // First 6 system regs
907 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
909 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
910 &ctx
->merged_wave_info
);
911 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
913 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
914 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
915 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
917 declare_global_input_sgprs(ctx
, stage
,
920 &user_sgpr_info
, &args
,
923 if (previous_stage
== MESA_SHADER_TESS_EVAL
) {
924 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
925 &ctx
->tcs_offchip_layout
);
927 declare_vs_specific_input_sgprs(ctx
, stage
,
933 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
934 &ctx
->gsvs_ring_stride
);
935 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
936 &ctx
->gsvs_num_entries
);
937 if (needs_view_index
)
938 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
939 &ctx
->abi
.view_index
);
941 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
942 &ctx
->gs_vtx_offset
[0]);
943 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
944 &ctx
->gs_vtx_offset
[2]);
945 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
946 &ctx
->abi
.gs_prim_id
);
947 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
948 &ctx
->abi
.gs_invocation_id
);
949 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
950 &ctx
->gs_vtx_offset
[4]);
952 if (previous_stage
== MESA_SHADER_VERTEX
) {
953 declare_vs_input_vgprs(ctx
, &args
);
955 declare_tes_input_vgprs(ctx
, &args
);
958 declare_global_input_sgprs(ctx
, stage
,
961 &user_sgpr_info
, &args
,
964 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
965 &ctx
->gsvs_ring_stride
);
966 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
967 &ctx
->gsvs_num_entries
);
968 if (needs_view_index
)
969 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
970 &ctx
->abi
.view_index
);
972 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
973 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
974 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
975 &ctx
->gs_vtx_offset
[0]);
976 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
977 &ctx
->gs_vtx_offset
[1]);
978 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
979 &ctx
->abi
.gs_prim_id
);
980 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
981 &ctx
->gs_vtx_offset
[2]);
982 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
983 &ctx
->gs_vtx_offset
[3]);
984 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
985 &ctx
->gs_vtx_offset
[4]);
986 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
987 &ctx
->gs_vtx_offset
[5]);
988 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
989 &ctx
->abi
.gs_invocation_id
);
992 case MESA_SHADER_FRAGMENT
:
993 declare_global_input_sgprs(ctx
, stage
, has_previous_stage
,
994 previous_stage
, &user_sgpr_info
,
997 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
998 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
999 &ctx
->sample_pos_offset
);
1001 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1002 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_sample
);
1003 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_center
);
1004 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->persp_centroid
);
1005 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1006 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_sample
);
1007 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_center
);
1008 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->linear_centroid
);
1009 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1010 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1011 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1012 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1013 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1014 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1015 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1016 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1017 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1020 unreachable("Shader stage not implemented");
1023 ctx
->main_function
= create_llvm_function(
1024 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1025 ctx
->max_workgroup_size
,
1026 ctx
->options
->unsafe_math
);
1027 set_llvm_calling_convention(ctx
->main_function
, stage
);
1030 ctx
->shader_info
->num_input_vgprs
= 0;
1031 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1033 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1035 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1036 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1038 assign_arguments(ctx
->main_function
, &args
);
1042 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1043 set_loc_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1045 if (ctx
->options
->supports_spill
) {
1046 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx
->ac
.i8
, AC_CONST_ADDR_SPACE
),
1048 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1049 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1050 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage
)
1059 set_global_input_locs(ctx
, stage
, has_previous_stage
, previous_stage
,
1060 &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1063 case MESA_SHADER_COMPUTE
:
1064 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1065 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1069 case MESA_SHADER_VERTEX
:
1070 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1071 previous_stage
, &user_sgpr_idx
);
1072 if (ctx
->abi
.view_index
)
1073 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1074 if (ctx
->options
->key
.vs
.as_ls
) {
1075 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1079 case MESA_SHADER_TESS_CTRL
:
1080 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1081 previous_stage
, &user_sgpr_idx
);
1082 if (has_previous_stage
)
1083 set_loc_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
,
1085 set_loc_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
1086 if (ctx
->abi
.view_index
)
1087 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1089 case MESA_SHADER_TESS_EVAL
:
1090 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
1091 if (ctx
->abi
.view_index
)
1092 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1094 case MESA_SHADER_GEOMETRY
:
1095 if (has_previous_stage
) {
1096 if (previous_stage
== MESA_SHADER_VERTEX
)
1097 set_vs_specific_input_locs(ctx
, stage
,
1102 set_loc_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
,
1105 set_loc_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
,
1107 if (ctx
->abi
.view_index
)
1108 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1110 case MESA_SHADER_FRAGMENT
:
1111 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
1112 set_loc_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
,
1117 unreachable("Shader stage not implemented");
1120 if (stage
== MESA_SHADER_TESS_CTRL
||
1121 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_ls
) ||
1122 /* GFX9 has the ESGS ring buffer in LDS. */
1123 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1124 ac_declare_lds_as_pointer(&ctx
->ac
);
1127 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1130 static LLVMValueRef
trim_vector(struct ac_llvm_context
*ctx
,
1131 LLVMValueRef value
, unsigned count
)
1133 unsigned num_components
= ac_get_llvm_num_components(value
);
1134 if (count
== num_components
)
1137 LLVMValueRef masks
[] = {
1138 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1139 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1142 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1145 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1146 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1150 build_store_values_extended(struct ac_llvm_context
*ac
,
1151 LLVMValueRef
*values
,
1152 unsigned value_count
,
1153 unsigned value_stride
,
1156 LLVMBuilderRef builder
= ac
->builder
;
1159 for (i
= 0; i
< value_count
; i
++) {
1160 LLVMValueRef ptr
= values
[i
* value_stride
];
1161 LLVMValueRef index
= LLVMConstInt(ac
->i32
, i
, false);
1162 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1163 LLVMBuildStore(builder
, value
, ptr
);
1167 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1168 const nir_ssa_def
*def
)
1170 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1171 if (def
->num_components
> 1) {
1172 type
= LLVMVectorType(type
, def
->num_components
);
1177 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1180 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1181 return (LLVMValueRef
)entry
->data
;
1185 get_memory_ptr(struct ac_nir_context
*ctx
, nir_src src
)
1187 LLVMValueRef ptr
= get_src(ctx
, src
);
1188 ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ac
.lds
, &ptr
, 1, "");
1189 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
1191 return LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1192 LLVMPointerType(ctx
->ac
.i32
, addr_space
), "");
1195 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1196 const struct nir_block
*b
)
1198 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1199 return (LLVMBasicBlockRef
)entry
->data
;
1202 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1204 unsigned num_components
)
1206 LLVMValueRef value
= get_src(ctx
, src
.src
);
1207 bool need_swizzle
= false;
1210 unsigned src_components
= ac_get_llvm_num_components(value
);
1211 for (unsigned i
= 0; i
< num_components
; ++i
) {
1212 assert(src
.swizzle
[i
] < src_components
);
1213 if (src
.swizzle
[i
] != i
)
1214 need_swizzle
= true;
1217 if (need_swizzle
|| num_components
!= src_components
) {
1218 LLVMValueRef masks
[] = {
1219 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1220 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1221 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1222 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1224 if (src_components
> 1 && num_components
== 1) {
1225 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1227 } else if (src_components
== 1 && num_components
> 1) {
1228 LLVMValueRef values
[] = {value
, value
, value
, value
};
1229 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1231 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1232 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1236 assert(!src
.negate
);
1241 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1242 LLVMIntPredicate pred
, LLVMValueRef src0
,
1245 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1246 return LLVMBuildSelect(ctx
->builder
, result
,
1247 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1251 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1252 LLVMRealPredicate pred
, LLVMValueRef src0
,
1255 LLVMValueRef result
;
1256 src0
= ac_to_float(ctx
, src0
);
1257 src1
= ac_to_float(ctx
, src1
);
1258 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1259 return LLVMBuildSelect(ctx
->builder
, result
,
1260 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1264 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1266 LLVMTypeRef result_type
,
1270 LLVMValueRef params
[] = {
1271 ac_to_float(ctx
, src0
),
1274 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1275 ac_get_elem_bits(ctx
, result_type
));
1276 assert(length
< sizeof(name
));
1277 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1280 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1282 LLVMTypeRef result_type
,
1283 LLVMValueRef src0
, LLVMValueRef src1
)
1286 LLVMValueRef params
[] = {
1287 ac_to_float(ctx
, src0
),
1288 ac_to_float(ctx
, src1
),
1291 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1292 ac_get_elem_bits(ctx
, result_type
));
1293 assert(length
< sizeof(name
));
1294 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1297 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1299 LLVMTypeRef result_type
,
1300 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1303 LLVMValueRef params
[] = {
1304 ac_to_float(ctx
, src0
),
1305 ac_to_float(ctx
, src1
),
1306 ac_to_float(ctx
, src2
),
1309 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1310 ac_get_elem_bits(ctx
, result_type
));
1311 assert(length
< sizeof(name
));
1312 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1315 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1316 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1318 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1320 return LLVMBuildSelect(ctx
->builder
, v
, ac_to_integer(ctx
, src1
),
1321 ac_to_integer(ctx
, src2
), "");
1324 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1325 LLVMIntPredicate pred
,
1326 LLVMValueRef src0
, LLVMValueRef src1
)
1328 return LLVMBuildSelect(ctx
->builder
,
1329 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1334 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1337 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1338 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1341 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1343 LLVMValueRef src0
, LLVMValueRef src1
)
1345 LLVMTypeRef ret_type
;
1346 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1348 LLVMValueRef params
[] = { src0
, src1
};
1349 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1352 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1353 params
, 2, AC_FUNC_ATTR_READNONE
);
1355 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1356 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1360 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1363 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1366 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1369 src0
= ac_to_float(ctx
, src0
);
1370 LLVMValueRef zero
= LLVMConstNull(LLVMTypeOf(src0
));
1371 return LLVMBuildSExt(ctx
->builder
,
1372 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, zero
, ""),
1376 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1380 LLVMValueRef result
= LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1385 return LLVMBuildZExt(ctx
->builder
, result
, ctx
->i64
, "");
1388 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1391 LLVMValueRef zero
= LLVMConstNull(LLVMTypeOf(src0
));
1392 return LLVMBuildSExt(ctx
->builder
,
1393 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, zero
, ""),
1397 static LLVMValueRef
emit_f2f16(struct ac_llvm_context
*ctx
,
1400 LLVMValueRef result
;
1401 LLVMValueRef cond
= NULL
;
1403 src0
= ac_to_float(ctx
, src0
);
1404 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->f16
, "");
1406 if (ctx
->chip_class
>= VI
) {
1407 LLVMValueRef args
[2];
1408 /* Check if the result is a denormal - and flush to 0 if so. */
1410 args
[1] = LLVMConstInt(ctx
->i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1411 cond
= ac_build_intrinsic(ctx
, "llvm.amdgcn.class.f16", ctx
->i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1414 /* need to convert back up to f32 */
1415 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->f32
, "");
1417 if (ctx
->chip_class
>= VI
)
1418 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->f32_0
, result
, "");
1421 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1422 * so compare the result and flush to 0 if it's smaller.
1424 LLVMValueRef temp
, cond2
;
1425 temp
= emit_intrin_1f_param(ctx
, "llvm.fabs", ctx
->f32
, result
);
1426 cond
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUGT
,
1427 LLVMBuildBitCast(ctx
->builder
, LLVMConstInt(ctx
->i32
, 0x38800000, false), ctx
->f32
, ""),
1429 cond2
= LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
,
1430 temp
, ctx
->f32_0
, "");
1431 cond
= LLVMBuildAnd(ctx
->builder
, cond
, cond2
, "");
1432 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->f32_0
, result
, "");
1437 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1438 LLVMValueRef src0
, LLVMValueRef src1
)
1440 LLVMValueRef dst64
, result
;
1441 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1442 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1444 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1445 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1446 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1450 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1451 LLVMValueRef src0
, LLVMValueRef src1
)
1453 LLVMValueRef dst64
, result
;
1454 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1455 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1457 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1458 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1459 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1463 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1465 const LLVMValueRef srcs
[3])
1467 LLVMValueRef result
;
1468 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1470 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1471 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1475 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1476 LLVMValueRef src0
, LLVMValueRef src1
,
1477 LLVMValueRef src2
, LLVMValueRef src3
)
1479 LLVMValueRef bfi_args
[3], result
;
1481 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1482 LLVMBuildSub(ctx
->builder
,
1483 LLVMBuildShl(ctx
->builder
,
1488 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1491 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1494 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1495 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1497 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1498 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1499 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1501 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1505 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1508 LLVMValueRef comp
[2];
1510 src0
= ac_to_float(ctx
, src0
);
1511 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1512 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1514 return ac_build_cvt_pkrtz_f16(ctx
, comp
);
1517 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1520 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1521 LLVMValueRef temps
[2], result
, val
;
1524 for (i
= 0; i
< 2; i
++) {
1525 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1526 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1527 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1528 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1531 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), temps
[0],
1533 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1538 static LLVMValueRef
emit_ddxy(struct ac_nir_context
*ctx
,
1544 LLVMValueRef result
;
1546 if (op
== nir_op_fddx_fine
)
1547 mask
= AC_TID_MASK_LEFT
;
1548 else if (op
== nir_op_fddy_fine
)
1549 mask
= AC_TID_MASK_TOP
;
1551 mask
= AC_TID_MASK_TOP_LEFT
;
1553 /* for DDX we want to next X pixel, DDY next Y pixel. */
1554 if (op
== nir_op_fddx_fine
||
1555 op
== nir_op_fddx_coarse
||
1561 result
= ac_build_ddxy(&ctx
->ac
, mask
, idx
, src0
);
1566 * this takes an I,J coordinate pair,
1567 * and works out the X and Y derivatives.
1568 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1570 static LLVMValueRef
emit_ddxy_interp(
1571 struct ac_nir_context
*ctx
,
1572 LLVMValueRef interp_ij
)
1574 LLVMValueRef result
[4], a
;
1577 for (i
= 0; i
< 2; i
++) {
1578 a
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_ij
,
1579 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
1580 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1581 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1583 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1586 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1588 LLVMValueRef src
[4], result
= NULL
;
1589 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1590 unsigned src_components
;
1591 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1593 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1594 switch (instr
->op
) {
1600 case nir_op_pack_half_2x16
:
1603 case nir_op_unpack_half_2x16
:
1607 src_components
= num_components
;
1610 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1611 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1613 switch (instr
->op
) {
1619 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1620 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1623 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1626 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1629 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1632 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1633 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1634 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1637 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1638 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1639 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1642 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1645 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1648 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1651 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1654 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1655 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1656 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1657 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1658 ac_to_float_type(&ctx
->ac
, def_type
), result
);
1659 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1660 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1663 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1664 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1665 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1668 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1671 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1674 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1677 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1678 src
[1] = ac_to_float(&ctx
->ac
, src
[1]);
1679 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1682 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1683 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1687 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1690 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1693 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1696 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1697 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1698 LLVMTypeOf(src
[0]), ""),
1702 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1703 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1704 LLVMTypeOf(src
[0]), ""),
1708 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1709 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1710 LLVMTypeOf(src
[0]), ""),
1714 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1717 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1720 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1723 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1726 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1729 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1732 result
= emit_float_cmp(&ctx
->ac
, LLVMRealOEQ
, src
[0], src
[1]);
1735 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1738 result
= emit_float_cmp(&ctx
->ac
, LLVMRealOLT
, src
[0], src
[1]);
1741 result
= emit_float_cmp(&ctx
->ac
, LLVMRealOGE
, src
[0], src
[1]);
1744 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1745 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1748 result
= emit_iabs(&ctx
->ac
, src
[0]);
1751 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1754 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1757 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1760 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1763 result
= ac_build_isign(&ctx
->ac
, src
[0],
1764 instr
->dest
.dest
.ssa
.bit_size
);
1767 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1768 result
= ac_build_fsign(&ctx
->ac
, src
[0],
1769 instr
->dest
.dest
.ssa
.bit_size
);
1772 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1773 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1776 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1777 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1780 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1781 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1783 case nir_op_fround_even
:
1784 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1785 ac_to_float_type(&ctx
->ac
, def_type
),src
[0]);
1788 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1789 result
= ac_build_fract(&ctx
->ac
, src
[0],
1790 instr
->dest
.dest
.ssa
.bit_size
);
1793 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1794 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1797 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1798 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1801 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1802 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1805 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1806 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1809 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1810 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1813 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1814 ac_to_float_type(&ctx
->ac
, def_type
), src
[0]);
1815 result
= ac_build_fdiv(&ctx
->ac
, instr
->dest
.dest
.ssa
.bit_size
== 32 ? ctx
->ac
.f32_1
: ctx
->ac
.f64_1
,
1819 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1820 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1821 if (ctx
->ac
.chip_class
< GFX9
&&
1822 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1823 /* Only pre-GFX9 chips do not flush denorms. */
1824 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1825 ac_to_float_type(&ctx
->ac
, def_type
),
1830 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1831 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1832 if (ctx
->ac
.chip_class
< GFX9
&&
1833 instr
->dest
.dest
.ssa
.bit_size
== 32) {
1834 /* Only pre-GFX9 chips do not flush denorms. */
1835 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1836 ac_to_float_type(&ctx
->ac
, def_type
),
1841 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fmuladd",
1842 ac_to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1845 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1846 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) == 32)
1847 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ldexp.f32", ctx
->ac
.f32
, src
, 2, AC_FUNC_ATTR_READNONE
);
1849 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ldexp.f64", ctx
->ac
.f64
, src
, 2, AC_FUNC_ATTR_READNONE
);
1851 case nir_op_ibitfield_extract
:
1852 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1854 case nir_op_ubitfield_extract
:
1855 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1857 case nir_op_bitfield_insert
:
1858 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1860 case nir_op_bitfield_reverse
:
1861 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1863 case nir_op_bit_count
:
1864 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) == 32)
1865 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1867 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i64", ctx
->ac
.i64
, src
, 1, AC_FUNC_ATTR_READNONE
);
1868 result
= LLVMBuildTrunc(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
1874 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1875 src
[i
] = ac_to_integer(&ctx
->ac
, src
[i
]);
1876 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1880 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1881 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1885 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1886 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1890 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1891 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1895 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1896 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1899 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1900 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1903 src
[0] = ac_to_float(&ctx
->ac
, src
[0]);
1904 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], ac_to_float_type(&ctx
->ac
, def_type
), "");
1908 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1909 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < ac_get_elem_bits(&ctx
->ac
, def_type
))
1910 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1912 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1916 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1917 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < ac_get_elem_bits(&ctx
->ac
, def_type
))
1918 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1920 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1923 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1925 case nir_op_find_lsb
:
1926 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1927 result
= ac_find_lsb(&ctx
->ac
, ctx
->ac
.i32
, src
[0]);
1929 case nir_op_ufind_msb
:
1930 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1931 result
= ac_build_umsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1933 case nir_op_ifind_msb
:
1934 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1935 result
= ac_build_imsb(&ctx
->ac
, src
[0], ctx
->ac
.i32
);
1937 case nir_op_uadd_carry
:
1938 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1939 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1940 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
1942 case nir_op_usub_borrow
:
1943 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1944 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1945 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
1948 result
= emit_b2f(&ctx
->ac
, src
[0]);
1951 result
= emit_f2b(&ctx
->ac
, src
[0]);
1954 result
= emit_b2i(&ctx
->ac
, src
[0], instr
->dest
.dest
.ssa
.bit_size
);
1957 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1958 result
= emit_i2b(&ctx
->ac
, src
[0]);
1960 case nir_op_fquantize2f16
:
1961 result
= emit_f2f16(&ctx
->ac
, src
[0]);
1963 case nir_op_umul_high
:
1964 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1965 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1966 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
1968 case nir_op_imul_high
:
1969 src
[0] = ac_to_integer(&ctx
->ac
, src
[0]);
1970 src
[1] = ac_to_integer(&ctx
->ac
, src
[1]);
1971 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
1973 case nir_op_pack_half_2x16
:
1974 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
1976 case nir_op_unpack_half_2x16
:
1977 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
1981 case nir_op_fddx_fine
:
1982 case nir_op_fddy_fine
:
1983 case nir_op_fddx_coarse
:
1984 case nir_op_fddy_coarse
:
1985 result
= emit_ddxy(ctx
, instr
->op
, src
[0]);
1988 case nir_op_unpack_64_2x32_split_x
: {
1989 assert(ac_get_llvm_num_components(src
[0]) == 1);
1990 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
1993 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
1998 case nir_op_unpack_64_2x32_split_y
: {
1999 assert(ac_get_llvm_num_components(src
[0]) == 1);
2000 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
2003 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
2008 case nir_op_pack_64_2x32_split
: {
2009 LLVMValueRef tmp
= LLVMGetUndef(ctx
->ac
.v2i32
);
2010 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2011 src
[0], ctx
->ac
.i32_0
, "");
2012 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
2013 src
[1], ctx
->ac
.i32_1
, "");
2014 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
2019 fprintf(stderr
, "Unknown NIR alu instr: ");
2020 nir_print_instr(&instr
->instr
, stderr
);
2021 fprintf(stderr
, "\n");
2026 assert(instr
->dest
.dest
.is_ssa
);
2027 result
= ac_to_integer(&ctx
->ac
, result
);
2028 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
2033 static void visit_load_const(struct ac_nir_context
*ctx
,
2034 const nir_load_const_instr
*instr
)
2036 LLVMValueRef values
[4], value
= NULL
;
2037 LLVMTypeRef element_type
=
2038 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
2040 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
2041 switch (instr
->def
.bit_size
) {
2043 values
[i
] = LLVMConstInt(element_type
,
2044 instr
->value
.u32
[i
], false);
2047 values
[i
] = LLVMConstInt(element_type
,
2048 instr
->value
.u64
[i
], false);
2052 "unsupported nir load_const bit_size: %d\n",
2053 instr
->def
.bit_size
);
2057 if (instr
->def
.num_components
> 1) {
2058 value
= LLVMConstVector(values
, instr
->def
.num_components
);
2062 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
2065 static LLVMValueRef
cast_ptr(struct ac_llvm_context
*ctx
, LLVMValueRef ptr
,
2068 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
2069 return LLVMBuildBitCast(ctx
->builder
, ptr
,
2070 LLVMPointerType(type
, addr_space
), "");
2074 get_buffer_size(struct ac_nir_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
2077 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2078 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2081 if (ctx
->ac
.chip_class
== VI
&& in_elements
) {
2082 /* On VI, the descriptor contains the size in bytes,
2083 * but TXQ must return the size in elements.
2084 * The stride is always non-zero for resources using TXQ.
2086 LLVMValueRef stride
=
2087 LLVMBuildExtractElement(ctx
->ac
.builder
, descriptor
,
2089 stride
= LLVMBuildLShr(ctx
->ac
.builder
, stride
,
2090 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
2091 stride
= LLVMBuildAnd(ctx
->ac
.builder
, stride
,
2092 LLVMConstInt(ctx
->ac
.i32
, 0x3fff, false), "");
2094 size
= LLVMBuildUDiv(ctx
->ac
.builder
, size
, stride
, "");
2100 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2103 static void build_int_type_name(
2105 char *buf
, unsigned bufsize
)
2107 assert(bufsize
>= 6);
2109 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2110 snprintf(buf
, bufsize
, "v%ui32",
2111 LLVMGetVectorSize(type
));
2116 static LLVMValueRef
radv_lower_gather4_integer(struct ac_llvm_context
*ctx
,
2117 struct ac_image_args
*args
,
2118 const nir_tex_instr
*instr
)
2120 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2121 LLVMValueRef coord
= args
->addr
;
2122 LLVMValueRef half_texel
[2];
2123 LLVMValueRef compare_cube_wa
= NULL
;
2124 LLVMValueRef result
;
2126 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2130 struct ac_image_args txq_args
= { 0 };
2132 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2133 txq_args
.opcode
= ac_image_get_resinfo
;
2134 txq_args
.dmask
= 0xf;
2135 txq_args
.addr
= ctx
->i32_0
;
2136 txq_args
.resource
= args
->resource
;
2137 LLVMValueRef size
= ac_build_image_opcode(ctx
, &txq_args
);
2139 for (c
= 0; c
< 2; c
++) {
2140 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2141 LLVMConstInt(ctx
->i32
, c
, false), "");
2142 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2143 half_texel
[c
] = ac_build_fdiv(ctx
, ctx
->f32_1
, half_texel
[c
]);
2144 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2145 LLVMConstReal(ctx
->f32
, -0.5), "");
2149 LLVMValueRef orig_coords
= args
->addr
;
2151 for (c
= 0; c
< 2; c
++) {
2153 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2154 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2155 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2156 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2157 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2158 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2163 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2164 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2165 * workaround by sampling using a scaled type and converting.
2166 * This is taken from amdgpu-pro shaders.
2168 /* NOTE this produces some ugly code compared to amdgpu-pro,
2169 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2170 * and then reads them back. -pro generates two selects,
2171 * one s_cmp for the descriptor rewriting
2172 * one v_cmp for the coordinate and result changes.
2174 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2175 LLVMValueRef tmp
, tmp2
;
2177 /* workaround 8/8/8/8 uint/sint cube gather bug */
2178 /* first detect it then change to a scaled read and f2i */
2179 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32_1
, "");
2182 /* extract the DATA_FORMAT */
2183 tmp
= ac_build_bfe(ctx
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2184 LLVMConstInt(ctx
->i32
, 6, false), false);
2186 /* is the DATA_FORMAT == 8_8_8_8 */
2187 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2189 if (stype
== GLSL_TYPE_UINT
)
2190 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2191 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2192 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2194 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2195 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2196 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2198 /* replace the NUM FORMAT in the descriptor */
2199 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2200 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2202 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32_1
, "");
2204 /* don't modify the coordinates for this case */
2205 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2208 result
= ac_build_image_opcode(ctx
, args
);
2210 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2211 LLVMValueRef tmp
, tmp2
;
2213 /* if the cube workaround is in place, f2i the result. */
2214 for (c
= 0; c
< 4; c
++) {
2215 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2216 if (stype
== GLSL_TYPE_UINT
)
2217 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2219 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2220 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2221 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2222 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2223 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2224 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2230 static LLVMValueRef
build_tex_intrinsic(struct ac_nir_context
*ctx
,
2231 const nir_tex_instr
*instr
,
2233 struct ac_image_args
*args
)
2235 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2236 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
2238 return ac_build_buffer_load_format(&ctx
->ac
,
2242 util_last_bit(mask
),
2246 args
->opcode
= ac_image_sample
;
2247 args
->compare
= instr
->is_shadow
;
2249 switch (instr
->op
) {
2251 case nir_texop_txf_ms
:
2252 case nir_texop_samples_identical
:
2253 args
->opcode
= lod_is_zero
||
2254 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
?
2255 ac_image_load
: ac_image_load_mip
;
2256 args
->compare
= false;
2257 args
->offset
= false;
2264 args
->level_zero
= true;
2269 case nir_texop_query_levels
:
2270 args
->opcode
= ac_image_get_resinfo
;
2273 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2274 args
->level_zero
= true;
2280 args
->opcode
= ac_image_gather4
;
2281 args
->level_zero
= true;
2284 args
->opcode
= ac_image_get_lod
;
2285 args
->compare
= false;
2286 args
->offset
= false;
2292 if (instr
->op
== nir_texop_tg4
&& ctx
->ac
.chip_class
<= VI
) {
2293 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2294 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2295 return radv_lower_gather4_integer(&ctx
->ac
, args
, instr
);
2298 return ac_build_image_opcode(&ctx
->ac
, args
);
2302 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
2303 unsigned desc_set
, unsigned binding
)
2305 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2306 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2307 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2308 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2309 unsigned base_offset
= layout
->binding
[binding
].offset
;
2310 LLVMValueRef offset
, stride
;
2312 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2313 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2314 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2315 layout
->binding
[binding
].dynamic_offset_offset
;
2316 desc_ptr
= ctx
->abi
.push_constants
;
2317 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2318 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2320 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
2322 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
2323 index
= LLVMBuildMul(ctx
->ac
.builder
, index
, stride
, "");
2324 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, index
, "");
2326 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2327 desc_ptr
= cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
2328 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2333 static LLVMValueRef
visit_vulkan_resource_reindex(struct ac_nir_context
*ctx
,
2334 nir_intrinsic_instr
*instr
)
2336 LLVMValueRef ptr
= get_src(ctx
, instr
->src
[0]);
2337 LLVMValueRef index
= get_src(ctx
, instr
->src
[1]);
2339 LLVMValueRef result
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
2340 LLVMSetMetadata(result
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2344 static LLVMValueRef
visit_load_push_constant(struct ac_nir_context
*ctx
,
2345 nir_intrinsic_instr
*instr
)
2347 LLVMValueRef ptr
, addr
;
2349 addr
= LLVMConstInt(ctx
->ac
.i32
, nir_intrinsic_base(instr
), 0);
2350 addr
= LLVMBuildAdd(ctx
->ac
.builder
, addr
,
2351 get_src(ctx
, instr
->src
[0]), "");
2353 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->abi
->push_constants
, addr
);
2354 ptr
= cast_ptr(&ctx
->ac
, ptr
, get_def_type(ctx
, &instr
->dest
.ssa
));
2356 return LLVMBuildLoad(ctx
->ac
.builder
, ptr
, "");
2359 static LLVMValueRef
visit_get_buffer_size(struct ac_nir_context
*ctx
,
2360 const nir_intrinsic_instr
*instr
)
2362 LLVMValueRef index
= get_src(ctx
, instr
->src
[0]);
2364 return get_buffer_size(ctx
, ctx
->abi
->load_ssbo(ctx
->abi
, index
, false), false);
2367 static uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2369 uint32_t new_mask
= 0;
2370 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2371 if (mask
& (1u << i
))
2372 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2376 static LLVMValueRef
extract_vector_range(struct ac_llvm_context
*ctx
, LLVMValueRef src
,
2377 unsigned start
, unsigned count
)
2379 LLVMTypeRef type
= LLVMTypeOf(src
);
2381 if (LLVMGetTypeKind(type
) != LLVMVectorTypeKind
) {
2387 unsigned src_elements
= LLVMGetVectorSize(type
);
2388 assert(start
< src_elements
);
2389 assert(start
+ count
<= src_elements
);
2391 if (start
== 0 && count
== src_elements
)
2395 return LLVMBuildExtractElement(ctx
->builder
, src
, LLVMConstInt(ctx
->i32
, start
, false), "");
2398 LLVMValueRef indices
[8];
2399 for (unsigned i
= 0; i
< count
; ++i
)
2400 indices
[i
] = LLVMConstInt(ctx
->i32
, start
+ i
, false);
2402 LLVMValueRef swizzle
= LLVMConstVector(indices
, count
);
2403 return LLVMBuildShuffleVector(ctx
->builder
, src
, src
, swizzle
, "");
2406 static void visit_store_ssbo(struct ac_nir_context
*ctx
,
2407 nir_intrinsic_instr
*instr
)
2409 const char *store_name
;
2410 LLVMValueRef src_data
= get_src(ctx
, instr
->src
[0]);
2411 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2412 int elem_size_mult
= ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2413 int components_32bit
= elem_size_mult
* instr
->num_components
;
2414 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2415 LLVMValueRef base_data
, base_offset
;
2416 LLVMValueRef params
[6];
2418 params
[1] = ctx
->abi
->load_ssbo(ctx
->abi
,
2419 get_src(ctx
, instr
->src
[1]), true);
2420 params
[2] = ctx
->ac
.i32_0
; /* vindex */
2421 params
[4] = ctx
->ac
.i1false
; /* glc */
2422 params
[5] = ctx
->ac
.i1false
; /* slc */
2424 if (components_32bit
> 1)
2425 data_type
= LLVMVectorType(ctx
->ac
.f32
, components_32bit
);
2427 writemask
= widen_mask(writemask
, elem_size_mult
);
2429 base_data
= ac_to_float(&ctx
->ac
, src_data
);
2430 base_data
= trim_vector(&ctx
->ac
, base_data
, instr
->num_components
);
2431 base_data
= LLVMBuildBitCast(ctx
->ac
.builder
, base_data
,
2433 base_offset
= get_src(ctx
, instr
->src
[2]); /* voffset */
2437 LLVMValueRef offset
;
2439 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2441 /* Due to an LLVM limitation, split 3-element writes
2442 * into a 2-element and a 1-element write. */
2444 writemask
|= 1 << (start
+ 2);
2449 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2454 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2455 } else if (count
== 2) {
2456 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2460 store_name
= "llvm.amdgcn.buffer.store.f32";
2462 data
= extract_vector_range(&ctx
->ac
, base_data
, start
, count
);
2464 offset
= base_offset
;
2466 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, LLVMConstInt(ctx
->ac
.i32
, start
* 4, false), "");
2470 ac_build_intrinsic(&ctx
->ac
, store_name
,
2471 ctx
->ac
.voidt
, params
, 6, 0);
2475 static LLVMValueRef
visit_atomic_ssbo(struct ac_nir_context
*ctx
,
2476 const nir_intrinsic_instr
*instr
)
2479 LLVMValueRef params
[6];
2482 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2483 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[3]), 0);
2485 params
[arg_count
++] = ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[2]), 0);
2486 params
[arg_count
++] = ctx
->abi
->load_ssbo(ctx
->abi
,
2487 get_src(ctx
, instr
->src
[0]),
2489 params
[arg_count
++] = ctx
->ac
.i32_0
; /* vindex */
2490 params
[arg_count
++] = get_src(ctx
, instr
->src
[1]); /* voffset */
2491 params
[arg_count
++] = LLVMConstInt(ctx
->ac
.i1
, 0, false); /* slc */
2493 switch (instr
->intrinsic
) {
2494 case nir_intrinsic_ssbo_atomic_add
:
2495 name
= "llvm.amdgcn.buffer.atomic.add";
2497 case nir_intrinsic_ssbo_atomic_imin
:
2498 name
= "llvm.amdgcn.buffer.atomic.smin";
2500 case nir_intrinsic_ssbo_atomic_umin
:
2501 name
= "llvm.amdgcn.buffer.atomic.umin";
2503 case nir_intrinsic_ssbo_atomic_imax
:
2504 name
= "llvm.amdgcn.buffer.atomic.smax";
2506 case nir_intrinsic_ssbo_atomic_umax
:
2507 name
= "llvm.amdgcn.buffer.atomic.umax";
2509 case nir_intrinsic_ssbo_atomic_and
:
2510 name
= "llvm.amdgcn.buffer.atomic.and";
2512 case nir_intrinsic_ssbo_atomic_or
:
2513 name
= "llvm.amdgcn.buffer.atomic.or";
2515 case nir_intrinsic_ssbo_atomic_xor
:
2516 name
= "llvm.amdgcn.buffer.atomic.xor";
2518 case nir_intrinsic_ssbo_atomic_exchange
:
2519 name
= "llvm.amdgcn.buffer.atomic.swap";
2521 case nir_intrinsic_ssbo_atomic_comp_swap
:
2522 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2528 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->ac
.i32
, params
, arg_count
, 0);
2531 static LLVMValueRef
visit_load_buffer(struct ac_nir_context
*ctx
,
2532 const nir_intrinsic_instr
*instr
)
2534 LLVMValueRef results
[2];
2535 int load_components
;
2536 int num_components
= instr
->num_components
;
2537 if (instr
->dest
.ssa
.bit_size
== 64)
2538 num_components
*= 2;
2540 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2541 load_components
= MIN2(num_components
- i
, 4);
2542 const char *load_name
;
2543 LLVMTypeRef data_type
= ctx
->ac
.f32
;
2544 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, i
* 4, false);
2545 offset
= LLVMBuildAdd(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[1]), offset
, "");
2547 if (load_components
== 3)
2548 data_type
= LLVMVectorType(ctx
->ac
.f32
, 4);
2549 else if (load_components
> 1)
2550 data_type
= LLVMVectorType(ctx
->ac
.f32
, load_components
);
2552 if (load_components
>= 3)
2553 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2554 else if (load_components
== 2)
2555 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2556 else if (load_components
== 1)
2557 load_name
= "llvm.amdgcn.buffer.load.f32";
2559 unreachable("unhandled number of components");
2561 LLVMValueRef params
[] = {
2562 ctx
->abi
->load_ssbo(ctx
->abi
,
2563 get_src(ctx
, instr
->src
[0]),
2571 results
[i
> 0 ? 1 : 0] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2575 LLVMValueRef ret
= results
[0];
2576 if (num_components
> 4 || num_components
== 3) {
2577 LLVMValueRef masks
[] = {
2578 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
2579 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
2580 LLVMConstInt(ctx
->ac
.i32
, 4, false), LLVMConstInt(ctx
->ac
.i32
, 5, false),
2581 LLVMConstInt(ctx
->ac
.i32
, 6, false), LLVMConstInt(ctx
->ac
.i32
, 7, false)
2584 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2585 ret
= LLVMBuildShuffleVector(ctx
->ac
.builder
, results
[0],
2586 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2589 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2590 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2593 static LLVMValueRef
visit_load_ubo_buffer(struct ac_nir_context
*ctx
,
2594 const nir_intrinsic_instr
*instr
)
2597 LLVMValueRef rsrc
= get_src(ctx
, instr
->src
[0]);
2598 LLVMValueRef offset
= get_src(ctx
, instr
->src
[1]);
2599 int num_components
= instr
->num_components
;
2601 if (ctx
->abi
->load_ubo
)
2602 rsrc
= ctx
->abi
->load_ubo(ctx
->abi
, rsrc
);
2604 if (instr
->dest
.ssa
.bit_size
== 64)
2605 num_components
*= 2;
2607 ret
= ac_build_buffer_load(&ctx
->ac
, rsrc
, num_components
, NULL
, offset
,
2608 NULL
, 0, false, false, true, true);
2609 ret
= trim_vector(&ctx
->ac
, ret
, num_components
);
2610 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
,
2611 get_def_type(ctx
, &instr
->dest
.ssa
), "");
2615 get_deref_offset(struct ac_nir_context
*ctx
, nir_deref_var
*deref
,
2616 bool vs_in
, unsigned *vertex_index_out
,
2617 LLVMValueRef
*vertex_index_ref
,
2618 unsigned *const_out
, LLVMValueRef
*indir_out
)
2620 unsigned const_offset
= 0;
2621 nir_deref
*tail
= &deref
->deref
;
2622 LLVMValueRef offset
= NULL
;
2624 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2626 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2627 if (vertex_index_out
)
2628 *vertex_index_out
= deref_array
->base_offset
;
2630 if (vertex_index_ref
) {
2631 LLVMValueRef vtx
= LLVMConstInt(ctx
->ac
.i32
, deref_array
->base_offset
, false);
2632 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2633 vtx
= LLVMBuildAdd(ctx
->ac
.builder
, vtx
, get_src(ctx
, deref_array
->indirect
), "");
2635 *vertex_index_ref
= vtx
;
2639 if (deref
->var
->data
.compact
) {
2640 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2641 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2642 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2643 /* We always lower indirect dereferences for "compact" array vars. */
2644 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2646 const_offset
= deref_array
->base_offset
;
2650 while (tail
->child
!= NULL
) {
2651 const struct glsl_type
*parent_type
= tail
->type
;
2654 if (tail
->deref_type
== nir_deref_type_array
) {
2655 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2656 LLVMValueRef index
, stride
, local_offset
;
2657 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2659 const_offset
+= size
* deref_array
->base_offset
;
2660 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2663 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2664 index
= get_src(ctx
, deref_array
->indirect
);
2665 stride
= LLVMConstInt(ctx
->ac
.i32
, size
, 0);
2666 local_offset
= LLVMBuildMul(ctx
->ac
.builder
, stride
, index
, "");
2669 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
, local_offset
, "");
2671 offset
= local_offset
;
2672 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2673 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2675 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2676 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2677 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2680 unreachable("unsupported deref type");
2684 if (const_offset
&& offset
)
2685 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2686 LLVMConstInt(ctx
->ac
.i32
, const_offset
, 0),
2689 *const_out
= const_offset
;
2690 *indir_out
= offset
;
2694 /* The offchip buffer layout for TCS->TES is
2696 * - attribute 0 of patch 0 vertex 0
2697 * - attribute 0 of patch 0 vertex 1
2698 * - attribute 0 of patch 0 vertex 2
2700 * - attribute 0 of patch 1 vertex 0
2701 * - attribute 0 of patch 1 vertex 1
2703 * - attribute 1 of patch 0 vertex 0
2704 * - attribute 1 of patch 0 vertex 1
2706 * - per patch attribute 0 of patch 0
2707 * - per patch attribute 0 of patch 1
2710 * Note that every attribute has 4 components.
2712 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
2713 LLVMValueRef vertex_index
,
2714 LLVMValueRef param_index
)
2716 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
;
2717 LLVMValueRef param_stride
, constant16
;
2718 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2720 vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
2721 num_patches
= unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 0, 9);
2723 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
2725 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
2726 vertices_per_patch
, "");
2728 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
2731 param_stride
= LLVMBuildMul(ctx
->ac
.builder
, vertices_per_patch
,
2734 base_addr
= rel_patch_id
;
2735 param_stride
= num_patches
;
2738 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
2739 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
2740 param_stride
, ""), "");
2742 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
2744 if (!vertex_index
) {
2745 LLVMValueRef patch_data_offset
=
2746 unpack_param(&ctx
->ac
, ctx
->tcs_offchip_layout
, 16, 16);
2748 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
2749 patch_data_offset
, "");
2754 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
2756 unsigned const_index
,
2758 LLVMValueRef vertex_index
,
2759 LLVMValueRef indir_index
)
2761 LLVMValueRef param_index
;
2764 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
2767 if (const_index
&& !is_compact
)
2768 param
+= const_index
;
2769 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
2771 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2775 mark_tess_output(struct radv_shader_context
*ctx
,
2776 bool is_patch
, uint32_t param
)
2780 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2782 ctx
->tess_outputs_written
|= (1ull << param
);
2786 get_dw_address(struct radv_shader_context
*ctx
,
2787 LLVMValueRef dw_addr
,
2789 unsigned const_index
,
2790 bool compact_const_index
,
2791 LLVMValueRef vertex_index
,
2792 LLVMValueRef stride
,
2793 LLVMValueRef indir_index
)
2798 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2799 LLVMBuildMul(ctx
->ac
.builder
,
2805 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2806 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
2807 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
2808 else if (const_index
&& !compact_const_index
)
2809 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2810 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2812 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2813 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
2815 if (const_index
&& compact_const_index
)
2816 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2817 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
2822 load_tcs_varyings(struct ac_shader_abi
*abi
,
2824 LLVMValueRef vertex_index
,
2825 LLVMValueRef indir_index
,
2826 unsigned const_index
,
2828 unsigned driver_location
,
2830 unsigned num_components
,
2835 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2836 LLVMValueRef dw_addr
, stride
;
2837 LLVMValueRef value
[4], result
;
2838 unsigned param
= shader_io_get_unique_index(location
);
2841 stride
= unpack_param(&ctx
->ac
, ctx
->tcs_in_layout
, 13, 8);
2842 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2845 stride
= get_tcs_out_vertex_stride(ctx
);
2846 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2848 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2853 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2856 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
2857 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
2858 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2861 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
2866 store_tcs_output(struct ac_shader_abi
*abi
,
2867 LLVMValueRef vertex_index
,
2868 LLVMValueRef param_index
,
2869 unsigned const_index
,
2871 unsigned driver_location
,
2878 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2879 LLVMValueRef dw_addr
;
2880 LLVMValueRef stride
= NULL
;
2881 LLVMValueRef buf_addr
= NULL
;
2883 bool store_lds
= true;
2886 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
2889 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
2893 param
= shader_io_get_unique_index(location
);
2894 if (location
== VARYING_SLOT_CLIP_DIST0
&&
2895 is_compact
&& const_index
> 3) {
2901 stride
= get_tcs_out_vertex_stride(ctx
);
2902 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2904 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2907 mark_tess_output(ctx
, is_patch
, param
);
2909 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2911 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2912 vertex_index
, param_index
);
2914 bool is_tess_factor
= false;
2915 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2916 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2917 is_tess_factor
= true;
2919 unsigned base
= is_compact
? const_index
: 0;
2920 for (unsigned chan
= 0; chan
< 8; chan
++) {
2921 if (!(writemask
& (1 << chan
)))
2923 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
2925 if (store_lds
|| is_tess_factor
) {
2926 LLVMValueRef dw_addr_chan
=
2927 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2928 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
2929 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
2932 if (!is_tess_factor
&& writemask
!= 0xF)
2933 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
2934 buf_addr
, ctx
->oc_lds
,
2935 4 * (base
+ chan
), 1, 0, true, false);
2938 if (writemask
== 0xF) {
2939 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
2940 buf_addr
, ctx
->oc_lds
,
2941 (base
* 4), 1, 0, true, false);
2946 load_tes_input(struct ac_shader_abi
*abi
,
2948 LLVMValueRef vertex_index
,
2949 LLVMValueRef param_index
,
2950 unsigned const_index
,
2952 unsigned driver_location
,
2954 unsigned num_components
,
2959 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2960 LLVMValueRef buf_addr
;
2961 LLVMValueRef result
;
2962 unsigned param
= shader_io_get_unique_index(location
);
2964 if (location
== VARYING_SLOT_CLIP_DIST0
&& is_compact
&& const_index
> 3) {
2969 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
2970 is_compact
, vertex_index
, param_index
);
2972 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
2973 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
2975 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
2976 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
2977 result
= trim_vector(&ctx
->ac
, result
, num_components
);
2982 load_gs_input(struct ac_shader_abi
*abi
,
2984 unsigned driver_location
,
2986 unsigned num_components
,
2987 unsigned vertex_index
,
2988 unsigned const_index
,
2991 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2992 LLVMValueRef vtx_offset
;
2993 unsigned param
, vtx_offset_param
;
2994 LLVMValueRef value
[4], result
;
2996 vtx_offset_param
= vertex_index
;
2997 assert(vtx_offset_param
< 6);
2998 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
2999 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3001 param
= shader_io_get_unique_index(location
);
3003 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
3004 if (ctx
->ac
.chip_class
>= GFX9
) {
3005 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
3006 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3007 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
3008 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
3010 LLVMValueRef soffset
=
3011 LLVMConstInt(ctx
->ac
.i32
,
3012 (param
* 4 + i
+ const_index
) * 256,
3015 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
3018 vtx_offset
, soffset
,
3019 0, 1, 0, true, false);
3021 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
],
3025 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
3026 result
= ac_to_integer(&ctx
->ac
, result
);
3031 build_gep_for_deref(struct ac_nir_context
*ctx
,
3032 nir_deref_var
*deref
)
3034 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
3035 assert(entry
->data
);
3036 LLVMValueRef val
= entry
->data
;
3037 nir_deref
*tail
= deref
->deref
.child
;
3038 while (tail
!= NULL
) {
3039 LLVMValueRef offset
;
3040 switch (tail
->deref_type
) {
3041 case nir_deref_type_array
: {
3042 nir_deref_array
*array
= nir_deref_as_array(tail
);
3043 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
3044 if (array
->deref_array_type
==
3045 nir_deref_array_type_indirect
) {
3046 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
3053 case nir_deref_type_struct
: {
3054 nir_deref_struct
*deref_struct
=
3055 nir_deref_as_struct(tail
);
3056 offset
= LLVMConstInt(ctx
->ac
.i32
,
3057 deref_struct
->index
, 0);
3061 unreachable("bad deref type");
3063 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
3069 static LLVMValueRef
load_tess_varyings(struct ac_nir_context
*ctx
,
3070 nir_intrinsic_instr
*instr
,
3073 LLVMValueRef result
;
3074 LLVMValueRef vertex_index
= NULL
;
3075 LLVMValueRef indir_index
= NULL
;
3076 unsigned const_index
= 0;
3077 unsigned location
= instr
->variables
[0]->var
->data
.location
;
3078 unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3079 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3080 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3082 get_deref_offset(ctx
, instr
->variables
[0],
3083 false, NULL
, is_patch
? NULL
: &vertex_index
,
3084 &const_index
, &indir_index
);
3086 LLVMTypeRef dest_type
= get_def_type(ctx
, &instr
->dest
.ssa
);
3088 LLVMTypeRef src_component_type
;
3089 if (LLVMGetTypeKind(dest_type
) == LLVMVectorTypeKind
)
3090 src_component_type
= LLVMGetElementType(dest_type
);
3092 src_component_type
= dest_type
;
3094 result
= ctx
->abi
->load_tess_varyings(ctx
->abi
, src_component_type
,
3095 vertex_index
, indir_index
,
3096 const_index
, location
, driver_location
,
3097 instr
->variables
[0]->var
->data
.location_frac
,
3098 instr
->num_components
,
3099 is_patch
, is_compact
, load_inputs
);
3100 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, dest_type
, "");
3103 static LLVMValueRef
visit_load_var(struct ac_nir_context
*ctx
,
3104 nir_intrinsic_instr
*instr
)
3106 LLVMValueRef values
[8];
3107 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3108 int ve
= instr
->dest
.ssa
.num_components
;
3109 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3110 LLVMValueRef indir_index
;
3112 unsigned const_index
;
3113 unsigned stride
= instr
->variables
[0]->var
->data
.compact
? 1 : 4;
3114 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
3115 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
3116 get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
3117 &const_index
, &indir_index
);
3119 if (instr
->dest
.ssa
.bit_size
== 64)
3122 switch (instr
->variables
[0]->var
->data
.mode
) {
3123 case nir_var_shader_in
:
3124 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3125 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3126 return load_tess_varyings(ctx
, instr
, true);
3129 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3130 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->dest
.ssa
.bit_size
);
3131 LLVMValueRef indir_index
;
3132 unsigned const_index
, vertex_index
;
3133 get_deref_offset(ctx
, instr
->variables
[0],
3134 false, &vertex_index
, NULL
,
3135 &const_index
, &indir_index
);
3137 return ctx
->abi
->load_inputs(ctx
->abi
, instr
->variables
[0]->var
->data
.location
,
3138 instr
->variables
[0]->var
->data
.driver_location
,
3139 instr
->variables
[0]->var
->data
.location_frac
,
3140 instr
->num_components
, vertex_index
, const_index
, type
);
3143 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3145 unsigned count
= glsl_count_attribute_slots(
3146 instr
->variables
[0]->var
->type
,
3147 ctx
->stage
== MESA_SHADER_VERTEX
);
3149 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3150 &ctx
->ac
, ctx
->abi
->inputs
+ idx
+ chan
, count
,
3151 stride
, false, true);
3153 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3157 values
[chan
] = ctx
->abi
->inputs
[idx
+ chan
+ const_index
* stride
];
3161 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3163 unsigned count
= glsl_count_attribute_slots(
3164 instr
->variables
[0]->var
->type
, false);
3166 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3167 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3168 stride
, true, true);
3170 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3174 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, ctx
->locals
[idx
+ chan
+ const_index
* stride
], "");
3178 case nir_var_shared
: {
3179 LLVMValueRef address
= build_gep_for_deref(ctx
,
3180 instr
->variables
[0]);
3181 LLVMValueRef val
= LLVMBuildLoad(ctx
->ac
.builder
, address
, "");
3182 return LLVMBuildBitCast(ctx
->ac
.builder
, val
,
3183 get_def_type(ctx
, &instr
->dest
.ssa
),
3186 case nir_var_shader_out
:
3187 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3188 return load_tess_varyings(ctx
, instr
, false);
3191 for (unsigned chan
= comp
; chan
< ve
+ comp
; chan
++) {
3193 unsigned count
= glsl_count_attribute_slots(
3194 instr
->variables
[0]->var
->type
, false);
3196 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3197 &ctx
->ac
, ctx
->abi
->outputs
+ idx
+ chan
, count
,
3198 stride
, true, true);
3200 values
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
,
3204 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
,
3205 ctx
->abi
->outputs
[idx
+ chan
+ const_index
* stride
],
3211 unreachable("unhandle variable mode");
3213 ret
= ac_build_varying_gather_values(&ctx
->ac
, values
, ve
, comp
);
3214 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3218 visit_store_var(struct ac_nir_context
*ctx
,
3219 nir_intrinsic_instr
*instr
)
3221 LLVMValueRef temp_ptr
, value
;
3222 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3223 unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3224 LLVMValueRef src
= ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
3225 int writemask
= instr
->const_index
[0] << comp
;
3226 LLVMValueRef indir_index
;
3227 unsigned const_index
;
3228 get_deref_offset(ctx
, instr
->variables
[0], false,
3229 NULL
, NULL
, &const_index
, &indir_index
);
3231 if (ac_get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3233 src
= LLVMBuildBitCast(ctx
->ac
.builder
, src
,
3234 LLVMVectorType(ctx
->ac
.f32
, ac_get_llvm_num_components(src
) * 2),
3237 writemask
= widen_mask(writemask
, 2);
3240 switch (instr
->variables
[0]->var
->data
.mode
) {
3241 case nir_var_shader_out
:
3243 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3244 LLVMValueRef vertex_index
= NULL
;
3245 LLVMValueRef indir_index
= NULL
;
3246 unsigned const_index
= 0;
3247 const unsigned location
= instr
->variables
[0]->var
->data
.location
;
3248 const unsigned driver_location
= instr
->variables
[0]->var
->data
.driver_location
;
3249 const unsigned comp
= instr
->variables
[0]->var
->data
.location_frac
;
3250 const bool is_patch
= instr
->variables
[0]->var
->data
.patch
;
3251 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
3253 get_deref_offset(ctx
, instr
->variables
[0],
3254 false, NULL
, is_patch
? NULL
: &vertex_index
,
3255 &const_index
, &indir_index
);
3257 ctx
->abi
->store_tcs_outputs(ctx
->abi
, vertex_index
, indir_index
,
3258 const_index
, location
, driver_location
,
3259 src
, comp
, is_patch
, is_compact
, writemask
);
3263 for (unsigned chan
= 0; chan
< 8; chan
++) {
3265 if (!(writemask
& (1 << chan
)))
3268 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- comp
);
3270 if (instr
->variables
[0]->var
->data
.compact
)
3273 unsigned count
= glsl_count_attribute_slots(
3274 instr
->variables
[0]->var
->type
, false);
3276 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3277 &ctx
->ac
, ctx
->abi
->outputs
+ idx
+ chan
, count
,
3278 stride
, true, true);
3280 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3281 value
, indir_index
, "");
3282 build_store_values_extended(&ctx
->ac
, ctx
->abi
->outputs
+ idx
+ chan
,
3283 count
, stride
, tmp_vec
);
3286 temp_ptr
= ctx
->abi
->outputs
[idx
+ chan
+ const_index
* stride
];
3288 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3293 for (unsigned chan
= 0; chan
< 8; chan
++) {
3294 if (!(writemask
& (1 << chan
)))
3297 value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3299 unsigned count
= glsl_count_attribute_slots(
3300 instr
->variables
[0]->var
->type
, false);
3302 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3303 &ctx
->ac
, ctx
->locals
+ idx
+ chan
, count
,
3306 tmp_vec
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp_vec
,
3307 value
, indir_index
, "");
3308 build_store_values_extended(&ctx
->ac
, ctx
->locals
+ idx
+ chan
,
3311 temp_ptr
= ctx
->locals
[idx
+ chan
+ const_index
* 4];
3313 LLVMBuildStore(ctx
->ac
.builder
, value
, temp_ptr
);
3317 case nir_var_shared
: {
3318 int writemask
= instr
->const_index
[0];
3319 LLVMValueRef address
= build_gep_for_deref(ctx
,
3320 instr
->variables
[0]);
3321 LLVMValueRef val
= get_src(ctx
, instr
->src
[0]);
3322 unsigned components
=
3323 glsl_get_vector_elements(
3324 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3325 if (writemask
== (1 << components
) - 1) {
3326 val
= LLVMBuildBitCast(
3327 ctx
->ac
.builder
, val
,
3328 LLVMGetElementType(LLVMTypeOf(address
)), "");
3329 LLVMBuildStore(ctx
->ac
.builder
, val
, address
);
3331 for (unsigned chan
= 0; chan
< 4; chan
++) {
3332 if (!(writemask
& (1 << chan
)))
3335 LLVMBuildStructGEP(ctx
->ac
.builder
,
3337 LLVMValueRef src
= ac_llvm_extract_elem(&ctx
->ac
, val
,
3339 src
= LLVMBuildBitCast(
3340 ctx
->ac
.builder
, src
,
3341 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3342 LLVMBuildStore(ctx
->ac
.builder
, src
, ptr
);
3352 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3355 case GLSL_SAMPLER_DIM_BUF
:
3357 case GLSL_SAMPLER_DIM_1D
:
3358 return array
? 2 : 1;
3359 case GLSL_SAMPLER_DIM_2D
:
3360 return array
? 3 : 2;
3361 case GLSL_SAMPLER_DIM_MS
:
3362 return array
? 4 : 3;
3363 case GLSL_SAMPLER_DIM_3D
:
3364 case GLSL_SAMPLER_DIM_CUBE
:
3366 case GLSL_SAMPLER_DIM_RECT
:
3367 case GLSL_SAMPLER_DIM_SUBPASS
:
3369 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3378 glsl_is_array_image(const struct glsl_type
*type
)
3380 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3382 if (glsl_sampler_type_is_array(type
))
3385 return dim
== GLSL_SAMPLER_DIM_CUBE
||
3386 dim
== GLSL_SAMPLER_DIM_3D
||
3387 dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3388 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
;
3392 /* Adjust the sample index according to FMASK.
3394 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3395 * which is the identity mapping. Each nibble says which physical sample
3396 * should be fetched to get that sample.
3398 * For example, 0x11111100 means there are only 2 samples stored and
3399 * the second sample covers 3/4 of the pixel. When reading samples 0
3400 * and 1, return physical sample 0 (determined by the first two 0s
3401 * in FMASK), otherwise return physical sample 1.
3403 * The sample index should be adjusted as follows:
3404 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3406 static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context
*ctx
,
3407 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3408 LLVMValueRef coord_z
,
3409 LLVMValueRef sample_index
,
3410 LLVMValueRef fmask_desc_ptr
)
3412 LLVMValueRef fmask_load_address
[4];
3415 fmask_load_address
[0] = coord_x
;
3416 fmask_load_address
[1] = coord_y
;
3418 fmask_load_address
[2] = coord_z
;
3419 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3422 struct ac_image_args args
= {0};
3424 args
.opcode
= ac_image_load
;
3425 args
.da
= coord_z
? true : false;
3426 args
.resource
= fmask_desc_ptr
;
3428 args
.addr
= ac_build_gather_values(ctx
, fmask_load_address
, coord_z
? 4 : 2);
3430 res
= ac_build_image_opcode(ctx
, &args
);
3432 res
= ac_to_integer(ctx
, res
);
3433 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3434 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3436 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3440 LLVMValueRef sample_index4
=
3441 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3442 LLVMValueRef shifted_fmask
=
3443 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3444 LLVMValueRef final_sample
=
3445 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3447 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3448 * resource descriptor is 0 (invalid),
3450 LLVMValueRef fmask_desc
=
3451 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3454 LLVMValueRef fmask_word1
=
3455 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3458 LLVMValueRef word1_is_nonzero
=
3459 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3460 fmask_word1
, ctx
->i32_0
, "");
3462 /* Replace the MSAA sample index. */
3464 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3465 final_sample
, sample_index
, "");
3466 return sample_index
;
3469 static LLVMValueRef
get_image_coords(struct ac_nir_context
*ctx
,
3470 const nir_intrinsic_instr
*instr
)
3472 const struct glsl_type
*type
= glsl_without_array(instr
->variables
[0]->var
->type
);
3474 LLVMValueRef src0
= get_src(ctx
, instr
->src
[0]);
3475 LLVMValueRef coords
[4];
3476 LLVMValueRef masks
[] = {
3477 LLVMConstInt(ctx
->ac
.i32
, 0, false), LLVMConstInt(ctx
->ac
.i32
, 1, false),
3478 LLVMConstInt(ctx
->ac
.i32
, 2, false), LLVMConstInt(ctx
->ac
.i32
, 3, false),
3481 LLVMValueRef sample_index
= ac_llvm_extract_elem(&ctx
->ac
, get_src(ctx
, instr
->src
[1]), 0);
3484 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3485 bool is_array
= glsl_sampler_type_is_array(type
);
3486 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3487 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3488 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3489 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3490 bool gfx9_1d
= ctx
->ac
.chip_class
>= GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3491 count
= image_type_to_components_count(dim
, is_array
);
3494 LLVMValueRef fmask_load_address
[3];
3497 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3498 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[1], "");
3500 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[2], "");
3502 fmask_load_address
[2] = NULL
;
3504 for (chan
= 0; chan
< 2; ++chan
)
3505 fmask_load_address
[chan
] =
3506 LLVMBuildAdd(ctx
->ac
.builder
, fmask_load_address
[chan
],
3507 LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3508 ctx
->ac
.i32
, ""), "");
3509 fmask_load_address
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3511 sample_index
= adjust_sample_index_using_fmask(&ctx
->ac
,
3512 fmask_load_address
[0],
3513 fmask_load_address
[1],
3514 fmask_load_address
[2],
3516 get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_FMASK
, NULL
, true, false));
3518 if (count
== 1 && !gfx9_1d
) {
3519 if (instr
->src
[0].ssa
->num_components
)
3520 res
= LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, masks
[0], "");
3527 for (chan
= 0; chan
< count
; ++chan
) {
3528 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, src0
, chan
);
3531 for (chan
= 0; chan
< 2; ++chan
)
3532 coords
[chan
] = LLVMBuildAdd(ctx
->ac
.builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->ac
.builder
, ctx
->abi
->frag_pos
[chan
],
3533 ctx
->ac
.i32
, ""), "");
3534 coords
[2] = ac_to_integer(&ctx
->ac
, ctx
->abi
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)]);
3540 coords
[2] = coords
[1];
3541 coords
[1] = ctx
->ac
.i32_0
;
3543 coords
[1] = ctx
->ac
.i32_0
;
3548 coords
[count
] = sample_index
;
3553 coords
[3] = LLVMGetUndef(ctx
->ac
.i32
);
3556 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3561 static LLVMValueRef
visit_image_load(struct ac_nir_context
*ctx
,
3562 const nir_intrinsic_instr
*instr
)
3564 LLVMValueRef params
[7];
3566 char intrinsic_name
[64];
3567 const nir_variable
*var
= instr
->variables
[0]->var
;
3568 const struct glsl_type
*type
= var
->type
;
3570 if(instr
->variables
[0]->deref
.child
)
3571 type
= instr
->variables
[0]->deref
.child
->type
;
3573 type
= glsl_without_array(type
);
3575 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3576 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3577 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
3578 unsigned num_channels
= util_last_bit(mask
);
3579 LLVMValueRef rsrc
, vindex
;
3581 rsrc
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, false);
3582 vindex
= LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3585 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3586 res
= ac_build_buffer_load_format(&ctx
->ac
, rsrc
, vindex
,
3587 ctx
->ac
.i32_0
, num_channels
,
3589 res
= ac_build_expand_to_vec4(&ctx
->ac
, res
, num_channels
);
3591 res
= trim_vector(&ctx
->ac
, res
, instr
->dest
.ssa
.num_components
);
3592 res
= ac_to_integer(&ctx
->ac
, res
);
3594 LLVMValueRef da
= glsl_is_array_image(type
) ? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3595 LLVMValueRef slc
= ctx
->ac
.i1false
;
3597 params
[0] = get_image_coords(ctx
, instr
);
3598 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3599 params
[2] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3600 params
[3] = (var
->data
.image
._volatile
|| var
->data
.image
.coherent
) ?
3601 ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3603 params
[5] = ctx
->ac
.i1false
;
3606 ac_get_image_intr_name("llvm.amdgcn.image.load",
3607 ctx
->ac
.v4f32
, /* vdata */
3608 LLVMTypeOf(params
[0]), /* coords */
3609 LLVMTypeOf(params
[1]), /* rsrc */
3610 intrinsic_name
, sizeof(intrinsic_name
));
3612 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.v4f32
,
3613 params
, 7, AC_FUNC_ATTR_READONLY
);
3615 return ac_to_integer(&ctx
->ac
, res
);
3618 static void visit_image_store(struct ac_nir_context
*ctx
,
3619 nir_intrinsic_instr
*instr
)
3621 LLVMValueRef params
[8];
3622 char intrinsic_name
[64];
3623 const nir_variable
*var
= instr
->variables
[0]->var
;
3624 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3625 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3626 LLVMValueRef glc
= ctx
->ac
.i1false
;
3627 bool force_glc
= ctx
->ac
.chip_class
== SI
;
3629 glc
= ctx
->ac
.i1true
;
3631 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
3632 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2])); /* data */
3633 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
, NULL
, true, true);
3634 params
[2] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3635 ctx
->ac
.i32_0
, ""); /* vindex */
3636 params
[3] = ctx
->ac
.i32_0
; /* voffset */
3637 params
[4] = glc
; /* glc */
3638 params
[5] = ctx
->ac
.i1false
; /* slc */
3639 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->ac
.voidt
,
3642 LLVMValueRef da
= glsl_is_array_image(type
) ? ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3643 LLVMValueRef slc
= ctx
->ac
.i1false
;
3645 params
[0] = ac_to_float(&ctx
->ac
, get_src(ctx
, instr
->src
[2]));
3646 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3647 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, true);
3648 params
[3] = LLVMConstInt(ctx
->ac
.i32
, 15, false); /* dmask */
3649 params
[4] = (force_glc
|| var
->data
.image
._volatile
|| var
->data
.image
.coherent
) ?
3650 ctx
->ac
.i1true
: ctx
->ac
.i1false
;
3652 params
[6] = ctx
->ac
.i1false
;
3655 ac_get_image_intr_name("llvm.amdgcn.image.store",
3656 LLVMTypeOf(params
[0]), /* vdata */
3657 LLVMTypeOf(params
[1]), /* coords */
3658 LLVMTypeOf(params
[2]), /* rsrc */
3659 intrinsic_name
, sizeof(intrinsic_name
));
3661 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.voidt
,
3667 static LLVMValueRef
visit_image_atomic(struct ac_nir_context
*ctx
,
3668 const nir_intrinsic_instr
*instr
)
3670 LLVMValueRef params
[7];
3671 int param_count
= 0;
3672 const nir_variable
*var
= instr
->variables
[0]->var
;
3674 const char *atomic_name
;
3675 char intrinsic_name
[41];
3676 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3677 MAYBE_UNUSED
int length
;
3679 bool is_unsigned
= glsl_get_sampler_result_type(type
) == GLSL_TYPE_UINT
;
3681 switch (instr
->intrinsic
) {
3682 case nir_intrinsic_image_atomic_add
:
3683 atomic_name
= "add";
3685 case nir_intrinsic_image_atomic_min
:
3686 atomic_name
= is_unsigned
? "umin" : "smin";
3688 case nir_intrinsic_image_atomic_max
:
3689 atomic_name
= is_unsigned
? "umax" : "smax";
3691 case nir_intrinsic_image_atomic_and
:
3692 atomic_name
= "and";
3694 case nir_intrinsic_image_atomic_or
:
3697 case nir_intrinsic_image_atomic_xor
:
3698 atomic_name
= "xor";
3700 case nir_intrinsic_image_atomic_exchange
:
3701 atomic_name
= "swap";
3703 case nir_intrinsic_image_atomic_comp_swap
:
3704 atomic_name
= "cmpswap";
3710 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3711 params
[param_count
++] = get_src(ctx
, instr
->src
[3]);
3712 params
[param_count
++] = get_src(ctx
, instr
->src
[2]);
3714 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3715 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_BUFFER
,
3717 params
[param_count
++] = LLVMBuildExtractElement(ctx
->ac
.builder
, get_src(ctx
, instr
->src
[0]),
3718 ctx
->ac
.i32_0
, ""); /* vindex */
3719 params
[param_count
++] = ctx
->ac
.i32_0
; /* voffset */
3720 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3722 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3723 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3725 char coords_type
[8];
3727 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3728 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
,
3730 params
[param_count
++] = ctx
->ac
.i1false
; /* r128 */
3731 params
[param_count
++] = glsl_is_array_image(type
) ? ctx
->ac
.i1true
: ctx
->ac
.i1false
; /* da */
3732 params
[param_count
++] = ctx
->ac
.i1false
; /* slc */
3734 build_int_type_name(LLVMTypeOf(coords
),
3735 coords_type
, sizeof(coords_type
));
3737 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3738 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3741 assert(length
< sizeof(intrinsic_name
));
3742 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->ac
.i32
, params
, param_count
, 0);
3745 static LLVMValueRef
visit_image_samples(struct ac_nir_context
*ctx
,
3746 const nir_intrinsic_instr
*instr
)
3748 const nir_variable
*var
= instr
->variables
[0]->var
;
3749 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3751 struct ac_image_args args
= { 0 };
3752 args
.da
= glsl_is_array_image(type
);
3754 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0],
3755 AC_DESC_IMAGE
, NULL
, true, false);
3756 args
.opcode
= ac_image_get_resinfo
;
3757 args
.addr
= ctx
->ac
.i32_0
;
3759 return ac_build_image_opcode(&ctx
->ac
, &args
);
3762 static LLVMValueRef
visit_image_size(struct ac_nir_context
*ctx
,
3763 const nir_intrinsic_instr
*instr
)
3766 const nir_variable
*var
= instr
->variables
[0]->var
;
3767 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3769 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3770 return get_buffer_size(ctx
,
3771 get_sampler_desc(ctx
, instr
->variables
[0],
3772 AC_DESC_BUFFER
, NULL
, true, false), true);
3774 struct ac_image_args args
= { 0 };
3776 args
.da
= glsl_is_array_image(type
);
3778 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], AC_DESC_IMAGE
, NULL
, true, false);
3779 args
.opcode
= ac_image_get_resinfo
;
3780 args
.addr
= ctx
->ac
.i32_0
;
3782 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3784 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3786 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3787 glsl_sampler_type_is_array(type
)) {
3788 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
3789 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3790 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
3791 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, z
, two
, "");
3793 if (ctx
->ac
.chip_class
>= GFX9
&&
3794 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
3795 glsl_sampler_type_is_array(type
)) {
3796 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
, two
, "");
3797 res
= LLVMBuildInsertElement(ctx
->ac
.builder
, res
, layers
,
3804 #define NOOP_WAITCNT 0xf7f
3805 #define LGKM_CNT 0x07f
3806 #define VM_CNT 0xf70
3808 static void emit_membar(struct ac_llvm_context
*ac
,
3809 const nir_intrinsic_instr
*instr
)
3811 unsigned waitcnt
= NOOP_WAITCNT
;
3813 switch (instr
->intrinsic
) {
3814 case nir_intrinsic_memory_barrier
:
3815 case nir_intrinsic_group_memory_barrier
:
3816 waitcnt
&= VM_CNT
& LGKM_CNT
;
3818 case nir_intrinsic_memory_barrier_atomic_counter
:
3819 case nir_intrinsic_memory_barrier_buffer
:
3820 case nir_intrinsic_memory_barrier_image
:
3823 case nir_intrinsic_memory_barrier_shared
:
3824 waitcnt
&= LGKM_CNT
;
3829 if (waitcnt
!= NOOP_WAITCNT
)
3830 ac_build_waitcnt(ac
, waitcnt
);
3833 static void emit_barrier(struct ac_llvm_context
*ac
, gl_shader_stage stage
)
3835 /* SI only (thanks to a hw bug workaround):
3836 * The real barrier instruction isn’t needed, because an entire patch
3837 * always fits into a single wave.
3839 if (ac
->chip_class
== SI
&& stage
== MESA_SHADER_TESS_CTRL
) {
3840 ac_build_waitcnt(ac
, LGKM_CNT
& VM_CNT
);
3843 ac_build_intrinsic(ac
, "llvm.amdgcn.s.barrier",
3844 ac
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3847 static void emit_discard(struct ac_nir_context
*ctx
,
3848 const nir_intrinsic_instr
*instr
)
3852 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3853 cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3854 get_src(ctx
, instr
->src
[0]),
3857 assert(instr
->intrinsic
== nir_intrinsic_discard
);
3858 cond
= LLVMConstInt(ctx
->ac
.i1
, false, 0);
3861 ac_build_kill_if_false(&ctx
->ac
, cond
);
3865 visit_load_helper_invocation(struct ac_nir_context
*ctx
)
3867 LLVMValueRef result
= ac_build_intrinsic(&ctx
->ac
,
3868 "llvm.amdgcn.ps.live",
3869 ctx
->ac
.i1
, NULL
, 0,
3870 AC_FUNC_ATTR_READNONE
);
3871 result
= LLVMBuildNot(ctx
->ac
.builder
, result
, "");
3872 return LLVMBuildSExt(ctx
->ac
.builder
, result
, ctx
->ac
.i32
, "");
3876 visit_load_local_invocation_index(struct ac_nir_context
*ctx
)
3878 LLVMValueRef result
;
3879 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3880 result
= LLVMBuildAnd(ctx
->ac
.builder
, ctx
->abi
->tg_size
,
3881 LLVMConstInt(ctx
->ac
.i32
, 0xfc0, false), "");
3883 return LLVMBuildAdd(ctx
->ac
.builder
, result
, thread_id
, "");
3887 visit_load_shared(struct ac_nir_context
*ctx
,
3888 const nir_intrinsic_instr
*instr
)
3890 LLVMValueRef values
[4], derived_ptr
, index
, ret
;
3892 LLVMValueRef ptr
= get_memory_ptr(ctx
, instr
->src
[0]);
3894 for (int chan
= 0; chan
< instr
->num_components
; chan
++) {
3895 index
= LLVMConstInt(ctx
->ac
.i32
, chan
, 0);
3896 derived_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
3897 values
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, derived_ptr
, "");
3900 ret
= ac_build_gather_values(&ctx
->ac
, values
, instr
->num_components
);
3901 return LLVMBuildBitCast(ctx
->ac
.builder
, ret
, get_def_type(ctx
, &instr
->dest
.ssa
), "");
3905 visit_store_shared(struct ac_nir_context
*ctx
,
3906 const nir_intrinsic_instr
*instr
)
3908 LLVMValueRef derived_ptr
, data
,index
;
3909 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3911 LLVMValueRef ptr
= get_memory_ptr(ctx
, instr
->src
[1]);
3912 LLVMValueRef src
= get_src(ctx
, instr
->src
[0]);
3914 int writemask
= nir_intrinsic_write_mask(instr
);
3915 for (int chan
= 0; chan
< 4; chan
++) {
3916 if (!(writemask
& (1 << chan
))) {
3919 data
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
);
3920 index
= LLVMConstInt(ctx
->ac
.i32
, chan
, 0);
3921 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
3922 LLVMBuildStore(builder
, data
, derived_ptr
);
3926 static LLVMValueRef
visit_var_atomic(struct ac_nir_context
*ctx
,
3927 const nir_intrinsic_instr
*instr
,
3928 LLVMValueRef ptr
, int src_idx
)
3930 LLVMValueRef result
;
3931 LLVMValueRef src
= get_src(ctx
, instr
->src
[src_idx
]);
3933 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
||
3934 instr
->intrinsic
== nir_intrinsic_shared_atomic_comp_swap
) {
3935 LLVMValueRef src1
= get_src(ctx
, instr
->src
[src_idx
+ 1]);
3936 result
= LLVMBuildAtomicCmpXchg(ctx
->ac
.builder
,
3938 LLVMAtomicOrderingSequentiallyConsistent
,
3939 LLVMAtomicOrderingSequentiallyConsistent
,
3942 LLVMAtomicRMWBinOp op
;
3943 switch (instr
->intrinsic
) {
3944 case nir_intrinsic_var_atomic_add
:
3945 case nir_intrinsic_shared_atomic_add
:
3946 op
= LLVMAtomicRMWBinOpAdd
;
3948 case nir_intrinsic_var_atomic_umin
:
3949 case nir_intrinsic_shared_atomic_umin
:
3950 op
= LLVMAtomicRMWBinOpUMin
;
3952 case nir_intrinsic_var_atomic_umax
:
3953 case nir_intrinsic_shared_atomic_umax
:
3954 op
= LLVMAtomicRMWBinOpUMax
;
3956 case nir_intrinsic_var_atomic_imin
:
3957 case nir_intrinsic_shared_atomic_imin
:
3958 op
= LLVMAtomicRMWBinOpMin
;
3960 case nir_intrinsic_var_atomic_imax
:
3961 case nir_intrinsic_shared_atomic_imax
:
3962 op
= LLVMAtomicRMWBinOpMax
;
3964 case nir_intrinsic_var_atomic_and
:
3965 case nir_intrinsic_shared_atomic_and
:
3966 op
= LLVMAtomicRMWBinOpAnd
;
3968 case nir_intrinsic_var_atomic_or
:
3969 case nir_intrinsic_shared_atomic_or
:
3970 op
= LLVMAtomicRMWBinOpOr
;
3972 case nir_intrinsic_var_atomic_xor
:
3973 case nir_intrinsic_shared_atomic_xor
:
3974 op
= LLVMAtomicRMWBinOpXor
;
3976 case nir_intrinsic_var_atomic_exchange
:
3977 case nir_intrinsic_shared_atomic_exchange
:
3978 op
= LLVMAtomicRMWBinOpXchg
;
3984 result
= LLVMBuildAtomicRMW(ctx
->ac
.builder
, op
, ptr
, ac_to_integer(&ctx
->ac
, src
),
3985 LLVMAtomicOrderingSequentiallyConsistent
,
3991 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
3992 enum glsl_interp_mode interp
, unsigned location
)
3994 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3997 case INTERP_MODE_FLAT
:
4000 case INTERP_MODE_SMOOTH
:
4001 case INTERP_MODE_NONE
:
4002 if (location
== INTERP_CENTER
)
4003 return ctx
->persp_center
;
4004 else if (location
== INTERP_CENTROID
)
4005 return ctx
->persp_centroid
;
4006 else if (location
== INTERP_SAMPLE
)
4007 return ctx
->persp_sample
;
4009 case INTERP_MODE_NOPERSPECTIVE
:
4010 if (location
== INTERP_CENTER
)
4011 return ctx
->linear_center
;
4012 else if (location
== INTERP_CENTROID
)
4013 return ctx
->linear_centroid
;
4014 else if (location
== INTERP_SAMPLE
)
4015 return ctx
->linear_sample
;
4021 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
4022 LLVMValueRef sample_id
)
4024 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4026 LLVMValueRef result
;
4027 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false));
4029 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
4030 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
4032 sample_id
= LLVMBuildAdd(ctx
->ac
.builder
, sample_id
, ctx
->sample_pos_offset
, "");
4033 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
4038 static LLVMValueRef
load_sample_pos(struct ac_nir_context
*ctx
)
4040 LLVMValueRef values
[2];
4041 LLVMValueRef pos
[2];
4043 pos
[0] = ac_to_float(&ctx
->ac
, ctx
->abi
->frag_pos
[0]);
4044 pos
[1] = ac_to_float(&ctx
->ac
, ctx
->abi
->frag_pos
[1]);
4046 values
[0] = ac_build_fract(&ctx
->ac
, pos
[0], 32);
4047 values
[1] = ac_build_fract(&ctx
->ac
, pos
[1], 32);
4048 return ac_build_gather_values(&ctx
->ac
, values
, 2);
4051 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
4053 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4054 uint8_t log2_ps_iter_samples
= ctx
->shader_info
->info
.ps
.force_persample
?
4055 ctx
->options
->key
.fs
.log2_num_samples
:
4056 ctx
->options
->key
.fs
.log2_ps_iter_samples
;
4058 /* The bit pattern matches that used by fixed function fragment
4060 static const uint16_t ps_iter_masks
[] = {
4061 0xffff, /* not used */
4067 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
4069 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
4071 LLVMValueRef result
, sample_id
;
4072 sample_id
= unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
4073 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
4074 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
4078 static LLVMValueRef
visit_interp(struct ac_nir_context
*ctx
,
4079 const nir_intrinsic_instr
*instr
)
4081 LLVMValueRef result
[4];
4082 LLVMValueRef interp_param
, attr_number
;
4085 LLVMValueRef src_c0
= NULL
;
4086 LLVMValueRef src_c1
= NULL
;
4087 LLVMValueRef src0
= NULL
;
4088 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
4089 switch (instr
->intrinsic
) {
4090 case nir_intrinsic_interp_var_at_centroid
:
4091 location
= INTERP_CENTROID
;
4093 case nir_intrinsic_interp_var_at_sample
:
4094 case nir_intrinsic_interp_var_at_offset
:
4095 location
= INTERP_CENTER
;
4096 src0
= get_src(ctx
, instr
->src
[0]);
4102 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
4103 src_c0
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, ctx
->ac
.i32_0
, ""));
4104 src_c1
= ac_to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
, src0
, ctx
->ac
.i32_1
, ""));
4105 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
4106 LLVMValueRef sample_position
;
4107 LLVMValueRef halfval
= LLVMConstReal(ctx
->ac
.f32
, 0.5f
);
4109 /* fetch sample ID */
4110 sample_position
= ctx
->abi
->load_sample_position(ctx
->abi
, src0
);
4112 src_c0
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
, ctx
->ac
.i32_0
, "");
4113 src_c0
= LLVMBuildFSub(ctx
->ac
.builder
, src_c0
, halfval
, "");
4114 src_c1
= LLVMBuildExtractElement(ctx
->ac
.builder
, sample_position
, ctx
->ac
.i32_1
, "");
4115 src_c1
= LLVMBuildFSub(ctx
->ac
.builder
, src_c1
, halfval
, "");
4117 interp_param
= ctx
->abi
->lookup_interp_param(ctx
->abi
, instr
->variables
[0]->var
->data
.interpolation
, location
);
4118 attr_number
= LLVMConstInt(ctx
->ac
.i32
, input_index
, false);
4120 if (location
== INTERP_CENTER
) {
4121 LLVMValueRef ij_out
[2];
4122 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
, interp_param
);
4125 * take the I then J parameters, and the DDX/Y for it, and
4126 * calculate the IJ inputs for the interpolator.
4127 * temp1 = ddx * offset/sample.x + I;
4128 * interp_param.I = ddy * offset/sample.y + temp1;
4129 * temp1 = ddx * offset/sample.x + J;
4130 * interp_param.J = ddy * offset/sample.y + temp1;
4132 for (unsigned i
= 0; i
< 2; i
++) {
4133 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->ac
.i32
, i
, false);
4134 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->ac
.i32
, i
+ 2, false);
4135 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4136 ddxy_out
, ix_ll
, "");
4137 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4138 ddxy_out
, iy_ll
, "");
4139 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4140 interp_param
, ix_ll
, "");
4141 LLVMValueRef temp1
, temp2
;
4143 interp_el
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_el
,
4146 temp1
= LLVMBuildFMul(ctx
->ac
.builder
, ddx_el
, src_c0
, "");
4147 temp1
= LLVMBuildFAdd(ctx
->ac
.builder
, temp1
, interp_el
, "");
4149 temp2
= LLVMBuildFMul(ctx
->ac
.builder
, ddy_el
, src_c1
, "");
4150 temp2
= LLVMBuildFAdd(ctx
->ac
.builder
, temp2
, temp1
, "");
4152 ij_out
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
,
4153 temp2
, ctx
->ac
.i32
, "");
4155 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
4159 for (chan
= 0; chan
< 4; chan
++) {
4160 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
4163 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
,
4164 interp_param
, ctx
->ac
.v2f32
, "");
4165 LLVMValueRef i
= LLVMBuildExtractElement(
4166 ctx
->ac
.builder
, interp_param
, ctx
->ac
.i32_0
, "");
4167 LLVMValueRef j
= LLVMBuildExtractElement(
4168 ctx
->ac
.builder
, interp_param
, ctx
->ac
.i32_1
, "");
4170 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
4171 llvm_chan
, attr_number
,
4172 ctx
->abi
->prim_mask
, i
, j
);
4174 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
4175 LLVMConstInt(ctx
->ac
.i32
, 2, false),
4176 llvm_chan
, attr_number
,
4177 ctx
->abi
->prim_mask
);
4180 return ac_build_varying_gather_values(&ctx
->ac
, result
, instr
->num_components
,
4181 instr
->variables
[0]->var
->data
.location_frac
);
4185 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
4187 LLVMValueRef gs_next_vertex
;
4188 LLVMValueRef can_emit
;
4190 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4192 assert(stream
== 0);
4194 /* Write vertex attribute values to GSVS ring */
4195 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
4196 ctx
->gs_next_vertex
,
4199 /* If this thread has already emitted the declared maximum number of
4200 * vertices, kill it: excessive vertex emissions are not supposed to
4201 * have any effect, and GS threads have no externally observable
4202 * effects other than emitting vertices.
4204 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
4205 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
4206 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
4208 /* loop num outputs */
4210 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4211 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
4216 if (!(ctx
->output_mask
& (1ull << i
)))
4219 if (i
== VARYING_SLOT_CLIP_DIST0
) {
4220 /* pack clip and cull into a single set of slots */
4221 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
4225 for (unsigned j
= 0; j
< length
; j
++) {
4226 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
4228 LLVMValueRef voffset
= LLVMConstInt(ctx
->ac
.i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
4229 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
4230 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4232 out_val
= LLVMBuildBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
4234 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
4236 voffset
, ctx
->gs2vs_offset
, 0,
4242 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
4244 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
4246 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
4250 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
4252 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4253 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
4257 load_tess_coord(struct ac_shader_abi
*abi
)
4259 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4261 LLVMValueRef coord
[4] = {
4268 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
4269 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
4270 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
4272 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
4276 load_patch_vertices_in(struct ac_shader_abi
*abi
)
4278 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4279 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
4282 static void visit_intrinsic(struct ac_nir_context
*ctx
,
4283 nir_intrinsic_instr
*instr
)
4285 LLVMValueRef result
= NULL
;
4287 switch (instr
->intrinsic
) {
4288 case nir_intrinsic_ballot
:
4289 result
= ac_build_ballot(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4291 case nir_intrinsic_read_invocation
:
4292 case nir_intrinsic_read_first_invocation
: {
4293 LLVMValueRef args
[2];
4296 args
[0] = get_src(ctx
, instr
->src
[0]);
4299 const char *intr_name
;
4300 if (instr
->intrinsic
== nir_intrinsic_read_invocation
) {
4302 intr_name
= "llvm.amdgcn.readlane";
4305 args
[1] = get_src(ctx
, instr
->src
[1]);
4308 intr_name
= "llvm.amdgcn.readfirstlane";
4311 /* We currently have no other way to prevent LLVM from lifting the icmp
4312 * calls to a dominating basic block.
4314 ac_build_optimization_barrier(&ctx
->ac
, &args
[0]);
4316 result
= ac_build_intrinsic(&ctx
->ac
, intr_name
,
4317 ctx
->ac
.i32
, args
, num_args
,
4318 AC_FUNC_ATTR_READNONE
|
4319 AC_FUNC_ATTR_CONVERGENT
);
4322 case nir_intrinsic_load_subgroup_invocation
:
4323 result
= ac_get_thread_id(&ctx
->ac
);
4325 case nir_intrinsic_load_work_group_id
: {
4326 LLVMValueRef values
[3];
4328 for (int i
= 0; i
< 3; i
++) {
4329 values
[i
] = ctx
->abi
->workgroup_ids
[i
] ?
4330 ctx
->abi
->workgroup_ids
[i
] : ctx
->ac
.i32_0
;
4333 result
= ac_build_gather_values(&ctx
->ac
, values
, 3);
4336 case nir_intrinsic_load_base_vertex
: {
4337 result
= ctx
->abi
->load_base_vertex(ctx
->abi
);
4340 case nir_intrinsic_load_local_group_size
:
4341 result
= ctx
->abi
->load_local_group_size(ctx
->abi
);
4343 case nir_intrinsic_load_vertex_id
:
4344 result
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
->vertex_id
,
4345 ctx
->abi
->base_vertex
, "");
4347 case nir_intrinsic_load_vertex_id_zero_base
: {
4348 result
= ctx
->abi
->vertex_id
;
4351 case nir_intrinsic_load_local_invocation_id
: {
4352 result
= ctx
->abi
->local_invocation_ids
;
4355 case nir_intrinsic_load_base_instance
:
4356 result
= ctx
->abi
->start_instance
;
4358 case nir_intrinsic_load_draw_id
:
4359 result
= ctx
->abi
->draw_id
;
4361 case nir_intrinsic_load_view_index
:
4362 result
= ctx
->abi
->view_index
;
4364 case nir_intrinsic_load_invocation_id
:
4365 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
4366 result
= unpack_param(&ctx
->ac
, ctx
->abi
->tcs_rel_ids
, 8, 5);
4368 result
= ctx
->abi
->gs_invocation_id
;
4370 case nir_intrinsic_load_primitive_id
:
4371 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4372 result
= ctx
->abi
->gs_prim_id
;
4373 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
4374 result
= ctx
->abi
->tcs_patch_id
;
4375 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4376 result
= ctx
->abi
->tes_patch_id
;
4378 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4380 case nir_intrinsic_load_sample_id
:
4381 result
= unpack_param(&ctx
->ac
, ctx
->abi
->ancillary
, 8, 4);
4383 case nir_intrinsic_load_sample_pos
:
4384 result
= load_sample_pos(ctx
);
4386 case nir_intrinsic_load_sample_mask_in
:
4387 result
= ctx
->abi
->load_sample_mask_in(ctx
->abi
);
4389 case nir_intrinsic_load_frag_coord
: {
4390 LLVMValueRef values
[4] = {
4391 ctx
->abi
->frag_pos
[0],
4392 ctx
->abi
->frag_pos
[1],
4393 ctx
->abi
->frag_pos
[2],
4394 ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, ctx
->abi
->frag_pos
[3])
4396 result
= ac_build_gather_values(&ctx
->ac
, values
, 4);
4399 case nir_intrinsic_load_front_face
:
4400 result
= ctx
->abi
->front_face
;
4402 case nir_intrinsic_load_helper_invocation
:
4403 result
= visit_load_helper_invocation(ctx
);
4405 case nir_intrinsic_load_instance_id
:
4406 result
= ctx
->abi
->instance_id
;
4408 case nir_intrinsic_load_num_work_groups
:
4409 result
= ctx
->abi
->num_work_groups
;
4411 case nir_intrinsic_load_local_invocation_index
:
4412 result
= visit_load_local_invocation_index(ctx
);
4414 case nir_intrinsic_load_push_constant
:
4415 result
= visit_load_push_constant(ctx
, instr
);
4417 case nir_intrinsic_vulkan_resource_index
: {
4418 LLVMValueRef index
= get_src(ctx
, instr
->src
[0]);
4419 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4420 unsigned binding
= nir_intrinsic_binding(instr
);
4422 result
= ctx
->abi
->load_resource(ctx
->abi
, index
, desc_set
,
4426 case nir_intrinsic_vulkan_resource_reindex
:
4427 result
= visit_vulkan_resource_reindex(ctx
, instr
);
4429 case nir_intrinsic_store_ssbo
:
4430 visit_store_ssbo(ctx
, instr
);
4432 case nir_intrinsic_load_ssbo
:
4433 result
= visit_load_buffer(ctx
, instr
);
4435 case nir_intrinsic_ssbo_atomic_add
:
4436 case nir_intrinsic_ssbo_atomic_imin
:
4437 case nir_intrinsic_ssbo_atomic_umin
:
4438 case nir_intrinsic_ssbo_atomic_imax
:
4439 case nir_intrinsic_ssbo_atomic_umax
:
4440 case nir_intrinsic_ssbo_atomic_and
:
4441 case nir_intrinsic_ssbo_atomic_or
:
4442 case nir_intrinsic_ssbo_atomic_xor
:
4443 case nir_intrinsic_ssbo_atomic_exchange
:
4444 case nir_intrinsic_ssbo_atomic_comp_swap
:
4445 result
= visit_atomic_ssbo(ctx
, instr
);
4447 case nir_intrinsic_load_ubo
:
4448 result
= visit_load_ubo_buffer(ctx
, instr
);
4450 case nir_intrinsic_get_buffer_size
:
4451 result
= visit_get_buffer_size(ctx
, instr
);
4453 case nir_intrinsic_load_var
:
4454 result
= visit_load_var(ctx
, instr
);
4456 case nir_intrinsic_store_var
:
4457 visit_store_var(ctx
, instr
);
4459 case nir_intrinsic_load_shared
:
4460 result
= visit_load_shared(ctx
, instr
);
4462 case nir_intrinsic_store_shared
:
4463 visit_store_shared(ctx
, instr
);
4465 case nir_intrinsic_image_samples
:
4466 result
= visit_image_samples(ctx
, instr
);
4468 case nir_intrinsic_image_load
:
4469 result
= visit_image_load(ctx
, instr
);
4471 case nir_intrinsic_image_store
:
4472 visit_image_store(ctx
, instr
);
4474 case nir_intrinsic_image_atomic_add
:
4475 case nir_intrinsic_image_atomic_min
:
4476 case nir_intrinsic_image_atomic_max
:
4477 case nir_intrinsic_image_atomic_and
:
4478 case nir_intrinsic_image_atomic_or
:
4479 case nir_intrinsic_image_atomic_xor
:
4480 case nir_intrinsic_image_atomic_exchange
:
4481 case nir_intrinsic_image_atomic_comp_swap
:
4482 result
= visit_image_atomic(ctx
, instr
);
4484 case nir_intrinsic_image_size
:
4485 result
= visit_image_size(ctx
, instr
);
4487 case nir_intrinsic_shader_clock
:
4488 result
= ac_build_shader_clock(&ctx
->ac
);
4490 case nir_intrinsic_discard
:
4491 case nir_intrinsic_discard_if
:
4492 emit_discard(ctx
, instr
);
4494 case nir_intrinsic_memory_barrier
:
4495 case nir_intrinsic_group_memory_barrier
:
4496 case nir_intrinsic_memory_barrier_atomic_counter
:
4497 case nir_intrinsic_memory_barrier_buffer
:
4498 case nir_intrinsic_memory_barrier_image
:
4499 case nir_intrinsic_memory_barrier_shared
:
4500 emit_membar(&ctx
->ac
, instr
);
4502 case nir_intrinsic_barrier
:
4503 emit_barrier(&ctx
->ac
, ctx
->stage
);
4505 case nir_intrinsic_shared_atomic_add
:
4506 case nir_intrinsic_shared_atomic_imin
:
4507 case nir_intrinsic_shared_atomic_umin
:
4508 case nir_intrinsic_shared_atomic_imax
:
4509 case nir_intrinsic_shared_atomic_umax
:
4510 case nir_intrinsic_shared_atomic_and
:
4511 case nir_intrinsic_shared_atomic_or
:
4512 case nir_intrinsic_shared_atomic_xor
:
4513 case nir_intrinsic_shared_atomic_exchange
:
4514 case nir_intrinsic_shared_atomic_comp_swap
: {
4515 LLVMValueRef ptr
= get_memory_ptr(ctx
, instr
->src
[0]);
4516 result
= visit_var_atomic(ctx
, instr
, ptr
, 1);
4519 case nir_intrinsic_var_atomic_add
:
4520 case nir_intrinsic_var_atomic_imin
:
4521 case nir_intrinsic_var_atomic_umin
:
4522 case nir_intrinsic_var_atomic_imax
:
4523 case nir_intrinsic_var_atomic_umax
:
4524 case nir_intrinsic_var_atomic_and
:
4525 case nir_intrinsic_var_atomic_or
:
4526 case nir_intrinsic_var_atomic_xor
:
4527 case nir_intrinsic_var_atomic_exchange
:
4528 case nir_intrinsic_var_atomic_comp_swap
: {
4529 LLVMValueRef ptr
= build_gep_for_deref(ctx
, instr
->variables
[0]);
4530 result
= visit_var_atomic(ctx
, instr
, ptr
, 0);
4533 case nir_intrinsic_interp_var_at_centroid
:
4534 case nir_intrinsic_interp_var_at_sample
:
4535 case nir_intrinsic_interp_var_at_offset
:
4536 result
= visit_interp(ctx
, instr
);
4538 case nir_intrinsic_emit_vertex
:
4539 ctx
->abi
->emit_vertex(ctx
->abi
, nir_intrinsic_stream_id(instr
), ctx
->abi
->outputs
);
4541 case nir_intrinsic_end_primitive
:
4542 ctx
->abi
->emit_primitive(ctx
->abi
, nir_intrinsic_stream_id(instr
));
4544 case nir_intrinsic_load_tess_coord
:
4545 result
= ctx
->abi
->load_tess_coord(ctx
->abi
);
4547 case nir_intrinsic_load_tess_level_outer
:
4548 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_OUTER
);
4550 case nir_intrinsic_load_tess_level_inner
:
4551 result
= ctx
->abi
->load_tess_level(ctx
->abi
, VARYING_SLOT_TESS_LEVEL_INNER
);
4553 case nir_intrinsic_load_patch_vertices_in
:
4554 result
= ctx
->abi
->load_patch_vertices_in(ctx
->abi
);
4556 case nir_intrinsic_vote_all
: {
4557 LLVMValueRef tmp
= ac_build_vote_all(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4558 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4561 case nir_intrinsic_vote_any
: {
4562 LLVMValueRef tmp
= ac_build_vote_any(&ctx
->ac
, get_src(ctx
, instr
->src
[0]));
4563 result
= LLVMBuildSExt(ctx
->ac
.builder
, tmp
, ctx
->ac
.i32
, "");
4567 fprintf(stderr
, "Unknown intrinsic: ");
4568 nir_print_instr(&instr
->instr
, stderr
);
4569 fprintf(stderr
, "\n");
4573 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4577 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
4579 return abi
->base_vertex
;
4582 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
4583 LLVMValueRef buffer_ptr
, bool write
)
4585 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4586 LLVMValueRef result
;
4588 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4590 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
4591 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4596 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
4598 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4599 LLVMValueRef result
;
4601 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
4603 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
4604 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
4609 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
4610 unsigned descriptor_set
,
4611 unsigned base_index
,
4612 unsigned constant_index
,
4614 enum ac_descriptor_type desc_type
,
4615 bool image
, bool write
)
4617 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4618 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
4619 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4620 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4621 unsigned offset
= binding
->offset
;
4622 unsigned stride
= binding
->size
;
4624 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4627 assert(base_index
< layout
->binding_count
);
4629 switch (desc_type
) {
4631 type
= ctx
->ac
.v8i32
;
4635 type
= ctx
->ac
.v8i32
;
4639 case AC_DESC_SAMPLER
:
4640 type
= ctx
->ac
.v4i32
;
4641 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4646 case AC_DESC_BUFFER
:
4647 type
= ctx
->ac
.v4i32
;
4651 unreachable("invalid desc_type\n");
4654 offset
+= constant_index
* stride
;
4656 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4657 (!index
|| binding
->immutable_samplers_equal
)) {
4658 if (binding
->immutable_samplers_equal
)
4661 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4663 LLVMValueRef constants
[] = {
4664 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
4665 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
4666 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
4667 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
4669 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4672 assert(stride
% type_size
== 0);
4675 index
= ctx
->ac
.i32_0
;
4677 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
4679 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->ac
.i32
, offset
, 0));
4680 list
= LLVMBuildPointerCast(builder
, list
, ac_array_in_const_addr_space(type
), "");
4682 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
4685 static LLVMValueRef
get_sampler_desc(struct ac_nir_context
*ctx
,
4686 const nir_deref_var
*deref
,
4687 enum ac_descriptor_type desc_type
,
4688 const nir_tex_instr
*tex_instr
,
4689 bool image
, bool write
)
4691 LLVMValueRef index
= NULL
;
4692 unsigned constant_index
= 0;
4693 unsigned descriptor_set
;
4694 unsigned base_index
;
4697 assert(tex_instr
&& !image
);
4699 base_index
= tex_instr
->sampler_index
;
4701 const nir_deref
*tail
= &deref
->deref
;
4702 while (tail
->child
) {
4703 const nir_deref_array
*child
= nir_deref_as_array(tail
->child
);
4704 unsigned array_size
= glsl_get_aoa_size(tail
->child
->type
);
4709 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4711 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4712 LLVMValueRef indirect
= get_src(ctx
, child
->indirect
);
4714 indirect
= LLVMBuildMul(ctx
->ac
.builder
, indirect
,
4715 LLVMConstInt(ctx
->ac
.i32
, array_size
, false), "");
4720 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
, indirect
, "");
4723 constant_index
+= child
->base_offset
* array_size
;
4725 tail
= &child
->deref
;
4727 descriptor_set
= deref
->var
->data
.descriptor_set
;
4728 base_index
= deref
->var
->data
.binding
;
4731 return ctx
->abi
->load_sampler_desc(ctx
->abi
,
4734 constant_index
, index
,
4735 desc_type
, image
, write
);
4738 static void set_tex_fetch_args(struct ac_llvm_context
*ctx
,
4739 struct ac_image_args
*args
,
4740 const nir_tex_instr
*instr
,
4742 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4743 LLVMValueRef
*param
, unsigned count
,
4746 unsigned is_rect
= 0;
4747 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4749 if (op
== nir_texop_lod
)
4751 /* Pad to power of two vector */
4752 while (count
< util_next_power_of_two(count
))
4753 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4756 args
->addr
= ac_build_gather_values(ctx
, param
, count
);
4758 args
->addr
= param
[0];
4760 args
->resource
= res_ptr
;
4761 args
->sampler
= samp_ptr
;
4763 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4764 args
->addr
= param
[0];
4768 args
->dmask
= dmask
;
4769 args
->unorm
= is_rect
;
4773 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4776 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4777 * filtering manually. The driver sets img7 to a mask clearing
4778 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4779 * s_and_b32 samp0, samp0, img7
4782 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4784 static LLVMValueRef
sici_fix_sampler_aniso(struct ac_nir_context
*ctx
,
4785 LLVMValueRef res
, LLVMValueRef samp
)
4787 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4788 LLVMValueRef img7
, samp0
;
4790 if (ctx
->ac
.chip_class
>= VI
)
4793 img7
= LLVMBuildExtractElement(builder
, res
,
4794 LLVMConstInt(ctx
->ac
.i32
, 7, 0), "");
4795 samp0
= LLVMBuildExtractElement(builder
, samp
,
4796 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4797 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4798 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4799 LLVMConstInt(ctx
->ac
.i32
, 0, 0), "");
4802 static void tex_fetch_ptrs(struct ac_nir_context
*ctx
,
4803 nir_tex_instr
*instr
,
4804 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4805 LLVMValueRef
*fmask_ptr
)
4807 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4808 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_BUFFER
, instr
, false, false);
4810 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_IMAGE
, instr
, false, false);
4813 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, AC_DESC_SAMPLER
, instr
, false, false);
4815 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_SAMPLER
, instr
, false, false);
4816 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4817 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4819 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4820 instr
->op
== nir_texop_samples_identical
))
4821 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, AC_DESC_FMASK
, instr
, false, false);
4824 static LLVMValueRef
apply_round_slice(struct ac_llvm_context
*ctx
,
4827 coord
= ac_to_float(ctx
, coord
);
4828 coord
= ac_build_intrinsic(ctx
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4829 coord
= ac_to_integer(ctx
, coord
);
4833 static void visit_tex(struct ac_nir_context
*ctx
, nir_tex_instr
*instr
)
4835 LLVMValueRef result
= NULL
;
4836 struct ac_image_args args
= { 0 };
4837 unsigned dmask
= 0xf;
4838 LLVMValueRef address
[16];
4839 LLVMValueRef coords
[5];
4840 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4841 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4842 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4843 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4844 LLVMValueRef derivs
[6];
4845 unsigned chan
, count
= 0;
4846 unsigned const_src
= 0, num_deriv_comp
= 0;
4847 bool lod_is_zero
= false;
4849 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4851 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4852 switch (instr
->src
[i
].src_type
) {
4853 case nir_tex_src_coord
:
4854 coord
= get_src(ctx
, instr
->src
[i
].src
);
4856 case nir_tex_src_projector
:
4858 case nir_tex_src_comparator
:
4859 comparator
= get_src(ctx
, instr
->src
[i
].src
);
4861 case nir_tex_src_offset
:
4862 offsets
= get_src(ctx
, instr
->src
[i
].src
);
4865 case nir_tex_src_bias
:
4866 bias
= get_src(ctx
, instr
->src
[i
].src
);
4868 case nir_tex_src_lod
: {
4869 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4871 if (val
&& val
->i32
[0] == 0)
4873 lod
= get_src(ctx
, instr
->src
[i
].src
);
4876 case nir_tex_src_ms_index
:
4877 sample_index
= get_src(ctx
, instr
->src
[i
].src
);
4879 case nir_tex_src_ms_mcs
:
4881 case nir_tex_src_ddx
:
4882 ddx
= get_src(ctx
, instr
->src
[i
].src
);
4883 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4885 case nir_tex_src_ddy
:
4886 ddy
= get_src(ctx
, instr
->src
[i
].src
);
4888 case nir_tex_src_texture_offset
:
4889 case nir_tex_src_sampler_offset
:
4890 case nir_tex_src_plane
:
4896 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4897 result
= get_buffer_size(ctx
, res_ptr
, true);
4901 if (instr
->op
== nir_texop_texture_samples
) {
4902 LLVMValueRef res
, samples
, is_msaa
;
4903 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->ac
.v8i32
, "");
4904 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
4905 LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
4906 is_msaa
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4907 LLVMConstInt(ctx
->ac
.i32
, 28, false), "");
4908 is_msaa
= LLVMBuildAnd(ctx
->ac
.builder
, is_msaa
,
4909 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4910 is_msaa
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, is_msaa
,
4911 LLVMConstInt(ctx
->ac
.i32
, 0xe, false), "");
4913 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
4914 LLVMConstInt(ctx
->ac
.i32
, 16, false), "");
4915 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
4916 LLVMConstInt(ctx
->ac
.i32
, 0xf, false), "");
4917 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->ac
.i32_1
,
4919 samples
= LLVMBuildSelect(ctx
->ac
.builder
, is_msaa
, samples
,
4926 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4927 coords
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, coord
, chan
);
4929 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4930 LLVMValueRef offset
[3], pack
;
4931 for (chan
= 0; chan
< 3; ++chan
)
4932 offset
[chan
] = ctx
->ac
.i32_0
;
4935 for (chan
= 0; chan
< ac_get_llvm_num_components(offsets
); chan
++) {
4936 offset
[chan
] = ac_llvm_extract_elem(&ctx
->ac
, offsets
, chan
);
4937 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
4938 LLVMConstInt(ctx
->ac
.i32
, 0x3f, false), "");
4940 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
4941 LLVMConstInt(ctx
->ac
.i32
, chan
* 8, false), "");
4943 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
4944 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
4945 address
[count
++] = pack
;
4948 /* pack LOD bias value */
4949 if (instr
->op
== nir_texop_txb
&& bias
) {
4950 address
[count
++] = bias
;
4953 /* Pack depth comparison value */
4954 if (instr
->is_shadow
&& comparator
) {
4955 LLVMValueRef z
= ac_to_float(&ctx
->ac
,
4956 ac_llvm_extract_elem(&ctx
->ac
, comparator
, 0));
4958 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4959 * so the depth comparison value isn't clamped for Z16 and
4960 * Z24 anymore. Do it manually here.
4962 * It's unnecessary if the original texture format was
4963 * Z32_FLOAT, but we don't know that here.
4965 if (ctx
->ac
.chip_class
== VI
&& ctx
->abi
->clamp_shadow_reference
)
4966 z
= ac_build_clamp(&ctx
->ac
, z
);
4968 address
[count
++] = z
;
4971 /* pack derivatives */
4973 int num_src_deriv_channels
, num_dest_deriv_channels
;
4974 switch (instr
->sampler_dim
) {
4975 case GLSL_SAMPLER_DIM_3D
:
4976 case GLSL_SAMPLER_DIM_CUBE
:
4978 num_src_deriv_channels
= 3;
4979 num_dest_deriv_channels
= 3;
4981 case GLSL_SAMPLER_DIM_2D
:
4983 num_src_deriv_channels
= 2;
4984 num_dest_deriv_channels
= 2;
4987 case GLSL_SAMPLER_DIM_1D
:
4988 num_src_deriv_channels
= 1;
4989 if (ctx
->ac
.chip_class
>= GFX9
) {
4990 num_dest_deriv_channels
= 2;
4993 num_dest_deriv_channels
= 1;
4999 for (unsigned i
= 0; i
< num_src_deriv_channels
; i
++) {
5000 derivs
[i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddx
, i
));
5001 derivs
[num_dest_deriv_channels
+ i
] = ac_to_float(&ctx
->ac
, ac_llvm_extract_elem(&ctx
->ac
, ddy
, i
));
5003 for (unsigned i
= num_src_deriv_channels
; i
< num_dest_deriv_channels
; i
++) {
5004 derivs
[i
] = ctx
->ac
.f32_0
;
5005 derivs
[num_dest_deriv_channels
+ i
] = ctx
->ac
.f32_0
;
5009 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
5010 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
5011 coords
[chan
] = ac_to_float(&ctx
->ac
, coords
[chan
]);
5012 if (instr
->coord_components
== 3)
5013 coords
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5014 ac_prepare_cube_coords(&ctx
->ac
,
5015 instr
->op
== nir_texop_txd
, instr
->is_array
,
5016 instr
->op
== nir_texop_lod
, coords
, derivs
);
5022 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
5023 address
[count
++] = derivs
[i
];
5026 /* Pack texture coordinates */
5028 address
[count
++] = coords
[0];
5029 if (instr
->coord_components
> 1) {
5030 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
5031 coords
[1] = apply_round_slice(&ctx
->ac
, coords
[1]);
5033 address
[count
++] = coords
[1];
5035 if (instr
->coord_components
> 2) {
5036 if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
5037 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
5038 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
5039 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
5041 instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
5042 coords
[2] = apply_round_slice(&ctx
->ac
, coords
[2]);
5044 address
[count
++] = coords
[2];
5047 if (ctx
->ac
.chip_class
>= GFX9
) {
5048 LLVMValueRef filler
;
5049 if (instr
->op
== nir_texop_txf
)
5050 filler
= ctx
->ac
.i32_0
;
5052 filler
= LLVMConstReal(ctx
->ac
.f32
, 0.5);
5054 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
) {
5055 /* No nir_texop_lod, because it does not take a slice
5056 * even with array textures. */
5057 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
) {
5058 address
[count
] = address
[count
- 1];
5059 address
[count
- 1] = filler
;
5062 address
[count
++] = filler
;
5068 if (lod
&& ((instr
->op
== nir_texop_txl
|| instr
->op
== nir_texop_txf
) && !lod_is_zero
)) {
5069 address
[count
++] = lod
;
5070 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
5071 address
[count
++] = sample_index
;
5072 } else if(instr
->op
== nir_texop_txs
) {
5075 address
[count
++] = lod
;
5077 address
[count
++] = ctx
->ac
.i32_0
;
5080 for (chan
= 0; chan
< count
; chan
++) {
5081 address
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
,
5082 address
[chan
], ctx
->ac
.i32
, "");
5085 if (instr
->op
== nir_texop_samples_identical
) {
5086 LLVMValueRef txf_address
[4];
5087 struct ac_image_args txf_args
= { 0 };
5088 unsigned txf_count
= count
;
5089 memcpy(txf_address
, address
, sizeof(txf_address
));
5091 if (!instr
->is_array
)
5092 txf_address
[2] = ctx
->ac
.i32_0
;
5093 txf_address
[3] = ctx
->ac
.i32_0
;
5095 set_tex_fetch_args(&ctx
->ac
, &txf_args
, instr
, nir_texop_txf
,
5097 txf_address
, txf_count
, 0xf);
5099 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
5101 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5102 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->ac
.i32_0
);
5106 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
5107 instr
->op
!= nir_texop_txs
) {
5108 unsigned sample_chan
= instr
->is_array
? 3 : 2;
5109 address
[sample_chan
] = adjust_sample_index_using_fmask(&ctx
->ac
,
5112 instr
->is_array
? address
[2] : NULL
,
5113 address
[sample_chan
],
5117 if (offsets
&& instr
->op
== nir_texop_txf
) {
5118 nir_const_value
*const_offset
=
5119 nir_src_as_const_value(instr
->src
[const_src
].src
);
5120 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
5121 assert(const_offset
);
5122 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
5123 if (num_offsets
> 2)
5124 address
[2] = LLVMBuildAdd(ctx
->ac
.builder
,
5125 address
[2], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[2], false), "");
5126 if (num_offsets
> 1)
5127 address
[1] = LLVMBuildAdd(ctx
->ac
.builder
,
5128 address
[1], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[1], false), "");
5129 address
[0] = LLVMBuildAdd(ctx
->ac
.builder
,
5130 address
[0], LLVMConstInt(ctx
->ac
.i32
, const_offset
->i32
[0], false), "");
5134 /* TODO TG4 support */
5135 if (instr
->op
== nir_texop_tg4
) {
5136 if (instr
->is_shadow
)
5139 dmask
= 1 << instr
->component
;
5141 set_tex_fetch_args(&ctx
->ac
, &args
, instr
, instr
->op
,
5142 res_ptr
, samp_ptr
, address
, count
, dmask
);
5144 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
5146 if (instr
->op
== nir_texop_query_levels
)
5147 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, LLVMConstInt(ctx
->ac
.i32
, 3, false), "");
5148 else if (instr
->is_shadow
&& instr
->is_new_style_shadow
&&
5149 instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&&
5150 instr
->op
!= nir_texop_tg4
)
5151 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, ctx
->ac
.i32_0
, "");
5152 else if (instr
->op
== nir_texop_txs
&&
5153 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
5155 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5156 LLVMValueRef six
= LLVMConstInt(ctx
->ac
.i32
, 6, false);
5157 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5158 z
= LLVMBuildSDiv(ctx
->ac
.builder
, z
, six
, "");
5159 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, z
, two
, "");
5160 } else if (ctx
->ac
.chip_class
>= GFX9
&&
5161 instr
->op
== nir_texop_txs
&&
5162 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
5164 LLVMValueRef two
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
5165 LLVMValueRef layers
= LLVMBuildExtractElement(ctx
->ac
.builder
, result
, two
, "");
5166 result
= LLVMBuildInsertElement(ctx
->ac
.builder
, result
, layers
,
5168 } else if (instr
->dest
.ssa
.num_components
!= 4)
5169 result
= trim_vector(&ctx
->ac
, result
, instr
->dest
.ssa
.num_components
);
5173 assert(instr
->dest
.is_ssa
);
5174 result
= ac_to_integer(&ctx
->ac
, result
);
5175 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5180 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
5182 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
5183 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
5185 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
5186 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
5189 static void visit_post_phi(struct ac_nir_context
*ctx
,
5190 nir_phi_instr
*instr
,
5191 LLVMValueRef llvm_phi
)
5193 nir_foreach_phi_src(src
, instr
) {
5194 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
5195 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
5197 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
5201 static void phi_post_pass(struct ac_nir_context
*ctx
)
5203 struct hash_entry
*entry
;
5204 hash_table_foreach(ctx
->phis
, entry
) {
5205 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
5206 (LLVMValueRef
)entry
->data
);
5211 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
5212 const nir_ssa_undef_instr
*instr
)
5214 unsigned num_components
= instr
->def
.num_components
;
5215 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
5218 if (num_components
== 1)
5219 undef
= LLVMGetUndef(type
);
5221 undef
= LLVMGetUndef(LLVMVectorType(type
, num_components
));
5223 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
5226 static void visit_jump(struct ac_nir_context
*ctx
,
5227 const nir_jump_instr
*instr
)
5229 switch (instr
->type
) {
5230 case nir_jump_break
:
5231 LLVMBuildBr(ctx
->ac
.builder
, ctx
->break_block
);
5232 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5234 case nir_jump_continue
:
5235 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5236 LLVMClearInsertionPosition(ctx
->ac
.builder
);
5239 fprintf(stderr
, "Unknown NIR jump instr: ");
5240 nir_print_instr(&instr
->instr
, stderr
);
5241 fprintf(stderr
, "\n");
5246 static void visit_cf_list(struct ac_nir_context
*ctx
,
5247 struct exec_list
*list
);
5249 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
5251 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
5252 nir_foreach_instr(instr
, block
)
5254 switch (instr
->type
) {
5255 case nir_instr_type_alu
:
5256 visit_alu(ctx
, nir_instr_as_alu(instr
));
5258 case nir_instr_type_load_const
:
5259 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
5261 case nir_instr_type_intrinsic
:
5262 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
5264 case nir_instr_type_tex
:
5265 visit_tex(ctx
, nir_instr_as_tex(instr
));
5267 case nir_instr_type_phi
:
5268 visit_phi(ctx
, nir_instr_as_phi(instr
));
5270 case nir_instr_type_ssa_undef
:
5271 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
5273 case nir_instr_type_jump
:
5274 visit_jump(ctx
, nir_instr_as_jump(instr
));
5277 fprintf(stderr
, "Unknown NIR instr type: ");
5278 nir_print_instr(instr
, stderr
);
5279 fprintf(stderr
, "\n");
5284 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
5287 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
5289 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
5291 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5292 LLVMBasicBlockRef merge_block
=
5293 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5294 LLVMBasicBlockRef if_block
=
5295 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5296 LLVMBasicBlockRef else_block
= merge_block
;
5297 if (!exec_list_is_empty(&if_stmt
->else_list
))
5298 else_block
= LLVMAppendBasicBlockInContext(
5299 ctx
->ac
.context
, fn
, "");
5301 LLVMValueRef cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
, value
,
5303 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, if_block
, else_block
);
5305 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, if_block
);
5306 visit_cf_list(ctx
, &if_stmt
->then_list
);
5307 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5308 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5310 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
5311 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, else_block
);
5312 visit_cf_list(ctx
, &if_stmt
->else_list
);
5313 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5314 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
5317 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
5320 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
5322 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
5323 LLVMBasicBlockRef continue_parent
= ctx
->continue_block
;
5324 LLVMBasicBlockRef break_parent
= ctx
->break_block
;
5326 ctx
->continue_block
=
5327 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5329 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
5331 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5332 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->continue_block
);
5333 visit_cf_list(ctx
, &loop
->body
);
5335 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
5336 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
5337 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->break_block
);
5339 ctx
->continue_block
= continue_parent
;
5340 ctx
->break_block
= break_parent
;
5343 static void visit_cf_list(struct ac_nir_context
*ctx
,
5344 struct exec_list
*list
)
5346 foreach_list_typed(nir_cf_node
, node
, node
, list
)
5348 switch (node
->type
) {
5349 case nir_cf_node_block
:
5350 visit_block(ctx
, nir_cf_node_as_block(node
));
5353 case nir_cf_node_if
:
5354 visit_if(ctx
, nir_cf_node_as_if(node
));
5357 case nir_cf_node_loop
:
5358 visit_loop(ctx
, nir_cf_node_as_loop(node
));
5368 handle_vs_input_decl(struct radv_shader_context
*ctx
,
5369 struct nir_variable
*variable
)
5371 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
5372 LLVMValueRef t_offset
;
5373 LLVMValueRef t_list
;
5375 LLVMValueRef buffer_index
;
5376 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
5377 int idx
= variable
->data
.location
;
5378 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
5379 uint8_t input_usage_mask
=
5380 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
5381 unsigned num_channels
= util_last_bit(input_usage_mask
);
5383 variable
->data
.driver_location
= idx
* 4;
5385 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
5386 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << (index
+ i
))) {
5387 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.instance_id
,
5388 ctx
->abi
.start_instance
, "");
5389 if (ctx
->options
->key
.vs
.as_ls
) {
5390 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5391 MAX2(2, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5393 ctx
->shader_info
->vs
.vgpr_comp_cnt
=
5394 MAX2(1, ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5397 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
5398 ctx
->abi
.base_vertex
, "");
5399 t_offset
= LLVMConstInt(ctx
->ac
.i32
, index
+ i
, false);
5401 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
5403 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
5406 num_channels
, false, true);
5408 input
= ac_build_expand_to_vec4(&ctx
->ac
, input
, num_channels
);
5410 for (unsigned chan
= 0; chan
< 4; chan
++) {
5411 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5412 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
5413 ac_to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->ac
.builder
,
5414 input
, llvm_chan
, ""));
5419 static void interp_fs_input(struct radv_shader_context
*ctx
,
5421 LLVMValueRef interp_param
,
5422 LLVMValueRef prim_mask
,
5423 LLVMValueRef result
[4])
5425 LLVMValueRef attr_number
;
5428 bool interp
= interp_param
!= NULL
;
5430 attr_number
= LLVMConstInt(ctx
->ac
.i32
, attr
, false);
5432 /* fs.constant returns the param from the middle vertex, so it's not
5433 * really useful for flat shading. It's meant to be used for custom
5434 * interpolation (but the intrinsic can't fetch from the other two
5437 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5438 * to do the right thing. The only reason we use fs.constant is that
5439 * fs.interp cannot be used on integers, because they can be equal
5443 interp_param
= LLVMBuildBitCast(ctx
->ac
.builder
, interp_param
,
5446 i
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
5448 j
= LLVMBuildExtractElement(ctx
->ac
.builder
, interp_param
,
5452 for (chan
= 0; chan
< 4; chan
++) {
5453 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
5456 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
5461 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
5462 LLVMConstInt(ctx
->ac
.i32
, 2, false),
5471 handle_fs_input_decl(struct radv_shader_context
*ctx
,
5472 struct nir_variable
*variable
)
5474 int idx
= variable
->data
.location
;
5475 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5476 LLVMValueRef interp
;
5478 variable
->data
.driver_location
= idx
* 4;
5479 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
5481 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
5482 unsigned interp_type
;
5483 if (variable
->data
.sample
)
5484 interp_type
= INTERP_SAMPLE
;
5485 else if (variable
->data
.centroid
)
5486 interp_type
= INTERP_CENTROID
;
5488 interp_type
= INTERP_CENTER
;
5490 interp
= lookup_interp_param(&ctx
->abi
, variable
->data
.interpolation
, interp_type
);
5494 for (unsigned i
= 0; i
< attrib_count
; ++i
)
5495 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
5500 handle_vs_inputs(struct radv_shader_context
*ctx
,
5501 struct nir_shader
*nir
) {
5502 nir_foreach_variable(variable
, &nir
->inputs
)
5503 handle_vs_input_decl(ctx
, variable
);
5507 prepare_interp_optimize(struct radv_shader_context
*ctx
,
5508 struct nir_shader
*nir
)
5510 if (!ctx
->options
->key
.fs
.multisample
)
5513 bool uses_center
= false;
5514 bool uses_centroid
= false;
5515 nir_foreach_variable(variable
, &nir
->inputs
) {
5516 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
5517 variable
->data
.sample
)
5520 if (variable
->data
.centroid
)
5521 uses_centroid
= true;
5526 if (uses_center
&& uses_centroid
) {
5527 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
5528 ctx
->persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->persp_center
, ctx
->persp_centroid
, "");
5529 ctx
->linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->linear_center
, ctx
->linear_centroid
, "");
5534 handle_fs_inputs(struct radv_shader_context
*ctx
,
5535 struct nir_shader
*nir
)
5537 prepare_interp_optimize(ctx
, nir
);
5539 nir_foreach_variable(variable
, &nir
->inputs
)
5540 handle_fs_input_decl(ctx
, variable
);
5544 if (ctx
->shader_info
->info
.ps
.uses_input_attachments
||
5545 ctx
->shader_info
->info
.needs_multiview_view_index
)
5546 ctx
->input_mask
|= 1ull << VARYING_SLOT_LAYER
;
5548 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
5549 LLVMValueRef interp_param
;
5550 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
5552 if (!(ctx
->input_mask
& (1ull << i
)))
5555 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
5556 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
5557 interp_param
= *inputs
;
5558 interp_fs_input(ctx
, index
, interp_param
, ctx
->abi
.prim_mask
,
5562 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
5564 } else if (i
== VARYING_SLOT_POS
) {
5565 for(int i
= 0; i
< 3; ++i
)
5566 inputs
[i
] = ctx
->abi
.frag_pos
[i
];
5568 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
5569 ctx
->abi
.frag_pos
[3]);
5572 ctx
->shader_info
->fs
.num_interp
= index
;
5573 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
5575 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
5576 ctx
->abi
.view_index
= ctx
->inputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5580 ac_build_alloca(struct ac_llvm_context
*ac
,
5584 LLVMBuilderRef builder
= ac
->builder
;
5585 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
5586 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5587 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
5588 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
5589 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
5593 LLVMPositionBuilderBefore(first_builder
, first_instr
);
5595 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
5598 res
= LLVMBuildAlloca(first_builder
, type
, name
);
5599 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
5601 LLVMDisposeBuilder(first_builder
);
5606 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5610 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5611 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5616 scan_shader_output_decl(struct radv_shader_context
*ctx
,
5617 struct nir_variable
*variable
,
5618 struct nir_shader
*shader
,
5619 gl_shader_stage stage
)
5621 int idx
= variable
->data
.location
+ variable
->data
.index
;
5622 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5623 uint64_t mask_attribs
;
5625 variable
->data
.driver_location
= idx
* 4;
5627 /* tess ctrl has it's own load/store paths for outputs */
5628 if (stage
== MESA_SHADER_TESS_CTRL
)
5631 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5632 if (stage
== MESA_SHADER_VERTEX
||
5633 stage
== MESA_SHADER_TESS_EVAL
||
5634 stage
== MESA_SHADER_GEOMETRY
) {
5635 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5636 int length
= shader
->info
.clip_distance_array_size
+
5637 shader
->info
.cull_distance_array_size
;
5638 if (stage
== MESA_SHADER_VERTEX
) {
5639 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5640 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5642 if (stage
== MESA_SHADER_TESS_EVAL
) {
5643 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
5644 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
5651 mask_attribs
= 1ull << idx
;
5655 ctx
->output_mask
|= mask_attribs
;
5659 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5660 struct nir_shader
*nir
,
5661 struct nir_variable
*variable
)
5663 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5664 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5666 /* tess ctrl has it's own load/store paths for outputs */
5667 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5670 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5671 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5672 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5673 int idx
= variable
->data
.location
+ variable
->data
.index
;
5674 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5675 int length
= nir
->info
.clip_distance_array_size
+
5676 nir
->info
.cull_distance_array_size
;
5685 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5686 for (unsigned chan
= 0; chan
< 4; chan
++) {
5687 ctx
->abi
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5688 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5694 glsl_base_to_llvm_type(struct ac_llvm_context
*ac
,
5695 enum glsl_base_type type
)
5699 case GLSL_TYPE_UINT
:
5700 case GLSL_TYPE_BOOL
:
5701 case GLSL_TYPE_SUBROUTINE
:
5703 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5705 case GLSL_TYPE_INT64
:
5706 case GLSL_TYPE_UINT64
:
5708 case GLSL_TYPE_DOUBLE
:
5711 unreachable("unknown GLSL type");
5716 glsl_to_llvm_type(struct ac_llvm_context
*ac
,
5717 const struct glsl_type
*type
)
5719 if (glsl_type_is_scalar(type
)) {
5720 return glsl_base_to_llvm_type(ac
, glsl_get_base_type(type
));
5723 if (glsl_type_is_vector(type
)) {
5724 return LLVMVectorType(
5725 glsl_base_to_llvm_type(ac
, glsl_get_base_type(type
)),
5726 glsl_get_vector_elements(type
));
5729 if (glsl_type_is_matrix(type
)) {
5730 return LLVMArrayType(
5731 glsl_to_llvm_type(ac
, glsl_get_column_type(type
)),
5732 glsl_get_matrix_columns(type
));
5735 if (glsl_type_is_array(type
)) {
5736 return LLVMArrayType(
5737 glsl_to_llvm_type(ac
, glsl_get_array_element(type
)),
5738 glsl_get_length(type
));
5741 assert(glsl_type_is_struct(type
));
5743 LLVMTypeRef member_types
[glsl_get_length(type
)];
5745 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5747 glsl_to_llvm_type(ac
,
5748 glsl_get_struct_field(type
, i
));
5751 return LLVMStructTypeInContext(ac
->context
, member_types
,
5752 glsl_get_length(type
), false);
5756 setup_locals(struct ac_nir_context
*ctx
,
5757 struct nir_function
*func
)
5760 ctx
->num_locals
= 0;
5761 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5762 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5763 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5764 variable
->data
.location_frac
= 0;
5765 ctx
->num_locals
+= attrib_count
;
5767 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5771 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5772 for (j
= 0; j
< 4; j
++) {
5773 ctx
->locals
[i
* 4 + j
] =
5774 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5780 setup_shared(struct ac_nir_context
*ctx
,
5781 struct nir_shader
*nir
)
5783 nir_foreach_variable(variable
, &nir
->shared
) {
5784 LLVMValueRef shared
=
5785 LLVMAddGlobalInAddressSpace(
5786 ctx
->ac
.module
, glsl_to_llvm_type(&ctx
->ac
, variable
->type
),
5787 variable
->name
? variable
->name
: "",
5788 AC_LOCAL_ADDR_SPACE
);
5789 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5793 /* Initialize arguments for the shader export intrinsic */
5795 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
5796 LLVMValueRef
*values
,
5797 unsigned enabled_channels
,
5799 struct ac_export_args
*args
)
5801 /* Specify the channels that are enabled. */
5802 args
->enabled_channels
= enabled_channels
;
5804 /* Specify whether the EXEC mask represents the valid mask */
5805 args
->valid_mask
= 0;
5807 /* Specify whether this is the last export */
5810 /* Specify the target we are exporting */
5811 args
->target
= target
;
5813 args
->compr
= false;
5814 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
5815 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
5816 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
5817 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
5819 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5820 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5821 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5822 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5823 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
5826 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
5827 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
5828 unsigned bits
, bool hi
) = NULL
;
5830 switch(col_format
) {
5831 case V_028714_SPI_SHADER_ZERO
:
5832 args
->enabled_channels
= 0; /* writemask */
5833 args
->target
= V_008DFC_SQ_EXP_NULL
;
5836 case V_028714_SPI_SHADER_32_R
:
5837 args
->enabled_channels
= 1;
5838 args
->out
[0] = values
[0];
5841 case V_028714_SPI_SHADER_32_GR
:
5842 args
->enabled_channels
= 0x3;
5843 args
->out
[0] = values
[0];
5844 args
->out
[1] = values
[1];
5847 case V_028714_SPI_SHADER_32_AR
:
5848 args
->enabled_channels
= 0x9;
5849 args
->out
[0] = values
[0];
5850 args
->out
[3] = values
[3];
5853 case V_028714_SPI_SHADER_FP16_ABGR
:
5854 packf
= ac_build_cvt_pkrtz_f16
;
5857 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5858 packf
= ac_build_cvt_pknorm_u16
;
5861 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5862 packf
= ac_build_cvt_pknorm_i16
;
5865 case V_028714_SPI_SHADER_UINT16_ABGR
:
5866 packi
= ac_build_cvt_pk_u16
;
5869 case V_028714_SPI_SHADER_SINT16_ABGR
:
5870 packi
= ac_build_cvt_pk_i16
;
5874 case V_028714_SPI_SHADER_32_ABGR
:
5875 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5879 /* Pack f16 or norm_i16/u16. */
5881 for (chan
= 0; chan
< 2; chan
++) {
5882 LLVMValueRef pack_args
[2] = {
5884 values
[2 * chan
+ 1]
5886 LLVMValueRef packed
;
5888 packed
= packf(&ctx
->ac
, pack_args
);
5889 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
5891 args
->compr
= 1; /* COMPR flag */
5896 for (chan
= 0; chan
< 2; chan
++) {
5897 LLVMValueRef pack_args
[2] = {
5898 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
5899 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
5901 LLVMValueRef packed
;
5903 packed
= packi(&ctx
->ac
, pack_args
,
5904 is_int8
? 8 : is_int10
? 10 : 16,
5906 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
5908 args
->compr
= 1; /* COMPR flag */
5913 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5915 for (unsigned i
= 0; i
< 4; ++i
) {
5916 if (!(args
->enabled_channels
& (1 << i
)))
5919 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
5924 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
5925 LLVMValueRef
*values
, unsigned enabled_channels
)
5927 struct ac_export_args args
;
5929 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
5930 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
5931 ac_build_export(&ctx
->ac
, &args
);
5935 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
5937 LLVMValueRef output
=
5938 ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(index
, chan
)];
5940 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
5944 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
5945 bool export_prim_id
,
5946 struct ac_vs_output_info
*outinfo
)
5948 uint32_t param_count
= 0;
5950 unsigned pos_idx
, num_pos_exports
= 0;
5951 struct ac_export_args args
, pos_args
[4] = {};
5952 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
5955 if (ctx
->options
->key
.has_multiview_view_index
) {
5956 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
5958 for(unsigned i
= 0; i
< 4; ++i
)
5959 ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
5960 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5963 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
5964 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
5967 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
5968 sizeof(outinfo
->vs_output_param_offset
));
5970 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
5971 LLVMValueRef slots
[8];
5974 if (outinfo
->cull_dist_mask
)
5975 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
5977 i
= VARYING_SLOT_CLIP_DIST0
;
5978 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
5979 slots
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
5981 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
5982 slots
[i
] = LLVMGetUndef(ctx
->ac
.f32
);
5984 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
5985 target
= V_008DFC_SQ_EXP_POS
+ 3;
5986 si_llvm_init_export_args(ctx
, &slots
[4], 0xf, target
, &args
);
5987 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5988 &args
, sizeof(args
));
5991 target
= V_008DFC_SQ_EXP_POS
+ 2;
5992 si_llvm_init_export_args(ctx
, &slots
[0], 0xf, target
, &args
);
5993 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5994 &args
, sizeof(args
));
5998 LLVMValueRef pos_values
[4] = {ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_0
, ctx
->ac
.f32_1
};
5999 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
6000 for (unsigned j
= 0; j
< 4; j
++)
6001 pos_values
[j
] = radv_load_output(ctx
, VARYING_SLOT_POS
, j
);
6003 si_llvm_init_export_args(ctx
, pos_values
, 0xf, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
6005 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
6006 outinfo
->writes_pointsize
= true;
6007 psize_value
= radv_load_output(ctx
, VARYING_SLOT_PSIZ
, 0);
6010 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
6011 outinfo
->writes_layer
= true;
6012 layer_value
= radv_load_output(ctx
, VARYING_SLOT_LAYER
, 0);
6015 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
6016 outinfo
->writes_viewport_index
= true;
6017 viewport_index_value
= radv_load_output(ctx
, VARYING_SLOT_VIEWPORT
, 0);
6020 if (outinfo
->writes_pointsize
||
6021 outinfo
->writes_layer
||
6022 outinfo
->writes_viewport_index
) {
6023 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
6024 (outinfo
->writes_layer
== true ? 4 : 0));
6025 pos_args
[1].valid_mask
= 0;
6026 pos_args
[1].done
= 0;
6027 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
6028 pos_args
[1].compr
= 0;
6029 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
6030 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
6031 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
6032 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
6034 if (outinfo
->writes_pointsize
== true)
6035 pos_args
[1].out
[0] = psize_value
;
6036 if (outinfo
->writes_layer
== true)
6037 pos_args
[1].out
[2] = layer_value
;
6038 if (outinfo
->writes_viewport_index
== true) {
6039 if (ctx
->options
->chip_class
>= GFX9
) {
6040 /* GFX9 has the layer in out.z[10:0] and the viewport
6041 * index in out.z[19:16].
6043 LLVMValueRef v
= viewport_index_value
;
6044 v
= ac_to_integer(&ctx
->ac
, v
);
6045 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
6046 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6048 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
6049 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
6051 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
6052 pos_args
[1].enabled_channels
|= 1 << 2;
6054 pos_args
[1].out
[3] = viewport_index_value
;
6055 pos_args
[1].enabled_channels
|= 1 << 3;
6059 for (i
= 0; i
< 4; i
++) {
6060 if (pos_args
[i
].out
[0])
6065 for (i
= 0; i
< 4; i
++) {
6066 if (!pos_args
[i
].out
[0])
6069 /* Specify the target we are exporting */
6070 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
6071 if (pos_idx
== num_pos_exports
)
6072 pos_args
[i
].done
= 1;
6073 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
6076 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6077 LLVMValueRef values
[4];
6078 if (!(ctx
->output_mask
& (1ull << i
)))
6081 if (i
!= VARYING_SLOT_LAYER
&&
6082 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
6083 i
< VARYING_SLOT_VAR0
)
6086 for (unsigned j
= 0; j
< 4; j
++)
6087 values
[j
] = ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
6089 unsigned output_usage_mask
;
6091 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
6092 !ctx
->is_gs_copy_shader
) {
6094 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
6095 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6097 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
6099 /* Enable all channels for the GS copy shader because
6100 * we don't know the output usage mask currently.
6102 output_usage_mask
= 0xf;
6105 radv_export_param(ctx
, param_count
, values
, output_usage_mask
);
6107 outinfo
->vs_output_param_offset
[i
] = param_count
++;
6110 if (export_prim_id
) {
6111 LLVMValueRef values
[4];
6113 values
[0] = ctx
->vs_prim_id
;
6114 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
6115 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
6116 for (unsigned j
= 1; j
< 4; j
++)
6117 values
[j
] = ctx
->ac
.f32_0
;
6119 radv_export_param(ctx
, param_count
, values
, 0xf);
6121 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
6122 outinfo
->export_prim_id
= true;
6125 outinfo
->pos_exports
= num_pos_exports
;
6126 outinfo
->param_exports
= param_count
;
6130 handle_es_outputs_post(struct radv_shader_context
*ctx
,
6131 struct ac_es_output_info
*outinfo
)
6134 uint64_t max_output_written
= 0;
6135 LLVMValueRef lds_base
= NULL
;
6137 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6141 if (!(ctx
->output_mask
& (1ull << i
)))
6144 if (i
== VARYING_SLOT_CLIP_DIST0
)
6145 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6147 param_index
= shader_io_get_unique_index(i
);
6149 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
6152 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
6154 if (ctx
->ac
.chip_class
>= GFX9
) {
6155 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
6156 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
6157 LLVMValueRef wave_idx
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6158 LLVMConstInt(ctx
->ac
.i32
, 24, false),
6159 LLVMConstInt(ctx
->ac
.i32
, 4, false), false);
6160 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
6161 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
6162 LLVMConstInt(ctx
->ac
.i32
, 64, false), ""), "");
6163 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
6164 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
6167 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6168 LLVMValueRef dw_addr
= NULL
;
6169 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
6173 if (!(ctx
->output_mask
& (1ull << i
)))
6176 if (i
== VARYING_SLOT_CLIP_DIST0
)
6177 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6179 param_index
= shader_io_get_unique_index(i
);
6182 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
6183 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
6186 for (j
= 0; j
< length
; j
++) {
6187 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
6188 out_val
= LLVMBuildBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
6190 if (ctx
->ac
.chip_class
>= GFX9
) {
6191 ac_lds_store(&ctx
->ac
, dw_addr
,
6192 LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], ""));
6193 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6195 ac_build_buffer_store_dword(&ctx
->ac
,
6198 NULL
, ctx
->es2gs_offset
,
6199 (4 * param_index
+ j
) * 4,
6207 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
6209 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
6210 LLVMValueRef vertex_dw_stride
= unpack_param(&ctx
->ac
, ctx
->ls_out_layout
, 13, 8);
6211 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
6212 vertex_dw_stride
, "");
6214 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6215 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
6218 if (!(ctx
->output_mask
& (1ull << i
)))
6221 if (i
== VARYING_SLOT_CLIP_DIST0
)
6222 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6223 int param
= shader_io_get_unique_index(i
);
6224 mark_tess_output(ctx
, false, param
);
6226 mark_tess_output(ctx
, false, param
+ 1);
6227 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
6228 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
6230 for (unsigned j
= 0; j
< length
; j
++) {
6231 ac_lds_store(&ctx
->ac
, dw_addr
,
6232 LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], ""));
6233 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
6238 struct ac_build_if_state
6240 struct radv_shader_context
*ctx
;
6241 LLVMValueRef condition
;
6242 LLVMBasicBlockRef entry_block
;
6243 LLVMBasicBlockRef true_block
;
6244 LLVMBasicBlockRef false_block
;
6245 LLVMBasicBlockRef merge_block
;
6248 static LLVMBasicBlockRef
6249 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
6251 LLVMBasicBlockRef current_block
;
6252 LLVMBasicBlockRef next_block
;
6253 LLVMBasicBlockRef new_block
;
6255 /* get current basic block */
6256 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
6258 /* chqeck if there's another block after this one */
6259 next_block
= LLVMGetNextBasicBlock(current_block
);
6261 /* insert the new block before the next block */
6262 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
6265 /* append new block after current block */
6266 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
6267 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
6273 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
6274 struct radv_shader_context
*ctx
,
6275 LLVMValueRef condition
)
6277 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
6279 memset(ifthen
, 0, sizeof *ifthen
);
6281 ifthen
->condition
= condition
;
6282 ifthen
->entry_block
= block
;
6284 /* create endif/merge basic block for the phi functions */
6285 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
6287 /* create/insert true_block before merge_block */
6288 ifthen
->true_block
=
6289 LLVMInsertBasicBlockInContext(ctx
->context
,
6290 ifthen
->merge_block
,
6293 /* successive code goes into the true block */
6294 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
6298 * End a conditional.
6301 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
6303 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
6305 /* Insert branch to the merge block from current block */
6306 LLVMBuildBr(builder
, ifthen
->merge_block
);
6309 * Now patch in the various branch instructions.
6312 /* Insert the conditional branch instruction at the end of entry_block */
6313 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
6314 if (ifthen
->false_block
) {
6315 /* we have an else clause */
6316 LLVMBuildCondBr(builder
, ifthen
->condition
,
6317 ifthen
->true_block
, ifthen
->false_block
);
6320 /* no else clause */
6321 LLVMBuildCondBr(builder
, ifthen
->condition
,
6322 ifthen
->true_block
, ifthen
->merge_block
);
6325 /* Resume building code at end of the ifthen->merge_block */
6326 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
6330 write_tess_factors(struct radv_shader_context
*ctx
)
6332 unsigned stride
, outer_comps
, inner_comps
;
6333 struct ac_build_if_state if_ctx
, inner_if_ctx
;
6334 LLVMValueRef invocation_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
6335 LLVMValueRef rel_patch_id
= unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
6336 unsigned tess_inner_index
= 0, tess_outer_index
;
6337 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
6338 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
6340 emit_barrier(&ctx
->ac
, ctx
->stage
);
6342 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
6362 ac_nir_build_if(&if_ctx
, ctx
,
6363 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
6364 invocation_id
, ctx
->ac
.i32_0
, ""));
6366 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
6369 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6370 mark_tess_output(ctx
, true, tess_inner_index
);
6371 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
6372 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
6375 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6376 mark_tess_output(ctx
, true, tess_outer_index
);
6377 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
6378 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
6380 for (i
= 0; i
< 4; i
++) {
6381 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6382 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
6386 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
6387 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
6388 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
6390 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
6392 for (i
= 0; i
< outer_comps
; i
++) {
6394 ac_lds_load(&ctx
->ac
, lds_outer
);
6395 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
6398 for (i
= 0; i
< inner_comps
; i
++) {
6399 inner
[i
] = out
[outer_comps
+i
] =
6400 ac_lds_load(&ctx
->ac
, lds_inner
);
6401 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
6406 /* Convert the outputs to vectors for stores. */
6407 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
6411 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
6414 buffer
= ctx
->hs_ring_tess_factor
;
6415 tf_base
= ctx
->tess_factor_offset
;
6416 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
6417 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
6418 unsigned tf_offset
= 0;
6420 if (ctx
->options
->chip_class
<= VI
) {
6421 ac_nir_build_if(&inner_if_ctx
, ctx
,
6422 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
6423 rel_patch_id
, ctx
->ac
.i32_0
, ""));
6425 /* Store the dynamic HS control word. */
6426 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
6427 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
6428 1, ctx
->ac
.i32_0
, tf_base
,
6429 0, 1, 0, true, false);
6432 ac_nir_build_endif(&inner_if_ctx
);
6435 /* Store the tessellation factors. */
6436 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
6437 MIN2(stride
, 4), byteoffset
, tf_base
,
6438 tf_offset
, 1, 0, true, false);
6440 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
6441 stride
- 4, byteoffset
, tf_base
,
6442 16 + tf_offset
, 1, 0, true, false);
6444 //store to offchip for TES to read - only if TES reads them
6445 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
6446 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
6447 LLVMValueRef tf_inner_offset
;
6448 unsigned param_outer
, param_inner
;
6450 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
6451 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6452 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
6454 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
6455 util_next_power_of_two(outer_comps
));
6457 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
6458 outer_comps
, tf_outer_offset
,
6459 ctx
->oc_lds
, 0, 1, 0, true, false);
6461 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
6462 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
6463 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
6465 inner_vec
= inner_comps
== 1 ? inner
[0] :
6466 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
6467 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
6468 inner_comps
, tf_inner_offset
,
6469 ctx
->oc_lds
, 0, 1, 0, true, false);
6472 ac_nir_build_endif(&if_ctx
);
6476 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
6478 write_tess_factors(ctx
);
6482 si_export_mrt_color(struct radv_shader_context
*ctx
,
6483 LLVMValueRef
*color
, unsigned index
, bool is_last
,
6484 struct ac_export_args
*args
)
6487 si_llvm_init_export_args(ctx
, color
, 0xf,
6488 V_008DFC_SQ_EXP_MRT
+ index
, args
);
6491 args
->valid_mask
= 1; /* whether the EXEC mask is valid */
6492 args
->done
= 1; /* DONE bit */
6493 } else if (!args
->enabled_channels
)
6494 return false; /* unnecessary NULL export */
6500 radv_export_mrt_z(struct radv_shader_context
*ctx
,
6501 LLVMValueRef depth
, LLVMValueRef stencil
,
6502 LLVMValueRef samplemask
)
6504 struct ac_export_args args
;
6506 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
6508 ac_build_export(&ctx
->ac
, &args
);
6512 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
6515 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
6516 struct ac_export_args color_args
[8];
6518 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
6519 LLVMValueRef values
[4];
6522 if (!(ctx
->output_mask
& (1ull << i
)))
6525 if (i
< FRAG_RESULT_DATA0
)
6528 for (unsigned j
= 0; j
< 4; j
++)
6529 values
[j
] = ac_to_float(&ctx
->ac
,
6530 radv_load_output(ctx
, i
, j
));
6532 if (!ctx
->shader_info
->info
.ps
.writes_z
&&
6533 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
6534 !ctx
->shader_info
->info
.ps
.writes_sample_mask
)
6535 last
= ctx
->output_mask
<= ((1ull << (i
+ 1)) - 1);
6537 bool ret
= si_export_mrt_color(ctx
, values
,
6538 i
- FRAG_RESULT_DATA0
,
6539 last
, &color_args
[index
]);
6544 /* Process depth, stencil, samplemask. */
6545 if (ctx
->shader_info
->info
.ps
.writes_z
) {
6546 depth
= ac_to_float(&ctx
->ac
,
6547 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
6549 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
6550 stencil
= ac_to_float(&ctx
->ac
,
6551 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
6553 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
6554 samplemask
= ac_to_float(&ctx
->ac
,
6555 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
6558 /* Export PS outputs. */
6559 for (unsigned i
= 0; i
< index
; i
++)
6560 ac_build_export(&ctx
->ac
, &color_args
[i
]);
6562 if (depth
|| stencil
|| samplemask
)
6563 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
6565 ac_build_export_null(&ctx
->ac
);
6569 emit_gs_epilogue(struct radv_shader_context
*ctx
)
6571 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
6575 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
6576 LLVMValueRef
*addrs
)
6578 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
6580 switch (ctx
->stage
) {
6581 case MESA_SHADER_VERTEX
:
6582 if (ctx
->options
->key
.vs
.as_ls
)
6583 handle_ls_outputs_post(ctx
);
6584 else if (ctx
->options
->key
.vs
.as_es
)
6585 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
6587 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
6588 &ctx
->shader_info
->vs
.outinfo
);
6590 case MESA_SHADER_FRAGMENT
:
6591 handle_fs_outputs_post(ctx
);
6593 case MESA_SHADER_GEOMETRY
:
6594 emit_gs_epilogue(ctx
);
6596 case MESA_SHADER_TESS_CTRL
:
6597 handle_tcs_outputs_post(ctx
);
6599 case MESA_SHADER_TESS_EVAL
:
6600 if (ctx
->options
->key
.tes
.as_es
)
6601 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
6603 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
6604 &ctx
->shader_info
->tes
.outinfo
);
6611 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
)
6613 LLVMPassManagerRef passmgr
;
6614 /* Create the pass manager */
6615 passmgr
= LLVMCreateFunctionPassManagerForModule(
6618 /* This pass should eliminate all the load and store instructions */
6619 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
6621 /* Add some optimization passes */
6622 LLVMAddScalarReplAggregatesPass(passmgr
);
6623 LLVMAddLICMPass(passmgr
);
6624 LLVMAddAggressiveDCEPass(passmgr
);
6625 LLVMAddCFGSimplificationPass(passmgr
);
6626 LLVMAddInstructionCombiningPass(passmgr
);
6629 LLVMInitializeFunctionPassManager(passmgr
);
6630 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6631 LLVMFinalizeFunctionPassManager(passmgr
);
6633 LLVMDisposeBuilder(ctx
->ac
.builder
);
6634 LLVMDisposePassManager(passmgr
);
6638 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
6640 struct ac_vs_output_info
*outinfo
;
6642 switch (ctx
->stage
) {
6643 case MESA_SHADER_FRAGMENT
:
6644 case MESA_SHADER_COMPUTE
:
6645 case MESA_SHADER_TESS_CTRL
:
6646 case MESA_SHADER_GEOMETRY
:
6648 case MESA_SHADER_VERTEX
:
6649 if (ctx
->options
->key
.vs
.as_ls
||
6650 ctx
->options
->key
.vs
.as_es
)
6652 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6654 case MESA_SHADER_TESS_EVAL
:
6655 if (ctx
->options
->key
.vs
.as_es
)
6657 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6660 unreachable("Unhandled shader type");
6663 ac_optimize_vs_outputs(&ctx
->ac
,
6665 outinfo
->vs_output_param_offset
,
6667 &outinfo
->param_exports
);
6671 ac_setup_rings(struct radv_shader_context
*ctx
)
6673 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6674 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6675 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_VS
, false));
6678 if (ctx
->is_gs_copy_shader
) {
6679 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_VS
, false));
6681 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6683 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_ESGS_GS
, false));
6684 ctx
->gsvs_ring
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_GSVS_GS
, false));
6686 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->ac
.v4i32
, "");
6688 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
6689 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, ctx
->ac
.i32_1
, "");
6690 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6691 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ctx
->gsvs_ring
, tmp
, ctx
->ac
.i32_1
, "");
6694 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6695 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6696 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
6697 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
6702 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6703 const struct nir_shader
*nir
)
6705 switch (nir
->info
.stage
) {
6706 case MESA_SHADER_TESS_CTRL
:
6707 return chip_class
>= CIK
? 128 : 64;
6708 case MESA_SHADER_GEOMETRY
:
6709 return chip_class
>= GFX9
? 128 : 64;
6710 case MESA_SHADER_COMPUTE
:
6716 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6717 nir
->info
.cs
.local_size
[1] *
6718 nir
->info
.cs
.local_size
[2];
6719 return max_workgroup_size
;
6722 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6723 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
6725 LLVMValueRef count
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6726 LLVMConstInt(ctx
->ac
.i32
, 8, false),
6727 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6728 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
6730 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
6731 ctx
->vs_prim_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.vertex_id
, ctx
->vs_prim_id
, "");
6732 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
6733 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
6736 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
6738 for(int i
= 5; i
>= 0; --i
) {
6739 ctx
->gs_vtx_offset
[i
] = ac_build_bfe(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
6740 LLVMConstInt(ctx
->ac
.i32
, (i
& 1) * 16, false),
6741 LLVMConstInt(ctx
->ac
.i32
, 16, false), false);
6744 ctx
->gs_wave_id
= ac_build_bfe(&ctx
->ac
, ctx
->merged_wave_info
,
6745 LLVMConstInt(ctx
->ac
.i32
, 16, false),
6746 LLVMConstInt(ctx
->ac
.i32
, 8, false), false);
6749 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6750 struct nir_shader
*nir
)
6752 struct ac_nir_context ctx
= {};
6753 struct nir_function
*func
;
6755 /* Last minute passes for both radv & radeonsi */
6756 ac_lower_subgroups(nir
);
6761 ctx
.stage
= nir
->info
.stage
;
6763 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6765 nir_foreach_variable(variable
, &nir
->outputs
)
6766 handle_shader_output_decl(&ctx
, nir
, variable
);
6768 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6769 _mesa_key_pointer_equal
);
6770 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6771 _mesa_key_pointer_equal
);
6772 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6773 _mesa_key_pointer_equal
);
6775 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6777 setup_locals(&ctx
, func
);
6779 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
6780 setup_shared(&ctx
, nir
);
6782 visit_cf_list(&ctx
, &func
->impl
->body
);
6783 phi_post_pass(&ctx
);
6785 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
6786 ctx
.abi
->emit_outputs(ctx
.abi
, AC_LLVM_MAX_OUTPUTS
,
6790 ralloc_free(ctx
.defs
);
6791 ralloc_free(ctx
.phis
);
6792 ralloc_free(ctx
.vars
);
6796 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6797 struct nir_shader
*const *shaders
,
6799 struct ac_shader_variant_info
*shader_info
,
6800 const struct ac_nir_compiler_options
*options
,
6803 struct radv_shader_context ctx
= {0};
6805 ctx
.options
= options
;
6806 ctx
.shader_info
= shader_info
;
6807 ctx
.context
= LLVMContextCreate();
6809 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
6811 ctx
.ac
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6812 LLVMSetTarget(ctx
.ac
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6814 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6815 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6816 LLVMSetDataLayout(ctx
.ac
.module
, data_layout_str
);
6817 LLVMDisposeTargetData(data_layout
);
6818 LLVMDisposeMessage(data_layout_str
);
6820 enum ac_float_mode float_mode
=
6821 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
6822 AC_FLOAT_MODE_DEFAULT
;
6824 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
6826 memset(shader_info
, 0, sizeof(*shader_info
));
6828 for(int i
= 0; i
< shader_count
; ++i
)
6829 ac_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
6831 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6832 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6833 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6834 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6836 ctx
.max_workgroup_size
= 0;
6837 for (int i
= 0; i
< shader_count
; ++i
) {
6838 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
6839 ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
6843 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
6844 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
6846 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6847 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6848 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
6849 ctx
.abi
.load_ubo
= radv_load_ubo
;
6850 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
6851 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
6852 ctx
.abi
.load_resource
= radv_load_resource
;
6853 ctx
.abi
.clamp_shadow_reference
= false;
6855 if (shader_count
>= 2)
6856 ac_init_exec_full_mask(&ctx
.ac
);
6858 if (ctx
.ac
.chip_class
== GFX9
&&
6859 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
6860 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
6862 for(int i
= 0; i
< shader_count
; ++i
) {
6863 ctx
.stage
= shaders
[i
]->info
.stage
;
6864 ctx
.output_mask
= 0;
6865 ctx
.tess_outputs_written
= 0;
6866 ctx
.num_output_clips
= shaders
[i
]->info
.clip_distance_array_size
;
6867 ctx
.num_output_culls
= shaders
[i
]->info
.cull_distance_array_size
;
6869 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6870 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "gs_next_vertex");
6871 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
6872 ctx
.abi
.load_inputs
= load_gs_input
;
6873 ctx
.abi
.emit_primitive
= visit_end_primitive
;
6874 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6875 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
6876 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
6877 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
6878 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6879 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
6880 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
6881 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
6882 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
6883 ctx
.abi
.load_tess_varyings
= load_tes_input
;
6884 ctx
.abi
.load_tess_coord
= load_tess_coord
;
6885 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
6886 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
6887 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
6888 if (shader_info
->info
.vs
.needs_instance_id
) {
6889 if (ctx
.options
->key
.vs
.as_ls
) {
6890 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6891 MAX2(2, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6893 ctx
.shader_info
->vs
.vgpr_comp_cnt
=
6894 MAX2(1, ctx
.shader_info
->vs
.vgpr_comp_cnt
);
6897 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
6898 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
6899 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
6900 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
6901 ctx
.abi
.load_sample_position
= load_sample_position
;
6902 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
6906 emit_barrier(&ctx
.ac
, ctx
.stage
);
6908 ac_setup_rings(&ctx
);
6910 LLVMBasicBlockRef merge_block
;
6911 if (shader_count
>= 2) {
6912 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6913 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6914 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
6916 LLVMValueRef count
= ac_build_bfe(&ctx
.ac
, ctx
.merged_wave_info
,
6917 LLVMConstInt(ctx
.ac
.i32
, 8 * i
, false),
6918 LLVMConstInt(ctx
.ac
.i32
, 8, false), false);
6919 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
6920 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
6921 thread_id
, count
, "");
6922 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
6924 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
6927 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
6928 handle_fs_inputs(&ctx
, shaders
[i
]);
6929 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
6930 handle_vs_inputs(&ctx
, shaders
[i
]);
6931 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
6932 prepare_gs_input_vgprs(&ctx
);
6934 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
6935 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
6937 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
6939 if (shader_count
>= 2) {
6940 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
6941 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
6944 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
6945 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
6946 shaders
[i
]->info
.cull_distance_array_size
> 4;
6947 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6948 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6949 shaders
[i
]->info
.gs
.vertices_out
;
6950 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
6951 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6952 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6953 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6954 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6958 LLVMBuildRetVoid(ctx
.ac
.builder
);
6960 if (options
->dump_preoptir
)
6961 ac_dump_module(ctx
.ac
.module
);
6963 ac_llvm_finalize_module(&ctx
);
6965 if (shader_count
== 1)
6966 ac_nir_eliminate_const_vs_outputs(&ctx
);
6969 ctx
.shader_info
->private_mem_vgprs
=
6970 ac_count_scratch_private_memory(ctx
.main_function
);
6973 return ctx
.ac
.module
;
6976 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
6978 unsigned *retval
= (unsigned *)context
;
6979 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
6980 char *description
= LLVMGetDiagInfoDescription(di
);
6982 if (severity
== LLVMDSError
) {
6984 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
6988 LLVMDisposeMessage(description
);
6991 static unsigned ac_llvm_compile(LLVMModuleRef M
,
6992 struct ac_shader_binary
*binary
,
6993 LLVMTargetMachineRef tm
)
6995 unsigned retval
= 0;
6997 LLVMContextRef llvm_ctx
;
6998 LLVMMemoryBufferRef out_buffer
;
6999 unsigned buffer_size
;
7000 const char *buffer_data
;
7003 /* Setup Diagnostic Handler*/
7004 llvm_ctx
= LLVMGetModuleContext(M
);
7006 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
7010 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
7013 /* Process Errors/Warnings */
7015 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
7021 /* Extract Shader Code*/
7022 buffer_size
= LLVMGetBufferSize(out_buffer
);
7023 buffer_data
= LLVMGetBufferStart(out_buffer
);
7025 ac_elf_read(buffer_data
, buffer_size
, binary
);
7028 LLVMDisposeMemoryBuffer(out_buffer
);
7034 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
7035 LLVMModuleRef llvm_module
,
7036 struct ac_shader_binary
*binary
,
7037 struct ac_shader_config
*config
,
7038 struct ac_shader_variant_info
*shader_info
,
7039 gl_shader_stage stage
,
7040 bool dump_shader
, bool supports_spill
)
7043 ac_dump_module(llvm_module
);
7045 memset(binary
, 0, sizeof(*binary
));
7046 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
7048 fprintf(stderr
, "compile failed\n");
7052 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
7054 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
7056 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
7057 LLVMDisposeModule(llvm_module
);
7058 LLVMContextDispose(ctx
);
7060 if (stage
== MESA_SHADER_FRAGMENT
) {
7061 shader_info
->num_input_vgprs
= 0;
7062 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
7063 shader_info
->num_input_vgprs
+= 2;
7064 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
7065 shader_info
->num_input_vgprs
+= 2;
7066 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
7067 shader_info
->num_input_vgprs
+= 2;
7068 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
7069 shader_info
->num_input_vgprs
+= 3;
7070 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
7071 shader_info
->num_input_vgprs
+= 2;
7072 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
7073 shader_info
->num_input_vgprs
+= 2;
7074 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
7075 shader_info
->num_input_vgprs
+= 2;
7076 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
7077 shader_info
->num_input_vgprs
+= 1;
7078 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
7079 shader_info
->num_input_vgprs
+= 1;
7080 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
7081 shader_info
->num_input_vgprs
+= 1;
7082 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
7083 shader_info
->num_input_vgprs
+= 1;
7084 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
7085 shader_info
->num_input_vgprs
+= 1;
7086 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
7087 shader_info
->num_input_vgprs
+= 1;
7088 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
7089 shader_info
->num_input_vgprs
+= 1;
7090 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
7091 shader_info
->num_input_vgprs
+= 1;
7092 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
7093 shader_info
->num_input_vgprs
+= 1;
7095 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
7097 /* +3 for scratch wave offset and VCC */
7098 config
->num_sgprs
= MAX2(config
->num_sgprs
,
7099 shader_info
->num_input_sgprs
+ 3);
7101 /* Enable 64-bit and 16-bit denormals, because there is no performance
7104 * If denormals are enabled, all floating-point output modifiers are
7107 * Don't enable denormals for 32-bit floats, because:
7108 * - Floating-point output modifiers would be ignored by the hw.
7109 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7110 * have to stop using those.
7111 * - SI & CI would be very slow.
7113 config
->float_mode
|= V_00B028_FP_64_DENORMS
;
7117 ac_fill_shader_info(struct ac_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct ac_nir_compiler_options
*options
)
7119 switch (nir
->info
.stage
) {
7120 case MESA_SHADER_COMPUTE
:
7121 for (int i
= 0; i
< 3; ++i
)
7122 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
7124 case MESA_SHADER_FRAGMENT
:
7125 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
7127 case MESA_SHADER_GEOMETRY
:
7128 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
7129 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
7130 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
7131 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
7133 case MESA_SHADER_TESS_EVAL
:
7134 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
7135 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
7136 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
7137 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
7138 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
7140 case MESA_SHADER_TESS_CTRL
:
7141 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
7143 case MESA_SHADER_VERTEX
:
7144 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
7145 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
7146 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7147 if (options
->key
.vs
.as_ls
)
7148 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
7155 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
7156 struct ac_shader_binary
*binary
,
7157 struct ac_shader_config
*config
,
7158 struct ac_shader_variant_info
*shader_info
,
7159 struct nir_shader
*const *nir
,
7161 const struct ac_nir_compiler_options
*options
,
7165 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, nir_count
, shader_info
,
7166 options
, dump_shader
);
7168 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
[0]->info
.stage
, dump_shader
, options
->supports_spill
);
7169 for (int i
= 0; i
< nir_count
; ++i
)
7170 ac_fill_shader_info(shader_info
, nir
[i
], options
);
7172 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7173 if (options
->chip_class
== GFX9
) {
7174 if (nir_count
== 2 &&
7175 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
7176 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
7182 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
7184 LLVMValueRef vtx_offset
=
7185 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
7186 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
7189 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
7193 if (!(ctx
->output_mask
& (1ull << i
)))
7196 if (i
== VARYING_SLOT_CLIP_DIST0
) {
7197 /* unpack clip and cull from a single set of slots */
7198 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
7203 for (unsigned j
= 0; j
< length
; j
++) {
7204 LLVMValueRef value
, soffset
;
7206 soffset
= LLVMConstInt(ctx
->ac
.i32
,
7208 ctx
->gs_max_out_vertices
* 16 * 4, false);
7210 value
= ac_build_buffer_load(&ctx
->ac
, ctx
->gsvs_ring
,
7212 vtx_offset
, soffset
,
7213 0, 1, 1, true, false);
7215 LLVMBuildStore(ctx
->ac
.builder
,
7216 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
7220 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
7223 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
7224 struct nir_shader
*geom_shader
,
7225 struct ac_shader_binary
*binary
,
7226 struct ac_shader_config
*config
,
7227 struct ac_shader_variant_info
*shader_info
,
7228 const struct ac_nir_compiler_options
*options
,
7231 struct radv_shader_context ctx
= {0};
7232 ctx
.context
= LLVMContextCreate();
7233 ctx
.options
= options
;
7234 ctx
.shader_info
= shader_info
;
7236 ac_llvm_context_init(&ctx
.ac
, ctx
.context
, options
->chip_class
,
7238 ctx
.ac
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
7240 ctx
.is_gs_copy_shader
= true;
7241 LLVMSetTarget(ctx
.ac
.module
, "amdgcn--");
7243 enum ac_float_mode float_mode
=
7244 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
7245 AC_FLOAT_MODE_DEFAULT
;
7247 ctx
.ac
.builder
= ac_create_builder(ctx
.context
, float_mode
);
7248 ctx
.stage
= MESA_SHADER_VERTEX
;
7250 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
7252 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
7253 ac_setup_rings(&ctx
);
7255 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
7256 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
7258 struct ac_nir_context nir_ctx
= {};
7259 nir_ctx
.ac
= ctx
.ac
;
7260 nir_ctx
.abi
= &ctx
.abi
;
7262 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
7263 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
7264 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
7267 ac_gs_copy_shader_emit(&ctx
);
7269 LLVMBuildRetVoid(ctx
.ac
.builder
);
7271 ac_llvm_finalize_module(&ctx
);
7273 ac_compile_llvm_module(tm
, ctx
.ac
.module
, binary
, config
, shader_info
,
7275 dump_shader
, options
->supports_spill
);
7279 ac_lower_indirect_derefs(struct nir_shader
*nir
, enum chip_class chip_class
)
7281 /* While it would be nice not to have this flag, we are constrained
7282 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
7285 bool llvm_has_working_vgpr_indexing
= chip_class
<= VI
;
7287 /* TODO: Indirect indexing of GS inputs is unimplemented.
7289 * TCS and TES load inputs directly from LDS or offchip memory, so
7290 * indirect indexing is trivial.
7292 nir_variable_mode indirect_mask
= 0;
7293 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
||
7294 (nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
&&
7295 nir
->info
.stage
!= MESA_SHADER_TESS_EVAL
&&
7296 !llvm_has_working_vgpr_indexing
)) {
7297 indirect_mask
|= nir_var_shader_in
;
7299 if (!llvm_has_working_vgpr_indexing
&&
7300 nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
)
7301 indirect_mask
|= nir_var_shader_out
;
7303 /* TODO: We shouldn't need to do this, however LLVM isn't currently
7304 * smart enough to handle indirects without causing excess spilling
7305 * causing the gpu to hang.
7307 * See the following thread for more details of the problem:
7308 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
7310 indirect_mask
|= nir_var_local
;
7312 nir_lower_indirect_derefs(nir
, indirect_mask
);