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ac: make use of if/loop build helpers
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 uint32_t tcs_vertices_per_patch;
131 };
132
133 static inline struct radv_shader_context *
134 radv_shader_context_from_abi(struct ac_shader_abi *abi)
135 {
136 struct radv_shader_context *ctx = NULL;
137 return container_of(abi, ctx, abi);
138 }
139
140 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
141 const nir_deref_var *deref,
142 enum ac_descriptor_type desc_type,
143 const nir_tex_instr *instr,
144 bool image, bool write);
145
146 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
147 {
148 return (index * 4) + chan;
149 }
150
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
152 {
153 /* handle patch indices separate */
154 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
155 return 0;
156 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
157 return 1;
158 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
159 return 2 + (slot - VARYING_SLOT_PATCH0);
160
161 if (slot == VARYING_SLOT_POS)
162 return 0;
163 if (slot == VARYING_SLOT_PSIZ)
164 return 1;
165 if (slot == VARYING_SLOT_CLIP_DIST0)
166 return 2;
167 /* 3 is reserved for clip dist as well */
168 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
169 return 4 + (slot - VARYING_SLOT_VAR0);
170 unreachable("illegal slot in get unique index\n");
171 }
172
173 static void set_llvm_calling_convention(LLVMValueRef func,
174 gl_shader_stage stage)
175 {
176 enum radeon_llvm_calling_convention calling_conv;
177
178 switch (stage) {
179 case MESA_SHADER_VERTEX:
180 case MESA_SHADER_TESS_EVAL:
181 calling_conv = RADEON_LLVM_AMDGPU_VS;
182 break;
183 case MESA_SHADER_GEOMETRY:
184 calling_conv = RADEON_LLVM_AMDGPU_GS;
185 break;
186 case MESA_SHADER_TESS_CTRL:
187 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
188 break;
189 case MESA_SHADER_FRAGMENT:
190 calling_conv = RADEON_LLVM_AMDGPU_PS;
191 break;
192 case MESA_SHADER_COMPUTE:
193 calling_conv = RADEON_LLVM_AMDGPU_CS;
194 break;
195 default:
196 unreachable("Unhandle shader type");
197 }
198
199 LLVMSetFunctionCallConv(func, calling_conv);
200 }
201
202 #define MAX_ARGS 23
203 struct arg_info {
204 LLVMTypeRef types[MAX_ARGS];
205 LLVMValueRef *assign[MAX_ARGS];
206 unsigned array_params_mask;
207 uint8_t count;
208 uint8_t sgpr_count;
209 uint8_t num_sgprs_used;
210 uint8_t num_vgprs_used;
211 };
212
213 enum ac_arg_regfile {
214 ARG_SGPR,
215 ARG_VGPR,
216 };
217
218 static void
219 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
220 LLVMValueRef *param_ptr)
221 {
222 assert(info->count < MAX_ARGS);
223
224 info->assign[info->count] = param_ptr;
225 info->types[info->count] = type;
226 info->count++;
227
228 if (regfile == ARG_SGPR) {
229 info->num_sgprs_used += ac_get_type_size(type) / 4;
230 info->sgpr_count++;
231 } else {
232 assert(regfile == ARG_VGPR);
233 info->num_vgprs_used += ac_get_type_size(type) / 4;
234 }
235 }
236
237 static inline void
238 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
239 {
240 info->array_params_mask |= (1 << info->count);
241 add_arg(info, ARG_SGPR, type, param_ptr);
242 }
243
244 static void assign_arguments(LLVMValueRef main_function,
245 struct arg_info *info)
246 {
247 unsigned i;
248 for (i = 0; i < info->count; i++) {
249 if (info->assign[i])
250 *info->assign[i] = LLVMGetParam(main_function, i);
251 }
252 }
253
254 static LLVMValueRef
255 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
256 LLVMBuilderRef builder, LLVMTypeRef *return_types,
257 unsigned num_return_elems,
258 struct arg_info *args,
259 unsigned max_workgroup_size,
260 bool unsafe_math)
261 {
262 LLVMTypeRef main_function_type, ret_type;
263 LLVMBasicBlockRef main_function_body;
264
265 if (num_return_elems)
266 ret_type = LLVMStructTypeInContext(ctx, return_types,
267 num_return_elems, true);
268 else
269 ret_type = LLVMVoidTypeInContext(ctx);
270
271 /* Setup the function */
272 main_function_type =
273 LLVMFunctionType(ret_type, args->types, args->count, 0);
274 LLVMValueRef main_function =
275 LLVMAddFunction(module, "main", main_function_type);
276 main_function_body =
277 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
278 LLVMPositionBuilderAtEnd(builder, main_function_body);
279
280 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
281 for (unsigned i = 0; i < args->sgpr_count; ++i) {
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
283
284 if (args->array_params_mask & (1 << i)) {
285 LLVMValueRef P = LLVMGetParam(main_function, i);
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
287 ac_add_attr_dereferenceable(P, UINT64_MAX);
288 }
289 }
290
291 if (max_workgroup_size) {
292 ac_llvm_add_target_dep_function_attr(main_function,
293 "amdgpu-max-work-group-size",
294 max_workgroup_size);
295 }
296 if (unsafe_math) {
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "less-precise-fpmad",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "no-infs-fp-math",
303 "true");
304 LLVMAddTargetDependentFunctionAttr(main_function,
305 "no-nans-fp-math",
306 "true");
307 LLVMAddTargetDependentFunctionAttr(main_function,
308 "unsafe-fp-math",
309 "true");
310 LLVMAddTargetDependentFunctionAttr(main_function,
311 "no-signed-zeros-fp-math",
312 "true");
313 }
314 return main_function;
315 }
316
317 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
318 LLVMValueRef param, unsigned rshift,
319 unsigned bitwidth)
320 {
321 LLVMValueRef value = param;
322 if (rshift)
323 value = LLVMBuildLShr(ctx->builder, value,
324 LLVMConstInt(ctx->i32, rshift, false), "");
325
326 if (rshift + bitwidth < 32) {
327 unsigned mask = (1 << bitwidth) - 1;
328 value = LLVMBuildAnd(ctx->builder, value,
329 LLVMConstInt(ctx->i32, mask, false), "");
330 }
331 return value;
332 }
333
334 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
335 {
336 switch (ctx->stage) {
337 case MESA_SHADER_TESS_CTRL:
338 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
339 case MESA_SHADER_TESS_EVAL:
340 return ctx->tes_rel_patch_id;
341 break;
342 default:
343 unreachable("Illegal stage");
344 }
345 }
346
347 /* Tessellation shaders pass outputs to the next shader using LDS.
348 *
349 * LS outputs = TCS inputs
350 * TCS outputs = TES inputs
351 *
352 * The LDS layout is:
353 * - TCS inputs for patch 0
354 * - TCS inputs for patch 1
355 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
356 * - ...
357 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
358 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
359 * - TCS outputs for patch 1
360 * - Per-patch TCS outputs for patch 1
361 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
362 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
363 * - ...
364 *
365 * All three shaders VS(LS), TCS, TES share the same LDS space.
366 */
367 static LLVMValueRef
368 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
369 {
370 if (ctx->stage == MESA_SHADER_VERTEX)
371 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
372 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
373 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
374 else {
375 assert(0);
376 return NULL;
377 }
378 }
379
380 static LLVMValueRef
381 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
382 {
383 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
384 }
385
386 static LLVMValueRef
387 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
388 {
389 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
390 }
391
392 static LLVMValueRef
393 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
394 {
395 return LLVMBuildMul(ctx->ac.builder,
396 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
397 LLVMConstInt(ctx->ac.i32, 4, false), "");
398 }
399
400 static LLVMValueRef
401 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
402 {
403 return LLVMBuildMul(ctx->ac.builder,
404 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
405 LLVMConstInt(ctx->ac.i32, 4, false), "");
406 }
407
408 static LLVMValueRef
409 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
410 {
411 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
412 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
413
414 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
415 }
416
417 static LLVMValueRef
418 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
419 {
420 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
421 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
422 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
423
424 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
425 LLVMBuildMul(ctx->ac.builder, patch_stride,
426 rel_patch_id, ""),
427 "");
428 }
429
430 static LLVMValueRef
431 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
432 {
433 LLVMValueRef patch0_patch_data_offset =
434 get_tcs_out_patch0_patch_data_offset(ctx);
435 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
436 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
437
438 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
439 LLVMBuildMul(ctx->ac.builder, patch_stride,
440 rel_patch_id, ""),
441 "");
442 }
443
444 static void
445 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
446 uint32_t indirect_offset)
447 {
448 ud_info->sgpr_idx = *sgpr_idx;
449 ud_info->num_sgprs = num_sgprs;
450 ud_info->indirect = indirect_offset > 0;
451 ud_info->indirect_offset = indirect_offset;
452 *sgpr_idx += num_sgprs;
453 }
454
455 static void
456 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
457 uint8_t num_sgprs)
458 {
459 struct ac_userdata_info *ud_info =
460 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
461 assert(ud_info);
462
463 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
464 }
465
466 static void
467 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
468 uint32_t indirect_offset)
469 {
470 struct ac_userdata_info *ud_info =
471 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
472 assert(ud_info);
473
474 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
475 }
476
477 struct user_sgpr_info {
478 bool need_ring_offsets;
479 uint8_t sgpr_count;
480 bool indirect_all_descriptor_sets;
481 };
482
483 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
484 gl_shader_stage stage)
485 {
486 switch (stage) {
487 case MESA_SHADER_VERTEX:
488 if (ctx->shader_info->info.needs_multiview_view_index ||
489 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
490 return true;
491 break;
492 case MESA_SHADER_TESS_EVAL:
493 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
494 return true;
495 break;
496 case MESA_SHADER_GEOMETRY:
497 case MESA_SHADER_TESS_CTRL:
498 if (ctx->shader_info->info.needs_multiview_view_index)
499 return true;
500 break;
501 default:
502 break;
503 }
504 return false;
505 }
506
507 static uint8_t
508 count_vs_user_sgprs(struct radv_shader_context *ctx)
509 {
510 uint8_t count = 0;
511
512 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
513 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
514
515 return count;
516 }
517
518 static void allocate_user_sgprs(struct radv_shader_context *ctx,
519 gl_shader_stage stage,
520 bool has_previous_stage,
521 gl_shader_stage previous_stage,
522 bool needs_view_index,
523 struct user_sgpr_info *user_sgpr_info)
524 {
525 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
526
527 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
528 if (stage == MESA_SHADER_GEOMETRY ||
529 stage == MESA_SHADER_VERTEX ||
530 stage == MESA_SHADER_TESS_CTRL ||
531 stage == MESA_SHADER_TESS_EVAL ||
532 ctx->is_gs_copy_shader)
533 user_sgpr_info->need_ring_offsets = true;
534
535 if (stage == MESA_SHADER_FRAGMENT &&
536 ctx->shader_info->info.ps.needs_sample_positions)
537 user_sgpr_info->need_ring_offsets = true;
538
539 /* 2 user sgprs will nearly always be allocated for scratch/rings */
540 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
541 user_sgpr_info->sgpr_count += 2;
542 }
543
544 switch (stage) {
545 case MESA_SHADER_COMPUTE:
546 if (ctx->shader_info->info.cs.uses_grid_size)
547 user_sgpr_info->sgpr_count += 3;
548 break;
549 case MESA_SHADER_FRAGMENT:
550 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
551 break;
552 case MESA_SHADER_VERTEX:
553 if (!ctx->is_gs_copy_shader)
554 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
555 if (ctx->options->key.vs.as_ls)
556 user_sgpr_info->sgpr_count++;
557 break;
558 case MESA_SHADER_TESS_CTRL:
559 if (has_previous_stage) {
560 if (previous_stage == MESA_SHADER_VERTEX)
561 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
562 user_sgpr_info->sgpr_count++;
563 }
564 user_sgpr_info->sgpr_count += 4;
565 break;
566 case MESA_SHADER_TESS_EVAL:
567 user_sgpr_info->sgpr_count += 1;
568 break;
569 case MESA_SHADER_GEOMETRY:
570 if (has_previous_stage) {
571 if (previous_stage == MESA_SHADER_VERTEX) {
572 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
573 } else {
574 user_sgpr_info->sgpr_count++;
575 }
576 }
577 user_sgpr_info->sgpr_count += 2;
578 break;
579 default:
580 break;
581 }
582
583 if (needs_view_index)
584 user_sgpr_info->sgpr_count++;
585
586 if (ctx->shader_info->info.loads_push_constants)
587 user_sgpr_info->sgpr_count += 2;
588
589 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
590 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
591
592 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
593 user_sgpr_info->sgpr_count += 2;
594 user_sgpr_info->indirect_all_descriptor_sets = true;
595 } else {
596 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
597 }
598 }
599
600 static void
601 declare_global_input_sgprs(struct radv_shader_context *ctx,
602 gl_shader_stage stage,
603 bool has_previous_stage,
604 gl_shader_stage previous_stage,
605 const struct user_sgpr_info *user_sgpr_info,
606 struct arg_info *args,
607 LLVMValueRef *desc_sets)
608 {
609 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
610 unsigned num_sets = ctx->options->layout ?
611 ctx->options->layout->num_sets : 0;
612 unsigned stage_mask = 1 << stage;
613
614 if (has_previous_stage)
615 stage_mask |= 1 << previous_stage;
616
617 /* 1 for each descriptor set */
618 if (!user_sgpr_info->indirect_all_descriptor_sets) {
619 for (unsigned i = 0; i < num_sets; ++i) {
620 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
621 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
622 add_array_arg(args, type,
623 &ctx->descriptor_sets[i]);
624 }
625 }
626 } else {
627 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
628 }
629
630 if (ctx->shader_info->info.loads_push_constants) {
631 /* 1 for push constants and dynamic descriptors */
632 add_array_arg(args, type, &ctx->abi.push_constants);
633 }
634 }
635
636 static void
637 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
638 gl_shader_stage stage,
639 bool has_previous_stage,
640 gl_shader_stage previous_stage,
641 struct arg_info *args)
642 {
643 if (!ctx->is_gs_copy_shader &&
644 (stage == MESA_SHADER_VERTEX ||
645 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
646 if (ctx->shader_info->info.vs.has_vertex_buffers) {
647 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
648 &ctx->vertex_buffers);
649 }
650 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
651 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
652 if (ctx->shader_info->info.vs.needs_draw_id) {
653 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
654 }
655 }
656 }
657
658 static void
659 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
660 {
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
662 if (!ctx->is_gs_copy_shader) {
663 if (ctx->options->key.vs.as_ls) {
664 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
665 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
666 } else {
667 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
668 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
669 }
670 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
671 }
672 }
673
674 static void
675 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
676 {
677 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
678 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
679 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
681 }
682
683 static void
684 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
685 bool has_previous_stage, gl_shader_stage previous_stage,
686 const struct user_sgpr_info *user_sgpr_info,
687 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
688 {
689 unsigned num_sets = ctx->options->layout ?
690 ctx->options->layout->num_sets : 0;
691 unsigned stage_mask = 1 << stage;
692
693 if (has_previous_stage)
694 stage_mask |= 1 << previous_stage;
695
696 if (!user_sgpr_info->indirect_all_descriptor_sets) {
697 for (unsigned i = 0; i < num_sets; ++i) {
698 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
699 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
700 set_loc_desc(ctx, i, user_sgpr_idx, 0);
701 } else
702 ctx->descriptor_sets[i] = NULL;
703 }
704 } else {
705 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
706 user_sgpr_idx, 2);
707
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
710 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
712 ctx->descriptor_sets[i] =
713 ac_build_load_to_sgpr(&ctx->ac,
714 desc_sets,
715 LLVMConstInt(ctx->ac.i32, i, false));
716
717 } else
718 ctx->descriptor_sets[i] = NULL;
719 }
720 ctx->shader_info->need_indirect_descriptor_sets = true;
721 }
722
723 if (ctx->shader_info->info.loads_push_constants) {
724 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
725 }
726 }
727
728 static void
729 set_vs_specific_input_locs(struct radv_shader_context *ctx,
730 gl_shader_stage stage, bool has_previous_stage,
731 gl_shader_stage previous_stage,
732 uint8_t *user_sgpr_idx)
733 {
734 if (!ctx->is_gs_copy_shader &&
735 (stage == MESA_SHADER_VERTEX ||
736 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
737 if (ctx->shader_info->info.vs.has_vertex_buffers) {
738 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
739 user_sgpr_idx, 2);
740 }
741
742 unsigned vs_num = 2;
743 if (ctx->shader_info->info.vs.needs_draw_id)
744 vs_num++;
745
746 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
747 user_sgpr_idx, vs_num);
748 }
749 }
750
751 static void create_function(struct radv_shader_context *ctx,
752 gl_shader_stage stage,
753 bool has_previous_stage,
754 gl_shader_stage previous_stage)
755 {
756 uint8_t user_sgpr_idx;
757 struct user_sgpr_info user_sgpr_info;
758 struct arg_info args = {};
759 LLVMValueRef desc_sets;
760 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
761 allocate_user_sgprs(ctx, stage, has_previous_stage,
762 previous_stage, needs_view_index, &user_sgpr_info);
763
764 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
765 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
766 &ctx->ring_offsets);
767 }
768
769 switch (stage) {
770 case MESA_SHADER_COMPUTE:
771 declare_global_input_sgprs(ctx, stage, has_previous_stage,
772 previous_stage, &user_sgpr_info,
773 &args, &desc_sets);
774
775 if (ctx->shader_info->info.cs.uses_grid_size) {
776 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
777 &ctx->abi.num_work_groups);
778 }
779
780 for (int i = 0; i < 3; i++) {
781 ctx->abi.workgroup_ids[i] = NULL;
782 if (ctx->shader_info->info.cs.uses_block_id[i]) {
783 add_arg(&args, ARG_SGPR, ctx->ac.i32,
784 &ctx->abi.workgroup_ids[i]);
785 }
786 }
787
788 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
789 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
790 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
791 &ctx->abi.local_invocation_ids);
792 break;
793 case MESA_SHADER_VERTEX:
794 declare_global_input_sgprs(ctx, stage, has_previous_stage,
795 previous_stage, &user_sgpr_info,
796 &args, &desc_sets);
797 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &args);
799
800 if (needs_view_index)
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->abi.view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (needs_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->abi.view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->abi.tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (needs_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->abi.view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->abi.tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (needs_view_index)
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->abi.view_index);
892
893 if (ctx->options->key.tes.as_es) {
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->es2gs_offset);
898 } else {
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 }
902 declare_tes_input_vgprs(ctx, &args);
903 break;
904 case MESA_SHADER_GEOMETRY:
905 if (has_previous_stage) {
906 // First 6 system regs
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->gs2vs_offset);
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->merged_wave_info);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
912
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
916
917 declare_global_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &user_sgpr_info, &args,
921 &desc_sets);
922
923 if (previous_stage == MESA_SHADER_TESS_EVAL) {
924 add_arg(&args, ARG_SGPR, ctx->ac.i32,
925 &ctx->tcs_offchip_layout);
926 } else {
927 declare_vs_specific_input_sgprs(ctx, stage,
928 has_previous_stage,
929 previous_stage,
930 &args);
931 }
932
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->gsvs_ring_stride);
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_num_entries);
937 if (needs_view_index)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->abi.view_index);
940
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->gs_vtx_offset[0]);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[2]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->abi.gs_prim_id);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_invocation_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[4]);
951
952 if (previous_stage == MESA_SHADER_VERTEX) {
953 declare_vs_input_vgprs(ctx, &args);
954 } else {
955 declare_tes_input_vgprs(ctx, &args);
956 }
957 } else {
958 declare_global_input_sgprs(ctx, stage,
959 has_previous_stage,
960 previous_stage,
961 &user_sgpr_info, &args,
962 &desc_sets);
963
964 add_arg(&args, ARG_SGPR, ctx->ac.i32,
965 &ctx->gsvs_ring_stride);
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_num_entries);
968 if (needs_view_index)
969 add_arg(&args, ARG_SGPR, ctx->ac.i32,
970 &ctx->abi.view_index);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
973 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[0]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[1]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->abi.gs_prim_id);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[2]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[3]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[4]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[5]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->abi.gs_invocation_id);
990 }
991 break;
992 case MESA_SHADER_FRAGMENT:
993 declare_global_input_sgprs(ctx, stage, has_previous_stage,
994 previous_stage, &user_sgpr_info,
995 &args, &desc_sets);
996
997 if (ctx->shader_info->info.ps.needs_sample_positions)
998 add_arg(&args, ARG_SGPR, ctx->ac.i32,
999 &ctx->sample_pos_offset);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1018 break;
1019 default:
1020 unreachable("Shader stage not implemented");
1021 }
1022
1023 ctx->main_function = create_llvm_function(
1024 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1025 ctx->max_workgroup_size,
1026 ctx->options->unsafe_math);
1027 set_llvm_calling_convention(ctx->main_function, stage);
1028
1029
1030 ctx->shader_info->num_input_vgprs = 0;
1031 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1032
1033 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1034
1035 if (ctx->stage != MESA_SHADER_FRAGMENT)
1036 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1037
1038 assign_arguments(ctx->main_function, &args);
1039
1040 user_sgpr_idx = 0;
1041
1042 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1043 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1044 &user_sgpr_idx, 2);
1045 if (ctx->options->supports_spill) {
1046 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1048 NULL, 0, AC_FUNC_ATTR_READNONE);
1049 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1050 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1051 }
1052 }
1053
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage)
1057 user_sgpr_idx = 0;
1058
1059 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1060 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1061
1062 switch (stage) {
1063 case MESA_SHADER_COMPUTE:
1064 if (ctx->shader_info->info.cs.uses_grid_size) {
1065 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1066 &user_sgpr_idx, 3);
1067 }
1068 break;
1069 case MESA_SHADER_VERTEX:
1070 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1071 previous_stage, &user_sgpr_idx);
1072 if (ctx->abi.view_index)
1073 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1074 if (ctx->options->key.vs.as_ls) {
1075 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1076 &user_sgpr_idx, 1);
1077 }
1078 break;
1079 case MESA_SHADER_TESS_CTRL:
1080 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1081 previous_stage, &user_sgpr_idx);
1082 if (has_previous_stage)
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1086 if (ctx->abi.view_index)
1087 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1088 break;
1089 case MESA_SHADER_TESS_EVAL:
1090 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1091 if (ctx->abi.view_index)
1092 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1093 break;
1094 case MESA_SHADER_GEOMETRY:
1095 if (has_previous_stage) {
1096 if (previous_stage == MESA_SHADER_VERTEX)
1097 set_vs_specific_input_locs(ctx, stage,
1098 has_previous_stage,
1099 previous_stage,
1100 &user_sgpr_idx);
1101 else
1102 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1103 &user_sgpr_idx, 1);
1104 }
1105 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1106 &user_sgpr_idx, 2);
1107 if (ctx->abi.view_index)
1108 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1109 break;
1110 case MESA_SHADER_FRAGMENT:
1111 if (ctx->shader_info->info.ps.needs_sample_positions) {
1112 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1113 &user_sgpr_idx, 1);
1114 }
1115 break;
1116 default:
1117 unreachable("Shader stage not implemented");
1118 }
1119
1120 if (stage == MESA_SHADER_TESS_CTRL ||
1121 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1122 /* GFX9 has the ESGS ring buffer in LDS. */
1123 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1124 ac_declare_lds_as_pointer(&ctx->ac);
1125 }
1126
1127 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1128 }
1129
1130 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1131 LLVMValueRef value, unsigned count)
1132 {
1133 unsigned num_components = ac_get_llvm_num_components(value);
1134 if (count == num_components)
1135 return value;
1136
1137 LLVMValueRef masks[] = {
1138 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1139 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1140
1141 if (count == 1)
1142 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1143 "");
1144
1145 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1146 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1147 }
1148
1149 static void
1150 build_store_values_extended(struct ac_llvm_context *ac,
1151 LLVMValueRef *values,
1152 unsigned value_count,
1153 unsigned value_stride,
1154 LLVMValueRef vec)
1155 {
1156 LLVMBuilderRef builder = ac->builder;
1157 unsigned i;
1158
1159 for (i = 0; i < value_count; i++) {
1160 LLVMValueRef ptr = values[i * value_stride];
1161 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1162 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1163 LLVMBuildStore(builder, value, ptr);
1164 }
1165 }
1166
1167 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1168 const nir_ssa_def *def)
1169 {
1170 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1171 if (def->num_components > 1) {
1172 type = LLVMVectorType(type, def->num_components);
1173 }
1174 return type;
1175 }
1176
1177 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1178 {
1179 assert(src.is_ssa);
1180 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1181 return (LLVMValueRef)entry->data;
1182 }
1183
1184 static LLVMValueRef
1185 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1186 {
1187 LLVMValueRef ptr = get_src(ctx, src);
1188 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1189 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1190
1191 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1192 LLVMPointerType(ctx->ac.i32, addr_space), "");
1193 }
1194
1195 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1196 const struct nir_block *b)
1197 {
1198 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1199 return (LLVMBasicBlockRef)entry->data;
1200 }
1201
1202 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1203 nir_alu_src src,
1204 unsigned num_components)
1205 {
1206 LLVMValueRef value = get_src(ctx, src.src);
1207 bool need_swizzle = false;
1208
1209 assert(value);
1210 unsigned src_components = ac_get_llvm_num_components(value);
1211 for (unsigned i = 0; i < num_components; ++i) {
1212 assert(src.swizzle[i] < src_components);
1213 if (src.swizzle[i] != i)
1214 need_swizzle = true;
1215 }
1216
1217 if (need_swizzle || num_components != src_components) {
1218 LLVMValueRef masks[] = {
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1220 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1221 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1222 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1223
1224 if (src_components > 1 && num_components == 1) {
1225 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1226 masks[0], "");
1227 } else if (src_components == 1 && num_components > 1) {
1228 LLVMValueRef values[] = {value, value, value, value};
1229 value = ac_build_gather_values(&ctx->ac, values, num_components);
1230 } else {
1231 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1232 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1233 swizzle, "");
1234 }
1235 }
1236 assert(!src.negate);
1237 assert(!src.abs);
1238 return value;
1239 }
1240
1241 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1242 LLVMIntPredicate pred, LLVMValueRef src0,
1243 LLVMValueRef src1)
1244 {
1245 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1246 return LLVMBuildSelect(ctx->builder, result,
1247 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1248 ctx->i32_0, "");
1249 }
1250
1251 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1252 LLVMRealPredicate pred, LLVMValueRef src0,
1253 LLVMValueRef src1)
1254 {
1255 LLVMValueRef result;
1256 src0 = ac_to_float(ctx, src0);
1257 src1 = ac_to_float(ctx, src1);
1258 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1259 return LLVMBuildSelect(ctx->builder, result,
1260 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1261 ctx->i32_0, "");
1262 }
1263
1264 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1265 const char *intrin,
1266 LLVMTypeRef result_type,
1267 LLVMValueRef src0)
1268 {
1269 char name[64];
1270 LLVMValueRef params[] = {
1271 ac_to_float(ctx, src0),
1272 };
1273
1274 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1275 ac_get_elem_bits(ctx, result_type));
1276 assert(length < sizeof(name));
1277 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1278 }
1279
1280 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0, LLVMValueRef src1)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 ac_to_float(ctx, src1),
1289 };
1290
1291 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1292 ac_get_elem_bits(ctx, result_type));
1293 assert(length < sizeof(name));
1294 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1295 }
1296
1297 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1298 const char *intrin,
1299 LLVMTypeRef result_type,
1300 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1301 {
1302 char name[64];
1303 LLVMValueRef params[] = {
1304 ac_to_float(ctx, src0),
1305 ac_to_float(ctx, src1),
1306 ac_to_float(ctx, src2),
1307 };
1308
1309 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1310 ac_get_elem_bits(ctx, result_type));
1311 assert(length < sizeof(name));
1312 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1313 }
1314
1315 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1319 ctx->i32_0, "");
1320 return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
1321 ac_to_integer(ctx, src2), "");
1322 }
1323
1324 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1325 LLVMIntPredicate pred,
1326 LLVMValueRef src0, LLVMValueRef src1)
1327 {
1328 return LLVMBuildSelect(ctx->builder,
1329 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1330 src0,
1331 src1, "");
1332
1333 }
1334 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1335 LLVMValueRef src0)
1336 {
1337 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1338 LLVMBuildNeg(ctx->builder, src0, ""));
1339 }
1340
1341 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1342 const char *intrin,
1343 LLVMValueRef src0, LLVMValueRef src1)
1344 {
1345 LLVMTypeRef ret_type;
1346 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1347 LLVMValueRef res;
1348 LLVMValueRef params[] = { src0, src1 };
1349 ret_type = LLVMStructTypeInContext(ctx->context, types,
1350 2, true);
1351
1352 res = ac_build_intrinsic(ctx, intrin, ret_type,
1353 params, 2, AC_FUNC_ATTR_READNONE);
1354
1355 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1356 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1357 return res;
1358 }
1359
1360 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1361 LLVMValueRef src0)
1362 {
1363 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1364 }
1365
1366 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1367 LLVMValueRef src0)
1368 {
1369 src0 = ac_to_float(ctx, src0);
1370 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
1371 return LLVMBuildSExt(ctx->builder,
1372 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, zero, ""),
1373 ctx->i32, "");
1374 }
1375
1376 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1377 LLVMValueRef src0,
1378 unsigned bitsize)
1379 {
1380 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1381
1382 if (bitsize == 32)
1383 return result;
1384
1385 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1386 }
1387
1388 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1389 LLVMValueRef src0)
1390 {
1391 LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
1392 return LLVMBuildSExt(ctx->builder,
1393 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, zero, ""),
1394 ctx->i32, "");
1395 }
1396
1397 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1398 LLVMValueRef src0)
1399 {
1400 LLVMValueRef result;
1401 LLVMValueRef cond = NULL;
1402
1403 src0 = ac_to_float(ctx, src0);
1404 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1405
1406 if (ctx->chip_class >= VI) {
1407 LLVMValueRef args[2];
1408 /* Check if the result is a denormal - and flush to 0 if so. */
1409 args[0] = result;
1410 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1411 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1412 }
1413
1414 /* need to convert back up to f32 */
1415 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1416
1417 if (ctx->chip_class >= VI)
1418 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1419 else {
1420 /* for SI/CIK */
1421 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1422 * so compare the result and flush to 0 if it's smaller.
1423 */
1424 LLVMValueRef temp, cond2;
1425 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1426 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1427 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1428 temp, "");
1429 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1430 temp, ctx->f32_0, "");
1431 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1432 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1433 }
1434 return result;
1435 }
1436
1437 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1438 LLVMValueRef src0, LLVMValueRef src1)
1439 {
1440 LLVMValueRef dst64, result;
1441 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1442 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1443
1444 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1445 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1446 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1447 return result;
1448 }
1449
1450 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1451 LLVMValueRef src0, LLVMValueRef src1)
1452 {
1453 LLVMValueRef dst64, result;
1454 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1455 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1456
1457 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1458 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1459 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1460 return result;
1461 }
1462
1463 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1464 bool is_signed,
1465 const LLVMValueRef srcs[3])
1466 {
1467 LLVMValueRef result;
1468 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1469
1470 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1471 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1472 return result;
1473 }
1474
1475 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1476 LLVMValueRef src0, LLVMValueRef src1,
1477 LLVMValueRef src2, LLVMValueRef src3)
1478 {
1479 LLVMValueRef bfi_args[3], result;
1480
1481 bfi_args[0] = LLVMBuildShl(ctx->builder,
1482 LLVMBuildSub(ctx->builder,
1483 LLVMBuildShl(ctx->builder,
1484 ctx->i32_1,
1485 src3, ""),
1486 ctx->i32_1, ""),
1487 src2, "");
1488 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1489 bfi_args[2] = src0;
1490
1491 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1492
1493 /* Calculate:
1494 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1495 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1496 */
1497 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1498 LLVMBuildAnd(ctx->builder, bfi_args[0],
1499 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1500
1501 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1502 return result;
1503 }
1504
1505 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1506 LLVMValueRef src0)
1507 {
1508 LLVMValueRef comp[2];
1509
1510 src0 = ac_to_float(ctx, src0);
1511 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1512 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1513
1514 return ac_build_cvt_pkrtz_f16(ctx, comp);
1515 }
1516
1517 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1518 LLVMValueRef src0)
1519 {
1520 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1521 LLVMValueRef temps[2], result, val;
1522 int i;
1523
1524 for (i = 0; i < 2; i++) {
1525 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1526 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1527 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1528 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1529 }
1530
1531 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1532 ctx->i32_0, "");
1533 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1534 ctx->i32_1, "");
1535 return result;
1536 }
1537
1538 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1539 nir_op op,
1540 LLVMValueRef src0)
1541 {
1542 unsigned mask;
1543 int idx;
1544 LLVMValueRef result;
1545
1546 if (op == nir_op_fddx_fine)
1547 mask = AC_TID_MASK_LEFT;
1548 else if (op == nir_op_fddy_fine)
1549 mask = AC_TID_MASK_TOP;
1550 else
1551 mask = AC_TID_MASK_TOP_LEFT;
1552
1553 /* for DDX we want to next X pixel, DDY next Y pixel. */
1554 if (op == nir_op_fddx_fine ||
1555 op == nir_op_fddx_coarse ||
1556 op == nir_op_fddx)
1557 idx = 1;
1558 else
1559 idx = 2;
1560
1561 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1562 return result;
1563 }
1564
1565 /*
1566 * this takes an I,J coordinate pair,
1567 * and works out the X and Y derivatives.
1568 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1569 */
1570 static LLVMValueRef emit_ddxy_interp(
1571 struct ac_nir_context *ctx,
1572 LLVMValueRef interp_ij)
1573 {
1574 LLVMValueRef result[4], a;
1575 unsigned i;
1576
1577 for (i = 0; i < 2; i++) {
1578 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1579 LLVMConstInt(ctx->ac.i32, i, false), "");
1580 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1581 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1582 }
1583 return ac_build_gather_values(&ctx->ac, result, 4);
1584 }
1585
1586 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1587 {
1588 LLVMValueRef src[4], result = NULL;
1589 unsigned num_components = instr->dest.dest.ssa.num_components;
1590 unsigned src_components;
1591 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1592
1593 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1594 switch (instr->op) {
1595 case nir_op_vec2:
1596 case nir_op_vec3:
1597 case nir_op_vec4:
1598 src_components = 1;
1599 break;
1600 case nir_op_pack_half_2x16:
1601 src_components = 2;
1602 break;
1603 case nir_op_unpack_half_2x16:
1604 src_components = 1;
1605 break;
1606 case nir_op_cube_face_coord:
1607 case nir_op_cube_face_index:
1608 src_components = 3;
1609 break;
1610 default:
1611 src_components = num_components;
1612 break;
1613 }
1614 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1615 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1616
1617 switch (instr->op) {
1618 case nir_op_fmov:
1619 case nir_op_imov:
1620 result = src[0];
1621 break;
1622 case nir_op_fneg:
1623 src[0] = ac_to_float(&ctx->ac, src[0]);
1624 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1625 break;
1626 case nir_op_ineg:
1627 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1628 break;
1629 case nir_op_inot:
1630 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1631 break;
1632 case nir_op_iadd:
1633 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1634 break;
1635 case nir_op_fadd:
1636 src[0] = ac_to_float(&ctx->ac, src[0]);
1637 src[1] = ac_to_float(&ctx->ac, src[1]);
1638 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1639 break;
1640 case nir_op_fsub:
1641 src[0] = ac_to_float(&ctx->ac, src[0]);
1642 src[1] = ac_to_float(&ctx->ac, src[1]);
1643 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1644 break;
1645 case nir_op_isub:
1646 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1647 break;
1648 case nir_op_imul:
1649 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1650 break;
1651 case nir_op_imod:
1652 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1653 break;
1654 case nir_op_umod:
1655 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1656 break;
1657 case nir_op_fmod:
1658 src[0] = ac_to_float(&ctx->ac, src[0]);
1659 src[1] = ac_to_float(&ctx->ac, src[1]);
1660 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1661 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1662 ac_to_float_type(&ctx->ac, def_type), result);
1663 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1664 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1665 break;
1666 case nir_op_frem:
1667 src[0] = ac_to_float(&ctx->ac, src[0]);
1668 src[1] = ac_to_float(&ctx->ac, src[1]);
1669 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1670 break;
1671 case nir_op_irem:
1672 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1673 break;
1674 case nir_op_idiv:
1675 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1676 break;
1677 case nir_op_udiv:
1678 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1679 break;
1680 case nir_op_fmul:
1681 src[0] = ac_to_float(&ctx->ac, src[0]);
1682 src[1] = ac_to_float(&ctx->ac, src[1]);
1683 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1684 break;
1685 case nir_op_frcp:
1686 src[0] = ac_to_float(&ctx->ac, src[0]);
1687 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1688 src[0]);
1689 break;
1690 case nir_op_iand:
1691 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1692 break;
1693 case nir_op_ior:
1694 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_ixor:
1697 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1698 break;
1699 case nir_op_ishl:
1700 result = LLVMBuildShl(ctx->ac.builder, src[0],
1701 LLVMBuildZExt(ctx->ac.builder, src[1],
1702 LLVMTypeOf(src[0]), ""),
1703 "");
1704 break;
1705 case nir_op_ishr:
1706 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1707 LLVMBuildZExt(ctx->ac.builder, src[1],
1708 LLVMTypeOf(src[0]), ""),
1709 "");
1710 break;
1711 case nir_op_ushr:
1712 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1713 LLVMBuildZExt(ctx->ac.builder, src[1],
1714 LLVMTypeOf(src[0]), ""),
1715 "");
1716 break;
1717 case nir_op_ilt:
1718 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1719 break;
1720 case nir_op_ine:
1721 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1722 break;
1723 case nir_op_ieq:
1724 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1725 break;
1726 case nir_op_ige:
1727 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1728 break;
1729 case nir_op_ult:
1730 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1731 break;
1732 case nir_op_uge:
1733 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1734 break;
1735 case nir_op_feq:
1736 result = emit_float_cmp(&ctx->ac, LLVMRealOEQ, src[0], src[1]);
1737 break;
1738 case nir_op_fne:
1739 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1740 break;
1741 case nir_op_flt:
1742 result = emit_float_cmp(&ctx->ac, LLVMRealOLT, src[0], src[1]);
1743 break;
1744 case nir_op_fge:
1745 result = emit_float_cmp(&ctx->ac, LLVMRealOGE, src[0], src[1]);
1746 break;
1747 case nir_op_fabs:
1748 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1749 ac_to_float_type(&ctx->ac, def_type), src[0]);
1750 break;
1751 case nir_op_iabs:
1752 result = emit_iabs(&ctx->ac, src[0]);
1753 break;
1754 case nir_op_imax:
1755 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1756 break;
1757 case nir_op_imin:
1758 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1759 break;
1760 case nir_op_umax:
1761 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1762 break;
1763 case nir_op_umin:
1764 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1765 break;
1766 case nir_op_isign:
1767 result = ac_build_isign(&ctx->ac, src[0],
1768 instr->dest.dest.ssa.bit_size);
1769 break;
1770 case nir_op_fsign:
1771 src[0] = ac_to_float(&ctx->ac, src[0]);
1772 result = ac_build_fsign(&ctx->ac, src[0],
1773 instr->dest.dest.ssa.bit_size);
1774 break;
1775 case nir_op_ffloor:
1776 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1777 ac_to_float_type(&ctx->ac, def_type), src[0]);
1778 break;
1779 case nir_op_ftrunc:
1780 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1781 ac_to_float_type(&ctx->ac, def_type), src[0]);
1782 break;
1783 case nir_op_fceil:
1784 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1785 ac_to_float_type(&ctx->ac, def_type), src[0]);
1786 break;
1787 case nir_op_fround_even:
1788 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1789 ac_to_float_type(&ctx->ac, def_type),src[0]);
1790 break;
1791 case nir_op_ffract:
1792 src[0] = ac_to_float(&ctx->ac, src[0]);
1793 result = ac_build_fract(&ctx->ac, src[0],
1794 instr->dest.dest.ssa.bit_size);
1795 break;
1796 case nir_op_fsin:
1797 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1798 ac_to_float_type(&ctx->ac, def_type), src[0]);
1799 break;
1800 case nir_op_fcos:
1801 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1802 ac_to_float_type(&ctx->ac, def_type), src[0]);
1803 break;
1804 case nir_op_fsqrt:
1805 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1806 ac_to_float_type(&ctx->ac, def_type), src[0]);
1807 break;
1808 case nir_op_fexp2:
1809 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1810 ac_to_float_type(&ctx->ac, def_type), src[0]);
1811 break;
1812 case nir_op_flog2:
1813 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1814 ac_to_float_type(&ctx->ac, def_type), src[0]);
1815 break;
1816 case nir_op_frsq:
1817 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1818 ac_to_float_type(&ctx->ac, def_type), src[0]);
1819 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1820 result);
1821 break;
1822 case nir_op_fmax:
1823 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1824 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1825 if (ctx->ac.chip_class < GFX9 &&
1826 instr->dest.dest.ssa.bit_size == 32) {
1827 /* Only pre-GFX9 chips do not flush denorms. */
1828 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1829 ac_to_float_type(&ctx->ac, def_type),
1830 result);
1831 }
1832 break;
1833 case nir_op_fmin:
1834 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1835 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1836 if (ctx->ac.chip_class < GFX9 &&
1837 instr->dest.dest.ssa.bit_size == 32) {
1838 /* Only pre-GFX9 chips do not flush denorms. */
1839 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1840 ac_to_float_type(&ctx->ac, def_type),
1841 result);
1842 }
1843 break;
1844 case nir_op_ffma:
1845 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1846 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1847 break;
1848 case nir_op_ldexp:
1849 src[0] = ac_to_float(&ctx->ac, src[0]);
1850 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1851 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f32", ctx->ac.f32, src, 2, AC_FUNC_ATTR_READNONE);
1852 else
1853 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f64", ctx->ac.f64, src, 2, AC_FUNC_ATTR_READNONE);
1854 break;
1855 case nir_op_ibitfield_extract:
1856 result = emit_bitfield_extract(&ctx->ac, true, src);
1857 break;
1858 case nir_op_ubitfield_extract:
1859 result = emit_bitfield_extract(&ctx->ac, false, src);
1860 break;
1861 case nir_op_bitfield_insert:
1862 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1863 break;
1864 case nir_op_bitfield_reverse:
1865 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1866 break;
1867 case nir_op_bit_count:
1868 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1869 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1870 else {
1871 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1872 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1873 }
1874 break;
1875 case nir_op_vec2:
1876 case nir_op_vec3:
1877 case nir_op_vec4:
1878 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1879 src[i] = ac_to_integer(&ctx->ac, src[i]);
1880 result = ac_build_gather_values(&ctx->ac, src, num_components);
1881 break;
1882 case nir_op_f2i32:
1883 case nir_op_f2i64:
1884 src[0] = ac_to_float(&ctx->ac, src[0]);
1885 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1886 break;
1887 case nir_op_f2u32:
1888 case nir_op_f2u64:
1889 src[0] = ac_to_float(&ctx->ac, src[0]);
1890 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1891 break;
1892 case nir_op_i2f32:
1893 case nir_op_i2f64:
1894 src[0] = ac_to_integer(&ctx->ac, src[0]);
1895 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1896 break;
1897 case nir_op_u2f32:
1898 case nir_op_u2f64:
1899 src[0] = ac_to_integer(&ctx->ac, src[0]);
1900 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1901 break;
1902 case nir_op_f2f64:
1903 src[0] = ac_to_float(&ctx->ac, src[0]);
1904 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1905 break;
1906 case nir_op_f2f32:
1907 src[0] = ac_to_float(&ctx->ac, src[0]);
1908 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1909 break;
1910 case nir_op_u2u32:
1911 case nir_op_u2u64:
1912 src[0] = ac_to_integer(&ctx->ac, src[0]);
1913 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1914 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1915 else
1916 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1917 break;
1918 case nir_op_i2i32:
1919 case nir_op_i2i64:
1920 src[0] = ac_to_integer(&ctx->ac, src[0]);
1921 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1922 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1923 else
1924 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1925 break;
1926 case nir_op_bcsel:
1927 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1928 break;
1929 case nir_op_find_lsb:
1930 src[0] = ac_to_integer(&ctx->ac, src[0]);
1931 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1932 break;
1933 case nir_op_ufind_msb:
1934 src[0] = ac_to_integer(&ctx->ac, src[0]);
1935 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1936 break;
1937 case nir_op_ifind_msb:
1938 src[0] = ac_to_integer(&ctx->ac, src[0]);
1939 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1940 break;
1941 case nir_op_uadd_carry:
1942 src[0] = ac_to_integer(&ctx->ac, src[0]);
1943 src[1] = ac_to_integer(&ctx->ac, src[1]);
1944 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1945 break;
1946 case nir_op_usub_borrow:
1947 src[0] = ac_to_integer(&ctx->ac, src[0]);
1948 src[1] = ac_to_integer(&ctx->ac, src[1]);
1949 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1950 break;
1951 case nir_op_b2f:
1952 result = emit_b2f(&ctx->ac, src[0]);
1953 break;
1954 case nir_op_f2b:
1955 result = emit_f2b(&ctx->ac, src[0]);
1956 break;
1957 case nir_op_b2i:
1958 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1959 break;
1960 case nir_op_i2b:
1961 src[0] = ac_to_integer(&ctx->ac, src[0]);
1962 result = emit_i2b(&ctx->ac, src[0]);
1963 break;
1964 case nir_op_fquantize2f16:
1965 result = emit_f2f16(&ctx->ac, src[0]);
1966 break;
1967 case nir_op_umul_high:
1968 src[0] = ac_to_integer(&ctx->ac, src[0]);
1969 src[1] = ac_to_integer(&ctx->ac, src[1]);
1970 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1971 break;
1972 case nir_op_imul_high:
1973 src[0] = ac_to_integer(&ctx->ac, src[0]);
1974 src[1] = ac_to_integer(&ctx->ac, src[1]);
1975 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1976 break;
1977 case nir_op_pack_half_2x16:
1978 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1979 break;
1980 case nir_op_unpack_half_2x16:
1981 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1982 break;
1983 case nir_op_fddx:
1984 case nir_op_fddy:
1985 case nir_op_fddx_fine:
1986 case nir_op_fddy_fine:
1987 case nir_op_fddx_coarse:
1988 case nir_op_fddy_coarse:
1989 result = emit_ddxy(ctx, instr->op, src[0]);
1990 break;
1991
1992 case nir_op_unpack_64_2x32_split_x: {
1993 assert(ac_get_llvm_num_components(src[0]) == 1);
1994 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1995 ctx->ac.v2i32,
1996 "");
1997 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1998 ctx->ac.i32_0, "");
1999 break;
2000 }
2001
2002 case nir_op_unpack_64_2x32_split_y: {
2003 assert(ac_get_llvm_num_components(src[0]) == 1);
2004 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2005 ctx->ac.v2i32,
2006 "");
2007 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2008 ctx->ac.i32_1, "");
2009 break;
2010 }
2011
2012 case nir_op_pack_64_2x32_split: {
2013 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2014 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2015 src[0], ctx->ac.i32_0, "");
2016 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2017 src[1], ctx->ac.i32_1, "");
2018 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2019 break;
2020 }
2021
2022 case nir_op_cube_face_coord: {
2023 src[0] = ac_to_float(&ctx->ac, src[0]);
2024 LLVMValueRef results[2];
2025 LLVMValueRef in[3];
2026 for (unsigned chan = 0; chan < 3; chan++)
2027 in[chan] = ac_llvm_extract_elem(&ctx->ac, src[0], chan);
2028 results[0] = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubetc",
2029 ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
2030 results[1] = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubesc",
2031 ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
2032 result = ac_build_gather_values(&ctx->ac, results, 2);
2033 break;
2034 }
2035
2036 case nir_op_cube_face_index: {
2037 src[0] = ac_to_float(&ctx->ac, src[0]);
2038 LLVMValueRef in[3];
2039 for (unsigned chan = 0; chan < 3; chan++)
2040 in[chan] = ac_llvm_extract_elem(&ctx->ac, src[0], chan);
2041 result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.cubeid",
2042 ctx->ac.f32, in, 3, AC_FUNC_ATTR_READNONE);
2043 break;
2044 }
2045
2046 default:
2047 fprintf(stderr, "Unknown NIR alu instr: ");
2048 nir_print_instr(&instr->instr, stderr);
2049 fprintf(stderr, "\n");
2050 abort();
2051 }
2052
2053 if (result) {
2054 assert(instr->dest.dest.is_ssa);
2055 result = ac_to_integer(&ctx->ac, result);
2056 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2057 result);
2058 }
2059 }
2060
2061 static void visit_load_const(struct ac_nir_context *ctx,
2062 const nir_load_const_instr *instr)
2063 {
2064 LLVMValueRef values[4], value = NULL;
2065 LLVMTypeRef element_type =
2066 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2067
2068 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2069 switch (instr->def.bit_size) {
2070 case 32:
2071 values[i] = LLVMConstInt(element_type,
2072 instr->value.u32[i], false);
2073 break;
2074 case 64:
2075 values[i] = LLVMConstInt(element_type,
2076 instr->value.u64[i], false);
2077 break;
2078 default:
2079 fprintf(stderr,
2080 "unsupported nir load_const bit_size: %d\n",
2081 instr->def.bit_size);
2082 abort();
2083 }
2084 }
2085 if (instr->def.num_components > 1) {
2086 value = LLVMConstVector(values, instr->def.num_components);
2087 } else
2088 value = values[0];
2089
2090 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2091 }
2092
2093 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2094 LLVMTypeRef type)
2095 {
2096 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2097 return LLVMBuildBitCast(ctx->builder, ptr,
2098 LLVMPointerType(type, addr_space), "");
2099 }
2100
2101 static LLVMValueRef
2102 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2103 {
2104 LLVMValueRef size =
2105 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2106 LLVMConstInt(ctx->ac.i32, 2, false), "");
2107
2108 /* VI only */
2109 if (ctx->ac.chip_class == VI && in_elements) {
2110 /* On VI, the descriptor contains the size in bytes,
2111 * but TXQ must return the size in elements.
2112 * The stride is always non-zero for resources using TXQ.
2113 */
2114 LLVMValueRef stride =
2115 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2116 ctx->ac.i32_1, "");
2117 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2118 LLVMConstInt(ctx->ac.i32, 16, false), "");
2119 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2120 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2121
2122 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2123 }
2124 return size;
2125 }
2126
2127 /**
2128 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2129 * intrinsic names).
2130 */
2131 static void build_int_type_name(
2132 LLVMTypeRef type,
2133 char *buf, unsigned bufsize)
2134 {
2135 assert(bufsize >= 6);
2136
2137 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2138 snprintf(buf, bufsize, "v%ui32",
2139 LLVMGetVectorSize(type));
2140 else
2141 strcpy(buf, "i32");
2142 }
2143
2144 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2145 struct ac_image_args *args,
2146 const nir_tex_instr *instr)
2147 {
2148 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2149 LLVMValueRef coord = args->addr;
2150 LLVMValueRef half_texel[2];
2151 LLVMValueRef compare_cube_wa = NULL;
2152 LLVMValueRef result;
2153 int c;
2154 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2155
2156 //TODO Rect
2157 {
2158 struct ac_image_args txq_args = { 0 };
2159
2160 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2161 txq_args.opcode = ac_image_get_resinfo;
2162 txq_args.dmask = 0xf;
2163 txq_args.addr = ctx->i32_0;
2164 txq_args.resource = args->resource;
2165 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2166
2167 for (c = 0; c < 2; c++) {
2168 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2169 LLVMConstInt(ctx->i32, c, false), "");
2170 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2171 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2172 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2173 LLVMConstReal(ctx->f32, -0.5), "");
2174 }
2175 }
2176
2177 LLVMValueRef orig_coords = args->addr;
2178
2179 for (c = 0; c < 2; c++) {
2180 LLVMValueRef tmp;
2181 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2182 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2183 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2184 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2185 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2186 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2187 }
2188
2189
2190 /*
2191 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2192 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2193 * workaround by sampling using a scaled type and converting.
2194 * This is taken from amdgpu-pro shaders.
2195 */
2196 /* NOTE this produces some ugly code compared to amdgpu-pro,
2197 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2198 * and then reads them back. -pro generates two selects,
2199 * one s_cmp for the descriptor rewriting
2200 * one v_cmp for the coordinate and result changes.
2201 */
2202 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2203 LLVMValueRef tmp, tmp2;
2204
2205 /* workaround 8/8/8/8 uint/sint cube gather bug */
2206 /* first detect it then change to a scaled read and f2i */
2207 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2208 tmp2 = tmp;
2209
2210 /* extract the DATA_FORMAT */
2211 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2212 LLVMConstInt(ctx->i32, 6, false), false);
2213
2214 /* is the DATA_FORMAT == 8_8_8_8 */
2215 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2216
2217 if (stype == GLSL_TYPE_UINT)
2218 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2219 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2220 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2221 else
2222 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2223 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2224 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2225
2226 /* replace the NUM FORMAT in the descriptor */
2227 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2228 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2229
2230 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2231
2232 /* don't modify the coordinates for this case */
2233 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2234 }
2235 args->addr = coord;
2236 result = ac_build_image_opcode(ctx, args);
2237
2238 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2239 LLVMValueRef tmp, tmp2;
2240
2241 /* if the cube workaround is in place, f2i the result. */
2242 for (c = 0; c < 4; c++) {
2243 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2244 if (stype == GLSL_TYPE_UINT)
2245 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2246 else
2247 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2248 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2249 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2250 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2251 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2252 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2253 }
2254 }
2255 return result;
2256 }
2257
2258 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2259 const nir_tex_instr *instr,
2260 bool lod_is_zero,
2261 struct ac_image_args *args)
2262 {
2263 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2264 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2265
2266 return ac_build_buffer_load_format(&ctx->ac,
2267 args->resource,
2268 args->addr,
2269 ctx->ac.i32_0,
2270 util_last_bit(mask),
2271 false, true);
2272 }
2273
2274 args->opcode = ac_image_sample;
2275 args->compare = instr->is_shadow;
2276
2277 switch (instr->op) {
2278 case nir_texop_txf:
2279 case nir_texop_txf_ms:
2280 case nir_texop_samples_identical:
2281 args->opcode = lod_is_zero ||
2282 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2283 ac_image_load : ac_image_load_mip;
2284 args->compare = false;
2285 args->offset = false;
2286 break;
2287 case nir_texop_txb:
2288 args->bias = true;
2289 break;
2290 case nir_texop_txl:
2291 if (lod_is_zero)
2292 args->level_zero = true;
2293 else
2294 args->lod = true;
2295 break;
2296 case nir_texop_txs:
2297 case nir_texop_query_levels:
2298 args->opcode = ac_image_get_resinfo;
2299 break;
2300 case nir_texop_tex:
2301 if (ctx->stage != MESA_SHADER_FRAGMENT)
2302 args->level_zero = true;
2303 break;
2304 case nir_texop_txd:
2305 args->deriv = true;
2306 break;
2307 case nir_texop_tg4:
2308 args->opcode = ac_image_gather4;
2309 args->level_zero = true;
2310 break;
2311 case nir_texop_lod:
2312 args->opcode = ac_image_get_lod;
2313 args->compare = false;
2314 args->offset = false;
2315 break;
2316 default:
2317 break;
2318 }
2319
2320 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2321 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2322 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2323 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2324 }
2325 }
2326 return ac_build_image_opcode(&ctx->ac, args);
2327 }
2328
2329 static LLVMValueRef
2330 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2331 unsigned desc_set, unsigned binding)
2332 {
2333 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2334 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2335 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2336 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2337 unsigned base_offset = layout->binding[binding].offset;
2338 LLVMValueRef offset, stride;
2339
2340 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2341 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2342 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2343 layout->binding[binding].dynamic_offset_offset;
2344 desc_ptr = ctx->abi.push_constants;
2345 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2346 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2347 } else
2348 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2349
2350 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2351 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2352 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2353
2354 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2355 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2356 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2357
2358 return desc_ptr;
2359 }
2360
2361 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2362 nir_intrinsic_instr *instr)
2363 {
2364 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2365 LLVMValueRef index = get_src(ctx, instr->src[1]);
2366
2367 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2368 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2369 return result;
2370 }
2371
2372 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2373 nir_intrinsic_instr *instr)
2374 {
2375 LLVMValueRef ptr, addr;
2376
2377 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2378 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2379 get_src(ctx, instr->src[0]), "");
2380
2381 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2382 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2383
2384 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2385 }
2386
2387 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2388 const nir_intrinsic_instr *instr)
2389 {
2390 LLVMValueRef index = get_src(ctx, instr->src[0]);
2391
2392 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2393 }
2394
2395 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2396 {
2397 uint32_t new_mask = 0;
2398 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2399 if (mask & (1u << i))
2400 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2401 return new_mask;
2402 }
2403
2404 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2405 unsigned start, unsigned count)
2406 {
2407 LLVMTypeRef type = LLVMTypeOf(src);
2408
2409 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2410 assert(start == 0);
2411 assert(count == 1);
2412 return src;
2413 }
2414
2415 unsigned src_elements = LLVMGetVectorSize(type);
2416 assert(start < src_elements);
2417 assert(start + count <= src_elements);
2418
2419 if (start == 0 && count == src_elements)
2420 return src;
2421
2422 if (count == 1)
2423 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2424
2425 assert(count <= 8);
2426 LLVMValueRef indices[8];
2427 for (unsigned i = 0; i < count; ++i)
2428 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2429
2430 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2431 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2432 }
2433
2434 static void visit_store_ssbo(struct ac_nir_context *ctx,
2435 nir_intrinsic_instr *instr)
2436 {
2437 const char *store_name;
2438 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2439 LLVMTypeRef data_type = ctx->ac.f32;
2440 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2441 int components_32bit = elem_size_mult * instr->num_components;
2442 unsigned writemask = nir_intrinsic_write_mask(instr);
2443 LLVMValueRef base_data, base_offset;
2444 LLVMValueRef params[6];
2445
2446 params[1] = ctx->abi->load_ssbo(ctx->abi,
2447 get_src(ctx, instr->src[1]), true);
2448 params[2] = ctx->ac.i32_0; /* vindex */
2449 params[4] = ctx->ac.i1false; /* glc */
2450 params[5] = ctx->ac.i1false; /* slc */
2451
2452 if (components_32bit > 1)
2453 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2454
2455 writemask = widen_mask(writemask, elem_size_mult);
2456
2457 base_data = ac_to_float(&ctx->ac, src_data);
2458 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2459 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2460 data_type, "");
2461 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2462 while (writemask) {
2463 int start, count;
2464 LLVMValueRef data;
2465 LLVMValueRef offset;
2466
2467 u_bit_scan_consecutive_range(&writemask, &start, &count);
2468
2469 /* Due to an LLVM limitation, split 3-element writes
2470 * into a 2-element and a 1-element write. */
2471 if (count == 3) {
2472 writemask |= 1 << (start + 2);
2473 count = 2;
2474 }
2475
2476 if (count > 4) {
2477 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2478 count = 4;
2479 }
2480
2481 if (count == 4) {
2482 store_name = "llvm.amdgcn.buffer.store.v4f32";
2483 } else if (count == 2) {
2484 store_name = "llvm.amdgcn.buffer.store.v2f32";
2485
2486 } else {
2487 assert(count == 1);
2488 store_name = "llvm.amdgcn.buffer.store.f32";
2489 }
2490 data = extract_vector_range(&ctx->ac, base_data, start, count);
2491
2492 offset = base_offset;
2493 if (start != 0) {
2494 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2495 }
2496 params[0] = data;
2497 params[3] = offset;
2498 ac_build_intrinsic(&ctx->ac, store_name,
2499 ctx->ac.voidt, params, 6, 0);
2500 }
2501 }
2502
2503 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2504 const nir_intrinsic_instr *instr)
2505 {
2506 const char *name;
2507 LLVMValueRef params[6];
2508 int arg_count = 0;
2509
2510 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2511 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2512 }
2513 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2514 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2515 get_src(ctx, instr->src[0]),
2516 true);
2517 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2518 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2519 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2520
2521 switch (instr->intrinsic) {
2522 case nir_intrinsic_ssbo_atomic_add:
2523 name = "llvm.amdgcn.buffer.atomic.add";
2524 break;
2525 case nir_intrinsic_ssbo_atomic_imin:
2526 name = "llvm.amdgcn.buffer.atomic.smin";
2527 break;
2528 case nir_intrinsic_ssbo_atomic_umin:
2529 name = "llvm.amdgcn.buffer.atomic.umin";
2530 break;
2531 case nir_intrinsic_ssbo_atomic_imax:
2532 name = "llvm.amdgcn.buffer.atomic.smax";
2533 break;
2534 case nir_intrinsic_ssbo_atomic_umax:
2535 name = "llvm.amdgcn.buffer.atomic.umax";
2536 break;
2537 case nir_intrinsic_ssbo_atomic_and:
2538 name = "llvm.amdgcn.buffer.atomic.and";
2539 break;
2540 case nir_intrinsic_ssbo_atomic_or:
2541 name = "llvm.amdgcn.buffer.atomic.or";
2542 break;
2543 case nir_intrinsic_ssbo_atomic_xor:
2544 name = "llvm.amdgcn.buffer.atomic.xor";
2545 break;
2546 case nir_intrinsic_ssbo_atomic_exchange:
2547 name = "llvm.amdgcn.buffer.atomic.swap";
2548 break;
2549 case nir_intrinsic_ssbo_atomic_comp_swap:
2550 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2551 break;
2552 default:
2553 abort();
2554 }
2555
2556 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2557 }
2558
2559 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2560 const nir_intrinsic_instr *instr)
2561 {
2562 LLVMValueRef results[2];
2563 int load_components;
2564 int num_components = instr->num_components;
2565 if (instr->dest.ssa.bit_size == 64)
2566 num_components *= 2;
2567
2568 for (int i = 0; i < num_components; i += load_components) {
2569 load_components = MIN2(num_components - i, 4);
2570 const char *load_name;
2571 LLVMTypeRef data_type = ctx->ac.f32;
2572 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2573 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2574
2575 if (load_components == 3)
2576 data_type = LLVMVectorType(ctx->ac.f32, 4);
2577 else if (load_components > 1)
2578 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2579
2580 if (load_components >= 3)
2581 load_name = "llvm.amdgcn.buffer.load.v4f32";
2582 else if (load_components == 2)
2583 load_name = "llvm.amdgcn.buffer.load.v2f32";
2584 else if (load_components == 1)
2585 load_name = "llvm.amdgcn.buffer.load.f32";
2586 else
2587 unreachable("unhandled number of components");
2588
2589 LLVMValueRef params[] = {
2590 ctx->abi->load_ssbo(ctx->abi,
2591 get_src(ctx, instr->src[0]),
2592 false),
2593 ctx->ac.i32_0,
2594 offset,
2595 ctx->ac.i1false,
2596 ctx->ac.i1false,
2597 };
2598
2599 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2600 }
2601
2602 assume(results[0]);
2603 LLVMValueRef ret = results[0];
2604 if (num_components > 4 || num_components == 3) {
2605 LLVMValueRef masks[] = {
2606 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2607 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2608 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2609 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2610 };
2611
2612 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2613 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2614 results[num_components > 4 ? 1 : 0], swizzle, "");
2615 }
2616
2617 return LLVMBuildBitCast(ctx->ac.builder, ret,
2618 get_def_type(ctx, &instr->dest.ssa), "");
2619 }
2620
2621 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2622 const nir_intrinsic_instr *instr)
2623 {
2624 LLVMValueRef ret;
2625 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2626 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2627 int num_components = instr->num_components;
2628
2629 if (ctx->abi->load_ubo)
2630 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2631
2632 if (instr->dest.ssa.bit_size == 64)
2633 num_components *= 2;
2634
2635 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2636 NULL, 0, false, false, true, true);
2637 ret = trim_vector(&ctx->ac, ret, num_components);
2638 return LLVMBuildBitCast(ctx->ac.builder, ret,
2639 get_def_type(ctx, &instr->dest.ssa), "");
2640 }
2641
2642 static void
2643 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2644 bool vs_in, unsigned *vertex_index_out,
2645 LLVMValueRef *vertex_index_ref,
2646 unsigned *const_out, LLVMValueRef *indir_out)
2647 {
2648 unsigned const_offset = 0;
2649 nir_deref *tail = &deref->deref;
2650 LLVMValueRef offset = NULL;
2651
2652 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2653 tail = tail->child;
2654 nir_deref_array *deref_array = nir_deref_as_array(tail);
2655 if (vertex_index_out)
2656 *vertex_index_out = deref_array->base_offset;
2657
2658 if (vertex_index_ref) {
2659 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2660 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2661 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2662 }
2663 *vertex_index_ref = vtx;
2664 }
2665 }
2666
2667 if (deref->var->data.compact) {
2668 assert(tail->child->deref_type == nir_deref_type_array);
2669 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2670 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2671 /* We always lower indirect dereferences for "compact" array vars. */
2672 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2673
2674 const_offset = deref_array->base_offset;
2675 goto out;
2676 }
2677
2678 while (tail->child != NULL) {
2679 const struct glsl_type *parent_type = tail->type;
2680 tail = tail->child;
2681
2682 if (tail->deref_type == nir_deref_type_array) {
2683 nir_deref_array *deref_array = nir_deref_as_array(tail);
2684 LLVMValueRef index, stride, local_offset;
2685 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2686
2687 const_offset += size * deref_array->base_offset;
2688 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2689 continue;
2690
2691 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2692 index = get_src(ctx, deref_array->indirect);
2693 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2694 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2695
2696 if (offset)
2697 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2698 else
2699 offset = local_offset;
2700 } else if (tail->deref_type == nir_deref_type_struct) {
2701 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2702
2703 for (unsigned i = 0; i < deref_struct->index; i++) {
2704 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2705 const_offset += glsl_count_attribute_slots(ft, vs_in);
2706 }
2707 } else
2708 unreachable("unsupported deref type");
2709
2710 }
2711 out:
2712 if (const_offset && offset)
2713 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2714 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2715 "");
2716
2717 *const_out = const_offset;
2718 *indir_out = offset;
2719 }
2720
2721
2722 /* The offchip buffer layout for TCS->TES is
2723 *
2724 * - attribute 0 of patch 0 vertex 0
2725 * - attribute 0 of patch 0 vertex 1
2726 * - attribute 0 of patch 0 vertex 2
2727 * ...
2728 * - attribute 0 of patch 1 vertex 0
2729 * - attribute 0 of patch 1 vertex 1
2730 * ...
2731 * - attribute 1 of patch 0 vertex 0
2732 * - attribute 1 of patch 0 vertex 1
2733 * ...
2734 * - per patch attribute 0 of patch 0
2735 * - per patch attribute 0 of patch 1
2736 * ...
2737 *
2738 * Note that every attribute has 4 components.
2739 */
2740 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2741 LLVMValueRef vertex_index,
2742 LLVMValueRef param_index)
2743 {
2744 LLVMValueRef base_addr, vertices_per_patch, num_patches;
2745 LLVMValueRef param_stride, constant16;
2746 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2747
2748 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
2749 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2750
2751 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2752 if (vertex_index) {
2753 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2754 vertices_per_patch, "");
2755
2756 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2757 vertex_index, "");
2758
2759 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2760 num_patches, "");
2761 } else {
2762 base_addr = rel_patch_id;
2763 param_stride = num_patches;
2764 }
2765
2766 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2767 LLVMBuildMul(ctx->ac.builder, param_index,
2768 param_stride, ""), "");
2769
2770 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2771
2772 if (!vertex_index) {
2773 LLVMValueRef patch_data_offset =
2774 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2775
2776 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2777 patch_data_offset, "");
2778 }
2779 return base_addr;
2780 }
2781
2782 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2783 unsigned param,
2784 unsigned const_index,
2785 bool is_compact,
2786 LLVMValueRef vertex_index,
2787 LLVMValueRef indir_index)
2788 {
2789 LLVMValueRef param_index;
2790
2791 if (indir_index)
2792 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2793 indir_index, "");
2794 else {
2795 if (const_index && !is_compact)
2796 param += const_index;
2797 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2798 }
2799 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2800 }
2801
2802 static void
2803 mark_tess_output(struct radv_shader_context *ctx,
2804 bool is_patch, uint32_t param)
2805
2806 {
2807 if (is_patch) {
2808 ctx->tess_patch_outputs_written |= (1ull << param);
2809 } else
2810 ctx->tess_outputs_written |= (1ull << param);
2811 }
2812
2813 static LLVMValueRef
2814 get_dw_address(struct radv_shader_context *ctx,
2815 LLVMValueRef dw_addr,
2816 unsigned param,
2817 unsigned const_index,
2818 bool compact_const_index,
2819 LLVMValueRef vertex_index,
2820 LLVMValueRef stride,
2821 LLVMValueRef indir_index)
2822
2823 {
2824
2825 if (vertex_index) {
2826 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2827 LLVMBuildMul(ctx->ac.builder,
2828 vertex_index,
2829 stride, ""), "");
2830 }
2831
2832 if (indir_index)
2833 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2834 LLVMBuildMul(ctx->ac.builder, indir_index,
2835 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2836 else if (const_index && !compact_const_index)
2837 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2838 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2839
2840 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2841 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2842
2843 if (const_index && compact_const_index)
2844 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2845 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2846 return dw_addr;
2847 }
2848
2849 static LLVMValueRef
2850 load_tcs_varyings(struct ac_shader_abi *abi,
2851 LLVMTypeRef type,
2852 LLVMValueRef vertex_index,
2853 LLVMValueRef indir_index,
2854 unsigned const_index,
2855 unsigned location,
2856 unsigned driver_location,
2857 unsigned component,
2858 unsigned num_components,
2859 bool is_patch,
2860 bool is_compact,
2861 bool load_input)
2862 {
2863 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2864 LLVMValueRef dw_addr, stride;
2865 LLVMValueRef value[4], result;
2866 unsigned param = shader_io_get_unique_index(location);
2867
2868 if (load_input) {
2869 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2870 dw_addr = get_tcs_in_current_patch_offset(ctx);
2871 } else {
2872 if (!is_patch) {
2873 stride = get_tcs_out_vertex_stride(ctx);
2874 dw_addr = get_tcs_out_current_patch_offset(ctx);
2875 } else {
2876 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2877 stride = NULL;
2878 }
2879 }
2880
2881 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2882 indir_index);
2883
2884 for (unsigned i = 0; i < num_components + component; i++) {
2885 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2886 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2887 ctx->ac.i32_1, "");
2888 }
2889 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2890 return result;
2891 }
2892
2893 static void
2894 store_tcs_output(struct ac_shader_abi *abi,
2895 LLVMValueRef vertex_index,
2896 LLVMValueRef param_index,
2897 unsigned const_index,
2898 unsigned location,
2899 unsigned driver_location,
2900 LLVMValueRef src,
2901 unsigned component,
2902 bool is_patch,
2903 bool is_compact,
2904 unsigned writemask)
2905 {
2906 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2907 LLVMValueRef dw_addr;
2908 LLVMValueRef stride = NULL;
2909 LLVMValueRef buf_addr = NULL;
2910 unsigned param;
2911 bool store_lds = true;
2912
2913 if (is_patch) {
2914 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2915 store_lds = false;
2916 } else {
2917 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2918 store_lds = false;
2919 }
2920
2921 param = shader_io_get_unique_index(location);
2922 if (location == VARYING_SLOT_CLIP_DIST0 &&
2923 is_compact && const_index > 3) {
2924 const_index -= 3;
2925 param++;
2926 }
2927
2928 if (!is_patch) {
2929 stride = get_tcs_out_vertex_stride(ctx);
2930 dw_addr = get_tcs_out_current_patch_offset(ctx);
2931 } else {
2932 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2933 }
2934
2935 mark_tess_output(ctx, is_patch, param);
2936
2937 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2938 param_index);
2939 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2940 vertex_index, param_index);
2941
2942 bool is_tess_factor = false;
2943 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2944 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2945 is_tess_factor = true;
2946
2947 unsigned base = is_compact ? const_index : 0;
2948 for (unsigned chan = 0; chan < 8; chan++) {
2949 if (!(writemask & (1 << chan)))
2950 continue;
2951 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2952
2953 if (store_lds || is_tess_factor) {
2954 LLVMValueRef dw_addr_chan =
2955 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2956 LLVMConstInt(ctx->ac.i32, chan, false), "");
2957 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2958 }
2959
2960 if (!is_tess_factor && writemask != 0xF)
2961 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2962 buf_addr, ctx->oc_lds,
2963 4 * (base + chan), 1, 0, true, false);
2964 }
2965
2966 if (writemask == 0xF) {
2967 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2968 buf_addr, ctx->oc_lds,
2969 (base * 4), 1, 0, true, false);
2970 }
2971 }
2972
2973 static LLVMValueRef
2974 load_tes_input(struct ac_shader_abi *abi,
2975 LLVMTypeRef type,
2976 LLVMValueRef vertex_index,
2977 LLVMValueRef param_index,
2978 unsigned const_index,
2979 unsigned location,
2980 unsigned driver_location,
2981 unsigned component,
2982 unsigned num_components,
2983 bool is_patch,
2984 bool is_compact,
2985 bool load_input)
2986 {
2987 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2988 LLVMValueRef buf_addr;
2989 LLVMValueRef result;
2990 unsigned param = shader_io_get_unique_index(location);
2991
2992 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2993 const_index -= 3;
2994 param++;
2995 }
2996
2997 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2998 is_compact, vertex_index, param_index);
2999
3000 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3001 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3002
3003 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3004 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3005 result = trim_vector(&ctx->ac, result, num_components);
3006 return result;
3007 }
3008
3009 static LLVMValueRef
3010 load_gs_input(struct ac_shader_abi *abi,
3011 unsigned location,
3012 unsigned driver_location,
3013 unsigned component,
3014 unsigned num_components,
3015 unsigned vertex_index,
3016 unsigned const_index,
3017 LLVMTypeRef type)
3018 {
3019 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3020 LLVMValueRef vtx_offset;
3021 unsigned param, vtx_offset_param;
3022 LLVMValueRef value[4], result;
3023
3024 vtx_offset_param = vertex_index;
3025 assert(vtx_offset_param < 6);
3026 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3027 LLVMConstInt(ctx->ac.i32, 4, false), "");
3028
3029 param = shader_io_get_unique_index(location);
3030
3031 for (unsigned i = component; i < num_components + component; i++) {
3032 if (ctx->ac.chip_class >= GFX9) {
3033 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3034 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3035 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3036 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3037 } else {
3038 LLVMValueRef soffset =
3039 LLVMConstInt(ctx->ac.i32,
3040 (param * 4 + i + const_index) * 256,
3041 false);
3042
3043 value[i] = ac_build_buffer_load(&ctx->ac,
3044 ctx->esgs_ring, 1,
3045 ctx->ac.i32_0,
3046 vtx_offset, soffset,
3047 0, 1, 0, true, false);
3048
3049 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3050 type, "");
3051 }
3052 }
3053 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3054 result = ac_to_integer(&ctx->ac, result);
3055 return result;
3056 }
3057
3058 static LLVMValueRef
3059 build_gep_for_deref(struct ac_nir_context *ctx,
3060 nir_deref_var *deref)
3061 {
3062 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3063 assert(entry->data);
3064 LLVMValueRef val = entry->data;
3065 nir_deref *tail = deref->deref.child;
3066 while (tail != NULL) {
3067 LLVMValueRef offset;
3068 switch (tail->deref_type) {
3069 case nir_deref_type_array: {
3070 nir_deref_array *array = nir_deref_as_array(tail);
3071 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3072 if (array->deref_array_type ==
3073 nir_deref_array_type_indirect) {
3074 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3075 get_src(ctx,
3076 array->indirect),
3077 "");
3078 }
3079 break;
3080 }
3081 case nir_deref_type_struct: {
3082 nir_deref_struct *deref_struct =
3083 nir_deref_as_struct(tail);
3084 offset = LLVMConstInt(ctx->ac.i32,
3085 deref_struct->index, 0);
3086 break;
3087 }
3088 default:
3089 unreachable("bad deref type");
3090 }
3091 val = ac_build_gep0(&ctx->ac, val, offset);
3092 tail = tail->child;
3093 }
3094 return val;
3095 }
3096
3097 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3098 nir_intrinsic_instr *instr,
3099 bool load_inputs)
3100 {
3101 LLVMValueRef result;
3102 LLVMValueRef vertex_index = NULL;
3103 LLVMValueRef indir_index = NULL;
3104 unsigned const_index = 0;
3105 unsigned location = instr->variables[0]->var->data.location;
3106 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3107 const bool is_patch = instr->variables[0]->var->data.patch;
3108 const bool is_compact = instr->variables[0]->var->data.compact;
3109
3110 get_deref_offset(ctx, instr->variables[0],
3111 false, NULL, is_patch ? NULL : &vertex_index,
3112 &const_index, &indir_index);
3113
3114 LLVMTypeRef dest_type = get_def_type(ctx, &instr->dest.ssa);
3115
3116 LLVMTypeRef src_component_type;
3117 if (LLVMGetTypeKind(dest_type) == LLVMVectorTypeKind)
3118 src_component_type = LLVMGetElementType(dest_type);
3119 else
3120 src_component_type = dest_type;
3121
3122 result = ctx->abi->load_tess_varyings(ctx->abi, src_component_type,
3123 vertex_index, indir_index,
3124 const_index, location, driver_location,
3125 instr->variables[0]->var->data.location_frac,
3126 instr->num_components,
3127 is_patch, is_compact, load_inputs);
3128 return LLVMBuildBitCast(ctx->ac.builder, result, dest_type, "");
3129 }
3130
3131 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3132 nir_intrinsic_instr *instr)
3133 {
3134 LLVMValueRef values[8];
3135 int idx = instr->variables[0]->var->data.driver_location;
3136 int ve = instr->dest.ssa.num_components;
3137 unsigned comp = instr->variables[0]->var->data.location_frac;
3138 LLVMValueRef indir_index;
3139 LLVMValueRef ret;
3140 unsigned const_index;
3141 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3142 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3143 instr->variables[0]->var->data.mode == nir_var_shader_in;
3144 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3145 &const_index, &indir_index);
3146
3147 if (instr->dest.ssa.bit_size == 64)
3148 ve *= 2;
3149
3150 switch (instr->variables[0]->var->data.mode) {
3151 case nir_var_shader_in:
3152 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3153 ctx->stage == MESA_SHADER_TESS_EVAL) {
3154 return load_tess_varyings(ctx, instr, true);
3155 }
3156
3157 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3158 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3159 LLVMValueRef indir_index;
3160 unsigned const_index, vertex_index;
3161 get_deref_offset(ctx, instr->variables[0],
3162 false, &vertex_index, NULL,
3163 &const_index, &indir_index);
3164
3165 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3166 instr->variables[0]->var->data.driver_location,
3167 instr->variables[0]->var->data.location_frac,
3168 instr->num_components, vertex_index, const_index, type);
3169 }
3170
3171 for (unsigned chan = comp; chan < ve + comp; chan++) {
3172 if (indir_index) {
3173 unsigned count = glsl_count_attribute_slots(
3174 instr->variables[0]->var->type,
3175 ctx->stage == MESA_SHADER_VERTEX);
3176 count -= chan / 4;
3177 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3178 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3179 stride, false, true);
3180
3181 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3182 tmp_vec,
3183 indir_index, "");
3184 } else
3185 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3186 }
3187 break;
3188 case nir_var_local:
3189 for (unsigned chan = 0; chan < ve; chan++) {
3190 if (indir_index) {
3191 unsigned count = glsl_count_attribute_slots(
3192 instr->variables[0]->var->type, false);
3193 count -= chan / 4;
3194 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3195 &ctx->ac, ctx->locals + idx + chan, count,
3196 stride, true, true);
3197
3198 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3199 tmp_vec,
3200 indir_index, "");
3201 } else {
3202 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3203 }
3204 }
3205 break;
3206 case nir_var_shared: {
3207 LLVMValueRef address = build_gep_for_deref(ctx,
3208 instr->variables[0]);
3209 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3210 return LLVMBuildBitCast(ctx->ac.builder, val,
3211 get_def_type(ctx, &instr->dest.ssa),
3212 "");
3213 }
3214 case nir_var_shader_out:
3215 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3216 return load_tess_varyings(ctx, instr, false);
3217 }
3218
3219 for (unsigned chan = comp; chan < ve + comp; chan++) {
3220 if (indir_index) {
3221 unsigned count = glsl_count_attribute_slots(
3222 instr->variables[0]->var->type, false);
3223 count -= chan / 4;
3224 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3225 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3226 stride, true, true);
3227
3228 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3229 tmp_vec,
3230 indir_index, "");
3231 } else {
3232 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3233 ctx->abi->outputs[idx + chan + const_index * stride],
3234 "");
3235 }
3236 }
3237 break;
3238 default:
3239 unreachable("unhandle variable mode");
3240 }
3241 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3242 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3243 }
3244
3245 static void
3246 visit_store_var(struct ac_nir_context *ctx,
3247 nir_intrinsic_instr *instr)
3248 {
3249 LLVMValueRef temp_ptr, value;
3250 int idx = instr->variables[0]->var->data.driver_location;
3251 unsigned comp = instr->variables[0]->var->data.location_frac;
3252 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3253 int writemask = instr->const_index[0] << comp;
3254 LLVMValueRef indir_index;
3255 unsigned const_index;
3256 get_deref_offset(ctx, instr->variables[0], false,
3257 NULL, NULL, &const_index, &indir_index);
3258
3259 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3260
3261 src = LLVMBuildBitCast(ctx->ac.builder, src,
3262 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3263 "");
3264
3265 writemask = widen_mask(writemask, 2);
3266 }
3267
3268 switch (instr->variables[0]->var->data.mode) {
3269 case nir_var_shader_out:
3270
3271 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3272 LLVMValueRef vertex_index = NULL;
3273 LLVMValueRef indir_index = NULL;
3274 unsigned const_index = 0;
3275 const unsigned location = instr->variables[0]->var->data.location;
3276 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3277 const unsigned comp = instr->variables[0]->var->data.location_frac;
3278 const bool is_patch = instr->variables[0]->var->data.patch;
3279 const bool is_compact = instr->variables[0]->var->data.compact;
3280
3281 get_deref_offset(ctx, instr->variables[0],
3282 false, NULL, is_patch ? NULL : &vertex_index,
3283 &const_index, &indir_index);
3284
3285 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3286 const_index, location, driver_location,
3287 src, comp, is_patch, is_compact, writemask);
3288 return;
3289 }
3290
3291 for (unsigned chan = 0; chan < 8; chan++) {
3292 int stride = 4;
3293 if (!(writemask & (1 << chan)))
3294 continue;
3295
3296 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3297
3298 if (instr->variables[0]->var->data.compact)
3299 stride = 1;
3300 if (indir_index) {
3301 unsigned count = glsl_count_attribute_slots(
3302 instr->variables[0]->var->type, false);
3303 count -= chan / 4;
3304 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3305 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3306 stride, true, true);
3307
3308 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3309 value, indir_index, "");
3310 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3311 count, stride, tmp_vec);
3312
3313 } else {
3314 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3315
3316 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3317 }
3318 }
3319 break;
3320 case nir_var_local:
3321 for (unsigned chan = 0; chan < 8; chan++) {
3322 if (!(writemask & (1 << chan)))
3323 continue;
3324
3325 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3326 if (indir_index) {
3327 unsigned count = glsl_count_attribute_slots(
3328 instr->variables[0]->var->type, false);
3329 count -= chan / 4;
3330 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3331 &ctx->ac, ctx->locals + idx + chan, count,
3332 4, true, true);
3333
3334 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3335 value, indir_index, "");
3336 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3337 count, 4, tmp_vec);
3338 } else {
3339 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3340
3341 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3342 }
3343 }
3344 break;
3345 case nir_var_shared: {
3346 int writemask = instr->const_index[0];
3347 LLVMValueRef address = build_gep_for_deref(ctx,
3348 instr->variables[0]);
3349 LLVMValueRef val = get_src(ctx, instr->src[0]);
3350 unsigned components =
3351 glsl_get_vector_elements(
3352 nir_deref_tail(&instr->variables[0]->deref)->type);
3353 if (writemask == (1 << components) - 1) {
3354 val = LLVMBuildBitCast(
3355 ctx->ac.builder, val,
3356 LLVMGetElementType(LLVMTypeOf(address)), "");
3357 LLVMBuildStore(ctx->ac.builder, val, address);
3358 } else {
3359 for (unsigned chan = 0; chan < 4; chan++) {
3360 if (!(writemask & (1 << chan)))
3361 continue;
3362 LLVMValueRef ptr =
3363 LLVMBuildStructGEP(ctx->ac.builder,
3364 address, chan, "");
3365 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3366 chan);
3367 src = LLVMBuildBitCast(
3368 ctx->ac.builder, src,
3369 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3370 LLVMBuildStore(ctx->ac.builder, src, ptr);
3371 }
3372 }
3373 break;
3374 }
3375 default:
3376 break;
3377 }
3378 }
3379
3380 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3381 {
3382 switch (dim) {
3383 case GLSL_SAMPLER_DIM_BUF:
3384 return 1;
3385 case GLSL_SAMPLER_DIM_1D:
3386 return array ? 2 : 1;
3387 case GLSL_SAMPLER_DIM_2D:
3388 return array ? 3 : 2;
3389 case GLSL_SAMPLER_DIM_MS:
3390 return array ? 4 : 3;
3391 case GLSL_SAMPLER_DIM_3D:
3392 case GLSL_SAMPLER_DIM_CUBE:
3393 return 3;
3394 case GLSL_SAMPLER_DIM_RECT:
3395 case GLSL_SAMPLER_DIM_SUBPASS:
3396 return 2;
3397 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3398 return 3;
3399 default:
3400 break;
3401 }
3402 return 0;
3403 }
3404
3405 static bool
3406 glsl_is_array_image(const struct glsl_type *type)
3407 {
3408 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3409
3410 if (glsl_sampler_type_is_array(type))
3411 return true;
3412
3413 return dim == GLSL_SAMPLER_DIM_CUBE ||
3414 dim == GLSL_SAMPLER_DIM_3D ||
3415 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3416 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3417 }
3418
3419
3420 /* Adjust the sample index according to FMASK.
3421 *
3422 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3423 * which is the identity mapping. Each nibble says which physical sample
3424 * should be fetched to get that sample.
3425 *
3426 * For example, 0x11111100 means there are only 2 samples stored and
3427 * the second sample covers 3/4 of the pixel. When reading samples 0
3428 * and 1, return physical sample 0 (determined by the first two 0s
3429 * in FMASK), otherwise return physical sample 1.
3430 *
3431 * The sample index should be adjusted as follows:
3432 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3433 */
3434 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3435 LLVMValueRef coord_x, LLVMValueRef coord_y,
3436 LLVMValueRef coord_z,
3437 LLVMValueRef sample_index,
3438 LLVMValueRef fmask_desc_ptr)
3439 {
3440 LLVMValueRef fmask_load_address[4];
3441 LLVMValueRef res;
3442
3443 fmask_load_address[0] = coord_x;
3444 fmask_load_address[1] = coord_y;
3445 if (coord_z) {
3446 fmask_load_address[2] = coord_z;
3447 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3448 }
3449
3450 struct ac_image_args args = {0};
3451
3452 args.opcode = ac_image_load;
3453 args.da = coord_z ? true : false;
3454 args.resource = fmask_desc_ptr;
3455 args.dmask = 0xf;
3456 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3457
3458 res = ac_build_image_opcode(ctx, &args);
3459
3460 res = ac_to_integer(ctx, res);
3461 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3462 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3463
3464 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3465 res,
3466 ctx->i32_0, "");
3467
3468 LLVMValueRef sample_index4 =
3469 LLVMBuildMul(ctx->builder, sample_index, four, "");
3470 LLVMValueRef shifted_fmask =
3471 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3472 LLVMValueRef final_sample =
3473 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3474
3475 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3476 * resource descriptor is 0 (invalid),
3477 */
3478 LLVMValueRef fmask_desc =
3479 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3480 ctx->v8i32, "");
3481
3482 LLVMValueRef fmask_word1 =
3483 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3484 ctx->i32_1, "");
3485
3486 LLVMValueRef word1_is_nonzero =
3487 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3488 fmask_word1, ctx->i32_0, "");
3489
3490 /* Replace the MSAA sample index. */
3491 sample_index =
3492 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3493 final_sample, sample_index, "");
3494 return sample_index;
3495 }
3496
3497 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3498 const nir_intrinsic_instr *instr)
3499 {
3500 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3501
3502 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3503 LLVMValueRef coords[4];
3504 LLVMValueRef masks[] = {
3505 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3506 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3507 };
3508 LLVMValueRef res;
3509 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3510
3511 int count;
3512 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3513 bool is_array = glsl_sampler_type_is_array(type);
3514 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3515 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3516 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3517 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3518 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3519 count = image_type_to_components_count(dim, is_array);
3520
3521 if (is_ms) {
3522 LLVMValueRef fmask_load_address[3];
3523 int chan;
3524
3525 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3526 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3527 if (is_array)
3528 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3529 else
3530 fmask_load_address[2] = NULL;
3531 if (add_frag_pos) {
3532 for (chan = 0; chan < 2; ++chan)
3533 fmask_load_address[chan] =
3534 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3535 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3536 ctx->ac.i32, ""), "");
3537 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3538 }
3539 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3540 fmask_load_address[0],
3541 fmask_load_address[1],
3542 fmask_load_address[2],
3543 sample_index,
3544 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3545 }
3546 if (count == 1 && !gfx9_1d) {
3547 if (instr->src[0].ssa->num_components)
3548 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3549 else
3550 res = src0;
3551 } else {
3552 int chan;
3553 if (is_ms)
3554 count--;
3555 for (chan = 0; chan < count; ++chan) {
3556 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3557 }
3558 if (add_frag_pos) {
3559 for (chan = 0; chan < 2; ++chan)
3560 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3561 ctx->ac.i32, ""), "");
3562 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3563 count++;
3564 }
3565
3566 if (gfx9_1d) {
3567 if (is_array) {
3568 coords[2] = coords[1];
3569 coords[1] = ctx->ac.i32_0;
3570 } else
3571 coords[1] = ctx->ac.i32_0;
3572 count++;
3573 }
3574
3575 if (is_ms) {
3576 coords[count] = sample_index;
3577 count++;
3578 }
3579
3580 if (count == 3) {
3581 coords[3] = LLVMGetUndef(ctx->ac.i32);
3582 count = 4;
3583 }
3584 res = ac_build_gather_values(&ctx->ac, coords, count);
3585 }
3586 return res;
3587 }
3588
3589 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3590 const nir_intrinsic_instr *instr)
3591 {
3592 LLVMValueRef params[7];
3593 LLVMValueRef res;
3594 char intrinsic_name[64];
3595 const nir_variable *var = instr->variables[0]->var;
3596 const struct glsl_type *type = var->type;
3597
3598 if(instr->variables[0]->deref.child)
3599 type = instr->variables[0]->deref.child->type;
3600
3601 type = glsl_without_array(type);
3602
3603 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3604 if (dim == GLSL_SAMPLER_DIM_BUF) {
3605 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3606 unsigned num_channels = util_last_bit(mask);
3607 LLVMValueRef rsrc, vindex;
3608
3609 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3610 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3611 ctx->ac.i32_0, "");
3612
3613 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3614 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3615 ctx->ac.i32_0, num_channels,
3616 false, false);
3617 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3618
3619 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3620 res = ac_to_integer(&ctx->ac, res);
3621 } else {
3622 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3623 LLVMValueRef slc = ctx->ac.i1false;
3624
3625 params[0] = get_image_coords(ctx, instr);
3626 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3627 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3628 params[3] = (var->data.image._volatile || var->data.image.coherent) ?
3629 ctx->ac.i1true : ctx->ac.i1false;
3630 params[4] = slc;
3631 params[5] = ctx->ac.i1false;
3632 params[6] = da;
3633
3634 ac_get_image_intr_name("llvm.amdgcn.image.load",
3635 ctx->ac.v4f32, /* vdata */
3636 LLVMTypeOf(params[0]), /* coords */
3637 LLVMTypeOf(params[1]), /* rsrc */
3638 intrinsic_name, sizeof(intrinsic_name));
3639
3640 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3641 params, 7, AC_FUNC_ATTR_READONLY);
3642 }
3643 return ac_to_integer(&ctx->ac, res);
3644 }
3645
3646 static void visit_image_store(struct ac_nir_context *ctx,
3647 nir_intrinsic_instr *instr)
3648 {
3649 LLVMValueRef params[8];
3650 char intrinsic_name[64];
3651 const nir_variable *var = instr->variables[0]->var;
3652 const struct glsl_type *type = glsl_without_array(var->type);
3653 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3654 LLVMValueRef glc = ctx->ac.i1false;
3655 bool force_glc = ctx->ac.chip_class == SI;
3656 if (force_glc)
3657 glc = ctx->ac.i1true;
3658
3659 if (dim == GLSL_SAMPLER_DIM_BUF) {
3660 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3661 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3662 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3663 ctx->ac.i32_0, ""); /* vindex */
3664 params[3] = ctx->ac.i32_0; /* voffset */
3665 params[4] = glc; /* glc */
3666 params[5] = ctx->ac.i1false; /* slc */
3667 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3668 params, 6, 0);
3669 } else {
3670 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3671 LLVMValueRef slc = ctx->ac.i1false;
3672
3673 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3674 params[1] = get_image_coords(ctx, instr); /* coords */
3675 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3676 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3677 params[4] = (force_glc || var->data.image._volatile || var->data.image.coherent) ?
3678 ctx->ac.i1true : ctx->ac.i1false;
3679 params[5] = slc;
3680 params[6] = ctx->ac.i1false;
3681 params[7] = da;
3682
3683 ac_get_image_intr_name("llvm.amdgcn.image.store",
3684 LLVMTypeOf(params[0]), /* vdata */
3685 LLVMTypeOf(params[1]), /* coords */
3686 LLVMTypeOf(params[2]), /* rsrc */
3687 intrinsic_name, sizeof(intrinsic_name));
3688
3689 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3690 params, 8, 0);
3691 }
3692
3693 }
3694
3695 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3696 const nir_intrinsic_instr *instr)
3697 {
3698 LLVMValueRef params[7];
3699 int param_count = 0;
3700 const nir_variable *var = instr->variables[0]->var;
3701
3702 const char *atomic_name;
3703 char intrinsic_name[41];
3704 const struct glsl_type *type = glsl_without_array(var->type);
3705 MAYBE_UNUSED int length;
3706
3707 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3708
3709 switch (instr->intrinsic) {
3710 case nir_intrinsic_image_atomic_add:
3711 atomic_name = "add";
3712 break;
3713 case nir_intrinsic_image_atomic_min:
3714 atomic_name = is_unsigned ? "umin" : "smin";
3715 break;
3716 case nir_intrinsic_image_atomic_max:
3717 atomic_name = is_unsigned ? "umax" : "smax";
3718 break;
3719 case nir_intrinsic_image_atomic_and:
3720 atomic_name = "and";
3721 break;
3722 case nir_intrinsic_image_atomic_or:
3723 atomic_name = "or";
3724 break;
3725 case nir_intrinsic_image_atomic_xor:
3726 atomic_name = "xor";
3727 break;
3728 case nir_intrinsic_image_atomic_exchange:
3729 atomic_name = "swap";
3730 break;
3731 case nir_intrinsic_image_atomic_comp_swap:
3732 atomic_name = "cmpswap";
3733 break;
3734 default:
3735 abort();
3736 }
3737
3738 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3739 params[param_count++] = get_src(ctx, instr->src[3]);
3740 params[param_count++] = get_src(ctx, instr->src[2]);
3741
3742 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3743 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3744 NULL, true, true);
3745 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3746 ctx->ac.i32_0, ""); /* vindex */
3747 params[param_count++] = ctx->ac.i32_0; /* voffset */
3748 params[param_count++] = ctx->ac.i1false; /* slc */
3749
3750 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3751 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3752 } else {
3753 char coords_type[8];
3754
3755 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3756 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3757 NULL, true, true);
3758 params[param_count++] = ctx->ac.i1false; /* r128 */
3759 params[param_count++] = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3760 params[param_count++] = ctx->ac.i1false; /* slc */
3761
3762 build_int_type_name(LLVMTypeOf(coords),
3763 coords_type, sizeof(coords_type));
3764
3765 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3766 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3767 }
3768
3769 assert(length < sizeof(intrinsic_name));
3770 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3771 }
3772
3773 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3774 const nir_intrinsic_instr *instr)
3775 {
3776 const nir_variable *var = instr->variables[0]->var;
3777 const struct glsl_type *type = glsl_without_array(var->type);
3778
3779 struct ac_image_args args = { 0 };
3780 args.da = glsl_is_array_image(type);
3781 args.dmask = 0xf;
3782 args.resource = get_sampler_desc(ctx, instr->variables[0],
3783 AC_DESC_IMAGE, NULL, true, false);
3784 args.opcode = ac_image_get_resinfo;
3785 args.addr = ctx->ac.i32_0;
3786
3787 return ac_build_image_opcode(&ctx->ac, &args);
3788 }
3789
3790 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3791 const nir_intrinsic_instr *instr)
3792 {
3793 LLVMValueRef res;
3794 const nir_variable *var = instr->variables[0]->var;
3795 const struct glsl_type *type = glsl_without_array(var->type);
3796
3797 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3798 return get_buffer_size(ctx,
3799 get_sampler_desc(ctx, instr->variables[0],
3800 AC_DESC_BUFFER, NULL, true, false), true);
3801
3802 struct ac_image_args args = { 0 };
3803
3804 args.da = glsl_is_array_image(type);
3805 args.dmask = 0xf;
3806 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3807 args.opcode = ac_image_get_resinfo;
3808 args.addr = ctx->ac.i32_0;
3809
3810 res = ac_build_image_opcode(&ctx->ac, &args);
3811
3812 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3813
3814 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3815 glsl_sampler_type_is_array(type)) {
3816 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3817 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3818 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3819 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3820 }
3821 if (ctx->ac.chip_class >= GFX9 &&
3822 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3823 glsl_sampler_type_is_array(type)) {
3824 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3825 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3826 ctx->ac.i32_1, "");
3827
3828 }
3829 return res;
3830 }
3831
3832 #define NOOP_WAITCNT 0xf7f
3833 #define LGKM_CNT 0x07f
3834 #define VM_CNT 0xf70
3835
3836 static void emit_membar(struct ac_llvm_context *ac,
3837 const nir_intrinsic_instr *instr)
3838 {
3839 unsigned waitcnt = NOOP_WAITCNT;
3840
3841 switch (instr->intrinsic) {
3842 case nir_intrinsic_memory_barrier:
3843 case nir_intrinsic_group_memory_barrier:
3844 waitcnt &= VM_CNT & LGKM_CNT;
3845 break;
3846 case nir_intrinsic_memory_barrier_atomic_counter:
3847 case nir_intrinsic_memory_barrier_buffer:
3848 case nir_intrinsic_memory_barrier_image:
3849 waitcnt &= VM_CNT;
3850 break;
3851 case nir_intrinsic_memory_barrier_shared:
3852 waitcnt &= LGKM_CNT;
3853 break;
3854 default:
3855 break;
3856 }
3857 if (waitcnt != NOOP_WAITCNT)
3858 ac_build_waitcnt(ac, waitcnt);
3859 }
3860
3861 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3862 {
3863 /* SI only (thanks to a hw bug workaround):
3864 * The real barrier instruction isn’t needed, because an entire patch
3865 * always fits into a single wave.
3866 */
3867 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3868 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3869 return;
3870 }
3871 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3872 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3873 }
3874
3875 static void emit_discard(struct ac_nir_context *ctx,
3876 const nir_intrinsic_instr *instr)
3877 {
3878 LLVMValueRef cond;
3879
3880 if (instr->intrinsic == nir_intrinsic_discard_if) {
3881 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3882 get_src(ctx, instr->src[0]),
3883 ctx->ac.i32_0, "");
3884 } else {
3885 assert(instr->intrinsic == nir_intrinsic_discard);
3886 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3887 }
3888
3889 ac_build_kill_if_false(&ctx->ac, cond);
3890 }
3891
3892 static LLVMValueRef
3893 visit_load_helper_invocation(struct ac_nir_context *ctx)
3894 {
3895 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3896 "llvm.amdgcn.ps.live",
3897 ctx->ac.i1, NULL, 0,
3898 AC_FUNC_ATTR_READNONE);
3899 result = LLVMBuildNot(ctx->ac.builder, result, "");
3900 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3901 }
3902
3903 static LLVMValueRef
3904 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3905 {
3906 LLVMValueRef result;
3907 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3908 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3909 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3910
3911 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3912 }
3913
3914 static LLVMValueRef
3915 visit_load_subgroup_id(struct ac_nir_context *ctx)
3916 {
3917 if (ctx->stage == MESA_SHADER_COMPUTE) {
3918 LLVMValueRef result;
3919 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3920 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3921 return LLVMBuildLShr(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 6, false), "");
3922 } else {
3923 return LLVMConstInt(ctx->ac.i32, 0, false);
3924 }
3925 }
3926
3927 static LLVMValueRef
3928 visit_load_num_subgroups(struct ac_nir_context *ctx)
3929 {
3930 if (ctx->stage == MESA_SHADER_COMPUTE) {
3931 return LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3932 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
3933 } else {
3934 return LLVMConstInt(ctx->ac.i32, 1, false);
3935 }
3936 }
3937
3938 static LLVMValueRef
3939 visit_first_invocation(struct ac_nir_context *ctx)
3940 {
3941 LLVMValueRef active_set = ac_build_ballot(&ctx->ac, ctx->ac.i32_1);
3942
3943 /* The second argument is whether cttz(0) should be defined, but we do not care. */
3944 LLVMValueRef args[] = {active_set, LLVMConstInt(ctx->ac.i1, 0, false)};
3945 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3946 "llvm.cttz.i64",
3947 ctx->ac.i64, args, 2,
3948 AC_FUNC_ATTR_NOUNWIND |
3949 AC_FUNC_ATTR_READNONE);
3950
3951 return LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
3952 }
3953
3954 static LLVMValueRef
3955 visit_load_shared(struct ac_nir_context *ctx,
3956 const nir_intrinsic_instr *instr)
3957 {
3958 LLVMValueRef values[4], derived_ptr, index, ret;
3959
3960 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3961
3962 for (int chan = 0; chan < instr->num_components; chan++) {
3963 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3964 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3965 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3966 }
3967
3968 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3969 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3970 }
3971
3972 static void
3973 visit_store_shared(struct ac_nir_context *ctx,
3974 const nir_intrinsic_instr *instr)
3975 {
3976 LLVMValueRef derived_ptr, data,index;
3977 LLVMBuilderRef builder = ctx->ac.builder;
3978
3979 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3980 LLVMValueRef src = get_src(ctx, instr->src[0]);
3981
3982 int writemask = nir_intrinsic_write_mask(instr);
3983 for (int chan = 0; chan < 4; chan++) {
3984 if (!(writemask & (1 << chan))) {
3985 continue;
3986 }
3987 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3988 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3989 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3990 LLVMBuildStore(builder, data, derived_ptr);
3991 }
3992 }
3993
3994 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3995 const nir_intrinsic_instr *instr,
3996 LLVMValueRef ptr, int src_idx)
3997 {
3998 LLVMValueRef result;
3999 LLVMValueRef src = get_src(ctx, instr->src[src_idx]);
4000
4001 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
4002 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
4003 LLVMValueRef src1 = get_src(ctx, instr->src[src_idx + 1]);
4004 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
4005 ptr, src, src1,
4006 LLVMAtomicOrderingSequentiallyConsistent,
4007 LLVMAtomicOrderingSequentiallyConsistent,
4008 false);
4009 } else {
4010 LLVMAtomicRMWBinOp op;
4011 switch (instr->intrinsic) {
4012 case nir_intrinsic_var_atomic_add:
4013 case nir_intrinsic_shared_atomic_add:
4014 op = LLVMAtomicRMWBinOpAdd;
4015 break;
4016 case nir_intrinsic_var_atomic_umin:
4017 case nir_intrinsic_shared_atomic_umin:
4018 op = LLVMAtomicRMWBinOpUMin;
4019 break;
4020 case nir_intrinsic_var_atomic_umax:
4021 case nir_intrinsic_shared_atomic_umax:
4022 op = LLVMAtomicRMWBinOpUMax;
4023 break;
4024 case nir_intrinsic_var_atomic_imin:
4025 case nir_intrinsic_shared_atomic_imin:
4026 op = LLVMAtomicRMWBinOpMin;
4027 break;
4028 case nir_intrinsic_var_atomic_imax:
4029 case nir_intrinsic_shared_atomic_imax:
4030 op = LLVMAtomicRMWBinOpMax;
4031 break;
4032 case nir_intrinsic_var_atomic_and:
4033 case nir_intrinsic_shared_atomic_and:
4034 op = LLVMAtomicRMWBinOpAnd;
4035 break;
4036 case nir_intrinsic_var_atomic_or:
4037 case nir_intrinsic_shared_atomic_or:
4038 op = LLVMAtomicRMWBinOpOr;
4039 break;
4040 case nir_intrinsic_var_atomic_xor:
4041 case nir_intrinsic_shared_atomic_xor:
4042 op = LLVMAtomicRMWBinOpXor;
4043 break;
4044 case nir_intrinsic_var_atomic_exchange:
4045 case nir_intrinsic_shared_atomic_exchange:
4046 op = LLVMAtomicRMWBinOpXchg;
4047 break;
4048 default:
4049 return NULL;
4050 }
4051
4052 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4053 LLVMAtomicOrderingSequentiallyConsistent,
4054 false);
4055 }
4056 return result;
4057 }
4058
4059 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4060 enum glsl_interp_mode interp, unsigned location)
4061 {
4062 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4063
4064 switch (interp) {
4065 case INTERP_MODE_FLAT:
4066 default:
4067 return NULL;
4068 case INTERP_MODE_SMOOTH:
4069 case INTERP_MODE_NONE:
4070 if (location == INTERP_CENTER)
4071 return ctx->persp_center;
4072 else if (location == INTERP_CENTROID)
4073 return ctx->persp_centroid;
4074 else if (location == INTERP_SAMPLE)
4075 return ctx->persp_sample;
4076 break;
4077 case INTERP_MODE_NOPERSPECTIVE:
4078 if (location == INTERP_CENTER)
4079 return ctx->linear_center;
4080 else if (location == INTERP_CENTROID)
4081 return ctx->linear_centroid;
4082 else if (location == INTERP_SAMPLE)
4083 return ctx->linear_sample;
4084 break;
4085 }
4086 return NULL;
4087 }
4088
4089 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4090 LLVMValueRef sample_id)
4091 {
4092 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4093
4094 LLVMValueRef result;
4095 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4096
4097 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4098 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4099
4100 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4101 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4102
4103 return result;
4104 }
4105
4106 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4107 {
4108 LLVMValueRef values[2];
4109 LLVMValueRef pos[2];
4110
4111 pos[0] = ac_to_float(&ctx->ac, ctx->abi->frag_pos[0]);
4112 pos[1] = ac_to_float(&ctx->ac, ctx->abi->frag_pos[1]);
4113
4114 values[0] = ac_build_fract(&ctx->ac, pos[0], 32);
4115 values[1] = ac_build_fract(&ctx->ac, pos[1], 32);
4116 return ac_build_gather_values(&ctx->ac, values, 2);
4117 }
4118
4119 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4120 {
4121 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4122 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4123 ctx->options->key.fs.log2_num_samples :
4124 ctx->options->key.fs.log2_ps_iter_samples;
4125
4126 /* The bit pattern matches that used by fixed function fragment
4127 * processing. */
4128 static const uint16_t ps_iter_masks[] = {
4129 0xffff, /* not used */
4130 0x5555,
4131 0x1111,
4132 0x0101,
4133 0x0001,
4134 };
4135 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4136
4137 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4138
4139 LLVMValueRef result, sample_id;
4140 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4141 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4142 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4143 return result;
4144 }
4145
4146 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4147 const nir_intrinsic_instr *instr)
4148 {
4149 LLVMValueRef result[4];
4150 LLVMValueRef interp_param, attr_number;
4151 unsigned location;
4152 unsigned chan;
4153 LLVMValueRef src_c0 = NULL;
4154 LLVMValueRef src_c1 = NULL;
4155 LLVMValueRef src0 = NULL;
4156 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4157 switch (instr->intrinsic) {
4158 case nir_intrinsic_interp_var_at_centroid:
4159 location = INTERP_CENTROID;
4160 break;
4161 case nir_intrinsic_interp_var_at_sample:
4162 case nir_intrinsic_interp_var_at_offset:
4163 location = INTERP_CENTER;
4164 src0 = get_src(ctx, instr->src[0]);
4165 break;
4166 default:
4167 break;
4168 }
4169
4170 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4171 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4172 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4173 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4174 LLVMValueRef sample_position;
4175 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4176
4177 /* fetch sample ID */
4178 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4179
4180 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4181 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4182 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4183 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4184 }
4185 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4186 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4187
4188 if (location == INTERP_CENTER) {
4189 LLVMValueRef ij_out[2];
4190 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4191
4192 /*
4193 * take the I then J parameters, and the DDX/Y for it, and
4194 * calculate the IJ inputs for the interpolator.
4195 * temp1 = ddx * offset/sample.x + I;
4196 * interp_param.I = ddy * offset/sample.y + temp1;
4197 * temp1 = ddx * offset/sample.x + J;
4198 * interp_param.J = ddy * offset/sample.y + temp1;
4199 */
4200 for (unsigned i = 0; i < 2; i++) {
4201 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4202 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4203 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4204 ddxy_out, ix_ll, "");
4205 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4206 ddxy_out, iy_ll, "");
4207 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4208 interp_param, ix_ll, "");
4209 LLVMValueRef temp1, temp2;
4210
4211 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4212 ctx->ac.f32, "");
4213
4214 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4215 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4216
4217 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4218 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4219
4220 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4221 temp2, ctx->ac.i32, "");
4222 }
4223 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4224
4225 }
4226
4227 for (chan = 0; chan < 4; chan++) {
4228 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4229
4230 if (interp_param) {
4231 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4232 interp_param, ctx->ac.v2f32, "");
4233 LLVMValueRef i = LLVMBuildExtractElement(
4234 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4235 LLVMValueRef j = LLVMBuildExtractElement(
4236 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4237
4238 result[chan] = ac_build_fs_interp(&ctx->ac,
4239 llvm_chan, attr_number,
4240 ctx->abi->prim_mask, i, j);
4241 } else {
4242 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4243 LLVMConstInt(ctx->ac.i32, 2, false),
4244 llvm_chan, attr_number,
4245 ctx->abi->prim_mask);
4246 }
4247 }
4248 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4249 instr->variables[0]->var->data.location_frac);
4250 }
4251
4252 static void
4253 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4254 {
4255 LLVMValueRef gs_next_vertex;
4256 LLVMValueRef can_emit;
4257 int idx;
4258 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4259
4260 assert(stream == 0);
4261
4262 /* Write vertex attribute values to GSVS ring */
4263 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4264 ctx->gs_next_vertex,
4265 "");
4266
4267 /* If this thread has already emitted the declared maximum number of
4268 * vertices, kill it: excessive vertex emissions are not supposed to
4269 * have any effect, and GS threads have no externally observable
4270 * effects other than emitting vertices.
4271 */
4272 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4273 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4274 ac_build_kill_if_false(&ctx->ac, can_emit);
4275
4276 /* loop num outputs */
4277 idx = 0;
4278 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4279 LLVMValueRef *out_ptr = &addrs[i * 4];
4280 int length = 4;
4281 int slot = idx;
4282 int slot_inc = 1;
4283
4284 if (!(ctx->output_mask & (1ull << i)))
4285 continue;
4286
4287 if (i == VARYING_SLOT_CLIP_DIST0) {
4288 /* pack clip and cull into a single set of slots */
4289 length = ctx->num_output_clips + ctx->num_output_culls;
4290 if (length > 4)
4291 slot_inc = 2;
4292 }
4293 for (unsigned j = 0; j < length; j++) {
4294 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4295 out_ptr[j], "");
4296 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4297 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4298 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4299
4300 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4301
4302 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4303 out_val, 1,
4304 voffset, ctx->gs2vs_offset, 0,
4305 1, 1, true, true);
4306 }
4307 idx += slot_inc;
4308 }
4309
4310 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4311 ctx->ac.i32_1, "");
4312 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4313
4314 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4315 }
4316
4317 static void
4318 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4319 {
4320 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4321 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4322 }
4323
4324 static LLVMValueRef
4325 load_tess_coord(struct ac_shader_abi *abi)
4326 {
4327 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4328
4329 LLVMValueRef coord[4] = {
4330 ctx->tes_u,
4331 ctx->tes_v,
4332 ctx->ac.f32_0,
4333 ctx->ac.f32_0,
4334 };
4335
4336 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4337 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4338 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4339
4340 return ac_build_gather_values(&ctx->ac, coord, 3);
4341 }
4342
4343 static LLVMValueRef
4344 load_patch_vertices_in(struct ac_shader_abi *abi)
4345 {
4346 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4347 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4348 }
4349
4350 static void visit_intrinsic(struct ac_nir_context *ctx,
4351 nir_intrinsic_instr *instr)
4352 {
4353 LLVMValueRef result = NULL;
4354
4355 switch (instr->intrinsic) {
4356 case nir_intrinsic_ballot:
4357 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4358 break;
4359 case nir_intrinsic_read_invocation:
4360 case nir_intrinsic_read_first_invocation: {
4361 LLVMValueRef args[2];
4362
4363 /* Value */
4364 args[0] = get_src(ctx, instr->src[0]);
4365
4366 unsigned num_args;
4367 const char *intr_name;
4368 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4369 num_args = 2;
4370 intr_name = "llvm.amdgcn.readlane";
4371
4372 /* Invocation */
4373 args[1] = get_src(ctx, instr->src[1]);
4374 } else {
4375 num_args = 1;
4376 intr_name = "llvm.amdgcn.readfirstlane";
4377 }
4378
4379 /* We currently have no other way to prevent LLVM from lifting the icmp
4380 * calls to a dominating basic block.
4381 */
4382 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4383
4384 result = ac_build_intrinsic(&ctx->ac, intr_name,
4385 ctx->ac.i32, args, num_args,
4386 AC_FUNC_ATTR_READNONE |
4387 AC_FUNC_ATTR_CONVERGENT);
4388 break;
4389 }
4390 case nir_intrinsic_load_subgroup_invocation:
4391 result = ac_get_thread_id(&ctx->ac);
4392 break;
4393 case nir_intrinsic_load_work_group_id: {
4394 LLVMValueRef values[3];
4395
4396 for (int i = 0; i < 3; i++) {
4397 values[i] = ctx->abi->workgroup_ids[i] ?
4398 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4399 }
4400
4401 result = ac_build_gather_values(&ctx->ac, values, 3);
4402 break;
4403 }
4404 case nir_intrinsic_load_base_vertex: {
4405 result = ctx->abi->load_base_vertex(ctx->abi);
4406 break;
4407 }
4408 case nir_intrinsic_load_local_group_size:
4409 result = ctx->abi->load_local_group_size(ctx->abi);
4410 break;
4411 case nir_intrinsic_load_vertex_id:
4412 result = LLVMBuildAdd(ctx->ac.builder, ctx->abi->vertex_id,
4413 ctx->abi->base_vertex, "");
4414 break;
4415 case nir_intrinsic_load_vertex_id_zero_base: {
4416 result = ctx->abi->vertex_id;
4417 break;
4418 }
4419 case nir_intrinsic_load_local_invocation_id: {
4420 result = ctx->abi->local_invocation_ids;
4421 break;
4422 }
4423 case nir_intrinsic_load_base_instance:
4424 result = ctx->abi->start_instance;
4425 break;
4426 case nir_intrinsic_load_draw_id:
4427 result = ctx->abi->draw_id;
4428 break;
4429 case nir_intrinsic_load_view_index:
4430 result = ctx->abi->view_index;
4431 break;
4432 case nir_intrinsic_load_invocation_id:
4433 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4434 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4435 else
4436 result = ctx->abi->gs_invocation_id;
4437 break;
4438 case nir_intrinsic_load_primitive_id:
4439 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4440 result = ctx->abi->gs_prim_id;
4441 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4442 result = ctx->abi->tcs_patch_id;
4443 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4444 result = ctx->abi->tes_patch_id;
4445 } else
4446 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4447 break;
4448 case nir_intrinsic_load_sample_id:
4449 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4450 break;
4451 case nir_intrinsic_load_sample_pos:
4452 result = load_sample_pos(ctx);
4453 break;
4454 case nir_intrinsic_load_sample_mask_in:
4455 result = ctx->abi->load_sample_mask_in(ctx->abi);
4456 break;
4457 case nir_intrinsic_load_frag_coord: {
4458 LLVMValueRef values[4] = {
4459 ctx->abi->frag_pos[0],
4460 ctx->abi->frag_pos[1],
4461 ctx->abi->frag_pos[2],
4462 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4463 };
4464 result = ac_build_gather_values(&ctx->ac, values, 4);
4465 break;
4466 }
4467 case nir_intrinsic_load_front_face:
4468 result = ctx->abi->front_face;
4469 break;
4470 case nir_intrinsic_load_helper_invocation:
4471 result = visit_load_helper_invocation(ctx);
4472 break;
4473 case nir_intrinsic_load_instance_id:
4474 result = ctx->abi->instance_id;
4475 break;
4476 case nir_intrinsic_load_num_work_groups:
4477 result = ctx->abi->num_work_groups;
4478 break;
4479 case nir_intrinsic_load_local_invocation_index:
4480 result = visit_load_local_invocation_index(ctx);
4481 break;
4482 case nir_intrinsic_load_subgroup_id:
4483 result = visit_load_subgroup_id(ctx);
4484 break;
4485 case nir_intrinsic_load_num_subgroups:
4486 result = visit_load_num_subgroups(ctx);
4487 break;
4488 case nir_intrinsic_first_invocation:
4489 result = visit_first_invocation(ctx);
4490 break;
4491 case nir_intrinsic_load_push_constant:
4492 result = visit_load_push_constant(ctx, instr);
4493 break;
4494 case nir_intrinsic_vulkan_resource_index: {
4495 LLVMValueRef index = get_src(ctx, instr->src[0]);
4496 unsigned desc_set = nir_intrinsic_desc_set(instr);
4497 unsigned binding = nir_intrinsic_binding(instr);
4498
4499 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4500 binding);
4501 break;
4502 }
4503 case nir_intrinsic_vulkan_resource_reindex:
4504 result = visit_vulkan_resource_reindex(ctx, instr);
4505 break;
4506 case nir_intrinsic_store_ssbo:
4507 visit_store_ssbo(ctx, instr);
4508 break;
4509 case nir_intrinsic_load_ssbo:
4510 result = visit_load_buffer(ctx, instr);
4511 break;
4512 case nir_intrinsic_ssbo_atomic_add:
4513 case nir_intrinsic_ssbo_atomic_imin:
4514 case nir_intrinsic_ssbo_atomic_umin:
4515 case nir_intrinsic_ssbo_atomic_imax:
4516 case nir_intrinsic_ssbo_atomic_umax:
4517 case nir_intrinsic_ssbo_atomic_and:
4518 case nir_intrinsic_ssbo_atomic_or:
4519 case nir_intrinsic_ssbo_atomic_xor:
4520 case nir_intrinsic_ssbo_atomic_exchange:
4521 case nir_intrinsic_ssbo_atomic_comp_swap:
4522 result = visit_atomic_ssbo(ctx, instr);
4523 break;
4524 case nir_intrinsic_load_ubo:
4525 result = visit_load_ubo_buffer(ctx, instr);
4526 break;
4527 case nir_intrinsic_get_buffer_size:
4528 result = visit_get_buffer_size(ctx, instr);
4529 break;
4530 case nir_intrinsic_load_var:
4531 result = visit_load_var(ctx, instr);
4532 break;
4533 case nir_intrinsic_store_var:
4534 visit_store_var(ctx, instr);
4535 break;
4536 case nir_intrinsic_load_shared:
4537 result = visit_load_shared(ctx, instr);
4538 break;
4539 case nir_intrinsic_store_shared:
4540 visit_store_shared(ctx, instr);
4541 break;
4542 case nir_intrinsic_image_samples:
4543 result = visit_image_samples(ctx, instr);
4544 break;
4545 case nir_intrinsic_image_load:
4546 result = visit_image_load(ctx, instr);
4547 break;
4548 case nir_intrinsic_image_store:
4549 visit_image_store(ctx, instr);
4550 break;
4551 case nir_intrinsic_image_atomic_add:
4552 case nir_intrinsic_image_atomic_min:
4553 case nir_intrinsic_image_atomic_max:
4554 case nir_intrinsic_image_atomic_and:
4555 case nir_intrinsic_image_atomic_or:
4556 case nir_intrinsic_image_atomic_xor:
4557 case nir_intrinsic_image_atomic_exchange:
4558 case nir_intrinsic_image_atomic_comp_swap:
4559 result = visit_image_atomic(ctx, instr);
4560 break;
4561 case nir_intrinsic_image_size:
4562 result = visit_image_size(ctx, instr);
4563 break;
4564 case nir_intrinsic_shader_clock:
4565 result = ac_build_shader_clock(&ctx->ac);
4566 break;
4567 case nir_intrinsic_discard:
4568 case nir_intrinsic_discard_if:
4569 emit_discard(ctx, instr);
4570 break;
4571 case nir_intrinsic_memory_barrier:
4572 case nir_intrinsic_group_memory_barrier:
4573 case nir_intrinsic_memory_barrier_atomic_counter:
4574 case nir_intrinsic_memory_barrier_buffer:
4575 case nir_intrinsic_memory_barrier_image:
4576 case nir_intrinsic_memory_barrier_shared:
4577 emit_membar(&ctx->ac, instr);
4578 break;
4579 case nir_intrinsic_barrier:
4580 emit_barrier(&ctx->ac, ctx->stage);
4581 break;
4582 case nir_intrinsic_shared_atomic_add:
4583 case nir_intrinsic_shared_atomic_imin:
4584 case nir_intrinsic_shared_atomic_umin:
4585 case nir_intrinsic_shared_atomic_imax:
4586 case nir_intrinsic_shared_atomic_umax:
4587 case nir_intrinsic_shared_atomic_and:
4588 case nir_intrinsic_shared_atomic_or:
4589 case nir_intrinsic_shared_atomic_xor:
4590 case nir_intrinsic_shared_atomic_exchange:
4591 case nir_intrinsic_shared_atomic_comp_swap: {
4592 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
4593 result = visit_var_atomic(ctx, instr, ptr, 1);
4594 break;
4595 }
4596 case nir_intrinsic_var_atomic_add:
4597 case nir_intrinsic_var_atomic_imin:
4598 case nir_intrinsic_var_atomic_umin:
4599 case nir_intrinsic_var_atomic_imax:
4600 case nir_intrinsic_var_atomic_umax:
4601 case nir_intrinsic_var_atomic_and:
4602 case nir_intrinsic_var_atomic_or:
4603 case nir_intrinsic_var_atomic_xor:
4604 case nir_intrinsic_var_atomic_exchange:
4605 case nir_intrinsic_var_atomic_comp_swap: {
4606 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4607 result = visit_var_atomic(ctx, instr, ptr, 0);
4608 break;
4609 }
4610 case nir_intrinsic_interp_var_at_centroid:
4611 case nir_intrinsic_interp_var_at_sample:
4612 case nir_intrinsic_interp_var_at_offset:
4613 result = visit_interp(ctx, instr);
4614 break;
4615 case nir_intrinsic_emit_vertex:
4616 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4617 break;
4618 case nir_intrinsic_end_primitive:
4619 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4620 break;
4621 case nir_intrinsic_load_tess_coord:
4622 result = ctx->abi->load_tess_coord(ctx->abi);
4623 break;
4624 case nir_intrinsic_load_tess_level_outer:
4625 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4626 break;
4627 case nir_intrinsic_load_tess_level_inner:
4628 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4629 break;
4630 case nir_intrinsic_load_patch_vertices_in:
4631 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4632 break;
4633 case nir_intrinsic_vote_all: {
4634 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4635 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4636 break;
4637 }
4638 case nir_intrinsic_vote_any: {
4639 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4640 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4641 break;
4642 }
4643 default:
4644 fprintf(stderr, "Unknown intrinsic: ");
4645 nir_print_instr(&instr->instr, stderr);
4646 fprintf(stderr, "\n");
4647 break;
4648 }
4649 if (result) {
4650 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4651 }
4652 }
4653
4654 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
4655 {
4656 return abi->base_vertex;
4657 }
4658
4659 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4660 LLVMValueRef buffer_ptr, bool write)
4661 {
4662 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4663 LLVMValueRef result;
4664
4665 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4666
4667 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4668 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4669
4670 return result;
4671 }
4672
4673 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4674 {
4675 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4676 LLVMValueRef result;
4677
4678 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4679
4680 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4681 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4682
4683 return result;
4684 }
4685
4686 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4687 unsigned descriptor_set,
4688 unsigned base_index,
4689 unsigned constant_index,
4690 LLVMValueRef index,
4691 enum ac_descriptor_type desc_type,
4692 bool image, bool write)
4693 {
4694 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4695 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4696 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4697 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4698 unsigned offset = binding->offset;
4699 unsigned stride = binding->size;
4700 unsigned type_size;
4701 LLVMBuilderRef builder = ctx->ac.builder;
4702 LLVMTypeRef type;
4703
4704 assert(base_index < layout->binding_count);
4705
4706 switch (desc_type) {
4707 case AC_DESC_IMAGE:
4708 type = ctx->ac.v8i32;
4709 type_size = 32;
4710 break;
4711 case AC_DESC_FMASK:
4712 type = ctx->ac.v8i32;
4713 offset += 32;
4714 type_size = 32;
4715 break;
4716 case AC_DESC_SAMPLER:
4717 type = ctx->ac.v4i32;
4718 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4719 offset += 64;
4720
4721 type_size = 16;
4722 break;
4723 case AC_DESC_BUFFER:
4724 type = ctx->ac.v4i32;
4725 type_size = 16;
4726 break;
4727 default:
4728 unreachable("invalid desc_type\n");
4729 }
4730
4731 offset += constant_index * stride;
4732
4733 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4734 (!index || binding->immutable_samplers_equal)) {
4735 if (binding->immutable_samplers_equal)
4736 constant_index = 0;
4737
4738 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4739
4740 LLVMValueRef constants[] = {
4741 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4742 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4743 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4744 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4745 };
4746 return ac_build_gather_values(&ctx->ac, constants, 4);
4747 }
4748
4749 assert(stride % type_size == 0);
4750
4751 if (!index)
4752 index = ctx->ac.i32_0;
4753
4754 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4755
4756 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4757 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4758
4759 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4760 }
4761
4762 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4763 const nir_deref_var *deref,
4764 enum ac_descriptor_type desc_type,
4765 const nir_tex_instr *tex_instr,
4766 bool image, bool write)
4767 {
4768 LLVMValueRef index = NULL;
4769 unsigned constant_index = 0;
4770 unsigned descriptor_set;
4771 unsigned base_index;
4772
4773 if (!deref) {
4774 assert(tex_instr && !image);
4775 descriptor_set = 0;
4776 base_index = tex_instr->sampler_index;
4777 } else {
4778 const nir_deref *tail = &deref->deref;
4779 while (tail->child) {
4780 const nir_deref_array *child = nir_deref_as_array(tail->child);
4781 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4782
4783 if (!array_size)
4784 array_size = 1;
4785
4786 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4787
4788 if (child->deref_array_type == nir_deref_array_type_indirect) {
4789 LLVMValueRef indirect = get_src(ctx, child->indirect);
4790
4791 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4792 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4793
4794 if (!index)
4795 index = indirect;
4796 else
4797 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4798 }
4799
4800 constant_index += child->base_offset * array_size;
4801
4802 tail = &child->deref;
4803 }
4804 descriptor_set = deref->var->data.descriptor_set;
4805 base_index = deref->var->data.binding;
4806 }
4807
4808 return ctx->abi->load_sampler_desc(ctx->abi,
4809 descriptor_set,
4810 base_index,
4811 constant_index, index,
4812 desc_type, image, write);
4813 }
4814
4815 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4816 struct ac_image_args *args,
4817 const nir_tex_instr *instr,
4818 nir_texop op,
4819 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4820 LLVMValueRef *param, unsigned count,
4821 unsigned dmask)
4822 {
4823 unsigned is_rect = 0;
4824 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4825
4826 if (op == nir_texop_lod)
4827 da = false;
4828 /* Pad to power of two vector */
4829 while (count < util_next_power_of_two(count))
4830 param[count++] = LLVMGetUndef(ctx->i32);
4831
4832 if (count > 1)
4833 args->addr = ac_build_gather_values(ctx, param, count);
4834 else
4835 args->addr = param[0];
4836
4837 args->resource = res_ptr;
4838 args->sampler = samp_ptr;
4839
4840 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4841 args->addr = param[0];
4842 return;
4843 }
4844
4845 args->dmask = dmask;
4846 args->unorm = is_rect;
4847 args->da = da;
4848 }
4849
4850 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4851 *
4852 * SI-CI:
4853 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4854 * filtering manually. The driver sets img7 to a mask clearing
4855 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4856 * s_and_b32 samp0, samp0, img7
4857 *
4858 * VI:
4859 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4860 */
4861 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4862 LLVMValueRef res, LLVMValueRef samp)
4863 {
4864 LLVMBuilderRef builder = ctx->ac.builder;
4865 LLVMValueRef img7, samp0;
4866
4867 if (ctx->ac.chip_class >= VI)
4868 return samp;
4869
4870 img7 = LLVMBuildExtractElement(builder, res,
4871 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4872 samp0 = LLVMBuildExtractElement(builder, samp,
4873 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4874 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4875 return LLVMBuildInsertElement(builder, samp, samp0,
4876 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4877 }
4878
4879 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4880 nir_tex_instr *instr,
4881 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4882 LLVMValueRef *fmask_ptr)
4883 {
4884 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4885 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4886 else
4887 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4888 if (samp_ptr) {
4889 if (instr->sampler)
4890 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4891 else
4892 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4893 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4894 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4895 }
4896 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4897 instr->op == nir_texop_samples_identical))
4898 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4899 }
4900
4901 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4902 LLVMValueRef coord)
4903 {
4904 coord = ac_to_float(ctx, coord);
4905 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4906 coord = ac_to_integer(ctx, coord);
4907 return coord;
4908 }
4909
4910 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4911 {
4912 LLVMValueRef result = NULL;
4913 struct ac_image_args args = { 0 };
4914 unsigned dmask = 0xf;
4915 LLVMValueRef address[16];
4916 LLVMValueRef coords[5];
4917 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4918 LLVMValueRef bias = NULL, offsets = NULL;
4919 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4920 LLVMValueRef ddx = NULL, ddy = NULL;
4921 LLVMValueRef derivs[6];
4922 unsigned chan, count = 0;
4923 unsigned const_src = 0, num_deriv_comp = 0;
4924 bool lod_is_zero = false;
4925
4926 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4927
4928 for (unsigned i = 0; i < instr->num_srcs; i++) {
4929 switch (instr->src[i].src_type) {
4930 case nir_tex_src_coord:
4931 coord = get_src(ctx, instr->src[i].src);
4932 break;
4933 case nir_tex_src_projector:
4934 break;
4935 case nir_tex_src_comparator:
4936 comparator = get_src(ctx, instr->src[i].src);
4937 break;
4938 case nir_tex_src_offset:
4939 offsets = get_src(ctx, instr->src[i].src);
4940 const_src = i;
4941 break;
4942 case nir_tex_src_bias:
4943 bias = get_src(ctx, instr->src[i].src);
4944 break;
4945 case nir_tex_src_lod: {
4946 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4947
4948 if (val && val->i32[0] == 0)
4949 lod_is_zero = true;
4950 lod = get_src(ctx, instr->src[i].src);
4951 break;
4952 }
4953 case nir_tex_src_ms_index:
4954 sample_index = get_src(ctx, instr->src[i].src);
4955 break;
4956 case nir_tex_src_ms_mcs:
4957 break;
4958 case nir_tex_src_ddx:
4959 ddx = get_src(ctx, instr->src[i].src);
4960 num_deriv_comp = instr->src[i].src.ssa->num_components;
4961 break;
4962 case nir_tex_src_ddy:
4963 ddy = get_src(ctx, instr->src[i].src);
4964 break;
4965 case nir_tex_src_texture_offset:
4966 case nir_tex_src_sampler_offset:
4967 case nir_tex_src_plane:
4968 default:
4969 break;
4970 }
4971 }
4972
4973 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4974 result = get_buffer_size(ctx, res_ptr, true);
4975 goto write_result;
4976 }
4977
4978 if (instr->op == nir_texop_texture_samples) {
4979 LLVMValueRef res, samples, is_msaa;
4980 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4981 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4982 LLVMConstInt(ctx->ac.i32, 3, false), "");
4983 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4984 LLVMConstInt(ctx->ac.i32, 28, false), "");
4985 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4986 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4987 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4988 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4989
4990 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4991 LLVMConstInt(ctx->ac.i32, 16, false), "");
4992 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4993 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4994 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4995 samples, "");
4996 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4997 ctx->ac.i32_1, "");
4998 result = samples;
4999 goto write_result;
5000 }
5001
5002 if (coord)
5003 for (chan = 0; chan < instr->coord_components; chan++)
5004 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
5005
5006 if (offsets && instr->op != nir_texop_txf) {
5007 LLVMValueRef offset[3], pack;
5008 for (chan = 0; chan < 3; ++chan)
5009 offset[chan] = ctx->ac.i32_0;
5010
5011 args.offset = true;
5012 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
5013 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
5014 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
5015 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
5016 if (chan)
5017 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
5018 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
5019 }
5020 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
5021 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
5022 address[count++] = pack;
5023
5024 }
5025 /* pack LOD bias value */
5026 if (instr->op == nir_texop_txb && bias) {
5027 address[count++] = bias;
5028 }
5029
5030 /* Pack depth comparison value */
5031 if (instr->is_shadow && comparator) {
5032 LLVMValueRef z = ac_to_float(&ctx->ac,
5033 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
5034
5035 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
5036 * so the depth comparison value isn't clamped for Z16 and
5037 * Z24 anymore. Do it manually here.
5038 *
5039 * It's unnecessary if the original texture format was
5040 * Z32_FLOAT, but we don't know that here.
5041 */
5042 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5043 z = ac_build_clamp(&ctx->ac, z);
5044
5045 address[count++] = z;
5046 }
5047
5048 /* pack derivatives */
5049 if (ddx || ddy) {
5050 int num_src_deriv_channels, num_dest_deriv_channels;
5051 switch (instr->sampler_dim) {
5052 case GLSL_SAMPLER_DIM_3D:
5053 case GLSL_SAMPLER_DIM_CUBE:
5054 num_deriv_comp = 3;
5055 num_src_deriv_channels = 3;
5056 num_dest_deriv_channels = 3;
5057 break;
5058 case GLSL_SAMPLER_DIM_2D:
5059 default:
5060 num_src_deriv_channels = 2;
5061 num_dest_deriv_channels = 2;
5062 num_deriv_comp = 2;
5063 break;
5064 case GLSL_SAMPLER_DIM_1D:
5065 num_src_deriv_channels = 1;
5066 if (ctx->ac.chip_class >= GFX9) {
5067 num_dest_deriv_channels = 2;
5068 num_deriv_comp = 2;
5069 } else {
5070 num_dest_deriv_channels = 1;
5071 num_deriv_comp = 1;
5072 }
5073 break;
5074 }
5075
5076 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5077 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5078 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5079 }
5080 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5081 derivs[i] = ctx->ac.f32_0;
5082 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5083 }
5084 }
5085
5086 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5087 for (chan = 0; chan < instr->coord_components; chan++)
5088 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5089 if (instr->coord_components == 3)
5090 coords[3] = LLVMGetUndef(ctx->ac.f32);
5091 ac_prepare_cube_coords(&ctx->ac,
5092 instr->op == nir_texop_txd, instr->is_array,
5093 instr->op == nir_texop_lod, coords, derivs);
5094 if (num_deriv_comp)
5095 num_deriv_comp--;
5096 }
5097
5098 if (ddx || ddy) {
5099 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5100 address[count++] = derivs[i];
5101 }
5102
5103 /* Pack texture coordinates */
5104 if (coord) {
5105 address[count++] = coords[0];
5106 if (instr->coord_components > 1) {
5107 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5108 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5109 }
5110 address[count++] = coords[1];
5111 }
5112 if (instr->coord_components > 2) {
5113 if ((instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
5114 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
5115 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
5116 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
5117 instr->is_array &&
5118 instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
5119 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5120 }
5121 address[count++] = coords[2];
5122 }
5123
5124 if (ctx->ac.chip_class >= GFX9) {
5125 LLVMValueRef filler;
5126 if (instr->op == nir_texop_txf)
5127 filler = ctx->ac.i32_0;
5128 else
5129 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5130
5131 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5132 /* No nir_texop_lod, because it does not take a slice
5133 * even with array textures. */
5134 if (instr->is_array && instr->op != nir_texop_lod ) {
5135 address[count] = address[count - 1];
5136 address[count - 1] = filler;
5137 count++;
5138 } else
5139 address[count++] = filler;
5140 }
5141 }
5142 }
5143
5144 /* Pack LOD */
5145 if (lod && ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && !lod_is_zero)) {
5146 address[count++] = lod;
5147 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5148 address[count++] = sample_index;
5149 } else if(instr->op == nir_texop_txs) {
5150 count = 0;
5151 if (lod)
5152 address[count++] = lod;
5153 else
5154 address[count++] = ctx->ac.i32_0;
5155 }
5156
5157 for (chan = 0; chan < count; chan++) {
5158 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5159 address[chan], ctx->ac.i32, "");
5160 }
5161
5162 if (instr->op == nir_texop_samples_identical) {
5163 LLVMValueRef txf_address[4];
5164 struct ac_image_args txf_args = { 0 };
5165 unsigned txf_count = count;
5166 memcpy(txf_address, address, sizeof(txf_address));
5167
5168 if (!instr->is_array)
5169 txf_address[2] = ctx->ac.i32_0;
5170 txf_address[3] = ctx->ac.i32_0;
5171
5172 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5173 fmask_ptr, NULL,
5174 txf_address, txf_count, 0xf);
5175
5176 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5177
5178 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5179 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5180 goto write_result;
5181 }
5182
5183 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5184 instr->op != nir_texop_txs) {
5185 unsigned sample_chan = instr->is_array ? 3 : 2;
5186 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5187 address[0],
5188 address[1],
5189 instr->is_array ? address[2] : NULL,
5190 address[sample_chan],
5191 fmask_ptr);
5192 }
5193
5194 if (offsets && instr->op == nir_texop_txf) {
5195 nir_const_value *const_offset =
5196 nir_src_as_const_value(instr->src[const_src].src);
5197 int num_offsets = instr->src[const_src].src.ssa->num_components;
5198 assert(const_offset);
5199 num_offsets = MIN2(num_offsets, instr->coord_components);
5200 if (num_offsets > 2)
5201 address[2] = LLVMBuildAdd(ctx->ac.builder,
5202 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5203 if (num_offsets > 1)
5204 address[1] = LLVMBuildAdd(ctx->ac.builder,
5205 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5206 address[0] = LLVMBuildAdd(ctx->ac.builder,
5207 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5208
5209 }
5210
5211 /* TODO TG4 support */
5212 if (instr->op == nir_texop_tg4) {
5213 if (instr->is_shadow)
5214 dmask = 1;
5215 else
5216 dmask = 1 << instr->component;
5217 }
5218 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5219 res_ptr, samp_ptr, address, count, dmask);
5220
5221 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5222
5223 if (instr->op == nir_texop_query_levels)
5224 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5225 else if (instr->is_shadow && instr->is_new_style_shadow &&
5226 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5227 instr->op != nir_texop_tg4)
5228 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5229 else if (instr->op == nir_texop_txs &&
5230 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5231 instr->is_array) {
5232 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5233 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5234 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5235 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5236 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5237 } else if (ctx->ac.chip_class >= GFX9 &&
5238 instr->op == nir_texop_txs &&
5239 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5240 instr->is_array) {
5241 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5242 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5243 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5244 ctx->ac.i32_1, "");
5245 } else if (instr->dest.ssa.num_components != 4)
5246 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5247
5248 write_result:
5249 if (result) {
5250 assert(instr->dest.is_ssa);
5251 result = ac_to_integer(&ctx->ac, result);
5252 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5253 }
5254 }
5255
5256
5257 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5258 {
5259 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5260 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5261
5262 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5263 _mesa_hash_table_insert(ctx->phis, instr, result);
5264 }
5265
5266 static void visit_post_phi(struct ac_nir_context *ctx,
5267 nir_phi_instr *instr,
5268 LLVMValueRef llvm_phi)
5269 {
5270 nir_foreach_phi_src(src, instr) {
5271 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5272 LLVMValueRef llvm_src = get_src(ctx, src->src);
5273
5274 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5275 }
5276 }
5277
5278 static void phi_post_pass(struct ac_nir_context *ctx)
5279 {
5280 struct hash_entry *entry;
5281 hash_table_foreach(ctx->phis, entry) {
5282 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5283 (LLVMValueRef)entry->data);
5284 }
5285 }
5286
5287
5288 static void visit_ssa_undef(struct ac_nir_context *ctx,
5289 const nir_ssa_undef_instr *instr)
5290 {
5291 unsigned num_components = instr->def.num_components;
5292 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5293 LLVMValueRef undef;
5294
5295 if (num_components == 1)
5296 undef = LLVMGetUndef(type);
5297 else {
5298 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5299 }
5300 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5301 }
5302
5303 static void visit_jump(struct ac_llvm_context *ctx,
5304 const nir_jump_instr *instr)
5305 {
5306 switch (instr->type) {
5307 case nir_jump_break:
5308 ac_build_break(ctx);
5309 break;
5310 case nir_jump_continue:
5311 ac_build_continue(ctx);
5312 break;
5313 default:
5314 fprintf(stderr, "Unknown NIR jump instr: ");
5315 nir_print_instr(&instr->instr, stderr);
5316 fprintf(stderr, "\n");
5317 abort();
5318 }
5319 }
5320
5321 static void visit_cf_list(struct ac_nir_context *ctx,
5322 struct exec_list *list);
5323
5324 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5325 {
5326 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5327 nir_foreach_instr(instr, block)
5328 {
5329 switch (instr->type) {
5330 case nir_instr_type_alu:
5331 visit_alu(ctx, nir_instr_as_alu(instr));
5332 break;
5333 case nir_instr_type_load_const:
5334 visit_load_const(ctx, nir_instr_as_load_const(instr));
5335 break;
5336 case nir_instr_type_intrinsic:
5337 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5338 break;
5339 case nir_instr_type_tex:
5340 visit_tex(ctx, nir_instr_as_tex(instr));
5341 break;
5342 case nir_instr_type_phi:
5343 visit_phi(ctx, nir_instr_as_phi(instr));
5344 break;
5345 case nir_instr_type_ssa_undef:
5346 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5347 break;
5348 case nir_instr_type_jump:
5349 visit_jump(&ctx->ac, nir_instr_as_jump(instr));
5350 break;
5351 default:
5352 fprintf(stderr, "Unknown NIR instr type: ");
5353 nir_print_instr(instr, stderr);
5354 fprintf(stderr, "\n");
5355 abort();
5356 }
5357 }
5358
5359 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5360 }
5361
5362 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5363 {
5364 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5365
5366 nir_block *then_block =
5367 (nir_block *) exec_list_get_head(&if_stmt->then_list);
5368
5369 ac_build_uif(&ctx->ac, value, then_block->index);
5370
5371 visit_cf_list(ctx, &if_stmt->then_list);
5372
5373 if (!exec_list_is_empty(&if_stmt->else_list)) {
5374 nir_block *else_block =
5375 (nir_block *) exec_list_get_head(&if_stmt->else_list);
5376
5377 ac_build_else(&ctx->ac, else_block->index);
5378 visit_cf_list(ctx, &if_stmt->else_list);
5379 }
5380
5381 ac_build_endif(&ctx->ac, then_block->index);
5382 }
5383
5384 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5385 {
5386 nir_block *first_loop_block =
5387 (nir_block *) exec_list_get_head(&loop->body);
5388
5389 ac_build_bgnloop(&ctx->ac, first_loop_block->index);
5390
5391 visit_cf_list(ctx, &loop->body);
5392
5393 ac_build_endloop(&ctx->ac, first_loop_block->index);
5394 }
5395
5396 static void visit_cf_list(struct ac_nir_context *ctx,
5397 struct exec_list *list)
5398 {
5399 foreach_list_typed(nir_cf_node, node, node, list)
5400 {
5401 switch (node->type) {
5402 case nir_cf_node_block:
5403 visit_block(ctx, nir_cf_node_as_block(node));
5404 break;
5405
5406 case nir_cf_node_if:
5407 visit_if(ctx, nir_cf_node_as_if(node));
5408 break;
5409
5410 case nir_cf_node_loop:
5411 visit_loop(ctx, nir_cf_node_as_loop(node));
5412 break;
5413
5414 default:
5415 assert(0);
5416 }
5417 }
5418 }
5419
5420 static void
5421 handle_vs_input_decl(struct radv_shader_context *ctx,
5422 struct nir_variable *variable)
5423 {
5424 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5425 LLVMValueRef t_offset;
5426 LLVMValueRef t_list;
5427 LLVMValueRef input;
5428 LLVMValueRef buffer_index;
5429 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5430 int idx = variable->data.location;
5431 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5432 uint8_t input_usage_mask =
5433 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5434 unsigned num_channels = util_last_bit(input_usage_mask);
5435
5436 variable->data.driver_location = idx * 4;
5437
5438 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5439 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5440 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5441 ctx->abi.start_instance, "");
5442 if (ctx->options->key.vs.as_ls) {
5443 ctx->shader_info->vs.vgpr_comp_cnt =
5444 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5445 } else {
5446 ctx->shader_info->vs.vgpr_comp_cnt =
5447 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5448 }
5449 } else
5450 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5451 ctx->abi.base_vertex, "");
5452 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5453
5454 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5455
5456 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5457 buffer_index,
5458 ctx->ac.i32_0,
5459 num_channels, false, true);
5460
5461 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5462
5463 for (unsigned chan = 0; chan < 4; chan++) {
5464 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5465 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5466 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5467 input, llvm_chan, ""));
5468 }
5469 }
5470 }
5471
5472 static void interp_fs_input(struct radv_shader_context *ctx,
5473 unsigned attr,
5474 LLVMValueRef interp_param,
5475 LLVMValueRef prim_mask,
5476 LLVMValueRef result[4])
5477 {
5478 LLVMValueRef attr_number;
5479 unsigned chan;
5480 LLVMValueRef i, j;
5481 bool interp = interp_param != NULL;
5482
5483 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5484
5485 /* fs.constant returns the param from the middle vertex, so it's not
5486 * really useful for flat shading. It's meant to be used for custom
5487 * interpolation (but the intrinsic can't fetch from the other two
5488 * vertices).
5489 *
5490 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5491 * to do the right thing. The only reason we use fs.constant is that
5492 * fs.interp cannot be used on integers, because they can be equal
5493 * to NaN.
5494 */
5495 if (interp) {
5496 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5497 ctx->ac.v2f32, "");
5498
5499 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5500 ctx->ac.i32_0, "");
5501 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5502 ctx->ac.i32_1, "");
5503 }
5504
5505 for (chan = 0; chan < 4; chan++) {
5506 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5507
5508 if (interp) {
5509 result[chan] = ac_build_fs_interp(&ctx->ac,
5510 llvm_chan,
5511 attr_number,
5512 prim_mask, i, j);
5513 } else {
5514 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5515 LLVMConstInt(ctx->ac.i32, 2, false),
5516 llvm_chan,
5517 attr_number,
5518 prim_mask);
5519 }
5520 }
5521 }
5522
5523 static void
5524 handle_fs_input_decl(struct radv_shader_context *ctx,
5525 struct nir_variable *variable)
5526 {
5527 int idx = variable->data.location;
5528 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5529 LLVMValueRef interp;
5530
5531 variable->data.driver_location = idx * 4;
5532 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5533
5534 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5535 unsigned interp_type;
5536 if (variable->data.sample)
5537 interp_type = INTERP_SAMPLE;
5538 else if (variable->data.centroid)
5539 interp_type = INTERP_CENTROID;
5540 else
5541 interp_type = INTERP_CENTER;
5542
5543 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5544 } else
5545 interp = NULL;
5546
5547 for (unsigned i = 0; i < attrib_count; ++i)
5548 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5549
5550 }
5551
5552 static void
5553 handle_vs_inputs(struct radv_shader_context *ctx,
5554 struct nir_shader *nir) {
5555 nir_foreach_variable(variable, &nir->inputs)
5556 handle_vs_input_decl(ctx, variable);
5557 }
5558
5559 static void
5560 prepare_interp_optimize(struct radv_shader_context *ctx,
5561 struct nir_shader *nir)
5562 {
5563 if (!ctx->options->key.fs.multisample)
5564 return;
5565
5566 bool uses_center = false;
5567 bool uses_centroid = false;
5568 nir_foreach_variable(variable, &nir->inputs) {
5569 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5570 variable->data.sample)
5571 continue;
5572
5573 if (variable->data.centroid)
5574 uses_centroid = true;
5575 else
5576 uses_center = true;
5577 }
5578
5579 if (uses_center && uses_centroid) {
5580 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5581 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5582 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5583 }
5584 }
5585
5586 static void
5587 handle_fs_inputs(struct radv_shader_context *ctx,
5588 struct nir_shader *nir)
5589 {
5590 prepare_interp_optimize(ctx, nir);
5591
5592 nir_foreach_variable(variable, &nir->inputs)
5593 handle_fs_input_decl(ctx, variable);
5594
5595 unsigned index = 0;
5596
5597 if (ctx->shader_info->info.ps.uses_input_attachments ||
5598 ctx->shader_info->info.needs_multiview_view_index)
5599 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5600
5601 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5602 LLVMValueRef interp_param;
5603 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5604
5605 if (!(ctx->input_mask & (1ull << i)))
5606 continue;
5607
5608 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5609 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5610 interp_param = *inputs;
5611 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5612 inputs);
5613
5614 if (!interp_param)
5615 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5616 ++index;
5617 } else if (i == VARYING_SLOT_POS) {
5618 for(int i = 0; i < 3; ++i)
5619 inputs[i] = ctx->abi.frag_pos[i];
5620
5621 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5622 ctx->abi.frag_pos[3]);
5623 }
5624 }
5625 ctx->shader_info->fs.num_interp = index;
5626 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5627
5628 if (ctx->shader_info->info.needs_multiview_view_index)
5629 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5630 }
5631
5632 static LLVMValueRef
5633 ac_build_alloca(struct ac_llvm_context *ac,
5634 LLVMTypeRef type,
5635 const char *name)
5636 {
5637 LLVMBuilderRef builder = ac->builder;
5638 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5639 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5640 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5641 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5642 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5643 LLVMValueRef res;
5644
5645 if (first_instr) {
5646 LLVMPositionBuilderBefore(first_builder, first_instr);
5647 } else {
5648 LLVMPositionBuilderAtEnd(first_builder, first_block);
5649 }
5650
5651 res = LLVMBuildAlloca(first_builder, type, name);
5652 LLVMBuildStore(builder, LLVMConstNull(type), res);
5653
5654 LLVMDisposeBuilder(first_builder);
5655
5656 return res;
5657 }
5658
5659 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5660 LLVMTypeRef type,
5661 const char *name)
5662 {
5663 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5664 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5665 return ptr;
5666 }
5667
5668 static void
5669 scan_shader_output_decl(struct radv_shader_context *ctx,
5670 struct nir_variable *variable,
5671 struct nir_shader *shader,
5672 gl_shader_stage stage)
5673 {
5674 int idx = variable->data.location + variable->data.index;
5675 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5676 uint64_t mask_attribs;
5677
5678 variable->data.driver_location = idx * 4;
5679
5680 /* tess ctrl has it's own load/store paths for outputs */
5681 if (stage == MESA_SHADER_TESS_CTRL)
5682 return;
5683
5684 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5685 if (stage == MESA_SHADER_VERTEX ||
5686 stage == MESA_SHADER_TESS_EVAL ||
5687 stage == MESA_SHADER_GEOMETRY) {
5688 if (idx == VARYING_SLOT_CLIP_DIST0) {
5689 int length = shader->info.clip_distance_array_size +
5690 shader->info.cull_distance_array_size;
5691 if (stage == MESA_SHADER_VERTEX) {
5692 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5693 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5694 }
5695 if (stage == MESA_SHADER_TESS_EVAL) {
5696 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5697 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5698 }
5699
5700 if (length > 4)
5701 attrib_count = 2;
5702 else
5703 attrib_count = 1;
5704 mask_attribs = 1ull << idx;
5705 }
5706 }
5707
5708 ctx->output_mask |= mask_attribs;
5709 }
5710
5711 static void
5712 handle_shader_output_decl(struct ac_nir_context *ctx,
5713 struct nir_shader *nir,
5714 struct nir_variable *variable)
5715 {
5716 unsigned output_loc = variable->data.driver_location / 4;
5717 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5718
5719 /* tess ctrl has it's own load/store paths for outputs */
5720 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5721 return;
5722
5723 if (ctx->stage == MESA_SHADER_VERTEX ||
5724 ctx->stage == MESA_SHADER_TESS_EVAL ||
5725 ctx->stage == MESA_SHADER_GEOMETRY) {
5726 int idx = variable->data.location + variable->data.index;
5727 if (idx == VARYING_SLOT_CLIP_DIST0) {
5728 int length = nir->info.clip_distance_array_size +
5729 nir->info.cull_distance_array_size;
5730
5731 if (length > 4)
5732 attrib_count = 2;
5733 else
5734 attrib_count = 1;
5735 }
5736 }
5737
5738 for (unsigned i = 0; i < attrib_count; ++i) {
5739 for (unsigned chan = 0; chan < 4; chan++) {
5740 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5741 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5742 }
5743 }
5744 }
5745
5746 static LLVMTypeRef
5747 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5748 enum glsl_base_type type)
5749 {
5750 switch (type) {
5751 case GLSL_TYPE_INT:
5752 case GLSL_TYPE_UINT:
5753 case GLSL_TYPE_BOOL:
5754 case GLSL_TYPE_SUBROUTINE:
5755 return ac->i32;
5756 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5757 return ac->f32;
5758 case GLSL_TYPE_INT64:
5759 case GLSL_TYPE_UINT64:
5760 return ac->i64;
5761 case GLSL_TYPE_DOUBLE:
5762 return ac->f64;
5763 default:
5764 unreachable("unknown GLSL type");
5765 }
5766 }
5767
5768 static LLVMTypeRef
5769 glsl_to_llvm_type(struct ac_llvm_context *ac,
5770 const struct glsl_type *type)
5771 {
5772 if (glsl_type_is_scalar(type)) {
5773 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5774 }
5775
5776 if (glsl_type_is_vector(type)) {
5777 return LLVMVectorType(
5778 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5779 glsl_get_vector_elements(type));
5780 }
5781
5782 if (glsl_type_is_matrix(type)) {
5783 return LLVMArrayType(
5784 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5785 glsl_get_matrix_columns(type));
5786 }
5787
5788 if (glsl_type_is_array(type)) {
5789 return LLVMArrayType(
5790 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5791 glsl_get_length(type));
5792 }
5793
5794 assert(glsl_type_is_struct(type));
5795
5796 LLVMTypeRef member_types[glsl_get_length(type)];
5797
5798 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5799 member_types[i] =
5800 glsl_to_llvm_type(ac,
5801 glsl_get_struct_field(type, i));
5802 }
5803
5804 return LLVMStructTypeInContext(ac->context, member_types,
5805 glsl_get_length(type), false);
5806 }
5807
5808 static void
5809 setup_locals(struct ac_nir_context *ctx,
5810 struct nir_function *func)
5811 {
5812 int i, j;
5813 ctx->num_locals = 0;
5814 nir_foreach_variable(variable, &func->impl->locals) {
5815 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5816 variable->data.driver_location = ctx->num_locals * 4;
5817 variable->data.location_frac = 0;
5818 ctx->num_locals += attrib_count;
5819 }
5820 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5821 if (!ctx->locals)
5822 return;
5823
5824 for (i = 0; i < ctx->num_locals; i++) {
5825 for (j = 0; j < 4; j++) {
5826 ctx->locals[i * 4 + j] =
5827 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5828 }
5829 }
5830 }
5831
5832 static void
5833 setup_shared(struct ac_nir_context *ctx,
5834 struct nir_shader *nir)
5835 {
5836 nir_foreach_variable(variable, &nir->shared) {
5837 LLVMValueRef shared =
5838 LLVMAddGlobalInAddressSpace(
5839 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5840 variable->name ? variable->name : "",
5841 AC_LOCAL_ADDR_SPACE);
5842 _mesa_hash_table_insert(ctx->vars, variable, shared);
5843 }
5844 }
5845
5846 /* Initialize arguments for the shader export intrinsic */
5847 static void
5848 si_llvm_init_export_args(struct radv_shader_context *ctx,
5849 LLVMValueRef *values,
5850 unsigned enabled_channels,
5851 unsigned target,
5852 struct ac_export_args *args)
5853 {
5854 /* Specify the channels that are enabled. */
5855 args->enabled_channels = enabled_channels;
5856
5857 /* Specify whether the EXEC mask represents the valid mask */
5858 args->valid_mask = 0;
5859
5860 /* Specify whether this is the last export */
5861 args->done = 0;
5862
5863 /* Specify the target we are exporting */
5864 args->target = target;
5865
5866 args->compr = false;
5867 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5868 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5869 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5870 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5871
5872 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5873 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5874 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5875 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5876 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5877 unsigned chan;
5878
5879 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5880 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5881 unsigned bits, bool hi) = NULL;
5882
5883 switch(col_format) {
5884 case V_028714_SPI_SHADER_ZERO:
5885 args->enabled_channels = 0; /* writemask */
5886 args->target = V_008DFC_SQ_EXP_NULL;
5887 break;
5888
5889 case V_028714_SPI_SHADER_32_R:
5890 args->enabled_channels = 1;
5891 args->out[0] = values[0];
5892 break;
5893
5894 case V_028714_SPI_SHADER_32_GR:
5895 args->enabled_channels = 0x3;
5896 args->out[0] = values[0];
5897 args->out[1] = values[1];
5898 break;
5899
5900 case V_028714_SPI_SHADER_32_AR:
5901 args->enabled_channels = 0x9;
5902 args->out[0] = values[0];
5903 args->out[3] = values[3];
5904 break;
5905
5906 case V_028714_SPI_SHADER_FP16_ABGR:
5907 packf = ac_build_cvt_pkrtz_f16;
5908 break;
5909
5910 case V_028714_SPI_SHADER_UNORM16_ABGR:
5911 packf = ac_build_cvt_pknorm_u16;
5912 break;
5913
5914 case V_028714_SPI_SHADER_SNORM16_ABGR:
5915 packf = ac_build_cvt_pknorm_i16;
5916 break;
5917
5918 case V_028714_SPI_SHADER_UINT16_ABGR:
5919 packi = ac_build_cvt_pk_u16;
5920 break;
5921
5922 case V_028714_SPI_SHADER_SINT16_ABGR:
5923 packi = ac_build_cvt_pk_i16;
5924 break;
5925
5926 default:
5927 case V_028714_SPI_SHADER_32_ABGR:
5928 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5929 break;
5930 }
5931
5932 /* Pack f16 or norm_i16/u16. */
5933 if (packf) {
5934 for (chan = 0; chan < 2; chan++) {
5935 LLVMValueRef pack_args[2] = {
5936 values[2 * chan],
5937 values[2 * chan + 1]
5938 };
5939 LLVMValueRef packed;
5940
5941 packed = packf(&ctx->ac, pack_args);
5942 args->out[chan] = ac_to_float(&ctx->ac, packed);
5943 }
5944 args->compr = 1; /* COMPR flag */
5945 }
5946
5947 /* Pack i16/u16. */
5948 if (packi) {
5949 for (chan = 0; chan < 2; chan++) {
5950 LLVMValueRef pack_args[2] = {
5951 ac_to_integer(&ctx->ac, values[2 * chan]),
5952 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5953 };
5954 LLVMValueRef packed;
5955
5956 packed = packi(&ctx->ac, pack_args,
5957 is_int8 ? 8 : is_int10 ? 10 : 16,
5958 chan == 1);
5959 args->out[chan] = ac_to_float(&ctx->ac, packed);
5960 }
5961 args->compr = 1; /* COMPR flag */
5962 }
5963 return;
5964 }
5965
5966 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5967
5968 for (unsigned i = 0; i < 4; ++i) {
5969 if (!(args->enabled_channels & (1 << i)))
5970 continue;
5971
5972 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5973 }
5974 }
5975
5976 static void
5977 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5978 LLVMValueRef *values, unsigned enabled_channels)
5979 {
5980 struct ac_export_args args;
5981
5982 si_llvm_init_export_args(ctx, values, enabled_channels,
5983 V_008DFC_SQ_EXP_PARAM + index, &args);
5984 ac_build_export(&ctx->ac, &args);
5985 }
5986
5987 static LLVMValueRef
5988 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5989 {
5990 LLVMValueRef output =
5991 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5992
5993 return LLVMBuildLoad(ctx->ac.builder, output, "");
5994 }
5995
5996 static void
5997 handle_vs_outputs_post(struct radv_shader_context *ctx,
5998 bool export_prim_id,
5999 struct ac_vs_output_info *outinfo)
6000 {
6001 uint32_t param_count = 0;
6002 unsigned target;
6003 unsigned pos_idx, num_pos_exports = 0;
6004 struct ac_export_args args, pos_args[4] = {};
6005 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
6006 int i;
6007
6008 if (ctx->options->key.has_multiview_view_index) {
6009 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
6010 if(!*tmp_out) {
6011 for(unsigned i = 0; i < 4; ++i)
6012 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
6013 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
6014 }
6015
6016 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
6017 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
6018 }
6019
6020 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6021 sizeof(outinfo->vs_output_param_offset));
6022
6023 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
6024 LLVMValueRef slots[8];
6025 unsigned j;
6026
6027 if (outinfo->cull_dist_mask)
6028 outinfo->cull_dist_mask <<= ctx->num_output_clips;
6029
6030 i = VARYING_SLOT_CLIP_DIST0;
6031 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
6032 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6033
6034 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
6035 slots[i] = LLVMGetUndef(ctx->ac.f32);
6036
6037 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
6038 target = V_008DFC_SQ_EXP_POS + 3;
6039 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
6040 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6041 &args, sizeof(args));
6042 }
6043
6044 target = V_008DFC_SQ_EXP_POS + 2;
6045 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
6046 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6047 &args, sizeof(args));
6048
6049 }
6050
6051 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6052 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6053 for (unsigned j = 0; j < 4; j++)
6054 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6055 }
6056 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6057
6058 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6059 outinfo->writes_pointsize = true;
6060 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6061 }
6062
6063 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6064 outinfo->writes_layer = true;
6065 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6066 }
6067
6068 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6069 outinfo->writes_viewport_index = true;
6070 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6071 }
6072
6073 if (outinfo->writes_pointsize ||
6074 outinfo->writes_layer ||
6075 outinfo->writes_viewport_index) {
6076 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6077 (outinfo->writes_layer == true ? 4 : 0));
6078 pos_args[1].valid_mask = 0;
6079 pos_args[1].done = 0;
6080 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6081 pos_args[1].compr = 0;
6082 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6083 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6084 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6085 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6086
6087 if (outinfo->writes_pointsize == true)
6088 pos_args[1].out[0] = psize_value;
6089 if (outinfo->writes_layer == true)
6090 pos_args[1].out[2] = layer_value;
6091 if (outinfo->writes_viewport_index == true) {
6092 if (ctx->options->chip_class >= GFX9) {
6093 /* GFX9 has the layer in out.z[10:0] and the viewport
6094 * index in out.z[19:16].
6095 */
6096 LLVMValueRef v = viewport_index_value;
6097 v = ac_to_integer(&ctx->ac, v);
6098 v = LLVMBuildShl(ctx->ac.builder, v,
6099 LLVMConstInt(ctx->ac.i32, 16, false),
6100 "");
6101 v = LLVMBuildOr(ctx->ac.builder, v,
6102 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6103
6104 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6105 pos_args[1].enabled_channels |= 1 << 2;
6106 } else {
6107 pos_args[1].out[3] = viewport_index_value;
6108 pos_args[1].enabled_channels |= 1 << 3;
6109 }
6110 }
6111 }
6112 for (i = 0; i < 4; i++) {
6113 if (pos_args[i].out[0])
6114 num_pos_exports++;
6115 }
6116
6117 pos_idx = 0;
6118 for (i = 0; i < 4; i++) {
6119 if (!pos_args[i].out[0])
6120 continue;
6121
6122 /* Specify the target we are exporting */
6123 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6124 if (pos_idx == num_pos_exports)
6125 pos_args[i].done = 1;
6126 ac_build_export(&ctx->ac, &pos_args[i]);
6127 }
6128
6129 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6130 LLVMValueRef values[4];
6131 if (!(ctx->output_mask & (1ull << i)))
6132 continue;
6133
6134 if (i != VARYING_SLOT_LAYER &&
6135 i != VARYING_SLOT_PRIMITIVE_ID &&
6136 i < VARYING_SLOT_VAR0)
6137 continue;
6138
6139 for (unsigned j = 0; j < 4; j++)
6140 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6141
6142 unsigned output_usage_mask;
6143
6144 if (ctx->stage == MESA_SHADER_VERTEX &&
6145 !ctx->is_gs_copy_shader) {
6146 output_usage_mask =
6147 ctx->shader_info->info.vs.output_usage_mask[i];
6148 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
6149 output_usage_mask =
6150 ctx->shader_info->info.tes.output_usage_mask[i];
6151 } else {
6152 /* Enable all channels for the GS copy shader because
6153 * we don't know the output usage mask currently.
6154 */
6155 output_usage_mask = 0xf;
6156 }
6157
6158 radv_export_param(ctx, param_count, values, output_usage_mask);
6159
6160 outinfo->vs_output_param_offset[i] = param_count++;
6161 }
6162
6163 if (export_prim_id) {
6164 LLVMValueRef values[4];
6165
6166 values[0] = ctx->vs_prim_id;
6167 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6168 ctx->shader_info->vs.vgpr_comp_cnt);
6169 for (unsigned j = 1; j < 4; j++)
6170 values[j] = ctx->ac.f32_0;
6171
6172 radv_export_param(ctx, param_count, values, 0xf);
6173
6174 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6175 outinfo->export_prim_id = true;
6176 }
6177
6178 outinfo->pos_exports = num_pos_exports;
6179 outinfo->param_exports = param_count;
6180 }
6181
6182 static void
6183 handle_es_outputs_post(struct radv_shader_context *ctx,
6184 struct ac_es_output_info *outinfo)
6185 {
6186 int j;
6187 uint64_t max_output_written = 0;
6188 LLVMValueRef lds_base = NULL;
6189
6190 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6191 int param_index;
6192 int length = 4;
6193
6194 if (!(ctx->output_mask & (1ull << i)))
6195 continue;
6196
6197 if (i == VARYING_SLOT_CLIP_DIST0)
6198 length = ctx->num_output_clips + ctx->num_output_culls;
6199
6200 param_index = shader_io_get_unique_index(i);
6201
6202 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6203 }
6204
6205 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6206
6207 if (ctx->ac.chip_class >= GFX9) {
6208 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6209 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6210 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6211 LLVMConstInt(ctx->ac.i32, 24, false),
6212 LLVMConstInt(ctx->ac.i32, 4, false), false);
6213 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6214 LLVMBuildMul(ctx->ac.builder, wave_idx,
6215 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6216 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6217 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6218 }
6219
6220 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6221 LLVMValueRef dw_addr = NULL;
6222 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6223 int param_index;
6224 int length = 4;
6225
6226 if (!(ctx->output_mask & (1ull << i)))
6227 continue;
6228
6229 if (i == VARYING_SLOT_CLIP_DIST0)
6230 length = ctx->num_output_clips + ctx->num_output_culls;
6231
6232 param_index = shader_io_get_unique_index(i);
6233
6234 if (lds_base) {
6235 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6236 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6237 "");
6238 }
6239 for (j = 0; j < length; j++) {
6240 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6241 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6242
6243 if (ctx->ac.chip_class >= GFX9) {
6244 ac_lds_store(&ctx->ac, dw_addr,
6245 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6246 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6247 } else {
6248 ac_build_buffer_store_dword(&ctx->ac,
6249 ctx->esgs_ring,
6250 out_val, 1,
6251 NULL, ctx->es2gs_offset,
6252 (4 * param_index + j) * 4,
6253 1, 1, true, true);
6254 }
6255 }
6256 }
6257 }
6258
6259 static void
6260 handle_ls_outputs_post(struct radv_shader_context *ctx)
6261 {
6262 LLVMValueRef vertex_id = ctx->rel_auto_id;
6263 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6264 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6265 vertex_dw_stride, "");
6266
6267 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6268 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6269 int length = 4;
6270
6271 if (!(ctx->output_mask & (1ull << i)))
6272 continue;
6273
6274 if (i == VARYING_SLOT_CLIP_DIST0)
6275 length = ctx->num_output_clips + ctx->num_output_culls;
6276 int param = shader_io_get_unique_index(i);
6277 mark_tess_output(ctx, false, param);
6278 if (length > 4)
6279 mark_tess_output(ctx, false, param + 1);
6280 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6281 LLVMConstInt(ctx->ac.i32, param * 4, false),
6282 "");
6283 for (unsigned j = 0; j < length; j++) {
6284 ac_lds_store(&ctx->ac, dw_addr,
6285 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6286 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6287 }
6288 }
6289 }
6290
6291 struct ac_build_if_state
6292 {
6293 struct radv_shader_context *ctx;
6294 LLVMValueRef condition;
6295 LLVMBasicBlockRef entry_block;
6296 LLVMBasicBlockRef true_block;
6297 LLVMBasicBlockRef false_block;
6298 LLVMBasicBlockRef merge_block;
6299 };
6300
6301 static LLVMBasicBlockRef
6302 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6303 {
6304 LLVMBasicBlockRef current_block;
6305 LLVMBasicBlockRef next_block;
6306 LLVMBasicBlockRef new_block;
6307
6308 /* get current basic block */
6309 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6310
6311 /* chqeck if there's another block after this one */
6312 next_block = LLVMGetNextBasicBlock(current_block);
6313 if (next_block) {
6314 /* insert the new block before the next block */
6315 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6316 }
6317 else {
6318 /* append new block after current block */
6319 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6320 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6321 }
6322 return new_block;
6323 }
6324
6325 static void
6326 ac_nir_build_if(struct ac_build_if_state *ifthen,
6327 struct radv_shader_context *ctx,
6328 LLVMValueRef condition)
6329 {
6330 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6331
6332 memset(ifthen, 0, sizeof *ifthen);
6333 ifthen->ctx = ctx;
6334 ifthen->condition = condition;
6335 ifthen->entry_block = block;
6336
6337 /* create endif/merge basic block for the phi functions */
6338 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6339
6340 /* create/insert true_block before merge_block */
6341 ifthen->true_block =
6342 LLVMInsertBasicBlockInContext(ctx->context,
6343 ifthen->merge_block,
6344 "if-true-block");
6345
6346 /* successive code goes into the true block */
6347 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6348 }
6349
6350 /**
6351 * End a conditional.
6352 */
6353 static void
6354 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6355 {
6356 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6357
6358 /* Insert branch to the merge block from current block */
6359 LLVMBuildBr(builder, ifthen->merge_block);
6360
6361 /*
6362 * Now patch in the various branch instructions.
6363 */
6364
6365 /* Insert the conditional branch instruction at the end of entry_block */
6366 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6367 if (ifthen->false_block) {
6368 /* we have an else clause */
6369 LLVMBuildCondBr(builder, ifthen->condition,
6370 ifthen->true_block, ifthen->false_block);
6371 }
6372 else {
6373 /* no else clause */
6374 LLVMBuildCondBr(builder, ifthen->condition,
6375 ifthen->true_block, ifthen->merge_block);
6376 }
6377
6378 /* Resume building code at end of the ifthen->merge_block */
6379 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6380 }
6381
6382 static void
6383 write_tess_factors(struct radv_shader_context *ctx)
6384 {
6385 unsigned stride, outer_comps, inner_comps;
6386 struct ac_build_if_state if_ctx, inner_if_ctx;
6387 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6388 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6389 unsigned tess_inner_index = 0, tess_outer_index;
6390 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
6391 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6392 int i;
6393 emit_barrier(&ctx->ac, ctx->stage);
6394
6395 switch (ctx->options->key.tcs.primitive_mode) {
6396 case GL_ISOLINES:
6397 stride = 2;
6398 outer_comps = 2;
6399 inner_comps = 0;
6400 break;
6401 case GL_TRIANGLES:
6402 stride = 4;
6403 outer_comps = 3;
6404 inner_comps = 1;
6405 break;
6406 case GL_QUADS:
6407 stride = 6;
6408 outer_comps = 4;
6409 inner_comps = 2;
6410 break;
6411 default:
6412 return;
6413 }
6414
6415 ac_nir_build_if(&if_ctx, ctx,
6416 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6417 invocation_id, ctx->ac.i32_0, ""));
6418
6419 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6420
6421 if (inner_comps) {
6422 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6423 mark_tess_output(ctx, true, tess_inner_index);
6424 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6425 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6426 }
6427
6428 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6429 mark_tess_output(ctx, true, tess_outer_index);
6430 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6431 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6432
6433 for (i = 0; i < 4; i++) {
6434 inner[i] = LLVMGetUndef(ctx->ac.i32);
6435 outer[i] = LLVMGetUndef(ctx->ac.i32);
6436 }
6437
6438 // LINES reverseal
6439 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6440 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6441 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6442 ctx->ac.i32_1, "");
6443 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6444 } else {
6445 for (i = 0; i < outer_comps; i++) {
6446 outer[i] = out[i] =
6447 ac_lds_load(&ctx->ac, lds_outer);
6448 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6449 ctx->ac.i32_1, "");
6450 }
6451 for (i = 0; i < inner_comps; i++) {
6452 inner[i] = out[outer_comps+i] =
6453 ac_lds_load(&ctx->ac, lds_inner);
6454 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6455 ctx->ac.i32_1, "");
6456 }
6457 }
6458
6459 /* Convert the outputs to vectors for stores. */
6460 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6461 vec1 = NULL;
6462
6463 if (stride > 4)
6464 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6465
6466
6467 buffer = ctx->hs_ring_tess_factor;
6468 tf_base = ctx->tess_factor_offset;
6469 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6470 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6471 unsigned tf_offset = 0;
6472
6473 if (ctx->options->chip_class <= VI) {
6474 ac_nir_build_if(&inner_if_ctx, ctx,
6475 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6476 rel_patch_id, ctx->ac.i32_0, ""));
6477
6478 /* Store the dynamic HS control word. */
6479 ac_build_buffer_store_dword(&ctx->ac, buffer,
6480 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6481 1, ctx->ac.i32_0, tf_base,
6482 0, 1, 0, true, false);
6483 tf_offset += 4;
6484
6485 ac_nir_build_endif(&inner_if_ctx);
6486 }
6487
6488 /* Store the tessellation factors. */
6489 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6490 MIN2(stride, 4), byteoffset, tf_base,
6491 tf_offset, 1, 0, true, false);
6492 if (vec1)
6493 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6494 stride - 4, byteoffset, tf_base,
6495 16 + tf_offset, 1, 0, true, false);
6496
6497 //store to offchip for TES to read - only if TES reads them
6498 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6499 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6500 LLVMValueRef tf_inner_offset;
6501 unsigned param_outer, param_inner;
6502
6503 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6504 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6505 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6506
6507 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6508 util_next_power_of_two(outer_comps));
6509
6510 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6511 outer_comps, tf_outer_offset,
6512 ctx->oc_lds, 0, 1, 0, true, false);
6513 if (inner_comps) {
6514 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6515 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6516 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6517
6518 inner_vec = inner_comps == 1 ? inner[0] :
6519 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6520 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6521 inner_comps, tf_inner_offset,
6522 ctx->oc_lds, 0, 1, 0, true, false);
6523 }
6524 }
6525 ac_nir_build_endif(&if_ctx);
6526 }
6527
6528 static void
6529 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6530 {
6531 write_tess_factors(ctx);
6532 }
6533
6534 static bool
6535 si_export_mrt_color(struct radv_shader_context *ctx,
6536 LLVMValueRef *color, unsigned index, bool is_last,
6537 struct ac_export_args *args)
6538 {
6539 /* Export */
6540 si_llvm_init_export_args(ctx, color, 0xf,
6541 V_008DFC_SQ_EXP_MRT + index, args);
6542
6543 if (is_last) {
6544 args->valid_mask = 1; /* whether the EXEC mask is valid */
6545 args->done = 1; /* DONE bit */
6546 } else if (!args->enabled_channels)
6547 return false; /* unnecessary NULL export */
6548
6549 return true;
6550 }
6551
6552 static void
6553 radv_export_mrt_z(struct radv_shader_context *ctx,
6554 LLVMValueRef depth, LLVMValueRef stencil,
6555 LLVMValueRef samplemask)
6556 {
6557 struct ac_export_args args;
6558
6559 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6560
6561 ac_build_export(&ctx->ac, &args);
6562 }
6563
6564 static void
6565 handle_fs_outputs_post(struct radv_shader_context *ctx)
6566 {
6567 unsigned index = 0;
6568 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6569 struct ac_export_args color_args[8];
6570
6571 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6572 LLVMValueRef values[4];
6573 bool last = false;
6574
6575 if (!(ctx->output_mask & (1ull << i)))
6576 continue;
6577
6578 if (i < FRAG_RESULT_DATA0)
6579 continue;
6580
6581 for (unsigned j = 0; j < 4; j++)
6582 values[j] = ac_to_float(&ctx->ac,
6583 radv_load_output(ctx, i, j));
6584
6585 if (!ctx->shader_info->info.ps.writes_z &&
6586 !ctx->shader_info->info.ps.writes_stencil &&
6587 !ctx->shader_info->info.ps.writes_sample_mask)
6588 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6589
6590 bool ret = si_export_mrt_color(ctx, values,
6591 i - FRAG_RESULT_DATA0,
6592 last, &color_args[index]);
6593 if (ret)
6594 index++;
6595 }
6596
6597 /* Process depth, stencil, samplemask. */
6598 if (ctx->shader_info->info.ps.writes_z) {
6599 depth = ac_to_float(&ctx->ac,
6600 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6601 }
6602 if (ctx->shader_info->info.ps.writes_stencil) {
6603 stencil = ac_to_float(&ctx->ac,
6604 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6605 }
6606 if (ctx->shader_info->info.ps.writes_sample_mask) {
6607 samplemask = ac_to_float(&ctx->ac,
6608 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6609 }
6610
6611 /* Export PS outputs. */
6612 for (unsigned i = 0; i < index; i++)
6613 ac_build_export(&ctx->ac, &color_args[i]);
6614
6615 if (depth || stencil || samplemask)
6616 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6617 else if (!index)
6618 ac_build_export_null(&ctx->ac);
6619 }
6620
6621 static void
6622 emit_gs_epilogue(struct radv_shader_context *ctx)
6623 {
6624 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6625 }
6626
6627 static void
6628 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6629 LLVMValueRef *addrs)
6630 {
6631 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6632
6633 switch (ctx->stage) {
6634 case MESA_SHADER_VERTEX:
6635 if (ctx->options->key.vs.as_ls)
6636 handle_ls_outputs_post(ctx);
6637 else if (ctx->options->key.vs.as_es)
6638 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6639 else
6640 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6641 &ctx->shader_info->vs.outinfo);
6642 break;
6643 case MESA_SHADER_FRAGMENT:
6644 handle_fs_outputs_post(ctx);
6645 break;
6646 case MESA_SHADER_GEOMETRY:
6647 emit_gs_epilogue(ctx);
6648 break;
6649 case MESA_SHADER_TESS_CTRL:
6650 handle_tcs_outputs_post(ctx);
6651 break;
6652 case MESA_SHADER_TESS_EVAL:
6653 if (ctx->options->key.tes.as_es)
6654 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6655 else
6656 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6657 &ctx->shader_info->tes.outinfo);
6658 break;
6659 default:
6660 break;
6661 }
6662 }
6663
6664 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6665 {
6666 LLVMPassManagerRef passmgr;
6667 /* Create the pass manager */
6668 passmgr = LLVMCreateFunctionPassManagerForModule(
6669 ctx->ac.module);
6670
6671 /* This pass should eliminate all the load and store instructions */
6672 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6673
6674 /* Add some optimization passes */
6675 LLVMAddScalarReplAggregatesPass(passmgr);
6676 LLVMAddLICMPass(passmgr);
6677 LLVMAddAggressiveDCEPass(passmgr);
6678 LLVMAddCFGSimplificationPass(passmgr);
6679 LLVMAddInstructionCombiningPass(passmgr);
6680
6681 /* Run the pass */
6682 LLVMInitializeFunctionPassManager(passmgr);
6683 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6684 LLVMFinalizeFunctionPassManager(passmgr);
6685
6686 LLVMDisposeBuilder(ctx->ac.builder);
6687 LLVMDisposePassManager(passmgr);
6688
6689 ac_llvm_context_dispose(&ctx->ac);
6690 }
6691
6692 static void
6693 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6694 {
6695 struct ac_vs_output_info *outinfo;
6696
6697 switch (ctx->stage) {
6698 case MESA_SHADER_FRAGMENT:
6699 case MESA_SHADER_COMPUTE:
6700 case MESA_SHADER_TESS_CTRL:
6701 case MESA_SHADER_GEOMETRY:
6702 return;
6703 case MESA_SHADER_VERTEX:
6704 if (ctx->options->key.vs.as_ls ||
6705 ctx->options->key.vs.as_es)
6706 return;
6707 outinfo = &ctx->shader_info->vs.outinfo;
6708 break;
6709 case MESA_SHADER_TESS_EVAL:
6710 if (ctx->options->key.vs.as_es)
6711 return;
6712 outinfo = &ctx->shader_info->tes.outinfo;
6713 break;
6714 default:
6715 unreachable("Unhandled shader type");
6716 }
6717
6718 ac_optimize_vs_outputs(&ctx->ac,
6719 ctx->main_function,
6720 outinfo->vs_output_param_offset,
6721 VARYING_SLOT_MAX,
6722 &outinfo->param_exports);
6723 }
6724
6725 static void
6726 ac_setup_rings(struct radv_shader_context *ctx)
6727 {
6728 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6729 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6730 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6731 }
6732
6733 if (ctx->is_gs_copy_shader) {
6734 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6735 }
6736 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6737 LLVMValueRef tmp;
6738 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6739 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6740
6741 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6742
6743 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6744 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6745 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6746 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6747 }
6748
6749 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6750 ctx->stage == MESA_SHADER_TESS_EVAL) {
6751 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6752 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6753 }
6754 }
6755
6756 static unsigned
6757 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6758 const struct nir_shader *nir)
6759 {
6760 switch (nir->info.stage) {
6761 case MESA_SHADER_TESS_CTRL:
6762 return chip_class >= CIK ? 128 : 64;
6763 case MESA_SHADER_GEOMETRY:
6764 return chip_class >= GFX9 ? 128 : 64;
6765 case MESA_SHADER_COMPUTE:
6766 break;
6767 default:
6768 return 0;
6769 }
6770
6771 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6772 nir->info.cs.local_size[1] *
6773 nir->info.cs.local_size[2];
6774 return max_workgroup_size;
6775 }
6776
6777 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6778 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6779 {
6780 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6781 LLVMConstInt(ctx->ac.i32, 8, false),
6782 LLVMConstInt(ctx->ac.i32, 8, false), false);
6783 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6784 ctx->ac.i32_0, "");
6785 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6786 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6787 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6788 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6789 }
6790
6791 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6792 {
6793 for(int i = 5; i >= 0; --i) {
6794 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6795 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6796 LLVMConstInt(ctx->ac.i32, 16, false), false);
6797 }
6798
6799 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6800 LLVMConstInt(ctx->ac.i32, 16, false),
6801 LLVMConstInt(ctx->ac.i32, 8, false), false);
6802 }
6803
6804 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6805 struct nir_shader *nir)
6806 {
6807 struct ac_nir_context ctx = {};
6808 struct nir_function *func;
6809
6810 /* Last minute passes for both radv & radeonsi */
6811 ac_lower_subgroups(nir);
6812
6813 ctx.ac = *ac;
6814 ctx.abi = abi;
6815
6816 ctx.stage = nir->info.stage;
6817
6818 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6819
6820 nir_foreach_variable(variable, &nir->outputs)
6821 handle_shader_output_decl(&ctx, nir, variable);
6822
6823 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6824 _mesa_key_pointer_equal);
6825 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6826 _mesa_key_pointer_equal);
6827 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6828 _mesa_key_pointer_equal);
6829
6830 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6831
6832 setup_locals(&ctx, func);
6833
6834 if (nir->info.stage == MESA_SHADER_COMPUTE)
6835 setup_shared(&ctx, nir);
6836
6837 visit_cf_list(&ctx, &func->impl->body);
6838 phi_post_pass(&ctx);
6839
6840 if (nir->info.stage != MESA_SHADER_COMPUTE)
6841 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6842 ctx.abi->outputs);
6843
6844 free(ctx.locals);
6845 ralloc_free(ctx.defs);
6846 ralloc_free(ctx.phis);
6847 ralloc_free(ctx.vars);
6848 }
6849
6850 static
6851 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6852 struct nir_shader *const *shaders,
6853 int shader_count,
6854 struct ac_shader_variant_info *shader_info,
6855 const struct ac_nir_compiler_options *options,
6856 bool dump_shader)
6857 {
6858 struct radv_shader_context ctx = {0};
6859 unsigned i;
6860 ctx.options = options;
6861 ctx.shader_info = shader_info;
6862 ctx.context = LLVMContextCreate();
6863
6864 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6865 options->family);
6866 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6867 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6868
6869 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6870 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6871 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6872 LLVMDisposeTargetData(data_layout);
6873 LLVMDisposeMessage(data_layout_str);
6874
6875 enum ac_float_mode float_mode =
6876 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6877 AC_FLOAT_MODE_DEFAULT;
6878
6879 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6880
6881 memset(shader_info, 0, sizeof(*shader_info));
6882
6883 for(int i = 0; i < shader_count; ++i)
6884 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6885
6886 for (i = 0; i < AC_UD_MAX_SETS; i++)
6887 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6888 for (i = 0; i < AC_UD_MAX_UD; i++)
6889 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6890
6891 ctx.max_workgroup_size = 0;
6892 for (int i = 0; i < shader_count; ++i) {
6893 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6894 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6895 shaders[i]));
6896 }
6897
6898 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6899 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6900
6901 ctx.abi.inputs = &ctx.inputs[0];
6902 ctx.abi.emit_outputs = handle_shader_outputs_post;
6903 ctx.abi.emit_vertex = visit_emit_vertex;
6904 ctx.abi.load_ubo = radv_load_ubo;
6905 ctx.abi.load_ssbo = radv_load_ssbo;
6906 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6907 ctx.abi.load_resource = radv_load_resource;
6908 ctx.abi.clamp_shadow_reference = false;
6909
6910 if (shader_count >= 2)
6911 ac_init_exec_full_mask(&ctx.ac);
6912
6913 if (ctx.ac.chip_class == GFX9 &&
6914 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6915 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6916
6917 for(int i = 0; i < shader_count; ++i) {
6918 ctx.stage = shaders[i]->info.stage;
6919 ctx.output_mask = 0;
6920 ctx.tess_outputs_written = 0;
6921 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6922 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6923
6924 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6925 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6926 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6927 ctx.abi.load_inputs = load_gs_input;
6928 ctx.abi.emit_primitive = visit_end_primitive;
6929 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6930 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6931 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6932 ctx.abi.load_tess_varyings = load_tcs_varyings;
6933 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6934 ctx.abi.store_tcs_outputs = store_tcs_output;
6935 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6936 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6937 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6938 ctx.abi.load_tess_varyings = load_tes_input;
6939 ctx.abi.load_tess_coord = load_tess_coord;
6940 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6941 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6942 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6943 if (shader_info->info.vs.needs_instance_id) {
6944 if (ctx.options->key.vs.as_ls) {
6945 ctx.shader_info->vs.vgpr_comp_cnt =
6946 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6947 } else {
6948 ctx.shader_info->vs.vgpr_comp_cnt =
6949 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6950 }
6951 }
6952 ctx.abi.load_base_vertex = radv_load_base_vertex;
6953 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6954 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6955 ctx.abi.lookup_interp_param = lookup_interp_param;
6956 ctx.abi.load_sample_position = load_sample_position;
6957 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6958 }
6959
6960 if (i)
6961 emit_barrier(&ctx.ac, ctx.stage);
6962
6963 ac_setup_rings(&ctx);
6964
6965 LLVMBasicBlockRef merge_block;
6966 if (shader_count >= 2) {
6967 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6968 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6969 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6970
6971 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6972 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6973 LLVMConstInt(ctx.ac.i32, 8, false), false);
6974 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6975 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6976 thread_id, count, "");
6977 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6978
6979 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6980 }
6981
6982 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6983 handle_fs_inputs(&ctx, shaders[i]);
6984 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6985 handle_vs_inputs(&ctx, shaders[i]);
6986 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6987 prepare_gs_input_vgprs(&ctx);
6988
6989 nir_foreach_variable(variable, &shaders[i]->outputs)
6990 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6991
6992 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6993
6994 if (shader_count >= 2) {
6995 LLVMBuildBr(ctx.ac.builder, merge_block);
6996 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6997 }
6998
6999 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
7000 unsigned addclip = shaders[i]->info.clip_distance_array_size +
7001 shaders[i]->info.cull_distance_array_size > 4;
7002 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
7003 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
7004 shaders[i]->info.gs.vertices_out;
7005 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
7006 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
7007 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
7008 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
7009 shader_info->vs.outputs_written = ctx.tess_outputs_written;
7010 }
7011 }
7012
7013 LLVMBuildRetVoid(ctx.ac.builder);
7014
7015 if (options->dump_preoptir)
7016 ac_dump_module(ctx.ac.module);
7017
7018 ac_llvm_finalize_module(&ctx);
7019
7020 if (shader_count == 1)
7021 ac_nir_eliminate_const_vs_outputs(&ctx);
7022
7023 if (dump_shader) {
7024 ctx.shader_info->private_mem_vgprs =
7025 ac_count_scratch_private_memory(ctx.main_function);
7026 }
7027
7028 return ctx.ac.module;
7029 }
7030
7031 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
7032 {
7033 unsigned *retval = (unsigned *)context;
7034 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
7035 char *description = LLVMGetDiagInfoDescription(di);
7036
7037 if (severity == LLVMDSError) {
7038 *retval = 1;
7039 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
7040 description);
7041 }
7042
7043 LLVMDisposeMessage(description);
7044 }
7045
7046 static unsigned ac_llvm_compile(LLVMModuleRef M,
7047 struct ac_shader_binary *binary,
7048 LLVMTargetMachineRef tm)
7049 {
7050 unsigned retval = 0;
7051 char *err;
7052 LLVMContextRef llvm_ctx;
7053 LLVMMemoryBufferRef out_buffer;
7054 unsigned buffer_size;
7055 const char *buffer_data;
7056 LLVMBool mem_err;
7057
7058 /* Setup Diagnostic Handler*/
7059 llvm_ctx = LLVMGetModuleContext(M);
7060
7061 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
7062 &retval);
7063
7064 /* Compile IR*/
7065 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
7066 &err, &out_buffer);
7067
7068 /* Process Errors/Warnings */
7069 if (mem_err) {
7070 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7071 free(err);
7072 retval = 1;
7073 goto out;
7074 }
7075
7076 /* Extract Shader Code*/
7077 buffer_size = LLVMGetBufferSize(out_buffer);
7078 buffer_data = LLVMGetBufferStart(out_buffer);
7079
7080 ac_elf_read(buffer_data, buffer_size, binary);
7081
7082 /* Clean up */
7083 LLVMDisposeMemoryBuffer(out_buffer);
7084
7085 out:
7086 return retval;
7087 }
7088
7089 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7090 LLVMModuleRef llvm_module,
7091 struct ac_shader_binary *binary,
7092 struct ac_shader_config *config,
7093 struct ac_shader_variant_info *shader_info,
7094 gl_shader_stage stage,
7095 bool dump_shader, bool supports_spill)
7096 {
7097 if (dump_shader)
7098 ac_dump_module(llvm_module);
7099
7100 memset(binary, 0, sizeof(*binary));
7101 int v = ac_llvm_compile(llvm_module, binary, tm);
7102 if (v) {
7103 fprintf(stderr, "compile failed\n");
7104 }
7105
7106 if (dump_shader)
7107 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7108
7109 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7110
7111 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7112 LLVMDisposeModule(llvm_module);
7113 LLVMContextDispose(ctx);
7114
7115 if (stage == MESA_SHADER_FRAGMENT) {
7116 shader_info->num_input_vgprs = 0;
7117 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7118 shader_info->num_input_vgprs += 2;
7119 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7120 shader_info->num_input_vgprs += 2;
7121 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7122 shader_info->num_input_vgprs += 2;
7123 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7124 shader_info->num_input_vgprs += 3;
7125 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7126 shader_info->num_input_vgprs += 2;
7127 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7128 shader_info->num_input_vgprs += 2;
7129 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7130 shader_info->num_input_vgprs += 2;
7131 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7132 shader_info->num_input_vgprs += 1;
7133 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7134 shader_info->num_input_vgprs += 1;
7135 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7136 shader_info->num_input_vgprs += 1;
7137 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7138 shader_info->num_input_vgprs += 1;
7139 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7140 shader_info->num_input_vgprs += 1;
7141 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7142 shader_info->num_input_vgprs += 1;
7143 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7144 shader_info->num_input_vgprs += 1;
7145 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7146 shader_info->num_input_vgprs += 1;
7147 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7148 shader_info->num_input_vgprs += 1;
7149 }
7150 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7151
7152 /* +3 for scratch wave offset and VCC */
7153 config->num_sgprs = MAX2(config->num_sgprs,
7154 shader_info->num_input_sgprs + 3);
7155
7156 /* Enable 64-bit and 16-bit denormals, because there is no performance
7157 * cost.
7158 *
7159 * If denormals are enabled, all floating-point output modifiers are
7160 * ignored.
7161 *
7162 * Don't enable denormals for 32-bit floats, because:
7163 * - Floating-point output modifiers would be ignored by the hw.
7164 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7165 * have to stop using those.
7166 * - SI & CI would be very slow.
7167 */
7168 config->float_mode |= V_00B028_FP_64_DENORMS;
7169 }
7170
7171 static void
7172 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7173 {
7174 switch (nir->info.stage) {
7175 case MESA_SHADER_COMPUTE:
7176 for (int i = 0; i < 3; ++i)
7177 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7178 break;
7179 case MESA_SHADER_FRAGMENT:
7180 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7181 break;
7182 case MESA_SHADER_GEOMETRY:
7183 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7184 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7185 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7186 shader_info->gs.invocations = nir->info.gs.invocations;
7187 break;
7188 case MESA_SHADER_TESS_EVAL:
7189 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7190 shader_info->tes.spacing = nir->info.tess.spacing;
7191 shader_info->tes.ccw = nir->info.tess.ccw;
7192 shader_info->tes.point_mode = nir->info.tess.point_mode;
7193 shader_info->tes.as_es = options->key.tes.as_es;
7194 break;
7195 case MESA_SHADER_TESS_CTRL:
7196 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7197 break;
7198 case MESA_SHADER_VERTEX:
7199 shader_info->vs.as_es = options->key.vs.as_es;
7200 shader_info->vs.as_ls = options->key.vs.as_ls;
7201 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7202 if (options->key.vs.as_ls)
7203 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7204 break;
7205 default:
7206 break;
7207 }
7208 }
7209
7210 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7211 struct ac_shader_binary *binary,
7212 struct ac_shader_config *config,
7213 struct ac_shader_variant_info *shader_info,
7214 struct nir_shader *const *nir,
7215 int nir_count,
7216 const struct ac_nir_compiler_options *options,
7217 bool dump_shader)
7218 {
7219
7220 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7221 options, dump_shader);
7222
7223 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7224 for (int i = 0; i < nir_count; ++i)
7225 ac_fill_shader_info(shader_info, nir[i], options);
7226
7227 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7228 if (options->chip_class == GFX9) {
7229 if (nir_count == 2 &&
7230 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7231 shader_info->gs.es_type = nir[0]->info.stage;
7232 }
7233 }
7234 }
7235
7236 static void
7237 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7238 {
7239 LLVMValueRef vtx_offset =
7240 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7241 LLVMConstInt(ctx->ac.i32, 4, false), "");
7242 int idx = 0;
7243
7244 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7245 int length = 4;
7246 int slot = idx;
7247 int slot_inc = 1;
7248 if (!(ctx->output_mask & (1ull << i)))
7249 continue;
7250
7251 if (i == VARYING_SLOT_CLIP_DIST0) {
7252 /* unpack clip and cull from a single set of slots */
7253 length = ctx->num_output_clips + ctx->num_output_culls;
7254 if (length > 4)
7255 slot_inc = 2;
7256 }
7257
7258 for (unsigned j = 0; j < length; j++) {
7259 LLVMValueRef value, soffset;
7260
7261 soffset = LLVMConstInt(ctx->ac.i32,
7262 (slot * 4 + j) *
7263 ctx->gs_max_out_vertices * 16 * 4, false);
7264
7265 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7266 1, ctx->ac.i32_0,
7267 vtx_offset, soffset,
7268 0, 1, 1, true, false);
7269
7270 LLVMBuildStore(ctx->ac.builder,
7271 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7272 }
7273 idx += slot_inc;
7274 }
7275 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7276 }
7277
7278 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7279 struct nir_shader *geom_shader,
7280 struct ac_shader_binary *binary,
7281 struct ac_shader_config *config,
7282 struct ac_shader_variant_info *shader_info,
7283 const struct ac_nir_compiler_options *options,
7284 bool dump_shader)
7285 {
7286 struct radv_shader_context ctx = {0};
7287 ctx.context = LLVMContextCreate();
7288 ctx.options = options;
7289 ctx.shader_info = shader_info;
7290
7291 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7292 options->family);
7293 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7294
7295 ctx.is_gs_copy_shader = true;
7296 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7297
7298 enum ac_float_mode float_mode =
7299 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7300 AC_FLOAT_MODE_DEFAULT;
7301
7302 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7303 ctx.stage = MESA_SHADER_VERTEX;
7304
7305 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7306
7307 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7308 ac_setup_rings(&ctx);
7309
7310 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7311 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7312
7313 struct ac_nir_context nir_ctx = {};
7314 nir_ctx.ac = ctx.ac;
7315 nir_ctx.abi = &ctx.abi;
7316
7317 nir_foreach_variable(variable, &geom_shader->outputs) {
7318 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7319 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7320 }
7321
7322 ac_gs_copy_shader_emit(&ctx);
7323
7324 LLVMBuildRetVoid(ctx.ac.builder);
7325
7326 ac_llvm_finalize_module(&ctx);
7327
7328 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7329 MESA_SHADER_VERTEX,
7330 dump_shader, options->supports_spill);
7331 }
7332
7333 void
7334 ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class chip_class)
7335 {
7336 /* While it would be nice not to have this flag, we are constrained
7337 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
7338 * on GFX9.
7339 */
7340 bool llvm_has_working_vgpr_indexing = chip_class <= VI;
7341
7342 /* TODO: Indirect indexing of GS inputs is unimplemented.
7343 *
7344 * TCS and TES load inputs directly from LDS or offchip memory, so
7345 * indirect indexing is trivial.
7346 */
7347 nir_variable_mode indirect_mask = 0;
7348 if (nir->info.stage == MESA_SHADER_GEOMETRY ||
7349 (nir->info.stage != MESA_SHADER_TESS_CTRL &&
7350 nir->info.stage != MESA_SHADER_TESS_EVAL &&
7351 !llvm_has_working_vgpr_indexing)) {
7352 indirect_mask |= nir_var_shader_in;
7353 }
7354 if (!llvm_has_working_vgpr_indexing &&
7355 nir->info.stage != MESA_SHADER_TESS_CTRL)
7356 indirect_mask |= nir_var_shader_out;
7357
7358 /* TODO: We shouldn't need to do this, however LLVM isn't currently
7359 * smart enough to handle indirects without causing excess spilling
7360 * causing the gpu to hang.
7361 *
7362 * See the following thread for more details of the problem:
7363 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
7364 */
7365 indirect_mask |= nir_var_local;
7366
7367 nir_lower_indirect_derefs(nir, indirect_mask);
7368 }