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amd/common: rename add_user_sgpr_array_argument() to add_array_arg()
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tcs_patch_id;
115 LLVMValueRef tcs_rel_ids;
116 LLVMValueRef tes_rel_patch_id;
117 LLVMValueRef tes_patch_id;
118 LLVMValueRef tes_u;
119 LLVMValueRef tes_v;
120
121 LLVMValueRef gsvs_ring_stride;
122 LLVMValueRef gsvs_num_entries;
123 LLVMValueRef gs2vs_offset;
124 LLVMValueRef gs_wave_id;
125 LLVMValueRef gs_vtx_offset[6];
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153
154 uint32_t tcs_patch_outputs_read;
155 uint64_t tcs_outputs_read;
156 };
157
158 static inline struct nir_to_llvm_context *
159 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
160 {
161 struct nir_to_llvm_context *ctx = NULL;
162 return container_of(abi, ctx, abi);
163 }
164
165 static LLVMTypeRef
166 nir2llvmtype(struct ac_nir_context *ctx,
167 const struct glsl_type *type)
168 {
169 switch (glsl_get_base_type(glsl_without_array(type))) {
170 case GLSL_TYPE_UINT:
171 case GLSL_TYPE_INT:
172 return ctx->ac.i32;
173 case GLSL_TYPE_UINT64:
174 case GLSL_TYPE_INT64:
175 return ctx->ac.i64;
176 case GLSL_TYPE_DOUBLE:
177 return ctx->ac.f64;
178 case GLSL_TYPE_FLOAT:
179 return ctx->ac.f32;
180 default:
181 assert(!"Unsupported type in nir2llvmtype()");
182 break;
183 }
184 return 0;
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 const nir_tex_instr *instr,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t sgpr_count;
256 uint8_t num_sgprs_used;
257 uint8_t num_vgprs_used;
258 };
259
260 enum ac_arg_regfile {
261 ARG_SGPR,
262 ARG_VGPR,
263 };
264
265 static void
266 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
267 LLVMValueRef *param_ptr)
268 {
269 assert(info->count < MAX_ARGS);
270
271 info->assign[info->count] = param_ptr;
272 info->types[info->count] = type;
273 info->count++;
274
275 if (regfile == ARG_SGPR) {
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 } else {
279 assert(regfile == ARG_VGPR);
280 info->num_vgprs_used += ac_get_type_size(type) / 4;
281 }
282 }
283
284 static inline void
285 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
286 {
287 info->array_params_mask |= (1 << info->count);
288 add_arg(info, ARG_SGPR, type, param_ptr);
289 }
290
291 static void assign_arguments(LLVMValueRef main_function,
292 struct arg_info *info)
293 {
294 unsigned i;
295 for (i = 0; i < info->count; i++) {
296 if (info->assign[i])
297 *info->assign[i] = LLVMGetParam(main_function, i);
298 }
299 }
300
301 static LLVMValueRef
302 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
303 LLVMBuilderRef builder, LLVMTypeRef *return_types,
304 unsigned num_return_elems,
305 struct arg_info *args,
306 unsigned max_workgroup_size,
307 bool unsafe_math)
308 {
309 LLVMTypeRef main_function_type, ret_type;
310 LLVMBasicBlockRef main_function_body;
311
312 if (num_return_elems)
313 ret_type = LLVMStructTypeInContext(ctx, return_types,
314 num_return_elems, true);
315 else
316 ret_type = LLVMVoidTypeInContext(ctx);
317
318 /* Setup the function */
319 main_function_type =
320 LLVMFunctionType(ret_type, args->types, args->count, 0);
321 LLVMValueRef main_function =
322 LLVMAddFunction(module, "main", main_function_type);
323 main_function_body =
324 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
325 LLVMPositionBuilderAtEnd(builder, main_function_body);
326
327 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
328 for (unsigned i = 0; i < args->sgpr_count; ++i) {
329 if (args->array_params_mask & (1 << i)) {
330 LLVMValueRef P = LLVMGetParam(main_function, i);
331 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
332 ac_add_attr_dereferenceable(P, UINT64_MAX);
333 }
334 else {
335 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
336 }
337 }
338
339 if (max_workgroup_size) {
340 ac_llvm_add_target_dep_function_attr(main_function,
341 "amdgpu-max-work-group-size",
342 max_workgroup_size);
343 }
344 if (unsafe_math) {
345 /* These were copied from some LLVM test. */
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "less-precise-fpmad",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-infs-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "no-nans-fp-math",
354 "true");
355 LLVMAddTargetDependentFunctionAttr(main_function,
356 "unsafe-fp-math",
357 "true");
358 }
359 return main_function;
360 }
361
362 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
363 {
364 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
365 CONST_ADDR_SPACE);
366 }
367
368 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
369 {
370 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
371 type = LLVMGetElementType(type);
372
373 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
374 return LLVMGetIntTypeWidth(type);
375
376 if (type == ctx->f16)
377 return 16;
378 if (type == ctx->f32)
379 return 32;
380 if (type == ctx->f64)
381 return 64;
382
383 unreachable("Unhandled type kind in get_elem_bits");
384 }
385
386 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
387 LLVMValueRef param, unsigned rshift,
388 unsigned bitwidth)
389 {
390 LLVMValueRef value = param;
391 if (rshift)
392 value = LLVMBuildLShr(ctx->builder, value,
393 LLVMConstInt(ctx->i32, rshift, false), "");
394
395 if (rshift + bitwidth < 32) {
396 unsigned mask = (1 << bitwidth) - 1;
397 value = LLVMBuildAnd(ctx->builder, value,
398 LLVMConstInt(ctx->i32, mask, false), "");
399 }
400 return value;
401 }
402
403 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
404 {
405 switch (ctx->stage) {
406 case MESA_SHADER_TESS_CTRL:
407 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
408 case MESA_SHADER_TESS_EVAL:
409 return ctx->tes_rel_patch_id;
410 break;
411 default:
412 unreachable("Illegal stage");
413 }
414 }
415
416 /* Tessellation shaders pass outputs to the next shader using LDS.
417 *
418 * LS outputs = TCS inputs
419 * TCS outputs = TES inputs
420 *
421 * The LDS layout is:
422 * - TCS inputs for patch 0
423 * - TCS inputs for patch 1
424 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
425 * - ...
426 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
427 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
428 * - TCS outputs for patch 1
429 * - Per-patch TCS outputs for patch 1
430 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
431 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
432 * - ...
433 *
434 * All three shaders VS(LS), TCS, TES share the same LDS space.
435 */
436 static LLVMValueRef
437 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
438 {
439 if (ctx->stage == MESA_SHADER_VERTEX)
440 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
441 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
442 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
443 else {
444 assert(0);
445 return NULL;
446 }
447 }
448
449 static LLVMValueRef
450 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
451 {
452 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
453 }
454
455 static LLVMValueRef
456 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
457 {
458 return LLVMBuildMul(ctx->builder,
459 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
460 LLVMConstInt(ctx->ac.i32, 4, false), "");
461 }
462
463 static LLVMValueRef
464 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
465 {
466 return LLVMBuildMul(ctx->builder,
467 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
468 LLVMConstInt(ctx->ac.i32, 4, false), "");
469 }
470
471 static LLVMValueRef
472 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
473 {
474 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
475 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
476
477 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
482 {
483 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
484 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
485 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
486
487 return LLVMBuildAdd(ctx->builder, patch0_offset,
488 LLVMBuildMul(ctx->builder, patch_stride,
489 rel_patch_id, ""),
490 "");
491 }
492
493 static LLVMValueRef
494 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
495 {
496 LLVMValueRef patch0_patch_data_offset =
497 get_tcs_out_patch0_patch_data_offset(ctx);
498 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
499 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
500
501 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
502 LLVMBuildMul(ctx->builder, patch_stride,
503 rel_patch_id, ""),
504 "");
505 }
506
507 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
508 {
509 ud_info->sgpr_idx = *sgpr_idx;
510 ud_info->num_sgprs = num_sgprs;
511 ud_info->indirect = false;
512 ud_info->indirect_offset = 0;
513 *sgpr_idx += num_sgprs;
514 }
515
516 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
517 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
518 {
519 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
520 }
521
522
523 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
524 uint32_t indirect_offset)
525 {
526 ud_info->sgpr_idx = sgpr_idx;
527 ud_info->num_sgprs = num_sgprs;
528 ud_info->indirect = true;
529 ud_info->indirect_offset = indirect_offset;
530 }
531
532 struct user_sgpr_info {
533 bool need_ring_offsets;
534 uint8_t sgpr_count;
535 bool indirect_all_descriptor_sets;
536 };
537
538 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
539 struct user_sgpr_info *user_sgpr_info)
540 {
541 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
542
543 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
544 if (ctx->stage == MESA_SHADER_GEOMETRY ||
545 ctx->stage == MESA_SHADER_VERTEX ||
546 ctx->stage == MESA_SHADER_TESS_CTRL ||
547 ctx->stage == MESA_SHADER_TESS_EVAL ||
548 ctx->is_gs_copy_shader)
549 user_sgpr_info->need_ring_offsets = true;
550
551 if (ctx->stage == MESA_SHADER_FRAGMENT &&
552 ctx->shader_info->info.ps.needs_sample_positions)
553 user_sgpr_info->need_ring_offsets = true;
554
555 /* 2 user sgprs will nearly always be allocated for scratch/rings */
556 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
557 user_sgpr_info->sgpr_count += 2;
558 }
559
560 switch (ctx->stage) {
561 case MESA_SHADER_COMPUTE:
562 if (ctx->shader_info->info.cs.uses_grid_size)
563 user_sgpr_info->sgpr_count += 3;
564 break;
565 case MESA_SHADER_FRAGMENT:
566 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
567 break;
568 case MESA_SHADER_VERTEX:
569 if (!ctx->is_gs_copy_shader) {
570 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
571 if (ctx->shader_info->info.vs.needs_draw_id) {
572 user_sgpr_info->sgpr_count += 3;
573 } else {
574 user_sgpr_info->sgpr_count += 2;
575 }
576 }
577 if (ctx->options->key.vs.as_ls)
578 user_sgpr_info->sgpr_count++;
579 break;
580 case MESA_SHADER_TESS_CTRL:
581 user_sgpr_info->sgpr_count += 4;
582 break;
583 case MESA_SHADER_TESS_EVAL:
584 user_sgpr_info->sgpr_count += 1;
585 break;
586 case MESA_SHADER_GEOMETRY:
587 user_sgpr_info->sgpr_count += 2;
588 break;
589 default:
590 break;
591 }
592
593 if (ctx->shader_info->info.needs_push_constants)
594 user_sgpr_info->sgpr_count += 2;
595
596 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
597 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
598 user_sgpr_info->sgpr_count += 2;
599 user_sgpr_info->indirect_all_descriptor_sets = true;
600 } else {
601 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
602 }
603 }
604
605 static void
606 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
607 gl_shader_stage stage,
608 bool has_previous_stage,
609 gl_shader_stage previous_stage,
610 const struct user_sgpr_info *user_sgpr_info,
611 LLVMValueRef desc_sets,
612 uint8_t *user_sgpr_idx)
613 {
614 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
615 unsigned stage_mask = 1 << stage;
616 if (has_previous_stage)
617 stage_mask |= 1 << previous_stage;
618
619 if (!user_sgpr_info->indirect_all_descriptor_sets) {
620 for (unsigned i = 0; i < num_sets; ++i) {
621 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
622 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
623 } else
624 ctx->descriptor_sets[i] = NULL;
625 }
626 } else {
627 uint32_t desc_sgpr_idx = *user_sgpr_idx;
628 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
629
630 for (unsigned i = 0; i < num_sets; ++i) {
631 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
632 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
633 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
634
635 } else
636 ctx->descriptor_sets[i] = NULL;
637 }
638 ctx->shader_info->need_indirect_descriptor_sets = true;
639 }
640
641 if (ctx->shader_info->info.needs_push_constants) {
642 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
643 }
644 }
645
646
647 static void
648 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
649 gl_shader_stage stage,
650 bool has_previous_stage,
651 gl_shader_stage previous_stage,
652 uint8_t *user_sgpr_idx)
653 {
654 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
655 if (ctx->shader_info->info.vs.has_vertex_buffers) {
656 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
657 }
658 unsigned vs_num = 2;
659 if (ctx->shader_info->info.vs.needs_draw_id)
660 vs_num++;
661
662 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
663 }
664 }
665
666 static void
667 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
668 gl_shader_stage stage,
669 bool has_previous_stage,
670 gl_shader_stage previous_stage,
671 const struct user_sgpr_info *user_sgpr_info,
672 struct arg_info *args,
673 LLVMValueRef *desc_sets)
674 {
675 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
676 unsigned num_sets = ctx->options->layout ?
677 ctx->options->layout->num_sets : 0;
678 unsigned stage_mask = 1 << stage;
679
680 if (has_previous_stage)
681 stage_mask |= 1 << previous_stage;
682
683 /* 1 for each descriptor set */
684 if (!user_sgpr_info->indirect_all_descriptor_sets) {
685 for (unsigned i = 0; i < num_sets; ++i) {
686 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
687 add_array_arg(args, type,
688 &ctx->descriptor_sets[i]);
689 }
690 }
691 } else {
692 add_array_arg(args, const_array(type, 32), desc_sets);
693 }
694
695 if (ctx->shader_info->info.needs_push_constants) {
696 /* 1 for push constants and dynamic descriptors */
697 add_array_arg(args, type, &ctx->push_constants);
698 }
699 }
700
701 static void
702 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
703 gl_shader_stage stage,
704 bool has_previous_stage,
705 gl_shader_stage previous_stage,
706 struct arg_info *args)
707 {
708 if (!ctx->is_gs_copy_shader &&
709 (stage == MESA_SHADER_VERTEX ||
710 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
711 if (ctx->shader_info->info.vs.has_vertex_buffers) {
712 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
713 &ctx->vertex_buffers);
714 }
715 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
716 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
717 if (ctx->shader_info->info.vs.needs_draw_id) {
718 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
719 }
720 }
721 }
722
723 static void
724 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
725 {
726 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
727 if (!ctx->is_gs_copy_shader) {
728 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
729 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
730 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
731 }
732 }
733
734 static void
735 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
736 {
737 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
738 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
739 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
740 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_patch_id);
741 }
742
743 static void create_function(struct nir_to_llvm_context *ctx,
744 gl_shader_stage stage,
745 bool has_previous_stage,
746 gl_shader_stage previous_stage)
747 {
748 uint8_t user_sgpr_idx;
749 struct user_sgpr_info user_sgpr_info;
750 struct arg_info args = {};
751 LLVMValueRef desc_sets;
752
753 allocate_user_sgprs(ctx, &user_sgpr_info);
754
755 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
756 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
757 &ctx->ring_offsets);
758 }
759
760 switch (stage) {
761 case MESA_SHADER_COMPUTE:
762 declare_global_input_sgprs(ctx, stage, has_previous_stage,
763 previous_stage, &user_sgpr_info,
764 &args, &desc_sets);
765
766 if (ctx->shader_info->info.cs.uses_grid_size) {
767 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
768 &ctx->num_work_groups);
769 }
770
771 for (int i = 0; i < 3; i++) {
772 ctx->workgroup_ids[i] = NULL;
773 if (ctx->shader_info->info.cs.uses_block_id[i]) {
774 add_arg(&args, ARG_SGPR, ctx->ac.i32,
775 &ctx->workgroup_ids[i]);
776 }
777 }
778
779 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
780 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
781 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
782 &ctx->local_invocation_ids);
783 break;
784 case MESA_SHADER_VERTEX:
785 declare_global_input_sgprs(ctx, stage, has_previous_stage,
786 previous_stage, &user_sgpr_info,
787 &args, &desc_sets);
788 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
789 previous_stage, &args);
790
791 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
792 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
793 if (ctx->options->key.vs.as_es)
794 add_arg(&args, ARG_SGPR, ctx->ac.i32,
795 &ctx->es2gs_offset);
796 else if (ctx->options->key.vs.as_ls)
797 add_arg(&args, ARG_SGPR, ctx->ac.i32,
798 &ctx->ls_out_layout);
799
800 declare_vs_input_vgprs(ctx, &args);
801 break;
802 case MESA_SHADER_TESS_CTRL:
803 if (has_previous_stage) {
804 // First 6 system regs
805 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
806 add_arg(&args, ARG_SGPR, ctx->ac.i32,
807 &ctx->merged_wave_info);
808 add_arg(&args, ARG_SGPR, ctx->ac.i32,
809 &ctx->tess_factor_offset);
810
811 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
812 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
813 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
814
815 declare_global_input_sgprs(ctx, stage,
816 has_previous_stage,
817 previous_stage,
818 &user_sgpr_info, &args,
819 &desc_sets);
820 declare_vs_specific_input_sgprs(ctx, stage,
821 has_previous_stage,
822 previous_stage, &args);
823
824 add_arg(&args, ARG_SGPR, ctx->ac.i32,
825 &ctx->ls_out_layout);
826
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->tcs_offchip_layout);
829 add_arg(&args, ARG_SGPR, ctx->ac.i32,
830 &ctx->tcs_out_offsets);
831 add_arg(&args, ARG_SGPR, ctx->ac.i32,
832 &ctx->tcs_out_layout);
833 add_arg(&args, ARG_SGPR, ctx->ac.i32,
834 &ctx->tcs_in_layout);
835 if (ctx->shader_info->info.needs_multiview_view_index)
836 add_arg(&args, ARG_SGPR, ctx->ac.i32,
837 &ctx->view_index);
838
839 add_arg(&args, ARG_VGPR, ctx->ac.i32,
840 &ctx->tcs_patch_id);
841 add_arg(&args, ARG_VGPR, ctx->ac.i32,
842 &ctx->tcs_rel_ids);
843
844 declare_vs_input_vgprs(ctx, &args);
845 } else {
846 declare_global_input_sgprs(ctx, stage,
847 has_previous_stage,
848 previous_stage,
849 &user_sgpr_info, &args,
850 &desc_sets);
851
852 add_arg(&args, ARG_SGPR, ctx->ac.i32,
853 &ctx->tcs_offchip_layout);
854 add_arg(&args, ARG_SGPR, ctx->ac.i32,
855 &ctx->tcs_out_offsets);
856 add_arg(&args, ARG_SGPR, ctx->ac.i32,
857 &ctx->tcs_out_layout);
858 add_arg(&args, ARG_SGPR, ctx->ac.i32,
859 &ctx->tcs_in_layout);
860 if (ctx->shader_info->info.needs_multiview_view_index)
861 add_arg(&args, ARG_SGPR, ctx->ac.i32,
862 &ctx->view_index);
863
864 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
865 add_arg(&args, ARG_SGPR, ctx->ac.i32,
866 &ctx->tess_factor_offset);
867 add_arg(&args, ARG_VGPR, ctx->ac.i32,
868 &ctx->tcs_patch_id);
869 add_arg(&args, ARG_VGPR, ctx->ac.i32,
870 &ctx->tcs_rel_ids);
871 }
872 break;
873 case MESA_SHADER_TESS_EVAL:
874 declare_global_input_sgprs(ctx, stage, has_previous_stage,
875 previous_stage, &user_sgpr_info,
876 &args, &desc_sets);
877
878 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
879 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
880 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
881
882 if (ctx->options->key.tes.as_es) {
883 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
884 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
885 add_arg(&args, ARG_SGPR, ctx->ac.i32,
886 &ctx->es2gs_offset);
887 } else {
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
889 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
890 }
891 declare_tes_input_vgprs(ctx, &args);
892 break;
893 case MESA_SHADER_GEOMETRY:
894 if (has_previous_stage) {
895 // First 6 system regs
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->gs2vs_offset);
898 add_arg(&args, ARG_SGPR, ctx->ac.i32,
899 &ctx->merged_wave_info);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
903 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
904 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
905
906 declare_global_input_sgprs(ctx, stage,
907 has_previous_stage,
908 previous_stage,
909 &user_sgpr_info, &args,
910 &desc_sets);
911
912 if (previous_stage == MESA_SHADER_TESS_EVAL) {
913 add_arg(&args, ARG_SGPR, ctx->ac.i32,
914 &ctx->tcs_offchip_layout);
915 } else {
916 declare_vs_specific_input_sgprs(ctx, stage,
917 has_previous_stage,
918 previous_stage,
919 &args);
920 }
921
922 add_arg(&args, ARG_SGPR, ctx->ac.i32,
923 &ctx->gsvs_ring_stride);
924 add_arg(&args, ARG_SGPR, ctx->ac.i32,
925 &ctx->gsvs_num_entries);
926 if (ctx->shader_info->info.needs_multiview_view_index)
927 add_arg(&args, ARG_SGPR, ctx->ac.i32,
928 &ctx->view_index);
929
930 add_arg(&args, ARG_VGPR, ctx->ac.i32,
931 &ctx->gs_vtx_offset[0]);
932 add_arg(&args, ARG_VGPR, ctx->ac.i32,
933 &ctx->gs_vtx_offset[2]);
934 add_arg(&args, ARG_VGPR, ctx->ac.i32,
935 &ctx->abi.gs_prim_id);
936 add_arg(&args, ARG_VGPR, ctx->ac.i32,
937 &ctx->abi.gs_invocation_id);
938 add_arg(&args, ARG_VGPR, ctx->ac.i32,
939 &ctx->gs_vtx_offset[4]);
940
941 if (previous_stage == MESA_SHADER_VERTEX) {
942 declare_vs_input_vgprs(ctx, &args);
943 } else {
944 declare_tes_input_vgprs(ctx, &args);
945 }
946 } else {
947 declare_global_input_sgprs(ctx, stage,
948 has_previous_stage,
949 previous_stage,
950 &user_sgpr_info, &args,
951 &desc_sets);
952
953 add_arg(&args, ARG_SGPR, ctx->ac.i32,
954 &ctx->gsvs_ring_stride);
955 add_arg(&args, ARG_SGPR, ctx->ac.i32,
956 &ctx->gsvs_num_entries);
957 if (ctx->shader_info->info.needs_multiview_view_index)
958 add_arg(&args, ARG_SGPR, ctx->ac.i32,
959 &ctx->view_index);
960
961 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
962 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
963 add_arg(&args, ARG_VGPR, ctx->ac.i32,
964 &ctx->gs_vtx_offset[0]);
965 add_arg(&args, ARG_VGPR, ctx->ac.i32,
966 &ctx->gs_vtx_offset[1]);
967 add_arg(&args, ARG_VGPR, ctx->ac.i32,
968 &ctx->abi.gs_prim_id);
969 add_arg(&args, ARG_VGPR, ctx->ac.i32,
970 &ctx->gs_vtx_offset[2]);
971 add_arg(&args, ARG_VGPR, ctx->ac.i32,
972 &ctx->gs_vtx_offset[3]);
973 add_arg(&args, ARG_VGPR, ctx->ac.i32,
974 &ctx->gs_vtx_offset[4]);
975 add_arg(&args, ARG_VGPR, ctx->ac.i32,
976 &ctx->gs_vtx_offset[5]);
977 add_arg(&args, ARG_VGPR, ctx->ac.i32,
978 &ctx->abi.gs_invocation_id);
979 }
980 break;
981 case MESA_SHADER_FRAGMENT:
982 declare_global_input_sgprs(ctx, stage, has_previous_stage,
983 previous_stage, &user_sgpr_info,
984 &args, &desc_sets);
985
986 if (ctx->shader_info->info.ps.needs_sample_positions)
987 add_arg(&args, ARG_SGPR, ctx->ac.i32,
988 &ctx->sample_pos_offset);
989
990 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
991 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
992 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
993 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
994 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
995 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
996 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
997 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
998 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
999 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1000 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1001 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1002 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1003 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1004 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1005 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1006 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1007 break;
1008 default:
1009 unreachable("Shader stage not implemented");
1010 }
1011
1012 ctx->main_function = create_llvm_function(
1013 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1014 ctx->max_workgroup_size,
1015 ctx->options->unsafe_math);
1016 set_llvm_calling_convention(ctx->main_function, stage);
1017
1018
1019 ctx->shader_info->num_input_vgprs = 0;
1020 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1021
1022 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1023
1024 if (ctx->stage != MESA_SHADER_FRAGMENT)
1025 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1026
1027 assign_arguments(ctx->main_function, &args);
1028
1029 user_sgpr_idx = 0;
1030
1031 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1032 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
1033 if (ctx->options->supports_spill) {
1034 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1035 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1036 NULL, 0, AC_FUNC_ATTR_READNONE);
1037 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1038 const_array(ctx->ac.v4i32, 16), "");
1039 }
1040 }
1041
1042 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1043 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1044 if (has_previous_stage)
1045 user_sgpr_idx = 0;
1046
1047 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
1048
1049 switch (stage) {
1050 case MESA_SHADER_COMPUTE:
1051 if (ctx->shader_info->info.cs.uses_grid_size) {
1052 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE,
1053 &user_sgpr_idx, 3);
1054 }
1055 break;
1056 case MESA_SHADER_VERTEX:
1057 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
1058 if (ctx->view_index)
1059 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1060 if (ctx->options->key.vs.as_ls) {
1061 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
1062 }
1063 if (ctx->options->key.vs.as_ls)
1064 ac_declare_lds_as_pointer(&ctx->ac);
1065 break;
1066 case MESA_SHADER_TESS_CTRL:
1067 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
1068 if (has_previous_stage)
1069 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
1070 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1071 if (ctx->view_index)
1072 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1073 ac_declare_lds_as_pointer(&ctx->ac);
1074 break;
1075 case MESA_SHADER_TESS_EVAL:
1076 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1077 if (ctx->view_index)
1078 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1079 break;
1080 case MESA_SHADER_GEOMETRY:
1081 if (has_previous_stage) {
1082 if (previous_stage == MESA_SHADER_VERTEX)
1083 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
1084 else
1085 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1086 }
1087 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
1088 if (ctx->view_index)
1089 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1090 if (has_previous_stage)
1091 ac_declare_lds_as_pointer(&ctx->ac);
1092 break;
1093 case MESA_SHADER_FRAGMENT:
1094 if (ctx->shader_info->info.ps.needs_sample_positions) {
1095 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
1096 }
1097 break;
1098 default:
1099 unreachable("Shader stage not implemented");
1100 }
1101
1102 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1103 }
1104
1105 static int get_llvm_num_components(LLVMValueRef value)
1106 {
1107 LLVMTypeRef type = LLVMTypeOf(value);
1108 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1109 ? LLVMGetVectorSize(type)
1110 : 1;
1111 return num_components;
1112 }
1113
1114 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1115 LLVMValueRef value,
1116 int index)
1117 {
1118 int count = get_llvm_num_components(value);
1119
1120 if (count == 1)
1121 return value;
1122
1123 return LLVMBuildExtractElement(ac->builder, value,
1124 LLVMConstInt(ac->i32, index, false), "");
1125 }
1126
1127 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1128 LLVMValueRef value, unsigned count)
1129 {
1130 unsigned num_components = get_llvm_num_components(value);
1131 if (count == num_components)
1132 return value;
1133
1134 LLVMValueRef masks[] = {
1135 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1136 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1137
1138 if (count == 1)
1139 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1140 "");
1141
1142 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1143 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1144 }
1145
1146 static void
1147 build_store_values_extended(struct ac_llvm_context *ac,
1148 LLVMValueRef *values,
1149 unsigned value_count,
1150 unsigned value_stride,
1151 LLVMValueRef vec)
1152 {
1153 LLVMBuilderRef builder = ac->builder;
1154 unsigned i;
1155
1156 for (i = 0; i < value_count; i++) {
1157 LLVMValueRef ptr = values[i * value_stride];
1158 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1159 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1160 LLVMBuildStore(builder, value, ptr);
1161 }
1162 }
1163
1164 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1165 const nir_ssa_def *def)
1166 {
1167 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1168 if (def->num_components > 1) {
1169 type = LLVMVectorType(type, def->num_components);
1170 }
1171 return type;
1172 }
1173
1174 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1175 {
1176 assert(src.is_ssa);
1177 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1178 return (LLVMValueRef)entry->data;
1179 }
1180
1181
1182 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1183 const struct nir_block *b)
1184 {
1185 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1186 return (LLVMBasicBlockRef)entry->data;
1187 }
1188
1189 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1190 nir_alu_src src,
1191 unsigned num_components)
1192 {
1193 LLVMValueRef value = get_src(ctx, src.src);
1194 bool need_swizzle = false;
1195
1196 assert(value);
1197 LLVMTypeRef type = LLVMTypeOf(value);
1198 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1199 ? LLVMGetVectorSize(type)
1200 : 1;
1201
1202 for (unsigned i = 0; i < num_components; ++i) {
1203 assert(src.swizzle[i] < src_components);
1204 if (src.swizzle[i] != i)
1205 need_swizzle = true;
1206 }
1207
1208 if (need_swizzle || num_components != src_components) {
1209 LLVMValueRef masks[] = {
1210 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1211 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1212 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1213 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1214
1215 if (src_components > 1 && num_components == 1) {
1216 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1217 masks[0], "");
1218 } else if (src_components == 1 && num_components > 1) {
1219 LLVMValueRef values[] = {value, value, value, value};
1220 value = ac_build_gather_values(&ctx->ac, values, num_components);
1221 } else {
1222 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1223 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1224 swizzle, "");
1225 }
1226 }
1227 assert(!src.negate);
1228 assert(!src.abs);
1229 return value;
1230 }
1231
1232 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1233 LLVMIntPredicate pred, LLVMValueRef src0,
1234 LLVMValueRef src1)
1235 {
1236 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1237 return LLVMBuildSelect(ctx->builder, result,
1238 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1239 ctx->i32_0, "");
1240 }
1241
1242 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1243 LLVMRealPredicate pred, LLVMValueRef src0,
1244 LLVMValueRef src1)
1245 {
1246 LLVMValueRef result;
1247 src0 = ac_to_float(ctx, src0);
1248 src1 = ac_to_float(ctx, src1);
1249 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1250 return LLVMBuildSelect(ctx->builder, result,
1251 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1252 ctx->i32_0, "");
1253 }
1254
1255 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1256 const char *intrin,
1257 LLVMTypeRef result_type,
1258 LLVMValueRef src0)
1259 {
1260 char name[64];
1261 LLVMValueRef params[] = {
1262 ac_to_float(ctx, src0),
1263 };
1264
1265 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1266 get_elem_bits(ctx, result_type));
1267 assert(length < sizeof(name));
1268 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1269 }
1270
1271 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1272 const char *intrin,
1273 LLVMTypeRef result_type,
1274 LLVMValueRef src0, LLVMValueRef src1)
1275 {
1276 char name[64];
1277 LLVMValueRef params[] = {
1278 ac_to_float(ctx, src0),
1279 ac_to_float(ctx, src1),
1280 };
1281
1282 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1283 get_elem_bits(ctx, result_type));
1284 assert(length < sizeof(name));
1285 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1286 }
1287
1288 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1289 const char *intrin,
1290 LLVMTypeRef result_type,
1291 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1292 {
1293 char name[64];
1294 LLVMValueRef params[] = {
1295 ac_to_float(ctx, src0),
1296 ac_to_float(ctx, src1),
1297 ac_to_float(ctx, src2),
1298 };
1299
1300 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1301 get_elem_bits(ctx, result_type));
1302 assert(length < sizeof(name));
1303 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1304 }
1305
1306 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1307 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1308 {
1309 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1310 ctx->i32_0, "");
1311 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1312 }
1313
1314 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1315 LLVMIntPredicate pred,
1316 LLVMValueRef src0, LLVMValueRef src1)
1317 {
1318 return LLVMBuildSelect(ctx->builder,
1319 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1320 src0,
1321 src1, "");
1322
1323 }
1324 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1325 LLVMValueRef src0)
1326 {
1327 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1328 LLVMBuildNeg(ctx->builder, src0, ""));
1329 }
1330
1331 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1332 LLVMValueRef src0)
1333 {
1334 LLVMValueRef cmp, val;
1335
1336 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1337 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1338 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1339 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1340 return val;
1341 }
1342
1343 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1344 LLVMValueRef src0)
1345 {
1346 LLVMValueRef cmp, val;
1347
1348 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1349 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1350 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1351 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1352 return val;
1353 }
1354
1355 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1356 LLVMValueRef src0)
1357 {
1358 const char *intr = "llvm.floor.f32";
1359 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1360 LLVMValueRef params[] = {
1361 fsrc0,
1362 };
1363 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1364 ctx->f32, params, 1,
1365 AC_FUNC_ATTR_READNONE);
1366 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1367 }
1368
1369 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1370 const char *intrin,
1371 LLVMValueRef src0, LLVMValueRef src1)
1372 {
1373 LLVMTypeRef ret_type;
1374 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1375 LLVMValueRef res;
1376 LLVMValueRef params[] = { src0, src1 };
1377 ret_type = LLVMStructTypeInContext(ctx->context, types,
1378 2, true);
1379
1380 res = ac_build_intrinsic(ctx, intrin, ret_type,
1381 params, 2, AC_FUNC_ATTR_READNONE);
1382
1383 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1384 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1385 return res;
1386 }
1387
1388 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1389 LLVMValueRef src0)
1390 {
1391 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1392 }
1393
1394 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1395 LLVMValueRef src0)
1396 {
1397 src0 = ac_to_float(ctx, src0);
1398 return LLVMBuildSExt(ctx->builder,
1399 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1400 ctx->i32, "");
1401 }
1402
1403 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1404 LLVMValueRef src0)
1405 {
1406 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1407 }
1408
1409 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1410 LLVMValueRef src0)
1411 {
1412 return LLVMBuildSExt(ctx->builder,
1413 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1414 ctx->i32, "");
1415 }
1416
1417 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1418 LLVMValueRef src0)
1419 {
1420 LLVMValueRef result;
1421 LLVMValueRef cond = NULL;
1422
1423 src0 = ac_to_float(&ctx->ac, src0);
1424 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1425
1426 if (ctx->options->chip_class >= VI) {
1427 LLVMValueRef args[2];
1428 /* Check if the result is a denormal - and flush to 0 if so. */
1429 args[0] = result;
1430 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1431 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1432 }
1433
1434 /* need to convert back up to f32 */
1435 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1436
1437 if (ctx->options->chip_class >= VI)
1438 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1439 else {
1440 /* for SI/CIK */
1441 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1442 * so compare the result and flush to 0 if it's smaller.
1443 */
1444 LLVMValueRef temp, cond2;
1445 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1446 ctx->ac.f32, result);
1447 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1448 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1449 temp, "");
1450 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1451 temp, ctx->ac.f32_0, "");
1452 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1453 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1454 }
1455 return result;
1456 }
1457
1458 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1459 LLVMValueRef src0, LLVMValueRef src1)
1460 {
1461 LLVMValueRef dst64, result;
1462 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1463 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1464
1465 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1466 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1467 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1468 return result;
1469 }
1470
1471 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1472 LLVMValueRef src0, LLVMValueRef src1)
1473 {
1474 LLVMValueRef dst64, result;
1475 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1476 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1477
1478 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1479 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1480 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1481 return result;
1482 }
1483
1484 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1485 bool is_signed,
1486 const LLVMValueRef srcs[3])
1487 {
1488 LLVMValueRef result;
1489 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1490
1491 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1492 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1493 return result;
1494 }
1495
1496 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1497 LLVMValueRef src0, LLVMValueRef src1,
1498 LLVMValueRef src2, LLVMValueRef src3)
1499 {
1500 LLVMValueRef bfi_args[3], result;
1501
1502 bfi_args[0] = LLVMBuildShl(ctx->builder,
1503 LLVMBuildSub(ctx->builder,
1504 LLVMBuildShl(ctx->builder,
1505 ctx->i32_1,
1506 src3, ""),
1507 ctx->i32_1, ""),
1508 src2, "");
1509 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1510 bfi_args[2] = src0;
1511
1512 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1513
1514 /* Calculate:
1515 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1516 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1517 */
1518 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1519 LLVMBuildAnd(ctx->builder, bfi_args[0],
1520 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1521
1522 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1523 return result;
1524 }
1525
1526 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1527 LLVMValueRef src0)
1528 {
1529 LLVMValueRef comp[2];
1530
1531 src0 = ac_to_float(ctx, src0);
1532 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1533 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1534
1535 return ac_build_cvt_pkrtz_f16(ctx, comp);
1536 }
1537
1538 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1539 LLVMValueRef src0)
1540 {
1541 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1542 LLVMValueRef temps[2], result, val;
1543 int i;
1544
1545 for (i = 0; i < 2; i++) {
1546 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1547 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1548 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1549 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1550 }
1551
1552 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1553 ctx->i32_0, "");
1554 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1555 ctx->i32_1, "");
1556 return result;
1557 }
1558
1559 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1560 nir_op op,
1561 LLVMValueRef src0)
1562 {
1563 unsigned mask;
1564 int idx;
1565 LLVMValueRef result;
1566
1567 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1568 mask = AC_TID_MASK_LEFT;
1569 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1570 mask = AC_TID_MASK_TOP;
1571 else
1572 mask = AC_TID_MASK_TOP_LEFT;
1573
1574 /* for DDX we want to next X pixel, DDY next Y pixel. */
1575 if (op == nir_op_fddx_fine ||
1576 op == nir_op_fddx_coarse ||
1577 op == nir_op_fddx)
1578 idx = 1;
1579 else
1580 idx = 2;
1581
1582 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1583 return result;
1584 }
1585
1586 /*
1587 * this takes an I,J coordinate pair,
1588 * and works out the X and Y derivatives.
1589 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1590 */
1591 static LLVMValueRef emit_ddxy_interp(
1592 struct ac_nir_context *ctx,
1593 LLVMValueRef interp_ij)
1594 {
1595 LLVMValueRef result[4], a;
1596 unsigned i;
1597
1598 for (i = 0; i < 2; i++) {
1599 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1600 LLVMConstInt(ctx->ac.i32, i, false), "");
1601 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1602 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1603 }
1604 return ac_build_gather_values(&ctx->ac, result, 4);
1605 }
1606
1607 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1608 {
1609 LLVMValueRef src[4], result = NULL;
1610 unsigned num_components = instr->dest.dest.ssa.num_components;
1611 unsigned src_components;
1612 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1613
1614 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1615 switch (instr->op) {
1616 case nir_op_vec2:
1617 case nir_op_vec3:
1618 case nir_op_vec4:
1619 src_components = 1;
1620 break;
1621 case nir_op_pack_half_2x16:
1622 src_components = 2;
1623 break;
1624 case nir_op_unpack_half_2x16:
1625 src_components = 1;
1626 break;
1627 default:
1628 src_components = num_components;
1629 break;
1630 }
1631 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1632 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1633
1634 switch (instr->op) {
1635 case nir_op_fmov:
1636 case nir_op_imov:
1637 result = src[0];
1638 break;
1639 case nir_op_fneg:
1640 src[0] = ac_to_float(&ctx->ac, src[0]);
1641 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1642 break;
1643 case nir_op_ineg:
1644 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1645 break;
1646 case nir_op_inot:
1647 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1648 break;
1649 case nir_op_iadd:
1650 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1651 break;
1652 case nir_op_fadd:
1653 src[0] = ac_to_float(&ctx->ac, src[0]);
1654 src[1] = ac_to_float(&ctx->ac, src[1]);
1655 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1656 break;
1657 case nir_op_fsub:
1658 src[0] = ac_to_float(&ctx->ac, src[0]);
1659 src[1] = ac_to_float(&ctx->ac, src[1]);
1660 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1661 break;
1662 case nir_op_isub:
1663 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1664 break;
1665 case nir_op_imul:
1666 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1667 break;
1668 case nir_op_imod:
1669 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1670 break;
1671 case nir_op_umod:
1672 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1673 break;
1674 case nir_op_fmod:
1675 src[0] = ac_to_float(&ctx->ac, src[0]);
1676 src[1] = ac_to_float(&ctx->ac, src[1]);
1677 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1678 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1679 ac_to_float_type(&ctx->ac, def_type), result);
1680 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1681 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1682 break;
1683 case nir_op_frem:
1684 src[0] = ac_to_float(&ctx->ac, src[0]);
1685 src[1] = ac_to_float(&ctx->ac, src[1]);
1686 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1687 break;
1688 case nir_op_irem:
1689 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1690 break;
1691 case nir_op_idiv:
1692 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1693 break;
1694 case nir_op_udiv:
1695 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1696 break;
1697 case nir_op_fmul:
1698 src[0] = ac_to_float(&ctx->ac, src[0]);
1699 src[1] = ac_to_float(&ctx->ac, src[1]);
1700 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1701 break;
1702 case nir_op_fdiv:
1703 src[0] = ac_to_float(&ctx->ac, src[0]);
1704 src[1] = ac_to_float(&ctx->ac, src[1]);
1705 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1706 break;
1707 case nir_op_frcp:
1708 src[0] = ac_to_float(&ctx->ac, src[0]);
1709 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1710 break;
1711 case nir_op_iand:
1712 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1713 break;
1714 case nir_op_ior:
1715 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1716 break;
1717 case nir_op_ixor:
1718 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1719 break;
1720 case nir_op_ishl:
1721 result = LLVMBuildShl(ctx->ac.builder, src[0],
1722 LLVMBuildZExt(ctx->ac.builder, src[1],
1723 LLVMTypeOf(src[0]), ""),
1724 "");
1725 break;
1726 case nir_op_ishr:
1727 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1728 LLVMBuildZExt(ctx->ac.builder, src[1],
1729 LLVMTypeOf(src[0]), ""),
1730 "");
1731 break;
1732 case nir_op_ushr:
1733 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1734 LLVMBuildZExt(ctx->ac.builder, src[1],
1735 LLVMTypeOf(src[0]), ""),
1736 "");
1737 break;
1738 case nir_op_ilt:
1739 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1740 break;
1741 case nir_op_ine:
1742 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1743 break;
1744 case nir_op_ieq:
1745 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1746 break;
1747 case nir_op_ige:
1748 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1749 break;
1750 case nir_op_ult:
1751 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1752 break;
1753 case nir_op_uge:
1754 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1755 break;
1756 case nir_op_feq:
1757 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1758 break;
1759 case nir_op_fne:
1760 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1761 break;
1762 case nir_op_flt:
1763 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1764 break;
1765 case nir_op_fge:
1766 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1767 break;
1768 case nir_op_fabs:
1769 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1770 ac_to_float_type(&ctx->ac, def_type), src[0]);
1771 break;
1772 case nir_op_iabs:
1773 result = emit_iabs(&ctx->ac, src[0]);
1774 break;
1775 case nir_op_imax:
1776 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1777 break;
1778 case nir_op_imin:
1779 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1780 break;
1781 case nir_op_umax:
1782 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1783 break;
1784 case nir_op_umin:
1785 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1786 break;
1787 case nir_op_isign:
1788 result = emit_isign(&ctx->ac, src[0]);
1789 break;
1790 case nir_op_fsign:
1791 src[0] = ac_to_float(&ctx->ac, src[0]);
1792 result = emit_fsign(&ctx->ac, src[0]);
1793 break;
1794 case nir_op_ffloor:
1795 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1796 ac_to_float_type(&ctx->ac, def_type), src[0]);
1797 break;
1798 case nir_op_ftrunc:
1799 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1800 ac_to_float_type(&ctx->ac, def_type), src[0]);
1801 break;
1802 case nir_op_fceil:
1803 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1804 ac_to_float_type(&ctx->ac, def_type), src[0]);
1805 break;
1806 case nir_op_fround_even:
1807 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1808 ac_to_float_type(&ctx->ac, def_type),src[0]);
1809 break;
1810 case nir_op_ffract:
1811 result = emit_ffract(&ctx->ac, src[0]);
1812 break;
1813 case nir_op_fsin:
1814 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1815 ac_to_float_type(&ctx->ac, def_type), src[0]);
1816 break;
1817 case nir_op_fcos:
1818 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1819 ac_to_float_type(&ctx->ac, def_type), src[0]);
1820 break;
1821 case nir_op_fsqrt:
1822 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1823 ac_to_float_type(&ctx->ac, def_type), src[0]);
1824 break;
1825 case nir_op_fexp2:
1826 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1827 ac_to_float_type(&ctx->ac, def_type), src[0]);
1828 break;
1829 case nir_op_flog2:
1830 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1831 ac_to_float_type(&ctx->ac, def_type), src[0]);
1832 break;
1833 case nir_op_frsq:
1834 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1835 ac_to_float_type(&ctx->ac, def_type), src[0]);
1836 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1837 break;
1838 case nir_op_fpow:
1839 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1840 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1841 break;
1842 case nir_op_fmax:
1843 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1844 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1845 if (instr->dest.dest.ssa.bit_size == 32)
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1847 ac_to_float_type(&ctx->ac, def_type),
1848 result);
1849 break;
1850 case nir_op_fmin:
1851 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1852 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1853 if (instr->dest.dest.ssa.bit_size == 32)
1854 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1855 ac_to_float_type(&ctx->ac, def_type),
1856 result);
1857 break;
1858 case nir_op_ffma:
1859 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1860 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1861 break;
1862 case nir_op_ibitfield_extract:
1863 result = emit_bitfield_extract(&ctx->ac, true, src);
1864 break;
1865 case nir_op_ubitfield_extract:
1866 result = emit_bitfield_extract(&ctx->ac, false, src);
1867 break;
1868 case nir_op_bitfield_insert:
1869 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1870 break;
1871 case nir_op_bitfield_reverse:
1872 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1873 break;
1874 case nir_op_bit_count:
1875 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1876 break;
1877 case nir_op_vec2:
1878 case nir_op_vec3:
1879 case nir_op_vec4:
1880 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1881 src[i] = ac_to_integer(&ctx->ac, src[i]);
1882 result = ac_build_gather_values(&ctx->ac, src, num_components);
1883 break;
1884 case nir_op_f2i32:
1885 case nir_op_f2i64:
1886 src[0] = ac_to_float(&ctx->ac, src[0]);
1887 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1888 break;
1889 case nir_op_f2u32:
1890 case nir_op_f2u64:
1891 src[0] = ac_to_float(&ctx->ac, src[0]);
1892 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1893 break;
1894 case nir_op_i2f32:
1895 case nir_op_i2f64:
1896 src[0] = ac_to_integer(&ctx->ac, src[0]);
1897 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1898 break;
1899 case nir_op_u2f32:
1900 case nir_op_u2f64:
1901 src[0] = ac_to_integer(&ctx->ac, src[0]);
1902 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1903 break;
1904 case nir_op_f2f64:
1905 src[0] = ac_to_float(&ctx->ac, src[0]);
1906 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1907 break;
1908 case nir_op_f2f32:
1909 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1910 break;
1911 case nir_op_u2u32:
1912 case nir_op_u2u64:
1913 src[0] = ac_to_integer(&ctx->ac, src[0]);
1914 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1915 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1916 else
1917 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1918 break;
1919 case nir_op_i2i32:
1920 case nir_op_i2i64:
1921 src[0] = ac_to_integer(&ctx->ac, src[0]);
1922 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1923 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1924 else
1925 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1926 break;
1927 case nir_op_bcsel:
1928 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1929 break;
1930 case nir_op_find_lsb:
1931 src[0] = ac_to_integer(&ctx->ac, src[0]);
1932 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1933 break;
1934 case nir_op_ufind_msb:
1935 src[0] = ac_to_integer(&ctx->ac, src[0]);
1936 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1937 break;
1938 case nir_op_ifind_msb:
1939 src[0] = ac_to_integer(&ctx->ac, src[0]);
1940 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1941 break;
1942 case nir_op_uadd_carry:
1943 src[0] = ac_to_integer(&ctx->ac, src[0]);
1944 src[1] = ac_to_integer(&ctx->ac, src[1]);
1945 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1946 break;
1947 case nir_op_usub_borrow:
1948 src[0] = ac_to_integer(&ctx->ac, src[0]);
1949 src[1] = ac_to_integer(&ctx->ac, src[1]);
1950 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1951 break;
1952 case nir_op_b2f:
1953 result = emit_b2f(&ctx->ac, src[0]);
1954 break;
1955 case nir_op_f2b:
1956 result = emit_f2b(&ctx->ac, src[0]);
1957 break;
1958 case nir_op_b2i:
1959 result = emit_b2i(&ctx->ac, src[0]);
1960 break;
1961 case nir_op_i2b:
1962 src[0] = ac_to_integer(&ctx->ac, src[0]);
1963 result = emit_i2b(&ctx->ac, src[0]);
1964 break;
1965 case nir_op_fquantize2f16:
1966 result = emit_f2f16(ctx->nctx, src[0]);
1967 break;
1968 case nir_op_umul_high:
1969 src[0] = ac_to_integer(&ctx->ac, src[0]);
1970 src[1] = ac_to_integer(&ctx->ac, src[1]);
1971 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1972 break;
1973 case nir_op_imul_high:
1974 src[0] = ac_to_integer(&ctx->ac, src[0]);
1975 src[1] = ac_to_integer(&ctx->ac, src[1]);
1976 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1977 break;
1978 case nir_op_pack_half_2x16:
1979 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1980 break;
1981 case nir_op_unpack_half_2x16:
1982 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1983 break;
1984 case nir_op_fddx:
1985 case nir_op_fddy:
1986 case nir_op_fddx_fine:
1987 case nir_op_fddy_fine:
1988 case nir_op_fddx_coarse:
1989 case nir_op_fddy_coarse:
1990 result = emit_ddxy(ctx, instr->op, src[0]);
1991 break;
1992
1993 case nir_op_unpack_64_2x32_split_x: {
1994 assert(instr->src[0].src.ssa->num_components == 1);
1995 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1996 ctx->ac.v2i32,
1997 "");
1998 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1999 ctx->ac.i32_0, "");
2000 break;
2001 }
2002
2003 case nir_op_unpack_64_2x32_split_y: {
2004 assert(instr->src[0].src.ssa->num_components == 1);
2005 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2006 ctx->ac.v2i32,
2007 "");
2008 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2009 ctx->ac.i32_1, "");
2010 break;
2011 }
2012
2013 case nir_op_pack_64_2x32_split: {
2014 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2015 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2016 src[0], ctx->ac.i32_0, "");
2017 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2018 src[1], ctx->ac.i32_1, "");
2019 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2020 break;
2021 }
2022
2023 default:
2024 fprintf(stderr, "Unknown NIR alu instr: ");
2025 nir_print_instr(&instr->instr, stderr);
2026 fprintf(stderr, "\n");
2027 abort();
2028 }
2029
2030 if (result) {
2031 assert(instr->dest.dest.is_ssa);
2032 result = ac_to_integer(&ctx->ac, result);
2033 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2034 result);
2035 }
2036 }
2037
2038 static void visit_load_const(struct ac_nir_context *ctx,
2039 const nir_load_const_instr *instr)
2040 {
2041 LLVMValueRef values[4], value = NULL;
2042 LLVMTypeRef element_type =
2043 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2044
2045 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2046 switch (instr->def.bit_size) {
2047 case 32:
2048 values[i] = LLVMConstInt(element_type,
2049 instr->value.u32[i], false);
2050 break;
2051 case 64:
2052 values[i] = LLVMConstInt(element_type,
2053 instr->value.u64[i], false);
2054 break;
2055 default:
2056 fprintf(stderr,
2057 "unsupported nir load_const bit_size: %d\n",
2058 instr->def.bit_size);
2059 abort();
2060 }
2061 }
2062 if (instr->def.num_components > 1) {
2063 value = LLVMConstVector(values, instr->def.num_components);
2064 } else
2065 value = values[0];
2066
2067 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2068 }
2069
2070 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2071 LLVMTypeRef type)
2072 {
2073 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2074 return LLVMBuildBitCast(ctx->builder, ptr,
2075 LLVMPointerType(type, addr_space), "");
2076 }
2077
2078 static LLVMValueRef
2079 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2080 {
2081 LLVMValueRef size =
2082 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2083 LLVMConstInt(ctx->ac.i32, 2, false), "");
2084
2085 /* VI only */
2086 if (ctx->ac.chip_class == VI && in_elements) {
2087 /* On VI, the descriptor contains the size in bytes,
2088 * but TXQ must return the size in elements.
2089 * The stride is always non-zero for resources using TXQ.
2090 */
2091 LLVMValueRef stride =
2092 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2093 ctx->ac.i32_1, "");
2094 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2095 LLVMConstInt(ctx->ac.i32, 16, false), "");
2096 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2097 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2098
2099 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2100 }
2101 return size;
2102 }
2103
2104 /**
2105 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2106 * intrinsic names).
2107 */
2108 static void build_int_type_name(
2109 LLVMTypeRef type,
2110 char *buf, unsigned bufsize)
2111 {
2112 assert(bufsize >= 6);
2113
2114 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2115 snprintf(buf, bufsize, "v%ui32",
2116 LLVMGetVectorSize(type));
2117 else
2118 strcpy(buf, "i32");
2119 }
2120
2121 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2122 struct ac_image_args *args,
2123 const nir_tex_instr *instr)
2124 {
2125 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2126 LLVMValueRef coord = args->addr;
2127 LLVMValueRef half_texel[2];
2128 LLVMValueRef compare_cube_wa = NULL;
2129 LLVMValueRef result;
2130 int c;
2131 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2132
2133 //TODO Rect
2134 {
2135 struct ac_image_args txq_args = { 0 };
2136
2137 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2138 txq_args.opcode = ac_image_get_resinfo;
2139 txq_args.dmask = 0xf;
2140 txq_args.addr = ctx->i32_0;
2141 txq_args.resource = args->resource;
2142 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2143
2144 for (c = 0; c < 2; c++) {
2145 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2146 LLVMConstInt(ctx->i32, c, false), "");
2147 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2148 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2149 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2150 LLVMConstReal(ctx->f32, -0.5), "");
2151 }
2152 }
2153
2154 LLVMValueRef orig_coords = args->addr;
2155
2156 for (c = 0; c < 2; c++) {
2157 LLVMValueRef tmp;
2158 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2159 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2160 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2161 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2162 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2163 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2164 }
2165
2166
2167 /*
2168 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2169 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2170 * workaround by sampling using a scaled type and converting.
2171 * This is taken from amdgpu-pro shaders.
2172 */
2173 /* NOTE this produces some ugly code compared to amdgpu-pro,
2174 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2175 * and then reads them back. -pro generates two selects,
2176 * one s_cmp for the descriptor rewriting
2177 * one v_cmp for the coordinate and result changes.
2178 */
2179 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2180 LLVMValueRef tmp, tmp2;
2181
2182 /* workaround 8/8/8/8 uint/sint cube gather bug */
2183 /* first detect it then change to a scaled read and f2i */
2184 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2185 tmp2 = tmp;
2186
2187 /* extract the DATA_FORMAT */
2188 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2189 LLVMConstInt(ctx->i32, 6, false), false);
2190
2191 /* is the DATA_FORMAT == 8_8_8_8 */
2192 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2193
2194 if (stype == GLSL_TYPE_UINT)
2195 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2196 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2197 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2198 else
2199 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2200 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2201 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2202
2203 /* replace the NUM FORMAT in the descriptor */
2204 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2205 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2206
2207 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2208
2209 /* don't modify the coordinates for this case */
2210 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2211 }
2212 args->addr = coord;
2213 result = ac_build_image_opcode(ctx, args);
2214
2215 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2216 LLVMValueRef tmp, tmp2;
2217
2218 /* if the cube workaround is in place, f2i the result. */
2219 for (c = 0; c < 4; c++) {
2220 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2221 if (stype == GLSL_TYPE_UINT)
2222 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2223 else
2224 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2225 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2226 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2227 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2228 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2229 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2230 }
2231 }
2232 return result;
2233 }
2234
2235 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2236 const nir_tex_instr *instr,
2237 bool lod_is_zero,
2238 struct ac_image_args *args)
2239 {
2240 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2241 return ac_build_buffer_load_format(&ctx->ac,
2242 args->resource,
2243 args->addr,
2244 ctx->ac.i32_0,
2245 true);
2246 }
2247
2248 args->opcode = ac_image_sample;
2249 args->compare = instr->is_shadow;
2250
2251 switch (instr->op) {
2252 case nir_texop_txf:
2253 case nir_texop_txf_ms:
2254 case nir_texop_samples_identical:
2255 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2256 args->compare = false;
2257 args->offset = false;
2258 break;
2259 case nir_texop_txb:
2260 args->bias = true;
2261 break;
2262 case nir_texop_txl:
2263 if (lod_is_zero)
2264 args->level_zero = true;
2265 else
2266 args->lod = true;
2267 break;
2268 case nir_texop_txs:
2269 case nir_texop_query_levels:
2270 args->opcode = ac_image_get_resinfo;
2271 break;
2272 case nir_texop_tex:
2273 if (ctx->stage != MESA_SHADER_FRAGMENT)
2274 args->level_zero = true;
2275 break;
2276 case nir_texop_txd:
2277 args->deriv = true;
2278 break;
2279 case nir_texop_tg4:
2280 args->opcode = ac_image_gather4;
2281 args->level_zero = true;
2282 break;
2283 case nir_texop_lod:
2284 args->opcode = ac_image_get_lod;
2285 args->compare = false;
2286 args->offset = false;
2287 break;
2288 default:
2289 break;
2290 }
2291
2292 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2293 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2294 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2295 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2296 }
2297 }
2298 return ac_build_image_opcode(&ctx->ac, args);
2299 }
2300
2301 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2302 nir_intrinsic_instr *instr)
2303 {
2304 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2305 unsigned desc_set = nir_intrinsic_desc_set(instr);
2306 unsigned binding = nir_intrinsic_binding(instr);
2307 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2308 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2309 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2310 unsigned base_offset = layout->binding[binding].offset;
2311 LLVMValueRef offset, stride;
2312
2313 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2314 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2315 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2316 layout->binding[binding].dynamic_offset_offset;
2317 desc_ptr = ctx->push_constants;
2318 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2319 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2320 } else
2321 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2322
2323 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2324 index = LLVMBuildMul(ctx->builder, index, stride, "");
2325 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2326
2327 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2328 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2329 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2330
2331 return desc_ptr;
2332 }
2333
2334 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2335 nir_intrinsic_instr *instr)
2336 {
2337 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2338 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2339
2340 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2341 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2342 return result;
2343 }
2344
2345 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2346 nir_intrinsic_instr *instr)
2347 {
2348 LLVMValueRef ptr, addr;
2349
2350 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2351 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2352
2353 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2354 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2355
2356 return LLVMBuildLoad(ctx->builder, ptr, "");
2357 }
2358
2359 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2360 const nir_intrinsic_instr *instr)
2361 {
2362 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2363
2364 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2365 }
2366 static void visit_store_ssbo(struct ac_nir_context *ctx,
2367 nir_intrinsic_instr *instr)
2368 {
2369 const char *store_name;
2370 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2371 LLVMTypeRef data_type = ctx->ac.f32;
2372 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2373 int components_32bit = elem_size_mult * instr->num_components;
2374 unsigned writemask = nir_intrinsic_write_mask(instr);
2375 LLVMValueRef base_data, base_offset;
2376 LLVMValueRef params[6];
2377
2378 params[1] = ctx->abi->load_ssbo(ctx->abi,
2379 get_src(ctx, instr->src[1]), true);
2380 params[2] = ctx->ac.i32_0; /* vindex */
2381 params[4] = ctx->ac.i1false; /* glc */
2382 params[5] = ctx->ac.i1false; /* slc */
2383
2384 if (components_32bit > 1)
2385 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2386
2387 base_data = ac_to_float(&ctx->ac, src_data);
2388 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2389 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2390 data_type, "");
2391 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2392 while (writemask) {
2393 int start, count;
2394 LLVMValueRef data;
2395 LLVMValueRef offset;
2396 LLVMValueRef tmp;
2397 u_bit_scan_consecutive_range(&writemask, &start, &count);
2398
2399 /* Due to an LLVM limitation, split 3-element writes
2400 * into a 2-element and a 1-element write. */
2401 if (count == 3) {
2402 writemask |= 1 << (start + 2);
2403 count = 2;
2404 }
2405
2406 start *= elem_size_mult;
2407 count *= elem_size_mult;
2408
2409 if (count > 4) {
2410 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2411 count = 4;
2412 }
2413
2414 if (count == 4) {
2415 store_name = "llvm.amdgcn.buffer.store.v4f32";
2416 data = base_data;
2417 } else if (count == 2) {
2418 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2419 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2420 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2421 ctx->ac.i32_0, "");
2422
2423 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2424 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2425 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2426 ctx->ac.i32_1, "");
2427 store_name = "llvm.amdgcn.buffer.store.v2f32";
2428
2429 } else {
2430 assert(count == 1);
2431 if (get_llvm_num_components(base_data) > 1)
2432 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2433 LLVMConstInt(ctx->ac.i32, start, false), "");
2434 else
2435 data = base_data;
2436 store_name = "llvm.amdgcn.buffer.store.f32";
2437 }
2438
2439 offset = base_offset;
2440 if (start != 0) {
2441 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2442 }
2443 params[0] = data;
2444 params[3] = offset;
2445 ac_build_intrinsic(&ctx->ac, store_name,
2446 ctx->ac.voidt, params, 6, 0);
2447 }
2448 }
2449
2450 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2451 const nir_intrinsic_instr *instr)
2452 {
2453 const char *name;
2454 LLVMValueRef params[6];
2455 int arg_count = 0;
2456
2457 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2458 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2459 }
2460 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2461 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2462 get_src(ctx, instr->src[0]),
2463 true);
2464 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2465 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2466 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2467
2468 switch (instr->intrinsic) {
2469 case nir_intrinsic_ssbo_atomic_add:
2470 name = "llvm.amdgcn.buffer.atomic.add";
2471 break;
2472 case nir_intrinsic_ssbo_atomic_imin:
2473 name = "llvm.amdgcn.buffer.atomic.smin";
2474 break;
2475 case nir_intrinsic_ssbo_atomic_umin:
2476 name = "llvm.amdgcn.buffer.atomic.umin";
2477 break;
2478 case nir_intrinsic_ssbo_atomic_imax:
2479 name = "llvm.amdgcn.buffer.atomic.smax";
2480 break;
2481 case nir_intrinsic_ssbo_atomic_umax:
2482 name = "llvm.amdgcn.buffer.atomic.umax";
2483 break;
2484 case nir_intrinsic_ssbo_atomic_and:
2485 name = "llvm.amdgcn.buffer.atomic.and";
2486 break;
2487 case nir_intrinsic_ssbo_atomic_or:
2488 name = "llvm.amdgcn.buffer.atomic.or";
2489 break;
2490 case nir_intrinsic_ssbo_atomic_xor:
2491 name = "llvm.amdgcn.buffer.atomic.xor";
2492 break;
2493 case nir_intrinsic_ssbo_atomic_exchange:
2494 name = "llvm.amdgcn.buffer.atomic.swap";
2495 break;
2496 case nir_intrinsic_ssbo_atomic_comp_swap:
2497 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2498 break;
2499 default:
2500 abort();
2501 }
2502
2503 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2504 }
2505
2506 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2507 const nir_intrinsic_instr *instr)
2508 {
2509 LLVMValueRef results[2];
2510 int load_components;
2511 int num_components = instr->num_components;
2512 if (instr->dest.ssa.bit_size == 64)
2513 num_components *= 2;
2514
2515 for (int i = 0; i < num_components; i += load_components) {
2516 load_components = MIN2(num_components - i, 4);
2517 const char *load_name;
2518 LLVMTypeRef data_type = ctx->ac.f32;
2519 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2520 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2521
2522 if (load_components == 3)
2523 data_type = LLVMVectorType(ctx->ac.f32, 4);
2524 else if (load_components > 1)
2525 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2526
2527 if (load_components >= 3)
2528 load_name = "llvm.amdgcn.buffer.load.v4f32";
2529 else if (load_components == 2)
2530 load_name = "llvm.amdgcn.buffer.load.v2f32";
2531 else if (load_components == 1)
2532 load_name = "llvm.amdgcn.buffer.load.f32";
2533 else
2534 unreachable("unhandled number of components");
2535
2536 LLVMValueRef params[] = {
2537 ctx->abi->load_ssbo(ctx->abi,
2538 get_src(ctx, instr->src[0]),
2539 false),
2540 ctx->ac.i32_0,
2541 offset,
2542 ctx->ac.i1false,
2543 ctx->ac.i1false,
2544 };
2545
2546 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2547
2548 }
2549
2550 assume(results[0]);
2551 LLVMValueRef ret = results[0];
2552 if (num_components > 4 || num_components == 3) {
2553 LLVMValueRef masks[] = {
2554 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2555 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2556 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2557 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2558 };
2559
2560 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2561 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2562 results[num_components > 4 ? 1 : 0], swizzle, "");
2563 }
2564
2565 return LLVMBuildBitCast(ctx->ac.builder, ret,
2566 get_def_type(ctx, &instr->dest.ssa), "");
2567 }
2568
2569 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2570 const nir_intrinsic_instr *instr)
2571 {
2572 LLVMValueRef results[8], ret;
2573 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2574 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2575 int num_components = instr->num_components;
2576
2577 if (ctx->abi->load_ubo)
2578 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2579
2580 if (instr->dest.ssa.bit_size == 64)
2581 num_components *= 2;
2582
2583 for (unsigned i = 0; i < num_components; ++i) {
2584 LLVMValueRef params[] = {
2585 rsrc,
2586 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2587 offset, "")
2588 };
2589 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2590 params, 2,
2591 AC_FUNC_ATTR_READNONE |
2592 AC_FUNC_ATTR_LEGACY);
2593 }
2594
2595
2596 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2597 return LLVMBuildBitCast(ctx->ac.builder, ret,
2598 get_def_type(ctx, &instr->dest.ssa), "");
2599 }
2600
2601 static void
2602 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2603 bool vs_in, unsigned *vertex_index_out,
2604 LLVMValueRef *vertex_index_ref,
2605 unsigned *const_out, LLVMValueRef *indir_out)
2606 {
2607 unsigned const_offset = 0;
2608 nir_deref *tail = &deref->deref;
2609 LLVMValueRef offset = NULL;
2610
2611 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2612 tail = tail->child;
2613 nir_deref_array *deref_array = nir_deref_as_array(tail);
2614 if (vertex_index_out)
2615 *vertex_index_out = deref_array->base_offset;
2616
2617 if (vertex_index_ref) {
2618 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2619 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2620 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2621 }
2622 *vertex_index_ref = vtx;
2623 }
2624 }
2625
2626 if (deref->var->data.compact) {
2627 assert(tail->child->deref_type == nir_deref_type_array);
2628 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2629 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2630 /* We always lower indirect dereferences for "compact" array vars. */
2631 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2632
2633 const_offset = deref_array->base_offset;
2634 goto out;
2635 }
2636
2637 while (tail->child != NULL) {
2638 const struct glsl_type *parent_type = tail->type;
2639 tail = tail->child;
2640
2641 if (tail->deref_type == nir_deref_type_array) {
2642 nir_deref_array *deref_array = nir_deref_as_array(tail);
2643 LLVMValueRef index, stride, local_offset;
2644 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2645
2646 const_offset += size * deref_array->base_offset;
2647 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2648 continue;
2649
2650 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2651 index = get_src(ctx, deref_array->indirect);
2652 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2653 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2654
2655 if (offset)
2656 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2657 else
2658 offset = local_offset;
2659 } else if (tail->deref_type == nir_deref_type_struct) {
2660 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2661
2662 for (unsigned i = 0; i < deref_struct->index; i++) {
2663 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2664 const_offset += glsl_count_attribute_slots(ft, vs_in);
2665 }
2666 } else
2667 unreachable("unsupported deref type");
2668
2669 }
2670 out:
2671 if (const_offset && offset)
2672 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2673 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2674 "");
2675
2676 *const_out = const_offset;
2677 *indir_out = offset;
2678 }
2679
2680
2681 /* The offchip buffer layout for TCS->TES is
2682 *
2683 * - attribute 0 of patch 0 vertex 0
2684 * - attribute 0 of patch 0 vertex 1
2685 * - attribute 0 of patch 0 vertex 2
2686 * ...
2687 * - attribute 0 of patch 1 vertex 0
2688 * - attribute 0 of patch 1 vertex 1
2689 * ...
2690 * - attribute 1 of patch 0 vertex 0
2691 * - attribute 1 of patch 0 vertex 1
2692 * ...
2693 * - per patch attribute 0 of patch 0
2694 * - per patch attribute 0 of patch 1
2695 * ...
2696 *
2697 * Note that every attribute has 4 components.
2698 */
2699 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2700 LLVMValueRef vertex_index,
2701 LLVMValueRef param_index)
2702 {
2703 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2704 LLVMValueRef param_stride, constant16;
2705 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2706
2707 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2708 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2709 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2710 num_patches, "");
2711
2712 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2713 if (vertex_index) {
2714 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2715 vertices_per_patch, "");
2716
2717 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2718 vertex_index, "");
2719
2720 param_stride = total_vertices;
2721 } else {
2722 base_addr = rel_patch_id;
2723 param_stride = num_patches;
2724 }
2725
2726 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2727 LLVMBuildMul(ctx->builder, param_index,
2728 param_stride, ""), "");
2729
2730 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2731
2732 if (!vertex_index) {
2733 LLVMValueRef patch_data_offset =
2734 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2735
2736 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2737 patch_data_offset, "");
2738 }
2739 return base_addr;
2740 }
2741
2742 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2743 unsigned param,
2744 unsigned const_index,
2745 bool is_compact,
2746 LLVMValueRef vertex_index,
2747 LLVMValueRef indir_index)
2748 {
2749 LLVMValueRef param_index;
2750
2751 if (indir_index)
2752 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2753 indir_index, "");
2754 else {
2755 if (const_index && !is_compact)
2756 param += const_index;
2757 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2758 }
2759 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2760 }
2761
2762 static void
2763 mark_tess_output(struct nir_to_llvm_context *ctx,
2764 bool is_patch, uint32_t param)
2765
2766 {
2767 if (is_patch) {
2768 ctx->tess_patch_outputs_written |= (1ull << param);
2769 } else
2770 ctx->tess_outputs_written |= (1ull << param);
2771 }
2772
2773 static LLVMValueRef
2774 get_dw_address(struct nir_to_llvm_context *ctx,
2775 LLVMValueRef dw_addr,
2776 unsigned param,
2777 unsigned const_index,
2778 bool compact_const_index,
2779 LLVMValueRef vertex_index,
2780 LLVMValueRef stride,
2781 LLVMValueRef indir_index)
2782
2783 {
2784
2785 if (vertex_index) {
2786 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2787 LLVMBuildMul(ctx->builder,
2788 vertex_index,
2789 stride, ""), "");
2790 }
2791
2792 if (indir_index)
2793 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2794 LLVMBuildMul(ctx->builder, indir_index,
2795 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2796 else if (const_index && !compact_const_index)
2797 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2798 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2799
2800 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2801 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2802
2803 if (const_index && compact_const_index)
2804 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2805 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2806 return dw_addr;
2807 }
2808
2809 static LLVMValueRef
2810 load_tcs_input(struct nir_to_llvm_context *ctx,
2811 nir_intrinsic_instr *instr)
2812 {
2813 LLVMValueRef dw_addr, stride;
2814 unsigned const_index;
2815 LLVMValueRef vertex_index;
2816 LLVMValueRef indir_index;
2817 unsigned param;
2818 LLVMValueRef value[4], result;
2819 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2820 const bool is_compact = instr->variables[0]->var->data.compact;
2821 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2822 get_deref_offset(ctx->nir, instr->variables[0],
2823 false, NULL, per_vertex ? &vertex_index : NULL,
2824 &const_index, &indir_index);
2825
2826 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2827 dw_addr = get_tcs_in_current_patch_offset(ctx);
2828 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2829 indir_index);
2830
2831 unsigned comp = instr->variables[0]->var->data.location_frac;
2832 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2833 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2834 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2835 ctx->ac.i32_1, "");
2836 }
2837 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2838 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2839 return result;
2840 }
2841
2842 static LLVMValueRef
2843 load_tcs_output(struct nir_to_llvm_context *ctx,
2844 nir_intrinsic_instr *instr)
2845 {
2846 LLVMValueRef dw_addr;
2847 LLVMValueRef stride = NULL;
2848 LLVMValueRef value[4], result;
2849 LLVMValueRef vertex_index = NULL;
2850 LLVMValueRef indir_index = NULL;
2851 unsigned const_index = 0;
2852 unsigned param;
2853 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2854 const bool is_compact = instr->variables[0]->var->data.compact;
2855 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2856 get_deref_offset(ctx->nir, instr->variables[0],
2857 false, NULL, per_vertex ? &vertex_index : NULL,
2858 &const_index, &indir_index);
2859
2860 if (!instr->variables[0]->var->data.patch) {
2861 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2862 dw_addr = get_tcs_out_current_patch_offset(ctx);
2863 } else {
2864 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2865 }
2866
2867 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2868 indir_index);
2869
2870 unsigned comp = instr->variables[0]->var->data.location_frac;
2871 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2872 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2873 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2874 ctx->ac.i32_1, "");
2875 }
2876 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2877 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2878 return result;
2879 }
2880
2881 static void
2882 store_tcs_output(struct nir_to_llvm_context *ctx,
2883 nir_intrinsic_instr *instr,
2884 LLVMValueRef src,
2885 unsigned writemask)
2886 {
2887 LLVMValueRef dw_addr;
2888 LLVMValueRef stride = NULL;
2889 LLVMValueRef buf_addr = NULL;
2890 LLVMValueRef vertex_index = NULL;
2891 LLVMValueRef indir_index = NULL;
2892 unsigned const_index = 0;
2893 unsigned param;
2894 const unsigned comp = instr->variables[0]->var->data.location_frac;
2895 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2896 const bool is_compact = instr->variables[0]->var->data.compact;
2897 bool store_lds = true;
2898
2899 if (instr->variables[0]->var->data.patch) {
2900 if (!(ctx->tcs_patch_outputs_read & (1U << (instr->variables[0]->var->data.location - VARYING_SLOT_PATCH0))))
2901 store_lds = false;
2902 } else {
2903 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2904 store_lds = false;
2905 }
2906 get_deref_offset(ctx->nir, instr->variables[0],
2907 false, NULL, per_vertex ? &vertex_index : NULL,
2908 &const_index, &indir_index);
2909
2910 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2911 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2912 is_compact && const_index > 3) {
2913 const_index -= 3;
2914 param++;
2915 }
2916
2917 if (!instr->variables[0]->var->data.patch) {
2918 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2919 dw_addr = get_tcs_out_current_patch_offset(ctx);
2920 } else {
2921 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2922 }
2923
2924 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2925
2926 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2927 indir_index);
2928 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2929 vertex_index, indir_index);
2930
2931 bool is_tess_factor = false;
2932 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2933 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2934 is_tess_factor = true;
2935
2936 unsigned base = is_compact ? const_index : 0;
2937 for (unsigned chan = 0; chan < 8; chan++) {
2938 if (!(writemask & (1 << chan)))
2939 continue;
2940 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2941
2942 if (store_lds || is_tess_factor)
2943 ac_lds_store(&ctx->ac, dw_addr, value);
2944
2945 if (!is_tess_factor && writemask != 0xF)
2946 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2947 buf_addr, ctx->oc_lds,
2948 4 * (base + chan), 1, 0, true, false);
2949
2950 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2951 ctx->ac.i32_1, "");
2952 }
2953
2954 if (writemask == 0xF) {
2955 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2956 buf_addr, ctx->oc_lds,
2957 (base * 4), 1, 0, true, false);
2958 }
2959 }
2960
2961 static LLVMValueRef
2962 load_tes_input(struct nir_to_llvm_context *ctx,
2963 const nir_intrinsic_instr *instr)
2964 {
2965 LLVMValueRef buf_addr;
2966 LLVMValueRef result;
2967 LLVMValueRef vertex_index = NULL;
2968 LLVMValueRef indir_index = NULL;
2969 unsigned const_index = 0;
2970 unsigned param;
2971 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2972 const bool is_compact = instr->variables[0]->var->data.compact;
2973
2974 get_deref_offset(ctx->nir, instr->variables[0],
2975 false, NULL, per_vertex ? &vertex_index : NULL,
2976 &const_index, &indir_index);
2977 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2978 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2979 is_compact && const_index > 3) {
2980 const_index -= 3;
2981 param++;
2982 }
2983
2984 unsigned comp = instr->variables[0]->var->data.location_frac;
2985 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2986 is_compact, vertex_index, indir_index);
2987
2988 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2989 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2990
2991 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2992 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2993 result = trim_vector(&ctx->ac, result, instr->num_components);
2994 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2995 return result;
2996 }
2997
2998 static LLVMValueRef
2999 load_gs_input(struct ac_shader_abi *abi,
3000 unsigned location,
3001 unsigned driver_location,
3002 unsigned component,
3003 unsigned num_components,
3004 unsigned vertex_index,
3005 unsigned const_index,
3006 LLVMTypeRef type)
3007 {
3008 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3009 LLVMValueRef vtx_offset;
3010 LLVMValueRef args[9];
3011 unsigned param, vtx_offset_param;
3012 LLVMValueRef value[4], result;
3013
3014 vtx_offset_param = vertex_index;
3015 assert(vtx_offset_param < 6);
3016 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3017 LLVMConstInt(ctx->ac.i32, 4, false), "");
3018
3019 param = shader_io_get_unique_index(location);
3020
3021 for (unsigned i = component; i < num_components + component; i++) {
3022 if (ctx->ac.chip_class >= GFX9) {
3023 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3024 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3025 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3026 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3027 } else {
3028 args[0] = ctx->esgs_ring;
3029 args[1] = vtx_offset;
3030 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3031 args[3] = ctx->ac.i32_0;
3032 args[4] = ctx->ac.i32_1; /* OFFEN */
3033 args[5] = ctx->ac.i32_0; /* IDXEN */
3034 args[6] = ctx->ac.i32_1; /* GLC */
3035 args[7] = ctx->ac.i32_0; /* SLC */
3036 args[8] = ctx->ac.i32_0; /* TFE */
3037
3038 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3039 ctx->ac.i32, args, 9,
3040 AC_FUNC_ATTR_READONLY |
3041 AC_FUNC_ATTR_LEGACY);
3042 }
3043 }
3044 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3045
3046 return result;
3047 }
3048
3049 static LLVMValueRef
3050 build_gep_for_deref(struct ac_nir_context *ctx,
3051 nir_deref_var *deref)
3052 {
3053 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3054 assert(entry->data);
3055 LLVMValueRef val = entry->data;
3056 nir_deref *tail = deref->deref.child;
3057 while (tail != NULL) {
3058 LLVMValueRef offset;
3059 switch (tail->deref_type) {
3060 case nir_deref_type_array: {
3061 nir_deref_array *array = nir_deref_as_array(tail);
3062 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3063 if (array->deref_array_type ==
3064 nir_deref_array_type_indirect) {
3065 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3066 get_src(ctx,
3067 array->indirect),
3068 "");
3069 }
3070 break;
3071 }
3072 case nir_deref_type_struct: {
3073 nir_deref_struct *deref_struct =
3074 nir_deref_as_struct(tail);
3075 offset = LLVMConstInt(ctx->ac.i32,
3076 deref_struct->index, 0);
3077 break;
3078 }
3079 default:
3080 unreachable("bad deref type");
3081 }
3082 val = ac_build_gep0(&ctx->ac, val, offset);
3083 tail = tail->child;
3084 }
3085 return val;
3086 }
3087
3088 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3089 nir_intrinsic_instr *instr)
3090 {
3091 LLVMValueRef values[8];
3092 int idx = instr->variables[0]->var->data.driver_location;
3093 int ve = instr->dest.ssa.num_components;
3094 unsigned comp = instr->variables[0]->var->data.location_frac;
3095 LLVMValueRef indir_index;
3096 LLVMValueRef ret;
3097 unsigned const_index;
3098 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3099 instr->variables[0]->var->data.mode == nir_var_shader_in;
3100 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3101 &const_index, &indir_index);
3102
3103 if (instr->dest.ssa.bit_size == 64)
3104 ve *= 2;
3105
3106 switch (instr->variables[0]->var->data.mode) {
3107 case nir_var_shader_in:
3108 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3109 return load_tcs_input(ctx->nctx, instr);
3110 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3111 return load_tes_input(ctx->nctx, instr);
3112 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3113 LLVMValueRef indir_index;
3114 unsigned const_index, vertex_index;
3115 get_deref_offset(ctx, instr->variables[0],
3116 false, &vertex_index, NULL,
3117 &const_index, &indir_index);
3118 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3119 instr->variables[0]->var->data.driver_location,
3120 instr->variables[0]->var->data.location_frac, ve,
3121 vertex_index, const_index,
3122 nir2llvmtype(ctx, instr->variables[0]->var->type));
3123 }
3124
3125 for (unsigned chan = comp; chan < ve + comp; chan++) {
3126 if (indir_index) {
3127 unsigned count = glsl_count_attribute_slots(
3128 instr->variables[0]->var->type,
3129 ctx->stage == MESA_SHADER_VERTEX);
3130 count -= chan / 4;
3131 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3132 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3133 4, false, true);
3134
3135 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3136 tmp_vec,
3137 indir_index, "");
3138 } else
3139 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3140 }
3141 break;
3142 case nir_var_local:
3143 for (unsigned chan = 0; chan < ve; chan++) {
3144 if (indir_index) {
3145 unsigned count = glsl_count_attribute_slots(
3146 instr->variables[0]->var->type, false);
3147 count -= chan / 4;
3148 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3149 &ctx->ac, ctx->locals + idx + chan, count,
3150 4, true, true);
3151
3152 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3153 tmp_vec,
3154 indir_index, "");
3155 } else {
3156 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3157 }
3158 }
3159 break;
3160 case nir_var_shared: {
3161 LLVMValueRef address = build_gep_for_deref(ctx,
3162 instr->variables[0]);
3163 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3164 return LLVMBuildBitCast(ctx->ac.builder, val,
3165 get_def_type(ctx, &instr->dest.ssa),
3166 "");
3167 }
3168 case nir_var_shader_out:
3169 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3170 return load_tcs_output(ctx->nctx, instr);
3171
3172 for (unsigned chan = comp; chan < ve + comp; chan++) {
3173 if (indir_index) {
3174 unsigned count = glsl_count_attribute_slots(
3175 instr->variables[0]->var->type, false);
3176 count -= chan / 4;
3177 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3178 &ctx->ac, ctx->outputs + idx + chan, count,
3179 4, true, true);
3180
3181 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3182 tmp_vec,
3183 indir_index, "");
3184 } else {
3185 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3186 ctx->outputs[idx + chan + const_index * 4],
3187 "");
3188 }
3189 }
3190 break;
3191 default:
3192 unreachable("unhandle variable mode");
3193 }
3194 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3195 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3196 }
3197
3198 static void
3199 visit_store_var(struct ac_nir_context *ctx,
3200 nir_intrinsic_instr *instr)
3201 {
3202 LLVMValueRef temp_ptr, value;
3203 int idx = instr->variables[0]->var->data.driver_location;
3204 unsigned comp = instr->variables[0]->var->data.location_frac;
3205 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3206 int writemask = instr->const_index[0] << comp;
3207 LLVMValueRef indir_index;
3208 unsigned const_index;
3209 get_deref_offset(ctx, instr->variables[0], false,
3210 NULL, NULL, &const_index, &indir_index);
3211
3212 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3213 int old_writemask = writemask;
3214
3215 src = LLVMBuildBitCast(ctx->ac.builder, src,
3216 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3217 "");
3218
3219 writemask = 0;
3220 for (unsigned chan = 0; chan < 4; chan++) {
3221 if (old_writemask & (1 << chan))
3222 writemask |= 3u << (2 * chan);
3223 }
3224 }
3225
3226 switch (instr->variables[0]->var->data.mode) {
3227 case nir_var_shader_out:
3228
3229 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3230 store_tcs_output(ctx->nctx, instr, src, writemask);
3231 return;
3232 }
3233
3234 for (unsigned chan = 0; chan < 8; chan++) {
3235 int stride = 4;
3236 if (!(writemask & (1 << chan)))
3237 continue;
3238
3239 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3240
3241 if (instr->variables[0]->var->data.compact)
3242 stride = 1;
3243 if (indir_index) {
3244 unsigned count = glsl_count_attribute_slots(
3245 instr->variables[0]->var->type, false);
3246 count -= chan / 4;
3247 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3248 &ctx->ac, ctx->outputs + idx + chan, count,
3249 stride, true, true);
3250
3251 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3252 value, indir_index, "");
3253 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3254 count, stride, tmp_vec);
3255
3256 } else {
3257 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3258
3259 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3260 }
3261 }
3262 break;
3263 case nir_var_local:
3264 for (unsigned chan = 0; chan < 8; chan++) {
3265 if (!(writemask & (1 << chan)))
3266 continue;
3267
3268 value = llvm_extract_elem(&ctx->ac, src, chan);
3269 if (indir_index) {
3270 unsigned count = glsl_count_attribute_slots(
3271 instr->variables[0]->var->type, false);
3272 count -= chan / 4;
3273 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3274 &ctx->ac, ctx->locals + idx + chan, count,
3275 4, true, true);
3276
3277 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3278 value, indir_index, "");
3279 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3280 count, 4, tmp_vec);
3281 } else {
3282 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3283
3284 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3285 }
3286 }
3287 break;
3288 case nir_var_shared: {
3289 int writemask = instr->const_index[0];
3290 LLVMValueRef address = build_gep_for_deref(ctx,
3291 instr->variables[0]);
3292 LLVMValueRef val = get_src(ctx, instr->src[0]);
3293 unsigned components =
3294 glsl_get_vector_elements(
3295 nir_deref_tail(&instr->variables[0]->deref)->type);
3296 if (writemask == (1 << components) - 1) {
3297 val = LLVMBuildBitCast(
3298 ctx->ac.builder, val,
3299 LLVMGetElementType(LLVMTypeOf(address)), "");
3300 LLVMBuildStore(ctx->ac.builder, val, address);
3301 } else {
3302 for (unsigned chan = 0; chan < 4; chan++) {
3303 if (!(writemask & (1 << chan)))
3304 continue;
3305 LLVMValueRef ptr =
3306 LLVMBuildStructGEP(ctx->ac.builder,
3307 address, chan, "");
3308 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3309 chan);
3310 src = LLVMBuildBitCast(
3311 ctx->ac.builder, src,
3312 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3313 LLVMBuildStore(ctx->ac.builder, src, ptr);
3314 }
3315 }
3316 break;
3317 }
3318 default:
3319 break;
3320 }
3321 }
3322
3323 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3324 {
3325 switch (dim) {
3326 case GLSL_SAMPLER_DIM_BUF:
3327 return 1;
3328 case GLSL_SAMPLER_DIM_1D:
3329 return array ? 2 : 1;
3330 case GLSL_SAMPLER_DIM_2D:
3331 return array ? 3 : 2;
3332 case GLSL_SAMPLER_DIM_MS:
3333 return array ? 4 : 3;
3334 case GLSL_SAMPLER_DIM_3D:
3335 case GLSL_SAMPLER_DIM_CUBE:
3336 return 3;
3337 case GLSL_SAMPLER_DIM_RECT:
3338 case GLSL_SAMPLER_DIM_SUBPASS:
3339 return 2;
3340 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3341 return 3;
3342 default:
3343 break;
3344 }
3345 return 0;
3346 }
3347
3348
3349
3350 /* Adjust the sample index according to FMASK.
3351 *
3352 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3353 * which is the identity mapping. Each nibble says which physical sample
3354 * should be fetched to get that sample.
3355 *
3356 * For example, 0x11111100 means there are only 2 samples stored and
3357 * the second sample covers 3/4 of the pixel. When reading samples 0
3358 * and 1, return physical sample 0 (determined by the first two 0s
3359 * in FMASK), otherwise return physical sample 1.
3360 *
3361 * The sample index should be adjusted as follows:
3362 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3363 */
3364 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3365 LLVMValueRef coord_x, LLVMValueRef coord_y,
3366 LLVMValueRef coord_z,
3367 LLVMValueRef sample_index,
3368 LLVMValueRef fmask_desc_ptr)
3369 {
3370 LLVMValueRef fmask_load_address[4];
3371 LLVMValueRef res;
3372
3373 fmask_load_address[0] = coord_x;
3374 fmask_load_address[1] = coord_y;
3375 if (coord_z) {
3376 fmask_load_address[2] = coord_z;
3377 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3378 }
3379
3380 struct ac_image_args args = {0};
3381
3382 args.opcode = ac_image_load;
3383 args.da = coord_z ? true : false;
3384 args.resource = fmask_desc_ptr;
3385 args.dmask = 0xf;
3386 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3387
3388 res = ac_build_image_opcode(ctx, &args);
3389
3390 res = ac_to_integer(ctx, res);
3391 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3392 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3393
3394 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3395 res,
3396 ctx->i32_0, "");
3397
3398 LLVMValueRef sample_index4 =
3399 LLVMBuildMul(ctx->builder, sample_index, four, "");
3400 LLVMValueRef shifted_fmask =
3401 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3402 LLVMValueRef final_sample =
3403 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3404
3405 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3406 * resource descriptor is 0 (invalid),
3407 */
3408 LLVMValueRef fmask_desc =
3409 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3410 ctx->v8i32, "");
3411
3412 LLVMValueRef fmask_word1 =
3413 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3414 ctx->i32_1, "");
3415
3416 LLVMValueRef word1_is_nonzero =
3417 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3418 fmask_word1, ctx->i32_0, "");
3419
3420 /* Replace the MSAA sample index. */
3421 sample_index =
3422 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3423 final_sample, sample_index, "");
3424 return sample_index;
3425 }
3426
3427 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3428 const nir_intrinsic_instr *instr)
3429 {
3430 const struct glsl_type *type = instr->variables[0]->var->type;
3431 if(instr->variables[0]->deref.child)
3432 type = instr->variables[0]->deref.child->type;
3433
3434 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3435 LLVMValueRef coords[4];
3436 LLVMValueRef masks[] = {
3437 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3438 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3439 };
3440 LLVMValueRef res;
3441 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3442
3443 int count;
3444 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3445 bool is_array = glsl_sampler_type_is_array(type);
3446 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3447 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3448 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3449 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3450 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3451 count = image_type_to_components_count(dim, is_array);
3452
3453 if (is_ms) {
3454 LLVMValueRef fmask_load_address[3];
3455 int chan;
3456
3457 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3458 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3459 if (is_array)
3460 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3461 else
3462 fmask_load_address[2] = NULL;
3463 if (add_frag_pos) {
3464 for (chan = 0; chan < 2; ++chan)
3465 fmask_load_address[chan] =
3466 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3467 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3468 ctx->ac.i32, ""), "");
3469 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3470 }
3471 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3472 fmask_load_address[0],
3473 fmask_load_address[1],
3474 fmask_load_address[2],
3475 sample_index,
3476 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3477 }
3478 if (count == 1 && !gfx9_1d) {
3479 if (instr->src[0].ssa->num_components)
3480 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3481 else
3482 res = src0;
3483 } else {
3484 int chan;
3485 if (is_ms)
3486 count--;
3487 for (chan = 0; chan < count; ++chan) {
3488 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3489 }
3490 if (add_frag_pos) {
3491 for (chan = 0; chan < 2; ++chan)
3492 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3493 ctx->ac.i32, ""), "");
3494 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3495 count++;
3496 }
3497
3498 if (gfx9_1d) {
3499 if (is_array) {
3500 coords[2] = coords[1];
3501 coords[1] = ctx->ac.i32_0;
3502 } else
3503 coords[1] = ctx->ac.i32_0;
3504 count++;
3505 }
3506
3507 if (is_ms) {
3508 coords[count] = sample_index;
3509 count++;
3510 }
3511
3512 if (count == 3) {
3513 coords[3] = LLVMGetUndef(ctx->ac.i32);
3514 count = 4;
3515 }
3516 res = ac_build_gather_values(&ctx->ac, coords, count);
3517 }
3518 return res;
3519 }
3520
3521 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3522 const nir_intrinsic_instr *instr)
3523 {
3524 LLVMValueRef params[7];
3525 LLVMValueRef res;
3526 char intrinsic_name[64];
3527 const nir_variable *var = instr->variables[0]->var;
3528 const struct glsl_type *type = var->type;
3529
3530 if(instr->variables[0]->deref.child)
3531 type = instr->variables[0]->deref.child->type;
3532
3533 type = glsl_without_array(type);
3534 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3535 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3536 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3537 ctx->ac.i32_0, ""); /* vindex */
3538 params[2] = ctx->ac.i32_0; /* voffset */
3539 params[3] = ctx->ac.i1false; /* glc */
3540 params[4] = ctx->ac.i1false; /* slc */
3541 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3542 params, 5, 0);
3543
3544 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3545 res = ac_to_integer(&ctx->ac, res);
3546 } else {
3547 bool is_da = glsl_sampler_type_is_array(type) ||
3548 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3549 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3550 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3551 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3552 LLVMValueRef glc = ctx->ac.i1false;
3553 LLVMValueRef slc = ctx->ac.i1false;
3554
3555 params[0] = get_image_coords(ctx, instr);
3556 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3557 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3558 if (HAVE_LLVM <= 0x0309) {
3559 params[3] = ctx->ac.i1false; /* r128 */
3560 params[4] = da;
3561 params[5] = glc;
3562 params[6] = slc;
3563 } else {
3564 LLVMValueRef lwe = ctx->ac.i1false;
3565 params[3] = glc;
3566 params[4] = slc;
3567 params[5] = lwe;
3568 params[6] = da;
3569 }
3570
3571 ac_get_image_intr_name("llvm.amdgcn.image.load",
3572 ctx->ac.v4f32, /* vdata */
3573 LLVMTypeOf(params[0]), /* coords */
3574 LLVMTypeOf(params[1]), /* rsrc */
3575 intrinsic_name, sizeof(intrinsic_name));
3576
3577 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3578 params, 7, AC_FUNC_ATTR_READONLY);
3579 }
3580 return ac_to_integer(&ctx->ac, res);
3581 }
3582
3583 static void visit_image_store(struct ac_nir_context *ctx,
3584 nir_intrinsic_instr *instr)
3585 {
3586 LLVMValueRef params[8];
3587 char intrinsic_name[64];
3588 const nir_variable *var = instr->variables[0]->var;
3589 const struct glsl_type *type = glsl_without_array(var->type);
3590 LLVMValueRef glc = ctx->ac.i1false;
3591 bool force_glc = ctx->ac.chip_class == SI;
3592 if (force_glc)
3593 glc = ctx->ac.i1true;
3594
3595 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3596 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3597 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3598 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3599 ctx->ac.i32_0, ""); /* vindex */
3600 params[3] = ctx->ac.i32_0; /* voffset */
3601 params[4] = glc; /* glc */
3602 params[5] = ctx->ac.i1false; /* slc */
3603 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3604 params, 6, 0);
3605 } else {
3606 bool is_da = glsl_sampler_type_is_array(type) ||
3607 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3608 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3609 LLVMValueRef slc = ctx->ac.i1false;
3610
3611 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3612 params[1] = get_image_coords(ctx, instr); /* coords */
3613 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3614 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3615 if (HAVE_LLVM <= 0x0309) {
3616 params[4] = ctx->ac.i1false; /* r128 */
3617 params[5] = da;
3618 params[6] = glc;
3619 params[7] = slc;
3620 } else {
3621 LLVMValueRef lwe = ctx->ac.i1false;
3622 params[4] = glc;
3623 params[5] = slc;
3624 params[6] = lwe;
3625 params[7] = da;
3626 }
3627
3628 ac_get_image_intr_name("llvm.amdgcn.image.store",
3629 LLVMTypeOf(params[0]), /* vdata */
3630 LLVMTypeOf(params[1]), /* coords */
3631 LLVMTypeOf(params[2]), /* rsrc */
3632 intrinsic_name, sizeof(intrinsic_name));
3633
3634 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3635 params, 8, 0);
3636 }
3637
3638 }
3639
3640 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3641 const nir_intrinsic_instr *instr)
3642 {
3643 LLVMValueRef params[7];
3644 int param_count = 0;
3645 const nir_variable *var = instr->variables[0]->var;
3646
3647 const char *atomic_name;
3648 char intrinsic_name[41];
3649 const struct glsl_type *type = glsl_without_array(var->type);
3650 MAYBE_UNUSED int length;
3651
3652 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3653
3654 switch (instr->intrinsic) {
3655 case nir_intrinsic_image_atomic_add:
3656 atomic_name = "add";
3657 break;
3658 case nir_intrinsic_image_atomic_min:
3659 atomic_name = is_unsigned ? "umin" : "smin";
3660 break;
3661 case nir_intrinsic_image_atomic_max:
3662 atomic_name = is_unsigned ? "umax" : "smax";
3663 break;
3664 case nir_intrinsic_image_atomic_and:
3665 atomic_name = "and";
3666 break;
3667 case nir_intrinsic_image_atomic_or:
3668 atomic_name = "or";
3669 break;
3670 case nir_intrinsic_image_atomic_xor:
3671 atomic_name = "xor";
3672 break;
3673 case nir_intrinsic_image_atomic_exchange:
3674 atomic_name = "swap";
3675 break;
3676 case nir_intrinsic_image_atomic_comp_swap:
3677 atomic_name = "cmpswap";
3678 break;
3679 default:
3680 abort();
3681 }
3682
3683 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3684 params[param_count++] = get_src(ctx, instr->src[3]);
3685 params[param_count++] = get_src(ctx, instr->src[2]);
3686
3687 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3688 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3689 NULL, true, true);
3690 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3691 ctx->ac.i32_0, ""); /* vindex */
3692 params[param_count++] = ctx->ac.i32_0; /* voffset */
3693 params[param_count++] = ctx->ac.i1false; /* slc */
3694
3695 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3696 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3697 } else {
3698 char coords_type[8];
3699
3700 bool da = glsl_sampler_type_is_array(type) ||
3701 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3702
3703 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3704 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3705 NULL, true, true);
3706 params[param_count++] = ctx->ac.i1false; /* r128 */
3707 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3708 params[param_count++] = ctx->ac.i1false; /* slc */
3709
3710 build_int_type_name(LLVMTypeOf(coords),
3711 coords_type, sizeof(coords_type));
3712
3713 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3714 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3715 }
3716
3717 assert(length < sizeof(intrinsic_name));
3718 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3719 }
3720
3721 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3722 const nir_intrinsic_instr *instr)
3723 {
3724 LLVMValueRef res;
3725 const nir_variable *var = instr->variables[0]->var;
3726 const struct glsl_type *type = instr->variables[0]->var->type;
3727 bool da = glsl_sampler_type_is_array(var->type) ||
3728 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3729 if(instr->variables[0]->deref.child)
3730 type = instr->variables[0]->deref.child->type;
3731
3732 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3733 return get_buffer_size(ctx,
3734 get_sampler_desc(ctx, instr->variables[0],
3735 AC_DESC_BUFFER, NULL, true, false), true);
3736
3737 struct ac_image_args args = { 0 };
3738
3739 args.da = da;
3740 args.dmask = 0xf;
3741 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3742 args.opcode = ac_image_get_resinfo;
3743 args.addr = ctx->ac.i32_0;
3744
3745 res = ac_build_image_opcode(&ctx->ac, &args);
3746
3747 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3748
3749 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3750 glsl_sampler_type_is_array(type)) {
3751 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3752 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3753 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3754 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3755 }
3756 if (ctx->ac.chip_class >= GFX9 &&
3757 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3758 glsl_sampler_type_is_array(type)) {
3759 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3760 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3761 ctx->ac.i32_1, "");
3762
3763 }
3764 return res;
3765 }
3766
3767 #define NOOP_WAITCNT 0xf7f
3768 #define LGKM_CNT 0x07f
3769 #define VM_CNT 0xf70
3770
3771 static void emit_membar(struct nir_to_llvm_context *ctx,
3772 const nir_intrinsic_instr *instr)
3773 {
3774 unsigned waitcnt = NOOP_WAITCNT;
3775
3776 switch (instr->intrinsic) {
3777 case nir_intrinsic_memory_barrier:
3778 case nir_intrinsic_group_memory_barrier:
3779 waitcnt &= VM_CNT & LGKM_CNT;
3780 break;
3781 case nir_intrinsic_memory_barrier_atomic_counter:
3782 case nir_intrinsic_memory_barrier_buffer:
3783 case nir_intrinsic_memory_barrier_image:
3784 waitcnt &= VM_CNT;
3785 break;
3786 case nir_intrinsic_memory_barrier_shared:
3787 waitcnt &= LGKM_CNT;
3788 break;
3789 default:
3790 break;
3791 }
3792 if (waitcnt != NOOP_WAITCNT)
3793 ac_build_waitcnt(&ctx->ac, waitcnt);
3794 }
3795
3796 static void emit_barrier(struct nir_to_llvm_context *ctx)
3797 {
3798 /* SI only (thanks to a hw bug workaround):
3799 * The real barrier instruction isn’t needed, because an entire patch
3800 * always fits into a single wave.
3801 */
3802 if (ctx->options->chip_class == SI &&
3803 ctx->stage == MESA_SHADER_TESS_CTRL) {
3804 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3805 return;
3806 }
3807 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3808 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3809 }
3810
3811 static void emit_discard_if(struct ac_nir_context *ctx,
3812 const nir_intrinsic_instr *instr)
3813 {
3814 LLVMValueRef cond;
3815
3816 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3817 get_src(ctx, instr->src[0]),
3818 ctx->ac.i32_0, "");
3819 ac_build_kill_if_false(&ctx->ac, cond);
3820 }
3821
3822 static LLVMValueRef
3823 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3824 {
3825 LLVMValueRef result;
3826 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3827 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3828 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3829
3830 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3831 }
3832
3833 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3834 const nir_intrinsic_instr *instr)
3835 {
3836 LLVMValueRef ptr, result;
3837 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3838 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3839
3840 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3841 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3842 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3843 ptr, src, src1,
3844 LLVMAtomicOrderingSequentiallyConsistent,
3845 LLVMAtomicOrderingSequentiallyConsistent,
3846 false);
3847 } else {
3848 LLVMAtomicRMWBinOp op;
3849 switch (instr->intrinsic) {
3850 case nir_intrinsic_var_atomic_add:
3851 op = LLVMAtomicRMWBinOpAdd;
3852 break;
3853 case nir_intrinsic_var_atomic_umin:
3854 op = LLVMAtomicRMWBinOpUMin;
3855 break;
3856 case nir_intrinsic_var_atomic_umax:
3857 op = LLVMAtomicRMWBinOpUMax;
3858 break;
3859 case nir_intrinsic_var_atomic_imin:
3860 op = LLVMAtomicRMWBinOpMin;
3861 break;
3862 case nir_intrinsic_var_atomic_imax:
3863 op = LLVMAtomicRMWBinOpMax;
3864 break;
3865 case nir_intrinsic_var_atomic_and:
3866 op = LLVMAtomicRMWBinOpAnd;
3867 break;
3868 case nir_intrinsic_var_atomic_or:
3869 op = LLVMAtomicRMWBinOpOr;
3870 break;
3871 case nir_intrinsic_var_atomic_xor:
3872 op = LLVMAtomicRMWBinOpXor;
3873 break;
3874 case nir_intrinsic_var_atomic_exchange:
3875 op = LLVMAtomicRMWBinOpXchg;
3876 break;
3877 default:
3878 return NULL;
3879 }
3880
3881 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3882 LLVMAtomicOrderingSequentiallyConsistent,
3883 false);
3884 }
3885 return result;
3886 }
3887
3888 #define INTERP_CENTER 0
3889 #define INTERP_CENTROID 1
3890 #define INTERP_SAMPLE 2
3891
3892 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3893 enum glsl_interp_mode interp, unsigned location)
3894 {
3895 switch (interp) {
3896 case INTERP_MODE_FLAT:
3897 default:
3898 return NULL;
3899 case INTERP_MODE_SMOOTH:
3900 case INTERP_MODE_NONE:
3901 if (location == INTERP_CENTER)
3902 return ctx->persp_center;
3903 else if (location == INTERP_CENTROID)
3904 return ctx->persp_centroid;
3905 else if (location == INTERP_SAMPLE)
3906 return ctx->persp_sample;
3907 break;
3908 case INTERP_MODE_NOPERSPECTIVE:
3909 if (location == INTERP_CENTER)
3910 return ctx->linear_center;
3911 else if (location == INTERP_CENTROID)
3912 return ctx->linear_centroid;
3913 else if (location == INTERP_SAMPLE)
3914 return ctx->linear_sample;
3915 break;
3916 }
3917 return NULL;
3918 }
3919
3920 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3921 LLVMValueRef sample_id)
3922 {
3923 LLVMValueRef result;
3924 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3925
3926 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3927 const_array(ctx->ac.v2f32, 64), "");
3928
3929 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3930 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3931
3932 return result;
3933 }
3934
3935 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3936 {
3937 LLVMValueRef values[2];
3938
3939 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3940 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3941 return ac_build_gather_values(&ctx->ac, values, 2);
3942 }
3943
3944 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3945 const nir_intrinsic_instr *instr)
3946 {
3947 LLVMValueRef result[4];
3948 LLVMValueRef interp_param, attr_number;
3949 unsigned location;
3950 unsigned chan;
3951 LLVMValueRef src_c0 = NULL;
3952 LLVMValueRef src_c1 = NULL;
3953 LLVMValueRef src0 = NULL;
3954 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3955 switch (instr->intrinsic) {
3956 case nir_intrinsic_interp_var_at_centroid:
3957 location = INTERP_CENTROID;
3958 break;
3959 case nir_intrinsic_interp_var_at_sample:
3960 case nir_intrinsic_interp_var_at_offset:
3961 location = INTERP_CENTER;
3962 src0 = get_src(ctx->nir, instr->src[0]);
3963 break;
3964 default:
3965 break;
3966 }
3967
3968 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3969 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3970 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3971 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3972 LLVMValueRef sample_position;
3973 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
3974
3975 /* fetch sample ID */
3976 sample_position = load_sample_position(ctx, src0);
3977
3978 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3979 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3980 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3981 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3982 }
3983 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3984 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3985
3986 if (location == INTERP_CENTER) {
3987 LLVMValueRef ij_out[2];
3988 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3989
3990 /*
3991 * take the I then J parameters, and the DDX/Y for it, and
3992 * calculate the IJ inputs for the interpolator.
3993 * temp1 = ddx * offset/sample.x + I;
3994 * interp_param.I = ddy * offset/sample.y + temp1;
3995 * temp1 = ddx * offset/sample.x + J;
3996 * interp_param.J = ddy * offset/sample.y + temp1;
3997 */
3998 for (unsigned i = 0; i < 2; i++) {
3999 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4000 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4001 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4002 ddxy_out, ix_ll, "");
4003 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4004 ddxy_out, iy_ll, "");
4005 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4006 interp_param, ix_ll, "");
4007 LLVMValueRef temp1, temp2;
4008
4009 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4010 ctx->ac.f32, "");
4011
4012 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4013 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4014
4015 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4016 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4017
4018 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4019 temp2, ctx->ac.i32, "");
4020 }
4021 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4022
4023 }
4024
4025 for (chan = 0; chan < 4; chan++) {
4026 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4027
4028 if (interp_param) {
4029 interp_param = LLVMBuildBitCast(ctx->builder,
4030 interp_param, ctx->ac.v2f32, "");
4031 LLVMValueRef i = LLVMBuildExtractElement(
4032 ctx->builder, interp_param, ctx->ac.i32_0, "");
4033 LLVMValueRef j = LLVMBuildExtractElement(
4034 ctx->builder, interp_param, ctx->ac.i32_1, "");
4035
4036 result[chan] = ac_build_fs_interp(&ctx->ac,
4037 llvm_chan, attr_number,
4038 ctx->prim_mask, i, j);
4039 } else {
4040 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4041 LLVMConstInt(ctx->ac.i32, 2, false),
4042 llvm_chan, attr_number,
4043 ctx->prim_mask);
4044 }
4045 }
4046 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4047 instr->variables[0]->var->data.location_frac);
4048 }
4049
4050 static void
4051 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4052 {
4053 LLVMValueRef gs_next_vertex;
4054 LLVMValueRef can_emit;
4055 int idx;
4056 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4057
4058 /* Write vertex attribute values to GSVS ring */
4059 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4060 ctx->gs_next_vertex,
4061 "");
4062
4063 /* If this thread has already emitted the declared maximum number of
4064 * vertices, kill it: excessive vertex emissions are not supposed to
4065 * have any effect, and GS threads have no externally observable
4066 * effects other than emitting vertices.
4067 */
4068 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4069 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4070 ac_build_kill_if_false(&ctx->ac, can_emit);
4071
4072 /* loop num outputs */
4073 idx = 0;
4074 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4075 LLVMValueRef *out_ptr = &addrs[i * 4];
4076 int length = 4;
4077 int slot = idx;
4078 int slot_inc = 1;
4079
4080 if (!(ctx->output_mask & (1ull << i)))
4081 continue;
4082
4083 if (i == VARYING_SLOT_CLIP_DIST0) {
4084 /* pack clip and cull into a single set of slots */
4085 length = ctx->num_output_clips + ctx->num_output_culls;
4086 if (length > 4)
4087 slot_inc = 2;
4088 }
4089 for (unsigned j = 0; j < length; j++) {
4090 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4091 out_ptr[j], "");
4092 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4093 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4094 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4095
4096 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4097
4098 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4099 out_val, 1,
4100 voffset, ctx->gs2vs_offset, 0,
4101 1, 1, true, true);
4102 }
4103 idx += slot_inc;
4104 }
4105
4106 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4107 ctx->ac.i32_1, "");
4108 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4109
4110 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4111 }
4112
4113 static void
4114 visit_end_primitive(struct nir_to_llvm_context *ctx,
4115 const nir_intrinsic_instr *instr)
4116 {
4117 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4118 }
4119
4120 static LLVMValueRef
4121 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4122 const nir_intrinsic_instr *instr)
4123 {
4124 LLVMValueRef coord[4] = {
4125 ctx->tes_u,
4126 ctx->tes_v,
4127 ctx->ac.f32_0,
4128 ctx->ac.f32_0,
4129 };
4130
4131 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4132 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4133 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4134
4135 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4136 return LLVMBuildBitCast(ctx->builder, result,
4137 get_def_type(ctx->nir, &instr->dest.ssa), "");
4138 }
4139
4140 static void visit_intrinsic(struct ac_nir_context *ctx,
4141 nir_intrinsic_instr *instr)
4142 {
4143 LLVMValueRef result = NULL;
4144
4145 switch (instr->intrinsic) {
4146 case nir_intrinsic_load_work_group_id: {
4147 LLVMValueRef values[3];
4148
4149 for (int i = 0; i < 3; i++) {
4150 values[i] = ctx->nctx->workgroup_ids[i] ?
4151 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4152 }
4153
4154 result = ac_build_gather_values(&ctx->ac, values, 3);
4155 break;
4156 }
4157 case nir_intrinsic_load_base_vertex: {
4158 result = ctx->abi->base_vertex;
4159 break;
4160 }
4161 case nir_intrinsic_load_vertex_id_zero_base: {
4162 result = ctx->abi->vertex_id;
4163 break;
4164 }
4165 case nir_intrinsic_load_local_invocation_id: {
4166 result = ctx->nctx->local_invocation_ids;
4167 break;
4168 }
4169 case nir_intrinsic_load_base_instance:
4170 result = ctx->abi->start_instance;
4171 break;
4172 case nir_intrinsic_load_draw_id:
4173 result = ctx->abi->draw_id;
4174 break;
4175 case nir_intrinsic_load_view_index:
4176 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4177 break;
4178 case nir_intrinsic_load_invocation_id:
4179 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4180 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4181 else
4182 result = ctx->abi->gs_invocation_id;
4183 break;
4184 case nir_intrinsic_load_primitive_id:
4185 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4186 if (ctx->nctx)
4187 ctx->nctx->shader_info->gs.uses_prim_id = true;
4188 result = ctx->abi->gs_prim_id;
4189 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4190 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4191 result = ctx->nctx->tcs_patch_id;
4192 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4193 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4194 result = ctx->nctx->tes_patch_id;
4195 } else
4196 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4197 break;
4198 case nir_intrinsic_load_sample_id:
4199 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4200 break;
4201 case nir_intrinsic_load_sample_pos:
4202 result = load_sample_pos(ctx);
4203 break;
4204 case nir_intrinsic_load_sample_mask_in:
4205 result = ctx->abi->sample_coverage;
4206 break;
4207 case nir_intrinsic_load_frag_coord: {
4208 LLVMValueRef values[4] = {
4209 ctx->abi->frag_pos[0],
4210 ctx->abi->frag_pos[1],
4211 ctx->abi->frag_pos[2],
4212 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4213 };
4214 result = ac_build_gather_values(&ctx->ac, values, 4);
4215 break;
4216 }
4217 case nir_intrinsic_load_front_face:
4218 result = ctx->abi->front_face;
4219 break;
4220 case nir_intrinsic_load_instance_id:
4221 result = ctx->abi->instance_id;
4222 break;
4223 case nir_intrinsic_load_num_work_groups:
4224 result = ctx->nctx->num_work_groups;
4225 break;
4226 case nir_intrinsic_load_local_invocation_index:
4227 result = visit_load_local_invocation_index(ctx->nctx);
4228 break;
4229 case nir_intrinsic_load_push_constant:
4230 result = visit_load_push_constant(ctx->nctx, instr);
4231 break;
4232 case nir_intrinsic_vulkan_resource_index:
4233 result = visit_vulkan_resource_index(ctx->nctx, instr);
4234 break;
4235 case nir_intrinsic_vulkan_resource_reindex:
4236 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4237 break;
4238 case nir_intrinsic_store_ssbo:
4239 visit_store_ssbo(ctx, instr);
4240 break;
4241 case nir_intrinsic_load_ssbo:
4242 result = visit_load_buffer(ctx, instr);
4243 break;
4244 case nir_intrinsic_ssbo_atomic_add:
4245 case nir_intrinsic_ssbo_atomic_imin:
4246 case nir_intrinsic_ssbo_atomic_umin:
4247 case nir_intrinsic_ssbo_atomic_imax:
4248 case nir_intrinsic_ssbo_atomic_umax:
4249 case nir_intrinsic_ssbo_atomic_and:
4250 case nir_intrinsic_ssbo_atomic_or:
4251 case nir_intrinsic_ssbo_atomic_xor:
4252 case nir_intrinsic_ssbo_atomic_exchange:
4253 case nir_intrinsic_ssbo_atomic_comp_swap:
4254 result = visit_atomic_ssbo(ctx, instr);
4255 break;
4256 case nir_intrinsic_load_ubo:
4257 result = visit_load_ubo_buffer(ctx, instr);
4258 break;
4259 case nir_intrinsic_get_buffer_size:
4260 result = visit_get_buffer_size(ctx, instr);
4261 break;
4262 case nir_intrinsic_load_var:
4263 result = visit_load_var(ctx, instr);
4264 break;
4265 case nir_intrinsic_store_var:
4266 visit_store_var(ctx, instr);
4267 break;
4268 case nir_intrinsic_image_load:
4269 result = visit_image_load(ctx, instr);
4270 break;
4271 case nir_intrinsic_image_store:
4272 visit_image_store(ctx, instr);
4273 break;
4274 case nir_intrinsic_image_atomic_add:
4275 case nir_intrinsic_image_atomic_min:
4276 case nir_intrinsic_image_atomic_max:
4277 case nir_intrinsic_image_atomic_and:
4278 case nir_intrinsic_image_atomic_or:
4279 case nir_intrinsic_image_atomic_xor:
4280 case nir_intrinsic_image_atomic_exchange:
4281 case nir_intrinsic_image_atomic_comp_swap:
4282 result = visit_image_atomic(ctx, instr);
4283 break;
4284 case nir_intrinsic_image_size:
4285 result = visit_image_size(ctx, instr);
4286 break;
4287 case nir_intrinsic_discard:
4288 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4289 LLVMVoidTypeInContext(ctx->ac.context),
4290 NULL, 0, AC_FUNC_ATTR_LEGACY);
4291 break;
4292 case nir_intrinsic_discard_if:
4293 emit_discard_if(ctx, instr);
4294 break;
4295 case nir_intrinsic_memory_barrier:
4296 case nir_intrinsic_group_memory_barrier:
4297 case nir_intrinsic_memory_barrier_atomic_counter:
4298 case nir_intrinsic_memory_barrier_buffer:
4299 case nir_intrinsic_memory_barrier_image:
4300 case nir_intrinsic_memory_barrier_shared:
4301 emit_membar(ctx->nctx, instr);
4302 break;
4303 case nir_intrinsic_barrier:
4304 emit_barrier(ctx->nctx);
4305 break;
4306 case nir_intrinsic_var_atomic_add:
4307 case nir_intrinsic_var_atomic_imin:
4308 case nir_intrinsic_var_atomic_umin:
4309 case nir_intrinsic_var_atomic_imax:
4310 case nir_intrinsic_var_atomic_umax:
4311 case nir_intrinsic_var_atomic_and:
4312 case nir_intrinsic_var_atomic_or:
4313 case nir_intrinsic_var_atomic_xor:
4314 case nir_intrinsic_var_atomic_exchange:
4315 case nir_intrinsic_var_atomic_comp_swap:
4316 result = visit_var_atomic(ctx->nctx, instr);
4317 break;
4318 case nir_intrinsic_interp_var_at_centroid:
4319 case nir_intrinsic_interp_var_at_sample:
4320 case nir_intrinsic_interp_var_at_offset:
4321 result = visit_interp(ctx->nctx, instr);
4322 break;
4323 case nir_intrinsic_emit_vertex:
4324 assert(instr->const_index[0] == 0);
4325 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4326 break;
4327 case nir_intrinsic_end_primitive:
4328 visit_end_primitive(ctx->nctx, instr);
4329 break;
4330 case nir_intrinsic_load_tess_coord:
4331 result = visit_load_tess_coord(ctx->nctx, instr);
4332 break;
4333 case nir_intrinsic_load_patch_vertices_in:
4334 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4335 break;
4336 default:
4337 fprintf(stderr, "Unknown intrinsic: ");
4338 nir_print_instr(&instr->instr, stderr);
4339 fprintf(stderr, "\n");
4340 break;
4341 }
4342 if (result) {
4343 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4344 }
4345 }
4346
4347 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4348 LLVMValueRef buffer_ptr, bool write)
4349 {
4350 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4351
4352 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4353 ctx->shader_info->fs.writes_memory = true;
4354
4355 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4356 }
4357
4358 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4359 {
4360 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4361
4362 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4363 }
4364
4365 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4366 unsigned descriptor_set,
4367 unsigned base_index,
4368 unsigned constant_index,
4369 LLVMValueRef index,
4370 enum ac_descriptor_type desc_type,
4371 bool image, bool write)
4372 {
4373 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4374 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4375 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4376 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4377 unsigned offset = binding->offset;
4378 unsigned stride = binding->size;
4379 unsigned type_size;
4380 LLVMBuilderRef builder = ctx->builder;
4381 LLVMTypeRef type;
4382
4383 assert(base_index < layout->binding_count);
4384
4385 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4386 ctx->shader_info->fs.writes_memory = true;
4387
4388 switch (desc_type) {
4389 case AC_DESC_IMAGE:
4390 type = ctx->ac.v8i32;
4391 type_size = 32;
4392 break;
4393 case AC_DESC_FMASK:
4394 type = ctx->ac.v8i32;
4395 offset += 32;
4396 type_size = 32;
4397 break;
4398 case AC_DESC_SAMPLER:
4399 type = ctx->ac.v4i32;
4400 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4401 offset += 64;
4402
4403 type_size = 16;
4404 break;
4405 case AC_DESC_BUFFER:
4406 type = ctx->ac.v4i32;
4407 type_size = 16;
4408 break;
4409 default:
4410 unreachable("invalid desc_type\n");
4411 }
4412
4413 offset += constant_index * stride;
4414
4415 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4416 (!index || binding->immutable_samplers_equal)) {
4417 if (binding->immutable_samplers_equal)
4418 constant_index = 0;
4419
4420 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4421
4422 LLVMValueRef constants[] = {
4423 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4424 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4425 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4426 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4427 };
4428 return ac_build_gather_values(&ctx->ac, constants, 4);
4429 }
4430
4431 assert(stride % type_size == 0);
4432
4433 if (!index)
4434 index = ctx->ac.i32_0;
4435
4436 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4437
4438 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4439 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4440
4441 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4442 }
4443
4444 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4445 const nir_deref_var *deref,
4446 enum ac_descriptor_type desc_type,
4447 const nir_tex_instr *tex_instr,
4448 bool image, bool write)
4449 {
4450 LLVMValueRef index = NULL;
4451 unsigned constant_index = 0;
4452 unsigned descriptor_set;
4453 unsigned base_index;
4454
4455 if (!deref) {
4456 assert(tex_instr && !image);
4457 descriptor_set = 0;
4458 base_index = tex_instr->sampler_index;
4459 } else {
4460 const nir_deref *tail = &deref->deref;
4461 while (tail->child) {
4462 const nir_deref_array *child = nir_deref_as_array(tail->child);
4463 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4464
4465 if (!array_size)
4466 array_size = 1;
4467
4468 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4469
4470 if (child->deref_array_type == nir_deref_array_type_indirect) {
4471 LLVMValueRef indirect = get_src(ctx, child->indirect);
4472
4473 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4474 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4475
4476 if (!index)
4477 index = indirect;
4478 else
4479 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4480 }
4481
4482 constant_index += child->base_offset * array_size;
4483
4484 tail = &child->deref;
4485 }
4486 descriptor_set = deref->var->data.descriptor_set;
4487 base_index = deref->var->data.binding;
4488 }
4489
4490 return ctx->abi->load_sampler_desc(ctx->abi,
4491 descriptor_set,
4492 base_index,
4493 constant_index, index,
4494 desc_type, image, write);
4495 }
4496
4497 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4498 struct ac_image_args *args,
4499 const nir_tex_instr *instr,
4500 nir_texop op,
4501 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4502 LLVMValueRef *param, unsigned count,
4503 unsigned dmask)
4504 {
4505 unsigned is_rect = 0;
4506 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4507
4508 if (op == nir_texop_lod)
4509 da = false;
4510 /* Pad to power of two vector */
4511 while (count < util_next_power_of_two(count))
4512 param[count++] = LLVMGetUndef(ctx->i32);
4513
4514 if (count > 1)
4515 args->addr = ac_build_gather_values(ctx, param, count);
4516 else
4517 args->addr = param[0];
4518
4519 args->resource = res_ptr;
4520 args->sampler = samp_ptr;
4521
4522 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4523 args->addr = param[0];
4524 return;
4525 }
4526
4527 args->dmask = dmask;
4528 args->unorm = is_rect;
4529 args->da = da;
4530 }
4531
4532 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4533 *
4534 * SI-CI:
4535 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4536 * filtering manually. The driver sets img7 to a mask clearing
4537 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4538 * s_and_b32 samp0, samp0, img7
4539 *
4540 * VI:
4541 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4542 */
4543 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4544 LLVMValueRef res, LLVMValueRef samp)
4545 {
4546 LLVMBuilderRef builder = ctx->ac.builder;
4547 LLVMValueRef img7, samp0;
4548
4549 if (ctx->ac.chip_class >= VI)
4550 return samp;
4551
4552 img7 = LLVMBuildExtractElement(builder, res,
4553 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4554 samp0 = LLVMBuildExtractElement(builder, samp,
4555 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4556 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4557 return LLVMBuildInsertElement(builder, samp, samp0,
4558 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4559 }
4560
4561 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4562 nir_tex_instr *instr,
4563 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4564 LLVMValueRef *fmask_ptr)
4565 {
4566 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4567 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4568 else
4569 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4570 if (samp_ptr) {
4571 if (instr->sampler)
4572 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4573 else
4574 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4575 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4576 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4577 }
4578 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4579 instr->op == nir_texop_samples_identical))
4580 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4581 }
4582
4583 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4584 LLVMValueRef coord)
4585 {
4586 coord = ac_to_float(ctx, coord);
4587 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4588 coord = ac_to_integer(ctx, coord);
4589 return coord;
4590 }
4591
4592 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4593 {
4594 LLVMValueRef result = NULL;
4595 struct ac_image_args args = { 0 };
4596 unsigned dmask = 0xf;
4597 LLVMValueRef address[16];
4598 LLVMValueRef coords[5];
4599 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4600 LLVMValueRef bias = NULL, offsets = NULL;
4601 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4602 LLVMValueRef ddx = NULL, ddy = NULL;
4603 LLVMValueRef derivs[6];
4604 unsigned chan, count = 0;
4605 unsigned const_src = 0, num_deriv_comp = 0;
4606 bool lod_is_zero = false;
4607
4608 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4609
4610 for (unsigned i = 0; i < instr->num_srcs; i++) {
4611 switch (instr->src[i].src_type) {
4612 case nir_tex_src_coord:
4613 coord = get_src(ctx, instr->src[i].src);
4614 break;
4615 case nir_tex_src_projector:
4616 break;
4617 case nir_tex_src_comparator:
4618 comparator = get_src(ctx, instr->src[i].src);
4619 break;
4620 case nir_tex_src_offset:
4621 offsets = get_src(ctx, instr->src[i].src);
4622 const_src = i;
4623 break;
4624 case nir_tex_src_bias:
4625 bias = get_src(ctx, instr->src[i].src);
4626 break;
4627 case nir_tex_src_lod: {
4628 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4629
4630 if (val && val->i32[0] == 0)
4631 lod_is_zero = true;
4632 lod = get_src(ctx, instr->src[i].src);
4633 break;
4634 }
4635 case nir_tex_src_ms_index:
4636 sample_index = get_src(ctx, instr->src[i].src);
4637 break;
4638 case nir_tex_src_ms_mcs:
4639 break;
4640 case nir_tex_src_ddx:
4641 ddx = get_src(ctx, instr->src[i].src);
4642 num_deriv_comp = instr->src[i].src.ssa->num_components;
4643 break;
4644 case nir_tex_src_ddy:
4645 ddy = get_src(ctx, instr->src[i].src);
4646 break;
4647 case nir_tex_src_texture_offset:
4648 case nir_tex_src_sampler_offset:
4649 case nir_tex_src_plane:
4650 default:
4651 break;
4652 }
4653 }
4654
4655 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4656 result = get_buffer_size(ctx, res_ptr, true);
4657 goto write_result;
4658 }
4659
4660 if (instr->op == nir_texop_texture_samples) {
4661 LLVMValueRef res, samples, is_msaa;
4662 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4663 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4664 LLVMConstInt(ctx->ac.i32, 3, false), "");
4665 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4666 LLVMConstInt(ctx->ac.i32, 28, false), "");
4667 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4668 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4669 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4670 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4671
4672 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4673 LLVMConstInt(ctx->ac.i32, 16, false), "");
4674 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4675 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4676 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4677 samples, "");
4678 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4679 ctx->ac.i32_1, "");
4680 result = samples;
4681 goto write_result;
4682 }
4683
4684 if (coord)
4685 for (chan = 0; chan < instr->coord_components; chan++)
4686 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4687
4688 if (offsets && instr->op != nir_texop_txf) {
4689 LLVMValueRef offset[3], pack;
4690 for (chan = 0; chan < 3; ++chan)
4691 offset[chan] = ctx->ac.i32_0;
4692
4693 args.offset = true;
4694 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4695 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4696 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4697 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4698 if (chan)
4699 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4700 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4701 }
4702 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4703 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4704 address[count++] = pack;
4705
4706 }
4707 /* pack LOD bias value */
4708 if (instr->op == nir_texop_txb && bias) {
4709 address[count++] = bias;
4710 }
4711
4712 /* Pack depth comparison value */
4713 if (instr->is_shadow && comparator) {
4714 LLVMValueRef z = ac_to_float(&ctx->ac,
4715 llvm_extract_elem(&ctx->ac, comparator, 0));
4716
4717 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4718 * so the depth comparison value isn't clamped for Z16 and
4719 * Z24 anymore. Do it manually here.
4720 *
4721 * It's unnecessary if the original texture format was
4722 * Z32_FLOAT, but we don't know that here.
4723 */
4724 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4725 z = ac_build_clamp(&ctx->ac, z);
4726
4727 address[count++] = z;
4728 }
4729
4730 /* pack derivatives */
4731 if (ddx || ddy) {
4732 int num_src_deriv_channels, num_dest_deriv_channels;
4733 switch (instr->sampler_dim) {
4734 case GLSL_SAMPLER_DIM_3D:
4735 case GLSL_SAMPLER_DIM_CUBE:
4736 num_deriv_comp = 3;
4737 num_src_deriv_channels = 3;
4738 num_dest_deriv_channels = 3;
4739 break;
4740 case GLSL_SAMPLER_DIM_2D:
4741 default:
4742 num_src_deriv_channels = 2;
4743 num_dest_deriv_channels = 2;
4744 num_deriv_comp = 2;
4745 break;
4746 case GLSL_SAMPLER_DIM_1D:
4747 num_src_deriv_channels = 1;
4748 if (ctx->ac.chip_class >= GFX9) {
4749 num_dest_deriv_channels = 2;
4750 num_deriv_comp = 2;
4751 } else {
4752 num_dest_deriv_channels = 1;
4753 num_deriv_comp = 1;
4754 }
4755 break;
4756 }
4757
4758 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4759 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4760 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4761 }
4762 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4763 derivs[i] = ctx->ac.f32_0;
4764 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4765 }
4766 }
4767
4768 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4769 for (chan = 0; chan < instr->coord_components; chan++)
4770 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4771 if (instr->coord_components == 3)
4772 coords[3] = LLVMGetUndef(ctx->ac.f32);
4773 ac_prepare_cube_coords(&ctx->ac,
4774 instr->op == nir_texop_txd, instr->is_array,
4775 instr->op == nir_texop_lod, coords, derivs);
4776 if (num_deriv_comp)
4777 num_deriv_comp--;
4778 }
4779
4780 if (ddx || ddy) {
4781 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4782 address[count++] = derivs[i];
4783 }
4784
4785 /* Pack texture coordinates */
4786 if (coord) {
4787 address[count++] = coords[0];
4788 if (instr->coord_components > 1) {
4789 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4790 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4791 }
4792 address[count++] = coords[1];
4793 }
4794 if (instr->coord_components > 2) {
4795 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4796 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4797 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4798 instr->op != nir_texop_txf) {
4799 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4800 }
4801 address[count++] = coords[2];
4802 }
4803
4804 if (ctx->ac.chip_class >= GFX9) {
4805 LLVMValueRef filler;
4806 if (instr->op == nir_texop_txf)
4807 filler = ctx->ac.i32_0;
4808 else
4809 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4810
4811 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4812 /* No nir_texop_lod, because it does not take a slice
4813 * even with array textures. */
4814 if (instr->is_array && instr->op != nir_texop_lod ) {
4815 address[count] = address[count - 1];
4816 address[count - 1] = filler;
4817 count++;
4818 } else
4819 address[count++] = filler;
4820 }
4821 }
4822 }
4823
4824 /* Pack LOD */
4825 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4826 instr->op == nir_texop_txf)) {
4827 address[count++] = lod;
4828 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4829 address[count++] = sample_index;
4830 } else if(instr->op == nir_texop_txs) {
4831 count = 0;
4832 if (lod)
4833 address[count++] = lod;
4834 else
4835 address[count++] = ctx->ac.i32_0;
4836 }
4837
4838 for (chan = 0; chan < count; chan++) {
4839 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4840 address[chan], ctx->ac.i32, "");
4841 }
4842
4843 if (instr->op == nir_texop_samples_identical) {
4844 LLVMValueRef txf_address[4];
4845 struct ac_image_args txf_args = { 0 };
4846 unsigned txf_count = count;
4847 memcpy(txf_address, address, sizeof(txf_address));
4848
4849 if (!instr->is_array)
4850 txf_address[2] = ctx->ac.i32_0;
4851 txf_address[3] = ctx->ac.i32_0;
4852
4853 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4854 fmask_ptr, NULL,
4855 txf_address, txf_count, 0xf);
4856
4857 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4858
4859 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4860 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4861 goto write_result;
4862 }
4863
4864 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4865 instr->op != nir_texop_txs) {
4866 unsigned sample_chan = instr->is_array ? 3 : 2;
4867 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4868 address[0],
4869 address[1],
4870 instr->is_array ? address[2] : NULL,
4871 address[sample_chan],
4872 fmask_ptr);
4873 }
4874
4875 if (offsets && instr->op == nir_texop_txf) {
4876 nir_const_value *const_offset =
4877 nir_src_as_const_value(instr->src[const_src].src);
4878 int num_offsets = instr->src[const_src].src.ssa->num_components;
4879 assert(const_offset);
4880 num_offsets = MIN2(num_offsets, instr->coord_components);
4881 if (num_offsets > 2)
4882 address[2] = LLVMBuildAdd(ctx->ac.builder,
4883 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4884 if (num_offsets > 1)
4885 address[1] = LLVMBuildAdd(ctx->ac.builder,
4886 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4887 address[0] = LLVMBuildAdd(ctx->ac.builder,
4888 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4889
4890 }
4891
4892 /* TODO TG4 support */
4893 if (instr->op == nir_texop_tg4) {
4894 if (instr->is_shadow)
4895 dmask = 1;
4896 else
4897 dmask = 1 << instr->component;
4898 }
4899 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4900 res_ptr, samp_ptr, address, count, dmask);
4901
4902 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4903
4904 if (instr->op == nir_texop_query_levels)
4905 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4906 else if (instr->is_shadow && instr->is_new_style_shadow &&
4907 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4908 instr->op != nir_texop_tg4)
4909 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4910 else if (instr->op == nir_texop_txs &&
4911 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4912 instr->is_array) {
4913 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4914 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4915 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4916 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4917 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4918 } else if (ctx->ac.chip_class >= GFX9 &&
4919 instr->op == nir_texop_txs &&
4920 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4921 instr->is_array) {
4922 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4923 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4924 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4925 ctx->ac.i32_1, "");
4926 } else if (instr->dest.ssa.num_components != 4)
4927 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4928
4929 write_result:
4930 if (result) {
4931 assert(instr->dest.is_ssa);
4932 result = ac_to_integer(&ctx->ac, result);
4933 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4934 }
4935 }
4936
4937
4938 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4939 {
4940 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4941 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4942
4943 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4944 _mesa_hash_table_insert(ctx->phis, instr, result);
4945 }
4946
4947 static void visit_post_phi(struct ac_nir_context *ctx,
4948 nir_phi_instr *instr,
4949 LLVMValueRef llvm_phi)
4950 {
4951 nir_foreach_phi_src(src, instr) {
4952 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4953 LLVMValueRef llvm_src = get_src(ctx, src->src);
4954
4955 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4956 }
4957 }
4958
4959 static void phi_post_pass(struct ac_nir_context *ctx)
4960 {
4961 struct hash_entry *entry;
4962 hash_table_foreach(ctx->phis, entry) {
4963 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4964 (LLVMValueRef)entry->data);
4965 }
4966 }
4967
4968
4969 static void visit_ssa_undef(struct ac_nir_context *ctx,
4970 const nir_ssa_undef_instr *instr)
4971 {
4972 unsigned num_components = instr->def.num_components;
4973 LLVMValueRef undef;
4974
4975 if (num_components == 1)
4976 undef = LLVMGetUndef(ctx->ac.i32);
4977 else {
4978 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4979 }
4980 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4981 }
4982
4983 static void visit_jump(struct ac_nir_context *ctx,
4984 const nir_jump_instr *instr)
4985 {
4986 switch (instr->type) {
4987 case nir_jump_break:
4988 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4989 LLVMClearInsertionPosition(ctx->ac.builder);
4990 break;
4991 case nir_jump_continue:
4992 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4993 LLVMClearInsertionPosition(ctx->ac.builder);
4994 break;
4995 default:
4996 fprintf(stderr, "Unknown NIR jump instr: ");
4997 nir_print_instr(&instr->instr, stderr);
4998 fprintf(stderr, "\n");
4999 abort();
5000 }
5001 }
5002
5003 static void visit_cf_list(struct ac_nir_context *ctx,
5004 struct exec_list *list);
5005
5006 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5007 {
5008 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5009 nir_foreach_instr(instr, block)
5010 {
5011 switch (instr->type) {
5012 case nir_instr_type_alu:
5013 visit_alu(ctx, nir_instr_as_alu(instr));
5014 break;
5015 case nir_instr_type_load_const:
5016 visit_load_const(ctx, nir_instr_as_load_const(instr));
5017 break;
5018 case nir_instr_type_intrinsic:
5019 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5020 break;
5021 case nir_instr_type_tex:
5022 visit_tex(ctx, nir_instr_as_tex(instr));
5023 break;
5024 case nir_instr_type_phi:
5025 visit_phi(ctx, nir_instr_as_phi(instr));
5026 break;
5027 case nir_instr_type_ssa_undef:
5028 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5029 break;
5030 case nir_instr_type_jump:
5031 visit_jump(ctx, nir_instr_as_jump(instr));
5032 break;
5033 default:
5034 fprintf(stderr, "Unknown NIR instr type: ");
5035 nir_print_instr(instr, stderr);
5036 fprintf(stderr, "\n");
5037 abort();
5038 }
5039 }
5040
5041 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5042 }
5043
5044 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5045 {
5046 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5047
5048 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5049 LLVMBasicBlockRef merge_block =
5050 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5051 LLVMBasicBlockRef if_block =
5052 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5053 LLVMBasicBlockRef else_block = merge_block;
5054 if (!exec_list_is_empty(&if_stmt->else_list))
5055 else_block = LLVMAppendBasicBlockInContext(
5056 ctx->ac.context, fn, "");
5057
5058 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5059 ctx->ac.i32_0, "");
5060 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5061
5062 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5063 visit_cf_list(ctx, &if_stmt->then_list);
5064 if (LLVMGetInsertBlock(ctx->ac.builder))
5065 LLVMBuildBr(ctx->ac.builder, merge_block);
5066
5067 if (!exec_list_is_empty(&if_stmt->else_list)) {
5068 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5069 visit_cf_list(ctx, &if_stmt->else_list);
5070 if (LLVMGetInsertBlock(ctx->ac.builder))
5071 LLVMBuildBr(ctx->ac.builder, merge_block);
5072 }
5073
5074 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5075 }
5076
5077 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5078 {
5079 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5080 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5081 LLVMBasicBlockRef break_parent = ctx->break_block;
5082
5083 ctx->continue_block =
5084 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5085 ctx->break_block =
5086 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5087
5088 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5089 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5090 visit_cf_list(ctx, &loop->body);
5091
5092 if (LLVMGetInsertBlock(ctx->ac.builder))
5093 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5094 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5095
5096 ctx->continue_block = continue_parent;
5097 ctx->break_block = break_parent;
5098 }
5099
5100 static void visit_cf_list(struct ac_nir_context *ctx,
5101 struct exec_list *list)
5102 {
5103 foreach_list_typed(nir_cf_node, node, node, list)
5104 {
5105 switch (node->type) {
5106 case nir_cf_node_block:
5107 visit_block(ctx, nir_cf_node_as_block(node));
5108 break;
5109
5110 case nir_cf_node_if:
5111 visit_if(ctx, nir_cf_node_as_if(node));
5112 break;
5113
5114 case nir_cf_node_loop:
5115 visit_loop(ctx, nir_cf_node_as_loop(node));
5116 break;
5117
5118 default:
5119 assert(0);
5120 }
5121 }
5122 }
5123
5124 static void
5125 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5126 struct nir_variable *variable)
5127 {
5128 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5129 LLVMValueRef t_offset;
5130 LLVMValueRef t_list;
5131 LLVMValueRef input;
5132 LLVMValueRef buffer_index;
5133 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5134 int idx = variable->data.location;
5135 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5136
5137 variable->data.driver_location = idx * 4;
5138
5139 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5140 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5141 ctx->abi.start_instance, "");
5142 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5143 ctx->shader_info->vs.vgpr_comp_cnt);
5144 } else
5145 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5146 ctx->abi.base_vertex, "");
5147
5148 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5149 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5150
5151 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5152
5153 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5154 buffer_index,
5155 ctx->ac.i32_0,
5156 true);
5157
5158 for (unsigned chan = 0; chan < 4; chan++) {
5159 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5160 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5161 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5162 input, llvm_chan, ""));
5163 }
5164 }
5165 }
5166
5167 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5168 unsigned attr,
5169 LLVMValueRef interp_param,
5170 LLVMValueRef prim_mask,
5171 LLVMValueRef result[4])
5172 {
5173 LLVMValueRef attr_number;
5174 unsigned chan;
5175 LLVMValueRef i, j;
5176 bool interp = interp_param != NULL;
5177
5178 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5179
5180 /* fs.constant returns the param from the middle vertex, so it's not
5181 * really useful for flat shading. It's meant to be used for custom
5182 * interpolation (but the intrinsic can't fetch from the other two
5183 * vertices).
5184 *
5185 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5186 * to do the right thing. The only reason we use fs.constant is that
5187 * fs.interp cannot be used on integers, because they can be equal
5188 * to NaN.
5189 */
5190 if (interp) {
5191 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5192 ctx->ac.v2f32, "");
5193
5194 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5195 ctx->ac.i32_0, "");
5196 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5197 ctx->ac.i32_1, "");
5198 }
5199
5200 for (chan = 0; chan < 4; chan++) {
5201 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5202
5203 if (interp) {
5204 result[chan] = ac_build_fs_interp(&ctx->ac,
5205 llvm_chan,
5206 attr_number,
5207 prim_mask, i, j);
5208 } else {
5209 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5210 LLVMConstInt(ctx->ac.i32, 2, false),
5211 llvm_chan,
5212 attr_number,
5213 prim_mask);
5214 }
5215 }
5216 }
5217
5218 static void
5219 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5220 struct nir_variable *variable)
5221 {
5222 int idx = variable->data.location;
5223 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5224 LLVMValueRef interp;
5225
5226 variable->data.driver_location = idx * 4;
5227 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5228
5229 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5230 unsigned interp_type;
5231 if (variable->data.sample) {
5232 interp_type = INTERP_SAMPLE;
5233 ctx->shader_info->info.ps.force_persample = true;
5234 } else if (variable->data.centroid)
5235 interp_type = INTERP_CENTROID;
5236 else
5237 interp_type = INTERP_CENTER;
5238
5239 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5240 } else
5241 interp = NULL;
5242
5243 for (unsigned i = 0; i < attrib_count; ++i)
5244 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5245
5246 }
5247
5248 static void
5249 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5250 struct nir_shader *nir) {
5251 nir_foreach_variable(variable, &nir->inputs)
5252 handle_vs_input_decl(ctx, variable);
5253 }
5254
5255 static void
5256 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5257 struct nir_shader *nir)
5258 {
5259 if (!ctx->options->key.fs.multisample)
5260 return;
5261
5262 bool uses_center = false;
5263 bool uses_centroid = false;
5264 nir_foreach_variable(variable, &nir->inputs) {
5265 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5266 variable->data.sample)
5267 continue;
5268
5269 if (variable->data.centroid)
5270 uses_centroid = true;
5271 else
5272 uses_center = true;
5273 }
5274
5275 if (uses_center && uses_centroid) {
5276 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5277 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5278 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5279 }
5280 }
5281
5282 static void
5283 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5284 struct nir_shader *nir)
5285 {
5286 prepare_interp_optimize(ctx, nir);
5287
5288 nir_foreach_variable(variable, &nir->inputs)
5289 handle_fs_input_decl(ctx, variable);
5290
5291 unsigned index = 0;
5292
5293 if (ctx->shader_info->info.ps.uses_input_attachments ||
5294 ctx->shader_info->info.needs_multiview_view_index)
5295 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5296
5297 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5298 LLVMValueRef interp_param;
5299 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5300
5301 if (!(ctx->input_mask & (1ull << i)))
5302 continue;
5303
5304 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5305 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5306 interp_param = *inputs;
5307 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5308 inputs);
5309
5310 if (!interp_param)
5311 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5312 ++index;
5313 } else if (i == VARYING_SLOT_POS) {
5314 for(int i = 0; i < 3; ++i)
5315 inputs[i] = ctx->abi.frag_pos[i];
5316
5317 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5318 ctx->abi.frag_pos[3]);
5319 }
5320 }
5321 ctx->shader_info->fs.num_interp = index;
5322 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5323 ctx->shader_info->fs.has_pcoord = true;
5324 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5325 ctx->shader_info->fs.prim_id_input = true;
5326 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5327 ctx->shader_info->fs.layer_input = true;
5328 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5329
5330 if (ctx->shader_info->info.needs_multiview_view_index)
5331 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5332 }
5333
5334 static LLVMValueRef
5335 ac_build_alloca(struct ac_llvm_context *ac,
5336 LLVMTypeRef type,
5337 const char *name)
5338 {
5339 LLVMBuilderRef builder = ac->builder;
5340 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5341 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5342 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5343 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5344 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5345 LLVMValueRef res;
5346
5347 if (first_instr) {
5348 LLVMPositionBuilderBefore(first_builder, first_instr);
5349 } else {
5350 LLVMPositionBuilderAtEnd(first_builder, first_block);
5351 }
5352
5353 res = LLVMBuildAlloca(first_builder, type, name);
5354 LLVMBuildStore(builder, LLVMConstNull(type), res);
5355
5356 LLVMDisposeBuilder(first_builder);
5357
5358 return res;
5359 }
5360
5361 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5362 LLVMTypeRef type,
5363 const char *name)
5364 {
5365 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5366 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5367 return ptr;
5368 }
5369
5370 static void
5371 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5372 struct nir_variable *variable,
5373 struct nir_shader *shader,
5374 gl_shader_stage stage)
5375 {
5376 int idx = variable->data.location + variable->data.index;
5377 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5378 uint64_t mask_attribs;
5379
5380 variable->data.driver_location = idx * 4;
5381
5382 /* tess ctrl has it's own load/store paths for outputs */
5383 if (stage == MESA_SHADER_TESS_CTRL)
5384 return;
5385
5386 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5387 if (stage == MESA_SHADER_VERTEX ||
5388 stage == MESA_SHADER_TESS_EVAL ||
5389 stage == MESA_SHADER_GEOMETRY) {
5390 if (idx == VARYING_SLOT_CLIP_DIST0) {
5391 int length = shader->info.clip_distance_array_size +
5392 shader->info.cull_distance_array_size;
5393 if (stage == MESA_SHADER_VERTEX) {
5394 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5395 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5396 }
5397 if (stage == MESA_SHADER_TESS_EVAL) {
5398 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5399 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5400 }
5401
5402 if (length > 4)
5403 attrib_count = 2;
5404 else
5405 attrib_count = 1;
5406 mask_attribs = 1ull << idx;
5407 }
5408 }
5409
5410 ctx->output_mask |= mask_attribs;
5411 }
5412
5413 static void
5414 handle_shader_output_decl(struct ac_nir_context *ctx,
5415 struct nir_shader *nir,
5416 struct nir_variable *variable)
5417 {
5418 unsigned output_loc = variable->data.driver_location / 4;
5419 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5420
5421 /* tess ctrl has it's own load/store paths for outputs */
5422 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5423 return;
5424
5425 if (ctx->stage == MESA_SHADER_VERTEX ||
5426 ctx->stage == MESA_SHADER_TESS_EVAL ||
5427 ctx->stage == MESA_SHADER_GEOMETRY) {
5428 int idx = variable->data.location + variable->data.index;
5429 if (idx == VARYING_SLOT_CLIP_DIST0) {
5430 int length = nir->info.clip_distance_array_size +
5431 nir->info.cull_distance_array_size;
5432
5433 if (length > 4)
5434 attrib_count = 2;
5435 else
5436 attrib_count = 1;
5437 }
5438 }
5439
5440 for (unsigned i = 0; i < attrib_count; ++i) {
5441 for (unsigned chan = 0; chan < 4; chan++) {
5442 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5443 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5444 }
5445 }
5446 }
5447
5448 static LLVMTypeRef
5449 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5450 enum glsl_base_type type)
5451 {
5452 switch (type) {
5453 case GLSL_TYPE_INT:
5454 case GLSL_TYPE_UINT:
5455 case GLSL_TYPE_BOOL:
5456 case GLSL_TYPE_SUBROUTINE:
5457 return ctx->ac.i32;
5458 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5459 return ctx->ac.f32;
5460 case GLSL_TYPE_INT64:
5461 case GLSL_TYPE_UINT64:
5462 return ctx->ac.i64;
5463 case GLSL_TYPE_DOUBLE:
5464 return ctx->ac.f64;
5465 default:
5466 unreachable("unknown GLSL type");
5467 }
5468 }
5469
5470 static LLVMTypeRef
5471 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5472 const struct glsl_type *type)
5473 {
5474 if (glsl_type_is_scalar(type)) {
5475 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5476 }
5477
5478 if (glsl_type_is_vector(type)) {
5479 return LLVMVectorType(
5480 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5481 glsl_get_vector_elements(type));
5482 }
5483
5484 if (glsl_type_is_matrix(type)) {
5485 return LLVMArrayType(
5486 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5487 glsl_get_matrix_columns(type));
5488 }
5489
5490 if (glsl_type_is_array(type)) {
5491 return LLVMArrayType(
5492 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5493 glsl_get_length(type));
5494 }
5495
5496 assert(glsl_type_is_struct(type));
5497
5498 LLVMTypeRef member_types[glsl_get_length(type)];
5499
5500 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5501 member_types[i] =
5502 glsl_to_llvm_type(ctx,
5503 glsl_get_struct_field(type, i));
5504 }
5505
5506 return LLVMStructTypeInContext(ctx->context, member_types,
5507 glsl_get_length(type), false);
5508 }
5509
5510 static void
5511 setup_locals(struct ac_nir_context *ctx,
5512 struct nir_function *func)
5513 {
5514 int i, j;
5515 ctx->num_locals = 0;
5516 nir_foreach_variable(variable, &func->impl->locals) {
5517 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5518 variable->data.driver_location = ctx->num_locals * 4;
5519 ctx->num_locals += attrib_count;
5520 }
5521 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5522 if (!ctx->locals)
5523 return;
5524
5525 for (i = 0; i < ctx->num_locals; i++) {
5526 for (j = 0; j < 4; j++) {
5527 ctx->locals[i * 4 + j] =
5528 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5529 }
5530 }
5531 }
5532
5533 static void
5534 setup_shared(struct ac_nir_context *ctx,
5535 struct nir_shader *nir)
5536 {
5537 nir_foreach_variable(variable, &nir->shared) {
5538 LLVMValueRef shared =
5539 LLVMAddGlobalInAddressSpace(
5540 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5541 variable->name ? variable->name : "",
5542 LOCAL_ADDR_SPACE);
5543 _mesa_hash_table_insert(ctx->vars, variable, shared);
5544 }
5545 }
5546
5547 static LLVMValueRef
5548 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5549 {
5550 v = ac_to_float(ctx, v);
5551 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5552 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5553 }
5554
5555
5556 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5557 LLVMValueRef src0, LLVMValueRef src1)
5558 {
5559 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5560 LLVMValueRef comp[2];
5561
5562 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5563 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5564 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5565 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5566 }
5567
5568 /* Initialize arguments for the shader export intrinsic */
5569 static void
5570 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5571 LLVMValueRef *values,
5572 unsigned target,
5573 struct ac_export_args *args)
5574 {
5575 /* Default is 0xf. Adjusted below depending on the format. */
5576 args->enabled_channels = 0xf;
5577
5578 /* Specify whether the EXEC mask represents the valid mask */
5579 args->valid_mask = 0;
5580
5581 /* Specify whether this is the last export */
5582 args->done = 0;
5583
5584 /* Specify the target we are exporting */
5585 args->target = target;
5586
5587 args->compr = false;
5588 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5589 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5590 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5591 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5592
5593 if (!values)
5594 return;
5595
5596 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5597 LLVMValueRef val[4];
5598 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5599 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5600 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5601 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5602
5603 switch(col_format) {
5604 case V_028714_SPI_SHADER_ZERO:
5605 args->enabled_channels = 0; /* writemask */
5606 args->target = V_008DFC_SQ_EXP_NULL;
5607 break;
5608
5609 case V_028714_SPI_SHADER_32_R:
5610 args->enabled_channels = 1;
5611 args->out[0] = values[0];
5612 break;
5613
5614 case V_028714_SPI_SHADER_32_GR:
5615 args->enabled_channels = 0x3;
5616 args->out[0] = values[0];
5617 args->out[1] = values[1];
5618 break;
5619
5620 case V_028714_SPI_SHADER_32_AR:
5621 args->enabled_channels = 0x9;
5622 args->out[0] = values[0];
5623 args->out[3] = values[3];
5624 break;
5625
5626 case V_028714_SPI_SHADER_FP16_ABGR:
5627 args->compr = 1;
5628
5629 for (unsigned chan = 0; chan < 2; chan++) {
5630 LLVMValueRef pack_args[2] = {
5631 values[2 * chan],
5632 values[2 * chan + 1]
5633 };
5634 LLVMValueRef packed;
5635
5636 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5637 args->out[chan] = packed;
5638 }
5639 break;
5640
5641 case V_028714_SPI_SHADER_UNORM16_ABGR:
5642 for (unsigned chan = 0; chan < 4; chan++) {
5643 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5644 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5645 LLVMConstReal(ctx->ac.f32, 65535), "");
5646 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5647 LLVMConstReal(ctx->ac.f32, 0.5), "");
5648 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5649 ctx->ac.i32, "");
5650 }
5651
5652 args->compr = 1;
5653 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5654 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5655 break;
5656
5657 case V_028714_SPI_SHADER_SNORM16_ABGR:
5658 for (unsigned chan = 0; chan < 4; chan++) {
5659 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5660 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5661 LLVMConstReal(ctx->ac.f32, 32767), "");
5662
5663 /* If positive, add 0.5, else add -0.5. */
5664 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5665 LLVMBuildSelect(ctx->builder,
5666 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5667 val[chan], ctx->ac.f32_0, ""),
5668 LLVMConstReal(ctx->ac.f32, 0.5),
5669 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5670 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5671 }
5672
5673 args->compr = 1;
5674 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5675 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5676 break;
5677
5678 case V_028714_SPI_SHADER_UINT16_ABGR: {
5679 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5680 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5681 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5682
5683 for (unsigned chan = 0; chan < 4; chan++) {
5684 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5685 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5686 }
5687
5688 args->compr = 1;
5689 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5690 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5691 break;
5692 }
5693
5694 case V_028714_SPI_SHADER_SINT16_ABGR: {
5695 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5696 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5697 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5698 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5699 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5700 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5701
5702 /* Clamp. */
5703 for (unsigned chan = 0; chan < 4; chan++) {
5704 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5705 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5706 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5707 }
5708
5709 args->compr = 1;
5710 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5711 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5712 break;
5713 }
5714
5715 default:
5716 case V_028714_SPI_SHADER_32_ABGR:
5717 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5718 break;
5719 }
5720 } else
5721 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5722
5723 for (unsigned i = 0; i < 4; ++i)
5724 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5725 }
5726
5727 static void
5728 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5729 bool export_prim_id,
5730 struct ac_vs_output_info *outinfo)
5731 {
5732 uint32_t param_count = 0;
5733 unsigned target;
5734 unsigned pos_idx, num_pos_exports = 0;
5735 struct ac_export_args args, pos_args[4] = {};
5736 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5737 int i;
5738
5739 if (ctx->options->key.has_multiview_view_index) {
5740 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5741 if(!*tmp_out) {
5742 for(unsigned i = 0; i < 4; ++i)
5743 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5744 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5745 }
5746
5747 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5748 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5749 }
5750
5751 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5752 sizeof(outinfo->vs_output_param_offset));
5753
5754 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5755 LLVMValueRef slots[8];
5756 unsigned j;
5757
5758 if (outinfo->cull_dist_mask)
5759 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5760
5761 i = VARYING_SLOT_CLIP_DIST0;
5762 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5763 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5764 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5765
5766 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5767 slots[i] = LLVMGetUndef(ctx->ac.f32);
5768
5769 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5770 target = V_008DFC_SQ_EXP_POS + 3;
5771 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5772 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5773 &args, sizeof(args));
5774 }
5775
5776 target = V_008DFC_SQ_EXP_POS + 2;
5777 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5778 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5779 &args, sizeof(args));
5780
5781 }
5782
5783 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5784 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5785 for (unsigned j = 0; j < 4; j++)
5786 pos_values[j] = LLVMBuildLoad(ctx->builder,
5787 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5788 }
5789 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5790
5791 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5792 outinfo->writes_pointsize = true;
5793 psize_value = LLVMBuildLoad(ctx->builder,
5794 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5795 }
5796
5797 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5798 outinfo->writes_layer = true;
5799 layer_value = LLVMBuildLoad(ctx->builder,
5800 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5801 }
5802
5803 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5804 outinfo->writes_viewport_index = true;
5805 viewport_index_value = LLVMBuildLoad(ctx->builder,
5806 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5807 }
5808
5809 if (outinfo->writes_pointsize ||
5810 outinfo->writes_layer ||
5811 outinfo->writes_viewport_index) {
5812 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5813 (outinfo->writes_layer == true ? 4 : 0));
5814 pos_args[1].valid_mask = 0;
5815 pos_args[1].done = 0;
5816 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5817 pos_args[1].compr = 0;
5818 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5819 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5820 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5821 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5822
5823 if (outinfo->writes_pointsize == true)
5824 pos_args[1].out[0] = psize_value;
5825 if (outinfo->writes_layer == true)
5826 pos_args[1].out[2] = layer_value;
5827 if (outinfo->writes_viewport_index == true) {
5828 if (ctx->options->chip_class >= GFX9) {
5829 /* GFX9 has the layer in out.z[10:0] and the viewport
5830 * index in out.z[19:16].
5831 */
5832 LLVMValueRef v = viewport_index_value;
5833 v = ac_to_integer(&ctx->ac, v);
5834 v = LLVMBuildShl(ctx->builder, v,
5835 LLVMConstInt(ctx->ac.i32, 16, false),
5836 "");
5837 v = LLVMBuildOr(ctx->builder, v,
5838 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5839
5840 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5841 pos_args[1].enabled_channels |= 1 << 2;
5842 } else {
5843 pos_args[1].out[3] = viewport_index_value;
5844 pos_args[1].enabled_channels |= 1 << 3;
5845 }
5846 }
5847 }
5848 for (i = 0; i < 4; i++) {
5849 if (pos_args[i].out[0])
5850 num_pos_exports++;
5851 }
5852
5853 pos_idx = 0;
5854 for (i = 0; i < 4; i++) {
5855 if (!pos_args[i].out[0])
5856 continue;
5857
5858 /* Specify the target we are exporting */
5859 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5860 if (pos_idx == num_pos_exports)
5861 pos_args[i].done = 1;
5862 ac_build_export(&ctx->ac, &pos_args[i]);
5863 }
5864
5865 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5866 LLVMValueRef values[4];
5867 if (!(ctx->output_mask & (1ull << i)))
5868 continue;
5869
5870 for (unsigned j = 0; j < 4; j++)
5871 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5872 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5873
5874 if (i == VARYING_SLOT_LAYER) {
5875 target = V_008DFC_SQ_EXP_PARAM + param_count;
5876 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5877 param_count++;
5878 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5879 target = V_008DFC_SQ_EXP_PARAM + param_count;
5880 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5881 param_count++;
5882 } else if (i >= VARYING_SLOT_VAR0) {
5883 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5884 target = V_008DFC_SQ_EXP_PARAM + param_count;
5885 outinfo->vs_output_param_offset[i] = param_count;
5886 param_count++;
5887 } else
5888 continue;
5889
5890 si_llvm_init_export_args(ctx, values, target, &args);
5891
5892 if (target >= V_008DFC_SQ_EXP_POS &&
5893 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5894 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5895 &args, sizeof(args));
5896 } else {
5897 ac_build_export(&ctx->ac, &args);
5898 }
5899 }
5900
5901 if (export_prim_id) {
5902 LLVMValueRef values[4];
5903 target = V_008DFC_SQ_EXP_PARAM + param_count;
5904 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5905 param_count++;
5906
5907 values[0] = ctx->vs_prim_id;
5908 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5909 ctx->shader_info->vs.vgpr_comp_cnt);
5910 for (unsigned j = 1; j < 4; j++)
5911 values[j] = ctx->ac.f32_0;
5912 si_llvm_init_export_args(ctx, values, target, &args);
5913 ac_build_export(&ctx->ac, &args);
5914 outinfo->export_prim_id = true;
5915 }
5916
5917 outinfo->pos_exports = num_pos_exports;
5918 outinfo->param_exports = param_count;
5919 }
5920
5921 static void
5922 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5923 struct ac_es_output_info *outinfo)
5924 {
5925 int j;
5926 uint64_t max_output_written = 0;
5927 LLVMValueRef lds_base = NULL;
5928
5929 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5930 int param_index;
5931 int length = 4;
5932
5933 if (!(ctx->output_mask & (1ull << i)))
5934 continue;
5935
5936 if (i == VARYING_SLOT_CLIP_DIST0)
5937 length = ctx->num_output_clips + ctx->num_output_culls;
5938
5939 param_index = shader_io_get_unique_index(i);
5940
5941 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5942 }
5943
5944 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5945
5946 if (ctx->ac.chip_class >= GFX9) {
5947 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5948 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5949 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5950 LLVMConstInt(ctx->ac.i32, 24, false),
5951 LLVMConstInt(ctx->ac.i32, 4, false), false);
5952 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5953 LLVMBuildMul(ctx->ac.builder, wave_idx,
5954 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5955 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5956 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5957 }
5958
5959 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5960 LLVMValueRef dw_addr;
5961 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5962 int param_index;
5963 int length = 4;
5964
5965 if (!(ctx->output_mask & (1ull << i)))
5966 continue;
5967
5968 if (i == VARYING_SLOT_CLIP_DIST0)
5969 length = ctx->num_output_clips + ctx->num_output_culls;
5970
5971 param_index = shader_io_get_unique_index(i);
5972
5973 if (lds_base) {
5974 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5975 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5976 "");
5977 }
5978 for (j = 0; j < length; j++) {
5979 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5980 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5981
5982 if (ctx->ac.chip_class >= GFX9) {
5983 ac_lds_store(&ctx->ac, dw_addr,
5984 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5985 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5986 } else {
5987 ac_build_buffer_store_dword(&ctx->ac,
5988 ctx->esgs_ring,
5989 out_val, 1,
5990 NULL, ctx->es2gs_offset,
5991 (4 * param_index + j) * 4,
5992 1, 1, true, true);
5993 }
5994 }
5995 }
5996 }
5997
5998 static void
5999 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6000 {
6001 LLVMValueRef vertex_id = ctx->rel_auto_id;
6002 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6003 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6004 vertex_dw_stride, "");
6005
6006 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6007 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6008 int length = 4;
6009
6010 if (!(ctx->output_mask & (1ull << i)))
6011 continue;
6012
6013 if (i == VARYING_SLOT_CLIP_DIST0)
6014 length = ctx->num_output_clips + ctx->num_output_culls;
6015 int param = shader_io_get_unique_index(i);
6016 mark_tess_output(ctx, false, param);
6017 if (length > 4)
6018 mark_tess_output(ctx, false, param + 1);
6019 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6020 LLVMConstInt(ctx->ac.i32, param * 4, false),
6021 "");
6022 for (unsigned j = 0; j < length; j++) {
6023 ac_lds_store(&ctx->ac, dw_addr,
6024 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6025 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6026 }
6027 }
6028 }
6029
6030 struct ac_build_if_state
6031 {
6032 struct nir_to_llvm_context *ctx;
6033 LLVMValueRef condition;
6034 LLVMBasicBlockRef entry_block;
6035 LLVMBasicBlockRef true_block;
6036 LLVMBasicBlockRef false_block;
6037 LLVMBasicBlockRef merge_block;
6038 };
6039
6040 static LLVMBasicBlockRef
6041 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6042 {
6043 LLVMBasicBlockRef current_block;
6044 LLVMBasicBlockRef next_block;
6045 LLVMBasicBlockRef new_block;
6046
6047 /* get current basic block */
6048 current_block = LLVMGetInsertBlock(ctx->builder);
6049
6050 /* chqeck if there's another block after this one */
6051 next_block = LLVMGetNextBasicBlock(current_block);
6052 if (next_block) {
6053 /* insert the new block before the next block */
6054 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6055 }
6056 else {
6057 /* append new block after current block */
6058 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6059 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6060 }
6061 return new_block;
6062 }
6063
6064 static void
6065 ac_nir_build_if(struct ac_build_if_state *ifthen,
6066 struct nir_to_llvm_context *ctx,
6067 LLVMValueRef condition)
6068 {
6069 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6070
6071 memset(ifthen, 0, sizeof *ifthen);
6072 ifthen->ctx = ctx;
6073 ifthen->condition = condition;
6074 ifthen->entry_block = block;
6075
6076 /* create endif/merge basic block for the phi functions */
6077 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6078
6079 /* create/insert true_block before merge_block */
6080 ifthen->true_block =
6081 LLVMInsertBasicBlockInContext(ctx->context,
6082 ifthen->merge_block,
6083 "if-true-block");
6084
6085 /* successive code goes into the true block */
6086 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6087 }
6088
6089 /**
6090 * End a conditional.
6091 */
6092 static void
6093 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6094 {
6095 LLVMBuilderRef builder = ifthen->ctx->builder;
6096
6097 /* Insert branch to the merge block from current block */
6098 LLVMBuildBr(builder, ifthen->merge_block);
6099
6100 /*
6101 * Now patch in the various branch instructions.
6102 */
6103
6104 /* Insert the conditional branch instruction at the end of entry_block */
6105 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6106 if (ifthen->false_block) {
6107 /* we have an else clause */
6108 LLVMBuildCondBr(builder, ifthen->condition,
6109 ifthen->true_block, ifthen->false_block);
6110 }
6111 else {
6112 /* no else clause */
6113 LLVMBuildCondBr(builder, ifthen->condition,
6114 ifthen->true_block, ifthen->merge_block);
6115 }
6116
6117 /* Resume building code at end of the ifthen->merge_block */
6118 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6119 }
6120
6121 static void
6122 write_tess_factors(struct nir_to_llvm_context *ctx)
6123 {
6124 unsigned stride, outer_comps, inner_comps;
6125 struct ac_build_if_state if_ctx, inner_if_ctx;
6126 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6127 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6128 unsigned tess_inner_index, tess_outer_index;
6129 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6130 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6131 int i;
6132 emit_barrier(ctx);
6133
6134 switch (ctx->options->key.tcs.primitive_mode) {
6135 case GL_ISOLINES:
6136 stride = 2;
6137 outer_comps = 2;
6138 inner_comps = 0;
6139 break;
6140 case GL_TRIANGLES:
6141 stride = 4;
6142 outer_comps = 3;
6143 inner_comps = 1;
6144 break;
6145 case GL_QUADS:
6146 stride = 6;
6147 outer_comps = 4;
6148 inner_comps = 2;
6149 break;
6150 default:
6151 return;
6152 }
6153
6154 ac_nir_build_if(&if_ctx, ctx,
6155 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6156 invocation_id, ctx->ac.i32_0, ""));
6157
6158 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6159 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6160
6161 mark_tess_output(ctx, true, tess_inner_index);
6162 mark_tess_output(ctx, true, tess_outer_index);
6163 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6164 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6165 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6166 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6167 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6168
6169 for (i = 0; i < 4; i++) {
6170 inner[i] = LLVMGetUndef(ctx->ac.i32);
6171 outer[i] = LLVMGetUndef(ctx->ac.i32);
6172 }
6173
6174 // LINES reverseal
6175 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6176 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6177 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6178 ctx->ac.i32_1, "");
6179 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6180 } else {
6181 for (i = 0; i < outer_comps; i++) {
6182 outer[i] = out[i] =
6183 ac_lds_load(&ctx->ac, lds_outer);
6184 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6185 ctx->ac.i32_1, "");
6186 }
6187 for (i = 0; i < inner_comps; i++) {
6188 inner[i] = out[outer_comps+i] =
6189 ac_lds_load(&ctx->ac, lds_inner);
6190 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6191 ctx->ac.i32_1, "");
6192 }
6193 }
6194
6195 /* Convert the outputs to vectors for stores. */
6196 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6197 vec1 = NULL;
6198
6199 if (stride > 4)
6200 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6201
6202
6203 buffer = ctx->hs_ring_tess_factor;
6204 tf_base = ctx->tess_factor_offset;
6205 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6206 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6207 unsigned tf_offset = 0;
6208
6209 if (ctx->options->chip_class <= VI) {
6210 ac_nir_build_if(&inner_if_ctx, ctx,
6211 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6212 rel_patch_id, ctx->ac.i32_0, ""));
6213
6214 /* Store the dynamic HS control word. */
6215 ac_build_buffer_store_dword(&ctx->ac, buffer,
6216 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6217 1, ctx->ac.i32_0, tf_base,
6218 0, 1, 0, true, false);
6219 tf_offset += 4;
6220
6221 ac_nir_build_endif(&inner_if_ctx);
6222 }
6223
6224 /* Store the tessellation factors. */
6225 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6226 MIN2(stride, 4), byteoffset, tf_base,
6227 tf_offset, 1, 0, true, false);
6228 if (vec1)
6229 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6230 stride - 4, byteoffset, tf_base,
6231 16 + tf_offset, 1, 0, true, false);
6232
6233 //store to offchip for TES to read - only if TES reads them
6234 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6235 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6236 LLVMValueRef tf_inner_offset;
6237 unsigned param_outer, param_inner;
6238
6239 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6240 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6241 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6242
6243 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6244 util_next_power_of_two(outer_comps));
6245
6246 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6247 outer_comps, tf_outer_offset,
6248 ctx->oc_lds, 0, 1, 0, true, false);
6249 if (inner_comps) {
6250 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6251 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6252 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6253
6254 inner_vec = inner_comps == 1 ? inner[0] :
6255 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6256 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6257 inner_comps, tf_inner_offset,
6258 ctx->oc_lds, 0, 1, 0, true, false);
6259 }
6260 }
6261 ac_nir_build_endif(&if_ctx);
6262 }
6263
6264 static void
6265 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6266 {
6267 write_tess_factors(ctx);
6268 }
6269
6270 static bool
6271 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6272 LLVMValueRef *color, unsigned param, bool is_last,
6273 struct ac_export_args *args)
6274 {
6275 /* Export */
6276 si_llvm_init_export_args(ctx, color, param,
6277 args);
6278
6279 if (is_last) {
6280 args->valid_mask = 1; /* whether the EXEC mask is valid */
6281 args->done = 1; /* DONE bit */
6282 } else if (!args->enabled_channels)
6283 return false; /* unnecessary NULL export */
6284
6285 return true;
6286 }
6287
6288 static void
6289 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6290 LLVMValueRef depth, LLVMValueRef stencil,
6291 LLVMValueRef samplemask)
6292 {
6293 struct ac_export_args args;
6294
6295 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6296
6297 ac_build_export(&ctx->ac, &args);
6298 }
6299
6300 static void
6301 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6302 {
6303 unsigned index = 0;
6304 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6305 struct ac_export_args color_args[8];
6306
6307 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6308 LLVMValueRef values[4];
6309
6310 if (!(ctx->output_mask & (1ull << i)))
6311 continue;
6312
6313 if (i == FRAG_RESULT_DEPTH) {
6314 ctx->shader_info->fs.writes_z = true;
6315 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6316 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6317 } else if (i == FRAG_RESULT_STENCIL) {
6318 ctx->shader_info->fs.writes_stencil = true;
6319 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6320 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6321 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6322 ctx->shader_info->fs.writes_sample_mask = true;
6323 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6324 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6325 } else {
6326 bool last = false;
6327 for (unsigned j = 0; j < 4; j++)
6328 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6329 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6330
6331 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6332 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6333
6334 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6335 if (ret)
6336 index++;
6337 }
6338 }
6339
6340 for (unsigned i = 0; i < index; i++)
6341 ac_build_export(&ctx->ac, &color_args[i]);
6342 if (depth || stencil || samplemask)
6343 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6344 else if (!index) {
6345 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6346 ac_build_export(&ctx->ac, &color_args[0]);
6347 }
6348
6349 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6350 }
6351
6352 static void
6353 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6354 {
6355 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6356 }
6357
6358 static void
6359 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6360 LLVMValueRef *addrs)
6361 {
6362 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6363
6364 switch (ctx->stage) {
6365 case MESA_SHADER_VERTEX:
6366 if (ctx->options->key.vs.as_ls)
6367 handle_ls_outputs_post(ctx);
6368 else if (ctx->options->key.vs.as_es)
6369 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6370 else
6371 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6372 &ctx->shader_info->vs.outinfo);
6373 break;
6374 case MESA_SHADER_FRAGMENT:
6375 handle_fs_outputs_post(ctx);
6376 break;
6377 case MESA_SHADER_GEOMETRY:
6378 emit_gs_epilogue(ctx);
6379 break;
6380 case MESA_SHADER_TESS_CTRL:
6381 handle_tcs_outputs_post(ctx);
6382 break;
6383 case MESA_SHADER_TESS_EVAL:
6384 if (ctx->options->key.tes.as_es)
6385 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6386 else
6387 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6388 &ctx->shader_info->tes.outinfo);
6389 break;
6390 default:
6391 break;
6392 }
6393 }
6394
6395 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6396 {
6397 LLVMPassManagerRef passmgr;
6398 /* Create the pass manager */
6399 passmgr = LLVMCreateFunctionPassManagerForModule(
6400 ctx->module);
6401
6402 /* This pass should eliminate all the load and store instructions */
6403 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6404
6405 /* Add some optimization passes */
6406 LLVMAddScalarReplAggregatesPass(passmgr);
6407 LLVMAddLICMPass(passmgr);
6408 LLVMAddAggressiveDCEPass(passmgr);
6409 LLVMAddCFGSimplificationPass(passmgr);
6410 LLVMAddInstructionCombiningPass(passmgr);
6411
6412 /* Run the pass */
6413 LLVMInitializeFunctionPassManager(passmgr);
6414 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6415 LLVMFinalizeFunctionPassManager(passmgr);
6416
6417 LLVMDisposeBuilder(ctx->builder);
6418 LLVMDisposePassManager(passmgr);
6419 }
6420
6421 static void
6422 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6423 {
6424 struct ac_vs_output_info *outinfo;
6425
6426 switch (ctx->stage) {
6427 case MESA_SHADER_FRAGMENT:
6428 case MESA_SHADER_COMPUTE:
6429 case MESA_SHADER_TESS_CTRL:
6430 case MESA_SHADER_GEOMETRY:
6431 return;
6432 case MESA_SHADER_VERTEX:
6433 if (ctx->options->key.vs.as_ls ||
6434 ctx->options->key.vs.as_es)
6435 return;
6436 outinfo = &ctx->shader_info->vs.outinfo;
6437 break;
6438 case MESA_SHADER_TESS_EVAL:
6439 if (ctx->options->key.vs.as_es)
6440 return;
6441 outinfo = &ctx->shader_info->tes.outinfo;
6442 break;
6443 default:
6444 unreachable("Unhandled shader type");
6445 }
6446
6447 ac_optimize_vs_outputs(&ctx->ac,
6448 ctx->main_function,
6449 outinfo->vs_output_param_offset,
6450 VARYING_SLOT_MAX,
6451 &outinfo->param_exports);
6452 }
6453
6454 static void
6455 ac_setup_rings(struct nir_to_llvm_context *ctx)
6456 {
6457 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6458 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6459 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6460 }
6461
6462 if (ctx->is_gs_copy_shader) {
6463 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6464 }
6465 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6466 LLVMValueRef tmp;
6467 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6468 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6469
6470 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6471
6472 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6473 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6474 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6475 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6476 }
6477
6478 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6479 ctx->stage == MESA_SHADER_TESS_EVAL) {
6480 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6481 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6482 }
6483 }
6484
6485 static unsigned
6486 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6487 const struct nir_shader *nir)
6488 {
6489 switch (nir->info.stage) {
6490 case MESA_SHADER_TESS_CTRL:
6491 return chip_class >= CIK ? 128 : 64;
6492 case MESA_SHADER_GEOMETRY:
6493 return chip_class >= GFX9 ? 128 : 64;
6494 case MESA_SHADER_COMPUTE:
6495 break;
6496 default:
6497 return 0;
6498 }
6499
6500 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6501 nir->info.cs.local_size[1] *
6502 nir->info.cs.local_size[2];
6503 return max_workgroup_size;
6504 }
6505
6506 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6507 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6508 {
6509 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6510 LLVMConstInt(ctx->ac.i32, 8, false),
6511 LLVMConstInt(ctx->ac.i32, 8, false), false);
6512 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6513 ctx->ac.i32_0, "");
6514 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6515 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6516 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6517 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6518 }
6519
6520 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6521 {
6522 for(int i = 5; i >= 0; --i) {
6523 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6524 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6525 LLVMConstInt(ctx->ac.i32, 16, false), false);
6526 }
6527
6528 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6529 LLVMConstInt(ctx->ac.i32, 16, false),
6530 LLVMConstInt(ctx->ac.i32, 8, false), false);
6531 }
6532
6533 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6534 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6535 {
6536 struct ac_nir_context ctx = {};
6537 struct nir_function *func;
6538
6539 ctx.ac = *ac;
6540 ctx.abi = abi;
6541
6542 ctx.nctx = nctx;
6543 if (nctx)
6544 nctx->nir = &ctx;
6545
6546 ctx.stage = nir->info.stage;
6547
6548 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6549
6550 nir_foreach_variable(variable, &nir->outputs)
6551 handle_shader_output_decl(&ctx, nir, variable);
6552
6553 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6554 _mesa_key_pointer_equal);
6555 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6556 _mesa_key_pointer_equal);
6557 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6558 _mesa_key_pointer_equal);
6559
6560 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6561
6562 setup_locals(&ctx, func);
6563
6564 if (nir->info.stage == MESA_SHADER_COMPUTE)
6565 setup_shared(&ctx, nir);
6566
6567 visit_cf_list(&ctx, &func->impl->body);
6568 phi_post_pass(&ctx);
6569
6570 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6571 ctx.outputs);
6572
6573 free(ctx.locals);
6574 ralloc_free(ctx.defs);
6575 ralloc_free(ctx.phis);
6576 ralloc_free(ctx.vars);
6577
6578 if (nctx)
6579 nctx->nir = NULL;
6580 }
6581
6582 static
6583 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6584 struct nir_shader *const *shaders,
6585 int shader_count,
6586 struct ac_shader_variant_info *shader_info,
6587 const struct ac_nir_compiler_options *options)
6588 {
6589 struct nir_to_llvm_context ctx = {0};
6590 unsigned i;
6591 ctx.options = options;
6592 ctx.shader_info = shader_info;
6593 ctx.context = LLVMContextCreate();
6594 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6595
6596 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6597 options->family);
6598 ctx.ac.module = ctx.module;
6599 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6600
6601 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6602 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6603 LLVMSetDataLayout(ctx.module, data_layout_str);
6604 LLVMDisposeTargetData(data_layout);
6605 LLVMDisposeMessage(data_layout_str);
6606
6607 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6608 ctx.ac.builder = ctx.builder;
6609
6610 memset(shader_info, 0, sizeof(*shader_info));
6611
6612 for(int i = 0; i < shader_count; ++i)
6613 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6614
6615 for (i = 0; i < AC_UD_MAX_SETS; i++)
6616 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6617 for (i = 0; i < AC_UD_MAX_UD; i++)
6618 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6619
6620 ctx.max_workgroup_size = 0;
6621 for (int i = 0; i < shader_count; ++i) {
6622 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6623 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6624 shaders[i]));
6625 }
6626
6627 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6628 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6629
6630 ctx.abi.inputs = &ctx.inputs[0];
6631 ctx.abi.emit_outputs = handle_shader_outputs_post;
6632 ctx.abi.emit_vertex = visit_emit_vertex;
6633 ctx.abi.load_ubo = radv_load_ubo;
6634 ctx.abi.load_ssbo = radv_load_ssbo;
6635 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6636 ctx.abi.clamp_shadow_reference = false;
6637
6638 if (shader_count >= 2)
6639 ac_init_exec_full_mask(&ctx.ac);
6640
6641 if (ctx.ac.chip_class == GFX9 &&
6642 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6643 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6644
6645 for(int i = 0; i < shader_count; ++i) {
6646 ctx.stage = shaders[i]->info.stage;
6647 ctx.output_mask = 0;
6648 ctx.tess_outputs_written = 0;
6649 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6650 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6651
6652 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6653 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6654 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6655 ctx.abi.load_inputs = load_gs_input;
6656 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6657 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6658 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6659 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6660 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6661 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6662 if (shader_info->info.vs.needs_instance_id) {
6663 ctx.shader_info->vs.vgpr_comp_cnt =
6664 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6665 }
6666 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6667 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6668 }
6669
6670 if (i)
6671 emit_barrier(&ctx);
6672
6673 ac_setup_rings(&ctx);
6674
6675 LLVMBasicBlockRef merge_block;
6676 if (shader_count >= 2) {
6677 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6678 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6679 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6680
6681 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6682 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6683 LLVMConstInt(ctx.ac.i32, 8, false), false);
6684 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6685 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6686 thread_id, count, "");
6687 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6688
6689 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6690 }
6691
6692 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6693 handle_fs_inputs(&ctx, shaders[i]);
6694 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6695 handle_vs_inputs(&ctx, shaders[i]);
6696 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6697 prepare_gs_input_vgprs(&ctx);
6698
6699 nir_foreach_variable(variable, &shaders[i]->outputs)
6700 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6701
6702 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6703
6704 if (shader_count >= 2) {
6705 LLVMBuildBr(ctx.ac.builder, merge_block);
6706 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6707 }
6708
6709 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6710 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6711 shaders[i]->info.cull_distance_array_size > 4;
6712 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6713 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6714 shaders[i]->info.gs.vertices_out;
6715 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6716 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6717 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6718 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6719 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6720 }
6721 }
6722
6723 LLVMBuildRetVoid(ctx.builder);
6724
6725 ac_llvm_finalize_module(&ctx);
6726
6727 if (shader_count == 1)
6728 ac_nir_eliminate_const_vs_outputs(&ctx);
6729
6730 return ctx.module;
6731 }
6732
6733 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6734 {
6735 unsigned *retval = (unsigned *)context;
6736 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6737 char *description = LLVMGetDiagInfoDescription(di);
6738
6739 if (severity == LLVMDSError) {
6740 *retval = 1;
6741 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6742 description);
6743 }
6744
6745 LLVMDisposeMessage(description);
6746 }
6747
6748 static unsigned ac_llvm_compile(LLVMModuleRef M,
6749 struct ac_shader_binary *binary,
6750 LLVMTargetMachineRef tm)
6751 {
6752 unsigned retval = 0;
6753 char *err;
6754 LLVMContextRef llvm_ctx;
6755 LLVMMemoryBufferRef out_buffer;
6756 unsigned buffer_size;
6757 const char *buffer_data;
6758 LLVMBool mem_err;
6759
6760 /* Setup Diagnostic Handler*/
6761 llvm_ctx = LLVMGetModuleContext(M);
6762
6763 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6764 &retval);
6765
6766 /* Compile IR*/
6767 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6768 &err, &out_buffer);
6769
6770 /* Process Errors/Warnings */
6771 if (mem_err) {
6772 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6773 free(err);
6774 retval = 1;
6775 goto out;
6776 }
6777
6778 /* Extract Shader Code*/
6779 buffer_size = LLVMGetBufferSize(out_buffer);
6780 buffer_data = LLVMGetBufferStart(out_buffer);
6781
6782 ac_elf_read(buffer_data, buffer_size, binary);
6783
6784 /* Clean up */
6785 LLVMDisposeMemoryBuffer(out_buffer);
6786
6787 out:
6788 return retval;
6789 }
6790
6791 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6792 LLVMModuleRef llvm_module,
6793 struct ac_shader_binary *binary,
6794 struct ac_shader_config *config,
6795 struct ac_shader_variant_info *shader_info,
6796 gl_shader_stage stage,
6797 bool dump_shader, bool supports_spill)
6798 {
6799 if (dump_shader)
6800 ac_dump_module(llvm_module);
6801
6802 memset(binary, 0, sizeof(*binary));
6803 int v = ac_llvm_compile(llvm_module, binary, tm);
6804 if (v) {
6805 fprintf(stderr, "compile failed\n");
6806 }
6807
6808 if (dump_shader)
6809 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6810
6811 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6812
6813 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6814 LLVMDisposeModule(llvm_module);
6815 LLVMContextDispose(ctx);
6816
6817 if (stage == MESA_SHADER_FRAGMENT) {
6818 shader_info->num_input_vgprs = 0;
6819 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6820 shader_info->num_input_vgprs += 2;
6821 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6822 shader_info->num_input_vgprs += 2;
6823 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6824 shader_info->num_input_vgprs += 2;
6825 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6826 shader_info->num_input_vgprs += 3;
6827 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6828 shader_info->num_input_vgprs += 2;
6829 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6830 shader_info->num_input_vgprs += 2;
6831 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6832 shader_info->num_input_vgprs += 2;
6833 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6834 shader_info->num_input_vgprs += 1;
6835 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6836 shader_info->num_input_vgprs += 1;
6837 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6838 shader_info->num_input_vgprs += 1;
6839 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6840 shader_info->num_input_vgprs += 1;
6841 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6842 shader_info->num_input_vgprs += 1;
6843 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6844 shader_info->num_input_vgprs += 1;
6845 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6846 shader_info->num_input_vgprs += 1;
6847 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6848 shader_info->num_input_vgprs += 1;
6849 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6850 shader_info->num_input_vgprs += 1;
6851 }
6852 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6853
6854 /* +3 for scratch wave offset and VCC */
6855 config->num_sgprs = MAX2(config->num_sgprs,
6856 shader_info->num_input_sgprs + 3);
6857 }
6858
6859 static void
6860 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6861 {
6862 switch (nir->info.stage) {
6863 case MESA_SHADER_COMPUTE:
6864 for (int i = 0; i < 3; ++i)
6865 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6866 break;
6867 case MESA_SHADER_FRAGMENT:
6868 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6869 break;
6870 case MESA_SHADER_GEOMETRY:
6871 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6872 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6873 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6874 shader_info->gs.invocations = nir->info.gs.invocations;
6875 break;
6876 case MESA_SHADER_TESS_EVAL:
6877 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6878 shader_info->tes.spacing = nir->info.tess.spacing;
6879 shader_info->tes.ccw = nir->info.tess.ccw;
6880 shader_info->tes.point_mode = nir->info.tess.point_mode;
6881 shader_info->tes.as_es = options->key.tes.as_es;
6882 break;
6883 case MESA_SHADER_TESS_CTRL:
6884 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6885 break;
6886 case MESA_SHADER_VERTEX:
6887 shader_info->vs.as_es = options->key.vs.as_es;
6888 shader_info->vs.as_ls = options->key.vs.as_ls;
6889 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6890 if (options->key.vs.as_ls)
6891 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6892 break;
6893 default:
6894 break;
6895 }
6896 }
6897
6898 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6899 struct ac_shader_binary *binary,
6900 struct ac_shader_config *config,
6901 struct ac_shader_variant_info *shader_info,
6902 struct nir_shader *const *nir,
6903 int nir_count,
6904 const struct ac_nir_compiler_options *options,
6905 bool dump_shader)
6906 {
6907
6908 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6909 options);
6910
6911 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6912 for (int i = 0; i < nir_count; ++i)
6913 ac_fill_shader_info(shader_info, nir[i], options);
6914 }
6915
6916 static void
6917 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6918 {
6919 LLVMValueRef args[9];
6920 args[0] = ctx->gsvs_ring;
6921 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6922 args[3] = ctx->ac.i32_0;
6923 args[4] = ctx->ac.i32_1; /* OFFEN */
6924 args[5] = ctx->ac.i32_0; /* IDXEN */
6925 args[6] = ctx->ac.i32_1; /* GLC */
6926 args[7] = ctx->ac.i32_1; /* SLC */
6927 args[8] = ctx->ac.i32_0; /* TFE */
6928
6929 int idx = 0;
6930
6931 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6932 int length = 4;
6933 int slot = idx;
6934 int slot_inc = 1;
6935 if (!(ctx->output_mask & (1ull << i)))
6936 continue;
6937
6938 if (i == VARYING_SLOT_CLIP_DIST0) {
6939 /* unpack clip and cull from a single set of slots */
6940 length = ctx->num_output_clips + ctx->num_output_culls;
6941 if (length > 4)
6942 slot_inc = 2;
6943 }
6944
6945 for (unsigned j = 0; j < length; j++) {
6946 LLVMValueRef value;
6947 args[2] = LLVMConstInt(ctx->ac.i32,
6948 (slot * 4 + j) *
6949 ctx->gs_max_out_vertices * 16 * 4, false);
6950
6951 value = ac_build_intrinsic(&ctx->ac,
6952 "llvm.SI.buffer.load.dword.i32.i32",
6953 ctx->ac.i32, args, 9,
6954 AC_FUNC_ATTR_READONLY |
6955 AC_FUNC_ATTR_LEGACY);
6956
6957 LLVMBuildStore(ctx->builder,
6958 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6959 }
6960 idx += slot_inc;
6961 }
6962 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6963 }
6964
6965 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6966 struct nir_shader *geom_shader,
6967 struct ac_shader_binary *binary,
6968 struct ac_shader_config *config,
6969 struct ac_shader_variant_info *shader_info,
6970 const struct ac_nir_compiler_options *options,
6971 bool dump_shader)
6972 {
6973 struct nir_to_llvm_context ctx = {0};
6974 ctx.context = LLVMContextCreate();
6975 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6976 ctx.options = options;
6977 ctx.shader_info = shader_info;
6978
6979 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6980 options->family);
6981 ctx.ac.module = ctx.module;
6982
6983 ctx.is_gs_copy_shader = true;
6984 LLVMSetTarget(ctx.module, "amdgcn--");
6985
6986 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6987 ctx.ac.builder = ctx.builder;
6988 ctx.stage = MESA_SHADER_VERTEX;
6989
6990 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6991
6992 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6993 ac_setup_rings(&ctx);
6994
6995 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6996 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6997
6998 struct ac_nir_context nir_ctx = {};
6999 nir_ctx.ac = ctx.ac;
7000 nir_ctx.abi = &ctx.abi;
7001
7002 nir_ctx.nctx = &ctx;
7003 ctx.nir = &nir_ctx;
7004
7005 nir_foreach_variable(variable, &geom_shader->outputs) {
7006 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7007 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7008 }
7009
7010 ac_gs_copy_shader_emit(&ctx);
7011
7012 ctx.nir = NULL;
7013
7014 LLVMBuildRetVoid(ctx.builder);
7015
7016 ac_llvm_finalize_module(&ctx);
7017
7018 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7019 MESA_SHADER_VERTEX,
7020 dump_shader, options->supports_spill);
7021 }