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radv/ac: correctly size shared memory usage.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_util.h"
26 #include "ac_binary.h"
27 #include "sid.h"
28 #include "nir/nir.h"
29 #include "../vulkan/radv_descriptor_set.h"
30 #include "util/bitscan.h"
31 #include <llvm-c/Transforms/Scalar.h>
32
33 enum radeon_llvm_calling_convention {
34 RADEON_LLVM_AMDGPU_VS = 87,
35 RADEON_LLVM_AMDGPU_GS = 88,
36 RADEON_LLVM_AMDGPU_PS = 89,
37 RADEON_LLVM_AMDGPU_CS = 90,
38 };
39
40 #define CONST_ADDR_SPACE 2
41 #define LOCAL_ADDR_SPACE 3
42
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
44 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
45
46 #define SENDMSG_GS 2
47 #define SENDMSG_GS_DONE 3
48
49 #define SENDMSG_GS_OP_NOP (0 << 4)
50 #define SENDMSG_GS_OP_CUT (1 << 4)
51 #define SENDMSG_GS_OP_EMIT (2 << 4)
52 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
53
54 enum desc_type {
55 DESC_IMAGE,
56 DESC_FMASK,
57 DESC_SAMPLER,
58 DESC_BUFFER,
59 };
60
61 struct nir_to_llvm_context {
62 struct ac_llvm_context ac;
63 const struct ac_nir_compiler_options *options;
64 struct ac_shader_variant_info *shader_info;
65
66 LLVMContextRef context;
67 LLVMModuleRef module;
68 LLVMBuilderRef builder;
69 LLVMValueRef main_function;
70
71 struct hash_table *defs;
72 struct hash_table *phis;
73
74 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
75 LLVMValueRef ring_offsets;
76 LLVMValueRef push_constants;
77 LLVMValueRef num_work_groups;
78 LLVMValueRef workgroup_ids;
79 LLVMValueRef local_invocation_ids;
80 LLVMValueRef tg_size;
81
82 LLVMValueRef vertex_buffers;
83 LLVMValueRef base_vertex;
84 LLVMValueRef start_instance;
85 LLVMValueRef draw_index;
86 LLVMValueRef vertex_id;
87 LLVMValueRef rel_auto_id;
88 LLVMValueRef vs_prim_id;
89 LLVMValueRef instance_id;
90
91 LLVMValueRef es2gs_offset;
92
93 LLVMValueRef gsvs_ring_stride;
94 LLVMValueRef gsvs_num_entries;
95 LLVMValueRef gs2vs_offset;
96 LLVMValueRef gs_wave_id;
97 LLVMValueRef gs_vtx_offset[6];
98 LLVMValueRef gs_prim_id, gs_invocation_id;
99
100 LLVMValueRef esgs_ring;
101 LLVMValueRef gsvs_ring;
102
103 LLVMValueRef prim_mask;
104 LLVMValueRef sample_positions;
105 LLVMValueRef persp_sample, persp_center, persp_centroid;
106 LLVMValueRef linear_sample, linear_center, linear_centroid;
107 LLVMValueRef front_face;
108 LLVMValueRef ancillary;
109 LLVMValueRef frag_pos[4];
110
111 LLVMBasicBlockRef continue_block;
112 LLVMBasicBlockRef break_block;
113
114 LLVMTypeRef i1;
115 LLVMTypeRef i8;
116 LLVMTypeRef i16;
117 LLVMTypeRef i32;
118 LLVMTypeRef i64;
119 LLVMTypeRef v2i32;
120 LLVMTypeRef v3i32;
121 LLVMTypeRef v4i32;
122 LLVMTypeRef v8i32;
123 LLVMTypeRef f64;
124 LLVMTypeRef f32;
125 LLVMTypeRef f16;
126 LLVMTypeRef v2f32;
127 LLVMTypeRef v4f32;
128 LLVMTypeRef v16i8;
129 LLVMTypeRef voidt;
130
131 LLVMValueRef i32zero;
132 LLVMValueRef i32one;
133 LLVMValueRef f32zero;
134 LLVMValueRef f32one;
135 LLVMValueRef v4f32empty;
136
137 unsigned uniform_md_kind;
138 LLVMValueRef empty_md;
139 gl_shader_stage stage;
140
141 LLVMValueRef lds;
142 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
143 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
144
145 LLVMValueRef shared_memory;
146 uint64_t input_mask;
147 uint64_t output_mask;
148 int num_locals;
149 LLVMValueRef *locals;
150 bool has_ddxy;
151 unsigned num_clips;
152 unsigned num_culls;
153
154 bool has_ds_bpermute;
155
156 bool is_gs_copy_shader;
157 LLVMValueRef gs_next_vertex;
158 unsigned gs_max_out_vertices;
159 };
160
161 struct ac_tex_info {
162 LLVMValueRef args[12];
163 int arg_count;
164 LLVMTypeRef dst_type;
165 bool has_offset;
166 };
167
168 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
169 nir_deref_var *deref,
170 enum desc_type desc_type);
171 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
172 {
173 return (index * 4) + chan;
174 }
175
176 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
177 {
178 if (slot == VARYING_SLOT_POS)
179 return 0;
180 if (slot == VARYING_SLOT_PSIZ)
181 return 1;
182 if (slot == VARYING_SLOT_CLIP_DIST0)
183 return 2;
184 if (slot == VARYING_SLOT_CLIP_DIST1)
185 return 3;
186 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
187 return 4 + (slot - VARYING_SLOT_VAR0);
188 unreachable("illegal slot in get unique index\n");
189 }
190
191 static unsigned llvm_get_type_size(LLVMTypeRef type)
192 {
193 LLVMTypeKind kind = LLVMGetTypeKind(type);
194
195 switch (kind) {
196 case LLVMIntegerTypeKind:
197 return LLVMGetIntTypeWidth(type) / 8;
198 case LLVMFloatTypeKind:
199 return 4;
200 case LLVMPointerTypeKind:
201 return 8;
202 case LLVMVectorTypeKind:
203 return LLVMGetVectorSize(type) *
204 llvm_get_type_size(LLVMGetElementType(type));
205 default:
206 assert(0);
207 return 0;
208 }
209 }
210
211 static void set_llvm_calling_convention(LLVMValueRef func,
212 gl_shader_stage stage)
213 {
214 enum radeon_llvm_calling_convention calling_conv;
215
216 switch (stage) {
217 case MESA_SHADER_VERTEX:
218 case MESA_SHADER_TESS_CTRL:
219 case MESA_SHADER_TESS_EVAL:
220 calling_conv = RADEON_LLVM_AMDGPU_VS;
221 break;
222 case MESA_SHADER_GEOMETRY:
223 calling_conv = RADEON_LLVM_AMDGPU_GS;
224 break;
225 case MESA_SHADER_FRAGMENT:
226 calling_conv = RADEON_LLVM_AMDGPU_PS;
227 break;
228 case MESA_SHADER_COMPUTE:
229 calling_conv = RADEON_LLVM_AMDGPU_CS;
230 break;
231 default:
232 unreachable("Unhandle shader type");
233 }
234
235 LLVMSetFunctionCallConv(func, calling_conv);
236 }
237
238 static LLVMValueRef
239 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
240 LLVMBuilderRef builder, LLVMTypeRef *return_types,
241 unsigned num_return_elems, LLVMTypeRef *param_types,
242 unsigned param_count, unsigned array_params_mask,
243 unsigned sgpr_params, bool unsafe_math)
244 {
245 LLVMTypeRef main_function_type, ret_type;
246 LLVMBasicBlockRef main_function_body;
247
248 if (num_return_elems)
249 ret_type = LLVMStructTypeInContext(ctx, return_types,
250 num_return_elems, true);
251 else
252 ret_type = LLVMVoidTypeInContext(ctx);
253
254 /* Setup the function */
255 main_function_type =
256 LLVMFunctionType(ret_type, param_types, param_count, 0);
257 LLVMValueRef main_function =
258 LLVMAddFunction(module, "main", main_function_type);
259 main_function_body =
260 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
261 LLVMPositionBuilderAtEnd(builder, main_function_body);
262
263 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
264 for (unsigned i = 0; i < sgpr_params; ++i) {
265 if (array_params_mask & (1 << i)) {
266 LLVMValueRef P = LLVMGetParam(main_function, i);
267 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
268 ac_add_attr_dereferenceable(P, UINT64_MAX);
269 }
270 else {
271 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
272 }
273 }
274
275 if (unsafe_math) {
276 /* These were copied from some LLVM test. */
277 LLVMAddTargetDependentFunctionAttr(main_function,
278 "less-precise-fpmad",
279 "true");
280 LLVMAddTargetDependentFunctionAttr(main_function,
281 "no-infs-fp-math",
282 "true");
283 LLVMAddTargetDependentFunctionAttr(main_function,
284 "no-nans-fp-math",
285 "true");
286 LLVMAddTargetDependentFunctionAttr(main_function,
287 "unsafe-fp-math",
288 "true");
289 }
290 return main_function;
291 }
292
293 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
294 {
295 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
296 CONST_ADDR_SPACE);
297 }
298
299 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
300 int idx,
301 LLVMTypeRef type)
302 {
303 LLVMValueRef offset;
304 LLVMValueRef ptr;
305 int addr_space;
306
307 offset = LLVMConstInt(ctx->i32, idx, false);
308
309 ptr = ctx->shared_memory;
310 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
311 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
312 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
313 return ptr;
314 }
315
316 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
317 {
318 if (t == ctx->f16 || t == ctx->i16)
319 return ctx->i16;
320 else if (t == ctx->f32 || t == ctx->i32)
321 return ctx->i32;
322 else if (t == ctx->f64 || t == ctx->i64)
323 return ctx->i64;
324 else
325 unreachable("Unhandled integer size");
326 }
327
328 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
329 {
330 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
331 LLVMTypeRef elem_type = LLVMGetElementType(t);
332 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
333 LLVMGetVectorSize(t));
334 }
335 return to_integer_type_scalar(ctx, t);
336 }
337
338 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
339 {
340 LLVMTypeRef type = LLVMTypeOf(v);
341 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
342 }
343
344 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
345 {
346 if (t == ctx->i16 || t == ctx->f16)
347 return ctx->f16;
348 else if (t == ctx->i32 || t == ctx->f32)
349 return ctx->f32;
350 else if (t == ctx->i64 || t == ctx->f64)
351 return ctx->f64;
352 else
353 unreachable("Unhandled float size");
354 }
355
356 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
357 {
358 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
359 LLVMTypeRef elem_type = LLVMGetElementType(t);
360 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
361 LLVMGetVectorSize(t));
362 }
363 return to_float_type_scalar(ctx, t);
364 }
365
366 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
367 {
368 LLVMTypeRef type = LLVMTypeOf(v);
369 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
370 }
371
372 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
373 {
374 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
375 type = LLVMGetElementType(type);
376
377 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
378 return LLVMGetIntTypeWidth(type);
379
380 if (type == ctx->f16)
381 return 16;
382 if (type == ctx->f32)
383 return 32;
384 if (type == ctx->f64)
385 return 64;
386
387 unreachable("Unhandled type kind in get_elem_bits");
388 }
389
390 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
391 LLVMValueRef param, unsigned rshift,
392 unsigned bitwidth)
393 {
394 LLVMValueRef value = param;
395 if (rshift)
396 value = LLVMBuildLShr(ctx->builder, value,
397 LLVMConstInt(ctx->i32, rshift, false), "");
398
399 if (rshift + bitwidth < 32) {
400 unsigned mask = (1 << bitwidth) - 1;
401 value = LLVMBuildAnd(ctx->builder, value,
402 LLVMConstInt(ctx->i32, mask, false), "");
403 }
404 return value;
405 }
406
407 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
408 {
409 ud_info->sgpr_idx = sgpr_idx;
410 ud_info->num_sgprs = num_sgprs;
411 ud_info->indirect = false;
412 ud_info->indirect_offset = 0;
413 }
414
415 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
416 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
417 {
418 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
419 }
420
421 #if 0
422 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
423 uint32_t indirect_offset)
424 {
425 ud_info->sgpr_idx = sgpr_idx;
426 ud_info->num_sgprs = num_sgprs;
427 ud_info->indirect = true;
428 ud_info->indirect_offset = indirect_offset;
429 }
430 #endif
431
432 static void create_function(struct nir_to_llvm_context *ctx)
433 {
434 LLVMTypeRef arg_types[23];
435 unsigned arg_idx = 0;
436 unsigned array_params_mask = 0;
437 unsigned sgpr_count = 0, user_sgpr_count;
438 unsigned i;
439 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
440 unsigned user_sgpr_idx;
441 bool need_push_constants;
442 bool need_ring_offsets = false;
443
444 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
445 if (ctx->stage == MESA_SHADER_GEOMETRY ||
446 ctx->stage == MESA_SHADER_VERTEX ||
447 ctx->is_gs_copy_shader)
448 need_ring_offsets = true;
449
450 need_push_constants = true;
451 if (!ctx->options->layout)
452 need_push_constants = false;
453 else if (!ctx->options->layout->push_constant_size &&
454 !ctx->options->layout->dynamic_offset_count)
455 need_push_constants = false;
456
457 if (need_ring_offsets && !ctx->options->supports_spill) {
458 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
459 }
460
461 /* 1 for each descriptor set */
462 for (unsigned i = 0; i < num_sets; ++i) {
463 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
464 array_params_mask |= (1 << arg_idx);
465 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
466 }
467 }
468
469 if (need_push_constants) {
470 /* 1 for push constants and dynamic descriptors */
471 array_params_mask |= (1 << arg_idx);
472 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
473 }
474
475 switch (ctx->stage) {
476 case MESA_SHADER_COMPUTE:
477 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
478 user_sgpr_count = arg_idx;
479 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
480 arg_types[arg_idx++] = ctx->i32;
481 sgpr_count = arg_idx;
482
483 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
484 break;
485 case MESA_SHADER_VERTEX:
486 if (!ctx->is_gs_copy_shader) {
487 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
488 arg_types[arg_idx++] = ctx->i32; // base vertex
489 arg_types[arg_idx++] = ctx->i32; // start instance
490 arg_types[arg_idx++] = ctx->i32; // draw index
491 }
492 user_sgpr_count = arg_idx;
493 if (ctx->options->key.vs.as_es)
494 arg_types[arg_idx++] = ctx->i32; //es2gs offset
495 sgpr_count = arg_idx;
496 arg_types[arg_idx++] = ctx->i32; // vertex id
497 if (!ctx->is_gs_copy_shader) {
498 arg_types[arg_idx++] = ctx->i32; // rel auto id
499 arg_types[arg_idx++] = ctx->i32; // vs prim id
500 arg_types[arg_idx++] = ctx->i32; // instance id
501 }
502 break;
503 case MESA_SHADER_GEOMETRY:
504 arg_types[arg_idx++] = ctx->i32; // gsvs stride
505 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
506 user_sgpr_count = arg_idx;
507 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
508 arg_types[arg_idx++] = ctx->i32; // wave id
509 sgpr_count = arg_idx;
510 arg_types[arg_idx++] = ctx->i32; // vtx0
511 arg_types[arg_idx++] = ctx->i32; // vtx1
512 arg_types[arg_idx++] = ctx->i32; // prim id
513 arg_types[arg_idx++] = ctx->i32; // vtx2
514 arg_types[arg_idx++] = ctx->i32; // vtx3
515 arg_types[arg_idx++] = ctx->i32; // vtx4
516 arg_types[arg_idx++] = ctx->i32; // vtx5
517 arg_types[arg_idx++] = ctx->i32; // GS instance id
518 break;
519 case MESA_SHADER_FRAGMENT:
520 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
521 user_sgpr_count = arg_idx;
522 arg_types[arg_idx++] = ctx->i32; /* prim mask */
523 sgpr_count = arg_idx;
524 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
525 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
526 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
527 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
528 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
529 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
530 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
531 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
532 arg_types[arg_idx++] = ctx->f32; /* pos x float */
533 arg_types[arg_idx++] = ctx->f32; /* pos y float */
534 arg_types[arg_idx++] = ctx->f32; /* pos z float */
535 arg_types[arg_idx++] = ctx->f32; /* pos w float */
536 arg_types[arg_idx++] = ctx->i32; /* front face */
537 arg_types[arg_idx++] = ctx->i32; /* ancillary */
538 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
539 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
540 break;
541 default:
542 unreachable("Shader stage not implemented");
543 }
544
545 ctx->main_function = create_llvm_function(
546 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
547 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
548 set_llvm_calling_convention(ctx->main_function, ctx->stage);
549
550 ctx->shader_info->num_input_sgprs = 0;
551 ctx->shader_info->num_input_vgprs = 0;
552
553 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
554 for (i = 0; i < user_sgpr_count; i++)
555 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
556
557 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
558 for (; i < sgpr_count; i++)
559 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
560
561 if (ctx->stage != MESA_SHADER_FRAGMENT)
562 for (; i < arg_idx; ++i)
563 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
564
565 arg_idx = 0;
566 user_sgpr_idx = 0;
567
568 if (ctx->options->supports_spill || need_ring_offsets) {
569 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
570 user_sgpr_idx += 2;
571 if (ctx->options->supports_spill) {
572 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
573 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
574 NULL, 0, AC_FUNC_ATTR_READNONE);
575 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
576 const_array(ctx->v16i8, 8), "");
577 } else
578 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
579 }
580
581 for (unsigned i = 0; i < num_sets; ++i) {
582 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
583 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
584 user_sgpr_idx += 2;
585 ctx->descriptor_sets[i] =
586 LLVMGetParam(ctx->main_function, arg_idx++);
587 } else
588 ctx->descriptor_sets[i] = NULL;
589 }
590
591 if (need_push_constants) {
592 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
593 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
594 user_sgpr_idx += 2;
595 }
596
597 switch (ctx->stage) {
598 case MESA_SHADER_COMPUTE:
599 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
600 user_sgpr_idx += 3;
601 ctx->num_work_groups =
602 LLVMGetParam(ctx->main_function, arg_idx++);
603 ctx->workgroup_ids =
604 LLVMGetParam(ctx->main_function, arg_idx++);
605 ctx->tg_size =
606 LLVMGetParam(ctx->main_function, arg_idx++);
607 ctx->local_invocation_ids =
608 LLVMGetParam(ctx->main_function, arg_idx++);
609 break;
610 case MESA_SHADER_VERTEX:
611 if (!ctx->is_gs_copy_shader) {
612 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
613 user_sgpr_idx += 2;
614 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
615 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
616 user_sgpr_idx += 3;
617 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
618 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
619 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
620 }
621 if (ctx->options->key.vs.as_es)
622 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
623 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
624 if (!ctx->is_gs_copy_shader) {
625 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
626 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
627 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
628 }
629 break;
630 case MESA_SHADER_GEOMETRY:
631 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
632 user_sgpr_idx += 2;
633 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
635 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
636 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
638 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
639 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
640 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
641 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
642 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
643 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
644 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
645 break;
646 case MESA_SHADER_FRAGMENT:
647 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
648 user_sgpr_idx += 2;
649 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
651 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
652 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
653 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
654 arg_idx++;
655 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
656 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
657 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
658 arg_idx++; /* line stipple */
659 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
660 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
661 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
662 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
663 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
664 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
665 break;
666 default:
667 unreachable("Shader stage not implemented");
668 }
669 }
670
671 static void setup_types(struct nir_to_llvm_context *ctx)
672 {
673 LLVMValueRef args[4];
674
675 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
676 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
677 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
678 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
679 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
680 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
681 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
682 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
683 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
684 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
685 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
686 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
687 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
688 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
689 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
690 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
691
692 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
693 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
694 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
695 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
696
697 args[0] = ctx->f32zero;
698 args[1] = ctx->f32zero;
699 args[2] = ctx->f32zero;
700 args[3] = ctx->f32one;
701 ctx->v4f32empty = LLVMConstVector(args, 4);
702
703 ctx->uniform_md_kind =
704 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
705 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
706
707 args[0] = LLVMConstReal(ctx->f32, 2.5);
708 }
709
710 static int get_llvm_num_components(LLVMValueRef value)
711 {
712 LLVMTypeRef type = LLVMTypeOf(value);
713 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
714 ? LLVMGetVectorSize(type)
715 : 1;
716 return num_components;
717 }
718
719 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
720 LLVMValueRef value,
721 int index)
722 {
723 int count = get_llvm_num_components(value);
724
725 assert(index < count);
726 if (count == 1)
727 return value;
728
729 return LLVMBuildExtractElement(ctx->builder, value,
730 LLVMConstInt(ctx->i32, index, false), "");
731 }
732
733 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
734 LLVMValueRef value, unsigned count)
735 {
736 unsigned num_components = get_llvm_num_components(value);
737 if (count == num_components)
738 return value;
739
740 LLVMValueRef masks[] = {
741 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
742 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
743
744 if (count == 1)
745 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
746 "");
747
748 LLVMValueRef swizzle = LLVMConstVector(masks, count);
749 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
750 }
751
752 static void
753 build_store_values_extended(struct nir_to_llvm_context *ctx,
754 LLVMValueRef *values,
755 unsigned value_count,
756 unsigned value_stride,
757 LLVMValueRef vec)
758 {
759 LLVMBuilderRef builder = ctx->builder;
760 unsigned i;
761
762 if (value_count == 1) {
763 LLVMBuildStore(builder, vec, values[0]);
764 return;
765 }
766
767 for (i = 0; i < value_count; i++) {
768 LLVMValueRef ptr = values[i * value_stride];
769 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
770 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
771 LLVMBuildStore(builder, value, ptr);
772 }
773 }
774
775 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
776 nir_ssa_def *def)
777 {
778 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
779 if (def->num_components > 1) {
780 type = LLVMVectorType(type, def->num_components);
781 }
782 return type;
783 }
784
785 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
786 {
787 assert(src.is_ssa);
788 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
789 return (LLVMValueRef)entry->data;
790 }
791
792
793 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
794 struct nir_block *b)
795 {
796 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
797 return (LLVMBasicBlockRef)entry->data;
798 }
799
800 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
801 nir_alu_src src,
802 unsigned num_components)
803 {
804 LLVMValueRef value = get_src(ctx, src.src);
805 bool need_swizzle = false;
806
807 assert(value);
808 LLVMTypeRef type = LLVMTypeOf(value);
809 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
810 ? LLVMGetVectorSize(type)
811 : 1;
812
813 for (unsigned i = 0; i < num_components; ++i) {
814 assert(src.swizzle[i] < src_components);
815 if (src.swizzle[i] != i)
816 need_swizzle = true;
817 }
818
819 if (need_swizzle || num_components != src_components) {
820 LLVMValueRef masks[] = {
821 LLVMConstInt(ctx->i32, src.swizzle[0], false),
822 LLVMConstInt(ctx->i32, src.swizzle[1], false),
823 LLVMConstInt(ctx->i32, src.swizzle[2], false),
824 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
825
826 if (src_components > 1 && num_components == 1) {
827 value = LLVMBuildExtractElement(ctx->builder, value,
828 masks[0], "");
829 } else if (src_components == 1 && num_components > 1) {
830 LLVMValueRef values[] = {value, value, value, value};
831 value = ac_build_gather_values(&ctx->ac, values, num_components);
832 } else {
833 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
834 value = LLVMBuildShuffleVector(ctx->builder, value, value,
835 swizzle, "");
836 }
837 }
838 assert(!src.negate);
839 assert(!src.abs);
840 return value;
841 }
842
843 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
844 LLVMIntPredicate pred, LLVMValueRef src0,
845 LLVMValueRef src1)
846 {
847 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
848 return LLVMBuildSelect(ctx->builder, result,
849 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
850 LLVMConstInt(ctx->i32, 0, false), "");
851 }
852
853 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
854 LLVMRealPredicate pred, LLVMValueRef src0,
855 LLVMValueRef src1)
856 {
857 LLVMValueRef result;
858 src0 = to_float(ctx, src0);
859 src1 = to_float(ctx, src1);
860 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
861 return LLVMBuildSelect(ctx->builder, result,
862 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
863 LLVMConstInt(ctx->i32, 0, false), "");
864 }
865
866 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
867 const char *intrin,
868 LLVMTypeRef result_type,
869 LLVMValueRef src0)
870 {
871 char name[64];
872 LLVMValueRef params[] = {
873 to_float(ctx, src0),
874 };
875
876 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
877 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
878 }
879
880 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
881 const char *intrin,
882 LLVMTypeRef result_type,
883 LLVMValueRef src0, LLVMValueRef src1)
884 {
885 char name[64];
886 LLVMValueRef params[] = {
887 to_float(ctx, src0),
888 to_float(ctx, src1),
889 };
890
891 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
892 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
893 }
894
895 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
896 const char *intrin,
897 LLVMTypeRef result_type,
898 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
899 {
900 char name[64];
901 LLVMValueRef params[] = {
902 to_float(ctx, src0),
903 to_float(ctx, src1),
904 to_float(ctx, src2),
905 };
906
907 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
908 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
909 }
910
911 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
912 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
913 {
914 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
915 ctx->i32zero, "");
916 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
917 }
918
919 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
920 LLVMValueRef src0)
921 {
922 LLVMValueRef params[2] = {
923 src0,
924
925 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
926 * add special code to check for x=0. The reason is that
927 * the LLVM behavior for x=0 is different from what we
928 * need here.
929 *
930 * The hardware already implements the correct behavior.
931 */
932 LLVMConstInt(ctx->i32, 1, false),
933 };
934 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
935 }
936
937 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
938 LLVMValueRef src0)
939 {
940 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.flbit.i32",
941 ctx->i32, &src0, 1,
942 AC_FUNC_ATTR_READNONE);
943
944 /* The HW returns the last bit index from MSB, but NIR wants
945 * the index from LSB. Invert it by doing "31 - msb". */
946 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
947 msb, "");
948
949 LLVMValueRef all_ones = LLVMConstInt(ctx->i32, -1, true);
950 LLVMValueRef cond = LLVMBuildOr(ctx->builder,
951 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
952 src0, ctx->i32zero, ""),
953 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
954 src0, all_ones, ""), "");
955
956 return LLVMBuildSelect(ctx->builder, cond, all_ones, msb, "");
957 }
958
959 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
960 LLVMValueRef src0)
961 {
962 LLVMValueRef args[2] = {
963 src0,
964 ctx->i32one,
965 };
966 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctlz.i32",
967 ctx->i32, args, ARRAY_SIZE(args),
968 AC_FUNC_ATTR_READNONE);
969
970 /* The HW returns the last bit index from MSB, but NIR wants
971 * the index from LSB. Invert it by doing "31 - msb". */
972 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
973 msb, "");
974
975 return LLVMBuildSelect(ctx->builder,
976 LLVMBuildICmp(ctx->builder, LLVMIntEQ, src0,
977 ctx->i32zero, ""),
978 LLVMConstInt(ctx->i32, -1, true), msb, "");
979 }
980
981 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
982 LLVMIntPredicate pred,
983 LLVMValueRef src0, LLVMValueRef src1)
984 {
985 return LLVMBuildSelect(ctx->builder,
986 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
987 src0,
988 src1, "");
989
990 }
991 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
992 LLVMValueRef src0)
993 {
994 return emit_minmax_int(ctx, LLVMIntSGT, src0,
995 LLVMBuildNeg(ctx->builder, src0, ""));
996 }
997
998 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
999 LLVMValueRef src0)
1000 {
1001 LLVMValueRef cmp, val;
1002
1003 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1004 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1005 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1006 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1007 return val;
1008 }
1009
1010 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1011 LLVMValueRef src0)
1012 {
1013 LLVMValueRef cmp, val;
1014
1015 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1016 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1017 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1018 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1019 return val;
1020 }
1021
1022 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1023 LLVMValueRef src0)
1024 {
1025 const char *intr = "llvm.floor.f32";
1026 LLVMValueRef fsrc0 = to_float(ctx, src0);
1027 LLVMValueRef params[] = {
1028 fsrc0,
1029 };
1030 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
1031 ctx->f32, params, 1,
1032 AC_FUNC_ATTR_READNONE);
1033 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1034 }
1035
1036 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1037 const char *intrin,
1038 LLVMValueRef src0, LLVMValueRef src1)
1039 {
1040 LLVMTypeRef ret_type;
1041 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1042 LLVMValueRef res;
1043 LLVMValueRef params[] = { src0, src1 };
1044 ret_type = LLVMStructTypeInContext(ctx->context, types,
1045 2, true);
1046
1047 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1048 params, 2, AC_FUNC_ATTR_READNONE);
1049
1050 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1051 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1052 return res;
1053 }
1054
1055 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1056 LLVMValueRef src0)
1057 {
1058 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1059 }
1060
1061 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1062 LLVMValueRef src0, LLVMValueRef src1)
1063 {
1064 LLVMValueRef dst64, result;
1065 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1066 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1067
1068 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1069 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1070 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1071 return result;
1072 }
1073
1074 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1075 LLVMValueRef src0, LLVMValueRef src1)
1076 {
1077 LLVMValueRef dst64, result;
1078 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1079 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1080
1081 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1082 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1083 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1084 return result;
1085 }
1086
1087 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1088 const char *intrin,
1089 LLVMValueRef srcs[3])
1090 {
1091 LLVMValueRef result;
1092 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1093 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1094
1095 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1096 return result;
1097 }
1098
1099 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1100 LLVMValueRef src0, LLVMValueRef src1,
1101 LLVMValueRef src2, LLVMValueRef src3)
1102 {
1103 LLVMValueRef bfi_args[3], result;
1104
1105 bfi_args[0] = LLVMBuildShl(ctx->builder,
1106 LLVMBuildSub(ctx->builder,
1107 LLVMBuildShl(ctx->builder,
1108 ctx->i32one,
1109 src3, ""),
1110 ctx->i32one, ""),
1111 src2, "");
1112 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1113 bfi_args[2] = src0;
1114
1115 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1116
1117 /* Calculate:
1118 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1119 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1120 */
1121 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1122 LLVMBuildAnd(ctx->builder, bfi_args[0],
1123 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1124
1125 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1126 return result;
1127 }
1128
1129 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1130 LLVMValueRef src0)
1131 {
1132 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1133 int i;
1134 LLVMValueRef comp[2];
1135
1136 src0 = to_float(ctx, src0);
1137 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1138 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1139 for (i = 0; i < 2; i++) {
1140 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1141 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1142 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1143 }
1144
1145 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1146 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1147
1148 return comp[0];
1149 }
1150
1151 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1152 LLVMValueRef src0)
1153 {
1154 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1155 LLVMValueRef temps[2], result, val;
1156 int i;
1157
1158 for (i = 0; i < 2; i++) {
1159 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1160 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1161 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1162 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1163 }
1164
1165 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1166 ctx->i32zero, "");
1167 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1168 ctx->i32one, "");
1169 return result;
1170 }
1171
1172 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1173 nir_op op,
1174 LLVMValueRef src0)
1175 {
1176 unsigned mask;
1177 int idx;
1178 LLVMValueRef result;
1179 ctx->has_ddxy = true;
1180
1181 if (!ctx->lds && !ctx->has_ds_bpermute)
1182 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1183 LLVMArrayType(ctx->i32, 64),
1184 "ddxy_lds", LOCAL_ADDR_SPACE);
1185
1186 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1187 mask = AC_TID_MASK_LEFT;
1188 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1189 mask = AC_TID_MASK_TOP;
1190 else
1191 mask = AC_TID_MASK_TOP_LEFT;
1192
1193 /* for DDX we want to next X pixel, DDY next Y pixel. */
1194 if (op == nir_op_fddx_fine ||
1195 op == nir_op_fddx_coarse ||
1196 op == nir_op_fddx)
1197 idx = 1;
1198 else
1199 idx = 2;
1200
1201 result = ac_emit_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1202 mask, idx, ctx->lds,
1203 src0);
1204 return result;
1205 }
1206
1207 /*
1208 * this takes an I,J coordinate pair,
1209 * and works out the X and Y derivatives.
1210 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1211 */
1212 static LLVMValueRef emit_ddxy_interp(
1213 struct nir_to_llvm_context *ctx,
1214 LLVMValueRef interp_ij)
1215 {
1216 LLVMValueRef result[4], a;
1217 unsigned i;
1218
1219 for (i = 0; i < 2; i++) {
1220 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1221 LLVMConstInt(ctx->i32, i, false), "");
1222 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1223 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1224 }
1225 return ac_build_gather_values(&ctx->ac, result, 4);
1226 }
1227
1228 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1229 {
1230 LLVMValueRef src[4], result = NULL;
1231 unsigned num_components = instr->dest.dest.ssa.num_components;
1232 unsigned src_components;
1233 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1234
1235 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1236 switch (instr->op) {
1237 case nir_op_vec2:
1238 case nir_op_vec3:
1239 case nir_op_vec4:
1240 src_components = 1;
1241 break;
1242 case nir_op_pack_half_2x16:
1243 src_components = 2;
1244 break;
1245 case nir_op_unpack_half_2x16:
1246 src_components = 1;
1247 break;
1248 default:
1249 src_components = num_components;
1250 break;
1251 }
1252 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1253 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1254
1255 switch (instr->op) {
1256 case nir_op_fmov:
1257 case nir_op_imov:
1258 result = src[0];
1259 break;
1260 case nir_op_fneg:
1261 src[0] = to_float(ctx, src[0]);
1262 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1263 break;
1264 case nir_op_ineg:
1265 result = LLVMBuildNeg(ctx->builder, src[0], "");
1266 break;
1267 case nir_op_inot:
1268 result = LLVMBuildNot(ctx->builder, src[0], "");
1269 break;
1270 case nir_op_iadd:
1271 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1272 break;
1273 case nir_op_fadd:
1274 src[0] = to_float(ctx, src[0]);
1275 src[1] = to_float(ctx, src[1]);
1276 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1277 break;
1278 case nir_op_fsub:
1279 src[0] = to_float(ctx, src[0]);
1280 src[1] = to_float(ctx, src[1]);
1281 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1282 break;
1283 case nir_op_isub:
1284 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1285 break;
1286 case nir_op_imul:
1287 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1288 break;
1289 case nir_op_imod:
1290 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1291 break;
1292 case nir_op_umod:
1293 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1294 break;
1295 case nir_op_fmod:
1296 src[0] = to_float(ctx, src[0]);
1297 src[1] = to_float(ctx, src[1]);
1298 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1299 result = emit_intrin_1f_param(ctx, "llvm.floor",
1300 to_float_type(ctx, def_type), result);
1301 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1302 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1303 break;
1304 case nir_op_frem:
1305 src[0] = to_float(ctx, src[0]);
1306 src[1] = to_float(ctx, src[1]);
1307 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1308 break;
1309 case nir_op_irem:
1310 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1311 break;
1312 case nir_op_idiv:
1313 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1314 break;
1315 case nir_op_udiv:
1316 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1317 break;
1318 case nir_op_fmul:
1319 src[0] = to_float(ctx, src[0]);
1320 src[1] = to_float(ctx, src[1]);
1321 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1322 break;
1323 case nir_op_fdiv:
1324 src[0] = to_float(ctx, src[0]);
1325 src[1] = to_float(ctx, src[1]);
1326 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1327 break;
1328 case nir_op_frcp:
1329 src[0] = to_float(ctx, src[0]);
1330 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1331 break;
1332 case nir_op_iand:
1333 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1334 break;
1335 case nir_op_ior:
1336 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1337 break;
1338 case nir_op_ixor:
1339 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1340 break;
1341 case nir_op_ishl:
1342 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1343 break;
1344 case nir_op_ishr:
1345 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1346 break;
1347 case nir_op_ushr:
1348 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1349 break;
1350 case nir_op_ilt:
1351 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1352 break;
1353 case nir_op_ine:
1354 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1355 break;
1356 case nir_op_ieq:
1357 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1358 break;
1359 case nir_op_ige:
1360 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1361 break;
1362 case nir_op_ult:
1363 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1364 break;
1365 case nir_op_uge:
1366 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1367 break;
1368 case nir_op_feq:
1369 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1370 break;
1371 case nir_op_fne:
1372 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1373 break;
1374 case nir_op_flt:
1375 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1376 break;
1377 case nir_op_fge:
1378 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1379 break;
1380 case nir_op_fabs:
1381 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1382 to_float_type(ctx, def_type), src[0]);
1383 break;
1384 case nir_op_iabs:
1385 result = emit_iabs(ctx, src[0]);
1386 break;
1387 case nir_op_imax:
1388 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1389 break;
1390 case nir_op_imin:
1391 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1392 break;
1393 case nir_op_umax:
1394 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1395 break;
1396 case nir_op_umin:
1397 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1398 break;
1399 case nir_op_isign:
1400 result = emit_isign(ctx, src[0]);
1401 break;
1402 case nir_op_fsign:
1403 src[0] = to_float(ctx, src[0]);
1404 result = emit_fsign(ctx, src[0]);
1405 break;
1406 case nir_op_ffloor:
1407 result = emit_intrin_1f_param(ctx, "llvm.floor",
1408 to_float_type(ctx, def_type), src[0]);
1409 break;
1410 case nir_op_ftrunc:
1411 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1412 to_float_type(ctx, def_type), src[0]);
1413 break;
1414 case nir_op_fceil:
1415 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1416 to_float_type(ctx, def_type), src[0]);
1417 break;
1418 case nir_op_fround_even:
1419 result = emit_intrin_1f_param(ctx, "llvm.rint",
1420 to_float_type(ctx, def_type),src[0]);
1421 break;
1422 case nir_op_ffract:
1423 result = emit_ffract(ctx, src[0]);
1424 break;
1425 case nir_op_fsin:
1426 result = emit_intrin_1f_param(ctx, "llvm.sin",
1427 to_float_type(ctx, def_type), src[0]);
1428 break;
1429 case nir_op_fcos:
1430 result = emit_intrin_1f_param(ctx, "llvm.cos",
1431 to_float_type(ctx, def_type), src[0]);
1432 break;
1433 case nir_op_fsqrt:
1434 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1435 to_float_type(ctx, def_type), src[0]);
1436 break;
1437 case nir_op_fexp2:
1438 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1439 to_float_type(ctx, def_type), src[0]);
1440 break;
1441 case nir_op_flog2:
1442 result = emit_intrin_1f_param(ctx, "llvm.log2",
1443 to_float_type(ctx, def_type), src[0]);
1444 break;
1445 case nir_op_frsq:
1446 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1447 to_float_type(ctx, def_type), src[0]);
1448 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1449 break;
1450 case nir_op_fpow:
1451 result = emit_intrin_2f_param(ctx, "llvm.pow",
1452 to_float_type(ctx, def_type), src[0], src[1]);
1453 break;
1454 case nir_op_fmax:
1455 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1456 to_float_type(ctx, def_type), src[0], src[1]);
1457 break;
1458 case nir_op_fmin:
1459 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1460 to_float_type(ctx, def_type), src[0], src[1]);
1461 break;
1462 case nir_op_ffma:
1463 result = emit_intrin_3f_param(ctx, "llvm.fma",
1464 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1465 break;
1466 case nir_op_ibitfield_extract:
1467 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1468 break;
1469 case nir_op_ubitfield_extract:
1470 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1471 break;
1472 case nir_op_bitfield_insert:
1473 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1474 break;
1475 case nir_op_bitfield_reverse:
1476 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1477 break;
1478 case nir_op_bit_count:
1479 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1480 break;
1481 case nir_op_vec2:
1482 case nir_op_vec3:
1483 case nir_op_vec4:
1484 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1485 src[i] = to_integer(ctx, src[i]);
1486 result = ac_build_gather_values(&ctx->ac, src, num_components);
1487 break;
1488 case nir_op_d2i:
1489 case nir_op_f2i:
1490 src[0] = to_float(ctx, src[0]);
1491 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1492 break;
1493 case nir_op_d2u:
1494 case nir_op_f2u:
1495 src[0] = to_float(ctx, src[0]);
1496 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1497 break;
1498 case nir_op_i2d:
1499 case nir_op_i2f:
1500 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1501 break;
1502 case nir_op_u2d:
1503 case nir_op_u2f:
1504 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1505 break;
1506 case nir_op_f2d:
1507 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1508 break;
1509 case nir_op_d2f:
1510 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1511 break;
1512 case nir_op_bcsel:
1513 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1514 break;
1515 case nir_op_find_lsb:
1516 result = emit_find_lsb(ctx, src[0]);
1517 break;
1518 case nir_op_ufind_msb:
1519 result = emit_ufind_msb(ctx, src[0]);
1520 break;
1521 case nir_op_ifind_msb:
1522 result = emit_ifind_msb(ctx, src[0]);
1523 break;
1524 case nir_op_uadd_carry:
1525 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1526 break;
1527 case nir_op_usub_borrow:
1528 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1529 break;
1530 case nir_op_b2f:
1531 result = emit_b2f(ctx, src[0]);
1532 break;
1533 case nir_op_fquantize2f16:
1534 src[0] = to_float(ctx, src[0]);
1535 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1536 /* need to convert back up to f32 */
1537 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1538 break;
1539 case nir_op_umul_high:
1540 result = emit_umul_high(ctx, src[0], src[1]);
1541 break;
1542 case nir_op_imul_high:
1543 result = emit_imul_high(ctx, src[0], src[1]);
1544 break;
1545 case nir_op_pack_half_2x16:
1546 result = emit_pack_half_2x16(ctx, src[0]);
1547 break;
1548 case nir_op_unpack_half_2x16:
1549 result = emit_unpack_half_2x16(ctx, src[0]);
1550 break;
1551 case nir_op_fddx:
1552 case nir_op_fddy:
1553 case nir_op_fddx_fine:
1554 case nir_op_fddy_fine:
1555 case nir_op_fddx_coarse:
1556 case nir_op_fddy_coarse:
1557 result = emit_ddxy(ctx, instr->op, src[0]);
1558 break;
1559 default:
1560 fprintf(stderr, "Unknown NIR alu instr: ");
1561 nir_print_instr(&instr->instr, stderr);
1562 fprintf(stderr, "\n");
1563 abort();
1564 }
1565
1566 if (result) {
1567 assert(instr->dest.dest.is_ssa);
1568 result = to_integer(ctx, result);
1569 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1570 result);
1571 }
1572 }
1573
1574 static void visit_load_const(struct nir_to_llvm_context *ctx,
1575 nir_load_const_instr *instr)
1576 {
1577 LLVMValueRef values[4], value = NULL;
1578 LLVMTypeRef element_type =
1579 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1580
1581 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1582 switch (instr->def.bit_size) {
1583 case 32:
1584 values[i] = LLVMConstInt(element_type,
1585 instr->value.u32[i], false);
1586 break;
1587 case 64:
1588 values[i] = LLVMConstInt(element_type,
1589 instr->value.u64[i], false);
1590 break;
1591 default:
1592 fprintf(stderr,
1593 "unsupported nir load_const bit_size: %d\n",
1594 instr->def.bit_size);
1595 abort();
1596 }
1597 }
1598 if (instr->def.num_components > 1) {
1599 value = LLVMConstVector(values, instr->def.num_components);
1600 } else
1601 value = values[0];
1602
1603 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1604 }
1605
1606 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1607 LLVMTypeRef type)
1608 {
1609 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1610 return LLVMBuildBitCast(ctx->builder, ptr,
1611 LLVMPointerType(type, addr_space), "");
1612 }
1613
1614 static LLVMValueRef
1615 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1616 {
1617 LLVMValueRef size =
1618 LLVMBuildExtractElement(ctx->builder, descriptor,
1619 LLVMConstInt(ctx->i32, 2, false), "");
1620
1621 /* VI only */
1622 if (ctx->options->chip_class >= VI && in_elements) {
1623 /* On VI, the descriptor contains the size in bytes,
1624 * but TXQ must return the size in elements.
1625 * The stride is always non-zero for resources using TXQ.
1626 */
1627 LLVMValueRef stride =
1628 LLVMBuildExtractElement(ctx->builder, descriptor,
1629 LLVMConstInt(ctx->i32, 1, false), "");
1630 stride = LLVMBuildLShr(ctx->builder, stride,
1631 LLVMConstInt(ctx->i32, 16, false), "");
1632 stride = LLVMBuildAnd(ctx->builder, stride,
1633 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1634
1635 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1636 }
1637 return size;
1638 }
1639
1640 /**
1641 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1642 * intrinsic names).
1643 */
1644 static void build_int_type_name(
1645 LLVMTypeRef type,
1646 char *buf, unsigned bufsize)
1647 {
1648 assert(bufsize >= 6);
1649
1650 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1651 snprintf(buf, bufsize, "v%ui32",
1652 LLVMGetVectorSize(type));
1653 else
1654 strcpy(buf, "i32");
1655 }
1656
1657 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1658 struct ac_tex_info *tinfo,
1659 nir_tex_instr *instr,
1660 const char *intr_name,
1661 unsigned coord_vgpr_index)
1662 {
1663 LLVMValueRef coord = tinfo->args[0];
1664 LLVMValueRef half_texel[2];
1665 int c;
1666
1667 //TODO Rect
1668 {
1669 LLVMValueRef txq_args[10];
1670 int txq_arg_count = 0;
1671 LLVMValueRef size;
1672 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1673 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1674 txq_args[txq_arg_count++] = tinfo->args[1];
1675 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1676 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1677 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1678 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1679 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1680 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1681 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1682 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1683 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1684 txq_args, txq_arg_count,
1685 AC_FUNC_ATTR_READNONE);
1686
1687 for (c = 0; c < 2; c++) {
1688 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1689 LLVMConstInt(ctx->i32, c, false), "");
1690 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1691 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1692 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1693 LLVMConstReal(ctx->f32, -0.5), "");
1694 }
1695 }
1696
1697 for (c = 0; c < 2; c++) {
1698 LLVMValueRef tmp;
1699 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1700 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1701 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1702 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1703 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1704 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1705 }
1706
1707 tinfo->args[0] = coord;
1708 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1709 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1710
1711 }
1712
1713 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1714 nir_tex_instr *instr,
1715 struct ac_tex_info *tinfo)
1716 {
1717 const char *name = "llvm.SI.image.sample";
1718 const char *infix = "";
1719 char intr_name[127];
1720 char type[64];
1721 bool is_shadow = instr->is_shadow;
1722 bool has_offset = tinfo->has_offset;
1723 switch (instr->op) {
1724 case nir_texop_txf:
1725 case nir_texop_txf_ms:
1726 case nir_texop_samples_identical:
1727 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1728 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1729 "llvm.SI.image.load.mip";
1730 is_shadow = false;
1731 has_offset = false;
1732 break;
1733 case nir_texop_txb:
1734 infix = ".b";
1735 break;
1736 case nir_texop_txl:
1737 infix = ".l";
1738 break;
1739 case nir_texop_txs:
1740 name = "llvm.SI.getresinfo";
1741 break;
1742 case nir_texop_query_levels:
1743 name = "llvm.SI.getresinfo";
1744 break;
1745 case nir_texop_tex:
1746 if (ctx->stage != MESA_SHADER_FRAGMENT)
1747 infix = ".lz";
1748 break;
1749 case nir_texop_txd:
1750 infix = ".d";
1751 break;
1752 case nir_texop_tg4:
1753 name = "llvm.SI.gather4";
1754 infix = ".lz";
1755 break;
1756 case nir_texop_lod:
1757 name = "llvm.SI.getlod";
1758 is_shadow = false;
1759 has_offset = false;
1760 break;
1761 default:
1762 break;
1763 }
1764
1765 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1766 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1767 has_offset ? ".o" : "", type);
1768
1769 if (instr->op == nir_texop_tg4) {
1770 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1771 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1772 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1773 (int)has_offset + (int)is_shadow);
1774 }
1775 }
1776 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1777 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1778
1779 }
1780
1781 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1782 nir_intrinsic_instr *instr)
1783 {
1784 LLVMValueRef index = get_src(ctx, instr->src[0]);
1785 unsigned desc_set = nir_intrinsic_desc_set(instr);
1786 unsigned binding = nir_intrinsic_binding(instr);
1787 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1788 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1789 unsigned base_offset = layout->binding[binding].offset;
1790 LLVMValueRef offset, stride;
1791
1792 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1793 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1794 desc_ptr = ctx->push_constants;
1795 base_offset = ctx->options->layout->push_constant_size;
1796 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1797 stride = LLVMConstInt(ctx->i32, 16, false);
1798 } else
1799 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1800
1801 offset = LLVMConstInt(ctx->i32, base_offset, false);
1802 index = LLVMBuildMul(ctx->builder, index, stride, "");
1803 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1804
1805 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1806 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1807 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1808
1809 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1810 }
1811
1812 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1813 nir_intrinsic_instr *instr)
1814 {
1815 LLVMValueRef ptr, addr;
1816
1817 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1818 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1819
1820 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1821 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1822
1823 return LLVMBuildLoad(ctx->builder, ptr, "");
1824 }
1825
1826 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1827 nir_intrinsic_instr *instr)
1828 {
1829 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1830
1831 return get_buffer_size(ctx, desc, false);
1832 }
1833 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1834 nir_intrinsic_instr *instr)
1835 {
1836 const char *store_name;
1837 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1838 LLVMTypeRef data_type = ctx->f32;
1839 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1840 int components_32bit = elem_size_mult * instr->num_components;
1841 unsigned writemask = nir_intrinsic_write_mask(instr);
1842 LLVMValueRef base_data, base_offset;
1843 LLVMValueRef params[6];
1844
1845 if (ctx->stage == MESA_SHADER_FRAGMENT)
1846 ctx->shader_info->fs.writes_memory = true;
1847
1848 params[1] = get_src(ctx, instr->src[1]);
1849 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1850 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1851 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1852
1853 if (components_32bit > 1)
1854 data_type = LLVMVectorType(ctx->f32, components_32bit);
1855
1856 base_data = to_float(ctx, src_data);
1857 base_data = trim_vector(ctx, base_data, instr->num_components);
1858 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1859 data_type, "");
1860 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1861 while (writemask) {
1862 int start, count;
1863 LLVMValueRef data;
1864 LLVMValueRef offset;
1865 LLVMValueRef tmp;
1866 u_bit_scan_consecutive_range(&writemask, &start, &count);
1867
1868 /* Due to an LLVM limitation, split 3-element writes
1869 * into a 2-element and a 1-element write. */
1870 if (count == 3) {
1871 writemask |= 1 << (start + 2);
1872 count = 2;
1873 }
1874
1875 start *= elem_size_mult;
1876 count *= elem_size_mult;
1877
1878 if (count > 4) {
1879 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1880 count = 4;
1881 }
1882
1883 if (count == 4) {
1884 store_name = "llvm.amdgcn.buffer.store.v4f32";
1885 data = base_data;
1886 } else if (count == 2) {
1887 tmp = LLVMBuildExtractElement(ctx->builder,
1888 base_data, LLVMConstInt(ctx->i32, start, false), "");
1889 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1890 ctx->i32zero, "");
1891
1892 tmp = LLVMBuildExtractElement(ctx->builder,
1893 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1894 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1895 ctx->i32one, "");
1896 store_name = "llvm.amdgcn.buffer.store.v2f32";
1897
1898 } else {
1899 assert(count == 1);
1900 if (get_llvm_num_components(base_data) > 1)
1901 data = LLVMBuildExtractElement(ctx->builder, base_data,
1902 LLVMConstInt(ctx->i32, start, false), "");
1903 else
1904 data = base_data;
1905 store_name = "llvm.amdgcn.buffer.store.f32";
1906 }
1907
1908 offset = base_offset;
1909 if (start != 0) {
1910 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1911 }
1912 params[0] = data;
1913 params[3] = offset;
1914 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1915 ctx->voidt, params, 6, 0);
1916 }
1917 }
1918
1919 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1920 nir_intrinsic_instr *instr)
1921 {
1922 const char *name;
1923 LLVMValueRef params[6];
1924 int arg_count = 0;
1925 if (ctx->stage == MESA_SHADER_FRAGMENT)
1926 ctx->shader_info->fs.writes_memory = true;
1927
1928 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1929 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1930 }
1931 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1932 params[arg_count++] = get_src(ctx, instr->src[0]);
1933 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1934 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1935 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1936
1937 switch (instr->intrinsic) {
1938 case nir_intrinsic_ssbo_atomic_add:
1939 name = "llvm.amdgcn.buffer.atomic.add";
1940 break;
1941 case nir_intrinsic_ssbo_atomic_imin:
1942 name = "llvm.amdgcn.buffer.atomic.smin";
1943 break;
1944 case nir_intrinsic_ssbo_atomic_umin:
1945 name = "llvm.amdgcn.buffer.atomic.umin";
1946 break;
1947 case nir_intrinsic_ssbo_atomic_imax:
1948 name = "llvm.amdgcn.buffer.atomic.smax";
1949 break;
1950 case nir_intrinsic_ssbo_atomic_umax:
1951 name = "llvm.amdgcn.buffer.atomic.umax";
1952 break;
1953 case nir_intrinsic_ssbo_atomic_and:
1954 name = "llvm.amdgcn.buffer.atomic.and";
1955 break;
1956 case nir_intrinsic_ssbo_atomic_or:
1957 name = "llvm.amdgcn.buffer.atomic.or";
1958 break;
1959 case nir_intrinsic_ssbo_atomic_xor:
1960 name = "llvm.amdgcn.buffer.atomic.xor";
1961 break;
1962 case nir_intrinsic_ssbo_atomic_exchange:
1963 name = "llvm.amdgcn.buffer.atomic.swap";
1964 break;
1965 case nir_intrinsic_ssbo_atomic_comp_swap:
1966 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1967 break;
1968 default:
1969 abort();
1970 }
1971
1972 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1973 }
1974
1975 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1976 nir_intrinsic_instr *instr)
1977 {
1978 LLVMValueRef results[2];
1979 int load_components;
1980 int num_components = instr->num_components;
1981 if (instr->dest.ssa.bit_size == 64)
1982 num_components *= 2;
1983
1984 for (int i = 0; i < num_components; i += load_components) {
1985 load_components = MIN2(num_components - i, 4);
1986 const char *load_name;
1987 LLVMTypeRef data_type = ctx->f32;
1988 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
1989 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
1990
1991 if (load_components == 3)
1992 data_type = LLVMVectorType(ctx->f32, 4);
1993 else if (load_components > 1)
1994 data_type = LLVMVectorType(ctx->f32, load_components);
1995
1996 if (load_components >= 3)
1997 load_name = "llvm.amdgcn.buffer.load.v4f32";
1998 else if (load_components == 2)
1999 load_name = "llvm.amdgcn.buffer.load.v2f32";
2000 else if (load_components == 1)
2001 load_name = "llvm.amdgcn.buffer.load.f32";
2002 else
2003 unreachable("unhandled number of components");
2004
2005 LLVMValueRef params[] = {
2006 get_src(ctx, instr->src[0]),
2007 LLVMConstInt(ctx->i32, 0, false),
2008 offset,
2009 LLVMConstInt(ctx->i1, 0, false),
2010 LLVMConstInt(ctx->i1, 0, false),
2011 };
2012
2013 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2014
2015 }
2016
2017 LLVMValueRef ret = results[0];
2018 if (num_components > 4 || num_components == 3) {
2019 LLVMValueRef masks[] = {
2020 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2021 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2022 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2023 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2024 };
2025
2026 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2027 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2028 results[num_components > 4 ? 1 : 0], swizzle, "");
2029 }
2030
2031 return LLVMBuildBitCast(ctx->builder, ret,
2032 get_def_type(ctx, &instr->dest.ssa), "");
2033 }
2034
2035 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2036 nir_intrinsic_instr *instr)
2037 {
2038 LLVMValueRef results[8], ret;
2039 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2040 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2041 int num_components = instr->num_components;
2042
2043 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2044
2045 if (instr->dest.ssa.bit_size == 64)
2046 num_components *= 2;
2047
2048 for (unsigned i = 0; i < num_components; ++i) {
2049 LLVMValueRef params[] = {
2050 rsrc,
2051 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2052 offset, "")
2053 };
2054 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2055 params, 2, AC_FUNC_ATTR_READNONE);
2056 }
2057
2058
2059 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2060 return LLVMBuildBitCast(ctx->builder, ret,
2061 get_def_type(ctx, &instr->dest.ssa), "");
2062 }
2063
2064 static void
2065 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2066 bool vs_in, unsigned *vertex_index_out,
2067 unsigned *const_out, LLVMValueRef *indir_out)
2068 {
2069 unsigned const_offset = 0;
2070 LLVMValueRef offset = NULL;
2071
2072 if (vertex_index_out != NULL) {
2073 tail = tail->child;
2074 nir_deref_array *deref_array = nir_deref_as_array(tail);
2075 *vertex_index_out = deref_array->base_offset;
2076 }
2077
2078 while (tail->child != NULL) {
2079 const struct glsl_type *parent_type = tail->type;
2080 tail = tail->child;
2081
2082 if (tail->deref_type == nir_deref_type_array) {
2083 nir_deref_array *deref_array = nir_deref_as_array(tail);
2084 LLVMValueRef index, stride, local_offset;
2085 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2086
2087 const_offset += size * deref_array->base_offset;
2088 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2089 continue;
2090
2091 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2092 index = get_src(ctx, deref_array->indirect);
2093 stride = LLVMConstInt(ctx->i32, size, 0);
2094 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2095
2096 if (offset)
2097 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2098 else
2099 offset = local_offset;
2100 } else if (tail->deref_type == nir_deref_type_struct) {
2101 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2102
2103 for (unsigned i = 0; i < deref_struct->index; i++) {
2104 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2105 const_offset += glsl_count_attribute_slots(ft, vs_in);
2106 }
2107 } else
2108 unreachable("unsupported deref type");
2109
2110 }
2111
2112 if (const_offset && offset)
2113 offset = LLVMBuildAdd(ctx->builder, offset,
2114 LLVMConstInt(ctx->i32, const_offset, 0),
2115 "");
2116
2117 *const_out = const_offset;
2118 *indir_out = offset;
2119 }
2120
2121 static LLVMValueRef
2122 load_gs_input(struct nir_to_llvm_context *ctx,
2123 nir_intrinsic_instr *instr)
2124 {
2125 LLVMValueRef indir_index, vtx_offset;
2126 unsigned const_index;
2127 LLVMValueRef args[9];
2128 unsigned param, vtx_offset_param;
2129 LLVMValueRef value[4], result;
2130 unsigned vertex_index;
2131 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2132 false, &vertex_index,
2133 &const_index, &indir_index);
2134 vtx_offset_param = vertex_index;
2135 assert(vtx_offset_param < 6);
2136 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2137 LLVMConstInt(ctx->i32, 4, false), "");
2138
2139 for (unsigned i = 0; i < instr->num_components; i++) {
2140 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2141 args[0] = ctx->esgs_ring;
2142 args[1] = vtx_offset;
2143 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2144 args[3] = ctx->i32zero;
2145 args[4] = ctx->i32one; /* OFFEN */
2146 args[5] = ctx->i32zero; /* IDXEN */
2147 args[6] = ctx->i32one; /* GLC */
2148 args[7] = ctx->i32zero; /* SLC */
2149 args[8] = ctx->i32zero; /* TFE */
2150
2151 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2152 ctx->i32, args, 9, AC_FUNC_ATTR_READONLY);
2153 }
2154 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2155
2156 return result;
2157 }
2158
2159 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2160 nir_intrinsic_instr *instr)
2161 {
2162 LLVMValueRef values[8];
2163 int idx = instr->variables[0]->var->data.driver_location;
2164 int ve = instr->dest.ssa.num_components;
2165 LLVMValueRef indir_index;
2166 LLVMValueRef ret;
2167 unsigned const_index;
2168 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2169 instr->variables[0]->var->data.mode == nir_var_shader_in;
2170 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2171 &const_index, &indir_index);
2172
2173 if (instr->dest.ssa.bit_size == 64)
2174 ve *= 2;
2175
2176 switch (instr->variables[0]->var->data.mode) {
2177 case nir_var_shader_in:
2178 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2179 return load_gs_input(ctx, instr);
2180 }
2181 for (unsigned chan = 0; chan < ve; chan++) {
2182 if (indir_index) {
2183 unsigned count = glsl_count_attribute_slots(
2184 instr->variables[0]->var->type,
2185 ctx->stage == MESA_SHADER_VERTEX);
2186 count -= chan / 4;
2187 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2188 &ctx->ac, ctx->inputs + idx + chan, count,
2189 4, false);
2190
2191 values[chan] = LLVMBuildExtractElement(ctx->builder,
2192 tmp_vec,
2193 indir_index, "");
2194 } else
2195 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2196 }
2197 break;
2198 case nir_var_local:
2199 for (unsigned chan = 0; chan < ve; chan++) {
2200 if (indir_index) {
2201 unsigned count = glsl_count_attribute_slots(
2202 instr->variables[0]->var->type, false);
2203 count -= chan / 4;
2204 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2205 &ctx->ac, ctx->locals + idx + chan, count,
2206 4, true);
2207
2208 values[chan] = LLVMBuildExtractElement(ctx->builder,
2209 tmp_vec,
2210 indir_index, "");
2211 } else {
2212 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2213 }
2214 }
2215 break;
2216 case nir_var_shader_out:
2217 for (unsigned chan = 0; chan < ve; chan++) {
2218 if (indir_index) {
2219 unsigned count = glsl_count_attribute_slots(
2220 instr->variables[0]->var->type, false);
2221 count -= chan / 4;
2222 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2223 &ctx->ac, ctx->outputs + idx + chan, count,
2224 4, true);
2225
2226 values[chan] = LLVMBuildExtractElement(ctx->builder,
2227 tmp_vec,
2228 indir_index, "");
2229 } else {
2230 values[chan] = LLVMBuildLoad(ctx->builder,
2231 ctx->outputs[idx + chan + const_index * 4],
2232 "");
2233 }
2234 }
2235 break;
2236 case nir_var_shared: {
2237 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2238 LLVMValueRef derived_ptr;
2239
2240 for (unsigned chan = 0; chan < ve; chan++) {
2241 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2242 if (indir_index)
2243 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2244 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2245
2246 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2247 }
2248 break;
2249 }
2250 default:
2251 unreachable("unhandle variable mode");
2252 }
2253 ret = ac_build_gather_values(&ctx->ac, values, ve);
2254 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2255 }
2256
2257 static void
2258 visit_store_var(struct nir_to_llvm_context *ctx,
2259 nir_intrinsic_instr *instr)
2260 {
2261 LLVMValueRef temp_ptr, value;
2262 int idx = instr->variables[0]->var->data.driver_location;
2263 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2264 int writemask = instr->const_index[0];
2265 LLVMValueRef indir_index;
2266 unsigned const_index;
2267 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2268 NULL, &const_index, &indir_index);
2269
2270 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2271 int old_writemask = writemask;
2272
2273 src = LLVMBuildBitCast(ctx->builder, src,
2274 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2275 "");
2276
2277 writemask = 0;
2278 for (unsigned chan = 0; chan < 4; chan++) {
2279 if (old_writemask & (1 << chan))
2280 writemask |= 3u << (2 * chan);
2281 }
2282 }
2283
2284 switch (instr->variables[0]->var->data.mode) {
2285 case nir_var_shader_out:
2286 for (unsigned chan = 0; chan < 8; chan++) {
2287 int stride = 4;
2288 if (!(writemask & (1 << chan)))
2289 continue;
2290
2291 value = llvm_extract_elem(ctx, src, chan);
2292
2293 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2294 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2295 stride = 1;
2296 if (indir_index) {
2297 unsigned count = glsl_count_attribute_slots(
2298 instr->variables[0]->var->type, false);
2299 count -= chan / 4;
2300 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2301 &ctx->ac, ctx->outputs + idx + chan, count,
2302 stride, true);
2303
2304 if (get_llvm_num_components(tmp_vec) > 1) {
2305 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2306 value, indir_index, "");
2307 } else
2308 tmp_vec = value;
2309 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2310 count, stride, tmp_vec);
2311
2312 } else {
2313 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2314
2315 LLVMBuildStore(ctx->builder, value, temp_ptr);
2316 }
2317 }
2318 break;
2319 case nir_var_local:
2320 for (unsigned chan = 0; chan < 8; chan++) {
2321 if (!(writemask & (1 << chan)))
2322 continue;
2323
2324 value = llvm_extract_elem(ctx, src, chan);
2325 if (indir_index) {
2326 unsigned count = glsl_count_attribute_slots(
2327 instr->variables[0]->var->type, false);
2328 count -= chan / 4;
2329 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2330 &ctx->ac, ctx->locals + idx + chan, count,
2331 4, true);
2332
2333 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2334 value, indir_index, "");
2335 build_store_values_extended(ctx, ctx->locals + idx + chan,
2336 count, 4, tmp_vec);
2337 } else {
2338 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2339
2340 LLVMBuildStore(ctx->builder, value, temp_ptr);
2341 }
2342 }
2343 break;
2344 case nir_var_shared: {
2345 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2346 for (unsigned chan = 0; chan < 8; chan++) {
2347 if (!(writemask & (1 << chan)))
2348 continue;
2349 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2350 LLVMValueRef derived_ptr;
2351
2352 if (indir_index)
2353 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2354
2355 value = llvm_extract_elem(ctx, src, chan);
2356 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2357 LLVMBuildStore(ctx->builder,
2358 to_integer(ctx, value), derived_ptr);
2359 }
2360 break;
2361 }
2362 default:
2363 break;
2364 }
2365 }
2366
2367 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2368 {
2369 switch (dim) {
2370 case GLSL_SAMPLER_DIM_BUF:
2371 return 1;
2372 case GLSL_SAMPLER_DIM_1D:
2373 return array ? 2 : 1;
2374 case GLSL_SAMPLER_DIM_2D:
2375 return array ? 3 : 2;
2376 case GLSL_SAMPLER_DIM_MS:
2377 return array ? 4 : 3;
2378 case GLSL_SAMPLER_DIM_3D:
2379 case GLSL_SAMPLER_DIM_CUBE:
2380 return 3;
2381 case GLSL_SAMPLER_DIM_RECT:
2382 case GLSL_SAMPLER_DIM_SUBPASS:
2383 return 2;
2384 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2385 return 3;
2386 default:
2387 break;
2388 }
2389 return 0;
2390 }
2391
2392 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2393 nir_intrinsic_instr *instr)
2394 {
2395 const struct glsl_type *type = instr->variables[0]->var->type;
2396 if(instr->variables[0]->deref.child)
2397 type = instr->variables[0]->deref.child->type;
2398
2399 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2400 LLVMValueRef coords[4];
2401 LLVMValueRef masks[] = {
2402 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2403 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2404 };
2405 LLVMValueRef res;
2406 int count;
2407 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2408 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2409 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2410 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2411 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2412
2413 count = image_type_to_components_count(dim,
2414 glsl_sampler_type_is_array(type));
2415
2416 if (count == 1) {
2417 if (instr->src[0].ssa->num_components)
2418 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2419 else
2420 res = src0;
2421 } else {
2422 int chan;
2423 if (is_ms)
2424 count--;
2425 for (chan = 0; chan < count; ++chan) {
2426 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2427 }
2428
2429 if (add_frag_pos) {
2430 for (chan = 0; chan < count; ++chan)
2431 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2432 }
2433 if (is_ms) {
2434 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2435 count++;
2436 }
2437
2438 if (count == 3) {
2439 coords[3] = LLVMGetUndef(ctx->i32);
2440 count = 4;
2441 }
2442 res = ac_build_gather_values(&ctx->ac, coords, count);
2443 }
2444 return res;
2445 }
2446
2447 static void build_type_name_for_intr(
2448 LLVMTypeRef type,
2449 char *buf, unsigned bufsize)
2450 {
2451 LLVMTypeRef elem_type = type;
2452
2453 assert(bufsize >= 8);
2454
2455 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2456 int ret = snprintf(buf, bufsize, "v%u",
2457 LLVMGetVectorSize(type));
2458 if (ret < 0) {
2459 char *type_name = LLVMPrintTypeToString(type);
2460 fprintf(stderr, "Error building type name for: %s\n",
2461 type_name);
2462 return;
2463 }
2464 elem_type = LLVMGetElementType(type);
2465 buf += ret;
2466 bufsize -= ret;
2467 }
2468 switch (LLVMGetTypeKind(elem_type)) {
2469 default: break;
2470 case LLVMIntegerTypeKind:
2471 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2472 break;
2473 case LLVMFloatTypeKind:
2474 snprintf(buf, bufsize, "f32");
2475 break;
2476 case LLVMDoubleTypeKind:
2477 snprintf(buf, bufsize, "f64");
2478 break;
2479 }
2480 }
2481
2482 static void get_image_intr_name(const char *base_name,
2483 LLVMTypeRef data_type,
2484 LLVMTypeRef coords_type,
2485 LLVMTypeRef rsrc_type,
2486 char *out_name, unsigned out_len)
2487 {
2488 char coords_type_name[8];
2489
2490 build_type_name_for_intr(coords_type, coords_type_name,
2491 sizeof(coords_type_name));
2492
2493 if (HAVE_LLVM <= 0x0309) {
2494 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2495 } else {
2496 char data_type_name[8];
2497 char rsrc_type_name[8];
2498
2499 build_type_name_for_intr(data_type, data_type_name,
2500 sizeof(data_type_name));
2501 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2502 sizeof(rsrc_type_name));
2503 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2504 data_type_name, coords_type_name, rsrc_type_name);
2505 }
2506 }
2507
2508 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2509 nir_intrinsic_instr *instr)
2510 {
2511 LLVMValueRef params[7];
2512 LLVMValueRef res;
2513 char intrinsic_name[64];
2514 const nir_variable *var = instr->variables[0]->var;
2515 const struct glsl_type *type = var->type;
2516 if(instr->variables[0]->deref.child)
2517 type = instr->variables[0]->deref.child->type;
2518
2519 type = glsl_without_array(type);
2520 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2521 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2522 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2523 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2524 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2525 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2526 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2527 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2528 params, 5, 0);
2529
2530 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2531 res = to_integer(ctx, res);
2532 } else {
2533 bool is_da = glsl_sampler_type_is_array(type) ||
2534 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2535 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2536 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2537 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2538
2539 params[0] = get_image_coords(ctx, instr);
2540 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2541 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2542 if (HAVE_LLVM <= 0x0309) {
2543 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2544 params[4] = da;
2545 params[5] = glc;
2546 params[6] = slc;
2547 } else {
2548 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2549 params[3] = glc;
2550 params[4] = slc;
2551 params[5] = lwe;
2552 params[6] = da;
2553 }
2554
2555 get_image_intr_name("llvm.amdgcn.image.load",
2556 ctx->v4f32, /* vdata */
2557 LLVMTypeOf(params[0]), /* coords */
2558 LLVMTypeOf(params[1]), /* rsrc */
2559 intrinsic_name, sizeof(intrinsic_name));
2560
2561 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2562 params, 7, AC_FUNC_ATTR_READONLY);
2563 }
2564 return to_integer(ctx, res);
2565 }
2566
2567 static void visit_image_store(struct nir_to_llvm_context *ctx,
2568 nir_intrinsic_instr *instr)
2569 {
2570 LLVMValueRef params[8];
2571 char intrinsic_name[64];
2572 const nir_variable *var = instr->variables[0]->var;
2573 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2574 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2575 const struct glsl_type *type = glsl_without_array(var->type);
2576
2577 if (ctx->stage == MESA_SHADER_FRAGMENT)
2578 ctx->shader_info->fs.writes_memory = true;
2579
2580 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2581 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2582 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2583 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2584 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2585 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2586 params[4] = i1false; /* glc */
2587 params[5] = i1false; /* slc */
2588 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2589 params, 6, 0);
2590 } else {
2591 bool is_da = glsl_sampler_type_is_array(type) ||
2592 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2593 LLVMValueRef da = is_da ? i1true : i1false;
2594 LLVMValueRef glc = i1false;
2595 LLVMValueRef slc = i1false;
2596
2597 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2598 params[1] = get_image_coords(ctx, instr); /* coords */
2599 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2600 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2601 if (HAVE_LLVM <= 0x0309) {
2602 params[4] = i1false; /* r128 */
2603 params[5] = da;
2604 params[6] = glc;
2605 params[7] = slc;
2606 } else {
2607 LLVMValueRef lwe = i1false;
2608 params[4] = glc;
2609 params[5] = slc;
2610 params[6] = lwe;
2611 params[7] = da;
2612 }
2613
2614 get_image_intr_name("llvm.amdgcn.image.store",
2615 LLVMTypeOf(params[0]), /* vdata */
2616 LLVMTypeOf(params[1]), /* coords */
2617 LLVMTypeOf(params[2]), /* rsrc */
2618 intrinsic_name, sizeof(intrinsic_name));
2619
2620 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2621 params, 8, 0);
2622 }
2623
2624 }
2625
2626 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2627 nir_intrinsic_instr *instr)
2628 {
2629 LLVMValueRef params[6];
2630 int param_count = 0;
2631 const nir_variable *var = instr->variables[0]->var;
2632 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2633 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2634 const char *base_name = "llvm.amdgcn.image.atomic";
2635 const char *atomic_name;
2636 LLVMValueRef coords;
2637 char intrinsic_name[32], coords_type[8];
2638 const struct glsl_type *type = glsl_without_array(var->type);
2639
2640 if (ctx->stage == MESA_SHADER_FRAGMENT)
2641 ctx->shader_info->fs.writes_memory = true;
2642
2643 params[param_count++] = get_src(ctx, instr->src[2]);
2644 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2645 params[param_count++] = get_src(ctx, instr->src[3]);
2646
2647 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2648 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2649 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2650 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2651 params[param_count++] = ctx->i32zero; /* voffset */
2652 params[param_count++] = i1false; /* glc */
2653 params[param_count++] = i1false; /* slc */
2654 } else {
2655 bool da = glsl_sampler_type_is_array(type) ||
2656 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2657
2658 coords = params[param_count++] = get_image_coords(ctx, instr);
2659 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2660 params[param_count++] = i1false; /* r128 */
2661 params[param_count++] = da ? i1true : i1false; /* da */
2662 params[param_count++] = i1false; /* slc */
2663 }
2664
2665 switch (instr->intrinsic) {
2666 case nir_intrinsic_image_atomic_add:
2667 atomic_name = "add";
2668 break;
2669 case nir_intrinsic_image_atomic_min:
2670 atomic_name = "smin";
2671 break;
2672 case nir_intrinsic_image_atomic_max:
2673 atomic_name = "smax";
2674 break;
2675 case nir_intrinsic_image_atomic_and:
2676 atomic_name = "and";
2677 break;
2678 case nir_intrinsic_image_atomic_or:
2679 atomic_name = "or";
2680 break;
2681 case nir_intrinsic_image_atomic_xor:
2682 atomic_name = "xor";
2683 break;
2684 case nir_intrinsic_image_atomic_exchange:
2685 atomic_name = "swap";
2686 break;
2687 case nir_intrinsic_image_atomic_comp_swap:
2688 atomic_name = "cmpswap";
2689 break;
2690 default:
2691 abort();
2692 }
2693 build_int_type_name(LLVMTypeOf(coords),
2694 coords_type, sizeof(coords_type));
2695
2696 snprintf(intrinsic_name, sizeof(intrinsic_name),
2697 "%s.%s.%s", base_name, atomic_name, coords_type);
2698 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2699 }
2700
2701 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2702 nir_intrinsic_instr *instr)
2703 {
2704 LLVMValueRef res;
2705 LLVMValueRef params[10];
2706 const nir_variable *var = instr->variables[0]->var;
2707 const struct glsl_type *type = instr->variables[0]->var->type;
2708 bool da = glsl_sampler_type_is_array(var->type) ||
2709 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2710 if(instr->variables[0]->deref.child)
2711 type = instr->variables[0]->deref.child->type;
2712
2713 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2714 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2715 params[0] = ctx->i32zero;
2716 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2717 params[2] = LLVMConstInt(ctx->i32, 15, false);
2718 params[3] = ctx->i32zero;
2719 params[4] = ctx->i32zero;
2720 params[5] = da ? ctx->i32one : ctx->i32zero;
2721 params[6] = ctx->i32zero;
2722 params[7] = ctx->i32zero;
2723 params[8] = ctx->i32zero;
2724 params[9] = ctx->i32zero;
2725
2726 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2727 params, 10, AC_FUNC_ATTR_READNONE);
2728
2729 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2730 glsl_sampler_type_is_array(type)) {
2731 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2732 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2733 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2734 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2735 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2736 }
2737 return res;
2738 }
2739
2740 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2741 {
2742 LLVMValueRef args[1] = {
2743 LLVMConstInt(ctx->i32, 0xf70, false),
2744 };
2745 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2746 ctx->voidt, args, 1, 0);
2747 }
2748
2749 static void emit_barrier(struct nir_to_llvm_context *ctx)
2750 {
2751 // TODO tess
2752 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2753 ctx->voidt, NULL, 0, 0);
2754 }
2755
2756 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2757 nir_intrinsic_instr *instr)
2758 {
2759 LLVMValueRef cond;
2760 ctx->shader_info->fs.can_discard = true;
2761
2762 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2763 get_src(ctx, instr->src[0]),
2764 ctx->i32zero, "");
2765
2766 cond = LLVMBuildSelect(ctx->builder, cond,
2767 LLVMConstReal(ctx->f32, -1.0f),
2768 ctx->f32zero, "");
2769 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2770 ctx->voidt,
2771 &cond, 1, 0);
2772 }
2773
2774 static LLVMValueRef
2775 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2776 {
2777 LLVMValueRef result;
2778 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2779 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2780 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2781
2782 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2783 }
2784
2785 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2786 nir_intrinsic_instr *instr)
2787 {
2788 LLVMValueRef ptr, result;
2789 int idx = instr->variables[0]->var->data.driver_location;
2790 LLVMValueRef src = get_src(ctx, instr->src[0]);
2791 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2792
2793 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2794 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2795 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2796 ptr, src, src1,
2797 LLVMAtomicOrderingSequentiallyConsistent,
2798 LLVMAtomicOrderingSequentiallyConsistent,
2799 false);
2800 } else {
2801 LLVMAtomicRMWBinOp op;
2802 switch (instr->intrinsic) {
2803 case nir_intrinsic_var_atomic_add:
2804 op = LLVMAtomicRMWBinOpAdd;
2805 break;
2806 case nir_intrinsic_var_atomic_umin:
2807 op = LLVMAtomicRMWBinOpUMin;
2808 break;
2809 case nir_intrinsic_var_atomic_umax:
2810 op = LLVMAtomicRMWBinOpUMax;
2811 break;
2812 case nir_intrinsic_var_atomic_imin:
2813 op = LLVMAtomicRMWBinOpMin;
2814 break;
2815 case nir_intrinsic_var_atomic_imax:
2816 op = LLVMAtomicRMWBinOpMax;
2817 break;
2818 case nir_intrinsic_var_atomic_and:
2819 op = LLVMAtomicRMWBinOpAnd;
2820 break;
2821 case nir_intrinsic_var_atomic_or:
2822 op = LLVMAtomicRMWBinOpOr;
2823 break;
2824 case nir_intrinsic_var_atomic_xor:
2825 op = LLVMAtomicRMWBinOpXor;
2826 break;
2827 case nir_intrinsic_var_atomic_exchange:
2828 op = LLVMAtomicRMWBinOpXchg;
2829 break;
2830 default:
2831 return NULL;
2832 }
2833
2834 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2835 LLVMAtomicOrderingSequentiallyConsistent,
2836 false);
2837 }
2838 return result;
2839 }
2840
2841 #define INTERP_CENTER 0
2842 #define INTERP_CENTROID 1
2843 #define INTERP_SAMPLE 2
2844
2845 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2846 enum glsl_interp_mode interp, unsigned location)
2847 {
2848 switch (interp) {
2849 case INTERP_MODE_FLAT:
2850 default:
2851 return NULL;
2852 case INTERP_MODE_SMOOTH:
2853 case INTERP_MODE_NONE:
2854 if (location == INTERP_CENTER)
2855 return ctx->persp_center;
2856 else if (location == INTERP_CENTROID)
2857 return ctx->persp_centroid;
2858 else if (location == INTERP_SAMPLE)
2859 return ctx->persp_sample;
2860 break;
2861 case INTERP_MODE_NOPERSPECTIVE:
2862 if (location == INTERP_CENTER)
2863 return ctx->linear_center;
2864 else if (location == INTERP_CENTROID)
2865 return ctx->linear_centroid;
2866 else if (location == INTERP_SAMPLE)
2867 return ctx->linear_sample;
2868 break;
2869 }
2870 return NULL;
2871 }
2872
2873 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2874 LLVMValueRef sample_id)
2875 {
2876 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2877 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2878 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2879 LLVMValueRef result[2];
2880
2881 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2882 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2883
2884 return ac_build_gather_values(&ctx->ac, result, 2);
2885 }
2886
2887 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2888 {
2889 LLVMValueRef values[2];
2890
2891 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2892 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2893 return ac_build_gather_values(&ctx->ac, values, 2);
2894 }
2895
2896 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2897 nir_intrinsic_instr *instr)
2898 {
2899 LLVMValueRef result[2];
2900 LLVMValueRef interp_param, attr_number;
2901 unsigned location;
2902 unsigned chan;
2903 LLVMValueRef src_c0, src_c1;
2904 const char *intr_name;
2905 LLVMValueRef src0;
2906 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2907 switch (instr->intrinsic) {
2908 case nir_intrinsic_interp_var_at_centroid:
2909 location = INTERP_CENTROID;
2910 break;
2911 case nir_intrinsic_interp_var_at_sample:
2912 case nir_intrinsic_interp_var_at_offset:
2913 location = INTERP_SAMPLE;
2914 src0 = get_src(ctx, instr->src[0]);
2915 break;
2916 default:
2917 break;
2918 }
2919
2920 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2921 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2922 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2923 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2924 LLVMValueRef sample_position;
2925 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2926
2927 /* fetch sample ID */
2928 sample_position = load_sample_position(ctx, src0);
2929
2930 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2931 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2932 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2933 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2934 }
2935 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2936 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2937
2938 if (location == INTERP_SAMPLE) {
2939 LLVMValueRef ij_out[2];
2940 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2941
2942 /*
2943 * take the I then J parameters, and the DDX/Y for it, and
2944 * calculate the IJ inputs for the interpolator.
2945 * temp1 = ddx * offset/sample.x + I;
2946 * interp_param.I = ddy * offset/sample.y + temp1;
2947 * temp1 = ddx * offset/sample.x + J;
2948 * interp_param.J = ddy * offset/sample.y + temp1;
2949 */
2950 for (unsigned i = 0; i < 2; i++) {
2951 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
2952 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
2953 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
2954 ddxy_out, ix_ll, "");
2955 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
2956 ddxy_out, iy_ll, "");
2957 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
2958 interp_param, ix_ll, "");
2959 LLVMValueRef temp1, temp2;
2960
2961 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
2962 ctx->f32, "");
2963
2964 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
2965 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
2966
2967 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
2968 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
2969
2970 ij_out[i] = LLVMBuildBitCast(ctx->builder,
2971 temp2, ctx->i32, "");
2972 }
2973 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
2974
2975 }
2976 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
2977 for (chan = 0; chan < 2; chan++) {
2978 LLVMValueRef args[4];
2979 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
2980
2981 args[0] = llvm_chan;
2982 args[1] = attr_number;
2983 args[2] = ctx->prim_mask;
2984 args[3] = interp_param;
2985 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
2986 ctx->f32, args, args[3] ? 4 : 3,
2987 AC_FUNC_ATTR_READNONE);
2988 }
2989 return ac_build_gather_values(&ctx->ac, result, 2);
2990 }
2991
2992 static void
2993 visit_emit_vertex(struct nir_to_llvm_context *ctx,
2994 nir_intrinsic_instr *instr)
2995 {
2996 LLVMValueRef gs_next_vertex;
2997 LLVMValueRef can_emit, kill;
2998 LLVMValueRef args[2];
2999 int idx;
3000
3001 assert(instr->const_index[0] == 0);
3002 /* Write vertex attribute values to GSVS ring */
3003 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3004 ctx->gs_next_vertex,
3005 "");
3006
3007 /* If this thread has already emitted the declared maximum number of
3008 * vertices, kill it: excessive vertex emissions are not supposed to
3009 * have any effect, and GS threads have no externally observable
3010 * effects other than emitting vertices.
3011 */
3012 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3013 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3014
3015 kill = LLVMBuildSelect(ctx->builder, can_emit,
3016 LLVMConstReal(ctx->f32, 1.0f),
3017 LLVMConstReal(ctx->f32, -1.0f), "");
3018 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3019 ctx->voidt, &kill, 1, 0);
3020
3021 /* loop num outputs */
3022 idx = 0;
3023 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3024 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3025 if (!(ctx->output_mask & (1ull << i)))
3026 continue;
3027
3028 for (unsigned j = 0; j < 4; j++) {
3029 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3030 out_ptr[j], "");
3031 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (idx * 4 + j) * ctx->gs_max_out_vertices, false);
3032 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3033 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3034
3035 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3036
3037 ac_build_tbuffer_store(&ctx->ac, ctx->gsvs_ring,
3038 out_val, 1,
3039 voffset, ctx->gs2vs_offset, 0,
3040 V_008F0C_BUF_DATA_FORMAT_32,
3041 V_008F0C_BUF_NUM_FORMAT_UINT,
3042 1, 0, 1, 1, 0);
3043 }
3044 idx++;
3045 }
3046
3047 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3048 ctx->i32one, "");
3049 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3050 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (0 << 8), false);
3051 args[1] = ctx->gs_wave_id;
3052 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
3053 ctx->voidt, args, 2, 0);
3054 }
3055
3056 static void
3057 visit_end_primitive(struct nir_to_llvm_context *ctx,
3058 nir_intrinsic_instr *instr)
3059 {
3060 LLVMValueRef args[2];
3061
3062 assert(instr->const_index[0] == 0);
3063 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_CUT | SENDMSG_GS | (0 << 8), false);
3064 args[1] = ctx->gs_wave_id;
3065
3066 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg", ctx->voidt,
3067 args, 2, 0);
3068 }
3069
3070 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3071 nir_intrinsic_instr *instr)
3072 {
3073 LLVMValueRef result = NULL;
3074
3075 switch (instr->intrinsic) {
3076 case nir_intrinsic_load_work_group_id: {
3077 result = ctx->workgroup_ids;
3078 break;
3079 }
3080 case nir_intrinsic_load_base_vertex: {
3081 result = ctx->base_vertex;
3082 break;
3083 }
3084 case nir_intrinsic_load_vertex_id_zero_base: {
3085 result = ctx->vertex_id;
3086 break;
3087 }
3088 case nir_intrinsic_load_local_invocation_id: {
3089 result = ctx->local_invocation_ids;
3090 break;
3091 }
3092 case nir_intrinsic_load_base_instance:
3093 result = ctx->start_instance;
3094 break;
3095 case nir_intrinsic_load_draw_id:
3096 result = ctx->draw_index;
3097 break;
3098 case nir_intrinsic_load_invocation_id:
3099 result = ctx->gs_invocation_id;
3100 break;
3101 case nir_intrinsic_load_primitive_id:
3102 if (ctx->stage == MESA_SHADER_GEOMETRY)
3103 result = ctx->gs_prim_id;
3104 else
3105 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3106 break;
3107 case nir_intrinsic_load_sample_id:
3108 ctx->shader_info->fs.force_persample = true;
3109 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3110 break;
3111 case nir_intrinsic_load_sample_pos:
3112 ctx->shader_info->fs.force_persample = true;
3113 result = load_sample_pos(ctx);
3114 break;
3115 case nir_intrinsic_load_front_face:
3116 result = ctx->front_face;
3117 break;
3118 case nir_intrinsic_load_instance_id:
3119 result = ctx->instance_id;
3120 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3121 ctx->shader_info->vs.vgpr_comp_cnt);
3122 break;
3123 case nir_intrinsic_load_num_work_groups:
3124 result = ctx->num_work_groups;
3125 break;
3126 case nir_intrinsic_load_local_invocation_index:
3127 result = visit_load_local_invocation_index(ctx);
3128 break;
3129 case nir_intrinsic_load_push_constant:
3130 result = visit_load_push_constant(ctx, instr);
3131 break;
3132 case nir_intrinsic_vulkan_resource_index:
3133 result = visit_vulkan_resource_index(ctx, instr);
3134 break;
3135 case nir_intrinsic_store_ssbo:
3136 visit_store_ssbo(ctx, instr);
3137 break;
3138 case nir_intrinsic_load_ssbo:
3139 result = visit_load_buffer(ctx, instr);
3140 break;
3141 case nir_intrinsic_ssbo_atomic_add:
3142 case nir_intrinsic_ssbo_atomic_imin:
3143 case nir_intrinsic_ssbo_atomic_umin:
3144 case nir_intrinsic_ssbo_atomic_imax:
3145 case nir_intrinsic_ssbo_atomic_umax:
3146 case nir_intrinsic_ssbo_atomic_and:
3147 case nir_intrinsic_ssbo_atomic_or:
3148 case nir_intrinsic_ssbo_atomic_xor:
3149 case nir_intrinsic_ssbo_atomic_exchange:
3150 case nir_intrinsic_ssbo_atomic_comp_swap:
3151 result = visit_atomic_ssbo(ctx, instr);
3152 break;
3153 case nir_intrinsic_load_ubo:
3154 result = visit_load_ubo_buffer(ctx, instr);
3155 break;
3156 case nir_intrinsic_get_buffer_size:
3157 result = visit_get_buffer_size(ctx, instr);
3158 break;
3159 case nir_intrinsic_load_var:
3160 result = visit_load_var(ctx, instr);
3161 break;
3162 case nir_intrinsic_store_var:
3163 visit_store_var(ctx, instr);
3164 break;
3165 case nir_intrinsic_image_load:
3166 result = visit_image_load(ctx, instr);
3167 break;
3168 case nir_intrinsic_image_store:
3169 visit_image_store(ctx, instr);
3170 break;
3171 case nir_intrinsic_image_atomic_add:
3172 case nir_intrinsic_image_atomic_min:
3173 case nir_intrinsic_image_atomic_max:
3174 case nir_intrinsic_image_atomic_and:
3175 case nir_intrinsic_image_atomic_or:
3176 case nir_intrinsic_image_atomic_xor:
3177 case nir_intrinsic_image_atomic_exchange:
3178 case nir_intrinsic_image_atomic_comp_swap:
3179 result = visit_image_atomic(ctx, instr);
3180 break;
3181 case nir_intrinsic_image_size:
3182 result = visit_image_size(ctx, instr);
3183 break;
3184 case nir_intrinsic_discard:
3185 ctx->shader_info->fs.can_discard = true;
3186 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3187 ctx->voidt,
3188 NULL, 0, 0);
3189 break;
3190 case nir_intrinsic_discard_if:
3191 emit_discard_if(ctx, instr);
3192 break;
3193 case nir_intrinsic_memory_barrier:
3194 emit_waitcnt(ctx);
3195 break;
3196 case nir_intrinsic_barrier:
3197 emit_barrier(ctx);
3198 break;
3199 case nir_intrinsic_var_atomic_add:
3200 case nir_intrinsic_var_atomic_imin:
3201 case nir_intrinsic_var_atomic_umin:
3202 case nir_intrinsic_var_atomic_imax:
3203 case nir_intrinsic_var_atomic_umax:
3204 case nir_intrinsic_var_atomic_and:
3205 case nir_intrinsic_var_atomic_or:
3206 case nir_intrinsic_var_atomic_xor:
3207 case nir_intrinsic_var_atomic_exchange:
3208 case nir_intrinsic_var_atomic_comp_swap:
3209 result = visit_var_atomic(ctx, instr);
3210 break;
3211 case nir_intrinsic_interp_var_at_centroid:
3212 case nir_intrinsic_interp_var_at_sample:
3213 case nir_intrinsic_interp_var_at_offset:
3214 result = visit_interp(ctx, instr);
3215 break;
3216 case nir_intrinsic_emit_vertex:
3217 visit_emit_vertex(ctx, instr);
3218 break;
3219 case nir_intrinsic_end_primitive:
3220 visit_end_primitive(ctx, instr);
3221 break;
3222 default:
3223 fprintf(stderr, "Unknown intrinsic: ");
3224 nir_print_instr(&instr->instr, stderr);
3225 fprintf(stderr, "\n");
3226 break;
3227 }
3228 if (result) {
3229 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3230 }
3231 }
3232
3233 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3234 nir_deref_var *deref,
3235 enum desc_type desc_type)
3236 {
3237 unsigned desc_set = deref->var->data.descriptor_set;
3238 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3239 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3240 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3241 unsigned offset = binding->offset;
3242 unsigned stride = binding->size;
3243 unsigned type_size;
3244 LLVMBuilderRef builder = ctx->builder;
3245 LLVMTypeRef type;
3246 LLVMValueRef index = NULL;
3247
3248 assert(deref->var->data.binding < layout->binding_count);
3249
3250 switch (desc_type) {
3251 case DESC_IMAGE:
3252 type = ctx->v8i32;
3253 type_size = 32;
3254 break;
3255 case DESC_FMASK:
3256 type = ctx->v8i32;
3257 offset += 32;
3258 type_size = 32;
3259 break;
3260 case DESC_SAMPLER:
3261 type = ctx->v4i32;
3262 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3263 offset += 64;
3264
3265 type_size = 16;
3266 break;
3267 case DESC_BUFFER:
3268 type = ctx->v4i32;
3269 type_size = 16;
3270 break;
3271 default:
3272 unreachable("invalid desc_type\n");
3273 }
3274
3275 if (deref->deref.child) {
3276 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3277
3278 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3279 offset += child->base_offset * stride;
3280 if (child->deref_array_type == nir_deref_array_type_indirect) {
3281 index = get_src(ctx, child->indirect);
3282 }
3283 }
3284
3285 assert(stride % type_size == 0);
3286
3287 if (!index)
3288 index = ctx->i32zero;
3289
3290 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3291
3292 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3293 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3294
3295 return ac_build_indexed_load_const(&ctx->ac, list, index);
3296 }
3297
3298 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3299 struct ac_tex_info *tinfo,
3300 nir_tex_instr *instr,
3301 nir_texop op,
3302 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3303 LLVMValueRef *param, unsigned count,
3304 unsigned dmask)
3305 {
3306 int num_args;
3307 unsigned is_rect = 0;
3308 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3309
3310 if (op == nir_texop_lod)
3311 da = false;
3312 /* Pad to power of two vector */
3313 while (count < util_next_power_of_two(count))
3314 param[count++] = LLVMGetUndef(ctx->i32);
3315
3316 if (count > 1)
3317 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3318 else
3319 tinfo->args[0] = param[0];
3320
3321 tinfo->args[1] = res_ptr;
3322 num_args = 2;
3323
3324 if (op == nir_texop_txf ||
3325 op == nir_texop_txf_ms ||
3326 op == nir_texop_query_levels ||
3327 op == nir_texop_texture_samples ||
3328 op == nir_texop_txs)
3329 tinfo->dst_type = ctx->v4i32;
3330 else {
3331 tinfo->dst_type = ctx->v4f32;
3332 tinfo->args[num_args++] = samp_ptr;
3333 }
3334
3335 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3336 tinfo->args[0] = res_ptr;
3337 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3338 tinfo->args[2] = param[0];
3339 tinfo->arg_count = 3;
3340 return;
3341 }
3342
3343 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3344 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3345 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3346 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3347 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3348 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3349 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3350 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3351
3352 tinfo->arg_count = num_args;
3353 }
3354
3355 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3356 *
3357 * SI-CI:
3358 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3359 * filtering manually. The driver sets img7 to a mask clearing
3360 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3361 * s_and_b32 samp0, samp0, img7
3362 *
3363 * VI:
3364 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3365 */
3366 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3367 LLVMValueRef res, LLVMValueRef samp)
3368 {
3369 LLVMBuilderRef builder = ctx->builder;
3370 LLVMValueRef img7, samp0;
3371
3372 if (ctx->options->chip_class >= VI)
3373 return samp;
3374
3375 img7 = LLVMBuildExtractElement(builder, res,
3376 LLVMConstInt(ctx->i32, 7, 0), "");
3377 samp0 = LLVMBuildExtractElement(builder, samp,
3378 LLVMConstInt(ctx->i32, 0, 0), "");
3379 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3380 return LLVMBuildInsertElement(builder, samp, samp0,
3381 LLVMConstInt(ctx->i32, 0, 0), "");
3382 }
3383
3384 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3385 nir_tex_instr *instr,
3386 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3387 LLVMValueRef *fmask_ptr)
3388 {
3389 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3390 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3391 else
3392 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3393 if (samp_ptr) {
3394 if (instr->sampler)
3395 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3396 else
3397 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3398 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3399 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3400 }
3401 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3402 instr->op == nir_texop_samples_identical))
3403 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3404 }
3405
3406 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3407 LLVMValueRef coord)
3408 {
3409 coord = to_float(ctx, coord);
3410 coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3411 coord = to_integer(ctx, coord);
3412 return coord;
3413 }
3414
3415 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3416 {
3417 LLVMValueRef result = NULL;
3418 struct ac_tex_info tinfo = { 0 };
3419 unsigned dmask = 0xf;
3420 LLVMValueRef address[16];
3421 LLVMValueRef coords[5];
3422 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3423 LLVMValueRef bias = NULL, offsets = NULL;
3424 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3425 LLVMValueRef ddx = NULL, ddy = NULL;
3426 LLVMValueRef derivs[6];
3427 unsigned chan, count = 0;
3428 unsigned const_src = 0, num_deriv_comp = 0;
3429
3430 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3431
3432 for (unsigned i = 0; i < instr->num_srcs; i++) {
3433 switch (instr->src[i].src_type) {
3434 case nir_tex_src_coord:
3435 coord = get_src(ctx, instr->src[i].src);
3436 break;
3437 case nir_tex_src_projector:
3438 break;
3439 case nir_tex_src_comparator:
3440 comparator = get_src(ctx, instr->src[i].src);
3441 break;
3442 case nir_tex_src_offset:
3443 offsets = get_src(ctx, instr->src[i].src);
3444 const_src = i;
3445 break;
3446 case nir_tex_src_bias:
3447 bias = get_src(ctx, instr->src[i].src);
3448 break;
3449 case nir_tex_src_lod:
3450 lod = get_src(ctx, instr->src[i].src);
3451 break;
3452 case nir_tex_src_ms_index:
3453 sample_index = get_src(ctx, instr->src[i].src);
3454 break;
3455 case nir_tex_src_ms_mcs:
3456 break;
3457 case nir_tex_src_ddx:
3458 ddx = get_src(ctx, instr->src[i].src);
3459 num_deriv_comp = instr->src[i].src.ssa->num_components;
3460 break;
3461 case nir_tex_src_ddy:
3462 ddy = get_src(ctx, instr->src[i].src);
3463 break;
3464 case nir_tex_src_texture_offset:
3465 case nir_tex_src_sampler_offset:
3466 case nir_tex_src_plane:
3467 default:
3468 break;
3469 }
3470 }
3471
3472 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3473 result = get_buffer_size(ctx, res_ptr, false);
3474 goto write_result;
3475 }
3476
3477 if (instr->op == nir_texop_texture_samples) {
3478 LLVMValueRef res, samples, is_msaa;
3479 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3480 samples = LLVMBuildExtractElement(ctx->builder, res,
3481 LLVMConstInt(ctx->i32, 3, false), "");
3482 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3483 LLVMConstInt(ctx->i32, 28, false), "");
3484 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3485 LLVMConstInt(ctx->i32, 0xe, false), "");
3486 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3487 LLVMConstInt(ctx->i32, 0xe, false), "");
3488
3489 samples = LLVMBuildLShr(ctx->builder, samples,
3490 LLVMConstInt(ctx->i32, 16, false), "");
3491 samples = LLVMBuildAnd(ctx->builder, samples,
3492 LLVMConstInt(ctx->i32, 0xf, false), "");
3493 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3494 samples, "");
3495 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3496 ctx->i32one, "");
3497 result = samples;
3498 goto write_result;
3499 }
3500
3501 if (coord)
3502 for (chan = 0; chan < instr->coord_components; chan++)
3503 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3504
3505 if (offsets && instr->op != nir_texop_txf) {
3506 LLVMValueRef offset[3], pack;
3507 for (chan = 0; chan < 3; ++chan)
3508 offset[chan] = ctx->i32zero;
3509
3510 tinfo.has_offset = true;
3511 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3512 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3513 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3514 LLVMConstInt(ctx->i32, 0x3f, false), "");
3515 if (chan)
3516 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3517 LLVMConstInt(ctx->i32, chan * 8, false), "");
3518 }
3519 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3520 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3521 address[count++] = pack;
3522
3523 }
3524 /* pack LOD bias value */
3525 if (instr->op == nir_texop_txb && bias) {
3526 address[count++] = bias;
3527 }
3528
3529 /* Pack depth comparison value */
3530 if (instr->is_shadow && comparator) {
3531 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3532 }
3533
3534 /* pack derivatives */
3535 if (ddx || ddy) {
3536 switch (instr->sampler_dim) {
3537 case GLSL_SAMPLER_DIM_3D:
3538 case GLSL_SAMPLER_DIM_CUBE:
3539 num_deriv_comp = 3;
3540 break;
3541 case GLSL_SAMPLER_DIM_2D:
3542 default:
3543 num_deriv_comp = 2;
3544 break;
3545 case GLSL_SAMPLER_DIM_1D:
3546 num_deriv_comp = 1;
3547 break;
3548 }
3549
3550 for (unsigned i = 0; i < num_deriv_comp; i++) {
3551 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3552 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3553 }
3554 }
3555
3556 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3557 for (chan = 0; chan < instr->coord_components; chan++)
3558 coords[chan] = to_float(ctx, coords[chan]);
3559 if (instr->coord_components == 3)
3560 coords[3] = LLVMGetUndef(ctx->f32);
3561 ac_prepare_cube_coords(&ctx->ac,
3562 instr->op == nir_texop_txd, instr->is_array,
3563 coords, derivs);
3564 if (num_deriv_comp)
3565 num_deriv_comp--;
3566 }
3567
3568 if (ddx || ddy) {
3569 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3570 address[count++] = derivs[i];
3571 }
3572
3573 /* Pack texture coordinates */
3574 if (coord) {
3575 address[count++] = coords[0];
3576 if (instr->coord_components > 1) {
3577 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3578 coords[1] = apply_round_slice(ctx, coords[1]);
3579 }
3580 address[count++] = coords[1];
3581 }
3582 if (instr->coord_components > 2) {
3583 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3584 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3585 coords[2] = apply_round_slice(ctx, coords[2]);
3586 }
3587 address[count++] = coords[2];
3588 }
3589 }
3590
3591 /* Pack LOD */
3592 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3593 address[count++] = lod;
3594 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3595 address[count++] = sample_index;
3596 } else if(instr->op == nir_texop_txs) {
3597 count = 0;
3598 if (lod)
3599 address[count++] = lod;
3600 else
3601 address[count++] = ctx->i32zero;
3602 }
3603
3604 for (chan = 0; chan < count; chan++) {
3605 address[chan] = LLVMBuildBitCast(ctx->builder,
3606 address[chan], ctx->i32, "");
3607 }
3608
3609 if (instr->op == nir_texop_samples_identical) {
3610 LLVMValueRef txf_address[4];
3611 struct ac_tex_info txf_info = { 0 };
3612 unsigned txf_count = count;
3613 memcpy(txf_address, address, sizeof(txf_address));
3614
3615 if (!instr->is_array)
3616 txf_address[2] = ctx->i32zero;
3617 txf_address[3] = ctx->i32zero;
3618
3619 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3620 fmask_ptr, NULL,
3621 txf_address, txf_count, 0xf);
3622
3623 result = build_tex_intrinsic(ctx, instr, &txf_info);
3624
3625 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3626 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3627 goto write_result;
3628 }
3629
3630 /* Adjust the sample index according to FMASK.
3631 *
3632 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3633 * which is the identity mapping. Each nibble says which physical sample
3634 * should be fetched to get that sample.
3635 *
3636 * For example, 0x11111100 means there are only 2 samples stored and
3637 * the second sample covers 3/4 of the pixel. When reading samples 0
3638 * and 1, return physical sample 0 (determined by the first two 0s
3639 * in FMASK), otherwise return physical sample 1.
3640 *
3641 * The sample index should be adjusted as follows:
3642 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3643 */
3644 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS) {
3645 LLVMValueRef txf_address[4];
3646 struct ac_tex_info txf_info = { 0 };
3647 unsigned txf_count = count;
3648 memcpy(txf_address, address, sizeof(txf_address));
3649
3650 if (!instr->is_array)
3651 txf_address[2] = ctx->i32zero;
3652 txf_address[3] = ctx->i32zero;
3653
3654 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3655 fmask_ptr, NULL,
3656 txf_address, txf_count, 0xf);
3657
3658 result = build_tex_intrinsic(ctx, instr, &txf_info);
3659 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3660 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3661
3662 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3663 result,
3664 ctx->i32zero, "");
3665
3666 unsigned sample_chan = instr->is_array ? 3 : 2;
3667
3668 LLVMValueRef sample_index4 =
3669 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3670 LLVMValueRef shifted_fmask =
3671 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3672 LLVMValueRef final_sample =
3673 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3674
3675 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3676 * resource descriptor is 0 (invalid),
3677 */
3678 LLVMValueRef fmask_desc =
3679 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3680 ctx->v8i32, "");
3681
3682 LLVMValueRef fmask_word1 =
3683 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3684 ctx->i32one, "");
3685
3686 LLVMValueRef word1_is_nonzero =
3687 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3688 fmask_word1, ctx->i32zero, "");
3689
3690 /* Replace the MSAA sample index. */
3691 address[sample_chan] =
3692 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3693 final_sample, address[sample_chan], "");
3694 }
3695
3696 if (offsets && instr->op == nir_texop_txf) {
3697 nir_const_value *const_offset =
3698 nir_src_as_const_value(instr->src[const_src].src);
3699 int num_offsets = instr->src[const_src].src.ssa->num_components;
3700 assert(const_offset);
3701 num_offsets = MIN2(num_offsets, instr->coord_components);
3702 if (num_offsets > 2)
3703 address[2] = LLVMBuildAdd(ctx->builder,
3704 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3705 if (num_offsets > 1)
3706 address[1] = LLVMBuildAdd(ctx->builder,
3707 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3708 address[0] = LLVMBuildAdd(ctx->builder,
3709 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3710
3711 }
3712
3713 /* TODO TG4 support */
3714 if (instr->op == nir_texop_tg4) {
3715 if (instr->is_shadow)
3716 dmask = 1;
3717 else
3718 dmask = 1 << instr->component;
3719 }
3720 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3721 res_ptr, samp_ptr, address, count, dmask);
3722
3723 result = build_tex_intrinsic(ctx, instr, &tinfo);
3724
3725 if (instr->op == nir_texop_query_levels)
3726 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3727 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3728 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3729 else if (instr->op == nir_texop_txs &&
3730 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3731 instr->is_array) {
3732 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3733 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3734 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3735 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3736 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3737 } else if (instr->dest.ssa.num_components != 4)
3738 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3739
3740 write_result:
3741 if (result) {
3742 assert(instr->dest.is_ssa);
3743 result = to_integer(ctx, result);
3744 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3745 }
3746 }
3747
3748
3749 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3750 {
3751 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3752 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3753
3754 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3755 _mesa_hash_table_insert(ctx->phis, instr, result);
3756 }
3757
3758 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3759 nir_phi_instr *instr,
3760 LLVMValueRef llvm_phi)
3761 {
3762 nir_foreach_phi_src(src, instr) {
3763 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3764 LLVMValueRef llvm_src = get_src(ctx, src->src);
3765
3766 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3767 }
3768 }
3769
3770 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3771 {
3772 struct hash_entry *entry;
3773 hash_table_foreach(ctx->phis, entry) {
3774 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3775 (LLVMValueRef)entry->data);
3776 }
3777 }
3778
3779
3780 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3781 nir_ssa_undef_instr *instr)
3782 {
3783 unsigned num_components = instr->def.num_components;
3784 LLVMValueRef undef;
3785
3786 if (num_components == 1)
3787 undef = LLVMGetUndef(ctx->i32);
3788 else {
3789 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3790 }
3791 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3792 }
3793
3794 static void visit_jump(struct nir_to_llvm_context *ctx,
3795 nir_jump_instr *instr)
3796 {
3797 switch (instr->type) {
3798 case nir_jump_break:
3799 LLVMBuildBr(ctx->builder, ctx->break_block);
3800 LLVMClearInsertionPosition(ctx->builder);
3801 break;
3802 case nir_jump_continue:
3803 LLVMBuildBr(ctx->builder, ctx->continue_block);
3804 LLVMClearInsertionPosition(ctx->builder);
3805 break;
3806 default:
3807 fprintf(stderr, "Unknown NIR jump instr: ");
3808 nir_print_instr(&instr->instr, stderr);
3809 fprintf(stderr, "\n");
3810 abort();
3811 }
3812 }
3813
3814 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3815 struct exec_list *list);
3816
3817 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3818 {
3819 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3820 nir_foreach_instr(instr, block)
3821 {
3822 switch (instr->type) {
3823 case nir_instr_type_alu:
3824 visit_alu(ctx, nir_instr_as_alu(instr));
3825 break;
3826 case nir_instr_type_load_const:
3827 visit_load_const(ctx, nir_instr_as_load_const(instr));
3828 break;
3829 case nir_instr_type_intrinsic:
3830 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3831 break;
3832 case nir_instr_type_tex:
3833 visit_tex(ctx, nir_instr_as_tex(instr));
3834 break;
3835 case nir_instr_type_phi:
3836 visit_phi(ctx, nir_instr_as_phi(instr));
3837 break;
3838 case nir_instr_type_ssa_undef:
3839 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3840 break;
3841 case nir_instr_type_jump:
3842 visit_jump(ctx, nir_instr_as_jump(instr));
3843 break;
3844 default:
3845 fprintf(stderr, "Unknown NIR instr type: ");
3846 nir_print_instr(instr, stderr);
3847 fprintf(stderr, "\n");
3848 abort();
3849 }
3850 }
3851
3852 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3853 }
3854
3855 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3856 {
3857 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3858
3859 LLVMBasicBlockRef merge_block =
3860 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3861 LLVMBasicBlockRef if_block =
3862 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3863 LLVMBasicBlockRef else_block = merge_block;
3864 if (!exec_list_is_empty(&if_stmt->else_list))
3865 else_block = LLVMAppendBasicBlockInContext(
3866 ctx->context, ctx->main_function, "");
3867
3868 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3869 LLVMConstInt(ctx->i32, 0, false), "");
3870 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3871
3872 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3873 visit_cf_list(ctx, &if_stmt->then_list);
3874 if (LLVMGetInsertBlock(ctx->builder))
3875 LLVMBuildBr(ctx->builder, merge_block);
3876
3877 if (!exec_list_is_empty(&if_stmt->else_list)) {
3878 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3879 visit_cf_list(ctx, &if_stmt->else_list);
3880 if (LLVMGetInsertBlock(ctx->builder))
3881 LLVMBuildBr(ctx->builder, merge_block);
3882 }
3883
3884 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3885 }
3886
3887 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3888 {
3889 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3890 LLVMBasicBlockRef break_parent = ctx->break_block;
3891
3892 ctx->continue_block =
3893 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3894 ctx->break_block =
3895 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3896
3897 LLVMBuildBr(ctx->builder, ctx->continue_block);
3898 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3899 visit_cf_list(ctx, &loop->body);
3900
3901 if (LLVMGetInsertBlock(ctx->builder))
3902 LLVMBuildBr(ctx->builder, ctx->continue_block);
3903 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3904
3905 ctx->continue_block = continue_parent;
3906 ctx->break_block = break_parent;
3907 }
3908
3909 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3910 struct exec_list *list)
3911 {
3912 foreach_list_typed(nir_cf_node, node, node, list)
3913 {
3914 switch (node->type) {
3915 case nir_cf_node_block:
3916 visit_block(ctx, nir_cf_node_as_block(node));
3917 break;
3918
3919 case nir_cf_node_if:
3920 visit_if(ctx, nir_cf_node_as_if(node));
3921 break;
3922
3923 case nir_cf_node_loop:
3924 visit_loop(ctx, nir_cf_node_as_loop(node));
3925 break;
3926
3927 default:
3928 assert(0);
3929 }
3930 }
3931 }
3932
3933 static void
3934 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3935 struct nir_variable *variable)
3936 {
3937 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3938 LLVMValueRef t_offset;
3939 LLVMValueRef t_list;
3940 LLVMValueRef args[3];
3941 LLVMValueRef input;
3942 LLVMValueRef buffer_index;
3943 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3944 int idx = variable->data.location;
3945 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3946
3947 variable->data.driver_location = idx * 4;
3948
3949 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3950 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3951 ctx->start_instance, "");
3952 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3953 ctx->shader_info->vs.vgpr_comp_cnt);
3954 } else
3955 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3956 ctx->base_vertex, "");
3957
3958 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3959 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3960
3961 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
3962 args[0] = t_list;
3963 args[1] = LLVMConstInt(ctx->i32, 0, false);
3964 args[2] = buffer_index;
3965 input = ac_emit_llvm_intrinsic(&ctx->ac,
3966 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3967 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3968
3969 for (unsigned chan = 0; chan < 4; chan++) {
3970 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3971 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3972 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3973 input, llvm_chan, ""));
3974 }
3975 }
3976 }
3977
3978
3979 static void interp_fs_input(struct nir_to_llvm_context *ctx,
3980 unsigned attr,
3981 LLVMValueRef interp_param,
3982 LLVMValueRef prim_mask,
3983 LLVMValueRef result[4])
3984 {
3985 const char *intr_name;
3986 LLVMValueRef attr_number;
3987 unsigned chan;
3988
3989 attr_number = LLVMConstInt(ctx->i32, attr, false);
3990
3991 /* fs.constant returns the param from the middle vertex, so it's not
3992 * really useful for flat shading. It's meant to be used for custom
3993 * interpolation (but the intrinsic can't fetch from the other two
3994 * vertices).
3995 *
3996 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
3997 * to do the right thing. The only reason we use fs.constant is that
3998 * fs.interp cannot be used on integers, because they can be equal
3999 * to NaN.
4000 */
4001 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
4002
4003 for (chan = 0; chan < 4; chan++) {
4004 LLVMValueRef args[4];
4005 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4006
4007 args[0] = llvm_chan;
4008 args[1] = attr_number;
4009 args[2] = prim_mask;
4010 args[3] = interp_param;
4011 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
4012 ctx->f32, args, args[3] ? 4 : 3,
4013 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
4014 }
4015 }
4016
4017 static void
4018 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4019 struct nir_variable *variable)
4020 {
4021 int idx = variable->data.location;
4022 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4023 LLVMValueRef interp;
4024
4025 variable->data.driver_location = idx * 4;
4026 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4027
4028 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4029 unsigned interp_type;
4030 if (variable->data.sample) {
4031 interp_type = INTERP_SAMPLE;
4032 ctx->shader_info->fs.force_persample = true;
4033 } else if (variable->data.centroid)
4034 interp_type = INTERP_CENTROID;
4035 else
4036 interp_type = INTERP_CENTER;
4037
4038 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4039 } else
4040 interp = NULL;
4041
4042 for (unsigned i = 0; i < attrib_count; ++i)
4043 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4044
4045 }
4046
4047 static void
4048 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4049 struct nir_variable *variable)
4050 {
4051 switch (ctx->stage) {
4052 case MESA_SHADER_VERTEX:
4053 handle_vs_input_decl(ctx, variable);
4054 break;
4055 case MESA_SHADER_FRAGMENT:
4056 handle_fs_input_decl(ctx, variable);
4057 break;
4058 default:
4059 break;
4060 }
4061
4062 }
4063
4064 static void
4065 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4066 struct nir_shader *nir)
4067 {
4068 unsigned index = 0;
4069 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4070 LLVMValueRef interp_param;
4071 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4072
4073 if (!(ctx->input_mask & (1ull << i)))
4074 continue;
4075
4076 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4077 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4078 interp_param = *inputs;
4079 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4080 inputs);
4081
4082 if (!interp_param)
4083 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4084 ++index;
4085 } else if (i == VARYING_SLOT_POS) {
4086 for(int i = 0; i < 3; ++i)
4087 inputs[i] = ctx->frag_pos[i];
4088
4089 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4090 }
4091 }
4092 ctx->shader_info->fs.num_interp = index;
4093 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4094 ctx->shader_info->fs.has_pcoord = true;
4095 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4096 ctx->shader_info->fs.prim_id_input = true;
4097 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4098 ctx->shader_info->fs.layer_input = true;
4099 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4100 }
4101
4102 static LLVMValueRef
4103 ac_build_alloca(struct nir_to_llvm_context *ctx,
4104 LLVMTypeRef type,
4105 const char *name)
4106 {
4107 LLVMBuilderRef builder = ctx->builder;
4108 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4109 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4110 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4111 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4112 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4113 LLVMValueRef res;
4114
4115 if (first_instr) {
4116 LLVMPositionBuilderBefore(first_builder, first_instr);
4117 } else {
4118 LLVMPositionBuilderAtEnd(first_builder, first_block);
4119 }
4120
4121 res = LLVMBuildAlloca(first_builder, type, name);
4122 LLVMBuildStore(builder, LLVMConstNull(type), res);
4123
4124 LLVMDisposeBuilder(first_builder);
4125
4126 return res;
4127 }
4128
4129 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4130 LLVMTypeRef type,
4131 const char *name)
4132 {
4133 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4134 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4135 return ptr;
4136 }
4137
4138 static void
4139 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4140 struct nir_variable *variable)
4141 {
4142 int idx = variable->data.location + variable->data.index;
4143 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4144
4145 variable->data.driver_location = idx * 4;
4146
4147 if (ctx->stage == MESA_SHADER_VERTEX ||
4148 ctx->stage == MESA_SHADER_GEOMETRY) {
4149 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4150 idx == VARYING_SLOT_CULL_DIST0) {
4151 int length = glsl_get_length(variable->type);
4152 if (ctx->stage == MESA_SHADER_VERTEX) {
4153 if (idx == VARYING_SLOT_CLIP_DIST0) {
4154 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4155 ctx->num_clips = length;
4156 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4157 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4158 ctx->num_culls = length;
4159 }
4160 }
4161 if (length > 4)
4162 attrib_count = 2;
4163 else
4164 attrib_count = 1;
4165 }
4166 }
4167
4168 for (unsigned i = 0; i < attrib_count; ++i) {
4169 for (unsigned chan = 0; chan < 4; chan++) {
4170 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4171 si_build_alloca_undef(ctx, ctx->f32, "");
4172 }
4173 }
4174 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4175 }
4176
4177 static void
4178 setup_locals(struct nir_to_llvm_context *ctx,
4179 struct nir_function *func)
4180 {
4181 int i, j;
4182 ctx->num_locals = 0;
4183 nir_foreach_variable(variable, &func->impl->locals) {
4184 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4185 variable->data.driver_location = ctx->num_locals * 4;
4186 ctx->num_locals += attrib_count;
4187 }
4188 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4189 if (!ctx->locals)
4190 return;
4191
4192 for (i = 0; i < ctx->num_locals; i++) {
4193 for (j = 0; j < 4; j++) {
4194 ctx->locals[i * 4 + j] =
4195 si_build_alloca_undef(ctx, ctx->f32, "temp");
4196 }
4197 }
4198 }
4199
4200 static LLVMValueRef
4201 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4202 {
4203 v = to_float(ctx, v);
4204 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4205 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4206 }
4207
4208
4209 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4210 LLVMValueRef src0, LLVMValueRef src1)
4211 {
4212 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4213 LLVMValueRef comp[2];
4214
4215 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4216 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4217 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4218 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4219 }
4220
4221 /* Initialize arguments for the shader export intrinsic */
4222 static void
4223 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4224 LLVMValueRef *values,
4225 unsigned target,
4226 LLVMValueRef *args)
4227 {
4228 /* Default is 0xf. Adjusted below depending on the format. */
4229 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4230 /* Specify whether the EXEC mask represents the valid mask */
4231 args[1] = LLVMConstInt(ctx->i32, 0, false);
4232
4233 /* Specify whether this is the last export */
4234 args[2] = LLVMConstInt(ctx->i32, 0, false);
4235 /* Specify the target we are exporting */
4236 args[3] = LLVMConstInt(ctx->i32, target, false);
4237
4238 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4239 args[5] = LLVMGetUndef(ctx->f32);
4240 args[6] = LLVMGetUndef(ctx->f32);
4241 args[7] = LLVMGetUndef(ctx->f32);
4242 args[8] = LLVMGetUndef(ctx->f32);
4243
4244 if (!values)
4245 return;
4246
4247 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4248 LLVMValueRef val[4];
4249 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4250 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4251 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4252
4253 switch(col_format) {
4254 case V_028714_SPI_SHADER_ZERO:
4255 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4256 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4257 break;
4258
4259 case V_028714_SPI_SHADER_32_R:
4260 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4261 args[5] = values[0];
4262 break;
4263
4264 case V_028714_SPI_SHADER_32_GR:
4265 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4266 args[5] = values[0];
4267 args[6] = values[1];
4268 break;
4269
4270 case V_028714_SPI_SHADER_32_AR:
4271 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4272 args[5] = values[0];
4273 args[8] = values[3];
4274 break;
4275
4276 case V_028714_SPI_SHADER_FP16_ABGR:
4277 args[4] = ctx->i32one;
4278
4279 for (unsigned chan = 0; chan < 2; chan++) {
4280 LLVMValueRef pack_args[2] = {
4281 values[2 * chan],
4282 values[2 * chan + 1]
4283 };
4284 LLVMValueRef packed;
4285
4286 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4287 ctx->i32, pack_args, 2,
4288 AC_FUNC_ATTR_READNONE);
4289 args[chan + 5] = packed;
4290 }
4291 break;
4292
4293 case V_028714_SPI_SHADER_UNORM16_ABGR:
4294 for (unsigned chan = 0; chan < 4; chan++) {
4295 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4296 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4297 LLVMConstReal(ctx->f32, 65535), "");
4298 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4299 LLVMConstReal(ctx->f32, 0.5), "");
4300 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4301 ctx->i32, "");
4302 }
4303
4304 args[4] = ctx->i32one;
4305 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4306 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4307 break;
4308
4309 case V_028714_SPI_SHADER_SNORM16_ABGR:
4310 for (unsigned chan = 0; chan < 4; chan++) {
4311 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4312 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4313 LLVMConstReal(ctx->f32, 32767), "");
4314
4315 /* If positive, add 0.5, else add -0.5. */
4316 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4317 LLVMBuildSelect(ctx->builder,
4318 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4319 val[chan], ctx->f32zero, ""),
4320 LLVMConstReal(ctx->f32, 0.5),
4321 LLVMConstReal(ctx->f32, -0.5), ""), "");
4322 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4323 }
4324
4325 args[4] = ctx->i32one;
4326 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4327 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4328 break;
4329
4330 case V_028714_SPI_SHADER_UINT16_ABGR: {
4331 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4332
4333 for (unsigned chan = 0; chan < 4; chan++) {
4334 val[chan] = to_integer(ctx, values[chan]);
4335 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4336 }
4337
4338 args[4] = ctx->i32one;
4339 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4340 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4341 break;
4342 }
4343
4344 case V_028714_SPI_SHADER_SINT16_ABGR: {
4345 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4346 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4347
4348 /* Clamp. */
4349 for (unsigned chan = 0; chan < 4; chan++) {
4350 val[chan] = to_integer(ctx, values[chan]);
4351 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4352 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4353 }
4354
4355 args[4] = ctx->i32one;
4356 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4357 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4358 break;
4359 }
4360
4361 default:
4362 case V_028714_SPI_SHADER_32_ABGR:
4363 memcpy(&args[5], values, sizeof(values[0]) * 4);
4364 break;
4365 }
4366 } else
4367 memcpy(&args[5], values, sizeof(values[0]) * 4);
4368
4369 for (unsigned i = 5; i < 9; ++i)
4370 args[i] = to_float(ctx, args[i]);
4371 }
4372
4373 static void
4374 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4375 {
4376 uint32_t param_count = 0;
4377 unsigned target;
4378 unsigned pos_idx, num_pos_exports = 0;
4379 LLVMValueRef args[9];
4380 LLVMValueRef pos_args[4][9] = { { 0 } };
4381 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4382 int i;
4383 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4384 (1ull << VARYING_SLOT_CLIP_DIST1) |
4385 (1ull << VARYING_SLOT_CULL_DIST0) |
4386 (1ull << VARYING_SLOT_CULL_DIST1));
4387
4388 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4389 ctx->shader_info->vs.layer_output = 0xffffffff;
4390 if (clip_mask) {
4391 LLVMValueRef slots[8];
4392 unsigned j;
4393
4394 if (ctx->shader_info->vs.cull_dist_mask)
4395 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_clips;
4396
4397 i = VARYING_SLOT_CLIP_DIST0;
4398 for (j = 0; j < ctx->num_clips; j++)
4399 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4400 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4401 i = VARYING_SLOT_CULL_DIST0;
4402 for (j = 0; j < ctx->num_culls; j++)
4403 slots[ctx->num_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4404 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4405
4406 for (i = ctx->num_clips + ctx->num_culls; i < 8; i++)
4407 slots[i] = LLVMGetUndef(ctx->f32);
4408
4409 if (ctx->num_clips + ctx->num_culls > 4) {
4410 target = V_008DFC_SQ_EXP_POS + 3;
4411 si_llvm_init_export_args(ctx, &slots[4], target, args);
4412 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4413 args, sizeof(args));
4414 }
4415
4416 target = V_008DFC_SQ_EXP_POS + 2;
4417 si_llvm_init_export_args(ctx, &slots[0], target, args);
4418 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4419 args, sizeof(args));
4420
4421 }
4422
4423 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4424 LLVMValueRef values[4];
4425 if (!(ctx->output_mask & (1ull << i)))
4426 continue;
4427
4428 for (unsigned j = 0; j < 4; j++)
4429 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4430 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4431
4432 if (i == VARYING_SLOT_POS) {
4433 target = V_008DFC_SQ_EXP_POS;
4434 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4435 i == VARYING_SLOT_CLIP_DIST1 ||
4436 i == VARYING_SLOT_CULL_DIST0 ||
4437 i == VARYING_SLOT_CULL_DIST1) {
4438 continue;
4439 } else if (i == VARYING_SLOT_PSIZ) {
4440 ctx->shader_info->vs.writes_pointsize = true;
4441 psize_value = values[0];
4442 continue;
4443 } else if (i == VARYING_SLOT_LAYER) {
4444 ctx->shader_info->vs.writes_layer = true;
4445 layer_value = values[0];
4446 ctx->shader_info->vs.layer_output = param_count;
4447 target = V_008DFC_SQ_EXP_PARAM + param_count;
4448 param_count++;
4449 } else if (i == VARYING_SLOT_VIEWPORT) {
4450 ctx->shader_info->vs.writes_viewport_index = true;
4451 viewport_index_value = values[0];
4452 continue;
4453 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4454 ctx->shader_info->vs.prim_id_output = param_count;
4455 target = V_008DFC_SQ_EXP_PARAM + param_count;
4456 param_count++;
4457 } else if (i >= VARYING_SLOT_VAR0) {
4458 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4459 target = V_008DFC_SQ_EXP_PARAM + param_count;
4460 param_count++;
4461 }
4462
4463 si_llvm_init_export_args(ctx, values, target, args);
4464
4465 if (target >= V_008DFC_SQ_EXP_POS &&
4466 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4467 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4468 args, sizeof(args));
4469 } else {
4470 ac_emit_llvm_intrinsic(&ctx->ac,
4471 "llvm.SI.export",
4472 ctx->voidt,
4473 args, 9, 0);
4474 }
4475 }
4476
4477 /* We need to add the position output manually if it's missing. */
4478 if (!pos_args[0][0]) {
4479 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4480 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4481 pos_args[0][2] = ctx->i32zero; /* last export? */
4482 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4483 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4484 pos_args[0][5] = ctx->f32zero; /* X */
4485 pos_args[0][6] = ctx->f32zero; /* Y */
4486 pos_args[0][7] = ctx->f32zero; /* Z */
4487 pos_args[0][8] = ctx->f32one; /* W */
4488 }
4489
4490 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4491 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4492 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4493 if (mask) {
4494 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4495 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4496 pos_args[1][2] = ctx->i32zero; /* last export? */
4497 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4498 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4499 pos_args[1][5] = ctx->f32zero; /* X */
4500 pos_args[1][6] = ctx->f32zero; /* Y */
4501 pos_args[1][7] = ctx->f32zero; /* Z */
4502 pos_args[1][8] = ctx->f32zero; /* W */
4503
4504 if (ctx->shader_info->vs.writes_pointsize == true)
4505 pos_args[1][5] = psize_value;
4506 if (ctx->shader_info->vs.writes_layer == true)
4507 pos_args[1][7] = layer_value;
4508 if (ctx->shader_info->vs.writes_viewport_index == true)
4509 pos_args[1][8] = viewport_index_value;
4510 }
4511 for (i = 0; i < 4; i++) {
4512 if (pos_args[i][0])
4513 num_pos_exports++;
4514 }
4515
4516 pos_idx = 0;
4517 for (i = 0; i < 4; i++) {
4518 if (!pos_args[i][0])
4519 continue;
4520
4521 /* Specify the target we are exporting */
4522 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4523 if (pos_idx == num_pos_exports)
4524 pos_args[i][2] = ctx->i32one;
4525 ac_emit_llvm_intrinsic(&ctx->ac,
4526 "llvm.SI.export",
4527 ctx->voidt,
4528 pos_args[i], 9, 0);
4529 }
4530
4531 ctx->shader_info->vs.pos_exports = num_pos_exports;
4532 ctx->shader_info->vs.param_exports = param_count;
4533 }
4534
4535 static void
4536 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4537 {
4538 int j;
4539 uint64_t max_output_written = 0;
4540 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4541 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4542 int param_index;
4543 if (!(ctx->output_mask & (1ull << i)))
4544 continue;
4545
4546 param_index = shader_io_get_unique_index(i);
4547
4548 if (param_index > max_output_written)
4549 max_output_written = param_index;
4550
4551 for (j = 0; j < 4; j++) {
4552 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4553 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4554
4555 ac_build_tbuffer_store(&ctx->ac,
4556 ctx->esgs_ring,
4557 out_val, 1,
4558 LLVMGetUndef(ctx->i32), ctx->es2gs_offset,
4559 (4 * param_index + j) * 4,
4560 V_008F0C_BUF_DATA_FORMAT_32,
4561 V_008F0C_BUF_NUM_FORMAT_UINT,
4562 0, 0, 1, 1, 0);
4563 }
4564 }
4565 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4566 }
4567
4568 static void
4569 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4570 LLVMValueRef *color, unsigned param, bool is_last)
4571 {
4572 LLVMValueRef args[9];
4573 /* Export */
4574 si_llvm_init_export_args(ctx, color, param,
4575 args);
4576
4577 if (is_last) {
4578 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4579 args[2] = ctx->i32one; /* DONE bit */
4580 } else if (args[0] == ctx->i32zero)
4581 return; /* unnecessary NULL export */
4582
4583 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4584 ctx->voidt, args, 9, 0);
4585 }
4586
4587 static void
4588 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4589 LLVMValueRef depth, LLVMValueRef stencil,
4590 LLVMValueRef samplemask)
4591 {
4592 LLVMValueRef args[9];
4593 unsigned mask = 0;
4594 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4595 args[2] = ctx->i32one; /* DONE bit */
4596 /* Specify the target we are exporting */
4597 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4598
4599 args[4] = ctx->i32zero; /* COMP flag */
4600 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4601 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4602 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4603 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4604
4605 if (depth) {
4606 args[5] = depth;
4607 mask |= 0x1;
4608 }
4609
4610 if (stencil) {
4611 args[6] = stencil;
4612 mask |= 0x2;
4613 }
4614
4615 if (samplemask) {
4616 args[7] = samplemask;
4617 mask |= 0x04;
4618 }
4619
4620 /* SI (except OLAND) has a bug that it only looks
4621 * at the X writemask component. */
4622 if (ctx->options->chip_class == SI &&
4623 ctx->options->family != CHIP_OLAND)
4624 mask |= 0x01;
4625
4626 args[0] = LLVMConstInt(ctx->i32, mask, false);
4627 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4628 ctx->voidt, args, 9, 0);
4629 }
4630
4631 static void
4632 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4633 {
4634 unsigned index = 0;
4635 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4636
4637 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4638 LLVMValueRef values[4];
4639
4640 if (!(ctx->output_mask & (1ull << i)))
4641 continue;
4642
4643 if (i == FRAG_RESULT_DEPTH) {
4644 ctx->shader_info->fs.writes_z = true;
4645 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4646 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4647 } else if (i == FRAG_RESULT_STENCIL) {
4648 ctx->shader_info->fs.writes_stencil = true;
4649 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4650 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4651 } else {
4652 bool last = false;
4653 for (unsigned j = 0; j < 4; j++)
4654 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4655 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4656
4657 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4658 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4659
4660 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4661 index++;
4662 }
4663 }
4664
4665 if (depth || stencil)
4666 si_export_mrt_z(ctx, depth, stencil, samplemask);
4667 else if (!index)
4668 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4669
4670 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4671 }
4672
4673 static void
4674 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4675 {
4676 LLVMValueRef args[2];
4677
4678 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE, false);
4679 args[1] = ctx->gs_wave_id;
4680 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
4681 ctx->voidt, args, 2, 0);
4682 }
4683
4684 static void
4685 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4686 {
4687 switch (ctx->stage) {
4688 case MESA_SHADER_VERTEX:
4689 if (ctx->options->key.vs.as_es)
4690 handle_es_outputs_post(ctx);
4691 else
4692 handle_vs_outputs_post(ctx);
4693 break;
4694 case MESA_SHADER_FRAGMENT:
4695 handle_fs_outputs_post(ctx);
4696 break;
4697 case MESA_SHADER_GEOMETRY:
4698 emit_gs_epilogue(ctx);
4699 break;
4700 default:
4701 break;
4702 }
4703 }
4704
4705 static void
4706 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4707 struct nir_variable *variable, uint32_t *offset, int idx)
4708 {
4709 unsigned size = glsl_count_attribute_slots(variable->type, false);
4710 variable->data.driver_location = *offset;
4711 *offset += size;
4712 }
4713
4714 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4715 {
4716 LLVMPassManagerRef passmgr;
4717 /* Create the pass manager */
4718 passmgr = LLVMCreateFunctionPassManagerForModule(
4719 ctx->module);
4720
4721 /* This pass should eliminate all the load and store instructions */
4722 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4723
4724 /* Add some optimization passes */
4725 LLVMAddScalarReplAggregatesPass(passmgr);
4726 LLVMAddLICMPass(passmgr);
4727 LLVMAddAggressiveDCEPass(passmgr);
4728 LLVMAddCFGSimplificationPass(passmgr);
4729 LLVMAddInstructionCombiningPass(passmgr);
4730
4731 /* Run the pass */
4732 LLVMInitializeFunctionPassManager(passmgr);
4733 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4734 LLVMFinalizeFunctionPassManager(passmgr);
4735
4736 LLVMDisposeBuilder(ctx->builder);
4737 LLVMDisposePassManager(passmgr);
4738 }
4739
4740 static void
4741 ac_setup_rings(struct nir_to_llvm_context *ctx)
4742 {
4743 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4744 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4745 }
4746
4747 if (ctx->is_gs_copy_shader) {
4748 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4749 }
4750 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4751 LLVMValueRef tmp;
4752 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4753 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4754
4755 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4756
4757 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4758 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4759 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4760 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4761
4762 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4763 }
4764 }
4765
4766 static
4767 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4768 struct nir_shader *nir,
4769 struct ac_shader_variant_info *shader_info,
4770 const struct ac_nir_compiler_options *options)
4771 {
4772 struct nir_to_llvm_context ctx = {0};
4773 struct nir_function *func;
4774 unsigned i;
4775 ctx.options = options;
4776 ctx.shader_info = shader_info;
4777 ctx.context = LLVMContextCreate();
4778 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4779
4780 ac_llvm_context_init(&ctx.ac, ctx.context);
4781 ctx.ac.module = ctx.module;
4782
4783 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4784
4785 memset(shader_info, 0, sizeof(*shader_info));
4786
4787 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4788 setup_types(&ctx);
4789
4790 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4791 ctx.ac.builder = ctx.builder;
4792 ctx.stage = nir->stage;
4793
4794 for (i = 0; i < AC_UD_MAX_SETS; i++)
4795 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4796 for (i = 0; i < AC_UD_MAX_UD; i++)
4797 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4798
4799 create_function(&ctx);
4800
4801 if (nir->stage == MESA_SHADER_COMPUTE) {
4802 int num_shared = 0;
4803 nir_foreach_variable(variable, &nir->shared)
4804 num_shared++;
4805 if (num_shared) {
4806 int idx = 0;
4807 uint32_t shared_size = 0;
4808 LLVMValueRef var;
4809 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4810 nir_foreach_variable(variable, &nir->shared) {
4811 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4812 idx++;
4813 }
4814
4815 shared_size *= 16;
4816 var = LLVMAddGlobalInAddressSpace(ctx.module,
4817 LLVMArrayType(ctx.i8, shared_size),
4818 "compute_lds",
4819 LOCAL_ADDR_SPACE);
4820 LLVMSetAlignment(var, 4);
4821 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4822 }
4823 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4824 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4825
4826 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4827 }
4828
4829 ac_setup_rings(&ctx);
4830
4831 nir_foreach_variable(variable, &nir->inputs)
4832 handle_shader_input_decl(&ctx, variable);
4833
4834 if (nir->stage == MESA_SHADER_FRAGMENT)
4835 handle_fs_inputs_pre(&ctx, nir);
4836
4837 nir_foreach_variable(variable, &nir->outputs)
4838 handle_shader_output_decl(&ctx, variable);
4839
4840 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4841 _mesa_key_pointer_equal);
4842 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4843 _mesa_key_pointer_equal);
4844
4845 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4846
4847 setup_locals(&ctx, func);
4848
4849 visit_cf_list(&ctx, &func->impl->body);
4850 phi_post_pass(&ctx);
4851
4852 handle_shader_outputs_post(&ctx);
4853 LLVMBuildRetVoid(ctx.builder);
4854
4855 ac_llvm_finalize_module(&ctx);
4856 free(ctx.locals);
4857 ralloc_free(ctx.defs);
4858 ralloc_free(ctx.phis);
4859
4860 if (nir->stage == MESA_SHADER_GEOMETRY) {
4861 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4862 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4863 nir->info->gs.vertices_out;
4864 }
4865 return ctx.module;
4866 }
4867
4868 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4869 {
4870 unsigned *retval = (unsigned *)context;
4871 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4872 char *description = LLVMGetDiagInfoDescription(di);
4873
4874 if (severity == LLVMDSError) {
4875 *retval = 1;
4876 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4877 description);
4878 }
4879
4880 LLVMDisposeMessage(description);
4881 }
4882
4883 static unsigned ac_llvm_compile(LLVMModuleRef M,
4884 struct ac_shader_binary *binary,
4885 LLVMTargetMachineRef tm)
4886 {
4887 unsigned retval = 0;
4888 char *err;
4889 LLVMContextRef llvm_ctx;
4890 LLVMMemoryBufferRef out_buffer;
4891 unsigned buffer_size;
4892 const char *buffer_data;
4893 LLVMBool mem_err;
4894
4895 /* Setup Diagnostic Handler*/
4896 llvm_ctx = LLVMGetModuleContext(M);
4897
4898 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4899 &retval);
4900
4901 /* Compile IR*/
4902 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4903 &err, &out_buffer);
4904
4905 /* Process Errors/Warnings */
4906 if (mem_err) {
4907 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4908 free(err);
4909 retval = 1;
4910 goto out;
4911 }
4912
4913 /* Extract Shader Code*/
4914 buffer_size = LLVMGetBufferSize(out_buffer);
4915 buffer_data = LLVMGetBufferStart(out_buffer);
4916
4917 ac_elf_read(buffer_data, buffer_size, binary);
4918
4919 /* Clean up */
4920 LLVMDisposeMemoryBuffer(out_buffer);
4921
4922 out:
4923 return retval;
4924 }
4925
4926 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4927 LLVMModuleRef llvm_module,
4928 struct ac_shader_binary *binary,
4929 struct ac_shader_config *config,
4930 struct ac_shader_variant_info *shader_info,
4931 gl_shader_stage stage,
4932 bool dump_shader, bool supports_spill)
4933 {
4934 if (dump_shader)
4935 ac_dump_module(llvm_module);
4936
4937 memset(binary, 0, sizeof(*binary));
4938 int v = ac_llvm_compile(llvm_module, binary, tm);
4939 if (v) {
4940 fprintf(stderr, "compile failed\n");
4941 }
4942
4943 if (dump_shader)
4944 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4945
4946 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4947
4948 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4949 LLVMDisposeModule(llvm_module);
4950 LLVMContextDispose(ctx);
4951
4952 if (stage == MESA_SHADER_FRAGMENT) {
4953 shader_info->num_input_vgprs = 0;
4954 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4955 shader_info->num_input_vgprs += 2;
4956 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4957 shader_info->num_input_vgprs += 2;
4958 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4959 shader_info->num_input_vgprs += 2;
4960 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4961 shader_info->num_input_vgprs += 3;
4962 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
4963 shader_info->num_input_vgprs += 2;
4964 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
4965 shader_info->num_input_vgprs += 2;
4966 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
4967 shader_info->num_input_vgprs += 2;
4968 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
4969 shader_info->num_input_vgprs += 1;
4970 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
4971 shader_info->num_input_vgprs += 1;
4972 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
4973 shader_info->num_input_vgprs += 1;
4974 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
4975 shader_info->num_input_vgprs += 1;
4976 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
4977 shader_info->num_input_vgprs += 1;
4978 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
4979 shader_info->num_input_vgprs += 1;
4980 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
4981 shader_info->num_input_vgprs += 1;
4982 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
4983 shader_info->num_input_vgprs += 1;
4984 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
4985 shader_info->num_input_vgprs += 1;
4986 }
4987 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
4988
4989 /* +3 for scratch wave offset and VCC */
4990 config->num_sgprs = MAX2(config->num_sgprs,
4991 shader_info->num_input_sgprs + 3);
4992 }
4993
4994 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
4995 struct ac_shader_binary *binary,
4996 struct ac_shader_config *config,
4997 struct ac_shader_variant_info *shader_info,
4998 struct nir_shader *nir,
4999 const struct ac_nir_compiler_options *options,
5000 bool dump_shader)
5001 {
5002
5003 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5004 options);
5005
5006 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5007 switch (nir->stage) {
5008 case MESA_SHADER_COMPUTE:
5009 for (int i = 0; i < 3; ++i)
5010 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5011 break;
5012 case MESA_SHADER_FRAGMENT:
5013 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5014 break;
5015 case MESA_SHADER_GEOMETRY:
5016 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5017 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5018 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5019 shader_info->gs.invocations = nir->info->gs.invocations;
5020 break;
5021 case MESA_SHADER_VERTEX:
5022 shader_info->vs.as_es = options->key.vs.as_es;
5023 break;
5024 default:
5025 break;
5026 }
5027 }
5028
5029 static void
5030 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5031 {
5032 LLVMValueRef args[9];
5033 args[0] = ctx->gsvs_ring;
5034 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5035 args[3] = ctx->i32zero;
5036 args[4] = ctx->i32one; /* OFFEN */
5037 args[5] = ctx->i32zero; /* IDXEN */
5038 args[6] = ctx->i32one; /* GLC */
5039 args[7] = ctx->i32one; /* SLC */
5040 args[8] = ctx->i32zero; /* TFE */
5041
5042 int idx = 0;
5043 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5044 if (!(ctx->output_mask & (1ull << i)))
5045 continue;
5046
5047 for (unsigned j = 0; j < 4; j++) {
5048 LLVMValueRef value;
5049 args[2] = LLVMConstInt(ctx->i32,
5050 (idx * 4 + j) *
5051 ctx->gs_max_out_vertices * 16 * 4, false);
5052
5053 value = ac_emit_llvm_intrinsic(&ctx->ac,
5054 "llvm.SI.buffer.load.dword.i32.i32",
5055 ctx->i32, args, 9,
5056 AC_FUNC_ATTR_READONLY);
5057
5058 LLVMBuildStore(ctx->builder,
5059 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5060 }
5061 idx++;
5062 }
5063 handle_vs_outputs_post(ctx);
5064 }
5065
5066 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5067 struct nir_shader *geom_shader,
5068 struct ac_shader_binary *binary,
5069 struct ac_shader_config *config,
5070 struct ac_shader_variant_info *shader_info,
5071 const struct ac_nir_compiler_options *options,
5072 bool dump_shader)
5073 {
5074 struct nir_to_llvm_context ctx = {0};
5075 ctx.context = LLVMContextCreate();
5076 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5077 ctx.options = options;
5078 ctx.shader_info = shader_info;
5079
5080 ac_llvm_context_init(&ctx.ac, ctx.context);
5081 ctx.ac.module = ctx.module;
5082
5083 ctx.is_gs_copy_shader = true;
5084 LLVMSetTarget(ctx.module, "amdgcn--");
5085 setup_types(&ctx);
5086
5087 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5088 ctx.ac.builder = ctx.builder;
5089 ctx.stage = MESA_SHADER_VERTEX;
5090
5091 create_function(&ctx);
5092
5093 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5094 ac_setup_rings(&ctx);
5095
5096 nir_foreach_variable(variable, &geom_shader->outputs)
5097 handle_shader_output_decl(&ctx, variable);
5098
5099 ac_gs_copy_shader_emit(&ctx);
5100
5101 LLVMBuildRetVoid(ctx.builder);
5102
5103 ac_llvm_finalize_module(&ctx);
5104
5105 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5106 MESA_SHADER_VERTEX,
5107 dump_shader, options->supports_spill);
5108 }