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radv: fix warning since using common gs emit code
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef gsvs_ring_stride;
87 LLVMValueRef gsvs_num_entries;
88 LLVMValueRef gs2vs_offset;
89 LLVMValueRef gs_wave_id;
90 LLVMValueRef gs_vtx_offset[6];
91 LLVMValueRef gs_prim_id, gs_invocation_id;
92
93 LLVMValueRef esgs_ring;
94 LLVMValueRef gsvs_ring;
95
96 LLVMValueRef prim_mask;
97 LLVMValueRef sample_positions;
98 LLVMValueRef persp_sample, persp_center, persp_centroid;
99 LLVMValueRef linear_sample, linear_center, linear_centroid;
100 LLVMValueRef front_face;
101 LLVMValueRef ancillary;
102 LLVMValueRef frag_pos[4];
103
104 LLVMBasicBlockRef continue_block;
105 LLVMBasicBlockRef break_block;
106
107 LLVMTypeRef i1;
108 LLVMTypeRef i8;
109 LLVMTypeRef i16;
110 LLVMTypeRef i32;
111 LLVMTypeRef i64;
112 LLVMTypeRef v2i32;
113 LLVMTypeRef v3i32;
114 LLVMTypeRef v4i32;
115 LLVMTypeRef v8i32;
116 LLVMTypeRef f64;
117 LLVMTypeRef f32;
118 LLVMTypeRef f16;
119 LLVMTypeRef v2f32;
120 LLVMTypeRef v4f32;
121 LLVMTypeRef v16i8;
122 LLVMTypeRef voidt;
123
124 LLVMValueRef i32zero;
125 LLVMValueRef i32one;
126 LLVMValueRef f32zero;
127 LLVMValueRef f32one;
128 LLVMValueRef v4f32empty;
129
130 unsigned uniform_md_kind;
131 LLVMValueRef empty_md;
132 gl_shader_stage stage;
133
134 LLVMValueRef lds;
135 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
136 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
137
138 LLVMValueRef shared_memory;
139 uint64_t input_mask;
140 uint64_t output_mask;
141 int num_locals;
142 LLVMValueRef *locals;
143 bool has_ddxy;
144 unsigned num_clips;
145 unsigned num_culls;
146
147 bool has_ds_bpermute;
148
149 bool is_gs_copy_shader;
150 LLVMValueRef gs_next_vertex;
151 unsigned gs_max_out_vertices;
152 };
153
154 struct ac_tex_info {
155 LLVMValueRef args[12];
156 int arg_count;
157 LLVMTypeRef dst_type;
158 bool has_offset;
159 };
160
161 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
162 nir_deref_var *deref,
163 enum desc_type desc_type);
164 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
165 {
166 return (index * 4) + chan;
167 }
168
169 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
170 {
171 if (slot == VARYING_SLOT_POS)
172 return 0;
173 if (slot == VARYING_SLOT_PSIZ)
174 return 1;
175 if (slot == VARYING_SLOT_CLIP_DIST0)
176 return 2;
177 if (slot == VARYING_SLOT_CLIP_DIST1)
178 return 3;
179 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
180 return 4 + (slot - VARYING_SLOT_VAR0);
181 unreachable("illegal slot in get unique index\n");
182 }
183
184 static unsigned llvm_get_type_size(LLVMTypeRef type)
185 {
186 LLVMTypeKind kind = LLVMGetTypeKind(type);
187
188 switch (kind) {
189 case LLVMIntegerTypeKind:
190 return LLVMGetIntTypeWidth(type) / 8;
191 case LLVMFloatTypeKind:
192 return 4;
193 case LLVMPointerTypeKind:
194 return 8;
195 case LLVMVectorTypeKind:
196 return LLVMGetVectorSize(type) *
197 llvm_get_type_size(LLVMGetElementType(type));
198 default:
199 assert(0);
200 return 0;
201 }
202 }
203
204 static void set_llvm_calling_convention(LLVMValueRef func,
205 gl_shader_stage stage)
206 {
207 enum radeon_llvm_calling_convention calling_conv;
208
209 switch (stage) {
210 case MESA_SHADER_VERTEX:
211 case MESA_SHADER_TESS_CTRL:
212 case MESA_SHADER_TESS_EVAL:
213 calling_conv = RADEON_LLVM_AMDGPU_VS;
214 break;
215 case MESA_SHADER_GEOMETRY:
216 calling_conv = RADEON_LLVM_AMDGPU_GS;
217 break;
218 case MESA_SHADER_FRAGMENT:
219 calling_conv = RADEON_LLVM_AMDGPU_PS;
220 break;
221 case MESA_SHADER_COMPUTE:
222 calling_conv = RADEON_LLVM_AMDGPU_CS;
223 break;
224 default:
225 unreachable("Unhandle shader type");
226 }
227
228 LLVMSetFunctionCallConv(func, calling_conv);
229 }
230
231 static LLVMValueRef
232 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
233 LLVMBuilderRef builder, LLVMTypeRef *return_types,
234 unsigned num_return_elems, LLVMTypeRef *param_types,
235 unsigned param_count, unsigned array_params_mask,
236 unsigned sgpr_params, bool unsafe_math)
237 {
238 LLVMTypeRef main_function_type, ret_type;
239 LLVMBasicBlockRef main_function_body;
240
241 if (num_return_elems)
242 ret_type = LLVMStructTypeInContext(ctx, return_types,
243 num_return_elems, true);
244 else
245 ret_type = LLVMVoidTypeInContext(ctx);
246
247 /* Setup the function */
248 main_function_type =
249 LLVMFunctionType(ret_type, param_types, param_count, 0);
250 LLVMValueRef main_function =
251 LLVMAddFunction(module, "main", main_function_type);
252 main_function_body =
253 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
254 LLVMPositionBuilderAtEnd(builder, main_function_body);
255
256 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
257 for (unsigned i = 0; i < sgpr_params; ++i) {
258 if (array_params_mask & (1 << i)) {
259 LLVMValueRef P = LLVMGetParam(main_function, i);
260 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
261 ac_add_attr_dereferenceable(P, UINT64_MAX);
262 }
263 else {
264 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
265 }
266 }
267
268 if (unsafe_math) {
269 /* These were copied from some LLVM test. */
270 LLVMAddTargetDependentFunctionAttr(main_function,
271 "less-precise-fpmad",
272 "true");
273 LLVMAddTargetDependentFunctionAttr(main_function,
274 "no-infs-fp-math",
275 "true");
276 LLVMAddTargetDependentFunctionAttr(main_function,
277 "no-nans-fp-math",
278 "true");
279 LLVMAddTargetDependentFunctionAttr(main_function,
280 "unsafe-fp-math",
281 "true");
282 }
283 return main_function;
284 }
285
286 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
287 {
288 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
289 CONST_ADDR_SPACE);
290 }
291
292 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
293 int idx,
294 LLVMTypeRef type)
295 {
296 LLVMValueRef offset;
297 LLVMValueRef ptr;
298 int addr_space;
299
300 offset = LLVMConstInt(ctx->i32, idx, false);
301
302 ptr = ctx->shared_memory;
303 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
304 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
305 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
306 return ptr;
307 }
308
309 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
310 {
311 if (t == ctx->f16 || t == ctx->i16)
312 return ctx->i16;
313 else if (t == ctx->f32 || t == ctx->i32)
314 return ctx->i32;
315 else if (t == ctx->f64 || t == ctx->i64)
316 return ctx->i64;
317 else
318 unreachable("Unhandled integer size");
319 }
320
321 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
322 {
323 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
324 LLVMTypeRef elem_type = LLVMGetElementType(t);
325 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
326 LLVMGetVectorSize(t));
327 }
328 return to_integer_type_scalar(ctx, t);
329 }
330
331 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
332 {
333 LLVMTypeRef type = LLVMTypeOf(v);
334 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
335 }
336
337 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
338 {
339 if (t == ctx->i16 || t == ctx->f16)
340 return ctx->f16;
341 else if (t == ctx->i32 || t == ctx->f32)
342 return ctx->f32;
343 else if (t == ctx->i64 || t == ctx->f64)
344 return ctx->f64;
345 else
346 unreachable("Unhandled float size");
347 }
348
349 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
350 {
351 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
352 LLVMTypeRef elem_type = LLVMGetElementType(t);
353 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
354 LLVMGetVectorSize(t));
355 }
356 return to_float_type_scalar(ctx, t);
357 }
358
359 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
360 {
361 LLVMTypeRef type = LLVMTypeOf(v);
362 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
363 }
364
365 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
401 {
402 ud_info->sgpr_idx = sgpr_idx;
403 ud_info->num_sgprs = num_sgprs;
404 ud_info->indirect = false;
405 ud_info->indirect_offset = 0;
406 }
407
408 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
409 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
410 {
411 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
412 }
413
414 #if 0
415 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
416 uint32_t indirect_offset)
417 {
418 ud_info->sgpr_idx = sgpr_idx;
419 ud_info->num_sgprs = num_sgprs;
420 ud_info->indirect = true;
421 ud_info->indirect_offset = indirect_offset;
422 }
423 #endif
424
425 static void create_function(struct nir_to_llvm_context *ctx)
426 {
427 LLVMTypeRef arg_types[23];
428 unsigned arg_idx = 0;
429 unsigned array_params_mask = 0;
430 unsigned sgpr_count = 0, user_sgpr_count;
431 unsigned i;
432 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
433 unsigned user_sgpr_idx;
434 bool need_push_constants;
435 bool need_ring_offsets = false;
436
437 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
438 if (ctx->stage == MESA_SHADER_GEOMETRY ||
439 ctx->stage == MESA_SHADER_VERTEX ||
440 ctx->is_gs_copy_shader)
441 need_ring_offsets = true;
442
443 need_push_constants = true;
444 if (!ctx->options->layout)
445 need_push_constants = false;
446 else if (!ctx->options->layout->push_constant_size &&
447 !ctx->options->layout->dynamic_offset_count)
448 need_push_constants = false;
449
450 if (need_ring_offsets && !ctx->options->supports_spill) {
451 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
452 }
453
454 /* 1 for each descriptor set */
455 for (unsigned i = 0; i < num_sets; ++i) {
456 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
457 array_params_mask |= (1 << arg_idx);
458 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
459 }
460 }
461
462 if (need_push_constants) {
463 /* 1 for push constants and dynamic descriptors */
464 array_params_mask |= (1 << arg_idx);
465 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
466 }
467
468 switch (ctx->stage) {
469 case MESA_SHADER_COMPUTE:
470 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
471 user_sgpr_count = arg_idx;
472 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
473 arg_types[arg_idx++] = ctx->i32;
474 sgpr_count = arg_idx;
475
476 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
477 break;
478 case MESA_SHADER_VERTEX:
479 if (!ctx->is_gs_copy_shader) {
480 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
481 arg_types[arg_idx++] = ctx->i32; // base vertex
482 arg_types[arg_idx++] = ctx->i32; // start instance
483 arg_types[arg_idx++] = ctx->i32; // draw index
484 }
485 user_sgpr_count = arg_idx;
486 if (ctx->options->key.vs.as_es)
487 arg_types[arg_idx++] = ctx->i32; //es2gs offset
488 sgpr_count = arg_idx;
489 arg_types[arg_idx++] = ctx->i32; // vertex id
490 if (!ctx->is_gs_copy_shader) {
491 arg_types[arg_idx++] = ctx->i32; // rel auto id
492 arg_types[arg_idx++] = ctx->i32; // vs prim id
493 arg_types[arg_idx++] = ctx->i32; // instance id
494 }
495 break;
496 case MESA_SHADER_GEOMETRY:
497 arg_types[arg_idx++] = ctx->i32; // gsvs stride
498 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
499 user_sgpr_count = arg_idx;
500 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
501 arg_types[arg_idx++] = ctx->i32; // wave id
502 sgpr_count = arg_idx;
503 arg_types[arg_idx++] = ctx->i32; // vtx0
504 arg_types[arg_idx++] = ctx->i32; // vtx1
505 arg_types[arg_idx++] = ctx->i32; // prim id
506 arg_types[arg_idx++] = ctx->i32; // vtx2
507 arg_types[arg_idx++] = ctx->i32; // vtx3
508 arg_types[arg_idx++] = ctx->i32; // vtx4
509 arg_types[arg_idx++] = ctx->i32; // vtx5
510 arg_types[arg_idx++] = ctx->i32; // GS instance id
511 break;
512 case MESA_SHADER_FRAGMENT:
513 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
514 user_sgpr_count = arg_idx;
515 arg_types[arg_idx++] = ctx->i32; /* prim mask */
516 sgpr_count = arg_idx;
517 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
518 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
519 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
520 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
521 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
522 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
523 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
524 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
525 arg_types[arg_idx++] = ctx->f32; /* pos x float */
526 arg_types[arg_idx++] = ctx->f32; /* pos y float */
527 arg_types[arg_idx++] = ctx->f32; /* pos z float */
528 arg_types[arg_idx++] = ctx->f32; /* pos w float */
529 arg_types[arg_idx++] = ctx->i32; /* front face */
530 arg_types[arg_idx++] = ctx->i32; /* ancillary */
531 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
532 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
533 break;
534 default:
535 unreachable("Shader stage not implemented");
536 }
537
538 ctx->main_function = create_llvm_function(
539 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
540 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
541 set_llvm_calling_convention(ctx->main_function, ctx->stage);
542
543 ctx->shader_info->num_input_sgprs = 0;
544 ctx->shader_info->num_input_vgprs = 0;
545
546 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
547 for (i = 0; i < user_sgpr_count; i++)
548 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
549
550 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
551 for (; i < sgpr_count; i++)
552 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
553
554 if (ctx->stage != MESA_SHADER_FRAGMENT)
555 for (; i < arg_idx; ++i)
556 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
557
558 arg_idx = 0;
559 user_sgpr_idx = 0;
560
561 if (ctx->options->supports_spill || need_ring_offsets) {
562 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
563 user_sgpr_idx += 2;
564 if (ctx->options->supports_spill) {
565 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
566 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
567 NULL, 0, AC_FUNC_ATTR_READNONE);
568 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
569 const_array(ctx->v16i8, 8), "");
570 } else
571 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
572 }
573
574 for (unsigned i = 0; i < num_sets; ++i) {
575 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
576 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
577 user_sgpr_idx += 2;
578 ctx->descriptor_sets[i] =
579 LLVMGetParam(ctx->main_function, arg_idx++);
580 } else
581 ctx->descriptor_sets[i] = NULL;
582 }
583
584 if (need_push_constants) {
585 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
586 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
587 user_sgpr_idx += 2;
588 }
589
590 switch (ctx->stage) {
591 case MESA_SHADER_COMPUTE:
592 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
593 user_sgpr_idx += 3;
594 ctx->num_work_groups =
595 LLVMGetParam(ctx->main_function, arg_idx++);
596 ctx->workgroup_ids =
597 LLVMGetParam(ctx->main_function, arg_idx++);
598 ctx->tg_size =
599 LLVMGetParam(ctx->main_function, arg_idx++);
600 ctx->local_invocation_ids =
601 LLVMGetParam(ctx->main_function, arg_idx++);
602 break;
603 case MESA_SHADER_VERTEX:
604 if (!ctx->is_gs_copy_shader) {
605 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
606 user_sgpr_idx += 2;
607 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
608 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
609 user_sgpr_idx += 3;
610 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
611 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
612 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
613 }
614 if (ctx->options->key.vs.as_es)
615 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
616 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
617 if (!ctx->is_gs_copy_shader) {
618 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
619 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
620 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
621 }
622 break;
623 case MESA_SHADER_GEOMETRY:
624 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
625 user_sgpr_idx += 2;
626 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
627 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
628 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
629 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
630 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
631 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
632 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
633 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
635 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
636 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
638 break;
639 case MESA_SHADER_FRAGMENT:
640 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
641 user_sgpr_idx += 2;
642 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
643 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
644 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
645 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
646 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
647 arg_idx++;
648 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
651 arg_idx++; /* line stipple */
652 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
653 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
655 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
656 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
657 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
658 break;
659 default:
660 unreachable("Shader stage not implemented");
661 }
662 }
663
664 static void setup_types(struct nir_to_llvm_context *ctx)
665 {
666 LLVMValueRef args[4];
667
668 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
669 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
670 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
671 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
672 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
673 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
674 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
675 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
676 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
677 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
678 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
679 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
680 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
681 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
682 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
683 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
684
685 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
686 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
687 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
688 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
689
690 args[0] = ctx->f32zero;
691 args[1] = ctx->f32zero;
692 args[2] = ctx->f32zero;
693 args[3] = ctx->f32one;
694 ctx->v4f32empty = LLVMConstVector(args, 4);
695
696 ctx->uniform_md_kind =
697 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
698 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
699
700 args[0] = LLVMConstReal(ctx->f32, 2.5);
701 }
702
703 static int get_llvm_num_components(LLVMValueRef value)
704 {
705 LLVMTypeRef type = LLVMTypeOf(value);
706 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
707 ? LLVMGetVectorSize(type)
708 : 1;
709 return num_components;
710 }
711
712 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
713 LLVMValueRef value,
714 int index)
715 {
716 int count = get_llvm_num_components(value);
717
718 assert(index < count);
719 if (count == 1)
720 return value;
721
722 return LLVMBuildExtractElement(ctx->builder, value,
723 LLVMConstInt(ctx->i32, index, false), "");
724 }
725
726 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
727 LLVMValueRef value, unsigned count)
728 {
729 unsigned num_components = get_llvm_num_components(value);
730 if (count == num_components)
731 return value;
732
733 LLVMValueRef masks[] = {
734 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
735 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
736
737 if (count == 1)
738 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
739 "");
740
741 LLVMValueRef swizzle = LLVMConstVector(masks, count);
742 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
743 }
744
745 static void
746 build_store_values_extended(struct nir_to_llvm_context *ctx,
747 LLVMValueRef *values,
748 unsigned value_count,
749 unsigned value_stride,
750 LLVMValueRef vec)
751 {
752 LLVMBuilderRef builder = ctx->builder;
753 unsigned i;
754
755 if (value_count == 1) {
756 LLVMBuildStore(builder, vec, values[0]);
757 return;
758 }
759
760 for (i = 0; i < value_count; i++) {
761 LLVMValueRef ptr = values[i * value_stride];
762 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
763 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
764 LLVMBuildStore(builder, value, ptr);
765 }
766 }
767
768 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
769 nir_ssa_def *def)
770 {
771 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
772 if (def->num_components > 1) {
773 type = LLVMVectorType(type, def->num_components);
774 }
775 return type;
776 }
777
778 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
779 {
780 assert(src.is_ssa);
781 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
782 return (LLVMValueRef)entry->data;
783 }
784
785
786 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
787 struct nir_block *b)
788 {
789 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
790 return (LLVMBasicBlockRef)entry->data;
791 }
792
793 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
794 nir_alu_src src,
795 unsigned num_components)
796 {
797 LLVMValueRef value = get_src(ctx, src.src);
798 bool need_swizzle = false;
799
800 assert(value);
801 LLVMTypeRef type = LLVMTypeOf(value);
802 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
803 ? LLVMGetVectorSize(type)
804 : 1;
805
806 for (unsigned i = 0; i < num_components; ++i) {
807 assert(src.swizzle[i] < src_components);
808 if (src.swizzle[i] != i)
809 need_swizzle = true;
810 }
811
812 if (need_swizzle || num_components != src_components) {
813 LLVMValueRef masks[] = {
814 LLVMConstInt(ctx->i32, src.swizzle[0], false),
815 LLVMConstInt(ctx->i32, src.swizzle[1], false),
816 LLVMConstInt(ctx->i32, src.swizzle[2], false),
817 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
818
819 if (src_components > 1 && num_components == 1) {
820 value = LLVMBuildExtractElement(ctx->builder, value,
821 masks[0], "");
822 } else if (src_components == 1 && num_components > 1) {
823 LLVMValueRef values[] = {value, value, value, value};
824 value = ac_build_gather_values(&ctx->ac, values, num_components);
825 } else {
826 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
827 value = LLVMBuildShuffleVector(ctx->builder, value, value,
828 swizzle, "");
829 }
830 }
831 assert(!src.negate);
832 assert(!src.abs);
833 return value;
834 }
835
836 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
837 LLVMIntPredicate pred, LLVMValueRef src0,
838 LLVMValueRef src1)
839 {
840 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
841 return LLVMBuildSelect(ctx->builder, result,
842 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
843 LLVMConstInt(ctx->i32, 0, false), "");
844 }
845
846 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
847 LLVMRealPredicate pred, LLVMValueRef src0,
848 LLVMValueRef src1)
849 {
850 LLVMValueRef result;
851 src0 = to_float(ctx, src0);
852 src1 = to_float(ctx, src1);
853 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
854 return LLVMBuildSelect(ctx->builder, result,
855 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
856 LLVMConstInt(ctx->i32, 0, false), "");
857 }
858
859 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
860 const char *intrin,
861 LLVMTypeRef result_type,
862 LLVMValueRef src0)
863 {
864 char name[64];
865 LLVMValueRef params[] = {
866 to_float(ctx, src0),
867 };
868
869 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
870 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
871 }
872
873 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
874 const char *intrin,
875 LLVMTypeRef result_type,
876 LLVMValueRef src0, LLVMValueRef src1)
877 {
878 char name[64];
879 LLVMValueRef params[] = {
880 to_float(ctx, src0),
881 to_float(ctx, src1),
882 };
883
884 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
885 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
886 }
887
888 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
889 const char *intrin,
890 LLVMTypeRef result_type,
891 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
892 {
893 char name[64];
894 LLVMValueRef params[] = {
895 to_float(ctx, src0),
896 to_float(ctx, src1),
897 to_float(ctx, src2),
898 };
899
900 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
901 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
902 }
903
904 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
905 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
906 {
907 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
908 ctx->i32zero, "");
909 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
910 }
911
912 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
913 LLVMValueRef src0)
914 {
915 LLVMValueRef params[2] = {
916 src0,
917
918 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
919 * add special code to check for x=0. The reason is that
920 * the LLVM behavior for x=0 is different from what we
921 * need here.
922 *
923 * The hardware already implements the correct behavior.
924 */
925 LLVMConstInt(ctx->i32, 1, false),
926 };
927 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
928 }
929
930 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
931 LLVMValueRef src0)
932 {
933 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.flbit.i32",
934 ctx->i32, &src0, 1,
935 AC_FUNC_ATTR_READNONE);
936
937 /* The HW returns the last bit index from MSB, but NIR wants
938 * the index from LSB. Invert it by doing "31 - msb". */
939 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
940 msb, "");
941
942 LLVMValueRef all_ones = LLVMConstInt(ctx->i32, -1, true);
943 LLVMValueRef cond = LLVMBuildOr(ctx->builder,
944 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
945 src0, ctx->i32zero, ""),
946 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
947 src0, all_ones, ""), "");
948
949 return LLVMBuildSelect(ctx->builder, cond, all_ones, msb, "");
950 }
951
952 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
953 LLVMValueRef src0)
954 {
955 LLVMValueRef args[2] = {
956 src0,
957 ctx->i32one,
958 };
959 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctlz.i32",
960 ctx->i32, args, ARRAY_SIZE(args),
961 AC_FUNC_ATTR_READNONE);
962
963 /* The HW returns the last bit index from MSB, but NIR wants
964 * the index from LSB. Invert it by doing "31 - msb". */
965 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
966 msb, "");
967
968 return LLVMBuildSelect(ctx->builder,
969 LLVMBuildICmp(ctx->builder, LLVMIntEQ, src0,
970 ctx->i32zero, ""),
971 LLVMConstInt(ctx->i32, -1, true), msb, "");
972 }
973
974 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
975 LLVMIntPredicate pred,
976 LLVMValueRef src0, LLVMValueRef src1)
977 {
978 return LLVMBuildSelect(ctx->builder,
979 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
980 src0,
981 src1, "");
982
983 }
984 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
985 LLVMValueRef src0)
986 {
987 return emit_minmax_int(ctx, LLVMIntSGT, src0,
988 LLVMBuildNeg(ctx->builder, src0, ""));
989 }
990
991 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
992 LLVMValueRef src0)
993 {
994 LLVMValueRef cmp, val;
995
996 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
997 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
998 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
999 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1000 return val;
1001 }
1002
1003 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1004 LLVMValueRef src0)
1005 {
1006 LLVMValueRef cmp, val;
1007
1008 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1009 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1010 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1011 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1012 return val;
1013 }
1014
1015 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1016 LLVMValueRef src0)
1017 {
1018 const char *intr = "llvm.floor.f32";
1019 LLVMValueRef fsrc0 = to_float(ctx, src0);
1020 LLVMValueRef params[] = {
1021 fsrc0,
1022 };
1023 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
1024 ctx->f32, params, 1,
1025 AC_FUNC_ATTR_READNONE);
1026 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1027 }
1028
1029 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1030 const char *intrin,
1031 LLVMValueRef src0, LLVMValueRef src1)
1032 {
1033 LLVMTypeRef ret_type;
1034 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1035 LLVMValueRef res;
1036 LLVMValueRef params[] = { src0, src1 };
1037 ret_type = LLVMStructTypeInContext(ctx->context, types,
1038 2, true);
1039
1040 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1041 params, 2, AC_FUNC_ATTR_READNONE);
1042
1043 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1044 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1045 return res;
1046 }
1047
1048 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1049 LLVMValueRef src0)
1050 {
1051 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1052 }
1053
1054 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1055 LLVMValueRef src0, LLVMValueRef src1)
1056 {
1057 LLVMValueRef dst64, result;
1058 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1059 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1060
1061 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1062 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1063 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1064 return result;
1065 }
1066
1067 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1068 LLVMValueRef src0, LLVMValueRef src1)
1069 {
1070 LLVMValueRef dst64, result;
1071 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1072 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1073
1074 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1075 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1076 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1077 return result;
1078 }
1079
1080 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1081 const char *intrin,
1082 LLVMValueRef srcs[3])
1083 {
1084 LLVMValueRef result;
1085 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1086 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1087
1088 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1089 return result;
1090 }
1091
1092 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1093 LLVMValueRef src0, LLVMValueRef src1,
1094 LLVMValueRef src2, LLVMValueRef src3)
1095 {
1096 LLVMValueRef bfi_args[3], result;
1097
1098 bfi_args[0] = LLVMBuildShl(ctx->builder,
1099 LLVMBuildSub(ctx->builder,
1100 LLVMBuildShl(ctx->builder,
1101 ctx->i32one,
1102 src3, ""),
1103 ctx->i32one, ""),
1104 src2, "");
1105 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1106 bfi_args[2] = src0;
1107
1108 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1109
1110 /* Calculate:
1111 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1112 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1113 */
1114 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1115 LLVMBuildAnd(ctx->builder, bfi_args[0],
1116 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1117
1118 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1119 return result;
1120 }
1121
1122 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1123 LLVMValueRef src0)
1124 {
1125 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1126 int i;
1127 LLVMValueRef comp[2];
1128
1129 src0 = to_float(ctx, src0);
1130 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1131 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1132 for (i = 0; i < 2; i++) {
1133 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1134 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1135 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1136 }
1137
1138 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1139 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1140
1141 return comp[0];
1142 }
1143
1144 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1145 LLVMValueRef src0)
1146 {
1147 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1148 LLVMValueRef temps[2], result, val;
1149 int i;
1150
1151 for (i = 0; i < 2; i++) {
1152 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1153 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1154 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1155 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1156 }
1157
1158 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1159 ctx->i32zero, "");
1160 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1161 ctx->i32one, "");
1162 return result;
1163 }
1164
1165 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1166 nir_op op,
1167 LLVMValueRef src0)
1168 {
1169 unsigned mask;
1170 int idx;
1171 LLVMValueRef result;
1172 ctx->has_ddxy = true;
1173
1174 if (!ctx->lds && !ctx->has_ds_bpermute)
1175 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1176 LLVMArrayType(ctx->i32, 64),
1177 "ddxy_lds", LOCAL_ADDR_SPACE);
1178
1179 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1180 mask = AC_TID_MASK_LEFT;
1181 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1182 mask = AC_TID_MASK_TOP;
1183 else
1184 mask = AC_TID_MASK_TOP_LEFT;
1185
1186 /* for DDX we want to next X pixel, DDY next Y pixel. */
1187 if (op == nir_op_fddx_fine ||
1188 op == nir_op_fddx_coarse ||
1189 op == nir_op_fddx)
1190 idx = 1;
1191 else
1192 idx = 2;
1193
1194 result = ac_emit_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1195 mask, idx, ctx->lds,
1196 src0);
1197 return result;
1198 }
1199
1200 /*
1201 * this takes an I,J coordinate pair,
1202 * and works out the X and Y derivatives.
1203 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1204 */
1205 static LLVMValueRef emit_ddxy_interp(
1206 struct nir_to_llvm_context *ctx,
1207 LLVMValueRef interp_ij)
1208 {
1209 LLVMValueRef result[4], a;
1210 unsigned i;
1211
1212 for (i = 0; i < 2; i++) {
1213 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1214 LLVMConstInt(ctx->i32, i, false), "");
1215 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1216 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1217 }
1218 return ac_build_gather_values(&ctx->ac, result, 4);
1219 }
1220
1221 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1222 {
1223 LLVMValueRef src[4], result = NULL;
1224 unsigned num_components = instr->dest.dest.ssa.num_components;
1225 unsigned src_components;
1226 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1227
1228 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1229 switch (instr->op) {
1230 case nir_op_vec2:
1231 case nir_op_vec3:
1232 case nir_op_vec4:
1233 src_components = 1;
1234 break;
1235 case nir_op_pack_half_2x16:
1236 src_components = 2;
1237 break;
1238 case nir_op_unpack_half_2x16:
1239 src_components = 1;
1240 break;
1241 default:
1242 src_components = num_components;
1243 break;
1244 }
1245 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1246 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1247
1248 switch (instr->op) {
1249 case nir_op_fmov:
1250 case nir_op_imov:
1251 result = src[0];
1252 break;
1253 case nir_op_fneg:
1254 src[0] = to_float(ctx, src[0]);
1255 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1256 break;
1257 case nir_op_ineg:
1258 result = LLVMBuildNeg(ctx->builder, src[0], "");
1259 break;
1260 case nir_op_inot:
1261 result = LLVMBuildNot(ctx->builder, src[0], "");
1262 break;
1263 case nir_op_iadd:
1264 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1265 break;
1266 case nir_op_fadd:
1267 src[0] = to_float(ctx, src[0]);
1268 src[1] = to_float(ctx, src[1]);
1269 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1270 break;
1271 case nir_op_fsub:
1272 src[0] = to_float(ctx, src[0]);
1273 src[1] = to_float(ctx, src[1]);
1274 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1275 break;
1276 case nir_op_isub:
1277 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1278 break;
1279 case nir_op_imul:
1280 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1281 break;
1282 case nir_op_imod:
1283 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1284 break;
1285 case nir_op_umod:
1286 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1287 break;
1288 case nir_op_fmod:
1289 src[0] = to_float(ctx, src[0]);
1290 src[1] = to_float(ctx, src[1]);
1291 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1292 result = emit_intrin_1f_param(ctx, "llvm.floor",
1293 to_float_type(ctx, def_type), result);
1294 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1295 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1296 break;
1297 case nir_op_frem:
1298 src[0] = to_float(ctx, src[0]);
1299 src[1] = to_float(ctx, src[1]);
1300 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1301 break;
1302 case nir_op_irem:
1303 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1304 break;
1305 case nir_op_idiv:
1306 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1307 break;
1308 case nir_op_udiv:
1309 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1310 break;
1311 case nir_op_fmul:
1312 src[0] = to_float(ctx, src[0]);
1313 src[1] = to_float(ctx, src[1]);
1314 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1315 break;
1316 case nir_op_fdiv:
1317 src[0] = to_float(ctx, src[0]);
1318 src[1] = to_float(ctx, src[1]);
1319 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1320 break;
1321 case nir_op_frcp:
1322 src[0] = to_float(ctx, src[0]);
1323 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1324 break;
1325 case nir_op_iand:
1326 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1327 break;
1328 case nir_op_ior:
1329 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1330 break;
1331 case nir_op_ixor:
1332 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1333 break;
1334 case nir_op_ishl:
1335 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1336 break;
1337 case nir_op_ishr:
1338 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1339 break;
1340 case nir_op_ushr:
1341 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1342 break;
1343 case nir_op_ilt:
1344 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1345 break;
1346 case nir_op_ine:
1347 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1348 break;
1349 case nir_op_ieq:
1350 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1351 break;
1352 case nir_op_ige:
1353 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1354 break;
1355 case nir_op_ult:
1356 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1357 break;
1358 case nir_op_uge:
1359 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1360 break;
1361 case nir_op_feq:
1362 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1363 break;
1364 case nir_op_fne:
1365 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1366 break;
1367 case nir_op_flt:
1368 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1369 break;
1370 case nir_op_fge:
1371 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1372 break;
1373 case nir_op_fabs:
1374 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1375 to_float_type(ctx, def_type), src[0]);
1376 break;
1377 case nir_op_iabs:
1378 result = emit_iabs(ctx, src[0]);
1379 break;
1380 case nir_op_imax:
1381 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1382 break;
1383 case nir_op_imin:
1384 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1385 break;
1386 case nir_op_umax:
1387 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1388 break;
1389 case nir_op_umin:
1390 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1391 break;
1392 case nir_op_isign:
1393 result = emit_isign(ctx, src[0]);
1394 break;
1395 case nir_op_fsign:
1396 src[0] = to_float(ctx, src[0]);
1397 result = emit_fsign(ctx, src[0]);
1398 break;
1399 case nir_op_ffloor:
1400 result = emit_intrin_1f_param(ctx, "llvm.floor",
1401 to_float_type(ctx, def_type), src[0]);
1402 break;
1403 case nir_op_ftrunc:
1404 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1405 to_float_type(ctx, def_type), src[0]);
1406 break;
1407 case nir_op_fceil:
1408 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1409 to_float_type(ctx, def_type), src[0]);
1410 break;
1411 case nir_op_fround_even:
1412 result = emit_intrin_1f_param(ctx, "llvm.rint",
1413 to_float_type(ctx, def_type),src[0]);
1414 break;
1415 case nir_op_ffract:
1416 result = emit_ffract(ctx, src[0]);
1417 break;
1418 case nir_op_fsin:
1419 result = emit_intrin_1f_param(ctx, "llvm.sin",
1420 to_float_type(ctx, def_type), src[0]);
1421 break;
1422 case nir_op_fcos:
1423 result = emit_intrin_1f_param(ctx, "llvm.cos",
1424 to_float_type(ctx, def_type), src[0]);
1425 break;
1426 case nir_op_fsqrt:
1427 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1428 to_float_type(ctx, def_type), src[0]);
1429 break;
1430 case nir_op_fexp2:
1431 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1432 to_float_type(ctx, def_type), src[0]);
1433 break;
1434 case nir_op_flog2:
1435 result = emit_intrin_1f_param(ctx, "llvm.log2",
1436 to_float_type(ctx, def_type), src[0]);
1437 break;
1438 case nir_op_frsq:
1439 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1440 to_float_type(ctx, def_type), src[0]);
1441 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1442 break;
1443 case nir_op_fpow:
1444 result = emit_intrin_2f_param(ctx, "llvm.pow",
1445 to_float_type(ctx, def_type), src[0], src[1]);
1446 break;
1447 case nir_op_fmax:
1448 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1449 to_float_type(ctx, def_type), src[0], src[1]);
1450 break;
1451 case nir_op_fmin:
1452 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1453 to_float_type(ctx, def_type), src[0], src[1]);
1454 break;
1455 case nir_op_ffma:
1456 result = emit_intrin_3f_param(ctx, "llvm.fma",
1457 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1458 break;
1459 case nir_op_ibitfield_extract:
1460 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1461 break;
1462 case nir_op_ubitfield_extract:
1463 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1464 break;
1465 case nir_op_bitfield_insert:
1466 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1467 break;
1468 case nir_op_bitfield_reverse:
1469 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1470 break;
1471 case nir_op_bit_count:
1472 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1473 break;
1474 case nir_op_vec2:
1475 case nir_op_vec3:
1476 case nir_op_vec4:
1477 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1478 src[i] = to_integer(ctx, src[i]);
1479 result = ac_build_gather_values(&ctx->ac, src, num_components);
1480 break;
1481 case nir_op_d2i:
1482 case nir_op_f2i:
1483 src[0] = to_float(ctx, src[0]);
1484 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1485 break;
1486 case nir_op_d2u:
1487 case nir_op_f2u:
1488 src[0] = to_float(ctx, src[0]);
1489 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1490 break;
1491 case nir_op_i2d:
1492 case nir_op_i2f:
1493 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1494 break;
1495 case nir_op_u2d:
1496 case nir_op_u2f:
1497 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1498 break;
1499 case nir_op_f2d:
1500 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1501 break;
1502 case nir_op_d2f:
1503 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1504 break;
1505 case nir_op_bcsel:
1506 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1507 break;
1508 case nir_op_find_lsb:
1509 result = emit_find_lsb(ctx, src[0]);
1510 break;
1511 case nir_op_ufind_msb:
1512 result = emit_ufind_msb(ctx, src[0]);
1513 break;
1514 case nir_op_ifind_msb:
1515 result = emit_ifind_msb(ctx, src[0]);
1516 break;
1517 case nir_op_uadd_carry:
1518 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1519 break;
1520 case nir_op_usub_borrow:
1521 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1522 break;
1523 case nir_op_b2f:
1524 result = emit_b2f(ctx, src[0]);
1525 break;
1526 case nir_op_fquantize2f16:
1527 src[0] = to_float(ctx, src[0]);
1528 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1529 /* need to convert back up to f32 */
1530 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1531 break;
1532 case nir_op_umul_high:
1533 result = emit_umul_high(ctx, src[0], src[1]);
1534 break;
1535 case nir_op_imul_high:
1536 result = emit_imul_high(ctx, src[0], src[1]);
1537 break;
1538 case nir_op_pack_half_2x16:
1539 result = emit_pack_half_2x16(ctx, src[0]);
1540 break;
1541 case nir_op_unpack_half_2x16:
1542 result = emit_unpack_half_2x16(ctx, src[0]);
1543 break;
1544 case nir_op_fddx:
1545 case nir_op_fddy:
1546 case nir_op_fddx_fine:
1547 case nir_op_fddy_fine:
1548 case nir_op_fddx_coarse:
1549 case nir_op_fddy_coarse:
1550 result = emit_ddxy(ctx, instr->op, src[0]);
1551 break;
1552 default:
1553 fprintf(stderr, "Unknown NIR alu instr: ");
1554 nir_print_instr(&instr->instr, stderr);
1555 fprintf(stderr, "\n");
1556 abort();
1557 }
1558
1559 if (result) {
1560 assert(instr->dest.dest.is_ssa);
1561 result = to_integer(ctx, result);
1562 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1563 result);
1564 }
1565 }
1566
1567 static void visit_load_const(struct nir_to_llvm_context *ctx,
1568 nir_load_const_instr *instr)
1569 {
1570 LLVMValueRef values[4], value = NULL;
1571 LLVMTypeRef element_type =
1572 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1573
1574 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1575 switch (instr->def.bit_size) {
1576 case 32:
1577 values[i] = LLVMConstInt(element_type,
1578 instr->value.u32[i], false);
1579 break;
1580 case 64:
1581 values[i] = LLVMConstInt(element_type,
1582 instr->value.u64[i], false);
1583 break;
1584 default:
1585 fprintf(stderr,
1586 "unsupported nir load_const bit_size: %d\n",
1587 instr->def.bit_size);
1588 abort();
1589 }
1590 }
1591 if (instr->def.num_components > 1) {
1592 value = LLVMConstVector(values, instr->def.num_components);
1593 } else
1594 value = values[0];
1595
1596 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1597 }
1598
1599 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1600 LLVMTypeRef type)
1601 {
1602 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1603 return LLVMBuildBitCast(ctx->builder, ptr,
1604 LLVMPointerType(type, addr_space), "");
1605 }
1606
1607 static LLVMValueRef
1608 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1609 {
1610 LLVMValueRef size =
1611 LLVMBuildExtractElement(ctx->builder, descriptor,
1612 LLVMConstInt(ctx->i32, 2, false), "");
1613
1614 /* VI only */
1615 if (ctx->options->chip_class >= VI && in_elements) {
1616 /* On VI, the descriptor contains the size in bytes,
1617 * but TXQ must return the size in elements.
1618 * The stride is always non-zero for resources using TXQ.
1619 */
1620 LLVMValueRef stride =
1621 LLVMBuildExtractElement(ctx->builder, descriptor,
1622 LLVMConstInt(ctx->i32, 1, false), "");
1623 stride = LLVMBuildLShr(ctx->builder, stride,
1624 LLVMConstInt(ctx->i32, 16, false), "");
1625 stride = LLVMBuildAnd(ctx->builder, stride,
1626 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1627
1628 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1629 }
1630 return size;
1631 }
1632
1633 /**
1634 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1635 * intrinsic names).
1636 */
1637 static void build_int_type_name(
1638 LLVMTypeRef type,
1639 char *buf, unsigned bufsize)
1640 {
1641 assert(bufsize >= 6);
1642
1643 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1644 snprintf(buf, bufsize, "v%ui32",
1645 LLVMGetVectorSize(type));
1646 else
1647 strcpy(buf, "i32");
1648 }
1649
1650 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1651 struct ac_tex_info *tinfo,
1652 nir_tex_instr *instr,
1653 const char *intr_name,
1654 unsigned coord_vgpr_index)
1655 {
1656 LLVMValueRef coord = tinfo->args[0];
1657 LLVMValueRef half_texel[2];
1658 int c;
1659
1660 //TODO Rect
1661 {
1662 LLVMValueRef txq_args[10];
1663 int txq_arg_count = 0;
1664 LLVMValueRef size;
1665 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1666 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1667 txq_args[txq_arg_count++] = tinfo->args[1];
1668 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1669 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1670 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1671 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1672 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1673 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1674 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1675 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1676 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1677 txq_args, txq_arg_count,
1678 AC_FUNC_ATTR_READNONE);
1679
1680 for (c = 0; c < 2; c++) {
1681 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1682 LLVMConstInt(ctx->i32, c, false), "");
1683 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1684 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1685 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1686 LLVMConstReal(ctx->f32, -0.5), "");
1687 }
1688 }
1689
1690 for (c = 0; c < 2; c++) {
1691 LLVMValueRef tmp;
1692 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1693 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1694 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1695 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1696 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1697 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1698 }
1699
1700 tinfo->args[0] = coord;
1701 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1702 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1703
1704 }
1705
1706 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1707 nir_tex_instr *instr,
1708 struct ac_tex_info *tinfo)
1709 {
1710 const char *name = "llvm.SI.image.sample";
1711 const char *infix = "";
1712 char intr_name[127];
1713 char type[64];
1714 bool is_shadow = instr->is_shadow;
1715 bool has_offset = tinfo->has_offset;
1716 switch (instr->op) {
1717 case nir_texop_txf:
1718 case nir_texop_txf_ms:
1719 case nir_texop_samples_identical:
1720 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1721 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1722 "llvm.SI.image.load.mip";
1723 is_shadow = false;
1724 has_offset = false;
1725 break;
1726 case nir_texop_txb:
1727 infix = ".b";
1728 break;
1729 case nir_texop_txl:
1730 infix = ".l";
1731 break;
1732 case nir_texop_txs:
1733 name = "llvm.SI.getresinfo";
1734 break;
1735 case nir_texop_query_levels:
1736 name = "llvm.SI.getresinfo";
1737 break;
1738 case nir_texop_tex:
1739 if (ctx->stage != MESA_SHADER_FRAGMENT)
1740 infix = ".lz";
1741 break;
1742 case nir_texop_txd:
1743 infix = ".d";
1744 break;
1745 case nir_texop_tg4:
1746 name = "llvm.SI.gather4";
1747 infix = ".lz";
1748 break;
1749 case nir_texop_lod:
1750 name = "llvm.SI.getlod";
1751 is_shadow = false;
1752 has_offset = false;
1753 break;
1754 default:
1755 break;
1756 }
1757
1758 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1759 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1760 has_offset ? ".o" : "", type);
1761
1762 if (instr->op == nir_texop_tg4) {
1763 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1764 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1765 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1766 (int)has_offset + (int)is_shadow);
1767 }
1768 }
1769 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1770 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1771
1772 }
1773
1774 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1775 nir_intrinsic_instr *instr)
1776 {
1777 LLVMValueRef index = get_src(ctx, instr->src[0]);
1778 unsigned desc_set = nir_intrinsic_desc_set(instr);
1779 unsigned binding = nir_intrinsic_binding(instr);
1780 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1781 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1782 unsigned base_offset = layout->binding[binding].offset;
1783 LLVMValueRef offset, stride;
1784
1785 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1786 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1787 desc_ptr = ctx->push_constants;
1788 base_offset = ctx->options->layout->push_constant_size;
1789 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1790 stride = LLVMConstInt(ctx->i32, 16, false);
1791 } else
1792 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1793
1794 offset = LLVMConstInt(ctx->i32, base_offset, false);
1795 index = LLVMBuildMul(ctx->builder, index, stride, "");
1796 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1797
1798 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1799 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1800 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1801
1802 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1803 }
1804
1805 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1806 nir_intrinsic_instr *instr)
1807 {
1808 LLVMValueRef ptr, addr;
1809
1810 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1811 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1812
1813 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1814 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1815
1816 return LLVMBuildLoad(ctx->builder, ptr, "");
1817 }
1818
1819 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1820 nir_intrinsic_instr *instr)
1821 {
1822 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1823
1824 return get_buffer_size(ctx, desc, false);
1825 }
1826 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1827 nir_intrinsic_instr *instr)
1828 {
1829 const char *store_name;
1830 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1831 LLVMTypeRef data_type = ctx->f32;
1832 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1833 int components_32bit = elem_size_mult * instr->num_components;
1834 unsigned writemask = nir_intrinsic_write_mask(instr);
1835 LLVMValueRef base_data, base_offset;
1836 LLVMValueRef params[6];
1837
1838 if (ctx->stage == MESA_SHADER_FRAGMENT)
1839 ctx->shader_info->fs.writes_memory = true;
1840
1841 params[1] = get_src(ctx, instr->src[1]);
1842 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1843 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1844 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1845
1846 if (components_32bit > 1)
1847 data_type = LLVMVectorType(ctx->f32, components_32bit);
1848
1849 base_data = to_float(ctx, src_data);
1850 base_data = trim_vector(ctx, base_data, instr->num_components);
1851 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1852 data_type, "");
1853 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1854 while (writemask) {
1855 int start, count;
1856 LLVMValueRef data;
1857 LLVMValueRef offset;
1858 LLVMValueRef tmp;
1859 u_bit_scan_consecutive_range(&writemask, &start, &count);
1860
1861 /* Due to an LLVM limitation, split 3-element writes
1862 * into a 2-element and a 1-element write. */
1863 if (count == 3) {
1864 writemask |= 1 << (start + 2);
1865 count = 2;
1866 }
1867
1868 start *= elem_size_mult;
1869 count *= elem_size_mult;
1870
1871 if (count > 4) {
1872 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1873 count = 4;
1874 }
1875
1876 if (count == 4) {
1877 store_name = "llvm.amdgcn.buffer.store.v4f32";
1878 data = base_data;
1879 } else if (count == 2) {
1880 tmp = LLVMBuildExtractElement(ctx->builder,
1881 base_data, LLVMConstInt(ctx->i32, start, false), "");
1882 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1883 ctx->i32zero, "");
1884
1885 tmp = LLVMBuildExtractElement(ctx->builder,
1886 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1887 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1888 ctx->i32one, "");
1889 store_name = "llvm.amdgcn.buffer.store.v2f32";
1890
1891 } else {
1892 assert(count == 1);
1893 if (get_llvm_num_components(base_data) > 1)
1894 data = LLVMBuildExtractElement(ctx->builder, base_data,
1895 LLVMConstInt(ctx->i32, start, false), "");
1896 else
1897 data = base_data;
1898 store_name = "llvm.amdgcn.buffer.store.f32";
1899 }
1900
1901 offset = base_offset;
1902 if (start != 0) {
1903 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1904 }
1905 params[0] = data;
1906 params[3] = offset;
1907 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1908 ctx->voidt, params, 6, 0);
1909 }
1910 }
1911
1912 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1913 nir_intrinsic_instr *instr)
1914 {
1915 const char *name;
1916 LLVMValueRef params[6];
1917 int arg_count = 0;
1918 if (ctx->stage == MESA_SHADER_FRAGMENT)
1919 ctx->shader_info->fs.writes_memory = true;
1920
1921 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1922 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1923 }
1924 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1925 params[arg_count++] = get_src(ctx, instr->src[0]);
1926 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1927 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1928 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1929
1930 switch (instr->intrinsic) {
1931 case nir_intrinsic_ssbo_atomic_add:
1932 name = "llvm.amdgcn.buffer.atomic.add";
1933 break;
1934 case nir_intrinsic_ssbo_atomic_imin:
1935 name = "llvm.amdgcn.buffer.atomic.smin";
1936 break;
1937 case nir_intrinsic_ssbo_atomic_umin:
1938 name = "llvm.amdgcn.buffer.atomic.umin";
1939 break;
1940 case nir_intrinsic_ssbo_atomic_imax:
1941 name = "llvm.amdgcn.buffer.atomic.smax";
1942 break;
1943 case nir_intrinsic_ssbo_atomic_umax:
1944 name = "llvm.amdgcn.buffer.atomic.umax";
1945 break;
1946 case nir_intrinsic_ssbo_atomic_and:
1947 name = "llvm.amdgcn.buffer.atomic.and";
1948 break;
1949 case nir_intrinsic_ssbo_atomic_or:
1950 name = "llvm.amdgcn.buffer.atomic.or";
1951 break;
1952 case nir_intrinsic_ssbo_atomic_xor:
1953 name = "llvm.amdgcn.buffer.atomic.xor";
1954 break;
1955 case nir_intrinsic_ssbo_atomic_exchange:
1956 name = "llvm.amdgcn.buffer.atomic.swap";
1957 break;
1958 case nir_intrinsic_ssbo_atomic_comp_swap:
1959 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1960 break;
1961 default:
1962 abort();
1963 }
1964
1965 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1966 }
1967
1968 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1969 nir_intrinsic_instr *instr)
1970 {
1971 LLVMValueRef results[2];
1972 int load_components;
1973 int num_components = instr->num_components;
1974 if (instr->dest.ssa.bit_size == 64)
1975 num_components *= 2;
1976
1977 for (int i = 0; i < num_components; i += load_components) {
1978 load_components = MIN2(num_components - i, 4);
1979 const char *load_name;
1980 LLVMTypeRef data_type = ctx->f32;
1981 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
1982 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
1983
1984 if (load_components == 3)
1985 data_type = LLVMVectorType(ctx->f32, 4);
1986 else if (load_components > 1)
1987 data_type = LLVMVectorType(ctx->f32, load_components);
1988
1989 if (load_components >= 3)
1990 load_name = "llvm.amdgcn.buffer.load.v4f32";
1991 else if (load_components == 2)
1992 load_name = "llvm.amdgcn.buffer.load.v2f32";
1993 else if (load_components == 1)
1994 load_name = "llvm.amdgcn.buffer.load.f32";
1995 else
1996 unreachable("unhandled number of components");
1997
1998 LLVMValueRef params[] = {
1999 get_src(ctx, instr->src[0]),
2000 LLVMConstInt(ctx->i32, 0, false),
2001 offset,
2002 LLVMConstInt(ctx->i1, 0, false),
2003 LLVMConstInt(ctx->i1, 0, false),
2004 };
2005
2006 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2007
2008 }
2009
2010 LLVMValueRef ret = results[0];
2011 if (num_components > 4 || num_components == 3) {
2012 LLVMValueRef masks[] = {
2013 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2014 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2015 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2016 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2017 };
2018
2019 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2020 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2021 results[num_components > 4 ? 1 : 0], swizzle, "");
2022 }
2023
2024 return LLVMBuildBitCast(ctx->builder, ret,
2025 get_def_type(ctx, &instr->dest.ssa), "");
2026 }
2027
2028 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2029 nir_intrinsic_instr *instr)
2030 {
2031 LLVMValueRef results[8], ret;
2032 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2033 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2034 int num_components = instr->num_components;
2035
2036 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2037
2038 if (instr->dest.ssa.bit_size == 64)
2039 num_components *= 2;
2040
2041 for (unsigned i = 0; i < num_components; ++i) {
2042 LLVMValueRef params[] = {
2043 rsrc,
2044 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2045 offset, "")
2046 };
2047 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2048 params, 2, AC_FUNC_ATTR_READNONE);
2049 }
2050
2051
2052 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2053 return LLVMBuildBitCast(ctx->builder, ret,
2054 get_def_type(ctx, &instr->dest.ssa), "");
2055 }
2056
2057 static void
2058 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2059 bool vs_in, unsigned *vertex_index_out,
2060 unsigned *const_out, LLVMValueRef *indir_out)
2061 {
2062 unsigned const_offset = 0;
2063 LLVMValueRef offset = NULL;
2064
2065 if (vertex_index_out != NULL) {
2066 tail = tail->child;
2067 nir_deref_array *deref_array = nir_deref_as_array(tail);
2068 *vertex_index_out = deref_array->base_offset;
2069 }
2070
2071 while (tail->child != NULL) {
2072 const struct glsl_type *parent_type = tail->type;
2073 tail = tail->child;
2074
2075 if (tail->deref_type == nir_deref_type_array) {
2076 nir_deref_array *deref_array = nir_deref_as_array(tail);
2077 LLVMValueRef index, stride, local_offset;
2078 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2079
2080 const_offset += size * deref_array->base_offset;
2081 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2082 continue;
2083
2084 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2085 index = get_src(ctx, deref_array->indirect);
2086 stride = LLVMConstInt(ctx->i32, size, 0);
2087 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2088
2089 if (offset)
2090 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2091 else
2092 offset = local_offset;
2093 } else if (tail->deref_type == nir_deref_type_struct) {
2094 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2095
2096 for (unsigned i = 0; i < deref_struct->index; i++) {
2097 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2098 const_offset += glsl_count_attribute_slots(ft, vs_in);
2099 }
2100 } else
2101 unreachable("unsupported deref type");
2102
2103 }
2104
2105 if (const_offset && offset)
2106 offset = LLVMBuildAdd(ctx->builder, offset,
2107 LLVMConstInt(ctx->i32, const_offset, 0),
2108 "");
2109
2110 *const_out = const_offset;
2111 *indir_out = offset;
2112 }
2113
2114 static LLVMValueRef
2115 load_gs_input(struct nir_to_llvm_context *ctx,
2116 nir_intrinsic_instr *instr)
2117 {
2118 LLVMValueRef indir_index, vtx_offset;
2119 unsigned const_index;
2120 LLVMValueRef args[9];
2121 unsigned param, vtx_offset_param;
2122 LLVMValueRef value[4], result;
2123 unsigned vertex_index;
2124 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2125 false, &vertex_index,
2126 &const_index, &indir_index);
2127 vtx_offset_param = vertex_index;
2128 assert(vtx_offset_param < 6);
2129 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2130 LLVMConstInt(ctx->i32, 4, false), "");
2131
2132 for (unsigned i = 0; i < instr->num_components; i++) {
2133 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2134 args[0] = ctx->esgs_ring;
2135 args[1] = vtx_offset;
2136 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2137 args[3] = ctx->i32zero;
2138 args[4] = ctx->i32one; /* OFFEN */
2139 args[5] = ctx->i32zero; /* IDXEN */
2140 args[6] = ctx->i32one; /* GLC */
2141 args[7] = ctx->i32zero; /* SLC */
2142 args[8] = ctx->i32zero; /* TFE */
2143
2144 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2145 ctx->i32, args, 9, AC_FUNC_ATTR_READONLY);
2146 }
2147 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2148
2149 return result;
2150 }
2151
2152 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2153 nir_intrinsic_instr *instr)
2154 {
2155 LLVMValueRef values[8];
2156 int idx = instr->variables[0]->var->data.driver_location;
2157 int ve = instr->dest.ssa.num_components;
2158 LLVMValueRef indir_index;
2159 LLVMValueRef ret;
2160 unsigned const_index;
2161 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2162 instr->variables[0]->var->data.mode == nir_var_shader_in;
2163 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2164 &const_index, &indir_index);
2165
2166 if (instr->dest.ssa.bit_size == 64)
2167 ve *= 2;
2168
2169 switch (instr->variables[0]->var->data.mode) {
2170 case nir_var_shader_in:
2171 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2172 return load_gs_input(ctx, instr);
2173 }
2174 for (unsigned chan = 0; chan < ve; chan++) {
2175 if (indir_index) {
2176 unsigned count = glsl_count_attribute_slots(
2177 instr->variables[0]->var->type,
2178 ctx->stage == MESA_SHADER_VERTEX);
2179 count -= chan / 4;
2180 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2181 &ctx->ac, ctx->inputs + idx + chan, count,
2182 4, false);
2183
2184 values[chan] = LLVMBuildExtractElement(ctx->builder,
2185 tmp_vec,
2186 indir_index, "");
2187 } else
2188 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2189 }
2190 break;
2191 case nir_var_local:
2192 for (unsigned chan = 0; chan < ve; chan++) {
2193 if (indir_index) {
2194 unsigned count = glsl_count_attribute_slots(
2195 instr->variables[0]->var->type, false);
2196 count -= chan / 4;
2197 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2198 &ctx->ac, ctx->locals + idx + chan, count,
2199 4, true);
2200
2201 values[chan] = LLVMBuildExtractElement(ctx->builder,
2202 tmp_vec,
2203 indir_index, "");
2204 } else {
2205 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2206 }
2207 }
2208 break;
2209 case nir_var_shader_out:
2210 for (unsigned chan = 0; chan < ve; chan++) {
2211 if (indir_index) {
2212 unsigned count = glsl_count_attribute_slots(
2213 instr->variables[0]->var->type, false);
2214 count -= chan / 4;
2215 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2216 &ctx->ac, ctx->outputs + idx + chan, count,
2217 4, true);
2218
2219 values[chan] = LLVMBuildExtractElement(ctx->builder,
2220 tmp_vec,
2221 indir_index, "");
2222 } else {
2223 values[chan] = LLVMBuildLoad(ctx->builder,
2224 ctx->outputs[idx + chan + const_index * 4],
2225 "");
2226 }
2227 }
2228 break;
2229 case nir_var_shared: {
2230 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2231 LLVMValueRef derived_ptr;
2232
2233 if (indir_index)
2234 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2235
2236 for (unsigned chan = 0; chan < ve; chan++) {
2237 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2238 if (indir_index)
2239 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2240 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2241
2242 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2243 }
2244 break;
2245 }
2246 default:
2247 unreachable("unhandle variable mode");
2248 }
2249 ret = ac_build_gather_values(&ctx->ac, values, ve);
2250 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2251 }
2252
2253 static void
2254 visit_store_var(struct nir_to_llvm_context *ctx,
2255 nir_intrinsic_instr *instr)
2256 {
2257 LLVMValueRef temp_ptr, value;
2258 int idx = instr->variables[0]->var->data.driver_location;
2259 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2260 int writemask = instr->const_index[0];
2261 LLVMValueRef indir_index;
2262 unsigned const_index;
2263 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2264 NULL, &const_index, &indir_index);
2265
2266 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2267 int old_writemask = writemask;
2268
2269 src = LLVMBuildBitCast(ctx->builder, src,
2270 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2271 "");
2272
2273 writemask = 0;
2274 for (unsigned chan = 0; chan < 4; chan++) {
2275 if (old_writemask & (1 << chan))
2276 writemask |= 3u << (2 * chan);
2277 }
2278 }
2279
2280 switch (instr->variables[0]->var->data.mode) {
2281 case nir_var_shader_out:
2282 for (unsigned chan = 0; chan < 8; chan++) {
2283 int stride = 4;
2284 if (!(writemask & (1 << chan)))
2285 continue;
2286
2287 value = llvm_extract_elem(ctx, src, chan);
2288
2289 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2290 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2291 stride = 1;
2292 if (indir_index) {
2293 unsigned count = glsl_count_attribute_slots(
2294 instr->variables[0]->var->type, false);
2295 count -= chan / 4;
2296 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2297 &ctx->ac, ctx->outputs + idx + chan, count,
2298 stride, true);
2299
2300 if (get_llvm_num_components(tmp_vec) > 1) {
2301 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2302 value, indir_index, "");
2303 } else
2304 tmp_vec = value;
2305 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2306 count, stride, tmp_vec);
2307
2308 } else {
2309 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2310
2311 LLVMBuildStore(ctx->builder, value, temp_ptr);
2312 }
2313 }
2314 break;
2315 case nir_var_local:
2316 for (unsigned chan = 0; chan < 8; chan++) {
2317 if (!(writemask & (1 << chan)))
2318 continue;
2319
2320 value = llvm_extract_elem(ctx, src, chan);
2321 if (indir_index) {
2322 unsigned count = glsl_count_attribute_slots(
2323 instr->variables[0]->var->type, false);
2324 count -= chan / 4;
2325 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2326 &ctx->ac, ctx->locals + idx + chan, count,
2327 4, true);
2328
2329 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2330 value, indir_index, "");
2331 build_store_values_extended(ctx, ctx->locals + idx + chan,
2332 count, 4, tmp_vec);
2333 } else {
2334 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2335
2336 LLVMBuildStore(ctx->builder, value, temp_ptr);
2337 }
2338 }
2339 break;
2340 case nir_var_shared: {
2341 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2342
2343 if (indir_index)
2344 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2345
2346 for (unsigned chan = 0; chan < 8; chan++) {
2347 if (!(writemask & (1 << chan)))
2348 continue;
2349 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2350 LLVMValueRef derived_ptr;
2351
2352 if (indir_index)
2353 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2354
2355 value = llvm_extract_elem(ctx, src, chan);
2356 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2357 LLVMBuildStore(ctx->builder,
2358 to_integer(ctx, value), derived_ptr);
2359 }
2360 break;
2361 }
2362 default:
2363 break;
2364 }
2365 }
2366
2367 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2368 {
2369 switch (dim) {
2370 case GLSL_SAMPLER_DIM_BUF:
2371 return 1;
2372 case GLSL_SAMPLER_DIM_1D:
2373 return array ? 2 : 1;
2374 case GLSL_SAMPLER_DIM_2D:
2375 return array ? 3 : 2;
2376 case GLSL_SAMPLER_DIM_MS:
2377 return array ? 4 : 3;
2378 case GLSL_SAMPLER_DIM_3D:
2379 case GLSL_SAMPLER_DIM_CUBE:
2380 return 3;
2381 case GLSL_SAMPLER_DIM_RECT:
2382 case GLSL_SAMPLER_DIM_SUBPASS:
2383 return 2;
2384 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2385 return 3;
2386 default:
2387 break;
2388 }
2389 return 0;
2390 }
2391
2392 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2393 nir_intrinsic_instr *instr)
2394 {
2395 const struct glsl_type *type = instr->variables[0]->var->type;
2396 if(instr->variables[0]->deref.child)
2397 type = instr->variables[0]->deref.child->type;
2398
2399 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2400 LLVMValueRef coords[4];
2401 LLVMValueRef masks[] = {
2402 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2403 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2404 };
2405 LLVMValueRef res;
2406 int count;
2407 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2408 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2409 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2410 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2411 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2412
2413 count = image_type_to_components_count(dim,
2414 glsl_sampler_type_is_array(type));
2415
2416 if (count == 1) {
2417 if (instr->src[0].ssa->num_components)
2418 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2419 else
2420 res = src0;
2421 } else {
2422 int chan;
2423 if (is_ms)
2424 count--;
2425 for (chan = 0; chan < count; ++chan) {
2426 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2427 }
2428
2429 if (add_frag_pos) {
2430 for (chan = 0; chan < count; ++chan)
2431 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2432 }
2433 if (is_ms) {
2434 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2435 count++;
2436 }
2437
2438 if (count == 3) {
2439 coords[3] = LLVMGetUndef(ctx->i32);
2440 count = 4;
2441 }
2442 res = ac_build_gather_values(&ctx->ac, coords, count);
2443 }
2444 return res;
2445 }
2446
2447 static void build_type_name_for_intr(
2448 LLVMTypeRef type,
2449 char *buf, unsigned bufsize)
2450 {
2451 LLVMTypeRef elem_type = type;
2452
2453 assert(bufsize >= 8);
2454
2455 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2456 int ret = snprintf(buf, bufsize, "v%u",
2457 LLVMGetVectorSize(type));
2458 if (ret < 0) {
2459 char *type_name = LLVMPrintTypeToString(type);
2460 fprintf(stderr, "Error building type name for: %s\n",
2461 type_name);
2462 return;
2463 }
2464 elem_type = LLVMGetElementType(type);
2465 buf += ret;
2466 bufsize -= ret;
2467 }
2468 switch (LLVMGetTypeKind(elem_type)) {
2469 default: break;
2470 case LLVMIntegerTypeKind:
2471 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2472 break;
2473 case LLVMFloatTypeKind:
2474 snprintf(buf, bufsize, "f32");
2475 break;
2476 case LLVMDoubleTypeKind:
2477 snprintf(buf, bufsize, "f64");
2478 break;
2479 }
2480 }
2481
2482 static void get_image_intr_name(const char *base_name,
2483 LLVMTypeRef data_type,
2484 LLVMTypeRef coords_type,
2485 LLVMTypeRef rsrc_type,
2486 char *out_name, unsigned out_len)
2487 {
2488 char coords_type_name[8];
2489
2490 build_type_name_for_intr(coords_type, coords_type_name,
2491 sizeof(coords_type_name));
2492
2493 if (HAVE_LLVM <= 0x0309) {
2494 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2495 } else {
2496 char data_type_name[8];
2497 char rsrc_type_name[8];
2498
2499 build_type_name_for_intr(data_type, data_type_name,
2500 sizeof(data_type_name));
2501 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2502 sizeof(rsrc_type_name));
2503 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2504 data_type_name, coords_type_name, rsrc_type_name);
2505 }
2506 }
2507
2508 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2509 nir_intrinsic_instr *instr)
2510 {
2511 LLVMValueRef params[7];
2512 LLVMValueRef res;
2513 char intrinsic_name[64];
2514 const nir_variable *var = instr->variables[0]->var;
2515 const struct glsl_type *type = var->type;
2516 if(instr->variables[0]->deref.child)
2517 type = instr->variables[0]->deref.child->type;
2518
2519 type = glsl_without_array(type);
2520 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2521 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2522 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2523 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2524 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2525 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2526 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2527 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2528 params, 5, 0);
2529
2530 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2531 res = to_integer(ctx, res);
2532 } else {
2533 bool is_da = glsl_sampler_type_is_array(type) ||
2534 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2535 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2536 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2537 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2538
2539 params[0] = get_image_coords(ctx, instr);
2540 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2541 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2542 if (HAVE_LLVM <= 0x0309) {
2543 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2544 params[4] = da;
2545 params[5] = glc;
2546 params[6] = slc;
2547 } else {
2548 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2549 params[3] = glc;
2550 params[4] = slc;
2551 params[5] = lwe;
2552 params[6] = da;
2553 }
2554
2555 get_image_intr_name("llvm.amdgcn.image.load",
2556 ctx->v4f32, /* vdata */
2557 LLVMTypeOf(params[0]), /* coords */
2558 LLVMTypeOf(params[1]), /* rsrc */
2559 intrinsic_name, sizeof(intrinsic_name));
2560
2561 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2562 params, 7, AC_FUNC_ATTR_READONLY);
2563 }
2564 return to_integer(ctx, res);
2565 }
2566
2567 static void visit_image_store(struct nir_to_llvm_context *ctx,
2568 nir_intrinsic_instr *instr)
2569 {
2570 LLVMValueRef params[8];
2571 char intrinsic_name[64];
2572 const nir_variable *var = instr->variables[0]->var;
2573 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2574 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2575 const struct glsl_type *type = glsl_without_array(var->type);
2576
2577 if (ctx->stage == MESA_SHADER_FRAGMENT)
2578 ctx->shader_info->fs.writes_memory = true;
2579
2580 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2581 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2582 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2583 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2584 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2585 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2586 params[4] = i1false; /* glc */
2587 params[5] = i1false; /* slc */
2588 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2589 params, 6, 0);
2590 } else {
2591 bool is_da = glsl_sampler_type_is_array(type) ||
2592 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2593 LLVMValueRef da = is_da ? i1true : i1false;
2594 LLVMValueRef glc = i1false;
2595 LLVMValueRef slc = i1false;
2596
2597 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2598 params[1] = get_image_coords(ctx, instr); /* coords */
2599 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2600 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2601 if (HAVE_LLVM <= 0x0309) {
2602 params[4] = i1false; /* r128 */
2603 params[5] = da;
2604 params[6] = glc;
2605 params[7] = slc;
2606 } else {
2607 LLVMValueRef lwe = i1false;
2608 params[4] = glc;
2609 params[5] = slc;
2610 params[6] = lwe;
2611 params[7] = da;
2612 }
2613
2614 get_image_intr_name("llvm.amdgcn.image.store",
2615 LLVMTypeOf(params[0]), /* vdata */
2616 LLVMTypeOf(params[1]), /* coords */
2617 LLVMTypeOf(params[2]), /* rsrc */
2618 intrinsic_name, sizeof(intrinsic_name));
2619
2620 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2621 params, 8, 0);
2622 }
2623
2624 }
2625
2626 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2627 nir_intrinsic_instr *instr)
2628 {
2629 LLVMValueRef params[6];
2630 int param_count = 0;
2631 const nir_variable *var = instr->variables[0]->var;
2632 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2633 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2634 const char *base_name = "llvm.amdgcn.image.atomic";
2635 const char *atomic_name;
2636 LLVMValueRef coords;
2637 char intrinsic_name[32], coords_type[8];
2638 const struct glsl_type *type = glsl_without_array(var->type);
2639
2640 if (ctx->stage == MESA_SHADER_FRAGMENT)
2641 ctx->shader_info->fs.writes_memory = true;
2642
2643 params[param_count++] = get_src(ctx, instr->src[2]);
2644 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2645 params[param_count++] = get_src(ctx, instr->src[3]);
2646
2647 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2648 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2649 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2650 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2651 params[param_count++] = ctx->i32zero; /* voffset */
2652 params[param_count++] = i1false; /* glc */
2653 params[param_count++] = i1false; /* slc */
2654 } else {
2655 bool da = glsl_sampler_type_is_array(type) ||
2656 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2657
2658 coords = params[param_count++] = get_image_coords(ctx, instr);
2659 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2660 params[param_count++] = i1false; /* r128 */
2661 params[param_count++] = da ? i1true : i1false; /* da */
2662 params[param_count++] = i1false; /* slc */
2663 }
2664
2665 switch (instr->intrinsic) {
2666 case nir_intrinsic_image_atomic_add:
2667 atomic_name = "add";
2668 break;
2669 case nir_intrinsic_image_atomic_min:
2670 atomic_name = "smin";
2671 break;
2672 case nir_intrinsic_image_atomic_max:
2673 atomic_name = "smax";
2674 break;
2675 case nir_intrinsic_image_atomic_and:
2676 atomic_name = "and";
2677 break;
2678 case nir_intrinsic_image_atomic_or:
2679 atomic_name = "or";
2680 break;
2681 case nir_intrinsic_image_atomic_xor:
2682 atomic_name = "xor";
2683 break;
2684 case nir_intrinsic_image_atomic_exchange:
2685 atomic_name = "swap";
2686 break;
2687 case nir_intrinsic_image_atomic_comp_swap:
2688 atomic_name = "cmpswap";
2689 break;
2690 default:
2691 abort();
2692 }
2693 build_int_type_name(LLVMTypeOf(coords),
2694 coords_type, sizeof(coords_type));
2695
2696 snprintf(intrinsic_name, sizeof(intrinsic_name),
2697 "%s.%s.%s", base_name, atomic_name, coords_type);
2698 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2699 }
2700
2701 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2702 nir_intrinsic_instr *instr)
2703 {
2704 LLVMValueRef res;
2705 LLVMValueRef params[10];
2706 const nir_variable *var = instr->variables[0]->var;
2707 const struct glsl_type *type = instr->variables[0]->var->type;
2708 bool da = glsl_sampler_type_is_array(var->type) ||
2709 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2710 if(instr->variables[0]->deref.child)
2711 type = instr->variables[0]->deref.child->type;
2712
2713 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2714 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2715 params[0] = ctx->i32zero;
2716 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2717 params[2] = LLVMConstInt(ctx->i32, 15, false);
2718 params[3] = ctx->i32zero;
2719 params[4] = ctx->i32zero;
2720 params[5] = da ? ctx->i32one : ctx->i32zero;
2721 params[6] = ctx->i32zero;
2722 params[7] = ctx->i32zero;
2723 params[8] = ctx->i32zero;
2724 params[9] = ctx->i32zero;
2725
2726 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2727 params, 10, AC_FUNC_ATTR_READNONE);
2728
2729 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2730 glsl_sampler_type_is_array(type)) {
2731 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2732 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2733 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2734 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2735 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2736 }
2737 return res;
2738 }
2739
2740 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2741 {
2742 LLVMValueRef args[1] = {
2743 LLVMConstInt(ctx->i32, 0xf70, false),
2744 };
2745 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2746 ctx->voidt, args, 1, 0);
2747 }
2748
2749 static void emit_barrier(struct nir_to_llvm_context *ctx)
2750 {
2751 // TODO tess
2752 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2753 ctx->voidt, NULL, 0, 0);
2754 }
2755
2756 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2757 nir_intrinsic_instr *instr)
2758 {
2759 LLVMValueRef cond;
2760 ctx->shader_info->fs.can_discard = true;
2761
2762 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2763 get_src(ctx, instr->src[0]),
2764 ctx->i32zero, "");
2765
2766 cond = LLVMBuildSelect(ctx->builder, cond,
2767 LLVMConstReal(ctx->f32, -1.0f),
2768 ctx->f32zero, "");
2769 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2770 ctx->voidt,
2771 &cond, 1, 0);
2772 }
2773
2774 static LLVMValueRef
2775 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2776 {
2777 LLVMValueRef result;
2778 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2779 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2780 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2781
2782 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2783 }
2784
2785 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2786 nir_intrinsic_instr *instr)
2787 {
2788 LLVMValueRef ptr, result;
2789 int idx = instr->variables[0]->var->data.driver_location;
2790 LLVMValueRef src = get_src(ctx, instr->src[0]);
2791 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2792
2793 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2794 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2795 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2796 ptr, src, src1,
2797 LLVMAtomicOrderingSequentiallyConsistent,
2798 LLVMAtomicOrderingSequentiallyConsistent,
2799 false);
2800 } else {
2801 LLVMAtomicRMWBinOp op;
2802 switch (instr->intrinsic) {
2803 case nir_intrinsic_var_atomic_add:
2804 op = LLVMAtomicRMWBinOpAdd;
2805 break;
2806 case nir_intrinsic_var_atomic_umin:
2807 op = LLVMAtomicRMWBinOpUMin;
2808 break;
2809 case nir_intrinsic_var_atomic_umax:
2810 op = LLVMAtomicRMWBinOpUMax;
2811 break;
2812 case nir_intrinsic_var_atomic_imin:
2813 op = LLVMAtomicRMWBinOpMin;
2814 break;
2815 case nir_intrinsic_var_atomic_imax:
2816 op = LLVMAtomicRMWBinOpMax;
2817 break;
2818 case nir_intrinsic_var_atomic_and:
2819 op = LLVMAtomicRMWBinOpAnd;
2820 break;
2821 case nir_intrinsic_var_atomic_or:
2822 op = LLVMAtomicRMWBinOpOr;
2823 break;
2824 case nir_intrinsic_var_atomic_xor:
2825 op = LLVMAtomicRMWBinOpXor;
2826 break;
2827 case nir_intrinsic_var_atomic_exchange:
2828 op = LLVMAtomicRMWBinOpXchg;
2829 break;
2830 default:
2831 return NULL;
2832 }
2833
2834 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2835 LLVMAtomicOrderingSequentiallyConsistent,
2836 false);
2837 }
2838 return result;
2839 }
2840
2841 #define INTERP_CENTER 0
2842 #define INTERP_CENTROID 1
2843 #define INTERP_SAMPLE 2
2844
2845 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2846 enum glsl_interp_mode interp, unsigned location)
2847 {
2848 switch (interp) {
2849 case INTERP_MODE_FLAT:
2850 default:
2851 return NULL;
2852 case INTERP_MODE_SMOOTH:
2853 case INTERP_MODE_NONE:
2854 if (location == INTERP_CENTER)
2855 return ctx->persp_center;
2856 else if (location == INTERP_CENTROID)
2857 return ctx->persp_centroid;
2858 else if (location == INTERP_SAMPLE)
2859 return ctx->persp_sample;
2860 break;
2861 case INTERP_MODE_NOPERSPECTIVE:
2862 if (location == INTERP_CENTER)
2863 return ctx->linear_center;
2864 else if (location == INTERP_CENTROID)
2865 return ctx->linear_centroid;
2866 else if (location == INTERP_SAMPLE)
2867 return ctx->linear_sample;
2868 break;
2869 }
2870 return NULL;
2871 }
2872
2873 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2874 LLVMValueRef sample_id)
2875 {
2876 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2877 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2878 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2879 LLVMValueRef result[2];
2880
2881 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2882 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2883
2884 return ac_build_gather_values(&ctx->ac, result, 2);
2885 }
2886
2887 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2888 {
2889 LLVMValueRef values[2];
2890
2891 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2892 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2893 return ac_build_gather_values(&ctx->ac, values, 2);
2894 }
2895
2896 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2897 nir_intrinsic_instr *instr)
2898 {
2899 LLVMValueRef result[2];
2900 LLVMValueRef interp_param, attr_number;
2901 unsigned location;
2902 unsigned chan;
2903 LLVMValueRef src_c0, src_c1;
2904 LLVMValueRef src0;
2905 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2906 switch (instr->intrinsic) {
2907 case nir_intrinsic_interp_var_at_centroid:
2908 location = INTERP_CENTROID;
2909 break;
2910 case nir_intrinsic_interp_var_at_sample:
2911 case nir_intrinsic_interp_var_at_offset:
2912 location = INTERP_SAMPLE;
2913 src0 = get_src(ctx, instr->src[0]);
2914 break;
2915 default:
2916 break;
2917 }
2918
2919 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2920 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2921 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2922 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2923 LLVMValueRef sample_position;
2924 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2925
2926 /* fetch sample ID */
2927 sample_position = load_sample_position(ctx, src0);
2928
2929 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2930 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2931 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2932 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2933 }
2934 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2935 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2936
2937 if (location == INTERP_SAMPLE) {
2938 LLVMValueRef ij_out[2];
2939 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2940
2941 /*
2942 * take the I then J parameters, and the DDX/Y for it, and
2943 * calculate the IJ inputs for the interpolator.
2944 * temp1 = ddx * offset/sample.x + I;
2945 * interp_param.I = ddy * offset/sample.y + temp1;
2946 * temp1 = ddx * offset/sample.x + J;
2947 * interp_param.J = ddy * offset/sample.y + temp1;
2948 */
2949 for (unsigned i = 0; i < 2; i++) {
2950 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
2951 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
2952 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
2953 ddxy_out, ix_ll, "");
2954 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
2955 ddxy_out, iy_ll, "");
2956 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
2957 interp_param, ix_ll, "");
2958 LLVMValueRef temp1, temp2;
2959
2960 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
2961 ctx->f32, "");
2962
2963 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
2964 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
2965
2966 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
2967 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
2968
2969 ij_out[i] = LLVMBuildBitCast(ctx->builder,
2970 temp2, ctx->i32, "");
2971 }
2972 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
2973
2974 }
2975
2976 for (chan = 0; chan < 2; chan++) {
2977 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
2978
2979 if (interp_param) {
2980 interp_param = LLVMBuildBitCast(ctx->builder,
2981 interp_param, LLVMVectorType(ctx->f32, 2), "");
2982 LLVMValueRef i = LLVMBuildExtractElement(
2983 ctx->builder, interp_param, ctx->i32zero, "");
2984 LLVMValueRef j = LLVMBuildExtractElement(
2985 ctx->builder, interp_param, ctx->i32one, "");
2986
2987 result[chan] = ac_build_fs_interp(&ctx->ac,
2988 llvm_chan, attr_number,
2989 ctx->prim_mask, i, j);
2990 } else {
2991 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2992 LLVMConstInt(ctx->i32, 2, false),
2993 llvm_chan, attr_number,
2994 ctx->prim_mask);
2995 }
2996 }
2997 return ac_build_gather_values(&ctx->ac, result, 2);
2998 }
2999
3000 static void
3001 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3002 nir_intrinsic_instr *instr)
3003 {
3004 LLVMValueRef gs_next_vertex;
3005 LLVMValueRef can_emit, kill;
3006 int idx;
3007
3008 assert(instr->const_index[0] == 0);
3009 /* Write vertex attribute values to GSVS ring */
3010 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3011 ctx->gs_next_vertex,
3012 "");
3013
3014 /* If this thread has already emitted the declared maximum number of
3015 * vertices, kill it: excessive vertex emissions are not supposed to
3016 * have any effect, and GS threads have no externally observable
3017 * effects other than emitting vertices.
3018 */
3019 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3020 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3021
3022 kill = LLVMBuildSelect(ctx->builder, can_emit,
3023 LLVMConstReal(ctx->f32, 1.0f),
3024 LLVMConstReal(ctx->f32, -1.0f), "");
3025 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3026 ctx->voidt, &kill, 1, 0);
3027
3028 /* loop num outputs */
3029 idx = 0;
3030 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3031 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3032 if (!(ctx->output_mask & (1ull << i)))
3033 continue;
3034
3035 for (unsigned j = 0; j < 4; j++) {
3036 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3037 out_ptr[j], "");
3038 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (idx * 4 + j) * ctx->gs_max_out_vertices, false);
3039 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3040 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3041
3042 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3043
3044 ac_build_tbuffer_store(&ctx->ac, ctx->gsvs_ring,
3045 out_val, 1,
3046 voffset, ctx->gs2vs_offset, 0,
3047 V_008F0C_BUF_DATA_FORMAT_32,
3048 V_008F0C_BUF_NUM_FORMAT_UINT,
3049 1, 0, 1, 1, 0);
3050 }
3051 idx++;
3052 }
3053
3054 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3055 ctx->i32one, "");
3056 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3057
3058 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3059 }
3060
3061 static void
3062 visit_end_primitive(struct nir_to_llvm_context *ctx,
3063 nir_intrinsic_instr *instr)
3064 {
3065 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3066 }
3067
3068 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3069 nir_intrinsic_instr *instr)
3070 {
3071 LLVMValueRef result = NULL;
3072
3073 switch (instr->intrinsic) {
3074 case nir_intrinsic_load_work_group_id: {
3075 result = ctx->workgroup_ids;
3076 break;
3077 }
3078 case nir_intrinsic_load_base_vertex: {
3079 result = ctx->base_vertex;
3080 break;
3081 }
3082 case nir_intrinsic_load_vertex_id_zero_base: {
3083 result = ctx->vertex_id;
3084 break;
3085 }
3086 case nir_intrinsic_load_local_invocation_id: {
3087 result = ctx->local_invocation_ids;
3088 break;
3089 }
3090 case nir_intrinsic_load_base_instance:
3091 result = ctx->start_instance;
3092 break;
3093 case nir_intrinsic_load_draw_id:
3094 result = ctx->draw_index;
3095 break;
3096 case nir_intrinsic_load_invocation_id:
3097 result = ctx->gs_invocation_id;
3098 break;
3099 case nir_intrinsic_load_primitive_id:
3100 if (ctx->stage == MESA_SHADER_GEOMETRY)
3101 result = ctx->gs_prim_id;
3102 else
3103 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3104 break;
3105 case nir_intrinsic_load_sample_id:
3106 ctx->shader_info->fs.force_persample = true;
3107 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3108 break;
3109 case nir_intrinsic_load_sample_pos:
3110 ctx->shader_info->fs.force_persample = true;
3111 result = load_sample_pos(ctx);
3112 break;
3113 case nir_intrinsic_load_front_face:
3114 result = ctx->front_face;
3115 break;
3116 case nir_intrinsic_load_instance_id:
3117 result = ctx->instance_id;
3118 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3119 ctx->shader_info->vs.vgpr_comp_cnt);
3120 break;
3121 case nir_intrinsic_load_num_work_groups:
3122 result = ctx->num_work_groups;
3123 break;
3124 case nir_intrinsic_load_local_invocation_index:
3125 result = visit_load_local_invocation_index(ctx);
3126 break;
3127 case nir_intrinsic_load_push_constant:
3128 result = visit_load_push_constant(ctx, instr);
3129 break;
3130 case nir_intrinsic_vulkan_resource_index:
3131 result = visit_vulkan_resource_index(ctx, instr);
3132 break;
3133 case nir_intrinsic_store_ssbo:
3134 visit_store_ssbo(ctx, instr);
3135 break;
3136 case nir_intrinsic_load_ssbo:
3137 result = visit_load_buffer(ctx, instr);
3138 break;
3139 case nir_intrinsic_ssbo_atomic_add:
3140 case nir_intrinsic_ssbo_atomic_imin:
3141 case nir_intrinsic_ssbo_atomic_umin:
3142 case nir_intrinsic_ssbo_atomic_imax:
3143 case nir_intrinsic_ssbo_atomic_umax:
3144 case nir_intrinsic_ssbo_atomic_and:
3145 case nir_intrinsic_ssbo_atomic_or:
3146 case nir_intrinsic_ssbo_atomic_xor:
3147 case nir_intrinsic_ssbo_atomic_exchange:
3148 case nir_intrinsic_ssbo_atomic_comp_swap:
3149 result = visit_atomic_ssbo(ctx, instr);
3150 break;
3151 case nir_intrinsic_load_ubo:
3152 result = visit_load_ubo_buffer(ctx, instr);
3153 break;
3154 case nir_intrinsic_get_buffer_size:
3155 result = visit_get_buffer_size(ctx, instr);
3156 break;
3157 case nir_intrinsic_load_var:
3158 result = visit_load_var(ctx, instr);
3159 break;
3160 case nir_intrinsic_store_var:
3161 visit_store_var(ctx, instr);
3162 break;
3163 case nir_intrinsic_image_load:
3164 result = visit_image_load(ctx, instr);
3165 break;
3166 case nir_intrinsic_image_store:
3167 visit_image_store(ctx, instr);
3168 break;
3169 case nir_intrinsic_image_atomic_add:
3170 case nir_intrinsic_image_atomic_min:
3171 case nir_intrinsic_image_atomic_max:
3172 case nir_intrinsic_image_atomic_and:
3173 case nir_intrinsic_image_atomic_or:
3174 case nir_intrinsic_image_atomic_xor:
3175 case nir_intrinsic_image_atomic_exchange:
3176 case nir_intrinsic_image_atomic_comp_swap:
3177 result = visit_image_atomic(ctx, instr);
3178 break;
3179 case nir_intrinsic_image_size:
3180 result = visit_image_size(ctx, instr);
3181 break;
3182 case nir_intrinsic_discard:
3183 ctx->shader_info->fs.can_discard = true;
3184 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3185 ctx->voidt,
3186 NULL, 0, 0);
3187 break;
3188 case nir_intrinsic_discard_if:
3189 emit_discard_if(ctx, instr);
3190 break;
3191 case nir_intrinsic_memory_barrier:
3192 emit_waitcnt(ctx);
3193 break;
3194 case nir_intrinsic_barrier:
3195 emit_barrier(ctx);
3196 break;
3197 case nir_intrinsic_var_atomic_add:
3198 case nir_intrinsic_var_atomic_imin:
3199 case nir_intrinsic_var_atomic_umin:
3200 case nir_intrinsic_var_atomic_imax:
3201 case nir_intrinsic_var_atomic_umax:
3202 case nir_intrinsic_var_atomic_and:
3203 case nir_intrinsic_var_atomic_or:
3204 case nir_intrinsic_var_atomic_xor:
3205 case nir_intrinsic_var_atomic_exchange:
3206 case nir_intrinsic_var_atomic_comp_swap:
3207 result = visit_var_atomic(ctx, instr);
3208 break;
3209 case nir_intrinsic_interp_var_at_centroid:
3210 case nir_intrinsic_interp_var_at_sample:
3211 case nir_intrinsic_interp_var_at_offset:
3212 result = visit_interp(ctx, instr);
3213 break;
3214 case nir_intrinsic_emit_vertex:
3215 visit_emit_vertex(ctx, instr);
3216 break;
3217 case nir_intrinsic_end_primitive:
3218 visit_end_primitive(ctx, instr);
3219 break;
3220 default:
3221 fprintf(stderr, "Unknown intrinsic: ");
3222 nir_print_instr(&instr->instr, stderr);
3223 fprintf(stderr, "\n");
3224 break;
3225 }
3226 if (result) {
3227 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3228 }
3229 }
3230
3231 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3232 nir_deref_var *deref,
3233 enum desc_type desc_type)
3234 {
3235 unsigned desc_set = deref->var->data.descriptor_set;
3236 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3237 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3238 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3239 unsigned offset = binding->offset;
3240 unsigned stride = binding->size;
3241 unsigned type_size;
3242 LLVMBuilderRef builder = ctx->builder;
3243 LLVMTypeRef type;
3244 LLVMValueRef index = NULL;
3245
3246 assert(deref->var->data.binding < layout->binding_count);
3247
3248 switch (desc_type) {
3249 case DESC_IMAGE:
3250 type = ctx->v8i32;
3251 type_size = 32;
3252 break;
3253 case DESC_FMASK:
3254 type = ctx->v8i32;
3255 offset += 32;
3256 type_size = 32;
3257 break;
3258 case DESC_SAMPLER:
3259 type = ctx->v4i32;
3260 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3261 offset += 64;
3262
3263 type_size = 16;
3264 break;
3265 case DESC_BUFFER:
3266 type = ctx->v4i32;
3267 type_size = 16;
3268 break;
3269 default:
3270 unreachable("invalid desc_type\n");
3271 }
3272
3273 if (deref->deref.child) {
3274 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3275
3276 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3277 offset += child->base_offset * stride;
3278 if (child->deref_array_type == nir_deref_array_type_indirect) {
3279 index = get_src(ctx, child->indirect);
3280 }
3281 }
3282
3283 assert(stride % type_size == 0);
3284
3285 if (!index)
3286 index = ctx->i32zero;
3287
3288 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3289
3290 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3291 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3292
3293 return ac_build_indexed_load_const(&ctx->ac, list, index);
3294 }
3295
3296 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3297 struct ac_tex_info *tinfo,
3298 nir_tex_instr *instr,
3299 nir_texop op,
3300 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3301 LLVMValueRef *param, unsigned count,
3302 unsigned dmask)
3303 {
3304 int num_args;
3305 unsigned is_rect = 0;
3306 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3307
3308 if (op == nir_texop_lod)
3309 da = false;
3310 /* Pad to power of two vector */
3311 while (count < util_next_power_of_two(count))
3312 param[count++] = LLVMGetUndef(ctx->i32);
3313
3314 if (count > 1)
3315 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3316 else
3317 tinfo->args[0] = param[0];
3318
3319 tinfo->args[1] = res_ptr;
3320 num_args = 2;
3321
3322 if (op == nir_texop_txf ||
3323 op == nir_texop_txf_ms ||
3324 op == nir_texop_query_levels ||
3325 op == nir_texop_texture_samples ||
3326 op == nir_texop_txs)
3327 tinfo->dst_type = ctx->v4i32;
3328 else {
3329 tinfo->dst_type = ctx->v4f32;
3330 tinfo->args[num_args++] = samp_ptr;
3331 }
3332
3333 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3334 tinfo->args[0] = res_ptr;
3335 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3336 tinfo->args[2] = param[0];
3337 tinfo->arg_count = 3;
3338 return;
3339 }
3340
3341 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3342 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3343 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3344 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3345 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3346 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3347 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3348 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3349
3350 tinfo->arg_count = num_args;
3351 }
3352
3353 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3354 *
3355 * SI-CI:
3356 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3357 * filtering manually. The driver sets img7 to a mask clearing
3358 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3359 * s_and_b32 samp0, samp0, img7
3360 *
3361 * VI:
3362 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3363 */
3364 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3365 LLVMValueRef res, LLVMValueRef samp)
3366 {
3367 LLVMBuilderRef builder = ctx->builder;
3368 LLVMValueRef img7, samp0;
3369
3370 if (ctx->options->chip_class >= VI)
3371 return samp;
3372
3373 img7 = LLVMBuildExtractElement(builder, res,
3374 LLVMConstInt(ctx->i32, 7, 0), "");
3375 samp0 = LLVMBuildExtractElement(builder, samp,
3376 LLVMConstInt(ctx->i32, 0, 0), "");
3377 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3378 return LLVMBuildInsertElement(builder, samp, samp0,
3379 LLVMConstInt(ctx->i32, 0, 0), "");
3380 }
3381
3382 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3383 nir_tex_instr *instr,
3384 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3385 LLVMValueRef *fmask_ptr)
3386 {
3387 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3388 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3389 else
3390 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3391 if (samp_ptr) {
3392 if (instr->sampler)
3393 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3394 else
3395 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3396 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3397 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3398 }
3399 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3400 instr->op == nir_texop_samples_identical))
3401 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3402 }
3403
3404 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3405 LLVMValueRef coord)
3406 {
3407 coord = to_float(ctx, coord);
3408 coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3409 coord = to_integer(ctx, coord);
3410 return coord;
3411 }
3412
3413 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3414 {
3415 LLVMValueRef result = NULL;
3416 struct ac_tex_info tinfo = { 0 };
3417 unsigned dmask = 0xf;
3418 LLVMValueRef address[16];
3419 LLVMValueRef coords[5];
3420 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3421 LLVMValueRef bias = NULL, offsets = NULL;
3422 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3423 LLVMValueRef ddx = NULL, ddy = NULL;
3424 LLVMValueRef derivs[6];
3425 unsigned chan, count = 0;
3426 unsigned const_src = 0, num_deriv_comp = 0;
3427
3428 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3429
3430 for (unsigned i = 0; i < instr->num_srcs; i++) {
3431 switch (instr->src[i].src_type) {
3432 case nir_tex_src_coord:
3433 coord = get_src(ctx, instr->src[i].src);
3434 break;
3435 case nir_tex_src_projector:
3436 break;
3437 case nir_tex_src_comparator:
3438 comparator = get_src(ctx, instr->src[i].src);
3439 break;
3440 case nir_tex_src_offset:
3441 offsets = get_src(ctx, instr->src[i].src);
3442 const_src = i;
3443 break;
3444 case nir_tex_src_bias:
3445 bias = get_src(ctx, instr->src[i].src);
3446 break;
3447 case nir_tex_src_lod:
3448 lod = get_src(ctx, instr->src[i].src);
3449 break;
3450 case nir_tex_src_ms_index:
3451 sample_index = get_src(ctx, instr->src[i].src);
3452 break;
3453 case nir_tex_src_ms_mcs:
3454 break;
3455 case nir_tex_src_ddx:
3456 ddx = get_src(ctx, instr->src[i].src);
3457 num_deriv_comp = instr->src[i].src.ssa->num_components;
3458 break;
3459 case nir_tex_src_ddy:
3460 ddy = get_src(ctx, instr->src[i].src);
3461 break;
3462 case nir_tex_src_texture_offset:
3463 case nir_tex_src_sampler_offset:
3464 case nir_tex_src_plane:
3465 default:
3466 break;
3467 }
3468 }
3469
3470 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3471 result = get_buffer_size(ctx, res_ptr, false);
3472 goto write_result;
3473 }
3474
3475 if (instr->op == nir_texop_texture_samples) {
3476 LLVMValueRef res, samples, is_msaa;
3477 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3478 samples = LLVMBuildExtractElement(ctx->builder, res,
3479 LLVMConstInt(ctx->i32, 3, false), "");
3480 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3481 LLVMConstInt(ctx->i32, 28, false), "");
3482 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3483 LLVMConstInt(ctx->i32, 0xe, false), "");
3484 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3485 LLVMConstInt(ctx->i32, 0xe, false), "");
3486
3487 samples = LLVMBuildLShr(ctx->builder, samples,
3488 LLVMConstInt(ctx->i32, 16, false), "");
3489 samples = LLVMBuildAnd(ctx->builder, samples,
3490 LLVMConstInt(ctx->i32, 0xf, false), "");
3491 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3492 samples, "");
3493 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3494 ctx->i32one, "");
3495 result = samples;
3496 goto write_result;
3497 }
3498
3499 if (coord)
3500 for (chan = 0; chan < instr->coord_components; chan++)
3501 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3502
3503 if (offsets && instr->op != nir_texop_txf) {
3504 LLVMValueRef offset[3], pack;
3505 for (chan = 0; chan < 3; ++chan)
3506 offset[chan] = ctx->i32zero;
3507
3508 tinfo.has_offset = true;
3509 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3510 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3511 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3512 LLVMConstInt(ctx->i32, 0x3f, false), "");
3513 if (chan)
3514 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3515 LLVMConstInt(ctx->i32, chan * 8, false), "");
3516 }
3517 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3518 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3519 address[count++] = pack;
3520
3521 }
3522 /* pack LOD bias value */
3523 if (instr->op == nir_texop_txb && bias) {
3524 address[count++] = bias;
3525 }
3526
3527 /* Pack depth comparison value */
3528 if (instr->is_shadow && comparator) {
3529 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3530 }
3531
3532 /* pack derivatives */
3533 if (ddx || ddy) {
3534 switch (instr->sampler_dim) {
3535 case GLSL_SAMPLER_DIM_3D:
3536 case GLSL_SAMPLER_DIM_CUBE:
3537 num_deriv_comp = 3;
3538 break;
3539 case GLSL_SAMPLER_DIM_2D:
3540 default:
3541 num_deriv_comp = 2;
3542 break;
3543 case GLSL_SAMPLER_DIM_1D:
3544 num_deriv_comp = 1;
3545 break;
3546 }
3547
3548 for (unsigned i = 0; i < num_deriv_comp; i++) {
3549 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3550 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3551 }
3552 }
3553
3554 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3555 for (chan = 0; chan < instr->coord_components; chan++)
3556 coords[chan] = to_float(ctx, coords[chan]);
3557 if (instr->coord_components == 3)
3558 coords[3] = LLVMGetUndef(ctx->f32);
3559 ac_prepare_cube_coords(&ctx->ac,
3560 instr->op == nir_texop_txd, instr->is_array,
3561 coords, derivs);
3562 if (num_deriv_comp)
3563 num_deriv_comp--;
3564 }
3565
3566 if (ddx || ddy) {
3567 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3568 address[count++] = derivs[i];
3569 }
3570
3571 /* Pack texture coordinates */
3572 if (coord) {
3573 address[count++] = coords[0];
3574 if (instr->coord_components > 1) {
3575 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3576 coords[1] = apply_round_slice(ctx, coords[1]);
3577 }
3578 address[count++] = coords[1];
3579 }
3580 if (instr->coord_components > 2) {
3581 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3582 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3583 coords[2] = apply_round_slice(ctx, coords[2]);
3584 }
3585 address[count++] = coords[2];
3586 }
3587 }
3588
3589 /* Pack LOD */
3590 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3591 address[count++] = lod;
3592 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3593 address[count++] = sample_index;
3594 } else if(instr->op == nir_texop_txs) {
3595 count = 0;
3596 if (lod)
3597 address[count++] = lod;
3598 else
3599 address[count++] = ctx->i32zero;
3600 }
3601
3602 for (chan = 0; chan < count; chan++) {
3603 address[chan] = LLVMBuildBitCast(ctx->builder,
3604 address[chan], ctx->i32, "");
3605 }
3606
3607 if (instr->op == nir_texop_samples_identical) {
3608 LLVMValueRef txf_address[4];
3609 struct ac_tex_info txf_info = { 0 };
3610 unsigned txf_count = count;
3611 memcpy(txf_address, address, sizeof(txf_address));
3612
3613 if (!instr->is_array)
3614 txf_address[2] = ctx->i32zero;
3615 txf_address[3] = ctx->i32zero;
3616
3617 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3618 fmask_ptr, NULL,
3619 txf_address, txf_count, 0xf);
3620
3621 result = build_tex_intrinsic(ctx, instr, &txf_info);
3622
3623 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3624 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3625 goto write_result;
3626 }
3627
3628 /* Adjust the sample index according to FMASK.
3629 *
3630 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3631 * which is the identity mapping. Each nibble says which physical sample
3632 * should be fetched to get that sample.
3633 *
3634 * For example, 0x11111100 means there are only 2 samples stored and
3635 * the second sample covers 3/4 of the pixel. When reading samples 0
3636 * and 1, return physical sample 0 (determined by the first two 0s
3637 * in FMASK), otherwise return physical sample 1.
3638 *
3639 * The sample index should be adjusted as follows:
3640 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3641 */
3642 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3643 instr->op != nir_texop_txs) {
3644 LLVMValueRef txf_address[4];
3645 struct ac_tex_info txf_info = { 0 };
3646 unsigned txf_count = count;
3647 memcpy(txf_address, address, sizeof(txf_address));
3648
3649 if (!instr->is_array)
3650 txf_address[2] = ctx->i32zero;
3651 txf_address[3] = ctx->i32zero;
3652
3653 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3654 fmask_ptr, NULL,
3655 txf_address, txf_count, 0xf);
3656
3657 result = build_tex_intrinsic(ctx, instr, &txf_info);
3658 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3659 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3660
3661 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3662 result,
3663 ctx->i32zero, "");
3664
3665 unsigned sample_chan = instr->is_array ? 3 : 2;
3666
3667 LLVMValueRef sample_index4 =
3668 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3669 LLVMValueRef shifted_fmask =
3670 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3671 LLVMValueRef final_sample =
3672 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3673
3674 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3675 * resource descriptor is 0 (invalid),
3676 */
3677 LLVMValueRef fmask_desc =
3678 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3679 ctx->v8i32, "");
3680
3681 LLVMValueRef fmask_word1 =
3682 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3683 ctx->i32one, "");
3684
3685 LLVMValueRef word1_is_nonzero =
3686 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3687 fmask_word1, ctx->i32zero, "");
3688
3689 /* Replace the MSAA sample index. */
3690 address[sample_chan] =
3691 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3692 final_sample, address[sample_chan], "");
3693 }
3694
3695 if (offsets && instr->op == nir_texop_txf) {
3696 nir_const_value *const_offset =
3697 nir_src_as_const_value(instr->src[const_src].src);
3698 int num_offsets = instr->src[const_src].src.ssa->num_components;
3699 assert(const_offset);
3700 num_offsets = MIN2(num_offsets, instr->coord_components);
3701 if (num_offsets > 2)
3702 address[2] = LLVMBuildAdd(ctx->builder,
3703 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3704 if (num_offsets > 1)
3705 address[1] = LLVMBuildAdd(ctx->builder,
3706 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3707 address[0] = LLVMBuildAdd(ctx->builder,
3708 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3709
3710 }
3711
3712 /* TODO TG4 support */
3713 if (instr->op == nir_texop_tg4) {
3714 if (instr->is_shadow)
3715 dmask = 1;
3716 else
3717 dmask = 1 << instr->component;
3718 }
3719 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3720 res_ptr, samp_ptr, address, count, dmask);
3721
3722 result = build_tex_intrinsic(ctx, instr, &tinfo);
3723
3724 if (instr->op == nir_texop_query_levels)
3725 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3726 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3727 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3728 else if (instr->op == nir_texop_txs &&
3729 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3730 instr->is_array) {
3731 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3732 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3733 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3734 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3735 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3736 } else if (instr->dest.ssa.num_components != 4)
3737 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3738
3739 write_result:
3740 if (result) {
3741 assert(instr->dest.is_ssa);
3742 result = to_integer(ctx, result);
3743 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3744 }
3745 }
3746
3747
3748 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3749 {
3750 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3751 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3752
3753 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3754 _mesa_hash_table_insert(ctx->phis, instr, result);
3755 }
3756
3757 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3758 nir_phi_instr *instr,
3759 LLVMValueRef llvm_phi)
3760 {
3761 nir_foreach_phi_src(src, instr) {
3762 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3763 LLVMValueRef llvm_src = get_src(ctx, src->src);
3764
3765 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3766 }
3767 }
3768
3769 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3770 {
3771 struct hash_entry *entry;
3772 hash_table_foreach(ctx->phis, entry) {
3773 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3774 (LLVMValueRef)entry->data);
3775 }
3776 }
3777
3778
3779 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3780 nir_ssa_undef_instr *instr)
3781 {
3782 unsigned num_components = instr->def.num_components;
3783 LLVMValueRef undef;
3784
3785 if (num_components == 1)
3786 undef = LLVMGetUndef(ctx->i32);
3787 else {
3788 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3789 }
3790 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3791 }
3792
3793 static void visit_jump(struct nir_to_llvm_context *ctx,
3794 nir_jump_instr *instr)
3795 {
3796 switch (instr->type) {
3797 case nir_jump_break:
3798 LLVMBuildBr(ctx->builder, ctx->break_block);
3799 LLVMClearInsertionPosition(ctx->builder);
3800 break;
3801 case nir_jump_continue:
3802 LLVMBuildBr(ctx->builder, ctx->continue_block);
3803 LLVMClearInsertionPosition(ctx->builder);
3804 break;
3805 default:
3806 fprintf(stderr, "Unknown NIR jump instr: ");
3807 nir_print_instr(&instr->instr, stderr);
3808 fprintf(stderr, "\n");
3809 abort();
3810 }
3811 }
3812
3813 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3814 struct exec_list *list);
3815
3816 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3817 {
3818 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3819 nir_foreach_instr(instr, block)
3820 {
3821 switch (instr->type) {
3822 case nir_instr_type_alu:
3823 visit_alu(ctx, nir_instr_as_alu(instr));
3824 break;
3825 case nir_instr_type_load_const:
3826 visit_load_const(ctx, nir_instr_as_load_const(instr));
3827 break;
3828 case nir_instr_type_intrinsic:
3829 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3830 break;
3831 case nir_instr_type_tex:
3832 visit_tex(ctx, nir_instr_as_tex(instr));
3833 break;
3834 case nir_instr_type_phi:
3835 visit_phi(ctx, nir_instr_as_phi(instr));
3836 break;
3837 case nir_instr_type_ssa_undef:
3838 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3839 break;
3840 case nir_instr_type_jump:
3841 visit_jump(ctx, nir_instr_as_jump(instr));
3842 break;
3843 default:
3844 fprintf(stderr, "Unknown NIR instr type: ");
3845 nir_print_instr(instr, stderr);
3846 fprintf(stderr, "\n");
3847 abort();
3848 }
3849 }
3850
3851 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3852 }
3853
3854 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3855 {
3856 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3857
3858 LLVMBasicBlockRef merge_block =
3859 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3860 LLVMBasicBlockRef if_block =
3861 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3862 LLVMBasicBlockRef else_block = merge_block;
3863 if (!exec_list_is_empty(&if_stmt->else_list))
3864 else_block = LLVMAppendBasicBlockInContext(
3865 ctx->context, ctx->main_function, "");
3866
3867 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3868 LLVMConstInt(ctx->i32, 0, false), "");
3869 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3870
3871 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3872 visit_cf_list(ctx, &if_stmt->then_list);
3873 if (LLVMGetInsertBlock(ctx->builder))
3874 LLVMBuildBr(ctx->builder, merge_block);
3875
3876 if (!exec_list_is_empty(&if_stmt->else_list)) {
3877 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3878 visit_cf_list(ctx, &if_stmt->else_list);
3879 if (LLVMGetInsertBlock(ctx->builder))
3880 LLVMBuildBr(ctx->builder, merge_block);
3881 }
3882
3883 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3884 }
3885
3886 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3887 {
3888 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3889 LLVMBasicBlockRef break_parent = ctx->break_block;
3890
3891 ctx->continue_block =
3892 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3893 ctx->break_block =
3894 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3895
3896 LLVMBuildBr(ctx->builder, ctx->continue_block);
3897 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3898 visit_cf_list(ctx, &loop->body);
3899
3900 if (LLVMGetInsertBlock(ctx->builder))
3901 LLVMBuildBr(ctx->builder, ctx->continue_block);
3902 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3903
3904 ctx->continue_block = continue_parent;
3905 ctx->break_block = break_parent;
3906 }
3907
3908 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3909 struct exec_list *list)
3910 {
3911 foreach_list_typed(nir_cf_node, node, node, list)
3912 {
3913 switch (node->type) {
3914 case nir_cf_node_block:
3915 visit_block(ctx, nir_cf_node_as_block(node));
3916 break;
3917
3918 case nir_cf_node_if:
3919 visit_if(ctx, nir_cf_node_as_if(node));
3920 break;
3921
3922 case nir_cf_node_loop:
3923 visit_loop(ctx, nir_cf_node_as_loop(node));
3924 break;
3925
3926 default:
3927 assert(0);
3928 }
3929 }
3930 }
3931
3932 static void
3933 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3934 struct nir_variable *variable)
3935 {
3936 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3937 LLVMValueRef t_offset;
3938 LLVMValueRef t_list;
3939 LLVMValueRef args[3];
3940 LLVMValueRef input;
3941 LLVMValueRef buffer_index;
3942 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3943 int idx = variable->data.location;
3944 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3945
3946 variable->data.driver_location = idx * 4;
3947
3948 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3949 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3950 ctx->start_instance, "");
3951 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3952 ctx->shader_info->vs.vgpr_comp_cnt);
3953 } else
3954 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3955 ctx->base_vertex, "");
3956
3957 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3958 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3959
3960 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
3961 args[0] = t_list;
3962 args[1] = LLVMConstInt(ctx->i32, 0, false);
3963 args[2] = buffer_index;
3964 input = ac_emit_llvm_intrinsic(&ctx->ac,
3965 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3966 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3967
3968 for (unsigned chan = 0; chan < 4; chan++) {
3969 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3970 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3971 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3972 input, llvm_chan, ""));
3973 }
3974 }
3975 }
3976
3977
3978 static void interp_fs_input(struct nir_to_llvm_context *ctx,
3979 unsigned attr,
3980 LLVMValueRef interp_param,
3981 LLVMValueRef prim_mask,
3982 LLVMValueRef result[4])
3983 {
3984 LLVMValueRef attr_number;
3985 unsigned chan;
3986 LLVMValueRef i, j;
3987 bool interp = interp_param != NULL;
3988
3989 attr_number = LLVMConstInt(ctx->i32, attr, false);
3990
3991 /* fs.constant returns the param from the middle vertex, so it's not
3992 * really useful for flat shading. It's meant to be used for custom
3993 * interpolation (but the intrinsic can't fetch from the other two
3994 * vertices).
3995 *
3996 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
3997 * to do the right thing. The only reason we use fs.constant is that
3998 * fs.interp cannot be used on integers, because they can be equal
3999 * to NaN.
4000 */
4001 if (interp) {
4002 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4003 LLVMVectorType(ctx->f32, 2), "");
4004
4005 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4006 ctx->i32zero, "");
4007 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4008 ctx->i32one, "");
4009 }
4010
4011 for (chan = 0; chan < 4; chan++) {
4012 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4013
4014 if (interp) {
4015 result[chan] = ac_build_fs_interp(&ctx->ac,
4016 llvm_chan,
4017 attr_number,
4018 prim_mask, i, j);
4019 } else {
4020 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4021 LLVMConstInt(ctx->i32, 2, false),
4022 llvm_chan,
4023 attr_number,
4024 prim_mask);
4025 }
4026 }
4027 }
4028
4029 static void
4030 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4031 struct nir_variable *variable)
4032 {
4033 int idx = variable->data.location;
4034 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4035 LLVMValueRef interp;
4036
4037 variable->data.driver_location = idx * 4;
4038 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4039
4040 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4041 unsigned interp_type;
4042 if (variable->data.sample) {
4043 interp_type = INTERP_SAMPLE;
4044 ctx->shader_info->fs.force_persample = true;
4045 } else if (variable->data.centroid)
4046 interp_type = INTERP_CENTROID;
4047 else
4048 interp_type = INTERP_CENTER;
4049
4050 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4051 } else
4052 interp = NULL;
4053
4054 for (unsigned i = 0; i < attrib_count; ++i)
4055 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4056
4057 }
4058
4059 static void
4060 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4061 struct nir_variable *variable)
4062 {
4063 switch (ctx->stage) {
4064 case MESA_SHADER_VERTEX:
4065 handle_vs_input_decl(ctx, variable);
4066 break;
4067 case MESA_SHADER_FRAGMENT:
4068 handle_fs_input_decl(ctx, variable);
4069 break;
4070 default:
4071 break;
4072 }
4073
4074 }
4075
4076 static void
4077 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4078 struct nir_shader *nir)
4079 {
4080 unsigned index = 0;
4081 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4082 LLVMValueRef interp_param;
4083 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4084
4085 if (!(ctx->input_mask & (1ull << i)))
4086 continue;
4087
4088 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4089 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4090 interp_param = *inputs;
4091 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4092 inputs);
4093
4094 if (!interp_param)
4095 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4096 ++index;
4097 } else if (i == VARYING_SLOT_POS) {
4098 for(int i = 0; i < 3; ++i)
4099 inputs[i] = ctx->frag_pos[i];
4100
4101 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4102 }
4103 }
4104 ctx->shader_info->fs.num_interp = index;
4105 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4106 ctx->shader_info->fs.has_pcoord = true;
4107 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4108 ctx->shader_info->fs.prim_id_input = true;
4109 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4110 ctx->shader_info->fs.layer_input = true;
4111 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4112 }
4113
4114 static LLVMValueRef
4115 ac_build_alloca(struct nir_to_llvm_context *ctx,
4116 LLVMTypeRef type,
4117 const char *name)
4118 {
4119 LLVMBuilderRef builder = ctx->builder;
4120 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4121 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4122 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4123 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4124 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4125 LLVMValueRef res;
4126
4127 if (first_instr) {
4128 LLVMPositionBuilderBefore(first_builder, first_instr);
4129 } else {
4130 LLVMPositionBuilderAtEnd(first_builder, first_block);
4131 }
4132
4133 res = LLVMBuildAlloca(first_builder, type, name);
4134 LLVMBuildStore(builder, LLVMConstNull(type), res);
4135
4136 LLVMDisposeBuilder(first_builder);
4137
4138 return res;
4139 }
4140
4141 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4142 LLVMTypeRef type,
4143 const char *name)
4144 {
4145 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4146 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4147 return ptr;
4148 }
4149
4150 static void
4151 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4152 struct nir_variable *variable)
4153 {
4154 int idx = variable->data.location + variable->data.index;
4155 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4156
4157 variable->data.driver_location = idx * 4;
4158
4159 if (ctx->stage == MESA_SHADER_VERTEX ||
4160 ctx->stage == MESA_SHADER_GEOMETRY) {
4161 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4162 idx == VARYING_SLOT_CULL_DIST0) {
4163 int length = glsl_get_length(variable->type);
4164 if (ctx->stage == MESA_SHADER_VERTEX) {
4165 if (idx == VARYING_SLOT_CLIP_DIST0) {
4166 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4167 ctx->num_clips = length;
4168 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4169 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4170 ctx->num_culls = length;
4171 }
4172 }
4173 if (length > 4)
4174 attrib_count = 2;
4175 else
4176 attrib_count = 1;
4177 }
4178 }
4179
4180 for (unsigned i = 0; i < attrib_count; ++i) {
4181 for (unsigned chan = 0; chan < 4; chan++) {
4182 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4183 si_build_alloca_undef(ctx, ctx->f32, "");
4184 }
4185 }
4186 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4187 }
4188
4189 static void
4190 setup_locals(struct nir_to_llvm_context *ctx,
4191 struct nir_function *func)
4192 {
4193 int i, j;
4194 ctx->num_locals = 0;
4195 nir_foreach_variable(variable, &func->impl->locals) {
4196 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4197 variable->data.driver_location = ctx->num_locals * 4;
4198 ctx->num_locals += attrib_count;
4199 }
4200 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4201 if (!ctx->locals)
4202 return;
4203
4204 for (i = 0; i < ctx->num_locals; i++) {
4205 for (j = 0; j < 4; j++) {
4206 ctx->locals[i * 4 + j] =
4207 si_build_alloca_undef(ctx, ctx->f32, "temp");
4208 }
4209 }
4210 }
4211
4212 static LLVMValueRef
4213 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4214 {
4215 v = to_float(ctx, v);
4216 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4217 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4218 }
4219
4220
4221 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4222 LLVMValueRef src0, LLVMValueRef src1)
4223 {
4224 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4225 LLVMValueRef comp[2];
4226
4227 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4228 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4229 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4230 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4231 }
4232
4233 /* Initialize arguments for the shader export intrinsic */
4234 static void
4235 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4236 LLVMValueRef *values,
4237 unsigned target,
4238 LLVMValueRef *args)
4239 {
4240 /* Default is 0xf. Adjusted below depending on the format. */
4241 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4242 /* Specify whether the EXEC mask represents the valid mask */
4243 args[1] = LLVMConstInt(ctx->i32, 0, false);
4244
4245 /* Specify whether this is the last export */
4246 args[2] = LLVMConstInt(ctx->i32, 0, false);
4247 /* Specify the target we are exporting */
4248 args[3] = LLVMConstInt(ctx->i32, target, false);
4249
4250 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4251 args[5] = LLVMGetUndef(ctx->f32);
4252 args[6] = LLVMGetUndef(ctx->f32);
4253 args[7] = LLVMGetUndef(ctx->f32);
4254 args[8] = LLVMGetUndef(ctx->f32);
4255
4256 if (!values)
4257 return;
4258
4259 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4260 LLVMValueRef val[4];
4261 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4262 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4263 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4264
4265 switch(col_format) {
4266 case V_028714_SPI_SHADER_ZERO:
4267 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4268 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4269 break;
4270
4271 case V_028714_SPI_SHADER_32_R:
4272 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4273 args[5] = values[0];
4274 break;
4275
4276 case V_028714_SPI_SHADER_32_GR:
4277 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4278 args[5] = values[0];
4279 args[6] = values[1];
4280 break;
4281
4282 case V_028714_SPI_SHADER_32_AR:
4283 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4284 args[5] = values[0];
4285 args[8] = values[3];
4286 break;
4287
4288 case V_028714_SPI_SHADER_FP16_ABGR:
4289 args[4] = ctx->i32one;
4290
4291 for (unsigned chan = 0; chan < 2; chan++) {
4292 LLVMValueRef pack_args[2] = {
4293 values[2 * chan],
4294 values[2 * chan + 1]
4295 };
4296 LLVMValueRef packed;
4297
4298 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4299 ctx->i32, pack_args, 2,
4300 AC_FUNC_ATTR_READNONE);
4301 args[chan + 5] = packed;
4302 }
4303 break;
4304
4305 case V_028714_SPI_SHADER_UNORM16_ABGR:
4306 for (unsigned chan = 0; chan < 4; chan++) {
4307 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4308 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4309 LLVMConstReal(ctx->f32, 65535), "");
4310 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4311 LLVMConstReal(ctx->f32, 0.5), "");
4312 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4313 ctx->i32, "");
4314 }
4315
4316 args[4] = ctx->i32one;
4317 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4318 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4319 break;
4320
4321 case V_028714_SPI_SHADER_SNORM16_ABGR:
4322 for (unsigned chan = 0; chan < 4; chan++) {
4323 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4324 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4325 LLVMConstReal(ctx->f32, 32767), "");
4326
4327 /* If positive, add 0.5, else add -0.5. */
4328 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4329 LLVMBuildSelect(ctx->builder,
4330 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4331 val[chan], ctx->f32zero, ""),
4332 LLVMConstReal(ctx->f32, 0.5),
4333 LLVMConstReal(ctx->f32, -0.5), ""), "");
4334 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4335 }
4336
4337 args[4] = ctx->i32one;
4338 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4339 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4340 break;
4341
4342 case V_028714_SPI_SHADER_UINT16_ABGR: {
4343 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4344
4345 for (unsigned chan = 0; chan < 4; chan++) {
4346 val[chan] = to_integer(ctx, values[chan]);
4347 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4348 }
4349
4350 args[4] = ctx->i32one;
4351 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4352 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4353 break;
4354 }
4355
4356 case V_028714_SPI_SHADER_SINT16_ABGR: {
4357 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4358 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4359
4360 /* Clamp. */
4361 for (unsigned chan = 0; chan < 4; chan++) {
4362 val[chan] = to_integer(ctx, values[chan]);
4363 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4364 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4365 }
4366
4367 args[4] = ctx->i32one;
4368 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4369 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4370 break;
4371 }
4372
4373 default:
4374 case V_028714_SPI_SHADER_32_ABGR:
4375 memcpy(&args[5], values, sizeof(values[0]) * 4);
4376 break;
4377 }
4378 } else
4379 memcpy(&args[5], values, sizeof(values[0]) * 4);
4380
4381 for (unsigned i = 5; i < 9; ++i)
4382 args[i] = to_float(ctx, args[i]);
4383 }
4384
4385 static void
4386 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4387 {
4388 uint32_t param_count = 0;
4389 unsigned target;
4390 unsigned pos_idx, num_pos_exports = 0;
4391 LLVMValueRef args[9];
4392 LLVMValueRef pos_args[4][9] = { { 0 } };
4393 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4394 int i;
4395 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4396 (1ull << VARYING_SLOT_CLIP_DIST1) |
4397 (1ull << VARYING_SLOT_CULL_DIST0) |
4398 (1ull << VARYING_SLOT_CULL_DIST1));
4399
4400 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4401 ctx->shader_info->vs.layer_output = 0xffffffff;
4402 if (clip_mask) {
4403 LLVMValueRef slots[8];
4404 unsigned j;
4405
4406 if (ctx->shader_info->vs.cull_dist_mask)
4407 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_clips;
4408
4409 i = VARYING_SLOT_CLIP_DIST0;
4410 for (j = 0; j < ctx->num_clips; j++)
4411 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4412 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4413 i = VARYING_SLOT_CULL_DIST0;
4414 for (j = 0; j < ctx->num_culls; j++)
4415 slots[ctx->num_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4416 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4417
4418 for (i = ctx->num_clips + ctx->num_culls; i < 8; i++)
4419 slots[i] = LLVMGetUndef(ctx->f32);
4420
4421 if (ctx->num_clips + ctx->num_culls > 4) {
4422 target = V_008DFC_SQ_EXP_POS + 3;
4423 si_llvm_init_export_args(ctx, &slots[4], target, args);
4424 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4425 args, sizeof(args));
4426 }
4427
4428 target = V_008DFC_SQ_EXP_POS + 2;
4429 si_llvm_init_export_args(ctx, &slots[0], target, args);
4430 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4431 args, sizeof(args));
4432
4433 }
4434
4435 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4436 LLVMValueRef values[4];
4437 if (!(ctx->output_mask & (1ull << i)))
4438 continue;
4439
4440 for (unsigned j = 0; j < 4; j++)
4441 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4442 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4443
4444 if (i == VARYING_SLOT_POS) {
4445 target = V_008DFC_SQ_EXP_POS;
4446 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4447 i == VARYING_SLOT_CLIP_DIST1 ||
4448 i == VARYING_SLOT_CULL_DIST0 ||
4449 i == VARYING_SLOT_CULL_DIST1) {
4450 continue;
4451 } else if (i == VARYING_SLOT_PSIZ) {
4452 ctx->shader_info->vs.writes_pointsize = true;
4453 psize_value = values[0];
4454 continue;
4455 } else if (i == VARYING_SLOT_LAYER) {
4456 ctx->shader_info->vs.writes_layer = true;
4457 layer_value = values[0];
4458 ctx->shader_info->vs.layer_output = param_count;
4459 target = V_008DFC_SQ_EXP_PARAM + param_count;
4460 param_count++;
4461 } else if (i == VARYING_SLOT_VIEWPORT) {
4462 ctx->shader_info->vs.writes_viewport_index = true;
4463 viewport_index_value = values[0];
4464 continue;
4465 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4466 ctx->shader_info->vs.prim_id_output = param_count;
4467 target = V_008DFC_SQ_EXP_PARAM + param_count;
4468 param_count++;
4469 } else if (i >= VARYING_SLOT_VAR0) {
4470 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4471 target = V_008DFC_SQ_EXP_PARAM + param_count;
4472 param_count++;
4473 }
4474
4475 si_llvm_init_export_args(ctx, values, target, args);
4476
4477 if (target >= V_008DFC_SQ_EXP_POS &&
4478 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4479 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4480 args, sizeof(args));
4481 } else {
4482 ac_emit_llvm_intrinsic(&ctx->ac,
4483 "llvm.SI.export",
4484 ctx->voidt,
4485 args, 9, 0);
4486 }
4487 }
4488
4489 /* We need to add the position output manually if it's missing. */
4490 if (!pos_args[0][0]) {
4491 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4492 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4493 pos_args[0][2] = ctx->i32zero; /* last export? */
4494 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4495 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4496 pos_args[0][5] = ctx->f32zero; /* X */
4497 pos_args[0][6] = ctx->f32zero; /* Y */
4498 pos_args[0][7] = ctx->f32zero; /* Z */
4499 pos_args[0][8] = ctx->f32one; /* W */
4500 }
4501
4502 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4503 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4504 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4505 if (mask) {
4506 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4507 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4508 pos_args[1][2] = ctx->i32zero; /* last export? */
4509 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4510 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4511 pos_args[1][5] = ctx->f32zero; /* X */
4512 pos_args[1][6] = ctx->f32zero; /* Y */
4513 pos_args[1][7] = ctx->f32zero; /* Z */
4514 pos_args[1][8] = ctx->f32zero; /* W */
4515
4516 if (ctx->shader_info->vs.writes_pointsize == true)
4517 pos_args[1][5] = psize_value;
4518 if (ctx->shader_info->vs.writes_layer == true)
4519 pos_args[1][7] = layer_value;
4520 if (ctx->shader_info->vs.writes_viewport_index == true)
4521 pos_args[1][8] = viewport_index_value;
4522 }
4523 for (i = 0; i < 4; i++) {
4524 if (pos_args[i][0])
4525 num_pos_exports++;
4526 }
4527
4528 pos_idx = 0;
4529 for (i = 0; i < 4; i++) {
4530 if (!pos_args[i][0])
4531 continue;
4532
4533 /* Specify the target we are exporting */
4534 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4535 if (pos_idx == num_pos_exports)
4536 pos_args[i][2] = ctx->i32one;
4537 ac_emit_llvm_intrinsic(&ctx->ac,
4538 "llvm.SI.export",
4539 ctx->voidt,
4540 pos_args[i], 9, 0);
4541 }
4542
4543 ctx->shader_info->vs.pos_exports = num_pos_exports;
4544 ctx->shader_info->vs.param_exports = param_count;
4545 }
4546
4547 static void
4548 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4549 {
4550 int j;
4551 uint64_t max_output_written = 0;
4552 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4553 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4554 int param_index;
4555 if (!(ctx->output_mask & (1ull << i)))
4556 continue;
4557
4558 param_index = shader_io_get_unique_index(i);
4559
4560 if (param_index > max_output_written)
4561 max_output_written = param_index;
4562
4563 for (j = 0; j < 4; j++) {
4564 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4565 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4566
4567 ac_build_tbuffer_store(&ctx->ac,
4568 ctx->esgs_ring,
4569 out_val, 1,
4570 LLVMGetUndef(ctx->i32), ctx->es2gs_offset,
4571 (4 * param_index + j) * 4,
4572 V_008F0C_BUF_DATA_FORMAT_32,
4573 V_008F0C_BUF_NUM_FORMAT_UINT,
4574 0, 0, 1, 1, 0);
4575 }
4576 }
4577 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4578 }
4579
4580 static void
4581 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4582 LLVMValueRef *color, unsigned param, bool is_last)
4583 {
4584 LLVMValueRef args[9];
4585 /* Export */
4586 si_llvm_init_export_args(ctx, color, param,
4587 args);
4588
4589 if (is_last) {
4590 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4591 args[2] = ctx->i32one; /* DONE bit */
4592 } else if (args[0] == ctx->i32zero)
4593 return; /* unnecessary NULL export */
4594
4595 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4596 ctx->voidt, args, 9, 0);
4597 }
4598
4599 static void
4600 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4601 LLVMValueRef depth, LLVMValueRef stencil,
4602 LLVMValueRef samplemask)
4603 {
4604 LLVMValueRef args[9];
4605 unsigned mask = 0;
4606 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4607 args[2] = ctx->i32one; /* DONE bit */
4608 /* Specify the target we are exporting */
4609 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4610
4611 args[4] = ctx->i32zero; /* COMP flag */
4612 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4613 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4614 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4615 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4616
4617 if (depth) {
4618 args[5] = depth;
4619 mask |= 0x1;
4620 }
4621
4622 if (stencil) {
4623 args[6] = stencil;
4624 mask |= 0x2;
4625 }
4626
4627 if (samplemask) {
4628 args[7] = samplemask;
4629 mask |= 0x04;
4630 }
4631
4632 /* SI (except OLAND) has a bug that it only looks
4633 * at the X writemask component. */
4634 if (ctx->options->chip_class == SI &&
4635 ctx->options->family != CHIP_OLAND)
4636 mask |= 0x01;
4637
4638 args[0] = LLVMConstInt(ctx->i32, mask, false);
4639 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4640 ctx->voidt, args, 9, 0);
4641 }
4642
4643 static void
4644 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4645 {
4646 unsigned index = 0;
4647 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4648
4649 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4650 LLVMValueRef values[4];
4651
4652 if (!(ctx->output_mask & (1ull << i)))
4653 continue;
4654
4655 if (i == FRAG_RESULT_DEPTH) {
4656 ctx->shader_info->fs.writes_z = true;
4657 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4658 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4659 } else if (i == FRAG_RESULT_STENCIL) {
4660 ctx->shader_info->fs.writes_stencil = true;
4661 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4662 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4663 } else {
4664 bool last = false;
4665 for (unsigned j = 0; j < 4; j++)
4666 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4667 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4668
4669 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4670 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4671
4672 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4673 index++;
4674 }
4675 }
4676
4677 if (depth || stencil)
4678 si_export_mrt_z(ctx, depth, stencil, samplemask);
4679 else if (!index)
4680 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4681
4682 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4683 }
4684
4685 static void
4686 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4687 {
4688 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4689 }
4690
4691 static void
4692 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4693 {
4694 switch (ctx->stage) {
4695 case MESA_SHADER_VERTEX:
4696 if (ctx->options->key.vs.as_es)
4697 handle_es_outputs_post(ctx);
4698 else
4699 handle_vs_outputs_post(ctx);
4700 break;
4701 case MESA_SHADER_FRAGMENT:
4702 handle_fs_outputs_post(ctx);
4703 break;
4704 case MESA_SHADER_GEOMETRY:
4705 emit_gs_epilogue(ctx);
4706 break;
4707 default:
4708 break;
4709 }
4710 }
4711
4712 static void
4713 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4714 struct nir_variable *variable, uint32_t *offset, int idx)
4715 {
4716 unsigned size = glsl_count_attribute_slots(variable->type, false);
4717 variable->data.driver_location = *offset;
4718 *offset += size;
4719 }
4720
4721 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4722 {
4723 LLVMPassManagerRef passmgr;
4724 /* Create the pass manager */
4725 passmgr = LLVMCreateFunctionPassManagerForModule(
4726 ctx->module);
4727
4728 /* This pass should eliminate all the load and store instructions */
4729 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4730
4731 /* Add some optimization passes */
4732 LLVMAddScalarReplAggregatesPass(passmgr);
4733 LLVMAddLICMPass(passmgr);
4734 LLVMAddAggressiveDCEPass(passmgr);
4735 LLVMAddCFGSimplificationPass(passmgr);
4736 LLVMAddInstructionCombiningPass(passmgr);
4737
4738 /* Run the pass */
4739 LLVMInitializeFunctionPassManager(passmgr);
4740 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4741 LLVMFinalizeFunctionPassManager(passmgr);
4742
4743 LLVMDisposeBuilder(ctx->builder);
4744 LLVMDisposePassManager(passmgr);
4745 }
4746
4747 static void
4748 ac_setup_rings(struct nir_to_llvm_context *ctx)
4749 {
4750 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4751 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4752 }
4753
4754 if (ctx->is_gs_copy_shader) {
4755 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4756 }
4757 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4758 LLVMValueRef tmp;
4759 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4760 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4761
4762 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4763
4764 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4765 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4766 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4767 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4768
4769 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4770 }
4771 }
4772
4773 static
4774 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4775 struct nir_shader *nir,
4776 struct ac_shader_variant_info *shader_info,
4777 const struct ac_nir_compiler_options *options)
4778 {
4779 struct nir_to_llvm_context ctx = {0};
4780 struct nir_function *func;
4781 unsigned i;
4782 ctx.options = options;
4783 ctx.shader_info = shader_info;
4784 ctx.context = LLVMContextCreate();
4785 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4786
4787 ac_llvm_context_init(&ctx.ac, ctx.context);
4788 ctx.ac.module = ctx.module;
4789
4790 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4791
4792 memset(shader_info, 0, sizeof(*shader_info));
4793
4794 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4795 setup_types(&ctx);
4796
4797 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4798 ctx.ac.builder = ctx.builder;
4799 ctx.stage = nir->stage;
4800
4801 for (i = 0; i < AC_UD_MAX_SETS; i++)
4802 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4803 for (i = 0; i < AC_UD_MAX_UD; i++)
4804 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4805
4806 create_function(&ctx);
4807
4808 if (nir->stage == MESA_SHADER_COMPUTE) {
4809 int num_shared = 0;
4810 nir_foreach_variable(variable, &nir->shared)
4811 num_shared++;
4812 if (num_shared) {
4813 int idx = 0;
4814 uint32_t shared_size = 0;
4815 LLVMValueRef var;
4816 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4817 nir_foreach_variable(variable, &nir->shared) {
4818 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4819 idx++;
4820 }
4821
4822 shared_size *= 16;
4823 var = LLVMAddGlobalInAddressSpace(ctx.module,
4824 LLVMArrayType(ctx.i8, shared_size),
4825 "compute_lds",
4826 LOCAL_ADDR_SPACE);
4827 LLVMSetAlignment(var, 4);
4828 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4829 }
4830 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4831 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4832
4833 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4834 }
4835
4836 ac_setup_rings(&ctx);
4837
4838 nir_foreach_variable(variable, &nir->inputs)
4839 handle_shader_input_decl(&ctx, variable);
4840
4841 if (nir->stage == MESA_SHADER_FRAGMENT)
4842 handle_fs_inputs_pre(&ctx, nir);
4843
4844 nir_foreach_variable(variable, &nir->outputs)
4845 handle_shader_output_decl(&ctx, variable);
4846
4847 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4848 _mesa_key_pointer_equal);
4849 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4850 _mesa_key_pointer_equal);
4851
4852 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4853
4854 setup_locals(&ctx, func);
4855
4856 visit_cf_list(&ctx, &func->impl->body);
4857 phi_post_pass(&ctx);
4858
4859 handle_shader_outputs_post(&ctx);
4860 LLVMBuildRetVoid(ctx.builder);
4861
4862 ac_llvm_finalize_module(&ctx);
4863 free(ctx.locals);
4864 ralloc_free(ctx.defs);
4865 ralloc_free(ctx.phis);
4866
4867 if (nir->stage == MESA_SHADER_GEOMETRY) {
4868 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4869 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4870 nir->info->gs.vertices_out;
4871 }
4872 return ctx.module;
4873 }
4874
4875 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4876 {
4877 unsigned *retval = (unsigned *)context;
4878 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4879 char *description = LLVMGetDiagInfoDescription(di);
4880
4881 if (severity == LLVMDSError) {
4882 *retval = 1;
4883 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4884 description);
4885 }
4886
4887 LLVMDisposeMessage(description);
4888 }
4889
4890 static unsigned ac_llvm_compile(LLVMModuleRef M,
4891 struct ac_shader_binary *binary,
4892 LLVMTargetMachineRef tm)
4893 {
4894 unsigned retval = 0;
4895 char *err;
4896 LLVMContextRef llvm_ctx;
4897 LLVMMemoryBufferRef out_buffer;
4898 unsigned buffer_size;
4899 const char *buffer_data;
4900 LLVMBool mem_err;
4901
4902 /* Setup Diagnostic Handler*/
4903 llvm_ctx = LLVMGetModuleContext(M);
4904
4905 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4906 &retval);
4907
4908 /* Compile IR*/
4909 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4910 &err, &out_buffer);
4911
4912 /* Process Errors/Warnings */
4913 if (mem_err) {
4914 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4915 free(err);
4916 retval = 1;
4917 goto out;
4918 }
4919
4920 /* Extract Shader Code*/
4921 buffer_size = LLVMGetBufferSize(out_buffer);
4922 buffer_data = LLVMGetBufferStart(out_buffer);
4923
4924 ac_elf_read(buffer_data, buffer_size, binary);
4925
4926 /* Clean up */
4927 LLVMDisposeMemoryBuffer(out_buffer);
4928
4929 out:
4930 return retval;
4931 }
4932
4933 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4934 LLVMModuleRef llvm_module,
4935 struct ac_shader_binary *binary,
4936 struct ac_shader_config *config,
4937 struct ac_shader_variant_info *shader_info,
4938 gl_shader_stage stage,
4939 bool dump_shader, bool supports_spill)
4940 {
4941 if (dump_shader)
4942 ac_dump_module(llvm_module);
4943
4944 memset(binary, 0, sizeof(*binary));
4945 int v = ac_llvm_compile(llvm_module, binary, tm);
4946 if (v) {
4947 fprintf(stderr, "compile failed\n");
4948 }
4949
4950 if (dump_shader)
4951 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4952
4953 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4954
4955 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4956 LLVMDisposeModule(llvm_module);
4957 LLVMContextDispose(ctx);
4958
4959 if (stage == MESA_SHADER_FRAGMENT) {
4960 shader_info->num_input_vgprs = 0;
4961 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4962 shader_info->num_input_vgprs += 2;
4963 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4964 shader_info->num_input_vgprs += 2;
4965 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4966 shader_info->num_input_vgprs += 2;
4967 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4968 shader_info->num_input_vgprs += 3;
4969 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
4970 shader_info->num_input_vgprs += 2;
4971 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
4972 shader_info->num_input_vgprs += 2;
4973 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
4974 shader_info->num_input_vgprs += 2;
4975 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
4976 shader_info->num_input_vgprs += 1;
4977 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
4978 shader_info->num_input_vgprs += 1;
4979 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
4980 shader_info->num_input_vgprs += 1;
4981 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
4982 shader_info->num_input_vgprs += 1;
4983 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
4984 shader_info->num_input_vgprs += 1;
4985 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
4986 shader_info->num_input_vgprs += 1;
4987 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
4988 shader_info->num_input_vgprs += 1;
4989 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
4990 shader_info->num_input_vgprs += 1;
4991 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
4992 shader_info->num_input_vgprs += 1;
4993 }
4994 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
4995
4996 /* +3 for scratch wave offset and VCC */
4997 config->num_sgprs = MAX2(config->num_sgprs,
4998 shader_info->num_input_sgprs + 3);
4999 }
5000
5001 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5002 struct ac_shader_binary *binary,
5003 struct ac_shader_config *config,
5004 struct ac_shader_variant_info *shader_info,
5005 struct nir_shader *nir,
5006 const struct ac_nir_compiler_options *options,
5007 bool dump_shader)
5008 {
5009
5010 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5011 options);
5012
5013 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5014 switch (nir->stage) {
5015 case MESA_SHADER_COMPUTE:
5016 for (int i = 0; i < 3; ++i)
5017 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5018 break;
5019 case MESA_SHADER_FRAGMENT:
5020 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5021 break;
5022 case MESA_SHADER_GEOMETRY:
5023 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5024 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5025 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5026 shader_info->gs.invocations = nir->info->gs.invocations;
5027 break;
5028 case MESA_SHADER_VERTEX:
5029 shader_info->vs.as_es = options->key.vs.as_es;
5030 break;
5031 default:
5032 break;
5033 }
5034 }
5035
5036 static void
5037 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5038 {
5039 LLVMValueRef args[9];
5040 args[0] = ctx->gsvs_ring;
5041 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5042 args[3] = ctx->i32zero;
5043 args[4] = ctx->i32one; /* OFFEN */
5044 args[5] = ctx->i32zero; /* IDXEN */
5045 args[6] = ctx->i32one; /* GLC */
5046 args[7] = ctx->i32one; /* SLC */
5047 args[8] = ctx->i32zero; /* TFE */
5048
5049 int idx = 0;
5050 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5051 if (!(ctx->output_mask & (1ull << i)))
5052 continue;
5053
5054 for (unsigned j = 0; j < 4; j++) {
5055 LLVMValueRef value;
5056 args[2] = LLVMConstInt(ctx->i32,
5057 (idx * 4 + j) *
5058 ctx->gs_max_out_vertices * 16 * 4, false);
5059
5060 value = ac_emit_llvm_intrinsic(&ctx->ac,
5061 "llvm.SI.buffer.load.dword.i32.i32",
5062 ctx->i32, args, 9,
5063 AC_FUNC_ATTR_READONLY);
5064
5065 LLVMBuildStore(ctx->builder,
5066 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5067 }
5068 idx++;
5069 }
5070 handle_vs_outputs_post(ctx);
5071 }
5072
5073 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5074 struct nir_shader *geom_shader,
5075 struct ac_shader_binary *binary,
5076 struct ac_shader_config *config,
5077 struct ac_shader_variant_info *shader_info,
5078 const struct ac_nir_compiler_options *options,
5079 bool dump_shader)
5080 {
5081 struct nir_to_llvm_context ctx = {0};
5082 ctx.context = LLVMContextCreate();
5083 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5084 ctx.options = options;
5085 ctx.shader_info = shader_info;
5086
5087 ac_llvm_context_init(&ctx.ac, ctx.context);
5088 ctx.ac.module = ctx.module;
5089
5090 ctx.is_gs_copy_shader = true;
5091 LLVMSetTarget(ctx.module, "amdgcn--");
5092 setup_types(&ctx);
5093
5094 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5095 ctx.ac.builder = ctx.builder;
5096 ctx.stage = MESA_SHADER_VERTEX;
5097
5098 create_function(&ctx);
5099
5100 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5101 ac_setup_rings(&ctx);
5102
5103 nir_foreach_variable(variable, &geom_shader->outputs)
5104 handle_shader_output_decl(&ctx, variable);
5105
5106 ac_gs_copy_shader_emit(&ctx);
5107
5108 LLVMBuildRetVoid(ctx.builder);
5109
5110 ac_llvm_finalize_module(&ctx);
5111
5112 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5113 MESA_SHADER_VERTEX,
5114 dump_shader, options->supports_spill);
5115 }