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ac/llvm: add i1false/i1true to common code.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef merged_wave_info;
112 LLVMValueRef tess_factor_offset;
113 LLVMValueRef tcs_patch_id;
114 LLVMValueRef tcs_rel_ids;
115 LLVMValueRef tes_rel_patch_id;
116 LLVMValueRef tes_patch_id;
117 LLVMValueRef tes_u;
118 LLVMValueRef tes_v;
119
120 LLVMValueRef gsvs_ring_stride;
121 LLVMValueRef gsvs_num_entries;
122 LLVMValueRef gs2vs_offset;
123 LLVMValueRef gs_wave_id;
124 LLVMValueRef gs_vtx_offset[6];
125 LLVMValueRef gs_prim_id, gs_invocation_id;
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 LLVMTypeRef i1;
138 LLVMTypeRef i8;
139 LLVMTypeRef i16;
140 LLVMTypeRef i32;
141 LLVMTypeRef i64;
142 LLVMTypeRef v2i32;
143 LLVMTypeRef v3i32;
144 LLVMTypeRef v4i32;
145 LLVMTypeRef v8i32;
146 LLVMTypeRef f64;
147 LLVMTypeRef f32;
148 LLVMTypeRef f16;
149 LLVMTypeRef v2f32;
150 LLVMTypeRef v4f32;
151 LLVMTypeRef voidt;
152
153 LLVMValueRef v4f32empty;
154
155 unsigned uniform_md_kind;
156 LLVMValueRef empty_md;
157 gl_shader_stage stage;
158
159 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
160
161 uint64_t input_mask;
162 uint64_t output_mask;
163 uint8_t num_output_clips;
164 uint8_t num_output_culls;
165
166 bool is_gs_copy_shader;
167 LLVMValueRef gs_next_vertex;
168 unsigned gs_max_out_vertices;
169
170 unsigned tes_primitive_mode;
171 uint64_t tess_outputs_written;
172 uint64_t tess_patch_outputs_written;
173 };
174
175 static inline struct nir_to_llvm_context *
176 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
177 {
178 struct nir_to_llvm_context *ctx = NULL;
179 return container_of(abi, ctx, abi);
180 }
181
182 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
183 const nir_deref_var *deref,
184 enum ac_descriptor_type desc_type,
185 bool image, bool write);
186
187 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
188 {
189 return (index * 4) + chan;
190 }
191
192 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
193 {
194 /* handle patch indices separate */
195 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
196 return 0;
197 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
198 return 1;
199 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
200 return 2 + (slot - VARYING_SLOT_PATCH0);
201
202 if (slot == VARYING_SLOT_POS)
203 return 0;
204 if (slot == VARYING_SLOT_PSIZ)
205 return 1;
206 if (slot == VARYING_SLOT_CLIP_DIST0)
207 return 2;
208 /* 3 is reserved for clip dist as well */
209 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
210 return 4 + (slot - VARYING_SLOT_VAR0);
211 unreachable("illegal slot in get unique index\n");
212 }
213
214 static void set_llvm_calling_convention(LLVMValueRef func,
215 gl_shader_stage stage)
216 {
217 enum radeon_llvm_calling_convention calling_conv;
218
219 switch (stage) {
220 case MESA_SHADER_VERTEX:
221 case MESA_SHADER_TESS_EVAL:
222 calling_conv = RADEON_LLVM_AMDGPU_VS;
223 break;
224 case MESA_SHADER_GEOMETRY:
225 calling_conv = RADEON_LLVM_AMDGPU_GS;
226 break;
227 case MESA_SHADER_TESS_CTRL:
228 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_FRAGMENT:
231 calling_conv = RADEON_LLVM_AMDGPU_PS;
232 break;
233 case MESA_SHADER_COMPUTE:
234 calling_conv = RADEON_LLVM_AMDGPU_CS;
235 break;
236 default:
237 unreachable("Unhandle shader type");
238 }
239
240 LLVMSetFunctionCallConv(func, calling_conv);
241 }
242
243 #define MAX_ARGS 23
244 struct arg_info {
245 LLVMTypeRef types[MAX_ARGS];
246 LLVMValueRef *assign[MAX_ARGS];
247 unsigned array_params_mask;
248 uint8_t count;
249 uint8_t user_sgpr_count;
250 uint8_t sgpr_count;
251 uint8_t num_user_sgprs_used;
252 uint8_t num_sgprs_used;
253 uint8_t num_vgprs_used;
254 };
255
256 static inline void
257 add_argument(struct arg_info *info,
258 LLVMTypeRef type, LLVMValueRef *param_ptr)
259 {
260 assert(info->count < MAX_ARGS);
261 info->assign[info->count] = param_ptr;
262 info->types[info->count] = type;
263 info->count++;
264 }
265
266 static inline void
267 add_sgpr_argument(struct arg_info *info,
268 LLVMTypeRef type, LLVMValueRef *param_ptr)
269 {
270 add_argument(info, type, param_ptr);
271 info->num_sgprs_used += ac_get_type_size(type) / 4;
272 info->sgpr_count++;
273 }
274
275 static inline void
276 add_user_sgpr_argument(struct arg_info *info,
277 LLVMTypeRef type,
278 LLVMValueRef *param_ptr)
279 {
280 add_sgpr_argument(info, type, param_ptr);
281 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
282 info->user_sgpr_count++;
283 }
284
285 static inline void
286 add_vgpr_argument(struct arg_info *info,
287 LLVMTypeRef type,
288 LLVMValueRef *param_ptr)
289 {
290 add_argument(info, type, param_ptr);
291 info->num_vgprs_used += ac_get_type_size(type) / 4;
292 }
293
294 static inline void
295 add_user_sgpr_array_argument(struct arg_info *info,
296 LLVMTypeRef type,
297 LLVMValueRef *param_ptr)
298 {
299 info->array_params_mask |= (1 << info->count);
300 add_user_sgpr_argument(info, type, param_ptr);
301 }
302
303 static void assign_arguments(LLVMValueRef main_function,
304 struct arg_info *info)
305 {
306 unsigned i;
307 for (i = 0; i < info->count; i++) {
308 if (info->assign[i])
309 *info->assign[i] = LLVMGetParam(main_function, i);
310 }
311 }
312
313 static LLVMValueRef
314 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
315 LLVMBuilderRef builder, LLVMTypeRef *return_types,
316 unsigned num_return_elems,
317 struct arg_info *args,
318 unsigned max_workgroup_size,
319 bool unsafe_math)
320 {
321 LLVMTypeRef main_function_type, ret_type;
322 LLVMBasicBlockRef main_function_body;
323
324 if (num_return_elems)
325 ret_type = LLVMStructTypeInContext(ctx, return_types,
326 num_return_elems, true);
327 else
328 ret_type = LLVMVoidTypeInContext(ctx);
329
330 /* Setup the function */
331 main_function_type =
332 LLVMFunctionType(ret_type, args->types, args->count, 0);
333 LLVMValueRef main_function =
334 LLVMAddFunction(module, "main", main_function_type);
335 main_function_body =
336 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
337 LLVMPositionBuilderAtEnd(builder, main_function_body);
338
339 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
340 for (unsigned i = 0; i < args->sgpr_count; ++i) {
341 if (args->array_params_mask & (1 << i)) {
342 LLVMValueRef P = LLVMGetParam(main_function, i);
343 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
344 ac_add_attr_dereferenceable(P, UINT64_MAX);
345 }
346 else {
347 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
348 }
349 }
350
351 if (max_workgroup_size) {
352 ac_llvm_add_target_dep_function_attr(main_function,
353 "amdgpu-max-work-group-size",
354 max_workgroup_size);
355 }
356 if (unsafe_math) {
357 /* These were copied from some LLVM test. */
358 LLVMAddTargetDependentFunctionAttr(main_function,
359 "less-precise-fpmad",
360 "true");
361 LLVMAddTargetDependentFunctionAttr(main_function,
362 "no-infs-fp-math",
363 "true");
364 LLVMAddTargetDependentFunctionAttr(main_function,
365 "no-nans-fp-math",
366 "true");
367 LLVMAddTargetDependentFunctionAttr(main_function,
368 "unsafe-fp-math",
369 "true");
370 }
371 return main_function;
372 }
373
374 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
375 {
376 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
377 CONST_ADDR_SPACE);
378 }
379
380 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
381 {
382 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
383 type = LLVMGetElementType(type);
384
385 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
386 return LLVMGetIntTypeWidth(type);
387
388 if (type == ctx->f16)
389 return 16;
390 if (type == ctx->f32)
391 return 32;
392 if (type == ctx->f64)
393 return 64;
394
395 unreachable("Unhandled type kind in get_elem_bits");
396 }
397
398 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
399 LLVMValueRef param, unsigned rshift,
400 unsigned bitwidth)
401 {
402 LLVMValueRef value = param;
403 if (rshift)
404 value = LLVMBuildLShr(ctx->builder, value,
405 LLVMConstInt(ctx->i32, rshift, false), "");
406
407 if (rshift + bitwidth < 32) {
408 unsigned mask = (1 << bitwidth) - 1;
409 value = LLVMBuildAnd(ctx->builder, value,
410 LLVMConstInt(ctx->i32, mask, false), "");
411 }
412 return value;
413 }
414
415 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
416 {
417 switch (ctx->stage) {
418 case MESA_SHADER_TESS_CTRL:
419 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
420 case MESA_SHADER_TESS_EVAL:
421 return ctx->tes_rel_patch_id;
422 break;
423 default:
424 unreachable("Illegal stage");
425 }
426 }
427
428 /* Tessellation shaders pass outputs to the next shader using LDS.
429 *
430 * LS outputs = TCS inputs
431 * TCS outputs = TES inputs
432 *
433 * The LDS layout is:
434 * - TCS inputs for patch 0
435 * - TCS inputs for patch 1
436 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
437 * - ...
438 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
439 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
440 * - TCS outputs for patch 1
441 * - Per-patch TCS outputs for patch 1
442 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
443 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
444 * - ...
445 *
446 * All three shaders VS(LS), TCS, TES share the same LDS space.
447 */
448 static LLVMValueRef
449 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
450 {
451 if (ctx->stage == MESA_SHADER_VERTEX)
452 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
453 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
454 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
455 else {
456 assert(0);
457 return NULL;
458 }
459 }
460
461 static LLVMValueRef
462 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
463 {
464 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
465 }
466
467 static LLVMValueRef
468 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
469 {
470 return LLVMBuildMul(ctx->builder,
471 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
472 LLVMConstInt(ctx->i32, 4, false), "");
473 }
474
475 static LLVMValueRef
476 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
477 {
478 return LLVMBuildMul(ctx->builder,
479 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
480 LLVMConstInt(ctx->i32, 4, false), "");
481 }
482
483 static LLVMValueRef
484 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
485 {
486 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
487 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
488
489 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
490 }
491
492 static LLVMValueRef
493 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
494 {
495 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
496 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
497 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
498
499 return LLVMBuildAdd(ctx->builder, patch0_offset,
500 LLVMBuildMul(ctx->builder, patch_stride,
501 rel_patch_id, ""),
502 "");
503 }
504
505 static LLVMValueRef
506 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
507 {
508 LLVMValueRef patch0_patch_data_offset =
509 get_tcs_out_patch0_patch_data_offset(ctx);
510 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
511 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
512
513 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
514 LLVMBuildMul(ctx->builder, patch_stride,
515 rel_patch_id, ""),
516 "");
517 }
518
519 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
520 {
521 ud_info->sgpr_idx = *sgpr_idx;
522 ud_info->num_sgprs = num_sgprs;
523 ud_info->indirect = false;
524 ud_info->indirect_offset = 0;
525 *sgpr_idx += num_sgprs;
526 }
527
528 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
529 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
530 {
531 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
532 }
533
534
535 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
536 uint32_t indirect_offset)
537 {
538 ud_info->sgpr_idx = sgpr_idx;
539 ud_info->num_sgprs = num_sgprs;
540 ud_info->indirect = true;
541 ud_info->indirect_offset = indirect_offset;
542 }
543
544 struct user_sgpr_info {
545 bool need_ring_offsets;
546 uint8_t sgpr_count;
547 bool indirect_all_descriptor_sets;
548 };
549
550 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
551 struct user_sgpr_info *user_sgpr_info)
552 {
553 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
554
555 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
556 if (ctx->stage == MESA_SHADER_GEOMETRY ||
557 ctx->stage == MESA_SHADER_VERTEX ||
558 ctx->stage == MESA_SHADER_TESS_CTRL ||
559 ctx->stage == MESA_SHADER_TESS_EVAL ||
560 ctx->is_gs_copy_shader)
561 user_sgpr_info->need_ring_offsets = true;
562
563 if (ctx->stage == MESA_SHADER_FRAGMENT &&
564 ctx->shader_info->info.ps.needs_sample_positions)
565 user_sgpr_info->need_ring_offsets = true;
566
567 /* 2 user sgprs will nearly always be allocated for scratch/rings */
568 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
569 user_sgpr_info->sgpr_count += 2;
570 }
571
572 switch (ctx->stage) {
573 case MESA_SHADER_COMPUTE:
574 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
575 break;
576 case MESA_SHADER_FRAGMENT:
577 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
578 break;
579 case MESA_SHADER_VERTEX:
580 if (!ctx->is_gs_copy_shader) {
581 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
582 if (ctx->shader_info->info.vs.needs_draw_id) {
583 user_sgpr_info->sgpr_count += 3;
584 } else {
585 user_sgpr_info->sgpr_count += 2;
586 }
587 }
588 if (ctx->options->key.vs.as_ls)
589 user_sgpr_info->sgpr_count++;
590 break;
591 case MESA_SHADER_TESS_CTRL:
592 user_sgpr_info->sgpr_count += 4;
593 break;
594 case MESA_SHADER_TESS_EVAL:
595 user_sgpr_info->sgpr_count += 1;
596 break;
597 case MESA_SHADER_GEOMETRY:
598 user_sgpr_info->sgpr_count += 2;
599 break;
600 default:
601 break;
602 }
603
604 if (ctx->shader_info->info.needs_push_constants)
605 user_sgpr_info->sgpr_count += 2;
606
607 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
608 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
609 user_sgpr_info->sgpr_count += 2;
610 user_sgpr_info->indirect_all_descriptor_sets = true;
611 } else {
612 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
613 }
614 }
615
616 static void
617 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
618 gl_shader_stage stage,
619 bool has_previous_stage,
620 gl_shader_stage previous_stage,
621 const struct user_sgpr_info *user_sgpr_info,
622 struct arg_info *args,
623 LLVMValueRef *desc_sets)
624 {
625 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
626 unsigned stage_mask = 1 << stage;
627 if (has_previous_stage)
628 stage_mask |= 1 << previous_stage;
629
630 /* 1 for each descriptor set */
631 if (!user_sgpr_info->indirect_all_descriptor_sets) {
632 for (unsigned i = 0; i < num_sets; ++i) {
633 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
634 add_user_sgpr_array_argument(args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
635 }
636 }
637 } else
638 add_user_sgpr_array_argument(args, const_array(const_array(ctx->i8, 1024 * 1024), 32), desc_sets);
639
640 if (ctx->shader_info->info.needs_push_constants) {
641 /* 1 for push constants and dynamic descriptors */
642 add_user_sgpr_array_argument(args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
643 }
644 }
645
646 static void
647 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
648 gl_shader_stage stage,
649 bool has_previous_stage,
650 gl_shader_stage previous_stage,
651 const struct user_sgpr_info *user_sgpr_info,
652 LLVMValueRef desc_sets,
653 uint8_t *user_sgpr_idx)
654 {
655 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
656 unsigned stage_mask = 1 << stage;
657 if (has_previous_stage)
658 stage_mask |= 1 << previous_stage;
659
660 if (!user_sgpr_info->indirect_all_descriptor_sets) {
661 for (unsigned i = 0; i < num_sets; ++i) {
662 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
663 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
664 } else
665 ctx->descriptor_sets[i] = NULL;
666 }
667 } else {
668 uint32_t desc_sgpr_idx = *user_sgpr_idx;
669 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
670
671 for (unsigned i = 0; i < num_sets; ++i) {
672 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
673 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
674 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
675
676 } else
677 ctx->descriptor_sets[i] = NULL;
678 }
679 ctx->shader_info->need_indirect_descriptor_sets = true;
680 }
681
682 if (ctx->shader_info->info.needs_push_constants) {
683 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
684 }
685 }
686
687 static void
688 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
689 gl_shader_stage stage,
690 bool has_previous_stage,
691 gl_shader_stage previous_stage,
692 struct arg_info *args)
693 {
694 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
695 if (ctx->shader_info->info.vs.has_vertex_buffers)
696 add_user_sgpr_argument(args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
697 add_user_sgpr_argument(args, ctx->i32, &ctx->abi.base_vertex); // base vertex
698 add_user_sgpr_argument(args, ctx->i32, &ctx->abi.start_instance);// start instance
699 if (ctx->shader_info->info.vs.needs_draw_id)
700 add_user_sgpr_argument(args, ctx->i32, &ctx->abi.draw_id); // draw id
701 }
702 }
703
704 static void
705 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
706 gl_shader_stage stage,
707 bool has_previous_stage,
708 gl_shader_stage previous_stage,
709 uint8_t *user_sgpr_idx)
710 {
711 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
712 if (ctx->shader_info->info.vs.has_vertex_buffers) {
713 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
714 }
715 unsigned vs_num = 2;
716 if (ctx->shader_info->info.vs.needs_draw_id)
717 vs_num++;
718
719 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
720 }
721 }
722
723
724 static void create_function(struct nir_to_llvm_context *ctx,
725 gl_shader_stage stage,
726 bool has_previous_stage,
727 gl_shader_stage previous_stage)
728 {
729 uint8_t user_sgpr_idx;
730 struct user_sgpr_info user_sgpr_info;
731 struct arg_info args = {};
732 LLVMValueRef desc_sets;
733
734 allocate_user_sgprs(ctx, &user_sgpr_info);
735
736 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
737 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
738 }
739
740 switch (stage) {
741 case MESA_SHADER_COMPUTE:
742 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
743 if (ctx->shader_info->info.cs.grid_components_used)
744 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
745 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
746 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
747 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
748 break;
749 case MESA_SHADER_VERTEX:
750 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
751 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
752 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
753 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
754 if (ctx->options->key.vs.as_es)
755 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
756 else if (ctx->options->key.vs.as_ls)
757 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
758 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
759 if (!ctx->is_gs_copy_shader) {
760 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
761 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
762 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
763 }
764 break;
765 case MESA_SHADER_TESS_CTRL:
766 if (has_previous_stage) {
767 // First 6 system regs
768 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
769 add_sgpr_argument(&args, ctx->i32, &ctx->merged_wave_info); // merged wave info
770 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
771
772 add_sgpr_argument(&args, ctx->i32, NULL); // scratch offset
773 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
774 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
775
776 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
777 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
778 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
779
780 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
781 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
782 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
783 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
784 if (ctx->shader_info->info.needs_multiview_view_index)
785 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
786
787 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
788 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
789 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
790 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
791 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
792 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
793 } else {
794 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
795 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
796 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
797 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
798 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
799 if (ctx->shader_info->info.needs_multiview_view_index)
800 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
801 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
802 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
803 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
804 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
805 }
806 break;
807 case MESA_SHADER_TESS_EVAL:
808 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
809 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
810 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
811 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
812 if (ctx->options->key.tes.as_es) {
813 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
814 add_sgpr_argument(&args, ctx->i32, NULL); //
815 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
816 } else {
817 add_sgpr_argument(&args, ctx->i32, NULL); //
818 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
819 }
820 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
821 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
822 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
823 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
824 break;
825 case MESA_SHADER_GEOMETRY:
826 if (has_previous_stage) {
827 // First 6 system regs
828 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // tess factor offset
829 add_sgpr_argument(&args, ctx->i32, &ctx->merged_wave_info); // merged wave info
830 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
831
832 add_sgpr_argument(&args, ctx->i32, NULL); // scratch offset
833 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
834 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
835
836 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
837 if (previous_stage == MESA_SHADER_TESS_EVAL)
838 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
839 else
840 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
841 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
842 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
843 if (ctx->shader_info->info.needs_multiview_view_index)
844 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
845
846 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx01
847 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]); // vtx23
848 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
849 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
850 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
851
852 if (previous_stage == MESA_SHADER_VERTEX) {
853 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
854 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
855 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
856 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
857 } else {
858 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
859 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
860 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
861 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
862 }
863 } else {
864 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
865 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
866 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
867 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
868 if (ctx->shader_info->info.needs_multiview_view_index)
869 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
870 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
871 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
872 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
873 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
874 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
875 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
876 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
877 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
878 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
879 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
880 }
881 break;
882 case MESA_SHADER_FRAGMENT:
883 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
884 if (ctx->shader_info->info.ps.needs_sample_positions)
885 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
886 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
887 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
888 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
889 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
890 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
891 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
892 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
893 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
894 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
895 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */
896 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */
897 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */
898 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */
899 add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /* front face */
900 add_vgpr_argument(&args, ctx->i32, &ctx->abi.ancillary); /* ancillary */
901 add_vgpr_argument(&args, ctx->i32, &ctx->abi.sample_coverage); /* sample coverage */
902 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
903 break;
904 default:
905 unreachable("Shader stage not implemented");
906 }
907
908 ctx->main_function = create_llvm_function(
909 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
910 ctx->max_workgroup_size,
911 ctx->options->unsafe_math);
912 set_llvm_calling_convention(ctx->main_function, stage);
913
914
915 ctx->shader_info->num_input_vgprs = 0;
916 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
917
918 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
919
920 if (ctx->stage != MESA_SHADER_FRAGMENT)
921 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
922
923 assign_arguments(ctx->main_function, &args);
924
925 user_sgpr_idx = 0;
926
927 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
928 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
929 if (ctx->options->supports_spill) {
930 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
931 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
932 NULL, 0, AC_FUNC_ATTR_READNONE);
933 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
934 const_array(ctx->v4i32, 16), "");
935 }
936 }
937
938 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
939 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
940 if (has_previous_stage)
941 user_sgpr_idx = 0;
942
943 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
944
945 switch (stage) {
946 case MESA_SHADER_COMPUTE:
947 if (ctx->shader_info->info.cs.grid_components_used) {
948 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
949 }
950 break;
951 case MESA_SHADER_VERTEX:
952 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
953 if (ctx->view_index)
954 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
955 if (ctx->options->key.vs.as_ls) {
956 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
957 }
958 if (ctx->options->key.vs.as_ls)
959 ac_declare_lds_as_pointer(&ctx->ac);
960 break;
961 case MESA_SHADER_TESS_CTRL:
962 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
963 if (has_previous_stage)
964 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
965 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
966 if (ctx->view_index)
967 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
968 ac_declare_lds_as_pointer(&ctx->ac);
969 break;
970 case MESA_SHADER_TESS_EVAL:
971 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
972 if (ctx->view_index)
973 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
974 break;
975 case MESA_SHADER_GEOMETRY:
976 if (has_previous_stage) {
977 if (previous_stage == MESA_SHADER_VERTEX)
978 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
979 else
980 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
981 }
982 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
983 if (ctx->view_index)
984 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
985 if (has_previous_stage)
986 ac_declare_lds_as_pointer(&ctx->ac);
987 break;
988 case MESA_SHADER_FRAGMENT:
989 if (ctx->shader_info->info.ps.needs_sample_positions) {
990 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
991 }
992 break;
993 default:
994 unreachable("Shader stage not implemented");
995 }
996
997 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
998 }
999
1000 static void setup_types(struct nir_to_llvm_context *ctx)
1001 {
1002 LLVMValueRef args[4];
1003
1004 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
1005 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
1006 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
1007 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
1008 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
1009 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
1010 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
1011 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
1012 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
1013 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
1014 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
1015 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
1016 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
1017 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
1018 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
1019
1020 args[0] = ctx->ac.f32_0;
1021 args[1] = ctx->ac.f32_0;
1022 args[2] = ctx->ac.f32_0;
1023 args[3] = ctx->ac.f32_1;
1024 ctx->v4f32empty = LLVMConstVector(args, 4);
1025
1026 ctx->uniform_md_kind =
1027 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
1028 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
1029
1030 args[0] = LLVMConstReal(ctx->f32, 2.5);
1031 }
1032
1033 static int get_llvm_num_components(LLVMValueRef value)
1034 {
1035 LLVMTypeRef type = LLVMTypeOf(value);
1036 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1037 ? LLVMGetVectorSize(type)
1038 : 1;
1039 return num_components;
1040 }
1041
1042 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1043 LLVMValueRef value,
1044 int index)
1045 {
1046 int count = get_llvm_num_components(value);
1047
1048 if (count == 1)
1049 return value;
1050
1051 return LLVMBuildExtractElement(ac->builder, value,
1052 LLVMConstInt(ac->i32, index, false), "");
1053 }
1054
1055 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1056 LLVMValueRef value, unsigned count)
1057 {
1058 unsigned num_components = get_llvm_num_components(value);
1059 if (count == num_components)
1060 return value;
1061
1062 LLVMValueRef masks[] = {
1063 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1064 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1065
1066 if (count == 1)
1067 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1068 "");
1069
1070 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1071 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1072 }
1073
1074 static void
1075 build_store_values_extended(struct ac_llvm_context *ac,
1076 LLVMValueRef *values,
1077 unsigned value_count,
1078 unsigned value_stride,
1079 LLVMValueRef vec)
1080 {
1081 LLVMBuilderRef builder = ac->builder;
1082 unsigned i;
1083
1084 for (i = 0; i < value_count; i++) {
1085 LLVMValueRef ptr = values[i * value_stride];
1086 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1087 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1088 LLVMBuildStore(builder, value, ptr);
1089 }
1090 }
1091
1092 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1093 const nir_ssa_def *def)
1094 {
1095 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1096 if (def->num_components > 1) {
1097 type = LLVMVectorType(type, def->num_components);
1098 }
1099 return type;
1100 }
1101
1102 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1103 {
1104 assert(src.is_ssa);
1105 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1106 return (LLVMValueRef)entry->data;
1107 }
1108
1109
1110 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1111 const struct nir_block *b)
1112 {
1113 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1114 return (LLVMBasicBlockRef)entry->data;
1115 }
1116
1117 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1118 nir_alu_src src,
1119 unsigned num_components)
1120 {
1121 LLVMValueRef value = get_src(ctx, src.src);
1122 bool need_swizzle = false;
1123
1124 assert(value);
1125 LLVMTypeRef type = LLVMTypeOf(value);
1126 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1127 ? LLVMGetVectorSize(type)
1128 : 1;
1129
1130 for (unsigned i = 0; i < num_components; ++i) {
1131 assert(src.swizzle[i] < src_components);
1132 if (src.swizzle[i] != i)
1133 need_swizzle = true;
1134 }
1135
1136 if (need_swizzle || num_components != src_components) {
1137 LLVMValueRef masks[] = {
1138 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1139 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1140 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1141 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1142
1143 if (src_components > 1 && num_components == 1) {
1144 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1145 masks[0], "");
1146 } else if (src_components == 1 && num_components > 1) {
1147 LLVMValueRef values[] = {value, value, value, value};
1148 value = ac_build_gather_values(&ctx->ac, values, num_components);
1149 } else {
1150 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1151 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1152 swizzle, "");
1153 }
1154 }
1155 assert(!src.negate);
1156 assert(!src.abs);
1157 return value;
1158 }
1159
1160 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1161 LLVMIntPredicate pred, LLVMValueRef src0,
1162 LLVMValueRef src1)
1163 {
1164 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1165 return LLVMBuildSelect(ctx->builder, result,
1166 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1167 LLVMConstInt(ctx->i32, 0, false), "");
1168 }
1169
1170 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1171 LLVMRealPredicate pred, LLVMValueRef src0,
1172 LLVMValueRef src1)
1173 {
1174 LLVMValueRef result;
1175 src0 = ac_to_float(ctx, src0);
1176 src1 = ac_to_float(ctx, src1);
1177 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1178 return LLVMBuildSelect(ctx->builder, result,
1179 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1180 LLVMConstInt(ctx->i32, 0, false), "");
1181 }
1182
1183 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1184 const char *intrin,
1185 LLVMTypeRef result_type,
1186 LLVMValueRef src0)
1187 {
1188 char name[64];
1189 LLVMValueRef params[] = {
1190 ac_to_float(ctx, src0),
1191 };
1192
1193 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1194 get_elem_bits(ctx, result_type));
1195 assert(length < sizeof(name));
1196 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1197 }
1198
1199 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1200 const char *intrin,
1201 LLVMTypeRef result_type,
1202 LLVMValueRef src0, LLVMValueRef src1)
1203 {
1204 char name[64];
1205 LLVMValueRef params[] = {
1206 ac_to_float(ctx, src0),
1207 ac_to_float(ctx, src1),
1208 };
1209
1210 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1211 get_elem_bits(ctx, result_type));
1212 assert(length < sizeof(name));
1213 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1214 }
1215
1216 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1217 const char *intrin,
1218 LLVMTypeRef result_type,
1219 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1220 {
1221 char name[64];
1222 LLVMValueRef params[] = {
1223 ac_to_float(ctx, src0),
1224 ac_to_float(ctx, src1),
1225 ac_to_float(ctx, src2),
1226 };
1227
1228 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1229 get_elem_bits(ctx, result_type));
1230 assert(length < sizeof(name));
1231 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1232 }
1233
1234 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1235 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1236 {
1237 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1238 ctx->i32_0, "");
1239 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1240 }
1241
1242 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1243 LLVMValueRef src0)
1244 {
1245 LLVMValueRef params[2] = {
1246 src0,
1247
1248 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1249 * add special code to check for x=0. The reason is that
1250 * the LLVM behavior for x=0 is different from what we
1251 * need here.
1252 *
1253 * The hardware already implements the correct behavior.
1254 */
1255 LLVMConstInt(ctx->i1, 1, false),
1256 };
1257
1258 LLVMValueRef lsb = ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32,
1259 params, 2,
1260 AC_FUNC_ATTR_READNONE);
1261
1262 /* TODO: We need an intrinsic to skip this conditional. */
1263 /* Check for zero: */
1264 return LLVMBuildSelect(ctx->builder, LLVMBuildICmp(ctx->builder,
1265 LLVMIntEQ, src0,
1266 ctx->i32_0, ""),
1267 LLVMConstInt(ctx->i32, -1, 0), lsb, "");
1268 }
1269
1270 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1271 LLVMValueRef src0)
1272 {
1273 return ac_build_imsb(ctx, src0, ctx->i32);
1274 }
1275
1276 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1277 LLVMValueRef src0)
1278 {
1279 return ac_build_umsb(ctx, src0, ctx->i32);
1280 }
1281
1282 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1283 LLVMIntPredicate pred,
1284 LLVMValueRef src0, LLVMValueRef src1)
1285 {
1286 return LLVMBuildSelect(ctx->builder,
1287 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1288 src0,
1289 src1, "");
1290
1291 }
1292 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1293 LLVMValueRef src0)
1294 {
1295 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1296 LLVMBuildNeg(ctx->builder, src0, ""));
1297 }
1298
1299 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1300 LLVMValueRef src0)
1301 {
1302 LLVMValueRef cmp, val;
1303
1304 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1305 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1306 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1307 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1308 return val;
1309 }
1310
1311 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1312 LLVMValueRef src0)
1313 {
1314 LLVMValueRef cmp, val;
1315
1316 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1317 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1318 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1319 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1320 return val;
1321 }
1322
1323 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1324 LLVMValueRef src0)
1325 {
1326 const char *intr = "llvm.floor.f32";
1327 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1328 LLVMValueRef params[] = {
1329 fsrc0,
1330 };
1331 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1332 ctx->f32, params, 1,
1333 AC_FUNC_ATTR_READNONE);
1334 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1335 }
1336
1337 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1338 const char *intrin,
1339 LLVMValueRef src0, LLVMValueRef src1)
1340 {
1341 LLVMTypeRef ret_type;
1342 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1343 LLVMValueRef res;
1344 LLVMValueRef params[] = { src0, src1 };
1345 ret_type = LLVMStructTypeInContext(ctx->context, types,
1346 2, true);
1347
1348 res = ac_build_intrinsic(ctx, intrin, ret_type,
1349 params, 2, AC_FUNC_ATTR_READNONE);
1350
1351 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1352 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1353 return res;
1354 }
1355
1356 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0)
1358 {
1359 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1360 }
1361
1362 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1363 LLVMValueRef src0)
1364 {
1365 src0 = ac_to_float(ctx, src0);
1366 return LLVMBuildSExt(ctx->builder,
1367 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1368 ctx->i32, "");
1369 }
1370
1371 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1372 LLVMValueRef src0)
1373 {
1374 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1375 }
1376
1377 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1378 LLVMValueRef src0)
1379 {
1380 return LLVMBuildSExt(ctx->builder,
1381 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1382 ctx->i32, "");
1383 }
1384
1385 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1386 LLVMValueRef src0)
1387 {
1388 LLVMValueRef result;
1389 LLVMValueRef cond = NULL;
1390
1391 src0 = ac_to_float(&ctx->ac, src0);
1392 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1393
1394 if (ctx->options->chip_class >= VI) {
1395 LLVMValueRef args[2];
1396 /* Check if the result is a denormal - and flush to 0 if so. */
1397 args[0] = result;
1398 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1399 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1400 }
1401
1402 /* need to convert back up to f32 */
1403 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1404
1405 if (ctx->options->chip_class >= VI)
1406 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1407 else {
1408 /* for SI/CIK */
1409 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1410 * so compare the result and flush to 0 if it's smaller.
1411 */
1412 LLVMValueRef temp, cond2;
1413 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1414 ctx->f32, result);
1415 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1416 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1417 temp, "");
1418 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1419 temp, ctx->ac.f32_0, "");
1420 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1421 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1422 }
1423 return result;
1424 }
1425
1426 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1427 LLVMValueRef src0, LLVMValueRef src1)
1428 {
1429 LLVMValueRef dst64, result;
1430 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1431 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1432
1433 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1434 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1435 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1436 return result;
1437 }
1438
1439 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1440 LLVMValueRef src0, LLVMValueRef src1)
1441 {
1442 LLVMValueRef dst64, result;
1443 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1444 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1445
1446 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1447 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1448 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1449 return result;
1450 }
1451
1452 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1453 bool is_signed,
1454 const LLVMValueRef srcs[3])
1455 {
1456 LLVMValueRef result;
1457 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1458
1459 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1460 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1461 return result;
1462 }
1463
1464 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1465 LLVMValueRef src0, LLVMValueRef src1,
1466 LLVMValueRef src2, LLVMValueRef src3)
1467 {
1468 LLVMValueRef bfi_args[3], result;
1469
1470 bfi_args[0] = LLVMBuildShl(ctx->builder,
1471 LLVMBuildSub(ctx->builder,
1472 LLVMBuildShl(ctx->builder,
1473 ctx->i32_1,
1474 src3, ""),
1475 ctx->i32_1, ""),
1476 src2, "");
1477 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1478 bfi_args[2] = src0;
1479
1480 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1481
1482 /* Calculate:
1483 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1484 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1485 */
1486 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1487 LLVMBuildAnd(ctx->builder, bfi_args[0],
1488 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1489
1490 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1491 return result;
1492 }
1493
1494 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1495 LLVMValueRef src0)
1496 {
1497 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1498 int i;
1499 LLVMValueRef comp[2];
1500
1501 src0 = ac_to_float(ctx, src0);
1502 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1503 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1504 for (i = 0; i < 2; i++) {
1505 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1506 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1507 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1508 }
1509
1510 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1511 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1512
1513 return comp[0];
1514 }
1515
1516 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1517 LLVMValueRef src0)
1518 {
1519 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1520 LLVMValueRef temps[2], result, val;
1521 int i;
1522
1523 for (i = 0; i < 2; i++) {
1524 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1525 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1526 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1527 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1528 }
1529
1530 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1531 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1532 ctx->i32_0, "");
1533 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1534 ctx->i32_1, "");
1535 return result;
1536 }
1537
1538 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1539 nir_op op,
1540 LLVMValueRef src0)
1541 {
1542 unsigned mask;
1543 int idx;
1544 LLVMValueRef result;
1545
1546 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1547 mask = AC_TID_MASK_LEFT;
1548 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1549 mask = AC_TID_MASK_TOP;
1550 else
1551 mask = AC_TID_MASK_TOP_LEFT;
1552
1553 /* for DDX we want to next X pixel, DDY next Y pixel. */
1554 if (op == nir_op_fddx_fine ||
1555 op == nir_op_fddx_coarse ||
1556 op == nir_op_fddx)
1557 idx = 1;
1558 else
1559 idx = 2;
1560
1561 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1562 return result;
1563 }
1564
1565 /*
1566 * this takes an I,J coordinate pair,
1567 * and works out the X and Y derivatives.
1568 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1569 */
1570 static LLVMValueRef emit_ddxy_interp(
1571 struct ac_nir_context *ctx,
1572 LLVMValueRef interp_ij)
1573 {
1574 LLVMValueRef result[4], a;
1575 unsigned i;
1576
1577 for (i = 0; i < 2; i++) {
1578 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1579 LLVMConstInt(ctx->ac.i32, i, false), "");
1580 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1581 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1582 }
1583 return ac_build_gather_values(&ctx->ac, result, 4);
1584 }
1585
1586 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1587 {
1588 LLVMValueRef src[4], result = NULL;
1589 unsigned num_components = instr->dest.dest.ssa.num_components;
1590 unsigned src_components;
1591 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1592
1593 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1594 switch (instr->op) {
1595 case nir_op_vec2:
1596 case nir_op_vec3:
1597 case nir_op_vec4:
1598 src_components = 1;
1599 break;
1600 case nir_op_pack_half_2x16:
1601 src_components = 2;
1602 break;
1603 case nir_op_unpack_half_2x16:
1604 src_components = 1;
1605 break;
1606 default:
1607 src_components = num_components;
1608 break;
1609 }
1610 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1611 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1612
1613 switch (instr->op) {
1614 case nir_op_fmov:
1615 case nir_op_imov:
1616 result = src[0];
1617 break;
1618 case nir_op_fneg:
1619 src[0] = ac_to_float(&ctx->ac, src[0]);
1620 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1621 break;
1622 case nir_op_ineg:
1623 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1624 break;
1625 case nir_op_inot:
1626 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1627 break;
1628 case nir_op_iadd:
1629 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1630 break;
1631 case nir_op_fadd:
1632 src[0] = ac_to_float(&ctx->ac, src[0]);
1633 src[1] = ac_to_float(&ctx->ac, src[1]);
1634 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1635 break;
1636 case nir_op_fsub:
1637 src[0] = ac_to_float(&ctx->ac, src[0]);
1638 src[1] = ac_to_float(&ctx->ac, src[1]);
1639 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1640 break;
1641 case nir_op_isub:
1642 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1643 break;
1644 case nir_op_imul:
1645 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1646 break;
1647 case nir_op_imod:
1648 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1649 break;
1650 case nir_op_umod:
1651 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1652 break;
1653 case nir_op_fmod:
1654 src[0] = ac_to_float(&ctx->ac, src[0]);
1655 src[1] = ac_to_float(&ctx->ac, src[1]);
1656 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1657 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1658 ac_to_float_type(&ctx->ac, def_type), result);
1659 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1660 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1661 break;
1662 case nir_op_frem:
1663 src[0] = ac_to_float(&ctx->ac, src[0]);
1664 src[1] = ac_to_float(&ctx->ac, src[1]);
1665 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1666 break;
1667 case nir_op_irem:
1668 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1669 break;
1670 case nir_op_idiv:
1671 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1672 break;
1673 case nir_op_udiv:
1674 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1675 break;
1676 case nir_op_fmul:
1677 src[0] = ac_to_float(&ctx->ac, src[0]);
1678 src[1] = ac_to_float(&ctx->ac, src[1]);
1679 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1680 break;
1681 case nir_op_fdiv:
1682 src[0] = ac_to_float(&ctx->ac, src[0]);
1683 src[1] = ac_to_float(&ctx->ac, src[1]);
1684 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1685 break;
1686 case nir_op_frcp:
1687 src[0] = ac_to_float(&ctx->ac, src[0]);
1688 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1689 break;
1690 case nir_op_iand:
1691 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1692 break;
1693 case nir_op_ior:
1694 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_ixor:
1697 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1698 break;
1699 case nir_op_ishl:
1700 result = LLVMBuildShl(ctx->ac.builder, src[0],
1701 LLVMBuildZExt(ctx->ac.builder, src[1],
1702 LLVMTypeOf(src[0]), ""),
1703 "");
1704 break;
1705 case nir_op_ishr:
1706 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1707 LLVMBuildZExt(ctx->ac.builder, src[1],
1708 LLVMTypeOf(src[0]), ""),
1709 "");
1710 break;
1711 case nir_op_ushr:
1712 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1713 LLVMBuildZExt(ctx->ac.builder, src[1],
1714 LLVMTypeOf(src[0]), ""),
1715 "");
1716 break;
1717 case nir_op_ilt:
1718 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1719 break;
1720 case nir_op_ine:
1721 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1722 break;
1723 case nir_op_ieq:
1724 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1725 break;
1726 case nir_op_ige:
1727 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1728 break;
1729 case nir_op_ult:
1730 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1731 break;
1732 case nir_op_uge:
1733 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1734 break;
1735 case nir_op_feq:
1736 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1737 break;
1738 case nir_op_fne:
1739 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1740 break;
1741 case nir_op_flt:
1742 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1743 break;
1744 case nir_op_fge:
1745 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1746 break;
1747 case nir_op_fabs:
1748 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1749 ac_to_float_type(&ctx->ac, def_type), src[0]);
1750 break;
1751 case nir_op_iabs:
1752 result = emit_iabs(&ctx->ac, src[0]);
1753 break;
1754 case nir_op_imax:
1755 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1756 break;
1757 case nir_op_imin:
1758 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1759 break;
1760 case nir_op_umax:
1761 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1762 break;
1763 case nir_op_umin:
1764 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1765 break;
1766 case nir_op_isign:
1767 result = emit_isign(&ctx->ac, src[0]);
1768 break;
1769 case nir_op_fsign:
1770 src[0] = ac_to_float(&ctx->ac, src[0]);
1771 result = emit_fsign(&ctx->ac, src[0]);
1772 break;
1773 case nir_op_ffloor:
1774 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1775 ac_to_float_type(&ctx->ac, def_type), src[0]);
1776 break;
1777 case nir_op_ftrunc:
1778 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1779 ac_to_float_type(&ctx->ac, def_type), src[0]);
1780 break;
1781 case nir_op_fceil:
1782 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1783 ac_to_float_type(&ctx->ac, def_type), src[0]);
1784 break;
1785 case nir_op_fround_even:
1786 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1787 ac_to_float_type(&ctx->ac, def_type),src[0]);
1788 break;
1789 case nir_op_ffract:
1790 result = emit_ffract(&ctx->ac, src[0]);
1791 break;
1792 case nir_op_fsin:
1793 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1794 ac_to_float_type(&ctx->ac, def_type), src[0]);
1795 break;
1796 case nir_op_fcos:
1797 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1798 ac_to_float_type(&ctx->ac, def_type), src[0]);
1799 break;
1800 case nir_op_fsqrt:
1801 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1802 ac_to_float_type(&ctx->ac, def_type), src[0]);
1803 break;
1804 case nir_op_fexp2:
1805 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1806 ac_to_float_type(&ctx->ac, def_type), src[0]);
1807 break;
1808 case nir_op_flog2:
1809 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1810 ac_to_float_type(&ctx->ac, def_type), src[0]);
1811 break;
1812 case nir_op_frsq:
1813 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1814 ac_to_float_type(&ctx->ac, def_type), src[0]);
1815 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1816 break;
1817 case nir_op_fpow:
1818 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1819 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1820 break;
1821 case nir_op_fmax:
1822 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1823 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1824 if (instr->dest.dest.ssa.bit_size == 32)
1825 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1826 ac_to_float_type(&ctx->ac, def_type),
1827 result);
1828 break;
1829 case nir_op_fmin:
1830 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1831 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1832 if (instr->dest.dest.ssa.bit_size == 32)
1833 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1834 ac_to_float_type(&ctx->ac, def_type),
1835 result);
1836 break;
1837 case nir_op_ffma:
1838 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1839 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1840 break;
1841 case nir_op_ibitfield_extract:
1842 result = emit_bitfield_extract(&ctx->ac, true, src);
1843 break;
1844 case nir_op_ubitfield_extract:
1845 result = emit_bitfield_extract(&ctx->ac, false, src);
1846 break;
1847 case nir_op_bitfield_insert:
1848 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1849 break;
1850 case nir_op_bitfield_reverse:
1851 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1852 break;
1853 case nir_op_bit_count:
1854 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1855 break;
1856 case nir_op_vec2:
1857 case nir_op_vec3:
1858 case nir_op_vec4:
1859 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1860 src[i] = ac_to_integer(&ctx->ac, src[i]);
1861 result = ac_build_gather_values(&ctx->ac, src, num_components);
1862 break;
1863 case nir_op_f2i32:
1864 case nir_op_f2i64:
1865 src[0] = ac_to_float(&ctx->ac, src[0]);
1866 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1867 break;
1868 case nir_op_f2u32:
1869 case nir_op_f2u64:
1870 src[0] = ac_to_float(&ctx->ac, src[0]);
1871 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1872 break;
1873 case nir_op_i2f32:
1874 case nir_op_i2f64:
1875 src[0] = ac_to_integer(&ctx->ac, src[0]);
1876 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1877 break;
1878 case nir_op_u2f32:
1879 case nir_op_u2f64:
1880 src[0] = ac_to_integer(&ctx->ac, src[0]);
1881 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1882 break;
1883 case nir_op_f2f64:
1884 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1885 break;
1886 case nir_op_f2f32:
1887 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1888 break;
1889 case nir_op_u2u32:
1890 case nir_op_u2u64:
1891 src[0] = ac_to_integer(&ctx->ac, src[0]);
1892 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1893 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1894 else
1895 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1896 break;
1897 case nir_op_i2i32:
1898 case nir_op_i2i64:
1899 src[0] = ac_to_integer(&ctx->ac, src[0]);
1900 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1901 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1902 else
1903 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1904 break;
1905 case nir_op_bcsel:
1906 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1907 break;
1908 case nir_op_find_lsb:
1909 src[0] = ac_to_integer(&ctx->ac, src[0]);
1910 result = emit_find_lsb(&ctx->ac, src[0]);
1911 break;
1912 case nir_op_ufind_msb:
1913 src[0] = ac_to_integer(&ctx->ac, src[0]);
1914 result = emit_ufind_msb(&ctx->ac, src[0]);
1915 break;
1916 case nir_op_ifind_msb:
1917 src[0] = ac_to_integer(&ctx->ac, src[0]);
1918 result = emit_ifind_msb(&ctx->ac, src[0]);
1919 break;
1920 case nir_op_uadd_carry:
1921 src[0] = ac_to_integer(&ctx->ac, src[0]);
1922 src[1] = ac_to_integer(&ctx->ac, src[1]);
1923 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1924 break;
1925 case nir_op_usub_borrow:
1926 src[0] = ac_to_integer(&ctx->ac, src[0]);
1927 src[1] = ac_to_integer(&ctx->ac, src[1]);
1928 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1929 break;
1930 case nir_op_b2f:
1931 result = emit_b2f(&ctx->ac, src[0]);
1932 break;
1933 case nir_op_f2b:
1934 result = emit_f2b(&ctx->ac, src[0]);
1935 break;
1936 case nir_op_b2i:
1937 result = emit_b2i(&ctx->ac, src[0]);
1938 break;
1939 case nir_op_i2b:
1940 src[0] = ac_to_integer(&ctx->ac, src[0]);
1941 result = emit_i2b(&ctx->ac, src[0]);
1942 break;
1943 case nir_op_fquantize2f16:
1944 result = emit_f2f16(ctx->nctx, src[0]);
1945 break;
1946 case nir_op_umul_high:
1947 src[0] = ac_to_integer(&ctx->ac, src[0]);
1948 src[1] = ac_to_integer(&ctx->ac, src[1]);
1949 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1950 break;
1951 case nir_op_imul_high:
1952 src[0] = ac_to_integer(&ctx->ac, src[0]);
1953 src[1] = ac_to_integer(&ctx->ac, src[1]);
1954 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1955 break;
1956 case nir_op_pack_half_2x16:
1957 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1958 break;
1959 case nir_op_unpack_half_2x16:
1960 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1961 break;
1962 case nir_op_fddx:
1963 case nir_op_fddy:
1964 case nir_op_fddx_fine:
1965 case nir_op_fddy_fine:
1966 case nir_op_fddx_coarse:
1967 case nir_op_fddy_coarse:
1968 result = emit_ddxy(ctx, instr->op, src[0]);
1969 break;
1970
1971 case nir_op_unpack_64_2x32_split_x: {
1972 assert(instr->src[0].src.ssa->num_components == 1);
1973 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1974 LLVMVectorType(ctx->ac.i32, 2),
1975 "");
1976 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1977 ctx->ac.i32_0, "");
1978 break;
1979 }
1980
1981 case nir_op_unpack_64_2x32_split_y: {
1982 assert(instr->src[0].src.ssa->num_components == 1);
1983 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1984 LLVMVectorType(ctx->ac.i32, 2),
1985 "");
1986 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1987 ctx->ac.i32_1, "");
1988 break;
1989 }
1990
1991 case nir_op_pack_64_2x32_split: {
1992 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1993 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1994 src[0], ctx->ac.i32_0, "");
1995 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1996 src[1], ctx->ac.i32_1, "");
1997 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1998 break;
1999 }
2000
2001 default:
2002 fprintf(stderr, "Unknown NIR alu instr: ");
2003 nir_print_instr(&instr->instr, stderr);
2004 fprintf(stderr, "\n");
2005 abort();
2006 }
2007
2008 if (result) {
2009 assert(instr->dest.dest.is_ssa);
2010 result = ac_to_integer(&ctx->ac, result);
2011 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2012 result);
2013 }
2014 }
2015
2016 static void visit_load_const(struct ac_nir_context *ctx,
2017 const nir_load_const_instr *instr)
2018 {
2019 LLVMValueRef values[4], value = NULL;
2020 LLVMTypeRef element_type =
2021 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2022
2023 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2024 switch (instr->def.bit_size) {
2025 case 32:
2026 values[i] = LLVMConstInt(element_type,
2027 instr->value.u32[i], false);
2028 break;
2029 case 64:
2030 values[i] = LLVMConstInt(element_type,
2031 instr->value.u64[i], false);
2032 break;
2033 default:
2034 fprintf(stderr,
2035 "unsupported nir load_const bit_size: %d\n",
2036 instr->def.bit_size);
2037 abort();
2038 }
2039 }
2040 if (instr->def.num_components > 1) {
2041 value = LLVMConstVector(values, instr->def.num_components);
2042 } else
2043 value = values[0];
2044
2045 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2046 }
2047
2048 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2049 LLVMTypeRef type)
2050 {
2051 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2052 return LLVMBuildBitCast(ctx->builder, ptr,
2053 LLVMPointerType(type, addr_space), "");
2054 }
2055
2056 static LLVMValueRef
2057 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2058 {
2059 LLVMValueRef size =
2060 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2061 LLVMConstInt(ctx->ac.i32, 2, false), "");
2062
2063 /* VI only */
2064 if (ctx->ac.chip_class == VI && in_elements) {
2065 /* On VI, the descriptor contains the size in bytes,
2066 * but TXQ must return the size in elements.
2067 * The stride is always non-zero for resources using TXQ.
2068 */
2069 LLVMValueRef stride =
2070 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2071 LLVMConstInt(ctx->ac.i32, 1, false), "");
2072 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2073 LLVMConstInt(ctx->ac.i32, 16, false), "");
2074 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2075 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2076
2077 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2078 }
2079 return size;
2080 }
2081
2082 /**
2083 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2084 * intrinsic names).
2085 */
2086 static void build_int_type_name(
2087 LLVMTypeRef type,
2088 char *buf, unsigned bufsize)
2089 {
2090 assert(bufsize >= 6);
2091
2092 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2093 snprintf(buf, bufsize, "v%ui32",
2094 LLVMGetVectorSize(type));
2095 else
2096 strcpy(buf, "i32");
2097 }
2098
2099 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2100 struct ac_image_args *args,
2101 const nir_tex_instr *instr)
2102 {
2103 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2104 LLVMValueRef coord = args->addr;
2105 LLVMValueRef half_texel[2];
2106 LLVMValueRef compare_cube_wa = NULL;
2107 LLVMValueRef result;
2108 int c;
2109 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2110
2111 //TODO Rect
2112 {
2113 struct ac_image_args txq_args = { 0 };
2114
2115 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2116 txq_args.opcode = ac_image_get_resinfo;
2117 txq_args.dmask = 0xf;
2118 txq_args.addr = ctx->i32_0;
2119 txq_args.resource = args->resource;
2120 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2121
2122 for (c = 0; c < 2; c++) {
2123 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2124 LLVMConstInt(ctx->i32, c, false), "");
2125 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2126 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2127 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2128 LLVMConstReal(ctx->f32, -0.5), "");
2129 }
2130 }
2131
2132 LLVMValueRef orig_coords = args->addr;
2133
2134 for (c = 0; c < 2; c++) {
2135 LLVMValueRef tmp;
2136 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2137 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2138 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2139 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2140 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2141 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2142 }
2143
2144
2145 /*
2146 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2147 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2148 * workaround by sampling using a scaled type and converting.
2149 * This is taken from amdgpu-pro shaders.
2150 */
2151 /* NOTE this produces some ugly code compared to amdgpu-pro,
2152 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2153 * and then reads them back. -pro generates two selects,
2154 * one s_cmp for the descriptor rewriting
2155 * one v_cmp for the coordinate and result changes.
2156 */
2157 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2158 LLVMValueRef tmp, tmp2;
2159
2160 /* workaround 8/8/8/8 uint/sint cube gather bug */
2161 /* first detect it then change to a scaled read and f2i */
2162 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2163 tmp2 = tmp;
2164
2165 /* extract the DATA_FORMAT */
2166 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2167 LLVMConstInt(ctx->i32, 6, false), false);
2168
2169 /* is the DATA_FORMAT == 8_8_8_8 */
2170 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2171
2172 if (stype == GLSL_TYPE_UINT)
2173 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2174 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2175 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2176 else
2177 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2178 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2179 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2180
2181 /* replace the NUM FORMAT in the descriptor */
2182 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2183 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2184
2185 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2186
2187 /* don't modify the coordinates for this case */
2188 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2189 }
2190 args->addr = coord;
2191 result = ac_build_image_opcode(ctx, args);
2192
2193 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2194 LLVMValueRef tmp, tmp2;
2195
2196 /* if the cube workaround is in place, f2i the result. */
2197 for (c = 0; c < 4; c++) {
2198 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2199 if (stype == GLSL_TYPE_UINT)
2200 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2201 else
2202 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2203 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2204 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2205 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2206 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2207 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2208 }
2209 }
2210 return result;
2211 }
2212
2213 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2214 const nir_tex_instr *instr,
2215 bool lod_is_zero,
2216 struct ac_image_args *args)
2217 {
2218 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2219 return ac_build_buffer_load_format(&ctx->ac,
2220 args->resource,
2221 args->addr,
2222 LLVMConstInt(ctx->ac.i32, 0, false),
2223 true);
2224 }
2225
2226 args->opcode = ac_image_sample;
2227 args->compare = instr->is_shadow;
2228
2229 switch (instr->op) {
2230 case nir_texop_txf:
2231 case nir_texop_txf_ms:
2232 case nir_texop_samples_identical:
2233 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2234 args->compare = false;
2235 args->offset = false;
2236 break;
2237 case nir_texop_txb:
2238 args->bias = true;
2239 break;
2240 case nir_texop_txl:
2241 if (lod_is_zero)
2242 args->level_zero = true;
2243 else
2244 args->lod = true;
2245 break;
2246 case nir_texop_txs:
2247 case nir_texop_query_levels:
2248 args->opcode = ac_image_get_resinfo;
2249 break;
2250 case nir_texop_tex:
2251 if (ctx->stage != MESA_SHADER_FRAGMENT)
2252 args->level_zero = true;
2253 break;
2254 case nir_texop_txd:
2255 args->deriv = true;
2256 break;
2257 case nir_texop_tg4:
2258 args->opcode = ac_image_gather4;
2259 args->level_zero = true;
2260 break;
2261 case nir_texop_lod:
2262 args->opcode = ac_image_get_lod;
2263 args->compare = false;
2264 args->offset = false;
2265 break;
2266 default:
2267 break;
2268 }
2269
2270 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2271 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2272 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2273 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2274 }
2275 }
2276 return ac_build_image_opcode(&ctx->ac, args);
2277 }
2278
2279 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2280 nir_intrinsic_instr *instr)
2281 {
2282 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2283 unsigned desc_set = nir_intrinsic_desc_set(instr);
2284 unsigned binding = nir_intrinsic_binding(instr);
2285 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2286 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2287 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2288 unsigned base_offset = layout->binding[binding].offset;
2289 LLVMValueRef offset, stride;
2290
2291 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2292 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2293 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2294 layout->binding[binding].dynamic_offset_offset;
2295 desc_ptr = ctx->push_constants;
2296 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2297 stride = LLVMConstInt(ctx->i32, 16, false);
2298 } else
2299 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2300
2301 offset = LLVMConstInt(ctx->i32, base_offset, false);
2302 index = LLVMBuildMul(ctx->builder, index, stride, "");
2303 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2304
2305 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2306 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2307 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2308
2309 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2310 }
2311
2312 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2313 nir_intrinsic_instr *instr)
2314 {
2315 LLVMValueRef ptr, addr;
2316
2317 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2318 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2319
2320 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2321 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2322
2323 return LLVMBuildLoad(ctx->builder, ptr, "");
2324 }
2325
2326 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2327 const nir_intrinsic_instr *instr)
2328 {
2329 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2330
2331 return get_buffer_size(ctx, desc, false);
2332 }
2333 static void visit_store_ssbo(struct ac_nir_context *ctx,
2334 nir_intrinsic_instr *instr)
2335 {
2336 const char *store_name;
2337 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2338 LLVMTypeRef data_type = ctx->ac.f32;
2339 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2340 int components_32bit = elem_size_mult * instr->num_components;
2341 unsigned writemask = nir_intrinsic_write_mask(instr);
2342 LLVMValueRef base_data, base_offset;
2343 LLVMValueRef params[6];
2344
2345 params[1] = ctx->abi->load_ssbo(ctx->abi,
2346 get_src(ctx, instr->src[1]), true);
2347 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2348 params[4] = ctx->ac.i1false; /* glc */
2349 params[5] = ctx->ac.i1false; /* slc */
2350
2351 if (components_32bit > 1)
2352 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2353
2354 base_data = ac_to_float(&ctx->ac, src_data);
2355 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2356 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2357 data_type, "");
2358 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2359 while (writemask) {
2360 int start, count;
2361 LLVMValueRef data;
2362 LLVMValueRef offset;
2363 LLVMValueRef tmp;
2364 u_bit_scan_consecutive_range(&writemask, &start, &count);
2365
2366 /* Due to an LLVM limitation, split 3-element writes
2367 * into a 2-element and a 1-element write. */
2368 if (count == 3) {
2369 writemask |= 1 << (start + 2);
2370 count = 2;
2371 }
2372
2373 start *= elem_size_mult;
2374 count *= elem_size_mult;
2375
2376 if (count > 4) {
2377 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2378 count = 4;
2379 }
2380
2381 if (count == 4) {
2382 store_name = "llvm.amdgcn.buffer.store.v4f32";
2383 data = base_data;
2384 } else if (count == 2) {
2385 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2386
2387 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2388 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2389 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2390 ctx->ac.i32_0, "");
2391
2392 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2393 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2394 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2395 ctx->ac.i32_1, "");
2396 store_name = "llvm.amdgcn.buffer.store.v2f32";
2397
2398 } else {
2399 assert(count == 1);
2400 if (get_llvm_num_components(base_data) > 1)
2401 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2402 LLVMConstInt(ctx->ac.i32, start, false), "");
2403 else
2404 data = base_data;
2405 store_name = "llvm.amdgcn.buffer.store.f32";
2406 }
2407
2408 offset = base_offset;
2409 if (start != 0) {
2410 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2411 }
2412 params[0] = data;
2413 params[3] = offset;
2414 ac_build_intrinsic(&ctx->ac, store_name,
2415 ctx->ac.voidt, params, 6, 0);
2416 }
2417 }
2418
2419 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2420 const nir_intrinsic_instr *instr)
2421 {
2422 const char *name;
2423 LLVMValueRef params[6];
2424 int arg_count = 0;
2425
2426 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2427 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2428 }
2429 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2430 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2431 get_src(ctx, instr->src[0]),
2432 true);
2433 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2434 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2435 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2436
2437 switch (instr->intrinsic) {
2438 case nir_intrinsic_ssbo_atomic_add:
2439 name = "llvm.amdgcn.buffer.atomic.add";
2440 break;
2441 case nir_intrinsic_ssbo_atomic_imin:
2442 name = "llvm.amdgcn.buffer.atomic.smin";
2443 break;
2444 case nir_intrinsic_ssbo_atomic_umin:
2445 name = "llvm.amdgcn.buffer.atomic.umin";
2446 break;
2447 case nir_intrinsic_ssbo_atomic_imax:
2448 name = "llvm.amdgcn.buffer.atomic.smax";
2449 break;
2450 case nir_intrinsic_ssbo_atomic_umax:
2451 name = "llvm.amdgcn.buffer.atomic.umax";
2452 break;
2453 case nir_intrinsic_ssbo_atomic_and:
2454 name = "llvm.amdgcn.buffer.atomic.and";
2455 break;
2456 case nir_intrinsic_ssbo_atomic_or:
2457 name = "llvm.amdgcn.buffer.atomic.or";
2458 break;
2459 case nir_intrinsic_ssbo_atomic_xor:
2460 name = "llvm.amdgcn.buffer.atomic.xor";
2461 break;
2462 case nir_intrinsic_ssbo_atomic_exchange:
2463 name = "llvm.amdgcn.buffer.atomic.swap";
2464 break;
2465 case nir_intrinsic_ssbo_atomic_comp_swap:
2466 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2467 break;
2468 default:
2469 abort();
2470 }
2471
2472 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2473 }
2474
2475 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2476 const nir_intrinsic_instr *instr)
2477 {
2478 LLVMValueRef results[2];
2479 int load_components;
2480 int num_components = instr->num_components;
2481 if (instr->dest.ssa.bit_size == 64)
2482 num_components *= 2;
2483
2484 for (int i = 0; i < num_components; i += load_components) {
2485 load_components = MIN2(num_components - i, 4);
2486 const char *load_name;
2487 LLVMTypeRef data_type = ctx->ac.f32;
2488 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2489 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2490
2491 if (load_components == 3)
2492 data_type = LLVMVectorType(ctx->ac.f32, 4);
2493 else if (load_components > 1)
2494 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2495
2496 if (load_components >= 3)
2497 load_name = "llvm.amdgcn.buffer.load.v4f32";
2498 else if (load_components == 2)
2499 load_name = "llvm.amdgcn.buffer.load.v2f32";
2500 else if (load_components == 1)
2501 load_name = "llvm.amdgcn.buffer.load.f32";
2502 else
2503 unreachable("unhandled number of components");
2504
2505 LLVMValueRef params[] = {
2506 ctx->abi->load_ssbo(ctx->abi,
2507 get_src(ctx, instr->src[0]),
2508 false),
2509 LLVMConstInt(ctx->ac.i32, 0, false),
2510 offset,
2511 ctx->ac.i1false,
2512 ctx->ac.i1false,
2513 };
2514
2515 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2516
2517 }
2518
2519 assume(results[0]);
2520 LLVMValueRef ret = results[0];
2521 if (num_components > 4 || num_components == 3) {
2522 LLVMValueRef masks[] = {
2523 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2524 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2525 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2526 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2527 };
2528
2529 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2530 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2531 results[num_components > 4 ? 1 : 0], swizzle, "");
2532 }
2533
2534 return LLVMBuildBitCast(ctx->ac.builder, ret,
2535 get_def_type(ctx, &instr->dest.ssa), "");
2536 }
2537
2538 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2539 const nir_intrinsic_instr *instr)
2540 {
2541 LLVMValueRef results[8], ret;
2542 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2543 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2544 int num_components = instr->num_components;
2545
2546 if (ctx->abi->load_ubo)
2547 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2548
2549 if (instr->dest.ssa.bit_size == 64)
2550 num_components *= 2;
2551
2552 for (unsigned i = 0; i < num_components; ++i) {
2553 LLVMValueRef params[] = {
2554 rsrc,
2555 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2556 offset, "")
2557 };
2558 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2559 params, 2,
2560 AC_FUNC_ATTR_READNONE |
2561 AC_FUNC_ATTR_LEGACY);
2562 }
2563
2564
2565 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2566 return LLVMBuildBitCast(ctx->ac.builder, ret,
2567 get_def_type(ctx, &instr->dest.ssa), "");
2568 }
2569
2570 static void
2571 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2572 bool vs_in, unsigned *vertex_index_out,
2573 LLVMValueRef *vertex_index_ref,
2574 unsigned *const_out, LLVMValueRef *indir_out)
2575 {
2576 unsigned const_offset = 0;
2577 nir_deref *tail = &deref->deref;
2578 LLVMValueRef offset = NULL;
2579
2580 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2581 tail = tail->child;
2582 nir_deref_array *deref_array = nir_deref_as_array(tail);
2583 if (vertex_index_out)
2584 *vertex_index_out = deref_array->base_offset;
2585
2586 if (vertex_index_ref) {
2587 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2588 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2589 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2590 }
2591 *vertex_index_ref = vtx;
2592 }
2593 }
2594
2595 if (deref->var->data.compact) {
2596 assert(tail->child->deref_type == nir_deref_type_array);
2597 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2598 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2599 /* We always lower indirect dereferences for "compact" array vars. */
2600 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2601
2602 const_offset = deref_array->base_offset;
2603 goto out;
2604 }
2605
2606 while (tail->child != NULL) {
2607 const struct glsl_type *parent_type = tail->type;
2608 tail = tail->child;
2609
2610 if (tail->deref_type == nir_deref_type_array) {
2611 nir_deref_array *deref_array = nir_deref_as_array(tail);
2612 LLVMValueRef index, stride, local_offset;
2613 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2614
2615 const_offset += size * deref_array->base_offset;
2616 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2617 continue;
2618
2619 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2620 index = get_src(ctx, deref_array->indirect);
2621 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2622 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2623
2624 if (offset)
2625 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2626 else
2627 offset = local_offset;
2628 } else if (tail->deref_type == nir_deref_type_struct) {
2629 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2630
2631 for (unsigned i = 0; i < deref_struct->index; i++) {
2632 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2633 const_offset += glsl_count_attribute_slots(ft, vs_in);
2634 }
2635 } else
2636 unreachable("unsupported deref type");
2637
2638 }
2639 out:
2640 if (const_offset && offset)
2641 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2642 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2643 "");
2644
2645 *const_out = const_offset;
2646 *indir_out = offset;
2647 }
2648
2649
2650 /* The offchip buffer layout for TCS->TES is
2651 *
2652 * - attribute 0 of patch 0 vertex 0
2653 * - attribute 0 of patch 0 vertex 1
2654 * - attribute 0 of patch 0 vertex 2
2655 * ...
2656 * - attribute 0 of patch 1 vertex 0
2657 * - attribute 0 of patch 1 vertex 1
2658 * ...
2659 * - attribute 1 of patch 0 vertex 0
2660 * - attribute 1 of patch 0 vertex 1
2661 * ...
2662 * - per patch attribute 0 of patch 0
2663 * - per patch attribute 0 of patch 1
2664 * ...
2665 *
2666 * Note that every attribute has 4 components.
2667 */
2668 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2669 LLVMValueRef vertex_index,
2670 LLVMValueRef param_index)
2671 {
2672 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2673 LLVMValueRef param_stride, constant16;
2674 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2675
2676 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2677 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2678 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2679 num_patches, "");
2680
2681 constant16 = LLVMConstInt(ctx->i32, 16, false);
2682 if (vertex_index) {
2683 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2684 vertices_per_patch, "");
2685
2686 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2687 vertex_index, "");
2688
2689 param_stride = total_vertices;
2690 } else {
2691 base_addr = rel_patch_id;
2692 param_stride = num_patches;
2693 }
2694
2695 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2696 LLVMBuildMul(ctx->builder, param_index,
2697 param_stride, ""), "");
2698
2699 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2700
2701 if (!vertex_index) {
2702 LLVMValueRef patch_data_offset =
2703 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2704
2705 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2706 patch_data_offset, "");
2707 }
2708 return base_addr;
2709 }
2710
2711 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2712 unsigned param,
2713 unsigned const_index,
2714 bool is_compact,
2715 LLVMValueRef vertex_index,
2716 LLVMValueRef indir_index)
2717 {
2718 LLVMValueRef param_index;
2719
2720 if (indir_index)
2721 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2722 indir_index, "");
2723 else {
2724 if (const_index && !is_compact)
2725 param += const_index;
2726 param_index = LLVMConstInt(ctx->i32, param, false);
2727 }
2728 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2729 }
2730
2731 static void
2732 mark_tess_output(struct nir_to_llvm_context *ctx,
2733 bool is_patch, uint32_t param)
2734
2735 {
2736 if (is_patch) {
2737 ctx->tess_patch_outputs_written |= (1ull << param);
2738 } else
2739 ctx->tess_outputs_written |= (1ull << param);
2740 }
2741
2742 static LLVMValueRef
2743 get_dw_address(struct nir_to_llvm_context *ctx,
2744 LLVMValueRef dw_addr,
2745 unsigned param,
2746 unsigned const_index,
2747 bool compact_const_index,
2748 LLVMValueRef vertex_index,
2749 LLVMValueRef stride,
2750 LLVMValueRef indir_index)
2751
2752 {
2753
2754 if (vertex_index) {
2755 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2756 LLVMBuildMul(ctx->builder,
2757 vertex_index,
2758 stride, ""), "");
2759 }
2760
2761 if (indir_index)
2762 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2763 LLVMBuildMul(ctx->builder, indir_index,
2764 LLVMConstInt(ctx->i32, 4, false), ""), "");
2765 else if (const_index && !compact_const_index)
2766 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2767 LLVMConstInt(ctx->i32, const_index, false), "");
2768
2769 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2770 LLVMConstInt(ctx->i32, param * 4, false), "");
2771
2772 if (const_index && compact_const_index)
2773 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2774 LLVMConstInt(ctx->i32, const_index, false), "");
2775 return dw_addr;
2776 }
2777
2778 static LLVMValueRef
2779 build_varying_gather_values(struct ac_llvm_context *ctx, LLVMValueRef *values,
2780 unsigned value_count, unsigned component)
2781 {
2782 LLVMValueRef vec = NULL;
2783
2784 if (value_count == 1) {
2785 return values[component];
2786 } else if (!value_count)
2787 unreachable("value_count is 0");
2788
2789 for (unsigned i = component; i < value_count + component; i++) {
2790 LLVMValueRef value = values[i];
2791
2792 if (!i)
2793 vec = LLVMGetUndef( LLVMVectorType(LLVMTypeOf(value), value_count));
2794 LLVMValueRef index = LLVMConstInt(ctx->i32, i - component, false);
2795 vec = LLVMBuildInsertElement(ctx->builder, vec, value, index, "");
2796 }
2797 return vec;
2798 }
2799
2800 static LLVMValueRef
2801 load_tcs_input(struct nir_to_llvm_context *ctx,
2802 nir_intrinsic_instr *instr)
2803 {
2804 LLVMValueRef dw_addr, stride;
2805 unsigned const_index;
2806 LLVMValueRef vertex_index;
2807 LLVMValueRef indir_index;
2808 unsigned param;
2809 LLVMValueRef value[4], result;
2810 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2811 const bool is_compact = instr->variables[0]->var->data.compact;
2812 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2813 get_deref_offset(ctx->nir, instr->variables[0],
2814 false, NULL, per_vertex ? &vertex_index : NULL,
2815 &const_index, &indir_index);
2816
2817 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2818 dw_addr = get_tcs_in_current_patch_offset(ctx);
2819 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2820 indir_index);
2821
2822 unsigned comp = instr->variables[0]->var->data.location_frac;
2823 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2824 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2825 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2826 ctx->ac.i32_1, "");
2827 }
2828 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2829 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2830 return result;
2831 }
2832
2833 static LLVMValueRef
2834 load_tcs_output(struct nir_to_llvm_context *ctx,
2835 nir_intrinsic_instr *instr)
2836 {
2837 LLVMValueRef dw_addr;
2838 LLVMValueRef stride = NULL;
2839 LLVMValueRef value[4], result;
2840 LLVMValueRef vertex_index = NULL;
2841 LLVMValueRef indir_index = NULL;
2842 unsigned const_index = 0;
2843 unsigned param;
2844 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2845 const bool is_compact = instr->variables[0]->var->data.compact;
2846 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2847 get_deref_offset(ctx->nir, instr->variables[0],
2848 false, NULL, per_vertex ? &vertex_index : NULL,
2849 &const_index, &indir_index);
2850
2851 if (!instr->variables[0]->var->data.patch) {
2852 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2853 dw_addr = get_tcs_out_current_patch_offset(ctx);
2854 } else {
2855 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2856 }
2857
2858 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2859 indir_index);
2860
2861 unsigned comp = instr->variables[0]->var->data.location_frac;
2862 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2863 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2864 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2865 ctx->ac.i32_1, "");
2866 }
2867 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2868 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2869 return result;
2870 }
2871
2872 static void
2873 store_tcs_output(struct nir_to_llvm_context *ctx,
2874 nir_intrinsic_instr *instr,
2875 LLVMValueRef src,
2876 unsigned writemask)
2877 {
2878 LLVMValueRef dw_addr;
2879 LLVMValueRef stride = NULL;
2880 LLVMValueRef buf_addr = NULL;
2881 LLVMValueRef vertex_index = NULL;
2882 LLVMValueRef indir_index = NULL;
2883 unsigned const_index = 0;
2884 unsigned param;
2885 const unsigned comp = instr->variables[0]->var->data.location_frac;
2886 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2887 const bool is_compact = instr->variables[0]->var->data.compact;
2888
2889 get_deref_offset(ctx->nir, instr->variables[0],
2890 false, NULL, per_vertex ? &vertex_index : NULL,
2891 &const_index, &indir_index);
2892
2893 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2894 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2895 is_compact && const_index > 3) {
2896 const_index -= 3;
2897 param++;
2898 }
2899
2900 if (!instr->variables[0]->var->data.patch) {
2901 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2902 dw_addr = get_tcs_out_current_patch_offset(ctx);
2903 } else {
2904 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2905 }
2906
2907 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2908
2909 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2910 indir_index);
2911 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2912 vertex_index, indir_index);
2913
2914 bool is_tess_factor = false;
2915 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2916 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2917 is_tess_factor = true;
2918
2919 unsigned base = is_compact ? const_index : 0;
2920 for (unsigned chan = 0; chan < 8; chan++) {
2921 if (!(writemask & (1 << chan)))
2922 continue;
2923 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2924
2925 ac_lds_store(&ctx->ac, dw_addr, value);
2926
2927 if (!is_tess_factor && writemask != 0xF)
2928 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2929 buf_addr, ctx->oc_lds,
2930 4 * (base + chan), 1, 0, true, false);
2931
2932 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2933 ctx->ac.i32_1, "");
2934 }
2935
2936 if (writemask == 0xF) {
2937 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2938 buf_addr, ctx->oc_lds,
2939 (base * 4), 1, 0, true, false);
2940 }
2941 }
2942
2943 static LLVMValueRef
2944 load_tes_input(struct nir_to_llvm_context *ctx,
2945 const nir_intrinsic_instr *instr)
2946 {
2947 LLVMValueRef buf_addr;
2948 LLVMValueRef result;
2949 LLVMValueRef vertex_index = NULL;
2950 LLVMValueRef indir_index = NULL;
2951 unsigned const_index = 0;
2952 unsigned param;
2953 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2954 const bool is_compact = instr->variables[0]->var->data.compact;
2955
2956 get_deref_offset(ctx->nir, instr->variables[0],
2957 false, NULL, per_vertex ? &vertex_index : NULL,
2958 &const_index, &indir_index);
2959 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2960 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2961 is_compact && const_index > 3) {
2962 const_index -= 3;
2963 param++;
2964 }
2965
2966 unsigned comp = instr->variables[0]->var->data.location_frac;
2967 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2968 is_compact, vertex_index, indir_index);
2969
2970 LLVMValueRef comp_offset = LLVMConstInt(ctx->i32, comp * 4, false);
2971 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2972
2973 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2974 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2975 result = trim_vector(&ctx->ac, result, instr->num_components);
2976 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2977 return result;
2978 }
2979
2980 static LLVMValueRef
2981 load_gs_input(struct nir_to_llvm_context *ctx,
2982 nir_intrinsic_instr *instr)
2983 {
2984 LLVMValueRef indir_index, vtx_offset;
2985 unsigned const_index;
2986 LLVMValueRef args[9];
2987 unsigned param, vtx_offset_param;
2988 LLVMValueRef value[4], result;
2989 unsigned vertex_index;
2990 get_deref_offset(ctx->nir, instr->variables[0],
2991 false, &vertex_index, NULL,
2992 &const_index, &indir_index);
2993 vtx_offset_param = vertex_index;
2994 assert(vtx_offset_param < 6);
2995 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2996 LLVMConstInt(ctx->i32, 4, false), "");
2997
2998 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2999
3000 unsigned comp = instr->variables[0]->var->data.location_frac;
3001 for (unsigned i = comp; i < instr->num_components + comp; i++) {
3002 if (ctx->ac.chip_class >= GFX9) {
3003 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3004 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3005 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3006 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3007 } else {
3008 args[0] = ctx->esgs_ring;
3009 args[1] = vtx_offset;
3010 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
3011 args[3] = ctx->ac.i32_0;
3012 args[4] = ctx->ac.i32_1; /* OFFEN */
3013 args[5] = ctx->ac.i32_0; /* IDXEN */
3014 args[6] = ctx->ac.i32_1; /* GLC */
3015 args[7] = ctx->ac.i32_0; /* SLC */
3016 args[8] = ctx->ac.i32_0; /* TFE */
3017
3018 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3019 ctx->i32, args, 9,
3020 AC_FUNC_ATTR_READONLY |
3021 AC_FUNC_ATTR_LEGACY);
3022 }
3023 }
3024 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
3025
3026 return result;
3027 }
3028
3029 static LLVMValueRef
3030 build_gep_for_deref(struct ac_nir_context *ctx,
3031 nir_deref_var *deref)
3032 {
3033 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3034 assert(entry->data);
3035 LLVMValueRef val = entry->data;
3036 nir_deref *tail = deref->deref.child;
3037 while (tail != NULL) {
3038 LLVMValueRef offset;
3039 switch (tail->deref_type) {
3040 case nir_deref_type_array: {
3041 nir_deref_array *array = nir_deref_as_array(tail);
3042 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3043 if (array->deref_array_type ==
3044 nir_deref_array_type_indirect) {
3045 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3046 get_src(ctx,
3047 array->indirect),
3048 "");
3049 }
3050 break;
3051 }
3052 case nir_deref_type_struct: {
3053 nir_deref_struct *deref_struct =
3054 nir_deref_as_struct(tail);
3055 offset = LLVMConstInt(ctx->ac.i32,
3056 deref_struct->index, 0);
3057 break;
3058 }
3059 default:
3060 unreachable("bad deref type");
3061 }
3062 val = ac_build_gep0(&ctx->ac, val, offset);
3063 tail = tail->child;
3064 }
3065 return val;
3066 }
3067
3068 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3069 nir_intrinsic_instr *instr)
3070 {
3071 LLVMValueRef values[8];
3072 int idx = instr->variables[0]->var->data.driver_location;
3073 int ve = instr->dest.ssa.num_components;
3074 unsigned comp = instr->variables[0]->var->data.location_frac;
3075 LLVMValueRef indir_index;
3076 LLVMValueRef ret;
3077 unsigned const_index;
3078 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3079 instr->variables[0]->var->data.mode == nir_var_shader_in;
3080 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3081 &const_index, &indir_index);
3082
3083 if (instr->dest.ssa.bit_size == 64)
3084 ve *= 2;
3085
3086 switch (instr->variables[0]->var->data.mode) {
3087 case nir_var_shader_in:
3088 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3089 return load_tcs_input(ctx->nctx, instr);
3090 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3091 return load_tes_input(ctx->nctx, instr);
3092 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3093 return load_gs_input(ctx->nctx, instr);
3094 }
3095
3096 for (unsigned chan = comp; chan < ve + comp; chan++) {
3097 if (indir_index) {
3098 unsigned count = glsl_count_attribute_slots(
3099 instr->variables[0]->var->type,
3100 ctx->stage == MESA_SHADER_VERTEX);
3101 count -= chan / 4;
3102 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3103 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3104 4, false, true);
3105
3106 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3107 tmp_vec,
3108 indir_index, "");
3109 } else
3110 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3111 }
3112 break;
3113 case nir_var_local:
3114 for (unsigned chan = 0; chan < ve; chan++) {
3115 if (indir_index) {
3116 unsigned count = glsl_count_attribute_slots(
3117 instr->variables[0]->var->type, false);
3118 count -= chan / 4;
3119 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3120 &ctx->ac, ctx->locals + idx + chan, count,
3121 4, true, true);
3122
3123 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3124 tmp_vec,
3125 indir_index, "");
3126 } else {
3127 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3128 }
3129 }
3130 break;
3131 case nir_var_shared: {
3132 LLVMValueRef address = build_gep_for_deref(ctx,
3133 instr->variables[0]);
3134 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3135 return LLVMBuildBitCast(ctx->ac.builder, val,
3136 get_def_type(ctx, &instr->dest.ssa),
3137 "");
3138 }
3139 case nir_var_shader_out:
3140 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3141 return load_tcs_output(ctx->nctx, instr);
3142
3143 for (unsigned chan = comp; chan < ve + comp; chan++) {
3144 if (indir_index) {
3145 unsigned count = glsl_count_attribute_slots(
3146 instr->variables[0]->var->type, false);
3147 count -= chan / 4;
3148 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3149 &ctx->ac, ctx->outputs + idx + chan, count,
3150 4, true, true);
3151
3152 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3153 tmp_vec,
3154 indir_index, "");
3155 } else {
3156 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3157 ctx->outputs[idx + chan + const_index * 4],
3158 "");
3159 }
3160 }
3161 break;
3162 default:
3163 unreachable("unhandle variable mode");
3164 }
3165 ret = build_varying_gather_values(&ctx->ac, values, ve, comp);
3166 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3167 }
3168
3169 static void
3170 visit_store_var(struct ac_nir_context *ctx,
3171 nir_intrinsic_instr *instr)
3172 {
3173 LLVMValueRef temp_ptr, value;
3174 int idx = instr->variables[0]->var->data.driver_location;
3175 unsigned comp = instr->variables[0]->var->data.location_frac;
3176 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3177 int writemask = instr->const_index[0] << comp;
3178 LLVMValueRef indir_index;
3179 unsigned const_index;
3180 get_deref_offset(ctx, instr->variables[0], false,
3181 NULL, NULL, &const_index, &indir_index);
3182
3183 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3184 int old_writemask = writemask;
3185
3186 src = LLVMBuildBitCast(ctx->ac.builder, src,
3187 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3188 "");
3189
3190 writemask = 0;
3191 for (unsigned chan = 0; chan < 4; chan++) {
3192 if (old_writemask & (1 << chan))
3193 writemask |= 3u << (2 * chan);
3194 }
3195 }
3196
3197 switch (instr->variables[0]->var->data.mode) {
3198 case nir_var_shader_out:
3199
3200 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3201 store_tcs_output(ctx->nctx, instr, src, writemask);
3202 return;
3203 }
3204
3205 for (unsigned chan = 0; chan < 8; chan++) {
3206 int stride = 4;
3207 if (!(writemask & (1 << chan)))
3208 continue;
3209
3210 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3211
3212 if (instr->variables[0]->var->data.compact)
3213 stride = 1;
3214 if (indir_index) {
3215 unsigned count = glsl_count_attribute_slots(
3216 instr->variables[0]->var->type, false);
3217 count -= chan / 4;
3218 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3219 &ctx->ac, ctx->outputs + idx + chan, count,
3220 stride, true, true);
3221
3222 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3223 value, indir_index, "");
3224 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3225 count, stride, tmp_vec);
3226
3227 } else {
3228 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3229
3230 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3231 }
3232 }
3233 break;
3234 case nir_var_local:
3235 for (unsigned chan = 0; chan < 8; chan++) {
3236 if (!(writemask & (1 << chan)))
3237 continue;
3238
3239 value = llvm_extract_elem(&ctx->ac, src, chan);
3240 if (indir_index) {
3241 unsigned count = glsl_count_attribute_slots(
3242 instr->variables[0]->var->type, false);
3243 count -= chan / 4;
3244 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3245 &ctx->ac, ctx->locals + idx + chan, count,
3246 4, true, true);
3247
3248 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3249 value, indir_index, "");
3250 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3251 count, 4, tmp_vec);
3252 } else {
3253 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3254
3255 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3256 }
3257 }
3258 break;
3259 case nir_var_shared: {
3260 int writemask = instr->const_index[0];
3261 LLVMValueRef address = build_gep_for_deref(ctx,
3262 instr->variables[0]);
3263 LLVMValueRef val = get_src(ctx, instr->src[0]);
3264 unsigned components =
3265 glsl_get_vector_elements(
3266 nir_deref_tail(&instr->variables[0]->deref)->type);
3267 if (writemask == (1 << components) - 1) {
3268 val = LLVMBuildBitCast(
3269 ctx->ac.builder, val,
3270 LLVMGetElementType(LLVMTypeOf(address)), "");
3271 LLVMBuildStore(ctx->ac.builder, val, address);
3272 } else {
3273 for (unsigned chan = 0; chan < 4; chan++) {
3274 if (!(writemask & (1 << chan)))
3275 continue;
3276 LLVMValueRef ptr =
3277 LLVMBuildStructGEP(ctx->ac.builder,
3278 address, chan, "");
3279 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3280 chan);
3281 src = LLVMBuildBitCast(
3282 ctx->ac.builder, src,
3283 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3284 LLVMBuildStore(ctx->ac.builder, src, ptr);
3285 }
3286 }
3287 break;
3288 }
3289 default:
3290 break;
3291 }
3292 }
3293
3294 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3295 {
3296 switch (dim) {
3297 case GLSL_SAMPLER_DIM_BUF:
3298 return 1;
3299 case GLSL_SAMPLER_DIM_1D:
3300 return array ? 2 : 1;
3301 case GLSL_SAMPLER_DIM_2D:
3302 return array ? 3 : 2;
3303 case GLSL_SAMPLER_DIM_MS:
3304 return array ? 4 : 3;
3305 case GLSL_SAMPLER_DIM_3D:
3306 case GLSL_SAMPLER_DIM_CUBE:
3307 return 3;
3308 case GLSL_SAMPLER_DIM_RECT:
3309 case GLSL_SAMPLER_DIM_SUBPASS:
3310 return 2;
3311 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3312 return 3;
3313 default:
3314 break;
3315 }
3316 return 0;
3317 }
3318
3319
3320
3321 /* Adjust the sample index according to FMASK.
3322 *
3323 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3324 * which is the identity mapping. Each nibble says which physical sample
3325 * should be fetched to get that sample.
3326 *
3327 * For example, 0x11111100 means there are only 2 samples stored and
3328 * the second sample covers 3/4 of the pixel. When reading samples 0
3329 * and 1, return physical sample 0 (determined by the first two 0s
3330 * in FMASK), otherwise return physical sample 1.
3331 *
3332 * The sample index should be adjusted as follows:
3333 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3334 */
3335 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3336 LLVMValueRef coord_x, LLVMValueRef coord_y,
3337 LLVMValueRef coord_z,
3338 LLVMValueRef sample_index,
3339 LLVMValueRef fmask_desc_ptr)
3340 {
3341 LLVMValueRef fmask_load_address[4];
3342 LLVMValueRef res;
3343
3344 fmask_load_address[0] = coord_x;
3345 fmask_load_address[1] = coord_y;
3346 if (coord_z) {
3347 fmask_load_address[2] = coord_z;
3348 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3349 }
3350
3351 struct ac_image_args args = {0};
3352
3353 args.opcode = ac_image_load;
3354 args.da = coord_z ? true : false;
3355 args.resource = fmask_desc_ptr;
3356 args.dmask = 0xf;
3357 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3358
3359 res = ac_build_image_opcode(ctx, &args);
3360
3361 res = ac_to_integer(ctx, res);
3362 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3363 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3364
3365 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3366 res,
3367 ctx->i32_0, "");
3368
3369 LLVMValueRef sample_index4 =
3370 LLVMBuildMul(ctx->builder, sample_index, four, "");
3371 LLVMValueRef shifted_fmask =
3372 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3373 LLVMValueRef final_sample =
3374 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3375
3376 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3377 * resource descriptor is 0 (invalid),
3378 */
3379 LLVMValueRef fmask_desc =
3380 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3381 ctx->v8i32, "");
3382
3383 LLVMValueRef fmask_word1 =
3384 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3385 ctx->i32_1, "");
3386
3387 LLVMValueRef word1_is_nonzero =
3388 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3389 fmask_word1, ctx->i32_0, "");
3390
3391 /* Replace the MSAA sample index. */
3392 sample_index =
3393 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3394 final_sample, sample_index, "");
3395 return sample_index;
3396 }
3397
3398 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3399 const nir_intrinsic_instr *instr)
3400 {
3401 const struct glsl_type *type = instr->variables[0]->var->type;
3402 if(instr->variables[0]->deref.child)
3403 type = instr->variables[0]->deref.child->type;
3404
3405 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3406 LLVMValueRef coords[4];
3407 LLVMValueRef masks[] = {
3408 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3409 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3410 };
3411 LLVMValueRef res;
3412 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3413
3414 int count;
3415 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3416 bool is_array = glsl_sampler_type_is_array(type);
3417 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3418 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3419 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3420 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3421 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3422 count = image_type_to_components_count(dim, is_array);
3423
3424 if (is_ms) {
3425 LLVMValueRef fmask_load_address[3];
3426 int chan;
3427
3428 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3429 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3430 if (is_array)
3431 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3432 else
3433 fmask_load_address[2] = NULL;
3434 if (add_frag_pos) {
3435 for (chan = 0; chan < 2; ++chan)
3436 fmask_load_address[chan] =
3437 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3438 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3439 ctx->ac.i32, ""), "");
3440 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3441 }
3442 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3443 fmask_load_address[0],
3444 fmask_load_address[1],
3445 fmask_load_address[2],
3446 sample_index,
3447 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3448 }
3449 if (count == 1 && !gfx9_1d) {
3450 if (instr->src[0].ssa->num_components)
3451 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3452 else
3453 res = src0;
3454 } else {
3455 int chan;
3456 if (is_ms)
3457 count--;
3458 for (chan = 0; chan < count; ++chan) {
3459 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3460 }
3461 if (add_frag_pos) {
3462 for (chan = 0; chan < 2; ++chan)
3463 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3464 ctx->ac.i32, ""), "");
3465 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3466 count++;
3467 }
3468
3469 if (gfx9_1d) {
3470 if (is_array) {
3471 coords[2] = coords[1];
3472 coords[1] = ctx->ac.i32_0;
3473 } else
3474 coords[1] = ctx->ac.i32_0;
3475 count++;
3476 }
3477
3478 if (is_ms) {
3479 coords[count] = sample_index;
3480 count++;
3481 }
3482
3483 if (count == 3) {
3484 coords[3] = LLVMGetUndef(ctx->ac.i32);
3485 count = 4;
3486 }
3487 res = ac_build_gather_values(&ctx->ac, coords, count);
3488 }
3489 return res;
3490 }
3491
3492 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3493 const nir_intrinsic_instr *instr)
3494 {
3495 LLVMValueRef params[7];
3496 LLVMValueRef res;
3497 char intrinsic_name[64];
3498 const nir_variable *var = instr->variables[0]->var;
3499 const struct glsl_type *type = var->type;
3500
3501 if(instr->variables[0]->deref.child)
3502 type = instr->variables[0]->deref.child->type;
3503
3504 type = glsl_without_array(type);
3505 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3506 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3507 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3508 ctx->ac.i32_0, ""); /* vindex */
3509 params[2] = ctx->ac.i32_0; /* voffset */
3510 params[3] = ctx->ac.i1false; /* glc */
3511 params[4] = ctx->ac.i1false; /* slc */
3512 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3513 params, 5, 0);
3514
3515 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3516 res = ac_to_integer(&ctx->ac, res);
3517 } else {
3518 bool is_da = glsl_sampler_type_is_array(type) ||
3519 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3520 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3521 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3522 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3523 LLVMValueRef glc = ctx->ac.i1false;
3524 LLVMValueRef slc = ctx->ac.i1false;
3525
3526 params[0] = get_image_coords(ctx, instr);
3527 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3528 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3529 if (HAVE_LLVM <= 0x0309) {
3530 params[3] = ctx->ac.i1false; /* r128 */
3531 params[4] = da;
3532 params[5] = glc;
3533 params[6] = slc;
3534 } else {
3535 LLVMValueRef lwe = ctx->ac.i1false;
3536 params[3] = glc;
3537 params[4] = slc;
3538 params[5] = lwe;
3539 params[6] = da;
3540 }
3541
3542 ac_get_image_intr_name("llvm.amdgcn.image.load",
3543 ctx->ac.v4f32, /* vdata */
3544 LLVMTypeOf(params[0]), /* coords */
3545 LLVMTypeOf(params[1]), /* rsrc */
3546 intrinsic_name, sizeof(intrinsic_name));
3547
3548 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3549 params, 7, AC_FUNC_ATTR_READONLY);
3550 }
3551 return ac_to_integer(&ctx->ac, res);
3552 }
3553
3554 static void visit_image_store(struct ac_nir_context *ctx,
3555 nir_intrinsic_instr *instr)
3556 {
3557 LLVMValueRef params[8];
3558 char intrinsic_name[64];
3559 const nir_variable *var = instr->variables[0]->var;
3560 const struct glsl_type *type = glsl_without_array(var->type);
3561 LLVMValueRef glc = ctx->ac.i1false;
3562 bool force_glc = ctx->ac.chip_class == SI;
3563 if (force_glc)
3564 glc = ctx->ac.i1true;
3565
3566 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3567 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3568 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3569 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3570 ctx->ac.i32_0, ""); /* vindex */
3571 params[3] = ctx->ac.i32_0; /* voffset */
3572 params[4] = glc; /* glc */
3573 params[5] = ctx->ac.i1false; /* slc */
3574 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3575 params, 6, 0);
3576 } else {
3577 bool is_da = glsl_sampler_type_is_array(type) ||
3578 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3579 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3580 LLVMValueRef slc = ctx->ac.i1false;
3581
3582 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3583 params[1] = get_image_coords(ctx, instr); /* coords */
3584 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3585 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3586 if (HAVE_LLVM <= 0x0309) {
3587 params[4] = ctx->ac.i1false; /* r128 */
3588 params[5] = da;
3589 params[6] = glc;
3590 params[7] = slc;
3591 } else {
3592 LLVMValueRef lwe = ctx->ac.i1false;
3593 params[4] = glc;
3594 params[5] = slc;
3595 params[6] = lwe;
3596 params[7] = da;
3597 }
3598
3599 ac_get_image_intr_name("llvm.amdgcn.image.store",
3600 LLVMTypeOf(params[0]), /* vdata */
3601 LLVMTypeOf(params[1]), /* coords */
3602 LLVMTypeOf(params[2]), /* rsrc */
3603 intrinsic_name, sizeof(intrinsic_name));
3604
3605 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3606 params, 8, 0);
3607 }
3608
3609 }
3610
3611 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3612 const nir_intrinsic_instr *instr)
3613 {
3614 LLVMValueRef params[7];
3615 int param_count = 0;
3616 const nir_variable *var = instr->variables[0]->var;
3617
3618 const char *atomic_name;
3619 char intrinsic_name[41];
3620 const struct glsl_type *type = glsl_without_array(var->type);
3621 MAYBE_UNUSED int length;
3622
3623 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3624
3625 switch (instr->intrinsic) {
3626 case nir_intrinsic_image_atomic_add:
3627 atomic_name = "add";
3628 break;
3629 case nir_intrinsic_image_atomic_min:
3630 atomic_name = is_unsigned ? "umin" : "smin";
3631 break;
3632 case nir_intrinsic_image_atomic_max:
3633 atomic_name = is_unsigned ? "umax" : "smax";
3634 break;
3635 case nir_intrinsic_image_atomic_and:
3636 atomic_name = "and";
3637 break;
3638 case nir_intrinsic_image_atomic_or:
3639 atomic_name = "or";
3640 break;
3641 case nir_intrinsic_image_atomic_xor:
3642 atomic_name = "xor";
3643 break;
3644 case nir_intrinsic_image_atomic_exchange:
3645 atomic_name = "swap";
3646 break;
3647 case nir_intrinsic_image_atomic_comp_swap:
3648 atomic_name = "cmpswap";
3649 break;
3650 default:
3651 abort();
3652 }
3653
3654 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3655 params[param_count++] = get_src(ctx, instr->src[3]);
3656 params[param_count++] = get_src(ctx, instr->src[2]);
3657
3658 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3659 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3660 true, true);
3661 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3662 ctx->ac.i32_0, ""); /* vindex */
3663 params[param_count++] = ctx->ac.i32_0; /* voffset */
3664 params[param_count++] = ctx->ac.i1false; /* slc */
3665
3666 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3667 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3668 } else {
3669 char coords_type[8];
3670
3671 bool da = glsl_sampler_type_is_array(type) ||
3672 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3673
3674 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3675 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3676 true, true);
3677 params[param_count++] = ctx->ac.i1false; /* r128 */
3678 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3679 params[param_count++] = ctx->ac.i1false; /* slc */
3680
3681 build_int_type_name(LLVMTypeOf(coords),
3682 coords_type, sizeof(coords_type));
3683
3684 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3685 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3686 }
3687
3688 assert(length < sizeof(intrinsic_name));
3689 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3690 }
3691
3692 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3693 const nir_intrinsic_instr *instr)
3694 {
3695 LLVMValueRef res;
3696 const nir_variable *var = instr->variables[0]->var;
3697 const struct glsl_type *type = instr->variables[0]->var->type;
3698 bool da = glsl_sampler_type_is_array(var->type) ||
3699 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3700 if(instr->variables[0]->deref.child)
3701 type = instr->variables[0]->deref.child->type;
3702
3703 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3704 return get_buffer_size(ctx,
3705 get_sampler_desc(ctx, instr->variables[0],
3706 AC_DESC_BUFFER, true, false), true);
3707
3708 struct ac_image_args args = { 0 };
3709
3710 args.da = da;
3711 args.dmask = 0xf;
3712 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3713 args.opcode = ac_image_get_resinfo;
3714 args.addr = ctx->ac.i32_0;
3715
3716 res = ac_build_image_opcode(&ctx->ac, &args);
3717
3718 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3719
3720 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3721 glsl_sampler_type_is_array(type)) {
3722 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3723 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3724 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3725 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3726 }
3727 if (ctx->ac.chip_class >= GFX9 &&
3728 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3729 glsl_sampler_type_is_array(type)) {
3730 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3731 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3732 ctx->ac.i32_1, "");
3733
3734 }
3735 return res;
3736 }
3737
3738 #define NOOP_WAITCNT 0xf7f
3739 #define LGKM_CNT 0x07f
3740 #define VM_CNT 0xf70
3741
3742 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3743 unsigned simm16)
3744 {
3745 LLVMValueRef args[1] = {
3746 LLVMConstInt(ctx->i32, simm16, false),
3747 };
3748 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3749 ctx->voidt, args, 1, 0);
3750 }
3751
3752 static void emit_barrier(struct nir_to_llvm_context *ctx)
3753 {
3754 /* SI only (thanks to a hw bug workaround):
3755 * The real barrier instruction isn’t needed, because an entire patch
3756 * always fits into a single wave.
3757 */
3758 if (ctx->options->chip_class == SI &&
3759 ctx->stage == MESA_SHADER_TESS_CTRL) {
3760 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3761 return;
3762 }
3763 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3764 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3765 }
3766
3767 static void emit_discard_if(struct ac_nir_context *ctx,
3768 const nir_intrinsic_instr *instr)
3769 {
3770 LLVMValueRef cond;
3771
3772 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3773 get_src(ctx, instr->src[0]),
3774 ctx->ac.i32_0, "");
3775 ac_build_kill_if_false(&ctx->ac, cond);
3776 }
3777
3778 static LLVMValueRef
3779 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3780 {
3781 LLVMValueRef result;
3782 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3783 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3784 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3785
3786 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3787 }
3788
3789 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3790 const nir_intrinsic_instr *instr)
3791 {
3792 LLVMValueRef ptr, result;
3793 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3794 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3795
3796 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3797 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3798 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3799 ptr, src, src1,
3800 LLVMAtomicOrderingSequentiallyConsistent,
3801 LLVMAtomicOrderingSequentiallyConsistent,
3802 false);
3803 } else {
3804 LLVMAtomicRMWBinOp op;
3805 switch (instr->intrinsic) {
3806 case nir_intrinsic_var_atomic_add:
3807 op = LLVMAtomicRMWBinOpAdd;
3808 break;
3809 case nir_intrinsic_var_atomic_umin:
3810 op = LLVMAtomicRMWBinOpUMin;
3811 break;
3812 case nir_intrinsic_var_atomic_umax:
3813 op = LLVMAtomicRMWBinOpUMax;
3814 break;
3815 case nir_intrinsic_var_atomic_imin:
3816 op = LLVMAtomicRMWBinOpMin;
3817 break;
3818 case nir_intrinsic_var_atomic_imax:
3819 op = LLVMAtomicRMWBinOpMax;
3820 break;
3821 case nir_intrinsic_var_atomic_and:
3822 op = LLVMAtomicRMWBinOpAnd;
3823 break;
3824 case nir_intrinsic_var_atomic_or:
3825 op = LLVMAtomicRMWBinOpOr;
3826 break;
3827 case nir_intrinsic_var_atomic_xor:
3828 op = LLVMAtomicRMWBinOpXor;
3829 break;
3830 case nir_intrinsic_var_atomic_exchange:
3831 op = LLVMAtomicRMWBinOpXchg;
3832 break;
3833 default:
3834 return NULL;
3835 }
3836
3837 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3838 LLVMAtomicOrderingSequentiallyConsistent,
3839 false);
3840 }
3841 return result;
3842 }
3843
3844 #define INTERP_CENTER 0
3845 #define INTERP_CENTROID 1
3846 #define INTERP_SAMPLE 2
3847
3848 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3849 enum glsl_interp_mode interp, unsigned location)
3850 {
3851 switch (interp) {
3852 case INTERP_MODE_FLAT:
3853 default:
3854 return NULL;
3855 case INTERP_MODE_SMOOTH:
3856 case INTERP_MODE_NONE:
3857 if (location == INTERP_CENTER)
3858 return ctx->persp_center;
3859 else if (location == INTERP_CENTROID)
3860 return ctx->persp_centroid;
3861 else if (location == INTERP_SAMPLE)
3862 return ctx->persp_sample;
3863 break;
3864 case INTERP_MODE_NOPERSPECTIVE:
3865 if (location == INTERP_CENTER)
3866 return ctx->linear_center;
3867 else if (location == INTERP_CENTROID)
3868 return ctx->linear_centroid;
3869 else if (location == INTERP_SAMPLE)
3870 return ctx->linear_sample;
3871 break;
3872 }
3873 return NULL;
3874 }
3875
3876 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3877 LLVMValueRef sample_id)
3878 {
3879 LLVMValueRef result;
3880 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3881
3882 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3883 const_array(ctx->v2f32, 64), "");
3884
3885 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3886 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3887
3888 return result;
3889 }
3890
3891 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3892 {
3893 LLVMValueRef values[2];
3894
3895 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3896 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3897 return ac_build_gather_values(&ctx->ac, values, 2);
3898 }
3899
3900 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3901 const nir_intrinsic_instr *instr)
3902 {
3903 LLVMValueRef result[4];
3904 LLVMValueRef interp_param, attr_number;
3905 unsigned location;
3906 unsigned chan;
3907 LLVMValueRef src_c0 = NULL;
3908 LLVMValueRef src_c1 = NULL;
3909 LLVMValueRef src0 = NULL;
3910 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3911 switch (instr->intrinsic) {
3912 case nir_intrinsic_interp_var_at_centroid:
3913 location = INTERP_CENTROID;
3914 break;
3915 case nir_intrinsic_interp_var_at_sample:
3916 case nir_intrinsic_interp_var_at_offset:
3917 location = INTERP_CENTER;
3918 src0 = get_src(ctx->nir, instr->src[0]);
3919 break;
3920 default:
3921 break;
3922 }
3923
3924 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3925 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3926 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3927 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3928 LLVMValueRef sample_position;
3929 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3930
3931 /* fetch sample ID */
3932 sample_position = load_sample_position(ctx, src0);
3933
3934 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3935 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3936 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3937 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3938 }
3939 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3940 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3941
3942 if (location == INTERP_CENTER) {
3943 LLVMValueRef ij_out[2];
3944 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3945
3946 /*
3947 * take the I then J parameters, and the DDX/Y for it, and
3948 * calculate the IJ inputs for the interpolator.
3949 * temp1 = ddx * offset/sample.x + I;
3950 * interp_param.I = ddy * offset/sample.y + temp1;
3951 * temp1 = ddx * offset/sample.x + J;
3952 * interp_param.J = ddy * offset/sample.y + temp1;
3953 */
3954 for (unsigned i = 0; i < 2; i++) {
3955 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3956 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3957 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3958 ddxy_out, ix_ll, "");
3959 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3960 ddxy_out, iy_ll, "");
3961 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3962 interp_param, ix_ll, "");
3963 LLVMValueRef temp1, temp2;
3964
3965 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3966 ctx->f32, "");
3967
3968 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3969 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3970
3971 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3972 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3973
3974 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3975 temp2, ctx->i32, "");
3976 }
3977 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3978
3979 }
3980
3981 for (chan = 0; chan < 4; chan++) {
3982 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3983
3984 if (interp_param) {
3985 interp_param = LLVMBuildBitCast(ctx->builder,
3986 interp_param, LLVMVectorType(ctx->f32, 2), "");
3987 LLVMValueRef i = LLVMBuildExtractElement(
3988 ctx->builder, interp_param, ctx->ac.i32_0, "");
3989 LLVMValueRef j = LLVMBuildExtractElement(
3990 ctx->builder, interp_param, ctx->ac.i32_1, "");
3991
3992 result[chan] = ac_build_fs_interp(&ctx->ac,
3993 llvm_chan, attr_number,
3994 ctx->prim_mask, i, j);
3995 } else {
3996 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3997 LLVMConstInt(ctx->i32, 2, false),
3998 llvm_chan, attr_number,
3999 ctx->prim_mask);
4000 }
4001 }
4002 return build_varying_gather_values(&ctx->ac, result, instr->num_components,
4003 instr->variables[0]->var->data.location_frac);
4004 }
4005
4006 static void
4007 visit_emit_vertex(struct nir_to_llvm_context *ctx,
4008 const nir_intrinsic_instr *instr)
4009 {
4010 LLVMValueRef gs_next_vertex;
4011 LLVMValueRef can_emit;
4012 int idx;
4013
4014 assert(instr->const_index[0] == 0);
4015 /* Write vertex attribute values to GSVS ring */
4016 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4017 ctx->gs_next_vertex,
4018 "");
4019
4020 /* If this thread has already emitted the declared maximum number of
4021 * vertices, kill it: excessive vertex emissions are not supposed to
4022 * have any effect, and GS threads have no externally observable
4023 * effects other than emitting vertices.
4024 */
4025 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4026 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
4027 ac_build_kill_if_false(&ctx->ac, can_emit);
4028
4029 /* loop num outputs */
4030 idx = 0;
4031 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4032 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
4033 int length = 4;
4034 int slot = idx;
4035 int slot_inc = 1;
4036
4037 if (!(ctx->output_mask & (1ull << i)))
4038 continue;
4039
4040 if (i == VARYING_SLOT_CLIP_DIST0) {
4041 /* pack clip and cull into a single set of slots */
4042 length = ctx->num_output_clips + ctx->num_output_culls;
4043 if (length > 4)
4044 slot_inc = 2;
4045 }
4046 for (unsigned j = 0; j < length; j++) {
4047 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4048 out_ptr[j], "");
4049 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4050 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4051 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
4052
4053 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4054
4055 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4056 out_val, 1,
4057 voffset, ctx->gs2vs_offset, 0,
4058 1, 1, true, true);
4059 }
4060 idx += slot_inc;
4061 }
4062
4063 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4064 ctx->ac.i32_1, "");
4065 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4066
4067 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4068 }
4069
4070 static void
4071 visit_end_primitive(struct nir_to_llvm_context *ctx,
4072 const nir_intrinsic_instr *instr)
4073 {
4074 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4075 }
4076
4077 static LLVMValueRef
4078 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4079 const nir_intrinsic_instr *instr)
4080 {
4081 LLVMValueRef coord[4] = {
4082 ctx->tes_u,
4083 ctx->tes_v,
4084 ctx->ac.f32_0,
4085 ctx->ac.f32_0,
4086 };
4087
4088 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4089 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4090 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4091
4092 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4093 return LLVMBuildBitCast(ctx->builder, result,
4094 get_def_type(ctx->nir, &instr->dest.ssa), "");
4095 }
4096
4097 static void visit_intrinsic(struct ac_nir_context *ctx,
4098 nir_intrinsic_instr *instr)
4099 {
4100 LLVMValueRef result = NULL;
4101
4102 switch (instr->intrinsic) {
4103 case nir_intrinsic_load_work_group_id: {
4104 result = ctx->nctx->workgroup_ids;
4105 break;
4106 }
4107 case nir_intrinsic_load_base_vertex: {
4108 result = ctx->abi->base_vertex;
4109 break;
4110 }
4111 case nir_intrinsic_load_vertex_id_zero_base: {
4112 result = ctx->abi->vertex_id;
4113 break;
4114 }
4115 case nir_intrinsic_load_local_invocation_id: {
4116 result = ctx->nctx->local_invocation_ids;
4117 break;
4118 }
4119 case nir_intrinsic_load_base_instance:
4120 result = ctx->abi->start_instance;
4121 break;
4122 case nir_intrinsic_load_draw_id:
4123 result = ctx->abi->draw_id;
4124 break;
4125 case nir_intrinsic_load_view_index:
4126 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4127 break;
4128 case nir_intrinsic_load_invocation_id:
4129 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4130 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4131 else
4132 result = ctx->nctx->gs_invocation_id;
4133 break;
4134 case nir_intrinsic_load_primitive_id:
4135 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4136 ctx->nctx->shader_info->gs.uses_prim_id = true;
4137 result = ctx->nctx->gs_prim_id;
4138 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4139 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4140 result = ctx->nctx->tcs_patch_id;
4141 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4142 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4143 result = ctx->nctx->tes_patch_id;
4144 } else
4145 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4146 break;
4147 case nir_intrinsic_load_sample_id:
4148 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4149 break;
4150 case nir_intrinsic_load_sample_pos:
4151 result = load_sample_pos(ctx);
4152 break;
4153 case nir_intrinsic_load_sample_mask_in:
4154 result = ctx->abi->sample_coverage;
4155 break;
4156 case nir_intrinsic_load_frag_coord: {
4157 LLVMValueRef values[4] = {
4158 ctx->abi->frag_pos[0],
4159 ctx->abi->frag_pos[1],
4160 ctx->abi->frag_pos[2],
4161 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4162 };
4163 result = ac_build_gather_values(&ctx->ac, values, 4);
4164 break;
4165 }
4166 case nir_intrinsic_load_front_face:
4167 result = ctx->abi->front_face;
4168 break;
4169 case nir_intrinsic_load_instance_id:
4170 result = ctx->abi->instance_id;
4171 break;
4172 case nir_intrinsic_load_num_work_groups:
4173 result = ctx->nctx->num_work_groups;
4174 break;
4175 case nir_intrinsic_load_local_invocation_index:
4176 result = visit_load_local_invocation_index(ctx->nctx);
4177 break;
4178 case nir_intrinsic_load_push_constant:
4179 result = visit_load_push_constant(ctx->nctx, instr);
4180 break;
4181 case nir_intrinsic_vulkan_resource_index:
4182 result = visit_vulkan_resource_index(ctx->nctx, instr);
4183 break;
4184 case nir_intrinsic_store_ssbo:
4185 visit_store_ssbo(ctx, instr);
4186 break;
4187 case nir_intrinsic_load_ssbo:
4188 result = visit_load_buffer(ctx, instr);
4189 break;
4190 case nir_intrinsic_ssbo_atomic_add:
4191 case nir_intrinsic_ssbo_atomic_imin:
4192 case nir_intrinsic_ssbo_atomic_umin:
4193 case nir_intrinsic_ssbo_atomic_imax:
4194 case nir_intrinsic_ssbo_atomic_umax:
4195 case nir_intrinsic_ssbo_atomic_and:
4196 case nir_intrinsic_ssbo_atomic_or:
4197 case nir_intrinsic_ssbo_atomic_xor:
4198 case nir_intrinsic_ssbo_atomic_exchange:
4199 case nir_intrinsic_ssbo_atomic_comp_swap:
4200 result = visit_atomic_ssbo(ctx, instr);
4201 break;
4202 case nir_intrinsic_load_ubo:
4203 result = visit_load_ubo_buffer(ctx, instr);
4204 break;
4205 case nir_intrinsic_get_buffer_size:
4206 result = visit_get_buffer_size(ctx, instr);
4207 break;
4208 case nir_intrinsic_load_var:
4209 result = visit_load_var(ctx, instr);
4210 break;
4211 case nir_intrinsic_store_var:
4212 visit_store_var(ctx, instr);
4213 break;
4214 case nir_intrinsic_image_load:
4215 result = visit_image_load(ctx, instr);
4216 break;
4217 case nir_intrinsic_image_store:
4218 visit_image_store(ctx, instr);
4219 break;
4220 case nir_intrinsic_image_atomic_add:
4221 case nir_intrinsic_image_atomic_min:
4222 case nir_intrinsic_image_atomic_max:
4223 case nir_intrinsic_image_atomic_and:
4224 case nir_intrinsic_image_atomic_or:
4225 case nir_intrinsic_image_atomic_xor:
4226 case nir_intrinsic_image_atomic_exchange:
4227 case nir_intrinsic_image_atomic_comp_swap:
4228 result = visit_image_atomic(ctx, instr);
4229 break;
4230 case nir_intrinsic_image_size:
4231 result = visit_image_size(ctx, instr);
4232 break;
4233 case nir_intrinsic_discard:
4234 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4235 LLVMVoidTypeInContext(ctx->ac.context),
4236 NULL, 0, AC_FUNC_ATTR_LEGACY);
4237 break;
4238 case nir_intrinsic_discard_if:
4239 emit_discard_if(ctx, instr);
4240 break;
4241 case nir_intrinsic_memory_barrier:
4242 emit_waitcnt(ctx->nctx, VM_CNT);
4243 break;
4244 case nir_intrinsic_barrier:
4245 emit_barrier(ctx->nctx);
4246 break;
4247 case nir_intrinsic_var_atomic_add:
4248 case nir_intrinsic_var_atomic_imin:
4249 case nir_intrinsic_var_atomic_umin:
4250 case nir_intrinsic_var_atomic_imax:
4251 case nir_intrinsic_var_atomic_umax:
4252 case nir_intrinsic_var_atomic_and:
4253 case nir_intrinsic_var_atomic_or:
4254 case nir_intrinsic_var_atomic_xor:
4255 case nir_intrinsic_var_atomic_exchange:
4256 case nir_intrinsic_var_atomic_comp_swap:
4257 result = visit_var_atomic(ctx->nctx, instr);
4258 break;
4259 case nir_intrinsic_interp_var_at_centroid:
4260 case nir_intrinsic_interp_var_at_sample:
4261 case nir_intrinsic_interp_var_at_offset:
4262 result = visit_interp(ctx->nctx, instr);
4263 break;
4264 case nir_intrinsic_emit_vertex:
4265 visit_emit_vertex(ctx->nctx, instr);
4266 break;
4267 case nir_intrinsic_end_primitive:
4268 visit_end_primitive(ctx->nctx, instr);
4269 break;
4270 case nir_intrinsic_load_tess_coord:
4271 result = visit_load_tess_coord(ctx->nctx, instr);
4272 break;
4273 case nir_intrinsic_load_patch_vertices_in:
4274 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4275 break;
4276 default:
4277 fprintf(stderr, "Unknown intrinsic: ");
4278 nir_print_instr(&instr->instr, stderr);
4279 fprintf(stderr, "\n");
4280 break;
4281 }
4282 if (result) {
4283 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4284 }
4285 }
4286
4287 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4288 LLVMValueRef buffer, bool write)
4289 {
4290 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4291
4292 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4293 ctx->shader_info->fs.writes_memory = true;
4294
4295 return buffer;
4296 }
4297
4298 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4299 unsigned descriptor_set,
4300 unsigned base_index,
4301 unsigned constant_index,
4302 LLVMValueRef index,
4303 enum ac_descriptor_type desc_type,
4304 bool image, bool write)
4305 {
4306 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4307 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4308 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4309 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4310 unsigned offset = binding->offset;
4311 unsigned stride = binding->size;
4312 unsigned type_size;
4313 LLVMBuilderRef builder = ctx->builder;
4314 LLVMTypeRef type;
4315
4316 assert(base_index < layout->binding_count);
4317
4318 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4319 ctx->shader_info->fs.writes_memory = true;
4320
4321 switch (desc_type) {
4322 case AC_DESC_IMAGE:
4323 type = ctx->v8i32;
4324 type_size = 32;
4325 break;
4326 case AC_DESC_FMASK:
4327 type = ctx->v8i32;
4328 offset += 32;
4329 type_size = 32;
4330 break;
4331 case AC_DESC_SAMPLER:
4332 type = ctx->v4i32;
4333 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4334 offset += 64;
4335
4336 type_size = 16;
4337 break;
4338 case AC_DESC_BUFFER:
4339 type = ctx->v4i32;
4340 type_size = 16;
4341 break;
4342 default:
4343 unreachable("invalid desc_type\n");
4344 }
4345
4346 offset += constant_index * stride;
4347
4348 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4349 (!index || binding->immutable_samplers_equal)) {
4350 if (binding->immutable_samplers_equal)
4351 constant_index = 0;
4352
4353 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4354
4355 LLVMValueRef constants[] = {
4356 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4357 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4358 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4359 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4360 };
4361 return ac_build_gather_values(&ctx->ac, constants, 4);
4362 }
4363
4364 assert(stride % type_size == 0);
4365
4366 if (!index)
4367 index = ctx->ac.i32_0;
4368
4369 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4370
4371 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4372 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4373
4374 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4375 }
4376
4377 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4378 const nir_deref_var *deref,
4379 enum ac_descriptor_type desc_type,
4380 bool image, bool write)
4381 {
4382 LLVMValueRef index = NULL;
4383 unsigned constant_index = 0;
4384 const nir_deref *tail = &deref->deref;
4385
4386 while (tail->child) {
4387 const nir_deref_array *child = nir_deref_as_array(tail->child);
4388 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4389
4390 if (!array_size)
4391 array_size = 1;
4392
4393 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4394
4395 if (child->deref_array_type == nir_deref_array_type_indirect) {
4396 LLVMValueRef indirect = get_src(ctx, child->indirect);
4397
4398 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4399 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4400
4401 if (!index)
4402 index = indirect;
4403 else
4404 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4405 }
4406
4407 constant_index += child->base_offset * array_size;
4408
4409 tail = &child->deref;
4410 }
4411
4412 return ctx->abi->load_sampler_desc(ctx->abi,
4413 deref->var->data.descriptor_set,
4414 deref->var->data.binding,
4415 constant_index, index,
4416 desc_type, image, write);
4417 }
4418
4419 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4420 struct ac_image_args *args,
4421 const nir_tex_instr *instr,
4422 nir_texop op,
4423 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4424 LLVMValueRef *param, unsigned count,
4425 unsigned dmask)
4426 {
4427 unsigned is_rect = 0;
4428 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4429
4430 if (op == nir_texop_lod)
4431 da = false;
4432 /* Pad to power of two vector */
4433 while (count < util_next_power_of_two(count))
4434 param[count++] = LLVMGetUndef(ctx->i32);
4435
4436 if (count > 1)
4437 args->addr = ac_build_gather_values(ctx, param, count);
4438 else
4439 args->addr = param[0];
4440
4441 args->resource = res_ptr;
4442 args->sampler = samp_ptr;
4443
4444 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4445 args->addr = param[0];
4446 return;
4447 }
4448
4449 args->dmask = dmask;
4450 args->unorm = is_rect;
4451 args->da = da;
4452 }
4453
4454 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4455 *
4456 * SI-CI:
4457 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4458 * filtering manually. The driver sets img7 to a mask clearing
4459 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4460 * s_and_b32 samp0, samp0, img7
4461 *
4462 * VI:
4463 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4464 */
4465 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4466 LLVMValueRef res, LLVMValueRef samp)
4467 {
4468 LLVMBuilderRef builder = ctx->ac.builder;
4469 LLVMValueRef img7, samp0;
4470
4471 if (ctx->ac.chip_class >= VI)
4472 return samp;
4473
4474 img7 = LLVMBuildExtractElement(builder, res,
4475 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4476 samp0 = LLVMBuildExtractElement(builder, samp,
4477 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4478 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4479 return LLVMBuildInsertElement(builder, samp, samp0,
4480 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4481 }
4482
4483 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4484 nir_tex_instr *instr,
4485 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4486 LLVMValueRef *fmask_ptr)
4487 {
4488 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4489 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4490 else
4491 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4492 if (samp_ptr) {
4493 if (instr->sampler)
4494 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4495 else
4496 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4497 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4498 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4499 }
4500 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4501 instr->op == nir_texop_samples_identical))
4502 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4503 }
4504
4505 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4506 LLVMValueRef coord)
4507 {
4508 coord = ac_to_float(ctx, coord);
4509 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4510 coord = ac_to_integer(ctx, coord);
4511 return coord;
4512 }
4513
4514 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4515 {
4516 LLVMValueRef result = NULL;
4517 struct ac_image_args args = { 0 };
4518 unsigned dmask = 0xf;
4519 LLVMValueRef address[16];
4520 LLVMValueRef coords[5];
4521 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4522 LLVMValueRef bias = NULL, offsets = NULL;
4523 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4524 LLVMValueRef ddx = NULL, ddy = NULL;
4525 LLVMValueRef derivs[6];
4526 unsigned chan, count = 0;
4527 unsigned const_src = 0, num_deriv_comp = 0;
4528 bool lod_is_zero = false;
4529
4530 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4531
4532 for (unsigned i = 0; i < instr->num_srcs; i++) {
4533 switch (instr->src[i].src_type) {
4534 case nir_tex_src_coord:
4535 coord = get_src(ctx, instr->src[i].src);
4536 break;
4537 case nir_tex_src_projector:
4538 break;
4539 case nir_tex_src_comparator:
4540 comparator = get_src(ctx, instr->src[i].src);
4541 break;
4542 case nir_tex_src_offset:
4543 offsets = get_src(ctx, instr->src[i].src);
4544 const_src = i;
4545 break;
4546 case nir_tex_src_bias:
4547 bias = get_src(ctx, instr->src[i].src);
4548 break;
4549 case nir_tex_src_lod: {
4550 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4551
4552 if (val && val->i32[0] == 0)
4553 lod_is_zero = true;
4554 lod = get_src(ctx, instr->src[i].src);
4555 break;
4556 }
4557 case nir_tex_src_ms_index:
4558 sample_index = get_src(ctx, instr->src[i].src);
4559 break;
4560 case nir_tex_src_ms_mcs:
4561 break;
4562 case nir_tex_src_ddx:
4563 ddx = get_src(ctx, instr->src[i].src);
4564 num_deriv_comp = instr->src[i].src.ssa->num_components;
4565 break;
4566 case nir_tex_src_ddy:
4567 ddy = get_src(ctx, instr->src[i].src);
4568 break;
4569 case nir_tex_src_texture_offset:
4570 case nir_tex_src_sampler_offset:
4571 case nir_tex_src_plane:
4572 default:
4573 break;
4574 }
4575 }
4576
4577 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4578 result = get_buffer_size(ctx, res_ptr, true);
4579 goto write_result;
4580 }
4581
4582 if (instr->op == nir_texop_texture_samples) {
4583 LLVMValueRef res, samples, is_msaa;
4584 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4585 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4586 LLVMConstInt(ctx->ac.i32, 3, false), "");
4587 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4588 LLVMConstInt(ctx->ac.i32, 28, false), "");
4589 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4590 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4591 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4592 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4593
4594 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4595 LLVMConstInt(ctx->ac.i32, 16, false), "");
4596 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4597 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4598 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4599 samples, "");
4600 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4601 ctx->ac.i32_1, "");
4602 result = samples;
4603 goto write_result;
4604 }
4605
4606 if (coord)
4607 for (chan = 0; chan < instr->coord_components; chan++)
4608 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4609
4610 if (offsets && instr->op != nir_texop_txf) {
4611 LLVMValueRef offset[3], pack;
4612 for (chan = 0; chan < 3; ++chan)
4613 offset[chan] = ctx->ac.i32_0;
4614
4615 args.offset = true;
4616 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4617 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4618 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4619 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4620 if (chan)
4621 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4622 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4623 }
4624 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4625 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4626 address[count++] = pack;
4627
4628 }
4629 /* pack LOD bias value */
4630 if (instr->op == nir_texop_txb && bias) {
4631 address[count++] = bias;
4632 }
4633
4634 /* Pack depth comparison value */
4635 if (instr->is_shadow && comparator) {
4636 LLVMValueRef z = ac_to_float(&ctx->ac,
4637 llvm_extract_elem(&ctx->ac, comparator, 0));
4638
4639 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4640 * so the depth comparison value isn't clamped for Z16 and
4641 * Z24 anymore. Do it manually here.
4642 *
4643 * It's unnecessary if the original texture format was
4644 * Z32_FLOAT, but we don't know that here.
4645 */
4646 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4647 z = ac_build_clamp(&ctx->ac, z);
4648
4649 address[count++] = z;
4650 }
4651
4652 /* pack derivatives */
4653 if (ddx || ddy) {
4654 int num_src_deriv_channels, num_dest_deriv_channels;
4655 switch (instr->sampler_dim) {
4656 case GLSL_SAMPLER_DIM_3D:
4657 case GLSL_SAMPLER_DIM_CUBE:
4658 num_deriv_comp = 3;
4659 num_src_deriv_channels = 3;
4660 num_dest_deriv_channels = 3;
4661 break;
4662 case GLSL_SAMPLER_DIM_2D:
4663 default:
4664 num_src_deriv_channels = 2;
4665 num_dest_deriv_channels = 2;
4666 num_deriv_comp = 2;
4667 break;
4668 case GLSL_SAMPLER_DIM_1D:
4669 num_src_deriv_channels = 1;
4670 if (ctx->ac.chip_class >= GFX9) {
4671 num_dest_deriv_channels = 2;
4672 num_deriv_comp = 2;
4673 } else {
4674 num_dest_deriv_channels = 1;
4675 num_deriv_comp = 1;
4676 }
4677 break;
4678 }
4679
4680 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4681 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4682 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4683 }
4684 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4685 derivs[i] = ctx->ac.f32_0;
4686 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4687 }
4688 }
4689
4690 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4691 for (chan = 0; chan < instr->coord_components; chan++)
4692 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4693 if (instr->coord_components == 3)
4694 coords[3] = LLVMGetUndef(ctx->ac.f32);
4695 ac_prepare_cube_coords(&ctx->ac,
4696 instr->op == nir_texop_txd, instr->is_array,
4697 instr->op == nir_texop_lod, coords, derivs);
4698 if (num_deriv_comp)
4699 num_deriv_comp--;
4700 }
4701
4702 if (ddx || ddy) {
4703 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4704 address[count++] = derivs[i];
4705 }
4706
4707 /* Pack texture coordinates */
4708 if (coord) {
4709 address[count++] = coords[0];
4710 if (instr->coord_components > 1) {
4711 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4712 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4713 }
4714 address[count++] = coords[1];
4715 }
4716 if (instr->coord_components > 2) {
4717 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4718 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4719 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4720 instr->op != nir_texop_txf) {
4721 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4722 }
4723 address[count++] = coords[2];
4724 }
4725
4726 if (ctx->ac.chip_class >= GFX9) {
4727 LLVMValueRef filler;
4728 if (instr->op == nir_texop_txf)
4729 filler = ctx->ac.i32_0;
4730 else
4731 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4732
4733 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4734 /* No nir_texop_lod, because it does not take a slice
4735 * even with array textures. */
4736 if (instr->is_array && instr->op != nir_texop_lod ) {
4737 address[count] = address[count - 1];
4738 address[count - 1] = filler;
4739 count++;
4740 } else
4741 address[count++] = filler;
4742 }
4743 }
4744 }
4745
4746 /* Pack LOD */
4747 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4748 instr->op == nir_texop_txf)) {
4749 address[count++] = lod;
4750 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4751 address[count++] = sample_index;
4752 } else if(instr->op == nir_texop_txs) {
4753 count = 0;
4754 if (lod)
4755 address[count++] = lod;
4756 else
4757 address[count++] = ctx->ac.i32_0;
4758 }
4759
4760 for (chan = 0; chan < count; chan++) {
4761 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4762 address[chan], ctx->ac.i32, "");
4763 }
4764
4765 if (instr->op == nir_texop_samples_identical) {
4766 LLVMValueRef txf_address[4];
4767 struct ac_image_args txf_args = { 0 };
4768 unsigned txf_count = count;
4769 memcpy(txf_address, address, sizeof(txf_address));
4770
4771 if (!instr->is_array)
4772 txf_address[2] = ctx->ac.i32_0;
4773 txf_address[3] = ctx->ac.i32_0;
4774
4775 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4776 fmask_ptr, NULL,
4777 txf_address, txf_count, 0xf);
4778
4779 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4780
4781 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4782 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4783 goto write_result;
4784 }
4785
4786 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4787 instr->op != nir_texop_txs) {
4788 unsigned sample_chan = instr->is_array ? 3 : 2;
4789 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4790 address[0],
4791 address[1],
4792 instr->is_array ? address[2] : NULL,
4793 address[sample_chan],
4794 fmask_ptr);
4795 }
4796
4797 if (offsets && instr->op == nir_texop_txf) {
4798 nir_const_value *const_offset =
4799 nir_src_as_const_value(instr->src[const_src].src);
4800 int num_offsets = instr->src[const_src].src.ssa->num_components;
4801 assert(const_offset);
4802 num_offsets = MIN2(num_offsets, instr->coord_components);
4803 if (num_offsets > 2)
4804 address[2] = LLVMBuildAdd(ctx->ac.builder,
4805 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4806 if (num_offsets > 1)
4807 address[1] = LLVMBuildAdd(ctx->ac.builder,
4808 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4809 address[0] = LLVMBuildAdd(ctx->ac.builder,
4810 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4811
4812 }
4813
4814 /* TODO TG4 support */
4815 if (instr->op == nir_texop_tg4) {
4816 if (instr->is_shadow)
4817 dmask = 1;
4818 else
4819 dmask = 1 << instr->component;
4820 }
4821 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4822 res_ptr, samp_ptr, address, count, dmask);
4823
4824 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4825
4826 if (instr->op == nir_texop_query_levels)
4827 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4828 else if (instr->is_shadow && instr->is_new_style_shadow &&
4829 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4830 instr->op != nir_texop_tg4)
4831 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4832 else if (instr->op == nir_texop_txs &&
4833 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4834 instr->is_array) {
4835 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4836 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4837 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4838 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4839 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4840 } else if (ctx->ac.chip_class >= GFX9 &&
4841 instr->op == nir_texop_txs &&
4842 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4843 instr->is_array) {
4844 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4845 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4846 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4847 ctx->ac.i32_1, "");
4848 } else if (instr->dest.ssa.num_components != 4)
4849 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4850
4851 write_result:
4852 if (result) {
4853 assert(instr->dest.is_ssa);
4854 result = ac_to_integer(&ctx->ac, result);
4855 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4856 }
4857 }
4858
4859
4860 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4861 {
4862 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4863 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4864
4865 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4866 _mesa_hash_table_insert(ctx->phis, instr, result);
4867 }
4868
4869 static void visit_post_phi(struct ac_nir_context *ctx,
4870 nir_phi_instr *instr,
4871 LLVMValueRef llvm_phi)
4872 {
4873 nir_foreach_phi_src(src, instr) {
4874 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4875 LLVMValueRef llvm_src = get_src(ctx, src->src);
4876
4877 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4878 }
4879 }
4880
4881 static void phi_post_pass(struct ac_nir_context *ctx)
4882 {
4883 struct hash_entry *entry;
4884 hash_table_foreach(ctx->phis, entry) {
4885 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4886 (LLVMValueRef)entry->data);
4887 }
4888 }
4889
4890
4891 static void visit_ssa_undef(struct ac_nir_context *ctx,
4892 const nir_ssa_undef_instr *instr)
4893 {
4894 unsigned num_components = instr->def.num_components;
4895 LLVMValueRef undef;
4896
4897 if (num_components == 1)
4898 undef = LLVMGetUndef(ctx->ac.i32);
4899 else {
4900 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4901 }
4902 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4903 }
4904
4905 static void visit_jump(struct ac_nir_context *ctx,
4906 const nir_jump_instr *instr)
4907 {
4908 switch (instr->type) {
4909 case nir_jump_break:
4910 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4911 LLVMClearInsertionPosition(ctx->ac.builder);
4912 break;
4913 case nir_jump_continue:
4914 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4915 LLVMClearInsertionPosition(ctx->ac.builder);
4916 break;
4917 default:
4918 fprintf(stderr, "Unknown NIR jump instr: ");
4919 nir_print_instr(&instr->instr, stderr);
4920 fprintf(stderr, "\n");
4921 abort();
4922 }
4923 }
4924
4925 static void visit_cf_list(struct ac_nir_context *ctx,
4926 struct exec_list *list);
4927
4928 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4929 {
4930 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4931 nir_foreach_instr(instr, block)
4932 {
4933 switch (instr->type) {
4934 case nir_instr_type_alu:
4935 visit_alu(ctx, nir_instr_as_alu(instr));
4936 break;
4937 case nir_instr_type_load_const:
4938 visit_load_const(ctx, nir_instr_as_load_const(instr));
4939 break;
4940 case nir_instr_type_intrinsic:
4941 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4942 break;
4943 case nir_instr_type_tex:
4944 visit_tex(ctx, nir_instr_as_tex(instr));
4945 break;
4946 case nir_instr_type_phi:
4947 visit_phi(ctx, nir_instr_as_phi(instr));
4948 break;
4949 case nir_instr_type_ssa_undef:
4950 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4951 break;
4952 case nir_instr_type_jump:
4953 visit_jump(ctx, nir_instr_as_jump(instr));
4954 break;
4955 default:
4956 fprintf(stderr, "Unknown NIR instr type: ");
4957 nir_print_instr(instr, stderr);
4958 fprintf(stderr, "\n");
4959 abort();
4960 }
4961 }
4962
4963 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4964 }
4965
4966 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4967 {
4968 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4969
4970 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4971 LLVMBasicBlockRef merge_block =
4972 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4973 LLVMBasicBlockRef if_block =
4974 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4975 LLVMBasicBlockRef else_block = merge_block;
4976 if (!exec_list_is_empty(&if_stmt->else_list))
4977 else_block = LLVMAppendBasicBlockInContext(
4978 ctx->ac.context, fn, "");
4979
4980 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4981 LLVMConstInt(ctx->ac.i32, 0, false), "");
4982 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4983
4984 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4985 visit_cf_list(ctx, &if_stmt->then_list);
4986 if (LLVMGetInsertBlock(ctx->ac.builder))
4987 LLVMBuildBr(ctx->ac.builder, merge_block);
4988
4989 if (!exec_list_is_empty(&if_stmt->else_list)) {
4990 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4991 visit_cf_list(ctx, &if_stmt->else_list);
4992 if (LLVMGetInsertBlock(ctx->ac.builder))
4993 LLVMBuildBr(ctx->ac.builder, merge_block);
4994 }
4995
4996 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4997 }
4998
4999 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5000 {
5001 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5002 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5003 LLVMBasicBlockRef break_parent = ctx->break_block;
5004
5005 ctx->continue_block =
5006 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5007 ctx->break_block =
5008 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5009
5010 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5011 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5012 visit_cf_list(ctx, &loop->body);
5013
5014 if (LLVMGetInsertBlock(ctx->ac.builder))
5015 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5016 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5017
5018 ctx->continue_block = continue_parent;
5019 ctx->break_block = break_parent;
5020 }
5021
5022 static void visit_cf_list(struct ac_nir_context *ctx,
5023 struct exec_list *list)
5024 {
5025 foreach_list_typed(nir_cf_node, node, node, list)
5026 {
5027 switch (node->type) {
5028 case nir_cf_node_block:
5029 visit_block(ctx, nir_cf_node_as_block(node));
5030 break;
5031
5032 case nir_cf_node_if:
5033 visit_if(ctx, nir_cf_node_as_if(node));
5034 break;
5035
5036 case nir_cf_node_loop:
5037 visit_loop(ctx, nir_cf_node_as_loop(node));
5038 break;
5039
5040 default:
5041 assert(0);
5042 }
5043 }
5044 }
5045
5046 static void
5047 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5048 struct nir_variable *variable)
5049 {
5050 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5051 LLVMValueRef t_offset;
5052 LLVMValueRef t_list;
5053 LLVMValueRef input;
5054 LLVMValueRef buffer_index;
5055 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5056 int idx = variable->data.location;
5057 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5058
5059 variable->data.driver_location = idx * 4;
5060
5061 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5062 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5063 ctx->abi.start_instance, "");
5064 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5065 ctx->shader_info->vs.vgpr_comp_cnt);
5066 } else
5067 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5068 ctx->abi.base_vertex, "");
5069
5070 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5071 t_offset = LLVMConstInt(ctx->i32, index + i, false);
5072
5073 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5074
5075 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5076 buffer_index,
5077 LLVMConstInt(ctx->i32, 0, false),
5078 true);
5079
5080 for (unsigned chan = 0; chan < 4; chan++) {
5081 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
5082 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5083 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5084 input, llvm_chan, ""));
5085 }
5086 }
5087 }
5088
5089 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5090 unsigned attr,
5091 LLVMValueRef interp_param,
5092 LLVMValueRef prim_mask,
5093 LLVMValueRef result[4])
5094 {
5095 LLVMValueRef attr_number;
5096 unsigned chan;
5097 LLVMValueRef i, j;
5098 bool interp = interp_param != NULL;
5099
5100 attr_number = LLVMConstInt(ctx->i32, attr, false);
5101
5102 /* fs.constant returns the param from the middle vertex, so it's not
5103 * really useful for flat shading. It's meant to be used for custom
5104 * interpolation (but the intrinsic can't fetch from the other two
5105 * vertices).
5106 *
5107 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5108 * to do the right thing. The only reason we use fs.constant is that
5109 * fs.interp cannot be used on integers, because they can be equal
5110 * to NaN.
5111 */
5112 if (interp) {
5113 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5114 LLVMVectorType(ctx->f32, 2), "");
5115
5116 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5117 ctx->ac.i32_0, "");
5118 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5119 ctx->ac.i32_1, "");
5120 }
5121
5122 for (chan = 0; chan < 4; chan++) {
5123 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
5124
5125 if (interp) {
5126 result[chan] = ac_build_fs_interp(&ctx->ac,
5127 llvm_chan,
5128 attr_number,
5129 prim_mask, i, j);
5130 } else {
5131 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5132 LLVMConstInt(ctx->i32, 2, false),
5133 llvm_chan,
5134 attr_number,
5135 prim_mask);
5136 }
5137 }
5138 }
5139
5140 static void
5141 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5142 struct nir_variable *variable)
5143 {
5144 int idx = variable->data.location;
5145 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5146 LLVMValueRef interp;
5147
5148 variable->data.driver_location = idx * 4;
5149 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5150
5151 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5152 unsigned interp_type;
5153 if (variable->data.sample) {
5154 interp_type = INTERP_SAMPLE;
5155 ctx->shader_info->info.ps.force_persample = true;
5156 } else if (variable->data.centroid)
5157 interp_type = INTERP_CENTROID;
5158 else
5159 interp_type = INTERP_CENTER;
5160
5161 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5162 } else
5163 interp = NULL;
5164
5165 for (unsigned i = 0; i < attrib_count; ++i)
5166 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5167
5168 }
5169
5170 static void
5171 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5172 struct nir_shader *nir) {
5173 nir_foreach_variable(variable, &nir->inputs)
5174 handle_vs_input_decl(ctx, variable);
5175 }
5176
5177 static void
5178 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5179 struct nir_shader *nir)
5180 {
5181 if (!ctx->options->key.fs.multisample)
5182 return;
5183
5184 bool uses_center = false;
5185 bool uses_centroid = false;
5186 nir_foreach_variable(variable, &nir->inputs) {
5187 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5188 variable->data.sample)
5189 continue;
5190
5191 if (variable->data.centroid)
5192 uses_centroid = true;
5193 else
5194 uses_center = true;
5195 }
5196
5197 if (uses_center && uses_centroid) {
5198 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5199 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5200 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5201 }
5202 }
5203
5204 static void
5205 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5206 struct nir_shader *nir)
5207 {
5208 prepare_interp_optimize(ctx, nir);
5209
5210 nir_foreach_variable(variable, &nir->inputs)
5211 handle_fs_input_decl(ctx, variable);
5212
5213 unsigned index = 0;
5214
5215 if (ctx->shader_info->info.ps.uses_input_attachments ||
5216 ctx->shader_info->info.needs_multiview_view_index)
5217 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5218
5219 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5220 LLVMValueRef interp_param;
5221 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5222
5223 if (!(ctx->input_mask & (1ull << i)))
5224 continue;
5225
5226 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5227 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5228 interp_param = *inputs;
5229 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5230 inputs);
5231
5232 if (!interp_param)
5233 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5234 ++index;
5235 } else if (i == VARYING_SLOT_POS) {
5236 for(int i = 0; i < 3; ++i)
5237 inputs[i] = ctx->abi.frag_pos[i];
5238
5239 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5240 ctx->abi.frag_pos[3]);
5241 }
5242 }
5243 ctx->shader_info->fs.num_interp = index;
5244 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5245 ctx->shader_info->fs.has_pcoord = true;
5246 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5247 ctx->shader_info->fs.prim_id_input = true;
5248 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5249 ctx->shader_info->fs.layer_input = true;
5250 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5251
5252 if (ctx->shader_info->info.needs_multiview_view_index)
5253 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5254 }
5255
5256 static LLVMValueRef
5257 ac_build_alloca(struct ac_llvm_context *ac,
5258 LLVMTypeRef type,
5259 const char *name)
5260 {
5261 LLVMBuilderRef builder = ac->builder;
5262 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5263 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5264 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5265 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5266 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5267 LLVMValueRef res;
5268
5269 if (first_instr) {
5270 LLVMPositionBuilderBefore(first_builder, first_instr);
5271 } else {
5272 LLVMPositionBuilderAtEnd(first_builder, first_block);
5273 }
5274
5275 res = LLVMBuildAlloca(first_builder, type, name);
5276 LLVMBuildStore(builder, LLVMConstNull(type), res);
5277
5278 LLVMDisposeBuilder(first_builder);
5279
5280 return res;
5281 }
5282
5283 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5284 LLVMTypeRef type,
5285 const char *name)
5286 {
5287 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5288 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5289 return ptr;
5290 }
5291
5292 static void
5293 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5294 struct nir_variable *variable,
5295 struct nir_shader *shader,
5296 gl_shader_stage stage)
5297 {
5298 int idx = variable->data.location + variable->data.index;
5299 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5300 uint64_t mask_attribs;
5301
5302 variable->data.driver_location = idx * 4;
5303
5304 /* tess ctrl has it's own load/store paths for outputs */
5305 if (stage == MESA_SHADER_TESS_CTRL)
5306 return;
5307
5308 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5309 if (stage == MESA_SHADER_VERTEX ||
5310 stage == MESA_SHADER_TESS_EVAL ||
5311 stage == MESA_SHADER_GEOMETRY) {
5312 if (idx == VARYING_SLOT_CLIP_DIST0) {
5313 int length = shader->info.clip_distance_array_size +
5314 shader->info.cull_distance_array_size;
5315 if (stage == MESA_SHADER_VERTEX) {
5316 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5317 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5318 }
5319 if (stage == MESA_SHADER_TESS_EVAL) {
5320 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5321 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5322 }
5323
5324 if (length > 4)
5325 attrib_count = 2;
5326 else
5327 attrib_count = 1;
5328 mask_attribs = 1ull << idx;
5329 }
5330 }
5331
5332 ctx->output_mask |= mask_attribs;
5333 }
5334
5335 static void
5336 handle_shader_output_decl(struct ac_nir_context *ctx,
5337 struct nir_shader *nir,
5338 struct nir_variable *variable)
5339 {
5340 unsigned output_loc = variable->data.driver_location / 4;
5341 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5342
5343 /* tess ctrl has it's own load/store paths for outputs */
5344 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5345 return;
5346
5347 if (ctx->stage == MESA_SHADER_VERTEX ||
5348 ctx->stage == MESA_SHADER_TESS_EVAL ||
5349 ctx->stage == MESA_SHADER_GEOMETRY) {
5350 int idx = variable->data.location + variable->data.index;
5351 if (idx == VARYING_SLOT_CLIP_DIST0) {
5352 int length = nir->info.clip_distance_array_size +
5353 nir->info.cull_distance_array_size;
5354
5355 if (length > 4)
5356 attrib_count = 2;
5357 else
5358 attrib_count = 1;
5359 }
5360 }
5361
5362 for (unsigned i = 0; i < attrib_count; ++i) {
5363 for (unsigned chan = 0; chan < 4; chan++) {
5364 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5365 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5366 }
5367 }
5368 }
5369
5370 static LLVMTypeRef
5371 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5372 enum glsl_base_type type)
5373 {
5374 switch (type) {
5375 case GLSL_TYPE_INT:
5376 case GLSL_TYPE_UINT:
5377 case GLSL_TYPE_BOOL:
5378 case GLSL_TYPE_SUBROUTINE:
5379 return ctx->i32;
5380 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5381 return ctx->f32;
5382 case GLSL_TYPE_INT64:
5383 case GLSL_TYPE_UINT64:
5384 return ctx->i64;
5385 case GLSL_TYPE_DOUBLE:
5386 return ctx->f64;
5387 default:
5388 unreachable("unknown GLSL type");
5389 }
5390 }
5391
5392 static LLVMTypeRef
5393 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5394 const struct glsl_type *type)
5395 {
5396 if (glsl_type_is_scalar(type)) {
5397 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5398 }
5399
5400 if (glsl_type_is_vector(type)) {
5401 return LLVMVectorType(
5402 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5403 glsl_get_vector_elements(type));
5404 }
5405
5406 if (glsl_type_is_matrix(type)) {
5407 return LLVMArrayType(
5408 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5409 glsl_get_matrix_columns(type));
5410 }
5411
5412 if (glsl_type_is_array(type)) {
5413 return LLVMArrayType(
5414 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5415 glsl_get_length(type));
5416 }
5417
5418 assert(glsl_type_is_struct(type));
5419
5420 LLVMTypeRef member_types[glsl_get_length(type)];
5421
5422 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5423 member_types[i] =
5424 glsl_to_llvm_type(ctx,
5425 glsl_get_struct_field(type, i));
5426 }
5427
5428 return LLVMStructTypeInContext(ctx->context, member_types,
5429 glsl_get_length(type), false);
5430 }
5431
5432 static void
5433 setup_locals(struct ac_nir_context *ctx,
5434 struct nir_function *func)
5435 {
5436 int i, j;
5437 ctx->num_locals = 0;
5438 nir_foreach_variable(variable, &func->impl->locals) {
5439 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5440 variable->data.driver_location = ctx->num_locals * 4;
5441 ctx->num_locals += attrib_count;
5442 }
5443 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5444 if (!ctx->locals)
5445 return;
5446
5447 for (i = 0; i < ctx->num_locals; i++) {
5448 for (j = 0; j < 4; j++) {
5449 ctx->locals[i * 4 + j] =
5450 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5451 }
5452 }
5453 }
5454
5455 static void
5456 setup_shared(struct ac_nir_context *ctx,
5457 struct nir_shader *nir)
5458 {
5459 nir_foreach_variable(variable, &nir->shared) {
5460 LLVMValueRef shared =
5461 LLVMAddGlobalInAddressSpace(
5462 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5463 variable->name ? variable->name : "",
5464 LOCAL_ADDR_SPACE);
5465 _mesa_hash_table_insert(ctx->vars, variable, shared);
5466 }
5467 }
5468
5469 static LLVMValueRef
5470 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5471 {
5472 v = ac_to_float(ctx, v);
5473 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5474 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5475 }
5476
5477
5478 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5479 LLVMValueRef src0, LLVMValueRef src1)
5480 {
5481 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5482 LLVMValueRef comp[2];
5483
5484 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5485 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5486 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5487 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5488 }
5489
5490 /* Initialize arguments for the shader export intrinsic */
5491 static void
5492 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5493 LLVMValueRef *values,
5494 unsigned target,
5495 struct ac_export_args *args)
5496 {
5497 /* Default is 0xf. Adjusted below depending on the format. */
5498 args->enabled_channels = 0xf;
5499
5500 /* Specify whether the EXEC mask represents the valid mask */
5501 args->valid_mask = 0;
5502
5503 /* Specify whether this is the last export */
5504 args->done = 0;
5505
5506 /* Specify the target we are exporting */
5507 args->target = target;
5508
5509 args->compr = false;
5510 args->out[0] = LLVMGetUndef(ctx->f32);
5511 args->out[1] = LLVMGetUndef(ctx->f32);
5512 args->out[2] = LLVMGetUndef(ctx->f32);
5513 args->out[3] = LLVMGetUndef(ctx->f32);
5514
5515 if (!values)
5516 return;
5517
5518 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5519 LLVMValueRef val[4];
5520 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5521 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5522 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5523 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5524
5525 switch(col_format) {
5526 case V_028714_SPI_SHADER_ZERO:
5527 args->enabled_channels = 0; /* writemask */
5528 args->target = V_008DFC_SQ_EXP_NULL;
5529 break;
5530
5531 case V_028714_SPI_SHADER_32_R:
5532 args->enabled_channels = 1;
5533 args->out[0] = values[0];
5534 break;
5535
5536 case V_028714_SPI_SHADER_32_GR:
5537 args->enabled_channels = 0x3;
5538 args->out[0] = values[0];
5539 args->out[1] = values[1];
5540 break;
5541
5542 case V_028714_SPI_SHADER_32_AR:
5543 args->enabled_channels = 0x9;
5544 args->out[0] = values[0];
5545 args->out[3] = values[3];
5546 break;
5547
5548 case V_028714_SPI_SHADER_FP16_ABGR:
5549 args->compr = 1;
5550
5551 for (unsigned chan = 0; chan < 2; chan++) {
5552 LLVMValueRef pack_args[2] = {
5553 values[2 * chan],
5554 values[2 * chan + 1]
5555 };
5556 LLVMValueRef packed;
5557
5558 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5559 args->out[chan] = packed;
5560 }
5561 break;
5562
5563 case V_028714_SPI_SHADER_UNORM16_ABGR:
5564 for (unsigned chan = 0; chan < 4; chan++) {
5565 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5566 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5567 LLVMConstReal(ctx->f32, 65535), "");
5568 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5569 LLVMConstReal(ctx->f32, 0.5), "");
5570 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5571 ctx->i32, "");
5572 }
5573
5574 args->compr = 1;
5575 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5576 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5577 break;
5578
5579 case V_028714_SPI_SHADER_SNORM16_ABGR:
5580 for (unsigned chan = 0; chan < 4; chan++) {
5581 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5582 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5583 LLVMConstReal(ctx->f32, 32767), "");
5584
5585 /* If positive, add 0.5, else add -0.5. */
5586 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5587 LLVMBuildSelect(ctx->builder,
5588 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5589 val[chan], ctx->ac.f32_0, ""),
5590 LLVMConstReal(ctx->f32, 0.5),
5591 LLVMConstReal(ctx->f32, -0.5), ""), "");
5592 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5593 }
5594
5595 args->compr = 1;
5596 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5597 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5598 break;
5599
5600 case V_028714_SPI_SHADER_UINT16_ABGR: {
5601 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5602 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5603 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
5604
5605 for (unsigned chan = 0; chan < 4; chan++) {
5606 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5607 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5608 }
5609
5610 args->compr = 1;
5611 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5612 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5613 break;
5614 }
5615
5616 case V_028714_SPI_SHADER_SINT16_ABGR: {
5617 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5618 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5619 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
5620 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5621 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5622 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
5623
5624 /* Clamp. */
5625 for (unsigned chan = 0; chan < 4; chan++) {
5626 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5627 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5628 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5629 }
5630
5631 args->compr = 1;
5632 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5633 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5634 break;
5635 }
5636
5637 default:
5638 case V_028714_SPI_SHADER_32_ABGR:
5639 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5640 break;
5641 }
5642 } else
5643 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5644
5645 for (unsigned i = 0; i < 4; ++i)
5646 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5647 }
5648
5649 static void
5650 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5651 bool export_prim_id,
5652 struct ac_vs_output_info *outinfo)
5653 {
5654 uint32_t param_count = 0;
5655 unsigned target;
5656 unsigned pos_idx, num_pos_exports = 0;
5657 struct ac_export_args args, pos_args[4] = {};
5658 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5659 int i;
5660
5661 if (ctx->options->key.has_multiview_view_index) {
5662 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5663 if(!*tmp_out) {
5664 for(unsigned i = 0; i < 4; ++i)
5665 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5666 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5667 }
5668
5669 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5670 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5671 }
5672
5673 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5674 sizeof(outinfo->vs_output_param_offset));
5675
5676 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5677 LLVMValueRef slots[8];
5678 unsigned j;
5679
5680 if (outinfo->cull_dist_mask)
5681 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5682
5683 i = VARYING_SLOT_CLIP_DIST0;
5684 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5685 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5686 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5687
5688 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5689 slots[i] = LLVMGetUndef(ctx->f32);
5690
5691 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5692 target = V_008DFC_SQ_EXP_POS + 3;
5693 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5694 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5695 &args, sizeof(args));
5696 }
5697
5698 target = V_008DFC_SQ_EXP_POS + 2;
5699 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5700 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5701 &args, sizeof(args));
5702
5703 }
5704
5705 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5706 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5707 for (unsigned j = 0; j < 4; j++)
5708 pos_values[j] = LLVMBuildLoad(ctx->builder,
5709 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5710 }
5711 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5712
5713 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5714 outinfo->writes_pointsize = true;
5715 psize_value = LLVMBuildLoad(ctx->builder,
5716 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5717 }
5718
5719 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5720 outinfo->writes_layer = true;
5721 layer_value = LLVMBuildLoad(ctx->builder,
5722 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5723 }
5724
5725 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5726 outinfo->writes_viewport_index = true;
5727 viewport_index_value = LLVMBuildLoad(ctx->builder,
5728 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5729 }
5730
5731 if (outinfo->writes_pointsize ||
5732 outinfo->writes_layer ||
5733 outinfo->writes_viewport_index) {
5734 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5735 (outinfo->writes_layer == true ? 4 : 0));
5736 pos_args[1].valid_mask = 0;
5737 pos_args[1].done = 0;
5738 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5739 pos_args[1].compr = 0;
5740 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5741 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5742 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5743 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5744
5745 if (outinfo->writes_pointsize == true)
5746 pos_args[1].out[0] = psize_value;
5747 if (outinfo->writes_layer == true)
5748 pos_args[1].out[2] = layer_value;
5749 if (outinfo->writes_viewport_index == true) {
5750 if (ctx->options->chip_class >= GFX9) {
5751 /* GFX9 has the layer in out.z[10:0] and the viewport
5752 * index in out.z[19:16].
5753 */
5754 LLVMValueRef v = viewport_index_value;
5755 v = ac_to_integer(&ctx->ac, v);
5756 v = LLVMBuildShl(ctx->builder, v,
5757 LLVMConstInt(ctx->i32, 16, false),
5758 "");
5759 v = LLVMBuildOr(ctx->builder, v,
5760 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5761
5762 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5763 pos_args[1].enabled_channels |= 1 << 2;
5764 } else {
5765 pos_args[1].out[3] = viewport_index_value;
5766 pos_args[1].enabled_channels |= 1 << 3;
5767 }
5768 }
5769 }
5770 for (i = 0; i < 4; i++) {
5771 if (pos_args[i].out[0])
5772 num_pos_exports++;
5773 }
5774
5775 pos_idx = 0;
5776 for (i = 0; i < 4; i++) {
5777 if (!pos_args[i].out[0])
5778 continue;
5779
5780 /* Specify the target we are exporting */
5781 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5782 if (pos_idx == num_pos_exports)
5783 pos_args[i].done = 1;
5784 ac_build_export(&ctx->ac, &pos_args[i]);
5785 }
5786
5787 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5788 LLVMValueRef values[4];
5789 if (!(ctx->output_mask & (1ull << i)))
5790 continue;
5791
5792 for (unsigned j = 0; j < 4; j++)
5793 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5794 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5795
5796 if (i == VARYING_SLOT_LAYER) {
5797 target = V_008DFC_SQ_EXP_PARAM + param_count;
5798 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5799 param_count++;
5800 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5801 target = V_008DFC_SQ_EXP_PARAM + param_count;
5802 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5803 param_count++;
5804 } else if (i >= VARYING_SLOT_VAR0) {
5805 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5806 target = V_008DFC_SQ_EXP_PARAM + param_count;
5807 outinfo->vs_output_param_offset[i] = param_count;
5808 param_count++;
5809 } else
5810 continue;
5811
5812 si_llvm_init_export_args(ctx, values, target, &args);
5813
5814 if (target >= V_008DFC_SQ_EXP_POS &&
5815 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5816 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5817 &args, sizeof(args));
5818 } else {
5819 ac_build_export(&ctx->ac, &args);
5820 }
5821 }
5822
5823 if (export_prim_id) {
5824 LLVMValueRef values[4];
5825 target = V_008DFC_SQ_EXP_PARAM + param_count;
5826 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5827 param_count++;
5828
5829 values[0] = ctx->vs_prim_id;
5830 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5831 ctx->shader_info->vs.vgpr_comp_cnt);
5832 for (unsigned j = 1; j < 4; j++)
5833 values[j] = ctx->ac.f32_0;
5834 si_llvm_init_export_args(ctx, values, target, &args);
5835 ac_build_export(&ctx->ac, &args);
5836 outinfo->export_prim_id = true;
5837 }
5838
5839 outinfo->pos_exports = num_pos_exports;
5840 outinfo->param_exports = param_count;
5841 }
5842
5843 static void
5844 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5845 struct ac_es_output_info *outinfo)
5846 {
5847 int j;
5848 uint64_t max_output_written = 0;
5849 LLVMValueRef lds_base = NULL;
5850
5851 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5852 int param_index;
5853 int length = 4;
5854
5855 if (!(ctx->output_mask & (1ull << i)))
5856 continue;
5857
5858 if (i == VARYING_SLOT_CLIP_DIST0)
5859 length = ctx->num_output_clips + ctx->num_output_culls;
5860
5861 param_index = shader_io_get_unique_index(i);
5862
5863 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5864 }
5865
5866 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5867
5868 if (ctx->ac.chip_class >= GFX9) {
5869 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5870 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5871 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5872 LLVMConstInt(ctx->ac.i32, 24, false),
5873 LLVMConstInt(ctx->ac.i32, 4, false), false);
5874 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5875 LLVMBuildMul(ctx->ac.builder, wave_idx,
5876 LLVMConstInt(ctx->i32, 64, false), ""), "");
5877 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5878 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
5879 }
5880
5881 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5882 LLVMValueRef dw_addr;
5883 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5884 int param_index;
5885 int length = 4;
5886
5887 if (!(ctx->output_mask & (1ull << i)))
5888 continue;
5889
5890 if (i == VARYING_SLOT_CLIP_DIST0)
5891 length = ctx->num_output_clips + ctx->num_output_culls;
5892
5893 param_index = shader_io_get_unique_index(i);
5894
5895 if (lds_base) {
5896 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5897 LLVMConstInt(ctx->i32, param_index * 4, false),
5898 "");
5899 }
5900 for (j = 0; j < length; j++) {
5901 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5902 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5903
5904 if (ctx->ac.chip_class >= GFX9) {
5905 ac_lds_store(&ctx->ac, dw_addr,
5906 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5907 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5908 } else {
5909 ac_build_buffer_store_dword(&ctx->ac,
5910 ctx->esgs_ring,
5911 out_val, 1,
5912 NULL, ctx->es2gs_offset,
5913 (4 * param_index + j) * 4,
5914 1, 1, true, true);
5915 }
5916 }
5917 }
5918 }
5919
5920 static void
5921 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5922 {
5923 LLVMValueRef vertex_id = ctx->rel_auto_id;
5924 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5925 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5926 vertex_dw_stride, "");
5927
5928 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5929 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5930 int length = 4;
5931
5932 if (!(ctx->output_mask & (1ull << i)))
5933 continue;
5934
5935 if (i == VARYING_SLOT_CLIP_DIST0)
5936 length = ctx->num_output_clips + ctx->num_output_culls;
5937 int param = shader_io_get_unique_index(i);
5938 mark_tess_output(ctx, false, param);
5939 if (length > 4)
5940 mark_tess_output(ctx, false, param + 1);
5941 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5942 LLVMConstInt(ctx->i32, param * 4, false),
5943 "");
5944 for (unsigned j = 0; j < length; j++) {
5945 ac_lds_store(&ctx->ac, dw_addr,
5946 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5947 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5948 }
5949 }
5950 }
5951
5952 struct ac_build_if_state
5953 {
5954 struct nir_to_llvm_context *ctx;
5955 LLVMValueRef condition;
5956 LLVMBasicBlockRef entry_block;
5957 LLVMBasicBlockRef true_block;
5958 LLVMBasicBlockRef false_block;
5959 LLVMBasicBlockRef merge_block;
5960 };
5961
5962 static LLVMBasicBlockRef
5963 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5964 {
5965 LLVMBasicBlockRef current_block;
5966 LLVMBasicBlockRef next_block;
5967 LLVMBasicBlockRef new_block;
5968
5969 /* get current basic block */
5970 current_block = LLVMGetInsertBlock(ctx->builder);
5971
5972 /* chqeck if there's another block after this one */
5973 next_block = LLVMGetNextBasicBlock(current_block);
5974 if (next_block) {
5975 /* insert the new block before the next block */
5976 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5977 }
5978 else {
5979 /* append new block after current block */
5980 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5981 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5982 }
5983 return new_block;
5984 }
5985
5986 static void
5987 ac_nir_build_if(struct ac_build_if_state *ifthen,
5988 struct nir_to_llvm_context *ctx,
5989 LLVMValueRef condition)
5990 {
5991 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5992
5993 memset(ifthen, 0, sizeof *ifthen);
5994 ifthen->ctx = ctx;
5995 ifthen->condition = condition;
5996 ifthen->entry_block = block;
5997
5998 /* create endif/merge basic block for the phi functions */
5999 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6000
6001 /* create/insert true_block before merge_block */
6002 ifthen->true_block =
6003 LLVMInsertBasicBlockInContext(ctx->context,
6004 ifthen->merge_block,
6005 "if-true-block");
6006
6007 /* successive code goes into the true block */
6008 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6009 }
6010
6011 /**
6012 * End a conditional.
6013 */
6014 static void
6015 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6016 {
6017 LLVMBuilderRef builder = ifthen->ctx->builder;
6018
6019 /* Insert branch to the merge block from current block */
6020 LLVMBuildBr(builder, ifthen->merge_block);
6021
6022 /*
6023 * Now patch in the various branch instructions.
6024 */
6025
6026 /* Insert the conditional branch instruction at the end of entry_block */
6027 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6028 if (ifthen->false_block) {
6029 /* we have an else clause */
6030 LLVMBuildCondBr(builder, ifthen->condition,
6031 ifthen->true_block, ifthen->false_block);
6032 }
6033 else {
6034 /* no else clause */
6035 LLVMBuildCondBr(builder, ifthen->condition,
6036 ifthen->true_block, ifthen->merge_block);
6037 }
6038
6039 /* Resume building code at end of the ifthen->merge_block */
6040 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6041 }
6042
6043 static void
6044 write_tess_factors(struct nir_to_llvm_context *ctx)
6045 {
6046 unsigned stride, outer_comps, inner_comps;
6047 struct ac_build_if_state if_ctx, inner_if_ctx;
6048 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6049 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6050 unsigned tess_inner_index, tess_outer_index;
6051 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6052 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6053 int i;
6054 emit_barrier(ctx);
6055
6056 switch (ctx->options->key.tcs.primitive_mode) {
6057 case GL_ISOLINES:
6058 stride = 2;
6059 outer_comps = 2;
6060 inner_comps = 0;
6061 break;
6062 case GL_TRIANGLES:
6063 stride = 4;
6064 outer_comps = 3;
6065 inner_comps = 1;
6066 break;
6067 case GL_QUADS:
6068 stride = 6;
6069 outer_comps = 4;
6070 inner_comps = 2;
6071 break;
6072 default:
6073 return;
6074 }
6075
6076 ac_nir_build_if(&if_ctx, ctx,
6077 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6078 invocation_id, ctx->ac.i32_0, ""));
6079
6080 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6081 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6082
6083 mark_tess_output(ctx, true, tess_inner_index);
6084 mark_tess_output(ctx, true, tess_outer_index);
6085 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6086 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6087 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
6088 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6089 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
6090
6091 for (i = 0; i < 4; i++) {
6092 inner[i] = LLVMGetUndef(ctx->i32);
6093 outer[i] = LLVMGetUndef(ctx->i32);
6094 }
6095
6096 // LINES reverseal
6097 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6098 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6099 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6100 LLVMConstInt(ctx->i32, 1, false), "");
6101 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6102 } else {
6103 for (i = 0; i < outer_comps; i++) {
6104 outer[i] = out[i] =
6105 ac_lds_load(&ctx->ac, lds_outer);
6106 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6107 LLVMConstInt(ctx->i32, 1, false), "");
6108 }
6109 for (i = 0; i < inner_comps; i++) {
6110 inner[i] = out[outer_comps+i] =
6111 ac_lds_load(&ctx->ac, lds_inner);
6112 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6113 LLVMConstInt(ctx->i32, 1, false), "");
6114 }
6115 }
6116
6117 /* Convert the outputs to vectors for stores. */
6118 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6119 vec1 = NULL;
6120
6121 if (stride > 4)
6122 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6123
6124
6125 buffer = ctx->hs_ring_tess_factor;
6126 tf_base = ctx->tess_factor_offset;
6127 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6128 LLVMConstInt(ctx->i32, 4 * stride, false), "");
6129 unsigned tf_offset = 0;
6130
6131 if (ctx->options->chip_class <= VI) {
6132 ac_nir_build_if(&inner_if_ctx, ctx,
6133 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6134 rel_patch_id, ctx->ac.i32_0, ""));
6135
6136 /* Store the dynamic HS control word. */
6137 ac_build_buffer_store_dword(&ctx->ac, buffer,
6138 LLVMConstInt(ctx->i32, 0x80000000, false),
6139 1, ctx->ac.i32_0, tf_base,
6140 0, 1, 0, true, false);
6141 tf_offset += 4;
6142
6143 ac_nir_build_endif(&inner_if_ctx);
6144 }
6145
6146 /* Store the tessellation factors. */
6147 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6148 MIN2(stride, 4), byteoffset, tf_base,
6149 tf_offset, 1, 0, true, false);
6150 if (vec1)
6151 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6152 stride - 4, byteoffset, tf_base,
6153 16 + tf_offset, 1, 0, true, false);
6154
6155 //store to offchip for TES to read - only if TES reads them
6156 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6157 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6158 LLVMValueRef tf_inner_offset;
6159 unsigned param_outer, param_inner;
6160
6161 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6162 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6163 LLVMConstInt(ctx->i32, param_outer, 0));
6164
6165 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6166 util_next_power_of_two(outer_comps));
6167
6168 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6169 outer_comps, tf_outer_offset,
6170 ctx->oc_lds, 0, 1, 0, true, false);
6171 if (inner_comps) {
6172 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6173 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6174 LLVMConstInt(ctx->i32, param_inner, 0));
6175
6176 inner_vec = inner_comps == 1 ? inner[0] :
6177 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6178 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6179 inner_comps, tf_inner_offset,
6180 ctx->oc_lds, 0, 1, 0, true, false);
6181 }
6182 }
6183 ac_nir_build_endif(&if_ctx);
6184 }
6185
6186 static void
6187 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6188 {
6189 write_tess_factors(ctx);
6190 }
6191
6192 static bool
6193 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6194 LLVMValueRef *color, unsigned param, bool is_last,
6195 struct ac_export_args *args)
6196 {
6197 /* Export */
6198 si_llvm_init_export_args(ctx, color, param,
6199 args);
6200
6201 if (is_last) {
6202 args->valid_mask = 1; /* whether the EXEC mask is valid */
6203 args->done = 1; /* DONE bit */
6204 } else if (!args->enabled_channels)
6205 return false; /* unnecessary NULL export */
6206
6207 return true;
6208 }
6209
6210 static void
6211 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6212 LLVMValueRef depth, LLVMValueRef stencil,
6213 LLVMValueRef samplemask)
6214 {
6215 struct ac_export_args args;
6216
6217 args.enabled_channels = 0;
6218 args.valid_mask = 1;
6219 args.done = 1;
6220 args.target = V_008DFC_SQ_EXP_MRTZ;
6221 args.compr = false;
6222
6223 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
6224 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6225 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
6226 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
6227
6228 if (depth) {
6229 args.out[0] = depth;
6230 args.enabled_channels |= 0x1;
6231 }
6232
6233 if (stencil) {
6234 args.out[1] = stencil;
6235 args.enabled_channels |= 0x2;
6236 }
6237
6238 if (samplemask) {
6239 args.out[2] = samplemask;
6240 args.enabled_channels |= 0x4;
6241 }
6242
6243 /* SI (except OLAND and HAINAN) has a bug that it only looks
6244 * at the X writemask component. */
6245 if (ctx->options->chip_class == SI &&
6246 ctx->options->family != CHIP_OLAND &&
6247 ctx->options->family != CHIP_HAINAN)
6248 args.enabled_channels |= 0x1;
6249
6250 ac_build_export(&ctx->ac, &args);
6251 }
6252
6253 static void
6254 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6255 {
6256 unsigned index = 0;
6257 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6258 struct ac_export_args color_args[8];
6259
6260 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6261 LLVMValueRef values[4];
6262
6263 if (!(ctx->output_mask & (1ull << i)))
6264 continue;
6265
6266 if (i == FRAG_RESULT_DEPTH) {
6267 ctx->shader_info->fs.writes_z = true;
6268 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6269 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6270 } else if (i == FRAG_RESULT_STENCIL) {
6271 ctx->shader_info->fs.writes_stencil = true;
6272 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6273 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6274 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6275 ctx->shader_info->fs.writes_sample_mask = true;
6276 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6277 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6278 } else {
6279 bool last = false;
6280 for (unsigned j = 0; j < 4; j++)
6281 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6282 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6283
6284 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6285 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6286
6287 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6288 if (ret)
6289 index++;
6290 }
6291 }
6292
6293 for (unsigned i = 0; i < index; i++)
6294 ac_build_export(&ctx->ac, &color_args[i]);
6295 if (depth || stencil || samplemask)
6296 si_export_mrt_z(ctx, depth, stencil, samplemask);
6297 else if (!index) {
6298 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6299 ac_build_export(&ctx->ac, &color_args[0]);
6300 }
6301
6302 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6303 }
6304
6305 static void
6306 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6307 {
6308 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6309 }
6310
6311 static void
6312 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6313 LLVMValueRef *addrs)
6314 {
6315 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6316
6317 switch (ctx->stage) {
6318 case MESA_SHADER_VERTEX:
6319 if (ctx->options->key.vs.as_ls)
6320 handle_ls_outputs_post(ctx);
6321 else if (ctx->options->key.vs.as_es)
6322 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6323 else
6324 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6325 &ctx->shader_info->vs.outinfo);
6326 break;
6327 case MESA_SHADER_FRAGMENT:
6328 handle_fs_outputs_post(ctx);
6329 break;
6330 case MESA_SHADER_GEOMETRY:
6331 emit_gs_epilogue(ctx);
6332 break;
6333 case MESA_SHADER_TESS_CTRL:
6334 handle_tcs_outputs_post(ctx);
6335 break;
6336 case MESA_SHADER_TESS_EVAL:
6337 if (ctx->options->key.tes.as_es)
6338 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6339 else
6340 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6341 &ctx->shader_info->tes.outinfo);
6342 break;
6343 default:
6344 break;
6345 }
6346 }
6347
6348 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6349 {
6350 LLVMPassManagerRef passmgr;
6351 /* Create the pass manager */
6352 passmgr = LLVMCreateFunctionPassManagerForModule(
6353 ctx->module);
6354
6355 /* This pass should eliminate all the load and store instructions */
6356 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6357
6358 /* Add some optimization passes */
6359 LLVMAddScalarReplAggregatesPass(passmgr);
6360 LLVMAddLICMPass(passmgr);
6361 LLVMAddAggressiveDCEPass(passmgr);
6362 LLVMAddCFGSimplificationPass(passmgr);
6363 LLVMAddInstructionCombiningPass(passmgr);
6364
6365 /* Run the pass */
6366 LLVMInitializeFunctionPassManager(passmgr);
6367 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6368 LLVMFinalizeFunctionPassManager(passmgr);
6369
6370 LLVMDisposeBuilder(ctx->builder);
6371 LLVMDisposePassManager(passmgr);
6372 }
6373
6374 static void
6375 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6376 {
6377 struct ac_vs_output_info *outinfo;
6378
6379 switch (ctx->stage) {
6380 case MESA_SHADER_FRAGMENT:
6381 case MESA_SHADER_COMPUTE:
6382 case MESA_SHADER_TESS_CTRL:
6383 case MESA_SHADER_GEOMETRY:
6384 return;
6385 case MESA_SHADER_VERTEX:
6386 if (ctx->options->key.vs.as_ls ||
6387 ctx->options->key.vs.as_es)
6388 return;
6389 outinfo = &ctx->shader_info->vs.outinfo;
6390 break;
6391 case MESA_SHADER_TESS_EVAL:
6392 if (ctx->options->key.vs.as_es)
6393 return;
6394 outinfo = &ctx->shader_info->tes.outinfo;
6395 break;
6396 default:
6397 unreachable("Unhandled shader type");
6398 }
6399
6400 ac_optimize_vs_outputs(&ctx->ac,
6401 ctx->main_function,
6402 outinfo->vs_output_param_offset,
6403 VARYING_SLOT_MAX,
6404 &outinfo->param_exports);
6405 }
6406
6407 static void
6408 ac_setup_rings(struct nir_to_llvm_context *ctx)
6409 {
6410 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6411 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6412 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6413 }
6414
6415 if (ctx->is_gs_copy_shader) {
6416 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6417 }
6418 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6419 LLVMValueRef tmp;
6420 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6421 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6422
6423 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6424
6425 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6426 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6427 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6428 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6429 }
6430
6431 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6432 ctx->stage == MESA_SHADER_TESS_EVAL) {
6433 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6434 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6435 }
6436 }
6437
6438 static unsigned
6439 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6440 const struct nir_shader *nir)
6441 {
6442 switch (nir->info.stage) {
6443 case MESA_SHADER_TESS_CTRL:
6444 return chip_class >= CIK ? 128 : 64;
6445 case MESA_SHADER_GEOMETRY:
6446 return chip_class >= GFX9 ? 128 : 64;
6447 case MESA_SHADER_COMPUTE:
6448 break;
6449 default:
6450 return 0;
6451 }
6452
6453 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6454 nir->info.cs.local_size[1] *
6455 nir->info.cs.local_size[2];
6456 return max_workgroup_size;
6457 }
6458
6459 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6460 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6461 {
6462 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6463 LLVMConstInt(ctx->ac.i32, 8, false),
6464 LLVMConstInt(ctx->ac.i32, 8, false), false);
6465 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6466 LLVMConstInt(ctx->ac.i32, 0, false), "");
6467 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6468 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6469 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6470 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6471 }
6472
6473 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6474 {
6475 for(int i = 5; i >= 0; --i) {
6476 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6477 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6478 LLVMConstInt(ctx->ac.i32, 16, false), false);
6479 }
6480
6481 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6482 LLVMConstInt(ctx->ac.i32, 16, false),
6483 LLVMConstInt(ctx->ac.i32, 8, false), false);
6484 }
6485
6486 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6487 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6488 {
6489 struct ac_nir_context ctx = {};
6490 struct nir_function *func;
6491
6492 ctx.ac = *ac;
6493 ctx.abi = abi;
6494
6495 ctx.nctx = nctx;
6496 if (nctx)
6497 nctx->nir = &ctx;
6498
6499 ctx.stage = nir->info.stage;
6500
6501 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6502
6503 nir_foreach_variable(variable, &nir->outputs)
6504 handle_shader_output_decl(&ctx, nir, variable);
6505
6506 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6507 _mesa_key_pointer_equal);
6508 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6509 _mesa_key_pointer_equal);
6510 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6511 _mesa_key_pointer_equal);
6512
6513 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6514
6515 setup_locals(&ctx, func);
6516
6517 if (nir->info.stage == MESA_SHADER_COMPUTE)
6518 setup_shared(&ctx, nir);
6519
6520 visit_cf_list(&ctx, &func->impl->body);
6521 phi_post_pass(&ctx);
6522
6523 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6524 ctx.outputs);
6525
6526 free(ctx.locals);
6527 ralloc_free(ctx.defs);
6528 ralloc_free(ctx.phis);
6529 ralloc_free(ctx.vars);
6530
6531 if (nctx)
6532 nctx->nir = NULL;
6533 }
6534
6535 static
6536 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6537 struct nir_shader *const *shaders,
6538 int shader_count,
6539 struct ac_shader_variant_info *shader_info,
6540 const struct ac_nir_compiler_options *options)
6541 {
6542 struct nir_to_llvm_context ctx = {0};
6543 unsigned i;
6544 ctx.options = options;
6545 ctx.shader_info = shader_info;
6546 ctx.context = LLVMContextCreate();
6547 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6548
6549 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6550 ctx.ac.module = ctx.module;
6551 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6552
6553 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6554 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6555 LLVMSetDataLayout(ctx.module, data_layout_str);
6556 LLVMDisposeTargetData(data_layout);
6557 LLVMDisposeMessage(data_layout_str);
6558
6559 setup_types(&ctx);
6560 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6561 ctx.ac.builder = ctx.builder;
6562
6563 memset(shader_info, 0, sizeof(*shader_info));
6564
6565 for(int i = 0; i < shader_count; ++i)
6566 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6567
6568 for (i = 0; i < AC_UD_MAX_SETS; i++)
6569 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6570 for (i = 0; i < AC_UD_MAX_UD; i++)
6571 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6572
6573 ctx.max_workgroup_size = 0;
6574 for (int i = 0; i < shader_count; ++i) {
6575 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6576 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6577 shaders[i]));
6578 }
6579
6580 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6581 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6582
6583 ctx.abi.inputs = &ctx.inputs[0];
6584 ctx.abi.emit_outputs = handle_shader_outputs_post;
6585 ctx.abi.load_ssbo = radv_load_ssbo;
6586 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6587 ctx.abi.clamp_shadow_reference = false;
6588
6589 if (shader_count >= 2)
6590 ac_init_exec_full_mask(&ctx.ac);
6591
6592 if (ctx.ac.chip_class == GFX9 &&
6593 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6594 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6595
6596 for(int i = 0; i < shader_count; ++i) {
6597 ctx.stage = shaders[i]->info.stage;
6598 ctx.output_mask = 0;
6599 ctx.tess_outputs_written = 0;
6600 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6601 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6602
6603 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6604 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6605
6606 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6607 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6608 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6609 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6610 if (shader_info->info.vs.needs_instance_id) {
6611 ctx.shader_info->vs.vgpr_comp_cnt =
6612 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6613 }
6614 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6615 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6616 }
6617
6618 if (i)
6619 emit_barrier(&ctx);
6620
6621 ac_setup_rings(&ctx);
6622
6623 LLVMBasicBlockRef merge_block;
6624 if (shader_count >= 2) {
6625 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6626 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6627 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6628
6629 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6630 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6631 LLVMConstInt(ctx.ac.i32, 8, false), false);
6632 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6633 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6634 thread_id, count, "");
6635 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6636
6637 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6638 }
6639
6640 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6641 handle_fs_inputs(&ctx, shaders[i]);
6642 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6643 handle_vs_inputs(&ctx, shaders[i]);
6644 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6645 prepare_gs_input_vgprs(&ctx);
6646
6647 nir_foreach_variable(variable, &shaders[i]->outputs)
6648 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6649
6650 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6651
6652 if (shader_count >= 2) {
6653 LLVMBuildBr(ctx.ac.builder, merge_block);
6654 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6655 }
6656
6657 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6658 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6659 shaders[i]->info.cull_distance_array_size > 4;
6660 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6661 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6662 shaders[i]->info.gs.vertices_out;
6663 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6664 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6665 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6666 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6667 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6668 }
6669 }
6670
6671 LLVMBuildRetVoid(ctx.builder);
6672
6673 ac_llvm_finalize_module(&ctx);
6674
6675 if (shader_count == 1)
6676 ac_nir_eliminate_const_vs_outputs(&ctx);
6677
6678 return ctx.module;
6679 }
6680
6681 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6682 {
6683 unsigned *retval = (unsigned *)context;
6684 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6685 char *description = LLVMGetDiagInfoDescription(di);
6686
6687 if (severity == LLVMDSError) {
6688 *retval = 1;
6689 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6690 description);
6691 }
6692
6693 LLVMDisposeMessage(description);
6694 }
6695
6696 static unsigned ac_llvm_compile(LLVMModuleRef M,
6697 struct ac_shader_binary *binary,
6698 LLVMTargetMachineRef tm)
6699 {
6700 unsigned retval = 0;
6701 char *err;
6702 LLVMContextRef llvm_ctx;
6703 LLVMMemoryBufferRef out_buffer;
6704 unsigned buffer_size;
6705 const char *buffer_data;
6706 LLVMBool mem_err;
6707
6708 /* Setup Diagnostic Handler*/
6709 llvm_ctx = LLVMGetModuleContext(M);
6710
6711 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6712 &retval);
6713
6714 /* Compile IR*/
6715 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6716 &err, &out_buffer);
6717
6718 /* Process Errors/Warnings */
6719 if (mem_err) {
6720 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6721 free(err);
6722 retval = 1;
6723 goto out;
6724 }
6725
6726 /* Extract Shader Code*/
6727 buffer_size = LLVMGetBufferSize(out_buffer);
6728 buffer_data = LLVMGetBufferStart(out_buffer);
6729
6730 ac_elf_read(buffer_data, buffer_size, binary);
6731
6732 /* Clean up */
6733 LLVMDisposeMemoryBuffer(out_buffer);
6734
6735 out:
6736 return retval;
6737 }
6738
6739 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6740 LLVMModuleRef llvm_module,
6741 struct ac_shader_binary *binary,
6742 struct ac_shader_config *config,
6743 struct ac_shader_variant_info *shader_info,
6744 gl_shader_stage stage,
6745 bool dump_shader, bool supports_spill)
6746 {
6747 if (dump_shader)
6748 ac_dump_module(llvm_module);
6749
6750 memset(binary, 0, sizeof(*binary));
6751 int v = ac_llvm_compile(llvm_module, binary, tm);
6752 if (v) {
6753 fprintf(stderr, "compile failed\n");
6754 }
6755
6756 if (dump_shader)
6757 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6758
6759 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6760
6761 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6762 LLVMDisposeModule(llvm_module);
6763 LLVMContextDispose(ctx);
6764
6765 if (stage == MESA_SHADER_FRAGMENT) {
6766 shader_info->num_input_vgprs = 0;
6767 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6768 shader_info->num_input_vgprs += 2;
6769 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6770 shader_info->num_input_vgprs += 2;
6771 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6772 shader_info->num_input_vgprs += 2;
6773 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6774 shader_info->num_input_vgprs += 3;
6775 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6776 shader_info->num_input_vgprs += 2;
6777 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6778 shader_info->num_input_vgprs += 2;
6779 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6780 shader_info->num_input_vgprs += 2;
6781 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6782 shader_info->num_input_vgprs += 1;
6783 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6784 shader_info->num_input_vgprs += 1;
6785 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6786 shader_info->num_input_vgprs += 1;
6787 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6788 shader_info->num_input_vgprs += 1;
6789 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6790 shader_info->num_input_vgprs += 1;
6791 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6792 shader_info->num_input_vgprs += 1;
6793 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6794 shader_info->num_input_vgprs += 1;
6795 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6796 shader_info->num_input_vgprs += 1;
6797 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6798 shader_info->num_input_vgprs += 1;
6799 }
6800 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6801
6802 /* +3 for scratch wave offset and VCC */
6803 config->num_sgprs = MAX2(config->num_sgprs,
6804 shader_info->num_input_sgprs + 3);
6805 }
6806
6807 static void
6808 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6809 {
6810 switch (nir->info.stage) {
6811 case MESA_SHADER_COMPUTE:
6812 for (int i = 0; i < 3; ++i)
6813 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6814 break;
6815 case MESA_SHADER_FRAGMENT:
6816 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6817 break;
6818 case MESA_SHADER_GEOMETRY:
6819 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6820 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6821 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6822 shader_info->gs.invocations = nir->info.gs.invocations;
6823 break;
6824 case MESA_SHADER_TESS_EVAL:
6825 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6826 shader_info->tes.spacing = nir->info.tess.spacing;
6827 shader_info->tes.ccw = nir->info.tess.ccw;
6828 shader_info->tes.point_mode = nir->info.tess.point_mode;
6829 shader_info->tes.as_es = options->key.tes.as_es;
6830 break;
6831 case MESA_SHADER_TESS_CTRL:
6832 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6833 break;
6834 case MESA_SHADER_VERTEX:
6835 shader_info->vs.as_es = options->key.vs.as_es;
6836 shader_info->vs.as_ls = options->key.vs.as_ls;
6837 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6838 if (options->key.vs.as_ls)
6839 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6840 break;
6841 default:
6842 break;
6843 }
6844 }
6845
6846 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6847 struct ac_shader_binary *binary,
6848 struct ac_shader_config *config,
6849 struct ac_shader_variant_info *shader_info,
6850 struct nir_shader *const *nir,
6851 int nir_count,
6852 const struct ac_nir_compiler_options *options,
6853 bool dump_shader)
6854 {
6855
6856 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6857 options);
6858
6859 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6860 for (int i = 0; i < nir_count; ++i)
6861 ac_fill_shader_info(shader_info, nir[i], options);
6862 }
6863
6864 static void
6865 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6866 {
6867 LLVMValueRef args[9];
6868 args[0] = ctx->gsvs_ring;
6869 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6870 args[3] = ctx->ac.i32_0;
6871 args[4] = ctx->ac.i32_1; /* OFFEN */
6872 args[5] = ctx->ac.i32_0; /* IDXEN */
6873 args[6] = ctx->ac.i32_1; /* GLC */
6874 args[7] = ctx->ac.i32_1; /* SLC */
6875 args[8] = ctx->ac.i32_0; /* TFE */
6876
6877 int idx = 0;
6878
6879 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6880 int length = 4;
6881 int slot = idx;
6882 int slot_inc = 1;
6883 if (!(ctx->output_mask & (1ull << i)))
6884 continue;
6885
6886 if (i == VARYING_SLOT_CLIP_DIST0) {
6887 /* unpack clip and cull from a single set of slots */
6888 length = ctx->num_output_clips + ctx->num_output_culls;
6889 if (length > 4)
6890 slot_inc = 2;
6891 }
6892
6893 for (unsigned j = 0; j < length; j++) {
6894 LLVMValueRef value;
6895 args[2] = LLVMConstInt(ctx->i32,
6896 (slot * 4 + j) *
6897 ctx->gs_max_out_vertices * 16 * 4, false);
6898
6899 value = ac_build_intrinsic(&ctx->ac,
6900 "llvm.SI.buffer.load.dword.i32.i32",
6901 ctx->i32, args, 9,
6902 AC_FUNC_ATTR_READONLY |
6903 AC_FUNC_ATTR_LEGACY);
6904
6905 LLVMBuildStore(ctx->builder,
6906 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6907 }
6908 idx += slot_inc;
6909 }
6910 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6911 }
6912
6913 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6914 struct nir_shader *geom_shader,
6915 struct ac_shader_binary *binary,
6916 struct ac_shader_config *config,
6917 struct ac_shader_variant_info *shader_info,
6918 const struct ac_nir_compiler_options *options,
6919 bool dump_shader)
6920 {
6921 struct nir_to_llvm_context ctx = {0};
6922 ctx.context = LLVMContextCreate();
6923 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6924 ctx.options = options;
6925 ctx.shader_info = shader_info;
6926
6927 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6928 ctx.ac.module = ctx.module;
6929
6930 ctx.is_gs_copy_shader = true;
6931 LLVMSetTarget(ctx.module, "amdgcn--");
6932 setup_types(&ctx);
6933
6934 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6935 ctx.ac.builder = ctx.builder;
6936 ctx.stage = MESA_SHADER_VERTEX;
6937
6938 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6939
6940 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6941 ac_setup_rings(&ctx);
6942
6943 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6944 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6945
6946 struct ac_nir_context nir_ctx = {};
6947 nir_ctx.ac = ctx.ac;
6948 nir_ctx.abi = &ctx.abi;
6949
6950 nir_ctx.nctx = &ctx;
6951 ctx.nir = &nir_ctx;
6952
6953 nir_foreach_variable(variable, &geom_shader->outputs) {
6954 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6955 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6956 }
6957
6958 ac_gs_copy_shader_emit(&ctx);
6959
6960 ctx.nir = NULL;
6961
6962 LLVMBuildRetVoid(ctx.builder);
6963
6964 ac_llvm_finalize_module(&ctx);
6965
6966 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6967 MESA_SHADER_VERTEX,
6968 dump_shader, options->supports_spill);
6969 }