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radv: fix regression with mask attrib setting code.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef gsvs_ring_stride;
87 LLVMValueRef gsvs_num_entries;
88 LLVMValueRef gs2vs_offset;
89 LLVMValueRef gs_wave_id;
90 LLVMValueRef gs_vtx_offset[6];
91 LLVMValueRef gs_prim_id, gs_invocation_id;
92
93 LLVMValueRef esgs_ring;
94 LLVMValueRef gsvs_ring;
95
96 LLVMValueRef prim_mask;
97 LLVMValueRef sample_positions;
98 LLVMValueRef persp_sample, persp_center, persp_centroid;
99 LLVMValueRef linear_sample, linear_center, linear_centroid;
100 LLVMValueRef front_face;
101 LLVMValueRef ancillary;
102 LLVMValueRef sample_coverage;
103 LLVMValueRef frag_pos[4];
104
105 LLVMBasicBlockRef continue_block;
106 LLVMBasicBlockRef break_block;
107
108 LLVMTypeRef i1;
109 LLVMTypeRef i8;
110 LLVMTypeRef i16;
111 LLVMTypeRef i32;
112 LLVMTypeRef i64;
113 LLVMTypeRef v2i32;
114 LLVMTypeRef v3i32;
115 LLVMTypeRef v4i32;
116 LLVMTypeRef v8i32;
117 LLVMTypeRef f64;
118 LLVMTypeRef f32;
119 LLVMTypeRef f16;
120 LLVMTypeRef v2f32;
121 LLVMTypeRef v4f32;
122 LLVMTypeRef v16i8;
123 LLVMTypeRef voidt;
124
125 LLVMValueRef i1true;
126 LLVMValueRef i1false;
127 LLVMValueRef i32zero;
128 LLVMValueRef i32one;
129 LLVMValueRef f32zero;
130 LLVMValueRef f32one;
131 LLVMValueRef v4f32empty;
132
133 unsigned uniform_md_kind;
134 LLVMValueRef empty_md;
135 gl_shader_stage stage;
136
137 LLVMValueRef lds;
138 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
139 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
140
141 LLVMValueRef shared_memory;
142 uint64_t input_mask;
143 uint64_t output_mask;
144 int num_locals;
145 LLVMValueRef *locals;
146 bool has_ddxy;
147 uint8_t num_output_clips;
148 uint8_t num_output_culls;
149
150 bool has_ds_bpermute;
151
152 bool is_gs_copy_shader;
153 LLVMValueRef gs_next_vertex;
154 unsigned gs_max_out_vertices;
155 };
156
157 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
158 nir_deref_var *deref,
159 enum desc_type desc_type);
160 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
161 {
162 return (index * 4) + chan;
163 }
164
165 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
166 {
167 if (slot == VARYING_SLOT_POS)
168 return 0;
169 if (slot == VARYING_SLOT_PSIZ)
170 return 1;
171 if (slot == VARYING_SLOT_CLIP_DIST0)
172 return 2;
173 /* 3 is reserved for clip dist as well */
174 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
175 return 4 + (slot - VARYING_SLOT_VAR0);
176 unreachable("illegal slot in get unique index\n");
177 }
178
179 static unsigned llvm_get_type_size(LLVMTypeRef type)
180 {
181 LLVMTypeKind kind = LLVMGetTypeKind(type);
182
183 switch (kind) {
184 case LLVMIntegerTypeKind:
185 return LLVMGetIntTypeWidth(type) / 8;
186 case LLVMFloatTypeKind:
187 return 4;
188 case LLVMPointerTypeKind:
189 return 8;
190 case LLVMVectorTypeKind:
191 return LLVMGetVectorSize(type) *
192 llvm_get_type_size(LLVMGetElementType(type));
193 default:
194 assert(0);
195 return 0;
196 }
197 }
198
199 static void set_llvm_calling_convention(LLVMValueRef func,
200 gl_shader_stage stage)
201 {
202 enum radeon_llvm_calling_convention calling_conv;
203
204 switch (stage) {
205 case MESA_SHADER_VERTEX:
206 case MESA_SHADER_TESS_CTRL:
207 case MESA_SHADER_TESS_EVAL:
208 calling_conv = RADEON_LLVM_AMDGPU_VS;
209 break;
210 case MESA_SHADER_GEOMETRY:
211 calling_conv = RADEON_LLVM_AMDGPU_GS;
212 break;
213 case MESA_SHADER_FRAGMENT:
214 calling_conv = RADEON_LLVM_AMDGPU_PS;
215 break;
216 case MESA_SHADER_COMPUTE:
217 calling_conv = RADEON_LLVM_AMDGPU_CS;
218 break;
219 default:
220 unreachable("Unhandle shader type");
221 }
222
223 LLVMSetFunctionCallConv(func, calling_conv);
224 }
225
226 static LLVMValueRef
227 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
228 LLVMBuilderRef builder, LLVMTypeRef *return_types,
229 unsigned num_return_elems, LLVMTypeRef *param_types,
230 unsigned param_count, unsigned array_params_mask,
231 unsigned sgpr_params, bool unsafe_math)
232 {
233 LLVMTypeRef main_function_type, ret_type;
234 LLVMBasicBlockRef main_function_body;
235
236 if (num_return_elems)
237 ret_type = LLVMStructTypeInContext(ctx, return_types,
238 num_return_elems, true);
239 else
240 ret_type = LLVMVoidTypeInContext(ctx);
241
242 /* Setup the function */
243 main_function_type =
244 LLVMFunctionType(ret_type, param_types, param_count, 0);
245 LLVMValueRef main_function =
246 LLVMAddFunction(module, "main", main_function_type);
247 main_function_body =
248 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
249 LLVMPositionBuilderAtEnd(builder, main_function_body);
250
251 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
252 for (unsigned i = 0; i < sgpr_params; ++i) {
253 if (array_params_mask & (1 << i)) {
254 LLVMValueRef P = LLVMGetParam(main_function, i);
255 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
256 ac_add_attr_dereferenceable(P, UINT64_MAX);
257 }
258 else {
259 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
260 }
261 }
262
263 if (unsafe_math) {
264 /* These were copied from some LLVM test. */
265 LLVMAddTargetDependentFunctionAttr(main_function,
266 "less-precise-fpmad",
267 "true");
268 LLVMAddTargetDependentFunctionAttr(main_function,
269 "no-infs-fp-math",
270 "true");
271 LLVMAddTargetDependentFunctionAttr(main_function,
272 "no-nans-fp-math",
273 "true");
274 LLVMAddTargetDependentFunctionAttr(main_function,
275 "unsafe-fp-math",
276 "true");
277 }
278 return main_function;
279 }
280
281 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
282 {
283 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
284 CONST_ADDR_SPACE);
285 }
286
287 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
288 int idx,
289 LLVMTypeRef type)
290 {
291 LLVMValueRef offset;
292 LLVMValueRef ptr;
293 int addr_space;
294
295 offset = LLVMConstInt(ctx->i32, idx * 16, false);
296
297 ptr = ctx->shared_memory;
298 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
299 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
300 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
301 return ptr;
302 }
303
304 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
305 {
306 if (t == ctx->f16 || t == ctx->i16)
307 return ctx->i16;
308 else if (t == ctx->f32 || t == ctx->i32)
309 return ctx->i32;
310 else if (t == ctx->f64 || t == ctx->i64)
311 return ctx->i64;
312 else
313 unreachable("Unhandled integer size");
314 }
315
316 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
317 {
318 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
319 LLVMTypeRef elem_type = LLVMGetElementType(t);
320 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
321 LLVMGetVectorSize(t));
322 }
323 return to_integer_type_scalar(ctx, t);
324 }
325
326 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
327 {
328 LLVMTypeRef type = LLVMTypeOf(v);
329 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
330 }
331
332 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
333 {
334 if (t == ctx->i16 || t == ctx->f16)
335 return ctx->f16;
336 else if (t == ctx->i32 || t == ctx->f32)
337 return ctx->f32;
338 else if (t == ctx->i64 || t == ctx->f64)
339 return ctx->f64;
340 else
341 unreachable("Unhandled float size");
342 }
343
344 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
345 {
346 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
347 LLVMTypeRef elem_type = LLVMGetElementType(t);
348 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
349 LLVMGetVectorSize(t));
350 }
351 return to_float_type_scalar(ctx, t);
352 }
353
354 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
355 {
356 LLVMTypeRef type = LLVMTypeOf(v);
357 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
358 }
359
360 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
361 {
362 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
363 type = LLVMGetElementType(type);
364
365 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
366 return LLVMGetIntTypeWidth(type);
367
368 if (type == ctx->f16)
369 return 16;
370 if (type == ctx->f32)
371 return 32;
372 if (type == ctx->f64)
373 return 64;
374
375 unreachable("Unhandled type kind in get_elem_bits");
376 }
377
378 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
379 LLVMValueRef param, unsigned rshift,
380 unsigned bitwidth)
381 {
382 LLVMValueRef value = param;
383 if (rshift)
384 value = LLVMBuildLShr(ctx->builder, value,
385 LLVMConstInt(ctx->i32, rshift, false), "");
386
387 if (rshift + bitwidth < 32) {
388 unsigned mask = (1 << bitwidth) - 1;
389 value = LLVMBuildAnd(ctx->builder, value,
390 LLVMConstInt(ctx->i32, mask, false), "");
391 }
392 return value;
393 }
394
395 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
396 {
397 ud_info->sgpr_idx = sgpr_idx;
398 ud_info->num_sgprs = num_sgprs;
399 ud_info->indirect = false;
400 ud_info->indirect_offset = 0;
401 }
402
403 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
404 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
405 {
406 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
407 }
408
409 #if 0
410 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
411 uint32_t indirect_offset)
412 {
413 ud_info->sgpr_idx = sgpr_idx;
414 ud_info->num_sgprs = num_sgprs;
415 ud_info->indirect = true;
416 ud_info->indirect_offset = indirect_offset;
417 }
418 #endif
419
420 static void create_function(struct nir_to_llvm_context *ctx)
421 {
422 LLVMTypeRef arg_types[23];
423 unsigned arg_idx = 0;
424 unsigned array_params_mask = 0;
425 unsigned sgpr_count = 0, user_sgpr_count;
426 unsigned i;
427 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
428 unsigned user_sgpr_idx;
429 bool need_push_constants;
430 bool need_ring_offsets = false;
431
432 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
433 if (ctx->stage == MESA_SHADER_GEOMETRY ||
434 ctx->stage == MESA_SHADER_VERTEX ||
435 ctx->is_gs_copy_shader)
436 need_ring_offsets = true;
437
438 need_push_constants = true;
439 if (!ctx->options->layout)
440 need_push_constants = false;
441 else if (!ctx->options->layout->push_constant_size &&
442 !ctx->options->layout->dynamic_offset_count)
443 need_push_constants = false;
444
445 if (need_ring_offsets && !ctx->options->supports_spill) {
446 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
447 }
448
449 /* 1 for each descriptor set */
450 for (unsigned i = 0; i < num_sets; ++i) {
451 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
452 array_params_mask |= (1 << arg_idx);
453 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
454 }
455 }
456
457 if (need_push_constants) {
458 /* 1 for push constants and dynamic descriptors */
459 array_params_mask |= (1 << arg_idx);
460 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
461 }
462
463 switch (ctx->stage) {
464 case MESA_SHADER_COMPUTE:
465 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
466 user_sgpr_count = arg_idx;
467 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
468 arg_types[arg_idx++] = ctx->i32;
469 sgpr_count = arg_idx;
470
471 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
472 break;
473 case MESA_SHADER_VERTEX:
474 if (!ctx->is_gs_copy_shader) {
475 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
476 arg_types[arg_idx++] = ctx->i32; // base vertex
477 arg_types[arg_idx++] = ctx->i32; // start instance
478 arg_types[arg_idx++] = ctx->i32; // draw index
479 }
480 user_sgpr_count = arg_idx;
481 if (ctx->options->key.vs.as_es)
482 arg_types[arg_idx++] = ctx->i32; //es2gs offset
483 sgpr_count = arg_idx;
484 arg_types[arg_idx++] = ctx->i32; // vertex id
485 if (!ctx->is_gs_copy_shader) {
486 arg_types[arg_idx++] = ctx->i32; // rel auto id
487 arg_types[arg_idx++] = ctx->i32; // vs prim id
488 arg_types[arg_idx++] = ctx->i32; // instance id
489 }
490 break;
491 case MESA_SHADER_GEOMETRY:
492 arg_types[arg_idx++] = ctx->i32; // gsvs stride
493 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
494 user_sgpr_count = arg_idx;
495 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
496 arg_types[arg_idx++] = ctx->i32; // wave id
497 sgpr_count = arg_idx;
498 arg_types[arg_idx++] = ctx->i32; // vtx0
499 arg_types[arg_idx++] = ctx->i32; // vtx1
500 arg_types[arg_idx++] = ctx->i32; // prim id
501 arg_types[arg_idx++] = ctx->i32; // vtx2
502 arg_types[arg_idx++] = ctx->i32; // vtx3
503 arg_types[arg_idx++] = ctx->i32; // vtx4
504 arg_types[arg_idx++] = ctx->i32; // vtx5
505 arg_types[arg_idx++] = ctx->i32; // GS instance id
506 break;
507 case MESA_SHADER_FRAGMENT:
508 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
509 user_sgpr_count = arg_idx;
510 arg_types[arg_idx++] = ctx->i32; /* prim mask */
511 sgpr_count = arg_idx;
512 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
513 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
514 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
515 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
516 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
517 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
518 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
519 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
520 arg_types[arg_idx++] = ctx->f32; /* pos x float */
521 arg_types[arg_idx++] = ctx->f32; /* pos y float */
522 arg_types[arg_idx++] = ctx->f32; /* pos z float */
523 arg_types[arg_idx++] = ctx->f32; /* pos w float */
524 arg_types[arg_idx++] = ctx->i32; /* front face */
525 arg_types[arg_idx++] = ctx->i32; /* ancillary */
526 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
527 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
528 break;
529 default:
530 unreachable("Shader stage not implemented");
531 }
532
533 ctx->main_function = create_llvm_function(
534 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
535 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
536 set_llvm_calling_convention(ctx->main_function, ctx->stage);
537
538 ctx->shader_info->num_input_sgprs = 0;
539 ctx->shader_info->num_input_vgprs = 0;
540
541 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
542 for (i = 0; i < user_sgpr_count; i++)
543 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
544
545 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
546 for (; i < sgpr_count; i++)
547 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
548
549 if (ctx->stage != MESA_SHADER_FRAGMENT)
550 for (; i < arg_idx; ++i)
551 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
552
553 arg_idx = 0;
554 user_sgpr_idx = 0;
555
556 if (ctx->options->supports_spill || need_ring_offsets) {
557 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
558 user_sgpr_idx += 2;
559 if (ctx->options->supports_spill) {
560 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
561 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
562 NULL, 0, AC_FUNC_ATTR_READNONE);
563 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
564 const_array(ctx->v16i8, 8), "");
565 } else
566 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
567 }
568
569 for (unsigned i = 0; i < num_sets; ++i) {
570 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
571 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
572 user_sgpr_idx += 2;
573 ctx->descriptor_sets[i] =
574 LLVMGetParam(ctx->main_function, arg_idx++);
575 } else
576 ctx->descriptor_sets[i] = NULL;
577 }
578
579 if (need_push_constants) {
580 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
581 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
582 user_sgpr_idx += 2;
583 }
584
585 switch (ctx->stage) {
586 case MESA_SHADER_COMPUTE:
587 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
588 user_sgpr_idx += 3;
589 ctx->num_work_groups =
590 LLVMGetParam(ctx->main_function, arg_idx++);
591 ctx->workgroup_ids =
592 LLVMGetParam(ctx->main_function, arg_idx++);
593 ctx->tg_size =
594 LLVMGetParam(ctx->main_function, arg_idx++);
595 ctx->local_invocation_ids =
596 LLVMGetParam(ctx->main_function, arg_idx++);
597 break;
598 case MESA_SHADER_VERTEX:
599 if (!ctx->is_gs_copy_shader) {
600 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
601 user_sgpr_idx += 2;
602 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
603 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
604 user_sgpr_idx += 3;
605 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
606 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
607 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
608 }
609 if (ctx->options->key.vs.as_es)
610 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
611 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
612 if (!ctx->is_gs_copy_shader) {
613 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
614 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
615 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
616 }
617 break;
618 case MESA_SHADER_GEOMETRY:
619 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
620 user_sgpr_idx += 2;
621 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
622 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
623 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
624 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
625 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
626 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
627 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
628 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
629 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
630 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
631 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
632 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
633 break;
634 case MESA_SHADER_FRAGMENT:
635 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
636 user_sgpr_idx += 2;
637 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
638 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
639 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
640 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
641 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
642 arg_idx++;
643 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
644 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
645 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
646 arg_idx++; /* line stipple */
647 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
648 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
651 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
652 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
653 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
654 break;
655 default:
656 unreachable("Shader stage not implemented");
657 }
658 }
659
660 static void setup_types(struct nir_to_llvm_context *ctx)
661 {
662 LLVMValueRef args[4];
663
664 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
665 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
666 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
667 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
668 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
669 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
670 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
671 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
672 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
673 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
674 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
675 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
676 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
677 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
678 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
679 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
680
681 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
682 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
683 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
684 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
685 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
686 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
687
688 args[0] = ctx->f32zero;
689 args[1] = ctx->f32zero;
690 args[2] = ctx->f32zero;
691 args[3] = ctx->f32one;
692 ctx->v4f32empty = LLVMConstVector(args, 4);
693
694 ctx->uniform_md_kind =
695 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
696 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
697
698 args[0] = LLVMConstReal(ctx->f32, 2.5);
699 }
700
701 static int get_llvm_num_components(LLVMValueRef value)
702 {
703 LLVMTypeRef type = LLVMTypeOf(value);
704 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
705 ? LLVMGetVectorSize(type)
706 : 1;
707 return num_components;
708 }
709
710 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
711 LLVMValueRef value,
712 int index)
713 {
714 int count = get_llvm_num_components(value);
715
716 assert(index < count);
717 if (count == 1)
718 return value;
719
720 return LLVMBuildExtractElement(ctx->builder, value,
721 LLVMConstInt(ctx->i32, index, false), "");
722 }
723
724 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
725 LLVMValueRef value, unsigned count)
726 {
727 unsigned num_components = get_llvm_num_components(value);
728 if (count == num_components)
729 return value;
730
731 LLVMValueRef masks[] = {
732 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
733 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
734
735 if (count == 1)
736 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
737 "");
738
739 LLVMValueRef swizzle = LLVMConstVector(masks, count);
740 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
741 }
742
743 static void
744 build_store_values_extended(struct nir_to_llvm_context *ctx,
745 LLVMValueRef *values,
746 unsigned value_count,
747 unsigned value_stride,
748 LLVMValueRef vec)
749 {
750 LLVMBuilderRef builder = ctx->builder;
751 unsigned i;
752
753 if (value_count == 1) {
754 LLVMBuildStore(builder, vec, values[0]);
755 return;
756 }
757
758 for (i = 0; i < value_count; i++) {
759 LLVMValueRef ptr = values[i * value_stride];
760 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
761 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
762 LLVMBuildStore(builder, value, ptr);
763 }
764 }
765
766 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
767 nir_ssa_def *def)
768 {
769 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
770 if (def->num_components > 1) {
771 type = LLVMVectorType(type, def->num_components);
772 }
773 return type;
774 }
775
776 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
777 {
778 assert(src.is_ssa);
779 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
780 return (LLVMValueRef)entry->data;
781 }
782
783
784 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
785 struct nir_block *b)
786 {
787 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
788 return (LLVMBasicBlockRef)entry->data;
789 }
790
791 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
792 nir_alu_src src,
793 unsigned num_components)
794 {
795 LLVMValueRef value = get_src(ctx, src.src);
796 bool need_swizzle = false;
797
798 assert(value);
799 LLVMTypeRef type = LLVMTypeOf(value);
800 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
801 ? LLVMGetVectorSize(type)
802 : 1;
803
804 for (unsigned i = 0; i < num_components; ++i) {
805 assert(src.swizzle[i] < src_components);
806 if (src.swizzle[i] != i)
807 need_swizzle = true;
808 }
809
810 if (need_swizzle || num_components != src_components) {
811 LLVMValueRef masks[] = {
812 LLVMConstInt(ctx->i32, src.swizzle[0], false),
813 LLVMConstInt(ctx->i32, src.swizzle[1], false),
814 LLVMConstInt(ctx->i32, src.swizzle[2], false),
815 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
816
817 if (src_components > 1 && num_components == 1) {
818 value = LLVMBuildExtractElement(ctx->builder, value,
819 masks[0], "");
820 } else if (src_components == 1 && num_components > 1) {
821 LLVMValueRef values[] = {value, value, value, value};
822 value = ac_build_gather_values(&ctx->ac, values, num_components);
823 } else {
824 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
825 value = LLVMBuildShuffleVector(ctx->builder, value, value,
826 swizzle, "");
827 }
828 }
829 assert(!src.negate);
830 assert(!src.abs);
831 return value;
832 }
833
834 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
835 LLVMIntPredicate pred, LLVMValueRef src0,
836 LLVMValueRef src1)
837 {
838 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
839 return LLVMBuildSelect(ctx->builder, result,
840 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
841 LLVMConstInt(ctx->i32, 0, false), "");
842 }
843
844 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
845 LLVMRealPredicate pred, LLVMValueRef src0,
846 LLVMValueRef src1)
847 {
848 LLVMValueRef result;
849 src0 = to_float(ctx, src0);
850 src1 = to_float(ctx, src1);
851 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
852 return LLVMBuildSelect(ctx->builder, result,
853 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
854 LLVMConstInt(ctx->i32, 0, false), "");
855 }
856
857 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
858 const char *intrin,
859 LLVMTypeRef result_type,
860 LLVMValueRef src0)
861 {
862 char name[64];
863 LLVMValueRef params[] = {
864 to_float(ctx, src0),
865 };
866
867 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
868 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
869 }
870
871 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
872 const char *intrin,
873 LLVMTypeRef result_type,
874 LLVMValueRef src0, LLVMValueRef src1)
875 {
876 char name[64];
877 LLVMValueRef params[] = {
878 to_float(ctx, src0),
879 to_float(ctx, src1),
880 };
881
882 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
883 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
884 }
885
886 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
887 const char *intrin,
888 LLVMTypeRef result_type,
889 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
890 {
891 char name[64];
892 LLVMValueRef params[] = {
893 to_float(ctx, src0),
894 to_float(ctx, src1),
895 to_float(ctx, src2),
896 };
897
898 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
899 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
900 }
901
902 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
903 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
904 {
905 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
906 ctx->i32zero, "");
907 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
908 }
909
910 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
911 LLVMValueRef src0)
912 {
913 LLVMValueRef params[2] = {
914 src0,
915
916 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
917 * add special code to check for x=0. The reason is that
918 * the LLVM behavior for x=0 is different from what we
919 * need here.
920 *
921 * The hardware already implements the correct behavior.
922 */
923 LLVMConstInt(ctx->i32, 1, false),
924 };
925 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
926 }
927
928 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
929 LLVMValueRef src0)
930 {
931 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
932 }
933
934 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
935 LLVMValueRef src0)
936 {
937 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
938 }
939
940 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
941 LLVMIntPredicate pred,
942 LLVMValueRef src0, LLVMValueRef src1)
943 {
944 return LLVMBuildSelect(ctx->builder,
945 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
946 src0,
947 src1, "");
948
949 }
950 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
951 LLVMValueRef src0)
952 {
953 return emit_minmax_int(ctx, LLVMIntSGT, src0,
954 LLVMBuildNeg(ctx->builder, src0, ""));
955 }
956
957 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
958 LLVMValueRef src0)
959 {
960 LLVMValueRef cmp, val;
961
962 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
963 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
964 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
965 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
966 return val;
967 }
968
969 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
970 LLVMValueRef src0)
971 {
972 LLVMValueRef cmp, val;
973
974 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
975 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
976 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
977 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
978 return val;
979 }
980
981 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
982 LLVMValueRef src0)
983 {
984 const char *intr = "llvm.floor.f32";
985 LLVMValueRef fsrc0 = to_float(ctx, src0);
986 LLVMValueRef params[] = {
987 fsrc0,
988 };
989 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
990 ctx->f32, params, 1,
991 AC_FUNC_ATTR_READNONE);
992 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
993 }
994
995 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
996 const char *intrin,
997 LLVMValueRef src0, LLVMValueRef src1)
998 {
999 LLVMTypeRef ret_type;
1000 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1001 LLVMValueRef res;
1002 LLVMValueRef params[] = { src0, src1 };
1003 ret_type = LLVMStructTypeInContext(ctx->context, types,
1004 2, true);
1005
1006 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1007 params, 2, AC_FUNC_ATTR_READNONE);
1008
1009 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1010 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1011 return res;
1012 }
1013
1014 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1015 LLVMValueRef src0)
1016 {
1017 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1018 }
1019
1020 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1021 LLVMValueRef src0, LLVMValueRef src1)
1022 {
1023 LLVMValueRef dst64, result;
1024 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1025 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1026
1027 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1028 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1029 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1030 return result;
1031 }
1032
1033 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1034 LLVMValueRef src0, LLVMValueRef src1)
1035 {
1036 LLVMValueRef dst64, result;
1037 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1038 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1039
1040 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1041 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1042 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1043 return result;
1044 }
1045
1046 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1047 bool is_signed,
1048 LLVMValueRef srcs[3])
1049 {
1050 LLVMValueRef result;
1051 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1052
1053 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1054 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1055 return result;
1056 }
1057
1058 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1059 LLVMValueRef src0, LLVMValueRef src1,
1060 LLVMValueRef src2, LLVMValueRef src3)
1061 {
1062 LLVMValueRef bfi_args[3], result;
1063
1064 bfi_args[0] = LLVMBuildShl(ctx->builder,
1065 LLVMBuildSub(ctx->builder,
1066 LLVMBuildShl(ctx->builder,
1067 ctx->i32one,
1068 src3, ""),
1069 ctx->i32one, ""),
1070 src2, "");
1071 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1072 bfi_args[2] = src0;
1073
1074 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1075
1076 /* Calculate:
1077 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1078 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1079 */
1080 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1081 LLVMBuildAnd(ctx->builder, bfi_args[0],
1082 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1083
1084 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1085 return result;
1086 }
1087
1088 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1089 LLVMValueRef src0)
1090 {
1091 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1092 int i;
1093 LLVMValueRef comp[2];
1094
1095 src0 = to_float(ctx, src0);
1096 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1097 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1098 for (i = 0; i < 2; i++) {
1099 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1100 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1101 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1102 }
1103
1104 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1105 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1106
1107 return comp[0];
1108 }
1109
1110 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1111 LLVMValueRef src0)
1112 {
1113 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1114 LLVMValueRef temps[2], result, val;
1115 int i;
1116
1117 for (i = 0; i < 2; i++) {
1118 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1119 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1120 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1121 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1122 }
1123
1124 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1125 ctx->i32zero, "");
1126 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1127 ctx->i32one, "");
1128 return result;
1129 }
1130
1131 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1132 nir_op op,
1133 LLVMValueRef src0)
1134 {
1135 unsigned mask;
1136 int idx;
1137 LLVMValueRef result;
1138 ctx->has_ddxy = true;
1139
1140 if (!ctx->lds && !ctx->has_ds_bpermute)
1141 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1142 LLVMArrayType(ctx->i32, 64),
1143 "ddxy_lds", LOCAL_ADDR_SPACE);
1144
1145 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1146 mask = AC_TID_MASK_LEFT;
1147 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1148 mask = AC_TID_MASK_TOP;
1149 else
1150 mask = AC_TID_MASK_TOP_LEFT;
1151
1152 /* for DDX we want to next X pixel, DDY next Y pixel. */
1153 if (op == nir_op_fddx_fine ||
1154 op == nir_op_fddx_coarse ||
1155 op == nir_op_fddx)
1156 idx = 1;
1157 else
1158 idx = 2;
1159
1160 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1161 mask, idx, ctx->lds,
1162 src0);
1163 return result;
1164 }
1165
1166 /*
1167 * this takes an I,J coordinate pair,
1168 * and works out the X and Y derivatives.
1169 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1170 */
1171 static LLVMValueRef emit_ddxy_interp(
1172 struct nir_to_llvm_context *ctx,
1173 LLVMValueRef interp_ij)
1174 {
1175 LLVMValueRef result[4], a;
1176 unsigned i;
1177
1178 for (i = 0; i < 2; i++) {
1179 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1180 LLVMConstInt(ctx->i32, i, false), "");
1181 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1182 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1183 }
1184 return ac_build_gather_values(&ctx->ac, result, 4);
1185 }
1186
1187 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1188 {
1189 LLVMValueRef src[4], result = NULL;
1190 unsigned num_components = instr->dest.dest.ssa.num_components;
1191 unsigned src_components;
1192 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1193
1194 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1195 switch (instr->op) {
1196 case nir_op_vec2:
1197 case nir_op_vec3:
1198 case nir_op_vec4:
1199 src_components = 1;
1200 break;
1201 case nir_op_pack_half_2x16:
1202 src_components = 2;
1203 break;
1204 case nir_op_unpack_half_2x16:
1205 src_components = 1;
1206 break;
1207 default:
1208 src_components = num_components;
1209 break;
1210 }
1211 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1212 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1213
1214 switch (instr->op) {
1215 case nir_op_fmov:
1216 case nir_op_imov:
1217 result = src[0];
1218 break;
1219 case nir_op_fneg:
1220 src[0] = to_float(ctx, src[0]);
1221 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1222 break;
1223 case nir_op_ineg:
1224 result = LLVMBuildNeg(ctx->builder, src[0], "");
1225 break;
1226 case nir_op_inot:
1227 result = LLVMBuildNot(ctx->builder, src[0], "");
1228 break;
1229 case nir_op_iadd:
1230 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1231 break;
1232 case nir_op_fadd:
1233 src[0] = to_float(ctx, src[0]);
1234 src[1] = to_float(ctx, src[1]);
1235 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1236 break;
1237 case nir_op_fsub:
1238 src[0] = to_float(ctx, src[0]);
1239 src[1] = to_float(ctx, src[1]);
1240 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1241 break;
1242 case nir_op_isub:
1243 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1244 break;
1245 case nir_op_imul:
1246 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1247 break;
1248 case nir_op_imod:
1249 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1250 break;
1251 case nir_op_umod:
1252 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1253 break;
1254 case nir_op_fmod:
1255 src[0] = to_float(ctx, src[0]);
1256 src[1] = to_float(ctx, src[1]);
1257 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1258 result = emit_intrin_1f_param(ctx, "llvm.floor",
1259 to_float_type(ctx, def_type), result);
1260 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1261 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1262 break;
1263 case nir_op_frem:
1264 src[0] = to_float(ctx, src[0]);
1265 src[1] = to_float(ctx, src[1]);
1266 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1267 break;
1268 case nir_op_irem:
1269 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1270 break;
1271 case nir_op_idiv:
1272 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1273 break;
1274 case nir_op_udiv:
1275 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1276 break;
1277 case nir_op_fmul:
1278 src[0] = to_float(ctx, src[0]);
1279 src[1] = to_float(ctx, src[1]);
1280 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1281 break;
1282 case nir_op_fdiv:
1283 src[0] = to_float(ctx, src[0]);
1284 src[1] = to_float(ctx, src[1]);
1285 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1286 break;
1287 case nir_op_frcp:
1288 src[0] = to_float(ctx, src[0]);
1289 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1290 break;
1291 case nir_op_iand:
1292 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1293 break;
1294 case nir_op_ior:
1295 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1296 break;
1297 case nir_op_ixor:
1298 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1299 break;
1300 case nir_op_ishl:
1301 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1302 break;
1303 case nir_op_ishr:
1304 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1305 break;
1306 case nir_op_ushr:
1307 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1308 break;
1309 case nir_op_ilt:
1310 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1311 break;
1312 case nir_op_ine:
1313 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1314 break;
1315 case nir_op_ieq:
1316 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1317 break;
1318 case nir_op_ige:
1319 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1320 break;
1321 case nir_op_ult:
1322 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1323 break;
1324 case nir_op_uge:
1325 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1326 break;
1327 case nir_op_feq:
1328 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1329 break;
1330 case nir_op_fne:
1331 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1332 break;
1333 case nir_op_flt:
1334 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1335 break;
1336 case nir_op_fge:
1337 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1338 break;
1339 case nir_op_fabs:
1340 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1341 to_float_type(ctx, def_type), src[0]);
1342 break;
1343 case nir_op_iabs:
1344 result = emit_iabs(ctx, src[0]);
1345 break;
1346 case nir_op_imax:
1347 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1348 break;
1349 case nir_op_imin:
1350 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1351 break;
1352 case nir_op_umax:
1353 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1354 break;
1355 case nir_op_umin:
1356 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1357 break;
1358 case nir_op_isign:
1359 result = emit_isign(ctx, src[0]);
1360 break;
1361 case nir_op_fsign:
1362 src[0] = to_float(ctx, src[0]);
1363 result = emit_fsign(ctx, src[0]);
1364 break;
1365 case nir_op_ffloor:
1366 result = emit_intrin_1f_param(ctx, "llvm.floor",
1367 to_float_type(ctx, def_type), src[0]);
1368 break;
1369 case nir_op_ftrunc:
1370 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1371 to_float_type(ctx, def_type), src[0]);
1372 break;
1373 case nir_op_fceil:
1374 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1375 to_float_type(ctx, def_type), src[0]);
1376 break;
1377 case nir_op_fround_even:
1378 result = emit_intrin_1f_param(ctx, "llvm.rint",
1379 to_float_type(ctx, def_type),src[0]);
1380 break;
1381 case nir_op_ffract:
1382 result = emit_ffract(ctx, src[0]);
1383 break;
1384 case nir_op_fsin:
1385 result = emit_intrin_1f_param(ctx, "llvm.sin",
1386 to_float_type(ctx, def_type), src[0]);
1387 break;
1388 case nir_op_fcos:
1389 result = emit_intrin_1f_param(ctx, "llvm.cos",
1390 to_float_type(ctx, def_type), src[0]);
1391 break;
1392 case nir_op_fsqrt:
1393 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1394 to_float_type(ctx, def_type), src[0]);
1395 break;
1396 case nir_op_fexp2:
1397 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1398 to_float_type(ctx, def_type), src[0]);
1399 break;
1400 case nir_op_flog2:
1401 result = emit_intrin_1f_param(ctx, "llvm.log2",
1402 to_float_type(ctx, def_type), src[0]);
1403 break;
1404 case nir_op_frsq:
1405 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1406 to_float_type(ctx, def_type), src[0]);
1407 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1408 break;
1409 case nir_op_fpow:
1410 result = emit_intrin_2f_param(ctx, "llvm.pow",
1411 to_float_type(ctx, def_type), src[0], src[1]);
1412 break;
1413 case nir_op_fmax:
1414 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1415 to_float_type(ctx, def_type), src[0], src[1]);
1416 break;
1417 case nir_op_fmin:
1418 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1419 to_float_type(ctx, def_type), src[0], src[1]);
1420 break;
1421 case nir_op_ffma:
1422 result = emit_intrin_3f_param(ctx, "llvm.fma",
1423 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1424 break;
1425 case nir_op_ibitfield_extract:
1426 result = emit_bitfield_extract(ctx, true, src);
1427 break;
1428 case nir_op_ubitfield_extract:
1429 result = emit_bitfield_extract(ctx, false, src);
1430 break;
1431 case nir_op_bitfield_insert:
1432 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1433 break;
1434 case nir_op_bitfield_reverse:
1435 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1436 break;
1437 case nir_op_bit_count:
1438 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1439 break;
1440 case nir_op_vec2:
1441 case nir_op_vec3:
1442 case nir_op_vec4:
1443 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1444 src[i] = to_integer(ctx, src[i]);
1445 result = ac_build_gather_values(&ctx->ac, src, num_components);
1446 break;
1447 case nir_op_f2i32:
1448 case nir_op_f2i64:
1449 src[0] = to_float(ctx, src[0]);
1450 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1451 break;
1452 case nir_op_f2u32:
1453 case nir_op_f2u64:
1454 src[0] = to_float(ctx, src[0]);
1455 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1456 break;
1457 case nir_op_i2f32:
1458 case nir_op_i2f64:
1459 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1460 break;
1461 case nir_op_u2f32:
1462 case nir_op_u2f64:
1463 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1464 break;
1465 case nir_op_f2f64:
1466 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1467 break;
1468 case nir_op_f2f32:
1469 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1470 break;
1471 case nir_op_u2u32:
1472 case nir_op_u2u64:
1473 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1474 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1475 else
1476 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1477 break;
1478 case nir_op_i2i32:
1479 case nir_op_i2i64:
1480 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1481 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1482 else
1483 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1484 break;
1485 case nir_op_bcsel:
1486 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1487 break;
1488 case nir_op_find_lsb:
1489 result = emit_find_lsb(ctx, src[0]);
1490 break;
1491 case nir_op_ufind_msb:
1492 result = emit_ufind_msb(ctx, src[0]);
1493 break;
1494 case nir_op_ifind_msb:
1495 result = emit_ifind_msb(ctx, src[0]);
1496 break;
1497 case nir_op_uadd_carry:
1498 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1499 break;
1500 case nir_op_usub_borrow:
1501 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1502 break;
1503 case nir_op_b2f:
1504 result = emit_b2f(ctx, src[0]);
1505 break;
1506 case nir_op_fquantize2f16:
1507 src[0] = to_float(ctx, src[0]);
1508 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1509 /* need to convert back up to f32 */
1510 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1511 break;
1512 case nir_op_umul_high:
1513 result = emit_umul_high(ctx, src[0], src[1]);
1514 break;
1515 case nir_op_imul_high:
1516 result = emit_imul_high(ctx, src[0], src[1]);
1517 break;
1518 case nir_op_pack_half_2x16:
1519 result = emit_pack_half_2x16(ctx, src[0]);
1520 break;
1521 case nir_op_unpack_half_2x16:
1522 result = emit_unpack_half_2x16(ctx, src[0]);
1523 break;
1524 case nir_op_fddx:
1525 case nir_op_fddy:
1526 case nir_op_fddx_fine:
1527 case nir_op_fddy_fine:
1528 case nir_op_fddx_coarse:
1529 case nir_op_fddy_coarse:
1530 result = emit_ddxy(ctx, instr->op, src[0]);
1531 break;
1532 default:
1533 fprintf(stderr, "Unknown NIR alu instr: ");
1534 nir_print_instr(&instr->instr, stderr);
1535 fprintf(stderr, "\n");
1536 abort();
1537 }
1538
1539 if (result) {
1540 assert(instr->dest.dest.is_ssa);
1541 result = to_integer(ctx, result);
1542 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1543 result);
1544 }
1545 }
1546
1547 static void visit_load_const(struct nir_to_llvm_context *ctx,
1548 nir_load_const_instr *instr)
1549 {
1550 LLVMValueRef values[4], value = NULL;
1551 LLVMTypeRef element_type =
1552 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1553
1554 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1555 switch (instr->def.bit_size) {
1556 case 32:
1557 values[i] = LLVMConstInt(element_type,
1558 instr->value.u32[i], false);
1559 break;
1560 case 64:
1561 values[i] = LLVMConstInt(element_type,
1562 instr->value.u64[i], false);
1563 break;
1564 default:
1565 fprintf(stderr,
1566 "unsupported nir load_const bit_size: %d\n",
1567 instr->def.bit_size);
1568 abort();
1569 }
1570 }
1571 if (instr->def.num_components > 1) {
1572 value = LLVMConstVector(values, instr->def.num_components);
1573 } else
1574 value = values[0];
1575
1576 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1577 }
1578
1579 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1580 LLVMTypeRef type)
1581 {
1582 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1583 return LLVMBuildBitCast(ctx->builder, ptr,
1584 LLVMPointerType(type, addr_space), "");
1585 }
1586
1587 static LLVMValueRef
1588 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1589 {
1590 LLVMValueRef size =
1591 LLVMBuildExtractElement(ctx->builder, descriptor,
1592 LLVMConstInt(ctx->i32, 2, false), "");
1593
1594 /* VI only */
1595 if (ctx->options->chip_class >= VI && in_elements) {
1596 /* On VI, the descriptor contains the size in bytes,
1597 * but TXQ must return the size in elements.
1598 * The stride is always non-zero for resources using TXQ.
1599 */
1600 LLVMValueRef stride =
1601 LLVMBuildExtractElement(ctx->builder, descriptor,
1602 LLVMConstInt(ctx->i32, 1, false), "");
1603 stride = LLVMBuildLShr(ctx->builder, stride,
1604 LLVMConstInt(ctx->i32, 16, false), "");
1605 stride = LLVMBuildAnd(ctx->builder, stride,
1606 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1607
1608 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1609 }
1610 return size;
1611 }
1612
1613 /**
1614 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1615 * intrinsic names).
1616 */
1617 static void build_int_type_name(
1618 LLVMTypeRef type,
1619 char *buf, unsigned bufsize)
1620 {
1621 assert(bufsize >= 6);
1622
1623 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1624 snprintf(buf, bufsize, "v%ui32",
1625 LLVMGetVectorSize(type));
1626 else
1627 strcpy(buf, "i32");
1628 }
1629
1630 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1631 struct ac_image_args *args,
1632 nir_tex_instr *instr)
1633 {
1634 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1635 LLVMValueRef coord = args->addr;
1636 LLVMValueRef half_texel[2];
1637 LLVMValueRef compare_cube_wa;
1638 LLVMValueRef result;
1639 int c;
1640 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1641
1642 //TODO Rect
1643 {
1644 struct ac_image_args txq_args = { 0 };
1645
1646 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1647 txq_args.opcode = ac_image_get_resinfo;
1648 txq_args.dmask = 0xf;
1649 txq_args.addr = ctx->i32zero;
1650 txq_args.resource = args->resource;
1651 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1652
1653 for (c = 0; c < 2; c++) {
1654 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1655 LLVMConstInt(ctx->i32, c, false), "");
1656 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1657 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1658 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1659 LLVMConstReal(ctx->f32, -0.5), "");
1660 }
1661 }
1662
1663 LLVMValueRef orig_coords = args->addr;
1664
1665 for (c = 0; c < 2; c++) {
1666 LLVMValueRef tmp;
1667 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1668 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1669 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1670 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1671 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1672 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1673 }
1674
1675
1676 /*
1677 * Apparantly cube has issue with integer types that the workaround doesn't solve,
1678 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
1679 * workaround by sampling using a scaled type and converting.
1680 * This is taken from amdgpu-pro shaders.
1681 */
1682 /* NOTE this produces some ugly code compared to amdgpu-pro,
1683 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
1684 * and then reads them back. -pro generates two selects,
1685 * one s_cmp for the descriptor rewriting
1686 * one v_cmp for the coordinate and result changes.
1687 */
1688 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1689 LLVMValueRef tmp, tmp2;
1690
1691 /* workaround 8/8/8/8 uint/sint cube gather bug */
1692 /* first detect it then change to a scaled read and f2i */
1693 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
1694 tmp2 = tmp;
1695
1696 /* extract the DATA_FORMAT */
1697 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
1698 LLVMConstInt(ctx->i32, 6, false), false);
1699
1700 /* is the DATA_FORMAT == 8_8_8_8 */
1701 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
1702
1703 if (stype == GLSL_TYPE_UINT)
1704 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
1705 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
1706 LLVMConstInt(ctx->i32, 0x10000000, false), "");
1707 else
1708 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
1709 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
1710 LLVMConstInt(ctx->i32, 0x14000000, false), "");
1711
1712 /* replace the NUM FORMAT in the descriptor */
1713 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT, false), "");
1714 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
1715
1716 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
1717
1718 /* don't modify the coordinates for this case */
1719 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
1720 }
1721 args->addr = coord;
1722 result = ac_build_image_opcode(&ctx->ac, args);
1723
1724 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1725 LLVMValueRef tmp, tmp2;
1726
1727 /* if the cube workaround is in place, f2i the result. */
1728 for (c = 0; c < 4; c++) {
1729 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
1730 if (stype == GLSL_TYPE_UINT)
1731 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
1732 else
1733 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
1734 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1735 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
1736 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
1737 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1738 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
1739 }
1740 }
1741 return result;
1742 }
1743
1744 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1745 nir_tex_instr *instr,
1746 struct ac_image_args *args)
1747 {
1748 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
1749 return ac_build_buffer_load_format(&ctx->ac,
1750 args->resource,
1751 args->addr,
1752 LLVMConstInt(ctx->i32, 0, false),
1753 true);
1754 }
1755
1756 args->opcode = ac_image_sample;
1757 args->compare = instr->is_shadow;
1758
1759 switch (instr->op) {
1760 case nir_texop_txf:
1761 case nir_texop_txf_ms:
1762 case nir_texop_samples_identical:
1763 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
1764 args->compare = false;
1765 args->offset = false;
1766 break;
1767 case nir_texop_txb:
1768 args->bias = true;
1769 break;
1770 case nir_texop_txl:
1771 args->lod = true;
1772 break;
1773 case nir_texop_txs:
1774 case nir_texop_query_levels:
1775 args->opcode = ac_image_get_resinfo;
1776 break;
1777 case nir_texop_tex:
1778 if (ctx->stage != MESA_SHADER_FRAGMENT)
1779 args->level_zero = true;
1780 break;
1781 case nir_texop_txd:
1782 args->deriv = true;
1783 break;
1784 case nir_texop_tg4:
1785 args->opcode = ac_image_gather4;
1786 args->level_zero = true;
1787 break;
1788 case nir_texop_lod:
1789 args->opcode = ac_image_get_lod;
1790 args->compare = false;
1791 args->offset = false;
1792 break;
1793 default:
1794 break;
1795 }
1796
1797 if (instr->op == nir_texop_tg4) {
1798 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1799 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1800 return radv_lower_gather4_integer(ctx, args, instr);
1801 }
1802 }
1803 return ac_build_image_opcode(&ctx->ac, args);
1804 }
1805
1806 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1807 nir_intrinsic_instr *instr)
1808 {
1809 LLVMValueRef index = get_src(ctx, instr->src[0]);
1810 unsigned desc_set = nir_intrinsic_desc_set(instr);
1811 unsigned binding = nir_intrinsic_binding(instr);
1812 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1813 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1814 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1815 unsigned base_offset = layout->binding[binding].offset;
1816 LLVMValueRef offset, stride;
1817
1818 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1819 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1820 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1821 layout->binding[binding].dynamic_offset_offset;
1822 desc_ptr = ctx->push_constants;
1823 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1824 stride = LLVMConstInt(ctx->i32, 16, false);
1825 } else
1826 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1827
1828 offset = LLVMConstInt(ctx->i32, base_offset, false);
1829 index = LLVMBuildMul(ctx->builder, index, stride, "");
1830 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1831
1832 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1833 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1834 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1835
1836 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1837 }
1838
1839 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1840 nir_intrinsic_instr *instr)
1841 {
1842 LLVMValueRef ptr, addr;
1843
1844 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1845 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1846
1847 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1848 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1849
1850 return LLVMBuildLoad(ctx->builder, ptr, "");
1851 }
1852
1853 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1854 nir_intrinsic_instr *instr)
1855 {
1856 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1857
1858 return get_buffer_size(ctx, desc, false);
1859 }
1860 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1861 nir_intrinsic_instr *instr)
1862 {
1863 const char *store_name;
1864 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1865 LLVMTypeRef data_type = ctx->f32;
1866 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1867 int components_32bit = elem_size_mult * instr->num_components;
1868 unsigned writemask = nir_intrinsic_write_mask(instr);
1869 LLVMValueRef base_data, base_offset;
1870 LLVMValueRef params[6];
1871
1872 if (ctx->stage == MESA_SHADER_FRAGMENT)
1873 ctx->shader_info->fs.writes_memory = true;
1874
1875 params[1] = get_src(ctx, instr->src[1]);
1876 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1877 params[4] = ctx->i1false; /* glc */
1878 params[5] = ctx->i1false; /* slc */
1879
1880 if (components_32bit > 1)
1881 data_type = LLVMVectorType(ctx->f32, components_32bit);
1882
1883 base_data = to_float(ctx, src_data);
1884 base_data = trim_vector(ctx, base_data, instr->num_components);
1885 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1886 data_type, "");
1887 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1888 while (writemask) {
1889 int start, count;
1890 LLVMValueRef data;
1891 LLVMValueRef offset;
1892 LLVMValueRef tmp;
1893 u_bit_scan_consecutive_range(&writemask, &start, &count);
1894
1895 /* Due to an LLVM limitation, split 3-element writes
1896 * into a 2-element and a 1-element write. */
1897 if (count == 3) {
1898 writemask |= 1 << (start + 2);
1899 count = 2;
1900 }
1901
1902 start *= elem_size_mult;
1903 count *= elem_size_mult;
1904
1905 if (count > 4) {
1906 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1907 count = 4;
1908 }
1909
1910 if (count == 4) {
1911 store_name = "llvm.amdgcn.buffer.store.v4f32";
1912 data = base_data;
1913 } else if (count == 2) {
1914 tmp = LLVMBuildExtractElement(ctx->builder,
1915 base_data, LLVMConstInt(ctx->i32, start, false), "");
1916 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1917 ctx->i32zero, "");
1918
1919 tmp = LLVMBuildExtractElement(ctx->builder,
1920 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1921 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1922 ctx->i32one, "");
1923 store_name = "llvm.amdgcn.buffer.store.v2f32";
1924
1925 } else {
1926 assert(count == 1);
1927 if (get_llvm_num_components(base_data) > 1)
1928 data = LLVMBuildExtractElement(ctx->builder, base_data,
1929 LLVMConstInt(ctx->i32, start, false), "");
1930 else
1931 data = base_data;
1932 store_name = "llvm.amdgcn.buffer.store.f32";
1933 }
1934
1935 offset = base_offset;
1936 if (start != 0) {
1937 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1938 }
1939 params[0] = data;
1940 params[3] = offset;
1941 ac_build_intrinsic(&ctx->ac, store_name,
1942 ctx->voidt, params, 6, 0);
1943 }
1944 }
1945
1946 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1947 nir_intrinsic_instr *instr)
1948 {
1949 const char *name;
1950 LLVMValueRef params[6];
1951 int arg_count = 0;
1952 if (ctx->stage == MESA_SHADER_FRAGMENT)
1953 ctx->shader_info->fs.writes_memory = true;
1954
1955 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1956 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1957 }
1958 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1959 params[arg_count++] = get_src(ctx, instr->src[0]);
1960 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1961 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1962 params[arg_count++] = ctx->i1false; /* slc */
1963
1964 switch (instr->intrinsic) {
1965 case nir_intrinsic_ssbo_atomic_add:
1966 name = "llvm.amdgcn.buffer.atomic.add";
1967 break;
1968 case nir_intrinsic_ssbo_atomic_imin:
1969 name = "llvm.amdgcn.buffer.atomic.smin";
1970 break;
1971 case nir_intrinsic_ssbo_atomic_umin:
1972 name = "llvm.amdgcn.buffer.atomic.umin";
1973 break;
1974 case nir_intrinsic_ssbo_atomic_imax:
1975 name = "llvm.amdgcn.buffer.atomic.smax";
1976 break;
1977 case nir_intrinsic_ssbo_atomic_umax:
1978 name = "llvm.amdgcn.buffer.atomic.umax";
1979 break;
1980 case nir_intrinsic_ssbo_atomic_and:
1981 name = "llvm.amdgcn.buffer.atomic.and";
1982 break;
1983 case nir_intrinsic_ssbo_atomic_or:
1984 name = "llvm.amdgcn.buffer.atomic.or";
1985 break;
1986 case nir_intrinsic_ssbo_atomic_xor:
1987 name = "llvm.amdgcn.buffer.atomic.xor";
1988 break;
1989 case nir_intrinsic_ssbo_atomic_exchange:
1990 name = "llvm.amdgcn.buffer.atomic.swap";
1991 break;
1992 case nir_intrinsic_ssbo_atomic_comp_swap:
1993 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1994 break;
1995 default:
1996 abort();
1997 }
1998
1999 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2000 }
2001
2002 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2003 nir_intrinsic_instr *instr)
2004 {
2005 LLVMValueRef results[2];
2006 int load_components;
2007 int num_components = instr->num_components;
2008 if (instr->dest.ssa.bit_size == 64)
2009 num_components *= 2;
2010
2011 for (int i = 0; i < num_components; i += load_components) {
2012 load_components = MIN2(num_components - i, 4);
2013 const char *load_name;
2014 LLVMTypeRef data_type = ctx->f32;
2015 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2016 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2017
2018 if (load_components == 3)
2019 data_type = LLVMVectorType(ctx->f32, 4);
2020 else if (load_components > 1)
2021 data_type = LLVMVectorType(ctx->f32, load_components);
2022
2023 if (load_components >= 3)
2024 load_name = "llvm.amdgcn.buffer.load.v4f32";
2025 else if (load_components == 2)
2026 load_name = "llvm.amdgcn.buffer.load.v2f32";
2027 else if (load_components == 1)
2028 load_name = "llvm.amdgcn.buffer.load.f32";
2029 else
2030 unreachable("unhandled number of components");
2031
2032 LLVMValueRef params[] = {
2033 get_src(ctx, instr->src[0]),
2034 LLVMConstInt(ctx->i32, 0, false),
2035 offset,
2036 ctx->i1false,
2037 ctx->i1false,
2038 };
2039
2040 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2041
2042 }
2043
2044 LLVMValueRef ret = results[0];
2045 if (num_components > 4 || num_components == 3) {
2046 LLVMValueRef masks[] = {
2047 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2048 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2049 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2050 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2051 };
2052
2053 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2054 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2055 results[num_components > 4 ? 1 : 0], swizzle, "");
2056 }
2057
2058 return LLVMBuildBitCast(ctx->builder, ret,
2059 get_def_type(ctx, &instr->dest.ssa), "");
2060 }
2061
2062 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2063 nir_intrinsic_instr *instr)
2064 {
2065 LLVMValueRef results[8], ret;
2066 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2067 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2068 int num_components = instr->num_components;
2069
2070 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2071
2072 if (instr->dest.ssa.bit_size == 64)
2073 num_components *= 2;
2074
2075 for (unsigned i = 0; i < num_components; ++i) {
2076 LLVMValueRef params[] = {
2077 rsrc,
2078 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2079 offset, "")
2080 };
2081 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2082 params, 2,
2083 AC_FUNC_ATTR_READNONE |
2084 AC_FUNC_ATTR_LEGACY);
2085 }
2086
2087
2088 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2089 return LLVMBuildBitCast(ctx->builder, ret,
2090 get_def_type(ctx, &instr->dest.ssa), "");
2091 }
2092
2093 static void
2094 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2095 bool vs_in, unsigned *vertex_index_out,
2096 unsigned *const_out, LLVMValueRef *indir_out)
2097 {
2098 unsigned const_offset = 0;
2099 LLVMValueRef offset = NULL;
2100
2101 if (vertex_index_out != NULL) {
2102 tail = tail->child;
2103 nir_deref_array *deref_array = nir_deref_as_array(tail);
2104 *vertex_index_out = deref_array->base_offset;
2105 }
2106
2107 while (tail->child != NULL) {
2108 const struct glsl_type *parent_type = tail->type;
2109 tail = tail->child;
2110
2111 if (tail->deref_type == nir_deref_type_array) {
2112 nir_deref_array *deref_array = nir_deref_as_array(tail);
2113 LLVMValueRef index, stride, local_offset;
2114 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2115
2116 const_offset += size * deref_array->base_offset;
2117 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2118 continue;
2119
2120 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2121 index = get_src(ctx, deref_array->indirect);
2122 stride = LLVMConstInt(ctx->i32, size, 0);
2123 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2124
2125 if (offset)
2126 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2127 else
2128 offset = local_offset;
2129 } else if (tail->deref_type == nir_deref_type_struct) {
2130 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2131
2132 for (unsigned i = 0; i < deref_struct->index; i++) {
2133 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2134 const_offset += glsl_count_attribute_slots(ft, vs_in);
2135 }
2136 } else
2137 unreachable("unsupported deref type");
2138
2139 }
2140
2141 if (const_offset && offset)
2142 offset = LLVMBuildAdd(ctx->builder, offset,
2143 LLVMConstInt(ctx->i32, const_offset, 0),
2144 "");
2145
2146 *const_out = const_offset;
2147 *indir_out = offset;
2148 }
2149
2150 static LLVMValueRef
2151 load_gs_input(struct nir_to_llvm_context *ctx,
2152 nir_intrinsic_instr *instr)
2153 {
2154 LLVMValueRef indir_index, vtx_offset;
2155 unsigned const_index;
2156 LLVMValueRef args[9];
2157 unsigned param, vtx_offset_param;
2158 LLVMValueRef value[4], result;
2159 unsigned vertex_index;
2160 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2161 false, &vertex_index,
2162 &const_index, &indir_index);
2163 vtx_offset_param = vertex_index;
2164 assert(vtx_offset_param < 6);
2165 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2166 LLVMConstInt(ctx->i32, 4, false), "");
2167
2168 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2169 for (unsigned i = 0; i < instr->num_components; i++) {
2170
2171 args[0] = ctx->esgs_ring;
2172 args[1] = vtx_offset;
2173 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2174 args[3] = ctx->i32zero;
2175 args[4] = ctx->i32one; /* OFFEN */
2176 args[5] = ctx->i32zero; /* IDXEN */
2177 args[6] = ctx->i32one; /* GLC */
2178 args[7] = ctx->i32zero; /* SLC */
2179 args[8] = ctx->i32zero; /* TFE */
2180
2181 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2182 ctx->i32, args, 9,
2183 AC_FUNC_ATTR_READONLY |
2184 AC_FUNC_ATTR_LEGACY);
2185 }
2186 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2187
2188 return result;
2189 }
2190
2191 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2192 nir_intrinsic_instr *instr)
2193 {
2194 LLVMValueRef values[8];
2195 int idx = instr->variables[0]->var->data.driver_location;
2196 int ve = instr->dest.ssa.num_components;
2197 LLVMValueRef indir_index;
2198 LLVMValueRef ret;
2199 unsigned const_index;
2200 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2201 instr->variables[0]->var->data.mode == nir_var_shader_in;
2202 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2203 &const_index, &indir_index);
2204
2205 if (instr->dest.ssa.bit_size == 64)
2206 ve *= 2;
2207
2208 switch (instr->variables[0]->var->data.mode) {
2209 case nir_var_shader_in:
2210 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2211 return load_gs_input(ctx, instr);
2212 }
2213 for (unsigned chan = 0; chan < ve; chan++) {
2214 if (indir_index) {
2215 unsigned count = glsl_count_attribute_slots(
2216 instr->variables[0]->var->type,
2217 ctx->stage == MESA_SHADER_VERTEX);
2218 count -= chan / 4;
2219 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2220 &ctx->ac, ctx->inputs + idx + chan, count,
2221 4, false);
2222
2223 values[chan] = LLVMBuildExtractElement(ctx->builder,
2224 tmp_vec,
2225 indir_index, "");
2226 } else
2227 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2228 }
2229 break;
2230 case nir_var_local:
2231 for (unsigned chan = 0; chan < ve; chan++) {
2232 if (indir_index) {
2233 unsigned count = glsl_count_attribute_slots(
2234 instr->variables[0]->var->type, false);
2235 count -= chan / 4;
2236 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2237 &ctx->ac, ctx->locals + idx + chan, count,
2238 4, true);
2239
2240 values[chan] = LLVMBuildExtractElement(ctx->builder,
2241 tmp_vec,
2242 indir_index, "");
2243 } else {
2244 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2245 }
2246 }
2247 break;
2248 case nir_var_shader_out:
2249 for (unsigned chan = 0; chan < ve; chan++) {
2250 if (indir_index) {
2251 unsigned count = glsl_count_attribute_slots(
2252 instr->variables[0]->var->type, false);
2253 count -= chan / 4;
2254 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2255 &ctx->ac, ctx->outputs + idx + chan, count,
2256 4, true);
2257
2258 values[chan] = LLVMBuildExtractElement(ctx->builder,
2259 tmp_vec,
2260 indir_index, "");
2261 } else {
2262 values[chan] = LLVMBuildLoad(ctx->builder,
2263 ctx->outputs[idx + chan + const_index * 4],
2264 "");
2265 }
2266 }
2267 break;
2268 case nir_var_shared: {
2269 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2270 LLVMValueRef derived_ptr;
2271
2272 if (indir_index)
2273 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2274
2275 for (unsigned chan = 0; chan < ve; chan++) {
2276 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2277 if (indir_index)
2278 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2279 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2280
2281 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2282 }
2283 break;
2284 }
2285 default:
2286 unreachable("unhandle variable mode");
2287 }
2288 ret = ac_build_gather_values(&ctx->ac, values, ve);
2289 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2290 }
2291
2292 static void
2293 visit_store_var(struct nir_to_llvm_context *ctx,
2294 nir_intrinsic_instr *instr)
2295 {
2296 LLVMValueRef temp_ptr, value;
2297 int idx = instr->variables[0]->var->data.driver_location;
2298 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2299 int writemask = instr->const_index[0];
2300 LLVMValueRef indir_index;
2301 unsigned const_index;
2302 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2303 NULL, &const_index, &indir_index);
2304
2305 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2306 int old_writemask = writemask;
2307
2308 src = LLVMBuildBitCast(ctx->builder, src,
2309 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2310 "");
2311
2312 writemask = 0;
2313 for (unsigned chan = 0; chan < 4; chan++) {
2314 if (old_writemask & (1 << chan))
2315 writemask |= 3u << (2 * chan);
2316 }
2317 }
2318
2319 switch (instr->variables[0]->var->data.mode) {
2320 case nir_var_shader_out:
2321 for (unsigned chan = 0; chan < 8; chan++) {
2322 int stride = 4;
2323 if (!(writemask & (1 << chan)))
2324 continue;
2325
2326 value = llvm_extract_elem(ctx, src, chan);
2327
2328 if (instr->variables[0]->var->data.compact)
2329 stride = 1;
2330 if (indir_index) {
2331 unsigned count = glsl_count_attribute_slots(
2332 instr->variables[0]->var->type, false);
2333 count -= chan / 4;
2334 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2335 &ctx->ac, ctx->outputs + idx + chan, count,
2336 stride, true);
2337
2338 if (get_llvm_num_components(tmp_vec) > 1) {
2339 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2340 value, indir_index, "");
2341 } else
2342 tmp_vec = value;
2343 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2344 count, stride, tmp_vec);
2345
2346 } else {
2347 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2348
2349 LLVMBuildStore(ctx->builder, value, temp_ptr);
2350 }
2351 }
2352 break;
2353 case nir_var_local:
2354 for (unsigned chan = 0; chan < 8; chan++) {
2355 if (!(writemask & (1 << chan)))
2356 continue;
2357
2358 value = llvm_extract_elem(ctx, src, chan);
2359 if (indir_index) {
2360 unsigned count = glsl_count_attribute_slots(
2361 instr->variables[0]->var->type, false);
2362 count -= chan / 4;
2363 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2364 &ctx->ac, ctx->locals + idx + chan, count,
2365 4, true);
2366
2367 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2368 value, indir_index, "");
2369 build_store_values_extended(ctx, ctx->locals + idx + chan,
2370 count, 4, tmp_vec);
2371 } else {
2372 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2373
2374 LLVMBuildStore(ctx->builder, value, temp_ptr);
2375 }
2376 }
2377 break;
2378 case nir_var_shared: {
2379 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2380
2381 if (indir_index)
2382 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2383
2384 for (unsigned chan = 0; chan < 8; chan++) {
2385 if (!(writemask & (1 << chan)))
2386 continue;
2387 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2388 LLVMValueRef derived_ptr;
2389
2390 if (indir_index)
2391 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2392
2393 value = llvm_extract_elem(ctx, src, chan);
2394 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2395 LLVMBuildStore(ctx->builder,
2396 to_integer(ctx, value), derived_ptr);
2397 }
2398 break;
2399 }
2400 default:
2401 break;
2402 }
2403 }
2404
2405 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2406 {
2407 switch (dim) {
2408 case GLSL_SAMPLER_DIM_BUF:
2409 return 1;
2410 case GLSL_SAMPLER_DIM_1D:
2411 return array ? 2 : 1;
2412 case GLSL_SAMPLER_DIM_2D:
2413 return array ? 3 : 2;
2414 case GLSL_SAMPLER_DIM_MS:
2415 return array ? 4 : 3;
2416 case GLSL_SAMPLER_DIM_3D:
2417 case GLSL_SAMPLER_DIM_CUBE:
2418 return 3;
2419 case GLSL_SAMPLER_DIM_RECT:
2420 case GLSL_SAMPLER_DIM_SUBPASS:
2421 return 2;
2422 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2423 return 3;
2424 default:
2425 break;
2426 }
2427 return 0;
2428 }
2429
2430
2431
2432 /* Adjust the sample index according to FMASK.
2433 *
2434 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2435 * which is the identity mapping. Each nibble says which physical sample
2436 * should be fetched to get that sample.
2437 *
2438 * For example, 0x11111100 means there are only 2 samples stored and
2439 * the second sample covers 3/4 of the pixel. When reading samples 0
2440 * and 1, return physical sample 0 (determined by the first two 0s
2441 * in FMASK), otherwise return physical sample 1.
2442 *
2443 * The sample index should be adjusted as follows:
2444 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2445 */
2446 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
2447 LLVMValueRef coord_x, LLVMValueRef coord_y,
2448 LLVMValueRef coord_z,
2449 LLVMValueRef sample_index,
2450 LLVMValueRef fmask_desc_ptr)
2451 {
2452 LLVMValueRef fmask_load_address[4];
2453 LLVMValueRef res;
2454
2455 fmask_load_address[0] = coord_x;
2456 fmask_load_address[1] = coord_y;
2457 if (coord_z) {
2458 fmask_load_address[2] = coord_z;
2459 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
2460 }
2461
2462 struct ac_image_args args = {0};
2463
2464 args.opcode = ac_image_load;
2465 args.da = coord_z ? true : false;
2466 args.resource = fmask_desc_ptr;
2467 args.dmask = 0xf;
2468 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
2469
2470 res = ac_build_image_opcode(&ctx->ac, &args);
2471
2472 res = to_integer(ctx, res);
2473 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
2474 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
2475
2476 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
2477 res,
2478 ctx->i32zero, "");
2479
2480 LLVMValueRef sample_index4 =
2481 LLVMBuildMul(ctx->builder, sample_index, four, "");
2482 LLVMValueRef shifted_fmask =
2483 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
2484 LLVMValueRef final_sample =
2485 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
2486
2487 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2488 * resource descriptor is 0 (invalid),
2489 */
2490 LLVMValueRef fmask_desc =
2491 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
2492 ctx->v8i32, "");
2493
2494 LLVMValueRef fmask_word1 =
2495 LLVMBuildExtractElement(ctx->builder, fmask_desc,
2496 ctx->i32one, "");
2497
2498 LLVMValueRef word1_is_nonzero =
2499 LLVMBuildICmp(ctx->builder, LLVMIntNE,
2500 fmask_word1, ctx->i32zero, "");
2501
2502 /* Replace the MSAA sample index. */
2503 sample_index =
2504 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
2505 final_sample, sample_index, "");
2506 return sample_index;
2507 }
2508
2509 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2510 nir_intrinsic_instr *instr)
2511 {
2512 const struct glsl_type *type = instr->variables[0]->var->type;
2513 if(instr->variables[0]->deref.child)
2514 type = instr->variables[0]->deref.child->type;
2515
2516 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2517 LLVMValueRef coords[4];
2518 LLVMValueRef masks[] = {
2519 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2520 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2521 };
2522 LLVMValueRef res;
2523 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2524
2525 int count;
2526 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2527 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2528 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2529 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2530 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2531
2532 count = image_type_to_components_count(dim,
2533 glsl_sampler_type_is_array(type));
2534
2535 if (is_ms) {
2536 LLVMValueRef fmask_load_address[3];
2537 int chan;
2538
2539 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2540 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
2541 if (glsl_sampler_type_is_array(type))
2542 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
2543 else
2544 fmask_load_address[2] = NULL;
2545 if (add_frag_pos) {
2546 for (chan = 0; chan < 2; ++chan)
2547 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2548 }
2549 sample_index = adjust_sample_index_using_fmask(ctx,
2550 fmask_load_address[0],
2551 fmask_load_address[1],
2552 fmask_load_address[2],
2553 sample_index,
2554 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
2555 }
2556 if (count == 1) {
2557 if (instr->src[0].ssa->num_components)
2558 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2559 else
2560 res = src0;
2561 } else {
2562 int chan;
2563 if (is_ms)
2564 count--;
2565 for (chan = 0; chan < count; ++chan) {
2566 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2567 }
2568
2569 if (add_frag_pos) {
2570 for (chan = 0; chan < count; ++chan)
2571 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2572 }
2573 if (is_ms) {
2574 coords[count] = sample_index;
2575 count++;
2576 }
2577
2578 if (count == 3) {
2579 coords[3] = LLVMGetUndef(ctx->i32);
2580 count = 4;
2581 }
2582 res = ac_build_gather_values(&ctx->ac, coords, count);
2583 }
2584 return res;
2585 }
2586
2587 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2588 nir_intrinsic_instr *instr)
2589 {
2590 LLVMValueRef params[7];
2591 LLVMValueRef res;
2592 char intrinsic_name[64];
2593 const nir_variable *var = instr->variables[0]->var;
2594 const struct glsl_type *type = var->type;
2595 if(instr->variables[0]->deref.child)
2596 type = instr->variables[0]->deref.child->type;
2597
2598 type = glsl_without_array(type);
2599 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2600 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2601 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2602 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2603 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2604 params[3] = ctx->i1false; /* glc */
2605 params[4] = ctx->i1false; /* slc */
2606 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2607 params, 5, 0);
2608
2609 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2610 res = to_integer(ctx, res);
2611 } else {
2612 bool is_da = glsl_sampler_type_is_array(type) ||
2613 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2614 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
2615 LLVMValueRef glc = ctx->i1false;
2616 LLVMValueRef slc = ctx->i1false;
2617
2618 params[0] = get_image_coords(ctx, instr);
2619 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2620 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2621 if (HAVE_LLVM <= 0x0309) {
2622 params[3] = ctx->i1false; /* r128 */
2623 params[4] = da;
2624 params[5] = glc;
2625 params[6] = slc;
2626 } else {
2627 LLVMValueRef lwe = ctx->i1false;
2628 params[3] = glc;
2629 params[4] = slc;
2630 params[5] = lwe;
2631 params[6] = da;
2632 }
2633
2634 ac_get_image_intr_name("llvm.amdgcn.image.load",
2635 ctx->v4f32, /* vdata */
2636 LLVMTypeOf(params[0]), /* coords */
2637 LLVMTypeOf(params[1]), /* rsrc */
2638 intrinsic_name, sizeof(intrinsic_name));
2639
2640 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2641 params, 7, AC_FUNC_ATTR_READONLY);
2642 }
2643 return to_integer(ctx, res);
2644 }
2645
2646 static void visit_image_store(struct nir_to_llvm_context *ctx,
2647 nir_intrinsic_instr *instr)
2648 {
2649 LLVMValueRef params[8];
2650 char intrinsic_name[64];
2651 const nir_variable *var = instr->variables[0]->var;
2652 const struct glsl_type *type = glsl_without_array(var->type);
2653
2654 if (ctx->stage == MESA_SHADER_FRAGMENT)
2655 ctx->shader_info->fs.writes_memory = true;
2656
2657 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2658 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2659 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2660 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2661 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2662 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2663 params[4] = ctx->i1false; /* glc */
2664 params[5] = ctx->i1false; /* slc */
2665 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2666 params, 6, 0);
2667 } else {
2668 bool is_da = glsl_sampler_type_is_array(type) ||
2669 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2670 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
2671 LLVMValueRef glc = ctx->i1false;
2672 LLVMValueRef slc = ctx->i1false;
2673
2674 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2675 params[1] = get_image_coords(ctx, instr); /* coords */
2676 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2677 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2678 if (HAVE_LLVM <= 0x0309) {
2679 params[4] = ctx->i1false; /* r128 */
2680 params[5] = da;
2681 params[6] = glc;
2682 params[7] = slc;
2683 } else {
2684 LLVMValueRef lwe = ctx->i1false;
2685 params[4] = glc;
2686 params[5] = slc;
2687 params[6] = lwe;
2688 params[7] = da;
2689 }
2690
2691 ac_get_image_intr_name("llvm.amdgcn.image.store",
2692 LLVMTypeOf(params[0]), /* vdata */
2693 LLVMTypeOf(params[1]), /* coords */
2694 LLVMTypeOf(params[2]), /* rsrc */
2695 intrinsic_name, sizeof(intrinsic_name));
2696
2697 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2698 params, 8, 0);
2699 }
2700
2701 }
2702
2703 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2704 nir_intrinsic_instr *instr)
2705 {
2706 LLVMValueRef params[6];
2707 int param_count = 0;
2708 const nir_variable *var = instr->variables[0]->var;
2709
2710 const char *base_name = "llvm.amdgcn.image.atomic";
2711 const char *atomic_name;
2712 LLVMValueRef coords;
2713 char intrinsic_name[32], coords_type[8];
2714 const struct glsl_type *type = glsl_without_array(var->type);
2715
2716 if (ctx->stage == MESA_SHADER_FRAGMENT)
2717 ctx->shader_info->fs.writes_memory = true;
2718
2719 params[param_count++] = get_src(ctx, instr->src[2]);
2720 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2721 params[param_count++] = get_src(ctx, instr->src[3]);
2722
2723 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2724 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2725 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2726 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2727 params[param_count++] = ctx->i32zero; /* voffset */
2728 params[param_count++] = ctx->i1false; /* glc */
2729 params[param_count++] = ctx->i1false; /* slc */
2730 } else {
2731 bool da = glsl_sampler_type_is_array(type) ||
2732 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2733
2734 coords = params[param_count++] = get_image_coords(ctx, instr);
2735 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2736 params[param_count++] = ctx->i1false; /* r128 */
2737 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
2738 params[param_count++] = ctx->i1false; /* slc */
2739 }
2740
2741 switch (instr->intrinsic) {
2742 case nir_intrinsic_image_atomic_add:
2743 atomic_name = "add";
2744 break;
2745 case nir_intrinsic_image_atomic_min:
2746 atomic_name = "smin";
2747 break;
2748 case nir_intrinsic_image_atomic_max:
2749 atomic_name = "smax";
2750 break;
2751 case nir_intrinsic_image_atomic_and:
2752 atomic_name = "and";
2753 break;
2754 case nir_intrinsic_image_atomic_or:
2755 atomic_name = "or";
2756 break;
2757 case nir_intrinsic_image_atomic_xor:
2758 atomic_name = "xor";
2759 break;
2760 case nir_intrinsic_image_atomic_exchange:
2761 atomic_name = "swap";
2762 break;
2763 case nir_intrinsic_image_atomic_comp_swap:
2764 atomic_name = "cmpswap";
2765 break;
2766 default:
2767 abort();
2768 }
2769 build_int_type_name(LLVMTypeOf(coords),
2770 coords_type, sizeof(coords_type));
2771
2772 snprintf(intrinsic_name, sizeof(intrinsic_name),
2773 "%s.%s.%s", base_name, atomic_name, coords_type);
2774 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2775 }
2776
2777 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2778 nir_intrinsic_instr *instr)
2779 {
2780 LLVMValueRef res;
2781 const nir_variable *var = instr->variables[0]->var;
2782 const struct glsl_type *type = instr->variables[0]->var->type;
2783 bool da = glsl_sampler_type_is_array(var->type) ||
2784 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2785 if(instr->variables[0]->deref.child)
2786 type = instr->variables[0]->deref.child->type;
2787
2788 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2789 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2790
2791 struct ac_image_args args = { 0 };
2792
2793 args.da = da;
2794 args.dmask = 0xf;
2795 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2796 args.opcode = ac_image_get_resinfo;
2797 args.addr = ctx->i32zero;
2798
2799 res = ac_build_image_opcode(&ctx->ac, &args);
2800
2801 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2802 glsl_sampler_type_is_array(type)) {
2803 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2804 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2805 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2806 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2807 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2808 }
2809 return res;
2810 }
2811
2812 #define NOOP_WAITCNT 0xf7f
2813 #define LGKM_CNT 0x07f
2814 #define VM_CNT 0xf70
2815
2816 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
2817 unsigned simm16)
2818 {
2819 LLVMValueRef args[1] = {
2820 LLVMConstInt(ctx->i32, simm16, false),
2821 };
2822 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2823 ctx->voidt, args, 1, 0);
2824 }
2825
2826 static void emit_barrier(struct nir_to_llvm_context *ctx)
2827 {
2828 // TODO tess
2829 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2830 ctx->voidt, NULL, 0, 0);
2831 }
2832
2833 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2834 nir_intrinsic_instr *instr)
2835 {
2836 LLVMValueRef cond;
2837 ctx->shader_info->fs.can_discard = true;
2838
2839 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2840 get_src(ctx, instr->src[0]),
2841 ctx->i32zero, "");
2842
2843 cond = LLVMBuildSelect(ctx->builder, cond,
2844 LLVMConstReal(ctx->f32, -1.0f),
2845 ctx->f32zero, "");
2846 ac_build_kill(&ctx->ac, cond);
2847 }
2848
2849 static LLVMValueRef
2850 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2851 {
2852 LLVMValueRef result;
2853 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2854 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2855 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2856
2857 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2858 }
2859
2860 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2861 nir_intrinsic_instr *instr)
2862 {
2863 LLVMValueRef ptr, result;
2864 int idx = instr->variables[0]->var->data.driver_location;
2865 LLVMValueRef src = get_src(ctx, instr->src[0]);
2866 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2867
2868 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2869 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2870 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2871 ptr, src, src1,
2872 LLVMAtomicOrderingSequentiallyConsistent,
2873 LLVMAtomicOrderingSequentiallyConsistent,
2874 false);
2875 } else {
2876 LLVMAtomicRMWBinOp op;
2877 switch (instr->intrinsic) {
2878 case nir_intrinsic_var_atomic_add:
2879 op = LLVMAtomicRMWBinOpAdd;
2880 break;
2881 case nir_intrinsic_var_atomic_umin:
2882 op = LLVMAtomicRMWBinOpUMin;
2883 break;
2884 case nir_intrinsic_var_atomic_umax:
2885 op = LLVMAtomicRMWBinOpUMax;
2886 break;
2887 case nir_intrinsic_var_atomic_imin:
2888 op = LLVMAtomicRMWBinOpMin;
2889 break;
2890 case nir_intrinsic_var_atomic_imax:
2891 op = LLVMAtomicRMWBinOpMax;
2892 break;
2893 case nir_intrinsic_var_atomic_and:
2894 op = LLVMAtomicRMWBinOpAnd;
2895 break;
2896 case nir_intrinsic_var_atomic_or:
2897 op = LLVMAtomicRMWBinOpOr;
2898 break;
2899 case nir_intrinsic_var_atomic_xor:
2900 op = LLVMAtomicRMWBinOpXor;
2901 break;
2902 case nir_intrinsic_var_atomic_exchange:
2903 op = LLVMAtomicRMWBinOpXchg;
2904 break;
2905 default:
2906 return NULL;
2907 }
2908
2909 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2910 LLVMAtomicOrderingSequentiallyConsistent,
2911 false);
2912 }
2913 return result;
2914 }
2915
2916 #define INTERP_CENTER 0
2917 #define INTERP_CENTROID 1
2918 #define INTERP_SAMPLE 2
2919
2920 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2921 enum glsl_interp_mode interp, unsigned location)
2922 {
2923 switch (interp) {
2924 case INTERP_MODE_FLAT:
2925 default:
2926 return NULL;
2927 case INTERP_MODE_SMOOTH:
2928 case INTERP_MODE_NONE:
2929 if (location == INTERP_CENTER)
2930 return ctx->persp_center;
2931 else if (location == INTERP_CENTROID)
2932 return ctx->persp_centroid;
2933 else if (location == INTERP_SAMPLE)
2934 return ctx->persp_sample;
2935 break;
2936 case INTERP_MODE_NOPERSPECTIVE:
2937 if (location == INTERP_CENTER)
2938 return ctx->linear_center;
2939 else if (location == INTERP_CENTROID)
2940 return ctx->linear_centroid;
2941 else if (location == INTERP_SAMPLE)
2942 return ctx->linear_sample;
2943 break;
2944 }
2945 return NULL;
2946 }
2947
2948 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2949 LLVMValueRef sample_id)
2950 {
2951 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2952 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2953 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2954 LLVMValueRef result[2];
2955
2956 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2957 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2958
2959 return ac_build_gather_values(&ctx->ac, result, 2);
2960 }
2961
2962 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2963 {
2964 LLVMValueRef values[2];
2965
2966 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2967 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2968 return ac_build_gather_values(&ctx->ac, values, 2);
2969 }
2970
2971 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2972 nir_intrinsic_instr *instr)
2973 {
2974 LLVMValueRef result[2];
2975 LLVMValueRef interp_param, attr_number;
2976 unsigned location;
2977 unsigned chan;
2978 LLVMValueRef src_c0, src_c1;
2979 LLVMValueRef src0;
2980 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2981 switch (instr->intrinsic) {
2982 case nir_intrinsic_interp_var_at_centroid:
2983 location = INTERP_CENTROID;
2984 break;
2985 case nir_intrinsic_interp_var_at_sample:
2986 location = INTERP_SAMPLE;
2987 src0 = get_src(ctx, instr->src[0]);
2988 break;
2989 case nir_intrinsic_interp_var_at_offset:
2990 location = INTERP_CENTER;
2991 src0 = get_src(ctx, instr->src[0]);
2992 default:
2993 break;
2994 }
2995
2996 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2997 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2998 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2999 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3000 LLVMValueRef sample_position;
3001 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3002
3003 /* fetch sample ID */
3004 sample_position = load_sample_position(ctx, src0);
3005
3006 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3007 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3008 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3009 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3010 }
3011 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3012 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3013
3014 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3015 LLVMValueRef ij_out[2];
3016 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3017
3018 /*
3019 * take the I then J parameters, and the DDX/Y for it, and
3020 * calculate the IJ inputs for the interpolator.
3021 * temp1 = ddx * offset/sample.x + I;
3022 * interp_param.I = ddy * offset/sample.y + temp1;
3023 * temp1 = ddx * offset/sample.x + J;
3024 * interp_param.J = ddy * offset/sample.y + temp1;
3025 */
3026 for (unsigned i = 0; i < 2; i++) {
3027 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3028 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3029 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3030 ddxy_out, ix_ll, "");
3031 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3032 ddxy_out, iy_ll, "");
3033 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3034 interp_param, ix_ll, "");
3035 LLVMValueRef temp1, temp2;
3036
3037 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3038 ctx->f32, "");
3039
3040 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3041 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3042
3043 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3044 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3045
3046 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3047 temp2, ctx->i32, "");
3048 }
3049 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3050
3051 }
3052
3053 for (chan = 0; chan < 2; chan++) {
3054 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3055
3056 if (interp_param) {
3057 interp_param = LLVMBuildBitCast(ctx->builder,
3058 interp_param, LLVMVectorType(ctx->f32, 2), "");
3059 LLVMValueRef i = LLVMBuildExtractElement(
3060 ctx->builder, interp_param, ctx->i32zero, "");
3061 LLVMValueRef j = LLVMBuildExtractElement(
3062 ctx->builder, interp_param, ctx->i32one, "");
3063
3064 result[chan] = ac_build_fs_interp(&ctx->ac,
3065 llvm_chan, attr_number,
3066 ctx->prim_mask, i, j);
3067 } else {
3068 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3069 LLVMConstInt(ctx->i32, 2, false),
3070 llvm_chan, attr_number,
3071 ctx->prim_mask);
3072 }
3073 }
3074 return ac_build_gather_values(&ctx->ac, result, 2);
3075 }
3076
3077 static void
3078 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3079 nir_intrinsic_instr *instr)
3080 {
3081 LLVMValueRef gs_next_vertex;
3082 LLVMValueRef can_emit, kill;
3083 int idx;
3084
3085 assert(instr->const_index[0] == 0);
3086 /* Write vertex attribute values to GSVS ring */
3087 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3088 ctx->gs_next_vertex,
3089 "");
3090
3091 /* If this thread has already emitted the declared maximum number of
3092 * vertices, kill it: excessive vertex emissions are not supposed to
3093 * have any effect, and GS threads have no externally observable
3094 * effects other than emitting vertices.
3095 */
3096 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3097 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3098
3099 kill = LLVMBuildSelect(ctx->builder, can_emit,
3100 LLVMConstReal(ctx->f32, 1.0f),
3101 LLVMConstReal(ctx->f32, -1.0f), "");
3102 ac_build_kill(&ctx->ac, kill);
3103
3104 /* loop num outputs */
3105 idx = 0;
3106 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3107 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3108 int length = 4;
3109 int slot = idx;
3110 int slot_inc = 1;
3111
3112 if (!(ctx->output_mask & (1ull << i)))
3113 continue;
3114
3115 if (i == VARYING_SLOT_CLIP_DIST0) {
3116 /* pack clip and cull into a single set of slots */
3117 length = ctx->num_output_clips + ctx->num_output_culls;
3118 if (length > 4)
3119 slot_inc = 2;
3120 }
3121 for (unsigned j = 0; j < length; j++) {
3122 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3123 out_ptr[j], "");
3124 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3125 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3126 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3127
3128 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3129
3130 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3131 out_val, 1,
3132 voffset, ctx->gs2vs_offset, 0,
3133 1, 1, true, true);
3134 }
3135 idx += slot_inc;
3136 }
3137
3138 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3139 ctx->i32one, "");
3140 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3141
3142 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3143 }
3144
3145 static void
3146 visit_end_primitive(struct nir_to_llvm_context *ctx,
3147 nir_intrinsic_instr *instr)
3148 {
3149 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3150 }
3151
3152 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3153 nir_intrinsic_instr *instr)
3154 {
3155 LLVMValueRef result = NULL;
3156
3157 switch (instr->intrinsic) {
3158 case nir_intrinsic_load_work_group_id: {
3159 result = ctx->workgroup_ids;
3160 break;
3161 }
3162 case nir_intrinsic_load_base_vertex: {
3163 result = ctx->base_vertex;
3164 break;
3165 }
3166 case nir_intrinsic_load_vertex_id_zero_base: {
3167 result = ctx->vertex_id;
3168 break;
3169 }
3170 case nir_intrinsic_load_local_invocation_id: {
3171 result = ctx->local_invocation_ids;
3172 break;
3173 }
3174 case nir_intrinsic_load_base_instance:
3175 result = ctx->start_instance;
3176 break;
3177 case nir_intrinsic_load_draw_id:
3178 result = ctx->draw_index;
3179 break;
3180 case nir_intrinsic_load_invocation_id:
3181 result = ctx->gs_invocation_id;
3182 break;
3183 case nir_intrinsic_load_primitive_id:
3184 if (ctx->stage == MESA_SHADER_GEOMETRY)
3185 result = ctx->gs_prim_id;
3186 else
3187 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3188 break;
3189 case nir_intrinsic_load_sample_id:
3190 ctx->shader_info->fs.force_persample = true;
3191 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3192 break;
3193 case nir_intrinsic_load_sample_pos:
3194 ctx->shader_info->fs.force_persample = true;
3195 result = load_sample_pos(ctx);
3196 break;
3197 case nir_intrinsic_load_sample_mask_in:
3198 result = ctx->sample_coverage;
3199 break;
3200 case nir_intrinsic_load_front_face:
3201 result = ctx->front_face;
3202 break;
3203 case nir_intrinsic_load_instance_id:
3204 result = ctx->instance_id;
3205 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3206 ctx->shader_info->vs.vgpr_comp_cnt);
3207 break;
3208 case nir_intrinsic_load_num_work_groups:
3209 result = ctx->num_work_groups;
3210 break;
3211 case nir_intrinsic_load_local_invocation_index:
3212 result = visit_load_local_invocation_index(ctx);
3213 break;
3214 case nir_intrinsic_load_push_constant:
3215 result = visit_load_push_constant(ctx, instr);
3216 break;
3217 case nir_intrinsic_vulkan_resource_index:
3218 result = visit_vulkan_resource_index(ctx, instr);
3219 break;
3220 case nir_intrinsic_store_ssbo:
3221 visit_store_ssbo(ctx, instr);
3222 break;
3223 case nir_intrinsic_load_ssbo:
3224 result = visit_load_buffer(ctx, instr);
3225 break;
3226 case nir_intrinsic_ssbo_atomic_add:
3227 case nir_intrinsic_ssbo_atomic_imin:
3228 case nir_intrinsic_ssbo_atomic_umin:
3229 case nir_intrinsic_ssbo_atomic_imax:
3230 case nir_intrinsic_ssbo_atomic_umax:
3231 case nir_intrinsic_ssbo_atomic_and:
3232 case nir_intrinsic_ssbo_atomic_or:
3233 case nir_intrinsic_ssbo_atomic_xor:
3234 case nir_intrinsic_ssbo_atomic_exchange:
3235 case nir_intrinsic_ssbo_atomic_comp_swap:
3236 result = visit_atomic_ssbo(ctx, instr);
3237 break;
3238 case nir_intrinsic_load_ubo:
3239 result = visit_load_ubo_buffer(ctx, instr);
3240 break;
3241 case nir_intrinsic_get_buffer_size:
3242 result = visit_get_buffer_size(ctx, instr);
3243 break;
3244 case nir_intrinsic_load_var:
3245 result = visit_load_var(ctx, instr);
3246 break;
3247 case nir_intrinsic_store_var:
3248 visit_store_var(ctx, instr);
3249 break;
3250 case nir_intrinsic_image_load:
3251 result = visit_image_load(ctx, instr);
3252 break;
3253 case nir_intrinsic_image_store:
3254 visit_image_store(ctx, instr);
3255 break;
3256 case nir_intrinsic_image_atomic_add:
3257 case nir_intrinsic_image_atomic_min:
3258 case nir_intrinsic_image_atomic_max:
3259 case nir_intrinsic_image_atomic_and:
3260 case nir_intrinsic_image_atomic_or:
3261 case nir_intrinsic_image_atomic_xor:
3262 case nir_intrinsic_image_atomic_exchange:
3263 case nir_intrinsic_image_atomic_comp_swap:
3264 result = visit_image_atomic(ctx, instr);
3265 break;
3266 case nir_intrinsic_image_size:
3267 result = visit_image_size(ctx, instr);
3268 break;
3269 case nir_intrinsic_discard:
3270 ctx->shader_info->fs.can_discard = true;
3271 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3272 ctx->voidt,
3273 NULL, 0, AC_FUNC_ATTR_LEGACY);
3274 break;
3275 case nir_intrinsic_discard_if:
3276 emit_discard_if(ctx, instr);
3277 break;
3278 case nir_intrinsic_memory_barrier:
3279 emit_waitcnt(ctx, VM_CNT);
3280 break;
3281 case nir_intrinsic_barrier:
3282 emit_barrier(ctx);
3283 break;
3284 case nir_intrinsic_var_atomic_add:
3285 case nir_intrinsic_var_atomic_imin:
3286 case nir_intrinsic_var_atomic_umin:
3287 case nir_intrinsic_var_atomic_imax:
3288 case nir_intrinsic_var_atomic_umax:
3289 case nir_intrinsic_var_atomic_and:
3290 case nir_intrinsic_var_atomic_or:
3291 case nir_intrinsic_var_atomic_xor:
3292 case nir_intrinsic_var_atomic_exchange:
3293 case nir_intrinsic_var_atomic_comp_swap:
3294 result = visit_var_atomic(ctx, instr);
3295 break;
3296 case nir_intrinsic_interp_var_at_centroid:
3297 case nir_intrinsic_interp_var_at_sample:
3298 case nir_intrinsic_interp_var_at_offset:
3299 result = visit_interp(ctx, instr);
3300 break;
3301 case nir_intrinsic_emit_vertex:
3302 visit_emit_vertex(ctx, instr);
3303 break;
3304 case nir_intrinsic_end_primitive:
3305 visit_end_primitive(ctx, instr);
3306 break;
3307 default:
3308 fprintf(stderr, "Unknown intrinsic: ");
3309 nir_print_instr(&instr->instr, stderr);
3310 fprintf(stderr, "\n");
3311 break;
3312 }
3313 if (result) {
3314 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3315 }
3316 }
3317
3318 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3319 nir_deref_var *deref,
3320 enum desc_type desc_type)
3321 {
3322 unsigned desc_set = deref->var->data.descriptor_set;
3323 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3324 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3325 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3326 unsigned offset = binding->offset;
3327 unsigned stride = binding->size;
3328 unsigned type_size;
3329 LLVMBuilderRef builder = ctx->builder;
3330 LLVMTypeRef type;
3331 LLVMValueRef index = NULL;
3332 unsigned constant_index = 0;
3333
3334 assert(deref->var->data.binding < layout->binding_count);
3335
3336 switch (desc_type) {
3337 case DESC_IMAGE:
3338 type = ctx->v8i32;
3339 type_size = 32;
3340 break;
3341 case DESC_FMASK:
3342 type = ctx->v8i32;
3343 offset += 32;
3344 type_size = 32;
3345 break;
3346 case DESC_SAMPLER:
3347 type = ctx->v4i32;
3348 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3349 offset += 64;
3350
3351 type_size = 16;
3352 break;
3353 case DESC_BUFFER:
3354 type = ctx->v4i32;
3355 type_size = 16;
3356 break;
3357 default:
3358 unreachable("invalid desc_type\n");
3359 }
3360
3361 if (deref->deref.child) {
3362 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3363
3364 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3365 offset += child->base_offset * stride;
3366 if (child->deref_array_type == nir_deref_array_type_indirect) {
3367 index = get_src(ctx, child->indirect);
3368 }
3369
3370 constant_index = child->base_offset;
3371 }
3372 if (desc_type == DESC_SAMPLER && binding->immutable_samplers &&
3373 (!index || binding->immutable_samplers_equal)) {
3374 if (binding->immutable_samplers_equal)
3375 constant_index = 0;
3376
3377 LLVMValueRef constants[] = {
3378 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 0], 0),
3379 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 1], 0),
3380 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 2], 0),
3381 LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 3], 0),
3382 };
3383 return ac_build_gather_values(&ctx->ac, constants, 4);
3384 }
3385
3386 assert(stride % type_size == 0);
3387
3388 if (!index)
3389 index = ctx->i32zero;
3390
3391 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3392
3393 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3394 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3395
3396 return ac_build_indexed_load_const(&ctx->ac, list, index);
3397 }
3398
3399 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3400 struct ac_image_args *args,
3401 nir_tex_instr *instr,
3402 nir_texop op,
3403 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3404 LLVMValueRef *param, unsigned count,
3405 unsigned dmask)
3406 {
3407 unsigned is_rect = 0;
3408 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3409
3410 if (op == nir_texop_lod)
3411 da = false;
3412 /* Pad to power of two vector */
3413 while (count < util_next_power_of_two(count))
3414 param[count++] = LLVMGetUndef(ctx->i32);
3415
3416 if (count > 1)
3417 args->addr = ac_build_gather_values(&ctx->ac, param, count);
3418 else
3419 args->addr = param[0];
3420
3421 args->resource = res_ptr;
3422 args->sampler = samp_ptr;
3423
3424 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3425 args->addr = param[0];
3426 return;
3427 }
3428
3429 args->dmask = dmask;
3430 args->unorm = is_rect;
3431 args->da = da;
3432 }
3433
3434 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3435 *
3436 * SI-CI:
3437 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3438 * filtering manually. The driver sets img7 to a mask clearing
3439 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3440 * s_and_b32 samp0, samp0, img7
3441 *
3442 * VI:
3443 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3444 */
3445 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3446 LLVMValueRef res, LLVMValueRef samp)
3447 {
3448 LLVMBuilderRef builder = ctx->builder;
3449 LLVMValueRef img7, samp0;
3450
3451 if (ctx->options->chip_class >= VI)
3452 return samp;
3453
3454 img7 = LLVMBuildExtractElement(builder, res,
3455 LLVMConstInt(ctx->i32, 7, 0), "");
3456 samp0 = LLVMBuildExtractElement(builder, samp,
3457 LLVMConstInt(ctx->i32, 0, 0), "");
3458 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3459 return LLVMBuildInsertElement(builder, samp, samp0,
3460 LLVMConstInt(ctx->i32, 0, 0), "");
3461 }
3462
3463 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3464 nir_tex_instr *instr,
3465 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3466 LLVMValueRef *fmask_ptr)
3467 {
3468 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3469 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3470 else
3471 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3472 if (samp_ptr) {
3473 if (instr->sampler)
3474 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3475 else
3476 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3477 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3478 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3479 }
3480 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3481 instr->op == nir_texop_samples_identical))
3482 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3483 }
3484
3485 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3486 LLVMValueRef coord)
3487 {
3488 coord = to_float(ctx, coord);
3489 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3490 coord = to_integer(ctx, coord);
3491 return coord;
3492 }
3493
3494 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3495 {
3496 LLVMValueRef result = NULL;
3497 struct ac_image_args args = { 0 };
3498 unsigned dmask = 0xf;
3499 LLVMValueRef address[16];
3500 LLVMValueRef coords[5];
3501 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3502 LLVMValueRef bias = NULL, offsets = NULL;
3503 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3504 LLVMValueRef ddx = NULL, ddy = NULL;
3505 LLVMValueRef derivs[6];
3506 unsigned chan, count = 0;
3507 unsigned const_src = 0, num_deriv_comp = 0;
3508
3509 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3510
3511 for (unsigned i = 0; i < instr->num_srcs; i++) {
3512 switch (instr->src[i].src_type) {
3513 case nir_tex_src_coord:
3514 coord = get_src(ctx, instr->src[i].src);
3515 break;
3516 case nir_tex_src_projector:
3517 break;
3518 case nir_tex_src_comparator:
3519 comparator = get_src(ctx, instr->src[i].src);
3520 break;
3521 case nir_tex_src_offset:
3522 offsets = get_src(ctx, instr->src[i].src);
3523 const_src = i;
3524 break;
3525 case nir_tex_src_bias:
3526 bias = get_src(ctx, instr->src[i].src);
3527 break;
3528 case nir_tex_src_lod:
3529 lod = get_src(ctx, instr->src[i].src);
3530 break;
3531 case nir_tex_src_ms_index:
3532 sample_index = get_src(ctx, instr->src[i].src);
3533 break;
3534 case nir_tex_src_ms_mcs:
3535 break;
3536 case nir_tex_src_ddx:
3537 ddx = get_src(ctx, instr->src[i].src);
3538 num_deriv_comp = instr->src[i].src.ssa->num_components;
3539 break;
3540 case nir_tex_src_ddy:
3541 ddy = get_src(ctx, instr->src[i].src);
3542 break;
3543 case nir_tex_src_texture_offset:
3544 case nir_tex_src_sampler_offset:
3545 case nir_tex_src_plane:
3546 default:
3547 break;
3548 }
3549 }
3550
3551 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3552 result = get_buffer_size(ctx, res_ptr, true);
3553 goto write_result;
3554 }
3555
3556 if (instr->op == nir_texop_texture_samples) {
3557 LLVMValueRef res, samples, is_msaa;
3558 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3559 samples = LLVMBuildExtractElement(ctx->builder, res,
3560 LLVMConstInt(ctx->i32, 3, false), "");
3561 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3562 LLVMConstInt(ctx->i32, 28, false), "");
3563 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3564 LLVMConstInt(ctx->i32, 0xe, false), "");
3565 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3566 LLVMConstInt(ctx->i32, 0xe, false), "");
3567
3568 samples = LLVMBuildLShr(ctx->builder, samples,
3569 LLVMConstInt(ctx->i32, 16, false), "");
3570 samples = LLVMBuildAnd(ctx->builder, samples,
3571 LLVMConstInt(ctx->i32, 0xf, false), "");
3572 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3573 samples, "");
3574 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3575 ctx->i32one, "");
3576 result = samples;
3577 goto write_result;
3578 }
3579
3580 if (coord)
3581 for (chan = 0; chan < instr->coord_components; chan++)
3582 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3583
3584 if (offsets && instr->op != nir_texop_txf) {
3585 LLVMValueRef offset[3], pack;
3586 for (chan = 0; chan < 3; ++chan)
3587 offset[chan] = ctx->i32zero;
3588
3589 args.offset = true;
3590 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3591 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3592 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3593 LLVMConstInt(ctx->i32, 0x3f, false), "");
3594 if (chan)
3595 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3596 LLVMConstInt(ctx->i32, chan * 8, false), "");
3597 }
3598 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3599 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3600 address[count++] = pack;
3601
3602 }
3603 /* pack LOD bias value */
3604 if (instr->op == nir_texop_txb && bias) {
3605 address[count++] = bias;
3606 }
3607
3608 /* Pack depth comparison value */
3609 if (instr->is_shadow && comparator) {
3610 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3611 }
3612
3613 /* pack derivatives */
3614 if (ddx || ddy) {
3615 switch (instr->sampler_dim) {
3616 case GLSL_SAMPLER_DIM_3D:
3617 case GLSL_SAMPLER_DIM_CUBE:
3618 num_deriv_comp = 3;
3619 break;
3620 case GLSL_SAMPLER_DIM_2D:
3621 default:
3622 num_deriv_comp = 2;
3623 break;
3624 case GLSL_SAMPLER_DIM_1D:
3625 num_deriv_comp = 1;
3626 break;
3627 }
3628
3629 for (unsigned i = 0; i < num_deriv_comp; i++) {
3630 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3631 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3632 }
3633 }
3634
3635 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3636 for (chan = 0; chan < instr->coord_components; chan++)
3637 coords[chan] = to_float(ctx, coords[chan]);
3638 if (instr->coord_components == 3)
3639 coords[3] = LLVMGetUndef(ctx->f32);
3640 ac_prepare_cube_coords(&ctx->ac,
3641 instr->op == nir_texop_txd, instr->is_array,
3642 coords, derivs);
3643 if (num_deriv_comp)
3644 num_deriv_comp--;
3645 }
3646
3647 if (ddx || ddy) {
3648 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3649 address[count++] = derivs[i];
3650 }
3651
3652 /* Pack texture coordinates */
3653 if (coord) {
3654 address[count++] = coords[0];
3655 if (instr->coord_components > 1) {
3656 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3657 coords[1] = apply_round_slice(ctx, coords[1]);
3658 }
3659 address[count++] = coords[1];
3660 }
3661 if (instr->coord_components > 2) {
3662 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3663 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3664 coords[2] = apply_round_slice(ctx, coords[2]);
3665 }
3666 address[count++] = coords[2];
3667 }
3668 }
3669
3670 /* Pack LOD */
3671 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3672 address[count++] = lod;
3673 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3674 address[count++] = sample_index;
3675 } else if(instr->op == nir_texop_txs) {
3676 count = 0;
3677 if (lod)
3678 address[count++] = lod;
3679 else
3680 address[count++] = ctx->i32zero;
3681 }
3682
3683 for (chan = 0; chan < count; chan++) {
3684 address[chan] = LLVMBuildBitCast(ctx->builder,
3685 address[chan], ctx->i32, "");
3686 }
3687
3688 if (instr->op == nir_texop_samples_identical) {
3689 LLVMValueRef txf_address[4];
3690 struct ac_image_args txf_args = { 0 };
3691 unsigned txf_count = count;
3692 memcpy(txf_address, address, sizeof(txf_address));
3693
3694 if (!instr->is_array)
3695 txf_address[2] = ctx->i32zero;
3696 txf_address[3] = ctx->i32zero;
3697
3698 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
3699 fmask_ptr, NULL,
3700 txf_address, txf_count, 0xf);
3701
3702 result = build_tex_intrinsic(ctx, instr, &txf_args);
3703
3704 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3705 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3706 goto write_result;
3707 }
3708
3709 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3710 instr->op != nir_texop_txs) {
3711 unsigned sample_chan = instr->is_array ? 3 : 2;
3712 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
3713 address[0],
3714 address[1],
3715 instr->is_array ? address[2] : NULL,
3716 address[sample_chan],
3717 fmask_ptr);
3718 }
3719
3720 if (offsets && instr->op == nir_texop_txf) {
3721 nir_const_value *const_offset =
3722 nir_src_as_const_value(instr->src[const_src].src);
3723 int num_offsets = instr->src[const_src].src.ssa->num_components;
3724 assert(const_offset);
3725 num_offsets = MIN2(num_offsets, instr->coord_components);
3726 if (num_offsets > 2)
3727 address[2] = LLVMBuildAdd(ctx->builder,
3728 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3729 if (num_offsets > 1)
3730 address[1] = LLVMBuildAdd(ctx->builder,
3731 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3732 address[0] = LLVMBuildAdd(ctx->builder,
3733 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3734
3735 }
3736
3737 /* TODO TG4 support */
3738 if (instr->op == nir_texop_tg4) {
3739 if (instr->is_shadow)
3740 dmask = 1;
3741 else
3742 dmask = 1 << instr->component;
3743 }
3744 set_tex_fetch_args(ctx, &args, instr, instr->op,
3745 res_ptr, samp_ptr, address, count, dmask);
3746
3747 result = build_tex_intrinsic(ctx, instr, &args);
3748
3749 if (instr->op == nir_texop_query_levels)
3750 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3751 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3752 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3753 else if (instr->op == nir_texop_txs &&
3754 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3755 instr->is_array) {
3756 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3757 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3758 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3759 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3760 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3761 } else if (instr->dest.ssa.num_components != 4)
3762 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3763
3764 write_result:
3765 if (result) {
3766 assert(instr->dest.is_ssa);
3767 result = to_integer(ctx, result);
3768 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3769 }
3770 }
3771
3772
3773 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3774 {
3775 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3776 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3777
3778 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3779 _mesa_hash_table_insert(ctx->phis, instr, result);
3780 }
3781
3782 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3783 nir_phi_instr *instr,
3784 LLVMValueRef llvm_phi)
3785 {
3786 nir_foreach_phi_src(src, instr) {
3787 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3788 LLVMValueRef llvm_src = get_src(ctx, src->src);
3789
3790 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3791 }
3792 }
3793
3794 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3795 {
3796 struct hash_entry *entry;
3797 hash_table_foreach(ctx->phis, entry) {
3798 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3799 (LLVMValueRef)entry->data);
3800 }
3801 }
3802
3803
3804 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3805 nir_ssa_undef_instr *instr)
3806 {
3807 unsigned num_components = instr->def.num_components;
3808 LLVMValueRef undef;
3809
3810 if (num_components == 1)
3811 undef = LLVMGetUndef(ctx->i32);
3812 else {
3813 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3814 }
3815 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3816 }
3817
3818 static void visit_jump(struct nir_to_llvm_context *ctx,
3819 nir_jump_instr *instr)
3820 {
3821 switch (instr->type) {
3822 case nir_jump_break:
3823 LLVMBuildBr(ctx->builder, ctx->break_block);
3824 LLVMClearInsertionPosition(ctx->builder);
3825 break;
3826 case nir_jump_continue:
3827 LLVMBuildBr(ctx->builder, ctx->continue_block);
3828 LLVMClearInsertionPosition(ctx->builder);
3829 break;
3830 default:
3831 fprintf(stderr, "Unknown NIR jump instr: ");
3832 nir_print_instr(&instr->instr, stderr);
3833 fprintf(stderr, "\n");
3834 abort();
3835 }
3836 }
3837
3838 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3839 struct exec_list *list);
3840
3841 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3842 {
3843 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3844 nir_foreach_instr(instr, block)
3845 {
3846 switch (instr->type) {
3847 case nir_instr_type_alu:
3848 visit_alu(ctx, nir_instr_as_alu(instr));
3849 break;
3850 case nir_instr_type_load_const:
3851 visit_load_const(ctx, nir_instr_as_load_const(instr));
3852 break;
3853 case nir_instr_type_intrinsic:
3854 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3855 break;
3856 case nir_instr_type_tex:
3857 visit_tex(ctx, nir_instr_as_tex(instr));
3858 break;
3859 case nir_instr_type_phi:
3860 visit_phi(ctx, nir_instr_as_phi(instr));
3861 break;
3862 case nir_instr_type_ssa_undef:
3863 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3864 break;
3865 case nir_instr_type_jump:
3866 visit_jump(ctx, nir_instr_as_jump(instr));
3867 break;
3868 default:
3869 fprintf(stderr, "Unknown NIR instr type: ");
3870 nir_print_instr(instr, stderr);
3871 fprintf(stderr, "\n");
3872 abort();
3873 }
3874 }
3875
3876 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3877 }
3878
3879 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3880 {
3881 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3882
3883 LLVMBasicBlockRef merge_block =
3884 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3885 LLVMBasicBlockRef if_block =
3886 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3887 LLVMBasicBlockRef else_block = merge_block;
3888 if (!exec_list_is_empty(&if_stmt->else_list))
3889 else_block = LLVMAppendBasicBlockInContext(
3890 ctx->context, ctx->main_function, "");
3891
3892 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3893 LLVMConstInt(ctx->i32, 0, false), "");
3894 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3895
3896 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3897 visit_cf_list(ctx, &if_stmt->then_list);
3898 if (LLVMGetInsertBlock(ctx->builder))
3899 LLVMBuildBr(ctx->builder, merge_block);
3900
3901 if (!exec_list_is_empty(&if_stmt->else_list)) {
3902 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3903 visit_cf_list(ctx, &if_stmt->else_list);
3904 if (LLVMGetInsertBlock(ctx->builder))
3905 LLVMBuildBr(ctx->builder, merge_block);
3906 }
3907
3908 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3909 }
3910
3911 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3912 {
3913 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3914 LLVMBasicBlockRef break_parent = ctx->break_block;
3915
3916 ctx->continue_block =
3917 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3918 ctx->break_block =
3919 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3920
3921 LLVMBuildBr(ctx->builder, ctx->continue_block);
3922 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3923 visit_cf_list(ctx, &loop->body);
3924
3925 if (LLVMGetInsertBlock(ctx->builder))
3926 LLVMBuildBr(ctx->builder, ctx->continue_block);
3927 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3928
3929 ctx->continue_block = continue_parent;
3930 ctx->break_block = break_parent;
3931 }
3932
3933 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3934 struct exec_list *list)
3935 {
3936 foreach_list_typed(nir_cf_node, node, node, list)
3937 {
3938 switch (node->type) {
3939 case nir_cf_node_block:
3940 visit_block(ctx, nir_cf_node_as_block(node));
3941 break;
3942
3943 case nir_cf_node_if:
3944 visit_if(ctx, nir_cf_node_as_if(node));
3945 break;
3946
3947 case nir_cf_node_loop:
3948 visit_loop(ctx, nir_cf_node_as_loop(node));
3949 break;
3950
3951 default:
3952 assert(0);
3953 }
3954 }
3955 }
3956
3957 static void
3958 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3959 struct nir_variable *variable)
3960 {
3961 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3962 LLVMValueRef t_offset;
3963 LLVMValueRef t_list;
3964 LLVMValueRef args[3];
3965 LLVMValueRef input;
3966 LLVMValueRef buffer_index;
3967 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3968 int idx = variable->data.location;
3969 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3970
3971 variable->data.driver_location = idx * 4;
3972
3973 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3974 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3975 ctx->start_instance, "");
3976 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3977 ctx->shader_info->vs.vgpr_comp_cnt);
3978 } else
3979 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3980 ctx->base_vertex, "");
3981
3982 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3983 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3984
3985 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
3986 args[0] = t_list;
3987 args[1] = LLVMConstInt(ctx->i32, 0, false);
3988 args[2] = buffer_index;
3989 input = ac_build_intrinsic(&ctx->ac,
3990 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3991 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND |
3992 AC_FUNC_ATTR_LEGACY);
3993
3994 for (unsigned chan = 0; chan < 4; chan++) {
3995 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3996 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3997 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3998 input, llvm_chan, ""));
3999 }
4000 }
4001 }
4002
4003 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4004 unsigned attr,
4005 LLVMValueRef interp_param,
4006 LLVMValueRef prim_mask,
4007 LLVMValueRef result[4])
4008 {
4009 LLVMValueRef attr_number;
4010 unsigned chan;
4011 LLVMValueRef i, j;
4012 bool interp = interp_param != NULL;
4013
4014 attr_number = LLVMConstInt(ctx->i32, attr, false);
4015
4016 /* fs.constant returns the param from the middle vertex, so it's not
4017 * really useful for flat shading. It's meant to be used for custom
4018 * interpolation (but the intrinsic can't fetch from the other two
4019 * vertices).
4020 *
4021 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4022 * to do the right thing. The only reason we use fs.constant is that
4023 * fs.interp cannot be used on integers, because they can be equal
4024 * to NaN.
4025 */
4026 if (interp) {
4027 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4028 LLVMVectorType(ctx->f32, 2), "");
4029
4030 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4031 ctx->i32zero, "");
4032 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4033 ctx->i32one, "");
4034 }
4035
4036 for (chan = 0; chan < 4; chan++) {
4037 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4038
4039 if (interp) {
4040 result[chan] = ac_build_fs_interp(&ctx->ac,
4041 llvm_chan,
4042 attr_number,
4043 prim_mask, i, j);
4044 } else {
4045 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4046 LLVMConstInt(ctx->i32, 2, false),
4047 llvm_chan,
4048 attr_number,
4049 prim_mask);
4050 }
4051 }
4052 }
4053
4054 static void
4055 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4056 struct nir_variable *variable)
4057 {
4058 int idx = variable->data.location;
4059 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4060 LLVMValueRef interp;
4061
4062 variable->data.driver_location = idx * 4;
4063 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4064
4065 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4066 unsigned interp_type;
4067 if (variable->data.sample) {
4068 interp_type = INTERP_SAMPLE;
4069 ctx->shader_info->fs.force_persample = true;
4070 } else if (variable->data.centroid)
4071 interp_type = INTERP_CENTROID;
4072 else
4073 interp_type = INTERP_CENTER;
4074
4075 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4076 } else
4077 interp = NULL;
4078
4079 for (unsigned i = 0; i < attrib_count; ++i)
4080 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4081
4082 }
4083
4084 static void
4085 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4086 struct nir_variable *variable)
4087 {
4088 switch (ctx->stage) {
4089 case MESA_SHADER_VERTEX:
4090 handle_vs_input_decl(ctx, variable);
4091 break;
4092 case MESA_SHADER_FRAGMENT:
4093 handle_fs_input_decl(ctx, variable);
4094 break;
4095 default:
4096 break;
4097 }
4098
4099 }
4100
4101 static void
4102 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4103 struct nir_shader *nir)
4104 {
4105 unsigned index = 0;
4106 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4107 LLVMValueRef interp_param;
4108 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4109
4110 if (!(ctx->input_mask & (1ull << i)))
4111 continue;
4112
4113 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4114 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4115 interp_param = *inputs;
4116 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4117 inputs);
4118
4119 if (!interp_param)
4120 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4121 ++index;
4122 } else if (i == VARYING_SLOT_POS) {
4123 for(int i = 0; i < 3; ++i)
4124 inputs[i] = ctx->frag_pos[i];
4125
4126 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4127 }
4128 }
4129 ctx->shader_info->fs.num_interp = index;
4130 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4131 ctx->shader_info->fs.has_pcoord = true;
4132 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4133 ctx->shader_info->fs.prim_id_input = true;
4134 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4135 ctx->shader_info->fs.layer_input = true;
4136 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4137 }
4138
4139 static LLVMValueRef
4140 ac_build_alloca(struct nir_to_llvm_context *ctx,
4141 LLVMTypeRef type,
4142 const char *name)
4143 {
4144 LLVMBuilderRef builder = ctx->builder;
4145 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4146 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4147 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4148 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4149 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4150 LLVMValueRef res;
4151
4152 if (first_instr) {
4153 LLVMPositionBuilderBefore(first_builder, first_instr);
4154 } else {
4155 LLVMPositionBuilderAtEnd(first_builder, first_block);
4156 }
4157
4158 res = LLVMBuildAlloca(first_builder, type, name);
4159 LLVMBuildStore(builder, LLVMConstNull(type), res);
4160
4161 LLVMDisposeBuilder(first_builder);
4162
4163 return res;
4164 }
4165
4166 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4167 LLVMTypeRef type,
4168 const char *name)
4169 {
4170 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4171 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4172 return ptr;
4173 }
4174
4175 static void
4176 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4177 struct nir_variable *variable)
4178 {
4179 int idx = variable->data.location + variable->data.index;
4180 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4181 unsigned mask_attribs;
4182 variable->data.driver_location = idx * 4;
4183
4184 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4185 if (ctx->stage == MESA_SHADER_VERTEX ||
4186 ctx->stage == MESA_SHADER_GEOMETRY) {
4187 if (idx == VARYING_SLOT_CLIP_DIST0) {
4188 int length = ctx->num_output_clips + ctx->num_output_culls;
4189 if (ctx->stage == MESA_SHADER_VERTEX) {
4190 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4191 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4192 }
4193
4194 if (length > 4)
4195 attrib_count = 2;
4196 else
4197 attrib_count = 1;
4198 mask_attribs = 1 << idx;
4199 }
4200 }
4201
4202 for (unsigned i = 0; i < attrib_count; ++i) {
4203 for (unsigned chan = 0; chan < 4; chan++) {
4204 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4205 si_build_alloca_undef(ctx, ctx->f32, "");
4206 }
4207 }
4208 ctx->output_mask |= mask_attribs;
4209 }
4210
4211 static void
4212 setup_locals(struct nir_to_llvm_context *ctx,
4213 struct nir_function *func)
4214 {
4215 int i, j;
4216 ctx->num_locals = 0;
4217 nir_foreach_variable(variable, &func->impl->locals) {
4218 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4219 variable->data.driver_location = ctx->num_locals * 4;
4220 ctx->num_locals += attrib_count;
4221 }
4222 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4223 if (!ctx->locals)
4224 return;
4225
4226 for (i = 0; i < ctx->num_locals; i++) {
4227 for (j = 0; j < 4; j++) {
4228 ctx->locals[i * 4 + j] =
4229 si_build_alloca_undef(ctx, ctx->f32, "temp");
4230 }
4231 }
4232 }
4233
4234 static LLVMValueRef
4235 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4236 {
4237 v = to_float(ctx, v);
4238 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4239 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4240 }
4241
4242
4243 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4244 LLVMValueRef src0, LLVMValueRef src1)
4245 {
4246 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4247 LLVMValueRef comp[2];
4248
4249 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4250 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4251 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4252 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4253 }
4254
4255 /* Initialize arguments for the shader export intrinsic */
4256 static void
4257 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4258 LLVMValueRef *values,
4259 unsigned target,
4260 struct ac_export_args *args)
4261 {
4262 /* Default is 0xf. Adjusted below depending on the format. */
4263 args->enabled_channels = 0xf;
4264
4265 /* Specify whether the EXEC mask represents the valid mask */
4266 args->valid_mask = 0;
4267
4268 /* Specify whether this is the last export */
4269 args->done = 0;
4270
4271 /* Specify the target we are exporting */
4272 args->target = target;
4273
4274 args->compr = false;
4275 args->out[0] = LLVMGetUndef(ctx->f32);
4276 args->out[1] = LLVMGetUndef(ctx->f32);
4277 args->out[2] = LLVMGetUndef(ctx->f32);
4278 args->out[3] = LLVMGetUndef(ctx->f32);
4279
4280 if (!values)
4281 return;
4282
4283 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4284 LLVMValueRef val[4];
4285 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4286 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4287 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4288
4289 switch(col_format) {
4290 case V_028714_SPI_SHADER_ZERO:
4291 args->enabled_channels = 0; /* writemask */
4292 args->target = V_008DFC_SQ_EXP_NULL;
4293 break;
4294
4295 case V_028714_SPI_SHADER_32_R:
4296 args->enabled_channels = 1;
4297 args->out[0] = values[0];
4298 break;
4299
4300 case V_028714_SPI_SHADER_32_GR:
4301 args->enabled_channels = 0x3;
4302 args->out[0] = values[0];
4303 args->out[1] = values[1];
4304 break;
4305
4306 case V_028714_SPI_SHADER_32_AR:
4307 args->enabled_channels = 0x9;
4308 args->out[0] = values[0];
4309 args->out[3] = values[3];
4310 break;
4311
4312 case V_028714_SPI_SHADER_FP16_ABGR:
4313 args->compr = 1;
4314
4315 for (unsigned chan = 0; chan < 2; chan++) {
4316 LLVMValueRef pack_args[2] = {
4317 values[2 * chan],
4318 values[2 * chan + 1]
4319 };
4320 LLVMValueRef packed;
4321
4322 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
4323 args->out[chan] = packed;
4324 }
4325 break;
4326
4327 case V_028714_SPI_SHADER_UNORM16_ABGR:
4328 for (unsigned chan = 0; chan < 4; chan++) {
4329 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
4330 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4331 LLVMConstReal(ctx->f32, 65535), "");
4332 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4333 LLVMConstReal(ctx->f32, 0.5), "");
4334 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4335 ctx->i32, "");
4336 }
4337
4338 args->compr = 1;
4339 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4340 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4341 break;
4342
4343 case V_028714_SPI_SHADER_SNORM16_ABGR:
4344 for (unsigned chan = 0; chan < 4; chan++) {
4345 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4346 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4347 LLVMConstReal(ctx->f32, 32767), "");
4348
4349 /* If positive, add 0.5, else add -0.5. */
4350 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4351 LLVMBuildSelect(ctx->builder,
4352 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4353 val[chan], ctx->f32zero, ""),
4354 LLVMConstReal(ctx->f32, 0.5),
4355 LLVMConstReal(ctx->f32, -0.5), ""), "");
4356 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4357 }
4358
4359 args->compr = 1;
4360 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4361 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4362 break;
4363
4364 case V_028714_SPI_SHADER_UINT16_ABGR: {
4365 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4366
4367 for (unsigned chan = 0; chan < 4; chan++) {
4368 val[chan] = to_integer(ctx, values[chan]);
4369 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4370 }
4371
4372 args->compr = 1;
4373 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4374 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4375 break;
4376 }
4377
4378 case V_028714_SPI_SHADER_SINT16_ABGR: {
4379 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4380 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4381
4382 /* Clamp. */
4383 for (unsigned chan = 0; chan < 4; chan++) {
4384 val[chan] = to_integer(ctx, values[chan]);
4385 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4386 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4387 }
4388
4389 args->compr = 1;
4390 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4391 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4392 break;
4393 }
4394
4395 default:
4396 case V_028714_SPI_SHADER_32_ABGR:
4397 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
4398 break;
4399 }
4400 } else
4401 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
4402
4403 for (unsigned i = 0; i < 4; ++i)
4404 args->out[i] = to_float(ctx, args->out[i]);
4405 }
4406
4407 static void
4408 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
4409 struct ac_vs_output_info *outinfo)
4410 {
4411 uint32_t param_count = 0;
4412 unsigned target;
4413 unsigned pos_idx, num_pos_exports = 0;
4414 struct ac_export_args args, pos_args[4] = {};
4415 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4416 int i;
4417
4418 outinfo->prim_id_output = 0xffffffff;
4419 outinfo->layer_output = 0xffffffff;
4420 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
4421 LLVMValueRef slots[8];
4422 unsigned j;
4423
4424 if (outinfo->cull_dist_mask)
4425 outinfo->cull_dist_mask <<= ctx->num_output_clips;
4426
4427 i = VARYING_SLOT_CLIP_DIST0;
4428 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
4429 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4430 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4431
4432 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
4433 slots[i] = LLVMGetUndef(ctx->f32);
4434
4435 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
4436 target = V_008DFC_SQ_EXP_POS + 3;
4437 si_llvm_init_export_args(ctx, &slots[4], target, &args);
4438 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4439 &args, sizeof(args));
4440 }
4441
4442 target = V_008DFC_SQ_EXP_POS + 2;
4443 si_llvm_init_export_args(ctx, &slots[0], target, &args);
4444 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4445 &args, sizeof(args));
4446
4447 }
4448
4449 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4450 LLVMValueRef values[4];
4451 if (!(ctx->output_mask & (1ull << i)))
4452 continue;
4453
4454 for (unsigned j = 0; j < 4; j++)
4455 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4456 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4457
4458 if (i == VARYING_SLOT_POS) {
4459 target = V_008DFC_SQ_EXP_POS;
4460 } else if (i == VARYING_SLOT_CLIP_DIST0) {
4461 continue;
4462 } else if (i == VARYING_SLOT_PSIZ) {
4463 outinfo->writes_pointsize = true;
4464 psize_value = values[0];
4465 continue;
4466 } else if (i == VARYING_SLOT_LAYER) {
4467 outinfo->writes_layer = true;
4468 layer_value = values[0];
4469 outinfo->layer_output = param_count;
4470 target = V_008DFC_SQ_EXP_PARAM + param_count;
4471 param_count++;
4472 } else if (i == VARYING_SLOT_VIEWPORT) {
4473 outinfo->writes_viewport_index = true;
4474 viewport_index_value = values[0];
4475 continue;
4476 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4477 outinfo->prim_id_output = param_count;
4478 target = V_008DFC_SQ_EXP_PARAM + param_count;
4479 param_count++;
4480 } else if (i >= VARYING_SLOT_VAR0) {
4481 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4482 target = V_008DFC_SQ_EXP_PARAM + param_count;
4483 param_count++;
4484 }
4485
4486 si_llvm_init_export_args(ctx, values, target, &args);
4487
4488 if (target >= V_008DFC_SQ_EXP_POS &&
4489 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4490 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
4491 &args, sizeof(args));
4492 } else {
4493 ac_build_export(&ctx->ac, &args);
4494 }
4495 }
4496
4497 /* We need to add the position output manually if it's missing. */
4498 if (!pos_args[0].out[0]) {
4499 pos_args[0].enabled_channels = 0xf;
4500 pos_args[0].valid_mask = 0;
4501 pos_args[0].done = 0;
4502 pos_args[0].target = V_008DFC_SQ_EXP_POS;
4503 pos_args[0].compr = 0;
4504 pos_args[0].out[0] = ctx->f32zero; /* X */
4505 pos_args[0].out[1] = ctx->f32zero; /* Y */
4506 pos_args[0].out[2] = ctx->f32zero; /* Z */
4507 pos_args[0].out[3] = ctx->f32one; /* W */
4508 }
4509
4510 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
4511 (outinfo->writes_layer == true ? 4 : 0) |
4512 (outinfo->writes_viewport_index == true ? 8 : 0));
4513 if (mask) {
4514 pos_args[1].enabled_channels = mask;
4515 pos_args[1].valid_mask = 0;
4516 pos_args[1].done = 0;
4517 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
4518 pos_args[1].compr = 0;
4519 pos_args[1].out[0] = ctx->f32zero; /* X */
4520 pos_args[1].out[1] = ctx->f32zero; /* Y */
4521 pos_args[1].out[2] = ctx->f32zero; /* Z */
4522 pos_args[1].out[3] = ctx->f32zero; /* W */
4523
4524 if (outinfo->writes_pointsize == true)
4525 pos_args[1].out[0] = psize_value;
4526 if (outinfo->writes_layer == true)
4527 pos_args[1].out[2] = layer_value;
4528 if (outinfo->writes_viewport_index == true)
4529 pos_args[1].out[3] = viewport_index_value;
4530 }
4531 for (i = 0; i < 4; i++) {
4532 if (pos_args[i].out[0])
4533 num_pos_exports++;
4534 }
4535
4536 pos_idx = 0;
4537 for (i = 0; i < 4; i++) {
4538 if (!pos_args[i].out[0])
4539 continue;
4540
4541 /* Specify the target we are exporting */
4542 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
4543 if (pos_idx == num_pos_exports)
4544 pos_args[i].done = 1;
4545 ac_build_export(&ctx->ac, &pos_args[i]);
4546 }
4547
4548 outinfo->pos_exports = num_pos_exports;
4549 outinfo->param_exports = param_count;
4550 }
4551
4552 static void
4553 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
4554 struct ac_es_output_info *outinfo)
4555 {
4556 int j;
4557 uint64_t max_output_written = 0;
4558 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4559 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4560 int param_index;
4561 int length = 4;
4562 int start = 0;
4563 if (!(ctx->output_mask & (1ull << i)))
4564 continue;
4565
4566 if (i == VARYING_SLOT_CLIP_DIST0)
4567 length = ctx->num_output_clips + ctx->num_output_culls;
4568
4569 param_index = shader_io_get_unique_index(i);
4570
4571 if (param_index > max_output_written)
4572 max_output_written = param_index;
4573
4574 for (j = 0; j < length; j++) {
4575 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4576 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4577
4578 ac_build_buffer_store_dword(&ctx->ac,
4579 ctx->esgs_ring,
4580 out_val, 1,
4581 NULL, ctx->es2gs_offset,
4582 (4 * param_index + j + start) * 4,
4583 1, 1, true, true);
4584 }
4585 }
4586 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
4587 }
4588
4589 static void
4590 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4591 LLVMValueRef *color, unsigned param, bool is_last)
4592 {
4593
4594 struct ac_export_args args;
4595
4596 /* Export */
4597 si_llvm_init_export_args(ctx, color, param,
4598 &args);
4599
4600 if (is_last) {
4601 args.valid_mask = 1; /* whether the EXEC mask is valid */
4602 args.done = 1; /* DONE bit */
4603 } else if (!args.enabled_channels)
4604 return; /* unnecessary NULL export */
4605
4606 ac_build_export(&ctx->ac, &args);
4607 }
4608
4609 static void
4610 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4611 LLVMValueRef depth, LLVMValueRef stencil,
4612 LLVMValueRef samplemask)
4613 {
4614 struct ac_export_args args;
4615
4616 args.enabled_channels = 0;
4617 args.valid_mask = 1;
4618 args.done = 1;
4619 args.target = V_008DFC_SQ_EXP_MRTZ;
4620 args.compr = false;
4621
4622 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
4623 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4624 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4625 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4626
4627 if (depth) {
4628 args.out[0] = depth;
4629 args.enabled_channels |= 0x1;
4630 }
4631
4632 if (stencil) {
4633 args.out[1] = stencil;
4634 args.enabled_channels |= 0x2;
4635 }
4636
4637 if (samplemask) {
4638 args.out[2] = samplemask;
4639 args.enabled_channels |= 0x4;
4640 }
4641
4642 /* SI (except OLAND) has a bug that it only looks
4643 * at the X writemask component. */
4644 if (ctx->options->chip_class == SI &&
4645 ctx->options->family != CHIP_OLAND)
4646 args.enabled_channels |= 0x1;
4647
4648 ac_build_export(&ctx->ac, &args);
4649 }
4650
4651 static void
4652 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4653 {
4654 unsigned index = 0;
4655 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4656
4657 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4658 LLVMValueRef values[4];
4659
4660 if (!(ctx->output_mask & (1ull << i)))
4661 continue;
4662
4663 if (i == FRAG_RESULT_DEPTH) {
4664 ctx->shader_info->fs.writes_z = true;
4665 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4666 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4667 } else if (i == FRAG_RESULT_STENCIL) {
4668 ctx->shader_info->fs.writes_stencil = true;
4669 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4670 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4671 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
4672 ctx->shader_info->fs.writes_sample_mask = true;
4673 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
4674 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4675 } else {
4676 bool last = false;
4677 for (unsigned j = 0; j < 4; j++)
4678 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4679 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4680
4681 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
4682 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4683
4684 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4685 index++;
4686 }
4687 }
4688
4689 if (depth || stencil || samplemask)
4690 si_export_mrt_z(ctx, depth, stencil, samplemask);
4691 else if (!index)
4692 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4693
4694 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4695 }
4696
4697 static void
4698 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4699 {
4700 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4701 }
4702
4703 static void
4704 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4705 {
4706 switch (ctx->stage) {
4707 case MESA_SHADER_VERTEX:
4708 if (ctx->options->key.vs.as_es)
4709 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
4710 else
4711 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
4712 break;
4713 case MESA_SHADER_FRAGMENT:
4714 handle_fs_outputs_post(ctx);
4715 break;
4716 case MESA_SHADER_GEOMETRY:
4717 emit_gs_epilogue(ctx);
4718 break;
4719 default:
4720 break;
4721 }
4722 }
4723
4724 static void
4725 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4726 struct nir_variable *variable, uint32_t *offset, int idx)
4727 {
4728 unsigned size = glsl_count_attribute_slots(variable->type, false);
4729 variable->data.driver_location = *offset;
4730 *offset += size;
4731 }
4732
4733 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4734 {
4735 LLVMPassManagerRef passmgr;
4736 /* Create the pass manager */
4737 passmgr = LLVMCreateFunctionPassManagerForModule(
4738 ctx->module);
4739
4740 /* This pass should eliminate all the load and store instructions */
4741 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4742
4743 /* Add some optimization passes */
4744 LLVMAddScalarReplAggregatesPass(passmgr);
4745 LLVMAddLICMPass(passmgr);
4746 LLVMAddAggressiveDCEPass(passmgr);
4747 LLVMAddCFGSimplificationPass(passmgr);
4748 LLVMAddInstructionCombiningPass(passmgr);
4749
4750 /* Run the pass */
4751 LLVMInitializeFunctionPassManager(passmgr);
4752 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4753 LLVMFinalizeFunctionPassManager(passmgr);
4754
4755 LLVMDisposeBuilder(ctx->builder);
4756 LLVMDisposePassManager(passmgr);
4757 }
4758
4759 static void
4760 ac_setup_rings(struct nir_to_llvm_context *ctx)
4761 {
4762 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4763 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4764 }
4765
4766 if (ctx->is_gs_copy_shader) {
4767 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4768 }
4769 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4770 LLVMValueRef tmp;
4771 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4772 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4773
4774 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4775
4776 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4777 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4778 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4779 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4780
4781 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4782 }
4783 }
4784
4785 static
4786 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4787 struct nir_shader *nir,
4788 struct ac_shader_variant_info *shader_info,
4789 const struct ac_nir_compiler_options *options)
4790 {
4791 struct nir_to_llvm_context ctx = {0};
4792 struct nir_function *func;
4793 unsigned i;
4794 ctx.options = options;
4795 ctx.shader_info = shader_info;
4796 ctx.context = LLVMContextCreate();
4797 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4798
4799 ac_llvm_context_init(&ctx.ac, ctx.context);
4800 ctx.ac.module = ctx.module;
4801
4802 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4803
4804 memset(shader_info, 0, sizeof(*shader_info));
4805
4806 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4807
4808 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
4809 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
4810 LLVMSetDataLayout(ctx.module, data_layout_str);
4811 LLVMDisposeTargetData(data_layout);
4812 LLVMDisposeMessage(data_layout_str);
4813
4814 setup_types(&ctx);
4815
4816 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4817 ctx.ac.builder = ctx.builder;
4818 ctx.stage = nir->stage;
4819
4820 for (i = 0; i < AC_UD_MAX_SETS; i++)
4821 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4822 for (i = 0; i < AC_UD_MAX_UD; i++)
4823 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4824
4825 create_function(&ctx);
4826
4827 if (nir->stage == MESA_SHADER_COMPUTE) {
4828 int num_shared = 0;
4829 nir_foreach_variable(variable, &nir->shared)
4830 num_shared++;
4831 if (num_shared) {
4832 int idx = 0;
4833 uint32_t shared_size = 0;
4834 LLVMValueRef var;
4835 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4836 nir_foreach_variable(variable, &nir->shared) {
4837 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4838 idx++;
4839 }
4840
4841 shared_size *= 16;
4842 var = LLVMAddGlobalInAddressSpace(ctx.module,
4843 LLVMArrayType(ctx.i8, shared_size),
4844 "compute_lds",
4845 LOCAL_ADDR_SPACE);
4846 LLVMSetAlignment(var, 4);
4847 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4848 }
4849 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4850 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4851
4852 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4853 }
4854
4855 ac_setup_rings(&ctx);
4856
4857 nir_foreach_variable(variable, &nir->inputs)
4858 handle_shader_input_decl(&ctx, variable);
4859
4860 if (nir->stage == MESA_SHADER_FRAGMENT)
4861 handle_fs_inputs_pre(&ctx, nir);
4862
4863 ctx.num_output_clips = nir->info->clip_distance_array_size;
4864 ctx.num_output_culls = nir->info->cull_distance_array_size;
4865
4866 nir_foreach_variable(variable, &nir->outputs)
4867 handle_shader_output_decl(&ctx, variable);
4868
4869 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4870 _mesa_key_pointer_equal);
4871 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4872 _mesa_key_pointer_equal);
4873
4874 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4875
4876 setup_locals(&ctx, func);
4877
4878 visit_cf_list(&ctx, &func->impl->body);
4879 phi_post_pass(&ctx);
4880
4881 handle_shader_outputs_post(&ctx);
4882 LLVMBuildRetVoid(ctx.builder);
4883
4884 ac_llvm_finalize_module(&ctx);
4885 free(ctx.locals);
4886 ralloc_free(ctx.defs);
4887 ralloc_free(ctx.phis);
4888
4889 if (nir->stage == MESA_SHADER_GEOMETRY) {
4890 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4891 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4892 nir->info->gs.vertices_out;
4893 }
4894 return ctx.module;
4895 }
4896
4897 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4898 {
4899 unsigned *retval = (unsigned *)context;
4900 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4901 char *description = LLVMGetDiagInfoDescription(di);
4902
4903 if (severity == LLVMDSError) {
4904 *retval = 1;
4905 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4906 description);
4907 }
4908
4909 LLVMDisposeMessage(description);
4910 }
4911
4912 static unsigned ac_llvm_compile(LLVMModuleRef M,
4913 struct ac_shader_binary *binary,
4914 LLVMTargetMachineRef tm)
4915 {
4916 unsigned retval = 0;
4917 char *err;
4918 LLVMContextRef llvm_ctx;
4919 LLVMMemoryBufferRef out_buffer;
4920 unsigned buffer_size;
4921 const char *buffer_data;
4922 LLVMBool mem_err;
4923
4924 /* Setup Diagnostic Handler*/
4925 llvm_ctx = LLVMGetModuleContext(M);
4926
4927 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4928 &retval);
4929
4930 /* Compile IR*/
4931 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4932 &err, &out_buffer);
4933
4934 /* Process Errors/Warnings */
4935 if (mem_err) {
4936 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4937 free(err);
4938 retval = 1;
4939 goto out;
4940 }
4941
4942 /* Extract Shader Code*/
4943 buffer_size = LLVMGetBufferSize(out_buffer);
4944 buffer_data = LLVMGetBufferStart(out_buffer);
4945
4946 ac_elf_read(buffer_data, buffer_size, binary);
4947
4948 /* Clean up */
4949 LLVMDisposeMemoryBuffer(out_buffer);
4950
4951 out:
4952 return retval;
4953 }
4954
4955 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4956 LLVMModuleRef llvm_module,
4957 struct ac_shader_binary *binary,
4958 struct ac_shader_config *config,
4959 struct ac_shader_variant_info *shader_info,
4960 gl_shader_stage stage,
4961 bool dump_shader, bool supports_spill)
4962 {
4963 if (dump_shader)
4964 ac_dump_module(llvm_module);
4965
4966 memset(binary, 0, sizeof(*binary));
4967 int v = ac_llvm_compile(llvm_module, binary, tm);
4968 if (v) {
4969 fprintf(stderr, "compile failed\n");
4970 }
4971
4972 if (dump_shader)
4973 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4974
4975 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4976
4977 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4978 LLVMDisposeModule(llvm_module);
4979 LLVMContextDispose(ctx);
4980
4981 if (stage == MESA_SHADER_FRAGMENT) {
4982 shader_info->num_input_vgprs = 0;
4983 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4984 shader_info->num_input_vgprs += 2;
4985 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4986 shader_info->num_input_vgprs += 2;
4987 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4988 shader_info->num_input_vgprs += 2;
4989 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4990 shader_info->num_input_vgprs += 3;
4991 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
4992 shader_info->num_input_vgprs += 2;
4993 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
4994 shader_info->num_input_vgprs += 2;
4995 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
4996 shader_info->num_input_vgprs += 2;
4997 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
4998 shader_info->num_input_vgprs += 1;
4999 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5000 shader_info->num_input_vgprs += 1;
5001 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5002 shader_info->num_input_vgprs += 1;
5003 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5004 shader_info->num_input_vgprs += 1;
5005 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5006 shader_info->num_input_vgprs += 1;
5007 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5008 shader_info->num_input_vgprs += 1;
5009 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5010 shader_info->num_input_vgprs += 1;
5011 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5012 shader_info->num_input_vgprs += 1;
5013 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5014 shader_info->num_input_vgprs += 1;
5015 }
5016 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5017
5018 /* +3 for scratch wave offset and VCC */
5019 config->num_sgprs = MAX2(config->num_sgprs,
5020 shader_info->num_input_sgprs + 3);
5021 }
5022
5023 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5024 struct ac_shader_binary *binary,
5025 struct ac_shader_config *config,
5026 struct ac_shader_variant_info *shader_info,
5027 struct nir_shader *nir,
5028 const struct ac_nir_compiler_options *options,
5029 bool dump_shader)
5030 {
5031
5032 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5033 options);
5034
5035 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5036 switch (nir->stage) {
5037 case MESA_SHADER_COMPUTE:
5038 for (int i = 0; i < 3; ++i)
5039 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5040 break;
5041 case MESA_SHADER_FRAGMENT:
5042 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5043 break;
5044 case MESA_SHADER_GEOMETRY:
5045 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5046 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5047 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5048 shader_info->gs.invocations = nir->info->gs.invocations;
5049 break;
5050 case MESA_SHADER_VERTEX:
5051 shader_info->vs.as_es = options->key.vs.as_es;
5052 break;
5053 default:
5054 break;
5055 }
5056 }
5057
5058 static void
5059 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5060 {
5061 LLVMValueRef args[9];
5062 args[0] = ctx->gsvs_ring;
5063 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5064 args[3] = ctx->i32zero;
5065 args[4] = ctx->i32one; /* OFFEN */
5066 args[5] = ctx->i32zero; /* IDXEN */
5067 args[6] = ctx->i32one; /* GLC */
5068 args[7] = ctx->i32one; /* SLC */
5069 args[8] = ctx->i32zero; /* TFE */
5070
5071 int idx = 0;
5072
5073 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5074 int length = 4;
5075 int slot = idx;
5076 int slot_inc = 1;
5077 if (!(ctx->output_mask & (1ull << i)))
5078 continue;
5079
5080 if (i == VARYING_SLOT_CLIP_DIST0) {
5081 /* unpack clip and cull from a single set of slots */
5082 length = ctx->num_output_clips + ctx->num_output_culls;
5083 if (length > 4)
5084 slot_inc = 2;
5085 }
5086
5087 for (unsigned j = 0; j < length; j++) {
5088 LLVMValueRef value;
5089 args[2] = LLVMConstInt(ctx->i32,
5090 (slot * 4 + j) *
5091 ctx->gs_max_out_vertices * 16 * 4, false);
5092
5093 value = ac_build_intrinsic(&ctx->ac,
5094 "llvm.SI.buffer.load.dword.i32.i32",
5095 ctx->i32, args, 9,
5096 AC_FUNC_ATTR_READONLY |
5097 AC_FUNC_ATTR_LEGACY);
5098
5099 LLVMBuildStore(ctx->builder,
5100 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5101 }
5102 idx += slot_inc;
5103 }
5104 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5105 }
5106
5107 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5108 struct nir_shader *geom_shader,
5109 struct ac_shader_binary *binary,
5110 struct ac_shader_config *config,
5111 struct ac_shader_variant_info *shader_info,
5112 const struct ac_nir_compiler_options *options,
5113 bool dump_shader)
5114 {
5115 struct nir_to_llvm_context ctx = {0};
5116 ctx.context = LLVMContextCreate();
5117 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5118 ctx.options = options;
5119 ctx.shader_info = shader_info;
5120
5121 ac_llvm_context_init(&ctx.ac, ctx.context);
5122 ctx.ac.module = ctx.module;
5123
5124 ctx.is_gs_copy_shader = true;
5125 LLVMSetTarget(ctx.module, "amdgcn--");
5126 setup_types(&ctx);
5127
5128 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5129 ctx.ac.builder = ctx.builder;
5130 ctx.stage = MESA_SHADER_VERTEX;
5131
5132 create_function(&ctx);
5133
5134 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5135 ac_setup_rings(&ctx);
5136
5137 ctx.num_output_clips = geom_shader->info->clip_distance_array_size;
5138 ctx.num_output_culls = geom_shader->info->cull_distance_array_size;
5139
5140 nir_foreach_variable(variable, &geom_shader->outputs)
5141 handle_shader_output_decl(&ctx, variable);
5142
5143 ac_gs_copy_shader_emit(&ctx);
5144
5145 LLVMBuildRetVoid(ctx.builder);
5146
5147 ac_llvm_finalize_module(&ctx);
5148
5149 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5150 MESA_SHADER_VERTEX,
5151 dump_shader, options->supports_spill);
5152 }