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ac/nir: add always_vector argument to ac_build_gather_values_extended
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct nir_to_llvm_context;
51
52 struct ac_nir_context {
53 struct ac_llvm_context ac;
54 struct ac_shader_abi *abi;
55
56 gl_shader_stage stage;
57
58 struct hash_table *defs;
59 struct hash_table *phis;
60 struct hash_table *vars;
61
62 LLVMValueRef main_function;
63 LLVMBasicBlockRef continue_block;
64 LLVMBasicBlockRef break_block;
65
66 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
67
68 int num_locals;
69 LLVMValueRef *locals;
70
71 LLVMValueRef ddxy_lds;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef tess_factor_offset;
112 LLVMValueRef tcs_patch_id;
113 LLVMValueRef tcs_rel_ids;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_patch_id;
116 LLVMValueRef tes_u;
117 LLVMValueRef tes_v;
118
119 LLVMValueRef gsvs_ring_stride;
120 LLVMValueRef gsvs_num_entries;
121 LLVMValueRef gs2vs_offset;
122 LLVMValueRef gs_wave_id;
123 LLVMValueRef gs_vtx_offset[6];
124 LLVMValueRef gs_prim_id, gs_invocation_id;
125
126 LLVMValueRef esgs_ring;
127 LLVMValueRef gsvs_ring;
128 LLVMValueRef hs_ring_tess_offchip;
129 LLVMValueRef hs_ring_tess_factor;
130
131 LLVMValueRef prim_mask;
132 LLVMValueRef sample_pos_offset;
133 LLVMValueRef persp_sample, persp_center, persp_centroid;
134 LLVMValueRef linear_sample, linear_center, linear_centroid;
135 LLVMValueRef ancillary;
136 LLVMValueRef sample_coverage;
137 LLVMValueRef frag_pos[4];
138
139 LLVMTypeRef i1;
140 LLVMTypeRef i8;
141 LLVMTypeRef i16;
142 LLVMTypeRef i32;
143 LLVMTypeRef i64;
144 LLVMTypeRef v2i32;
145 LLVMTypeRef v3i32;
146 LLVMTypeRef v4i32;
147 LLVMTypeRef v8i32;
148 LLVMTypeRef f64;
149 LLVMTypeRef f32;
150 LLVMTypeRef f16;
151 LLVMTypeRef v2f32;
152 LLVMTypeRef v4f32;
153 LLVMTypeRef voidt;
154
155 LLVMValueRef i1true;
156 LLVMValueRef i1false;
157 LLVMValueRef i32zero;
158 LLVMValueRef i32one;
159 LLVMValueRef f32zero;
160 LLVMValueRef f32one;
161 LLVMValueRef v4f32empty;
162
163 unsigned uniform_md_kind;
164 LLVMValueRef empty_md;
165 gl_shader_stage stage;
166
167 LLVMValueRef lds;
168 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
169
170 uint64_t input_mask;
171 uint64_t output_mask;
172 uint8_t num_output_clips;
173 uint8_t num_output_culls;
174
175 bool is_gs_copy_shader;
176 LLVMValueRef gs_next_vertex;
177 unsigned gs_max_out_vertices;
178
179 unsigned tes_primitive_mode;
180 uint64_t tess_outputs_written;
181 uint64_t tess_patch_outputs_written;
182 };
183
184 static inline struct nir_to_llvm_context *
185 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
186 {
187 struct nir_to_llvm_context *ctx = NULL;
188 return container_of(abi, ctx, abi);
189 }
190
191 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
192 const nir_deref_var *deref,
193 enum ac_descriptor_type desc_type,
194 bool image, bool write);
195
196 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
197 {
198 return (index * 4) + chan;
199 }
200
201 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
202 {
203 /* handle patch indices separate */
204 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
205 return 0;
206 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
207 return 1;
208 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
209 return 2 + (slot - VARYING_SLOT_PATCH0);
210
211 if (slot == VARYING_SLOT_POS)
212 return 0;
213 if (slot == VARYING_SLOT_PSIZ)
214 return 1;
215 if (slot == VARYING_SLOT_CLIP_DIST0)
216 return 2;
217 /* 3 is reserved for clip dist as well */
218 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
219 return 4 + (slot - VARYING_SLOT_VAR0);
220 unreachable("illegal slot in get unique index\n");
221 }
222
223 static unsigned llvm_get_type_size(LLVMTypeRef type)
224 {
225 LLVMTypeKind kind = LLVMGetTypeKind(type);
226
227 switch (kind) {
228 case LLVMIntegerTypeKind:
229 return LLVMGetIntTypeWidth(type) / 8;
230 case LLVMFloatTypeKind:
231 return 4;
232 case LLVMPointerTypeKind:
233 return 8;
234 case LLVMVectorTypeKind:
235 return LLVMGetVectorSize(type) *
236 llvm_get_type_size(LLVMGetElementType(type));
237 default:
238 assert(0);
239 return 0;
240 }
241 }
242
243 static void set_llvm_calling_convention(LLVMValueRef func,
244 gl_shader_stage stage)
245 {
246 enum radeon_llvm_calling_convention calling_conv;
247
248 switch (stage) {
249 case MESA_SHADER_VERTEX:
250 case MESA_SHADER_TESS_CTRL:
251 case MESA_SHADER_TESS_EVAL:
252 calling_conv = RADEON_LLVM_AMDGPU_VS;
253 break;
254 case MESA_SHADER_GEOMETRY:
255 calling_conv = RADEON_LLVM_AMDGPU_GS;
256 break;
257 case MESA_SHADER_FRAGMENT:
258 calling_conv = RADEON_LLVM_AMDGPU_PS;
259 break;
260 case MESA_SHADER_COMPUTE:
261 calling_conv = RADEON_LLVM_AMDGPU_CS;
262 break;
263 default:
264 unreachable("Unhandle shader type");
265 }
266
267 LLVMSetFunctionCallConv(func, calling_conv);
268 }
269
270 #define MAX_ARGS 23
271 struct arg_info {
272 LLVMTypeRef types[MAX_ARGS];
273 LLVMValueRef *assign[MAX_ARGS];
274 unsigned array_params_mask;
275 uint8_t count;
276 uint8_t user_sgpr_count;
277 uint8_t sgpr_count;
278 uint8_t num_user_sgprs_used;
279 uint8_t num_sgprs_used;
280 uint8_t num_vgprs_used;
281 };
282
283 static inline void
284 add_argument(struct arg_info *info,
285 LLVMTypeRef type, LLVMValueRef *param_ptr)
286 {
287 assert(info->count < MAX_ARGS);
288 info->assign[info->count] = param_ptr;
289 info->types[info->count] = type;
290 info->count++;
291 }
292
293 static inline void
294 add_sgpr_argument(struct arg_info *info,
295 LLVMTypeRef type, LLVMValueRef *param_ptr)
296 {
297 add_argument(info, type, param_ptr);
298 info->num_sgprs_used += llvm_get_type_size(type) / 4;
299 info->sgpr_count++;
300 }
301
302 static inline void
303 add_user_sgpr_argument(struct arg_info *info,
304 LLVMTypeRef type,
305 LLVMValueRef *param_ptr)
306 {
307 add_sgpr_argument(info, type, param_ptr);
308 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
309 info->user_sgpr_count++;
310 }
311
312 static inline void
313 add_vgpr_argument(struct arg_info *info,
314 LLVMTypeRef type,
315 LLVMValueRef *param_ptr)
316 {
317 add_argument(info, type, param_ptr);
318 info->num_vgprs_used += llvm_get_type_size(type) / 4;
319 }
320
321 static inline void
322 add_user_sgpr_array_argument(struct arg_info *info,
323 LLVMTypeRef type,
324 LLVMValueRef *param_ptr)
325 {
326 info->array_params_mask |= (1 << info->count);
327 add_user_sgpr_argument(info, type, param_ptr);
328 }
329
330 static void assign_arguments(LLVMValueRef main_function,
331 struct arg_info *info)
332 {
333 unsigned i;
334 for (i = 0; i < info->count; i++) {
335 if (info->assign[i])
336 *info->assign[i] = LLVMGetParam(main_function, i);
337 }
338 }
339
340 static LLVMValueRef
341 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
342 LLVMBuilderRef builder, LLVMTypeRef *return_types,
343 unsigned num_return_elems,
344 struct arg_info *args,
345 unsigned max_workgroup_size,
346 bool unsafe_math)
347 {
348 LLVMTypeRef main_function_type, ret_type;
349 LLVMBasicBlockRef main_function_body;
350
351 if (num_return_elems)
352 ret_type = LLVMStructTypeInContext(ctx, return_types,
353 num_return_elems, true);
354 else
355 ret_type = LLVMVoidTypeInContext(ctx);
356
357 /* Setup the function */
358 main_function_type =
359 LLVMFunctionType(ret_type, args->types, args->count, 0);
360 LLVMValueRef main_function =
361 LLVMAddFunction(module, "main", main_function_type);
362 main_function_body =
363 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
364 LLVMPositionBuilderAtEnd(builder, main_function_body);
365
366 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
367 for (unsigned i = 0; i < args->sgpr_count; ++i) {
368 if (args->array_params_mask & (1 << i)) {
369 LLVMValueRef P = LLVMGetParam(main_function, i);
370 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
371 ac_add_attr_dereferenceable(P, UINT64_MAX);
372 }
373 else {
374 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
375 }
376 }
377
378 if (max_workgroup_size) {
379 ac_llvm_add_target_dep_function_attr(main_function,
380 "amdgpu-max-work-group-size",
381 max_workgroup_size);
382 }
383 if (unsafe_math) {
384 /* These were copied from some LLVM test. */
385 LLVMAddTargetDependentFunctionAttr(main_function,
386 "less-precise-fpmad",
387 "true");
388 LLVMAddTargetDependentFunctionAttr(main_function,
389 "no-infs-fp-math",
390 "true");
391 LLVMAddTargetDependentFunctionAttr(main_function,
392 "no-nans-fp-math",
393 "true");
394 LLVMAddTargetDependentFunctionAttr(main_function,
395 "unsafe-fp-math",
396 "true");
397 }
398 return main_function;
399 }
400
401 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
402 {
403 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
404 CONST_ADDR_SPACE);
405 }
406
407 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
408 {
409 if (t == ctx->f16 || t == ctx->i16)
410 return ctx->i16;
411 else if (t == ctx->f32 || t == ctx->i32)
412 return ctx->i32;
413 else if (t == ctx->f64 || t == ctx->i64)
414 return ctx->i64;
415 else
416 unreachable("Unhandled integer size");
417 }
418
419 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
420 {
421 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
422 LLVMTypeRef elem_type = LLVMGetElementType(t);
423 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
424 LLVMGetVectorSize(t));
425 }
426 return to_integer_type_scalar(ctx, t);
427 }
428
429 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
430 {
431 LLVMTypeRef type = LLVMTypeOf(v);
432 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
433 }
434
435 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
436 {
437 if (t == ctx->i16 || t == ctx->f16)
438 return ctx->f16;
439 else if (t == ctx->i32 || t == ctx->f32)
440 return ctx->f32;
441 else if (t == ctx->i64 || t == ctx->f64)
442 return ctx->f64;
443 else
444 unreachable("Unhandled float size");
445 }
446
447 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
448 {
449 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
450 LLVMTypeRef elem_type = LLVMGetElementType(t);
451 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
452 LLVMGetVectorSize(t));
453 }
454 return to_float_type_scalar(ctx, t);
455 }
456
457 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
458 {
459 LLVMTypeRef type = LLVMTypeOf(v);
460 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
461 }
462
463 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
464 {
465 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
466 type = LLVMGetElementType(type);
467
468 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
469 return LLVMGetIntTypeWidth(type);
470
471 if (type == ctx->f16)
472 return 16;
473 if (type == ctx->f32)
474 return 32;
475 if (type == ctx->f64)
476 return 64;
477
478 unreachable("Unhandled type kind in get_elem_bits");
479 }
480
481 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
482 LLVMValueRef param, unsigned rshift,
483 unsigned bitwidth)
484 {
485 LLVMValueRef value = param;
486 if (rshift)
487 value = LLVMBuildLShr(ctx->builder, value,
488 LLVMConstInt(ctx->i32, rshift, false), "");
489
490 if (rshift + bitwidth < 32) {
491 unsigned mask = (1 << bitwidth) - 1;
492 value = LLVMBuildAnd(ctx->builder, value,
493 LLVMConstInt(ctx->i32, mask, false), "");
494 }
495 return value;
496 }
497
498 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
499 {
500 switch (ctx->stage) {
501 case MESA_SHADER_TESS_CTRL:
502 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
503 case MESA_SHADER_TESS_EVAL:
504 return ctx->tes_rel_patch_id;
505 break;
506 default:
507 unreachable("Illegal stage");
508 }
509 }
510
511 /* Tessellation shaders pass outputs to the next shader using LDS.
512 *
513 * LS outputs = TCS inputs
514 * TCS outputs = TES inputs
515 *
516 * The LDS layout is:
517 * - TCS inputs for patch 0
518 * - TCS inputs for patch 1
519 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
520 * - ...
521 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
522 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
523 * - TCS outputs for patch 1
524 * - Per-patch TCS outputs for patch 1
525 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
526 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
527 * - ...
528 *
529 * All three shaders VS(LS), TCS, TES share the same LDS space.
530 */
531 static LLVMValueRef
532 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
533 {
534 if (ctx->stage == MESA_SHADER_VERTEX)
535 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
536 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
537 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
538 else {
539 assert(0);
540 return NULL;
541 }
542 }
543
544 static LLVMValueRef
545 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
546 {
547 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
548 }
549
550 static LLVMValueRef
551 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
552 {
553 return LLVMBuildMul(ctx->builder,
554 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
555 LLVMConstInt(ctx->i32, 4, false), "");
556 }
557
558 static LLVMValueRef
559 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
560 {
561 return LLVMBuildMul(ctx->builder,
562 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
563 LLVMConstInt(ctx->i32, 4, false), "");
564 }
565
566 static LLVMValueRef
567 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
568 {
569 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
570 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
571
572 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
573 }
574
575 static LLVMValueRef
576 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
577 {
578 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
579 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
580 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
581
582 return LLVMBuildAdd(ctx->builder, patch0_offset,
583 LLVMBuildMul(ctx->builder, patch_stride,
584 rel_patch_id, ""),
585 "");
586 }
587
588 static LLVMValueRef
589 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
590 {
591 LLVMValueRef patch0_patch_data_offset =
592 get_tcs_out_patch0_patch_data_offset(ctx);
593 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
594 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
595
596 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
597 LLVMBuildMul(ctx->builder, patch_stride,
598 rel_patch_id, ""),
599 "");
600 }
601
602 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
603 {
604 ud_info->sgpr_idx = *sgpr_idx;
605 ud_info->num_sgprs = num_sgprs;
606 ud_info->indirect = false;
607 ud_info->indirect_offset = 0;
608 *sgpr_idx += num_sgprs;
609 }
610
611 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
612 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
613 {
614 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
615 }
616
617
618 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
619 uint32_t indirect_offset)
620 {
621 ud_info->sgpr_idx = sgpr_idx;
622 ud_info->num_sgprs = num_sgprs;
623 ud_info->indirect = true;
624 ud_info->indirect_offset = indirect_offset;
625 }
626
627 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
628 {
629 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
630 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
631 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
632 "tess_lds");
633 }
634
635 struct user_sgpr_info {
636 bool need_ring_offsets;
637 uint8_t sgpr_count;
638 bool indirect_all_descriptor_sets;
639 };
640
641 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
642 struct user_sgpr_info *user_sgpr_info)
643 {
644 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
645
646 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
647 if (ctx->stage == MESA_SHADER_GEOMETRY ||
648 ctx->stage == MESA_SHADER_VERTEX ||
649 ctx->stage == MESA_SHADER_TESS_CTRL ||
650 ctx->stage == MESA_SHADER_TESS_EVAL ||
651 ctx->is_gs_copy_shader)
652 user_sgpr_info->need_ring_offsets = true;
653
654 if (ctx->stage == MESA_SHADER_FRAGMENT &&
655 ctx->shader_info->info.ps.needs_sample_positions)
656 user_sgpr_info->need_ring_offsets = true;
657
658 /* 2 user sgprs will nearly always be allocated for scratch/rings */
659 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
660 user_sgpr_info->sgpr_count += 2;
661 }
662
663 switch (ctx->stage) {
664 case MESA_SHADER_COMPUTE:
665 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
666 break;
667 case MESA_SHADER_FRAGMENT:
668 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
669 break;
670 case MESA_SHADER_VERTEX:
671 if (!ctx->is_gs_copy_shader) {
672 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
673 if (ctx->shader_info->info.vs.needs_draw_id) {
674 user_sgpr_info->sgpr_count += 3;
675 } else {
676 user_sgpr_info->sgpr_count += 2;
677 }
678 }
679 if (ctx->options->key.vs.as_ls)
680 user_sgpr_info->sgpr_count++;
681 break;
682 case MESA_SHADER_TESS_CTRL:
683 user_sgpr_info->sgpr_count += 4;
684 break;
685 case MESA_SHADER_TESS_EVAL:
686 user_sgpr_info->sgpr_count += 1;
687 break;
688 case MESA_SHADER_GEOMETRY:
689 user_sgpr_info->sgpr_count += 2;
690 break;
691 default:
692 break;
693 }
694
695 if (ctx->shader_info->info.needs_push_constants)
696 user_sgpr_info->sgpr_count += 2;
697
698 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
699 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
700 user_sgpr_info->sgpr_count += 2;
701 user_sgpr_info->indirect_all_descriptor_sets = true;
702 } else {
703 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
704 }
705 }
706
707 static void create_function(struct nir_to_llvm_context *ctx)
708 {
709 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
710 uint8_t user_sgpr_idx;
711 struct user_sgpr_info user_sgpr_info;
712 struct arg_info args = {};
713 LLVMValueRef desc_sets;
714
715 allocate_user_sgprs(ctx, &user_sgpr_info);
716 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
717 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
718 }
719
720 /* 1 for each descriptor set */
721 if (!user_sgpr_info.indirect_all_descriptor_sets) {
722 for (unsigned i = 0; i < num_sets; ++i) {
723 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
724 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
725 }
726 }
727 } else
728 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
729
730 if (ctx->shader_info->info.needs_push_constants) {
731 /* 1 for push constants and dynamic descriptors */
732 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
733 }
734
735 switch (ctx->stage) {
736 case MESA_SHADER_COMPUTE:
737 if (ctx->shader_info->info.cs.grid_components_used)
738 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
739 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
740 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
741 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
742 break;
743 case MESA_SHADER_VERTEX:
744 if (!ctx->is_gs_copy_shader) {
745 if (ctx->shader_info->info.vs.has_vertex_buffers)
746 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
747 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
748 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
749 if (ctx->shader_info->info.vs.needs_draw_id)
750 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
751 }
752 if (ctx->options->key.vs.as_es)
753 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
754 else if (ctx->options->key.vs.as_ls)
755 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
756 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
757 if (!ctx->is_gs_copy_shader) {
758 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
759 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
760 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
761 }
762 break;
763 case MESA_SHADER_TESS_CTRL:
764 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
765 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
766 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
767 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
768 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
769 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
770 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
771 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
772 break;
773 case MESA_SHADER_TESS_EVAL:
774 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
775 if (ctx->options->key.tes.as_es) {
776 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
777 add_sgpr_argument(&args, ctx->i32, NULL); //
778 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
779 } else {
780 add_sgpr_argument(&args, ctx->i32, NULL); //
781 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
782 }
783 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
784 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
785 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
786 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
787 break;
788 case MESA_SHADER_GEOMETRY:
789 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
790 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
791 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
792 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
793 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
796 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
797 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
798 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
799 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
800 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
801 break;
802 case MESA_SHADER_FRAGMENT:
803 if (ctx->shader_info->info.ps.needs_sample_positions)
804 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
805 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
806 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
807 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
808 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
809 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
810 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
811 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
812 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
813 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
814 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos x float */
815 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos y float */
816 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos z float */
817 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos w float */
818 add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /* front face */
819 add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /* ancillary */
820 add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /* sample coverage */
821 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
822 break;
823 default:
824 unreachable("Shader stage not implemented");
825 }
826
827 ctx->main_function = create_llvm_function(
828 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
829 ctx->max_workgroup_size,
830 ctx->options->unsafe_math);
831 set_llvm_calling_convention(ctx->main_function, ctx->stage);
832
833
834 ctx->shader_info->num_input_vgprs = 0;
835 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
836 ctx->options->supports_spill ? 2 : 0;
837
838 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
839 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
840
841 if (ctx->stage != MESA_SHADER_FRAGMENT)
842 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
843
844 assign_arguments(ctx->main_function, &args);
845
846 user_sgpr_idx = 0;
847
848 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
849 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
850 if (ctx->options->supports_spill) {
851 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
852 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
853 NULL, 0, AC_FUNC_ATTR_READNONE);
854 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
855 const_array(ctx->v4i32, 16), "");
856 }
857 }
858
859 if (!user_sgpr_info.indirect_all_descriptor_sets) {
860 for (unsigned i = 0; i < num_sets; ++i) {
861 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
862 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
863 } else
864 ctx->descriptor_sets[i] = NULL;
865 }
866 } else {
867 uint32_t desc_sgpr_idx = user_sgpr_idx;
868 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
869
870 for (unsigned i = 0; i < num_sets; ++i) {
871 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
872 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
873 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
874
875 } else
876 ctx->descriptor_sets[i] = NULL;
877 }
878 ctx->shader_info->need_indirect_descriptor_sets = true;
879 }
880
881 if (ctx->shader_info->info.needs_push_constants) {
882 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
883 }
884
885 switch (ctx->stage) {
886 case MESA_SHADER_COMPUTE:
887 if (ctx->shader_info->info.cs.grid_components_used) {
888 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
889 }
890 break;
891 case MESA_SHADER_VERTEX:
892 if (!ctx->is_gs_copy_shader) {
893 if (ctx->shader_info->info.vs.has_vertex_buffers) {
894 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
895 }
896 unsigned vs_num = 2;
897 if (ctx->shader_info->info.vs.needs_draw_id)
898 vs_num++;
899
900 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
901 }
902 if (ctx->options->key.vs.as_ls) {
903 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
904 }
905 if (ctx->options->key.vs.as_ls)
906 declare_tess_lds(ctx);
907 break;
908 case MESA_SHADER_TESS_CTRL:
909 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
910 declare_tess_lds(ctx);
911 break;
912 case MESA_SHADER_TESS_EVAL:
913 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
914 break;
915 case MESA_SHADER_GEOMETRY:
916 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
917 break;
918 case MESA_SHADER_FRAGMENT:
919 if (ctx->shader_info->info.ps.needs_sample_positions) {
920 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
921 }
922 break;
923 default:
924 unreachable("Shader stage not implemented");
925 }
926 }
927
928 static void setup_types(struct nir_to_llvm_context *ctx)
929 {
930 LLVMValueRef args[4];
931
932 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
933 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
934 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
935 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
936 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
937 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
938 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
939 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
940 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
941 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
942 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
943 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
944 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
945 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
946 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
947
948 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
949 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
950 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
951 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
952 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
953 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
954
955 args[0] = ctx->f32zero;
956 args[1] = ctx->f32zero;
957 args[2] = ctx->f32zero;
958 args[3] = ctx->f32one;
959 ctx->v4f32empty = LLVMConstVector(args, 4);
960
961 ctx->uniform_md_kind =
962 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
963 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
964
965 args[0] = LLVMConstReal(ctx->f32, 2.5);
966 }
967
968 static int get_llvm_num_components(LLVMValueRef value)
969 {
970 LLVMTypeRef type = LLVMTypeOf(value);
971 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
972 ? LLVMGetVectorSize(type)
973 : 1;
974 return num_components;
975 }
976
977 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
978 LLVMValueRef value,
979 int index)
980 {
981 int count = get_llvm_num_components(value);
982
983 assert(index < count);
984 if (count == 1)
985 return value;
986
987 return LLVMBuildExtractElement(ac->builder, value,
988 LLVMConstInt(ac->i32, index, false), "");
989 }
990
991 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
992 LLVMValueRef value, unsigned count)
993 {
994 unsigned num_components = get_llvm_num_components(value);
995 if (count == num_components)
996 return value;
997
998 LLVMValueRef masks[] = {
999 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1000 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1001
1002 if (count == 1)
1003 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1004 "");
1005
1006 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1007 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1008 }
1009
1010 static void
1011 build_store_values_extended(struct ac_llvm_context *ac,
1012 LLVMValueRef *values,
1013 unsigned value_count,
1014 unsigned value_stride,
1015 LLVMValueRef vec)
1016 {
1017 LLVMBuilderRef builder = ac->builder;
1018 unsigned i;
1019
1020 for (i = 0; i < value_count; i++) {
1021 LLVMValueRef ptr = values[i * value_stride];
1022 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1023 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1024 LLVMBuildStore(builder, value, ptr);
1025 }
1026 }
1027
1028 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1029 const nir_ssa_def *def)
1030 {
1031 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1032 if (def->num_components > 1) {
1033 type = LLVMVectorType(type, def->num_components);
1034 }
1035 return type;
1036 }
1037
1038 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1039 {
1040 assert(src.is_ssa);
1041 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1042 return (LLVMValueRef)entry->data;
1043 }
1044
1045
1046 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1047 const struct nir_block *b)
1048 {
1049 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1050 return (LLVMBasicBlockRef)entry->data;
1051 }
1052
1053 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1054 nir_alu_src src,
1055 unsigned num_components)
1056 {
1057 LLVMValueRef value = get_src(ctx, src.src);
1058 bool need_swizzle = false;
1059
1060 assert(value);
1061 LLVMTypeRef type = LLVMTypeOf(value);
1062 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1063 ? LLVMGetVectorSize(type)
1064 : 1;
1065
1066 for (unsigned i = 0; i < num_components; ++i) {
1067 assert(src.swizzle[i] < src_components);
1068 if (src.swizzle[i] != i)
1069 need_swizzle = true;
1070 }
1071
1072 if (need_swizzle || num_components != src_components) {
1073 LLVMValueRef masks[] = {
1074 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1075 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1076 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1077 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1078
1079 if (src_components > 1 && num_components == 1) {
1080 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1081 masks[0], "");
1082 } else if (src_components == 1 && num_components > 1) {
1083 LLVMValueRef values[] = {value, value, value, value};
1084 value = ac_build_gather_values(&ctx->ac, values, num_components);
1085 } else {
1086 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1087 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1088 swizzle, "");
1089 }
1090 }
1091 assert(!src.negate);
1092 assert(!src.abs);
1093 return value;
1094 }
1095
1096 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1097 LLVMIntPredicate pred, LLVMValueRef src0,
1098 LLVMValueRef src1)
1099 {
1100 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1101 return LLVMBuildSelect(ctx->builder, result,
1102 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1103 LLVMConstInt(ctx->i32, 0, false), "");
1104 }
1105
1106 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1107 LLVMRealPredicate pred, LLVMValueRef src0,
1108 LLVMValueRef src1)
1109 {
1110 LLVMValueRef result;
1111 src0 = to_float(ctx, src0);
1112 src1 = to_float(ctx, src1);
1113 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1114 return LLVMBuildSelect(ctx->builder, result,
1115 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1116 LLVMConstInt(ctx->i32, 0, false), "");
1117 }
1118
1119 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1120 const char *intrin,
1121 LLVMTypeRef result_type,
1122 LLVMValueRef src0)
1123 {
1124 char name[64];
1125 LLVMValueRef params[] = {
1126 to_float(ctx, src0),
1127 };
1128
1129 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1130 get_elem_bits(ctx, result_type));
1131 assert(length < sizeof(name));
1132 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1133 }
1134
1135 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1136 const char *intrin,
1137 LLVMTypeRef result_type,
1138 LLVMValueRef src0, LLVMValueRef src1)
1139 {
1140 char name[64];
1141 LLVMValueRef params[] = {
1142 to_float(ctx, src0),
1143 to_float(ctx, src1),
1144 };
1145
1146 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1147 get_elem_bits(ctx, result_type));
1148 assert(length < sizeof(name));
1149 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1150 }
1151
1152 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1153 const char *intrin,
1154 LLVMTypeRef result_type,
1155 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1156 {
1157 char name[64];
1158 LLVMValueRef params[] = {
1159 to_float(ctx, src0),
1160 to_float(ctx, src1),
1161 to_float(ctx, src2),
1162 };
1163
1164 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1165 get_elem_bits(ctx, result_type));
1166 assert(length < sizeof(name));
1167 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1168 }
1169
1170 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1171 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1172 {
1173 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1174 ctx->i32_0, "");
1175 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1176 }
1177
1178 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1179 LLVMValueRef src0)
1180 {
1181 LLVMValueRef params[2] = {
1182 src0,
1183
1184 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1185 * add special code to check for x=0. The reason is that
1186 * the LLVM behavior for x=0 is different from what we
1187 * need here.
1188 *
1189 * The hardware already implements the correct behavior.
1190 */
1191 LLVMConstInt(ctx->i1, 1, false),
1192 };
1193 return ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1194 }
1195
1196 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1197 LLVMValueRef src0)
1198 {
1199 return ac_build_imsb(ctx, src0, ctx->i32);
1200 }
1201
1202 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1203 LLVMValueRef src0)
1204 {
1205 return ac_build_umsb(ctx, src0, ctx->i32);
1206 }
1207
1208 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1209 LLVMIntPredicate pred,
1210 LLVMValueRef src0, LLVMValueRef src1)
1211 {
1212 return LLVMBuildSelect(ctx->builder,
1213 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1214 src0,
1215 src1, "");
1216
1217 }
1218 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1219 LLVMValueRef src0)
1220 {
1221 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1222 LLVMBuildNeg(ctx->builder, src0, ""));
1223 }
1224
1225 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1226 LLVMValueRef src0)
1227 {
1228 LLVMValueRef cmp, val;
1229
1230 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1231 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1232 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1233 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1234 return val;
1235 }
1236
1237 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1238 LLVMValueRef src0)
1239 {
1240 LLVMValueRef cmp, val;
1241
1242 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1243 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1244 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1245 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1246 return val;
1247 }
1248
1249 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1250 LLVMValueRef src0)
1251 {
1252 const char *intr = "llvm.floor.f32";
1253 LLVMValueRef fsrc0 = to_float(ctx, src0);
1254 LLVMValueRef params[] = {
1255 fsrc0,
1256 };
1257 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1258 ctx->f32, params, 1,
1259 AC_FUNC_ATTR_READNONE);
1260 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1261 }
1262
1263 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1264 const char *intrin,
1265 LLVMValueRef src0, LLVMValueRef src1)
1266 {
1267 LLVMTypeRef ret_type;
1268 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1269 LLVMValueRef res;
1270 LLVMValueRef params[] = { src0, src1 };
1271 ret_type = LLVMStructTypeInContext(ctx->context, types,
1272 2, true);
1273
1274 res = ac_build_intrinsic(ctx, intrin, ret_type,
1275 params, 2, AC_FUNC_ATTR_READNONE);
1276
1277 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1278 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1279 return res;
1280 }
1281
1282 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1283 LLVMValueRef src0)
1284 {
1285 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1286 }
1287
1288 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1289 LLVMValueRef src0)
1290 {
1291 src0 = to_float(ctx, src0);
1292 return LLVMBuildSExt(ctx->builder,
1293 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1294 ctx->i32, "");
1295 }
1296
1297 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1298 LLVMValueRef src0)
1299 {
1300 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1301 }
1302
1303 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1304 LLVMValueRef src0)
1305 {
1306 return LLVMBuildSExt(ctx->builder,
1307 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1308 ctx->i32, "");
1309 }
1310
1311 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1312 LLVMValueRef src0)
1313 {
1314 LLVMValueRef result;
1315 LLVMValueRef cond;
1316
1317 src0 = to_float(&ctx->ac, src0);
1318 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1319
1320 /* TODO SI/CIK options here */
1321 if (ctx->options->chip_class >= VI) {
1322 LLVMValueRef args[2];
1323 /* Check if the result is a denormal - and flush to 0 if so. */
1324 args[0] = result;
1325 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1326 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1327 }
1328
1329 /* need to convert back up to f32 */
1330 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1331
1332 if (ctx->options->chip_class >= VI)
1333 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1334
1335 return result;
1336 }
1337
1338 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1339 LLVMValueRef src0, LLVMValueRef src1)
1340 {
1341 LLVMValueRef dst64, result;
1342 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1343 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1344
1345 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1346 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1347 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1348 return result;
1349 }
1350
1351 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1352 LLVMValueRef src0, LLVMValueRef src1)
1353 {
1354 LLVMValueRef dst64, result;
1355 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1356 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1357
1358 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1359 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1360 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1361 return result;
1362 }
1363
1364 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1365 bool is_signed,
1366 const LLVMValueRef srcs[3])
1367 {
1368 LLVMValueRef result;
1369 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1370
1371 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1372 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1373 return result;
1374 }
1375
1376 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1377 LLVMValueRef src0, LLVMValueRef src1,
1378 LLVMValueRef src2, LLVMValueRef src3)
1379 {
1380 LLVMValueRef bfi_args[3], result;
1381
1382 bfi_args[0] = LLVMBuildShl(ctx->builder,
1383 LLVMBuildSub(ctx->builder,
1384 LLVMBuildShl(ctx->builder,
1385 ctx->i32_1,
1386 src3, ""),
1387 ctx->i32_1, ""),
1388 src2, "");
1389 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1390 bfi_args[2] = src0;
1391
1392 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1393
1394 /* Calculate:
1395 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1396 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1397 */
1398 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1399 LLVMBuildAnd(ctx->builder, bfi_args[0],
1400 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1401
1402 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1403 return result;
1404 }
1405
1406 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1407 LLVMValueRef src0)
1408 {
1409 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1410 int i;
1411 LLVMValueRef comp[2];
1412
1413 src0 = to_float(ctx, src0);
1414 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1415 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1416 for (i = 0; i < 2; i++) {
1417 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1418 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1419 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1420 }
1421
1422 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1423 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1424
1425 return comp[0];
1426 }
1427
1428 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1429 LLVMValueRef src0)
1430 {
1431 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1432 LLVMValueRef temps[2], result, val;
1433 int i;
1434
1435 for (i = 0; i < 2; i++) {
1436 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1437 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1438 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1439 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1440 }
1441
1442 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1443 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1444 ctx->i32_0, "");
1445 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1446 ctx->i32_1, "");
1447 return result;
1448 }
1449
1450 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1451 nir_op op,
1452 LLVMValueRef src0)
1453 {
1454 unsigned mask;
1455 int idx;
1456 LLVMValueRef result;
1457 bool has_ds_bpermute = ctx->abi->chip_class >= VI;
1458
1459 if (!ctx->ddxy_lds && !has_ds_bpermute)
1460 ctx->ddxy_lds = LLVMAddGlobalInAddressSpace(ctx->ac.module,
1461 LLVMArrayType(ctx->ac.i32, 64),
1462 "ddxy_lds", LOCAL_ADDR_SPACE);
1463
1464 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1465 mask = AC_TID_MASK_LEFT;
1466 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1467 mask = AC_TID_MASK_TOP;
1468 else
1469 mask = AC_TID_MASK_TOP_LEFT;
1470
1471 /* for DDX we want to next X pixel, DDY next Y pixel. */
1472 if (op == nir_op_fddx_fine ||
1473 op == nir_op_fddx_coarse ||
1474 op == nir_op_fddx)
1475 idx = 1;
1476 else
1477 idx = 2;
1478
1479 result = ac_build_ddxy(&ctx->ac, has_ds_bpermute,
1480 mask, idx, ctx->ddxy_lds,
1481 src0);
1482 return result;
1483 }
1484
1485 /*
1486 * this takes an I,J coordinate pair,
1487 * and works out the X and Y derivatives.
1488 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1489 */
1490 static LLVMValueRef emit_ddxy_interp(
1491 struct ac_nir_context *ctx,
1492 LLVMValueRef interp_ij)
1493 {
1494 LLVMValueRef result[4], a;
1495 unsigned i;
1496
1497 for (i = 0; i < 2; i++) {
1498 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1499 LLVMConstInt(ctx->ac.i32, i, false), "");
1500 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1501 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1502 }
1503 return ac_build_gather_values(&ctx->ac, result, 4);
1504 }
1505
1506 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1507 {
1508 LLVMValueRef src[4], result = NULL;
1509 unsigned num_components = instr->dest.dest.ssa.num_components;
1510 unsigned src_components;
1511 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1512
1513 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1514 switch (instr->op) {
1515 case nir_op_vec2:
1516 case nir_op_vec3:
1517 case nir_op_vec4:
1518 src_components = 1;
1519 break;
1520 case nir_op_pack_half_2x16:
1521 src_components = 2;
1522 break;
1523 case nir_op_unpack_half_2x16:
1524 src_components = 1;
1525 break;
1526 default:
1527 src_components = num_components;
1528 break;
1529 }
1530 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1531 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1532
1533 switch (instr->op) {
1534 case nir_op_fmov:
1535 case nir_op_imov:
1536 result = src[0];
1537 break;
1538 case nir_op_fneg:
1539 src[0] = to_float(&ctx->ac, src[0]);
1540 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1541 break;
1542 case nir_op_ineg:
1543 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1544 break;
1545 case nir_op_inot:
1546 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1547 break;
1548 case nir_op_iadd:
1549 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1550 break;
1551 case nir_op_fadd:
1552 src[0] = to_float(&ctx->ac, src[0]);
1553 src[1] = to_float(&ctx->ac, src[1]);
1554 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1555 break;
1556 case nir_op_fsub:
1557 src[0] = to_float(&ctx->ac, src[0]);
1558 src[1] = to_float(&ctx->ac, src[1]);
1559 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1560 break;
1561 case nir_op_isub:
1562 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1563 break;
1564 case nir_op_imul:
1565 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1566 break;
1567 case nir_op_imod:
1568 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1569 break;
1570 case nir_op_umod:
1571 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1572 break;
1573 case nir_op_fmod:
1574 src[0] = to_float(&ctx->ac, src[0]);
1575 src[1] = to_float(&ctx->ac, src[1]);
1576 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1577 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1578 to_float_type(&ctx->ac, def_type), result);
1579 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1580 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1581 break;
1582 case nir_op_frem:
1583 src[0] = to_float(&ctx->ac, src[0]);
1584 src[1] = to_float(&ctx->ac, src[1]);
1585 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1586 break;
1587 case nir_op_irem:
1588 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1589 break;
1590 case nir_op_idiv:
1591 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1592 break;
1593 case nir_op_udiv:
1594 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1595 break;
1596 case nir_op_fmul:
1597 src[0] = to_float(&ctx->ac, src[0]);
1598 src[1] = to_float(&ctx->ac, src[1]);
1599 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1600 break;
1601 case nir_op_fdiv:
1602 src[0] = to_float(&ctx->ac, src[0]);
1603 src[1] = to_float(&ctx->ac, src[1]);
1604 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1605 break;
1606 case nir_op_frcp:
1607 src[0] = to_float(&ctx->ac, src[0]);
1608 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1609 break;
1610 case nir_op_iand:
1611 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1612 break;
1613 case nir_op_ior:
1614 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1615 break;
1616 case nir_op_ixor:
1617 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1618 break;
1619 case nir_op_ishl:
1620 result = LLVMBuildShl(ctx->ac.builder, src[0],
1621 LLVMBuildZExt(ctx->ac.builder, src[1],
1622 LLVMTypeOf(src[0]), ""),
1623 "");
1624 break;
1625 case nir_op_ishr:
1626 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1627 LLVMBuildZExt(ctx->ac.builder, src[1],
1628 LLVMTypeOf(src[0]), ""),
1629 "");
1630 break;
1631 case nir_op_ushr:
1632 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1633 LLVMBuildZExt(ctx->ac.builder, src[1],
1634 LLVMTypeOf(src[0]), ""),
1635 "");
1636 break;
1637 case nir_op_ilt:
1638 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1639 break;
1640 case nir_op_ine:
1641 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1642 break;
1643 case nir_op_ieq:
1644 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1645 break;
1646 case nir_op_ige:
1647 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1648 break;
1649 case nir_op_ult:
1650 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1651 break;
1652 case nir_op_uge:
1653 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1654 break;
1655 case nir_op_feq:
1656 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1657 break;
1658 case nir_op_fne:
1659 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1660 break;
1661 case nir_op_flt:
1662 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1663 break;
1664 case nir_op_fge:
1665 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1666 break;
1667 case nir_op_fabs:
1668 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1669 to_float_type(&ctx->ac, def_type), src[0]);
1670 break;
1671 case nir_op_iabs:
1672 result = emit_iabs(&ctx->ac, src[0]);
1673 break;
1674 case nir_op_imax:
1675 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1676 break;
1677 case nir_op_imin:
1678 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1679 break;
1680 case nir_op_umax:
1681 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1682 break;
1683 case nir_op_umin:
1684 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1685 break;
1686 case nir_op_isign:
1687 result = emit_isign(&ctx->ac, src[0]);
1688 break;
1689 case nir_op_fsign:
1690 src[0] = to_float(&ctx->ac, src[0]);
1691 result = emit_fsign(&ctx->ac, src[0]);
1692 break;
1693 case nir_op_ffloor:
1694 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1695 to_float_type(&ctx->ac, def_type), src[0]);
1696 break;
1697 case nir_op_ftrunc:
1698 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1699 to_float_type(&ctx->ac, def_type), src[0]);
1700 break;
1701 case nir_op_fceil:
1702 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1703 to_float_type(&ctx->ac, def_type), src[0]);
1704 break;
1705 case nir_op_fround_even:
1706 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1707 to_float_type(&ctx->ac, def_type),src[0]);
1708 break;
1709 case nir_op_ffract:
1710 result = emit_ffract(&ctx->ac, src[0]);
1711 break;
1712 case nir_op_fsin:
1713 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1714 to_float_type(&ctx->ac, def_type), src[0]);
1715 break;
1716 case nir_op_fcos:
1717 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1718 to_float_type(&ctx->ac, def_type), src[0]);
1719 break;
1720 case nir_op_fsqrt:
1721 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1722 to_float_type(&ctx->ac, def_type), src[0]);
1723 break;
1724 case nir_op_fexp2:
1725 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1726 to_float_type(&ctx->ac, def_type), src[0]);
1727 break;
1728 case nir_op_flog2:
1729 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1730 to_float_type(&ctx->ac, def_type), src[0]);
1731 break;
1732 case nir_op_frsq:
1733 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1734 to_float_type(&ctx->ac, def_type), src[0]);
1735 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1736 break;
1737 case nir_op_fpow:
1738 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1739 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1740 break;
1741 case nir_op_fmax:
1742 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1743 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1744 if (instr->dest.dest.ssa.bit_size == 32)
1745 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1746 to_float_type(&ctx->ac, def_type),
1747 result);
1748 break;
1749 case nir_op_fmin:
1750 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1751 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1752 if (instr->dest.dest.ssa.bit_size == 32)
1753 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1754 to_float_type(&ctx->ac, def_type),
1755 result);
1756 break;
1757 case nir_op_ffma:
1758 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1759 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1760 break;
1761 case nir_op_ibitfield_extract:
1762 result = emit_bitfield_extract(&ctx->ac, true, src);
1763 break;
1764 case nir_op_ubitfield_extract:
1765 result = emit_bitfield_extract(&ctx->ac, false, src);
1766 break;
1767 case nir_op_bitfield_insert:
1768 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1769 break;
1770 case nir_op_bitfield_reverse:
1771 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1772 break;
1773 case nir_op_bit_count:
1774 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1775 break;
1776 case nir_op_vec2:
1777 case nir_op_vec3:
1778 case nir_op_vec4:
1779 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1780 src[i] = to_integer(&ctx->ac, src[i]);
1781 result = ac_build_gather_values(&ctx->ac, src, num_components);
1782 break;
1783 case nir_op_f2i32:
1784 case nir_op_f2i64:
1785 src[0] = to_float(&ctx->ac, src[0]);
1786 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1787 break;
1788 case nir_op_f2u32:
1789 case nir_op_f2u64:
1790 src[0] = to_float(&ctx->ac, src[0]);
1791 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1792 break;
1793 case nir_op_i2f32:
1794 case nir_op_i2f64:
1795 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1796 break;
1797 case nir_op_u2f32:
1798 case nir_op_u2f64:
1799 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1800 break;
1801 case nir_op_f2f64:
1802 result = LLVMBuildFPExt(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1803 break;
1804 case nir_op_f2f32:
1805 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1806 break;
1807 case nir_op_u2u32:
1808 case nir_op_u2u64:
1809 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1810 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1811 else
1812 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1813 break;
1814 case nir_op_i2i32:
1815 case nir_op_i2i64:
1816 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1817 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1818 else
1819 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1820 break;
1821 case nir_op_bcsel:
1822 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1823 break;
1824 case nir_op_find_lsb:
1825 result = emit_find_lsb(&ctx->ac, src[0]);
1826 break;
1827 case nir_op_ufind_msb:
1828 result = emit_ufind_msb(&ctx->ac, src[0]);
1829 break;
1830 case nir_op_ifind_msb:
1831 result = emit_ifind_msb(&ctx->ac, src[0]);
1832 break;
1833 case nir_op_uadd_carry:
1834 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1835 break;
1836 case nir_op_usub_borrow:
1837 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1838 break;
1839 case nir_op_b2f:
1840 result = emit_b2f(&ctx->ac, src[0]);
1841 break;
1842 case nir_op_f2b:
1843 result = emit_f2b(&ctx->ac, src[0]);
1844 break;
1845 case nir_op_b2i:
1846 result = emit_b2i(&ctx->ac, src[0]);
1847 break;
1848 case nir_op_i2b:
1849 result = emit_i2b(&ctx->ac, src[0]);
1850 break;
1851 case nir_op_fquantize2f16:
1852 result = emit_f2f16(ctx->nctx, src[0]);
1853 break;
1854 case nir_op_umul_high:
1855 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1856 break;
1857 case nir_op_imul_high:
1858 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1859 break;
1860 case nir_op_pack_half_2x16:
1861 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1862 break;
1863 case nir_op_unpack_half_2x16:
1864 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1865 break;
1866 case nir_op_fddx:
1867 case nir_op_fddy:
1868 case nir_op_fddx_fine:
1869 case nir_op_fddy_fine:
1870 case nir_op_fddx_coarse:
1871 case nir_op_fddy_coarse:
1872 result = emit_ddxy(ctx, instr->op, src[0]);
1873 break;
1874
1875 case nir_op_unpack_64_2x32_split_x: {
1876 assert(instr->src[0].src.ssa->num_components == 1);
1877 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1878 LLVMVectorType(ctx->ac.i32, 2),
1879 "");
1880 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1881 ctx->ac.i32_0, "");
1882 break;
1883 }
1884
1885 case nir_op_unpack_64_2x32_split_y: {
1886 assert(instr->src[0].src.ssa->num_components == 1);
1887 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1888 LLVMVectorType(ctx->ac.i32, 2),
1889 "");
1890 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1891 ctx->ac.i32_0, "");
1892 break;
1893 }
1894
1895 case nir_op_pack_64_2x32_split: {
1896 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1897 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1898 src[0], ctx->ac.i32_0, "");
1899 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1900 src[1], ctx->ac.i32_1, "");
1901 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1902 break;
1903 }
1904
1905 default:
1906 fprintf(stderr, "Unknown NIR alu instr: ");
1907 nir_print_instr(&instr->instr, stderr);
1908 fprintf(stderr, "\n");
1909 abort();
1910 }
1911
1912 if (result) {
1913 assert(instr->dest.dest.is_ssa);
1914 result = to_integer(&ctx->ac, result);
1915 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1916 result);
1917 }
1918 }
1919
1920 static void visit_load_const(struct ac_nir_context *ctx,
1921 const nir_load_const_instr *instr)
1922 {
1923 LLVMValueRef values[4], value = NULL;
1924 LLVMTypeRef element_type =
1925 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1926
1927 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1928 switch (instr->def.bit_size) {
1929 case 32:
1930 values[i] = LLVMConstInt(element_type,
1931 instr->value.u32[i], false);
1932 break;
1933 case 64:
1934 values[i] = LLVMConstInt(element_type,
1935 instr->value.u64[i], false);
1936 break;
1937 default:
1938 fprintf(stderr,
1939 "unsupported nir load_const bit_size: %d\n",
1940 instr->def.bit_size);
1941 abort();
1942 }
1943 }
1944 if (instr->def.num_components > 1) {
1945 value = LLVMConstVector(values, instr->def.num_components);
1946 } else
1947 value = values[0];
1948
1949 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1950 }
1951
1952 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1953 LLVMTypeRef type)
1954 {
1955 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1956 return LLVMBuildBitCast(ctx->builder, ptr,
1957 LLVMPointerType(type, addr_space), "");
1958 }
1959
1960 static LLVMValueRef
1961 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1962 {
1963 LLVMValueRef size =
1964 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1965 LLVMConstInt(ctx->ac.i32, 2, false), "");
1966
1967 /* VI only */
1968 if (ctx->abi->chip_class >= VI && in_elements) {
1969 /* On VI, the descriptor contains the size in bytes,
1970 * but TXQ must return the size in elements.
1971 * The stride is always non-zero for resources using TXQ.
1972 */
1973 LLVMValueRef stride =
1974 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1975 LLVMConstInt(ctx->ac.i32, 1, false), "");
1976 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1977 LLVMConstInt(ctx->ac.i32, 16, false), "");
1978 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1979 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1980
1981 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1982 }
1983 return size;
1984 }
1985
1986 /**
1987 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1988 * intrinsic names).
1989 */
1990 static void build_int_type_name(
1991 LLVMTypeRef type,
1992 char *buf, unsigned bufsize)
1993 {
1994 assert(bufsize >= 6);
1995
1996 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1997 snprintf(buf, bufsize, "v%ui32",
1998 LLVMGetVectorSize(type));
1999 else
2000 strcpy(buf, "i32");
2001 }
2002
2003 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2004 struct ac_image_args *args,
2005 const nir_tex_instr *instr)
2006 {
2007 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2008 LLVMValueRef coord = args->addr;
2009 LLVMValueRef half_texel[2];
2010 LLVMValueRef compare_cube_wa;
2011 LLVMValueRef result;
2012 int c;
2013 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2014
2015 //TODO Rect
2016 {
2017 struct ac_image_args txq_args = { 0 };
2018
2019 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2020 txq_args.opcode = ac_image_get_resinfo;
2021 txq_args.dmask = 0xf;
2022 txq_args.addr = ctx->i32_0;
2023 txq_args.resource = args->resource;
2024 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2025
2026 for (c = 0; c < 2; c++) {
2027 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2028 LLVMConstInt(ctx->i32, c, false), "");
2029 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2030 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2031 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2032 LLVMConstReal(ctx->f32, -0.5), "");
2033 }
2034 }
2035
2036 LLVMValueRef orig_coords = args->addr;
2037
2038 for (c = 0; c < 2; c++) {
2039 LLVMValueRef tmp;
2040 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2041 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2042 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2043 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2044 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2045 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2046 }
2047
2048
2049 /*
2050 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2051 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2052 * workaround by sampling using a scaled type and converting.
2053 * This is taken from amdgpu-pro shaders.
2054 */
2055 /* NOTE this produces some ugly code compared to amdgpu-pro,
2056 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2057 * and then reads them back. -pro generates two selects,
2058 * one s_cmp for the descriptor rewriting
2059 * one v_cmp for the coordinate and result changes.
2060 */
2061 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2062 LLVMValueRef tmp, tmp2;
2063
2064 /* workaround 8/8/8/8 uint/sint cube gather bug */
2065 /* first detect it then change to a scaled read and f2i */
2066 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2067 tmp2 = tmp;
2068
2069 /* extract the DATA_FORMAT */
2070 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2071 LLVMConstInt(ctx->i32, 6, false), false);
2072
2073 /* is the DATA_FORMAT == 8_8_8_8 */
2074 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2075
2076 if (stype == GLSL_TYPE_UINT)
2077 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2078 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2079 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2080 else
2081 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2082 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2083 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2084
2085 /* replace the NUM FORMAT in the descriptor */
2086 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2087 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2088
2089 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2090
2091 /* don't modify the coordinates for this case */
2092 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2093 }
2094 args->addr = coord;
2095 result = ac_build_image_opcode(ctx, args);
2096
2097 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2098 LLVMValueRef tmp, tmp2;
2099
2100 /* if the cube workaround is in place, f2i the result. */
2101 for (c = 0; c < 4; c++) {
2102 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2103 if (stype == GLSL_TYPE_UINT)
2104 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2105 else
2106 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2107 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2108 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2109 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2110 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2111 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2112 }
2113 }
2114 return result;
2115 }
2116
2117 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2118 const nir_tex_instr *instr,
2119 bool lod_is_zero,
2120 struct ac_image_args *args)
2121 {
2122 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2123 return ac_build_buffer_load_format(&ctx->ac,
2124 args->resource,
2125 args->addr,
2126 LLVMConstInt(ctx->ac.i32, 0, false),
2127 true);
2128 }
2129
2130 args->opcode = ac_image_sample;
2131 args->compare = instr->is_shadow;
2132
2133 switch (instr->op) {
2134 case nir_texop_txf:
2135 case nir_texop_txf_ms:
2136 case nir_texop_samples_identical:
2137 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2138 args->compare = false;
2139 args->offset = false;
2140 break;
2141 case nir_texop_txb:
2142 args->bias = true;
2143 break;
2144 case nir_texop_txl:
2145 if (lod_is_zero)
2146 args->level_zero = true;
2147 else
2148 args->lod = true;
2149 break;
2150 case nir_texop_txs:
2151 case nir_texop_query_levels:
2152 args->opcode = ac_image_get_resinfo;
2153 break;
2154 case nir_texop_tex:
2155 if (ctx->stage != MESA_SHADER_FRAGMENT)
2156 args->level_zero = true;
2157 break;
2158 case nir_texop_txd:
2159 args->deriv = true;
2160 break;
2161 case nir_texop_tg4:
2162 args->opcode = ac_image_gather4;
2163 args->level_zero = true;
2164 break;
2165 case nir_texop_lod:
2166 args->opcode = ac_image_get_lod;
2167 args->compare = false;
2168 args->offset = false;
2169 break;
2170 default:
2171 break;
2172 }
2173
2174 if (instr->op == nir_texop_tg4) {
2175 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2176 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2177 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2178 }
2179 }
2180 return ac_build_image_opcode(&ctx->ac, args);
2181 }
2182
2183 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2184 nir_intrinsic_instr *instr)
2185 {
2186 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2187 unsigned desc_set = nir_intrinsic_desc_set(instr);
2188 unsigned binding = nir_intrinsic_binding(instr);
2189 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2190 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2191 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2192 unsigned base_offset = layout->binding[binding].offset;
2193 LLVMValueRef offset, stride;
2194
2195 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2196 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2197 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2198 layout->binding[binding].dynamic_offset_offset;
2199 desc_ptr = ctx->push_constants;
2200 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2201 stride = LLVMConstInt(ctx->i32, 16, false);
2202 } else
2203 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2204
2205 offset = LLVMConstInt(ctx->i32, base_offset, false);
2206 index = LLVMBuildMul(ctx->builder, index, stride, "");
2207 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2208
2209 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2210 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2211 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2212
2213 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2214 }
2215
2216 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2217 nir_intrinsic_instr *instr)
2218 {
2219 LLVMValueRef ptr, addr;
2220
2221 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2222 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2223
2224 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2225 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2226
2227 return LLVMBuildLoad(ctx->builder, ptr, "");
2228 }
2229
2230 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2231 const nir_intrinsic_instr *instr)
2232 {
2233 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2234
2235 return get_buffer_size(ctx, desc, false);
2236 }
2237 static void visit_store_ssbo(struct ac_nir_context *ctx,
2238 nir_intrinsic_instr *instr)
2239 {
2240 const char *store_name;
2241 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2242 LLVMTypeRef data_type = ctx->ac.f32;
2243 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2244 int components_32bit = elem_size_mult * instr->num_components;
2245 unsigned writemask = nir_intrinsic_write_mask(instr);
2246 LLVMValueRef base_data, base_offset;
2247 LLVMValueRef params[6];
2248 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2249
2250 params[1] = ctx->abi->load_ssbo(ctx->abi,
2251 get_src(ctx, instr->src[1]), true);
2252 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2253 params[4] = i1false; /* glc */
2254 params[5] = i1false; /* slc */
2255
2256 if (components_32bit > 1)
2257 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2258
2259 base_data = to_float(&ctx->ac, src_data);
2260 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2261 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2262 data_type, "");
2263 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2264 while (writemask) {
2265 int start, count;
2266 LLVMValueRef data;
2267 LLVMValueRef offset;
2268 LLVMValueRef tmp;
2269 u_bit_scan_consecutive_range(&writemask, &start, &count);
2270
2271 /* Due to an LLVM limitation, split 3-element writes
2272 * into a 2-element and a 1-element write. */
2273 if (count == 3) {
2274 writemask |= 1 << (start + 2);
2275 count = 2;
2276 }
2277
2278 start *= elem_size_mult;
2279 count *= elem_size_mult;
2280
2281 if (count > 4) {
2282 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2283 count = 4;
2284 }
2285
2286 if (count == 4) {
2287 store_name = "llvm.amdgcn.buffer.store.v4f32";
2288 data = base_data;
2289 } else if (count == 2) {
2290 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2291
2292 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2293 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2294 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2295 ctx->ac.i32_0, "");
2296
2297 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2298 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2299 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2300 ctx->ac.i32_1, "");
2301 store_name = "llvm.amdgcn.buffer.store.v2f32";
2302
2303 } else {
2304 assert(count == 1);
2305 if (get_llvm_num_components(base_data) > 1)
2306 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2307 LLVMConstInt(ctx->ac.i32, start, false), "");
2308 else
2309 data = base_data;
2310 store_name = "llvm.amdgcn.buffer.store.f32";
2311 }
2312
2313 offset = base_offset;
2314 if (start != 0) {
2315 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2316 }
2317 params[0] = data;
2318 params[3] = offset;
2319 ac_build_intrinsic(&ctx->ac, store_name,
2320 ctx->ac.voidt, params, 6, 0);
2321 }
2322 }
2323
2324 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2325 const nir_intrinsic_instr *instr)
2326 {
2327 const char *name;
2328 LLVMValueRef params[6];
2329 int arg_count = 0;
2330
2331 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2332 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2333 }
2334 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2335 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2336 get_src(ctx, instr->src[0]),
2337 true);
2338 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2339 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2340 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2341
2342 switch (instr->intrinsic) {
2343 case nir_intrinsic_ssbo_atomic_add:
2344 name = "llvm.amdgcn.buffer.atomic.add";
2345 break;
2346 case nir_intrinsic_ssbo_atomic_imin:
2347 name = "llvm.amdgcn.buffer.atomic.smin";
2348 break;
2349 case nir_intrinsic_ssbo_atomic_umin:
2350 name = "llvm.amdgcn.buffer.atomic.umin";
2351 break;
2352 case nir_intrinsic_ssbo_atomic_imax:
2353 name = "llvm.amdgcn.buffer.atomic.smax";
2354 break;
2355 case nir_intrinsic_ssbo_atomic_umax:
2356 name = "llvm.amdgcn.buffer.atomic.umax";
2357 break;
2358 case nir_intrinsic_ssbo_atomic_and:
2359 name = "llvm.amdgcn.buffer.atomic.and";
2360 break;
2361 case nir_intrinsic_ssbo_atomic_or:
2362 name = "llvm.amdgcn.buffer.atomic.or";
2363 break;
2364 case nir_intrinsic_ssbo_atomic_xor:
2365 name = "llvm.amdgcn.buffer.atomic.xor";
2366 break;
2367 case nir_intrinsic_ssbo_atomic_exchange:
2368 name = "llvm.amdgcn.buffer.atomic.swap";
2369 break;
2370 case nir_intrinsic_ssbo_atomic_comp_swap:
2371 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2372 break;
2373 default:
2374 abort();
2375 }
2376
2377 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2378 }
2379
2380 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2381 const nir_intrinsic_instr *instr)
2382 {
2383 LLVMValueRef results[2];
2384 int load_components;
2385 int num_components = instr->num_components;
2386 if (instr->dest.ssa.bit_size == 64)
2387 num_components *= 2;
2388
2389 for (int i = 0; i < num_components; i += load_components) {
2390 load_components = MIN2(num_components - i, 4);
2391 const char *load_name;
2392 LLVMTypeRef data_type = ctx->ac.f32;
2393 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2394 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2395
2396 if (load_components == 3)
2397 data_type = LLVMVectorType(ctx->ac.f32, 4);
2398 else if (load_components > 1)
2399 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2400
2401 if (load_components >= 3)
2402 load_name = "llvm.amdgcn.buffer.load.v4f32";
2403 else if (load_components == 2)
2404 load_name = "llvm.amdgcn.buffer.load.v2f32";
2405 else if (load_components == 1)
2406 load_name = "llvm.amdgcn.buffer.load.f32";
2407 else
2408 unreachable("unhandled number of components");
2409
2410 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2411 LLVMValueRef params[] = {
2412 ctx->abi->load_ssbo(ctx->abi,
2413 get_src(ctx, instr->src[0]),
2414 false),
2415 LLVMConstInt(ctx->ac.i32, 0, false),
2416 offset,
2417 i1false,
2418 i1false,
2419 };
2420
2421 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2422
2423 }
2424
2425 LLVMValueRef ret = results[0];
2426 if (num_components > 4 || num_components == 3) {
2427 LLVMValueRef masks[] = {
2428 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2429 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2430 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2431 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2432 };
2433
2434 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2435 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2436 results[num_components > 4 ? 1 : 0], swizzle, "");
2437 }
2438
2439 return LLVMBuildBitCast(ctx->ac.builder, ret,
2440 get_def_type(ctx, &instr->dest.ssa), "");
2441 }
2442
2443 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2444 const nir_intrinsic_instr *instr)
2445 {
2446 LLVMValueRef results[8], ret;
2447 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2448 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2449 int num_components = instr->num_components;
2450
2451 if (ctx->abi->load_ubo)
2452 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2453
2454 if (instr->dest.ssa.bit_size == 64)
2455 num_components *= 2;
2456
2457 for (unsigned i = 0; i < num_components; ++i) {
2458 LLVMValueRef params[] = {
2459 rsrc,
2460 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2461 offset, "")
2462 };
2463 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2464 params, 2,
2465 AC_FUNC_ATTR_READNONE |
2466 AC_FUNC_ATTR_LEGACY);
2467 }
2468
2469
2470 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2471 return LLVMBuildBitCast(ctx->ac.builder, ret,
2472 get_def_type(ctx, &instr->dest.ssa), "");
2473 }
2474
2475 static void
2476 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2477 bool vs_in, unsigned *vertex_index_out,
2478 LLVMValueRef *vertex_index_ref,
2479 unsigned *const_out, LLVMValueRef *indir_out)
2480 {
2481 unsigned const_offset = 0;
2482 nir_deref *tail = &deref->deref;
2483 LLVMValueRef offset = NULL;
2484
2485 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2486 tail = tail->child;
2487 nir_deref_array *deref_array = nir_deref_as_array(tail);
2488 if (vertex_index_out)
2489 *vertex_index_out = deref_array->base_offset;
2490
2491 if (vertex_index_ref) {
2492 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2493 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2494 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2495 }
2496 *vertex_index_ref = vtx;
2497 }
2498 }
2499
2500 if (deref->var->data.compact) {
2501 assert(tail->child->deref_type == nir_deref_type_array);
2502 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2503 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2504 /* We always lower indirect dereferences for "compact" array vars. */
2505 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2506
2507 const_offset = deref_array->base_offset;
2508 goto out;
2509 }
2510
2511 while (tail->child != NULL) {
2512 const struct glsl_type *parent_type = tail->type;
2513 tail = tail->child;
2514
2515 if (tail->deref_type == nir_deref_type_array) {
2516 nir_deref_array *deref_array = nir_deref_as_array(tail);
2517 LLVMValueRef index, stride, local_offset;
2518 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2519
2520 const_offset += size * deref_array->base_offset;
2521 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2522 continue;
2523
2524 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2525 index = get_src(ctx, deref_array->indirect);
2526 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2527 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2528
2529 if (offset)
2530 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2531 else
2532 offset = local_offset;
2533 } else if (tail->deref_type == nir_deref_type_struct) {
2534 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2535
2536 for (unsigned i = 0; i < deref_struct->index; i++) {
2537 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2538 const_offset += glsl_count_attribute_slots(ft, vs_in);
2539 }
2540 } else
2541 unreachable("unsupported deref type");
2542
2543 }
2544 out:
2545 if (const_offset && offset)
2546 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2547 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2548 "");
2549
2550 *const_out = const_offset;
2551 *indir_out = offset;
2552 }
2553
2554 static LLVMValueRef
2555 lds_load(struct nir_to_llvm_context *ctx,
2556 LLVMValueRef dw_addr)
2557 {
2558 LLVMValueRef value;
2559 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2560 return value;
2561 }
2562
2563 static void
2564 lds_store(struct nir_to_llvm_context *ctx,
2565 LLVMValueRef dw_addr, LLVMValueRef value)
2566 {
2567 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2568 ac_build_indexed_store(&ctx->ac, ctx->lds,
2569 dw_addr, value);
2570 }
2571
2572 /* The offchip buffer layout for TCS->TES is
2573 *
2574 * - attribute 0 of patch 0 vertex 0
2575 * - attribute 0 of patch 0 vertex 1
2576 * - attribute 0 of patch 0 vertex 2
2577 * ...
2578 * - attribute 0 of patch 1 vertex 0
2579 * - attribute 0 of patch 1 vertex 1
2580 * ...
2581 * - attribute 1 of patch 0 vertex 0
2582 * - attribute 1 of patch 0 vertex 1
2583 * ...
2584 * - per patch attribute 0 of patch 0
2585 * - per patch attribute 0 of patch 1
2586 * ...
2587 *
2588 * Note that every attribute has 4 components.
2589 */
2590 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2591 LLVMValueRef vertex_index,
2592 LLVMValueRef param_index)
2593 {
2594 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2595 LLVMValueRef param_stride, constant16;
2596 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2597
2598 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2599 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2600 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2601 num_patches, "");
2602
2603 constant16 = LLVMConstInt(ctx->i32, 16, false);
2604 if (vertex_index) {
2605 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2606 vertices_per_patch, "");
2607
2608 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2609 vertex_index, "");
2610
2611 param_stride = total_vertices;
2612 } else {
2613 base_addr = rel_patch_id;
2614 param_stride = num_patches;
2615 }
2616
2617 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2618 LLVMBuildMul(ctx->builder, param_index,
2619 param_stride, ""), "");
2620
2621 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2622
2623 if (!vertex_index) {
2624 LLVMValueRef patch_data_offset =
2625 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2626
2627 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2628 patch_data_offset, "");
2629 }
2630 return base_addr;
2631 }
2632
2633 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2634 unsigned param,
2635 unsigned const_index,
2636 bool is_compact,
2637 LLVMValueRef vertex_index,
2638 LLVMValueRef indir_index)
2639 {
2640 LLVMValueRef param_index;
2641
2642 if (indir_index)
2643 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2644 indir_index, "");
2645 else {
2646 if (const_index && !is_compact)
2647 param += const_index;
2648 param_index = LLVMConstInt(ctx->i32, param, false);
2649 }
2650 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2651 }
2652
2653 static void
2654 mark_tess_output(struct nir_to_llvm_context *ctx,
2655 bool is_patch, uint32_t param)
2656
2657 {
2658 if (is_patch) {
2659 ctx->tess_patch_outputs_written |= (1ull << param);
2660 } else
2661 ctx->tess_outputs_written |= (1ull << param);
2662 }
2663
2664 static LLVMValueRef
2665 get_dw_address(struct nir_to_llvm_context *ctx,
2666 LLVMValueRef dw_addr,
2667 unsigned param,
2668 unsigned const_index,
2669 bool compact_const_index,
2670 LLVMValueRef vertex_index,
2671 LLVMValueRef stride,
2672 LLVMValueRef indir_index)
2673
2674 {
2675
2676 if (vertex_index) {
2677 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2678 LLVMBuildMul(ctx->builder,
2679 vertex_index,
2680 stride, ""), "");
2681 }
2682
2683 if (indir_index)
2684 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2685 LLVMBuildMul(ctx->builder, indir_index,
2686 LLVMConstInt(ctx->i32, 4, false), ""), "");
2687 else if (const_index && !compact_const_index)
2688 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2689 LLVMConstInt(ctx->i32, const_index, false), "");
2690
2691 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2692 LLVMConstInt(ctx->i32, param * 4, false), "");
2693
2694 if (const_index && compact_const_index)
2695 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2696 LLVMConstInt(ctx->i32, const_index, false), "");
2697 return dw_addr;
2698 }
2699
2700 static LLVMValueRef
2701 load_tcs_input(struct nir_to_llvm_context *ctx,
2702 nir_intrinsic_instr *instr)
2703 {
2704 LLVMValueRef dw_addr, stride;
2705 unsigned const_index;
2706 LLVMValueRef vertex_index;
2707 LLVMValueRef indir_index;
2708 unsigned param;
2709 LLVMValueRef value[4], result;
2710 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2711 const bool is_compact = instr->variables[0]->var->data.compact;
2712 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2713 get_deref_offset(ctx->nir, instr->variables[0],
2714 false, NULL, per_vertex ? &vertex_index : NULL,
2715 &const_index, &indir_index);
2716
2717 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2718 dw_addr = get_tcs_in_current_patch_offset(ctx);
2719 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2720 indir_index);
2721
2722 for (unsigned i = 0; i < instr->num_components; i++) {
2723 value[i] = lds_load(ctx, dw_addr);
2724 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2725 ctx->i32one, "");
2726 }
2727 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2728 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2729 return result;
2730 }
2731
2732 static LLVMValueRef
2733 load_tcs_output(struct nir_to_llvm_context *ctx,
2734 nir_intrinsic_instr *instr)
2735 {
2736 LLVMValueRef dw_addr, stride;
2737 LLVMValueRef value[4], result;
2738 LLVMValueRef vertex_index = NULL;
2739 LLVMValueRef indir_index = NULL;
2740 unsigned const_index = 0;
2741 unsigned param;
2742 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2743 const bool is_compact = instr->variables[0]->var->data.compact;
2744 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2745 get_deref_offset(ctx->nir, instr->variables[0],
2746 false, NULL, per_vertex ? &vertex_index : NULL,
2747 &const_index, &indir_index);
2748
2749 if (!instr->variables[0]->var->data.patch) {
2750 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2751 dw_addr = get_tcs_out_current_patch_offset(ctx);
2752 } else {
2753 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2754 }
2755
2756 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2757 indir_index);
2758
2759 for (unsigned i = 0; i < instr->num_components; i++) {
2760 value[i] = lds_load(ctx, dw_addr);
2761 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2762 ctx->i32one, "");
2763 }
2764 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2765 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2766 return result;
2767 }
2768
2769 static void
2770 store_tcs_output(struct nir_to_llvm_context *ctx,
2771 nir_intrinsic_instr *instr,
2772 LLVMValueRef src,
2773 unsigned writemask)
2774 {
2775 LLVMValueRef stride, dw_addr;
2776 LLVMValueRef buf_addr = NULL;
2777 LLVMValueRef vertex_index = NULL;
2778 LLVMValueRef indir_index = NULL;
2779 unsigned const_index = 0;
2780 unsigned param;
2781 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2782 const bool is_compact = instr->variables[0]->var->data.compact;
2783
2784 get_deref_offset(ctx->nir, instr->variables[0],
2785 false, NULL, per_vertex ? &vertex_index : NULL,
2786 &const_index, &indir_index);
2787
2788 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2789 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2790 is_compact && const_index > 3) {
2791 const_index -= 3;
2792 param++;
2793 }
2794
2795 if (!instr->variables[0]->var->data.patch) {
2796 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2797 dw_addr = get_tcs_out_current_patch_offset(ctx);
2798 } else {
2799 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2800 }
2801
2802 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2803
2804 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2805 indir_index);
2806 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2807 vertex_index, indir_index);
2808
2809 unsigned base = is_compact ? const_index : 0;
2810 for (unsigned chan = 0; chan < 8; chan++) {
2811 bool is_tess_factor = false;
2812 if (!(writemask & (1 << chan)))
2813 continue;
2814 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2815
2816 lds_store(ctx, dw_addr, value);
2817
2818 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2819 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2820 is_tess_factor = true;
2821
2822 if (!is_tess_factor && writemask != 0xF)
2823 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2824 buf_addr, ctx->oc_lds,
2825 4 * (base + chan), 1, 0, true, false);
2826
2827 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2828 ctx->i32one, "");
2829 }
2830
2831 if (writemask == 0xF) {
2832 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2833 buf_addr, ctx->oc_lds,
2834 (base * 4), 1, 0, true, false);
2835 }
2836 }
2837
2838 static LLVMValueRef
2839 load_tes_input(struct nir_to_llvm_context *ctx,
2840 const nir_intrinsic_instr *instr)
2841 {
2842 LLVMValueRef buf_addr;
2843 LLVMValueRef result;
2844 LLVMValueRef vertex_index = NULL;
2845 LLVMValueRef indir_index = NULL;
2846 unsigned const_index = 0;
2847 unsigned param;
2848 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2849 const bool is_compact = instr->variables[0]->var->data.compact;
2850
2851 get_deref_offset(ctx->nir, instr->variables[0],
2852 false, NULL, per_vertex ? &vertex_index : NULL,
2853 &const_index, &indir_index);
2854 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2855 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2856 is_compact && const_index > 3) {
2857 const_index -= 3;
2858 param++;
2859 }
2860 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2861 is_compact, vertex_index, indir_index);
2862
2863 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2864 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2865 result = trim_vector(&ctx->ac, result, instr->num_components);
2866 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2867 return result;
2868 }
2869
2870 static LLVMValueRef
2871 load_gs_input(struct nir_to_llvm_context *ctx,
2872 nir_intrinsic_instr *instr)
2873 {
2874 LLVMValueRef indir_index, vtx_offset;
2875 unsigned const_index;
2876 LLVMValueRef args[9];
2877 unsigned param, vtx_offset_param;
2878 LLVMValueRef value[4], result;
2879 unsigned vertex_index;
2880 get_deref_offset(ctx->nir, instr->variables[0],
2881 false, &vertex_index, NULL,
2882 &const_index, &indir_index);
2883 vtx_offset_param = vertex_index;
2884 assert(vtx_offset_param < 6);
2885 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2886 LLVMConstInt(ctx->i32, 4, false), "");
2887
2888 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2889 for (unsigned i = 0; i < instr->num_components; i++) {
2890
2891 args[0] = ctx->esgs_ring;
2892 args[1] = vtx_offset;
2893 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2894 args[3] = ctx->i32zero;
2895 args[4] = ctx->i32one; /* OFFEN */
2896 args[5] = ctx->i32zero; /* IDXEN */
2897 args[6] = ctx->i32one; /* GLC */
2898 args[7] = ctx->i32zero; /* SLC */
2899 args[8] = ctx->i32zero; /* TFE */
2900
2901 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2902 ctx->i32, args, 9,
2903 AC_FUNC_ATTR_READONLY |
2904 AC_FUNC_ATTR_LEGACY);
2905 }
2906 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2907
2908 return result;
2909 }
2910
2911 static LLVMValueRef
2912 build_gep_for_deref(struct ac_nir_context *ctx,
2913 nir_deref_var *deref)
2914 {
2915 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2916 assert(entry->data);
2917 LLVMValueRef val = entry->data;
2918 nir_deref *tail = deref->deref.child;
2919 while (tail != NULL) {
2920 LLVMValueRef offset;
2921 switch (tail->deref_type) {
2922 case nir_deref_type_array: {
2923 nir_deref_array *array = nir_deref_as_array(tail);
2924 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2925 if (array->deref_array_type ==
2926 nir_deref_array_type_indirect) {
2927 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2928 get_src(ctx,
2929 array->indirect),
2930 "");
2931 }
2932 break;
2933 }
2934 case nir_deref_type_struct: {
2935 nir_deref_struct *deref_struct =
2936 nir_deref_as_struct(tail);
2937 offset = LLVMConstInt(ctx->ac.i32,
2938 deref_struct->index, 0);
2939 break;
2940 }
2941 default:
2942 unreachable("bad deref type");
2943 }
2944 val = ac_build_gep0(&ctx->ac, val, offset);
2945 tail = tail->child;
2946 }
2947 return val;
2948 }
2949
2950 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2951 nir_intrinsic_instr *instr)
2952 {
2953 LLVMValueRef values[8];
2954 int idx = instr->variables[0]->var->data.driver_location;
2955 int ve = instr->dest.ssa.num_components;
2956 LLVMValueRef indir_index;
2957 LLVMValueRef ret;
2958 unsigned const_index;
2959 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2960 instr->variables[0]->var->data.mode == nir_var_shader_in;
2961 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2962 &const_index, &indir_index);
2963
2964 if (instr->dest.ssa.bit_size == 64)
2965 ve *= 2;
2966
2967 switch (instr->variables[0]->var->data.mode) {
2968 case nir_var_shader_in:
2969 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2970 return load_tcs_input(ctx->nctx, instr);
2971 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2972 return load_tes_input(ctx->nctx, instr);
2973 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2974 return load_gs_input(ctx->nctx, instr);
2975 }
2976 for (unsigned chan = 0; chan < ve; chan++) {
2977 if (indir_index) {
2978 unsigned count = glsl_count_attribute_slots(
2979 instr->variables[0]->var->type,
2980 ctx->stage == MESA_SHADER_VERTEX);
2981 count -= chan / 4;
2982 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2983 &ctx->ac, ctx->abi->inputs + idx + chan, count,
2984 4, false, true);
2985
2986 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2987 tmp_vec,
2988 indir_index, "");
2989 } else
2990 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
2991 }
2992 break;
2993 case nir_var_local:
2994 for (unsigned chan = 0; chan < ve; chan++) {
2995 if (indir_index) {
2996 unsigned count = glsl_count_attribute_slots(
2997 instr->variables[0]->var->type, false);
2998 count -= chan / 4;
2999 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3000 &ctx->ac, ctx->locals + idx + chan, count,
3001 4, true, true);
3002
3003 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3004 tmp_vec,
3005 indir_index, "");
3006 } else {
3007 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3008 }
3009 }
3010 break;
3011 case nir_var_shared: {
3012 LLVMValueRef address = build_gep_for_deref(ctx,
3013 instr->variables[0]);
3014 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3015 return LLVMBuildBitCast(ctx->ac.builder, val,
3016 get_def_type(ctx, &instr->dest.ssa),
3017 "");
3018 }
3019 case nir_var_shader_out:
3020 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3021 return load_tcs_output(ctx->nctx, instr);
3022 for (unsigned chan = 0; chan < ve; chan++) {
3023 if (indir_index) {
3024 unsigned count = glsl_count_attribute_slots(
3025 instr->variables[0]->var->type, false);
3026 count -= chan / 4;
3027 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3028 &ctx->ac, ctx->outputs + idx + chan, count,
3029 4, true, true);
3030
3031 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3032 tmp_vec,
3033 indir_index, "");
3034 } else {
3035 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3036 ctx->outputs[idx + chan + const_index * 4],
3037 "");
3038 }
3039 }
3040 break;
3041 default:
3042 unreachable("unhandle variable mode");
3043 }
3044 ret = ac_build_gather_values(&ctx->ac, values, ve);
3045 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3046 }
3047
3048 static void
3049 visit_store_var(struct ac_nir_context *ctx,
3050 nir_intrinsic_instr *instr)
3051 {
3052 LLVMValueRef temp_ptr, value;
3053 int idx = instr->variables[0]->var->data.driver_location;
3054 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3055 int writemask = instr->const_index[0];
3056 LLVMValueRef indir_index;
3057 unsigned const_index;
3058 get_deref_offset(ctx, instr->variables[0], false,
3059 NULL, NULL, &const_index, &indir_index);
3060
3061 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3062 int old_writemask = writemask;
3063
3064 src = LLVMBuildBitCast(ctx->ac.builder, src,
3065 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3066 "");
3067
3068 writemask = 0;
3069 for (unsigned chan = 0; chan < 4; chan++) {
3070 if (old_writemask & (1 << chan))
3071 writemask |= 3u << (2 * chan);
3072 }
3073 }
3074
3075 switch (instr->variables[0]->var->data.mode) {
3076 case nir_var_shader_out:
3077
3078 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3079 store_tcs_output(ctx->nctx, instr, src, writemask);
3080 return;
3081 }
3082
3083 for (unsigned chan = 0; chan < 8; chan++) {
3084 int stride = 4;
3085 if (!(writemask & (1 << chan)))
3086 continue;
3087
3088 value = llvm_extract_elem(&ctx->ac, src, chan);
3089
3090 if (instr->variables[0]->var->data.compact)
3091 stride = 1;
3092 if (indir_index) {
3093 unsigned count = glsl_count_attribute_slots(
3094 instr->variables[0]->var->type, false);
3095 count -= chan / 4;
3096 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3097 &ctx->ac, ctx->outputs + idx + chan, count,
3098 stride, true, true);
3099
3100 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3101 value, indir_index, "");
3102 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3103 count, stride, tmp_vec);
3104
3105 } else {
3106 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3107
3108 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3109 }
3110 }
3111 break;
3112 case nir_var_local:
3113 for (unsigned chan = 0; chan < 8; chan++) {
3114 if (!(writemask & (1 << chan)))
3115 continue;
3116
3117 value = llvm_extract_elem(&ctx->ac, src, chan);
3118 if (indir_index) {
3119 unsigned count = glsl_count_attribute_slots(
3120 instr->variables[0]->var->type, false);
3121 count -= chan / 4;
3122 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3123 &ctx->ac, ctx->locals + idx + chan, count,
3124 4, true, true);
3125
3126 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3127 value, indir_index, "");
3128 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3129 count, 4, tmp_vec);
3130 } else {
3131 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3132
3133 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3134 }
3135 }
3136 break;
3137 case nir_var_shared: {
3138 int writemask = instr->const_index[0];
3139 LLVMValueRef address = build_gep_for_deref(ctx,
3140 instr->variables[0]);
3141 LLVMValueRef val = get_src(ctx, instr->src[0]);
3142 unsigned components =
3143 glsl_get_vector_elements(
3144 nir_deref_tail(&instr->variables[0]->deref)->type);
3145 if (writemask == (1 << components) - 1) {
3146 val = LLVMBuildBitCast(
3147 ctx->ac.builder, val,
3148 LLVMGetElementType(LLVMTypeOf(address)), "");
3149 LLVMBuildStore(ctx->ac.builder, val, address);
3150 } else {
3151 for (unsigned chan = 0; chan < 4; chan++) {
3152 if (!(writemask & (1 << chan)))
3153 continue;
3154 LLVMValueRef ptr =
3155 LLVMBuildStructGEP(ctx->ac.builder,
3156 address, chan, "");
3157 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3158 chan);
3159 src = LLVMBuildBitCast(
3160 ctx->ac.builder, src,
3161 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3162 LLVMBuildStore(ctx->ac.builder, src, ptr);
3163 }
3164 }
3165 break;
3166 }
3167 default:
3168 break;
3169 }
3170 }
3171
3172 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3173 {
3174 switch (dim) {
3175 case GLSL_SAMPLER_DIM_BUF:
3176 return 1;
3177 case GLSL_SAMPLER_DIM_1D:
3178 return array ? 2 : 1;
3179 case GLSL_SAMPLER_DIM_2D:
3180 return array ? 3 : 2;
3181 case GLSL_SAMPLER_DIM_MS:
3182 return array ? 4 : 3;
3183 case GLSL_SAMPLER_DIM_3D:
3184 case GLSL_SAMPLER_DIM_CUBE:
3185 return 3;
3186 case GLSL_SAMPLER_DIM_RECT:
3187 case GLSL_SAMPLER_DIM_SUBPASS:
3188 return 2;
3189 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3190 return 3;
3191 default:
3192 break;
3193 }
3194 return 0;
3195 }
3196
3197
3198
3199 /* Adjust the sample index according to FMASK.
3200 *
3201 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3202 * which is the identity mapping. Each nibble says which physical sample
3203 * should be fetched to get that sample.
3204 *
3205 * For example, 0x11111100 means there are only 2 samples stored and
3206 * the second sample covers 3/4 of the pixel. When reading samples 0
3207 * and 1, return physical sample 0 (determined by the first two 0s
3208 * in FMASK), otherwise return physical sample 1.
3209 *
3210 * The sample index should be adjusted as follows:
3211 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3212 */
3213 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3214 LLVMValueRef coord_x, LLVMValueRef coord_y,
3215 LLVMValueRef coord_z,
3216 LLVMValueRef sample_index,
3217 LLVMValueRef fmask_desc_ptr)
3218 {
3219 LLVMValueRef fmask_load_address[4];
3220 LLVMValueRef res;
3221
3222 fmask_load_address[0] = coord_x;
3223 fmask_load_address[1] = coord_y;
3224 if (coord_z) {
3225 fmask_load_address[2] = coord_z;
3226 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3227 }
3228
3229 struct ac_image_args args = {0};
3230
3231 args.opcode = ac_image_load;
3232 args.da = coord_z ? true : false;
3233 args.resource = fmask_desc_ptr;
3234 args.dmask = 0xf;
3235 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3236
3237 res = ac_build_image_opcode(ctx, &args);
3238
3239 res = to_integer(ctx, res);
3240 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3241 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3242
3243 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3244 res,
3245 ctx->i32_0, "");
3246
3247 LLVMValueRef sample_index4 =
3248 LLVMBuildMul(ctx->builder, sample_index, four, "");
3249 LLVMValueRef shifted_fmask =
3250 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3251 LLVMValueRef final_sample =
3252 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3253
3254 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3255 * resource descriptor is 0 (invalid),
3256 */
3257 LLVMValueRef fmask_desc =
3258 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3259 ctx->v8i32, "");
3260
3261 LLVMValueRef fmask_word1 =
3262 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3263 ctx->i32_1, "");
3264
3265 LLVMValueRef word1_is_nonzero =
3266 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3267 fmask_word1, ctx->i32_0, "");
3268
3269 /* Replace the MSAA sample index. */
3270 sample_index =
3271 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3272 final_sample, sample_index, "");
3273 return sample_index;
3274 }
3275
3276 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3277 const nir_intrinsic_instr *instr)
3278 {
3279 const struct glsl_type *type = instr->variables[0]->var->type;
3280 if(instr->variables[0]->deref.child)
3281 type = instr->variables[0]->deref.child->type;
3282
3283 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3284 LLVMValueRef coords[4];
3285 LLVMValueRef masks[] = {
3286 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3287 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3288 };
3289 LLVMValueRef res;
3290 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3291
3292 int count;
3293 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3294 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3295 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3296 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3297 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3298
3299 count = image_type_to_components_count(dim,
3300 glsl_sampler_type_is_array(type));
3301
3302 if (is_ms) {
3303 LLVMValueRef fmask_load_address[3];
3304 int chan;
3305
3306 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3307 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3308 if (glsl_sampler_type_is_array(type))
3309 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3310 else
3311 fmask_load_address[2] = NULL;
3312 if (add_frag_pos) {
3313 for (chan = 0; chan < 2; ++chan)
3314 fmask_load_address[chan] = LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->nctx->frag_pos[chan], ctx->ac.i32, ""), "");
3315 }
3316 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3317 fmask_load_address[0],
3318 fmask_load_address[1],
3319 fmask_load_address[2],
3320 sample_index,
3321 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3322 }
3323 if (count == 1) {
3324 if (instr->src[0].ssa->num_components)
3325 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3326 else
3327 res = src0;
3328 } else {
3329 int chan;
3330 if (is_ms)
3331 count--;
3332 for (chan = 0; chan < count; ++chan) {
3333 coords[chan] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[chan], "");
3334 }
3335
3336 if (add_frag_pos) {
3337 for (chan = 0; chan < count; ++chan)
3338 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->nctx->frag_pos[chan], ctx->ac.i32, ""), "");
3339 }
3340 if (is_ms) {
3341 coords[count] = sample_index;
3342 count++;
3343 }
3344
3345 if (count == 3) {
3346 coords[3] = LLVMGetUndef(ctx->ac.i32);
3347 count = 4;
3348 }
3349 res = ac_build_gather_values(&ctx->ac, coords, count);
3350 }
3351 return res;
3352 }
3353
3354 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3355 const nir_intrinsic_instr *instr)
3356 {
3357 LLVMValueRef params[7];
3358 LLVMValueRef res;
3359 char intrinsic_name[64];
3360 const nir_variable *var = instr->variables[0]->var;
3361 const struct glsl_type *type = var->type;
3362 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3363 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3364
3365 if(instr->variables[0]->deref.child)
3366 type = instr->variables[0]->deref.child->type;
3367
3368 type = glsl_without_array(type);
3369 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3370 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3371 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3372 ctx->ac.i32_0, ""); /* vindex */
3373 params[2] = ctx->ac.i32_0; /* voffset */
3374 params[3] = i1false; /* glc */
3375 params[4] = i1false; /* slc */
3376 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3377 params, 5, 0);
3378
3379 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3380 res = to_integer(&ctx->ac, res);
3381 } else {
3382 bool is_da = glsl_sampler_type_is_array(type) ||
3383 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3384 LLVMValueRef da = is_da ? i1true : i1false;
3385 LLVMValueRef glc = i1false;
3386 LLVMValueRef slc = i1false;
3387
3388 params[0] = get_image_coords(ctx, instr);
3389 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3390 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3391 if (HAVE_LLVM <= 0x0309) {
3392 params[3] = i1false; /* r128 */
3393 params[4] = da;
3394 params[5] = glc;
3395 params[6] = slc;
3396 } else {
3397 LLVMValueRef lwe = i1false;
3398 params[3] = glc;
3399 params[4] = slc;
3400 params[5] = lwe;
3401 params[6] = da;
3402 }
3403
3404 ac_get_image_intr_name("llvm.amdgcn.image.load",
3405 ctx->ac.v4f32, /* vdata */
3406 LLVMTypeOf(params[0]), /* coords */
3407 LLVMTypeOf(params[1]), /* rsrc */
3408 intrinsic_name, sizeof(intrinsic_name));
3409
3410 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3411 params, 7, AC_FUNC_ATTR_READONLY);
3412 }
3413 return to_integer(&ctx->ac, res);
3414 }
3415
3416 static void visit_image_store(struct ac_nir_context *ctx,
3417 nir_intrinsic_instr *instr)
3418 {
3419 LLVMValueRef params[8];
3420 char intrinsic_name[64];
3421 const nir_variable *var = instr->variables[0]->var;
3422 const struct glsl_type *type = glsl_without_array(var->type);
3423 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3424 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3425 LLVMValueRef glc = i1false;
3426 bool force_glc = ctx->abi->chip_class == SI;
3427 if (force_glc)
3428 glc = i1true;
3429
3430 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3431 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3432 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3433 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3434 ctx->ac.i32_0, ""); /* vindex */
3435 params[3] = ctx->ac.i32_0; /* voffset */
3436 params[4] = glc; /* glc */
3437 params[5] = i1false; /* slc */
3438 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3439 params, 6, 0);
3440 } else {
3441 bool is_da = glsl_sampler_type_is_array(type) ||
3442 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3443 LLVMValueRef da = is_da ? i1true : i1false;
3444 LLVMValueRef slc = i1false;
3445
3446 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3447 params[1] = get_image_coords(ctx, instr); /* coords */
3448 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3449 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3450 if (HAVE_LLVM <= 0x0309) {
3451 params[4] = i1false; /* r128 */
3452 params[5] = da;
3453 params[6] = glc;
3454 params[7] = slc;
3455 } else {
3456 LLVMValueRef lwe = i1false;
3457 params[4] = glc;
3458 params[5] = slc;
3459 params[6] = lwe;
3460 params[7] = da;
3461 }
3462
3463 ac_get_image_intr_name("llvm.amdgcn.image.store",
3464 LLVMTypeOf(params[0]), /* vdata */
3465 LLVMTypeOf(params[1]), /* coords */
3466 LLVMTypeOf(params[2]), /* rsrc */
3467 intrinsic_name, sizeof(intrinsic_name));
3468
3469 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3470 params, 8, 0);
3471 }
3472
3473 }
3474
3475 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3476 const nir_intrinsic_instr *instr)
3477 {
3478 LLVMValueRef params[6];
3479 int param_count = 0;
3480 const nir_variable *var = instr->variables[0]->var;
3481
3482 const char *atomic_name;
3483 char intrinsic_name[41];
3484 const struct glsl_type *type = glsl_without_array(var->type);
3485 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3486 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3487 MAYBE_UNUSED int length;
3488
3489 switch (instr->intrinsic) {
3490 case nir_intrinsic_image_atomic_add:
3491 atomic_name = "add";
3492 break;
3493 case nir_intrinsic_image_atomic_min:
3494 atomic_name = "smin";
3495 break;
3496 case nir_intrinsic_image_atomic_max:
3497 atomic_name = "smax";
3498 break;
3499 case nir_intrinsic_image_atomic_and:
3500 atomic_name = "and";
3501 break;
3502 case nir_intrinsic_image_atomic_or:
3503 atomic_name = "or";
3504 break;
3505 case nir_intrinsic_image_atomic_xor:
3506 atomic_name = "xor";
3507 break;
3508 case nir_intrinsic_image_atomic_exchange:
3509 atomic_name = "swap";
3510 break;
3511 case nir_intrinsic_image_atomic_comp_swap:
3512 atomic_name = "cmpswap";
3513 break;
3514 default:
3515 abort();
3516 }
3517
3518 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3519 params[param_count++] = get_src(ctx, instr->src[3]);
3520 params[param_count++] = get_src(ctx, instr->src[2]);
3521
3522 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3523 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3524 true, true);
3525 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3526 ctx->ac.i32_0, ""); /* vindex */
3527 params[param_count++] = ctx->ac.i32_0; /* voffset */
3528 params[param_count++] = i1false; /* slc */
3529
3530 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3531 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3532 } else {
3533 char coords_type[8];
3534
3535 bool da = glsl_sampler_type_is_array(type) ||
3536 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3537
3538 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3539 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3540 true, true);
3541 params[param_count++] = i1false; /* r128 */
3542 params[param_count++] = da ? i1true : i1false; /* da */
3543 params[param_count++] = i1false; /* slc */
3544
3545 build_int_type_name(LLVMTypeOf(coords),
3546 coords_type, sizeof(coords_type));
3547
3548 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3549 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3550 }
3551
3552 assert(length < sizeof(intrinsic_name));
3553 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3554 }
3555
3556 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3557 const nir_intrinsic_instr *instr)
3558 {
3559 LLVMValueRef res;
3560 const nir_variable *var = instr->variables[0]->var;
3561 const struct glsl_type *type = instr->variables[0]->var->type;
3562 bool da = glsl_sampler_type_is_array(var->type) ||
3563 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3564 if(instr->variables[0]->deref.child)
3565 type = instr->variables[0]->deref.child->type;
3566
3567 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3568 return get_buffer_size(ctx,
3569 get_sampler_desc(ctx, instr->variables[0],
3570 AC_DESC_BUFFER, true, false), true);
3571
3572 struct ac_image_args args = { 0 };
3573
3574 args.da = da;
3575 args.dmask = 0xf;
3576 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3577 args.opcode = ac_image_get_resinfo;
3578 args.addr = ctx->ac.i32_0;
3579
3580 res = ac_build_image_opcode(&ctx->ac, &args);
3581
3582 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3583 glsl_sampler_type_is_array(type)) {
3584 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3585 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3586 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3587 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3588 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3589 }
3590 return res;
3591 }
3592
3593 #define NOOP_WAITCNT 0xf7f
3594 #define LGKM_CNT 0x07f
3595 #define VM_CNT 0xf70
3596
3597 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3598 unsigned simm16)
3599 {
3600 LLVMValueRef args[1] = {
3601 LLVMConstInt(ctx->i32, simm16, false),
3602 };
3603 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3604 ctx->voidt, args, 1, 0);
3605 }
3606
3607 static void emit_barrier(struct nir_to_llvm_context *ctx)
3608 {
3609 /* SI only (thanks to a hw bug workaround):
3610 * The real barrier instruction isn’t needed, because an entire patch
3611 * always fits into a single wave.
3612 */
3613 if (ctx->options->chip_class == SI &&
3614 ctx->stage == MESA_SHADER_TESS_CTRL) {
3615 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3616 return;
3617 }
3618 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3619 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3620 }
3621
3622 static void emit_discard_if(struct ac_nir_context *ctx,
3623 const nir_intrinsic_instr *instr)
3624 {
3625 LLVMValueRef cond;
3626
3627 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
3628 get_src(ctx, instr->src[0]),
3629 ctx->ac.i32_0, "");
3630
3631 cond = LLVMBuildSelect(ctx->ac.builder, cond,
3632 LLVMConstReal(ctx->ac.f32, -1.0f),
3633 ctx->ac.f32_0, "");
3634 ac_build_kill(&ctx->ac, cond);
3635 }
3636
3637 static LLVMValueRef
3638 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3639 {
3640 LLVMValueRef result;
3641 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3642 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3643 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3644
3645 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3646 }
3647
3648 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3649 const nir_intrinsic_instr *instr)
3650 {
3651 LLVMValueRef ptr, result;
3652 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3653 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3654
3655 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3656 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3657 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3658 ptr, src, src1,
3659 LLVMAtomicOrderingSequentiallyConsistent,
3660 LLVMAtomicOrderingSequentiallyConsistent,
3661 false);
3662 } else {
3663 LLVMAtomicRMWBinOp op;
3664 switch (instr->intrinsic) {
3665 case nir_intrinsic_var_atomic_add:
3666 op = LLVMAtomicRMWBinOpAdd;
3667 break;
3668 case nir_intrinsic_var_atomic_umin:
3669 op = LLVMAtomicRMWBinOpUMin;
3670 break;
3671 case nir_intrinsic_var_atomic_umax:
3672 op = LLVMAtomicRMWBinOpUMax;
3673 break;
3674 case nir_intrinsic_var_atomic_imin:
3675 op = LLVMAtomicRMWBinOpMin;
3676 break;
3677 case nir_intrinsic_var_atomic_imax:
3678 op = LLVMAtomicRMWBinOpMax;
3679 break;
3680 case nir_intrinsic_var_atomic_and:
3681 op = LLVMAtomicRMWBinOpAnd;
3682 break;
3683 case nir_intrinsic_var_atomic_or:
3684 op = LLVMAtomicRMWBinOpOr;
3685 break;
3686 case nir_intrinsic_var_atomic_xor:
3687 op = LLVMAtomicRMWBinOpXor;
3688 break;
3689 case nir_intrinsic_var_atomic_exchange:
3690 op = LLVMAtomicRMWBinOpXchg;
3691 break;
3692 default:
3693 return NULL;
3694 }
3695
3696 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3697 LLVMAtomicOrderingSequentiallyConsistent,
3698 false);
3699 }
3700 return result;
3701 }
3702
3703 #define INTERP_CENTER 0
3704 #define INTERP_CENTROID 1
3705 #define INTERP_SAMPLE 2
3706
3707 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3708 enum glsl_interp_mode interp, unsigned location)
3709 {
3710 switch (interp) {
3711 case INTERP_MODE_FLAT:
3712 default:
3713 return NULL;
3714 case INTERP_MODE_SMOOTH:
3715 case INTERP_MODE_NONE:
3716 if (location == INTERP_CENTER)
3717 return ctx->persp_center;
3718 else if (location == INTERP_CENTROID)
3719 return ctx->persp_centroid;
3720 else if (location == INTERP_SAMPLE)
3721 return ctx->persp_sample;
3722 break;
3723 case INTERP_MODE_NOPERSPECTIVE:
3724 if (location == INTERP_CENTER)
3725 return ctx->linear_center;
3726 else if (location == INTERP_CENTROID)
3727 return ctx->linear_centroid;
3728 else if (location == INTERP_SAMPLE)
3729 return ctx->linear_sample;
3730 break;
3731 }
3732 return NULL;
3733 }
3734
3735 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3736 LLVMValueRef sample_id)
3737 {
3738 LLVMValueRef result;
3739 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3740
3741 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3742 const_array(ctx->v2f32, 64), "");
3743
3744 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3745 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3746
3747 return result;
3748 }
3749
3750 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3751 {
3752 LLVMValueRef values[2];
3753
3754 values[0] = emit_ffract(&ctx->ac, ctx->frag_pos[0]);
3755 values[1] = emit_ffract(&ctx->ac, ctx->frag_pos[1]);
3756 return ac_build_gather_values(&ctx->ac, values, 2);
3757 }
3758
3759 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3760 const nir_intrinsic_instr *instr)
3761 {
3762 LLVMValueRef result[2];
3763 LLVMValueRef interp_param, attr_number;
3764 unsigned location;
3765 unsigned chan;
3766 LLVMValueRef src_c0, src_c1;
3767 LLVMValueRef src0;
3768 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3769 switch (instr->intrinsic) {
3770 case nir_intrinsic_interp_var_at_centroid:
3771 location = INTERP_CENTROID;
3772 break;
3773 case nir_intrinsic_interp_var_at_sample:
3774 case nir_intrinsic_interp_var_at_offset:
3775 location = INTERP_CENTER;
3776 src0 = get_src(ctx->nir, instr->src[0]);
3777 break;
3778 default:
3779 break;
3780 }
3781
3782 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3783 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3784 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3785 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3786 LLVMValueRef sample_position;
3787 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3788
3789 /* fetch sample ID */
3790 sample_position = load_sample_position(ctx, src0);
3791
3792 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3793 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3794 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3795 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3796 }
3797 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3798 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3799
3800 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3801 LLVMValueRef ij_out[2];
3802 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3803
3804 /*
3805 * take the I then J parameters, and the DDX/Y for it, and
3806 * calculate the IJ inputs for the interpolator.
3807 * temp1 = ddx * offset/sample.x + I;
3808 * interp_param.I = ddy * offset/sample.y + temp1;
3809 * temp1 = ddx * offset/sample.x + J;
3810 * interp_param.J = ddy * offset/sample.y + temp1;
3811 */
3812 for (unsigned i = 0; i < 2; i++) {
3813 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3814 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3815 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3816 ddxy_out, ix_ll, "");
3817 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3818 ddxy_out, iy_ll, "");
3819 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3820 interp_param, ix_ll, "");
3821 LLVMValueRef temp1, temp2;
3822
3823 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3824 ctx->f32, "");
3825
3826 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3827 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3828
3829 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3830 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3831
3832 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3833 temp2, ctx->i32, "");
3834 }
3835 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3836
3837 }
3838
3839 for (chan = 0; chan < 2; chan++) {
3840 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3841
3842 if (interp_param) {
3843 interp_param = LLVMBuildBitCast(ctx->builder,
3844 interp_param, LLVMVectorType(ctx->f32, 2), "");
3845 LLVMValueRef i = LLVMBuildExtractElement(
3846 ctx->builder, interp_param, ctx->i32zero, "");
3847 LLVMValueRef j = LLVMBuildExtractElement(
3848 ctx->builder, interp_param, ctx->i32one, "");
3849
3850 result[chan] = ac_build_fs_interp(&ctx->ac,
3851 llvm_chan, attr_number,
3852 ctx->prim_mask, i, j);
3853 } else {
3854 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3855 LLVMConstInt(ctx->i32, 2, false),
3856 llvm_chan, attr_number,
3857 ctx->prim_mask);
3858 }
3859 }
3860 return ac_build_gather_values(&ctx->ac, result, 2);
3861 }
3862
3863 static void
3864 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3865 const nir_intrinsic_instr *instr)
3866 {
3867 LLVMValueRef gs_next_vertex;
3868 LLVMValueRef can_emit, kill;
3869 int idx;
3870
3871 assert(instr->const_index[0] == 0);
3872 /* Write vertex attribute values to GSVS ring */
3873 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3874 ctx->gs_next_vertex,
3875 "");
3876
3877 /* If this thread has already emitted the declared maximum number of
3878 * vertices, kill it: excessive vertex emissions are not supposed to
3879 * have any effect, and GS threads have no externally observable
3880 * effects other than emitting vertices.
3881 */
3882 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3883 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3884
3885 kill = LLVMBuildSelect(ctx->builder, can_emit,
3886 LLVMConstReal(ctx->f32, 1.0f),
3887 LLVMConstReal(ctx->f32, -1.0f), "");
3888 ac_build_kill(&ctx->ac, kill);
3889
3890 /* loop num outputs */
3891 idx = 0;
3892 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3893 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3894 int length = 4;
3895 int slot = idx;
3896 int slot_inc = 1;
3897
3898 if (!(ctx->output_mask & (1ull << i)))
3899 continue;
3900
3901 if (i == VARYING_SLOT_CLIP_DIST0) {
3902 /* pack clip and cull into a single set of slots */
3903 length = ctx->num_output_clips + ctx->num_output_culls;
3904 if (length > 4)
3905 slot_inc = 2;
3906 }
3907 for (unsigned j = 0; j < length; j++) {
3908 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3909 out_ptr[j], "");
3910 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3911 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3912 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3913
3914 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3915
3916 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3917 out_val, 1,
3918 voffset, ctx->gs2vs_offset, 0,
3919 1, 1, true, true);
3920 }
3921 idx += slot_inc;
3922 }
3923
3924 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3925 ctx->i32one, "");
3926 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3927
3928 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3929 }
3930
3931 static void
3932 visit_end_primitive(struct nir_to_llvm_context *ctx,
3933 const nir_intrinsic_instr *instr)
3934 {
3935 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3936 }
3937
3938 static LLVMValueRef
3939 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3940 const nir_intrinsic_instr *instr)
3941 {
3942 LLVMValueRef coord[4] = {
3943 ctx->tes_u,
3944 ctx->tes_v,
3945 ctx->f32zero,
3946 ctx->f32zero,
3947 };
3948
3949 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3950 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3951 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3952
3953 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3954 return LLVMBuildBitCast(ctx->builder, result,
3955 get_def_type(ctx->nir, &instr->dest.ssa), "");
3956 }
3957
3958 static void visit_intrinsic(struct ac_nir_context *ctx,
3959 nir_intrinsic_instr *instr)
3960 {
3961 LLVMValueRef result = NULL;
3962
3963 switch (instr->intrinsic) {
3964 case nir_intrinsic_load_work_group_id: {
3965 result = ctx->nctx->workgroup_ids;
3966 break;
3967 }
3968 case nir_intrinsic_load_base_vertex: {
3969 result = ctx->abi->base_vertex;
3970 break;
3971 }
3972 case nir_intrinsic_load_vertex_id_zero_base: {
3973 result = ctx->abi->vertex_id;
3974 break;
3975 }
3976 case nir_intrinsic_load_local_invocation_id: {
3977 result = ctx->nctx->local_invocation_ids;
3978 break;
3979 }
3980 case nir_intrinsic_load_base_instance:
3981 result = ctx->abi->start_instance;
3982 break;
3983 case nir_intrinsic_load_draw_id:
3984 result = ctx->abi->draw_id;
3985 break;
3986 case nir_intrinsic_load_invocation_id:
3987 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3988 result = unpack_param(ctx->nctx, ctx->nctx->tcs_rel_ids, 8, 5);
3989 else
3990 result = ctx->nctx->gs_invocation_id;
3991 break;
3992 case nir_intrinsic_load_primitive_id:
3993 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3994 ctx->nctx->shader_info->gs.uses_prim_id = true;
3995 result = ctx->nctx->gs_prim_id;
3996 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3997 ctx->nctx->shader_info->tcs.uses_prim_id = true;
3998 result = ctx->nctx->tcs_patch_id;
3999 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4000 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4001 result = ctx->nctx->tes_patch_id;
4002 } else
4003 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4004 break;
4005 case nir_intrinsic_load_sample_id:
4006 ctx->nctx->shader_info->fs.force_persample = true;
4007 result = unpack_param(ctx->nctx, ctx->nctx->ancillary, 8, 4);
4008 break;
4009 case nir_intrinsic_load_sample_pos:
4010 ctx->nctx->shader_info->fs.force_persample = true;
4011 result = load_sample_pos(ctx->nctx);
4012 break;
4013 case nir_intrinsic_load_sample_mask_in:
4014 result = ctx->nctx->sample_coverage;
4015 break;
4016 case nir_intrinsic_load_front_face:
4017 result = ctx->abi->front_face;
4018 break;
4019 case nir_intrinsic_load_instance_id:
4020 result = ctx->abi->instance_id;
4021 break;
4022 case nir_intrinsic_load_num_work_groups:
4023 result = ctx->nctx->num_work_groups;
4024 break;
4025 case nir_intrinsic_load_local_invocation_index:
4026 result = visit_load_local_invocation_index(ctx->nctx);
4027 break;
4028 case nir_intrinsic_load_push_constant:
4029 result = visit_load_push_constant(ctx->nctx, instr);
4030 break;
4031 case nir_intrinsic_vulkan_resource_index:
4032 result = visit_vulkan_resource_index(ctx->nctx, instr);
4033 break;
4034 case nir_intrinsic_store_ssbo:
4035 visit_store_ssbo(ctx, instr);
4036 break;
4037 case nir_intrinsic_load_ssbo:
4038 result = visit_load_buffer(ctx, instr);
4039 break;
4040 case nir_intrinsic_ssbo_atomic_add:
4041 case nir_intrinsic_ssbo_atomic_imin:
4042 case nir_intrinsic_ssbo_atomic_umin:
4043 case nir_intrinsic_ssbo_atomic_imax:
4044 case nir_intrinsic_ssbo_atomic_umax:
4045 case nir_intrinsic_ssbo_atomic_and:
4046 case nir_intrinsic_ssbo_atomic_or:
4047 case nir_intrinsic_ssbo_atomic_xor:
4048 case nir_intrinsic_ssbo_atomic_exchange:
4049 case nir_intrinsic_ssbo_atomic_comp_swap:
4050 result = visit_atomic_ssbo(ctx, instr);
4051 break;
4052 case nir_intrinsic_load_ubo:
4053 result = visit_load_ubo_buffer(ctx, instr);
4054 break;
4055 case nir_intrinsic_get_buffer_size:
4056 result = visit_get_buffer_size(ctx, instr);
4057 break;
4058 case nir_intrinsic_load_var:
4059 result = visit_load_var(ctx, instr);
4060 break;
4061 case nir_intrinsic_store_var:
4062 visit_store_var(ctx, instr);
4063 break;
4064 case nir_intrinsic_image_load:
4065 result = visit_image_load(ctx, instr);
4066 break;
4067 case nir_intrinsic_image_store:
4068 visit_image_store(ctx, instr);
4069 break;
4070 case nir_intrinsic_image_atomic_add:
4071 case nir_intrinsic_image_atomic_min:
4072 case nir_intrinsic_image_atomic_max:
4073 case nir_intrinsic_image_atomic_and:
4074 case nir_intrinsic_image_atomic_or:
4075 case nir_intrinsic_image_atomic_xor:
4076 case nir_intrinsic_image_atomic_exchange:
4077 case nir_intrinsic_image_atomic_comp_swap:
4078 result = visit_image_atomic(ctx, instr);
4079 break;
4080 case nir_intrinsic_image_size:
4081 result = visit_image_size(ctx, instr);
4082 break;
4083 case nir_intrinsic_discard:
4084 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4085 LLVMVoidTypeInContext(ctx->ac.context),
4086 NULL, 0, AC_FUNC_ATTR_LEGACY);
4087 break;
4088 case nir_intrinsic_discard_if:
4089 emit_discard_if(ctx, instr);
4090 break;
4091 case nir_intrinsic_memory_barrier:
4092 emit_waitcnt(ctx->nctx, VM_CNT);
4093 break;
4094 case nir_intrinsic_barrier:
4095 emit_barrier(ctx->nctx);
4096 break;
4097 case nir_intrinsic_var_atomic_add:
4098 case nir_intrinsic_var_atomic_imin:
4099 case nir_intrinsic_var_atomic_umin:
4100 case nir_intrinsic_var_atomic_imax:
4101 case nir_intrinsic_var_atomic_umax:
4102 case nir_intrinsic_var_atomic_and:
4103 case nir_intrinsic_var_atomic_or:
4104 case nir_intrinsic_var_atomic_xor:
4105 case nir_intrinsic_var_atomic_exchange:
4106 case nir_intrinsic_var_atomic_comp_swap:
4107 result = visit_var_atomic(ctx->nctx, instr);
4108 break;
4109 case nir_intrinsic_interp_var_at_centroid:
4110 case nir_intrinsic_interp_var_at_sample:
4111 case nir_intrinsic_interp_var_at_offset:
4112 result = visit_interp(ctx->nctx, instr);
4113 break;
4114 case nir_intrinsic_emit_vertex:
4115 visit_emit_vertex(ctx->nctx, instr);
4116 break;
4117 case nir_intrinsic_end_primitive:
4118 visit_end_primitive(ctx->nctx, instr);
4119 break;
4120 case nir_intrinsic_load_tess_coord:
4121 result = visit_load_tess_coord(ctx->nctx, instr);
4122 break;
4123 case nir_intrinsic_load_patch_vertices_in:
4124 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4125 break;
4126 default:
4127 fprintf(stderr, "Unknown intrinsic: ");
4128 nir_print_instr(&instr->instr, stderr);
4129 fprintf(stderr, "\n");
4130 break;
4131 }
4132 if (result) {
4133 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4134 }
4135 }
4136
4137 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4138 LLVMValueRef buffer, bool write)
4139 {
4140 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4141
4142 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4143 ctx->shader_info->fs.writes_memory = true;
4144
4145 return buffer;
4146 }
4147
4148 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4149 unsigned descriptor_set,
4150 unsigned base_index,
4151 unsigned constant_index,
4152 LLVMValueRef index,
4153 enum ac_descriptor_type desc_type,
4154 bool image, bool write)
4155 {
4156 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4157 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4158 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4159 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4160 unsigned offset = binding->offset;
4161 unsigned stride = binding->size;
4162 unsigned type_size;
4163 LLVMBuilderRef builder = ctx->builder;
4164 LLVMTypeRef type;
4165
4166 assert(base_index < layout->binding_count);
4167
4168 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4169 ctx->shader_info->fs.writes_memory = true;
4170
4171 switch (desc_type) {
4172 case AC_DESC_IMAGE:
4173 type = ctx->v8i32;
4174 type_size = 32;
4175 break;
4176 case AC_DESC_FMASK:
4177 type = ctx->v8i32;
4178 offset += 32;
4179 type_size = 32;
4180 break;
4181 case AC_DESC_SAMPLER:
4182 type = ctx->v4i32;
4183 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4184 offset += 64;
4185
4186 type_size = 16;
4187 break;
4188 case AC_DESC_BUFFER:
4189 type = ctx->v4i32;
4190 type_size = 16;
4191 break;
4192 default:
4193 unreachable("invalid desc_type\n");
4194 }
4195
4196 offset += constant_index * stride;
4197
4198 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4199 (!index || binding->immutable_samplers_equal)) {
4200 if (binding->immutable_samplers_equal)
4201 constant_index = 0;
4202
4203 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4204
4205 LLVMValueRef constants[] = {
4206 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4207 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4208 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4209 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4210 };
4211 return ac_build_gather_values(&ctx->ac, constants, 4);
4212 }
4213
4214 assert(stride % type_size == 0);
4215
4216 if (!index)
4217 index = ctx->i32zero;
4218
4219 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4220
4221 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4222 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4223
4224 return ac_build_indexed_load_const(&ctx->ac, list, index);
4225 }
4226
4227 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4228 const nir_deref_var *deref,
4229 enum ac_descriptor_type desc_type,
4230 bool image, bool write)
4231 {
4232 LLVMValueRef index = NULL;
4233 unsigned constant_index = 0;
4234 const nir_deref *tail = &deref->deref;
4235
4236 while (tail->child) {
4237 const nir_deref_array *child = nir_deref_as_array(tail->child);
4238 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4239
4240 if (!array_size)
4241 array_size = 1;
4242
4243 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4244
4245 if (child->deref_array_type == nir_deref_array_type_indirect) {
4246 LLVMValueRef indirect = get_src(ctx, child->indirect);
4247
4248 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4249 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4250
4251 if (!index)
4252 index = indirect;
4253 else
4254 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4255 }
4256
4257 constant_index += child->base_offset * array_size;
4258
4259 tail = &child->deref;
4260 }
4261
4262 return ctx->abi->load_sampler_desc(ctx->abi,
4263 deref->var->data.descriptor_set,
4264 deref->var->data.binding,
4265 constant_index, index,
4266 desc_type, image, write);
4267 }
4268
4269 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4270 struct ac_image_args *args,
4271 const nir_tex_instr *instr,
4272 nir_texop op,
4273 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4274 LLVMValueRef *param, unsigned count,
4275 unsigned dmask)
4276 {
4277 unsigned is_rect = 0;
4278 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4279
4280 if (op == nir_texop_lod)
4281 da = false;
4282 /* Pad to power of two vector */
4283 while (count < util_next_power_of_two(count))
4284 param[count++] = LLVMGetUndef(ctx->i32);
4285
4286 if (count > 1)
4287 args->addr = ac_build_gather_values(ctx, param, count);
4288 else
4289 args->addr = param[0];
4290
4291 args->resource = res_ptr;
4292 args->sampler = samp_ptr;
4293
4294 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4295 args->addr = param[0];
4296 return;
4297 }
4298
4299 args->dmask = dmask;
4300 args->unorm = is_rect;
4301 args->da = da;
4302 }
4303
4304 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4305 *
4306 * SI-CI:
4307 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4308 * filtering manually. The driver sets img7 to a mask clearing
4309 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4310 * s_and_b32 samp0, samp0, img7
4311 *
4312 * VI:
4313 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4314 */
4315 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4316 LLVMValueRef res, LLVMValueRef samp)
4317 {
4318 LLVMBuilderRef builder = ctx->ac.builder;
4319 LLVMValueRef img7, samp0;
4320
4321 if (ctx->abi->chip_class >= VI)
4322 return samp;
4323
4324 img7 = LLVMBuildExtractElement(builder, res,
4325 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4326 samp0 = LLVMBuildExtractElement(builder, samp,
4327 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4328 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4329 return LLVMBuildInsertElement(builder, samp, samp0,
4330 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4331 }
4332
4333 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4334 nir_tex_instr *instr,
4335 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4336 LLVMValueRef *fmask_ptr)
4337 {
4338 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4339 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4340 else
4341 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4342 if (samp_ptr) {
4343 if (instr->sampler)
4344 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4345 else
4346 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4347 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4348 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4349 }
4350 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4351 instr->op == nir_texop_samples_identical))
4352 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4353 }
4354
4355 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4356 LLVMValueRef coord)
4357 {
4358 coord = to_float(ctx, coord);
4359 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4360 coord = to_integer(ctx, coord);
4361 return coord;
4362 }
4363
4364 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4365 {
4366 LLVMValueRef result = NULL;
4367 struct ac_image_args args = { 0 };
4368 unsigned dmask = 0xf;
4369 LLVMValueRef address[16];
4370 LLVMValueRef coords[5];
4371 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4372 LLVMValueRef bias = NULL, offsets = NULL;
4373 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4374 LLVMValueRef ddx = NULL, ddy = NULL;
4375 LLVMValueRef derivs[6];
4376 unsigned chan, count = 0;
4377 unsigned const_src = 0, num_deriv_comp = 0;
4378 bool lod_is_zero = false;
4379
4380 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4381
4382 for (unsigned i = 0; i < instr->num_srcs; i++) {
4383 switch (instr->src[i].src_type) {
4384 case nir_tex_src_coord:
4385 coord = get_src(ctx, instr->src[i].src);
4386 break;
4387 case nir_tex_src_projector:
4388 break;
4389 case nir_tex_src_comparator:
4390 comparator = get_src(ctx, instr->src[i].src);
4391 break;
4392 case nir_tex_src_offset:
4393 offsets = get_src(ctx, instr->src[i].src);
4394 const_src = i;
4395 break;
4396 case nir_tex_src_bias:
4397 bias = get_src(ctx, instr->src[i].src);
4398 break;
4399 case nir_tex_src_lod: {
4400 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4401
4402 if (val && val->i32[0] == 0)
4403 lod_is_zero = true;
4404 lod = get_src(ctx, instr->src[i].src);
4405 break;
4406 }
4407 case nir_tex_src_ms_index:
4408 sample_index = get_src(ctx, instr->src[i].src);
4409 break;
4410 case nir_tex_src_ms_mcs:
4411 break;
4412 case nir_tex_src_ddx:
4413 ddx = get_src(ctx, instr->src[i].src);
4414 num_deriv_comp = instr->src[i].src.ssa->num_components;
4415 break;
4416 case nir_tex_src_ddy:
4417 ddy = get_src(ctx, instr->src[i].src);
4418 break;
4419 case nir_tex_src_texture_offset:
4420 case nir_tex_src_sampler_offset:
4421 case nir_tex_src_plane:
4422 default:
4423 break;
4424 }
4425 }
4426
4427 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4428 result = get_buffer_size(ctx, res_ptr, true);
4429 goto write_result;
4430 }
4431
4432 if (instr->op == nir_texop_texture_samples) {
4433 LLVMValueRef res, samples, is_msaa;
4434 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4435 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4436 LLVMConstInt(ctx->ac.i32, 3, false), "");
4437 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4438 LLVMConstInt(ctx->ac.i32, 28, false), "");
4439 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4440 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4441 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4442 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4443
4444 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4445 LLVMConstInt(ctx->ac.i32, 16, false), "");
4446 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4447 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4448 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4449 samples, "");
4450 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4451 ctx->ac.i32_1, "");
4452 result = samples;
4453 goto write_result;
4454 }
4455
4456 if (coord)
4457 for (chan = 0; chan < instr->coord_components; chan++)
4458 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4459
4460 if (offsets && instr->op != nir_texop_txf) {
4461 LLVMValueRef offset[3], pack;
4462 for (chan = 0; chan < 3; ++chan)
4463 offset[chan] = ctx->ac.i32_0;
4464
4465 args.offset = true;
4466 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4467 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4468 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4469 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4470 if (chan)
4471 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4472 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4473 }
4474 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4475 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4476 address[count++] = pack;
4477
4478 }
4479 /* pack LOD bias value */
4480 if (instr->op == nir_texop_txb && bias) {
4481 address[count++] = bias;
4482 }
4483
4484 /* Pack depth comparison value */
4485 if (instr->is_shadow && comparator) {
4486 address[count++] = llvm_extract_elem(&ctx->ac, comparator, 0);
4487 }
4488
4489 /* pack derivatives */
4490 if (ddx || ddy) {
4491 switch (instr->sampler_dim) {
4492 case GLSL_SAMPLER_DIM_3D:
4493 case GLSL_SAMPLER_DIM_CUBE:
4494 num_deriv_comp = 3;
4495 break;
4496 case GLSL_SAMPLER_DIM_2D:
4497 default:
4498 num_deriv_comp = 2;
4499 break;
4500 case GLSL_SAMPLER_DIM_1D:
4501 num_deriv_comp = 1;
4502 break;
4503 }
4504
4505 for (unsigned i = 0; i < num_deriv_comp; i++) {
4506 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4507 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4508 }
4509 }
4510
4511 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4512 if (instr->is_array && instr->op != nir_texop_lod)
4513 coords[3] = apply_round_slice(&ctx->ac, coords[3]);
4514 for (chan = 0; chan < instr->coord_components; chan++)
4515 coords[chan] = to_float(&ctx->ac, coords[chan]);
4516 if (instr->coord_components == 3)
4517 coords[3] = LLVMGetUndef(ctx->ac.f32);
4518 ac_prepare_cube_coords(&ctx->ac,
4519 instr->op == nir_texop_txd, instr->is_array,
4520 coords, derivs);
4521 if (num_deriv_comp)
4522 num_deriv_comp--;
4523 }
4524
4525 if (ddx || ddy) {
4526 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4527 address[count++] = derivs[i];
4528 }
4529
4530 /* Pack texture coordinates */
4531 if (coord) {
4532 address[count++] = coords[0];
4533 if (instr->coord_components > 1) {
4534 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4535 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4536 }
4537 address[count++] = coords[1];
4538 }
4539 if (instr->coord_components > 2) {
4540 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4541 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4542 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4543 instr->op != nir_texop_txf) {
4544 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4545 }
4546 address[count++] = coords[2];
4547 }
4548 }
4549
4550 /* Pack LOD */
4551 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4552 instr->op == nir_texop_txf)) {
4553 address[count++] = lod;
4554 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4555 address[count++] = sample_index;
4556 } else if(instr->op == nir_texop_txs) {
4557 count = 0;
4558 if (lod)
4559 address[count++] = lod;
4560 else
4561 address[count++] = ctx->ac.i32_0;
4562 }
4563
4564 for (chan = 0; chan < count; chan++) {
4565 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4566 address[chan], ctx->ac.i32, "");
4567 }
4568
4569 if (instr->op == nir_texop_samples_identical) {
4570 LLVMValueRef txf_address[4];
4571 struct ac_image_args txf_args = { 0 };
4572 unsigned txf_count = count;
4573 memcpy(txf_address, address, sizeof(txf_address));
4574
4575 if (!instr->is_array)
4576 txf_address[2] = ctx->ac.i32_0;
4577 txf_address[3] = ctx->ac.i32_0;
4578
4579 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4580 fmask_ptr, NULL,
4581 txf_address, txf_count, 0xf);
4582
4583 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4584
4585 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4586 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4587 goto write_result;
4588 }
4589
4590 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4591 instr->op != nir_texop_txs) {
4592 unsigned sample_chan = instr->is_array ? 3 : 2;
4593 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4594 address[0],
4595 address[1],
4596 instr->is_array ? address[2] : NULL,
4597 address[sample_chan],
4598 fmask_ptr);
4599 }
4600
4601 if (offsets && instr->op == nir_texop_txf) {
4602 nir_const_value *const_offset =
4603 nir_src_as_const_value(instr->src[const_src].src);
4604 int num_offsets = instr->src[const_src].src.ssa->num_components;
4605 assert(const_offset);
4606 num_offsets = MIN2(num_offsets, instr->coord_components);
4607 if (num_offsets > 2)
4608 address[2] = LLVMBuildAdd(ctx->ac.builder,
4609 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4610 if (num_offsets > 1)
4611 address[1] = LLVMBuildAdd(ctx->ac.builder,
4612 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4613 address[0] = LLVMBuildAdd(ctx->ac.builder,
4614 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4615
4616 }
4617
4618 /* TODO TG4 support */
4619 if (instr->op == nir_texop_tg4) {
4620 if (instr->is_shadow)
4621 dmask = 1;
4622 else
4623 dmask = 1 << instr->component;
4624 }
4625 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4626 res_ptr, samp_ptr, address, count, dmask);
4627
4628 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4629
4630 if (instr->op == nir_texop_query_levels)
4631 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4632 else if (instr->is_shadow && instr->is_new_style_shadow &&
4633 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4634 instr->op != nir_texop_tg4)
4635 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4636 else if (instr->op == nir_texop_txs &&
4637 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4638 instr->is_array) {
4639 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4640 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4641 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4642 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4643 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4644 } else if (instr->dest.ssa.num_components != 4)
4645 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4646
4647 write_result:
4648 if (result) {
4649 assert(instr->dest.is_ssa);
4650 result = to_integer(&ctx->ac, result);
4651 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4652 }
4653 }
4654
4655
4656 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4657 {
4658 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4659 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4660
4661 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4662 _mesa_hash_table_insert(ctx->phis, instr, result);
4663 }
4664
4665 static void visit_post_phi(struct ac_nir_context *ctx,
4666 nir_phi_instr *instr,
4667 LLVMValueRef llvm_phi)
4668 {
4669 nir_foreach_phi_src(src, instr) {
4670 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4671 LLVMValueRef llvm_src = get_src(ctx, src->src);
4672
4673 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4674 }
4675 }
4676
4677 static void phi_post_pass(struct ac_nir_context *ctx)
4678 {
4679 struct hash_entry *entry;
4680 hash_table_foreach(ctx->phis, entry) {
4681 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4682 (LLVMValueRef)entry->data);
4683 }
4684 }
4685
4686
4687 static void visit_ssa_undef(struct ac_nir_context *ctx,
4688 const nir_ssa_undef_instr *instr)
4689 {
4690 unsigned num_components = instr->def.num_components;
4691 LLVMValueRef undef;
4692
4693 if (num_components == 1)
4694 undef = LLVMGetUndef(ctx->ac.i32);
4695 else {
4696 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4697 }
4698 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4699 }
4700
4701 static void visit_jump(struct ac_nir_context *ctx,
4702 const nir_jump_instr *instr)
4703 {
4704 switch (instr->type) {
4705 case nir_jump_break:
4706 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4707 LLVMClearInsertionPosition(ctx->ac.builder);
4708 break;
4709 case nir_jump_continue:
4710 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4711 LLVMClearInsertionPosition(ctx->ac.builder);
4712 break;
4713 default:
4714 fprintf(stderr, "Unknown NIR jump instr: ");
4715 nir_print_instr(&instr->instr, stderr);
4716 fprintf(stderr, "\n");
4717 abort();
4718 }
4719 }
4720
4721 static void visit_cf_list(struct ac_nir_context *ctx,
4722 struct exec_list *list);
4723
4724 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4725 {
4726 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4727 nir_foreach_instr(instr, block)
4728 {
4729 switch (instr->type) {
4730 case nir_instr_type_alu:
4731 visit_alu(ctx, nir_instr_as_alu(instr));
4732 break;
4733 case nir_instr_type_load_const:
4734 visit_load_const(ctx, nir_instr_as_load_const(instr));
4735 break;
4736 case nir_instr_type_intrinsic:
4737 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4738 break;
4739 case nir_instr_type_tex:
4740 visit_tex(ctx, nir_instr_as_tex(instr));
4741 break;
4742 case nir_instr_type_phi:
4743 visit_phi(ctx, nir_instr_as_phi(instr));
4744 break;
4745 case nir_instr_type_ssa_undef:
4746 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4747 break;
4748 case nir_instr_type_jump:
4749 visit_jump(ctx, nir_instr_as_jump(instr));
4750 break;
4751 default:
4752 fprintf(stderr, "Unknown NIR instr type: ");
4753 nir_print_instr(instr, stderr);
4754 fprintf(stderr, "\n");
4755 abort();
4756 }
4757 }
4758
4759 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4760 }
4761
4762 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4763 {
4764 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4765
4766 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4767 LLVMBasicBlockRef merge_block =
4768 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4769 LLVMBasicBlockRef if_block =
4770 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4771 LLVMBasicBlockRef else_block = merge_block;
4772 if (!exec_list_is_empty(&if_stmt->else_list))
4773 else_block = LLVMAppendBasicBlockInContext(
4774 ctx->ac.context, fn, "");
4775
4776 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4777 LLVMConstInt(ctx->ac.i32, 0, false), "");
4778 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4779
4780 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4781 visit_cf_list(ctx, &if_stmt->then_list);
4782 if (LLVMGetInsertBlock(ctx->ac.builder))
4783 LLVMBuildBr(ctx->ac.builder, merge_block);
4784
4785 if (!exec_list_is_empty(&if_stmt->else_list)) {
4786 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4787 visit_cf_list(ctx, &if_stmt->else_list);
4788 if (LLVMGetInsertBlock(ctx->ac.builder))
4789 LLVMBuildBr(ctx->ac.builder, merge_block);
4790 }
4791
4792 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4793 }
4794
4795 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4796 {
4797 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4798 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4799 LLVMBasicBlockRef break_parent = ctx->break_block;
4800
4801 ctx->continue_block =
4802 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4803 ctx->break_block =
4804 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4805
4806 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4807 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4808 visit_cf_list(ctx, &loop->body);
4809
4810 if (LLVMGetInsertBlock(ctx->ac.builder))
4811 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4812 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4813
4814 ctx->continue_block = continue_parent;
4815 ctx->break_block = break_parent;
4816 }
4817
4818 static void visit_cf_list(struct ac_nir_context *ctx,
4819 struct exec_list *list)
4820 {
4821 foreach_list_typed(nir_cf_node, node, node, list)
4822 {
4823 switch (node->type) {
4824 case nir_cf_node_block:
4825 visit_block(ctx, nir_cf_node_as_block(node));
4826 break;
4827
4828 case nir_cf_node_if:
4829 visit_if(ctx, nir_cf_node_as_if(node));
4830 break;
4831
4832 case nir_cf_node_loop:
4833 visit_loop(ctx, nir_cf_node_as_loop(node));
4834 break;
4835
4836 default:
4837 assert(0);
4838 }
4839 }
4840 }
4841
4842 static void
4843 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4844 struct nir_variable *variable)
4845 {
4846 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4847 LLVMValueRef t_offset;
4848 LLVMValueRef t_list;
4849 LLVMValueRef input;
4850 LLVMValueRef buffer_index;
4851 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4852 int idx = variable->data.location;
4853 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4854
4855 variable->data.driver_location = idx * 4;
4856
4857 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4858 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4859 ctx->abi.start_instance, "");
4860 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4861 ctx->shader_info->vs.vgpr_comp_cnt);
4862 } else
4863 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4864 ctx->abi.base_vertex, "");
4865
4866 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4867 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4868
4869 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4870
4871 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4872 buffer_index,
4873 LLVMConstInt(ctx->i32, 0, false),
4874 true);
4875
4876 for (unsigned chan = 0; chan < 4; chan++) {
4877 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4878 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4879 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4880 input, llvm_chan, ""));
4881 }
4882 }
4883 }
4884
4885 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4886 unsigned attr,
4887 LLVMValueRef interp_param,
4888 LLVMValueRef prim_mask,
4889 LLVMValueRef result[4])
4890 {
4891 LLVMValueRef attr_number;
4892 unsigned chan;
4893 LLVMValueRef i, j;
4894 bool interp = interp_param != NULL;
4895
4896 attr_number = LLVMConstInt(ctx->i32, attr, false);
4897
4898 /* fs.constant returns the param from the middle vertex, so it's not
4899 * really useful for flat shading. It's meant to be used for custom
4900 * interpolation (but the intrinsic can't fetch from the other two
4901 * vertices).
4902 *
4903 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4904 * to do the right thing. The only reason we use fs.constant is that
4905 * fs.interp cannot be used on integers, because they can be equal
4906 * to NaN.
4907 */
4908 if (interp) {
4909 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4910 LLVMVectorType(ctx->f32, 2), "");
4911
4912 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4913 ctx->i32zero, "");
4914 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4915 ctx->i32one, "");
4916 }
4917
4918 for (chan = 0; chan < 4; chan++) {
4919 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4920
4921 if (interp) {
4922 result[chan] = ac_build_fs_interp(&ctx->ac,
4923 llvm_chan,
4924 attr_number,
4925 prim_mask, i, j);
4926 } else {
4927 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4928 LLVMConstInt(ctx->i32, 2, false),
4929 llvm_chan,
4930 attr_number,
4931 prim_mask);
4932 }
4933 }
4934 }
4935
4936 static void
4937 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4938 struct nir_variable *variable)
4939 {
4940 int idx = variable->data.location;
4941 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4942 LLVMValueRef interp;
4943
4944 variable->data.driver_location = idx * 4;
4945 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4946
4947 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4948 unsigned interp_type;
4949 if (variable->data.sample) {
4950 interp_type = INTERP_SAMPLE;
4951 ctx->shader_info->fs.force_persample = true;
4952 } else if (variable->data.centroid)
4953 interp_type = INTERP_CENTROID;
4954 else
4955 interp_type = INTERP_CENTER;
4956
4957 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4958 } else
4959 interp = NULL;
4960
4961 for (unsigned i = 0; i < attrib_count; ++i)
4962 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4963
4964 }
4965
4966 static void
4967 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4968 struct nir_variable *variable)
4969 {
4970 switch (ctx->stage) {
4971 case MESA_SHADER_VERTEX:
4972 handle_vs_input_decl(ctx, variable);
4973 break;
4974 case MESA_SHADER_FRAGMENT:
4975 handle_fs_input_decl(ctx, variable);
4976 break;
4977 default:
4978 break;
4979 }
4980
4981 }
4982
4983 static void
4984 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4985 struct nir_shader *nir)
4986 {
4987 unsigned index = 0;
4988 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4989 LLVMValueRef interp_param;
4990 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4991
4992 if (!(ctx->input_mask & (1ull << i)))
4993 continue;
4994
4995 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4996 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4997 interp_param = *inputs;
4998 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4999 inputs);
5000
5001 if (!interp_param)
5002 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5003 ++index;
5004 } else if (i == VARYING_SLOT_POS) {
5005 for(int i = 0; i < 3; ++i)
5006 inputs[i] = ctx->frag_pos[i];
5007
5008 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
5009 }
5010 }
5011 ctx->shader_info->fs.num_interp = index;
5012 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5013 ctx->shader_info->fs.has_pcoord = true;
5014 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5015 ctx->shader_info->fs.prim_id_input = true;
5016 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5017 ctx->shader_info->fs.layer_input = true;
5018 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5019 }
5020
5021 static LLVMValueRef
5022 ac_build_alloca(struct ac_llvm_context *ac,
5023 LLVMTypeRef type,
5024 const char *name)
5025 {
5026 LLVMBuilderRef builder = ac->builder;
5027 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5028 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5029 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5030 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5031 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5032 LLVMValueRef res;
5033
5034 if (first_instr) {
5035 LLVMPositionBuilderBefore(first_builder, first_instr);
5036 } else {
5037 LLVMPositionBuilderAtEnd(first_builder, first_block);
5038 }
5039
5040 res = LLVMBuildAlloca(first_builder, type, name);
5041 LLVMBuildStore(builder, LLVMConstNull(type), res);
5042
5043 LLVMDisposeBuilder(first_builder);
5044
5045 return res;
5046 }
5047
5048 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5049 LLVMTypeRef type,
5050 const char *name)
5051 {
5052 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5053 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5054 return ptr;
5055 }
5056
5057 static void
5058 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5059 struct nir_variable *variable)
5060 {
5061 int idx = variable->data.location + variable->data.index;
5062 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5063 uint64_t mask_attribs;
5064
5065 variable->data.driver_location = idx * 4;
5066
5067 /* tess ctrl has it's own load/store paths for outputs */
5068 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5069 return;
5070
5071 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5072 if (ctx->stage == MESA_SHADER_VERTEX ||
5073 ctx->stage == MESA_SHADER_TESS_EVAL ||
5074 ctx->stage == MESA_SHADER_GEOMETRY) {
5075 if (idx == VARYING_SLOT_CLIP_DIST0) {
5076 int length = ctx->num_output_clips + ctx->num_output_culls;
5077 if (ctx->stage == MESA_SHADER_VERTEX) {
5078 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5079 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5080 }
5081 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5082 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5083 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5084 }
5085
5086 if (length > 4)
5087 attrib_count = 2;
5088 else
5089 attrib_count = 1;
5090 mask_attribs = 1ull << idx;
5091 }
5092 }
5093
5094 ctx->output_mask |= mask_attribs;
5095 }
5096
5097 static void
5098 handle_shader_output_decl(struct ac_nir_context *ctx,
5099 struct nir_shader *nir,
5100 struct nir_variable *variable)
5101 {
5102 unsigned output_loc = variable->data.driver_location / 4;
5103 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5104
5105 /* tess ctrl has it's own load/store paths for outputs */
5106 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5107 return;
5108
5109 if (ctx->stage == MESA_SHADER_VERTEX ||
5110 ctx->stage == MESA_SHADER_TESS_EVAL ||
5111 ctx->stage == MESA_SHADER_GEOMETRY) {
5112 int idx = variable->data.location + variable->data.index;
5113 if (idx == VARYING_SLOT_CLIP_DIST0) {
5114 int length = nir->info.clip_distance_array_size +
5115 nir->info.cull_distance_array_size;
5116
5117 if (length > 4)
5118 attrib_count = 2;
5119 else
5120 attrib_count = 1;
5121 }
5122 }
5123
5124 for (unsigned i = 0; i < attrib_count; ++i) {
5125 for (unsigned chan = 0; chan < 4; chan++) {
5126 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5127 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5128 }
5129 }
5130 }
5131
5132 static LLVMTypeRef
5133 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5134 enum glsl_base_type type)
5135 {
5136 switch (type) {
5137 case GLSL_TYPE_INT:
5138 case GLSL_TYPE_UINT:
5139 case GLSL_TYPE_BOOL:
5140 case GLSL_TYPE_SUBROUTINE:
5141 return ctx->i32;
5142 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5143 return ctx->f32;
5144 case GLSL_TYPE_INT64:
5145 case GLSL_TYPE_UINT64:
5146 return ctx->i64;
5147 case GLSL_TYPE_DOUBLE:
5148 return ctx->f64;
5149 default:
5150 unreachable("unknown GLSL type");
5151 }
5152 }
5153
5154 static LLVMTypeRef
5155 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5156 const struct glsl_type *type)
5157 {
5158 if (glsl_type_is_scalar(type)) {
5159 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5160 }
5161
5162 if (glsl_type_is_vector(type)) {
5163 return LLVMVectorType(
5164 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5165 glsl_get_vector_elements(type));
5166 }
5167
5168 if (glsl_type_is_matrix(type)) {
5169 return LLVMArrayType(
5170 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5171 glsl_get_matrix_columns(type));
5172 }
5173
5174 if (glsl_type_is_array(type)) {
5175 return LLVMArrayType(
5176 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5177 glsl_get_length(type));
5178 }
5179
5180 assert(glsl_type_is_struct(type));
5181
5182 LLVMTypeRef member_types[glsl_get_length(type)];
5183
5184 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5185 member_types[i] =
5186 glsl_to_llvm_type(ctx,
5187 glsl_get_struct_field(type, i));
5188 }
5189
5190 return LLVMStructTypeInContext(ctx->context, member_types,
5191 glsl_get_length(type), false);
5192 }
5193
5194 static void
5195 setup_locals(struct ac_nir_context *ctx,
5196 struct nir_function *func)
5197 {
5198 int i, j;
5199 ctx->num_locals = 0;
5200 nir_foreach_variable(variable, &func->impl->locals) {
5201 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5202 variable->data.driver_location = ctx->num_locals * 4;
5203 ctx->num_locals += attrib_count;
5204 }
5205 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5206 if (!ctx->locals)
5207 return;
5208
5209 for (i = 0; i < ctx->num_locals; i++) {
5210 for (j = 0; j < 4; j++) {
5211 ctx->locals[i * 4 + j] =
5212 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5213 }
5214 }
5215 }
5216
5217 static void
5218 setup_shared(struct ac_nir_context *ctx,
5219 struct nir_shader *nir)
5220 {
5221 nir_foreach_variable(variable, &nir->shared) {
5222 LLVMValueRef shared =
5223 LLVMAddGlobalInAddressSpace(
5224 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5225 variable->name ? variable->name : "",
5226 LOCAL_ADDR_SPACE);
5227 _mesa_hash_table_insert(ctx->vars, variable, shared);
5228 }
5229 }
5230
5231 static LLVMValueRef
5232 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5233 {
5234 v = to_float(ctx, v);
5235 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5236 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5237 }
5238
5239
5240 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5241 LLVMValueRef src0, LLVMValueRef src1)
5242 {
5243 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5244 LLVMValueRef comp[2];
5245
5246 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5247 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5248 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5249 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5250 }
5251
5252 /* Initialize arguments for the shader export intrinsic */
5253 static void
5254 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5255 LLVMValueRef *values,
5256 unsigned target,
5257 struct ac_export_args *args)
5258 {
5259 /* Default is 0xf. Adjusted below depending on the format. */
5260 args->enabled_channels = 0xf;
5261
5262 /* Specify whether the EXEC mask represents the valid mask */
5263 args->valid_mask = 0;
5264
5265 /* Specify whether this is the last export */
5266 args->done = 0;
5267
5268 /* Specify the target we are exporting */
5269 args->target = target;
5270
5271 args->compr = false;
5272 args->out[0] = LLVMGetUndef(ctx->f32);
5273 args->out[1] = LLVMGetUndef(ctx->f32);
5274 args->out[2] = LLVMGetUndef(ctx->f32);
5275 args->out[3] = LLVMGetUndef(ctx->f32);
5276
5277 if (!values)
5278 return;
5279
5280 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5281 LLVMValueRef val[4];
5282 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5283 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5284 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5285
5286 switch(col_format) {
5287 case V_028714_SPI_SHADER_ZERO:
5288 args->enabled_channels = 0; /* writemask */
5289 args->target = V_008DFC_SQ_EXP_NULL;
5290 break;
5291
5292 case V_028714_SPI_SHADER_32_R:
5293 args->enabled_channels = 1;
5294 args->out[0] = values[0];
5295 break;
5296
5297 case V_028714_SPI_SHADER_32_GR:
5298 args->enabled_channels = 0x3;
5299 args->out[0] = values[0];
5300 args->out[1] = values[1];
5301 break;
5302
5303 case V_028714_SPI_SHADER_32_AR:
5304 args->enabled_channels = 0x9;
5305 args->out[0] = values[0];
5306 args->out[3] = values[3];
5307 break;
5308
5309 case V_028714_SPI_SHADER_FP16_ABGR:
5310 args->compr = 1;
5311
5312 for (unsigned chan = 0; chan < 2; chan++) {
5313 LLVMValueRef pack_args[2] = {
5314 values[2 * chan],
5315 values[2 * chan + 1]
5316 };
5317 LLVMValueRef packed;
5318
5319 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5320 args->out[chan] = packed;
5321 }
5322 break;
5323
5324 case V_028714_SPI_SHADER_UNORM16_ABGR:
5325 for (unsigned chan = 0; chan < 4; chan++) {
5326 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5327 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5328 LLVMConstReal(ctx->f32, 65535), "");
5329 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5330 LLVMConstReal(ctx->f32, 0.5), "");
5331 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5332 ctx->i32, "");
5333 }
5334
5335 args->compr = 1;
5336 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5337 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5338 break;
5339
5340 case V_028714_SPI_SHADER_SNORM16_ABGR:
5341 for (unsigned chan = 0; chan < 4; chan++) {
5342 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5343 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5344 LLVMConstReal(ctx->f32, 32767), "");
5345
5346 /* If positive, add 0.5, else add -0.5. */
5347 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5348 LLVMBuildSelect(ctx->builder,
5349 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5350 val[chan], ctx->f32zero, ""),
5351 LLVMConstReal(ctx->f32, 0.5),
5352 LLVMConstReal(ctx->f32, -0.5), ""), "");
5353 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5354 }
5355
5356 args->compr = 1;
5357 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5358 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5359 break;
5360
5361 case V_028714_SPI_SHADER_UINT16_ABGR: {
5362 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5363
5364 for (unsigned chan = 0; chan < 4; chan++) {
5365 val[chan] = to_integer(&ctx->ac, values[chan]);
5366 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], max);
5367 }
5368
5369 args->compr = 1;
5370 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5371 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5372 break;
5373 }
5374
5375 case V_028714_SPI_SHADER_SINT16_ABGR: {
5376 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5377 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5378
5379 /* Clamp. */
5380 for (unsigned chan = 0; chan < 4; chan++) {
5381 val[chan] = to_integer(&ctx->ac, values[chan]);
5382 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], max);
5383 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], min);
5384 }
5385
5386 args->compr = 1;
5387 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5388 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5389 break;
5390 }
5391
5392 default:
5393 case V_028714_SPI_SHADER_32_ABGR:
5394 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5395 break;
5396 }
5397 } else
5398 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5399
5400 for (unsigned i = 0; i < 4; ++i)
5401 args->out[i] = to_float(&ctx->ac, args->out[i]);
5402 }
5403
5404 static void
5405 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5406 bool export_prim_id,
5407 struct ac_vs_output_info *outinfo)
5408 {
5409 uint32_t param_count = 0;
5410 unsigned target;
5411 unsigned pos_idx, num_pos_exports = 0;
5412 struct ac_export_args args, pos_args[4] = {};
5413 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5414 int i;
5415
5416 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5417 sizeof(outinfo->vs_output_param_offset));
5418
5419 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5420 LLVMValueRef slots[8];
5421 unsigned j;
5422
5423 if (outinfo->cull_dist_mask)
5424 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5425
5426 i = VARYING_SLOT_CLIP_DIST0;
5427 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5428 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5429 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5430
5431 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5432 slots[i] = LLVMGetUndef(ctx->f32);
5433
5434 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5435 target = V_008DFC_SQ_EXP_POS + 3;
5436 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5437 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5438 &args, sizeof(args));
5439 }
5440
5441 target = V_008DFC_SQ_EXP_POS + 2;
5442 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5443 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5444 &args, sizeof(args));
5445
5446 }
5447
5448 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5449 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5450 for (unsigned j = 0; j < 4; j++)
5451 pos_values[j] = LLVMBuildLoad(ctx->builder,
5452 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5453 }
5454 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5455
5456 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5457 outinfo->writes_pointsize = true;
5458 psize_value = LLVMBuildLoad(ctx->builder,
5459 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5460 }
5461
5462 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5463 outinfo->writes_layer = true;
5464 layer_value = LLVMBuildLoad(ctx->builder,
5465 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5466 }
5467
5468 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5469 outinfo->writes_viewport_index = true;
5470 viewport_index_value = LLVMBuildLoad(ctx->builder,
5471 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5472 }
5473
5474 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5475 (outinfo->writes_layer == true ? 4 : 0) |
5476 (outinfo->writes_viewport_index == true ? 8 : 0));
5477 if (mask) {
5478 pos_args[1].enabled_channels = mask;
5479 pos_args[1].valid_mask = 0;
5480 pos_args[1].done = 0;
5481 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5482 pos_args[1].compr = 0;
5483 pos_args[1].out[0] = ctx->f32zero; /* X */
5484 pos_args[1].out[1] = ctx->f32zero; /* Y */
5485 pos_args[1].out[2] = ctx->f32zero; /* Z */
5486 pos_args[1].out[3] = ctx->f32zero; /* W */
5487
5488 if (outinfo->writes_pointsize == true)
5489 pos_args[1].out[0] = psize_value;
5490 if (outinfo->writes_layer == true)
5491 pos_args[1].out[2] = layer_value;
5492 if (outinfo->writes_viewport_index == true)
5493 pos_args[1].out[3] = viewport_index_value;
5494 }
5495 for (i = 0; i < 4; i++) {
5496 if (pos_args[i].out[0])
5497 num_pos_exports++;
5498 }
5499
5500 pos_idx = 0;
5501 for (i = 0; i < 4; i++) {
5502 if (!pos_args[i].out[0])
5503 continue;
5504
5505 /* Specify the target we are exporting */
5506 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5507 if (pos_idx == num_pos_exports)
5508 pos_args[i].done = 1;
5509 ac_build_export(&ctx->ac, &pos_args[i]);
5510 }
5511
5512 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5513 LLVMValueRef values[4];
5514 if (!(ctx->output_mask & (1ull << i)))
5515 continue;
5516
5517 for (unsigned j = 0; j < 4; j++)
5518 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5519 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5520
5521 if (i == VARYING_SLOT_LAYER) {
5522 target = V_008DFC_SQ_EXP_PARAM + param_count;
5523 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5524 param_count++;
5525 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5526 target = V_008DFC_SQ_EXP_PARAM + param_count;
5527 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5528 param_count++;
5529 } else if (i >= VARYING_SLOT_VAR0) {
5530 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5531 target = V_008DFC_SQ_EXP_PARAM + param_count;
5532 outinfo->vs_output_param_offset[i] = param_count;
5533 param_count++;
5534 } else
5535 continue;
5536
5537 si_llvm_init_export_args(ctx, values, target, &args);
5538
5539 if (target >= V_008DFC_SQ_EXP_POS &&
5540 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5541 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5542 &args, sizeof(args));
5543 } else {
5544 ac_build_export(&ctx->ac, &args);
5545 }
5546 }
5547
5548 if (export_prim_id) {
5549 LLVMValueRef values[4];
5550 target = V_008DFC_SQ_EXP_PARAM + param_count;
5551 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5552 param_count++;
5553
5554 values[0] = ctx->vs_prim_id;
5555 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5556 ctx->shader_info->vs.vgpr_comp_cnt);
5557 for (unsigned j = 1; j < 4; j++)
5558 values[j] = ctx->f32zero;
5559 si_llvm_init_export_args(ctx, values, target, &args);
5560 ac_build_export(&ctx->ac, &args);
5561 outinfo->export_prim_id = true;
5562 }
5563
5564 outinfo->pos_exports = num_pos_exports;
5565 outinfo->param_exports = param_count;
5566 }
5567
5568 static void
5569 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5570 struct ac_es_output_info *outinfo)
5571 {
5572 int j;
5573 uint64_t max_output_written = 0;
5574 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5575 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5576 int param_index;
5577 int length = 4;
5578
5579 if (!(ctx->output_mask & (1ull << i)))
5580 continue;
5581
5582 if (i == VARYING_SLOT_CLIP_DIST0)
5583 length = ctx->num_output_clips + ctx->num_output_culls;
5584
5585 param_index = shader_io_get_unique_index(i);
5586
5587 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5588
5589 for (j = 0; j < length; j++) {
5590 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5591 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5592
5593 ac_build_buffer_store_dword(&ctx->ac,
5594 ctx->esgs_ring,
5595 out_val, 1,
5596 NULL, ctx->es2gs_offset,
5597 (4 * param_index + j) * 4,
5598 1, 1, true, true);
5599 }
5600 }
5601 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5602 }
5603
5604 static void
5605 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5606 {
5607 LLVMValueRef vertex_id = ctx->rel_auto_id;
5608 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5609 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5610 vertex_dw_stride, "");
5611
5612 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5613 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5614 int length = 4;
5615
5616 if (!(ctx->output_mask & (1ull << i)))
5617 continue;
5618
5619 if (i == VARYING_SLOT_CLIP_DIST0)
5620 length = ctx->num_output_clips + ctx->num_output_culls;
5621 int param = shader_io_get_unique_index(i);
5622 mark_tess_output(ctx, false, param);
5623 if (length > 4)
5624 mark_tess_output(ctx, false, param + 1);
5625 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5626 LLVMConstInt(ctx->i32, param * 4, false),
5627 "");
5628 for (unsigned j = 0; j < length; j++) {
5629 lds_store(ctx, dw_addr,
5630 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5631 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5632 }
5633 }
5634 }
5635
5636 struct ac_build_if_state
5637 {
5638 struct nir_to_llvm_context *ctx;
5639 LLVMValueRef condition;
5640 LLVMBasicBlockRef entry_block;
5641 LLVMBasicBlockRef true_block;
5642 LLVMBasicBlockRef false_block;
5643 LLVMBasicBlockRef merge_block;
5644 };
5645
5646 static LLVMBasicBlockRef
5647 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5648 {
5649 LLVMBasicBlockRef current_block;
5650 LLVMBasicBlockRef next_block;
5651 LLVMBasicBlockRef new_block;
5652
5653 /* get current basic block */
5654 current_block = LLVMGetInsertBlock(ctx->builder);
5655
5656 /* chqeck if there's another block after this one */
5657 next_block = LLVMGetNextBasicBlock(current_block);
5658 if (next_block) {
5659 /* insert the new block before the next block */
5660 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5661 }
5662 else {
5663 /* append new block after current block */
5664 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5665 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5666 }
5667 return new_block;
5668 }
5669
5670 static void
5671 ac_nir_build_if(struct ac_build_if_state *ifthen,
5672 struct nir_to_llvm_context *ctx,
5673 LLVMValueRef condition)
5674 {
5675 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5676
5677 memset(ifthen, 0, sizeof *ifthen);
5678 ifthen->ctx = ctx;
5679 ifthen->condition = condition;
5680 ifthen->entry_block = block;
5681
5682 /* create endif/merge basic block for the phi functions */
5683 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5684
5685 /* create/insert true_block before merge_block */
5686 ifthen->true_block =
5687 LLVMInsertBasicBlockInContext(ctx->context,
5688 ifthen->merge_block,
5689 "if-true-block");
5690
5691 /* successive code goes into the true block */
5692 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5693 }
5694
5695 /**
5696 * End a conditional.
5697 */
5698 static void
5699 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5700 {
5701 LLVMBuilderRef builder = ifthen->ctx->builder;
5702
5703 /* Insert branch to the merge block from current block */
5704 LLVMBuildBr(builder, ifthen->merge_block);
5705
5706 /*
5707 * Now patch in the various branch instructions.
5708 */
5709
5710 /* Insert the conditional branch instruction at the end of entry_block */
5711 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5712 if (ifthen->false_block) {
5713 /* we have an else clause */
5714 LLVMBuildCondBr(builder, ifthen->condition,
5715 ifthen->true_block, ifthen->false_block);
5716 }
5717 else {
5718 /* no else clause */
5719 LLVMBuildCondBr(builder, ifthen->condition,
5720 ifthen->true_block, ifthen->merge_block);
5721 }
5722
5723 /* Resume building code at end of the ifthen->merge_block */
5724 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5725 }
5726
5727 static void
5728 write_tess_factors(struct nir_to_llvm_context *ctx)
5729 {
5730 unsigned stride, outer_comps, inner_comps;
5731 struct ac_build_if_state if_ctx, inner_if_ctx;
5732 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5733 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5734 unsigned tess_inner_index, tess_outer_index;
5735 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5736 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5737 int i;
5738 emit_barrier(ctx);
5739
5740 switch (ctx->options->key.tcs.primitive_mode) {
5741 case GL_ISOLINES:
5742 stride = 2;
5743 outer_comps = 2;
5744 inner_comps = 0;
5745 break;
5746 case GL_TRIANGLES:
5747 stride = 4;
5748 outer_comps = 3;
5749 inner_comps = 1;
5750 break;
5751 case GL_QUADS:
5752 stride = 6;
5753 outer_comps = 4;
5754 inner_comps = 2;
5755 break;
5756 default:
5757 return;
5758 }
5759
5760 ac_nir_build_if(&if_ctx, ctx,
5761 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5762 invocation_id, ctx->i32zero, ""));
5763
5764 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5765 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5766
5767 mark_tess_output(ctx, true, tess_inner_index);
5768 mark_tess_output(ctx, true, tess_outer_index);
5769 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5770 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5771 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5772 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5773 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5774
5775 for (i = 0; i < 4; i++) {
5776 inner[i] = LLVMGetUndef(ctx->i32);
5777 outer[i] = LLVMGetUndef(ctx->i32);
5778 }
5779
5780 // LINES reverseal
5781 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5782 outer[0] = out[1] = lds_load(ctx, lds_outer);
5783 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5784 LLVMConstInt(ctx->i32, 1, false), "");
5785 outer[1] = out[0] = lds_load(ctx, lds_outer);
5786 } else {
5787 for (i = 0; i < outer_comps; i++) {
5788 outer[i] = out[i] =
5789 lds_load(ctx, lds_outer);
5790 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5791 LLVMConstInt(ctx->i32, 1, false), "");
5792 }
5793 for (i = 0; i < inner_comps; i++) {
5794 inner[i] = out[outer_comps+i] =
5795 lds_load(ctx, lds_inner);
5796 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5797 LLVMConstInt(ctx->i32, 1, false), "");
5798 }
5799 }
5800
5801 /* Convert the outputs to vectors for stores. */
5802 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5803 vec1 = NULL;
5804
5805 if (stride > 4)
5806 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5807
5808
5809 buffer = ctx->hs_ring_tess_factor;
5810 tf_base = ctx->tess_factor_offset;
5811 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5812 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5813
5814 ac_nir_build_if(&inner_if_ctx, ctx,
5815 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5816 rel_patch_id, ctx->i32zero, ""));
5817
5818 /* Store the dynamic HS control word. */
5819 ac_build_buffer_store_dword(&ctx->ac, buffer,
5820 LLVMConstInt(ctx->i32, 0x80000000, false),
5821 1, ctx->i32zero, tf_base,
5822 0, 1, 0, true, false);
5823 ac_nir_build_endif(&inner_if_ctx);
5824
5825 /* Store the tessellation factors. */
5826 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5827 MIN2(stride, 4), byteoffset, tf_base,
5828 4, 1, 0, true, false);
5829 if (vec1)
5830 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5831 stride - 4, byteoffset, tf_base,
5832 20, 1, 0, true, false);
5833
5834 //TODO store to offchip for TES to read - only if TES reads them
5835 if (1) {
5836 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5837 LLVMValueRef tf_inner_offset;
5838 unsigned param_outer, param_inner;
5839
5840 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5841 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5842 LLVMConstInt(ctx->i32, param_outer, 0));
5843
5844 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5845 util_next_power_of_two(outer_comps));
5846
5847 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5848 outer_comps, tf_outer_offset,
5849 ctx->oc_lds, 0, 1, 0, true, false);
5850 if (inner_comps) {
5851 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5852 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5853 LLVMConstInt(ctx->i32, param_inner, 0));
5854
5855 inner_vec = inner_comps == 1 ? inner[0] :
5856 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5857 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5858 inner_comps, tf_inner_offset,
5859 ctx->oc_lds, 0, 1, 0, true, false);
5860 }
5861 }
5862 ac_nir_build_endif(&if_ctx);
5863 }
5864
5865 static void
5866 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5867 {
5868 write_tess_factors(ctx);
5869 }
5870
5871 static bool
5872 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5873 LLVMValueRef *color, unsigned param, bool is_last,
5874 struct ac_export_args *args)
5875 {
5876 /* Export */
5877 si_llvm_init_export_args(ctx, color, param,
5878 args);
5879
5880 if (is_last) {
5881 args->valid_mask = 1; /* whether the EXEC mask is valid */
5882 args->done = 1; /* DONE bit */
5883 } else if (!args->enabled_channels)
5884 return false; /* unnecessary NULL export */
5885
5886 return true;
5887 }
5888
5889 static void
5890 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5891 LLVMValueRef depth, LLVMValueRef stencil,
5892 LLVMValueRef samplemask)
5893 {
5894 struct ac_export_args args;
5895
5896 args.enabled_channels = 0;
5897 args.valid_mask = 1;
5898 args.done = 1;
5899 args.target = V_008DFC_SQ_EXP_MRTZ;
5900 args.compr = false;
5901
5902 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5903 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5904 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5905 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5906
5907 if (depth) {
5908 args.out[0] = depth;
5909 args.enabled_channels |= 0x1;
5910 }
5911
5912 if (stencil) {
5913 args.out[1] = stencil;
5914 args.enabled_channels |= 0x2;
5915 }
5916
5917 if (samplemask) {
5918 args.out[2] = samplemask;
5919 args.enabled_channels |= 0x4;
5920 }
5921
5922 /* SI (except OLAND and HAINAN) has a bug that it only looks
5923 * at the X writemask component. */
5924 if (ctx->options->chip_class == SI &&
5925 ctx->options->family != CHIP_OLAND &&
5926 ctx->options->family != CHIP_HAINAN)
5927 args.enabled_channels |= 0x1;
5928
5929 ac_build_export(&ctx->ac, &args);
5930 }
5931
5932 static void
5933 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5934 {
5935 unsigned index = 0;
5936 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5937 struct ac_export_args color_args[8];
5938
5939 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5940 LLVMValueRef values[4];
5941
5942 if (!(ctx->output_mask & (1ull << i)))
5943 continue;
5944
5945 if (i == FRAG_RESULT_DEPTH) {
5946 ctx->shader_info->fs.writes_z = true;
5947 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5948 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5949 } else if (i == FRAG_RESULT_STENCIL) {
5950 ctx->shader_info->fs.writes_stencil = true;
5951 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5952 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5953 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5954 ctx->shader_info->fs.writes_sample_mask = true;
5955 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5956 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5957 } else {
5958 bool last = false;
5959 for (unsigned j = 0; j < 4; j++)
5960 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5961 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5962
5963 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5964 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5965
5966 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5967 if (ret)
5968 index++;
5969 }
5970 }
5971
5972 for (unsigned i = 0; i < index; i++)
5973 ac_build_export(&ctx->ac, &color_args[i]);
5974 if (depth || stencil || samplemask)
5975 si_export_mrt_z(ctx, depth, stencil, samplemask);
5976 else if (!index) {
5977 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5978 ac_build_export(&ctx->ac, &color_args[0]);
5979 }
5980
5981 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5982 }
5983
5984 static void
5985 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5986 {
5987 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5988 }
5989
5990 static void
5991 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
5992 LLVMValueRef *addrs)
5993 {
5994 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
5995
5996 switch (ctx->stage) {
5997 case MESA_SHADER_VERTEX:
5998 if (ctx->options->key.vs.as_ls)
5999 handle_ls_outputs_post(ctx);
6000 else if (ctx->options->key.vs.as_es)
6001 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6002 else
6003 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6004 &ctx->shader_info->vs.outinfo);
6005 break;
6006 case MESA_SHADER_FRAGMENT:
6007 handle_fs_outputs_post(ctx);
6008 break;
6009 case MESA_SHADER_GEOMETRY:
6010 emit_gs_epilogue(ctx);
6011 break;
6012 case MESA_SHADER_TESS_CTRL:
6013 handle_tcs_outputs_post(ctx);
6014 break;
6015 case MESA_SHADER_TESS_EVAL:
6016 if (ctx->options->key.tes.as_es)
6017 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6018 else
6019 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6020 &ctx->shader_info->tes.outinfo);
6021 break;
6022 default:
6023 break;
6024 }
6025 }
6026
6027 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6028 {
6029 LLVMPassManagerRef passmgr;
6030 /* Create the pass manager */
6031 passmgr = LLVMCreateFunctionPassManagerForModule(
6032 ctx->module);
6033
6034 /* This pass should eliminate all the load and store instructions */
6035 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6036
6037 /* Add some optimization passes */
6038 LLVMAddScalarReplAggregatesPass(passmgr);
6039 LLVMAddLICMPass(passmgr);
6040 LLVMAddAggressiveDCEPass(passmgr);
6041 LLVMAddCFGSimplificationPass(passmgr);
6042 LLVMAddInstructionCombiningPass(passmgr);
6043
6044 /* Run the pass */
6045 LLVMInitializeFunctionPassManager(passmgr);
6046 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6047 LLVMFinalizeFunctionPassManager(passmgr);
6048
6049 LLVMDisposeBuilder(ctx->builder);
6050 LLVMDisposePassManager(passmgr);
6051 }
6052
6053 static void
6054 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6055 {
6056 struct ac_vs_output_info *outinfo;
6057
6058 switch (ctx->stage) {
6059 case MESA_SHADER_FRAGMENT:
6060 case MESA_SHADER_COMPUTE:
6061 case MESA_SHADER_TESS_CTRL:
6062 case MESA_SHADER_GEOMETRY:
6063 return;
6064 case MESA_SHADER_VERTEX:
6065 if (ctx->options->key.vs.as_ls ||
6066 ctx->options->key.vs.as_es)
6067 return;
6068 outinfo = &ctx->shader_info->vs.outinfo;
6069 break;
6070 case MESA_SHADER_TESS_EVAL:
6071 if (ctx->options->key.vs.as_es)
6072 return;
6073 outinfo = &ctx->shader_info->tes.outinfo;
6074 break;
6075 default:
6076 unreachable("Unhandled shader type");
6077 }
6078
6079 ac_optimize_vs_outputs(&ctx->ac,
6080 ctx->main_function,
6081 outinfo->vs_output_param_offset,
6082 VARYING_SLOT_MAX,
6083 &outinfo->param_exports);
6084 }
6085
6086 static void
6087 ac_setup_rings(struct nir_to_llvm_context *ctx)
6088 {
6089 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6090 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6091 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6092 }
6093
6094 if (ctx->is_gs_copy_shader) {
6095 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6096 }
6097 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6098 LLVMValueRef tmp;
6099 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6100 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6101
6102 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6103
6104 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6105 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6106 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6107 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6108 }
6109
6110 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6111 ctx->stage == MESA_SHADER_TESS_EVAL) {
6112 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6113 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6114 }
6115 }
6116
6117 static unsigned
6118 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6119 const struct nir_shader *nir)
6120 {
6121 switch (nir->stage) {
6122 case MESA_SHADER_TESS_CTRL:
6123 return chip_class >= CIK ? 128 : 64;
6124 case MESA_SHADER_GEOMETRY:
6125 return 64;
6126 case MESA_SHADER_COMPUTE:
6127 break;
6128 default:
6129 return 0;
6130 }
6131
6132 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6133 nir->info.cs.local_size[1] *
6134 nir->info.cs.local_size[2];
6135 return max_workgroup_size;
6136 }
6137
6138 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6139 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6140 {
6141 struct ac_nir_context ctx = {};
6142 struct nir_function *func;
6143
6144 ctx.ac = *ac;
6145 ctx.abi = abi;
6146
6147 ctx.nctx = nctx;
6148 if (nctx)
6149 nctx->nir = &ctx;
6150
6151 ctx.stage = nir->stage;
6152
6153 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6154
6155 nir_foreach_variable(variable, &nir->outputs)
6156 handle_shader_output_decl(&ctx, nir, variable);
6157
6158 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6159 _mesa_key_pointer_equal);
6160 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6161 _mesa_key_pointer_equal);
6162 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6163 _mesa_key_pointer_equal);
6164
6165 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6166
6167 setup_locals(&ctx, func);
6168
6169 if (nir->stage == MESA_SHADER_COMPUTE)
6170 setup_shared(&ctx, nir);
6171
6172 visit_cf_list(&ctx, &func->impl->body);
6173 phi_post_pass(&ctx);
6174
6175 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6176 ctx.outputs);
6177
6178 free(ctx.locals);
6179 ralloc_free(ctx.defs);
6180 ralloc_free(ctx.phis);
6181 ralloc_free(ctx.vars);
6182
6183 if (nctx)
6184 nctx->nir = NULL;
6185 }
6186
6187 static
6188 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6189 struct nir_shader *nir,
6190 struct ac_shader_variant_info *shader_info,
6191 const struct ac_nir_compiler_options *options)
6192 {
6193 struct nir_to_llvm_context ctx = {0};
6194 unsigned i;
6195 ctx.options = options;
6196 ctx.shader_info = shader_info;
6197 ctx.context = LLVMContextCreate();
6198 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6199
6200 ac_llvm_context_init(&ctx.ac, ctx.context);
6201 ctx.ac.module = ctx.module;
6202
6203 memset(shader_info, 0, sizeof(*shader_info));
6204
6205 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6206
6207 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6208
6209 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6210 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6211 LLVMSetDataLayout(ctx.module, data_layout_str);
6212 LLVMDisposeTargetData(data_layout);
6213 LLVMDisposeMessage(data_layout_str);
6214
6215 setup_types(&ctx);
6216
6217 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6218 ctx.ac.builder = ctx.builder;
6219 ctx.stage = nir->stage;
6220 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6221
6222 for (i = 0; i < AC_UD_MAX_SETS; i++)
6223 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6224 for (i = 0; i < AC_UD_MAX_UD; i++)
6225 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6226
6227 create_function(&ctx);
6228
6229 if (nir->stage == MESA_SHADER_GEOMETRY) {
6230 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6231
6232 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6233 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6234 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6235 } else if (nir->stage == MESA_SHADER_VERTEX) {
6236 if (shader_info->info.vs.needs_instance_id) {
6237 ctx.shader_info->vs.vgpr_comp_cnt =
6238 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6239 }
6240 } else if (nir->stage == MESA_SHADER_FRAGMENT) {
6241 shader_info->fs.can_discard = nir->info.fs.uses_discard;
6242 }
6243
6244 ac_setup_rings(&ctx);
6245
6246 ctx.num_output_clips = nir->info.clip_distance_array_size;
6247 ctx.num_output_culls = nir->info.cull_distance_array_size;
6248
6249 nir_foreach_variable(variable, &nir->inputs)
6250 handle_shader_input_decl(&ctx, variable);
6251
6252 if (nir->stage == MESA_SHADER_FRAGMENT)
6253 handle_fs_inputs_pre(&ctx, nir);
6254
6255 ctx.abi.chip_class = options->chip_class;
6256 ctx.abi.inputs = &ctx.inputs[0];
6257 ctx.abi.emit_outputs = handle_shader_outputs_post;
6258 ctx.abi.load_ssbo = radv_load_ssbo;
6259 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6260
6261 nir_foreach_variable(variable, &nir->outputs)
6262 scan_shader_output_decl(&ctx, variable);
6263
6264 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6265
6266 LLVMBuildRetVoid(ctx.builder);
6267
6268 ac_llvm_finalize_module(&ctx);
6269
6270 ac_nir_eliminate_const_vs_outputs(&ctx);
6271
6272 if (nir->stage == MESA_SHADER_GEOMETRY) {
6273 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6274 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6275 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6276 nir->info.gs.vertices_out;
6277 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6278 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6279 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6280 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6281 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6282 }
6283
6284 return ctx.module;
6285 }
6286
6287 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6288 {
6289 unsigned *retval = (unsigned *)context;
6290 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6291 char *description = LLVMGetDiagInfoDescription(di);
6292
6293 if (severity == LLVMDSError) {
6294 *retval = 1;
6295 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6296 description);
6297 }
6298
6299 LLVMDisposeMessage(description);
6300 }
6301
6302 static unsigned ac_llvm_compile(LLVMModuleRef M,
6303 struct ac_shader_binary *binary,
6304 LLVMTargetMachineRef tm)
6305 {
6306 unsigned retval = 0;
6307 char *err;
6308 LLVMContextRef llvm_ctx;
6309 LLVMMemoryBufferRef out_buffer;
6310 unsigned buffer_size;
6311 const char *buffer_data;
6312 LLVMBool mem_err;
6313
6314 /* Setup Diagnostic Handler*/
6315 llvm_ctx = LLVMGetModuleContext(M);
6316
6317 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6318 &retval);
6319
6320 /* Compile IR*/
6321 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6322 &err, &out_buffer);
6323
6324 /* Process Errors/Warnings */
6325 if (mem_err) {
6326 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6327 free(err);
6328 retval = 1;
6329 goto out;
6330 }
6331
6332 /* Extract Shader Code*/
6333 buffer_size = LLVMGetBufferSize(out_buffer);
6334 buffer_data = LLVMGetBufferStart(out_buffer);
6335
6336 ac_elf_read(buffer_data, buffer_size, binary);
6337
6338 /* Clean up */
6339 LLVMDisposeMemoryBuffer(out_buffer);
6340
6341 out:
6342 return retval;
6343 }
6344
6345 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6346 LLVMModuleRef llvm_module,
6347 struct ac_shader_binary *binary,
6348 struct ac_shader_config *config,
6349 struct ac_shader_variant_info *shader_info,
6350 gl_shader_stage stage,
6351 bool dump_shader, bool supports_spill)
6352 {
6353 if (dump_shader)
6354 ac_dump_module(llvm_module);
6355
6356 memset(binary, 0, sizeof(*binary));
6357 int v = ac_llvm_compile(llvm_module, binary, tm);
6358 if (v) {
6359 fprintf(stderr, "compile failed\n");
6360 }
6361
6362 if (dump_shader)
6363 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6364
6365 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6366
6367 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6368 LLVMDisposeModule(llvm_module);
6369 LLVMContextDispose(ctx);
6370
6371 if (stage == MESA_SHADER_FRAGMENT) {
6372 shader_info->num_input_vgprs = 0;
6373 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6374 shader_info->num_input_vgprs += 2;
6375 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6376 shader_info->num_input_vgprs += 2;
6377 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6378 shader_info->num_input_vgprs += 2;
6379 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6380 shader_info->num_input_vgprs += 3;
6381 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6382 shader_info->num_input_vgprs += 2;
6383 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6384 shader_info->num_input_vgprs += 2;
6385 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6386 shader_info->num_input_vgprs += 2;
6387 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6388 shader_info->num_input_vgprs += 1;
6389 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6390 shader_info->num_input_vgprs += 1;
6391 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6392 shader_info->num_input_vgprs += 1;
6393 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6394 shader_info->num_input_vgprs += 1;
6395 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6396 shader_info->num_input_vgprs += 1;
6397 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6398 shader_info->num_input_vgprs += 1;
6399 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6400 shader_info->num_input_vgprs += 1;
6401 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6402 shader_info->num_input_vgprs += 1;
6403 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6404 shader_info->num_input_vgprs += 1;
6405 }
6406 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6407
6408 /* +3 for scratch wave offset and VCC */
6409 config->num_sgprs = MAX2(config->num_sgprs,
6410 shader_info->num_input_sgprs + 3);
6411 }
6412
6413 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6414 struct ac_shader_binary *binary,
6415 struct ac_shader_config *config,
6416 struct ac_shader_variant_info *shader_info,
6417 struct nir_shader *nir,
6418 const struct ac_nir_compiler_options *options,
6419 bool dump_shader)
6420 {
6421
6422 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6423 options);
6424
6425 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6426 switch (nir->stage) {
6427 case MESA_SHADER_COMPUTE:
6428 for (int i = 0; i < 3; ++i)
6429 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6430 break;
6431 case MESA_SHADER_FRAGMENT:
6432 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6433 break;
6434 case MESA_SHADER_GEOMETRY:
6435 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6436 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6437 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6438 shader_info->gs.invocations = nir->info.gs.invocations;
6439 break;
6440 case MESA_SHADER_TESS_EVAL:
6441 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6442 shader_info->tes.spacing = nir->info.tess.spacing;
6443 shader_info->tes.ccw = nir->info.tess.ccw;
6444 shader_info->tes.point_mode = nir->info.tess.point_mode;
6445 shader_info->tes.as_es = options->key.tes.as_es;
6446 break;
6447 case MESA_SHADER_TESS_CTRL:
6448 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6449 break;
6450 case MESA_SHADER_VERTEX:
6451 shader_info->vs.as_es = options->key.vs.as_es;
6452 shader_info->vs.as_ls = options->key.vs.as_ls;
6453 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6454 if (options->key.vs.as_ls)
6455 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6456 break;
6457 default:
6458 break;
6459 }
6460 }
6461
6462 static void
6463 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6464 {
6465 LLVMValueRef args[9];
6466 args[0] = ctx->gsvs_ring;
6467 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6468 args[3] = ctx->i32zero;
6469 args[4] = ctx->i32one; /* OFFEN */
6470 args[5] = ctx->i32zero; /* IDXEN */
6471 args[6] = ctx->i32one; /* GLC */
6472 args[7] = ctx->i32one; /* SLC */
6473 args[8] = ctx->i32zero; /* TFE */
6474
6475 int idx = 0;
6476
6477 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6478 int length = 4;
6479 int slot = idx;
6480 int slot_inc = 1;
6481 if (!(ctx->output_mask & (1ull << i)))
6482 continue;
6483
6484 if (i == VARYING_SLOT_CLIP_DIST0) {
6485 /* unpack clip and cull from a single set of slots */
6486 length = ctx->num_output_clips + ctx->num_output_culls;
6487 if (length > 4)
6488 slot_inc = 2;
6489 }
6490
6491 for (unsigned j = 0; j < length; j++) {
6492 LLVMValueRef value;
6493 args[2] = LLVMConstInt(ctx->i32,
6494 (slot * 4 + j) *
6495 ctx->gs_max_out_vertices * 16 * 4, false);
6496
6497 value = ac_build_intrinsic(&ctx->ac,
6498 "llvm.SI.buffer.load.dword.i32.i32",
6499 ctx->i32, args, 9,
6500 AC_FUNC_ATTR_READONLY |
6501 AC_FUNC_ATTR_LEGACY);
6502
6503 LLVMBuildStore(ctx->builder,
6504 to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6505 }
6506 idx += slot_inc;
6507 }
6508 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6509 }
6510
6511 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6512 struct nir_shader *geom_shader,
6513 struct ac_shader_binary *binary,
6514 struct ac_shader_config *config,
6515 struct ac_shader_variant_info *shader_info,
6516 const struct ac_nir_compiler_options *options,
6517 bool dump_shader)
6518 {
6519 struct nir_to_llvm_context ctx = {0};
6520 ctx.context = LLVMContextCreate();
6521 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6522 ctx.options = options;
6523 ctx.shader_info = shader_info;
6524
6525 ac_llvm_context_init(&ctx.ac, ctx.context);
6526 ctx.ac.module = ctx.module;
6527
6528 ctx.is_gs_copy_shader = true;
6529 LLVMSetTarget(ctx.module, "amdgcn--");
6530 setup_types(&ctx);
6531
6532 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6533 ctx.ac.builder = ctx.builder;
6534 ctx.stage = MESA_SHADER_VERTEX;
6535
6536 create_function(&ctx);
6537
6538 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6539 ac_setup_rings(&ctx);
6540
6541 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6542 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6543
6544 struct ac_nir_context nir_ctx = {};
6545 nir_ctx.ac = ctx.ac;
6546 nir_ctx.abi = &ctx.abi;
6547
6548 nir_ctx.nctx = &ctx;
6549 ctx.nir = &nir_ctx;
6550
6551 nir_foreach_variable(variable, &geom_shader->outputs) {
6552 scan_shader_output_decl(&ctx, variable);
6553 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6554 }
6555
6556 ac_gs_copy_shader_emit(&ctx);
6557
6558 ctx.nir = NULL;
6559
6560 LLVMBuildRetVoid(ctx.builder);
6561
6562 ac_llvm_finalize_module(&ctx);
6563
6564 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6565 MESA_SHADER_VERTEX,
6566 dump_shader, options->supports_spill);
6567 }