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ac: replace llvm.AMDGPU.kilp by llvm.amdgcn.kill with LLVM 6
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 gl_shader_stage stage;
135
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137
138 uint64_t input_mask;
139 uint64_t output_mask;
140 uint8_t num_output_clips;
141 uint8_t num_output_culls;
142
143 bool is_gs_copy_shader;
144 LLVMValueRef gs_next_vertex;
145 unsigned gs_max_out_vertices;
146
147 unsigned tes_primitive_mode;
148 uint64_t tess_outputs_written;
149 uint64_t tess_patch_outputs_written;
150
151 uint32_t tcs_patch_outputs_read;
152 uint64_t tcs_outputs_read;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMTypeRef
163 nir2llvmtype(struct ac_nir_context *ctx,
164 const struct glsl_type *type)
165 {
166 switch (glsl_get_base_type(glsl_without_array(type))) {
167 case GLSL_TYPE_UINT:
168 case GLSL_TYPE_INT:
169 return ctx->ac.i32;
170 case GLSL_TYPE_UINT64:
171 case GLSL_TYPE_INT64:
172 return ctx->ac.i64;
173 case GLSL_TYPE_DOUBLE:
174 return ctx->ac.f64;
175 case GLSL_TYPE_FLOAT:
176 return ctx->ac.f32;
177 default:
178 assert(!"Unsupported type in nir2llvmtype()");
179 break;
180 }
181 return 0;
182 }
183
184 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
185 const nir_deref_var *deref,
186 enum ac_descriptor_type desc_type,
187 const nir_tex_instr *instr,
188 bool image, bool write);
189
190 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
191 {
192 return (index * 4) + chan;
193 }
194
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
196 {
197 /* handle patch indices separate */
198 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
199 return 0;
200 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
201 return 1;
202 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
203 return 2 + (slot - VARYING_SLOT_PATCH0);
204
205 if (slot == VARYING_SLOT_POS)
206 return 0;
207 if (slot == VARYING_SLOT_PSIZ)
208 return 1;
209 if (slot == VARYING_SLOT_CLIP_DIST0)
210 return 2;
211 /* 3 is reserved for clip dist as well */
212 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
213 return 4 + (slot - VARYING_SLOT_VAR0);
214 unreachable("illegal slot in get unique index\n");
215 }
216
217 static void set_llvm_calling_convention(LLVMValueRef func,
218 gl_shader_stage stage)
219 {
220 enum radeon_llvm_calling_convention calling_conv;
221
222 switch (stage) {
223 case MESA_SHADER_VERTEX:
224 case MESA_SHADER_TESS_EVAL:
225 calling_conv = RADEON_LLVM_AMDGPU_VS;
226 break;
227 case MESA_SHADER_GEOMETRY:
228 calling_conv = RADEON_LLVM_AMDGPU_GS;
229 break;
230 case MESA_SHADER_TESS_CTRL:
231 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t sgpr_count;
253 uint8_t num_sgprs_used;
254 uint8_t num_vgprs_used;
255 };
256
257 enum ac_arg_regfile {
258 ARG_SGPR,
259 ARG_VGPR,
260 };
261
262 static void
263 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
264 LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271
272 if (regfile == ARG_SGPR) {
273 info->num_sgprs_used += ac_get_type_size(type) / 4;
274 info->sgpr_count++;
275 } else {
276 assert(regfile == ARG_VGPR);
277 info->num_vgprs_used += ac_get_type_size(type) / 4;
278 }
279 }
280
281 static inline void
282 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 info->array_params_mask |= (1 << info->count);
285 add_arg(info, ARG_SGPR, type, param_ptr);
286 }
287
288 static void assign_arguments(LLVMValueRef main_function,
289 struct arg_info *info)
290 {
291 unsigned i;
292 for (i = 0; i < info->count; i++) {
293 if (info->assign[i])
294 *info->assign[i] = LLVMGetParam(main_function, i);
295 }
296 }
297
298 static LLVMValueRef
299 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
300 LLVMBuilderRef builder, LLVMTypeRef *return_types,
301 unsigned num_return_elems,
302 struct arg_info *args,
303 unsigned max_workgroup_size,
304 bool unsafe_math)
305 {
306 LLVMTypeRef main_function_type, ret_type;
307 LLVMBasicBlockRef main_function_body;
308
309 if (num_return_elems)
310 ret_type = LLVMStructTypeInContext(ctx, return_types,
311 num_return_elems, true);
312 else
313 ret_type = LLVMVoidTypeInContext(ctx);
314
315 /* Setup the function */
316 main_function_type =
317 LLVMFunctionType(ret_type, args->types, args->count, 0);
318 LLVMValueRef main_function =
319 LLVMAddFunction(module, "main", main_function_type);
320 main_function_body =
321 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
322 LLVMPositionBuilderAtEnd(builder, main_function_body);
323
324 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
325 for (unsigned i = 0; i < args->sgpr_count; ++i) {
326 if (args->array_params_mask & (1 << i)) {
327 LLVMValueRef P = LLVMGetParam(main_function, i);
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
329 ac_add_attr_dereferenceable(P, UINT64_MAX);
330 }
331 else {
332 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
333 }
334 }
335
336 if (max_workgroup_size) {
337 ac_llvm_add_target_dep_function_attr(main_function,
338 "amdgpu-max-work-group-size",
339 max_workgroup_size);
340 }
341 if (unsafe_math) {
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function,
344 "less-precise-fpmad",
345 "true");
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "no-infs-fp-math",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-nans-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "unsafe-fp-math",
354 "true");
355 }
356 return main_function;
357 }
358
359 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
360 {
361 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
362 CONST_ADDR_SPACE);
363 }
364
365 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
401 {
402 switch (ctx->stage) {
403 case MESA_SHADER_TESS_CTRL:
404 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
405 case MESA_SHADER_TESS_EVAL:
406 return ctx->tes_rel_patch_id;
407 break;
408 default:
409 unreachable("Illegal stage");
410 }
411 }
412
413 /* Tessellation shaders pass outputs to the next shader using LDS.
414 *
415 * LS outputs = TCS inputs
416 * TCS outputs = TES inputs
417 *
418 * The LDS layout is:
419 * - TCS inputs for patch 0
420 * - TCS inputs for patch 1
421 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
422 * - ...
423 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
424 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
425 * - TCS outputs for patch 1
426 * - Per-patch TCS outputs for patch 1
427 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
428 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
429 * - ...
430 *
431 * All three shaders VS(LS), TCS, TES share the same LDS space.
432 */
433 static LLVMValueRef
434 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
435 {
436 if (ctx->stage == MESA_SHADER_VERTEX)
437 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
438 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
439 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
440 else {
441 assert(0);
442 return NULL;
443 }
444 }
445
446 static LLVMValueRef
447 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
448 {
449 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
450 }
451
452 static LLVMValueRef
453 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
454 {
455 return LLVMBuildMul(ctx->builder,
456 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
457 LLVMConstInt(ctx->ac.i32, 4, false), "");
458 }
459
460 static LLVMValueRef
461 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
462 {
463 return LLVMBuildMul(ctx->builder,
464 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
465 LLVMConstInt(ctx->ac.i32, 4, false), "");
466 }
467
468 static LLVMValueRef
469 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
470 {
471 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
472 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
473
474 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
475 }
476
477 static LLVMValueRef
478 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
479 {
480 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
481 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
482 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
483
484 return LLVMBuildAdd(ctx->builder, patch0_offset,
485 LLVMBuildMul(ctx->builder, patch_stride,
486 rel_patch_id, ""),
487 "");
488 }
489
490 static LLVMValueRef
491 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch0_patch_data_offset =
494 get_tcs_out_patch0_patch_data_offset(ctx);
495 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
496 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
497
498 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
499 LLVMBuildMul(ctx->builder, patch_stride,
500 rel_patch_id, ""),
501 "");
502 }
503
504 static void
505 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
506 uint32_t indirect_offset)
507 {
508 ud_info->sgpr_idx = *sgpr_idx;
509 ud_info->num_sgprs = num_sgprs;
510 ud_info->indirect = indirect_offset > 0;
511 ud_info->indirect_offset = indirect_offset;
512 *sgpr_idx += num_sgprs;
513 }
514
515 static void
516 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
517 uint8_t num_sgprs)
518 {
519 struct ac_userdata_info *ud_info =
520 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
521 assert(ud_info);
522
523 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
524 }
525
526 static void
527 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
528 uint32_t indirect_offset)
529 {
530 struct ac_userdata_info *ud_info =
531 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
532 assert(ud_info);
533
534 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
535 }
536
537 struct user_sgpr_info {
538 bool need_ring_offsets;
539 uint8_t sgpr_count;
540 bool indirect_all_descriptor_sets;
541 };
542
543 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
544 gl_shader_stage stage,
545 struct user_sgpr_info *user_sgpr_info)
546 {
547 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
548
549 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
550 if (stage == MESA_SHADER_GEOMETRY ||
551 stage == MESA_SHADER_VERTEX ||
552 stage == MESA_SHADER_TESS_CTRL ||
553 stage == MESA_SHADER_TESS_EVAL ||
554 ctx->is_gs_copy_shader)
555 user_sgpr_info->need_ring_offsets = true;
556
557 if (stage == MESA_SHADER_FRAGMENT &&
558 ctx->shader_info->info.ps.needs_sample_positions)
559 user_sgpr_info->need_ring_offsets = true;
560
561 /* 2 user sgprs will nearly always be allocated for scratch/rings */
562 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
563 user_sgpr_info->sgpr_count += 2;
564 }
565
566 /* FIXME: fix the number of user sgprs for merged shaders on GFX9 */
567 switch (stage) {
568 case MESA_SHADER_COMPUTE:
569 if (ctx->shader_info->info.cs.uses_grid_size)
570 user_sgpr_info->sgpr_count += 3;
571 break;
572 case MESA_SHADER_FRAGMENT:
573 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
574 break;
575 case MESA_SHADER_VERTEX:
576 if (!ctx->is_gs_copy_shader) {
577 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
578 if (ctx->shader_info->info.vs.needs_draw_id) {
579 user_sgpr_info->sgpr_count += 3;
580 } else {
581 user_sgpr_info->sgpr_count += 2;
582 }
583 }
584 if (ctx->options->key.vs.as_ls)
585 user_sgpr_info->sgpr_count++;
586 break;
587 case MESA_SHADER_TESS_CTRL:
588 user_sgpr_info->sgpr_count += 4;
589 break;
590 case MESA_SHADER_TESS_EVAL:
591 user_sgpr_info->sgpr_count += 1;
592 break;
593 case MESA_SHADER_GEOMETRY:
594 user_sgpr_info->sgpr_count += 2;
595 break;
596 default:
597 break;
598 }
599
600 if (ctx->shader_info->info.loads_push_constants)
601 user_sgpr_info->sgpr_count += 2;
602
603 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
604 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
605
606 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
607 user_sgpr_info->sgpr_count += 2;
608 user_sgpr_info->indirect_all_descriptor_sets = true;
609 } else {
610 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
611 }
612 }
613
614 static void
615 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
616 gl_shader_stage stage,
617 bool has_previous_stage,
618 gl_shader_stage previous_stage,
619 const struct user_sgpr_info *user_sgpr_info,
620 struct arg_info *args,
621 LLVMValueRef *desc_sets)
622 {
623 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
624 unsigned num_sets = ctx->options->layout ?
625 ctx->options->layout->num_sets : 0;
626 unsigned stage_mask = 1 << stage;
627
628 if (has_previous_stage)
629 stage_mask |= 1 << previous_stage;
630
631 /* 1 for each descriptor set */
632 if (!user_sgpr_info->indirect_all_descriptor_sets) {
633 for (unsigned i = 0; i < num_sets; ++i) {
634 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
635 add_array_arg(args, type,
636 &ctx->descriptor_sets[i]);
637 }
638 }
639 } else {
640 add_array_arg(args, const_array(type, 32), desc_sets);
641 }
642
643 if (ctx->shader_info->info.loads_push_constants) {
644 /* 1 for push constants and dynamic descriptors */
645 add_array_arg(args, type, &ctx->push_constants);
646 }
647 }
648
649 static void
650 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
651 gl_shader_stage stage,
652 bool has_previous_stage,
653 gl_shader_stage previous_stage,
654 struct arg_info *args)
655 {
656 if (!ctx->is_gs_copy_shader &&
657 (stage == MESA_SHADER_VERTEX ||
658 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
659 if (ctx->shader_info->info.vs.has_vertex_buffers) {
660 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
661 &ctx->vertex_buffers);
662 }
663 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
664 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
665 if (ctx->shader_info->info.vs.needs_draw_id) {
666 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
667 }
668 }
669 }
670
671 static void
672 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
673 {
674 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
675 if (!ctx->is_gs_copy_shader) {
676 if (ctx->options->key.vs.as_ls) {
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
678 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
679 } else {
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
681 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
682 }
683 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
684 }
685 }
686
687 static void
688 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
689 {
690 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
691 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
692 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
693 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
694 }
695
696 static void
697 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
698 bool has_previous_stage, gl_shader_stage previous_stage,
699 const struct user_sgpr_info *user_sgpr_info,
700 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
701 {
702 unsigned num_sets = ctx->options->layout ?
703 ctx->options->layout->num_sets : 0;
704 unsigned stage_mask = 1 << stage;
705
706 if (has_previous_stage)
707 stage_mask |= 1 << previous_stage;
708
709 if (!user_sgpr_info->indirect_all_descriptor_sets) {
710 for (unsigned i = 0; i < num_sets; ++i) {
711 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
712 set_loc_desc(ctx, i, user_sgpr_idx, 0);
713 } else
714 ctx->descriptor_sets[i] = NULL;
715 }
716 } else {
717 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
718 user_sgpr_idx, 2);
719
720 for (unsigned i = 0; i < num_sets; ++i) {
721 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
722 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
723 ctx->descriptor_sets[i] =
724 ac_build_load_to_sgpr(&ctx->ac,
725 desc_sets,
726 LLVMConstInt(ctx->ac.i32, i, false));
727
728 } else
729 ctx->descriptor_sets[i] = NULL;
730 }
731 ctx->shader_info->need_indirect_descriptor_sets = true;
732 }
733
734 if (ctx->shader_info->info.loads_push_constants) {
735 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
736 }
737 }
738
739 static void
740 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
741 gl_shader_stage stage, bool has_previous_stage,
742 gl_shader_stage previous_stage,
743 uint8_t *user_sgpr_idx)
744 {
745 if (!ctx->is_gs_copy_shader &&
746 (stage == MESA_SHADER_VERTEX ||
747 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
748 if (ctx->shader_info->info.vs.has_vertex_buffers) {
749 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
750 user_sgpr_idx, 2);
751 }
752
753 unsigned vs_num = 2;
754 if (ctx->shader_info->info.vs.needs_draw_id)
755 vs_num++;
756
757 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
758 user_sgpr_idx, vs_num);
759 }
760 }
761
762 static void create_function(struct nir_to_llvm_context *ctx,
763 gl_shader_stage stage,
764 bool has_previous_stage,
765 gl_shader_stage previous_stage)
766 {
767 uint8_t user_sgpr_idx;
768 struct user_sgpr_info user_sgpr_info;
769 struct arg_info args = {};
770 LLVMValueRef desc_sets;
771
772 allocate_user_sgprs(ctx, stage, &user_sgpr_info);
773
774 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
775 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
776 &ctx->ring_offsets);
777 }
778
779 switch (stage) {
780 case MESA_SHADER_COMPUTE:
781 declare_global_input_sgprs(ctx, stage, has_previous_stage,
782 previous_stage, &user_sgpr_info,
783 &args, &desc_sets);
784
785 if (ctx->shader_info->info.cs.uses_grid_size) {
786 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
787 &ctx->num_work_groups);
788 }
789
790 for (int i = 0; i < 3; i++) {
791 ctx->workgroup_ids[i] = NULL;
792 if (ctx->shader_info->info.cs.uses_block_id[i]) {
793 add_arg(&args, ARG_SGPR, ctx->ac.i32,
794 &ctx->workgroup_ids[i]);
795 }
796 }
797
798 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
799 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
800 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
801 &ctx->local_invocation_ids);
802 break;
803 case MESA_SHADER_VERTEX:
804 declare_global_input_sgprs(ctx, stage, has_previous_stage,
805 previous_stage, &user_sgpr_info,
806 &args, &desc_sets);
807 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
808 previous_stage, &args);
809
810 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
811 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
812 if (ctx->options->key.vs.as_es)
813 add_arg(&args, ARG_SGPR, ctx->ac.i32,
814 &ctx->es2gs_offset);
815 else if (ctx->options->key.vs.as_ls)
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->ls_out_layout);
818
819 declare_vs_input_vgprs(ctx, &args);
820 break;
821 case MESA_SHADER_TESS_CTRL:
822 if (has_previous_stage) {
823 // First 6 system regs
824 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
825 add_arg(&args, ARG_SGPR, ctx->ac.i32,
826 &ctx->merged_wave_info);
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->tess_factor_offset);
829
830 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
831 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
832 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
833
834 declare_global_input_sgprs(ctx, stage,
835 has_previous_stage,
836 previous_stage,
837 &user_sgpr_info, &args,
838 &desc_sets);
839 declare_vs_specific_input_sgprs(ctx, stage,
840 has_previous_stage,
841 previous_stage, &args);
842
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->ls_out_layout);
845
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_offchip_layout);
848 add_arg(&args, ARG_SGPR, ctx->ac.i32,
849 &ctx->tcs_out_offsets);
850 add_arg(&args, ARG_SGPR, ctx->ac.i32,
851 &ctx->tcs_out_layout);
852 add_arg(&args, ARG_SGPR, ctx->ac.i32,
853 &ctx->tcs_in_layout);
854 if (ctx->shader_info->info.needs_multiview_view_index)
855 add_arg(&args, ARG_SGPR, ctx->ac.i32,
856 &ctx->view_index);
857
858 add_arg(&args, ARG_VGPR, ctx->ac.i32,
859 &ctx->abi.tcs_patch_id);
860 add_arg(&args, ARG_VGPR, ctx->ac.i32,
861 &ctx->abi.tcs_rel_ids);
862
863 declare_vs_input_vgprs(ctx, &args);
864 } else {
865 declare_global_input_sgprs(ctx, stage,
866 has_previous_stage,
867 previous_stage,
868 &user_sgpr_info, &args,
869 &desc_sets);
870
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_offchip_layout);
873 add_arg(&args, ARG_SGPR, ctx->ac.i32,
874 &ctx->tcs_out_offsets);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tcs_out_layout);
877 add_arg(&args, ARG_SGPR, ctx->ac.i32,
878 &ctx->tcs_in_layout);
879 if (ctx->shader_info->info.needs_multiview_view_index)
880 add_arg(&args, ARG_SGPR, ctx->ac.i32,
881 &ctx->view_index);
882
883 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
884 add_arg(&args, ARG_SGPR, ctx->ac.i32,
885 &ctx->tess_factor_offset);
886 add_arg(&args, ARG_VGPR, ctx->ac.i32,
887 &ctx->abi.tcs_patch_id);
888 add_arg(&args, ARG_VGPR, ctx->ac.i32,
889 &ctx->abi.tcs_rel_ids);
890 }
891 break;
892 case MESA_SHADER_TESS_EVAL:
893 declare_global_input_sgprs(ctx, stage, has_previous_stage,
894 previous_stage, &user_sgpr_info,
895 &args, &desc_sets);
896
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
898 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
900
901 if (ctx->options->key.tes.as_es) {
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
903 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
904 add_arg(&args, ARG_SGPR, ctx->ac.i32,
905 &ctx->es2gs_offset);
906 } else {
907 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
908 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
909 }
910 declare_tes_input_vgprs(ctx, &args);
911 break;
912 case MESA_SHADER_GEOMETRY:
913 if (has_previous_stage) {
914 // First 6 system regs
915 add_arg(&args, ARG_SGPR, ctx->ac.i32,
916 &ctx->gs2vs_offset);
917 add_arg(&args, ARG_SGPR, ctx->ac.i32,
918 &ctx->merged_wave_info);
919 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
920
921 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
922 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
923 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
924
925 declare_global_input_sgprs(ctx, stage,
926 has_previous_stage,
927 previous_stage,
928 &user_sgpr_info, &args,
929 &desc_sets);
930
931 if (previous_stage == MESA_SHADER_TESS_EVAL) {
932 add_arg(&args, ARG_SGPR, ctx->ac.i32,
933 &ctx->tcs_offchip_layout);
934 } else {
935 declare_vs_specific_input_sgprs(ctx, stage,
936 has_previous_stage,
937 previous_stage,
938 &args);
939 }
940
941 add_arg(&args, ARG_SGPR, ctx->ac.i32,
942 &ctx->gsvs_ring_stride);
943 add_arg(&args, ARG_SGPR, ctx->ac.i32,
944 &ctx->gsvs_num_entries);
945 if (ctx->shader_info->info.needs_multiview_view_index)
946 add_arg(&args, ARG_SGPR, ctx->ac.i32,
947 &ctx->view_index);
948
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[0]);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->gs_vtx_offset[2]);
953 add_arg(&args, ARG_VGPR, ctx->ac.i32,
954 &ctx->abi.gs_prim_id);
955 add_arg(&args, ARG_VGPR, ctx->ac.i32,
956 &ctx->abi.gs_invocation_id);
957 add_arg(&args, ARG_VGPR, ctx->ac.i32,
958 &ctx->gs_vtx_offset[4]);
959
960 if (previous_stage == MESA_SHADER_VERTEX) {
961 declare_vs_input_vgprs(ctx, &args);
962 } else {
963 declare_tes_input_vgprs(ctx, &args);
964 }
965 } else {
966 declare_global_input_sgprs(ctx, stage,
967 has_previous_stage,
968 previous_stage,
969 &user_sgpr_info, &args,
970 &desc_sets);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32,
973 &ctx->gsvs_ring_stride);
974 add_arg(&args, ARG_SGPR, ctx->ac.i32,
975 &ctx->gsvs_num_entries);
976 if (ctx->shader_info->info.needs_multiview_view_index)
977 add_arg(&args, ARG_SGPR, ctx->ac.i32,
978 &ctx->view_index);
979
980 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
981 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[0]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[1]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->abi.gs_prim_id);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[2]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->gs_vtx_offset[3]);
992 add_arg(&args, ARG_VGPR, ctx->ac.i32,
993 &ctx->gs_vtx_offset[4]);
994 add_arg(&args, ARG_VGPR, ctx->ac.i32,
995 &ctx->gs_vtx_offset[5]);
996 add_arg(&args, ARG_VGPR, ctx->ac.i32,
997 &ctx->abi.gs_invocation_id);
998 }
999 break;
1000 case MESA_SHADER_FRAGMENT:
1001 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1002 previous_stage, &user_sgpr_info,
1003 &args, &desc_sets);
1004
1005 if (ctx->shader_info->info.ps.needs_sample_positions)
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1007 &ctx->sample_pos_offset);
1008
1009 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1011 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1012 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1013 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1014 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1015 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1016 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1017 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1018 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1019 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1020 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1021 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1022 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1023 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1024 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1025 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1026 break;
1027 default:
1028 unreachable("Shader stage not implemented");
1029 }
1030
1031 ctx->main_function = create_llvm_function(
1032 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1033 ctx->max_workgroup_size,
1034 ctx->options->unsafe_math);
1035 set_llvm_calling_convention(ctx->main_function, stage);
1036
1037
1038 ctx->shader_info->num_input_vgprs = 0;
1039 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1040
1041 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1042
1043 if (ctx->stage != MESA_SHADER_FRAGMENT)
1044 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1045
1046 assign_arguments(ctx->main_function, &args);
1047
1048 user_sgpr_idx = 0;
1049
1050 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1051 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1052 &user_sgpr_idx, 2);
1053 if (ctx->options->supports_spill) {
1054 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1055 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1056 NULL, 0, AC_FUNC_ATTR_READNONE);
1057 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1058 const_array(ctx->ac.v4i32, 16), "");
1059 }
1060 }
1061
1062 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1063 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1064 if (has_previous_stage)
1065 user_sgpr_idx = 0;
1066
1067 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1068 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1069
1070 switch (stage) {
1071 case MESA_SHADER_COMPUTE:
1072 if (ctx->shader_info->info.cs.uses_grid_size) {
1073 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1074 &user_sgpr_idx, 3);
1075 }
1076 break;
1077 case MESA_SHADER_VERTEX:
1078 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1079 previous_stage, &user_sgpr_idx);
1080 if (ctx->view_index)
1081 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1082 if (ctx->options->key.vs.as_ls) {
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 }
1086 if (ctx->options->key.vs.as_ls)
1087 ac_declare_lds_as_pointer(&ctx->ac);
1088 break;
1089 case MESA_SHADER_TESS_CTRL:
1090 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1091 previous_stage, &user_sgpr_idx);
1092 if (has_previous_stage)
1093 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1094 &user_sgpr_idx, 1);
1095 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1096 if (ctx->view_index)
1097 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1098 ac_declare_lds_as_pointer(&ctx->ac);
1099 break;
1100 case MESA_SHADER_TESS_EVAL:
1101 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1102 if (ctx->view_index)
1103 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1104 break;
1105 case MESA_SHADER_GEOMETRY:
1106 if (has_previous_stage) {
1107 if (previous_stage == MESA_SHADER_VERTEX)
1108 set_vs_specific_input_locs(ctx, stage,
1109 has_previous_stage,
1110 previous_stage,
1111 &user_sgpr_idx);
1112 else
1113 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1114 &user_sgpr_idx, 1);
1115 }
1116 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1117 &user_sgpr_idx, 2);
1118 if (ctx->view_index)
1119 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1120 if (has_previous_stage)
1121 ac_declare_lds_as_pointer(&ctx->ac);
1122 break;
1123 case MESA_SHADER_FRAGMENT:
1124 if (ctx->shader_info->info.ps.needs_sample_positions) {
1125 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1126 &user_sgpr_idx, 1);
1127 }
1128 break;
1129 default:
1130 unreachable("Shader stage not implemented");
1131 }
1132
1133 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1134 }
1135
1136 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1137 LLVMValueRef value, unsigned count)
1138 {
1139 unsigned num_components = ac_get_llvm_num_components(value);
1140 if (count == num_components)
1141 return value;
1142
1143 LLVMValueRef masks[] = {
1144 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1145 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1146
1147 if (count == 1)
1148 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1149 "");
1150
1151 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1152 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1153 }
1154
1155 static void
1156 build_store_values_extended(struct ac_llvm_context *ac,
1157 LLVMValueRef *values,
1158 unsigned value_count,
1159 unsigned value_stride,
1160 LLVMValueRef vec)
1161 {
1162 LLVMBuilderRef builder = ac->builder;
1163 unsigned i;
1164
1165 for (i = 0; i < value_count; i++) {
1166 LLVMValueRef ptr = values[i * value_stride];
1167 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1168 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1169 LLVMBuildStore(builder, value, ptr);
1170 }
1171 }
1172
1173 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1174 const nir_ssa_def *def)
1175 {
1176 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1177 if (def->num_components > 1) {
1178 type = LLVMVectorType(type, def->num_components);
1179 }
1180 return type;
1181 }
1182
1183 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1184 {
1185 assert(src.is_ssa);
1186 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1187 return (LLVMValueRef)entry->data;
1188 }
1189
1190
1191 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1192 const struct nir_block *b)
1193 {
1194 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1195 return (LLVMBasicBlockRef)entry->data;
1196 }
1197
1198 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1199 nir_alu_src src,
1200 unsigned num_components)
1201 {
1202 LLVMValueRef value = get_src(ctx, src.src);
1203 bool need_swizzle = false;
1204
1205 assert(value);
1206 LLVMTypeRef type = LLVMTypeOf(value);
1207 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1208 ? LLVMGetVectorSize(type)
1209 : 1;
1210
1211 for (unsigned i = 0; i < num_components; ++i) {
1212 assert(src.swizzle[i] < src_components);
1213 if (src.swizzle[i] != i)
1214 need_swizzle = true;
1215 }
1216
1217 if (need_swizzle || num_components != src_components) {
1218 LLVMValueRef masks[] = {
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1220 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1221 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1222 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1223
1224 if (src_components > 1 && num_components == 1) {
1225 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1226 masks[0], "");
1227 } else if (src_components == 1 && num_components > 1) {
1228 LLVMValueRef values[] = {value, value, value, value};
1229 value = ac_build_gather_values(&ctx->ac, values, num_components);
1230 } else {
1231 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1232 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1233 swizzle, "");
1234 }
1235 }
1236 assert(!src.negate);
1237 assert(!src.abs);
1238 return value;
1239 }
1240
1241 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1242 LLVMIntPredicate pred, LLVMValueRef src0,
1243 LLVMValueRef src1)
1244 {
1245 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1246 return LLVMBuildSelect(ctx->builder, result,
1247 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1248 ctx->i32_0, "");
1249 }
1250
1251 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1252 LLVMRealPredicate pred, LLVMValueRef src0,
1253 LLVMValueRef src1)
1254 {
1255 LLVMValueRef result;
1256 src0 = ac_to_float(ctx, src0);
1257 src1 = ac_to_float(ctx, src1);
1258 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1259 return LLVMBuildSelect(ctx->builder, result,
1260 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1261 ctx->i32_0, "");
1262 }
1263
1264 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1265 const char *intrin,
1266 LLVMTypeRef result_type,
1267 LLVMValueRef src0)
1268 {
1269 char name[64];
1270 LLVMValueRef params[] = {
1271 ac_to_float(ctx, src0),
1272 };
1273
1274 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1275 get_elem_bits(ctx, result_type));
1276 assert(length < sizeof(name));
1277 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1278 }
1279
1280 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0, LLVMValueRef src1)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 ac_to_float(ctx, src1),
1289 };
1290
1291 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1292 get_elem_bits(ctx, result_type));
1293 assert(length < sizeof(name));
1294 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1295 }
1296
1297 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1298 const char *intrin,
1299 LLVMTypeRef result_type,
1300 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1301 {
1302 char name[64];
1303 LLVMValueRef params[] = {
1304 ac_to_float(ctx, src0),
1305 ac_to_float(ctx, src1),
1306 ac_to_float(ctx, src2),
1307 };
1308
1309 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1310 get_elem_bits(ctx, result_type));
1311 assert(length < sizeof(name));
1312 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1313 }
1314
1315 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1319 ctx->i32_0, "");
1320 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1321 }
1322
1323 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1324 LLVMIntPredicate pred,
1325 LLVMValueRef src0, LLVMValueRef src1)
1326 {
1327 return LLVMBuildSelect(ctx->builder,
1328 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1329 src0,
1330 src1, "");
1331
1332 }
1333 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1334 LLVMValueRef src0)
1335 {
1336 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1337 LLVMBuildNeg(ctx->builder, src0, ""));
1338 }
1339
1340 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1341 LLVMValueRef src0,
1342 unsigned bitsize)
1343 {
1344 LLVMValueRef cmp, val, zero, one;
1345 LLVMTypeRef type;
1346
1347 if (bitsize == 32) {
1348 type = ctx->f32;
1349 zero = ctx->f32_0;
1350 one = ctx->f32_1;
1351 } else {
1352 type = ctx->f64;
1353 zero = ctx->f64_0;
1354 one = ctx->f64_1;
1355 }
1356
1357 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1358 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1359 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1360 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1361 return val;
1362 }
1363
1364 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1365 LLVMValueRef src0, unsigned bitsize)
1366 {
1367 LLVMValueRef cmp, val, zero, one;
1368 LLVMTypeRef type;
1369
1370 if (bitsize == 32) {
1371 type = ctx->i32;
1372 zero = ctx->i32_0;
1373 one = ctx->i32_1;
1374 } else {
1375 type = ctx->i64;
1376 zero = ctx->i64_0;
1377 one = ctx->i64_1;
1378 }
1379
1380 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1381 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1382 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1383 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1384 return val;
1385 }
1386
1387 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1388 LLVMValueRef src0)
1389 {
1390 const char *intr = "llvm.floor.f32";
1391 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1392 LLVMValueRef params[] = {
1393 fsrc0,
1394 };
1395 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1396 ctx->f32, params, 1,
1397 AC_FUNC_ATTR_READNONE);
1398 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1399 }
1400
1401 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1402 const char *intrin,
1403 LLVMValueRef src0, LLVMValueRef src1)
1404 {
1405 LLVMTypeRef ret_type;
1406 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1407 LLVMValueRef res;
1408 LLVMValueRef params[] = { src0, src1 };
1409 ret_type = LLVMStructTypeInContext(ctx->context, types,
1410 2, true);
1411
1412 res = ac_build_intrinsic(ctx, intrin, ret_type,
1413 params, 2, AC_FUNC_ATTR_READNONE);
1414
1415 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1416 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1417 return res;
1418 }
1419
1420 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1421 LLVMValueRef src0)
1422 {
1423 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1424 }
1425
1426 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1427 LLVMValueRef src0)
1428 {
1429 src0 = ac_to_float(ctx, src0);
1430 return LLVMBuildSExt(ctx->builder,
1431 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1432 ctx->i32, "");
1433 }
1434
1435 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1436 LLVMValueRef src0,
1437 unsigned bitsize)
1438 {
1439 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1440
1441 if (bitsize == 32)
1442 return result;
1443
1444 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1445 }
1446
1447 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1448 LLVMValueRef src0)
1449 {
1450 return LLVMBuildSExt(ctx->builder,
1451 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1452 ctx->i32, "");
1453 }
1454
1455 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1456 LLVMValueRef src0)
1457 {
1458 LLVMValueRef result;
1459 LLVMValueRef cond = NULL;
1460
1461 src0 = ac_to_float(&ctx->ac, src0);
1462 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1463
1464 if (ctx->options->chip_class >= VI) {
1465 LLVMValueRef args[2];
1466 /* Check if the result is a denormal - and flush to 0 if so. */
1467 args[0] = result;
1468 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1469 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1470 }
1471
1472 /* need to convert back up to f32 */
1473 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1474
1475 if (ctx->options->chip_class >= VI)
1476 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1477 else {
1478 /* for SI/CIK */
1479 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1480 * so compare the result and flush to 0 if it's smaller.
1481 */
1482 LLVMValueRef temp, cond2;
1483 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1484 ctx->ac.f32, result);
1485 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1486 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1487 temp, "");
1488 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1489 temp, ctx->ac.f32_0, "");
1490 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1491 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1492 }
1493 return result;
1494 }
1495
1496 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1497 LLVMValueRef src0, LLVMValueRef src1)
1498 {
1499 LLVMValueRef dst64, result;
1500 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1501 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1502
1503 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1504 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1505 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1510 LLVMValueRef src0, LLVMValueRef src1)
1511 {
1512 LLVMValueRef dst64, result;
1513 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1514 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1515
1516 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1517 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1518 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1519 return result;
1520 }
1521
1522 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1523 bool is_signed,
1524 const LLVMValueRef srcs[3])
1525 {
1526 LLVMValueRef result;
1527 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1528
1529 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1530 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1531 return result;
1532 }
1533
1534 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1535 LLVMValueRef src0, LLVMValueRef src1,
1536 LLVMValueRef src2, LLVMValueRef src3)
1537 {
1538 LLVMValueRef bfi_args[3], result;
1539
1540 bfi_args[0] = LLVMBuildShl(ctx->builder,
1541 LLVMBuildSub(ctx->builder,
1542 LLVMBuildShl(ctx->builder,
1543 ctx->i32_1,
1544 src3, ""),
1545 ctx->i32_1, ""),
1546 src2, "");
1547 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1548 bfi_args[2] = src0;
1549
1550 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1551
1552 /* Calculate:
1553 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1554 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1555 */
1556 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1557 LLVMBuildAnd(ctx->builder, bfi_args[0],
1558 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1559
1560 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1561 return result;
1562 }
1563
1564 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1565 LLVMValueRef src0)
1566 {
1567 LLVMValueRef comp[2];
1568
1569 src0 = ac_to_float(ctx, src0);
1570 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1571 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1572
1573 return ac_build_cvt_pkrtz_f16(ctx, comp);
1574 }
1575
1576 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1577 LLVMValueRef src0)
1578 {
1579 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1580 LLVMValueRef temps[2], result, val;
1581 int i;
1582
1583 for (i = 0; i < 2; i++) {
1584 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1585 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1586 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1587 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1588 }
1589
1590 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1591 ctx->i32_0, "");
1592 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1593 ctx->i32_1, "");
1594 return result;
1595 }
1596
1597 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1598 nir_op op,
1599 LLVMValueRef src0)
1600 {
1601 unsigned mask;
1602 int idx;
1603 LLVMValueRef result;
1604
1605 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1606 mask = AC_TID_MASK_LEFT;
1607 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1608 mask = AC_TID_MASK_TOP;
1609 else
1610 mask = AC_TID_MASK_TOP_LEFT;
1611
1612 /* for DDX we want to next X pixel, DDY next Y pixel. */
1613 if (op == nir_op_fddx_fine ||
1614 op == nir_op_fddx_coarse ||
1615 op == nir_op_fddx)
1616 idx = 1;
1617 else
1618 idx = 2;
1619
1620 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1621 return result;
1622 }
1623
1624 /*
1625 * this takes an I,J coordinate pair,
1626 * and works out the X and Y derivatives.
1627 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1628 */
1629 static LLVMValueRef emit_ddxy_interp(
1630 struct ac_nir_context *ctx,
1631 LLVMValueRef interp_ij)
1632 {
1633 LLVMValueRef result[4], a;
1634 unsigned i;
1635
1636 for (i = 0; i < 2; i++) {
1637 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1638 LLVMConstInt(ctx->ac.i32, i, false), "");
1639 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1640 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1641 }
1642 return ac_build_gather_values(&ctx->ac, result, 4);
1643 }
1644
1645 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1646 {
1647 LLVMValueRef src[4], result = NULL;
1648 unsigned num_components = instr->dest.dest.ssa.num_components;
1649 unsigned src_components;
1650 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1651
1652 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1653 switch (instr->op) {
1654 case nir_op_vec2:
1655 case nir_op_vec3:
1656 case nir_op_vec4:
1657 src_components = 1;
1658 break;
1659 case nir_op_pack_half_2x16:
1660 src_components = 2;
1661 break;
1662 case nir_op_unpack_half_2x16:
1663 src_components = 1;
1664 break;
1665 default:
1666 src_components = num_components;
1667 break;
1668 }
1669 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1670 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1671
1672 switch (instr->op) {
1673 case nir_op_fmov:
1674 case nir_op_imov:
1675 result = src[0];
1676 break;
1677 case nir_op_fneg:
1678 src[0] = ac_to_float(&ctx->ac, src[0]);
1679 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1680 break;
1681 case nir_op_ineg:
1682 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1683 break;
1684 case nir_op_inot:
1685 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1686 break;
1687 case nir_op_iadd:
1688 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_fadd:
1691 src[0] = ac_to_float(&ctx->ac, src[0]);
1692 src[1] = ac_to_float(&ctx->ac, src[1]);
1693 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1694 break;
1695 case nir_op_fsub:
1696 src[0] = ac_to_float(&ctx->ac, src[0]);
1697 src[1] = ac_to_float(&ctx->ac, src[1]);
1698 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1699 break;
1700 case nir_op_isub:
1701 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_imul:
1704 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1705 break;
1706 case nir_op_imod:
1707 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1708 break;
1709 case nir_op_umod:
1710 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1711 break;
1712 case nir_op_fmod:
1713 src[0] = ac_to_float(&ctx->ac, src[0]);
1714 src[1] = ac_to_float(&ctx->ac, src[1]);
1715 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1716 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1717 ac_to_float_type(&ctx->ac, def_type), result);
1718 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1719 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1720 break;
1721 case nir_op_frem:
1722 src[0] = ac_to_float(&ctx->ac, src[0]);
1723 src[1] = ac_to_float(&ctx->ac, src[1]);
1724 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1725 break;
1726 case nir_op_irem:
1727 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1728 break;
1729 case nir_op_idiv:
1730 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1731 break;
1732 case nir_op_udiv:
1733 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1734 break;
1735 case nir_op_fmul:
1736 src[0] = ac_to_float(&ctx->ac, src[0]);
1737 src[1] = ac_to_float(&ctx->ac, src[1]);
1738 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1739 break;
1740 case nir_op_fdiv:
1741 src[0] = ac_to_float(&ctx->ac, src[0]);
1742 src[1] = ac_to_float(&ctx->ac, src[1]);
1743 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1744 break;
1745 case nir_op_frcp:
1746 src[0] = ac_to_float(&ctx->ac, src[0]);
1747 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1748 src[0]);
1749 break;
1750 case nir_op_iand:
1751 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1752 break;
1753 case nir_op_ior:
1754 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1755 break;
1756 case nir_op_ixor:
1757 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1758 break;
1759 case nir_op_ishl:
1760 result = LLVMBuildShl(ctx->ac.builder, src[0],
1761 LLVMBuildZExt(ctx->ac.builder, src[1],
1762 LLVMTypeOf(src[0]), ""),
1763 "");
1764 break;
1765 case nir_op_ishr:
1766 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1767 LLVMBuildZExt(ctx->ac.builder, src[1],
1768 LLVMTypeOf(src[0]), ""),
1769 "");
1770 break;
1771 case nir_op_ushr:
1772 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1773 LLVMBuildZExt(ctx->ac.builder, src[1],
1774 LLVMTypeOf(src[0]), ""),
1775 "");
1776 break;
1777 case nir_op_ilt:
1778 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1779 break;
1780 case nir_op_ine:
1781 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1782 break;
1783 case nir_op_ieq:
1784 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1785 break;
1786 case nir_op_ige:
1787 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1788 break;
1789 case nir_op_ult:
1790 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1791 break;
1792 case nir_op_uge:
1793 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1794 break;
1795 case nir_op_feq:
1796 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1797 break;
1798 case nir_op_fne:
1799 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1800 break;
1801 case nir_op_flt:
1802 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1803 break;
1804 case nir_op_fge:
1805 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1806 break;
1807 case nir_op_fabs:
1808 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1809 ac_to_float_type(&ctx->ac, def_type), src[0]);
1810 break;
1811 case nir_op_iabs:
1812 result = emit_iabs(&ctx->ac, src[0]);
1813 break;
1814 case nir_op_imax:
1815 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1816 break;
1817 case nir_op_imin:
1818 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1819 break;
1820 case nir_op_umax:
1821 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1822 break;
1823 case nir_op_umin:
1824 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1825 break;
1826 case nir_op_isign:
1827 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1828 break;
1829 case nir_op_fsign:
1830 src[0] = ac_to_float(&ctx->ac, src[0]);
1831 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1832 break;
1833 case nir_op_ffloor:
1834 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1835 ac_to_float_type(&ctx->ac, def_type), src[0]);
1836 break;
1837 case nir_op_ftrunc:
1838 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1839 ac_to_float_type(&ctx->ac, def_type), src[0]);
1840 break;
1841 case nir_op_fceil:
1842 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1843 ac_to_float_type(&ctx->ac, def_type), src[0]);
1844 break;
1845 case nir_op_fround_even:
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1847 ac_to_float_type(&ctx->ac, def_type),src[0]);
1848 break;
1849 case nir_op_ffract:
1850 result = emit_ffract(&ctx->ac, src[0]);
1851 break;
1852 case nir_op_fsin:
1853 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1854 ac_to_float_type(&ctx->ac, def_type), src[0]);
1855 break;
1856 case nir_op_fcos:
1857 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1858 ac_to_float_type(&ctx->ac, def_type), src[0]);
1859 break;
1860 case nir_op_fsqrt:
1861 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1862 ac_to_float_type(&ctx->ac, def_type), src[0]);
1863 break;
1864 case nir_op_fexp2:
1865 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1866 ac_to_float_type(&ctx->ac, def_type), src[0]);
1867 break;
1868 case nir_op_flog2:
1869 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1870 ac_to_float_type(&ctx->ac, def_type), src[0]);
1871 break;
1872 case nir_op_frsq:
1873 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1874 ac_to_float_type(&ctx->ac, def_type), src[0]);
1875 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1876 result);
1877 break;
1878 case nir_op_fpow:
1879 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1880 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1881 break;
1882 case nir_op_fmax:
1883 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1884 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1885 if (instr->dest.dest.ssa.bit_size == 32)
1886 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1887 ac_to_float_type(&ctx->ac, def_type),
1888 result);
1889 break;
1890 case nir_op_fmin:
1891 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1892 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1893 if (instr->dest.dest.ssa.bit_size == 32)
1894 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1895 ac_to_float_type(&ctx->ac, def_type),
1896 result);
1897 break;
1898 case nir_op_ffma:
1899 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1900 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1901 break;
1902 case nir_op_ibitfield_extract:
1903 result = emit_bitfield_extract(&ctx->ac, true, src);
1904 break;
1905 case nir_op_ubitfield_extract:
1906 result = emit_bitfield_extract(&ctx->ac, false, src);
1907 break;
1908 case nir_op_bitfield_insert:
1909 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1910 break;
1911 case nir_op_bitfield_reverse:
1912 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1913 break;
1914 case nir_op_bit_count:
1915 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1916 break;
1917 case nir_op_vec2:
1918 case nir_op_vec3:
1919 case nir_op_vec4:
1920 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1921 src[i] = ac_to_integer(&ctx->ac, src[i]);
1922 result = ac_build_gather_values(&ctx->ac, src, num_components);
1923 break;
1924 case nir_op_f2i32:
1925 case nir_op_f2i64:
1926 src[0] = ac_to_float(&ctx->ac, src[0]);
1927 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1928 break;
1929 case nir_op_f2u32:
1930 case nir_op_f2u64:
1931 src[0] = ac_to_float(&ctx->ac, src[0]);
1932 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1933 break;
1934 case nir_op_i2f32:
1935 case nir_op_i2f64:
1936 src[0] = ac_to_integer(&ctx->ac, src[0]);
1937 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1938 break;
1939 case nir_op_u2f32:
1940 case nir_op_u2f64:
1941 src[0] = ac_to_integer(&ctx->ac, src[0]);
1942 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1943 break;
1944 case nir_op_f2f64:
1945 src[0] = ac_to_float(&ctx->ac, src[0]);
1946 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1947 break;
1948 case nir_op_f2f32:
1949 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1950 break;
1951 case nir_op_u2u32:
1952 case nir_op_u2u64:
1953 src[0] = ac_to_integer(&ctx->ac, src[0]);
1954 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1955 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1956 else
1957 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1958 break;
1959 case nir_op_i2i32:
1960 case nir_op_i2i64:
1961 src[0] = ac_to_integer(&ctx->ac, src[0]);
1962 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1963 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1964 else
1965 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1966 break;
1967 case nir_op_bcsel:
1968 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1969 break;
1970 case nir_op_find_lsb:
1971 src[0] = ac_to_integer(&ctx->ac, src[0]);
1972 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1973 break;
1974 case nir_op_ufind_msb:
1975 src[0] = ac_to_integer(&ctx->ac, src[0]);
1976 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1977 break;
1978 case nir_op_ifind_msb:
1979 src[0] = ac_to_integer(&ctx->ac, src[0]);
1980 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1981 break;
1982 case nir_op_uadd_carry:
1983 src[0] = ac_to_integer(&ctx->ac, src[0]);
1984 src[1] = ac_to_integer(&ctx->ac, src[1]);
1985 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1986 break;
1987 case nir_op_usub_borrow:
1988 src[0] = ac_to_integer(&ctx->ac, src[0]);
1989 src[1] = ac_to_integer(&ctx->ac, src[1]);
1990 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1991 break;
1992 case nir_op_b2f:
1993 result = emit_b2f(&ctx->ac, src[0]);
1994 break;
1995 case nir_op_f2b:
1996 result = emit_f2b(&ctx->ac, src[0]);
1997 break;
1998 case nir_op_b2i:
1999 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2000 break;
2001 case nir_op_i2b:
2002 src[0] = ac_to_integer(&ctx->ac, src[0]);
2003 result = emit_i2b(&ctx->ac, src[0]);
2004 break;
2005 case nir_op_fquantize2f16:
2006 result = emit_f2f16(ctx->nctx, src[0]);
2007 break;
2008 case nir_op_umul_high:
2009 src[0] = ac_to_integer(&ctx->ac, src[0]);
2010 src[1] = ac_to_integer(&ctx->ac, src[1]);
2011 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2012 break;
2013 case nir_op_imul_high:
2014 src[0] = ac_to_integer(&ctx->ac, src[0]);
2015 src[1] = ac_to_integer(&ctx->ac, src[1]);
2016 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2017 break;
2018 case nir_op_pack_half_2x16:
2019 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2020 break;
2021 case nir_op_unpack_half_2x16:
2022 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2023 break;
2024 case nir_op_fddx:
2025 case nir_op_fddy:
2026 case nir_op_fddx_fine:
2027 case nir_op_fddy_fine:
2028 case nir_op_fddx_coarse:
2029 case nir_op_fddy_coarse:
2030 result = emit_ddxy(ctx, instr->op, src[0]);
2031 break;
2032
2033 case nir_op_unpack_64_2x32_split_x: {
2034 assert(instr->src[0].src.ssa->num_components == 1);
2035 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2036 ctx->ac.v2i32,
2037 "");
2038 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2039 ctx->ac.i32_0, "");
2040 break;
2041 }
2042
2043 case nir_op_unpack_64_2x32_split_y: {
2044 assert(instr->src[0].src.ssa->num_components == 1);
2045 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2046 ctx->ac.v2i32,
2047 "");
2048 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2049 ctx->ac.i32_1, "");
2050 break;
2051 }
2052
2053 case nir_op_pack_64_2x32_split: {
2054 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2055 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2056 src[0], ctx->ac.i32_0, "");
2057 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2058 src[1], ctx->ac.i32_1, "");
2059 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2060 break;
2061 }
2062
2063 default:
2064 fprintf(stderr, "Unknown NIR alu instr: ");
2065 nir_print_instr(&instr->instr, stderr);
2066 fprintf(stderr, "\n");
2067 abort();
2068 }
2069
2070 if (result) {
2071 assert(instr->dest.dest.is_ssa);
2072 result = ac_to_integer(&ctx->ac, result);
2073 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2074 result);
2075 }
2076 }
2077
2078 static void visit_load_const(struct ac_nir_context *ctx,
2079 const nir_load_const_instr *instr)
2080 {
2081 LLVMValueRef values[4], value = NULL;
2082 LLVMTypeRef element_type =
2083 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2084
2085 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2086 switch (instr->def.bit_size) {
2087 case 32:
2088 values[i] = LLVMConstInt(element_type,
2089 instr->value.u32[i], false);
2090 break;
2091 case 64:
2092 values[i] = LLVMConstInt(element_type,
2093 instr->value.u64[i], false);
2094 break;
2095 default:
2096 fprintf(stderr,
2097 "unsupported nir load_const bit_size: %d\n",
2098 instr->def.bit_size);
2099 abort();
2100 }
2101 }
2102 if (instr->def.num_components > 1) {
2103 value = LLVMConstVector(values, instr->def.num_components);
2104 } else
2105 value = values[0];
2106
2107 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2108 }
2109
2110 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2111 LLVMTypeRef type)
2112 {
2113 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2114 return LLVMBuildBitCast(ctx->builder, ptr,
2115 LLVMPointerType(type, addr_space), "");
2116 }
2117
2118 static LLVMValueRef
2119 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2120 {
2121 LLVMValueRef size =
2122 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2123 LLVMConstInt(ctx->ac.i32, 2, false), "");
2124
2125 /* VI only */
2126 if (ctx->ac.chip_class == VI && in_elements) {
2127 /* On VI, the descriptor contains the size in bytes,
2128 * but TXQ must return the size in elements.
2129 * The stride is always non-zero for resources using TXQ.
2130 */
2131 LLVMValueRef stride =
2132 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2133 ctx->ac.i32_1, "");
2134 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2135 LLVMConstInt(ctx->ac.i32, 16, false), "");
2136 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2137 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2138
2139 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2140 }
2141 return size;
2142 }
2143
2144 /**
2145 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2146 * intrinsic names).
2147 */
2148 static void build_int_type_name(
2149 LLVMTypeRef type,
2150 char *buf, unsigned bufsize)
2151 {
2152 assert(bufsize >= 6);
2153
2154 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2155 snprintf(buf, bufsize, "v%ui32",
2156 LLVMGetVectorSize(type));
2157 else
2158 strcpy(buf, "i32");
2159 }
2160
2161 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2162 struct ac_image_args *args,
2163 const nir_tex_instr *instr)
2164 {
2165 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2166 LLVMValueRef coord = args->addr;
2167 LLVMValueRef half_texel[2];
2168 LLVMValueRef compare_cube_wa = NULL;
2169 LLVMValueRef result;
2170 int c;
2171 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2172
2173 //TODO Rect
2174 {
2175 struct ac_image_args txq_args = { 0 };
2176
2177 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2178 txq_args.opcode = ac_image_get_resinfo;
2179 txq_args.dmask = 0xf;
2180 txq_args.addr = ctx->i32_0;
2181 txq_args.resource = args->resource;
2182 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2183
2184 for (c = 0; c < 2; c++) {
2185 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2186 LLVMConstInt(ctx->i32, c, false), "");
2187 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2188 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2189 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2190 LLVMConstReal(ctx->f32, -0.5), "");
2191 }
2192 }
2193
2194 LLVMValueRef orig_coords = args->addr;
2195
2196 for (c = 0; c < 2; c++) {
2197 LLVMValueRef tmp;
2198 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2199 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2200 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2201 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2202 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2203 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2204 }
2205
2206
2207 /*
2208 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2209 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2210 * workaround by sampling using a scaled type and converting.
2211 * This is taken from amdgpu-pro shaders.
2212 */
2213 /* NOTE this produces some ugly code compared to amdgpu-pro,
2214 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2215 * and then reads them back. -pro generates two selects,
2216 * one s_cmp for the descriptor rewriting
2217 * one v_cmp for the coordinate and result changes.
2218 */
2219 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2220 LLVMValueRef tmp, tmp2;
2221
2222 /* workaround 8/8/8/8 uint/sint cube gather bug */
2223 /* first detect it then change to a scaled read and f2i */
2224 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2225 tmp2 = tmp;
2226
2227 /* extract the DATA_FORMAT */
2228 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2229 LLVMConstInt(ctx->i32, 6, false), false);
2230
2231 /* is the DATA_FORMAT == 8_8_8_8 */
2232 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2233
2234 if (stype == GLSL_TYPE_UINT)
2235 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2236 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2237 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2238 else
2239 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2240 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2241 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2242
2243 /* replace the NUM FORMAT in the descriptor */
2244 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2245 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2246
2247 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2248
2249 /* don't modify the coordinates for this case */
2250 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2251 }
2252 args->addr = coord;
2253 result = ac_build_image_opcode(ctx, args);
2254
2255 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2256 LLVMValueRef tmp, tmp2;
2257
2258 /* if the cube workaround is in place, f2i the result. */
2259 for (c = 0; c < 4; c++) {
2260 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2261 if (stype == GLSL_TYPE_UINT)
2262 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2263 else
2264 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2265 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2266 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2267 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2268 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2269 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2270 }
2271 }
2272 return result;
2273 }
2274
2275 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2276 const nir_tex_instr *instr,
2277 bool lod_is_zero,
2278 struct ac_image_args *args)
2279 {
2280 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2281 return ac_build_buffer_load_format(&ctx->ac,
2282 args->resource,
2283 args->addr,
2284 ctx->ac.i32_0,
2285 true);
2286 }
2287
2288 args->opcode = ac_image_sample;
2289 args->compare = instr->is_shadow;
2290
2291 switch (instr->op) {
2292 case nir_texop_txf:
2293 case nir_texop_txf_ms:
2294 case nir_texop_samples_identical:
2295 args->opcode = lod_is_zero ||
2296 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2297 ac_image_load : ac_image_load_mip;
2298 args->compare = false;
2299 args->offset = false;
2300 break;
2301 case nir_texop_txb:
2302 args->bias = true;
2303 break;
2304 case nir_texop_txl:
2305 if (lod_is_zero)
2306 args->level_zero = true;
2307 else
2308 args->lod = true;
2309 break;
2310 case nir_texop_txs:
2311 case nir_texop_query_levels:
2312 args->opcode = ac_image_get_resinfo;
2313 break;
2314 case nir_texop_tex:
2315 if (ctx->stage != MESA_SHADER_FRAGMENT)
2316 args->level_zero = true;
2317 break;
2318 case nir_texop_txd:
2319 args->deriv = true;
2320 break;
2321 case nir_texop_tg4:
2322 args->opcode = ac_image_gather4;
2323 args->level_zero = true;
2324 break;
2325 case nir_texop_lod:
2326 args->opcode = ac_image_get_lod;
2327 args->compare = false;
2328 args->offset = false;
2329 break;
2330 default:
2331 break;
2332 }
2333
2334 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2335 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2336 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2337 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2338 }
2339 }
2340 return ac_build_image_opcode(&ctx->ac, args);
2341 }
2342
2343 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2344 nir_intrinsic_instr *instr)
2345 {
2346 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2347 unsigned desc_set = nir_intrinsic_desc_set(instr);
2348 unsigned binding = nir_intrinsic_binding(instr);
2349 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2350 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2351 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2352 unsigned base_offset = layout->binding[binding].offset;
2353 LLVMValueRef offset, stride;
2354
2355 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2356 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2357 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2358 layout->binding[binding].dynamic_offset_offset;
2359 desc_ptr = ctx->push_constants;
2360 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2361 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2362 } else
2363 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2364
2365 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2366 index = LLVMBuildMul(ctx->builder, index, stride, "");
2367 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2368
2369 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2370 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2371 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2372
2373 return desc_ptr;
2374 }
2375
2376 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2377 nir_intrinsic_instr *instr)
2378 {
2379 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2380 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2381
2382 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2383 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2384 return result;
2385 }
2386
2387 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2388 nir_intrinsic_instr *instr)
2389 {
2390 LLVMValueRef ptr, addr;
2391
2392 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2393 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2394
2395 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2396 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2397
2398 return LLVMBuildLoad(ctx->builder, ptr, "");
2399 }
2400
2401 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2402 const nir_intrinsic_instr *instr)
2403 {
2404 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2405
2406 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2407 }
2408 static void visit_store_ssbo(struct ac_nir_context *ctx,
2409 nir_intrinsic_instr *instr)
2410 {
2411 const char *store_name;
2412 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2413 LLVMTypeRef data_type = ctx->ac.f32;
2414 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2415 int components_32bit = elem_size_mult * instr->num_components;
2416 unsigned writemask = nir_intrinsic_write_mask(instr);
2417 LLVMValueRef base_data, base_offset;
2418 LLVMValueRef params[6];
2419
2420 params[1] = ctx->abi->load_ssbo(ctx->abi,
2421 get_src(ctx, instr->src[1]), true);
2422 params[2] = ctx->ac.i32_0; /* vindex */
2423 params[4] = ctx->ac.i1false; /* glc */
2424 params[5] = ctx->ac.i1false; /* slc */
2425
2426 if (components_32bit > 1)
2427 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2428
2429 base_data = ac_to_float(&ctx->ac, src_data);
2430 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2431 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2432 data_type, "");
2433 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2434 while (writemask) {
2435 int start, count;
2436 LLVMValueRef data;
2437 LLVMValueRef offset;
2438 LLVMValueRef tmp;
2439 u_bit_scan_consecutive_range(&writemask, &start, &count);
2440
2441 /* Due to an LLVM limitation, split 3-element writes
2442 * into a 2-element and a 1-element write. */
2443 if (count == 3) {
2444 writemask |= 1 << (start + 2);
2445 count = 2;
2446 }
2447
2448 start *= elem_size_mult;
2449 count *= elem_size_mult;
2450
2451 if (count > 4) {
2452 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2453 count = 4;
2454 }
2455
2456 if (count == 4) {
2457 store_name = "llvm.amdgcn.buffer.store.v4f32";
2458 data = base_data;
2459 } else if (count == 2) {
2460 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2461 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2462 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2463 ctx->ac.i32_0, "");
2464
2465 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2466 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2467 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2468 ctx->ac.i32_1, "");
2469 store_name = "llvm.amdgcn.buffer.store.v2f32";
2470
2471 } else {
2472 assert(count == 1);
2473 if (ac_get_llvm_num_components(base_data) > 1)
2474 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2475 LLVMConstInt(ctx->ac.i32, start, false), "");
2476 else
2477 data = base_data;
2478 store_name = "llvm.amdgcn.buffer.store.f32";
2479 }
2480
2481 offset = base_offset;
2482 if (start != 0) {
2483 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2484 }
2485 params[0] = data;
2486 params[3] = offset;
2487 ac_build_intrinsic(&ctx->ac, store_name,
2488 ctx->ac.voidt, params, 6, 0);
2489 }
2490 }
2491
2492 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2493 const nir_intrinsic_instr *instr)
2494 {
2495 const char *name;
2496 LLVMValueRef params[6];
2497 int arg_count = 0;
2498
2499 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2500 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2501 }
2502 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2503 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2504 get_src(ctx, instr->src[0]),
2505 true);
2506 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2507 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2508 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2509
2510 switch (instr->intrinsic) {
2511 case nir_intrinsic_ssbo_atomic_add:
2512 name = "llvm.amdgcn.buffer.atomic.add";
2513 break;
2514 case nir_intrinsic_ssbo_atomic_imin:
2515 name = "llvm.amdgcn.buffer.atomic.smin";
2516 break;
2517 case nir_intrinsic_ssbo_atomic_umin:
2518 name = "llvm.amdgcn.buffer.atomic.umin";
2519 break;
2520 case nir_intrinsic_ssbo_atomic_imax:
2521 name = "llvm.amdgcn.buffer.atomic.smax";
2522 break;
2523 case nir_intrinsic_ssbo_atomic_umax:
2524 name = "llvm.amdgcn.buffer.atomic.umax";
2525 break;
2526 case nir_intrinsic_ssbo_atomic_and:
2527 name = "llvm.amdgcn.buffer.atomic.and";
2528 break;
2529 case nir_intrinsic_ssbo_atomic_or:
2530 name = "llvm.amdgcn.buffer.atomic.or";
2531 break;
2532 case nir_intrinsic_ssbo_atomic_xor:
2533 name = "llvm.amdgcn.buffer.atomic.xor";
2534 break;
2535 case nir_intrinsic_ssbo_atomic_exchange:
2536 name = "llvm.amdgcn.buffer.atomic.swap";
2537 break;
2538 case nir_intrinsic_ssbo_atomic_comp_swap:
2539 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2540 break;
2541 default:
2542 abort();
2543 }
2544
2545 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2546 }
2547
2548 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2549 const nir_intrinsic_instr *instr)
2550 {
2551 LLVMValueRef results[2];
2552 int load_components;
2553 int num_components = instr->num_components;
2554 if (instr->dest.ssa.bit_size == 64)
2555 num_components *= 2;
2556
2557 for (int i = 0; i < num_components; i += load_components) {
2558 load_components = MIN2(num_components - i, 4);
2559 const char *load_name;
2560 LLVMTypeRef data_type = ctx->ac.f32;
2561 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2562 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2563
2564 if (load_components == 3)
2565 data_type = LLVMVectorType(ctx->ac.f32, 4);
2566 else if (load_components > 1)
2567 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2568
2569 if (load_components >= 3)
2570 load_name = "llvm.amdgcn.buffer.load.v4f32";
2571 else if (load_components == 2)
2572 load_name = "llvm.amdgcn.buffer.load.v2f32";
2573 else if (load_components == 1)
2574 load_name = "llvm.amdgcn.buffer.load.f32";
2575 else
2576 unreachable("unhandled number of components");
2577
2578 LLVMValueRef params[] = {
2579 ctx->abi->load_ssbo(ctx->abi,
2580 get_src(ctx, instr->src[0]),
2581 false),
2582 ctx->ac.i32_0,
2583 offset,
2584 ctx->ac.i1false,
2585 ctx->ac.i1false,
2586 };
2587
2588 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2589
2590 }
2591
2592 assume(results[0]);
2593 LLVMValueRef ret = results[0];
2594 if (num_components > 4 || num_components == 3) {
2595 LLVMValueRef masks[] = {
2596 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2597 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2598 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2599 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2600 };
2601
2602 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2603 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2604 results[num_components > 4 ? 1 : 0], swizzle, "");
2605 }
2606
2607 return LLVMBuildBitCast(ctx->ac.builder, ret,
2608 get_def_type(ctx, &instr->dest.ssa), "");
2609 }
2610
2611 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2612 const nir_intrinsic_instr *instr)
2613 {
2614 LLVMValueRef ret;
2615 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2616 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2617 int num_components = instr->num_components;
2618
2619 if (ctx->abi->load_ubo)
2620 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2621
2622 if (instr->dest.ssa.bit_size == 64)
2623 num_components *= 2;
2624
2625 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2626 NULL, 0, false, false, true, true);
2627 ret = trim_vector(&ctx->ac, ret, num_components);
2628 return LLVMBuildBitCast(ctx->ac.builder, ret,
2629 get_def_type(ctx, &instr->dest.ssa), "");
2630 }
2631
2632 static void
2633 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2634 bool vs_in, unsigned *vertex_index_out,
2635 LLVMValueRef *vertex_index_ref,
2636 unsigned *const_out, LLVMValueRef *indir_out)
2637 {
2638 unsigned const_offset = 0;
2639 nir_deref *tail = &deref->deref;
2640 LLVMValueRef offset = NULL;
2641
2642 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2643 tail = tail->child;
2644 nir_deref_array *deref_array = nir_deref_as_array(tail);
2645 if (vertex_index_out)
2646 *vertex_index_out = deref_array->base_offset;
2647
2648 if (vertex_index_ref) {
2649 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2650 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2651 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2652 }
2653 *vertex_index_ref = vtx;
2654 }
2655 }
2656
2657 if (deref->var->data.compact) {
2658 assert(tail->child->deref_type == nir_deref_type_array);
2659 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2660 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2661 /* We always lower indirect dereferences for "compact" array vars. */
2662 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2663
2664 const_offset = deref_array->base_offset;
2665 goto out;
2666 }
2667
2668 while (tail->child != NULL) {
2669 const struct glsl_type *parent_type = tail->type;
2670 tail = tail->child;
2671
2672 if (tail->deref_type == nir_deref_type_array) {
2673 nir_deref_array *deref_array = nir_deref_as_array(tail);
2674 LLVMValueRef index, stride, local_offset;
2675 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2676
2677 const_offset += size * deref_array->base_offset;
2678 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2679 continue;
2680
2681 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2682 index = get_src(ctx, deref_array->indirect);
2683 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2684 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2685
2686 if (offset)
2687 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2688 else
2689 offset = local_offset;
2690 } else if (tail->deref_type == nir_deref_type_struct) {
2691 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2692
2693 for (unsigned i = 0; i < deref_struct->index; i++) {
2694 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2695 const_offset += glsl_count_attribute_slots(ft, vs_in);
2696 }
2697 } else
2698 unreachable("unsupported deref type");
2699
2700 }
2701 out:
2702 if (const_offset && offset)
2703 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2704 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2705 "");
2706
2707 *const_out = const_offset;
2708 *indir_out = offset;
2709 }
2710
2711
2712 /* The offchip buffer layout for TCS->TES is
2713 *
2714 * - attribute 0 of patch 0 vertex 0
2715 * - attribute 0 of patch 0 vertex 1
2716 * - attribute 0 of patch 0 vertex 2
2717 * ...
2718 * - attribute 0 of patch 1 vertex 0
2719 * - attribute 0 of patch 1 vertex 1
2720 * ...
2721 * - attribute 1 of patch 0 vertex 0
2722 * - attribute 1 of patch 0 vertex 1
2723 * ...
2724 * - per patch attribute 0 of patch 0
2725 * - per patch attribute 0 of patch 1
2726 * ...
2727 *
2728 * Note that every attribute has 4 components.
2729 */
2730 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2731 LLVMValueRef vertex_index,
2732 LLVMValueRef param_index)
2733 {
2734 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2735 LLVMValueRef param_stride, constant16;
2736 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2737
2738 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2739 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2740 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2741 num_patches, "");
2742
2743 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2744 if (vertex_index) {
2745 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2746 vertices_per_patch, "");
2747
2748 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2749 vertex_index, "");
2750
2751 param_stride = total_vertices;
2752 } else {
2753 base_addr = rel_patch_id;
2754 param_stride = num_patches;
2755 }
2756
2757 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2758 LLVMBuildMul(ctx->builder, param_index,
2759 param_stride, ""), "");
2760
2761 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2762
2763 if (!vertex_index) {
2764 LLVMValueRef patch_data_offset =
2765 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2766
2767 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2768 patch_data_offset, "");
2769 }
2770 return base_addr;
2771 }
2772
2773 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2774 unsigned param,
2775 unsigned const_index,
2776 bool is_compact,
2777 LLVMValueRef vertex_index,
2778 LLVMValueRef indir_index)
2779 {
2780 LLVMValueRef param_index;
2781
2782 if (indir_index)
2783 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2784 indir_index, "");
2785 else {
2786 if (const_index && !is_compact)
2787 param += const_index;
2788 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2789 }
2790 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2791 }
2792
2793 static void
2794 mark_tess_output(struct nir_to_llvm_context *ctx,
2795 bool is_patch, uint32_t param)
2796
2797 {
2798 if (is_patch) {
2799 ctx->tess_patch_outputs_written |= (1ull << param);
2800 } else
2801 ctx->tess_outputs_written |= (1ull << param);
2802 }
2803
2804 static LLVMValueRef
2805 get_dw_address(struct nir_to_llvm_context *ctx,
2806 LLVMValueRef dw_addr,
2807 unsigned param,
2808 unsigned const_index,
2809 bool compact_const_index,
2810 LLVMValueRef vertex_index,
2811 LLVMValueRef stride,
2812 LLVMValueRef indir_index)
2813
2814 {
2815
2816 if (vertex_index) {
2817 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2818 LLVMBuildMul(ctx->builder,
2819 vertex_index,
2820 stride, ""), "");
2821 }
2822
2823 if (indir_index)
2824 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2825 LLVMBuildMul(ctx->builder, indir_index,
2826 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2827 else if (const_index && !compact_const_index)
2828 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2829 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2830
2831 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2832 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2833
2834 if (const_index && compact_const_index)
2835 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2836 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2837 return dw_addr;
2838 }
2839
2840 static LLVMValueRef
2841 load_tcs_input(struct ac_shader_abi *abi,
2842 LLVMValueRef vertex_index,
2843 LLVMValueRef indir_index,
2844 unsigned const_index,
2845 unsigned location,
2846 unsigned driver_location,
2847 unsigned component,
2848 unsigned num_components,
2849 bool is_patch,
2850 bool is_compact)
2851 {
2852 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2853 LLVMValueRef dw_addr, stride;
2854 LLVMValueRef value[4], result;
2855 unsigned param = shader_io_get_unique_index(location);
2856
2857 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2858 dw_addr = get_tcs_in_current_patch_offset(ctx);
2859 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2860 indir_index);
2861
2862 for (unsigned i = 0; i < num_components + component; i++) {
2863 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2864 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2865 ctx->ac.i32_1, "");
2866 }
2867 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2868 return result;
2869 }
2870
2871 static LLVMValueRef
2872 load_tcs_output(struct nir_to_llvm_context *ctx,
2873 nir_intrinsic_instr *instr)
2874 {
2875 LLVMValueRef dw_addr;
2876 LLVMValueRef stride = NULL;
2877 LLVMValueRef value[4], result;
2878 LLVMValueRef vertex_index = NULL;
2879 LLVMValueRef indir_index = NULL;
2880 unsigned const_index = 0;
2881 unsigned param;
2882 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2883 const bool is_compact = instr->variables[0]->var->data.compact;
2884 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2885 get_deref_offset(ctx->nir, instr->variables[0],
2886 false, NULL, per_vertex ? &vertex_index : NULL,
2887 &const_index, &indir_index);
2888
2889 if (!instr->variables[0]->var->data.patch) {
2890 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2891 dw_addr = get_tcs_out_current_patch_offset(ctx);
2892 } else {
2893 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2894 }
2895
2896 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2897 indir_index);
2898
2899 unsigned comp = instr->variables[0]->var->data.location_frac;
2900 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2901 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2902 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2903 ctx->ac.i32_1, "");
2904 }
2905 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2906 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2907 return result;
2908 }
2909
2910 static void
2911 store_tcs_output(struct ac_shader_abi *abi,
2912 LLVMValueRef vertex_index,
2913 LLVMValueRef param_index,
2914 unsigned const_index,
2915 unsigned location,
2916 unsigned driver_location,
2917 LLVMValueRef src,
2918 unsigned component,
2919 bool is_patch,
2920 bool is_compact,
2921 unsigned writemask)
2922 {
2923 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2924 LLVMValueRef dw_addr;
2925 LLVMValueRef stride = NULL;
2926 LLVMValueRef buf_addr = NULL;
2927 unsigned param;
2928 bool store_lds = true;
2929
2930 if (is_patch) {
2931 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2932 store_lds = false;
2933 } else {
2934 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2935 store_lds = false;
2936 }
2937
2938 param = shader_io_get_unique_index(location);
2939 if (location == VARYING_SLOT_CLIP_DIST0 &&
2940 is_compact && const_index > 3) {
2941 const_index -= 3;
2942 param++;
2943 }
2944
2945 if (!is_patch) {
2946 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2947 dw_addr = get_tcs_out_current_patch_offset(ctx);
2948 } else {
2949 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2950 }
2951
2952 mark_tess_output(ctx, is_patch, param);
2953
2954 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2955 param_index);
2956 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2957 vertex_index, param_index);
2958
2959 bool is_tess_factor = false;
2960 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2961 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2962 is_tess_factor = true;
2963
2964 unsigned base = is_compact ? const_index : 0;
2965 for (unsigned chan = 0; chan < 8; chan++) {
2966 if (!(writemask & (1 << chan)))
2967 continue;
2968 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2969
2970 if (store_lds || is_tess_factor)
2971 ac_lds_store(&ctx->ac, dw_addr, value);
2972
2973 if (!is_tess_factor && writemask != 0xF)
2974 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2975 buf_addr, ctx->oc_lds,
2976 4 * (base + chan), 1, 0, true, false);
2977
2978 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2979 ctx->ac.i32_1, "");
2980 }
2981
2982 if (writemask == 0xF) {
2983 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2984 buf_addr, ctx->oc_lds,
2985 (base * 4), 1, 0, true, false);
2986 }
2987 }
2988
2989 static LLVMValueRef
2990 load_tes_input(struct ac_shader_abi *abi,
2991 LLVMValueRef vertex_index,
2992 LLVMValueRef param_index,
2993 unsigned const_index,
2994 unsigned location,
2995 unsigned driver_location,
2996 unsigned component,
2997 unsigned num_components,
2998 bool is_patch,
2999 bool is_compact)
3000 {
3001 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3002 LLVMValueRef buf_addr;
3003 LLVMValueRef result;
3004 unsigned param = shader_io_get_unique_index(location);
3005
3006 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3007 const_index -= 3;
3008 param++;
3009 }
3010
3011 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3012 is_compact, vertex_index, param_index);
3013
3014 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3015 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3016
3017 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3018 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3019 result = trim_vector(&ctx->ac, result, num_components);
3020 return result;
3021 }
3022
3023 static LLVMValueRef
3024 load_gs_input(struct ac_shader_abi *abi,
3025 unsigned location,
3026 unsigned driver_location,
3027 unsigned component,
3028 unsigned num_components,
3029 unsigned vertex_index,
3030 unsigned const_index,
3031 LLVMTypeRef type)
3032 {
3033 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3034 LLVMValueRef vtx_offset;
3035 LLVMValueRef args[9];
3036 unsigned param, vtx_offset_param;
3037 LLVMValueRef value[4], result;
3038
3039 vtx_offset_param = vertex_index;
3040 assert(vtx_offset_param < 6);
3041 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3042 LLVMConstInt(ctx->ac.i32, 4, false), "");
3043
3044 param = shader_io_get_unique_index(location);
3045
3046 for (unsigned i = component; i < num_components + component; i++) {
3047 if (ctx->ac.chip_class >= GFX9) {
3048 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3049 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3050 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3051 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3052 } else {
3053 args[0] = ctx->esgs_ring;
3054 args[1] = vtx_offset;
3055 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3056 args[3] = ctx->ac.i32_0;
3057 args[4] = ctx->ac.i32_1; /* OFFEN */
3058 args[5] = ctx->ac.i32_0; /* IDXEN */
3059 args[6] = ctx->ac.i32_1; /* GLC */
3060 args[7] = ctx->ac.i32_0; /* SLC */
3061 args[8] = ctx->ac.i32_0; /* TFE */
3062
3063 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3064 ctx->ac.i32, args, 9,
3065 AC_FUNC_ATTR_READONLY |
3066 AC_FUNC_ATTR_LEGACY);
3067 }
3068 }
3069 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3070
3071 return result;
3072 }
3073
3074 static LLVMValueRef
3075 build_gep_for_deref(struct ac_nir_context *ctx,
3076 nir_deref_var *deref)
3077 {
3078 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3079 assert(entry->data);
3080 LLVMValueRef val = entry->data;
3081 nir_deref *tail = deref->deref.child;
3082 while (tail != NULL) {
3083 LLVMValueRef offset;
3084 switch (tail->deref_type) {
3085 case nir_deref_type_array: {
3086 nir_deref_array *array = nir_deref_as_array(tail);
3087 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3088 if (array->deref_array_type ==
3089 nir_deref_array_type_indirect) {
3090 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3091 get_src(ctx,
3092 array->indirect),
3093 "");
3094 }
3095 break;
3096 }
3097 case nir_deref_type_struct: {
3098 nir_deref_struct *deref_struct =
3099 nir_deref_as_struct(tail);
3100 offset = LLVMConstInt(ctx->ac.i32,
3101 deref_struct->index, 0);
3102 break;
3103 }
3104 default:
3105 unreachable("bad deref type");
3106 }
3107 val = ac_build_gep0(&ctx->ac, val, offset);
3108 tail = tail->child;
3109 }
3110 return val;
3111 }
3112
3113 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3114 nir_intrinsic_instr *instr)
3115 {
3116 LLVMValueRef values[8];
3117 int idx = instr->variables[0]->var->data.driver_location;
3118 int ve = instr->dest.ssa.num_components;
3119 unsigned comp = instr->variables[0]->var->data.location_frac;
3120 LLVMValueRef indir_index;
3121 LLVMValueRef ret;
3122 unsigned const_index;
3123 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3124 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3125 instr->variables[0]->var->data.mode == nir_var_shader_in;
3126 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3127 &const_index, &indir_index);
3128
3129 if (instr->dest.ssa.bit_size == 64)
3130 ve *= 2;
3131
3132 switch (instr->variables[0]->var->data.mode) {
3133 case nir_var_shader_in:
3134 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3135 ctx->stage == MESA_SHADER_TESS_EVAL) {
3136 LLVMValueRef result;
3137 LLVMValueRef vertex_index = NULL;
3138 LLVMValueRef indir_index = NULL;
3139 unsigned const_index = 0;
3140 unsigned location = instr->variables[0]->var->data.location;
3141 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3142 const bool is_patch = instr->variables[0]->var->data.patch;
3143 const bool is_compact = instr->variables[0]->var->data.compact;
3144
3145 get_deref_offset(ctx, instr->variables[0],
3146 false, NULL, is_patch ? NULL : &vertex_index,
3147 &const_index, &indir_index);
3148
3149 result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, indir_index,
3150 const_index, location, driver_location,
3151 instr->variables[0]->var->data.location_frac,
3152 instr->num_components,
3153 is_patch, is_compact);
3154 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3155 }
3156
3157 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3158 LLVMValueRef indir_index;
3159 unsigned const_index, vertex_index;
3160 get_deref_offset(ctx, instr->variables[0],
3161 false, &vertex_index, NULL,
3162 &const_index, &indir_index);
3163 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3164 instr->variables[0]->var->data.driver_location,
3165 instr->variables[0]->var->data.location_frac, ve,
3166 vertex_index, const_index,
3167 nir2llvmtype(ctx, instr->variables[0]->var->type));
3168 }
3169
3170 for (unsigned chan = comp; chan < ve + comp; chan++) {
3171 if (indir_index) {
3172 unsigned count = glsl_count_attribute_slots(
3173 instr->variables[0]->var->type,
3174 ctx->stage == MESA_SHADER_VERTEX);
3175 count -= chan / 4;
3176 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3177 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3178 stride, false, true);
3179
3180 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3181 tmp_vec,
3182 indir_index, "");
3183 } else
3184 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3185 }
3186 break;
3187 case nir_var_local:
3188 for (unsigned chan = 0; chan < ve; chan++) {
3189 if (indir_index) {
3190 unsigned count = glsl_count_attribute_slots(
3191 instr->variables[0]->var->type, false);
3192 count -= chan / 4;
3193 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3194 &ctx->ac, ctx->locals + idx + chan, count,
3195 stride, true, true);
3196
3197 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3198 tmp_vec,
3199 indir_index, "");
3200 } else {
3201 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3202 }
3203 }
3204 break;
3205 case nir_var_shared: {
3206 LLVMValueRef address = build_gep_for_deref(ctx,
3207 instr->variables[0]);
3208 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3209 return LLVMBuildBitCast(ctx->ac.builder, val,
3210 get_def_type(ctx, &instr->dest.ssa),
3211 "");
3212 }
3213 case nir_var_shader_out:
3214 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3215 return load_tcs_output(ctx->nctx, instr);
3216
3217 for (unsigned chan = comp; chan < ve + comp; chan++) {
3218 if (indir_index) {
3219 unsigned count = glsl_count_attribute_slots(
3220 instr->variables[0]->var->type, false);
3221 count -= chan / 4;
3222 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3223 &ctx->ac, ctx->outputs + idx + chan, count,
3224 stride, true, true);
3225
3226 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3227 tmp_vec,
3228 indir_index, "");
3229 } else {
3230 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3231 ctx->outputs[idx + chan + const_index * stride],
3232 "");
3233 }
3234 }
3235 break;
3236 default:
3237 unreachable("unhandle variable mode");
3238 }
3239 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3240 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3241 }
3242
3243 static void
3244 visit_store_var(struct ac_nir_context *ctx,
3245 nir_intrinsic_instr *instr)
3246 {
3247 LLVMValueRef temp_ptr, value;
3248 int idx = instr->variables[0]->var->data.driver_location;
3249 unsigned comp = instr->variables[0]->var->data.location_frac;
3250 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3251 int writemask = instr->const_index[0] << comp;
3252 LLVMValueRef indir_index;
3253 unsigned const_index;
3254 get_deref_offset(ctx, instr->variables[0], false,
3255 NULL, NULL, &const_index, &indir_index);
3256
3257 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3258 int old_writemask = writemask;
3259
3260 src = LLVMBuildBitCast(ctx->ac.builder, src,
3261 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3262 "");
3263
3264 writemask = 0;
3265 for (unsigned chan = 0; chan < 4; chan++) {
3266 if (old_writemask & (1 << chan))
3267 writemask |= 3u << (2 * chan);
3268 }
3269 }
3270
3271 switch (instr->variables[0]->var->data.mode) {
3272 case nir_var_shader_out:
3273
3274 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3275 LLVMValueRef vertex_index = NULL;
3276 LLVMValueRef indir_index = NULL;
3277 unsigned const_index = 0;
3278 const unsigned location = instr->variables[0]->var->data.location;
3279 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3280 const unsigned comp = instr->variables[0]->var->data.location_frac;
3281 const bool is_patch = instr->variables[0]->var->data.patch;
3282 const bool is_compact = instr->variables[0]->var->data.compact;
3283
3284 get_deref_offset(ctx, instr->variables[0],
3285 false, NULL, is_patch ? NULL : &vertex_index,
3286 &const_index, &indir_index);
3287
3288 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3289 const_index, location, driver_location,
3290 src, comp, is_patch, is_compact, writemask);
3291 return;
3292 }
3293
3294 for (unsigned chan = 0; chan < 8; chan++) {
3295 int stride = 4;
3296 if (!(writemask & (1 << chan)))
3297 continue;
3298
3299 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3300
3301 if (instr->variables[0]->var->data.compact)
3302 stride = 1;
3303 if (indir_index) {
3304 unsigned count = glsl_count_attribute_slots(
3305 instr->variables[0]->var->type, false);
3306 count -= chan / 4;
3307 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3308 &ctx->ac, ctx->outputs + idx + chan, count,
3309 stride, true, true);
3310
3311 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3312 value, indir_index, "");
3313 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3314 count, stride, tmp_vec);
3315
3316 } else {
3317 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3318
3319 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3320 }
3321 }
3322 break;
3323 case nir_var_local:
3324 for (unsigned chan = 0; chan < 8; chan++) {
3325 if (!(writemask & (1 << chan)))
3326 continue;
3327
3328 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3329 if (indir_index) {
3330 unsigned count = glsl_count_attribute_slots(
3331 instr->variables[0]->var->type, false);
3332 count -= chan / 4;
3333 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3334 &ctx->ac, ctx->locals + idx + chan, count,
3335 4, true, true);
3336
3337 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3338 value, indir_index, "");
3339 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3340 count, 4, tmp_vec);
3341 } else {
3342 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3343
3344 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3345 }
3346 }
3347 break;
3348 case nir_var_shared: {
3349 int writemask = instr->const_index[0];
3350 LLVMValueRef address = build_gep_for_deref(ctx,
3351 instr->variables[0]);
3352 LLVMValueRef val = get_src(ctx, instr->src[0]);
3353 unsigned components =
3354 glsl_get_vector_elements(
3355 nir_deref_tail(&instr->variables[0]->deref)->type);
3356 if (writemask == (1 << components) - 1) {
3357 val = LLVMBuildBitCast(
3358 ctx->ac.builder, val,
3359 LLVMGetElementType(LLVMTypeOf(address)), "");
3360 LLVMBuildStore(ctx->ac.builder, val, address);
3361 } else {
3362 for (unsigned chan = 0; chan < 4; chan++) {
3363 if (!(writemask & (1 << chan)))
3364 continue;
3365 LLVMValueRef ptr =
3366 LLVMBuildStructGEP(ctx->ac.builder,
3367 address, chan, "");
3368 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3369 chan);
3370 src = LLVMBuildBitCast(
3371 ctx->ac.builder, src,
3372 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3373 LLVMBuildStore(ctx->ac.builder, src, ptr);
3374 }
3375 }
3376 break;
3377 }
3378 default:
3379 break;
3380 }
3381 }
3382
3383 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3384 {
3385 switch (dim) {
3386 case GLSL_SAMPLER_DIM_BUF:
3387 return 1;
3388 case GLSL_SAMPLER_DIM_1D:
3389 return array ? 2 : 1;
3390 case GLSL_SAMPLER_DIM_2D:
3391 return array ? 3 : 2;
3392 case GLSL_SAMPLER_DIM_MS:
3393 return array ? 4 : 3;
3394 case GLSL_SAMPLER_DIM_3D:
3395 case GLSL_SAMPLER_DIM_CUBE:
3396 return 3;
3397 case GLSL_SAMPLER_DIM_RECT:
3398 case GLSL_SAMPLER_DIM_SUBPASS:
3399 return 2;
3400 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3401 return 3;
3402 default:
3403 break;
3404 }
3405 return 0;
3406 }
3407
3408
3409
3410 /* Adjust the sample index according to FMASK.
3411 *
3412 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3413 * which is the identity mapping. Each nibble says which physical sample
3414 * should be fetched to get that sample.
3415 *
3416 * For example, 0x11111100 means there are only 2 samples stored and
3417 * the second sample covers 3/4 of the pixel. When reading samples 0
3418 * and 1, return physical sample 0 (determined by the first two 0s
3419 * in FMASK), otherwise return physical sample 1.
3420 *
3421 * The sample index should be adjusted as follows:
3422 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3423 */
3424 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3425 LLVMValueRef coord_x, LLVMValueRef coord_y,
3426 LLVMValueRef coord_z,
3427 LLVMValueRef sample_index,
3428 LLVMValueRef fmask_desc_ptr)
3429 {
3430 LLVMValueRef fmask_load_address[4];
3431 LLVMValueRef res;
3432
3433 fmask_load_address[0] = coord_x;
3434 fmask_load_address[1] = coord_y;
3435 if (coord_z) {
3436 fmask_load_address[2] = coord_z;
3437 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3438 }
3439
3440 struct ac_image_args args = {0};
3441
3442 args.opcode = ac_image_load;
3443 args.da = coord_z ? true : false;
3444 args.resource = fmask_desc_ptr;
3445 args.dmask = 0xf;
3446 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3447
3448 res = ac_build_image_opcode(ctx, &args);
3449
3450 res = ac_to_integer(ctx, res);
3451 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3452 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3453
3454 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3455 res,
3456 ctx->i32_0, "");
3457
3458 LLVMValueRef sample_index4 =
3459 LLVMBuildMul(ctx->builder, sample_index, four, "");
3460 LLVMValueRef shifted_fmask =
3461 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3462 LLVMValueRef final_sample =
3463 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3464
3465 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3466 * resource descriptor is 0 (invalid),
3467 */
3468 LLVMValueRef fmask_desc =
3469 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3470 ctx->v8i32, "");
3471
3472 LLVMValueRef fmask_word1 =
3473 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3474 ctx->i32_1, "");
3475
3476 LLVMValueRef word1_is_nonzero =
3477 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3478 fmask_word1, ctx->i32_0, "");
3479
3480 /* Replace the MSAA sample index. */
3481 sample_index =
3482 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3483 final_sample, sample_index, "");
3484 return sample_index;
3485 }
3486
3487 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3488 const nir_intrinsic_instr *instr)
3489 {
3490 const struct glsl_type *type = instr->variables[0]->var->type;
3491 if(instr->variables[0]->deref.child)
3492 type = instr->variables[0]->deref.child->type;
3493
3494 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3495 LLVMValueRef coords[4];
3496 LLVMValueRef masks[] = {
3497 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3498 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3499 };
3500 LLVMValueRef res;
3501 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3502
3503 int count;
3504 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3505 bool is_array = glsl_sampler_type_is_array(type);
3506 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3507 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3508 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3509 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3510 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3511 count = image_type_to_components_count(dim, is_array);
3512
3513 if (is_ms) {
3514 LLVMValueRef fmask_load_address[3];
3515 int chan;
3516
3517 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3518 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3519 if (is_array)
3520 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3521 else
3522 fmask_load_address[2] = NULL;
3523 if (add_frag_pos) {
3524 for (chan = 0; chan < 2; ++chan)
3525 fmask_load_address[chan] =
3526 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3527 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3528 ctx->ac.i32, ""), "");
3529 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3530 }
3531 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3532 fmask_load_address[0],
3533 fmask_load_address[1],
3534 fmask_load_address[2],
3535 sample_index,
3536 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3537 }
3538 if (count == 1 && !gfx9_1d) {
3539 if (instr->src[0].ssa->num_components)
3540 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3541 else
3542 res = src0;
3543 } else {
3544 int chan;
3545 if (is_ms)
3546 count--;
3547 for (chan = 0; chan < count; ++chan) {
3548 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3549 }
3550 if (add_frag_pos) {
3551 for (chan = 0; chan < 2; ++chan)
3552 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3553 ctx->ac.i32, ""), "");
3554 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3555 count++;
3556 }
3557
3558 if (gfx9_1d) {
3559 if (is_array) {
3560 coords[2] = coords[1];
3561 coords[1] = ctx->ac.i32_0;
3562 } else
3563 coords[1] = ctx->ac.i32_0;
3564 count++;
3565 }
3566
3567 if (is_ms) {
3568 coords[count] = sample_index;
3569 count++;
3570 }
3571
3572 if (count == 3) {
3573 coords[3] = LLVMGetUndef(ctx->ac.i32);
3574 count = 4;
3575 }
3576 res = ac_build_gather_values(&ctx->ac, coords, count);
3577 }
3578 return res;
3579 }
3580
3581 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3582 const nir_intrinsic_instr *instr)
3583 {
3584 LLVMValueRef params[7];
3585 LLVMValueRef res;
3586 char intrinsic_name[64];
3587 const nir_variable *var = instr->variables[0]->var;
3588 const struct glsl_type *type = var->type;
3589
3590 if(instr->variables[0]->deref.child)
3591 type = instr->variables[0]->deref.child->type;
3592
3593 type = glsl_without_array(type);
3594 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3595 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3596 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3597 ctx->ac.i32_0, ""); /* vindex */
3598 params[2] = ctx->ac.i32_0; /* voffset */
3599 params[3] = ctx->ac.i1false; /* glc */
3600 params[4] = ctx->ac.i1false; /* slc */
3601 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3602 params, 5, 0);
3603
3604 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3605 res = ac_to_integer(&ctx->ac, res);
3606 } else {
3607 bool is_da = glsl_sampler_type_is_array(type) ||
3608 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3609 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3610 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3611 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3612 LLVMValueRef glc = ctx->ac.i1false;
3613 LLVMValueRef slc = ctx->ac.i1false;
3614
3615 params[0] = get_image_coords(ctx, instr);
3616 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3617 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3618 if (HAVE_LLVM <= 0x0309) {
3619 params[3] = ctx->ac.i1false; /* r128 */
3620 params[4] = da;
3621 params[5] = glc;
3622 params[6] = slc;
3623 } else {
3624 LLVMValueRef lwe = ctx->ac.i1false;
3625 params[3] = glc;
3626 params[4] = slc;
3627 params[5] = lwe;
3628 params[6] = da;
3629 }
3630
3631 ac_get_image_intr_name("llvm.amdgcn.image.load",
3632 ctx->ac.v4f32, /* vdata */
3633 LLVMTypeOf(params[0]), /* coords */
3634 LLVMTypeOf(params[1]), /* rsrc */
3635 intrinsic_name, sizeof(intrinsic_name));
3636
3637 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3638 params, 7, AC_FUNC_ATTR_READONLY);
3639 }
3640 return ac_to_integer(&ctx->ac, res);
3641 }
3642
3643 static void visit_image_store(struct ac_nir_context *ctx,
3644 nir_intrinsic_instr *instr)
3645 {
3646 LLVMValueRef params[8];
3647 char intrinsic_name[64];
3648 const nir_variable *var = instr->variables[0]->var;
3649 const struct glsl_type *type = glsl_without_array(var->type);
3650 LLVMValueRef glc = ctx->ac.i1false;
3651 bool force_glc = ctx->ac.chip_class == SI;
3652 if (force_glc)
3653 glc = ctx->ac.i1true;
3654
3655 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3656 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3657 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3658 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3659 ctx->ac.i32_0, ""); /* vindex */
3660 params[3] = ctx->ac.i32_0; /* voffset */
3661 params[4] = glc; /* glc */
3662 params[5] = ctx->ac.i1false; /* slc */
3663 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3664 params, 6, 0);
3665 } else {
3666 bool is_da = glsl_sampler_type_is_array(type) ||
3667 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3668 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3669 LLVMValueRef slc = ctx->ac.i1false;
3670
3671 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3672 params[1] = get_image_coords(ctx, instr); /* coords */
3673 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3674 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3675 if (HAVE_LLVM <= 0x0309) {
3676 params[4] = ctx->ac.i1false; /* r128 */
3677 params[5] = da;
3678 params[6] = glc;
3679 params[7] = slc;
3680 } else {
3681 LLVMValueRef lwe = ctx->ac.i1false;
3682 params[4] = glc;
3683 params[5] = slc;
3684 params[6] = lwe;
3685 params[7] = da;
3686 }
3687
3688 ac_get_image_intr_name("llvm.amdgcn.image.store",
3689 LLVMTypeOf(params[0]), /* vdata */
3690 LLVMTypeOf(params[1]), /* coords */
3691 LLVMTypeOf(params[2]), /* rsrc */
3692 intrinsic_name, sizeof(intrinsic_name));
3693
3694 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3695 params, 8, 0);
3696 }
3697
3698 }
3699
3700 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3701 const nir_intrinsic_instr *instr)
3702 {
3703 LLVMValueRef params[7];
3704 int param_count = 0;
3705 const nir_variable *var = instr->variables[0]->var;
3706
3707 const char *atomic_name;
3708 char intrinsic_name[41];
3709 const struct glsl_type *type = glsl_without_array(var->type);
3710 MAYBE_UNUSED int length;
3711
3712 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3713
3714 switch (instr->intrinsic) {
3715 case nir_intrinsic_image_atomic_add:
3716 atomic_name = "add";
3717 break;
3718 case nir_intrinsic_image_atomic_min:
3719 atomic_name = is_unsigned ? "umin" : "smin";
3720 break;
3721 case nir_intrinsic_image_atomic_max:
3722 atomic_name = is_unsigned ? "umax" : "smax";
3723 break;
3724 case nir_intrinsic_image_atomic_and:
3725 atomic_name = "and";
3726 break;
3727 case nir_intrinsic_image_atomic_or:
3728 atomic_name = "or";
3729 break;
3730 case nir_intrinsic_image_atomic_xor:
3731 atomic_name = "xor";
3732 break;
3733 case nir_intrinsic_image_atomic_exchange:
3734 atomic_name = "swap";
3735 break;
3736 case nir_intrinsic_image_atomic_comp_swap:
3737 atomic_name = "cmpswap";
3738 break;
3739 default:
3740 abort();
3741 }
3742
3743 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3744 params[param_count++] = get_src(ctx, instr->src[3]);
3745 params[param_count++] = get_src(ctx, instr->src[2]);
3746
3747 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3748 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3749 NULL, true, true);
3750 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3751 ctx->ac.i32_0, ""); /* vindex */
3752 params[param_count++] = ctx->ac.i32_0; /* voffset */
3753 params[param_count++] = ctx->ac.i1false; /* slc */
3754
3755 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3756 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3757 } else {
3758 char coords_type[8];
3759
3760 bool da = glsl_sampler_type_is_array(type) ||
3761 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3762
3763 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3764 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3765 NULL, true, true);
3766 params[param_count++] = ctx->ac.i1false; /* r128 */
3767 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3768 params[param_count++] = ctx->ac.i1false; /* slc */
3769
3770 build_int_type_name(LLVMTypeOf(coords),
3771 coords_type, sizeof(coords_type));
3772
3773 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3774 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3775 }
3776
3777 assert(length < sizeof(intrinsic_name));
3778 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3779 }
3780
3781 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3782 const nir_intrinsic_instr *instr)
3783 {
3784 LLVMValueRef res;
3785 const nir_variable *var = instr->variables[0]->var;
3786 const struct glsl_type *type = instr->variables[0]->var->type;
3787 bool da = glsl_sampler_type_is_array(var->type) ||
3788 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3789 if(instr->variables[0]->deref.child)
3790 type = instr->variables[0]->deref.child->type;
3791
3792 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3793 return get_buffer_size(ctx,
3794 get_sampler_desc(ctx, instr->variables[0],
3795 AC_DESC_BUFFER, NULL, true, false), true);
3796
3797 struct ac_image_args args = { 0 };
3798
3799 args.da = da;
3800 args.dmask = 0xf;
3801 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3802 args.opcode = ac_image_get_resinfo;
3803 args.addr = ctx->ac.i32_0;
3804
3805 res = ac_build_image_opcode(&ctx->ac, &args);
3806
3807 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3808
3809 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3810 glsl_sampler_type_is_array(type)) {
3811 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3812 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3813 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3814 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3815 }
3816 if (ctx->ac.chip_class >= GFX9 &&
3817 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3818 glsl_sampler_type_is_array(type)) {
3819 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3820 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3821 ctx->ac.i32_1, "");
3822
3823 }
3824 return res;
3825 }
3826
3827 #define NOOP_WAITCNT 0xf7f
3828 #define LGKM_CNT 0x07f
3829 #define VM_CNT 0xf70
3830
3831 static void emit_membar(struct nir_to_llvm_context *ctx,
3832 const nir_intrinsic_instr *instr)
3833 {
3834 unsigned waitcnt = NOOP_WAITCNT;
3835
3836 switch (instr->intrinsic) {
3837 case nir_intrinsic_memory_barrier:
3838 case nir_intrinsic_group_memory_barrier:
3839 waitcnt &= VM_CNT & LGKM_CNT;
3840 break;
3841 case nir_intrinsic_memory_barrier_atomic_counter:
3842 case nir_intrinsic_memory_barrier_buffer:
3843 case nir_intrinsic_memory_barrier_image:
3844 waitcnt &= VM_CNT;
3845 break;
3846 case nir_intrinsic_memory_barrier_shared:
3847 waitcnt &= LGKM_CNT;
3848 break;
3849 default:
3850 break;
3851 }
3852 if (waitcnt != NOOP_WAITCNT)
3853 ac_build_waitcnt(&ctx->ac, waitcnt);
3854 }
3855
3856 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3857 {
3858 /* SI only (thanks to a hw bug workaround):
3859 * The real barrier instruction isn’t needed, because an entire patch
3860 * always fits into a single wave.
3861 */
3862 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3863 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3864 return;
3865 }
3866 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3867 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3868 }
3869
3870 static void emit_discard(struct ac_nir_context *ctx,
3871 const nir_intrinsic_instr *instr)
3872 {
3873 LLVMValueRef cond;
3874
3875 if (instr->intrinsic == nir_intrinsic_discard_if) {
3876 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3877 get_src(ctx, instr->src[0]),
3878 ctx->ac.i32_0, "");
3879 } else {
3880 assert(instr->intrinsic == nir_intrinsic_discard);
3881 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3882 }
3883
3884 ac_build_kill_if_false(&ctx->ac, cond);
3885 }
3886
3887 static LLVMValueRef
3888 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3889 {
3890 LLVMValueRef result;
3891 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3892 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3893 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3894
3895 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3896 }
3897
3898 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3899 const nir_intrinsic_instr *instr)
3900 {
3901 LLVMValueRef ptr, result;
3902 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3903 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3904
3905 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3906 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3907 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3908 ptr, src, src1,
3909 LLVMAtomicOrderingSequentiallyConsistent,
3910 LLVMAtomicOrderingSequentiallyConsistent,
3911 false);
3912 } else {
3913 LLVMAtomicRMWBinOp op;
3914 switch (instr->intrinsic) {
3915 case nir_intrinsic_var_atomic_add:
3916 op = LLVMAtomicRMWBinOpAdd;
3917 break;
3918 case nir_intrinsic_var_atomic_umin:
3919 op = LLVMAtomicRMWBinOpUMin;
3920 break;
3921 case nir_intrinsic_var_atomic_umax:
3922 op = LLVMAtomicRMWBinOpUMax;
3923 break;
3924 case nir_intrinsic_var_atomic_imin:
3925 op = LLVMAtomicRMWBinOpMin;
3926 break;
3927 case nir_intrinsic_var_atomic_imax:
3928 op = LLVMAtomicRMWBinOpMax;
3929 break;
3930 case nir_intrinsic_var_atomic_and:
3931 op = LLVMAtomicRMWBinOpAnd;
3932 break;
3933 case nir_intrinsic_var_atomic_or:
3934 op = LLVMAtomicRMWBinOpOr;
3935 break;
3936 case nir_intrinsic_var_atomic_xor:
3937 op = LLVMAtomicRMWBinOpXor;
3938 break;
3939 case nir_intrinsic_var_atomic_exchange:
3940 op = LLVMAtomicRMWBinOpXchg;
3941 break;
3942 default:
3943 return NULL;
3944 }
3945
3946 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3947 LLVMAtomicOrderingSequentiallyConsistent,
3948 false);
3949 }
3950 return result;
3951 }
3952
3953 #define INTERP_CENTER 0
3954 #define INTERP_CENTROID 1
3955 #define INTERP_SAMPLE 2
3956
3957 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3958 enum glsl_interp_mode interp, unsigned location)
3959 {
3960 switch (interp) {
3961 case INTERP_MODE_FLAT:
3962 default:
3963 return NULL;
3964 case INTERP_MODE_SMOOTH:
3965 case INTERP_MODE_NONE:
3966 if (location == INTERP_CENTER)
3967 return ctx->persp_center;
3968 else if (location == INTERP_CENTROID)
3969 return ctx->persp_centroid;
3970 else if (location == INTERP_SAMPLE)
3971 return ctx->persp_sample;
3972 break;
3973 case INTERP_MODE_NOPERSPECTIVE:
3974 if (location == INTERP_CENTER)
3975 return ctx->linear_center;
3976 else if (location == INTERP_CENTROID)
3977 return ctx->linear_centroid;
3978 else if (location == INTERP_SAMPLE)
3979 return ctx->linear_sample;
3980 break;
3981 }
3982 return NULL;
3983 }
3984
3985 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3986 LLVMValueRef sample_id)
3987 {
3988 LLVMValueRef result;
3989 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3990
3991 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3992 const_array(ctx->ac.v2f32, 64), "");
3993
3994 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3995 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3996
3997 return result;
3998 }
3999
4000 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4001 {
4002 LLVMValueRef values[2];
4003
4004 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
4005 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
4006 return ac_build_gather_values(&ctx->ac, values, 2);
4007 }
4008
4009 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
4010 const nir_intrinsic_instr *instr)
4011 {
4012 LLVMValueRef result[4];
4013 LLVMValueRef interp_param, attr_number;
4014 unsigned location;
4015 unsigned chan;
4016 LLVMValueRef src_c0 = NULL;
4017 LLVMValueRef src_c1 = NULL;
4018 LLVMValueRef src0 = NULL;
4019 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4020 switch (instr->intrinsic) {
4021 case nir_intrinsic_interp_var_at_centroid:
4022 location = INTERP_CENTROID;
4023 break;
4024 case nir_intrinsic_interp_var_at_sample:
4025 case nir_intrinsic_interp_var_at_offset:
4026 location = INTERP_CENTER;
4027 src0 = get_src(ctx->nir, instr->src[0]);
4028 break;
4029 default:
4030 break;
4031 }
4032
4033 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4034 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4035 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4036 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4037 LLVMValueRef sample_position;
4038 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4039
4040 /* fetch sample ID */
4041 sample_position = load_sample_position(ctx, src0);
4042
4043 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4044 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4045 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4046 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4047 }
4048 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4049 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4050
4051 if (location == INTERP_CENTER) {
4052 LLVMValueRef ij_out[2];
4053 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4054
4055 /*
4056 * take the I then J parameters, and the DDX/Y for it, and
4057 * calculate the IJ inputs for the interpolator.
4058 * temp1 = ddx * offset/sample.x + I;
4059 * interp_param.I = ddy * offset/sample.y + temp1;
4060 * temp1 = ddx * offset/sample.x + J;
4061 * interp_param.J = ddy * offset/sample.y + temp1;
4062 */
4063 for (unsigned i = 0; i < 2; i++) {
4064 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4065 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4066 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4067 ddxy_out, ix_ll, "");
4068 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4069 ddxy_out, iy_ll, "");
4070 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4071 interp_param, ix_ll, "");
4072 LLVMValueRef temp1, temp2;
4073
4074 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4075 ctx->ac.f32, "");
4076
4077 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4078 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4079
4080 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4081 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4082
4083 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4084 temp2, ctx->ac.i32, "");
4085 }
4086 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4087
4088 }
4089
4090 for (chan = 0; chan < 4; chan++) {
4091 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4092
4093 if (interp_param) {
4094 interp_param = LLVMBuildBitCast(ctx->builder,
4095 interp_param, ctx->ac.v2f32, "");
4096 LLVMValueRef i = LLVMBuildExtractElement(
4097 ctx->builder, interp_param, ctx->ac.i32_0, "");
4098 LLVMValueRef j = LLVMBuildExtractElement(
4099 ctx->builder, interp_param, ctx->ac.i32_1, "");
4100
4101 result[chan] = ac_build_fs_interp(&ctx->ac,
4102 llvm_chan, attr_number,
4103 ctx->prim_mask, i, j);
4104 } else {
4105 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4106 LLVMConstInt(ctx->ac.i32, 2, false),
4107 llvm_chan, attr_number,
4108 ctx->prim_mask);
4109 }
4110 }
4111 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4112 instr->variables[0]->var->data.location_frac);
4113 }
4114
4115 static void
4116 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4117 {
4118 LLVMValueRef gs_next_vertex;
4119 LLVMValueRef can_emit;
4120 int idx;
4121 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4122
4123 /* Write vertex attribute values to GSVS ring */
4124 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4125 ctx->gs_next_vertex,
4126 "");
4127
4128 /* If this thread has already emitted the declared maximum number of
4129 * vertices, kill it: excessive vertex emissions are not supposed to
4130 * have any effect, and GS threads have no externally observable
4131 * effects other than emitting vertices.
4132 */
4133 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4134 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4135 ac_build_kill_if_false(&ctx->ac, can_emit);
4136
4137 /* loop num outputs */
4138 idx = 0;
4139 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4140 LLVMValueRef *out_ptr = &addrs[i * 4];
4141 int length = 4;
4142 int slot = idx;
4143 int slot_inc = 1;
4144
4145 if (!(ctx->output_mask & (1ull << i)))
4146 continue;
4147
4148 if (i == VARYING_SLOT_CLIP_DIST0) {
4149 /* pack clip and cull into a single set of slots */
4150 length = ctx->num_output_clips + ctx->num_output_culls;
4151 if (length > 4)
4152 slot_inc = 2;
4153 }
4154 for (unsigned j = 0; j < length; j++) {
4155 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4156 out_ptr[j], "");
4157 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4158 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4159 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4160
4161 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4162
4163 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4164 out_val, 1,
4165 voffset, ctx->gs2vs_offset, 0,
4166 1, 1, true, true);
4167 }
4168 idx += slot_inc;
4169 }
4170
4171 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4172 ctx->ac.i32_1, "");
4173 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4174
4175 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4176 }
4177
4178 static void
4179 visit_end_primitive(struct nir_to_llvm_context *ctx,
4180 const nir_intrinsic_instr *instr)
4181 {
4182 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4183 }
4184
4185 static LLVMValueRef
4186 load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
4187 unsigned num_components)
4188 {
4189 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4190
4191 LLVMValueRef coord[4] = {
4192 ctx->tes_u,
4193 ctx->tes_v,
4194 ctx->ac.f32_0,
4195 ctx->ac.f32_0,
4196 };
4197
4198 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4199 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4200 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4201
4202 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, num_components);
4203 return LLVMBuildBitCast(ctx->builder, result, type, "");
4204 }
4205
4206 static LLVMValueRef
4207 load_patch_vertices_in(struct ac_shader_abi *abi)
4208 {
4209 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4210 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4211 }
4212
4213 static void visit_intrinsic(struct ac_nir_context *ctx,
4214 nir_intrinsic_instr *instr)
4215 {
4216 LLVMValueRef result = NULL;
4217
4218 switch (instr->intrinsic) {
4219 case nir_intrinsic_load_work_group_id: {
4220 LLVMValueRef values[3];
4221
4222 for (int i = 0; i < 3; i++) {
4223 values[i] = ctx->nctx->workgroup_ids[i] ?
4224 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4225 }
4226
4227 result = ac_build_gather_values(&ctx->ac, values, 3);
4228 break;
4229 }
4230 case nir_intrinsic_load_base_vertex: {
4231 result = ctx->abi->base_vertex;
4232 break;
4233 }
4234 case nir_intrinsic_load_vertex_id_zero_base: {
4235 result = ctx->abi->vertex_id;
4236 break;
4237 }
4238 case nir_intrinsic_load_local_invocation_id: {
4239 result = ctx->nctx->local_invocation_ids;
4240 break;
4241 }
4242 case nir_intrinsic_load_base_instance:
4243 result = ctx->abi->start_instance;
4244 break;
4245 case nir_intrinsic_load_draw_id:
4246 result = ctx->abi->draw_id;
4247 break;
4248 case nir_intrinsic_load_view_index:
4249 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4250 break;
4251 case nir_intrinsic_load_invocation_id:
4252 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4253 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4254 else
4255 result = ctx->abi->gs_invocation_id;
4256 break;
4257 case nir_intrinsic_load_primitive_id:
4258 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4259 result = ctx->abi->gs_prim_id;
4260 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4261 result = ctx->abi->tcs_patch_id;
4262 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4263 result = ctx->abi->tes_patch_id;
4264 } else
4265 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4266 break;
4267 case nir_intrinsic_load_sample_id:
4268 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4269 break;
4270 case nir_intrinsic_load_sample_pos:
4271 result = load_sample_pos(ctx);
4272 break;
4273 case nir_intrinsic_load_sample_mask_in:
4274 result = ctx->abi->sample_coverage;
4275 break;
4276 case nir_intrinsic_load_frag_coord: {
4277 LLVMValueRef values[4] = {
4278 ctx->abi->frag_pos[0],
4279 ctx->abi->frag_pos[1],
4280 ctx->abi->frag_pos[2],
4281 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4282 };
4283 result = ac_build_gather_values(&ctx->ac, values, 4);
4284 break;
4285 }
4286 case nir_intrinsic_load_front_face:
4287 result = ctx->abi->front_face;
4288 break;
4289 case nir_intrinsic_load_instance_id:
4290 result = ctx->abi->instance_id;
4291 break;
4292 case nir_intrinsic_load_num_work_groups:
4293 result = ctx->nctx->num_work_groups;
4294 break;
4295 case nir_intrinsic_load_local_invocation_index:
4296 result = visit_load_local_invocation_index(ctx->nctx);
4297 break;
4298 case nir_intrinsic_load_push_constant:
4299 result = visit_load_push_constant(ctx->nctx, instr);
4300 break;
4301 case nir_intrinsic_vulkan_resource_index:
4302 result = visit_vulkan_resource_index(ctx->nctx, instr);
4303 break;
4304 case nir_intrinsic_vulkan_resource_reindex:
4305 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4306 break;
4307 case nir_intrinsic_store_ssbo:
4308 visit_store_ssbo(ctx, instr);
4309 break;
4310 case nir_intrinsic_load_ssbo:
4311 result = visit_load_buffer(ctx, instr);
4312 break;
4313 case nir_intrinsic_ssbo_atomic_add:
4314 case nir_intrinsic_ssbo_atomic_imin:
4315 case nir_intrinsic_ssbo_atomic_umin:
4316 case nir_intrinsic_ssbo_atomic_imax:
4317 case nir_intrinsic_ssbo_atomic_umax:
4318 case nir_intrinsic_ssbo_atomic_and:
4319 case nir_intrinsic_ssbo_atomic_or:
4320 case nir_intrinsic_ssbo_atomic_xor:
4321 case nir_intrinsic_ssbo_atomic_exchange:
4322 case nir_intrinsic_ssbo_atomic_comp_swap:
4323 result = visit_atomic_ssbo(ctx, instr);
4324 break;
4325 case nir_intrinsic_load_ubo:
4326 result = visit_load_ubo_buffer(ctx, instr);
4327 break;
4328 case nir_intrinsic_get_buffer_size:
4329 result = visit_get_buffer_size(ctx, instr);
4330 break;
4331 case nir_intrinsic_load_var:
4332 result = visit_load_var(ctx, instr);
4333 break;
4334 case nir_intrinsic_store_var:
4335 visit_store_var(ctx, instr);
4336 break;
4337 case nir_intrinsic_image_load:
4338 result = visit_image_load(ctx, instr);
4339 break;
4340 case nir_intrinsic_image_store:
4341 visit_image_store(ctx, instr);
4342 break;
4343 case nir_intrinsic_image_atomic_add:
4344 case nir_intrinsic_image_atomic_min:
4345 case nir_intrinsic_image_atomic_max:
4346 case nir_intrinsic_image_atomic_and:
4347 case nir_intrinsic_image_atomic_or:
4348 case nir_intrinsic_image_atomic_xor:
4349 case nir_intrinsic_image_atomic_exchange:
4350 case nir_intrinsic_image_atomic_comp_swap:
4351 result = visit_image_atomic(ctx, instr);
4352 break;
4353 case nir_intrinsic_image_size:
4354 result = visit_image_size(ctx, instr);
4355 break;
4356 case nir_intrinsic_discard:
4357 case nir_intrinsic_discard_if:
4358 emit_discard(ctx, instr);
4359 break;
4360 case nir_intrinsic_memory_barrier:
4361 case nir_intrinsic_group_memory_barrier:
4362 case nir_intrinsic_memory_barrier_atomic_counter:
4363 case nir_intrinsic_memory_barrier_buffer:
4364 case nir_intrinsic_memory_barrier_image:
4365 case nir_intrinsic_memory_barrier_shared:
4366 emit_membar(ctx->nctx, instr);
4367 break;
4368 case nir_intrinsic_barrier:
4369 emit_barrier(&ctx->ac, ctx->stage);
4370 break;
4371 case nir_intrinsic_var_atomic_add:
4372 case nir_intrinsic_var_atomic_imin:
4373 case nir_intrinsic_var_atomic_umin:
4374 case nir_intrinsic_var_atomic_imax:
4375 case nir_intrinsic_var_atomic_umax:
4376 case nir_intrinsic_var_atomic_and:
4377 case nir_intrinsic_var_atomic_or:
4378 case nir_intrinsic_var_atomic_xor:
4379 case nir_intrinsic_var_atomic_exchange:
4380 case nir_intrinsic_var_atomic_comp_swap:
4381 result = visit_var_atomic(ctx->nctx, instr);
4382 break;
4383 case nir_intrinsic_interp_var_at_centroid:
4384 case nir_intrinsic_interp_var_at_sample:
4385 case nir_intrinsic_interp_var_at_offset:
4386 result = visit_interp(ctx->nctx, instr);
4387 break;
4388 case nir_intrinsic_emit_vertex:
4389 assert(instr->const_index[0] == 0);
4390 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4391 break;
4392 case nir_intrinsic_end_primitive:
4393 visit_end_primitive(ctx->nctx, instr);
4394 break;
4395 case nir_intrinsic_load_tess_coord: {
4396 LLVMTypeRef type = ctx->nctx ?
4397 get_def_type(ctx->nctx->nir, &instr->dest.ssa) :
4398 NULL;
4399 result = ctx->abi->load_tess_coord(ctx->abi, type, instr->num_components);
4400 break;
4401 }
4402 case nir_intrinsic_load_tess_level_outer:
4403 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4404 break;
4405 case nir_intrinsic_load_tess_level_inner:
4406 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4407 break;
4408 case nir_intrinsic_load_patch_vertices_in:
4409 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4410 break;
4411 default:
4412 fprintf(stderr, "Unknown intrinsic: ");
4413 nir_print_instr(&instr->instr, stderr);
4414 fprintf(stderr, "\n");
4415 break;
4416 }
4417 if (result) {
4418 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4419 }
4420 }
4421
4422 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4423 LLVMValueRef buffer_ptr, bool write)
4424 {
4425 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4426
4427 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4428 ctx->shader_info->fs.writes_memory = true;
4429
4430 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4431 }
4432
4433 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4434 {
4435 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4436
4437 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4438 }
4439
4440 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4441 unsigned descriptor_set,
4442 unsigned base_index,
4443 unsigned constant_index,
4444 LLVMValueRef index,
4445 enum ac_descriptor_type desc_type,
4446 bool image, bool write)
4447 {
4448 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4449 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4450 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4451 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4452 unsigned offset = binding->offset;
4453 unsigned stride = binding->size;
4454 unsigned type_size;
4455 LLVMBuilderRef builder = ctx->builder;
4456 LLVMTypeRef type;
4457
4458 assert(base_index < layout->binding_count);
4459
4460 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4461 ctx->shader_info->fs.writes_memory = true;
4462
4463 switch (desc_type) {
4464 case AC_DESC_IMAGE:
4465 type = ctx->ac.v8i32;
4466 type_size = 32;
4467 break;
4468 case AC_DESC_FMASK:
4469 type = ctx->ac.v8i32;
4470 offset += 32;
4471 type_size = 32;
4472 break;
4473 case AC_DESC_SAMPLER:
4474 type = ctx->ac.v4i32;
4475 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4476 offset += 64;
4477
4478 type_size = 16;
4479 break;
4480 case AC_DESC_BUFFER:
4481 type = ctx->ac.v4i32;
4482 type_size = 16;
4483 break;
4484 default:
4485 unreachable("invalid desc_type\n");
4486 }
4487
4488 offset += constant_index * stride;
4489
4490 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4491 (!index || binding->immutable_samplers_equal)) {
4492 if (binding->immutable_samplers_equal)
4493 constant_index = 0;
4494
4495 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4496
4497 LLVMValueRef constants[] = {
4498 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4499 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4500 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4501 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4502 };
4503 return ac_build_gather_values(&ctx->ac, constants, 4);
4504 }
4505
4506 assert(stride % type_size == 0);
4507
4508 if (!index)
4509 index = ctx->ac.i32_0;
4510
4511 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4512
4513 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4514 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4515
4516 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4517 }
4518
4519 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4520 const nir_deref_var *deref,
4521 enum ac_descriptor_type desc_type,
4522 const nir_tex_instr *tex_instr,
4523 bool image, bool write)
4524 {
4525 LLVMValueRef index = NULL;
4526 unsigned constant_index = 0;
4527 unsigned descriptor_set;
4528 unsigned base_index;
4529
4530 if (!deref) {
4531 assert(tex_instr && !image);
4532 descriptor_set = 0;
4533 base_index = tex_instr->sampler_index;
4534 } else {
4535 const nir_deref *tail = &deref->deref;
4536 while (tail->child) {
4537 const nir_deref_array *child = nir_deref_as_array(tail->child);
4538 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4539
4540 if (!array_size)
4541 array_size = 1;
4542
4543 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4544
4545 if (child->deref_array_type == nir_deref_array_type_indirect) {
4546 LLVMValueRef indirect = get_src(ctx, child->indirect);
4547
4548 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4549 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4550
4551 if (!index)
4552 index = indirect;
4553 else
4554 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4555 }
4556
4557 constant_index += child->base_offset * array_size;
4558
4559 tail = &child->deref;
4560 }
4561 descriptor_set = deref->var->data.descriptor_set;
4562 base_index = deref->var->data.binding;
4563 }
4564
4565 return ctx->abi->load_sampler_desc(ctx->abi,
4566 descriptor_set,
4567 base_index,
4568 constant_index, index,
4569 desc_type, image, write);
4570 }
4571
4572 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4573 struct ac_image_args *args,
4574 const nir_tex_instr *instr,
4575 nir_texop op,
4576 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4577 LLVMValueRef *param, unsigned count,
4578 unsigned dmask)
4579 {
4580 unsigned is_rect = 0;
4581 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4582
4583 if (op == nir_texop_lod)
4584 da = false;
4585 /* Pad to power of two vector */
4586 while (count < util_next_power_of_two(count))
4587 param[count++] = LLVMGetUndef(ctx->i32);
4588
4589 if (count > 1)
4590 args->addr = ac_build_gather_values(ctx, param, count);
4591 else
4592 args->addr = param[0];
4593
4594 args->resource = res_ptr;
4595 args->sampler = samp_ptr;
4596
4597 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4598 args->addr = param[0];
4599 return;
4600 }
4601
4602 args->dmask = dmask;
4603 args->unorm = is_rect;
4604 args->da = da;
4605 }
4606
4607 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4608 *
4609 * SI-CI:
4610 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4611 * filtering manually. The driver sets img7 to a mask clearing
4612 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4613 * s_and_b32 samp0, samp0, img7
4614 *
4615 * VI:
4616 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4617 */
4618 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4619 LLVMValueRef res, LLVMValueRef samp)
4620 {
4621 LLVMBuilderRef builder = ctx->ac.builder;
4622 LLVMValueRef img7, samp0;
4623
4624 if (ctx->ac.chip_class >= VI)
4625 return samp;
4626
4627 img7 = LLVMBuildExtractElement(builder, res,
4628 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4629 samp0 = LLVMBuildExtractElement(builder, samp,
4630 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4631 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4632 return LLVMBuildInsertElement(builder, samp, samp0,
4633 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4634 }
4635
4636 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4637 nir_tex_instr *instr,
4638 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4639 LLVMValueRef *fmask_ptr)
4640 {
4641 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4642 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4643 else
4644 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4645 if (samp_ptr) {
4646 if (instr->sampler)
4647 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4648 else
4649 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4650 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4651 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4652 }
4653 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4654 instr->op == nir_texop_samples_identical))
4655 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4656 }
4657
4658 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4659 LLVMValueRef coord)
4660 {
4661 coord = ac_to_float(ctx, coord);
4662 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4663 coord = ac_to_integer(ctx, coord);
4664 return coord;
4665 }
4666
4667 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4668 {
4669 LLVMValueRef result = NULL;
4670 struct ac_image_args args = { 0 };
4671 unsigned dmask = 0xf;
4672 LLVMValueRef address[16];
4673 LLVMValueRef coords[5];
4674 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4675 LLVMValueRef bias = NULL, offsets = NULL;
4676 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4677 LLVMValueRef ddx = NULL, ddy = NULL;
4678 LLVMValueRef derivs[6];
4679 unsigned chan, count = 0;
4680 unsigned const_src = 0, num_deriv_comp = 0;
4681 bool lod_is_zero = false;
4682
4683 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4684
4685 for (unsigned i = 0; i < instr->num_srcs; i++) {
4686 switch (instr->src[i].src_type) {
4687 case nir_tex_src_coord:
4688 coord = get_src(ctx, instr->src[i].src);
4689 break;
4690 case nir_tex_src_projector:
4691 break;
4692 case nir_tex_src_comparator:
4693 comparator = get_src(ctx, instr->src[i].src);
4694 break;
4695 case nir_tex_src_offset:
4696 offsets = get_src(ctx, instr->src[i].src);
4697 const_src = i;
4698 break;
4699 case nir_tex_src_bias:
4700 bias = get_src(ctx, instr->src[i].src);
4701 break;
4702 case nir_tex_src_lod: {
4703 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4704
4705 if (val && val->i32[0] == 0)
4706 lod_is_zero = true;
4707 lod = get_src(ctx, instr->src[i].src);
4708 break;
4709 }
4710 case nir_tex_src_ms_index:
4711 sample_index = get_src(ctx, instr->src[i].src);
4712 break;
4713 case nir_tex_src_ms_mcs:
4714 break;
4715 case nir_tex_src_ddx:
4716 ddx = get_src(ctx, instr->src[i].src);
4717 num_deriv_comp = instr->src[i].src.ssa->num_components;
4718 break;
4719 case nir_tex_src_ddy:
4720 ddy = get_src(ctx, instr->src[i].src);
4721 break;
4722 case nir_tex_src_texture_offset:
4723 case nir_tex_src_sampler_offset:
4724 case nir_tex_src_plane:
4725 default:
4726 break;
4727 }
4728 }
4729
4730 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4731 result = get_buffer_size(ctx, res_ptr, true);
4732 goto write_result;
4733 }
4734
4735 if (instr->op == nir_texop_texture_samples) {
4736 LLVMValueRef res, samples, is_msaa;
4737 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4738 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4739 LLVMConstInt(ctx->ac.i32, 3, false), "");
4740 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4741 LLVMConstInt(ctx->ac.i32, 28, false), "");
4742 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4743 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4744 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4745 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4746
4747 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4748 LLVMConstInt(ctx->ac.i32, 16, false), "");
4749 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4750 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4751 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4752 samples, "");
4753 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4754 ctx->ac.i32_1, "");
4755 result = samples;
4756 goto write_result;
4757 }
4758
4759 if (coord)
4760 for (chan = 0; chan < instr->coord_components; chan++)
4761 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4762
4763 if (offsets && instr->op != nir_texop_txf) {
4764 LLVMValueRef offset[3], pack;
4765 for (chan = 0; chan < 3; ++chan)
4766 offset[chan] = ctx->ac.i32_0;
4767
4768 args.offset = true;
4769 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4770 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4771 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4772 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4773 if (chan)
4774 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4775 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4776 }
4777 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4778 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4779 address[count++] = pack;
4780
4781 }
4782 /* pack LOD bias value */
4783 if (instr->op == nir_texop_txb && bias) {
4784 address[count++] = bias;
4785 }
4786
4787 /* Pack depth comparison value */
4788 if (instr->is_shadow && comparator) {
4789 LLVMValueRef z = ac_to_float(&ctx->ac,
4790 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4791
4792 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4793 * so the depth comparison value isn't clamped for Z16 and
4794 * Z24 anymore. Do it manually here.
4795 *
4796 * It's unnecessary if the original texture format was
4797 * Z32_FLOAT, but we don't know that here.
4798 */
4799 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4800 z = ac_build_clamp(&ctx->ac, z);
4801
4802 address[count++] = z;
4803 }
4804
4805 /* pack derivatives */
4806 if (ddx || ddy) {
4807 int num_src_deriv_channels, num_dest_deriv_channels;
4808 switch (instr->sampler_dim) {
4809 case GLSL_SAMPLER_DIM_3D:
4810 case GLSL_SAMPLER_DIM_CUBE:
4811 num_deriv_comp = 3;
4812 num_src_deriv_channels = 3;
4813 num_dest_deriv_channels = 3;
4814 break;
4815 case GLSL_SAMPLER_DIM_2D:
4816 default:
4817 num_src_deriv_channels = 2;
4818 num_dest_deriv_channels = 2;
4819 num_deriv_comp = 2;
4820 break;
4821 case GLSL_SAMPLER_DIM_1D:
4822 num_src_deriv_channels = 1;
4823 if (ctx->ac.chip_class >= GFX9) {
4824 num_dest_deriv_channels = 2;
4825 num_deriv_comp = 2;
4826 } else {
4827 num_dest_deriv_channels = 1;
4828 num_deriv_comp = 1;
4829 }
4830 break;
4831 }
4832
4833 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4834 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4835 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4836 }
4837 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4838 derivs[i] = ctx->ac.f32_0;
4839 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4840 }
4841 }
4842
4843 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4844 for (chan = 0; chan < instr->coord_components; chan++)
4845 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4846 if (instr->coord_components == 3)
4847 coords[3] = LLVMGetUndef(ctx->ac.f32);
4848 ac_prepare_cube_coords(&ctx->ac,
4849 instr->op == nir_texop_txd, instr->is_array,
4850 instr->op == nir_texop_lod, coords, derivs);
4851 if (num_deriv_comp)
4852 num_deriv_comp--;
4853 }
4854
4855 if (ddx || ddy) {
4856 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4857 address[count++] = derivs[i];
4858 }
4859
4860 /* Pack texture coordinates */
4861 if (coord) {
4862 address[count++] = coords[0];
4863 if (instr->coord_components > 1) {
4864 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4865 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4866 }
4867 address[count++] = coords[1];
4868 }
4869 if (instr->coord_components > 2) {
4870 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4871 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4872 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4873 instr->op != nir_texop_txf) {
4874 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4875 }
4876 address[count++] = coords[2];
4877 }
4878
4879 if (ctx->ac.chip_class >= GFX9) {
4880 LLVMValueRef filler;
4881 if (instr->op == nir_texop_txf)
4882 filler = ctx->ac.i32_0;
4883 else
4884 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4885
4886 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4887 /* No nir_texop_lod, because it does not take a slice
4888 * even with array textures. */
4889 if (instr->is_array && instr->op != nir_texop_lod ) {
4890 address[count] = address[count - 1];
4891 address[count - 1] = filler;
4892 count++;
4893 } else
4894 address[count++] = filler;
4895 }
4896 }
4897 }
4898
4899 /* Pack LOD */
4900 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4901 instr->op == nir_texop_txf)) {
4902 address[count++] = lod;
4903 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4904 address[count++] = sample_index;
4905 } else if(instr->op == nir_texop_txs) {
4906 count = 0;
4907 if (lod)
4908 address[count++] = lod;
4909 else
4910 address[count++] = ctx->ac.i32_0;
4911 }
4912
4913 for (chan = 0; chan < count; chan++) {
4914 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4915 address[chan], ctx->ac.i32, "");
4916 }
4917
4918 if (instr->op == nir_texop_samples_identical) {
4919 LLVMValueRef txf_address[4];
4920 struct ac_image_args txf_args = { 0 };
4921 unsigned txf_count = count;
4922 memcpy(txf_address, address, sizeof(txf_address));
4923
4924 if (!instr->is_array)
4925 txf_address[2] = ctx->ac.i32_0;
4926 txf_address[3] = ctx->ac.i32_0;
4927
4928 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4929 fmask_ptr, NULL,
4930 txf_address, txf_count, 0xf);
4931
4932 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4933
4934 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4935 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4936 goto write_result;
4937 }
4938
4939 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4940 instr->op != nir_texop_txs) {
4941 unsigned sample_chan = instr->is_array ? 3 : 2;
4942 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4943 address[0],
4944 address[1],
4945 instr->is_array ? address[2] : NULL,
4946 address[sample_chan],
4947 fmask_ptr);
4948 }
4949
4950 if (offsets && instr->op == nir_texop_txf) {
4951 nir_const_value *const_offset =
4952 nir_src_as_const_value(instr->src[const_src].src);
4953 int num_offsets = instr->src[const_src].src.ssa->num_components;
4954 assert(const_offset);
4955 num_offsets = MIN2(num_offsets, instr->coord_components);
4956 if (num_offsets > 2)
4957 address[2] = LLVMBuildAdd(ctx->ac.builder,
4958 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4959 if (num_offsets > 1)
4960 address[1] = LLVMBuildAdd(ctx->ac.builder,
4961 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4962 address[0] = LLVMBuildAdd(ctx->ac.builder,
4963 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4964
4965 }
4966
4967 /* TODO TG4 support */
4968 if (instr->op == nir_texop_tg4) {
4969 if (instr->is_shadow)
4970 dmask = 1;
4971 else
4972 dmask = 1 << instr->component;
4973 }
4974 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4975 res_ptr, samp_ptr, address, count, dmask);
4976
4977 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4978
4979 if (instr->op == nir_texop_query_levels)
4980 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4981 else if (instr->is_shadow && instr->is_new_style_shadow &&
4982 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4983 instr->op != nir_texop_tg4)
4984 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4985 else if (instr->op == nir_texop_txs &&
4986 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4987 instr->is_array) {
4988 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4989 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4990 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4991 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4992 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4993 } else if (ctx->ac.chip_class >= GFX9 &&
4994 instr->op == nir_texop_txs &&
4995 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4996 instr->is_array) {
4997 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4998 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4999 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5000 ctx->ac.i32_1, "");
5001 } else if (instr->dest.ssa.num_components != 4)
5002 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5003
5004 write_result:
5005 if (result) {
5006 assert(instr->dest.is_ssa);
5007 result = ac_to_integer(&ctx->ac, result);
5008 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5009 }
5010 }
5011
5012
5013 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5014 {
5015 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5016 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5017
5018 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5019 _mesa_hash_table_insert(ctx->phis, instr, result);
5020 }
5021
5022 static void visit_post_phi(struct ac_nir_context *ctx,
5023 nir_phi_instr *instr,
5024 LLVMValueRef llvm_phi)
5025 {
5026 nir_foreach_phi_src(src, instr) {
5027 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5028 LLVMValueRef llvm_src = get_src(ctx, src->src);
5029
5030 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5031 }
5032 }
5033
5034 static void phi_post_pass(struct ac_nir_context *ctx)
5035 {
5036 struct hash_entry *entry;
5037 hash_table_foreach(ctx->phis, entry) {
5038 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5039 (LLVMValueRef)entry->data);
5040 }
5041 }
5042
5043
5044 static void visit_ssa_undef(struct ac_nir_context *ctx,
5045 const nir_ssa_undef_instr *instr)
5046 {
5047 unsigned num_components = instr->def.num_components;
5048 LLVMValueRef undef;
5049
5050 if (num_components == 1)
5051 undef = LLVMGetUndef(ctx->ac.i32);
5052 else {
5053 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5054 }
5055 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5056 }
5057
5058 static void visit_jump(struct ac_nir_context *ctx,
5059 const nir_jump_instr *instr)
5060 {
5061 switch (instr->type) {
5062 case nir_jump_break:
5063 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5064 LLVMClearInsertionPosition(ctx->ac.builder);
5065 break;
5066 case nir_jump_continue:
5067 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5068 LLVMClearInsertionPosition(ctx->ac.builder);
5069 break;
5070 default:
5071 fprintf(stderr, "Unknown NIR jump instr: ");
5072 nir_print_instr(&instr->instr, stderr);
5073 fprintf(stderr, "\n");
5074 abort();
5075 }
5076 }
5077
5078 static void visit_cf_list(struct ac_nir_context *ctx,
5079 struct exec_list *list);
5080
5081 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5082 {
5083 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5084 nir_foreach_instr(instr, block)
5085 {
5086 switch (instr->type) {
5087 case nir_instr_type_alu:
5088 visit_alu(ctx, nir_instr_as_alu(instr));
5089 break;
5090 case nir_instr_type_load_const:
5091 visit_load_const(ctx, nir_instr_as_load_const(instr));
5092 break;
5093 case nir_instr_type_intrinsic:
5094 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5095 break;
5096 case nir_instr_type_tex:
5097 visit_tex(ctx, nir_instr_as_tex(instr));
5098 break;
5099 case nir_instr_type_phi:
5100 visit_phi(ctx, nir_instr_as_phi(instr));
5101 break;
5102 case nir_instr_type_ssa_undef:
5103 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5104 break;
5105 case nir_instr_type_jump:
5106 visit_jump(ctx, nir_instr_as_jump(instr));
5107 break;
5108 default:
5109 fprintf(stderr, "Unknown NIR instr type: ");
5110 nir_print_instr(instr, stderr);
5111 fprintf(stderr, "\n");
5112 abort();
5113 }
5114 }
5115
5116 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5117 }
5118
5119 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5120 {
5121 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5122
5123 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5124 LLVMBasicBlockRef merge_block =
5125 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5126 LLVMBasicBlockRef if_block =
5127 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5128 LLVMBasicBlockRef else_block = merge_block;
5129 if (!exec_list_is_empty(&if_stmt->else_list))
5130 else_block = LLVMAppendBasicBlockInContext(
5131 ctx->ac.context, fn, "");
5132
5133 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5134 ctx->ac.i32_0, "");
5135 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5136
5137 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5138 visit_cf_list(ctx, &if_stmt->then_list);
5139 if (LLVMGetInsertBlock(ctx->ac.builder))
5140 LLVMBuildBr(ctx->ac.builder, merge_block);
5141
5142 if (!exec_list_is_empty(&if_stmt->else_list)) {
5143 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5144 visit_cf_list(ctx, &if_stmt->else_list);
5145 if (LLVMGetInsertBlock(ctx->ac.builder))
5146 LLVMBuildBr(ctx->ac.builder, merge_block);
5147 }
5148
5149 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5150 }
5151
5152 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5153 {
5154 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5155 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5156 LLVMBasicBlockRef break_parent = ctx->break_block;
5157
5158 ctx->continue_block =
5159 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5160 ctx->break_block =
5161 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5162
5163 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5164 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5165 visit_cf_list(ctx, &loop->body);
5166
5167 if (LLVMGetInsertBlock(ctx->ac.builder))
5168 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5169 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5170
5171 ctx->continue_block = continue_parent;
5172 ctx->break_block = break_parent;
5173 }
5174
5175 static void visit_cf_list(struct ac_nir_context *ctx,
5176 struct exec_list *list)
5177 {
5178 foreach_list_typed(nir_cf_node, node, node, list)
5179 {
5180 switch (node->type) {
5181 case nir_cf_node_block:
5182 visit_block(ctx, nir_cf_node_as_block(node));
5183 break;
5184
5185 case nir_cf_node_if:
5186 visit_if(ctx, nir_cf_node_as_if(node));
5187 break;
5188
5189 case nir_cf_node_loop:
5190 visit_loop(ctx, nir_cf_node_as_loop(node));
5191 break;
5192
5193 default:
5194 assert(0);
5195 }
5196 }
5197 }
5198
5199 static void
5200 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5201 struct nir_variable *variable)
5202 {
5203 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5204 LLVMValueRef t_offset;
5205 LLVMValueRef t_list;
5206 LLVMValueRef input;
5207 LLVMValueRef buffer_index;
5208 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5209 int idx = variable->data.location;
5210 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5211
5212 variable->data.driver_location = idx * 4;
5213
5214 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5215 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5216 ctx->abi.start_instance, "");
5217 if (ctx->options->key.vs.as_ls) {
5218 ctx->shader_info->vs.vgpr_comp_cnt =
5219 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5220 } else {
5221 ctx->shader_info->vs.vgpr_comp_cnt =
5222 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5223 }
5224 } else
5225 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5226 ctx->abi.base_vertex, "");
5227
5228 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5229 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5230
5231 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5232
5233 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5234 buffer_index,
5235 ctx->ac.i32_0,
5236 true);
5237
5238 for (unsigned chan = 0; chan < 4; chan++) {
5239 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5240 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5241 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5242 input, llvm_chan, ""));
5243 }
5244 }
5245 }
5246
5247 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5248 unsigned attr,
5249 LLVMValueRef interp_param,
5250 LLVMValueRef prim_mask,
5251 LLVMValueRef result[4])
5252 {
5253 LLVMValueRef attr_number;
5254 unsigned chan;
5255 LLVMValueRef i, j;
5256 bool interp = interp_param != NULL;
5257
5258 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5259
5260 /* fs.constant returns the param from the middle vertex, so it's not
5261 * really useful for flat shading. It's meant to be used for custom
5262 * interpolation (but the intrinsic can't fetch from the other two
5263 * vertices).
5264 *
5265 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5266 * to do the right thing. The only reason we use fs.constant is that
5267 * fs.interp cannot be used on integers, because they can be equal
5268 * to NaN.
5269 */
5270 if (interp) {
5271 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5272 ctx->ac.v2f32, "");
5273
5274 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5275 ctx->ac.i32_0, "");
5276 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5277 ctx->ac.i32_1, "");
5278 }
5279
5280 for (chan = 0; chan < 4; chan++) {
5281 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5282
5283 if (interp) {
5284 result[chan] = ac_build_fs_interp(&ctx->ac,
5285 llvm_chan,
5286 attr_number,
5287 prim_mask, i, j);
5288 } else {
5289 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5290 LLVMConstInt(ctx->ac.i32, 2, false),
5291 llvm_chan,
5292 attr_number,
5293 prim_mask);
5294 }
5295 }
5296 }
5297
5298 static void
5299 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5300 struct nir_variable *variable)
5301 {
5302 int idx = variable->data.location;
5303 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5304 LLVMValueRef interp;
5305
5306 variable->data.driver_location = idx * 4;
5307 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5308
5309 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5310 unsigned interp_type;
5311 if (variable->data.sample) {
5312 interp_type = INTERP_SAMPLE;
5313 ctx->shader_info->info.ps.force_persample = true;
5314 } else if (variable->data.centroid)
5315 interp_type = INTERP_CENTROID;
5316 else
5317 interp_type = INTERP_CENTER;
5318
5319 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5320 } else
5321 interp = NULL;
5322
5323 for (unsigned i = 0; i < attrib_count; ++i)
5324 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5325
5326 }
5327
5328 static void
5329 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5330 struct nir_shader *nir) {
5331 nir_foreach_variable(variable, &nir->inputs)
5332 handle_vs_input_decl(ctx, variable);
5333 }
5334
5335 static void
5336 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5337 struct nir_shader *nir)
5338 {
5339 if (!ctx->options->key.fs.multisample)
5340 return;
5341
5342 bool uses_center = false;
5343 bool uses_centroid = false;
5344 nir_foreach_variable(variable, &nir->inputs) {
5345 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5346 variable->data.sample)
5347 continue;
5348
5349 if (variable->data.centroid)
5350 uses_centroid = true;
5351 else
5352 uses_center = true;
5353 }
5354
5355 if (uses_center && uses_centroid) {
5356 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5357 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5358 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5359 }
5360 }
5361
5362 static void
5363 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5364 struct nir_shader *nir)
5365 {
5366 prepare_interp_optimize(ctx, nir);
5367
5368 nir_foreach_variable(variable, &nir->inputs)
5369 handle_fs_input_decl(ctx, variable);
5370
5371 unsigned index = 0;
5372
5373 if (ctx->shader_info->info.ps.uses_input_attachments ||
5374 ctx->shader_info->info.needs_multiview_view_index)
5375 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5376
5377 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5378 LLVMValueRef interp_param;
5379 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5380
5381 if (!(ctx->input_mask & (1ull << i)))
5382 continue;
5383
5384 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5385 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5386 interp_param = *inputs;
5387 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5388 inputs);
5389
5390 if (!interp_param)
5391 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5392 ++index;
5393 } else if (i == VARYING_SLOT_POS) {
5394 for(int i = 0; i < 3; ++i)
5395 inputs[i] = ctx->abi.frag_pos[i];
5396
5397 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5398 ctx->abi.frag_pos[3]);
5399 }
5400 }
5401 ctx->shader_info->fs.num_interp = index;
5402 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5403 ctx->shader_info->fs.has_pcoord = true;
5404 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5405 ctx->shader_info->fs.prim_id_input = true;
5406 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5407 ctx->shader_info->fs.layer_input = true;
5408 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5409
5410 if (ctx->shader_info->info.needs_multiview_view_index)
5411 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5412 }
5413
5414 static LLVMValueRef
5415 ac_build_alloca(struct ac_llvm_context *ac,
5416 LLVMTypeRef type,
5417 const char *name)
5418 {
5419 LLVMBuilderRef builder = ac->builder;
5420 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5421 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5422 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5423 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5424 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5425 LLVMValueRef res;
5426
5427 if (first_instr) {
5428 LLVMPositionBuilderBefore(first_builder, first_instr);
5429 } else {
5430 LLVMPositionBuilderAtEnd(first_builder, first_block);
5431 }
5432
5433 res = LLVMBuildAlloca(first_builder, type, name);
5434 LLVMBuildStore(builder, LLVMConstNull(type), res);
5435
5436 LLVMDisposeBuilder(first_builder);
5437
5438 return res;
5439 }
5440
5441 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5442 LLVMTypeRef type,
5443 const char *name)
5444 {
5445 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5446 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5447 return ptr;
5448 }
5449
5450 static void
5451 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5452 struct nir_variable *variable,
5453 struct nir_shader *shader,
5454 gl_shader_stage stage)
5455 {
5456 int idx = variable->data.location + variable->data.index;
5457 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5458 uint64_t mask_attribs;
5459
5460 variable->data.driver_location = idx * 4;
5461
5462 /* tess ctrl has it's own load/store paths for outputs */
5463 if (stage == MESA_SHADER_TESS_CTRL)
5464 return;
5465
5466 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5467 if (stage == MESA_SHADER_VERTEX ||
5468 stage == MESA_SHADER_TESS_EVAL ||
5469 stage == MESA_SHADER_GEOMETRY) {
5470 if (idx == VARYING_SLOT_CLIP_DIST0) {
5471 int length = shader->info.clip_distance_array_size +
5472 shader->info.cull_distance_array_size;
5473 if (stage == MESA_SHADER_VERTEX) {
5474 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5475 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5476 }
5477 if (stage == MESA_SHADER_TESS_EVAL) {
5478 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5479 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5480 }
5481
5482 if (length > 4)
5483 attrib_count = 2;
5484 else
5485 attrib_count = 1;
5486 mask_attribs = 1ull << idx;
5487 }
5488 }
5489
5490 ctx->output_mask |= mask_attribs;
5491 }
5492
5493 static void
5494 handle_shader_output_decl(struct ac_nir_context *ctx,
5495 struct nir_shader *nir,
5496 struct nir_variable *variable)
5497 {
5498 unsigned output_loc = variable->data.driver_location / 4;
5499 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5500
5501 /* tess ctrl has it's own load/store paths for outputs */
5502 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5503 return;
5504
5505 if (ctx->stage == MESA_SHADER_VERTEX ||
5506 ctx->stage == MESA_SHADER_TESS_EVAL ||
5507 ctx->stage == MESA_SHADER_GEOMETRY) {
5508 int idx = variable->data.location + variable->data.index;
5509 if (idx == VARYING_SLOT_CLIP_DIST0) {
5510 int length = nir->info.clip_distance_array_size +
5511 nir->info.cull_distance_array_size;
5512
5513 if (length > 4)
5514 attrib_count = 2;
5515 else
5516 attrib_count = 1;
5517 }
5518 }
5519
5520 for (unsigned i = 0; i < attrib_count; ++i) {
5521 for (unsigned chan = 0; chan < 4; chan++) {
5522 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5523 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5524 }
5525 }
5526 }
5527
5528 static LLVMTypeRef
5529 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5530 enum glsl_base_type type)
5531 {
5532 switch (type) {
5533 case GLSL_TYPE_INT:
5534 case GLSL_TYPE_UINT:
5535 case GLSL_TYPE_BOOL:
5536 case GLSL_TYPE_SUBROUTINE:
5537 return ctx->ac.i32;
5538 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5539 return ctx->ac.f32;
5540 case GLSL_TYPE_INT64:
5541 case GLSL_TYPE_UINT64:
5542 return ctx->ac.i64;
5543 case GLSL_TYPE_DOUBLE:
5544 return ctx->ac.f64;
5545 default:
5546 unreachable("unknown GLSL type");
5547 }
5548 }
5549
5550 static LLVMTypeRef
5551 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5552 const struct glsl_type *type)
5553 {
5554 if (glsl_type_is_scalar(type)) {
5555 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5556 }
5557
5558 if (glsl_type_is_vector(type)) {
5559 return LLVMVectorType(
5560 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5561 glsl_get_vector_elements(type));
5562 }
5563
5564 if (glsl_type_is_matrix(type)) {
5565 return LLVMArrayType(
5566 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5567 glsl_get_matrix_columns(type));
5568 }
5569
5570 if (glsl_type_is_array(type)) {
5571 return LLVMArrayType(
5572 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5573 glsl_get_length(type));
5574 }
5575
5576 assert(glsl_type_is_struct(type));
5577
5578 LLVMTypeRef member_types[glsl_get_length(type)];
5579
5580 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5581 member_types[i] =
5582 glsl_to_llvm_type(ctx,
5583 glsl_get_struct_field(type, i));
5584 }
5585
5586 return LLVMStructTypeInContext(ctx->context, member_types,
5587 glsl_get_length(type), false);
5588 }
5589
5590 static void
5591 setup_locals(struct ac_nir_context *ctx,
5592 struct nir_function *func)
5593 {
5594 int i, j;
5595 ctx->num_locals = 0;
5596 nir_foreach_variable(variable, &func->impl->locals) {
5597 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5598 variable->data.driver_location = ctx->num_locals * 4;
5599 variable->data.location_frac = 0;
5600 ctx->num_locals += attrib_count;
5601 }
5602 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5603 if (!ctx->locals)
5604 return;
5605
5606 for (i = 0; i < ctx->num_locals; i++) {
5607 for (j = 0; j < 4; j++) {
5608 ctx->locals[i * 4 + j] =
5609 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5610 }
5611 }
5612 }
5613
5614 static void
5615 setup_shared(struct ac_nir_context *ctx,
5616 struct nir_shader *nir)
5617 {
5618 nir_foreach_variable(variable, &nir->shared) {
5619 LLVMValueRef shared =
5620 LLVMAddGlobalInAddressSpace(
5621 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5622 variable->name ? variable->name : "",
5623 LOCAL_ADDR_SPACE);
5624 _mesa_hash_table_insert(ctx->vars, variable, shared);
5625 }
5626 }
5627
5628 static LLVMValueRef
5629 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5630 {
5631 v = ac_to_float(ctx, v);
5632 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5633 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5634 }
5635
5636
5637 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5638 LLVMValueRef src0, LLVMValueRef src1)
5639 {
5640 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5641 LLVMValueRef comp[2];
5642
5643 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5644 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5645 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5646 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5647 }
5648
5649 /* Initialize arguments for the shader export intrinsic */
5650 static void
5651 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5652 LLVMValueRef *values,
5653 unsigned target,
5654 struct ac_export_args *args)
5655 {
5656 /* Default is 0xf. Adjusted below depending on the format. */
5657 args->enabled_channels = 0xf;
5658
5659 /* Specify whether the EXEC mask represents the valid mask */
5660 args->valid_mask = 0;
5661
5662 /* Specify whether this is the last export */
5663 args->done = 0;
5664
5665 /* Specify the target we are exporting */
5666 args->target = target;
5667
5668 args->compr = false;
5669 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5670 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5671 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5672 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5673
5674 if (!values)
5675 return;
5676
5677 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5678 LLVMValueRef val[4];
5679 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5680 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5681 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5682 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5683
5684 switch(col_format) {
5685 case V_028714_SPI_SHADER_ZERO:
5686 args->enabled_channels = 0; /* writemask */
5687 args->target = V_008DFC_SQ_EXP_NULL;
5688 break;
5689
5690 case V_028714_SPI_SHADER_32_R:
5691 args->enabled_channels = 1;
5692 args->out[0] = values[0];
5693 break;
5694
5695 case V_028714_SPI_SHADER_32_GR:
5696 args->enabled_channels = 0x3;
5697 args->out[0] = values[0];
5698 args->out[1] = values[1];
5699 break;
5700
5701 case V_028714_SPI_SHADER_32_AR:
5702 args->enabled_channels = 0x9;
5703 args->out[0] = values[0];
5704 args->out[3] = values[3];
5705 break;
5706
5707 case V_028714_SPI_SHADER_FP16_ABGR:
5708 args->compr = 1;
5709
5710 for (unsigned chan = 0; chan < 2; chan++) {
5711 LLVMValueRef pack_args[2] = {
5712 values[2 * chan],
5713 values[2 * chan + 1]
5714 };
5715 LLVMValueRef packed;
5716
5717 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5718 args->out[chan] = packed;
5719 }
5720 break;
5721
5722 case V_028714_SPI_SHADER_UNORM16_ABGR:
5723 for (unsigned chan = 0; chan < 4; chan++) {
5724 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5725 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5726 LLVMConstReal(ctx->ac.f32, 65535), "");
5727 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5728 LLVMConstReal(ctx->ac.f32, 0.5), "");
5729 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5730 ctx->ac.i32, "");
5731 }
5732
5733 args->compr = 1;
5734 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5735 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5736 break;
5737
5738 case V_028714_SPI_SHADER_SNORM16_ABGR:
5739 for (unsigned chan = 0; chan < 4; chan++) {
5740 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5741 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5742 LLVMConstReal(ctx->ac.f32, 32767), "");
5743
5744 /* If positive, add 0.5, else add -0.5. */
5745 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5746 LLVMBuildSelect(ctx->builder,
5747 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5748 val[chan], ctx->ac.f32_0, ""),
5749 LLVMConstReal(ctx->ac.f32, 0.5),
5750 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5751 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5752 }
5753
5754 args->compr = 1;
5755 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5756 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5757 break;
5758
5759 case V_028714_SPI_SHADER_UINT16_ABGR: {
5760 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5761 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5762 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5763
5764 for (unsigned chan = 0; chan < 4; chan++) {
5765 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5766 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5767 }
5768
5769 args->compr = 1;
5770 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5771 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5772 break;
5773 }
5774
5775 case V_028714_SPI_SHADER_SINT16_ABGR: {
5776 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5777 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5778 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5779 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5780 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5781 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5782
5783 /* Clamp. */
5784 for (unsigned chan = 0; chan < 4; chan++) {
5785 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5786 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5787 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5788 }
5789
5790 args->compr = 1;
5791 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5792 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5793 break;
5794 }
5795
5796 default:
5797 case V_028714_SPI_SHADER_32_ABGR:
5798 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5799 break;
5800 }
5801 } else
5802 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5803
5804 for (unsigned i = 0; i < 4; ++i)
5805 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5806 }
5807
5808 static void
5809 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5810 bool export_prim_id,
5811 struct ac_vs_output_info *outinfo)
5812 {
5813 uint32_t param_count = 0;
5814 unsigned target;
5815 unsigned pos_idx, num_pos_exports = 0;
5816 struct ac_export_args args, pos_args[4] = {};
5817 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5818 int i;
5819
5820 if (ctx->options->key.has_multiview_view_index) {
5821 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5822 if(!*tmp_out) {
5823 for(unsigned i = 0; i < 4; ++i)
5824 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5825 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5826 }
5827
5828 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5829 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5830 }
5831
5832 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5833 sizeof(outinfo->vs_output_param_offset));
5834
5835 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5836 LLVMValueRef slots[8];
5837 unsigned j;
5838
5839 if (outinfo->cull_dist_mask)
5840 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5841
5842 i = VARYING_SLOT_CLIP_DIST0;
5843 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5844 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5845 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5846
5847 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5848 slots[i] = LLVMGetUndef(ctx->ac.f32);
5849
5850 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5851 target = V_008DFC_SQ_EXP_POS + 3;
5852 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5853 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5854 &args, sizeof(args));
5855 }
5856
5857 target = V_008DFC_SQ_EXP_POS + 2;
5858 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5859 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5860 &args, sizeof(args));
5861
5862 }
5863
5864 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5865 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5866 for (unsigned j = 0; j < 4; j++)
5867 pos_values[j] = LLVMBuildLoad(ctx->builder,
5868 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5869 }
5870 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5871
5872 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5873 outinfo->writes_pointsize = true;
5874 psize_value = LLVMBuildLoad(ctx->builder,
5875 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5876 }
5877
5878 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5879 outinfo->writes_layer = true;
5880 layer_value = LLVMBuildLoad(ctx->builder,
5881 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5882 }
5883
5884 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5885 outinfo->writes_viewport_index = true;
5886 viewport_index_value = LLVMBuildLoad(ctx->builder,
5887 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5888 }
5889
5890 if (outinfo->writes_pointsize ||
5891 outinfo->writes_layer ||
5892 outinfo->writes_viewport_index) {
5893 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5894 (outinfo->writes_layer == true ? 4 : 0));
5895 pos_args[1].valid_mask = 0;
5896 pos_args[1].done = 0;
5897 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5898 pos_args[1].compr = 0;
5899 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5900 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5901 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5902 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5903
5904 if (outinfo->writes_pointsize == true)
5905 pos_args[1].out[0] = psize_value;
5906 if (outinfo->writes_layer == true)
5907 pos_args[1].out[2] = layer_value;
5908 if (outinfo->writes_viewport_index == true) {
5909 if (ctx->options->chip_class >= GFX9) {
5910 /* GFX9 has the layer in out.z[10:0] and the viewport
5911 * index in out.z[19:16].
5912 */
5913 LLVMValueRef v = viewport_index_value;
5914 v = ac_to_integer(&ctx->ac, v);
5915 v = LLVMBuildShl(ctx->builder, v,
5916 LLVMConstInt(ctx->ac.i32, 16, false),
5917 "");
5918 v = LLVMBuildOr(ctx->builder, v,
5919 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5920
5921 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5922 pos_args[1].enabled_channels |= 1 << 2;
5923 } else {
5924 pos_args[1].out[3] = viewport_index_value;
5925 pos_args[1].enabled_channels |= 1 << 3;
5926 }
5927 }
5928 }
5929 for (i = 0; i < 4; i++) {
5930 if (pos_args[i].out[0])
5931 num_pos_exports++;
5932 }
5933
5934 pos_idx = 0;
5935 for (i = 0; i < 4; i++) {
5936 if (!pos_args[i].out[0])
5937 continue;
5938
5939 /* Specify the target we are exporting */
5940 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5941 if (pos_idx == num_pos_exports)
5942 pos_args[i].done = 1;
5943 ac_build_export(&ctx->ac, &pos_args[i]);
5944 }
5945
5946 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5947 LLVMValueRef values[4];
5948 if (!(ctx->output_mask & (1ull << i)))
5949 continue;
5950
5951 for (unsigned j = 0; j < 4; j++)
5952 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5953 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5954
5955 if (i == VARYING_SLOT_LAYER) {
5956 target = V_008DFC_SQ_EXP_PARAM + param_count;
5957 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5958 param_count++;
5959 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5960 target = V_008DFC_SQ_EXP_PARAM + param_count;
5961 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5962 param_count++;
5963 } else if (i >= VARYING_SLOT_VAR0) {
5964 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5965 target = V_008DFC_SQ_EXP_PARAM + param_count;
5966 outinfo->vs_output_param_offset[i] = param_count;
5967 param_count++;
5968 } else
5969 continue;
5970
5971 si_llvm_init_export_args(ctx, values, target, &args);
5972
5973 if (target >= V_008DFC_SQ_EXP_POS &&
5974 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5975 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5976 &args, sizeof(args));
5977 } else {
5978 ac_build_export(&ctx->ac, &args);
5979 }
5980 }
5981
5982 if (export_prim_id) {
5983 LLVMValueRef values[4];
5984 target = V_008DFC_SQ_EXP_PARAM + param_count;
5985 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5986 param_count++;
5987
5988 values[0] = ctx->vs_prim_id;
5989 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5990 ctx->shader_info->vs.vgpr_comp_cnt);
5991 for (unsigned j = 1; j < 4; j++)
5992 values[j] = ctx->ac.f32_0;
5993 si_llvm_init_export_args(ctx, values, target, &args);
5994 ac_build_export(&ctx->ac, &args);
5995 outinfo->export_prim_id = true;
5996 }
5997
5998 outinfo->pos_exports = num_pos_exports;
5999 outinfo->param_exports = param_count;
6000 }
6001
6002 static void
6003 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6004 struct ac_es_output_info *outinfo)
6005 {
6006 int j;
6007 uint64_t max_output_written = 0;
6008 LLVMValueRef lds_base = NULL;
6009
6010 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6011 int param_index;
6012 int length = 4;
6013
6014 if (!(ctx->output_mask & (1ull << i)))
6015 continue;
6016
6017 if (i == VARYING_SLOT_CLIP_DIST0)
6018 length = ctx->num_output_clips + ctx->num_output_culls;
6019
6020 param_index = shader_io_get_unique_index(i);
6021
6022 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6023 }
6024
6025 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6026
6027 if (ctx->ac.chip_class >= GFX9) {
6028 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6029 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6030 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6031 LLVMConstInt(ctx->ac.i32, 24, false),
6032 LLVMConstInt(ctx->ac.i32, 4, false), false);
6033 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6034 LLVMBuildMul(ctx->ac.builder, wave_idx,
6035 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6036 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6037 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6038 }
6039
6040 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6041 LLVMValueRef dw_addr;
6042 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6043 int param_index;
6044 int length = 4;
6045
6046 if (!(ctx->output_mask & (1ull << i)))
6047 continue;
6048
6049 if (i == VARYING_SLOT_CLIP_DIST0)
6050 length = ctx->num_output_clips + ctx->num_output_culls;
6051
6052 param_index = shader_io_get_unique_index(i);
6053
6054 if (lds_base) {
6055 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6056 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6057 "");
6058 }
6059 for (j = 0; j < length; j++) {
6060 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6061 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6062
6063 if (ctx->ac.chip_class >= GFX9) {
6064 ac_lds_store(&ctx->ac, dw_addr,
6065 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6066 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6067 } else {
6068 ac_build_buffer_store_dword(&ctx->ac,
6069 ctx->esgs_ring,
6070 out_val, 1,
6071 NULL, ctx->es2gs_offset,
6072 (4 * param_index + j) * 4,
6073 1, 1, true, true);
6074 }
6075 }
6076 }
6077 }
6078
6079 static void
6080 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6081 {
6082 LLVMValueRef vertex_id = ctx->rel_auto_id;
6083 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6084 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6085 vertex_dw_stride, "");
6086
6087 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6088 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6089 int length = 4;
6090
6091 if (!(ctx->output_mask & (1ull << i)))
6092 continue;
6093
6094 if (i == VARYING_SLOT_CLIP_DIST0)
6095 length = ctx->num_output_clips + ctx->num_output_culls;
6096 int param = shader_io_get_unique_index(i);
6097 mark_tess_output(ctx, false, param);
6098 if (length > 4)
6099 mark_tess_output(ctx, false, param + 1);
6100 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6101 LLVMConstInt(ctx->ac.i32, param * 4, false),
6102 "");
6103 for (unsigned j = 0; j < length; j++) {
6104 ac_lds_store(&ctx->ac, dw_addr,
6105 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6106 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6107 }
6108 }
6109 }
6110
6111 struct ac_build_if_state
6112 {
6113 struct nir_to_llvm_context *ctx;
6114 LLVMValueRef condition;
6115 LLVMBasicBlockRef entry_block;
6116 LLVMBasicBlockRef true_block;
6117 LLVMBasicBlockRef false_block;
6118 LLVMBasicBlockRef merge_block;
6119 };
6120
6121 static LLVMBasicBlockRef
6122 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6123 {
6124 LLVMBasicBlockRef current_block;
6125 LLVMBasicBlockRef next_block;
6126 LLVMBasicBlockRef new_block;
6127
6128 /* get current basic block */
6129 current_block = LLVMGetInsertBlock(ctx->builder);
6130
6131 /* chqeck if there's another block after this one */
6132 next_block = LLVMGetNextBasicBlock(current_block);
6133 if (next_block) {
6134 /* insert the new block before the next block */
6135 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6136 }
6137 else {
6138 /* append new block after current block */
6139 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6140 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6141 }
6142 return new_block;
6143 }
6144
6145 static void
6146 ac_nir_build_if(struct ac_build_if_state *ifthen,
6147 struct nir_to_llvm_context *ctx,
6148 LLVMValueRef condition)
6149 {
6150 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6151
6152 memset(ifthen, 0, sizeof *ifthen);
6153 ifthen->ctx = ctx;
6154 ifthen->condition = condition;
6155 ifthen->entry_block = block;
6156
6157 /* create endif/merge basic block for the phi functions */
6158 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6159
6160 /* create/insert true_block before merge_block */
6161 ifthen->true_block =
6162 LLVMInsertBasicBlockInContext(ctx->context,
6163 ifthen->merge_block,
6164 "if-true-block");
6165
6166 /* successive code goes into the true block */
6167 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6168 }
6169
6170 /**
6171 * End a conditional.
6172 */
6173 static void
6174 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6175 {
6176 LLVMBuilderRef builder = ifthen->ctx->builder;
6177
6178 /* Insert branch to the merge block from current block */
6179 LLVMBuildBr(builder, ifthen->merge_block);
6180
6181 /*
6182 * Now patch in the various branch instructions.
6183 */
6184
6185 /* Insert the conditional branch instruction at the end of entry_block */
6186 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6187 if (ifthen->false_block) {
6188 /* we have an else clause */
6189 LLVMBuildCondBr(builder, ifthen->condition,
6190 ifthen->true_block, ifthen->false_block);
6191 }
6192 else {
6193 /* no else clause */
6194 LLVMBuildCondBr(builder, ifthen->condition,
6195 ifthen->true_block, ifthen->merge_block);
6196 }
6197
6198 /* Resume building code at end of the ifthen->merge_block */
6199 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6200 }
6201
6202 static void
6203 write_tess_factors(struct nir_to_llvm_context *ctx)
6204 {
6205 unsigned stride, outer_comps, inner_comps;
6206 struct ac_build_if_state if_ctx, inner_if_ctx;
6207 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6208 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6209 unsigned tess_inner_index, tess_outer_index;
6210 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6211 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6212 int i;
6213 emit_barrier(&ctx->ac, ctx->stage);
6214
6215 switch (ctx->options->key.tcs.primitive_mode) {
6216 case GL_ISOLINES:
6217 stride = 2;
6218 outer_comps = 2;
6219 inner_comps = 0;
6220 break;
6221 case GL_TRIANGLES:
6222 stride = 4;
6223 outer_comps = 3;
6224 inner_comps = 1;
6225 break;
6226 case GL_QUADS:
6227 stride = 6;
6228 outer_comps = 4;
6229 inner_comps = 2;
6230 break;
6231 default:
6232 return;
6233 }
6234
6235 ac_nir_build_if(&if_ctx, ctx,
6236 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6237 invocation_id, ctx->ac.i32_0, ""));
6238
6239 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6240 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6241
6242 mark_tess_output(ctx, true, tess_inner_index);
6243 mark_tess_output(ctx, true, tess_outer_index);
6244 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6245 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6246 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6247 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6248 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6249
6250 for (i = 0; i < 4; i++) {
6251 inner[i] = LLVMGetUndef(ctx->ac.i32);
6252 outer[i] = LLVMGetUndef(ctx->ac.i32);
6253 }
6254
6255 // LINES reverseal
6256 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6257 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6258 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6259 ctx->ac.i32_1, "");
6260 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6261 } else {
6262 for (i = 0; i < outer_comps; i++) {
6263 outer[i] = out[i] =
6264 ac_lds_load(&ctx->ac, lds_outer);
6265 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6266 ctx->ac.i32_1, "");
6267 }
6268 for (i = 0; i < inner_comps; i++) {
6269 inner[i] = out[outer_comps+i] =
6270 ac_lds_load(&ctx->ac, lds_inner);
6271 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6272 ctx->ac.i32_1, "");
6273 }
6274 }
6275
6276 /* Convert the outputs to vectors for stores. */
6277 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6278 vec1 = NULL;
6279
6280 if (stride > 4)
6281 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6282
6283
6284 buffer = ctx->hs_ring_tess_factor;
6285 tf_base = ctx->tess_factor_offset;
6286 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6287 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6288 unsigned tf_offset = 0;
6289
6290 if (ctx->options->chip_class <= VI) {
6291 ac_nir_build_if(&inner_if_ctx, ctx,
6292 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6293 rel_patch_id, ctx->ac.i32_0, ""));
6294
6295 /* Store the dynamic HS control word. */
6296 ac_build_buffer_store_dword(&ctx->ac, buffer,
6297 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6298 1, ctx->ac.i32_0, tf_base,
6299 0, 1, 0, true, false);
6300 tf_offset += 4;
6301
6302 ac_nir_build_endif(&inner_if_ctx);
6303 }
6304
6305 /* Store the tessellation factors. */
6306 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6307 MIN2(stride, 4), byteoffset, tf_base,
6308 tf_offset, 1, 0, true, false);
6309 if (vec1)
6310 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6311 stride - 4, byteoffset, tf_base,
6312 16 + tf_offset, 1, 0, true, false);
6313
6314 //store to offchip for TES to read - only if TES reads them
6315 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6316 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6317 LLVMValueRef tf_inner_offset;
6318 unsigned param_outer, param_inner;
6319
6320 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6321 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6322 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6323
6324 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6325 util_next_power_of_two(outer_comps));
6326
6327 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6328 outer_comps, tf_outer_offset,
6329 ctx->oc_lds, 0, 1, 0, true, false);
6330 if (inner_comps) {
6331 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6332 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6333 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6334
6335 inner_vec = inner_comps == 1 ? inner[0] :
6336 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6337 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6338 inner_comps, tf_inner_offset,
6339 ctx->oc_lds, 0, 1, 0, true, false);
6340 }
6341 }
6342 ac_nir_build_endif(&if_ctx);
6343 }
6344
6345 static void
6346 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6347 {
6348 write_tess_factors(ctx);
6349 }
6350
6351 static bool
6352 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6353 LLVMValueRef *color, unsigned param, bool is_last,
6354 struct ac_export_args *args)
6355 {
6356 /* Export */
6357 si_llvm_init_export_args(ctx, color, param,
6358 args);
6359
6360 if (is_last) {
6361 args->valid_mask = 1; /* whether the EXEC mask is valid */
6362 args->done = 1; /* DONE bit */
6363 } else if (!args->enabled_channels)
6364 return false; /* unnecessary NULL export */
6365
6366 return true;
6367 }
6368
6369 static void
6370 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6371 LLVMValueRef depth, LLVMValueRef stencil,
6372 LLVMValueRef samplemask)
6373 {
6374 struct ac_export_args args;
6375
6376 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6377
6378 ac_build_export(&ctx->ac, &args);
6379 }
6380
6381 static void
6382 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6383 {
6384 unsigned index = 0;
6385 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6386 struct ac_export_args color_args[8];
6387
6388 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6389 LLVMValueRef values[4];
6390
6391 if (!(ctx->output_mask & (1ull << i)))
6392 continue;
6393
6394 if (i == FRAG_RESULT_DEPTH) {
6395 ctx->shader_info->fs.writes_z = true;
6396 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6397 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6398 } else if (i == FRAG_RESULT_STENCIL) {
6399 ctx->shader_info->fs.writes_stencil = true;
6400 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6401 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6402 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6403 ctx->shader_info->fs.writes_sample_mask = true;
6404 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6405 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6406 } else {
6407 bool last = false;
6408 for (unsigned j = 0; j < 4; j++)
6409 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6410 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6411
6412 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6413 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6414
6415 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6416 if (ret)
6417 index++;
6418 }
6419 }
6420
6421 for (unsigned i = 0; i < index; i++)
6422 ac_build_export(&ctx->ac, &color_args[i]);
6423 if (depth || stencil || samplemask)
6424 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6425 else if (!index) {
6426 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6427 ac_build_export(&ctx->ac, &color_args[0]);
6428 }
6429 }
6430
6431 static void
6432 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6433 {
6434 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6435 }
6436
6437 static void
6438 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6439 LLVMValueRef *addrs)
6440 {
6441 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6442
6443 switch (ctx->stage) {
6444 case MESA_SHADER_VERTEX:
6445 if (ctx->options->key.vs.as_ls)
6446 handle_ls_outputs_post(ctx);
6447 else if (ctx->options->key.vs.as_es)
6448 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6449 else
6450 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6451 &ctx->shader_info->vs.outinfo);
6452 break;
6453 case MESA_SHADER_FRAGMENT:
6454 handle_fs_outputs_post(ctx);
6455 break;
6456 case MESA_SHADER_GEOMETRY:
6457 emit_gs_epilogue(ctx);
6458 break;
6459 case MESA_SHADER_TESS_CTRL:
6460 handle_tcs_outputs_post(ctx);
6461 break;
6462 case MESA_SHADER_TESS_EVAL:
6463 if (ctx->options->key.tes.as_es)
6464 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6465 else
6466 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6467 &ctx->shader_info->tes.outinfo);
6468 break;
6469 default:
6470 break;
6471 }
6472 }
6473
6474 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6475 {
6476 LLVMPassManagerRef passmgr;
6477 /* Create the pass manager */
6478 passmgr = LLVMCreateFunctionPassManagerForModule(
6479 ctx->module);
6480
6481 /* This pass should eliminate all the load and store instructions */
6482 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6483
6484 /* Add some optimization passes */
6485 LLVMAddScalarReplAggregatesPass(passmgr);
6486 LLVMAddLICMPass(passmgr);
6487 LLVMAddAggressiveDCEPass(passmgr);
6488 LLVMAddCFGSimplificationPass(passmgr);
6489 LLVMAddInstructionCombiningPass(passmgr);
6490
6491 /* Run the pass */
6492 LLVMInitializeFunctionPassManager(passmgr);
6493 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6494 LLVMFinalizeFunctionPassManager(passmgr);
6495
6496 LLVMDisposeBuilder(ctx->builder);
6497 LLVMDisposePassManager(passmgr);
6498 }
6499
6500 static void
6501 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6502 {
6503 struct ac_vs_output_info *outinfo;
6504
6505 switch (ctx->stage) {
6506 case MESA_SHADER_FRAGMENT:
6507 case MESA_SHADER_COMPUTE:
6508 case MESA_SHADER_TESS_CTRL:
6509 case MESA_SHADER_GEOMETRY:
6510 return;
6511 case MESA_SHADER_VERTEX:
6512 if (ctx->options->key.vs.as_ls ||
6513 ctx->options->key.vs.as_es)
6514 return;
6515 outinfo = &ctx->shader_info->vs.outinfo;
6516 break;
6517 case MESA_SHADER_TESS_EVAL:
6518 if (ctx->options->key.vs.as_es)
6519 return;
6520 outinfo = &ctx->shader_info->tes.outinfo;
6521 break;
6522 default:
6523 unreachable("Unhandled shader type");
6524 }
6525
6526 ac_optimize_vs_outputs(&ctx->ac,
6527 ctx->main_function,
6528 outinfo->vs_output_param_offset,
6529 VARYING_SLOT_MAX,
6530 &outinfo->param_exports);
6531 }
6532
6533 static void
6534 ac_setup_rings(struct nir_to_llvm_context *ctx)
6535 {
6536 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6537 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6538 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6539 }
6540
6541 if (ctx->is_gs_copy_shader) {
6542 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6543 }
6544 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6545 LLVMValueRef tmp;
6546 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6547 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6548
6549 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6550
6551 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6552 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6553 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6554 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6555 }
6556
6557 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6558 ctx->stage == MESA_SHADER_TESS_EVAL) {
6559 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6560 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6561 }
6562 }
6563
6564 static unsigned
6565 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6566 const struct nir_shader *nir)
6567 {
6568 switch (nir->info.stage) {
6569 case MESA_SHADER_TESS_CTRL:
6570 return chip_class >= CIK ? 128 : 64;
6571 case MESA_SHADER_GEOMETRY:
6572 return chip_class >= GFX9 ? 128 : 64;
6573 case MESA_SHADER_COMPUTE:
6574 break;
6575 default:
6576 return 0;
6577 }
6578
6579 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6580 nir->info.cs.local_size[1] *
6581 nir->info.cs.local_size[2];
6582 return max_workgroup_size;
6583 }
6584
6585 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6586 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6587 {
6588 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6589 LLVMConstInt(ctx->ac.i32, 8, false),
6590 LLVMConstInt(ctx->ac.i32, 8, false), false);
6591 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6592 ctx->ac.i32_0, "");
6593 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6594 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6595 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6596 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6597 }
6598
6599 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6600 {
6601 for(int i = 5; i >= 0; --i) {
6602 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6603 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6604 LLVMConstInt(ctx->ac.i32, 16, false), false);
6605 }
6606
6607 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6608 LLVMConstInt(ctx->ac.i32, 16, false),
6609 LLVMConstInt(ctx->ac.i32, 8, false), false);
6610 }
6611
6612 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6613 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6614 {
6615 struct ac_nir_context ctx = {};
6616 struct nir_function *func;
6617
6618 ctx.ac = *ac;
6619 ctx.abi = abi;
6620
6621 ctx.nctx = nctx;
6622 if (nctx)
6623 nctx->nir = &ctx;
6624
6625 ctx.stage = nir->info.stage;
6626
6627 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6628
6629 nir_foreach_variable(variable, &nir->outputs)
6630 handle_shader_output_decl(&ctx, nir, variable);
6631
6632 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6633 _mesa_key_pointer_equal);
6634 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6635 _mesa_key_pointer_equal);
6636 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6637 _mesa_key_pointer_equal);
6638
6639 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6640
6641 setup_locals(&ctx, func);
6642
6643 if (nir->info.stage == MESA_SHADER_COMPUTE)
6644 setup_shared(&ctx, nir);
6645
6646 visit_cf_list(&ctx, &func->impl->body);
6647 phi_post_pass(&ctx);
6648
6649 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6650 ctx.outputs);
6651
6652 free(ctx.locals);
6653 ralloc_free(ctx.defs);
6654 ralloc_free(ctx.phis);
6655 ralloc_free(ctx.vars);
6656
6657 if (nctx)
6658 nctx->nir = NULL;
6659 }
6660
6661 static
6662 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6663 struct nir_shader *const *shaders,
6664 int shader_count,
6665 struct ac_shader_variant_info *shader_info,
6666 const struct ac_nir_compiler_options *options)
6667 {
6668 struct nir_to_llvm_context ctx = {0};
6669 unsigned i;
6670 ctx.options = options;
6671 ctx.shader_info = shader_info;
6672 ctx.context = LLVMContextCreate();
6673 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6674
6675 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6676 options->family);
6677 ctx.ac.module = ctx.module;
6678 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6679
6680 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6681 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6682 LLVMSetDataLayout(ctx.module, data_layout_str);
6683 LLVMDisposeTargetData(data_layout);
6684 LLVMDisposeMessage(data_layout_str);
6685
6686 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6687 ctx.ac.builder = ctx.builder;
6688
6689 memset(shader_info, 0, sizeof(*shader_info));
6690
6691 for(int i = 0; i < shader_count; ++i)
6692 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6693
6694 for (i = 0; i < AC_UD_MAX_SETS; i++)
6695 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6696 for (i = 0; i < AC_UD_MAX_UD; i++)
6697 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6698
6699 ctx.max_workgroup_size = 0;
6700 for (int i = 0; i < shader_count; ++i) {
6701 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6702 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6703 shaders[i]));
6704 }
6705
6706 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6707 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6708
6709 ctx.abi.inputs = &ctx.inputs[0];
6710 ctx.abi.emit_outputs = handle_shader_outputs_post;
6711 ctx.abi.emit_vertex = visit_emit_vertex;
6712 ctx.abi.load_ubo = radv_load_ubo;
6713 ctx.abi.load_ssbo = radv_load_ssbo;
6714 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6715 ctx.abi.clamp_shadow_reference = false;
6716
6717 if (shader_count >= 2)
6718 ac_init_exec_full_mask(&ctx.ac);
6719
6720 if (ctx.ac.chip_class == GFX9 &&
6721 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6722 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6723
6724 for(int i = 0; i < shader_count; ++i) {
6725 ctx.stage = shaders[i]->info.stage;
6726 ctx.output_mask = 0;
6727 ctx.tess_outputs_written = 0;
6728 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6729 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6730
6731 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6732 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6733 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6734 ctx.abi.load_inputs = load_gs_input;
6735 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6736 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6737 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6738 ctx.abi.load_tess_inputs = load_tcs_input;
6739 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6740 ctx.abi.store_tcs_outputs = store_tcs_output;
6741 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6742 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6743 ctx.abi.load_tess_inputs = load_tes_input;
6744 ctx.abi.load_tess_coord = load_tess_coord;
6745 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6746 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6747 if (shader_info->info.vs.needs_instance_id) {
6748 if (ctx.options->key.vs.as_ls) {
6749 ctx.shader_info->vs.vgpr_comp_cnt =
6750 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6751 } else {
6752 ctx.shader_info->vs.vgpr_comp_cnt =
6753 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6754 }
6755 }
6756 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6757 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6758 }
6759
6760 if (i)
6761 emit_barrier(&ctx.ac, ctx.stage);
6762
6763 ac_setup_rings(&ctx);
6764
6765 LLVMBasicBlockRef merge_block;
6766 if (shader_count >= 2) {
6767 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6768 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6769 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6770
6771 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6772 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6773 LLVMConstInt(ctx.ac.i32, 8, false), false);
6774 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6775 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6776 thread_id, count, "");
6777 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6778
6779 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6780 }
6781
6782 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6783 handle_fs_inputs(&ctx, shaders[i]);
6784 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6785 handle_vs_inputs(&ctx, shaders[i]);
6786 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6787 prepare_gs_input_vgprs(&ctx);
6788
6789 nir_foreach_variable(variable, &shaders[i]->outputs)
6790 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6791
6792 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6793
6794 if (shader_count >= 2) {
6795 LLVMBuildBr(ctx.ac.builder, merge_block);
6796 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6797 }
6798
6799 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6800 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6801 shaders[i]->info.cull_distance_array_size > 4;
6802 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6803 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6804 shaders[i]->info.gs.vertices_out;
6805 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6806 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6807 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6808 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6809 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6810 }
6811 }
6812
6813 LLVMBuildRetVoid(ctx.builder);
6814
6815 ac_llvm_finalize_module(&ctx);
6816
6817 if (shader_count == 1)
6818 ac_nir_eliminate_const_vs_outputs(&ctx);
6819
6820 return ctx.module;
6821 }
6822
6823 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6824 {
6825 unsigned *retval = (unsigned *)context;
6826 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6827 char *description = LLVMGetDiagInfoDescription(di);
6828
6829 if (severity == LLVMDSError) {
6830 *retval = 1;
6831 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6832 description);
6833 }
6834
6835 LLVMDisposeMessage(description);
6836 }
6837
6838 static unsigned ac_llvm_compile(LLVMModuleRef M,
6839 struct ac_shader_binary *binary,
6840 LLVMTargetMachineRef tm)
6841 {
6842 unsigned retval = 0;
6843 char *err;
6844 LLVMContextRef llvm_ctx;
6845 LLVMMemoryBufferRef out_buffer;
6846 unsigned buffer_size;
6847 const char *buffer_data;
6848 LLVMBool mem_err;
6849
6850 /* Setup Diagnostic Handler*/
6851 llvm_ctx = LLVMGetModuleContext(M);
6852
6853 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6854 &retval);
6855
6856 /* Compile IR*/
6857 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6858 &err, &out_buffer);
6859
6860 /* Process Errors/Warnings */
6861 if (mem_err) {
6862 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6863 free(err);
6864 retval = 1;
6865 goto out;
6866 }
6867
6868 /* Extract Shader Code*/
6869 buffer_size = LLVMGetBufferSize(out_buffer);
6870 buffer_data = LLVMGetBufferStart(out_buffer);
6871
6872 ac_elf_read(buffer_data, buffer_size, binary);
6873
6874 /* Clean up */
6875 LLVMDisposeMemoryBuffer(out_buffer);
6876
6877 out:
6878 return retval;
6879 }
6880
6881 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6882 LLVMModuleRef llvm_module,
6883 struct ac_shader_binary *binary,
6884 struct ac_shader_config *config,
6885 struct ac_shader_variant_info *shader_info,
6886 gl_shader_stage stage,
6887 bool dump_shader, bool supports_spill)
6888 {
6889 if (dump_shader)
6890 ac_dump_module(llvm_module);
6891
6892 memset(binary, 0, sizeof(*binary));
6893 int v = ac_llvm_compile(llvm_module, binary, tm);
6894 if (v) {
6895 fprintf(stderr, "compile failed\n");
6896 }
6897
6898 if (dump_shader)
6899 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6900
6901 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6902
6903 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6904 LLVMDisposeModule(llvm_module);
6905 LLVMContextDispose(ctx);
6906
6907 if (stage == MESA_SHADER_FRAGMENT) {
6908 shader_info->num_input_vgprs = 0;
6909 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6910 shader_info->num_input_vgprs += 2;
6911 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6912 shader_info->num_input_vgprs += 2;
6913 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6914 shader_info->num_input_vgprs += 2;
6915 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6916 shader_info->num_input_vgprs += 3;
6917 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6918 shader_info->num_input_vgprs += 2;
6919 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6920 shader_info->num_input_vgprs += 2;
6921 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6922 shader_info->num_input_vgprs += 2;
6923 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6924 shader_info->num_input_vgprs += 1;
6925 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6926 shader_info->num_input_vgprs += 1;
6927 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6928 shader_info->num_input_vgprs += 1;
6929 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6930 shader_info->num_input_vgprs += 1;
6931 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6932 shader_info->num_input_vgprs += 1;
6933 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6934 shader_info->num_input_vgprs += 1;
6935 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6936 shader_info->num_input_vgprs += 1;
6937 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6938 shader_info->num_input_vgprs += 1;
6939 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6940 shader_info->num_input_vgprs += 1;
6941 }
6942 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6943
6944 /* +3 for scratch wave offset and VCC */
6945 config->num_sgprs = MAX2(config->num_sgprs,
6946 shader_info->num_input_sgprs + 3);
6947
6948 /* Enable 64-bit and 16-bit denormals, because there is no performance
6949 * cost.
6950 *
6951 * If denormals are enabled, all floating-point output modifiers are
6952 * ignored.
6953 *
6954 * Don't enable denormals for 32-bit floats, because:
6955 * - Floating-point output modifiers would be ignored by the hw.
6956 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6957 * have to stop using those.
6958 * - SI & CI would be very slow.
6959 */
6960 config->float_mode |= V_00B028_FP_64_DENORMS;
6961 }
6962
6963 static void
6964 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6965 {
6966 switch (nir->info.stage) {
6967 case MESA_SHADER_COMPUTE:
6968 for (int i = 0; i < 3; ++i)
6969 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6970 break;
6971 case MESA_SHADER_FRAGMENT:
6972 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6973 break;
6974 case MESA_SHADER_GEOMETRY:
6975 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6976 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6977 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6978 shader_info->gs.invocations = nir->info.gs.invocations;
6979 break;
6980 case MESA_SHADER_TESS_EVAL:
6981 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6982 shader_info->tes.spacing = nir->info.tess.spacing;
6983 shader_info->tes.ccw = nir->info.tess.ccw;
6984 shader_info->tes.point_mode = nir->info.tess.point_mode;
6985 shader_info->tes.as_es = options->key.tes.as_es;
6986 break;
6987 case MESA_SHADER_TESS_CTRL:
6988 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6989 break;
6990 case MESA_SHADER_VERTEX:
6991 shader_info->vs.as_es = options->key.vs.as_es;
6992 shader_info->vs.as_ls = options->key.vs.as_ls;
6993 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
6994 if (options->key.vs.as_ls)
6995 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6996 break;
6997 default:
6998 break;
6999 }
7000 }
7001
7002 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7003 struct ac_shader_binary *binary,
7004 struct ac_shader_config *config,
7005 struct ac_shader_variant_info *shader_info,
7006 struct nir_shader *const *nir,
7007 int nir_count,
7008 const struct ac_nir_compiler_options *options,
7009 bool dump_shader)
7010 {
7011
7012 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7013 options);
7014
7015 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7016 for (int i = 0; i < nir_count; ++i)
7017 ac_fill_shader_info(shader_info, nir[i], options);
7018
7019 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7020 if (options->chip_class == GFX9) {
7021 if (nir_count == 2 &&
7022 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7023 shader_info->gs.es_type = nir[0]->info.stage;
7024 }
7025 }
7026 }
7027
7028 static void
7029 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7030 {
7031 LLVMValueRef args[9];
7032 args[0] = ctx->gsvs_ring;
7033 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
7034 args[3] = ctx->ac.i32_0;
7035 args[4] = ctx->ac.i32_1; /* OFFEN */
7036 args[5] = ctx->ac.i32_0; /* IDXEN */
7037 args[6] = ctx->ac.i32_1; /* GLC */
7038 args[7] = ctx->ac.i32_1; /* SLC */
7039 args[8] = ctx->ac.i32_0; /* TFE */
7040
7041 int idx = 0;
7042
7043 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7044 int length = 4;
7045 int slot = idx;
7046 int slot_inc = 1;
7047 if (!(ctx->output_mask & (1ull << i)))
7048 continue;
7049
7050 if (i == VARYING_SLOT_CLIP_DIST0) {
7051 /* unpack clip and cull from a single set of slots */
7052 length = ctx->num_output_clips + ctx->num_output_culls;
7053 if (length > 4)
7054 slot_inc = 2;
7055 }
7056
7057 for (unsigned j = 0; j < length; j++) {
7058 LLVMValueRef value;
7059 args[2] = LLVMConstInt(ctx->ac.i32,
7060 (slot * 4 + j) *
7061 ctx->gs_max_out_vertices * 16 * 4, false);
7062
7063 value = ac_build_intrinsic(&ctx->ac,
7064 "llvm.SI.buffer.load.dword.i32.i32",
7065 ctx->ac.i32, args, 9,
7066 AC_FUNC_ATTR_READONLY |
7067 AC_FUNC_ATTR_LEGACY);
7068
7069 LLVMBuildStore(ctx->builder,
7070 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7071 }
7072 idx += slot_inc;
7073 }
7074 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7075 }
7076
7077 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7078 struct nir_shader *geom_shader,
7079 struct ac_shader_binary *binary,
7080 struct ac_shader_config *config,
7081 struct ac_shader_variant_info *shader_info,
7082 const struct ac_nir_compiler_options *options,
7083 bool dump_shader)
7084 {
7085 struct nir_to_llvm_context ctx = {0};
7086 ctx.context = LLVMContextCreate();
7087 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7088 ctx.options = options;
7089 ctx.shader_info = shader_info;
7090
7091 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7092 options->family);
7093 ctx.ac.module = ctx.module;
7094
7095 ctx.is_gs_copy_shader = true;
7096 LLVMSetTarget(ctx.module, "amdgcn--");
7097
7098 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7099 ctx.ac.builder = ctx.builder;
7100 ctx.stage = MESA_SHADER_VERTEX;
7101
7102 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7103
7104 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7105 ac_setup_rings(&ctx);
7106
7107 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7108 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7109
7110 struct ac_nir_context nir_ctx = {};
7111 nir_ctx.ac = ctx.ac;
7112 nir_ctx.abi = &ctx.abi;
7113
7114 nir_ctx.nctx = &ctx;
7115 ctx.nir = &nir_ctx;
7116
7117 nir_foreach_variable(variable, &geom_shader->outputs) {
7118 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7119 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7120 }
7121
7122 ac_gs_copy_shader_emit(&ctx);
7123
7124 ctx.nir = NULL;
7125
7126 LLVMBuildRetVoid(ctx.builder);
7127
7128 ac_llvm_finalize_module(&ctx);
7129
7130 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7131 MESA_SHADER_VERTEX,
7132 dump_shader, options->supports_spill);
7133 }