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ac: call load_tcs_input() via the abi
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tcs_patch_id;
115 LLVMValueRef tcs_rel_ids;
116 LLVMValueRef tes_rel_patch_id;
117 LLVMValueRef tes_patch_id;
118 LLVMValueRef tes_u;
119 LLVMValueRef tes_v;
120
121 LLVMValueRef gsvs_ring_stride;
122 LLVMValueRef gsvs_num_entries;
123 LLVMValueRef gs2vs_offset;
124 LLVMValueRef gs_wave_id;
125 LLVMValueRef gs_vtx_offset[6];
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 gl_shader_stage stage;
138
139 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
140
141 uint64_t input_mask;
142 uint64_t output_mask;
143 uint8_t num_output_clips;
144 uint8_t num_output_culls;
145
146 bool is_gs_copy_shader;
147 LLVMValueRef gs_next_vertex;
148 unsigned gs_max_out_vertices;
149
150 unsigned tes_primitive_mode;
151 uint64_t tess_outputs_written;
152 uint64_t tess_patch_outputs_written;
153
154 uint32_t tcs_patch_outputs_read;
155 uint64_t tcs_outputs_read;
156 };
157
158 static inline struct nir_to_llvm_context *
159 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
160 {
161 struct nir_to_llvm_context *ctx = NULL;
162 return container_of(abi, ctx, abi);
163 }
164
165 static LLVMTypeRef
166 nir2llvmtype(struct ac_nir_context *ctx,
167 const struct glsl_type *type)
168 {
169 switch (glsl_get_base_type(glsl_without_array(type))) {
170 case GLSL_TYPE_UINT:
171 case GLSL_TYPE_INT:
172 return ctx->ac.i32;
173 case GLSL_TYPE_UINT64:
174 case GLSL_TYPE_INT64:
175 return ctx->ac.i64;
176 case GLSL_TYPE_DOUBLE:
177 return ctx->ac.f64;
178 case GLSL_TYPE_FLOAT:
179 return ctx->ac.f32;
180 default:
181 assert(!"Unsupported type in nir2llvmtype()");
182 break;
183 }
184 return 0;
185 }
186
187 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
188 const nir_deref_var *deref,
189 enum ac_descriptor_type desc_type,
190 const nir_tex_instr *instr,
191 bool image, bool write);
192
193 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
194 {
195 return (index * 4) + chan;
196 }
197
198 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
199 {
200 /* handle patch indices separate */
201 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
202 return 0;
203 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
204 return 1;
205 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
206 return 2 + (slot - VARYING_SLOT_PATCH0);
207
208 if (slot == VARYING_SLOT_POS)
209 return 0;
210 if (slot == VARYING_SLOT_PSIZ)
211 return 1;
212 if (slot == VARYING_SLOT_CLIP_DIST0)
213 return 2;
214 /* 3 is reserved for clip dist as well */
215 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
216 return 4 + (slot - VARYING_SLOT_VAR0);
217 unreachable("illegal slot in get unique index\n");
218 }
219
220 static void set_llvm_calling_convention(LLVMValueRef func,
221 gl_shader_stage stage)
222 {
223 enum radeon_llvm_calling_convention calling_conv;
224
225 switch (stage) {
226 case MESA_SHADER_VERTEX:
227 case MESA_SHADER_TESS_EVAL:
228 calling_conv = RADEON_LLVM_AMDGPU_VS;
229 break;
230 case MESA_SHADER_GEOMETRY:
231 calling_conv = RADEON_LLVM_AMDGPU_GS;
232 break;
233 case MESA_SHADER_TESS_CTRL:
234 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
235 break;
236 case MESA_SHADER_FRAGMENT:
237 calling_conv = RADEON_LLVM_AMDGPU_PS;
238 break;
239 case MESA_SHADER_COMPUTE:
240 calling_conv = RADEON_LLVM_AMDGPU_CS;
241 break;
242 default:
243 unreachable("Unhandle shader type");
244 }
245
246 LLVMSetFunctionCallConv(func, calling_conv);
247 }
248
249 #define MAX_ARGS 23
250 struct arg_info {
251 LLVMTypeRef types[MAX_ARGS];
252 LLVMValueRef *assign[MAX_ARGS];
253 unsigned array_params_mask;
254 uint8_t count;
255 uint8_t sgpr_count;
256 uint8_t num_sgprs_used;
257 uint8_t num_vgprs_used;
258 };
259
260 enum ac_arg_regfile {
261 ARG_SGPR,
262 ARG_VGPR,
263 };
264
265 static void
266 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
267 LLVMValueRef *param_ptr)
268 {
269 assert(info->count < MAX_ARGS);
270
271 info->assign[info->count] = param_ptr;
272 info->types[info->count] = type;
273 info->count++;
274
275 if (regfile == ARG_SGPR) {
276 info->num_sgprs_used += ac_get_type_size(type) / 4;
277 info->sgpr_count++;
278 } else {
279 assert(regfile == ARG_VGPR);
280 info->num_vgprs_used += ac_get_type_size(type) / 4;
281 }
282 }
283
284 static inline void
285 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
286 {
287 info->array_params_mask |= (1 << info->count);
288 add_arg(info, ARG_SGPR, type, param_ptr);
289 }
290
291 static void assign_arguments(LLVMValueRef main_function,
292 struct arg_info *info)
293 {
294 unsigned i;
295 for (i = 0; i < info->count; i++) {
296 if (info->assign[i])
297 *info->assign[i] = LLVMGetParam(main_function, i);
298 }
299 }
300
301 static LLVMValueRef
302 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
303 LLVMBuilderRef builder, LLVMTypeRef *return_types,
304 unsigned num_return_elems,
305 struct arg_info *args,
306 unsigned max_workgroup_size,
307 bool unsafe_math)
308 {
309 LLVMTypeRef main_function_type, ret_type;
310 LLVMBasicBlockRef main_function_body;
311
312 if (num_return_elems)
313 ret_type = LLVMStructTypeInContext(ctx, return_types,
314 num_return_elems, true);
315 else
316 ret_type = LLVMVoidTypeInContext(ctx);
317
318 /* Setup the function */
319 main_function_type =
320 LLVMFunctionType(ret_type, args->types, args->count, 0);
321 LLVMValueRef main_function =
322 LLVMAddFunction(module, "main", main_function_type);
323 main_function_body =
324 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
325 LLVMPositionBuilderAtEnd(builder, main_function_body);
326
327 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
328 for (unsigned i = 0; i < args->sgpr_count; ++i) {
329 if (args->array_params_mask & (1 << i)) {
330 LLVMValueRef P = LLVMGetParam(main_function, i);
331 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
332 ac_add_attr_dereferenceable(P, UINT64_MAX);
333 }
334 else {
335 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
336 }
337 }
338
339 if (max_workgroup_size) {
340 ac_llvm_add_target_dep_function_attr(main_function,
341 "amdgpu-max-work-group-size",
342 max_workgroup_size);
343 }
344 if (unsafe_math) {
345 /* These were copied from some LLVM test. */
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "less-precise-fpmad",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-infs-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "no-nans-fp-math",
354 "true");
355 LLVMAddTargetDependentFunctionAttr(main_function,
356 "unsafe-fp-math",
357 "true");
358 }
359 return main_function;
360 }
361
362 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
363 {
364 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
365 CONST_ADDR_SPACE);
366 }
367
368 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
369 {
370 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
371 type = LLVMGetElementType(type);
372
373 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
374 return LLVMGetIntTypeWidth(type);
375
376 if (type == ctx->f16)
377 return 16;
378 if (type == ctx->f32)
379 return 32;
380 if (type == ctx->f64)
381 return 64;
382
383 unreachable("Unhandled type kind in get_elem_bits");
384 }
385
386 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
387 LLVMValueRef param, unsigned rshift,
388 unsigned bitwidth)
389 {
390 LLVMValueRef value = param;
391 if (rshift)
392 value = LLVMBuildLShr(ctx->builder, value,
393 LLVMConstInt(ctx->i32, rshift, false), "");
394
395 if (rshift + bitwidth < 32) {
396 unsigned mask = (1 << bitwidth) - 1;
397 value = LLVMBuildAnd(ctx->builder, value,
398 LLVMConstInt(ctx->i32, mask, false), "");
399 }
400 return value;
401 }
402
403 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
404 {
405 switch (ctx->stage) {
406 case MESA_SHADER_TESS_CTRL:
407 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
408 case MESA_SHADER_TESS_EVAL:
409 return ctx->tes_rel_patch_id;
410 break;
411 default:
412 unreachable("Illegal stage");
413 }
414 }
415
416 /* Tessellation shaders pass outputs to the next shader using LDS.
417 *
418 * LS outputs = TCS inputs
419 * TCS outputs = TES inputs
420 *
421 * The LDS layout is:
422 * - TCS inputs for patch 0
423 * - TCS inputs for patch 1
424 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
425 * - ...
426 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
427 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
428 * - TCS outputs for patch 1
429 * - Per-patch TCS outputs for patch 1
430 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
431 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
432 * - ...
433 *
434 * All three shaders VS(LS), TCS, TES share the same LDS space.
435 */
436 static LLVMValueRef
437 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
438 {
439 if (ctx->stage == MESA_SHADER_VERTEX)
440 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
441 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
442 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
443 else {
444 assert(0);
445 return NULL;
446 }
447 }
448
449 static LLVMValueRef
450 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
451 {
452 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
453 }
454
455 static LLVMValueRef
456 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
457 {
458 return LLVMBuildMul(ctx->builder,
459 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
460 LLVMConstInt(ctx->ac.i32, 4, false), "");
461 }
462
463 static LLVMValueRef
464 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
465 {
466 return LLVMBuildMul(ctx->builder,
467 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
468 LLVMConstInt(ctx->ac.i32, 4, false), "");
469 }
470
471 static LLVMValueRef
472 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
473 {
474 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
475 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
476
477 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
478 }
479
480 static LLVMValueRef
481 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
482 {
483 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
484 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
485 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
486
487 return LLVMBuildAdd(ctx->builder, patch0_offset,
488 LLVMBuildMul(ctx->builder, patch_stride,
489 rel_patch_id, ""),
490 "");
491 }
492
493 static LLVMValueRef
494 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
495 {
496 LLVMValueRef patch0_patch_data_offset =
497 get_tcs_out_patch0_patch_data_offset(ctx);
498 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
499 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
500
501 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
502 LLVMBuildMul(ctx->builder, patch_stride,
503 rel_patch_id, ""),
504 "");
505 }
506
507 static void
508 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
509 uint32_t indirect_offset)
510 {
511 ud_info->sgpr_idx = *sgpr_idx;
512 ud_info->num_sgprs = num_sgprs;
513 ud_info->indirect = indirect_offset > 0;
514 ud_info->indirect_offset = indirect_offset;
515 *sgpr_idx += num_sgprs;
516 }
517
518 static void
519 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
520 uint8_t num_sgprs)
521 {
522 struct ac_userdata_info *ud_info =
523 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
524 assert(ud_info);
525
526 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
527 }
528
529 static void
530 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
531 uint32_t indirect_offset)
532 {
533 struct ac_userdata_info *ud_info =
534 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
535 assert(ud_info);
536
537 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
538 }
539
540 struct user_sgpr_info {
541 bool need_ring_offsets;
542 uint8_t sgpr_count;
543 bool indirect_all_descriptor_sets;
544 };
545
546 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
547 struct user_sgpr_info *user_sgpr_info)
548 {
549 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
550
551 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
552 if (ctx->stage == MESA_SHADER_GEOMETRY ||
553 ctx->stage == MESA_SHADER_VERTEX ||
554 ctx->stage == MESA_SHADER_TESS_CTRL ||
555 ctx->stage == MESA_SHADER_TESS_EVAL ||
556 ctx->is_gs_copy_shader)
557 user_sgpr_info->need_ring_offsets = true;
558
559 if (ctx->stage == MESA_SHADER_FRAGMENT &&
560 ctx->shader_info->info.ps.needs_sample_positions)
561 user_sgpr_info->need_ring_offsets = true;
562
563 /* 2 user sgprs will nearly always be allocated for scratch/rings */
564 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
565 user_sgpr_info->sgpr_count += 2;
566 }
567
568 switch (ctx->stage) {
569 case MESA_SHADER_COMPUTE:
570 if (ctx->shader_info->info.cs.uses_grid_size)
571 user_sgpr_info->sgpr_count += 3;
572 break;
573 case MESA_SHADER_FRAGMENT:
574 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
575 break;
576 case MESA_SHADER_VERTEX:
577 if (!ctx->is_gs_copy_shader) {
578 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
579 if (ctx->shader_info->info.vs.needs_draw_id) {
580 user_sgpr_info->sgpr_count += 3;
581 } else {
582 user_sgpr_info->sgpr_count += 2;
583 }
584 }
585 if (ctx->options->key.vs.as_ls)
586 user_sgpr_info->sgpr_count++;
587 break;
588 case MESA_SHADER_TESS_CTRL:
589 user_sgpr_info->sgpr_count += 4;
590 break;
591 case MESA_SHADER_TESS_EVAL:
592 user_sgpr_info->sgpr_count += 1;
593 break;
594 case MESA_SHADER_GEOMETRY:
595 user_sgpr_info->sgpr_count += 2;
596 break;
597 default:
598 break;
599 }
600
601 if (ctx->shader_info->info.needs_push_constants)
602 user_sgpr_info->sgpr_count += 2;
603
604 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
605 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
606 user_sgpr_info->sgpr_count += 2;
607 user_sgpr_info->indirect_all_descriptor_sets = true;
608 } else {
609 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
610 }
611 }
612
613 static void
614 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
615 gl_shader_stage stage,
616 bool has_previous_stage,
617 gl_shader_stage previous_stage,
618 const struct user_sgpr_info *user_sgpr_info,
619 struct arg_info *args,
620 LLVMValueRef *desc_sets)
621 {
622 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
623 unsigned num_sets = ctx->options->layout ?
624 ctx->options->layout->num_sets : 0;
625 unsigned stage_mask = 1 << stage;
626
627 if (has_previous_stage)
628 stage_mask |= 1 << previous_stage;
629
630 /* 1 for each descriptor set */
631 if (!user_sgpr_info->indirect_all_descriptor_sets) {
632 for (unsigned i = 0; i < num_sets; ++i) {
633 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
634 add_array_arg(args, type,
635 &ctx->descriptor_sets[i]);
636 }
637 }
638 } else {
639 add_array_arg(args, const_array(type, 32), desc_sets);
640 }
641
642 if (ctx->shader_info->info.needs_push_constants) {
643 /* 1 for push constants and dynamic descriptors */
644 add_array_arg(args, type, &ctx->push_constants);
645 }
646 }
647
648 static void
649 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
650 gl_shader_stage stage,
651 bool has_previous_stage,
652 gl_shader_stage previous_stage,
653 struct arg_info *args)
654 {
655 if (!ctx->is_gs_copy_shader &&
656 (stage == MESA_SHADER_VERTEX ||
657 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
658 if (ctx->shader_info->info.vs.has_vertex_buffers) {
659 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
660 &ctx->vertex_buffers);
661 }
662 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
663 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
664 if (ctx->shader_info->info.vs.needs_draw_id) {
665 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
666 }
667 }
668 }
669
670 static void
671 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
672 {
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
674 if (!ctx->is_gs_copy_shader) {
675 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
676 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
677 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
678 }
679 }
680
681 static void
682 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
683 {
684 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
685 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
686 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
687 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_patch_id);
688 }
689
690 static void
691 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
692 bool has_previous_stage, gl_shader_stage previous_stage,
693 const struct user_sgpr_info *user_sgpr_info,
694 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
695 {
696 unsigned num_sets = ctx->options->layout ?
697 ctx->options->layout->num_sets : 0;
698 unsigned stage_mask = 1 << stage;
699
700 if (has_previous_stage)
701 stage_mask |= 1 << previous_stage;
702
703 if (!user_sgpr_info->indirect_all_descriptor_sets) {
704 for (unsigned i = 0; i < num_sets; ++i) {
705 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
706 set_loc_desc(ctx, i, user_sgpr_idx, 0);
707 } else
708 ctx->descriptor_sets[i] = NULL;
709 }
710 } else {
711 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
712 user_sgpr_idx, 2);
713
714 for (unsigned i = 0; i < num_sets; ++i) {
715 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
716 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
717 ctx->descriptor_sets[i] =
718 ac_build_load_to_sgpr(&ctx->ac,
719 desc_sets,
720 LLVMConstInt(ctx->ac.i32, i, false));
721
722 } else
723 ctx->descriptor_sets[i] = NULL;
724 }
725 ctx->shader_info->need_indirect_descriptor_sets = true;
726 }
727
728 if (ctx->shader_info->info.needs_push_constants) {
729 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
730 }
731 }
732
733 static void
734 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
735 gl_shader_stage stage, bool has_previous_stage,
736 gl_shader_stage previous_stage,
737 uint8_t *user_sgpr_idx)
738 {
739 if (!ctx->is_gs_copy_shader &&
740 (stage == MESA_SHADER_VERTEX ||
741 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
742 if (ctx->shader_info->info.vs.has_vertex_buffers) {
743 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
744 user_sgpr_idx, 2);
745 }
746
747 unsigned vs_num = 2;
748 if (ctx->shader_info->info.vs.needs_draw_id)
749 vs_num++;
750
751 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
752 user_sgpr_idx, vs_num);
753 }
754 }
755
756 static void create_function(struct nir_to_llvm_context *ctx,
757 gl_shader_stage stage,
758 bool has_previous_stage,
759 gl_shader_stage previous_stage)
760 {
761 uint8_t user_sgpr_idx;
762 struct user_sgpr_info user_sgpr_info;
763 struct arg_info args = {};
764 LLVMValueRef desc_sets;
765
766 allocate_user_sgprs(ctx, &user_sgpr_info);
767
768 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
769 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
770 &ctx->ring_offsets);
771 }
772
773 switch (stage) {
774 case MESA_SHADER_COMPUTE:
775 declare_global_input_sgprs(ctx, stage, has_previous_stage,
776 previous_stage, &user_sgpr_info,
777 &args, &desc_sets);
778
779 if (ctx->shader_info->info.cs.uses_grid_size) {
780 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
781 &ctx->num_work_groups);
782 }
783
784 for (int i = 0; i < 3; i++) {
785 ctx->workgroup_ids[i] = NULL;
786 if (ctx->shader_info->info.cs.uses_block_id[i]) {
787 add_arg(&args, ARG_SGPR, ctx->ac.i32,
788 &ctx->workgroup_ids[i]);
789 }
790 }
791
792 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
793 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
794 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
795 &ctx->local_invocation_ids);
796 break;
797 case MESA_SHADER_VERTEX:
798 declare_global_input_sgprs(ctx, stage, has_previous_stage,
799 previous_stage, &user_sgpr_info,
800 &args, &desc_sets);
801 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
802 previous_stage, &args);
803
804 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
805 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
806 if (ctx->options->key.vs.as_es)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->es2gs_offset);
809 else if (ctx->options->key.vs.as_ls)
810 add_arg(&args, ARG_SGPR, ctx->ac.i32,
811 &ctx->ls_out_layout);
812
813 declare_vs_input_vgprs(ctx, &args);
814 break;
815 case MESA_SHADER_TESS_CTRL:
816 if (has_previous_stage) {
817 // First 6 system regs
818 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
819 add_arg(&args, ARG_SGPR, ctx->ac.i32,
820 &ctx->merged_wave_info);
821 add_arg(&args, ARG_SGPR, ctx->ac.i32,
822 &ctx->tess_factor_offset);
823
824 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
825 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
826 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
827
828 declare_global_input_sgprs(ctx, stage,
829 has_previous_stage,
830 previous_stage,
831 &user_sgpr_info, &args,
832 &desc_sets);
833 declare_vs_specific_input_sgprs(ctx, stage,
834 has_previous_stage,
835 previous_stage, &args);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->ls_out_layout);
839
840 add_arg(&args, ARG_SGPR, ctx->ac.i32,
841 &ctx->tcs_offchip_layout);
842 add_arg(&args, ARG_SGPR, ctx->ac.i32,
843 &ctx->tcs_out_offsets);
844 add_arg(&args, ARG_SGPR, ctx->ac.i32,
845 &ctx->tcs_out_layout);
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->tcs_in_layout);
848 if (ctx->shader_info->info.needs_multiview_view_index)
849 add_arg(&args, ARG_SGPR, ctx->ac.i32,
850 &ctx->view_index);
851
852 add_arg(&args, ARG_VGPR, ctx->ac.i32,
853 &ctx->tcs_patch_id);
854 add_arg(&args, ARG_VGPR, ctx->ac.i32,
855 &ctx->tcs_rel_ids);
856
857 declare_vs_input_vgprs(ctx, &args);
858 } else {
859 declare_global_input_sgprs(ctx, stage,
860 has_previous_stage,
861 previous_stage,
862 &user_sgpr_info, &args,
863 &desc_sets);
864
865 add_arg(&args, ARG_SGPR, ctx->ac.i32,
866 &ctx->tcs_offchip_layout);
867 add_arg(&args, ARG_SGPR, ctx->ac.i32,
868 &ctx->tcs_out_offsets);
869 add_arg(&args, ARG_SGPR, ctx->ac.i32,
870 &ctx->tcs_out_layout);
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->tcs_in_layout);
873 if (ctx->shader_info->info.needs_multiview_view_index)
874 add_arg(&args, ARG_SGPR, ctx->ac.i32,
875 &ctx->view_index);
876
877 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
878 add_arg(&args, ARG_SGPR, ctx->ac.i32,
879 &ctx->tess_factor_offset);
880 add_arg(&args, ARG_VGPR, ctx->ac.i32,
881 &ctx->tcs_patch_id);
882 add_arg(&args, ARG_VGPR, ctx->ac.i32,
883 &ctx->tcs_rel_ids);
884 }
885 break;
886 case MESA_SHADER_TESS_EVAL:
887 declare_global_input_sgprs(ctx, stage, has_previous_stage,
888 previous_stage, &user_sgpr_info,
889 &args, &desc_sets);
890
891 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
892 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
894
895 if (ctx->options->key.tes.as_es) {
896 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
897 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
898 add_arg(&args, ARG_SGPR, ctx->ac.i32,
899 &ctx->es2gs_offset);
900 } else {
901 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
902 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
903 }
904 declare_tes_input_vgprs(ctx, &args);
905 break;
906 case MESA_SHADER_GEOMETRY:
907 if (has_previous_stage) {
908 // First 6 system regs
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->gs2vs_offset);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32,
912 &ctx->merged_wave_info);
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
914
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
916 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
917 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
918
919 declare_global_input_sgprs(ctx, stage,
920 has_previous_stage,
921 previous_stage,
922 &user_sgpr_info, &args,
923 &desc_sets);
924
925 if (previous_stage == MESA_SHADER_TESS_EVAL) {
926 add_arg(&args, ARG_SGPR, ctx->ac.i32,
927 &ctx->tcs_offchip_layout);
928 } else {
929 declare_vs_specific_input_sgprs(ctx, stage,
930 has_previous_stage,
931 previous_stage,
932 &args);
933 }
934
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_ring_stride);
937 add_arg(&args, ARG_SGPR, ctx->ac.i32,
938 &ctx->gsvs_num_entries);
939 if (ctx->shader_info->info.needs_multiview_view_index)
940 add_arg(&args, ARG_SGPR, ctx->ac.i32,
941 &ctx->view_index);
942
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[0]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->gs_vtx_offset[2]);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_prim_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->abi.gs_invocation_id);
951 add_arg(&args, ARG_VGPR, ctx->ac.i32,
952 &ctx->gs_vtx_offset[4]);
953
954 if (previous_stage == MESA_SHADER_VERTEX) {
955 declare_vs_input_vgprs(ctx, &args);
956 } else {
957 declare_tes_input_vgprs(ctx, &args);
958 }
959 } else {
960 declare_global_input_sgprs(ctx, stage,
961 has_previous_stage,
962 previous_stage,
963 &user_sgpr_info, &args,
964 &desc_sets);
965
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_ring_stride);
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->gsvs_num_entries);
970 if (ctx->shader_info->info.needs_multiview_view_index)
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->view_index);
973
974 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
975 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[0]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->gs_vtx_offset[1]);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->abi.gs_prim_id);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[2]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[3]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[4]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->gs_vtx_offset[5]);
990 add_arg(&args, ARG_VGPR, ctx->ac.i32,
991 &ctx->abi.gs_invocation_id);
992 }
993 break;
994 case MESA_SHADER_FRAGMENT:
995 declare_global_input_sgprs(ctx, stage, has_previous_stage,
996 previous_stage, &user_sgpr_info,
997 &args, &desc_sets);
998
999 if (ctx->shader_info->info.ps.needs_sample_positions)
1000 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1001 &ctx->sample_pos_offset);
1002
1003 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1009 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1010 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1015 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1018 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1019 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1020 break;
1021 default:
1022 unreachable("Shader stage not implemented");
1023 }
1024
1025 ctx->main_function = create_llvm_function(
1026 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1027 ctx->max_workgroup_size,
1028 ctx->options->unsafe_math);
1029 set_llvm_calling_convention(ctx->main_function, stage);
1030
1031
1032 ctx->shader_info->num_input_vgprs = 0;
1033 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1034
1035 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1036
1037 if (ctx->stage != MESA_SHADER_FRAGMENT)
1038 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1039
1040 assign_arguments(ctx->main_function, &args);
1041
1042 user_sgpr_idx = 0;
1043
1044 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1045 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1046 &user_sgpr_idx, 2);
1047 if (ctx->options->supports_spill) {
1048 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1049 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1050 NULL, 0, AC_FUNC_ATTR_READNONE);
1051 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1052 const_array(ctx->ac.v4i32, 16), "");
1053 }
1054 }
1055
1056 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1057 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1058 if (has_previous_stage)
1059 user_sgpr_idx = 0;
1060
1061 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1062 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1063
1064 switch (stage) {
1065 case MESA_SHADER_COMPUTE:
1066 if (ctx->shader_info->info.cs.uses_grid_size) {
1067 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1068 &user_sgpr_idx, 3);
1069 }
1070 break;
1071 case MESA_SHADER_VERTEX:
1072 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1073 previous_stage, &user_sgpr_idx);
1074 if (ctx->view_index)
1075 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1076 if (ctx->options->key.vs.as_ls) {
1077 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1078 &user_sgpr_idx, 1);
1079 }
1080 if (ctx->options->key.vs.as_ls)
1081 ac_declare_lds_as_pointer(&ctx->ac);
1082 break;
1083 case MESA_SHADER_TESS_CTRL:
1084 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1085 previous_stage, &user_sgpr_idx);
1086 if (has_previous_stage)
1087 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1088 &user_sgpr_idx, 1);
1089 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1090 if (ctx->view_index)
1091 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1092 ac_declare_lds_as_pointer(&ctx->ac);
1093 break;
1094 case MESA_SHADER_TESS_EVAL:
1095 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1096 if (ctx->view_index)
1097 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1098 break;
1099 case MESA_SHADER_GEOMETRY:
1100 if (has_previous_stage) {
1101 if (previous_stage == MESA_SHADER_VERTEX)
1102 set_vs_specific_input_locs(ctx, stage,
1103 has_previous_stage,
1104 previous_stage,
1105 &user_sgpr_idx);
1106 else
1107 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1108 &user_sgpr_idx, 1);
1109 }
1110 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1111 &user_sgpr_idx, 2);
1112 if (ctx->view_index)
1113 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1114 if (has_previous_stage)
1115 ac_declare_lds_as_pointer(&ctx->ac);
1116 break;
1117 case MESA_SHADER_FRAGMENT:
1118 if (ctx->shader_info->info.ps.needs_sample_positions) {
1119 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1120 &user_sgpr_idx, 1);
1121 }
1122 break;
1123 default:
1124 unreachable("Shader stage not implemented");
1125 }
1126
1127 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1128 }
1129
1130 static int get_llvm_num_components(LLVMValueRef value)
1131 {
1132 LLVMTypeRef type = LLVMTypeOf(value);
1133 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1134 ? LLVMGetVectorSize(type)
1135 : 1;
1136 return num_components;
1137 }
1138
1139 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1140 LLVMValueRef value,
1141 int index)
1142 {
1143 int count = get_llvm_num_components(value);
1144
1145 if (count == 1)
1146 return value;
1147
1148 return LLVMBuildExtractElement(ac->builder, value,
1149 LLVMConstInt(ac->i32, index, false), "");
1150 }
1151
1152 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1153 LLVMValueRef value, unsigned count)
1154 {
1155 unsigned num_components = get_llvm_num_components(value);
1156 if (count == num_components)
1157 return value;
1158
1159 LLVMValueRef masks[] = {
1160 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1161 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1162
1163 if (count == 1)
1164 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1165 "");
1166
1167 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1168 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1169 }
1170
1171 static void
1172 build_store_values_extended(struct ac_llvm_context *ac,
1173 LLVMValueRef *values,
1174 unsigned value_count,
1175 unsigned value_stride,
1176 LLVMValueRef vec)
1177 {
1178 LLVMBuilderRef builder = ac->builder;
1179 unsigned i;
1180
1181 for (i = 0; i < value_count; i++) {
1182 LLVMValueRef ptr = values[i * value_stride];
1183 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1184 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1185 LLVMBuildStore(builder, value, ptr);
1186 }
1187 }
1188
1189 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1190 const nir_ssa_def *def)
1191 {
1192 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1193 if (def->num_components > 1) {
1194 type = LLVMVectorType(type, def->num_components);
1195 }
1196 return type;
1197 }
1198
1199 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1200 {
1201 assert(src.is_ssa);
1202 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1203 return (LLVMValueRef)entry->data;
1204 }
1205
1206
1207 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1208 const struct nir_block *b)
1209 {
1210 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1211 return (LLVMBasicBlockRef)entry->data;
1212 }
1213
1214 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1215 nir_alu_src src,
1216 unsigned num_components)
1217 {
1218 LLVMValueRef value = get_src(ctx, src.src);
1219 bool need_swizzle = false;
1220
1221 assert(value);
1222 LLVMTypeRef type = LLVMTypeOf(value);
1223 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1224 ? LLVMGetVectorSize(type)
1225 : 1;
1226
1227 for (unsigned i = 0; i < num_components; ++i) {
1228 assert(src.swizzle[i] < src_components);
1229 if (src.swizzle[i] != i)
1230 need_swizzle = true;
1231 }
1232
1233 if (need_swizzle || num_components != src_components) {
1234 LLVMValueRef masks[] = {
1235 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1236 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1237 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1238 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1239
1240 if (src_components > 1 && num_components == 1) {
1241 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1242 masks[0], "");
1243 } else if (src_components == 1 && num_components > 1) {
1244 LLVMValueRef values[] = {value, value, value, value};
1245 value = ac_build_gather_values(&ctx->ac, values, num_components);
1246 } else {
1247 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1248 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1249 swizzle, "");
1250 }
1251 }
1252 assert(!src.negate);
1253 assert(!src.abs);
1254 return value;
1255 }
1256
1257 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1258 LLVMIntPredicate pred, LLVMValueRef src0,
1259 LLVMValueRef src1)
1260 {
1261 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1262 return LLVMBuildSelect(ctx->builder, result,
1263 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1264 ctx->i32_0, "");
1265 }
1266
1267 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1268 LLVMRealPredicate pred, LLVMValueRef src0,
1269 LLVMValueRef src1)
1270 {
1271 LLVMValueRef result;
1272 src0 = ac_to_float(ctx, src0);
1273 src1 = ac_to_float(ctx, src1);
1274 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1275 return LLVMBuildSelect(ctx->builder, result,
1276 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1277 ctx->i32_0, "");
1278 }
1279
1280 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMTypeRef result_type,
1283 LLVMValueRef src0)
1284 {
1285 char name[64];
1286 LLVMValueRef params[] = {
1287 ac_to_float(ctx, src0),
1288 };
1289
1290 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1291 get_elem_bits(ctx, result_type));
1292 assert(length < sizeof(name));
1293 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1294 }
1295
1296 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1297 const char *intrin,
1298 LLVMTypeRef result_type,
1299 LLVMValueRef src0, LLVMValueRef src1)
1300 {
1301 char name[64];
1302 LLVMValueRef params[] = {
1303 ac_to_float(ctx, src0),
1304 ac_to_float(ctx, src1),
1305 };
1306
1307 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1308 get_elem_bits(ctx, result_type));
1309 assert(length < sizeof(name));
1310 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1311 }
1312
1313 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1314 const char *intrin,
1315 LLVMTypeRef result_type,
1316 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1317 {
1318 char name[64];
1319 LLVMValueRef params[] = {
1320 ac_to_float(ctx, src0),
1321 ac_to_float(ctx, src1),
1322 ac_to_float(ctx, src2),
1323 };
1324
1325 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1326 get_elem_bits(ctx, result_type));
1327 assert(length < sizeof(name));
1328 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1329 }
1330
1331 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1332 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1333 {
1334 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1335 ctx->i32_0, "");
1336 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1337 }
1338
1339 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1340 LLVMIntPredicate pred,
1341 LLVMValueRef src0, LLVMValueRef src1)
1342 {
1343 return LLVMBuildSelect(ctx->builder,
1344 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1345 src0,
1346 src1, "");
1347
1348 }
1349 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1350 LLVMValueRef src0)
1351 {
1352 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1353 LLVMBuildNeg(ctx->builder, src0, ""));
1354 }
1355
1356 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0)
1358 {
1359 LLVMValueRef cmp, val;
1360
1361 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1362 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1363 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1364 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1365 return val;
1366 }
1367
1368 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1369 LLVMValueRef src0)
1370 {
1371 LLVMValueRef cmp, val;
1372
1373 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1374 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1375 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1376 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1377 return val;
1378 }
1379
1380 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1381 LLVMValueRef src0)
1382 {
1383 const char *intr = "llvm.floor.f32";
1384 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1385 LLVMValueRef params[] = {
1386 fsrc0,
1387 };
1388 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1389 ctx->f32, params, 1,
1390 AC_FUNC_ATTR_READNONE);
1391 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1392 }
1393
1394 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1395 const char *intrin,
1396 LLVMValueRef src0, LLVMValueRef src1)
1397 {
1398 LLVMTypeRef ret_type;
1399 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1400 LLVMValueRef res;
1401 LLVMValueRef params[] = { src0, src1 };
1402 ret_type = LLVMStructTypeInContext(ctx->context, types,
1403 2, true);
1404
1405 res = ac_build_intrinsic(ctx, intrin, ret_type,
1406 params, 2, AC_FUNC_ATTR_READNONE);
1407
1408 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1409 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1410 return res;
1411 }
1412
1413 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1414 LLVMValueRef src0)
1415 {
1416 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1417 }
1418
1419 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1420 LLVMValueRef src0)
1421 {
1422 src0 = ac_to_float(ctx, src0);
1423 return LLVMBuildSExt(ctx->builder,
1424 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1425 ctx->i32, "");
1426 }
1427
1428 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1429 LLVMValueRef src0)
1430 {
1431 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1432 }
1433
1434 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0)
1436 {
1437 return LLVMBuildSExt(ctx->builder,
1438 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1439 ctx->i32, "");
1440 }
1441
1442 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1443 LLVMValueRef src0)
1444 {
1445 LLVMValueRef result;
1446 LLVMValueRef cond = NULL;
1447
1448 src0 = ac_to_float(&ctx->ac, src0);
1449 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1450
1451 if (ctx->options->chip_class >= VI) {
1452 LLVMValueRef args[2];
1453 /* Check if the result is a denormal - and flush to 0 if so. */
1454 args[0] = result;
1455 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1456 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1457 }
1458
1459 /* need to convert back up to f32 */
1460 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1461
1462 if (ctx->options->chip_class >= VI)
1463 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1464 else {
1465 /* for SI/CIK */
1466 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1467 * so compare the result and flush to 0 if it's smaller.
1468 */
1469 LLVMValueRef temp, cond2;
1470 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1471 ctx->ac.f32, result);
1472 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1473 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1474 temp, "");
1475 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1476 temp, ctx->ac.f32_0, "");
1477 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1478 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1479 }
1480 return result;
1481 }
1482
1483 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1484 LLVMValueRef src0, LLVMValueRef src1)
1485 {
1486 LLVMValueRef dst64, result;
1487 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1488 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1489
1490 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1491 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1492 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1493 return result;
1494 }
1495
1496 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1497 LLVMValueRef src0, LLVMValueRef src1)
1498 {
1499 LLVMValueRef dst64, result;
1500 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1501 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1502
1503 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1504 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1505 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1510 bool is_signed,
1511 const LLVMValueRef srcs[3])
1512 {
1513 LLVMValueRef result;
1514 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1515
1516 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1517 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1518 return result;
1519 }
1520
1521 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1522 LLVMValueRef src0, LLVMValueRef src1,
1523 LLVMValueRef src2, LLVMValueRef src3)
1524 {
1525 LLVMValueRef bfi_args[3], result;
1526
1527 bfi_args[0] = LLVMBuildShl(ctx->builder,
1528 LLVMBuildSub(ctx->builder,
1529 LLVMBuildShl(ctx->builder,
1530 ctx->i32_1,
1531 src3, ""),
1532 ctx->i32_1, ""),
1533 src2, "");
1534 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1535 bfi_args[2] = src0;
1536
1537 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1538
1539 /* Calculate:
1540 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1541 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1542 */
1543 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1544 LLVMBuildAnd(ctx->builder, bfi_args[0],
1545 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1546
1547 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1548 return result;
1549 }
1550
1551 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1552 LLVMValueRef src0)
1553 {
1554 LLVMValueRef comp[2];
1555
1556 src0 = ac_to_float(ctx, src0);
1557 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1558 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1559
1560 return ac_build_cvt_pkrtz_f16(ctx, comp);
1561 }
1562
1563 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1564 LLVMValueRef src0)
1565 {
1566 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1567 LLVMValueRef temps[2], result, val;
1568 int i;
1569
1570 for (i = 0; i < 2; i++) {
1571 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1572 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1573 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1574 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1575 }
1576
1577 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1578 ctx->i32_0, "");
1579 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1580 ctx->i32_1, "");
1581 return result;
1582 }
1583
1584 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1585 nir_op op,
1586 LLVMValueRef src0)
1587 {
1588 unsigned mask;
1589 int idx;
1590 LLVMValueRef result;
1591
1592 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1593 mask = AC_TID_MASK_LEFT;
1594 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1595 mask = AC_TID_MASK_TOP;
1596 else
1597 mask = AC_TID_MASK_TOP_LEFT;
1598
1599 /* for DDX we want to next X pixel, DDY next Y pixel. */
1600 if (op == nir_op_fddx_fine ||
1601 op == nir_op_fddx_coarse ||
1602 op == nir_op_fddx)
1603 idx = 1;
1604 else
1605 idx = 2;
1606
1607 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1608 return result;
1609 }
1610
1611 /*
1612 * this takes an I,J coordinate pair,
1613 * and works out the X and Y derivatives.
1614 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1615 */
1616 static LLVMValueRef emit_ddxy_interp(
1617 struct ac_nir_context *ctx,
1618 LLVMValueRef interp_ij)
1619 {
1620 LLVMValueRef result[4], a;
1621 unsigned i;
1622
1623 for (i = 0; i < 2; i++) {
1624 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1625 LLVMConstInt(ctx->ac.i32, i, false), "");
1626 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1627 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1628 }
1629 return ac_build_gather_values(&ctx->ac, result, 4);
1630 }
1631
1632 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1633 {
1634 LLVMValueRef src[4], result = NULL;
1635 unsigned num_components = instr->dest.dest.ssa.num_components;
1636 unsigned src_components;
1637 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1638
1639 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1640 switch (instr->op) {
1641 case nir_op_vec2:
1642 case nir_op_vec3:
1643 case nir_op_vec4:
1644 src_components = 1;
1645 break;
1646 case nir_op_pack_half_2x16:
1647 src_components = 2;
1648 break;
1649 case nir_op_unpack_half_2x16:
1650 src_components = 1;
1651 break;
1652 default:
1653 src_components = num_components;
1654 break;
1655 }
1656 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1657 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1658
1659 switch (instr->op) {
1660 case nir_op_fmov:
1661 case nir_op_imov:
1662 result = src[0];
1663 break;
1664 case nir_op_fneg:
1665 src[0] = ac_to_float(&ctx->ac, src[0]);
1666 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1667 break;
1668 case nir_op_ineg:
1669 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1670 break;
1671 case nir_op_inot:
1672 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1673 break;
1674 case nir_op_iadd:
1675 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1676 break;
1677 case nir_op_fadd:
1678 src[0] = ac_to_float(&ctx->ac, src[0]);
1679 src[1] = ac_to_float(&ctx->ac, src[1]);
1680 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1681 break;
1682 case nir_op_fsub:
1683 src[0] = ac_to_float(&ctx->ac, src[0]);
1684 src[1] = ac_to_float(&ctx->ac, src[1]);
1685 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1686 break;
1687 case nir_op_isub:
1688 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_imul:
1691 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1692 break;
1693 case nir_op_imod:
1694 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_umod:
1697 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1698 break;
1699 case nir_op_fmod:
1700 src[0] = ac_to_float(&ctx->ac, src[0]);
1701 src[1] = ac_to_float(&ctx->ac, src[1]);
1702 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1703 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1704 ac_to_float_type(&ctx->ac, def_type), result);
1705 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1706 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1707 break;
1708 case nir_op_frem:
1709 src[0] = ac_to_float(&ctx->ac, src[0]);
1710 src[1] = ac_to_float(&ctx->ac, src[1]);
1711 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_irem:
1714 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_idiv:
1717 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_udiv:
1720 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1721 break;
1722 case nir_op_fmul:
1723 src[0] = ac_to_float(&ctx->ac, src[0]);
1724 src[1] = ac_to_float(&ctx->ac, src[1]);
1725 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1726 break;
1727 case nir_op_fdiv:
1728 src[0] = ac_to_float(&ctx->ac, src[0]);
1729 src[1] = ac_to_float(&ctx->ac, src[1]);
1730 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1731 break;
1732 case nir_op_frcp:
1733 src[0] = ac_to_float(&ctx->ac, src[0]);
1734 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1735 break;
1736 case nir_op_iand:
1737 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_ior:
1740 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1741 break;
1742 case nir_op_ixor:
1743 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1744 break;
1745 case nir_op_ishl:
1746 result = LLVMBuildShl(ctx->ac.builder, src[0],
1747 LLVMBuildZExt(ctx->ac.builder, src[1],
1748 LLVMTypeOf(src[0]), ""),
1749 "");
1750 break;
1751 case nir_op_ishr:
1752 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1753 LLVMBuildZExt(ctx->ac.builder, src[1],
1754 LLVMTypeOf(src[0]), ""),
1755 "");
1756 break;
1757 case nir_op_ushr:
1758 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1759 LLVMBuildZExt(ctx->ac.builder, src[1],
1760 LLVMTypeOf(src[0]), ""),
1761 "");
1762 break;
1763 case nir_op_ilt:
1764 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1765 break;
1766 case nir_op_ine:
1767 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1768 break;
1769 case nir_op_ieq:
1770 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1771 break;
1772 case nir_op_ige:
1773 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1774 break;
1775 case nir_op_ult:
1776 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1777 break;
1778 case nir_op_uge:
1779 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1780 break;
1781 case nir_op_feq:
1782 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1783 break;
1784 case nir_op_fne:
1785 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1786 break;
1787 case nir_op_flt:
1788 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1789 break;
1790 case nir_op_fge:
1791 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1792 break;
1793 case nir_op_fabs:
1794 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1795 ac_to_float_type(&ctx->ac, def_type), src[0]);
1796 break;
1797 case nir_op_iabs:
1798 result = emit_iabs(&ctx->ac, src[0]);
1799 break;
1800 case nir_op_imax:
1801 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1802 break;
1803 case nir_op_imin:
1804 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1805 break;
1806 case nir_op_umax:
1807 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1808 break;
1809 case nir_op_umin:
1810 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1811 break;
1812 case nir_op_isign:
1813 result = emit_isign(&ctx->ac, src[0]);
1814 break;
1815 case nir_op_fsign:
1816 src[0] = ac_to_float(&ctx->ac, src[0]);
1817 result = emit_fsign(&ctx->ac, src[0]);
1818 break;
1819 case nir_op_ffloor:
1820 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1821 ac_to_float_type(&ctx->ac, def_type), src[0]);
1822 break;
1823 case nir_op_ftrunc:
1824 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1825 ac_to_float_type(&ctx->ac, def_type), src[0]);
1826 break;
1827 case nir_op_fceil:
1828 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1829 ac_to_float_type(&ctx->ac, def_type), src[0]);
1830 break;
1831 case nir_op_fround_even:
1832 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1833 ac_to_float_type(&ctx->ac, def_type),src[0]);
1834 break;
1835 case nir_op_ffract:
1836 result = emit_ffract(&ctx->ac, src[0]);
1837 break;
1838 case nir_op_fsin:
1839 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1840 ac_to_float_type(&ctx->ac, def_type), src[0]);
1841 break;
1842 case nir_op_fcos:
1843 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1844 ac_to_float_type(&ctx->ac, def_type), src[0]);
1845 break;
1846 case nir_op_fsqrt:
1847 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1848 ac_to_float_type(&ctx->ac, def_type), src[0]);
1849 break;
1850 case nir_op_fexp2:
1851 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1852 ac_to_float_type(&ctx->ac, def_type), src[0]);
1853 break;
1854 case nir_op_flog2:
1855 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1856 ac_to_float_type(&ctx->ac, def_type), src[0]);
1857 break;
1858 case nir_op_frsq:
1859 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1860 ac_to_float_type(&ctx->ac, def_type), src[0]);
1861 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1862 break;
1863 case nir_op_fpow:
1864 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1865 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1866 break;
1867 case nir_op_fmax:
1868 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1869 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1870 if (instr->dest.dest.ssa.bit_size == 32)
1871 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1872 ac_to_float_type(&ctx->ac, def_type),
1873 result);
1874 break;
1875 case nir_op_fmin:
1876 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1877 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1878 if (instr->dest.dest.ssa.bit_size == 32)
1879 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1880 ac_to_float_type(&ctx->ac, def_type),
1881 result);
1882 break;
1883 case nir_op_ffma:
1884 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1885 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1886 break;
1887 case nir_op_ibitfield_extract:
1888 result = emit_bitfield_extract(&ctx->ac, true, src);
1889 break;
1890 case nir_op_ubitfield_extract:
1891 result = emit_bitfield_extract(&ctx->ac, false, src);
1892 break;
1893 case nir_op_bitfield_insert:
1894 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1895 break;
1896 case nir_op_bitfield_reverse:
1897 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1898 break;
1899 case nir_op_bit_count:
1900 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1901 break;
1902 case nir_op_vec2:
1903 case nir_op_vec3:
1904 case nir_op_vec4:
1905 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1906 src[i] = ac_to_integer(&ctx->ac, src[i]);
1907 result = ac_build_gather_values(&ctx->ac, src, num_components);
1908 break;
1909 case nir_op_f2i32:
1910 case nir_op_f2i64:
1911 src[0] = ac_to_float(&ctx->ac, src[0]);
1912 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1913 break;
1914 case nir_op_f2u32:
1915 case nir_op_f2u64:
1916 src[0] = ac_to_float(&ctx->ac, src[0]);
1917 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1918 break;
1919 case nir_op_i2f32:
1920 case nir_op_i2f64:
1921 src[0] = ac_to_integer(&ctx->ac, src[0]);
1922 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1923 break;
1924 case nir_op_u2f32:
1925 case nir_op_u2f64:
1926 src[0] = ac_to_integer(&ctx->ac, src[0]);
1927 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1928 break;
1929 case nir_op_f2f64:
1930 src[0] = ac_to_float(&ctx->ac, src[0]);
1931 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1932 break;
1933 case nir_op_f2f32:
1934 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1935 break;
1936 case nir_op_u2u32:
1937 case nir_op_u2u64:
1938 src[0] = ac_to_integer(&ctx->ac, src[0]);
1939 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1940 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1941 else
1942 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1943 break;
1944 case nir_op_i2i32:
1945 case nir_op_i2i64:
1946 src[0] = ac_to_integer(&ctx->ac, src[0]);
1947 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1948 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1949 else
1950 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1951 break;
1952 case nir_op_bcsel:
1953 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1954 break;
1955 case nir_op_find_lsb:
1956 src[0] = ac_to_integer(&ctx->ac, src[0]);
1957 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1958 break;
1959 case nir_op_ufind_msb:
1960 src[0] = ac_to_integer(&ctx->ac, src[0]);
1961 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1962 break;
1963 case nir_op_ifind_msb:
1964 src[0] = ac_to_integer(&ctx->ac, src[0]);
1965 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1966 break;
1967 case nir_op_uadd_carry:
1968 src[0] = ac_to_integer(&ctx->ac, src[0]);
1969 src[1] = ac_to_integer(&ctx->ac, src[1]);
1970 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1971 break;
1972 case nir_op_usub_borrow:
1973 src[0] = ac_to_integer(&ctx->ac, src[0]);
1974 src[1] = ac_to_integer(&ctx->ac, src[1]);
1975 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1976 break;
1977 case nir_op_b2f:
1978 result = emit_b2f(&ctx->ac, src[0]);
1979 break;
1980 case nir_op_f2b:
1981 result = emit_f2b(&ctx->ac, src[0]);
1982 break;
1983 case nir_op_b2i:
1984 result = emit_b2i(&ctx->ac, src[0]);
1985 break;
1986 case nir_op_i2b:
1987 src[0] = ac_to_integer(&ctx->ac, src[0]);
1988 result = emit_i2b(&ctx->ac, src[0]);
1989 break;
1990 case nir_op_fquantize2f16:
1991 result = emit_f2f16(ctx->nctx, src[0]);
1992 break;
1993 case nir_op_umul_high:
1994 src[0] = ac_to_integer(&ctx->ac, src[0]);
1995 src[1] = ac_to_integer(&ctx->ac, src[1]);
1996 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1997 break;
1998 case nir_op_imul_high:
1999 src[0] = ac_to_integer(&ctx->ac, src[0]);
2000 src[1] = ac_to_integer(&ctx->ac, src[1]);
2001 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2002 break;
2003 case nir_op_pack_half_2x16:
2004 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2005 break;
2006 case nir_op_unpack_half_2x16:
2007 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2008 break;
2009 case nir_op_fddx:
2010 case nir_op_fddy:
2011 case nir_op_fddx_fine:
2012 case nir_op_fddy_fine:
2013 case nir_op_fddx_coarse:
2014 case nir_op_fddy_coarse:
2015 result = emit_ddxy(ctx, instr->op, src[0]);
2016 break;
2017
2018 case nir_op_unpack_64_2x32_split_x: {
2019 assert(instr->src[0].src.ssa->num_components == 1);
2020 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2021 ctx->ac.v2i32,
2022 "");
2023 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2024 ctx->ac.i32_0, "");
2025 break;
2026 }
2027
2028 case nir_op_unpack_64_2x32_split_y: {
2029 assert(instr->src[0].src.ssa->num_components == 1);
2030 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2031 ctx->ac.v2i32,
2032 "");
2033 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2034 ctx->ac.i32_1, "");
2035 break;
2036 }
2037
2038 case nir_op_pack_64_2x32_split: {
2039 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2040 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2041 src[0], ctx->ac.i32_0, "");
2042 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2043 src[1], ctx->ac.i32_1, "");
2044 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2045 break;
2046 }
2047
2048 default:
2049 fprintf(stderr, "Unknown NIR alu instr: ");
2050 nir_print_instr(&instr->instr, stderr);
2051 fprintf(stderr, "\n");
2052 abort();
2053 }
2054
2055 if (result) {
2056 assert(instr->dest.dest.is_ssa);
2057 result = ac_to_integer(&ctx->ac, result);
2058 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2059 result);
2060 }
2061 }
2062
2063 static void visit_load_const(struct ac_nir_context *ctx,
2064 const nir_load_const_instr *instr)
2065 {
2066 LLVMValueRef values[4], value = NULL;
2067 LLVMTypeRef element_type =
2068 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2069
2070 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2071 switch (instr->def.bit_size) {
2072 case 32:
2073 values[i] = LLVMConstInt(element_type,
2074 instr->value.u32[i], false);
2075 break;
2076 case 64:
2077 values[i] = LLVMConstInt(element_type,
2078 instr->value.u64[i], false);
2079 break;
2080 default:
2081 fprintf(stderr,
2082 "unsupported nir load_const bit_size: %d\n",
2083 instr->def.bit_size);
2084 abort();
2085 }
2086 }
2087 if (instr->def.num_components > 1) {
2088 value = LLVMConstVector(values, instr->def.num_components);
2089 } else
2090 value = values[0];
2091
2092 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2093 }
2094
2095 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2096 LLVMTypeRef type)
2097 {
2098 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2099 return LLVMBuildBitCast(ctx->builder, ptr,
2100 LLVMPointerType(type, addr_space), "");
2101 }
2102
2103 static LLVMValueRef
2104 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2105 {
2106 LLVMValueRef size =
2107 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2108 LLVMConstInt(ctx->ac.i32, 2, false), "");
2109
2110 /* VI only */
2111 if (ctx->ac.chip_class == VI && in_elements) {
2112 /* On VI, the descriptor contains the size in bytes,
2113 * but TXQ must return the size in elements.
2114 * The stride is always non-zero for resources using TXQ.
2115 */
2116 LLVMValueRef stride =
2117 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2118 ctx->ac.i32_1, "");
2119 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2120 LLVMConstInt(ctx->ac.i32, 16, false), "");
2121 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2122 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2123
2124 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2125 }
2126 return size;
2127 }
2128
2129 /**
2130 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2131 * intrinsic names).
2132 */
2133 static void build_int_type_name(
2134 LLVMTypeRef type,
2135 char *buf, unsigned bufsize)
2136 {
2137 assert(bufsize >= 6);
2138
2139 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2140 snprintf(buf, bufsize, "v%ui32",
2141 LLVMGetVectorSize(type));
2142 else
2143 strcpy(buf, "i32");
2144 }
2145
2146 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2147 struct ac_image_args *args,
2148 const nir_tex_instr *instr)
2149 {
2150 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2151 LLVMValueRef coord = args->addr;
2152 LLVMValueRef half_texel[2];
2153 LLVMValueRef compare_cube_wa = NULL;
2154 LLVMValueRef result;
2155 int c;
2156 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2157
2158 //TODO Rect
2159 {
2160 struct ac_image_args txq_args = { 0 };
2161
2162 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2163 txq_args.opcode = ac_image_get_resinfo;
2164 txq_args.dmask = 0xf;
2165 txq_args.addr = ctx->i32_0;
2166 txq_args.resource = args->resource;
2167 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2168
2169 for (c = 0; c < 2; c++) {
2170 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2171 LLVMConstInt(ctx->i32, c, false), "");
2172 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2173 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2174 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2175 LLVMConstReal(ctx->f32, -0.5), "");
2176 }
2177 }
2178
2179 LLVMValueRef orig_coords = args->addr;
2180
2181 for (c = 0; c < 2; c++) {
2182 LLVMValueRef tmp;
2183 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2184 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2185 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2186 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2187 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2188 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2189 }
2190
2191
2192 /*
2193 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2194 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2195 * workaround by sampling using a scaled type and converting.
2196 * This is taken from amdgpu-pro shaders.
2197 */
2198 /* NOTE this produces some ugly code compared to amdgpu-pro,
2199 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2200 * and then reads them back. -pro generates two selects,
2201 * one s_cmp for the descriptor rewriting
2202 * one v_cmp for the coordinate and result changes.
2203 */
2204 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2205 LLVMValueRef tmp, tmp2;
2206
2207 /* workaround 8/8/8/8 uint/sint cube gather bug */
2208 /* first detect it then change to a scaled read and f2i */
2209 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2210 tmp2 = tmp;
2211
2212 /* extract the DATA_FORMAT */
2213 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2214 LLVMConstInt(ctx->i32, 6, false), false);
2215
2216 /* is the DATA_FORMAT == 8_8_8_8 */
2217 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2218
2219 if (stype == GLSL_TYPE_UINT)
2220 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2221 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2222 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2223 else
2224 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2225 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2226 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2227
2228 /* replace the NUM FORMAT in the descriptor */
2229 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2230 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2231
2232 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2233
2234 /* don't modify the coordinates for this case */
2235 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2236 }
2237 args->addr = coord;
2238 result = ac_build_image_opcode(ctx, args);
2239
2240 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2241 LLVMValueRef tmp, tmp2;
2242
2243 /* if the cube workaround is in place, f2i the result. */
2244 for (c = 0; c < 4; c++) {
2245 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2246 if (stype == GLSL_TYPE_UINT)
2247 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2248 else
2249 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2250 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2251 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2252 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2253 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2254 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2255 }
2256 }
2257 return result;
2258 }
2259
2260 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2261 const nir_tex_instr *instr,
2262 bool lod_is_zero,
2263 struct ac_image_args *args)
2264 {
2265 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2266 return ac_build_buffer_load_format(&ctx->ac,
2267 args->resource,
2268 args->addr,
2269 ctx->ac.i32_0,
2270 true);
2271 }
2272
2273 args->opcode = ac_image_sample;
2274 args->compare = instr->is_shadow;
2275
2276 switch (instr->op) {
2277 case nir_texop_txf:
2278 case nir_texop_txf_ms:
2279 case nir_texop_samples_identical:
2280 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2281 args->compare = false;
2282 args->offset = false;
2283 break;
2284 case nir_texop_txb:
2285 args->bias = true;
2286 break;
2287 case nir_texop_txl:
2288 if (lod_is_zero)
2289 args->level_zero = true;
2290 else
2291 args->lod = true;
2292 break;
2293 case nir_texop_txs:
2294 case nir_texop_query_levels:
2295 args->opcode = ac_image_get_resinfo;
2296 break;
2297 case nir_texop_tex:
2298 if (ctx->stage != MESA_SHADER_FRAGMENT)
2299 args->level_zero = true;
2300 break;
2301 case nir_texop_txd:
2302 args->deriv = true;
2303 break;
2304 case nir_texop_tg4:
2305 args->opcode = ac_image_gather4;
2306 args->level_zero = true;
2307 break;
2308 case nir_texop_lod:
2309 args->opcode = ac_image_get_lod;
2310 args->compare = false;
2311 args->offset = false;
2312 break;
2313 default:
2314 break;
2315 }
2316
2317 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2318 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2319 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2320 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2321 }
2322 }
2323 return ac_build_image_opcode(&ctx->ac, args);
2324 }
2325
2326 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2327 nir_intrinsic_instr *instr)
2328 {
2329 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2330 unsigned desc_set = nir_intrinsic_desc_set(instr);
2331 unsigned binding = nir_intrinsic_binding(instr);
2332 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2333 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2334 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2335 unsigned base_offset = layout->binding[binding].offset;
2336 LLVMValueRef offset, stride;
2337
2338 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2339 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2340 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2341 layout->binding[binding].dynamic_offset_offset;
2342 desc_ptr = ctx->push_constants;
2343 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2344 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2345 } else
2346 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2347
2348 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2349 index = LLVMBuildMul(ctx->builder, index, stride, "");
2350 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2351
2352 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2353 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2354 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2355
2356 return desc_ptr;
2357 }
2358
2359 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2360 nir_intrinsic_instr *instr)
2361 {
2362 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2363 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2364
2365 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2366 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2367 return result;
2368 }
2369
2370 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2371 nir_intrinsic_instr *instr)
2372 {
2373 LLVMValueRef ptr, addr;
2374
2375 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2376 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2377
2378 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2379 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2380
2381 return LLVMBuildLoad(ctx->builder, ptr, "");
2382 }
2383
2384 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2385 const nir_intrinsic_instr *instr)
2386 {
2387 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2388
2389 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2390 }
2391 static void visit_store_ssbo(struct ac_nir_context *ctx,
2392 nir_intrinsic_instr *instr)
2393 {
2394 const char *store_name;
2395 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2396 LLVMTypeRef data_type = ctx->ac.f32;
2397 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2398 int components_32bit = elem_size_mult * instr->num_components;
2399 unsigned writemask = nir_intrinsic_write_mask(instr);
2400 LLVMValueRef base_data, base_offset;
2401 LLVMValueRef params[6];
2402
2403 params[1] = ctx->abi->load_ssbo(ctx->abi,
2404 get_src(ctx, instr->src[1]), true);
2405 params[2] = ctx->ac.i32_0; /* vindex */
2406 params[4] = ctx->ac.i1false; /* glc */
2407 params[5] = ctx->ac.i1false; /* slc */
2408
2409 if (components_32bit > 1)
2410 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2411
2412 base_data = ac_to_float(&ctx->ac, src_data);
2413 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2414 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2415 data_type, "");
2416 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2417 while (writemask) {
2418 int start, count;
2419 LLVMValueRef data;
2420 LLVMValueRef offset;
2421 LLVMValueRef tmp;
2422 u_bit_scan_consecutive_range(&writemask, &start, &count);
2423
2424 /* Due to an LLVM limitation, split 3-element writes
2425 * into a 2-element and a 1-element write. */
2426 if (count == 3) {
2427 writemask |= 1 << (start + 2);
2428 count = 2;
2429 }
2430
2431 start *= elem_size_mult;
2432 count *= elem_size_mult;
2433
2434 if (count > 4) {
2435 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2436 count = 4;
2437 }
2438
2439 if (count == 4) {
2440 store_name = "llvm.amdgcn.buffer.store.v4f32";
2441 data = base_data;
2442 } else if (count == 2) {
2443 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2444 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2445 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2446 ctx->ac.i32_0, "");
2447
2448 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2449 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2450 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2451 ctx->ac.i32_1, "");
2452 store_name = "llvm.amdgcn.buffer.store.v2f32";
2453
2454 } else {
2455 assert(count == 1);
2456 if (get_llvm_num_components(base_data) > 1)
2457 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2458 LLVMConstInt(ctx->ac.i32, start, false), "");
2459 else
2460 data = base_data;
2461 store_name = "llvm.amdgcn.buffer.store.f32";
2462 }
2463
2464 offset = base_offset;
2465 if (start != 0) {
2466 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2467 }
2468 params[0] = data;
2469 params[3] = offset;
2470 ac_build_intrinsic(&ctx->ac, store_name,
2471 ctx->ac.voidt, params, 6, 0);
2472 }
2473 }
2474
2475 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2476 const nir_intrinsic_instr *instr)
2477 {
2478 const char *name;
2479 LLVMValueRef params[6];
2480 int arg_count = 0;
2481
2482 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2483 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2484 }
2485 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2486 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2487 get_src(ctx, instr->src[0]),
2488 true);
2489 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2490 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2491 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2492
2493 switch (instr->intrinsic) {
2494 case nir_intrinsic_ssbo_atomic_add:
2495 name = "llvm.amdgcn.buffer.atomic.add";
2496 break;
2497 case nir_intrinsic_ssbo_atomic_imin:
2498 name = "llvm.amdgcn.buffer.atomic.smin";
2499 break;
2500 case nir_intrinsic_ssbo_atomic_umin:
2501 name = "llvm.amdgcn.buffer.atomic.umin";
2502 break;
2503 case nir_intrinsic_ssbo_atomic_imax:
2504 name = "llvm.amdgcn.buffer.atomic.smax";
2505 break;
2506 case nir_intrinsic_ssbo_atomic_umax:
2507 name = "llvm.amdgcn.buffer.atomic.umax";
2508 break;
2509 case nir_intrinsic_ssbo_atomic_and:
2510 name = "llvm.amdgcn.buffer.atomic.and";
2511 break;
2512 case nir_intrinsic_ssbo_atomic_or:
2513 name = "llvm.amdgcn.buffer.atomic.or";
2514 break;
2515 case nir_intrinsic_ssbo_atomic_xor:
2516 name = "llvm.amdgcn.buffer.atomic.xor";
2517 break;
2518 case nir_intrinsic_ssbo_atomic_exchange:
2519 name = "llvm.amdgcn.buffer.atomic.swap";
2520 break;
2521 case nir_intrinsic_ssbo_atomic_comp_swap:
2522 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2523 break;
2524 default:
2525 abort();
2526 }
2527
2528 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2529 }
2530
2531 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2532 const nir_intrinsic_instr *instr)
2533 {
2534 LLVMValueRef results[2];
2535 int load_components;
2536 int num_components = instr->num_components;
2537 if (instr->dest.ssa.bit_size == 64)
2538 num_components *= 2;
2539
2540 for (int i = 0; i < num_components; i += load_components) {
2541 load_components = MIN2(num_components - i, 4);
2542 const char *load_name;
2543 LLVMTypeRef data_type = ctx->ac.f32;
2544 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2545 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2546
2547 if (load_components == 3)
2548 data_type = LLVMVectorType(ctx->ac.f32, 4);
2549 else if (load_components > 1)
2550 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2551
2552 if (load_components >= 3)
2553 load_name = "llvm.amdgcn.buffer.load.v4f32";
2554 else if (load_components == 2)
2555 load_name = "llvm.amdgcn.buffer.load.v2f32";
2556 else if (load_components == 1)
2557 load_name = "llvm.amdgcn.buffer.load.f32";
2558 else
2559 unreachable("unhandled number of components");
2560
2561 LLVMValueRef params[] = {
2562 ctx->abi->load_ssbo(ctx->abi,
2563 get_src(ctx, instr->src[0]),
2564 false),
2565 ctx->ac.i32_0,
2566 offset,
2567 ctx->ac.i1false,
2568 ctx->ac.i1false,
2569 };
2570
2571 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2572
2573 }
2574
2575 assume(results[0]);
2576 LLVMValueRef ret = results[0];
2577 if (num_components > 4 || num_components == 3) {
2578 LLVMValueRef masks[] = {
2579 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2580 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2581 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2582 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2583 };
2584
2585 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2586 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2587 results[num_components > 4 ? 1 : 0], swizzle, "");
2588 }
2589
2590 return LLVMBuildBitCast(ctx->ac.builder, ret,
2591 get_def_type(ctx, &instr->dest.ssa), "");
2592 }
2593
2594 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2595 const nir_intrinsic_instr *instr)
2596 {
2597 LLVMValueRef results[8], ret;
2598 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2599 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2600 int num_components = instr->num_components;
2601
2602 if (ctx->abi->load_ubo)
2603 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2604
2605 if (instr->dest.ssa.bit_size == 64)
2606 num_components *= 2;
2607
2608 for (unsigned i = 0; i < num_components; ++i) {
2609 LLVMValueRef params[] = {
2610 rsrc,
2611 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2612 offset, "")
2613 };
2614 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2615 params, 2,
2616 AC_FUNC_ATTR_READNONE |
2617 AC_FUNC_ATTR_LEGACY);
2618 }
2619
2620
2621 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2622 return LLVMBuildBitCast(ctx->ac.builder, ret,
2623 get_def_type(ctx, &instr->dest.ssa), "");
2624 }
2625
2626 static void
2627 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2628 bool vs_in, unsigned *vertex_index_out,
2629 LLVMValueRef *vertex_index_ref,
2630 unsigned *const_out, LLVMValueRef *indir_out)
2631 {
2632 unsigned const_offset = 0;
2633 nir_deref *tail = &deref->deref;
2634 LLVMValueRef offset = NULL;
2635
2636 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2637 tail = tail->child;
2638 nir_deref_array *deref_array = nir_deref_as_array(tail);
2639 if (vertex_index_out)
2640 *vertex_index_out = deref_array->base_offset;
2641
2642 if (vertex_index_ref) {
2643 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2644 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2645 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2646 }
2647 *vertex_index_ref = vtx;
2648 }
2649 }
2650
2651 if (deref->var->data.compact) {
2652 assert(tail->child->deref_type == nir_deref_type_array);
2653 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2654 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2655 /* We always lower indirect dereferences for "compact" array vars. */
2656 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2657
2658 const_offset = deref_array->base_offset;
2659 goto out;
2660 }
2661
2662 while (tail->child != NULL) {
2663 const struct glsl_type *parent_type = tail->type;
2664 tail = tail->child;
2665
2666 if (tail->deref_type == nir_deref_type_array) {
2667 nir_deref_array *deref_array = nir_deref_as_array(tail);
2668 LLVMValueRef index, stride, local_offset;
2669 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2670
2671 const_offset += size * deref_array->base_offset;
2672 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2673 continue;
2674
2675 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2676 index = get_src(ctx, deref_array->indirect);
2677 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2678 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2679
2680 if (offset)
2681 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2682 else
2683 offset = local_offset;
2684 } else if (tail->deref_type == nir_deref_type_struct) {
2685 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2686
2687 for (unsigned i = 0; i < deref_struct->index; i++) {
2688 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2689 const_offset += glsl_count_attribute_slots(ft, vs_in);
2690 }
2691 } else
2692 unreachable("unsupported deref type");
2693
2694 }
2695 out:
2696 if (const_offset && offset)
2697 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2698 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2699 "");
2700
2701 *const_out = const_offset;
2702 *indir_out = offset;
2703 }
2704
2705
2706 /* The offchip buffer layout for TCS->TES is
2707 *
2708 * - attribute 0 of patch 0 vertex 0
2709 * - attribute 0 of patch 0 vertex 1
2710 * - attribute 0 of patch 0 vertex 2
2711 * ...
2712 * - attribute 0 of patch 1 vertex 0
2713 * - attribute 0 of patch 1 vertex 1
2714 * ...
2715 * - attribute 1 of patch 0 vertex 0
2716 * - attribute 1 of patch 0 vertex 1
2717 * ...
2718 * - per patch attribute 0 of patch 0
2719 * - per patch attribute 0 of patch 1
2720 * ...
2721 *
2722 * Note that every attribute has 4 components.
2723 */
2724 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2725 LLVMValueRef vertex_index,
2726 LLVMValueRef param_index)
2727 {
2728 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2729 LLVMValueRef param_stride, constant16;
2730 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2731
2732 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2733 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2734 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2735 num_patches, "");
2736
2737 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2738 if (vertex_index) {
2739 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2740 vertices_per_patch, "");
2741
2742 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2743 vertex_index, "");
2744
2745 param_stride = total_vertices;
2746 } else {
2747 base_addr = rel_patch_id;
2748 param_stride = num_patches;
2749 }
2750
2751 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2752 LLVMBuildMul(ctx->builder, param_index,
2753 param_stride, ""), "");
2754
2755 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2756
2757 if (!vertex_index) {
2758 LLVMValueRef patch_data_offset =
2759 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2760
2761 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2762 patch_data_offset, "");
2763 }
2764 return base_addr;
2765 }
2766
2767 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2768 unsigned param,
2769 unsigned const_index,
2770 bool is_compact,
2771 LLVMValueRef vertex_index,
2772 LLVMValueRef indir_index)
2773 {
2774 LLVMValueRef param_index;
2775
2776 if (indir_index)
2777 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2778 indir_index, "");
2779 else {
2780 if (const_index && !is_compact)
2781 param += const_index;
2782 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2783 }
2784 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2785 }
2786
2787 static void
2788 mark_tess_output(struct nir_to_llvm_context *ctx,
2789 bool is_patch, uint32_t param)
2790
2791 {
2792 if (is_patch) {
2793 ctx->tess_patch_outputs_written |= (1ull << param);
2794 } else
2795 ctx->tess_outputs_written |= (1ull << param);
2796 }
2797
2798 static LLVMValueRef
2799 get_dw_address(struct nir_to_llvm_context *ctx,
2800 LLVMValueRef dw_addr,
2801 unsigned param,
2802 unsigned const_index,
2803 bool compact_const_index,
2804 LLVMValueRef vertex_index,
2805 LLVMValueRef stride,
2806 LLVMValueRef indir_index)
2807
2808 {
2809
2810 if (vertex_index) {
2811 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2812 LLVMBuildMul(ctx->builder,
2813 vertex_index,
2814 stride, ""), "");
2815 }
2816
2817 if (indir_index)
2818 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2819 LLVMBuildMul(ctx->builder, indir_index,
2820 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2821 else if (const_index && !compact_const_index)
2822 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2823 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2824
2825 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2826 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2827
2828 if (const_index && compact_const_index)
2829 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2830 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2831 return dw_addr;
2832 }
2833
2834 static LLVMValueRef
2835 load_tcs_input(struct ac_shader_abi *abi,
2836 LLVMValueRef vertex_index,
2837 LLVMValueRef indir_index,
2838 unsigned const_index,
2839 unsigned location,
2840 unsigned driver_location,
2841 unsigned component,
2842 unsigned num_components,
2843 bool is_patch,
2844 bool is_compact)
2845 {
2846 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2847 LLVMValueRef dw_addr, stride;
2848 LLVMValueRef value[4], result;
2849 unsigned param = shader_io_get_unique_index(location);
2850
2851 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2852 dw_addr = get_tcs_in_current_patch_offset(ctx);
2853 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2854 indir_index);
2855
2856 for (unsigned i = 0; i < num_components + component; i++) {
2857 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2858 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2859 ctx->ac.i32_1, "");
2860 }
2861 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2862 return result;
2863 }
2864
2865 static LLVMValueRef
2866 load_tcs_output(struct nir_to_llvm_context *ctx,
2867 nir_intrinsic_instr *instr)
2868 {
2869 LLVMValueRef dw_addr;
2870 LLVMValueRef stride = NULL;
2871 LLVMValueRef value[4], result;
2872 LLVMValueRef vertex_index = NULL;
2873 LLVMValueRef indir_index = NULL;
2874 unsigned const_index = 0;
2875 unsigned param;
2876 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2877 const bool is_compact = instr->variables[0]->var->data.compact;
2878 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2879 get_deref_offset(ctx->nir, instr->variables[0],
2880 false, NULL, per_vertex ? &vertex_index : NULL,
2881 &const_index, &indir_index);
2882
2883 if (!instr->variables[0]->var->data.patch) {
2884 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2885 dw_addr = get_tcs_out_current_patch_offset(ctx);
2886 } else {
2887 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2888 }
2889
2890 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2891 indir_index);
2892
2893 unsigned comp = instr->variables[0]->var->data.location_frac;
2894 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2895 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2896 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2897 ctx->ac.i32_1, "");
2898 }
2899 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2900 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2901 return result;
2902 }
2903
2904 static void
2905 store_tcs_output(struct nir_to_llvm_context *ctx,
2906 nir_intrinsic_instr *instr,
2907 LLVMValueRef src,
2908 unsigned writemask)
2909 {
2910 LLVMValueRef dw_addr;
2911 LLVMValueRef stride = NULL;
2912 LLVMValueRef buf_addr = NULL;
2913 LLVMValueRef vertex_index = NULL;
2914 LLVMValueRef indir_index = NULL;
2915 unsigned const_index = 0;
2916 unsigned param;
2917 const unsigned comp = instr->variables[0]->var->data.location_frac;
2918 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2919 const bool is_compact = instr->variables[0]->var->data.compact;
2920 bool store_lds = true;
2921
2922 if (instr->variables[0]->var->data.patch) {
2923 if (!(ctx->tcs_patch_outputs_read & (1U << (instr->variables[0]->var->data.location - VARYING_SLOT_PATCH0))))
2924 store_lds = false;
2925 } else {
2926 if (!(ctx->tcs_outputs_read & (1ULL << instr->variables[0]->var->data.location)))
2927 store_lds = false;
2928 }
2929 get_deref_offset(ctx->nir, instr->variables[0],
2930 false, NULL, per_vertex ? &vertex_index : NULL,
2931 &const_index, &indir_index);
2932
2933 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2934 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2935 is_compact && const_index > 3) {
2936 const_index -= 3;
2937 param++;
2938 }
2939
2940 if (!instr->variables[0]->var->data.patch) {
2941 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2942 dw_addr = get_tcs_out_current_patch_offset(ctx);
2943 } else {
2944 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2945 }
2946
2947 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2948
2949 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2950 indir_index);
2951 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2952 vertex_index, indir_index);
2953
2954 bool is_tess_factor = false;
2955 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2956 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2957 is_tess_factor = true;
2958
2959 unsigned base = is_compact ? const_index : 0;
2960 for (unsigned chan = 0; chan < 8; chan++) {
2961 if (!(writemask & (1 << chan)))
2962 continue;
2963 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2964
2965 if (store_lds || is_tess_factor)
2966 ac_lds_store(&ctx->ac, dw_addr, value);
2967
2968 if (!is_tess_factor && writemask != 0xF)
2969 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2970 buf_addr, ctx->oc_lds,
2971 4 * (base + chan), 1, 0, true, false);
2972
2973 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2974 ctx->ac.i32_1, "");
2975 }
2976
2977 if (writemask == 0xF) {
2978 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2979 buf_addr, ctx->oc_lds,
2980 (base * 4), 1, 0, true, false);
2981 }
2982 }
2983
2984 static LLVMValueRef
2985 load_tes_input(struct ac_shader_abi *abi,
2986 LLVMValueRef vertex_index,
2987 LLVMValueRef param_index,
2988 unsigned const_index,
2989 unsigned location,
2990 unsigned driver_location,
2991 unsigned component,
2992 unsigned num_components,
2993 bool is_patch,
2994 bool is_compact)
2995 {
2996 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2997 LLVMValueRef buf_addr;
2998 LLVMValueRef result;
2999 unsigned param = shader_io_get_unique_index(location);
3000
3001 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3002 const_index -= 3;
3003 param++;
3004 }
3005
3006 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3007 is_compact, vertex_index, param_index);
3008
3009 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3010 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3011
3012 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3013 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3014 result = trim_vector(&ctx->ac, result, num_components);
3015 return result;
3016 }
3017
3018 static LLVMValueRef
3019 load_gs_input(struct ac_shader_abi *abi,
3020 unsigned location,
3021 unsigned driver_location,
3022 unsigned component,
3023 unsigned num_components,
3024 unsigned vertex_index,
3025 unsigned const_index,
3026 LLVMTypeRef type)
3027 {
3028 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3029 LLVMValueRef vtx_offset;
3030 LLVMValueRef args[9];
3031 unsigned param, vtx_offset_param;
3032 LLVMValueRef value[4], result;
3033
3034 vtx_offset_param = vertex_index;
3035 assert(vtx_offset_param < 6);
3036 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3037 LLVMConstInt(ctx->ac.i32, 4, false), "");
3038
3039 param = shader_io_get_unique_index(location);
3040
3041 for (unsigned i = component; i < num_components + component; i++) {
3042 if (ctx->ac.chip_class >= GFX9) {
3043 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3044 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3045 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3046 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3047 } else {
3048 args[0] = ctx->esgs_ring;
3049 args[1] = vtx_offset;
3050 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3051 args[3] = ctx->ac.i32_0;
3052 args[4] = ctx->ac.i32_1; /* OFFEN */
3053 args[5] = ctx->ac.i32_0; /* IDXEN */
3054 args[6] = ctx->ac.i32_1; /* GLC */
3055 args[7] = ctx->ac.i32_0; /* SLC */
3056 args[8] = ctx->ac.i32_0; /* TFE */
3057
3058 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3059 ctx->ac.i32, args, 9,
3060 AC_FUNC_ATTR_READONLY |
3061 AC_FUNC_ATTR_LEGACY);
3062 }
3063 }
3064 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3065
3066 return result;
3067 }
3068
3069 static LLVMValueRef
3070 build_gep_for_deref(struct ac_nir_context *ctx,
3071 nir_deref_var *deref)
3072 {
3073 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3074 assert(entry->data);
3075 LLVMValueRef val = entry->data;
3076 nir_deref *tail = deref->deref.child;
3077 while (tail != NULL) {
3078 LLVMValueRef offset;
3079 switch (tail->deref_type) {
3080 case nir_deref_type_array: {
3081 nir_deref_array *array = nir_deref_as_array(tail);
3082 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3083 if (array->deref_array_type ==
3084 nir_deref_array_type_indirect) {
3085 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3086 get_src(ctx,
3087 array->indirect),
3088 "");
3089 }
3090 break;
3091 }
3092 case nir_deref_type_struct: {
3093 nir_deref_struct *deref_struct =
3094 nir_deref_as_struct(tail);
3095 offset = LLVMConstInt(ctx->ac.i32,
3096 deref_struct->index, 0);
3097 break;
3098 }
3099 default:
3100 unreachable("bad deref type");
3101 }
3102 val = ac_build_gep0(&ctx->ac, val, offset);
3103 tail = tail->child;
3104 }
3105 return val;
3106 }
3107
3108 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3109 nir_intrinsic_instr *instr)
3110 {
3111 LLVMValueRef values[8];
3112 int idx = instr->variables[0]->var->data.driver_location;
3113 int ve = instr->dest.ssa.num_components;
3114 unsigned comp = instr->variables[0]->var->data.location_frac;
3115 LLVMValueRef indir_index;
3116 LLVMValueRef ret;
3117 unsigned const_index;
3118 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3119 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3120 instr->variables[0]->var->data.mode == nir_var_shader_in;
3121 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3122 &const_index, &indir_index);
3123
3124 if (instr->dest.ssa.bit_size == 64)
3125 ve *= 2;
3126
3127 switch (instr->variables[0]->var->data.mode) {
3128 case nir_var_shader_in:
3129 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3130 ctx->stage == MESA_SHADER_TESS_EVAL) {
3131 LLVMValueRef result;
3132 LLVMValueRef vertex_index = NULL;
3133 LLVMValueRef indir_index = NULL;
3134 unsigned const_index = 0;
3135 unsigned location = instr->variables[0]->var->data.location;
3136 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3137 const bool is_patch = instr->variables[0]->var->data.patch;
3138 const bool is_compact = instr->variables[0]->var->data.compact;
3139
3140 get_deref_offset(ctx, instr->variables[0],
3141 false, NULL, is_patch ? NULL : &vertex_index,
3142 &const_index, &indir_index);
3143
3144 result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, indir_index,
3145 const_index, location, driver_location,
3146 instr->variables[0]->var->data.location_frac,
3147 instr->num_components,
3148 is_patch, is_compact);
3149 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3150 }
3151
3152 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3153 LLVMValueRef indir_index;
3154 unsigned const_index, vertex_index;
3155 get_deref_offset(ctx, instr->variables[0],
3156 false, &vertex_index, NULL,
3157 &const_index, &indir_index);
3158 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3159 instr->variables[0]->var->data.driver_location,
3160 instr->variables[0]->var->data.location_frac, ve,
3161 vertex_index, const_index,
3162 nir2llvmtype(ctx, instr->variables[0]->var->type));
3163 }
3164
3165 for (unsigned chan = comp; chan < ve + comp; chan++) {
3166 if (indir_index) {
3167 unsigned count = glsl_count_attribute_slots(
3168 instr->variables[0]->var->type,
3169 ctx->stage == MESA_SHADER_VERTEX);
3170 count -= chan / 4;
3171 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3172 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3173 stride, false, true);
3174
3175 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3176 tmp_vec,
3177 indir_index, "");
3178 } else
3179 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3180 }
3181 break;
3182 case nir_var_local:
3183 for (unsigned chan = 0; chan < ve; chan++) {
3184 if (indir_index) {
3185 unsigned count = glsl_count_attribute_slots(
3186 instr->variables[0]->var->type, false);
3187 count -= chan / 4;
3188 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3189 &ctx->ac, ctx->locals + idx + chan, count,
3190 stride, true, true);
3191
3192 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3193 tmp_vec,
3194 indir_index, "");
3195 } else {
3196 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3197 }
3198 }
3199 break;
3200 case nir_var_shared: {
3201 LLVMValueRef address = build_gep_for_deref(ctx,
3202 instr->variables[0]);
3203 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3204 return LLVMBuildBitCast(ctx->ac.builder, val,
3205 get_def_type(ctx, &instr->dest.ssa),
3206 "");
3207 }
3208 case nir_var_shader_out:
3209 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3210 return load_tcs_output(ctx->nctx, instr);
3211
3212 for (unsigned chan = comp; chan < ve + comp; chan++) {
3213 if (indir_index) {
3214 unsigned count = glsl_count_attribute_slots(
3215 instr->variables[0]->var->type, false);
3216 count -= chan / 4;
3217 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3218 &ctx->ac, ctx->outputs + idx + chan, count,
3219 stride, true, true);
3220
3221 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3222 tmp_vec,
3223 indir_index, "");
3224 } else {
3225 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3226 ctx->outputs[idx + chan + const_index * stride],
3227 "");
3228 }
3229 }
3230 break;
3231 default:
3232 unreachable("unhandle variable mode");
3233 }
3234 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3235 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3236 }
3237
3238 static void
3239 visit_store_var(struct ac_nir_context *ctx,
3240 nir_intrinsic_instr *instr)
3241 {
3242 LLVMValueRef temp_ptr, value;
3243 int idx = instr->variables[0]->var->data.driver_location;
3244 unsigned comp = instr->variables[0]->var->data.location_frac;
3245 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3246 int writemask = instr->const_index[0] << comp;
3247 LLVMValueRef indir_index;
3248 unsigned const_index;
3249 get_deref_offset(ctx, instr->variables[0], false,
3250 NULL, NULL, &const_index, &indir_index);
3251
3252 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3253 int old_writemask = writemask;
3254
3255 src = LLVMBuildBitCast(ctx->ac.builder, src,
3256 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3257 "");
3258
3259 writemask = 0;
3260 for (unsigned chan = 0; chan < 4; chan++) {
3261 if (old_writemask & (1 << chan))
3262 writemask |= 3u << (2 * chan);
3263 }
3264 }
3265
3266 switch (instr->variables[0]->var->data.mode) {
3267 case nir_var_shader_out:
3268
3269 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3270 store_tcs_output(ctx->nctx, instr, src, writemask);
3271 return;
3272 }
3273
3274 for (unsigned chan = 0; chan < 8; chan++) {
3275 int stride = 4;
3276 if (!(writemask & (1 << chan)))
3277 continue;
3278
3279 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3280
3281 if (instr->variables[0]->var->data.compact)
3282 stride = 1;
3283 if (indir_index) {
3284 unsigned count = glsl_count_attribute_slots(
3285 instr->variables[0]->var->type, false);
3286 count -= chan / 4;
3287 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3288 &ctx->ac, ctx->outputs + idx + chan, count,
3289 stride, true, true);
3290
3291 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3292 value, indir_index, "");
3293 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3294 count, stride, tmp_vec);
3295
3296 } else {
3297 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3298
3299 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3300 }
3301 }
3302 break;
3303 case nir_var_local:
3304 for (unsigned chan = 0; chan < 8; chan++) {
3305 if (!(writemask & (1 << chan)))
3306 continue;
3307
3308 value = llvm_extract_elem(&ctx->ac, src, chan);
3309 if (indir_index) {
3310 unsigned count = glsl_count_attribute_slots(
3311 instr->variables[0]->var->type, false);
3312 count -= chan / 4;
3313 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3314 &ctx->ac, ctx->locals + idx + chan, count,
3315 4, true, true);
3316
3317 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3318 value, indir_index, "");
3319 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3320 count, 4, tmp_vec);
3321 } else {
3322 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3323
3324 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3325 }
3326 }
3327 break;
3328 case nir_var_shared: {
3329 int writemask = instr->const_index[0];
3330 LLVMValueRef address = build_gep_for_deref(ctx,
3331 instr->variables[0]);
3332 LLVMValueRef val = get_src(ctx, instr->src[0]);
3333 unsigned components =
3334 glsl_get_vector_elements(
3335 nir_deref_tail(&instr->variables[0]->deref)->type);
3336 if (writemask == (1 << components) - 1) {
3337 val = LLVMBuildBitCast(
3338 ctx->ac.builder, val,
3339 LLVMGetElementType(LLVMTypeOf(address)), "");
3340 LLVMBuildStore(ctx->ac.builder, val, address);
3341 } else {
3342 for (unsigned chan = 0; chan < 4; chan++) {
3343 if (!(writemask & (1 << chan)))
3344 continue;
3345 LLVMValueRef ptr =
3346 LLVMBuildStructGEP(ctx->ac.builder,
3347 address, chan, "");
3348 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3349 chan);
3350 src = LLVMBuildBitCast(
3351 ctx->ac.builder, src,
3352 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3353 LLVMBuildStore(ctx->ac.builder, src, ptr);
3354 }
3355 }
3356 break;
3357 }
3358 default:
3359 break;
3360 }
3361 }
3362
3363 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3364 {
3365 switch (dim) {
3366 case GLSL_SAMPLER_DIM_BUF:
3367 return 1;
3368 case GLSL_SAMPLER_DIM_1D:
3369 return array ? 2 : 1;
3370 case GLSL_SAMPLER_DIM_2D:
3371 return array ? 3 : 2;
3372 case GLSL_SAMPLER_DIM_MS:
3373 return array ? 4 : 3;
3374 case GLSL_SAMPLER_DIM_3D:
3375 case GLSL_SAMPLER_DIM_CUBE:
3376 return 3;
3377 case GLSL_SAMPLER_DIM_RECT:
3378 case GLSL_SAMPLER_DIM_SUBPASS:
3379 return 2;
3380 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3381 return 3;
3382 default:
3383 break;
3384 }
3385 return 0;
3386 }
3387
3388
3389
3390 /* Adjust the sample index according to FMASK.
3391 *
3392 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3393 * which is the identity mapping. Each nibble says which physical sample
3394 * should be fetched to get that sample.
3395 *
3396 * For example, 0x11111100 means there are only 2 samples stored and
3397 * the second sample covers 3/4 of the pixel. When reading samples 0
3398 * and 1, return physical sample 0 (determined by the first two 0s
3399 * in FMASK), otherwise return physical sample 1.
3400 *
3401 * The sample index should be adjusted as follows:
3402 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3403 */
3404 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3405 LLVMValueRef coord_x, LLVMValueRef coord_y,
3406 LLVMValueRef coord_z,
3407 LLVMValueRef sample_index,
3408 LLVMValueRef fmask_desc_ptr)
3409 {
3410 LLVMValueRef fmask_load_address[4];
3411 LLVMValueRef res;
3412
3413 fmask_load_address[0] = coord_x;
3414 fmask_load_address[1] = coord_y;
3415 if (coord_z) {
3416 fmask_load_address[2] = coord_z;
3417 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3418 }
3419
3420 struct ac_image_args args = {0};
3421
3422 args.opcode = ac_image_load;
3423 args.da = coord_z ? true : false;
3424 args.resource = fmask_desc_ptr;
3425 args.dmask = 0xf;
3426 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3427
3428 res = ac_build_image_opcode(ctx, &args);
3429
3430 res = ac_to_integer(ctx, res);
3431 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3432 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3433
3434 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3435 res,
3436 ctx->i32_0, "");
3437
3438 LLVMValueRef sample_index4 =
3439 LLVMBuildMul(ctx->builder, sample_index, four, "");
3440 LLVMValueRef shifted_fmask =
3441 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3442 LLVMValueRef final_sample =
3443 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3444
3445 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3446 * resource descriptor is 0 (invalid),
3447 */
3448 LLVMValueRef fmask_desc =
3449 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3450 ctx->v8i32, "");
3451
3452 LLVMValueRef fmask_word1 =
3453 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3454 ctx->i32_1, "");
3455
3456 LLVMValueRef word1_is_nonzero =
3457 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3458 fmask_word1, ctx->i32_0, "");
3459
3460 /* Replace the MSAA sample index. */
3461 sample_index =
3462 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3463 final_sample, sample_index, "");
3464 return sample_index;
3465 }
3466
3467 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3468 const nir_intrinsic_instr *instr)
3469 {
3470 const struct glsl_type *type = instr->variables[0]->var->type;
3471 if(instr->variables[0]->deref.child)
3472 type = instr->variables[0]->deref.child->type;
3473
3474 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3475 LLVMValueRef coords[4];
3476 LLVMValueRef masks[] = {
3477 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3478 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3479 };
3480 LLVMValueRef res;
3481 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3482
3483 int count;
3484 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3485 bool is_array = glsl_sampler_type_is_array(type);
3486 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3487 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3488 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3489 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3490 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3491 count = image_type_to_components_count(dim, is_array);
3492
3493 if (is_ms) {
3494 LLVMValueRef fmask_load_address[3];
3495 int chan;
3496
3497 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3498 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3499 if (is_array)
3500 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3501 else
3502 fmask_load_address[2] = NULL;
3503 if (add_frag_pos) {
3504 for (chan = 0; chan < 2; ++chan)
3505 fmask_load_address[chan] =
3506 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3507 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3508 ctx->ac.i32, ""), "");
3509 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3510 }
3511 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3512 fmask_load_address[0],
3513 fmask_load_address[1],
3514 fmask_load_address[2],
3515 sample_index,
3516 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3517 }
3518 if (count == 1 && !gfx9_1d) {
3519 if (instr->src[0].ssa->num_components)
3520 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3521 else
3522 res = src0;
3523 } else {
3524 int chan;
3525 if (is_ms)
3526 count--;
3527 for (chan = 0; chan < count; ++chan) {
3528 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3529 }
3530 if (add_frag_pos) {
3531 for (chan = 0; chan < 2; ++chan)
3532 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3533 ctx->ac.i32, ""), "");
3534 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3535 count++;
3536 }
3537
3538 if (gfx9_1d) {
3539 if (is_array) {
3540 coords[2] = coords[1];
3541 coords[1] = ctx->ac.i32_0;
3542 } else
3543 coords[1] = ctx->ac.i32_0;
3544 count++;
3545 }
3546
3547 if (is_ms) {
3548 coords[count] = sample_index;
3549 count++;
3550 }
3551
3552 if (count == 3) {
3553 coords[3] = LLVMGetUndef(ctx->ac.i32);
3554 count = 4;
3555 }
3556 res = ac_build_gather_values(&ctx->ac, coords, count);
3557 }
3558 return res;
3559 }
3560
3561 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3562 const nir_intrinsic_instr *instr)
3563 {
3564 LLVMValueRef params[7];
3565 LLVMValueRef res;
3566 char intrinsic_name[64];
3567 const nir_variable *var = instr->variables[0]->var;
3568 const struct glsl_type *type = var->type;
3569
3570 if(instr->variables[0]->deref.child)
3571 type = instr->variables[0]->deref.child->type;
3572
3573 type = glsl_without_array(type);
3574 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3575 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3576 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3577 ctx->ac.i32_0, ""); /* vindex */
3578 params[2] = ctx->ac.i32_0; /* voffset */
3579 params[3] = ctx->ac.i1false; /* glc */
3580 params[4] = ctx->ac.i1false; /* slc */
3581 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3582 params, 5, 0);
3583
3584 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3585 res = ac_to_integer(&ctx->ac, res);
3586 } else {
3587 bool is_da = glsl_sampler_type_is_array(type) ||
3588 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3589 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3590 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3591 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3592 LLVMValueRef glc = ctx->ac.i1false;
3593 LLVMValueRef slc = ctx->ac.i1false;
3594
3595 params[0] = get_image_coords(ctx, instr);
3596 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3597 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3598 if (HAVE_LLVM <= 0x0309) {
3599 params[3] = ctx->ac.i1false; /* r128 */
3600 params[4] = da;
3601 params[5] = glc;
3602 params[6] = slc;
3603 } else {
3604 LLVMValueRef lwe = ctx->ac.i1false;
3605 params[3] = glc;
3606 params[4] = slc;
3607 params[5] = lwe;
3608 params[6] = da;
3609 }
3610
3611 ac_get_image_intr_name("llvm.amdgcn.image.load",
3612 ctx->ac.v4f32, /* vdata */
3613 LLVMTypeOf(params[0]), /* coords */
3614 LLVMTypeOf(params[1]), /* rsrc */
3615 intrinsic_name, sizeof(intrinsic_name));
3616
3617 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3618 params, 7, AC_FUNC_ATTR_READONLY);
3619 }
3620 return ac_to_integer(&ctx->ac, res);
3621 }
3622
3623 static void visit_image_store(struct ac_nir_context *ctx,
3624 nir_intrinsic_instr *instr)
3625 {
3626 LLVMValueRef params[8];
3627 char intrinsic_name[64];
3628 const nir_variable *var = instr->variables[0]->var;
3629 const struct glsl_type *type = glsl_without_array(var->type);
3630 LLVMValueRef glc = ctx->ac.i1false;
3631 bool force_glc = ctx->ac.chip_class == SI;
3632 if (force_glc)
3633 glc = ctx->ac.i1true;
3634
3635 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3636 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3637 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3638 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3639 ctx->ac.i32_0, ""); /* vindex */
3640 params[3] = ctx->ac.i32_0; /* voffset */
3641 params[4] = glc; /* glc */
3642 params[5] = ctx->ac.i1false; /* slc */
3643 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3644 params, 6, 0);
3645 } else {
3646 bool is_da = glsl_sampler_type_is_array(type) ||
3647 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3648 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3649 LLVMValueRef slc = ctx->ac.i1false;
3650
3651 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3652 params[1] = get_image_coords(ctx, instr); /* coords */
3653 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3654 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3655 if (HAVE_LLVM <= 0x0309) {
3656 params[4] = ctx->ac.i1false; /* r128 */
3657 params[5] = da;
3658 params[6] = glc;
3659 params[7] = slc;
3660 } else {
3661 LLVMValueRef lwe = ctx->ac.i1false;
3662 params[4] = glc;
3663 params[5] = slc;
3664 params[6] = lwe;
3665 params[7] = da;
3666 }
3667
3668 ac_get_image_intr_name("llvm.amdgcn.image.store",
3669 LLVMTypeOf(params[0]), /* vdata */
3670 LLVMTypeOf(params[1]), /* coords */
3671 LLVMTypeOf(params[2]), /* rsrc */
3672 intrinsic_name, sizeof(intrinsic_name));
3673
3674 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3675 params, 8, 0);
3676 }
3677
3678 }
3679
3680 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3681 const nir_intrinsic_instr *instr)
3682 {
3683 LLVMValueRef params[7];
3684 int param_count = 0;
3685 const nir_variable *var = instr->variables[0]->var;
3686
3687 const char *atomic_name;
3688 char intrinsic_name[41];
3689 const struct glsl_type *type = glsl_without_array(var->type);
3690 MAYBE_UNUSED int length;
3691
3692 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3693
3694 switch (instr->intrinsic) {
3695 case nir_intrinsic_image_atomic_add:
3696 atomic_name = "add";
3697 break;
3698 case nir_intrinsic_image_atomic_min:
3699 atomic_name = is_unsigned ? "umin" : "smin";
3700 break;
3701 case nir_intrinsic_image_atomic_max:
3702 atomic_name = is_unsigned ? "umax" : "smax";
3703 break;
3704 case nir_intrinsic_image_atomic_and:
3705 atomic_name = "and";
3706 break;
3707 case nir_intrinsic_image_atomic_or:
3708 atomic_name = "or";
3709 break;
3710 case nir_intrinsic_image_atomic_xor:
3711 atomic_name = "xor";
3712 break;
3713 case nir_intrinsic_image_atomic_exchange:
3714 atomic_name = "swap";
3715 break;
3716 case nir_intrinsic_image_atomic_comp_swap:
3717 atomic_name = "cmpswap";
3718 break;
3719 default:
3720 abort();
3721 }
3722
3723 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3724 params[param_count++] = get_src(ctx, instr->src[3]);
3725 params[param_count++] = get_src(ctx, instr->src[2]);
3726
3727 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3728 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3729 NULL, true, true);
3730 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3731 ctx->ac.i32_0, ""); /* vindex */
3732 params[param_count++] = ctx->ac.i32_0; /* voffset */
3733 params[param_count++] = ctx->ac.i1false; /* slc */
3734
3735 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3736 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3737 } else {
3738 char coords_type[8];
3739
3740 bool da = glsl_sampler_type_is_array(type) ||
3741 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3742
3743 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3744 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3745 NULL, true, true);
3746 params[param_count++] = ctx->ac.i1false; /* r128 */
3747 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3748 params[param_count++] = ctx->ac.i1false; /* slc */
3749
3750 build_int_type_name(LLVMTypeOf(coords),
3751 coords_type, sizeof(coords_type));
3752
3753 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3754 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3755 }
3756
3757 assert(length < sizeof(intrinsic_name));
3758 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3759 }
3760
3761 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3762 const nir_intrinsic_instr *instr)
3763 {
3764 LLVMValueRef res;
3765 const nir_variable *var = instr->variables[0]->var;
3766 const struct glsl_type *type = instr->variables[0]->var->type;
3767 bool da = glsl_sampler_type_is_array(var->type) ||
3768 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3769 if(instr->variables[0]->deref.child)
3770 type = instr->variables[0]->deref.child->type;
3771
3772 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3773 return get_buffer_size(ctx,
3774 get_sampler_desc(ctx, instr->variables[0],
3775 AC_DESC_BUFFER, NULL, true, false), true);
3776
3777 struct ac_image_args args = { 0 };
3778
3779 args.da = da;
3780 args.dmask = 0xf;
3781 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3782 args.opcode = ac_image_get_resinfo;
3783 args.addr = ctx->ac.i32_0;
3784
3785 res = ac_build_image_opcode(&ctx->ac, &args);
3786
3787 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3788
3789 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3790 glsl_sampler_type_is_array(type)) {
3791 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3792 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3793 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3794 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3795 }
3796 if (ctx->ac.chip_class >= GFX9 &&
3797 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3798 glsl_sampler_type_is_array(type)) {
3799 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3800 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3801 ctx->ac.i32_1, "");
3802
3803 }
3804 return res;
3805 }
3806
3807 #define NOOP_WAITCNT 0xf7f
3808 #define LGKM_CNT 0x07f
3809 #define VM_CNT 0xf70
3810
3811 static void emit_membar(struct nir_to_llvm_context *ctx,
3812 const nir_intrinsic_instr *instr)
3813 {
3814 unsigned waitcnt = NOOP_WAITCNT;
3815
3816 switch (instr->intrinsic) {
3817 case nir_intrinsic_memory_barrier:
3818 case nir_intrinsic_group_memory_barrier:
3819 waitcnt &= VM_CNT & LGKM_CNT;
3820 break;
3821 case nir_intrinsic_memory_barrier_atomic_counter:
3822 case nir_intrinsic_memory_barrier_buffer:
3823 case nir_intrinsic_memory_barrier_image:
3824 waitcnt &= VM_CNT;
3825 break;
3826 case nir_intrinsic_memory_barrier_shared:
3827 waitcnt &= LGKM_CNT;
3828 break;
3829 default:
3830 break;
3831 }
3832 if (waitcnt != NOOP_WAITCNT)
3833 ac_build_waitcnt(&ctx->ac, waitcnt);
3834 }
3835
3836 static void emit_barrier(struct nir_to_llvm_context *ctx)
3837 {
3838 /* SI only (thanks to a hw bug workaround):
3839 * The real barrier instruction isn’t needed, because an entire patch
3840 * always fits into a single wave.
3841 */
3842 if (ctx->options->chip_class == SI &&
3843 ctx->stage == MESA_SHADER_TESS_CTRL) {
3844 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3845 return;
3846 }
3847 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3848 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3849 }
3850
3851 static void emit_discard_if(struct ac_nir_context *ctx,
3852 const nir_intrinsic_instr *instr)
3853 {
3854 LLVMValueRef cond;
3855
3856 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3857 get_src(ctx, instr->src[0]),
3858 ctx->ac.i32_0, "");
3859 ac_build_kill_if_false(&ctx->ac, cond);
3860 }
3861
3862 static LLVMValueRef
3863 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3864 {
3865 LLVMValueRef result;
3866 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3867 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3868 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3869
3870 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3871 }
3872
3873 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3874 const nir_intrinsic_instr *instr)
3875 {
3876 LLVMValueRef ptr, result;
3877 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3878 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3879
3880 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3881 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3882 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3883 ptr, src, src1,
3884 LLVMAtomicOrderingSequentiallyConsistent,
3885 LLVMAtomicOrderingSequentiallyConsistent,
3886 false);
3887 } else {
3888 LLVMAtomicRMWBinOp op;
3889 switch (instr->intrinsic) {
3890 case nir_intrinsic_var_atomic_add:
3891 op = LLVMAtomicRMWBinOpAdd;
3892 break;
3893 case nir_intrinsic_var_atomic_umin:
3894 op = LLVMAtomicRMWBinOpUMin;
3895 break;
3896 case nir_intrinsic_var_atomic_umax:
3897 op = LLVMAtomicRMWBinOpUMax;
3898 break;
3899 case nir_intrinsic_var_atomic_imin:
3900 op = LLVMAtomicRMWBinOpMin;
3901 break;
3902 case nir_intrinsic_var_atomic_imax:
3903 op = LLVMAtomicRMWBinOpMax;
3904 break;
3905 case nir_intrinsic_var_atomic_and:
3906 op = LLVMAtomicRMWBinOpAnd;
3907 break;
3908 case nir_intrinsic_var_atomic_or:
3909 op = LLVMAtomicRMWBinOpOr;
3910 break;
3911 case nir_intrinsic_var_atomic_xor:
3912 op = LLVMAtomicRMWBinOpXor;
3913 break;
3914 case nir_intrinsic_var_atomic_exchange:
3915 op = LLVMAtomicRMWBinOpXchg;
3916 break;
3917 default:
3918 return NULL;
3919 }
3920
3921 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3922 LLVMAtomicOrderingSequentiallyConsistent,
3923 false);
3924 }
3925 return result;
3926 }
3927
3928 #define INTERP_CENTER 0
3929 #define INTERP_CENTROID 1
3930 #define INTERP_SAMPLE 2
3931
3932 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3933 enum glsl_interp_mode interp, unsigned location)
3934 {
3935 switch (interp) {
3936 case INTERP_MODE_FLAT:
3937 default:
3938 return NULL;
3939 case INTERP_MODE_SMOOTH:
3940 case INTERP_MODE_NONE:
3941 if (location == INTERP_CENTER)
3942 return ctx->persp_center;
3943 else if (location == INTERP_CENTROID)
3944 return ctx->persp_centroid;
3945 else if (location == INTERP_SAMPLE)
3946 return ctx->persp_sample;
3947 break;
3948 case INTERP_MODE_NOPERSPECTIVE:
3949 if (location == INTERP_CENTER)
3950 return ctx->linear_center;
3951 else if (location == INTERP_CENTROID)
3952 return ctx->linear_centroid;
3953 else if (location == INTERP_SAMPLE)
3954 return ctx->linear_sample;
3955 break;
3956 }
3957 return NULL;
3958 }
3959
3960 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3961 LLVMValueRef sample_id)
3962 {
3963 LLVMValueRef result;
3964 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3965
3966 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3967 const_array(ctx->ac.v2f32, 64), "");
3968
3969 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3970 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3971
3972 return result;
3973 }
3974
3975 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3976 {
3977 LLVMValueRef values[2];
3978
3979 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3980 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3981 return ac_build_gather_values(&ctx->ac, values, 2);
3982 }
3983
3984 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3985 const nir_intrinsic_instr *instr)
3986 {
3987 LLVMValueRef result[4];
3988 LLVMValueRef interp_param, attr_number;
3989 unsigned location;
3990 unsigned chan;
3991 LLVMValueRef src_c0 = NULL;
3992 LLVMValueRef src_c1 = NULL;
3993 LLVMValueRef src0 = NULL;
3994 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3995 switch (instr->intrinsic) {
3996 case nir_intrinsic_interp_var_at_centroid:
3997 location = INTERP_CENTROID;
3998 break;
3999 case nir_intrinsic_interp_var_at_sample:
4000 case nir_intrinsic_interp_var_at_offset:
4001 location = INTERP_CENTER;
4002 src0 = get_src(ctx->nir, instr->src[0]);
4003 break;
4004 default:
4005 break;
4006 }
4007
4008 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4009 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
4010 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4011 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4012 LLVMValueRef sample_position;
4013 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4014
4015 /* fetch sample ID */
4016 sample_position = load_sample_position(ctx, src0);
4017
4018 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4019 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4020 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4021 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4022 }
4023 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4024 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4025
4026 if (location == INTERP_CENTER) {
4027 LLVMValueRef ij_out[2];
4028 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4029
4030 /*
4031 * take the I then J parameters, and the DDX/Y for it, and
4032 * calculate the IJ inputs for the interpolator.
4033 * temp1 = ddx * offset/sample.x + I;
4034 * interp_param.I = ddy * offset/sample.y + temp1;
4035 * temp1 = ddx * offset/sample.x + J;
4036 * interp_param.J = ddy * offset/sample.y + temp1;
4037 */
4038 for (unsigned i = 0; i < 2; i++) {
4039 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4040 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4041 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4042 ddxy_out, ix_ll, "");
4043 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4044 ddxy_out, iy_ll, "");
4045 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4046 interp_param, ix_ll, "");
4047 LLVMValueRef temp1, temp2;
4048
4049 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4050 ctx->ac.f32, "");
4051
4052 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4053 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4054
4055 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4056 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4057
4058 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4059 temp2, ctx->ac.i32, "");
4060 }
4061 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4062
4063 }
4064
4065 for (chan = 0; chan < 4; chan++) {
4066 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4067
4068 if (interp_param) {
4069 interp_param = LLVMBuildBitCast(ctx->builder,
4070 interp_param, ctx->ac.v2f32, "");
4071 LLVMValueRef i = LLVMBuildExtractElement(
4072 ctx->builder, interp_param, ctx->ac.i32_0, "");
4073 LLVMValueRef j = LLVMBuildExtractElement(
4074 ctx->builder, interp_param, ctx->ac.i32_1, "");
4075
4076 result[chan] = ac_build_fs_interp(&ctx->ac,
4077 llvm_chan, attr_number,
4078 ctx->prim_mask, i, j);
4079 } else {
4080 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4081 LLVMConstInt(ctx->ac.i32, 2, false),
4082 llvm_chan, attr_number,
4083 ctx->prim_mask);
4084 }
4085 }
4086 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4087 instr->variables[0]->var->data.location_frac);
4088 }
4089
4090 static void
4091 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4092 {
4093 LLVMValueRef gs_next_vertex;
4094 LLVMValueRef can_emit;
4095 int idx;
4096 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4097
4098 /* Write vertex attribute values to GSVS ring */
4099 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4100 ctx->gs_next_vertex,
4101 "");
4102
4103 /* If this thread has already emitted the declared maximum number of
4104 * vertices, kill it: excessive vertex emissions are not supposed to
4105 * have any effect, and GS threads have no externally observable
4106 * effects other than emitting vertices.
4107 */
4108 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4109 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4110 ac_build_kill_if_false(&ctx->ac, can_emit);
4111
4112 /* loop num outputs */
4113 idx = 0;
4114 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4115 LLVMValueRef *out_ptr = &addrs[i * 4];
4116 int length = 4;
4117 int slot = idx;
4118 int slot_inc = 1;
4119
4120 if (!(ctx->output_mask & (1ull << i)))
4121 continue;
4122
4123 if (i == VARYING_SLOT_CLIP_DIST0) {
4124 /* pack clip and cull into a single set of slots */
4125 length = ctx->num_output_clips + ctx->num_output_culls;
4126 if (length > 4)
4127 slot_inc = 2;
4128 }
4129 for (unsigned j = 0; j < length; j++) {
4130 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4131 out_ptr[j], "");
4132 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4133 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4134 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4135
4136 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4137
4138 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4139 out_val, 1,
4140 voffset, ctx->gs2vs_offset, 0,
4141 1, 1, true, true);
4142 }
4143 idx += slot_inc;
4144 }
4145
4146 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4147 ctx->ac.i32_1, "");
4148 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4149
4150 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4151 }
4152
4153 static void
4154 visit_end_primitive(struct nir_to_llvm_context *ctx,
4155 const nir_intrinsic_instr *instr)
4156 {
4157 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4158 }
4159
4160 static LLVMValueRef
4161 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4162 const nir_intrinsic_instr *instr)
4163 {
4164 LLVMValueRef coord[4] = {
4165 ctx->tes_u,
4166 ctx->tes_v,
4167 ctx->ac.f32_0,
4168 ctx->ac.f32_0,
4169 };
4170
4171 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4172 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4173 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4174
4175 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4176 return LLVMBuildBitCast(ctx->builder, result,
4177 get_def_type(ctx->nir, &instr->dest.ssa), "");
4178 }
4179
4180 static void visit_intrinsic(struct ac_nir_context *ctx,
4181 nir_intrinsic_instr *instr)
4182 {
4183 LLVMValueRef result = NULL;
4184
4185 switch (instr->intrinsic) {
4186 case nir_intrinsic_load_work_group_id: {
4187 LLVMValueRef values[3];
4188
4189 for (int i = 0; i < 3; i++) {
4190 values[i] = ctx->nctx->workgroup_ids[i] ?
4191 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4192 }
4193
4194 result = ac_build_gather_values(&ctx->ac, values, 3);
4195 break;
4196 }
4197 case nir_intrinsic_load_base_vertex: {
4198 result = ctx->abi->base_vertex;
4199 break;
4200 }
4201 case nir_intrinsic_load_vertex_id_zero_base: {
4202 result = ctx->abi->vertex_id;
4203 break;
4204 }
4205 case nir_intrinsic_load_local_invocation_id: {
4206 result = ctx->nctx->local_invocation_ids;
4207 break;
4208 }
4209 case nir_intrinsic_load_base_instance:
4210 result = ctx->abi->start_instance;
4211 break;
4212 case nir_intrinsic_load_draw_id:
4213 result = ctx->abi->draw_id;
4214 break;
4215 case nir_intrinsic_load_view_index:
4216 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4217 break;
4218 case nir_intrinsic_load_invocation_id:
4219 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4220 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4221 else
4222 result = ctx->abi->gs_invocation_id;
4223 break;
4224 case nir_intrinsic_load_primitive_id:
4225 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4226 result = ctx->abi->gs_prim_id;
4227 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4228 result = ctx->nctx->tcs_patch_id;
4229 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4230 result = ctx->nctx->tes_patch_id;
4231 } else
4232 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4233 break;
4234 case nir_intrinsic_load_sample_id:
4235 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4236 break;
4237 case nir_intrinsic_load_sample_pos:
4238 result = load_sample_pos(ctx);
4239 break;
4240 case nir_intrinsic_load_sample_mask_in:
4241 result = ctx->abi->sample_coverage;
4242 break;
4243 case nir_intrinsic_load_frag_coord: {
4244 LLVMValueRef values[4] = {
4245 ctx->abi->frag_pos[0],
4246 ctx->abi->frag_pos[1],
4247 ctx->abi->frag_pos[2],
4248 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4249 };
4250 result = ac_build_gather_values(&ctx->ac, values, 4);
4251 break;
4252 }
4253 case nir_intrinsic_load_front_face:
4254 result = ctx->abi->front_face;
4255 break;
4256 case nir_intrinsic_load_instance_id:
4257 result = ctx->abi->instance_id;
4258 break;
4259 case nir_intrinsic_load_num_work_groups:
4260 result = ctx->nctx->num_work_groups;
4261 break;
4262 case nir_intrinsic_load_local_invocation_index:
4263 result = visit_load_local_invocation_index(ctx->nctx);
4264 break;
4265 case nir_intrinsic_load_push_constant:
4266 result = visit_load_push_constant(ctx->nctx, instr);
4267 break;
4268 case nir_intrinsic_vulkan_resource_index:
4269 result = visit_vulkan_resource_index(ctx->nctx, instr);
4270 break;
4271 case nir_intrinsic_vulkan_resource_reindex:
4272 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4273 break;
4274 case nir_intrinsic_store_ssbo:
4275 visit_store_ssbo(ctx, instr);
4276 break;
4277 case nir_intrinsic_load_ssbo:
4278 result = visit_load_buffer(ctx, instr);
4279 break;
4280 case nir_intrinsic_ssbo_atomic_add:
4281 case nir_intrinsic_ssbo_atomic_imin:
4282 case nir_intrinsic_ssbo_atomic_umin:
4283 case nir_intrinsic_ssbo_atomic_imax:
4284 case nir_intrinsic_ssbo_atomic_umax:
4285 case nir_intrinsic_ssbo_atomic_and:
4286 case nir_intrinsic_ssbo_atomic_or:
4287 case nir_intrinsic_ssbo_atomic_xor:
4288 case nir_intrinsic_ssbo_atomic_exchange:
4289 case nir_intrinsic_ssbo_atomic_comp_swap:
4290 result = visit_atomic_ssbo(ctx, instr);
4291 break;
4292 case nir_intrinsic_load_ubo:
4293 result = visit_load_ubo_buffer(ctx, instr);
4294 break;
4295 case nir_intrinsic_get_buffer_size:
4296 result = visit_get_buffer_size(ctx, instr);
4297 break;
4298 case nir_intrinsic_load_var:
4299 result = visit_load_var(ctx, instr);
4300 break;
4301 case nir_intrinsic_store_var:
4302 visit_store_var(ctx, instr);
4303 break;
4304 case nir_intrinsic_image_load:
4305 result = visit_image_load(ctx, instr);
4306 break;
4307 case nir_intrinsic_image_store:
4308 visit_image_store(ctx, instr);
4309 break;
4310 case nir_intrinsic_image_atomic_add:
4311 case nir_intrinsic_image_atomic_min:
4312 case nir_intrinsic_image_atomic_max:
4313 case nir_intrinsic_image_atomic_and:
4314 case nir_intrinsic_image_atomic_or:
4315 case nir_intrinsic_image_atomic_xor:
4316 case nir_intrinsic_image_atomic_exchange:
4317 case nir_intrinsic_image_atomic_comp_swap:
4318 result = visit_image_atomic(ctx, instr);
4319 break;
4320 case nir_intrinsic_image_size:
4321 result = visit_image_size(ctx, instr);
4322 break;
4323 case nir_intrinsic_discard:
4324 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4325 LLVMVoidTypeInContext(ctx->ac.context),
4326 NULL, 0, AC_FUNC_ATTR_LEGACY);
4327 break;
4328 case nir_intrinsic_discard_if:
4329 emit_discard_if(ctx, instr);
4330 break;
4331 case nir_intrinsic_memory_barrier:
4332 case nir_intrinsic_group_memory_barrier:
4333 case nir_intrinsic_memory_barrier_atomic_counter:
4334 case nir_intrinsic_memory_barrier_buffer:
4335 case nir_intrinsic_memory_barrier_image:
4336 case nir_intrinsic_memory_barrier_shared:
4337 emit_membar(ctx->nctx, instr);
4338 break;
4339 case nir_intrinsic_barrier:
4340 emit_barrier(ctx->nctx);
4341 break;
4342 case nir_intrinsic_var_atomic_add:
4343 case nir_intrinsic_var_atomic_imin:
4344 case nir_intrinsic_var_atomic_umin:
4345 case nir_intrinsic_var_atomic_imax:
4346 case nir_intrinsic_var_atomic_umax:
4347 case nir_intrinsic_var_atomic_and:
4348 case nir_intrinsic_var_atomic_or:
4349 case nir_intrinsic_var_atomic_xor:
4350 case nir_intrinsic_var_atomic_exchange:
4351 case nir_intrinsic_var_atomic_comp_swap:
4352 result = visit_var_atomic(ctx->nctx, instr);
4353 break;
4354 case nir_intrinsic_interp_var_at_centroid:
4355 case nir_intrinsic_interp_var_at_sample:
4356 case nir_intrinsic_interp_var_at_offset:
4357 result = visit_interp(ctx->nctx, instr);
4358 break;
4359 case nir_intrinsic_emit_vertex:
4360 assert(instr->const_index[0] == 0);
4361 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4362 break;
4363 case nir_intrinsic_end_primitive:
4364 visit_end_primitive(ctx->nctx, instr);
4365 break;
4366 case nir_intrinsic_load_tess_coord:
4367 result = visit_load_tess_coord(ctx->nctx, instr);
4368 break;
4369 case nir_intrinsic_load_patch_vertices_in:
4370 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4371 break;
4372 default:
4373 fprintf(stderr, "Unknown intrinsic: ");
4374 nir_print_instr(&instr->instr, stderr);
4375 fprintf(stderr, "\n");
4376 break;
4377 }
4378 if (result) {
4379 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4380 }
4381 }
4382
4383 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4384 LLVMValueRef buffer_ptr, bool write)
4385 {
4386 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4387
4388 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4389 ctx->shader_info->fs.writes_memory = true;
4390
4391 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4392 }
4393
4394 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4395 {
4396 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4397
4398 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4399 }
4400
4401 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4402 unsigned descriptor_set,
4403 unsigned base_index,
4404 unsigned constant_index,
4405 LLVMValueRef index,
4406 enum ac_descriptor_type desc_type,
4407 bool image, bool write)
4408 {
4409 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4410 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4411 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4412 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4413 unsigned offset = binding->offset;
4414 unsigned stride = binding->size;
4415 unsigned type_size;
4416 LLVMBuilderRef builder = ctx->builder;
4417 LLVMTypeRef type;
4418
4419 assert(base_index < layout->binding_count);
4420
4421 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4422 ctx->shader_info->fs.writes_memory = true;
4423
4424 switch (desc_type) {
4425 case AC_DESC_IMAGE:
4426 type = ctx->ac.v8i32;
4427 type_size = 32;
4428 break;
4429 case AC_DESC_FMASK:
4430 type = ctx->ac.v8i32;
4431 offset += 32;
4432 type_size = 32;
4433 break;
4434 case AC_DESC_SAMPLER:
4435 type = ctx->ac.v4i32;
4436 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4437 offset += 64;
4438
4439 type_size = 16;
4440 break;
4441 case AC_DESC_BUFFER:
4442 type = ctx->ac.v4i32;
4443 type_size = 16;
4444 break;
4445 default:
4446 unreachable("invalid desc_type\n");
4447 }
4448
4449 offset += constant_index * stride;
4450
4451 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4452 (!index || binding->immutable_samplers_equal)) {
4453 if (binding->immutable_samplers_equal)
4454 constant_index = 0;
4455
4456 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4457
4458 LLVMValueRef constants[] = {
4459 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4460 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4461 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4462 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4463 };
4464 return ac_build_gather_values(&ctx->ac, constants, 4);
4465 }
4466
4467 assert(stride % type_size == 0);
4468
4469 if (!index)
4470 index = ctx->ac.i32_0;
4471
4472 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4473
4474 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4475 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4476
4477 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4478 }
4479
4480 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4481 const nir_deref_var *deref,
4482 enum ac_descriptor_type desc_type,
4483 const nir_tex_instr *tex_instr,
4484 bool image, bool write)
4485 {
4486 LLVMValueRef index = NULL;
4487 unsigned constant_index = 0;
4488 unsigned descriptor_set;
4489 unsigned base_index;
4490
4491 if (!deref) {
4492 assert(tex_instr && !image);
4493 descriptor_set = 0;
4494 base_index = tex_instr->sampler_index;
4495 } else {
4496 const nir_deref *tail = &deref->deref;
4497 while (tail->child) {
4498 const nir_deref_array *child = nir_deref_as_array(tail->child);
4499 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4500
4501 if (!array_size)
4502 array_size = 1;
4503
4504 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4505
4506 if (child->deref_array_type == nir_deref_array_type_indirect) {
4507 LLVMValueRef indirect = get_src(ctx, child->indirect);
4508
4509 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4510 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4511
4512 if (!index)
4513 index = indirect;
4514 else
4515 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4516 }
4517
4518 constant_index += child->base_offset * array_size;
4519
4520 tail = &child->deref;
4521 }
4522 descriptor_set = deref->var->data.descriptor_set;
4523 base_index = deref->var->data.binding;
4524 }
4525
4526 return ctx->abi->load_sampler_desc(ctx->abi,
4527 descriptor_set,
4528 base_index,
4529 constant_index, index,
4530 desc_type, image, write);
4531 }
4532
4533 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4534 struct ac_image_args *args,
4535 const nir_tex_instr *instr,
4536 nir_texop op,
4537 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4538 LLVMValueRef *param, unsigned count,
4539 unsigned dmask)
4540 {
4541 unsigned is_rect = 0;
4542 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4543
4544 if (op == nir_texop_lod)
4545 da = false;
4546 /* Pad to power of two vector */
4547 while (count < util_next_power_of_two(count))
4548 param[count++] = LLVMGetUndef(ctx->i32);
4549
4550 if (count > 1)
4551 args->addr = ac_build_gather_values(ctx, param, count);
4552 else
4553 args->addr = param[0];
4554
4555 args->resource = res_ptr;
4556 args->sampler = samp_ptr;
4557
4558 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4559 args->addr = param[0];
4560 return;
4561 }
4562
4563 args->dmask = dmask;
4564 args->unorm = is_rect;
4565 args->da = da;
4566 }
4567
4568 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4569 *
4570 * SI-CI:
4571 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4572 * filtering manually. The driver sets img7 to a mask clearing
4573 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4574 * s_and_b32 samp0, samp0, img7
4575 *
4576 * VI:
4577 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4578 */
4579 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4580 LLVMValueRef res, LLVMValueRef samp)
4581 {
4582 LLVMBuilderRef builder = ctx->ac.builder;
4583 LLVMValueRef img7, samp0;
4584
4585 if (ctx->ac.chip_class >= VI)
4586 return samp;
4587
4588 img7 = LLVMBuildExtractElement(builder, res,
4589 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4590 samp0 = LLVMBuildExtractElement(builder, samp,
4591 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4592 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4593 return LLVMBuildInsertElement(builder, samp, samp0,
4594 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4595 }
4596
4597 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4598 nir_tex_instr *instr,
4599 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4600 LLVMValueRef *fmask_ptr)
4601 {
4602 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4603 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4604 else
4605 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4606 if (samp_ptr) {
4607 if (instr->sampler)
4608 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4609 else
4610 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4611 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4612 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4613 }
4614 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4615 instr->op == nir_texop_samples_identical))
4616 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4617 }
4618
4619 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4620 LLVMValueRef coord)
4621 {
4622 coord = ac_to_float(ctx, coord);
4623 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4624 coord = ac_to_integer(ctx, coord);
4625 return coord;
4626 }
4627
4628 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4629 {
4630 LLVMValueRef result = NULL;
4631 struct ac_image_args args = { 0 };
4632 unsigned dmask = 0xf;
4633 LLVMValueRef address[16];
4634 LLVMValueRef coords[5];
4635 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4636 LLVMValueRef bias = NULL, offsets = NULL;
4637 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4638 LLVMValueRef ddx = NULL, ddy = NULL;
4639 LLVMValueRef derivs[6];
4640 unsigned chan, count = 0;
4641 unsigned const_src = 0, num_deriv_comp = 0;
4642 bool lod_is_zero = false;
4643
4644 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4645
4646 for (unsigned i = 0; i < instr->num_srcs; i++) {
4647 switch (instr->src[i].src_type) {
4648 case nir_tex_src_coord:
4649 coord = get_src(ctx, instr->src[i].src);
4650 break;
4651 case nir_tex_src_projector:
4652 break;
4653 case nir_tex_src_comparator:
4654 comparator = get_src(ctx, instr->src[i].src);
4655 break;
4656 case nir_tex_src_offset:
4657 offsets = get_src(ctx, instr->src[i].src);
4658 const_src = i;
4659 break;
4660 case nir_tex_src_bias:
4661 bias = get_src(ctx, instr->src[i].src);
4662 break;
4663 case nir_tex_src_lod: {
4664 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4665
4666 if (val && val->i32[0] == 0)
4667 lod_is_zero = true;
4668 lod = get_src(ctx, instr->src[i].src);
4669 break;
4670 }
4671 case nir_tex_src_ms_index:
4672 sample_index = get_src(ctx, instr->src[i].src);
4673 break;
4674 case nir_tex_src_ms_mcs:
4675 break;
4676 case nir_tex_src_ddx:
4677 ddx = get_src(ctx, instr->src[i].src);
4678 num_deriv_comp = instr->src[i].src.ssa->num_components;
4679 break;
4680 case nir_tex_src_ddy:
4681 ddy = get_src(ctx, instr->src[i].src);
4682 break;
4683 case nir_tex_src_texture_offset:
4684 case nir_tex_src_sampler_offset:
4685 case nir_tex_src_plane:
4686 default:
4687 break;
4688 }
4689 }
4690
4691 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4692 result = get_buffer_size(ctx, res_ptr, true);
4693 goto write_result;
4694 }
4695
4696 if (instr->op == nir_texop_texture_samples) {
4697 LLVMValueRef res, samples, is_msaa;
4698 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4699 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4700 LLVMConstInt(ctx->ac.i32, 3, false), "");
4701 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4702 LLVMConstInt(ctx->ac.i32, 28, false), "");
4703 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4704 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4705 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4706 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4707
4708 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4709 LLVMConstInt(ctx->ac.i32, 16, false), "");
4710 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4711 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4712 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4713 samples, "");
4714 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4715 ctx->ac.i32_1, "");
4716 result = samples;
4717 goto write_result;
4718 }
4719
4720 if (coord)
4721 for (chan = 0; chan < instr->coord_components; chan++)
4722 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4723
4724 if (offsets && instr->op != nir_texop_txf) {
4725 LLVMValueRef offset[3], pack;
4726 for (chan = 0; chan < 3; ++chan)
4727 offset[chan] = ctx->ac.i32_0;
4728
4729 args.offset = true;
4730 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4731 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4732 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4733 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4734 if (chan)
4735 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4736 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4737 }
4738 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4739 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4740 address[count++] = pack;
4741
4742 }
4743 /* pack LOD bias value */
4744 if (instr->op == nir_texop_txb && bias) {
4745 address[count++] = bias;
4746 }
4747
4748 /* Pack depth comparison value */
4749 if (instr->is_shadow && comparator) {
4750 LLVMValueRef z = ac_to_float(&ctx->ac,
4751 llvm_extract_elem(&ctx->ac, comparator, 0));
4752
4753 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4754 * so the depth comparison value isn't clamped for Z16 and
4755 * Z24 anymore. Do it manually here.
4756 *
4757 * It's unnecessary if the original texture format was
4758 * Z32_FLOAT, but we don't know that here.
4759 */
4760 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4761 z = ac_build_clamp(&ctx->ac, z);
4762
4763 address[count++] = z;
4764 }
4765
4766 /* pack derivatives */
4767 if (ddx || ddy) {
4768 int num_src_deriv_channels, num_dest_deriv_channels;
4769 switch (instr->sampler_dim) {
4770 case GLSL_SAMPLER_DIM_3D:
4771 case GLSL_SAMPLER_DIM_CUBE:
4772 num_deriv_comp = 3;
4773 num_src_deriv_channels = 3;
4774 num_dest_deriv_channels = 3;
4775 break;
4776 case GLSL_SAMPLER_DIM_2D:
4777 default:
4778 num_src_deriv_channels = 2;
4779 num_dest_deriv_channels = 2;
4780 num_deriv_comp = 2;
4781 break;
4782 case GLSL_SAMPLER_DIM_1D:
4783 num_src_deriv_channels = 1;
4784 if (ctx->ac.chip_class >= GFX9) {
4785 num_dest_deriv_channels = 2;
4786 num_deriv_comp = 2;
4787 } else {
4788 num_dest_deriv_channels = 1;
4789 num_deriv_comp = 1;
4790 }
4791 break;
4792 }
4793
4794 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4795 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4796 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4797 }
4798 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4799 derivs[i] = ctx->ac.f32_0;
4800 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4801 }
4802 }
4803
4804 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4805 for (chan = 0; chan < instr->coord_components; chan++)
4806 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4807 if (instr->coord_components == 3)
4808 coords[3] = LLVMGetUndef(ctx->ac.f32);
4809 ac_prepare_cube_coords(&ctx->ac,
4810 instr->op == nir_texop_txd, instr->is_array,
4811 instr->op == nir_texop_lod, coords, derivs);
4812 if (num_deriv_comp)
4813 num_deriv_comp--;
4814 }
4815
4816 if (ddx || ddy) {
4817 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4818 address[count++] = derivs[i];
4819 }
4820
4821 /* Pack texture coordinates */
4822 if (coord) {
4823 address[count++] = coords[0];
4824 if (instr->coord_components > 1) {
4825 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4826 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4827 }
4828 address[count++] = coords[1];
4829 }
4830 if (instr->coord_components > 2) {
4831 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4832 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4833 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4834 instr->op != nir_texop_txf) {
4835 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4836 }
4837 address[count++] = coords[2];
4838 }
4839
4840 if (ctx->ac.chip_class >= GFX9) {
4841 LLVMValueRef filler;
4842 if (instr->op == nir_texop_txf)
4843 filler = ctx->ac.i32_0;
4844 else
4845 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4846
4847 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4848 /* No nir_texop_lod, because it does not take a slice
4849 * even with array textures. */
4850 if (instr->is_array && instr->op != nir_texop_lod ) {
4851 address[count] = address[count - 1];
4852 address[count - 1] = filler;
4853 count++;
4854 } else
4855 address[count++] = filler;
4856 }
4857 }
4858 }
4859
4860 /* Pack LOD */
4861 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4862 instr->op == nir_texop_txf)) {
4863 address[count++] = lod;
4864 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4865 address[count++] = sample_index;
4866 } else if(instr->op == nir_texop_txs) {
4867 count = 0;
4868 if (lod)
4869 address[count++] = lod;
4870 else
4871 address[count++] = ctx->ac.i32_0;
4872 }
4873
4874 for (chan = 0; chan < count; chan++) {
4875 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4876 address[chan], ctx->ac.i32, "");
4877 }
4878
4879 if (instr->op == nir_texop_samples_identical) {
4880 LLVMValueRef txf_address[4];
4881 struct ac_image_args txf_args = { 0 };
4882 unsigned txf_count = count;
4883 memcpy(txf_address, address, sizeof(txf_address));
4884
4885 if (!instr->is_array)
4886 txf_address[2] = ctx->ac.i32_0;
4887 txf_address[3] = ctx->ac.i32_0;
4888
4889 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4890 fmask_ptr, NULL,
4891 txf_address, txf_count, 0xf);
4892
4893 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4894
4895 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4896 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4897 goto write_result;
4898 }
4899
4900 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4901 instr->op != nir_texop_txs) {
4902 unsigned sample_chan = instr->is_array ? 3 : 2;
4903 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4904 address[0],
4905 address[1],
4906 instr->is_array ? address[2] : NULL,
4907 address[sample_chan],
4908 fmask_ptr);
4909 }
4910
4911 if (offsets && instr->op == nir_texop_txf) {
4912 nir_const_value *const_offset =
4913 nir_src_as_const_value(instr->src[const_src].src);
4914 int num_offsets = instr->src[const_src].src.ssa->num_components;
4915 assert(const_offset);
4916 num_offsets = MIN2(num_offsets, instr->coord_components);
4917 if (num_offsets > 2)
4918 address[2] = LLVMBuildAdd(ctx->ac.builder,
4919 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4920 if (num_offsets > 1)
4921 address[1] = LLVMBuildAdd(ctx->ac.builder,
4922 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4923 address[0] = LLVMBuildAdd(ctx->ac.builder,
4924 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4925
4926 }
4927
4928 /* TODO TG4 support */
4929 if (instr->op == nir_texop_tg4) {
4930 if (instr->is_shadow)
4931 dmask = 1;
4932 else
4933 dmask = 1 << instr->component;
4934 }
4935 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4936 res_ptr, samp_ptr, address, count, dmask);
4937
4938 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4939
4940 if (instr->op == nir_texop_query_levels)
4941 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4942 else if (instr->is_shadow && instr->is_new_style_shadow &&
4943 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4944 instr->op != nir_texop_tg4)
4945 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4946 else if (instr->op == nir_texop_txs &&
4947 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4948 instr->is_array) {
4949 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4950 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4951 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4952 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4953 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4954 } else if (ctx->ac.chip_class >= GFX9 &&
4955 instr->op == nir_texop_txs &&
4956 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4957 instr->is_array) {
4958 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4959 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4960 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4961 ctx->ac.i32_1, "");
4962 } else if (instr->dest.ssa.num_components != 4)
4963 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4964
4965 write_result:
4966 if (result) {
4967 assert(instr->dest.is_ssa);
4968 result = ac_to_integer(&ctx->ac, result);
4969 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4970 }
4971 }
4972
4973
4974 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4975 {
4976 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4977 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4978
4979 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4980 _mesa_hash_table_insert(ctx->phis, instr, result);
4981 }
4982
4983 static void visit_post_phi(struct ac_nir_context *ctx,
4984 nir_phi_instr *instr,
4985 LLVMValueRef llvm_phi)
4986 {
4987 nir_foreach_phi_src(src, instr) {
4988 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4989 LLVMValueRef llvm_src = get_src(ctx, src->src);
4990
4991 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4992 }
4993 }
4994
4995 static void phi_post_pass(struct ac_nir_context *ctx)
4996 {
4997 struct hash_entry *entry;
4998 hash_table_foreach(ctx->phis, entry) {
4999 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5000 (LLVMValueRef)entry->data);
5001 }
5002 }
5003
5004
5005 static void visit_ssa_undef(struct ac_nir_context *ctx,
5006 const nir_ssa_undef_instr *instr)
5007 {
5008 unsigned num_components = instr->def.num_components;
5009 LLVMValueRef undef;
5010
5011 if (num_components == 1)
5012 undef = LLVMGetUndef(ctx->ac.i32);
5013 else {
5014 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5015 }
5016 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5017 }
5018
5019 static void visit_jump(struct ac_nir_context *ctx,
5020 const nir_jump_instr *instr)
5021 {
5022 switch (instr->type) {
5023 case nir_jump_break:
5024 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5025 LLVMClearInsertionPosition(ctx->ac.builder);
5026 break;
5027 case nir_jump_continue:
5028 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5029 LLVMClearInsertionPosition(ctx->ac.builder);
5030 break;
5031 default:
5032 fprintf(stderr, "Unknown NIR jump instr: ");
5033 nir_print_instr(&instr->instr, stderr);
5034 fprintf(stderr, "\n");
5035 abort();
5036 }
5037 }
5038
5039 static void visit_cf_list(struct ac_nir_context *ctx,
5040 struct exec_list *list);
5041
5042 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5043 {
5044 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5045 nir_foreach_instr(instr, block)
5046 {
5047 switch (instr->type) {
5048 case nir_instr_type_alu:
5049 visit_alu(ctx, nir_instr_as_alu(instr));
5050 break;
5051 case nir_instr_type_load_const:
5052 visit_load_const(ctx, nir_instr_as_load_const(instr));
5053 break;
5054 case nir_instr_type_intrinsic:
5055 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5056 break;
5057 case nir_instr_type_tex:
5058 visit_tex(ctx, nir_instr_as_tex(instr));
5059 break;
5060 case nir_instr_type_phi:
5061 visit_phi(ctx, nir_instr_as_phi(instr));
5062 break;
5063 case nir_instr_type_ssa_undef:
5064 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5065 break;
5066 case nir_instr_type_jump:
5067 visit_jump(ctx, nir_instr_as_jump(instr));
5068 break;
5069 default:
5070 fprintf(stderr, "Unknown NIR instr type: ");
5071 nir_print_instr(instr, stderr);
5072 fprintf(stderr, "\n");
5073 abort();
5074 }
5075 }
5076
5077 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5078 }
5079
5080 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5081 {
5082 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5083
5084 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5085 LLVMBasicBlockRef merge_block =
5086 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5087 LLVMBasicBlockRef if_block =
5088 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5089 LLVMBasicBlockRef else_block = merge_block;
5090 if (!exec_list_is_empty(&if_stmt->else_list))
5091 else_block = LLVMAppendBasicBlockInContext(
5092 ctx->ac.context, fn, "");
5093
5094 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5095 ctx->ac.i32_0, "");
5096 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5097
5098 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5099 visit_cf_list(ctx, &if_stmt->then_list);
5100 if (LLVMGetInsertBlock(ctx->ac.builder))
5101 LLVMBuildBr(ctx->ac.builder, merge_block);
5102
5103 if (!exec_list_is_empty(&if_stmt->else_list)) {
5104 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5105 visit_cf_list(ctx, &if_stmt->else_list);
5106 if (LLVMGetInsertBlock(ctx->ac.builder))
5107 LLVMBuildBr(ctx->ac.builder, merge_block);
5108 }
5109
5110 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5111 }
5112
5113 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5114 {
5115 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5116 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5117 LLVMBasicBlockRef break_parent = ctx->break_block;
5118
5119 ctx->continue_block =
5120 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5121 ctx->break_block =
5122 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5123
5124 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5125 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5126 visit_cf_list(ctx, &loop->body);
5127
5128 if (LLVMGetInsertBlock(ctx->ac.builder))
5129 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5130 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5131
5132 ctx->continue_block = continue_parent;
5133 ctx->break_block = break_parent;
5134 }
5135
5136 static void visit_cf_list(struct ac_nir_context *ctx,
5137 struct exec_list *list)
5138 {
5139 foreach_list_typed(nir_cf_node, node, node, list)
5140 {
5141 switch (node->type) {
5142 case nir_cf_node_block:
5143 visit_block(ctx, nir_cf_node_as_block(node));
5144 break;
5145
5146 case nir_cf_node_if:
5147 visit_if(ctx, nir_cf_node_as_if(node));
5148 break;
5149
5150 case nir_cf_node_loop:
5151 visit_loop(ctx, nir_cf_node_as_loop(node));
5152 break;
5153
5154 default:
5155 assert(0);
5156 }
5157 }
5158 }
5159
5160 static void
5161 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5162 struct nir_variable *variable)
5163 {
5164 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5165 LLVMValueRef t_offset;
5166 LLVMValueRef t_list;
5167 LLVMValueRef input;
5168 LLVMValueRef buffer_index;
5169 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5170 int idx = variable->data.location;
5171 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5172
5173 variable->data.driver_location = idx * 4;
5174
5175 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5176 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5177 ctx->abi.start_instance, "");
5178 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5179 ctx->shader_info->vs.vgpr_comp_cnt);
5180 } else
5181 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5182 ctx->abi.base_vertex, "");
5183
5184 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5185 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5186
5187 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5188
5189 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5190 buffer_index,
5191 ctx->ac.i32_0,
5192 true);
5193
5194 for (unsigned chan = 0; chan < 4; chan++) {
5195 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5196 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5197 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5198 input, llvm_chan, ""));
5199 }
5200 }
5201 }
5202
5203 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5204 unsigned attr,
5205 LLVMValueRef interp_param,
5206 LLVMValueRef prim_mask,
5207 LLVMValueRef result[4])
5208 {
5209 LLVMValueRef attr_number;
5210 unsigned chan;
5211 LLVMValueRef i, j;
5212 bool interp = interp_param != NULL;
5213
5214 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5215
5216 /* fs.constant returns the param from the middle vertex, so it's not
5217 * really useful for flat shading. It's meant to be used for custom
5218 * interpolation (but the intrinsic can't fetch from the other two
5219 * vertices).
5220 *
5221 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5222 * to do the right thing. The only reason we use fs.constant is that
5223 * fs.interp cannot be used on integers, because they can be equal
5224 * to NaN.
5225 */
5226 if (interp) {
5227 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5228 ctx->ac.v2f32, "");
5229
5230 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5231 ctx->ac.i32_0, "");
5232 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5233 ctx->ac.i32_1, "");
5234 }
5235
5236 for (chan = 0; chan < 4; chan++) {
5237 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5238
5239 if (interp) {
5240 result[chan] = ac_build_fs_interp(&ctx->ac,
5241 llvm_chan,
5242 attr_number,
5243 prim_mask, i, j);
5244 } else {
5245 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5246 LLVMConstInt(ctx->ac.i32, 2, false),
5247 llvm_chan,
5248 attr_number,
5249 prim_mask);
5250 }
5251 }
5252 }
5253
5254 static void
5255 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5256 struct nir_variable *variable)
5257 {
5258 int idx = variable->data.location;
5259 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5260 LLVMValueRef interp;
5261
5262 variable->data.driver_location = idx * 4;
5263 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5264
5265 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5266 unsigned interp_type;
5267 if (variable->data.sample) {
5268 interp_type = INTERP_SAMPLE;
5269 ctx->shader_info->info.ps.force_persample = true;
5270 } else if (variable->data.centroid)
5271 interp_type = INTERP_CENTROID;
5272 else
5273 interp_type = INTERP_CENTER;
5274
5275 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5276 } else
5277 interp = NULL;
5278
5279 for (unsigned i = 0; i < attrib_count; ++i)
5280 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5281
5282 }
5283
5284 static void
5285 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5286 struct nir_shader *nir) {
5287 nir_foreach_variable(variable, &nir->inputs)
5288 handle_vs_input_decl(ctx, variable);
5289 }
5290
5291 static void
5292 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5293 struct nir_shader *nir)
5294 {
5295 if (!ctx->options->key.fs.multisample)
5296 return;
5297
5298 bool uses_center = false;
5299 bool uses_centroid = false;
5300 nir_foreach_variable(variable, &nir->inputs) {
5301 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5302 variable->data.sample)
5303 continue;
5304
5305 if (variable->data.centroid)
5306 uses_centroid = true;
5307 else
5308 uses_center = true;
5309 }
5310
5311 if (uses_center && uses_centroid) {
5312 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5313 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5314 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5315 }
5316 }
5317
5318 static void
5319 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5320 struct nir_shader *nir)
5321 {
5322 prepare_interp_optimize(ctx, nir);
5323
5324 nir_foreach_variable(variable, &nir->inputs)
5325 handle_fs_input_decl(ctx, variable);
5326
5327 unsigned index = 0;
5328
5329 if (ctx->shader_info->info.ps.uses_input_attachments ||
5330 ctx->shader_info->info.needs_multiview_view_index)
5331 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5332
5333 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5334 LLVMValueRef interp_param;
5335 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5336
5337 if (!(ctx->input_mask & (1ull << i)))
5338 continue;
5339
5340 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5341 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5342 interp_param = *inputs;
5343 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5344 inputs);
5345
5346 if (!interp_param)
5347 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5348 ++index;
5349 } else if (i == VARYING_SLOT_POS) {
5350 for(int i = 0; i < 3; ++i)
5351 inputs[i] = ctx->abi.frag_pos[i];
5352
5353 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5354 ctx->abi.frag_pos[3]);
5355 }
5356 }
5357 ctx->shader_info->fs.num_interp = index;
5358 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5359 ctx->shader_info->fs.has_pcoord = true;
5360 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5361 ctx->shader_info->fs.prim_id_input = true;
5362 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5363 ctx->shader_info->fs.layer_input = true;
5364 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5365
5366 if (ctx->shader_info->info.needs_multiview_view_index)
5367 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5368 }
5369
5370 static LLVMValueRef
5371 ac_build_alloca(struct ac_llvm_context *ac,
5372 LLVMTypeRef type,
5373 const char *name)
5374 {
5375 LLVMBuilderRef builder = ac->builder;
5376 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5377 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5378 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5379 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5380 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5381 LLVMValueRef res;
5382
5383 if (first_instr) {
5384 LLVMPositionBuilderBefore(first_builder, first_instr);
5385 } else {
5386 LLVMPositionBuilderAtEnd(first_builder, first_block);
5387 }
5388
5389 res = LLVMBuildAlloca(first_builder, type, name);
5390 LLVMBuildStore(builder, LLVMConstNull(type), res);
5391
5392 LLVMDisposeBuilder(first_builder);
5393
5394 return res;
5395 }
5396
5397 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5398 LLVMTypeRef type,
5399 const char *name)
5400 {
5401 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5402 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5403 return ptr;
5404 }
5405
5406 static void
5407 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5408 struct nir_variable *variable,
5409 struct nir_shader *shader,
5410 gl_shader_stage stage)
5411 {
5412 int idx = variable->data.location + variable->data.index;
5413 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5414 uint64_t mask_attribs;
5415
5416 variable->data.driver_location = idx * 4;
5417
5418 /* tess ctrl has it's own load/store paths for outputs */
5419 if (stage == MESA_SHADER_TESS_CTRL)
5420 return;
5421
5422 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5423 if (stage == MESA_SHADER_VERTEX ||
5424 stage == MESA_SHADER_TESS_EVAL ||
5425 stage == MESA_SHADER_GEOMETRY) {
5426 if (idx == VARYING_SLOT_CLIP_DIST0) {
5427 int length = shader->info.clip_distance_array_size +
5428 shader->info.cull_distance_array_size;
5429 if (stage == MESA_SHADER_VERTEX) {
5430 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5431 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5432 }
5433 if (stage == MESA_SHADER_TESS_EVAL) {
5434 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5435 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5436 }
5437
5438 if (length > 4)
5439 attrib_count = 2;
5440 else
5441 attrib_count = 1;
5442 mask_attribs = 1ull << idx;
5443 }
5444 }
5445
5446 ctx->output_mask |= mask_attribs;
5447 }
5448
5449 static void
5450 handle_shader_output_decl(struct ac_nir_context *ctx,
5451 struct nir_shader *nir,
5452 struct nir_variable *variable)
5453 {
5454 unsigned output_loc = variable->data.driver_location / 4;
5455 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5456
5457 /* tess ctrl has it's own load/store paths for outputs */
5458 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5459 return;
5460
5461 if (ctx->stage == MESA_SHADER_VERTEX ||
5462 ctx->stage == MESA_SHADER_TESS_EVAL ||
5463 ctx->stage == MESA_SHADER_GEOMETRY) {
5464 int idx = variable->data.location + variable->data.index;
5465 if (idx == VARYING_SLOT_CLIP_DIST0) {
5466 int length = nir->info.clip_distance_array_size +
5467 nir->info.cull_distance_array_size;
5468
5469 if (length > 4)
5470 attrib_count = 2;
5471 else
5472 attrib_count = 1;
5473 }
5474 }
5475
5476 for (unsigned i = 0; i < attrib_count; ++i) {
5477 for (unsigned chan = 0; chan < 4; chan++) {
5478 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5479 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5480 }
5481 }
5482 }
5483
5484 static LLVMTypeRef
5485 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5486 enum glsl_base_type type)
5487 {
5488 switch (type) {
5489 case GLSL_TYPE_INT:
5490 case GLSL_TYPE_UINT:
5491 case GLSL_TYPE_BOOL:
5492 case GLSL_TYPE_SUBROUTINE:
5493 return ctx->ac.i32;
5494 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5495 return ctx->ac.f32;
5496 case GLSL_TYPE_INT64:
5497 case GLSL_TYPE_UINT64:
5498 return ctx->ac.i64;
5499 case GLSL_TYPE_DOUBLE:
5500 return ctx->ac.f64;
5501 default:
5502 unreachable("unknown GLSL type");
5503 }
5504 }
5505
5506 static LLVMTypeRef
5507 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5508 const struct glsl_type *type)
5509 {
5510 if (glsl_type_is_scalar(type)) {
5511 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5512 }
5513
5514 if (glsl_type_is_vector(type)) {
5515 return LLVMVectorType(
5516 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5517 glsl_get_vector_elements(type));
5518 }
5519
5520 if (glsl_type_is_matrix(type)) {
5521 return LLVMArrayType(
5522 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5523 glsl_get_matrix_columns(type));
5524 }
5525
5526 if (glsl_type_is_array(type)) {
5527 return LLVMArrayType(
5528 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5529 glsl_get_length(type));
5530 }
5531
5532 assert(glsl_type_is_struct(type));
5533
5534 LLVMTypeRef member_types[glsl_get_length(type)];
5535
5536 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5537 member_types[i] =
5538 glsl_to_llvm_type(ctx,
5539 glsl_get_struct_field(type, i));
5540 }
5541
5542 return LLVMStructTypeInContext(ctx->context, member_types,
5543 glsl_get_length(type), false);
5544 }
5545
5546 static void
5547 setup_locals(struct ac_nir_context *ctx,
5548 struct nir_function *func)
5549 {
5550 int i, j;
5551 ctx->num_locals = 0;
5552 nir_foreach_variable(variable, &func->impl->locals) {
5553 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5554 variable->data.driver_location = ctx->num_locals * 4;
5555 ctx->num_locals += attrib_count;
5556 }
5557 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5558 if (!ctx->locals)
5559 return;
5560
5561 for (i = 0; i < ctx->num_locals; i++) {
5562 for (j = 0; j < 4; j++) {
5563 ctx->locals[i * 4 + j] =
5564 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5565 }
5566 }
5567 }
5568
5569 static void
5570 setup_shared(struct ac_nir_context *ctx,
5571 struct nir_shader *nir)
5572 {
5573 nir_foreach_variable(variable, &nir->shared) {
5574 LLVMValueRef shared =
5575 LLVMAddGlobalInAddressSpace(
5576 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5577 variable->name ? variable->name : "",
5578 LOCAL_ADDR_SPACE);
5579 _mesa_hash_table_insert(ctx->vars, variable, shared);
5580 }
5581 }
5582
5583 static LLVMValueRef
5584 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5585 {
5586 v = ac_to_float(ctx, v);
5587 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5588 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5589 }
5590
5591
5592 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5593 LLVMValueRef src0, LLVMValueRef src1)
5594 {
5595 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5596 LLVMValueRef comp[2];
5597
5598 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5599 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5600 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5601 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5602 }
5603
5604 /* Initialize arguments for the shader export intrinsic */
5605 static void
5606 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5607 LLVMValueRef *values,
5608 unsigned target,
5609 struct ac_export_args *args)
5610 {
5611 /* Default is 0xf. Adjusted below depending on the format. */
5612 args->enabled_channels = 0xf;
5613
5614 /* Specify whether the EXEC mask represents the valid mask */
5615 args->valid_mask = 0;
5616
5617 /* Specify whether this is the last export */
5618 args->done = 0;
5619
5620 /* Specify the target we are exporting */
5621 args->target = target;
5622
5623 args->compr = false;
5624 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5625 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5626 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5627 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5628
5629 if (!values)
5630 return;
5631
5632 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5633 LLVMValueRef val[4];
5634 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5635 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5636 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5637 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5638
5639 switch(col_format) {
5640 case V_028714_SPI_SHADER_ZERO:
5641 args->enabled_channels = 0; /* writemask */
5642 args->target = V_008DFC_SQ_EXP_NULL;
5643 break;
5644
5645 case V_028714_SPI_SHADER_32_R:
5646 args->enabled_channels = 1;
5647 args->out[0] = values[0];
5648 break;
5649
5650 case V_028714_SPI_SHADER_32_GR:
5651 args->enabled_channels = 0x3;
5652 args->out[0] = values[0];
5653 args->out[1] = values[1];
5654 break;
5655
5656 case V_028714_SPI_SHADER_32_AR:
5657 args->enabled_channels = 0x9;
5658 args->out[0] = values[0];
5659 args->out[3] = values[3];
5660 break;
5661
5662 case V_028714_SPI_SHADER_FP16_ABGR:
5663 args->compr = 1;
5664
5665 for (unsigned chan = 0; chan < 2; chan++) {
5666 LLVMValueRef pack_args[2] = {
5667 values[2 * chan],
5668 values[2 * chan + 1]
5669 };
5670 LLVMValueRef packed;
5671
5672 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5673 args->out[chan] = packed;
5674 }
5675 break;
5676
5677 case V_028714_SPI_SHADER_UNORM16_ABGR:
5678 for (unsigned chan = 0; chan < 4; chan++) {
5679 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5680 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5681 LLVMConstReal(ctx->ac.f32, 65535), "");
5682 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5683 LLVMConstReal(ctx->ac.f32, 0.5), "");
5684 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5685 ctx->ac.i32, "");
5686 }
5687
5688 args->compr = 1;
5689 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5690 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5691 break;
5692
5693 case V_028714_SPI_SHADER_SNORM16_ABGR:
5694 for (unsigned chan = 0; chan < 4; chan++) {
5695 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5696 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5697 LLVMConstReal(ctx->ac.f32, 32767), "");
5698
5699 /* If positive, add 0.5, else add -0.5. */
5700 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5701 LLVMBuildSelect(ctx->builder,
5702 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5703 val[chan], ctx->ac.f32_0, ""),
5704 LLVMConstReal(ctx->ac.f32, 0.5),
5705 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5706 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5707 }
5708
5709 args->compr = 1;
5710 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5711 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5712 break;
5713
5714 case V_028714_SPI_SHADER_UINT16_ABGR: {
5715 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5716 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5717 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5718
5719 for (unsigned chan = 0; chan < 4; chan++) {
5720 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5721 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5722 }
5723
5724 args->compr = 1;
5725 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5726 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5727 break;
5728 }
5729
5730 case V_028714_SPI_SHADER_SINT16_ABGR: {
5731 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5732 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5733 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5734 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5735 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5736 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5737
5738 /* Clamp. */
5739 for (unsigned chan = 0; chan < 4; chan++) {
5740 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5741 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5742 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5743 }
5744
5745 args->compr = 1;
5746 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5747 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5748 break;
5749 }
5750
5751 default:
5752 case V_028714_SPI_SHADER_32_ABGR:
5753 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5754 break;
5755 }
5756 } else
5757 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5758
5759 for (unsigned i = 0; i < 4; ++i)
5760 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5761 }
5762
5763 static void
5764 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5765 bool export_prim_id,
5766 struct ac_vs_output_info *outinfo)
5767 {
5768 uint32_t param_count = 0;
5769 unsigned target;
5770 unsigned pos_idx, num_pos_exports = 0;
5771 struct ac_export_args args, pos_args[4] = {};
5772 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5773 int i;
5774
5775 if (ctx->options->key.has_multiview_view_index) {
5776 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5777 if(!*tmp_out) {
5778 for(unsigned i = 0; i < 4; ++i)
5779 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5780 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5781 }
5782
5783 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5784 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5785 }
5786
5787 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5788 sizeof(outinfo->vs_output_param_offset));
5789
5790 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5791 LLVMValueRef slots[8];
5792 unsigned j;
5793
5794 if (outinfo->cull_dist_mask)
5795 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5796
5797 i = VARYING_SLOT_CLIP_DIST0;
5798 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5799 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5800 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5801
5802 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5803 slots[i] = LLVMGetUndef(ctx->ac.f32);
5804
5805 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5806 target = V_008DFC_SQ_EXP_POS + 3;
5807 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5808 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5809 &args, sizeof(args));
5810 }
5811
5812 target = V_008DFC_SQ_EXP_POS + 2;
5813 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5814 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5815 &args, sizeof(args));
5816
5817 }
5818
5819 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5820 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5821 for (unsigned j = 0; j < 4; j++)
5822 pos_values[j] = LLVMBuildLoad(ctx->builder,
5823 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5824 }
5825 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5826
5827 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5828 outinfo->writes_pointsize = true;
5829 psize_value = LLVMBuildLoad(ctx->builder,
5830 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5831 }
5832
5833 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5834 outinfo->writes_layer = true;
5835 layer_value = LLVMBuildLoad(ctx->builder,
5836 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5837 }
5838
5839 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5840 outinfo->writes_viewport_index = true;
5841 viewport_index_value = LLVMBuildLoad(ctx->builder,
5842 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5843 }
5844
5845 if (outinfo->writes_pointsize ||
5846 outinfo->writes_layer ||
5847 outinfo->writes_viewport_index) {
5848 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5849 (outinfo->writes_layer == true ? 4 : 0));
5850 pos_args[1].valid_mask = 0;
5851 pos_args[1].done = 0;
5852 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5853 pos_args[1].compr = 0;
5854 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5855 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5856 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5857 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5858
5859 if (outinfo->writes_pointsize == true)
5860 pos_args[1].out[0] = psize_value;
5861 if (outinfo->writes_layer == true)
5862 pos_args[1].out[2] = layer_value;
5863 if (outinfo->writes_viewport_index == true) {
5864 if (ctx->options->chip_class >= GFX9) {
5865 /* GFX9 has the layer in out.z[10:0] and the viewport
5866 * index in out.z[19:16].
5867 */
5868 LLVMValueRef v = viewport_index_value;
5869 v = ac_to_integer(&ctx->ac, v);
5870 v = LLVMBuildShl(ctx->builder, v,
5871 LLVMConstInt(ctx->ac.i32, 16, false),
5872 "");
5873 v = LLVMBuildOr(ctx->builder, v,
5874 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5875
5876 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5877 pos_args[1].enabled_channels |= 1 << 2;
5878 } else {
5879 pos_args[1].out[3] = viewport_index_value;
5880 pos_args[1].enabled_channels |= 1 << 3;
5881 }
5882 }
5883 }
5884 for (i = 0; i < 4; i++) {
5885 if (pos_args[i].out[0])
5886 num_pos_exports++;
5887 }
5888
5889 pos_idx = 0;
5890 for (i = 0; i < 4; i++) {
5891 if (!pos_args[i].out[0])
5892 continue;
5893
5894 /* Specify the target we are exporting */
5895 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5896 if (pos_idx == num_pos_exports)
5897 pos_args[i].done = 1;
5898 ac_build_export(&ctx->ac, &pos_args[i]);
5899 }
5900
5901 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5902 LLVMValueRef values[4];
5903 if (!(ctx->output_mask & (1ull << i)))
5904 continue;
5905
5906 for (unsigned j = 0; j < 4; j++)
5907 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5908 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5909
5910 if (i == VARYING_SLOT_LAYER) {
5911 target = V_008DFC_SQ_EXP_PARAM + param_count;
5912 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5913 param_count++;
5914 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5915 target = V_008DFC_SQ_EXP_PARAM + param_count;
5916 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5917 param_count++;
5918 } else if (i >= VARYING_SLOT_VAR0) {
5919 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5920 target = V_008DFC_SQ_EXP_PARAM + param_count;
5921 outinfo->vs_output_param_offset[i] = param_count;
5922 param_count++;
5923 } else
5924 continue;
5925
5926 si_llvm_init_export_args(ctx, values, target, &args);
5927
5928 if (target >= V_008DFC_SQ_EXP_POS &&
5929 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5930 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5931 &args, sizeof(args));
5932 } else {
5933 ac_build_export(&ctx->ac, &args);
5934 }
5935 }
5936
5937 if (export_prim_id) {
5938 LLVMValueRef values[4];
5939 target = V_008DFC_SQ_EXP_PARAM + param_count;
5940 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5941 param_count++;
5942
5943 values[0] = ctx->vs_prim_id;
5944 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5945 ctx->shader_info->vs.vgpr_comp_cnt);
5946 for (unsigned j = 1; j < 4; j++)
5947 values[j] = ctx->ac.f32_0;
5948 si_llvm_init_export_args(ctx, values, target, &args);
5949 ac_build_export(&ctx->ac, &args);
5950 outinfo->export_prim_id = true;
5951 }
5952
5953 outinfo->pos_exports = num_pos_exports;
5954 outinfo->param_exports = param_count;
5955 }
5956
5957 static void
5958 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5959 struct ac_es_output_info *outinfo)
5960 {
5961 int j;
5962 uint64_t max_output_written = 0;
5963 LLVMValueRef lds_base = NULL;
5964
5965 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5966 int param_index;
5967 int length = 4;
5968
5969 if (!(ctx->output_mask & (1ull << i)))
5970 continue;
5971
5972 if (i == VARYING_SLOT_CLIP_DIST0)
5973 length = ctx->num_output_clips + ctx->num_output_culls;
5974
5975 param_index = shader_io_get_unique_index(i);
5976
5977 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5978 }
5979
5980 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5981
5982 if (ctx->ac.chip_class >= GFX9) {
5983 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5984 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5985 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5986 LLVMConstInt(ctx->ac.i32, 24, false),
5987 LLVMConstInt(ctx->ac.i32, 4, false), false);
5988 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5989 LLVMBuildMul(ctx->ac.builder, wave_idx,
5990 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5991 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5992 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5993 }
5994
5995 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5996 LLVMValueRef dw_addr;
5997 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5998 int param_index;
5999 int length = 4;
6000
6001 if (!(ctx->output_mask & (1ull << i)))
6002 continue;
6003
6004 if (i == VARYING_SLOT_CLIP_DIST0)
6005 length = ctx->num_output_clips + ctx->num_output_culls;
6006
6007 param_index = shader_io_get_unique_index(i);
6008
6009 if (lds_base) {
6010 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6011 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6012 "");
6013 }
6014 for (j = 0; j < length; j++) {
6015 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6016 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6017
6018 if (ctx->ac.chip_class >= GFX9) {
6019 ac_lds_store(&ctx->ac, dw_addr,
6020 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6021 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6022 } else {
6023 ac_build_buffer_store_dword(&ctx->ac,
6024 ctx->esgs_ring,
6025 out_val, 1,
6026 NULL, ctx->es2gs_offset,
6027 (4 * param_index + j) * 4,
6028 1, 1, true, true);
6029 }
6030 }
6031 }
6032 }
6033
6034 static void
6035 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6036 {
6037 LLVMValueRef vertex_id = ctx->rel_auto_id;
6038 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6039 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6040 vertex_dw_stride, "");
6041
6042 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6043 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6044 int length = 4;
6045
6046 if (!(ctx->output_mask & (1ull << i)))
6047 continue;
6048
6049 if (i == VARYING_SLOT_CLIP_DIST0)
6050 length = ctx->num_output_clips + ctx->num_output_culls;
6051 int param = shader_io_get_unique_index(i);
6052 mark_tess_output(ctx, false, param);
6053 if (length > 4)
6054 mark_tess_output(ctx, false, param + 1);
6055 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6056 LLVMConstInt(ctx->ac.i32, param * 4, false),
6057 "");
6058 for (unsigned j = 0; j < length; j++) {
6059 ac_lds_store(&ctx->ac, dw_addr,
6060 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6061 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6062 }
6063 }
6064 }
6065
6066 struct ac_build_if_state
6067 {
6068 struct nir_to_llvm_context *ctx;
6069 LLVMValueRef condition;
6070 LLVMBasicBlockRef entry_block;
6071 LLVMBasicBlockRef true_block;
6072 LLVMBasicBlockRef false_block;
6073 LLVMBasicBlockRef merge_block;
6074 };
6075
6076 static LLVMBasicBlockRef
6077 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6078 {
6079 LLVMBasicBlockRef current_block;
6080 LLVMBasicBlockRef next_block;
6081 LLVMBasicBlockRef new_block;
6082
6083 /* get current basic block */
6084 current_block = LLVMGetInsertBlock(ctx->builder);
6085
6086 /* chqeck if there's another block after this one */
6087 next_block = LLVMGetNextBasicBlock(current_block);
6088 if (next_block) {
6089 /* insert the new block before the next block */
6090 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6091 }
6092 else {
6093 /* append new block after current block */
6094 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6095 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6096 }
6097 return new_block;
6098 }
6099
6100 static void
6101 ac_nir_build_if(struct ac_build_if_state *ifthen,
6102 struct nir_to_llvm_context *ctx,
6103 LLVMValueRef condition)
6104 {
6105 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6106
6107 memset(ifthen, 0, sizeof *ifthen);
6108 ifthen->ctx = ctx;
6109 ifthen->condition = condition;
6110 ifthen->entry_block = block;
6111
6112 /* create endif/merge basic block for the phi functions */
6113 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6114
6115 /* create/insert true_block before merge_block */
6116 ifthen->true_block =
6117 LLVMInsertBasicBlockInContext(ctx->context,
6118 ifthen->merge_block,
6119 "if-true-block");
6120
6121 /* successive code goes into the true block */
6122 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6123 }
6124
6125 /**
6126 * End a conditional.
6127 */
6128 static void
6129 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6130 {
6131 LLVMBuilderRef builder = ifthen->ctx->builder;
6132
6133 /* Insert branch to the merge block from current block */
6134 LLVMBuildBr(builder, ifthen->merge_block);
6135
6136 /*
6137 * Now patch in the various branch instructions.
6138 */
6139
6140 /* Insert the conditional branch instruction at the end of entry_block */
6141 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6142 if (ifthen->false_block) {
6143 /* we have an else clause */
6144 LLVMBuildCondBr(builder, ifthen->condition,
6145 ifthen->true_block, ifthen->false_block);
6146 }
6147 else {
6148 /* no else clause */
6149 LLVMBuildCondBr(builder, ifthen->condition,
6150 ifthen->true_block, ifthen->merge_block);
6151 }
6152
6153 /* Resume building code at end of the ifthen->merge_block */
6154 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6155 }
6156
6157 static void
6158 write_tess_factors(struct nir_to_llvm_context *ctx)
6159 {
6160 unsigned stride, outer_comps, inner_comps;
6161 struct ac_build_if_state if_ctx, inner_if_ctx;
6162 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6163 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6164 unsigned tess_inner_index, tess_outer_index;
6165 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6166 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6167 int i;
6168 emit_barrier(ctx);
6169
6170 switch (ctx->options->key.tcs.primitive_mode) {
6171 case GL_ISOLINES:
6172 stride = 2;
6173 outer_comps = 2;
6174 inner_comps = 0;
6175 break;
6176 case GL_TRIANGLES:
6177 stride = 4;
6178 outer_comps = 3;
6179 inner_comps = 1;
6180 break;
6181 case GL_QUADS:
6182 stride = 6;
6183 outer_comps = 4;
6184 inner_comps = 2;
6185 break;
6186 default:
6187 return;
6188 }
6189
6190 ac_nir_build_if(&if_ctx, ctx,
6191 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6192 invocation_id, ctx->ac.i32_0, ""));
6193
6194 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6195 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6196
6197 mark_tess_output(ctx, true, tess_inner_index);
6198 mark_tess_output(ctx, true, tess_outer_index);
6199 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6200 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6201 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6202 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6203 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6204
6205 for (i = 0; i < 4; i++) {
6206 inner[i] = LLVMGetUndef(ctx->ac.i32);
6207 outer[i] = LLVMGetUndef(ctx->ac.i32);
6208 }
6209
6210 // LINES reverseal
6211 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6212 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6213 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6214 ctx->ac.i32_1, "");
6215 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6216 } else {
6217 for (i = 0; i < outer_comps; i++) {
6218 outer[i] = out[i] =
6219 ac_lds_load(&ctx->ac, lds_outer);
6220 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6221 ctx->ac.i32_1, "");
6222 }
6223 for (i = 0; i < inner_comps; i++) {
6224 inner[i] = out[outer_comps+i] =
6225 ac_lds_load(&ctx->ac, lds_inner);
6226 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6227 ctx->ac.i32_1, "");
6228 }
6229 }
6230
6231 /* Convert the outputs to vectors for stores. */
6232 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6233 vec1 = NULL;
6234
6235 if (stride > 4)
6236 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6237
6238
6239 buffer = ctx->hs_ring_tess_factor;
6240 tf_base = ctx->tess_factor_offset;
6241 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6242 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6243 unsigned tf_offset = 0;
6244
6245 if (ctx->options->chip_class <= VI) {
6246 ac_nir_build_if(&inner_if_ctx, ctx,
6247 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6248 rel_patch_id, ctx->ac.i32_0, ""));
6249
6250 /* Store the dynamic HS control word. */
6251 ac_build_buffer_store_dword(&ctx->ac, buffer,
6252 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6253 1, ctx->ac.i32_0, tf_base,
6254 0, 1, 0, true, false);
6255 tf_offset += 4;
6256
6257 ac_nir_build_endif(&inner_if_ctx);
6258 }
6259
6260 /* Store the tessellation factors. */
6261 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6262 MIN2(stride, 4), byteoffset, tf_base,
6263 tf_offset, 1, 0, true, false);
6264 if (vec1)
6265 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6266 stride - 4, byteoffset, tf_base,
6267 16 + tf_offset, 1, 0, true, false);
6268
6269 //store to offchip for TES to read - only if TES reads them
6270 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6271 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6272 LLVMValueRef tf_inner_offset;
6273 unsigned param_outer, param_inner;
6274
6275 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6276 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6277 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6278
6279 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6280 util_next_power_of_two(outer_comps));
6281
6282 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6283 outer_comps, tf_outer_offset,
6284 ctx->oc_lds, 0, 1, 0, true, false);
6285 if (inner_comps) {
6286 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6287 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6288 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6289
6290 inner_vec = inner_comps == 1 ? inner[0] :
6291 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6292 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6293 inner_comps, tf_inner_offset,
6294 ctx->oc_lds, 0, 1, 0, true, false);
6295 }
6296 }
6297 ac_nir_build_endif(&if_ctx);
6298 }
6299
6300 static void
6301 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6302 {
6303 write_tess_factors(ctx);
6304 }
6305
6306 static bool
6307 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6308 LLVMValueRef *color, unsigned param, bool is_last,
6309 struct ac_export_args *args)
6310 {
6311 /* Export */
6312 si_llvm_init_export_args(ctx, color, param,
6313 args);
6314
6315 if (is_last) {
6316 args->valid_mask = 1; /* whether the EXEC mask is valid */
6317 args->done = 1; /* DONE bit */
6318 } else if (!args->enabled_channels)
6319 return false; /* unnecessary NULL export */
6320
6321 return true;
6322 }
6323
6324 static void
6325 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6326 LLVMValueRef depth, LLVMValueRef stencil,
6327 LLVMValueRef samplemask)
6328 {
6329 struct ac_export_args args;
6330
6331 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6332
6333 ac_build_export(&ctx->ac, &args);
6334 }
6335
6336 static void
6337 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6338 {
6339 unsigned index = 0;
6340 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6341 struct ac_export_args color_args[8];
6342
6343 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6344 LLVMValueRef values[4];
6345
6346 if (!(ctx->output_mask & (1ull << i)))
6347 continue;
6348
6349 if (i == FRAG_RESULT_DEPTH) {
6350 ctx->shader_info->fs.writes_z = true;
6351 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6352 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6353 } else if (i == FRAG_RESULT_STENCIL) {
6354 ctx->shader_info->fs.writes_stencil = true;
6355 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6356 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6357 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6358 ctx->shader_info->fs.writes_sample_mask = true;
6359 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6360 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6361 } else {
6362 bool last = false;
6363 for (unsigned j = 0; j < 4; j++)
6364 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6365 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6366
6367 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6368 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6369
6370 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6371 if (ret)
6372 index++;
6373 }
6374 }
6375
6376 for (unsigned i = 0; i < index; i++)
6377 ac_build_export(&ctx->ac, &color_args[i]);
6378 if (depth || stencil || samplemask)
6379 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6380 else if (!index) {
6381 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6382 ac_build_export(&ctx->ac, &color_args[0]);
6383 }
6384
6385 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6386 }
6387
6388 static void
6389 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6390 {
6391 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6392 }
6393
6394 static void
6395 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6396 LLVMValueRef *addrs)
6397 {
6398 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6399
6400 switch (ctx->stage) {
6401 case MESA_SHADER_VERTEX:
6402 if (ctx->options->key.vs.as_ls)
6403 handle_ls_outputs_post(ctx);
6404 else if (ctx->options->key.vs.as_es)
6405 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6406 else
6407 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6408 &ctx->shader_info->vs.outinfo);
6409 break;
6410 case MESA_SHADER_FRAGMENT:
6411 handle_fs_outputs_post(ctx);
6412 break;
6413 case MESA_SHADER_GEOMETRY:
6414 emit_gs_epilogue(ctx);
6415 break;
6416 case MESA_SHADER_TESS_CTRL:
6417 handle_tcs_outputs_post(ctx);
6418 break;
6419 case MESA_SHADER_TESS_EVAL:
6420 if (ctx->options->key.tes.as_es)
6421 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6422 else
6423 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6424 &ctx->shader_info->tes.outinfo);
6425 break;
6426 default:
6427 break;
6428 }
6429 }
6430
6431 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6432 {
6433 LLVMPassManagerRef passmgr;
6434 /* Create the pass manager */
6435 passmgr = LLVMCreateFunctionPassManagerForModule(
6436 ctx->module);
6437
6438 /* This pass should eliminate all the load and store instructions */
6439 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6440
6441 /* Add some optimization passes */
6442 LLVMAddScalarReplAggregatesPass(passmgr);
6443 LLVMAddLICMPass(passmgr);
6444 LLVMAddAggressiveDCEPass(passmgr);
6445 LLVMAddCFGSimplificationPass(passmgr);
6446 LLVMAddInstructionCombiningPass(passmgr);
6447
6448 /* Run the pass */
6449 LLVMInitializeFunctionPassManager(passmgr);
6450 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6451 LLVMFinalizeFunctionPassManager(passmgr);
6452
6453 LLVMDisposeBuilder(ctx->builder);
6454 LLVMDisposePassManager(passmgr);
6455 }
6456
6457 static void
6458 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6459 {
6460 struct ac_vs_output_info *outinfo;
6461
6462 switch (ctx->stage) {
6463 case MESA_SHADER_FRAGMENT:
6464 case MESA_SHADER_COMPUTE:
6465 case MESA_SHADER_TESS_CTRL:
6466 case MESA_SHADER_GEOMETRY:
6467 return;
6468 case MESA_SHADER_VERTEX:
6469 if (ctx->options->key.vs.as_ls ||
6470 ctx->options->key.vs.as_es)
6471 return;
6472 outinfo = &ctx->shader_info->vs.outinfo;
6473 break;
6474 case MESA_SHADER_TESS_EVAL:
6475 if (ctx->options->key.vs.as_es)
6476 return;
6477 outinfo = &ctx->shader_info->tes.outinfo;
6478 break;
6479 default:
6480 unreachable("Unhandled shader type");
6481 }
6482
6483 ac_optimize_vs_outputs(&ctx->ac,
6484 ctx->main_function,
6485 outinfo->vs_output_param_offset,
6486 VARYING_SLOT_MAX,
6487 &outinfo->param_exports);
6488 }
6489
6490 static void
6491 ac_setup_rings(struct nir_to_llvm_context *ctx)
6492 {
6493 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6494 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6495 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6496 }
6497
6498 if (ctx->is_gs_copy_shader) {
6499 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6500 }
6501 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6502 LLVMValueRef tmp;
6503 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6504 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6505
6506 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6507
6508 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6509 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6510 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6511 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6512 }
6513
6514 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6515 ctx->stage == MESA_SHADER_TESS_EVAL) {
6516 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6517 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6518 }
6519 }
6520
6521 static unsigned
6522 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6523 const struct nir_shader *nir)
6524 {
6525 switch (nir->info.stage) {
6526 case MESA_SHADER_TESS_CTRL:
6527 return chip_class >= CIK ? 128 : 64;
6528 case MESA_SHADER_GEOMETRY:
6529 return chip_class >= GFX9 ? 128 : 64;
6530 case MESA_SHADER_COMPUTE:
6531 break;
6532 default:
6533 return 0;
6534 }
6535
6536 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6537 nir->info.cs.local_size[1] *
6538 nir->info.cs.local_size[2];
6539 return max_workgroup_size;
6540 }
6541
6542 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6543 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6544 {
6545 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6546 LLVMConstInt(ctx->ac.i32, 8, false),
6547 LLVMConstInt(ctx->ac.i32, 8, false), false);
6548 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6549 ctx->ac.i32_0, "");
6550 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6551 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6552 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6553 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6554 }
6555
6556 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6557 {
6558 for(int i = 5; i >= 0; --i) {
6559 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6560 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6561 LLVMConstInt(ctx->ac.i32, 16, false), false);
6562 }
6563
6564 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6565 LLVMConstInt(ctx->ac.i32, 16, false),
6566 LLVMConstInt(ctx->ac.i32, 8, false), false);
6567 }
6568
6569 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6570 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6571 {
6572 struct ac_nir_context ctx = {};
6573 struct nir_function *func;
6574
6575 ctx.ac = *ac;
6576 ctx.abi = abi;
6577
6578 ctx.nctx = nctx;
6579 if (nctx)
6580 nctx->nir = &ctx;
6581
6582 ctx.stage = nir->info.stage;
6583
6584 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6585
6586 nir_foreach_variable(variable, &nir->outputs)
6587 handle_shader_output_decl(&ctx, nir, variable);
6588
6589 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6590 _mesa_key_pointer_equal);
6591 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6592 _mesa_key_pointer_equal);
6593 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6594 _mesa_key_pointer_equal);
6595
6596 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6597
6598 setup_locals(&ctx, func);
6599
6600 if (nir->info.stage == MESA_SHADER_COMPUTE)
6601 setup_shared(&ctx, nir);
6602
6603 visit_cf_list(&ctx, &func->impl->body);
6604 phi_post_pass(&ctx);
6605
6606 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6607 ctx.outputs);
6608
6609 free(ctx.locals);
6610 ralloc_free(ctx.defs);
6611 ralloc_free(ctx.phis);
6612 ralloc_free(ctx.vars);
6613
6614 if (nctx)
6615 nctx->nir = NULL;
6616 }
6617
6618 static
6619 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6620 struct nir_shader *const *shaders,
6621 int shader_count,
6622 struct ac_shader_variant_info *shader_info,
6623 const struct ac_nir_compiler_options *options)
6624 {
6625 struct nir_to_llvm_context ctx = {0};
6626 unsigned i;
6627 ctx.options = options;
6628 ctx.shader_info = shader_info;
6629 ctx.context = LLVMContextCreate();
6630 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6631
6632 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6633 options->family);
6634 ctx.ac.module = ctx.module;
6635 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6636
6637 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6638 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6639 LLVMSetDataLayout(ctx.module, data_layout_str);
6640 LLVMDisposeTargetData(data_layout);
6641 LLVMDisposeMessage(data_layout_str);
6642
6643 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6644 ctx.ac.builder = ctx.builder;
6645
6646 memset(shader_info, 0, sizeof(*shader_info));
6647
6648 for(int i = 0; i < shader_count; ++i)
6649 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6650
6651 for (i = 0; i < AC_UD_MAX_SETS; i++)
6652 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6653 for (i = 0; i < AC_UD_MAX_UD; i++)
6654 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6655
6656 ctx.max_workgroup_size = 0;
6657 for (int i = 0; i < shader_count; ++i) {
6658 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6659 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6660 shaders[i]));
6661 }
6662
6663 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6664 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6665
6666 ctx.abi.inputs = &ctx.inputs[0];
6667 ctx.abi.emit_outputs = handle_shader_outputs_post;
6668 ctx.abi.emit_vertex = visit_emit_vertex;
6669 ctx.abi.load_ubo = radv_load_ubo;
6670 ctx.abi.load_ssbo = radv_load_ssbo;
6671 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6672 ctx.abi.clamp_shadow_reference = false;
6673
6674 if (shader_count >= 2)
6675 ac_init_exec_full_mask(&ctx.ac);
6676
6677 if (ctx.ac.chip_class == GFX9 &&
6678 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6679 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6680
6681 for(int i = 0; i < shader_count; ++i) {
6682 ctx.stage = shaders[i]->info.stage;
6683 ctx.output_mask = 0;
6684 ctx.tess_outputs_written = 0;
6685 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6686 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6687
6688 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6689 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6690 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6691 ctx.abi.load_inputs = load_gs_input;
6692 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6693 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6694 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6695 ctx.abi.load_tess_inputs = load_tcs_input;
6696 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6697 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6698 ctx.abi.load_tess_inputs = load_tes_input;
6699 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6700 if (shader_info->info.vs.needs_instance_id) {
6701 ctx.shader_info->vs.vgpr_comp_cnt =
6702 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6703 }
6704 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6705 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6706 }
6707
6708 if (i)
6709 emit_barrier(&ctx);
6710
6711 ac_setup_rings(&ctx);
6712
6713 LLVMBasicBlockRef merge_block;
6714 if (shader_count >= 2) {
6715 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6716 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6717 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6718
6719 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6720 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6721 LLVMConstInt(ctx.ac.i32, 8, false), false);
6722 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6723 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6724 thread_id, count, "");
6725 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6726
6727 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6728 }
6729
6730 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6731 handle_fs_inputs(&ctx, shaders[i]);
6732 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6733 handle_vs_inputs(&ctx, shaders[i]);
6734 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6735 prepare_gs_input_vgprs(&ctx);
6736
6737 nir_foreach_variable(variable, &shaders[i]->outputs)
6738 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6739
6740 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6741
6742 if (shader_count >= 2) {
6743 LLVMBuildBr(ctx.ac.builder, merge_block);
6744 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6745 }
6746
6747 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6748 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6749 shaders[i]->info.cull_distance_array_size > 4;
6750 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6751 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6752 shaders[i]->info.gs.vertices_out;
6753 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6754 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6755 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6756 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6757 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6758 }
6759 }
6760
6761 LLVMBuildRetVoid(ctx.builder);
6762
6763 ac_llvm_finalize_module(&ctx);
6764
6765 if (shader_count == 1)
6766 ac_nir_eliminate_const_vs_outputs(&ctx);
6767
6768 return ctx.module;
6769 }
6770
6771 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6772 {
6773 unsigned *retval = (unsigned *)context;
6774 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6775 char *description = LLVMGetDiagInfoDescription(di);
6776
6777 if (severity == LLVMDSError) {
6778 *retval = 1;
6779 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6780 description);
6781 }
6782
6783 LLVMDisposeMessage(description);
6784 }
6785
6786 static unsigned ac_llvm_compile(LLVMModuleRef M,
6787 struct ac_shader_binary *binary,
6788 LLVMTargetMachineRef tm)
6789 {
6790 unsigned retval = 0;
6791 char *err;
6792 LLVMContextRef llvm_ctx;
6793 LLVMMemoryBufferRef out_buffer;
6794 unsigned buffer_size;
6795 const char *buffer_data;
6796 LLVMBool mem_err;
6797
6798 /* Setup Diagnostic Handler*/
6799 llvm_ctx = LLVMGetModuleContext(M);
6800
6801 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6802 &retval);
6803
6804 /* Compile IR*/
6805 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6806 &err, &out_buffer);
6807
6808 /* Process Errors/Warnings */
6809 if (mem_err) {
6810 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6811 free(err);
6812 retval = 1;
6813 goto out;
6814 }
6815
6816 /* Extract Shader Code*/
6817 buffer_size = LLVMGetBufferSize(out_buffer);
6818 buffer_data = LLVMGetBufferStart(out_buffer);
6819
6820 ac_elf_read(buffer_data, buffer_size, binary);
6821
6822 /* Clean up */
6823 LLVMDisposeMemoryBuffer(out_buffer);
6824
6825 out:
6826 return retval;
6827 }
6828
6829 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6830 LLVMModuleRef llvm_module,
6831 struct ac_shader_binary *binary,
6832 struct ac_shader_config *config,
6833 struct ac_shader_variant_info *shader_info,
6834 gl_shader_stage stage,
6835 bool dump_shader, bool supports_spill)
6836 {
6837 if (dump_shader)
6838 ac_dump_module(llvm_module);
6839
6840 memset(binary, 0, sizeof(*binary));
6841 int v = ac_llvm_compile(llvm_module, binary, tm);
6842 if (v) {
6843 fprintf(stderr, "compile failed\n");
6844 }
6845
6846 if (dump_shader)
6847 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6848
6849 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6850
6851 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6852 LLVMDisposeModule(llvm_module);
6853 LLVMContextDispose(ctx);
6854
6855 if (stage == MESA_SHADER_FRAGMENT) {
6856 shader_info->num_input_vgprs = 0;
6857 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6858 shader_info->num_input_vgprs += 2;
6859 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6860 shader_info->num_input_vgprs += 2;
6861 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6862 shader_info->num_input_vgprs += 2;
6863 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6864 shader_info->num_input_vgprs += 3;
6865 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6866 shader_info->num_input_vgprs += 2;
6867 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6868 shader_info->num_input_vgprs += 2;
6869 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6870 shader_info->num_input_vgprs += 2;
6871 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6872 shader_info->num_input_vgprs += 1;
6873 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6874 shader_info->num_input_vgprs += 1;
6875 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6876 shader_info->num_input_vgprs += 1;
6877 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6878 shader_info->num_input_vgprs += 1;
6879 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6880 shader_info->num_input_vgprs += 1;
6881 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6882 shader_info->num_input_vgprs += 1;
6883 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6884 shader_info->num_input_vgprs += 1;
6885 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6886 shader_info->num_input_vgprs += 1;
6887 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6888 shader_info->num_input_vgprs += 1;
6889 }
6890 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6891
6892 /* +3 for scratch wave offset and VCC */
6893 config->num_sgprs = MAX2(config->num_sgprs,
6894 shader_info->num_input_sgprs + 3);
6895 }
6896
6897 static void
6898 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6899 {
6900 switch (nir->info.stage) {
6901 case MESA_SHADER_COMPUTE:
6902 for (int i = 0; i < 3; ++i)
6903 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6904 break;
6905 case MESA_SHADER_FRAGMENT:
6906 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6907 break;
6908 case MESA_SHADER_GEOMETRY:
6909 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6910 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6911 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6912 shader_info->gs.invocations = nir->info.gs.invocations;
6913 break;
6914 case MESA_SHADER_TESS_EVAL:
6915 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6916 shader_info->tes.spacing = nir->info.tess.spacing;
6917 shader_info->tes.ccw = nir->info.tess.ccw;
6918 shader_info->tes.point_mode = nir->info.tess.point_mode;
6919 shader_info->tes.as_es = options->key.tes.as_es;
6920 break;
6921 case MESA_SHADER_TESS_CTRL:
6922 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6923 break;
6924 case MESA_SHADER_VERTEX:
6925 shader_info->vs.as_es = options->key.vs.as_es;
6926 shader_info->vs.as_ls = options->key.vs.as_ls;
6927 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6928 if (options->key.vs.as_ls)
6929 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6930 break;
6931 default:
6932 break;
6933 }
6934 }
6935
6936 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6937 struct ac_shader_binary *binary,
6938 struct ac_shader_config *config,
6939 struct ac_shader_variant_info *shader_info,
6940 struct nir_shader *const *nir,
6941 int nir_count,
6942 const struct ac_nir_compiler_options *options,
6943 bool dump_shader)
6944 {
6945
6946 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6947 options);
6948
6949 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6950 for (int i = 0; i < nir_count; ++i)
6951 ac_fill_shader_info(shader_info, nir[i], options);
6952 }
6953
6954 static void
6955 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6956 {
6957 LLVMValueRef args[9];
6958 args[0] = ctx->gsvs_ring;
6959 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6960 args[3] = ctx->ac.i32_0;
6961 args[4] = ctx->ac.i32_1; /* OFFEN */
6962 args[5] = ctx->ac.i32_0; /* IDXEN */
6963 args[6] = ctx->ac.i32_1; /* GLC */
6964 args[7] = ctx->ac.i32_1; /* SLC */
6965 args[8] = ctx->ac.i32_0; /* TFE */
6966
6967 int idx = 0;
6968
6969 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6970 int length = 4;
6971 int slot = idx;
6972 int slot_inc = 1;
6973 if (!(ctx->output_mask & (1ull << i)))
6974 continue;
6975
6976 if (i == VARYING_SLOT_CLIP_DIST0) {
6977 /* unpack clip and cull from a single set of slots */
6978 length = ctx->num_output_clips + ctx->num_output_culls;
6979 if (length > 4)
6980 slot_inc = 2;
6981 }
6982
6983 for (unsigned j = 0; j < length; j++) {
6984 LLVMValueRef value;
6985 args[2] = LLVMConstInt(ctx->ac.i32,
6986 (slot * 4 + j) *
6987 ctx->gs_max_out_vertices * 16 * 4, false);
6988
6989 value = ac_build_intrinsic(&ctx->ac,
6990 "llvm.SI.buffer.load.dword.i32.i32",
6991 ctx->ac.i32, args, 9,
6992 AC_FUNC_ATTR_READONLY |
6993 AC_FUNC_ATTR_LEGACY);
6994
6995 LLVMBuildStore(ctx->builder,
6996 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6997 }
6998 idx += slot_inc;
6999 }
7000 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7001 }
7002
7003 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7004 struct nir_shader *geom_shader,
7005 struct ac_shader_binary *binary,
7006 struct ac_shader_config *config,
7007 struct ac_shader_variant_info *shader_info,
7008 const struct ac_nir_compiler_options *options,
7009 bool dump_shader)
7010 {
7011 struct nir_to_llvm_context ctx = {0};
7012 ctx.context = LLVMContextCreate();
7013 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7014 ctx.options = options;
7015 ctx.shader_info = shader_info;
7016
7017 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7018 options->family);
7019 ctx.ac.module = ctx.module;
7020
7021 ctx.is_gs_copy_shader = true;
7022 LLVMSetTarget(ctx.module, "amdgcn--");
7023
7024 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7025 ctx.ac.builder = ctx.builder;
7026 ctx.stage = MESA_SHADER_VERTEX;
7027
7028 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7029
7030 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7031 ac_setup_rings(&ctx);
7032
7033 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7034 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7035
7036 struct ac_nir_context nir_ctx = {};
7037 nir_ctx.ac = ctx.ac;
7038 nir_ctx.abi = &ctx.abi;
7039
7040 nir_ctx.nctx = &ctx;
7041 ctx.nir = &nir_ctx;
7042
7043 nir_foreach_variable(variable, &geom_shader->outputs) {
7044 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7045 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7046 }
7047
7048 ac_gs_copy_shader_emit(&ctx);
7049
7050 ctx.nir = NULL;
7051
7052 LLVMBuildRetVoid(ctx.builder);
7053
7054 ac_llvm_finalize_module(&ctx);
7055
7056 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7057 MESA_SHADER_VERTEX,
7058 dump_shader, options->supports_spill);
7059 }