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ac/nir: consolidate setting userdata location
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 #include "ac_exp_param.h"
35
36 enum radeon_llvm_calling_convention {
37 RADEON_LLVM_AMDGPU_VS = 87,
38 RADEON_LLVM_AMDGPU_GS = 88,
39 RADEON_LLVM_AMDGPU_PS = 89,
40 RADEON_LLVM_AMDGPU_CS = 90,
41 };
42
43 #define CONST_ADDR_SPACE 2
44 #define LOCAL_ADDR_SPACE 3
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 enum desc_type {
50 DESC_IMAGE,
51 DESC_FMASK,
52 DESC_SAMPLER,
53 DESC_BUFFER,
54 };
55
56 struct nir_to_llvm_context {
57 struct ac_llvm_context ac;
58 const struct ac_nir_compiler_options *options;
59 struct ac_shader_variant_info *shader_info;
60 unsigned max_workgroup_size;
61 LLVMContextRef context;
62 LLVMModuleRef module;
63 LLVMBuilderRef builder;
64 LLVMValueRef main_function;
65
66 struct hash_table *defs;
67 struct hash_table *phis;
68
69 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
70 LLVMValueRef ring_offsets;
71 LLVMValueRef push_constants;
72 LLVMValueRef num_work_groups;
73 LLVMValueRef workgroup_ids;
74 LLVMValueRef local_invocation_ids;
75 LLVMValueRef tg_size;
76
77 LLVMValueRef vertex_buffers;
78 LLVMValueRef base_vertex;
79 LLVMValueRef start_instance;
80 LLVMValueRef draw_index;
81 LLVMValueRef vertex_id;
82 LLVMValueRef rel_auto_id;
83 LLVMValueRef vs_prim_id;
84 LLVMValueRef instance_id;
85 LLVMValueRef ls_out_layout;
86 LLVMValueRef es2gs_offset;
87
88 LLVMValueRef tcs_offchip_layout;
89 LLVMValueRef tcs_out_offsets;
90 LLVMValueRef tcs_out_layout;
91 LLVMValueRef tcs_in_layout;
92 LLVMValueRef oc_lds;
93 LLVMValueRef tess_factor_offset;
94 LLVMValueRef tcs_patch_id;
95 LLVMValueRef tcs_rel_ids;
96 LLVMValueRef tes_rel_patch_id;
97 LLVMValueRef tes_patch_id;
98 LLVMValueRef tes_u;
99 LLVMValueRef tes_v;
100
101 LLVMValueRef gsvs_ring_stride;
102 LLVMValueRef gsvs_num_entries;
103 LLVMValueRef gs2vs_offset;
104 LLVMValueRef gs_wave_id;
105 LLVMValueRef gs_vtx_offset[6];
106 LLVMValueRef gs_prim_id, gs_invocation_id;
107
108 LLVMValueRef esgs_ring;
109 LLVMValueRef gsvs_ring;
110 LLVMValueRef hs_ring_tess_offchip;
111 LLVMValueRef hs_ring_tess_factor;
112
113 LLVMValueRef prim_mask;
114 LLVMValueRef sample_pos_offset;
115 LLVMValueRef persp_sample, persp_center, persp_centroid;
116 LLVMValueRef linear_sample, linear_center, linear_centroid;
117 LLVMValueRef front_face;
118 LLVMValueRef ancillary;
119 LLVMValueRef sample_coverage;
120 LLVMValueRef frag_pos[4];
121
122 LLVMBasicBlockRef continue_block;
123 LLVMBasicBlockRef break_block;
124
125 LLVMTypeRef i1;
126 LLVMTypeRef i8;
127 LLVMTypeRef i16;
128 LLVMTypeRef i32;
129 LLVMTypeRef i64;
130 LLVMTypeRef v2i32;
131 LLVMTypeRef v3i32;
132 LLVMTypeRef v4i32;
133 LLVMTypeRef v8i32;
134 LLVMTypeRef f64;
135 LLVMTypeRef f32;
136 LLVMTypeRef f16;
137 LLVMTypeRef v2f32;
138 LLVMTypeRef v4f32;
139 LLVMTypeRef v16i8;
140 LLVMTypeRef voidt;
141
142 LLVMValueRef i1true;
143 LLVMValueRef i1false;
144 LLVMValueRef i32zero;
145 LLVMValueRef i32one;
146 LLVMValueRef f32zero;
147 LLVMValueRef f32one;
148 LLVMValueRef v4f32empty;
149
150 unsigned uniform_md_kind;
151 LLVMValueRef empty_md;
152 gl_shader_stage stage;
153
154 LLVMValueRef lds;
155 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
156 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
157
158 LLVMValueRef shared_memory;
159 uint64_t input_mask;
160 uint64_t output_mask;
161 int num_locals;
162 LLVMValueRef *locals;
163 bool has_ddxy;
164 uint8_t num_output_clips;
165 uint8_t num_output_culls;
166
167 bool has_ds_bpermute;
168
169 bool is_gs_copy_shader;
170 LLVMValueRef gs_next_vertex;
171 unsigned gs_max_out_vertices;
172
173 unsigned tes_primitive_mode;
174 uint64_t tess_outputs_written;
175 uint64_t tess_patch_outputs_written;
176 };
177
178 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
179 nir_deref_var *deref,
180 enum desc_type desc_type);
181 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
182 {
183 return (index * 4) + chan;
184 }
185
186 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
187 {
188 /* handle patch indices separate */
189 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
190 return 0;
191 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
192 return 1;
193 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
194 return 2 + (slot - VARYING_SLOT_PATCH0);
195
196 if (slot == VARYING_SLOT_POS)
197 return 0;
198 if (slot == VARYING_SLOT_PSIZ)
199 return 1;
200 if (slot == VARYING_SLOT_CLIP_DIST0)
201 return 2;
202 /* 3 is reserved for clip dist as well */
203 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
204 return 4 + (slot - VARYING_SLOT_VAR0);
205 unreachable("illegal slot in get unique index\n");
206 }
207
208 static unsigned llvm_get_type_size(LLVMTypeRef type)
209 {
210 LLVMTypeKind kind = LLVMGetTypeKind(type);
211
212 switch (kind) {
213 case LLVMIntegerTypeKind:
214 return LLVMGetIntTypeWidth(type) / 8;
215 case LLVMFloatTypeKind:
216 return 4;
217 case LLVMPointerTypeKind:
218 return 8;
219 case LLVMVectorTypeKind:
220 return LLVMGetVectorSize(type) *
221 llvm_get_type_size(LLVMGetElementType(type));
222 default:
223 assert(0);
224 return 0;
225 }
226 }
227
228 static void set_llvm_calling_convention(LLVMValueRef func,
229 gl_shader_stage stage)
230 {
231 enum radeon_llvm_calling_convention calling_conv;
232
233 switch (stage) {
234 case MESA_SHADER_VERTEX:
235 case MESA_SHADER_TESS_CTRL:
236 case MESA_SHADER_TESS_EVAL:
237 calling_conv = RADEON_LLVM_AMDGPU_VS;
238 break;
239 case MESA_SHADER_GEOMETRY:
240 calling_conv = RADEON_LLVM_AMDGPU_GS;
241 break;
242 case MESA_SHADER_FRAGMENT:
243 calling_conv = RADEON_LLVM_AMDGPU_PS;
244 break;
245 case MESA_SHADER_COMPUTE:
246 calling_conv = RADEON_LLVM_AMDGPU_CS;
247 break;
248 default:
249 unreachable("Unhandle shader type");
250 }
251
252 LLVMSetFunctionCallConv(func, calling_conv);
253 }
254
255 static LLVMValueRef
256 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
257 LLVMBuilderRef builder, LLVMTypeRef *return_types,
258 unsigned num_return_elems, LLVMTypeRef *param_types,
259 unsigned param_count, unsigned array_params_mask,
260 unsigned sgpr_params, unsigned max_workgroup_size,
261 bool unsafe_math)
262 {
263 LLVMTypeRef main_function_type, ret_type;
264 LLVMBasicBlockRef main_function_body;
265
266 if (num_return_elems)
267 ret_type = LLVMStructTypeInContext(ctx, return_types,
268 num_return_elems, true);
269 else
270 ret_type = LLVMVoidTypeInContext(ctx);
271
272 /* Setup the function */
273 main_function_type =
274 LLVMFunctionType(ret_type, param_types, param_count, 0);
275 LLVMValueRef main_function =
276 LLVMAddFunction(module, "main", main_function_type);
277 main_function_body =
278 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
279 LLVMPositionBuilderAtEnd(builder, main_function_body);
280
281 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
282 for (unsigned i = 0; i < sgpr_params; ++i) {
283 if (array_params_mask & (1 << i)) {
284 LLVMValueRef P = LLVMGetParam(main_function, i);
285 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
286 ac_add_attr_dereferenceable(P, UINT64_MAX);
287 }
288 else {
289 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
290 }
291 }
292
293 if (max_workgroup_size) {
294 ac_llvm_add_target_dep_function_attr(main_function,
295 "amdgpu-max-work-group-size",
296 max_workgroup_size);
297 }
298 if (unsafe_math) {
299 /* These were copied from some LLVM test. */
300 LLVMAddTargetDependentFunctionAttr(main_function,
301 "less-precise-fpmad",
302 "true");
303 LLVMAddTargetDependentFunctionAttr(main_function,
304 "no-infs-fp-math",
305 "true");
306 LLVMAddTargetDependentFunctionAttr(main_function,
307 "no-nans-fp-math",
308 "true");
309 LLVMAddTargetDependentFunctionAttr(main_function,
310 "unsafe-fp-math",
311 "true");
312 }
313 return main_function;
314 }
315
316 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
317 {
318 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
319 CONST_ADDR_SPACE);
320 }
321
322 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
323 int idx,
324 LLVMTypeRef type)
325 {
326 LLVMValueRef offset;
327 LLVMValueRef ptr;
328 int addr_space;
329
330 offset = LLVMConstInt(ctx->i32, idx * 16, false);
331
332 ptr = ctx->shared_memory;
333 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
334 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
335 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
336 return ptr;
337 }
338
339 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
340 {
341 if (t == ctx->f16 || t == ctx->i16)
342 return ctx->i16;
343 else if (t == ctx->f32 || t == ctx->i32)
344 return ctx->i32;
345 else if (t == ctx->f64 || t == ctx->i64)
346 return ctx->i64;
347 else
348 unreachable("Unhandled integer size");
349 }
350
351 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
352 {
353 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
354 LLVMTypeRef elem_type = LLVMGetElementType(t);
355 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
356 LLVMGetVectorSize(t));
357 }
358 return to_integer_type_scalar(ctx, t);
359 }
360
361 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
362 {
363 LLVMTypeRef type = LLVMTypeOf(v);
364 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
365 }
366
367 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
368 {
369 if (t == ctx->i16 || t == ctx->f16)
370 return ctx->f16;
371 else if (t == ctx->i32 || t == ctx->f32)
372 return ctx->f32;
373 else if (t == ctx->i64 || t == ctx->f64)
374 return ctx->f64;
375 else
376 unreachable("Unhandled float size");
377 }
378
379 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
380 {
381 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
382 LLVMTypeRef elem_type = LLVMGetElementType(t);
383 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
384 LLVMGetVectorSize(t));
385 }
386 return to_float_type_scalar(ctx, t);
387 }
388
389 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
390 {
391 LLVMTypeRef type = LLVMTypeOf(v);
392 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
393 }
394
395 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
396 {
397 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
398 type = LLVMGetElementType(type);
399
400 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
401 return LLVMGetIntTypeWidth(type);
402
403 if (type == ctx->f16)
404 return 16;
405 if (type == ctx->f32)
406 return 32;
407 if (type == ctx->f64)
408 return 64;
409
410 unreachable("Unhandled type kind in get_elem_bits");
411 }
412
413 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
414 LLVMValueRef param, unsigned rshift,
415 unsigned bitwidth)
416 {
417 LLVMValueRef value = param;
418 if (rshift)
419 value = LLVMBuildLShr(ctx->builder, value,
420 LLVMConstInt(ctx->i32, rshift, false), "");
421
422 if (rshift + bitwidth < 32) {
423 unsigned mask = (1 << bitwidth) - 1;
424 value = LLVMBuildAnd(ctx->builder, value,
425 LLVMConstInt(ctx->i32, mask, false), "");
426 }
427 return value;
428 }
429
430 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
431 {
432 switch (ctx->stage) {
433 case MESA_SHADER_TESS_CTRL:
434 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
435 case MESA_SHADER_TESS_EVAL:
436 return ctx->tes_rel_patch_id;
437 break;
438 default:
439 unreachable("Illegal stage");
440 }
441 }
442
443 /* Tessellation shaders pass outputs to the next shader using LDS.
444 *
445 * LS outputs = TCS inputs
446 * TCS outputs = TES inputs
447 *
448 * The LDS layout is:
449 * - TCS inputs for patch 0
450 * - TCS inputs for patch 1
451 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
452 * - ...
453 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
454 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
455 * - TCS outputs for patch 1
456 * - Per-patch TCS outputs for patch 1
457 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
458 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
459 * - ...
460 *
461 * All three shaders VS(LS), TCS, TES share the same LDS space.
462 */
463 static LLVMValueRef
464 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
465 {
466 if (ctx->stage == MESA_SHADER_VERTEX)
467 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
468 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
469 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
470 else {
471 assert(0);
472 return NULL;
473 }
474 }
475
476 static LLVMValueRef
477 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
478 {
479 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
480 }
481
482 static LLVMValueRef
483 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
484 {
485 return LLVMBuildMul(ctx->builder,
486 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
487 LLVMConstInt(ctx->i32, 4, false), "");
488 }
489
490 static LLVMValueRef
491 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
492 {
493 return LLVMBuildMul(ctx->builder,
494 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
495 LLVMConstInt(ctx->i32, 4, false), "");
496 }
497
498 static LLVMValueRef
499 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
500 {
501 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
502 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
503
504 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
505 }
506
507 static LLVMValueRef
508 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
509 {
510 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
511 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
512 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
513
514 return LLVMBuildAdd(ctx->builder, patch0_offset,
515 LLVMBuildMul(ctx->builder, patch_stride,
516 rel_patch_id, ""),
517 "");
518 }
519
520 static LLVMValueRef
521 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
522 {
523 LLVMValueRef patch0_patch_data_offset =
524 get_tcs_out_patch0_patch_data_offset(ctx);
525 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
526 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
527
528 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
529 LLVMBuildMul(ctx->builder, patch_stride,
530 rel_patch_id, ""),
531 "");
532 }
533
534 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
535 {
536 ud_info->sgpr_idx = *sgpr_idx;
537 ud_info->num_sgprs = num_sgprs;
538 ud_info->indirect = false;
539 ud_info->indirect_offset = 0;
540 *sgpr_idx += num_sgprs;
541 }
542
543 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
544 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
545 {
546 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
547 }
548
549
550 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
551 uint32_t indirect_offset)
552 {
553 ud_info->sgpr_idx = sgpr_idx;
554 ud_info->num_sgprs = num_sgprs;
555 ud_info->indirect = true;
556 ud_info->indirect_offset = indirect_offset;
557 }
558
559 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
560 {
561 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
562 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
563 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
564 "tess_lds");
565 }
566
567 struct user_sgpr_info {
568 bool need_ring_offsets;
569 uint8_t sgpr_count;
570 bool indirect_all_descriptor_sets;
571 };
572
573 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
574 struct user_sgpr_info *user_sgpr_info)
575 {
576 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
577
578 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
579 if (ctx->stage == MESA_SHADER_GEOMETRY ||
580 ctx->stage == MESA_SHADER_VERTEX ||
581 ctx->stage == MESA_SHADER_TESS_CTRL ||
582 ctx->stage == MESA_SHADER_TESS_EVAL ||
583 ctx->is_gs_copy_shader)
584 user_sgpr_info->need_ring_offsets = true;
585
586 if (ctx->stage == MESA_SHADER_FRAGMENT &&
587 ctx->shader_info->info.ps.needs_sample_positions)
588 user_sgpr_info->need_ring_offsets = true;
589
590 /* 2 user sgprs will nearly always be allocated for scratch/rings */
591 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
592 user_sgpr_info->sgpr_count += 2;
593 }
594
595 switch (ctx->stage) {
596 case MESA_SHADER_COMPUTE:
597 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
598 break;
599 case MESA_SHADER_FRAGMENT:
600 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
601 break;
602 case MESA_SHADER_VERTEX:
603 if (!ctx->is_gs_copy_shader) {
604 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
605 if (ctx->shader_info->info.vs.needs_draw_id) {
606 user_sgpr_info->sgpr_count += 3;
607 } else {
608 user_sgpr_info->sgpr_count += 2;
609 }
610 }
611 if (ctx->options->key.vs.as_ls)
612 user_sgpr_info->sgpr_count++;
613 break;
614 case MESA_SHADER_TESS_CTRL:
615 user_sgpr_info->sgpr_count += 4;
616 break;
617 case MESA_SHADER_TESS_EVAL:
618 user_sgpr_info->sgpr_count += 1;
619 break;
620 case MESA_SHADER_GEOMETRY:
621 user_sgpr_info->sgpr_count += 2;
622 break;
623 default:
624 break;
625 }
626
627 if (ctx->shader_info->info.needs_push_constants)
628 user_sgpr_info->sgpr_count += 2;
629
630 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
631 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
632 user_sgpr_info->sgpr_count += 2;
633 user_sgpr_info->indirect_all_descriptor_sets = true;
634 } else {
635 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
636 }
637 }
638
639 static void create_function(struct nir_to_llvm_context *ctx)
640 {
641 LLVMTypeRef arg_types[23];
642 unsigned arg_idx = 0;
643 unsigned array_params_mask = 0;
644 unsigned sgpr_count = 0, user_sgpr_count;
645 unsigned i;
646 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
647 uint8_t user_sgpr_idx;
648 struct user_sgpr_info user_sgpr_info;
649
650 allocate_user_sgprs(ctx, &user_sgpr_info);
651 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
652 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* address of rings */
653 }
654
655 /* 1 for each descriptor set */
656 if (!user_sgpr_info.indirect_all_descriptor_sets) {
657 for (unsigned i = 0; i < num_sets; ++i) {
658 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
659 array_params_mask |= (1 << arg_idx);
660 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
661 }
662 }
663 } else {
664 array_params_mask |= (1 << arg_idx);
665 arg_types[arg_idx++] = const_array(const_array(ctx->i8, 1024 * 1024), 32);
666 }
667
668 if (ctx->shader_info->info.needs_push_constants) {
669 /* 1 for push constants and dynamic descriptors */
670 array_params_mask |= (1 << arg_idx);
671 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
672 }
673
674 switch (ctx->stage) {
675 case MESA_SHADER_COMPUTE:
676 if (ctx->shader_info->info.cs.grid_components_used)
677 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used); /* grid size */
678 user_sgpr_count = arg_idx;
679 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
680 arg_types[arg_idx++] = ctx->i32;
681 sgpr_count = arg_idx;
682
683 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
684 break;
685 case MESA_SHADER_VERTEX:
686 if (!ctx->is_gs_copy_shader) {
687 if (ctx->shader_info->info.vs.has_vertex_buffers)
688 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
689 arg_types[arg_idx++] = ctx->i32; // base vertex
690 arg_types[arg_idx++] = ctx->i32; // start instance
691 if (ctx->shader_info->info.vs.needs_draw_id)
692 arg_types[arg_idx++] = ctx->i32; // draw index
693 }
694 user_sgpr_count = arg_idx;
695 if (ctx->options->key.vs.as_es)
696 arg_types[arg_idx++] = ctx->i32; //es2gs offset
697 else if (ctx->options->key.vs.as_ls) {
698 arg_types[arg_idx++] = ctx->i32; //ls out layout
699 user_sgpr_count++;
700 }
701 sgpr_count = arg_idx;
702 arg_types[arg_idx++] = ctx->i32; // vertex id
703 if (!ctx->is_gs_copy_shader) {
704 arg_types[arg_idx++] = ctx->i32; // rel auto id
705 arg_types[arg_idx++] = ctx->i32; // vs prim id
706 arg_types[arg_idx++] = ctx->i32; // instance id
707 }
708 break;
709 case MESA_SHADER_TESS_CTRL:
710 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
711 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
712 arg_types[arg_idx++] = ctx->i32; // tcs out layout
713 arg_types[arg_idx++] = ctx->i32; // tcs in layout
714 user_sgpr_count = arg_idx;
715 arg_types[arg_idx++] = ctx->i32; // param oc lds
716 arg_types[arg_idx++] = ctx->i32; // tess factor offset
717 sgpr_count = arg_idx;
718 arg_types[arg_idx++] = ctx->i32; // patch id
719 arg_types[arg_idx++] = ctx->i32; // rel ids;
720 break;
721 case MESA_SHADER_TESS_EVAL:
722 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
723 user_sgpr_count = arg_idx;
724 if (ctx->options->key.tes.as_es) {
725 arg_types[arg_idx++] = ctx->i32; // OC LDS
726 arg_types[arg_idx++] = ctx->i32; //
727 arg_types[arg_idx++] = ctx->i32; // es2gs offset
728 } else {
729 arg_types[arg_idx++] = ctx->i32; //
730 arg_types[arg_idx++] = ctx->i32; // OC LDS
731 }
732 sgpr_count = arg_idx;
733 arg_types[arg_idx++] = ctx->f32; // tes_u
734 arg_types[arg_idx++] = ctx->f32; // tes_v
735 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
736 arg_types[arg_idx++] = ctx->i32; // tes patch id
737 break;
738 case MESA_SHADER_GEOMETRY:
739 arg_types[arg_idx++] = ctx->i32; // gsvs stride
740 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
741 user_sgpr_count = arg_idx;
742 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
743 arg_types[arg_idx++] = ctx->i32; // wave id
744 sgpr_count = arg_idx;
745 arg_types[arg_idx++] = ctx->i32; // vtx0
746 arg_types[arg_idx++] = ctx->i32; // vtx1
747 arg_types[arg_idx++] = ctx->i32; // prim id
748 arg_types[arg_idx++] = ctx->i32; // vtx2
749 arg_types[arg_idx++] = ctx->i32; // vtx3
750 arg_types[arg_idx++] = ctx->i32; // vtx4
751 arg_types[arg_idx++] = ctx->i32; // vtx5
752 arg_types[arg_idx++] = ctx->i32; // GS instance id
753 break;
754 case MESA_SHADER_FRAGMENT:
755 if (ctx->shader_info->info.ps.needs_sample_positions)
756 arg_types[arg_idx++] = ctx->i32; /* sample position offset */
757 user_sgpr_count = arg_idx;
758 arg_types[arg_idx++] = ctx->i32; /* prim mask */
759 sgpr_count = arg_idx;
760 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
761 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
762 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
763 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
764 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
765 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
766 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
767 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
768 arg_types[arg_idx++] = ctx->f32; /* pos x float */
769 arg_types[arg_idx++] = ctx->f32; /* pos y float */
770 arg_types[arg_idx++] = ctx->f32; /* pos z float */
771 arg_types[arg_idx++] = ctx->f32; /* pos w float */
772 arg_types[arg_idx++] = ctx->i32; /* front face */
773 arg_types[arg_idx++] = ctx->i32; /* ancillary */
774 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
775 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
776 break;
777 default:
778 unreachable("Shader stage not implemented");
779 }
780
781 ctx->main_function = create_llvm_function(
782 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
783 arg_idx, array_params_mask, sgpr_count, ctx->max_workgroup_size,
784 ctx->options->unsafe_math);
785 set_llvm_calling_convention(ctx->main_function, ctx->stage);
786
787 ctx->shader_info->num_input_sgprs = 0;
788 ctx->shader_info->num_input_vgprs = 0;
789
790 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
791 for (i = 0; i < user_sgpr_count; i++)
792 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
793
794 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
795 for (; i < sgpr_count; i++)
796 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
797
798 if (ctx->stage != MESA_SHADER_FRAGMENT)
799 for (; i < arg_idx; ++i)
800 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
801
802 arg_idx = 0;
803 user_sgpr_idx = 0;
804
805 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
806 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
807 if (ctx->options->supports_spill) {
808 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
809 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
810 NULL, 0, AC_FUNC_ATTR_READNONE);
811 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
812 const_array(ctx->v16i8, 16), "");
813 } else
814 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
815 }
816
817 if (!user_sgpr_info.indirect_all_descriptor_sets) {
818 for (unsigned i = 0; i < num_sets; ++i) {
819 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
820 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
821 ctx->descriptor_sets[i] =
822 LLVMGetParam(ctx->main_function, arg_idx++);
823 } else
824 ctx->descriptor_sets[i] = NULL;
825 }
826 } else {
827 uint32_t desc_sgpr_idx = user_sgpr_idx;
828 LLVMValueRef desc_sets = LLVMGetParam(ctx->main_function, arg_idx++);
829 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
830
831 for (unsigned i = 0; i < num_sets; ++i) {
832 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
833 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
834 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
835
836 } else
837 ctx->descriptor_sets[i] = NULL;
838 }
839 ctx->shader_info->need_indirect_descriptor_sets = true;
840 }
841
842 if (ctx->shader_info->info.needs_push_constants) {
843 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
844 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
845 }
846
847 switch (ctx->stage) {
848 case MESA_SHADER_COMPUTE:
849 if (ctx->shader_info->info.cs.grid_components_used) {
850 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
851 ctx->num_work_groups =
852 LLVMGetParam(ctx->main_function, arg_idx++);
853 }
854 ctx->workgroup_ids =
855 LLVMGetParam(ctx->main_function, arg_idx++);
856 ctx->tg_size =
857 LLVMGetParam(ctx->main_function, arg_idx++);
858 ctx->local_invocation_ids =
859 LLVMGetParam(ctx->main_function, arg_idx++);
860 break;
861 case MESA_SHADER_VERTEX:
862 if (!ctx->is_gs_copy_shader) {
863 if (ctx->shader_info->info.vs.has_vertex_buffers) {
864 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
865 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
866 }
867 unsigned vs_num = 2;
868 if (ctx->shader_info->info.vs.needs_draw_id)
869 vs_num++;
870
871 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
872
873 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
874 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
875 if (ctx->shader_info->info.vs.needs_draw_id)
876 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
877 }
878 if (ctx->options->key.vs.as_es)
879 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
880 else if (ctx->options->key.vs.as_ls) {
881 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
882 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
883 }
884 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
885 if (!ctx->is_gs_copy_shader) {
886 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
887 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
888 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
889 }
890 if (ctx->options->key.vs.as_ls)
891 declare_tess_lds(ctx);
892 break;
893 case MESA_SHADER_TESS_CTRL:
894 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
895 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
896 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
897 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
898 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
899 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
900 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
901 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
902 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
903
904 declare_tess_lds(ctx);
905 break;
906 case MESA_SHADER_TESS_EVAL:
907 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
908 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
909 if (ctx->options->key.tes.as_es) {
910 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
911 arg_idx++;
912 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
913 } else {
914 arg_idx++;
915 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
916 }
917 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
918 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
919 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
920 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
921 break;
922 case MESA_SHADER_GEOMETRY:
923 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
924 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
925 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
926 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
927 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
928 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
929 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
930 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
931 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
932 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
933 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
934 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
935 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
936 break;
937 case MESA_SHADER_FRAGMENT:
938 if (ctx->shader_info->info.ps.needs_sample_positions) {
939 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
940 ctx->sample_pos_offset = LLVMGetParam(ctx->main_function, arg_idx++);
941 }
942 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
943 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
944 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
945 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
946 arg_idx++;
947 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
948 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
949 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
950 arg_idx++; /* line stipple */
951 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
952 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
953 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
954 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
955 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
956 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
957 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
958 break;
959 default:
960 unreachable("Shader stage not implemented");
961 }
962 }
963
964 static void setup_types(struct nir_to_llvm_context *ctx)
965 {
966 LLVMValueRef args[4];
967
968 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
969 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
970 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
971 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
972 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
973 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
974 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
975 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
976 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
977 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
978 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
979 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
980 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
981 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
982 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
983 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
984
985 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
986 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
987 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
988 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
989 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
990 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
991
992 args[0] = ctx->f32zero;
993 args[1] = ctx->f32zero;
994 args[2] = ctx->f32zero;
995 args[3] = ctx->f32one;
996 ctx->v4f32empty = LLVMConstVector(args, 4);
997
998 ctx->uniform_md_kind =
999 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
1000 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
1001
1002 args[0] = LLVMConstReal(ctx->f32, 2.5);
1003 }
1004
1005 static int get_llvm_num_components(LLVMValueRef value)
1006 {
1007 LLVMTypeRef type = LLVMTypeOf(value);
1008 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1009 ? LLVMGetVectorSize(type)
1010 : 1;
1011 return num_components;
1012 }
1013
1014 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
1015 LLVMValueRef value,
1016 int index)
1017 {
1018 int count = get_llvm_num_components(value);
1019
1020 assert(index < count);
1021 if (count == 1)
1022 return value;
1023
1024 return LLVMBuildExtractElement(ctx->builder, value,
1025 LLVMConstInt(ctx->i32, index, false), "");
1026 }
1027
1028 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
1029 LLVMValueRef value, unsigned count)
1030 {
1031 unsigned num_components = get_llvm_num_components(value);
1032 if (count == num_components)
1033 return value;
1034
1035 LLVMValueRef masks[] = {
1036 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1037 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1038
1039 if (count == 1)
1040 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1041 "");
1042
1043 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1044 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1045 }
1046
1047 static void
1048 build_store_values_extended(struct nir_to_llvm_context *ctx,
1049 LLVMValueRef *values,
1050 unsigned value_count,
1051 unsigned value_stride,
1052 LLVMValueRef vec)
1053 {
1054 LLVMBuilderRef builder = ctx->builder;
1055 unsigned i;
1056
1057 if (value_count == 1) {
1058 LLVMBuildStore(builder, vec, values[0]);
1059 return;
1060 }
1061
1062 for (i = 0; i < value_count; i++) {
1063 LLVMValueRef ptr = values[i * value_stride];
1064 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
1065 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1066 LLVMBuildStore(builder, value, ptr);
1067 }
1068 }
1069
1070 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
1071 nir_ssa_def *def)
1072 {
1073 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
1074 if (def->num_components > 1) {
1075 type = LLVMVectorType(type, def->num_components);
1076 }
1077 return type;
1078 }
1079
1080 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
1081 {
1082 assert(src.is_ssa);
1083 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1084 return (LLVMValueRef)entry->data;
1085 }
1086
1087
1088 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1089 struct nir_block *b)
1090 {
1091 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1092 return (LLVMBasicBlockRef)entry->data;
1093 }
1094
1095 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1096 nir_alu_src src,
1097 unsigned num_components)
1098 {
1099 LLVMValueRef value = get_src(ctx, src.src);
1100 bool need_swizzle = false;
1101
1102 assert(value);
1103 LLVMTypeRef type = LLVMTypeOf(value);
1104 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1105 ? LLVMGetVectorSize(type)
1106 : 1;
1107
1108 for (unsigned i = 0; i < num_components; ++i) {
1109 assert(src.swizzle[i] < src_components);
1110 if (src.swizzle[i] != i)
1111 need_swizzle = true;
1112 }
1113
1114 if (need_swizzle || num_components != src_components) {
1115 LLVMValueRef masks[] = {
1116 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1117 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1118 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1119 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1120
1121 if (src_components > 1 && num_components == 1) {
1122 value = LLVMBuildExtractElement(ctx->builder, value,
1123 masks[0], "");
1124 } else if (src_components == 1 && num_components > 1) {
1125 LLVMValueRef values[] = {value, value, value, value};
1126 value = ac_build_gather_values(&ctx->ac, values, num_components);
1127 } else {
1128 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1129 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1130 swizzle, "");
1131 }
1132 }
1133 assert(!src.negate);
1134 assert(!src.abs);
1135 return value;
1136 }
1137
1138 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
1139 LLVMIntPredicate pred, LLVMValueRef src0,
1140 LLVMValueRef src1)
1141 {
1142 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1143 return LLVMBuildSelect(ctx->builder, result,
1144 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1145 LLVMConstInt(ctx->i32, 0, false), "");
1146 }
1147
1148 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
1149 LLVMRealPredicate pred, LLVMValueRef src0,
1150 LLVMValueRef src1)
1151 {
1152 LLVMValueRef result;
1153 src0 = to_float(ctx, src0);
1154 src1 = to_float(ctx, src1);
1155 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1156 return LLVMBuildSelect(ctx->builder, result,
1157 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1158 LLVMConstInt(ctx->i32, 0, false), "");
1159 }
1160
1161 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
1162 const char *intrin,
1163 LLVMTypeRef result_type,
1164 LLVMValueRef src0)
1165 {
1166 char name[64];
1167 LLVMValueRef params[] = {
1168 to_float(ctx, src0),
1169 };
1170
1171 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1172 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1173 }
1174
1175 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
1176 const char *intrin,
1177 LLVMTypeRef result_type,
1178 LLVMValueRef src0, LLVMValueRef src1)
1179 {
1180 char name[64];
1181 LLVMValueRef params[] = {
1182 to_float(ctx, src0),
1183 to_float(ctx, src1),
1184 };
1185
1186 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1187 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1188 }
1189
1190 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
1191 const char *intrin,
1192 LLVMTypeRef result_type,
1193 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1194 {
1195 char name[64];
1196 LLVMValueRef params[] = {
1197 to_float(ctx, src0),
1198 to_float(ctx, src1),
1199 to_float(ctx, src2),
1200 };
1201
1202 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1203 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1204 }
1205
1206 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
1207 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1208 {
1209 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1210 ctx->i32zero, "");
1211 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1212 }
1213
1214 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1215 LLVMValueRef src0)
1216 {
1217 LLVMValueRef params[2] = {
1218 src0,
1219
1220 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1221 * add special code to check for x=0. The reason is that
1222 * the LLVM behavior for x=0 is different from what we
1223 * need here.
1224 *
1225 * The hardware already implements the correct behavior.
1226 */
1227 LLVMConstInt(ctx->i32, 1, false),
1228 };
1229 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1230 }
1231
1232 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1233 LLVMValueRef src0)
1234 {
1235 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1236 }
1237
1238 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1239 LLVMValueRef src0)
1240 {
1241 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1242 }
1243
1244 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1245 LLVMIntPredicate pred,
1246 LLVMValueRef src0, LLVMValueRef src1)
1247 {
1248 return LLVMBuildSelect(ctx->builder,
1249 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1250 src0,
1251 src1, "");
1252
1253 }
1254 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1255 LLVMValueRef src0)
1256 {
1257 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1258 LLVMBuildNeg(ctx->builder, src0, ""));
1259 }
1260
1261 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1262 LLVMValueRef src0)
1263 {
1264 LLVMValueRef cmp, val;
1265
1266 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1267 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1268 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1269 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1270 return val;
1271 }
1272
1273 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1274 LLVMValueRef src0)
1275 {
1276 LLVMValueRef cmp, val;
1277
1278 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1279 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1280 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1281 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1282 return val;
1283 }
1284
1285 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1286 LLVMValueRef src0)
1287 {
1288 const char *intr = "llvm.floor.f32";
1289 LLVMValueRef fsrc0 = to_float(ctx, src0);
1290 LLVMValueRef params[] = {
1291 fsrc0,
1292 };
1293 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1294 ctx->f32, params, 1,
1295 AC_FUNC_ATTR_READNONE);
1296 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1297 }
1298
1299 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1300 const char *intrin,
1301 LLVMValueRef src0, LLVMValueRef src1)
1302 {
1303 LLVMTypeRef ret_type;
1304 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1305 LLVMValueRef res;
1306 LLVMValueRef params[] = { src0, src1 };
1307 ret_type = LLVMStructTypeInContext(ctx->context, types,
1308 2, true);
1309
1310 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1311 params, 2, AC_FUNC_ATTR_READNONE);
1312
1313 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1314 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1315 return res;
1316 }
1317
1318 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1319 LLVMValueRef src0)
1320 {
1321 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1322 }
1323
1324 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1325 LLVMValueRef src0)
1326 {
1327 LLVMValueRef result;
1328 LLVMValueRef cond;
1329
1330 src0 = to_float(ctx, src0);
1331 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1332
1333 /* TODO SI/CIK options here */
1334 if (ctx->options->chip_class >= VI) {
1335 LLVMValueRef args[2];
1336 /* Check if the result is a denormal - and flush to 0 if so. */
1337 args[0] = result;
1338 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1339 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1340 }
1341
1342 /* need to convert back up to f32 */
1343 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1344
1345 if (ctx->options->chip_class >= VI)
1346 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1347
1348 return result;
1349 }
1350
1351 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1352 LLVMValueRef src0, LLVMValueRef src1)
1353 {
1354 LLVMValueRef dst64, result;
1355 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1356 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1357
1358 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1359 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1360 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1361 return result;
1362 }
1363
1364 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1365 LLVMValueRef src0, LLVMValueRef src1)
1366 {
1367 LLVMValueRef dst64, result;
1368 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1369 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1370
1371 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1372 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1373 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1374 return result;
1375 }
1376
1377 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1378 bool is_signed,
1379 LLVMValueRef srcs[3])
1380 {
1381 LLVMValueRef result;
1382 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1383
1384 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1385 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1386 return result;
1387 }
1388
1389 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1390 LLVMValueRef src0, LLVMValueRef src1,
1391 LLVMValueRef src2, LLVMValueRef src3)
1392 {
1393 LLVMValueRef bfi_args[3], result;
1394
1395 bfi_args[0] = LLVMBuildShl(ctx->builder,
1396 LLVMBuildSub(ctx->builder,
1397 LLVMBuildShl(ctx->builder,
1398 ctx->i32one,
1399 src3, ""),
1400 ctx->i32one, ""),
1401 src2, "");
1402 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1403 bfi_args[2] = src0;
1404
1405 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1406
1407 /* Calculate:
1408 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1409 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1410 */
1411 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1412 LLVMBuildAnd(ctx->builder, bfi_args[0],
1413 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1414
1415 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1416 return result;
1417 }
1418
1419 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1420 LLVMValueRef src0)
1421 {
1422 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1423 int i;
1424 LLVMValueRef comp[2];
1425
1426 src0 = to_float(ctx, src0);
1427 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1428 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1429 for (i = 0; i < 2; i++) {
1430 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1431 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1432 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1433 }
1434
1435 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1436 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1437
1438 return comp[0];
1439 }
1440
1441 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1442 LLVMValueRef src0)
1443 {
1444 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1445 LLVMValueRef temps[2], result, val;
1446 int i;
1447
1448 for (i = 0; i < 2; i++) {
1449 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1450 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1451 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1452 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1453 }
1454
1455 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1456 ctx->i32zero, "");
1457 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1458 ctx->i32one, "");
1459 return result;
1460 }
1461
1462 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1463 nir_op op,
1464 LLVMValueRef src0)
1465 {
1466 unsigned mask;
1467 int idx;
1468 LLVMValueRef result;
1469 ctx->has_ddxy = true;
1470
1471 if (!ctx->lds && !ctx->has_ds_bpermute)
1472 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1473 LLVMArrayType(ctx->i32, 64),
1474 "ddxy_lds", LOCAL_ADDR_SPACE);
1475
1476 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1477 mask = AC_TID_MASK_LEFT;
1478 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1479 mask = AC_TID_MASK_TOP;
1480 else
1481 mask = AC_TID_MASK_TOP_LEFT;
1482
1483 /* for DDX we want to next X pixel, DDY next Y pixel. */
1484 if (op == nir_op_fddx_fine ||
1485 op == nir_op_fddx_coarse ||
1486 op == nir_op_fddx)
1487 idx = 1;
1488 else
1489 idx = 2;
1490
1491 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1492 mask, idx, ctx->lds,
1493 src0);
1494 return result;
1495 }
1496
1497 /*
1498 * this takes an I,J coordinate pair,
1499 * and works out the X and Y derivatives.
1500 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1501 */
1502 static LLVMValueRef emit_ddxy_interp(
1503 struct nir_to_llvm_context *ctx,
1504 LLVMValueRef interp_ij)
1505 {
1506 LLVMValueRef result[4], a;
1507 unsigned i;
1508
1509 for (i = 0; i < 2; i++) {
1510 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1511 LLVMConstInt(ctx->i32, i, false), "");
1512 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1513 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1514 }
1515 return ac_build_gather_values(&ctx->ac, result, 4);
1516 }
1517
1518 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1519 {
1520 LLVMValueRef src[4], result = NULL;
1521 unsigned num_components = instr->dest.dest.ssa.num_components;
1522 unsigned src_components;
1523 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1524
1525 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1526 switch (instr->op) {
1527 case nir_op_vec2:
1528 case nir_op_vec3:
1529 case nir_op_vec4:
1530 src_components = 1;
1531 break;
1532 case nir_op_pack_half_2x16:
1533 src_components = 2;
1534 break;
1535 case nir_op_unpack_half_2x16:
1536 src_components = 1;
1537 break;
1538 default:
1539 src_components = num_components;
1540 break;
1541 }
1542 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1543 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1544
1545 switch (instr->op) {
1546 case nir_op_fmov:
1547 case nir_op_imov:
1548 result = src[0];
1549 break;
1550 case nir_op_fneg:
1551 src[0] = to_float(ctx, src[0]);
1552 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1553 break;
1554 case nir_op_ineg:
1555 result = LLVMBuildNeg(ctx->builder, src[0], "");
1556 break;
1557 case nir_op_inot:
1558 result = LLVMBuildNot(ctx->builder, src[0], "");
1559 break;
1560 case nir_op_iadd:
1561 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1562 break;
1563 case nir_op_fadd:
1564 src[0] = to_float(ctx, src[0]);
1565 src[1] = to_float(ctx, src[1]);
1566 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1567 break;
1568 case nir_op_fsub:
1569 src[0] = to_float(ctx, src[0]);
1570 src[1] = to_float(ctx, src[1]);
1571 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1572 break;
1573 case nir_op_isub:
1574 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1575 break;
1576 case nir_op_imul:
1577 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1578 break;
1579 case nir_op_imod:
1580 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1581 break;
1582 case nir_op_umod:
1583 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1584 break;
1585 case nir_op_fmod:
1586 src[0] = to_float(ctx, src[0]);
1587 src[1] = to_float(ctx, src[1]);
1588 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1589 result = emit_intrin_1f_param(ctx, "llvm.floor",
1590 to_float_type(ctx, def_type), result);
1591 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1592 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1593 break;
1594 case nir_op_frem:
1595 src[0] = to_float(ctx, src[0]);
1596 src[1] = to_float(ctx, src[1]);
1597 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1598 break;
1599 case nir_op_irem:
1600 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1601 break;
1602 case nir_op_idiv:
1603 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1604 break;
1605 case nir_op_udiv:
1606 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1607 break;
1608 case nir_op_fmul:
1609 src[0] = to_float(ctx, src[0]);
1610 src[1] = to_float(ctx, src[1]);
1611 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1612 break;
1613 case nir_op_fdiv:
1614 src[0] = to_float(ctx, src[0]);
1615 src[1] = to_float(ctx, src[1]);
1616 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1617 break;
1618 case nir_op_frcp:
1619 src[0] = to_float(ctx, src[0]);
1620 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1621 break;
1622 case nir_op_iand:
1623 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1624 break;
1625 case nir_op_ior:
1626 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1627 break;
1628 case nir_op_ixor:
1629 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1630 break;
1631 case nir_op_ishl:
1632 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1633 break;
1634 case nir_op_ishr:
1635 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1636 break;
1637 case nir_op_ushr:
1638 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1639 break;
1640 case nir_op_ilt:
1641 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1642 break;
1643 case nir_op_ine:
1644 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1645 break;
1646 case nir_op_ieq:
1647 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1648 break;
1649 case nir_op_ige:
1650 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1651 break;
1652 case nir_op_ult:
1653 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1654 break;
1655 case nir_op_uge:
1656 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1657 break;
1658 case nir_op_feq:
1659 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1660 break;
1661 case nir_op_fne:
1662 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1663 break;
1664 case nir_op_flt:
1665 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1666 break;
1667 case nir_op_fge:
1668 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1669 break;
1670 case nir_op_fabs:
1671 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1672 to_float_type(ctx, def_type), src[0]);
1673 break;
1674 case nir_op_iabs:
1675 result = emit_iabs(ctx, src[0]);
1676 break;
1677 case nir_op_imax:
1678 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1679 break;
1680 case nir_op_imin:
1681 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1682 break;
1683 case nir_op_umax:
1684 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1685 break;
1686 case nir_op_umin:
1687 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1688 break;
1689 case nir_op_isign:
1690 result = emit_isign(ctx, src[0]);
1691 break;
1692 case nir_op_fsign:
1693 src[0] = to_float(ctx, src[0]);
1694 result = emit_fsign(ctx, src[0]);
1695 break;
1696 case nir_op_ffloor:
1697 result = emit_intrin_1f_param(ctx, "llvm.floor",
1698 to_float_type(ctx, def_type), src[0]);
1699 break;
1700 case nir_op_ftrunc:
1701 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1702 to_float_type(ctx, def_type), src[0]);
1703 break;
1704 case nir_op_fceil:
1705 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1706 to_float_type(ctx, def_type), src[0]);
1707 break;
1708 case nir_op_fround_even:
1709 result = emit_intrin_1f_param(ctx, "llvm.rint",
1710 to_float_type(ctx, def_type),src[0]);
1711 break;
1712 case nir_op_ffract:
1713 result = emit_ffract(ctx, src[0]);
1714 break;
1715 case nir_op_fsin:
1716 result = emit_intrin_1f_param(ctx, "llvm.sin",
1717 to_float_type(ctx, def_type), src[0]);
1718 break;
1719 case nir_op_fcos:
1720 result = emit_intrin_1f_param(ctx, "llvm.cos",
1721 to_float_type(ctx, def_type), src[0]);
1722 break;
1723 case nir_op_fsqrt:
1724 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1725 to_float_type(ctx, def_type), src[0]);
1726 break;
1727 case nir_op_fexp2:
1728 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1729 to_float_type(ctx, def_type), src[0]);
1730 break;
1731 case nir_op_flog2:
1732 result = emit_intrin_1f_param(ctx, "llvm.log2",
1733 to_float_type(ctx, def_type), src[0]);
1734 break;
1735 case nir_op_frsq:
1736 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1737 to_float_type(ctx, def_type), src[0]);
1738 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1739 break;
1740 case nir_op_fpow:
1741 result = emit_intrin_2f_param(ctx, "llvm.pow",
1742 to_float_type(ctx, def_type), src[0], src[1]);
1743 break;
1744 case nir_op_fmax:
1745 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1746 to_float_type(ctx, def_type), src[0], src[1]);
1747 if (instr->dest.dest.ssa.bit_size == 32)
1748 result = emit_intrin_1f_param(ctx, "llvm.canonicalize",
1749 to_float_type(ctx, def_type),
1750 result);
1751 break;
1752 case nir_op_fmin:
1753 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1754 to_float_type(ctx, def_type), src[0], src[1]);
1755 if (instr->dest.dest.ssa.bit_size == 32)
1756 result = emit_intrin_1f_param(ctx, "llvm.canonicalize",
1757 to_float_type(ctx, def_type),
1758 result);
1759 break;
1760 case nir_op_ffma:
1761 result = emit_intrin_3f_param(ctx, "llvm.fma",
1762 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1763 break;
1764 case nir_op_ibitfield_extract:
1765 result = emit_bitfield_extract(ctx, true, src);
1766 break;
1767 case nir_op_ubitfield_extract:
1768 result = emit_bitfield_extract(ctx, false, src);
1769 break;
1770 case nir_op_bitfield_insert:
1771 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1772 break;
1773 case nir_op_bitfield_reverse:
1774 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1775 break;
1776 case nir_op_bit_count:
1777 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1778 break;
1779 case nir_op_vec2:
1780 case nir_op_vec3:
1781 case nir_op_vec4:
1782 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1783 src[i] = to_integer(ctx, src[i]);
1784 result = ac_build_gather_values(&ctx->ac, src, num_components);
1785 break;
1786 case nir_op_f2i32:
1787 case nir_op_f2i64:
1788 src[0] = to_float(ctx, src[0]);
1789 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1790 break;
1791 case nir_op_f2u32:
1792 case nir_op_f2u64:
1793 src[0] = to_float(ctx, src[0]);
1794 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1795 break;
1796 case nir_op_i2f32:
1797 case nir_op_i2f64:
1798 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1799 break;
1800 case nir_op_u2f32:
1801 case nir_op_u2f64:
1802 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1803 break;
1804 case nir_op_f2f64:
1805 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1806 break;
1807 case nir_op_f2f32:
1808 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1809 break;
1810 case nir_op_u2u32:
1811 case nir_op_u2u64:
1812 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1813 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1814 else
1815 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1816 break;
1817 case nir_op_i2i32:
1818 case nir_op_i2i64:
1819 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1820 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1821 else
1822 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1823 break;
1824 case nir_op_bcsel:
1825 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1826 break;
1827 case nir_op_find_lsb:
1828 result = emit_find_lsb(ctx, src[0]);
1829 break;
1830 case nir_op_ufind_msb:
1831 result = emit_ufind_msb(ctx, src[0]);
1832 break;
1833 case nir_op_ifind_msb:
1834 result = emit_ifind_msb(ctx, src[0]);
1835 break;
1836 case nir_op_uadd_carry:
1837 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1838 break;
1839 case nir_op_usub_borrow:
1840 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1841 break;
1842 case nir_op_b2f:
1843 result = emit_b2f(ctx, src[0]);
1844 break;
1845 case nir_op_fquantize2f16:
1846 result = emit_f2f16(ctx, src[0]);
1847 break;
1848 case nir_op_umul_high:
1849 result = emit_umul_high(ctx, src[0], src[1]);
1850 break;
1851 case nir_op_imul_high:
1852 result = emit_imul_high(ctx, src[0], src[1]);
1853 break;
1854 case nir_op_pack_half_2x16:
1855 result = emit_pack_half_2x16(ctx, src[0]);
1856 break;
1857 case nir_op_unpack_half_2x16:
1858 result = emit_unpack_half_2x16(ctx, src[0]);
1859 break;
1860 case nir_op_fddx:
1861 case nir_op_fddy:
1862 case nir_op_fddx_fine:
1863 case nir_op_fddy_fine:
1864 case nir_op_fddx_coarse:
1865 case nir_op_fddy_coarse:
1866 result = emit_ddxy(ctx, instr->op, src[0]);
1867 break;
1868 default:
1869 fprintf(stderr, "Unknown NIR alu instr: ");
1870 nir_print_instr(&instr->instr, stderr);
1871 fprintf(stderr, "\n");
1872 abort();
1873 }
1874
1875 if (result) {
1876 assert(instr->dest.dest.is_ssa);
1877 result = to_integer(ctx, result);
1878 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1879 result);
1880 }
1881 }
1882
1883 static void visit_load_const(struct nir_to_llvm_context *ctx,
1884 nir_load_const_instr *instr)
1885 {
1886 LLVMValueRef values[4], value = NULL;
1887 LLVMTypeRef element_type =
1888 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1889
1890 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1891 switch (instr->def.bit_size) {
1892 case 32:
1893 values[i] = LLVMConstInt(element_type,
1894 instr->value.u32[i], false);
1895 break;
1896 case 64:
1897 values[i] = LLVMConstInt(element_type,
1898 instr->value.u64[i], false);
1899 break;
1900 default:
1901 fprintf(stderr,
1902 "unsupported nir load_const bit_size: %d\n",
1903 instr->def.bit_size);
1904 abort();
1905 }
1906 }
1907 if (instr->def.num_components > 1) {
1908 value = LLVMConstVector(values, instr->def.num_components);
1909 } else
1910 value = values[0];
1911
1912 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1913 }
1914
1915 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1916 LLVMTypeRef type)
1917 {
1918 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1919 return LLVMBuildBitCast(ctx->builder, ptr,
1920 LLVMPointerType(type, addr_space), "");
1921 }
1922
1923 static LLVMValueRef
1924 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1925 {
1926 LLVMValueRef size =
1927 LLVMBuildExtractElement(ctx->builder, descriptor,
1928 LLVMConstInt(ctx->i32, 2, false), "");
1929
1930 /* VI only */
1931 if (ctx->options->chip_class >= VI && in_elements) {
1932 /* On VI, the descriptor contains the size in bytes,
1933 * but TXQ must return the size in elements.
1934 * The stride is always non-zero for resources using TXQ.
1935 */
1936 LLVMValueRef stride =
1937 LLVMBuildExtractElement(ctx->builder, descriptor,
1938 LLVMConstInt(ctx->i32, 1, false), "");
1939 stride = LLVMBuildLShr(ctx->builder, stride,
1940 LLVMConstInt(ctx->i32, 16, false), "");
1941 stride = LLVMBuildAnd(ctx->builder, stride,
1942 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1943
1944 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1945 }
1946 return size;
1947 }
1948
1949 /**
1950 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1951 * intrinsic names).
1952 */
1953 static void build_int_type_name(
1954 LLVMTypeRef type,
1955 char *buf, unsigned bufsize)
1956 {
1957 assert(bufsize >= 6);
1958
1959 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1960 snprintf(buf, bufsize, "v%ui32",
1961 LLVMGetVectorSize(type));
1962 else
1963 strcpy(buf, "i32");
1964 }
1965
1966 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1967 struct ac_image_args *args,
1968 nir_tex_instr *instr)
1969 {
1970 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1971 LLVMValueRef coord = args->addr;
1972 LLVMValueRef half_texel[2];
1973 LLVMValueRef compare_cube_wa;
1974 LLVMValueRef result;
1975 int c;
1976 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1977
1978 //TODO Rect
1979 {
1980 struct ac_image_args txq_args = { 0 };
1981
1982 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1983 txq_args.opcode = ac_image_get_resinfo;
1984 txq_args.dmask = 0xf;
1985 txq_args.addr = ctx->i32zero;
1986 txq_args.resource = args->resource;
1987 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1988
1989 for (c = 0; c < 2; c++) {
1990 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1991 LLVMConstInt(ctx->i32, c, false), "");
1992 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1993 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1994 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1995 LLVMConstReal(ctx->f32, -0.5), "");
1996 }
1997 }
1998
1999 LLVMValueRef orig_coords = args->addr;
2000
2001 for (c = 0; c < 2; c++) {
2002 LLVMValueRef tmp;
2003 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2004 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2005 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2006 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2007 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2008 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2009 }
2010
2011
2012 /*
2013 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2014 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2015 * workaround by sampling using a scaled type and converting.
2016 * This is taken from amdgpu-pro shaders.
2017 */
2018 /* NOTE this produces some ugly code compared to amdgpu-pro,
2019 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2020 * and then reads them back. -pro generates two selects,
2021 * one s_cmp for the descriptor rewriting
2022 * one v_cmp for the coordinate and result changes.
2023 */
2024 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2025 LLVMValueRef tmp, tmp2;
2026
2027 /* workaround 8/8/8/8 uint/sint cube gather bug */
2028 /* first detect it then change to a scaled read and f2i */
2029 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
2030 tmp2 = tmp;
2031
2032 /* extract the DATA_FORMAT */
2033 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
2034 LLVMConstInt(ctx->i32, 6, false), false);
2035
2036 /* is the DATA_FORMAT == 8_8_8_8 */
2037 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2038
2039 if (stype == GLSL_TYPE_UINT)
2040 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2041 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2042 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2043 else
2044 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2045 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2046 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2047
2048 /* replace the NUM FORMAT in the descriptor */
2049 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2050 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2051
2052 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
2053
2054 /* don't modify the coordinates for this case */
2055 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2056 }
2057 args->addr = coord;
2058 result = ac_build_image_opcode(&ctx->ac, args);
2059
2060 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2061 LLVMValueRef tmp, tmp2;
2062
2063 /* if the cube workaround is in place, f2i the result. */
2064 for (c = 0; c < 4; c++) {
2065 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2066 if (stype == GLSL_TYPE_UINT)
2067 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2068 else
2069 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2070 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2071 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2072 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2073 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2074 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2075 }
2076 }
2077 return result;
2078 }
2079
2080 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
2081 nir_tex_instr *instr,
2082 bool lod_is_zero,
2083 struct ac_image_args *args)
2084 {
2085 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2086 return ac_build_buffer_load_format(&ctx->ac,
2087 args->resource,
2088 args->addr,
2089 LLVMConstInt(ctx->i32, 0, false),
2090 true);
2091 }
2092
2093 args->opcode = ac_image_sample;
2094 args->compare = instr->is_shadow;
2095
2096 switch (instr->op) {
2097 case nir_texop_txf:
2098 case nir_texop_txf_ms:
2099 case nir_texop_samples_identical:
2100 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2101 args->compare = false;
2102 args->offset = false;
2103 break;
2104 case nir_texop_txb:
2105 args->bias = true;
2106 break;
2107 case nir_texop_txl:
2108 if (lod_is_zero)
2109 args->level_zero = true;
2110 else
2111 args->lod = true;
2112 break;
2113 case nir_texop_txs:
2114 case nir_texop_query_levels:
2115 args->opcode = ac_image_get_resinfo;
2116 break;
2117 case nir_texop_tex:
2118 if (ctx->stage != MESA_SHADER_FRAGMENT)
2119 args->level_zero = true;
2120 break;
2121 case nir_texop_txd:
2122 args->deriv = true;
2123 break;
2124 case nir_texop_tg4:
2125 args->opcode = ac_image_gather4;
2126 args->level_zero = true;
2127 break;
2128 case nir_texop_lod:
2129 args->opcode = ac_image_get_lod;
2130 args->compare = false;
2131 args->offset = false;
2132 break;
2133 default:
2134 break;
2135 }
2136
2137 if (instr->op == nir_texop_tg4) {
2138 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2139 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2140 return radv_lower_gather4_integer(ctx, args, instr);
2141 }
2142 }
2143 return ac_build_image_opcode(&ctx->ac, args);
2144 }
2145
2146 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2147 nir_intrinsic_instr *instr)
2148 {
2149 LLVMValueRef index = get_src(ctx, instr->src[0]);
2150 unsigned desc_set = nir_intrinsic_desc_set(instr);
2151 unsigned binding = nir_intrinsic_binding(instr);
2152 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2153 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2154 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2155 unsigned base_offset = layout->binding[binding].offset;
2156 LLVMValueRef offset, stride;
2157
2158 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2159 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2160 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2161 layout->binding[binding].dynamic_offset_offset;
2162 desc_ptr = ctx->push_constants;
2163 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2164 stride = LLVMConstInt(ctx->i32, 16, false);
2165 } else
2166 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2167
2168 offset = LLVMConstInt(ctx->i32, base_offset, false);
2169 index = LLVMBuildMul(ctx->builder, index, stride, "");
2170 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2171
2172 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2173 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2174 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2175
2176 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2177 }
2178
2179 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2180 nir_intrinsic_instr *instr)
2181 {
2182 LLVMValueRef ptr, addr;
2183
2184 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2185 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2186
2187 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2188 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2189
2190 return LLVMBuildLoad(ctx->builder, ptr, "");
2191 }
2192
2193 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2194 nir_intrinsic_instr *instr)
2195 {
2196 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2197
2198 return get_buffer_size(ctx, desc, false);
2199 }
2200 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2201 nir_intrinsic_instr *instr)
2202 {
2203 const char *store_name;
2204 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2205 LLVMTypeRef data_type = ctx->f32;
2206 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2207 int components_32bit = elem_size_mult * instr->num_components;
2208 unsigned writemask = nir_intrinsic_write_mask(instr);
2209 LLVMValueRef base_data, base_offset;
2210 LLVMValueRef params[6];
2211
2212 if (ctx->stage == MESA_SHADER_FRAGMENT)
2213 ctx->shader_info->fs.writes_memory = true;
2214
2215 params[1] = get_src(ctx, instr->src[1]);
2216 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2217 params[4] = ctx->i1false; /* glc */
2218 params[5] = ctx->i1false; /* slc */
2219
2220 if (components_32bit > 1)
2221 data_type = LLVMVectorType(ctx->f32, components_32bit);
2222
2223 base_data = to_float(ctx, src_data);
2224 base_data = trim_vector(ctx, base_data, instr->num_components);
2225 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2226 data_type, "");
2227 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2228 while (writemask) {
2229 int start, count;
2230 LLVMValueRef data;
2231 LLVMValueRef offset;
2232 LLVMValueRef tmp;
2233 u_bit_scan_consecutive_range(&writemask, &start, &count);
2234
2235 /* Due to an LLVM limitation, split 3-element writes
2236 * into a 2-element and a 1-element write. */
2237 if (count == 3) {
2238 writemask |= 1 << (start + 2);
2239 count = 2;
2240 }
2241
2242 start *= elem_size_mult;
2243 count *= elem_size_mult;
2244
2245 if (count > 4) {
2246 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2247 count = 4;
2248 }
2249
2250 if (count == 4) {
2251 store_name = "llvm.amdgcn.buffer.store.v4f32";
2252 data = base_data;
2253 } else if (count == 2) {
2254 tmp = LLVMBuildExtractElement(ctx->builder,
2255 base_data, LLVMConstInt(ctx->i32, start, false), "");
2256 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2257 ctx->i32zero, "");
2258
2259 tmp = LLVMBuildExtractElement(ctx->builder,
2260 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2261 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2262 ctx->i32one, "");
2263 store_name = "llvm.amdgcn.buffer.store.v2f32";
2264
2265 } else {
2266 assert(count == 1);
2267 if (get_llvm_num_components(base_data) > 1)
2268 data = LLVMBuildExtractElement(ctx->builder, base_data,
2269 LLVMConstInt(ctx->i32, start, false), "");
2270 else
2271 data = base_data;
2272 store_name = "llvm.amdgcn.buffer.store.f32";
2273 }
2274
2275 offset = base_offset;
2276 if (start != 0) {
2277 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2278 }
2279 params[0] = data;
2280 params[3] = offset;
2281 ac_build_intrinsic(&ctx->ac, store_name,
2282 ctx->voidt, params, 6, 0);
2283 }
2284 }
2285
2286 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2287 nir_intrinsic_instr *instr)
2288 {
2289 const char *name;
2290 LLVMValueRef params[6];
2291 int arg_count = 0;
2292 if (ctx->stage == MESA_SHADER_FRAGMENT)
2293 ctx->shader_info->fs.writes_memory = true;
2294
2295 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2296 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2297 }
2298 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2299 params[arg_count++] = get_src(ctx, instr->src[0]);
2300 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2301 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2302 params[arg_count++] = ctx->i1false; /* slc */
2303
2304 switch (instr->intrinsic) {
2305 case nir_intrinsic_ssbo_atomic_add:
2306 name = "llvm.amdgcn.buffer.atomic.add";
2307 break;
2308 case nir_intrinsic_ssbo_atomic_imin:
2309 name = "llvm.amdgcn.buffer.atomic.smin";
2310 break;
2311 case nir_intrinsic_ssbo_atomic_umin:
2312 name = "llvm.amdgcn.buffer.atomic.umin";
2313 break;
2314 case nir_intrinsic_ssbo_atomic_imax:
2315 name = "llvm.amdgcn.buffer.atomic.smax";
2316 break;
2317 case nir_intrinsic_ssbo_atomic_umax:
2318 name = "llvm.amdgcn.buffer.atomic.umax";
2319 break;
2320 case nir_intrinsic_ssbo_atomic_and:
2321 name = "llvm.amdgcn.buffer.atomic.and";
2322 break;
2323 case nir_intrinsic_ssbo_atomic_or:
2324 name = "llvm.amdgcn.buffer.atomic.or";
2325 break;
2326 case nir_intrinsic_ssbo_atomic_xor:
2327 name = "llvm.amdgcn.buffer.atomic.xor";
2328 break;
2329 case nir_intrinsic_ssbo_atomic_exchange:
2330 name = "llvm.amdgcn.buffer.atomic.swap";
2331 break;
2332 case nir_intrinsic_ssbo_atomic_comp_swap:
2333 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2334 break;
2335 default:
2336 abort();
2337 }
2338
2339 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2340 }
2341
2342 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2343 nir_intrinsic_instr *instr)
2344 {
2345 LLVMValueRef results[2];
2346 int load_components;
2347 int num_components = instr->num_components;
2348 if (instr->dest.ssa.bit_size == 64)
2349 num_components *= 2;
2350
2351 for (int i = 0; i < num_components; i += load_components) {
2352 load_components = MIN2(num_components - i, 4);
2353 const char *load_name;
2354 LLVMTypeRef data_type = ctx->f32;
2355 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2356 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2357
2358 if (load_components == 3)
2359 data_type = LLVMVectorType(ctx->f32, 4);
2360 else if (load_components > 1)
2361 data_type = LLVMVectorType(ctx->f32, load_components);
2362
2363 if (load_components >= 3)
2364 load_name = "llvm.amdgcn.buffer.load.v4f32";
2365 else if (load_components == 2)
2366 load_name = "llvm.amdgcn.buffer.load.v2f32";
2367 else if (load_components == 1)
2368 load_name = "llvm.amdgcn.buffer.load.f32";
2369 else
2370 unreachable("unhandled number of components");
2371
2372 LLVMValueRef params[] = {
2373 get_src(ctx, instr->src[0]),
2374 LLVMConstInt(ctx->i32, 0, false),
2375 offset,
2376 ctx->i1false,
2377 ctx->i1false,
2378 };
2379
2380 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2381
2382 }
2383
2384 LLVMValueRef ret = results[0];
2385 if (num_components > 4 || num_components == 3) {
2386 LLVMValueRef masks[] = {
2387 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2388 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2389 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2390 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2391 };
2392
2393 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2394 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2395 results[num_components > 4 ? 1 : 0], swizzle, "");
2396 }
2397
2398 return LLVMBuildBitCast(ctx->builder, ret,
2399 get_def_type(ctx, &instr->dest.ssa), "");
2400 }
2401
2402 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2403 nir_intrinsic_instr *instr)
2404 {
2405 LLVMValueRef results[8], ret;
2406 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2407 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2408 int num_components = instr->num_components;
2409
2410 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2411
2412 if (instr->dest.ssa.bit_size == 64)
2413 num_components *= 2;
2414
2415 for (unsigned i = 0; i < num_components; ++i) {
2416 LLVMValueRef params[] = {
2417 rsrc,
2418 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2419 offset, "")
2420 };
2421 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2422 params, 2,
2423 AC_FUNC_ATTR_READNONE |
2424 AC_FUNC_ATTR_LEGACY);
2425 }
2426
2427
2428 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2429 return LLVMBuildBitCast(ctx->builder, ret,
2430 get_def_type(ctx, &instr->dest.ssa), "");
2431 }
2432
2433 static void
2434 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2435 bool vs_in, unsigned *vertex_index_out,
2436 LLVMValueRef *vertex_index_ref,
2437 unsigned *const_out, LLVMValueRef *indir_out)
2438 {
2439 unsigned const_offset = 0;
2440 nir_deref *tail = &deref->deref;
2441 LLVMValueRef offset = NULL;
2442
2443 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2444 tail = tail->child;
2445 nir_deref_array *deref_array = nir_deref_as_array(tail);
2446 if (vertex_index_out)
2447 *vertex_index_out = deref_array->base_offset;
2448
2449 if (vertex_index_ref) {
2450 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2451 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2452 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2453 }
2454 *vertex_index_ref = vtx;
2455 }
2456 }
2457
2458 if (deref->var->data.compact) {
2459 assert(tail->child->deref_type == nir_deref_type_array);
2460 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2461 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2462 /* We always lower indirect dereferences for "compact" array vars. */
2463 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2464
2465 const_offset = deref_array->base_offset;
2466 goto out;
2467 }
2468
2469 while (tail->child != NULL) {
2470 const struct glsl_type *parent_type = tail->type;
2471 tail = tail->child;
2472
2473 if (tail->deref_type == nir_deref_type_array) {
2474 nir_deref_array *deref_array = nir_deref_as_array(tail);
2475 LLVMValueRef index, stride, local_offset;
2476 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2477
2478 const_offset += size * deref_array->base_offset;
2479 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2480 continue;
2481
2482 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2483 index = get_src(ctx, deref_array->indirect);
2484 stride = LLVMConstInt(ctx->i32, size, 0);
2485 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2486
2487 if (offset)
2488 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2489 else
2490 offset = local_offset;
2491 } else if (tail->deref_type == nir_deref_type_struct) {
2492 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2493
2494 for (unsigned i = 0; i < deref_struct->index; i++) {
2495 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2496 const_offset += glsl_count_attribute_slots(ft, vs_in);
2497 }
2498 } else
2499 unreachable("unsupported deref type");
2500
2501 }
2502 out:
2503 if (const_offset && offset)
2504 offset = LLVMBuildAdd(ctx->builder, offset,
2505 LLVMConstInt(ctx->i32, const_offset, 0),
2506 "");
2507
2508 *const_out = const_offset;
2509 *indir_out = offset;
2510 }
2511
2512 static LLVMValueRef
2513 lds_load(struct nir_to_llvm_context *ctx,
2514 LLVMValueRef dw_addr)
2515 {
2516 LLVMValueRef value;
2517 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2518 return value;
2519 }
2520
2521 static void
2522 lds_store(struct nir_to_llvm_context *ctx,
2523 LLVMValueRef dw_addr, LLVMValueRef value)
2524 {
2525 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2526 ac_build_indexed_store(&ctx->ac, ctx->lds,
2527 dw_addr, value);
2528 }
2529
2530 /* The offchip buffer layout for TCS->TES is
2531 *
2532 * - attribute 0 of patch 0 vertex 0
2533 * - attribute 0 of patch 0 vertex 1
2534 * - attribute 0 of patch 0 vertex 2
2535 * ...
2536 * - attribute 0 of patch 1 vertex 0
2537 * - attribute 0 of patch 1 vertex 1
2538 * ...
2539 * - attribute 1 of patch 0 vertex 0
2540 * - attribute 1 of patch 0 vertex 1
2541 * ...
2542 * - per patch attribute 0 of patch 0
2543 * - per patch attribute 0 of patch 1
2544 * ...
2545 *
2546 * Note that every attribute has 4 components.
2547 */
2548 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2549 LLVMValueRef vertex_index,
2550 LLVMValueRef param_index)
2551 {
2552 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2553 LLVMValueRef param_stride, constant16;
2554 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2555
2556 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2557 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2558 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2559 num_patches, "");
2560
2561 constant16 = LLVMConstInt(ctx->i32, 16, false);
2562 if (vertex_index) {
2563 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2564 vertices_per_patch, "");
2565
2566 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2567 vertex_index, "");
2568
2569 param_stride = total_vertices;
2570 } else {
2571 base_addr = rel_patch_id;
2572 param_stride = num_patches;
2573 }
2574
2575 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2576 LLVMBuildMul(ctx->builder, param_index,
2577 param_stride, ""), "");
2578
2579 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2580
2581 if (!vertex_index) {
2582 LLVMValueRef patch_data_offset =
2583 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2584
2585 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2586 patch_data_offset, "");
2587 }
2588 return base_addr;
2589 }
2590
2591 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2592 unsigned param,
2593 unsigned const_index,
2594 bool is_compact,
2595 LLVMValueRef vertex_index,
2596 LLVMValueRef indir_index)
2597 {
2598 LLVMValueRef param_index;
2599
2600 if (indir_index)
2601 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2602 indir_index, "");
2603 else {
2604 if (const_index && !is_compact)
2605 param += const_index;
2606 param_index = LLVMConstInt(ctx->i32, param, false);
2607 }
2608 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2609 }
2610
2611 static void
2612 mark_tess_output(struct nir_to_llvm_context *ctx,
2613 bool is_patch, uint32_t param)
2614
2615 {
2616 if (is_patch) {
2617 ctx->tess_patch_outputs_written |= (1ull << param);
2618 } else
2619 ctx->tess_outputs_written |= (1ull << param);
2620 }
2621
2622 static LLVMValueRef
2623 get_dw_address(struct nir_to_llvm_context *ctx,
2624 LLVMValueRef dw_addr,
2625 unsigned param,
2626 unsigned const_index,
2627 bool compact_const_index,
2628 LLVMValueRef vertex_index,
2629 LLVMValueRef stride,
2630 LLVMValueRef indir_index)
2631
2632 {
2633
2634 if (vertex_index) {
2635 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2636 LLVMBuildMul(ctx->builder,
2637 vertex_index,
2638 stride, ""), "");
2639 }
2640
2641 if (indir_index)
2642 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2643 LLVMBuildMul(ctx->builder, indir_index,
2644 LLVMConstInt(ctx->i32, 4, false), ""), "");
2645 else if (const_index && !compact_const_index)
2646 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2647 LLVMConstInt(ctx->i32, const_index, false), "");
2648
2649 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2650 LLVMConstInt(ctx->i32, param * 4, false), "");
2651
2652 if (const_index && compact_const_index)
2653 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2654 LLVMConstInt(ctx->i32, const_index, false), "");
2655 return dw_addr;
2656 }
2657
2658 static LLVMValueRef
2659 load_tcs_input(struct nir_to_llvm_context *ctx,
2660 nir_intrinsic_instr *instr)
2661 {
2662 LLVMValueRef dw_addr, stride;
2663 unsigned const_index;
2664 LLVMValueRef vertex_index;
2665 LLVMValueRef indir_index;
2666 unsigned param;
2667 LLVMValueRef value[4], result;
2668 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2669 const bool is_compact = instr->variables[0]->var->data.compact;
2670 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2671 radv_get_deref_offset(ctx, instr->variables[0],
2672 false, NULL, per_vertex ? &vertex_index : NULL,
2673 &const_index, &indir_index);
2674
2675 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2676 dw_addr = get_tcs_in_current_patch_offset(ctx);
2677 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2678 indir_index);
2679
2680 for (unsigned i = 0; i < instr->num_components; i++) {
2681 value[i] = lds_load(ctx, dw_addr);
2682 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2683 ctx->i32one, "");
2684 }
2685 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2686 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2687 return result;
2688 }
2689
2690 static LLVMValueRef
2691 load_tcs_output(struct nir_to_llvm_context *ctx,
2692 nir_intrinsic_instr *instr)
2693 {
2694 LLVMValueRef dw_addr, stride;
2695 LLVMValueRef value[4], result;
2696 LLVMValueRef vertex_index = NULL;
2697 LLVMValueRef indir_index = NULL;
2698 unsigned const_index = 0;
2699 unsigned param;
2700 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2701 const bool is_compact = instr->variables[0]->var->data.compact;
2702 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2703 radv_get_deref_offset(ctx, instr->variables[0],
2704 false, NULL, per_vertex ? &vertex_index : NULL,
2705 &const_index, &indir_index);
2706
2707 if (!instr->variables[0]->var->data.patch) {
2708 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2709 dw_addr = get_tcs_out_current_patch_offset(ctx);
2710 } else {
2711 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2712 }
2713
2714 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2715 indir_index);
2716
2717 for (unsigned i = 0; i < instr->num_components; i++) {
2718 value[i] = lds_load(ctx, dw_addr);
2719 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2720 ctx->i32one, "");
2721 }
2722 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2723 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2724 return result;
2725 }
2726
2727 static void
2728 store_tcs_output(struct nir_to_llvm_context *ctx,
2729 nir_intrinsic_instr *instr,
2730 LLVMValueRef src,
2731 unsigned writemask)
2732 {
2733 LLVMValueRef stride, dw_addr;
2734 LLVMValueRef buf_addr = NULL;
2735 LLVMValueRef vertex_index = NULL;
2736 LLVMValueRef indir_index = NULL;
2737 unsigned const_index = 0;
2738 unsigned param;
2739 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2740 const bool is_compact = instr->variables[0]->var->data.compact;
2741
2742 radv_get_deref_offset(ctx, instr->variables[0],
2743 false, NULL, per_vertex ? &vertex_index : NULL,
2744 &const_index, &indir_index);
2745
2746 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2747 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2748 is_compact && const_index > 3) {
2749 const_index -= 3;
2750 param++;
2751 }
2752
2753 if (!instr->variables[0]->var->data.patch) {
2754 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2755 dw_addr = get_tcs_out_current_patch_offset(ctx);
2756 } else {
2757 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2758 }
2759
2760 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2761
2762 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2763 indir_index);
2764 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2765 vertex_index, indir_index);
2766
2767 unsigned base = is_compact ? const_index : 0;
2768 for (unsigned chan = 0; chan < 8; chan++) {
2769 bool is_tess_factor = false;
2770 if (!(writemask & (1 << chan)))
2771 continue;
2772 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2773
2774 lds_store(ctx, dw_addr, value);
2775
2776 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2777 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2778 is_tess_factor = true;
2779
2780 if (!is_tess_factor && writemask != 0xF)
2781 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2782 buf_addr, ctx->oc_lds,
2783 4 * (base + chan), 1, 0, true, false);
2784
2785 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2786 ctx->i32one, "");
2787 }
2788
2789 if (writemask == 0xF) {
2790 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2791 buf_addr, ctx->oc_lds,
2792 (base * 4), 1, 0, true, false);
2793 }
2794 }
2795
2796 static LLVMValueRef
2797 load_tes_input(struct nir_to_llvm_context *ctx,
2798 nir_intrinsic_instr *instr)
2799 {
2800 LLVMValueRef buf_addr;
2801 LLVMValueRef result;
2802 LLVMValueRef vertex_index = NULL;
2803 LLVMValueRef indir_index = NULL;
2804 unsigned const_index = 0;
2805 unsigned param;
2806 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2807 const bool is_compact = instr->variables[0]->var->data.compact;
2808
2809 radv_get_deref_offset(ctx, instr->variables[0],
2810 false, NULL, per_vertex ? &vertex_index : NULL,
2811 &const_index, &indir_index);
2812 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2813 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2814 is_compact && const_index > 3) {
2815 const_index -= 3;
2816 param++;
2817 }
2818 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2819 is_compact, vertex_index, indir_index);
2820
2821 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2822 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2823 result = trim_vector(ctx, result, instr->num_components);
2824 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2825 return result;
2826 }
2827
2828 static LLVMValueRef
2829 load_gs_input(struct nir_to_llvm_context *ctx,
2830 nir_intrinsic_instr *instr)
2831 {
2832 LLVMValueRef indir_index, vtx_offset;
2833 unsigned const_index;
2834 LLVMValueRef args[9];
2835 unsigned param, vtx_offset_param;
2836 LLVMValueRef value[4], result;
2837 unsigned vertex_index;
2838 radv_get_deref_offset(ctx, instr->variables[0],
2839 false, &vertex_index, NULL,
2840 &const_index, &indir_index);
2841 vtx_offset_param = vertex_index;
2842 assert(vtx_offset_param < 6);
2843 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2844 LLVMConstInt(ctx->i32, 4, false), "");
2845
2846 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2847 for (unsigned i = 0; i < instr->num_components; i++) {
2848
2849 args[0] = ctx->esgs_ring;
2850 args[1] = vtx_offset;
2851 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2852 args[3] = ctx->i32zero;
2853 args[4] = ctx->i32one; /* OFFEN */
2854 args[5] = ctx->i32zero; /* IDXEN */
2855 args[6] = ctx->i32one; /* GLC */
2856 args[7] = ctx->i32zero; /* SLC */
2857 args[8] = ctx->i32zero; /* TFE */
2858
2859 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2860 ctx->i32, args, 9,
2861 AC_FUNC_ATTR_READONLY |
2862 AC_FUNC_ATTR_LEGACY);
2863 }
2864 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2865
2866 return result;
2867 }
2868
2869 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2870 nir_intrinsic_instr *instr)
2871 {
2872 LLVMValueRef values[8];
2873 int idx = instr->variables[0]->var->data.driver_location;
2874 int ve = instr->dest.ssa.num_components;
2875 LLVMValueRef indir_index;
2876 LLVMValueRef ret;
2877 unsigned const_index;
2878 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2879 instr->variables[0]->var->data.mode == nir_var_shader_in;
2880 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2881 &const_index, &indir_index);
2882
2883 if (instr->dest.ssa.bit_size == 64)
2884 ve *= 2;
2885
2886 switch (instr->variables[0]->var->data.mode) {
2887 case nir_var_shader_in:
2888 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2889 return load_tcs_input(ctx, instr);
2890 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2891 return load_tes_input(ctx, instr);
2892 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2893 return load_gs_input(ctx, instr);
2894 }
2895 for (unsigned chan = 0; chan < ve; chan++) {
2896 if (indir_index) {
2897 unsigned count = glsl_count_attribute_slots(
2898 instr->variables[0]->var->type,
2899 ctx->stage == MESA_SHADER_VERTEX);
2900 count -= chan / 4;
2901 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2902 &ctx->ac, ctx->inputs + idx + chan, count,
2903 4, false);
2904
2905 values[chan] = LLVMBuildExtractElement(ctx->builder,
2906 tmp_vec,
2907 indir_index, "");
2908 } else
2909 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2910 }
2911 break;
2912 case nir_var_local:
2913 for (unsigned chan = 0; chan < ve; chan++) {
2914 if (indir_index) {
2915 unsigned count = glsl_count_attribute_slots(
2916 instr->variables[0]->var->type, false);
2917 count -= chan / 4;
2918 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2919 &ctx->ac, ctx->locals + idx + chan, count,
2920 4, true);
2921
2922 values[chan] = LLVMBuildExtractElement(ctx->builder,
2923 tmp_vec,
2924 indir_index, "");
2925 } else {
2926 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2927 }
2928 }
2929 break;
2930 case nir_var_shader_out:
2931 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2932 return load_tcs_output(ctx, instr);
2933 for (unsigned chan = 0; chan < ve; chan++) {
2934 if (indir_index) {
2935 unsigned count = glsl_count_attribute_slots(
2936 instr->variables[0]->var->type, false);
2937 count -= chan / 4;
2938 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2939 &ctx->ac, ctx->outputs + idx + chan, count,
2940 4, true);
2941
2942 values[chan] = LLVMBuildExtractElement(ctx->builder,
2943 tmp_vec,
2944 indir_index, "");
2945 } else {
2946 values[chan] = LLVMBuildLoad(ctx->builder,
2947 ctx->outputs[idx + chan + const_index * 4],
2948 "");
2949 }
2950 }
2951 break;
2952 case nir_var_shared: {
2953 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2954 LLVMValueRef derived_ptr;
2955
2956 if (indir_index)
2957 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2958
2959 for (unsigned chan = 0; chan < ve; chan++) {
2960 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2961 if (indir_index)
2962 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2963 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2964
2965 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2966 }
2967 break;
2968 }
2969 default:
2970 unreachable("unhandle variable mode");
2971 }
2972 ret = ac_build_gather_values(&ctx->ac, values, ve);
2973 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2974 }
2975
2976 static void
2977 visit_store_var(struct nir_to_llvm_context *ctx,
2978 nir_intrinsic_instr *instr)
2979 {
2980 LLVMValueRef temp_ptr, value;
2981 int idx = instr->variables[0]->var->data.driver_location;
2982 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2983 int writemask = instr->const_index[0];
2984 LLVMValueRef indir_index;
2985 unsigned const_index;
2986 radv_get_deref_offset(ctx, instr->variables[0], false,
2987 NULL, NULL, &const_index, &indir_index);
2988
2989 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2990 int old_writemask = writemask;
2991
2992 src = LLVMBuildBitCast(ctx->builder, src,
2993 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2994 "");
2995
2996 writemask = 0;
2997 for (unsigned chan = 0; chan < 4; chan++) {
2998 if (old_writemask & (1 << chan))
2999 writemask |= 3u << (2 * chan);
3000 }
3001 }
3002
3003 switch (instr->variables[0]->var->data.mode) {
3004 case nir_var_shader_out:
3005
3006 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3007 store_tcs_output(ctx, instr, src, writemask);
3008 return;
3009 }
3010
3011 for (unsigned chan = 0; chan < 8; chan++) {
3012 int stride = 4;
3013 if (!(writemask & (1 << chan)))
3014 continue;
3015
3016 value = llvm_extract_elem(ctx, src, chan);
3017
3018 if (instr->variables[0]->var->data.compact)
3019 stride = 1;
3020 if (indir_index) {
3021 unsigned count = glsl_count_attribute_slots(
3022 instr->variables[0]->var->type, false);
3023 count -= chan / 4;
3024 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3025 &ctx->ac, ctx->outputs + idx + chan, count,
3026 stride, true);
3027
3028 if (get_llvm_num_components(tmp_vec) > 1) {
3029 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3030 value, indir_index, "");
3031 } else
3032 tmp_vec = value;
3033 build_store_values_extended(ctx, ctx->outputs + idx + chan,
3034 count, stride, tmp_vec);
3035
3036 } else {
3037 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3038
3039 LLVMBuildStore(ctx->builder, value, temp_ptr);
3040 }
3041 }
3042 break;
3043 case nir_var_local:
3044 for (unsigned chan = 0; chan < 8; chan++) {
3045 if (!(writemask & (1 << chan)))
3046 continue;
3047
3048 value = llvm_extract_elem(ctx, src, chan);
3049 if (indir_index) {
3050 unsigned count = glsl_count_attribute_slots(
3051 instr->variables[0]->var->type, false);
3052 count -= chan / 4;
3053 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3054 &ctx->ac, ctx->locals + idx + chan, count,
3055 4, true);
3056
3057 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3058 value, indir_index, "");
3059 build_store_values_extended(ctx, ctx->locals + idx + chan,
3060 count, 4, tmp_vec);
3061 } else {
3062 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3063
3064 LLVMBuildStore(ctx->builder, value, temp_ptr);
3065 }
3066 }
3067 break;
3068 case nir_var_shared: {
3069 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3070
3071 if (indir_index)
3072 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
3073
3074 for (unsigned chan = 0; chan < 8; chan++) {
3075 if (!(writemask & (1 << chan)))
3076 continue;
3077 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
3078 LLVMValueRef derived_ptr;
3079
3080 if (indir_index)
3081 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
3082
3083 value = llvm_extract_elem(ctx, src, chan);
3084 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
3085 LLVMBuildStore(ctx->builder,
3086 to_integer(ctx, value), derived_ptr);
3087 }
3088 break;
3089 }
3090 default:
3091 break;
3092 }
3093 }
3094
3095 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3096 {
3097 switch (dim) {
3098 case GLSL_SAMPLER_DIM_BUF:
3099 return 1;
3100 case GLSL_SAMPLER_DIM_1D:
3101 return array ? 2 : 1;
3102 case GLSL_SAMPLER_DIM_2D:
3103 return array ? 3 : 2;
3104 case GLSL_SAMPLER_DIM_MS:
3105 return array ? 4 : 3;
3106 case GLSL_SAMPLER_DIM_3D:
3107 case GLSL_SAMPLER_DIM_CUBE:
3108 return 3;
3109 case GLSL_SAMPLER_DIM_RECT:
3110 case GLSL_SAMPLER_DIM_SUBPASS:
3111 return 2;
3112 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3113 return 3;
3114 default:
3115 break;
3116 }
3117 return 0;
3118 }
3119
3120
3121
3122 /* Adjust the sample index according to FMASK.
3123 *
3124 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3125 * which is the identity mapping. Each nibble says which physical sample
3126 * should be fetched to get that sample.
3127 *
3128 * For example, 0x11111100 means there are only 2 samples stored and
3129 * the second sample covers 3/4 of the pixel. When reading samples 0
3130 * and 1, return physical sample 0 (determined by the first two 0s
3131 * in FMASK), otherwise return physical sample 1.
3132 *
3133 * The sample index should be adjusted as follows:
3134 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3135 */
3136 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3137 LLVMValueRef coord_x, LLVMValueRef coord_y,
3138 LLVMValueRef coord_z,
3139 LLVMValueRef sample_index,
3140 LLVMValueRef fmask_desc_ptr)
3141 {
3142 LLVMValueRef fmask_load_address[4];
3143 LLVMValueRef res;
3144
3145 fmask_load_address[0] = coord_x;
3146 fmask_load_address[1] = coord_y;
3147 if (coord_z) {
3148 fmask_load_address[2] = coord_z;
3149 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3150 }
3151
3152 struct ac_image_args args = {0};
3153
3154 args.opcode = ac_image_load;
3155 args.da = coord_z ? true : false;
3156 args.resource = fmask_desc_ptr;
3157 args.dmask = 0xf;
3158 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3159
3160 res = ac_build_image_opcode(&ctx->ac, &args);
3161
3162 res = to_integer(ctx, res);
3163 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3164 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3165
3166 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3167 res,
3168 ctx->i32zero, "");
3169
3170 LLVMValueRef sample_index4 =
3171 LLVMBuildMul(ctx->builder, sample_index, four, "");
3172 LLVMValueRef shifted_fmask =
3173 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3174 LLVMValueRef final_sample =
3175 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3176
3177 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3178 * resource descriptor is 0 (invalid),
3179 */
3180 LLVMValueRef fmask_desc =
3181 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3182 ctx->v8i32, "");
3183
3184 LLVMValueRef fmask_word1 =
3185 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3186 ctx->i32one, "");
3187
3188 LLVMValueRef word1_is_nonzero =
3189 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3190 fmask_word1, ctx->i32zero, "");
3191
3192 /* Replace the MSAA sample index. */
3193 sample_index =
3194 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3195 final_sample, sample_index, "");
3196 return sample_index;
3197 }
3198
3199 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3200 nir_intrinsic_instr *instr)
3201 {
3202 const struct glsl_type *type = instr->variables[0]->var->type;
3203 if(instr->variables[0]->deref.child)
3204 type = instr->variables[0]->deref.child->type;
3205
3206 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3207 LLVMValueRef coords[4];
3208 LLVMValueRef masks[] = {
3209 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3210 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3211 };
3212 LLVMValueRef res;
3213 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3214
3215 int count;
3216 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3217 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3218 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3219 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3220 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3221
3222 count = image_type_to_components_count(dim,
3223 glsl_sampler_type_is_array(type));
3224
3225 if (is_ms) {
3226 LLVMValueRef fmask_load_address[3];
3227 int chan;
3228
3229 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3230 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3231 if (glsl_sampler_type_is_array(type))
3232 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3233 else
3234 fmask_load_address[2] = NULL;
3235 if (add_frag_pos) {
3236 for (chan = 0; chan < 2; ++chan)
3237 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3238 }
3239 sample_index = adjust_sample_index_using_fmask(ctx,
3240 fmask_load_address[0],
3241 fmask_load_address[1],
3242 fmask_load_address[2],
3243 sample_index,
3244 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3245 }
3246 if (count == 1) {
3247 if (instr->src[0].ssa->num_components)
3248 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3249 else
3250 res = src0;
3251 } else {
3252 int chan;
3253 if (is_ms)
3254 count--;
3255 for (chan = 0; chan < count; ++chan) {
3256 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3257 }
3258
3259 if (add_frag_pos) {
3260 for (chan = 0; chan < count; ++chan)
3261 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3262 }
3263 if (is_ms) {
3264 coords[count] = sample_index;
3265 count++;
3266 }
3267
3268 if (count == 3) {
3269 coords[3] = LLVMGetUndef(ctx->i32);
3270 count = 4;
3271 }
3272 res = ac_build_gather_values(&ctx->ac, coords, count);
3273 }
3274 return res;
3275 }
3276
3277 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3278 nir_intrinsic_instr *instr)
3279 {
3280 LLVMValueRef params[7];
3281 LLVMValueRef res;
3282 char intrinsic_name[64];
3283 const nir_variable *var = instr->variables[0]->var;
3284 const struct glsl_type *type = var->type;
3285 if(instr->variables[0]->deref.child)
3286 type = instr->variables[0]->deref.child->type;
3287
3288 type = glsl_without_array(type);
3289 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3290 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3291 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3292 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3293 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3294 params[3] = ctx->i1false; /* glc */
3295 params[4] = ctx->i1false; /* slc */
3296 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3297 params, 5, 0);
3298
3299 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3300 res = to_integer(ctx, res);
3301 } else {
3302 bool is_da = glsl_sampler_type_is_array(type) ||
3303 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3304 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3305 LLVMValueRef glc = ctx->i1false;
3306 LLVMValueRef slc = ctx->i1false;
3307
3308 params[0] = get_image_coords(ctx, instr);
3309 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3310 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3311 if (HAVE_LLVM <= 0x0309) {
3312 params[3] = ctx->i1false; /* r128 */
3313 params[4] = da;
3314 params[5] = glc;
3315 params[6] = slc;
3316 } else {
3317 LLVMValueRef lwe = ctx->i1false;
3318 params[3] = glc;
3319 params[4] = slc;
3320 params[5] = lwe;
3321 params[6] = da;
3322 }
3323
3324 ac_get_image_intr_name("llvm.amdgcn.image.load",
3325 ctx->v4f32, /* vdata */
3326 LLVMTypeOf(params[0]), /* coords */
3327 LLVMTypeOf(params[1]), /* rsrc */
3328 intrinsic_name, sizeof(intrinsic_name));
3329
3330 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3331 params, 7, AC_FUNC_ATTR_READONLY);
3332 }
3333 return to_integer(ctx, res);
3334 }
3335
3336 static void visit_image_store(struct nir_to_llvm_context *ctx,
3337 nir_intrinsic_instr *instr)
3338 {
3339 LLVMValueRef params[8];
3340 char intrinsic_name[64];
3341 const nir_variable *var = instr->variables[0]->var;
3342 const struct glsl_type *type = glsl_without_array(var->type);
3343
3344 if (ctx->stage == MESA_SHADER_FRAGMENT)
3345 ctx->shader_info->fs.writes_memory = true;
3346
3347 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3348 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
3349 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3350 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3351 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3352 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3353 params[4] = ctx->i1false; /* glc */
3354 params[5] = ctx->i1false; /* slc */
3355 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3356 params, 6, 0);
3357 } else {
3358 bool is_da = glsl_sampler_type_is_array(type) ||
3359 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3360 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3361 LLVMValueRef glc = ctx->i1false;
3362 LLVMValueRef slc = ctx->i1false;
3363
3364 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
3365 params[1] = get_image_coords(ctx, instr); /* coords */
3366 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3367 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3368 if (HAVE_LLVM <= 0x0309) {
3369 params[4] = ctx->i1false; /* r128 */
3370 params[5] = da;
3371 params[6] = glc;
3372 params[7] = slc;
3373 } else {
3374 LLVMValueRef lwe = ctx->i1false;
3375 params[4] = glc;
3376 params[5] = slc;
3377 params[6] = lwe;
3378 params[7] = da;
3379 }
3380
3381 ac_get_image_intr_name("llvm.amdgcn.image.store",
3382 LLVMTypeOf(params[0]), /* vdata */
3383 LLVMTypeOf(params[1]), /* coords */
3384 LLVMTypeOf(params[2]), /* rsrc */
3385 intrinsic_name, sizeof(intrinsic_name));
3386
3387 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3388 params, 8, 0);
3389 }
3390
3391 }
3392
3393 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3394 nir_intrinsic_instr *instr)
3395 {
3396 LLVMValueRef params[6];
3397 int param_count = 0;
3398 const nir_variable *var = instr->variables[0]->var;
3399
3400 const char *base_name = "llvm.amdgcn.image.atomic";
3401 const char *atomic_name;
3402 LLVMValueRef coords;
3403 char intrinsic_name[32], coords_type[8];
3404 const struct glsl_type *type = glsl_without_array(var->type);
3405
3406 if (ctx->stage == MESA_SHADER_FRAGMENT)
3407 ctx->shader_info->fs.writes_memory = true;
3408
3409 params[param_count++] = get_src(ctx, instr->src[2]);
3410 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3411 params[param_count++] = get_src(ctx, instr->src[3]);
3412
3413 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3414 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3415 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3416 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3417 params[param_count++] = ctx->i32zero; /* voffset */
3418 params[param_count++] = ctx->i1false; /* glc */
3419 params[param_count++] = ctx->i1false; /* slc */
3420 } else {
3421 bool da = glsl_sampler_type_is_array(type) ||
3422 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3423
3424 coords = params[param_count++] = get_image_coords(ctx, instr);
3425 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3426 params[param_count++] = ctx->i1false; /* r128 */
3427 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3428 params[param_count++] = ctx->i1false; /* slc */
3429 }
3430
3431 switch (instr->intrinsic) {
3432 case nir_intrinsic_image_atomic_add:
3433 atomic_name = "add";
3434 break;
3435 case nir_intrinsic_image_atomic_min:
3436 atomic_name = "smin";
3437 break;
3438 case nir_intrinsic_image_atomic_max:
3439 atomic_name = "smax";
3440 break;
3441 case nir_intrinsic_image_atomic_and:
3442 atomic_name = "and";
3443 break;
3444 case nir_intrinsic_image_atomic_or:
3445 atomic_name = "or";
3446 break;
3447 case nir_intrinsic_image_atomic_xor:
3448 atomic_name = "xor";
3449 break;
3450 case nir_intrinsic_image_atomic_exchange:
3451 atomic_name = "swap";
3452 break;
3453 case nir_intrinsic_image_atomic_comp_swap:
3454 atomic_name = "cmpswap";
3455 break;
3456 default:
3457 abort();
3458 }
3459 build_int_type_name(LLVMTypeOf(coords),
3460 coords_type, sizeof(coords_type));
3461
3462 snprintf(intrinsic_name, sizeof(intrinsic_name),
3463 "%s.%s.%s", base_name, atomic_name, coords_type);
3464 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3465 }
3466
3467 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3468 nir_intrinsic_instr *instr)
3469 {
3470 LLVMValueRef res;
3471 const nir_variable *var = instr->variables[0]->var;
3472 const struct glsl_type *type = instr->variables[0]->var->type;
3473 bool da = glsl_sampler_type_is_array(var->type) ||
3474 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3475 if(instr->variables[0]->deref.child)
3476 type = instr->variables[0]->deref.child->type;
3477
3478 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3479 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3480
3481 struct ac_image_args args = { 0 };
3482
3483 args.da = da;
3484 args.dmask = 0xf;
3485 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3486 args.opcode = ac_image_get_resinfo;
3487 args.addr = ctx->i32zero;
3488
3489 res = ac_build_image_opcode(&ctx->ac, &args);
3490
3491 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3492 glsl_sampler_type_is_array(type)) {
3493 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3494 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3495 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3496 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3497 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3498 }
3499 return res;
3500 }
3501
3502 #define NOOP_WAITCNT 0xf7f
3503 #define LGKM_CNT 0x07f
3504 #define VM_CNT 0xf70
3505
3506 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3507 unsigned simm16)
3508 {
3509 LLVMValueRef args[1] = {
3510 LLVMConstInt(ctx->i32, simm16, false),
3511 };
3512 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3513 ctx->voidt, args, 1, 0);
3514 }
3515
3516 static void emit_barrier(struct nir_to_llvm_context *ctx)
3517 {
3518 /* SI only (thanks to a hw bug workaround):
3519 * The real barrier instruction isn’t needed, because an entire patch
3520 * always fits into a single wave.
3521 */
3522 if (ctx->options->chip_class == SI &&
3523 ctx->stage == MESA_SHADER_TESS_CTRL) {
3524 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3525 return;
3526 }
3527 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3528 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3529 }
3530
3531 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3532 nir_intrinsic_instr *instr)
3533 {
3534 LLVMValueRef cond;
3535 ctx->shader_info->fs.can_discard = true;
3536
3537 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3538 get_src(ctx, instr->src[0]),
3539 ctx->i32zero, "");
3540
3541 cond = LLVMBuildSelect(ctx->builder, cond,
3542 LLVMConstReal(ctx->f32, -1.0f),
3543 ctx->f32zero, "");
3544 ac_build_kill(&ctx->ac, cond);
3545 }
3546
3547 static LLVMValueRef
3548 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3549 {
3550 LLVMValueRef result;
3551 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3552 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3553 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3554
3555 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3556 }
3557
3558 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3559 nir_intrinsic_instr *instr)
3560 {
3561 LLVMValueRef ptr, result;
3562 int idx = instr->variables[0]->var->data.driver_location;
3563 LLVMValueRef src = get_src(ctx, instr->src[0]);
3564 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3565
3566 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3567 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3568 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3569 ptr, src, src1,
3570 LLVMAtomicOrderingSequentiallyConsistent,
3571 LLVMAtomicOrderingSequentiallyConsistent,
3572 false);
3573 } else {
3574 LLVMAtomicRMWBinOp op;
3575 switch (instr->intrinsic) {
3576 case nir_intrinsic_var_atomic_add:
3577 op = LLVMAtomicRMWBinOpAdd;
3578 break;
3579 case nir_intrinsic_var_atomic_umin:
3580 op = LLVMAtomicRMWBinOpUMin;
3581 break;
3582 case nir_intrinsic_var_atomic_umax:
3583 op = LLVMAtomicRMWBinOpUMax;
3584 break;
3585 case nir_intrinsic_var_atomic_imin:
3586 op = LLVMAtomicRMWBinOpMin;
3587 break;
3588 case nir_intrinsic_var_atomic_imax:
3589 op = LLVMAtomicRMWBinOpMax;
3590 break;
3591 case nir_intrinsic_var_atomic_and:
3592 op = LLVMAtomicRMWBinOpAnd;
3593 break;
3594 case nir_intrinsic_var_atomic_or:
3595 op = LLVMAtomicRMWBinOpOr;
3596 break;
3597 case nir_intrinsic_var_atomic_xor:
3598 op = LLVMAtomicRMWBinOpXor;
3599 break;
3600 case nir_intrinsic_var_atomic_exchange:
3601 op = LLVMAtomicRMWBinOpXchg;
3602 break;
3603 default:
3604 return NULL;
3605 }
3606
3607 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3608 LLVMAtomicOrderingSequentiallyConsistent,
3609 false);
3610 }
3611 return result;
3612 }
3613
3614 #define INTERP_CENTER 0
3615 #define INTERP_CENTROID 1
3616 #define INTERP_SAMPLE 2
3617
3618 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3619 enum glsl_interp_mode interp, unsigned location)
3620 {
3621 switch (interp) {
3622 case INTERP_MODE_FLAT:
3623 default:
3624 return NULL;
3625 case INTERP_MODE_SMOOTH:
3626 case INTERP_MODE_NONE:
3627 if (location == INTERP_CENTER)
3628 return ctx->persp_center;
3629 else if (location == INTERP_CENTROID)
3630 return ctx->persp_centroid;
3631 else if (location == INTERP_SAMPLE)
3632 return ctx->persp_sample;
3633 break;
3634 case INTERP_MODE_NOPERSPECTIVE:
3635 if (location == INTERP_CENTER)
3636 return ctx->linear_center;
3637 else if (location == INTERP_CENTROID)
3638 return ctx->linear_centroid;
3639 else if (location == INTERP_SAMPLE)
3640 return ctx->linear_sample;
3641 break;
3642 }
3643 return NULL;
3644 }
3645
3646 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3647 LLVMValueRef sample_id)
3648 {
3649 LLVMValueRef result;
3650 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3651
3652 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3653 const_array(ctx->v2f32, 64), "");
3654
3655 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3656 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3657
3658 return result;
3659 }
3660
3661 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3662 {
3663 LLVMValueRef values[2];
3664
3665 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3666 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3667 return ac_build_gather_values(&ctx->ac, values, 2);
3668 }
3669
3670 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3671 nir_intrinsic_instr *instr)
3672 {
3673 LLVMValueRef result[2];
3674 LLVMValueRef interp_param, attr_number;
3675 unsigned location;
3676 unsigned chan;
3677 LLVMValueRef src_c0, src_c1;
3678 LLVMValueRef src0;
3679 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3680 switch (instr->intrinsic) {
3681 case nir_intrinsic_interp_var_at_centroid:
3682 location = INTERP_CENTROID;
3683 break;
3684 case nir_intrinsic_interp_var_at_sample:
3685 case nir_intrinsic_interp_var_at_offset:
3686 location = INTERP_CENTER;
3687 src0 = get_src(ctx, instr->src[0]);
3688 break;
3689 default:
3690 break;
3691 }
3692
3693 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3694 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3695 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3696 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3697 LLVMValueRef sample_position;
3698 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3699
3700 /* fetch sample ID */
3701 sample_position = load_sample_position(ctx, src0);
3702
3703 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3704 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3705 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3706 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3707 }
3708 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3709 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3710
3711 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3712 LLVMValueRef ij_out[2];
3713 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3714
3715 /*
3716 * take the I then J parameters, and the DDX/Y for it, and
3717 * calculate the IJ inputs for the interpolator.
3718 * temp1 = ddx * offset/sample.x + I;
3719 * interp_param.I = ddy * offset/sample.y + temp1;
3720 * temp1 = ddx * offset/sample.x + J;
3721 * interp_param.J = ddy * offset/sample.y + temp1;
3722 */
3723 for (unsigned i = 0; i < 2; i++) {
3724 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3725 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3726 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3727 ddxy_out, ix_ll, "");
3728 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3729 ddxy_out, iy_ll, "");
3730 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3731 interp_param, ix_ll, "");
3732 LLVMValueRef temp1, temp2;
3733
3734 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3735 ctx->f32, "");
3736
3737 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3738 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3739
3740 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3741 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3742
3743 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3744 temp2, ctx->i32, "");
3745 }
3746 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3747
3748 }
3749
3750 for (chan = 0; chan < 2; chan++) {
3751 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3752
3753 if (interp_param) {
3754 interp_param = LLVMBuildBitCast(ctx->builder,
3755 interp_param, LLVMVectorType(ctx->f32, 2), "");
3756 LLVMValueRef i = LLVMBuildExtractElement(
3757 ctx->builder, interp_param, ctx->i32zero, "");
3758 LLVMValueRef j = LLVMBuildExtractElement(
3759 ctx->builder, interp_param, ctx->i32one, "");
3760
3761 result[chan] = ac_build_fs_interp(&ctx->ac,
3762 llvm_chan, attr_number,
3763 ctx->prim_mask, i, j);
3764 } else {
3765 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3766 LLVMConstInt(ctx->i32, 2, false),
3767 llvm_chan, attr_number,
3768 ctx->prim_mask);
3769 }
3770 }
3771 return ac_build_gather_values(&ctx->ac, result, 2);
3772 }
3773
3774 static void
3775 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3776 nir_intrinsic_instr *instr)
3777 {
3778 LLVMValueRef gs_next_vertex;
3779 LLVMValueRef can_emit, kill;
3780 int idx;
3781
3782 assert(instr->const_index[0] == 0);
3783 /* Write vertex attribute values to GSVS ring */
3784 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3785 ctx->gs_next_vertex,
3786 "");
3787
3788 /* If this thread has already emitted the declared maximum number of
3789 * vertices, kill it: excessive vertex emissions are not supposed to
3790 * have any effect, and GS threads have no externally observable
3791 * effects other than emitting vertices.
3792 */
3793 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3794 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3795
3796 kill = LLVMBuildSelect(ctx->builder, can_emit,
3797 LLVMConstReal(ctx->f32, 1.0f),
3798 LLVMConstReal(ctx->f32, -1.0f), "");
3799 ac_build_kill(&ctx->ac, kill);
3800
3801 /* loop num outputs */
3802 idx = 0;
3803 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3804 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3805 int length = 4;
3806 int slot = idx;
3807 int slot_inc = 1;
3808
3809 if (!(ctx->output_mask & (1ull << i)))
3810 continue;
3811
3812 if (i == VARYING_SLOT_CLIP_DIST0) {
3813 /* pack clip and cull into a single set of slots */
3814 length = ctx->num_output_clips + ctx->num_output_culls;
3815 if (length > 4)
3816 slot_inc = 2;
3817 }
3818 for (unsigned j = 0; j < length; j++) {
3819 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3820 out_ptr[j], "");
3821 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3822 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3823 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3824
3825 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3826
3827 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3828 out_val, 1,
3829 voffset, ctx->gs2vs_offset, 0,
3830 1, 1, true, true);
3831 }
3832 idx += slot_inc;
3833 }
3834
3835 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3836 ctx->i32one, "");
3837 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3838
3839 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3840 }
3841
3842 static void
3843 visit_end_primitive(struct nir_to_llvm_context *ctx,
3844 nir_intrinsic_instr *instr)
3845 {
3846 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3847 }
3848
3849 static LLVMValueRef
3850 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3851 nir_intrinsic_instr *instr)
3852 {
3853 LLVMValueRef coord[4] = {
3854 ctx->tes_u,
3855 ctx->tes_v,
3856 ctx->f32zero,
3857 ctx->f32zero,
3858 };
3859
3860 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3861 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3862 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3863
3864 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3865 return LLVMBuildBitCast(ctx->builder, result,
3866 get_def_type(ctx, &instr->dest.ssa), "");
3867 }
3868
3869 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3870 nir_intrinsic_instr *instr)
3871 {
3872 LLVMValueRef result = NULL;
3873
3874 switch (instr->intrinsic) {
3875 case nir_intrinsic_load_work_group_id: {
3876 result = ctx->workgroup_ids;
3877 break;
3878 }
3879 case nir_intrinsic_load_base_vertex: {
3880 result = ctx->base_vertex;
3881 break;
3882 }
3883 case nir_intrinsic_load_vertex_id_zero_base: {
3884 result = ctx->vertex_id;
3885 break;
3886 }
3887 case nir_intrinsic_load_local_invocation_id: {
3888 result = ctx->local_invocation_ids;
3889 break;
3890 }
3891 case nir_intrinsic_load_base_instance:
3892 result = ctx->start_instance;
3893 break;
3894 case nir_intrinsic_load_draw_id:
3895 result = ctx->draw_index;
3896 break;
3897 case nir_intrinsic_load_invocation_id:
3898 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3899 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3900 else
3901 result = ctx->gs_invocation_id;
3902 break;
3903 case nir_intrinsic_load_primitive_id:
3904 if (ctx->stage == MESA_SHADER_GEOMETRY)
3905 result = ctx->gs_prim_id;
3906 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
3907 result = ctx->tcs_patch_id;
3908 else if (ctx->stage == MESA_SHADER_TESS_EVAL)
3909 result = ctx->tes_patch_id;
3910 else
3911 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3912 break;
3913 case nir_intrinsic_load_sample_id:
3914 ctx->shader_info->fs.force_persample = true;
3915 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3916 break;
3917 case nir_intrinsic_load_sample_pos:
3918 ctx->shader_info->fs.force_persample = true;
3919 result = load_sample_pos(ctx);
3920 break;
3921 case nir_intrinsic_load_sample_mask_in:
3922 result = ctx->sample_coverage;
3923 break;
3924 case nir_intrinsic_load_front_face:
3925 result = ctx->front_face;
3926 break;
3927 case nir_intrinsic_load_instance_id:
3928 result = ctx->instance_id;
3929 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3930 ctx->shader_info->vs.vgpr_comp_cnt);
3931 break;
3932 case nir_intrinsic_load_num_work_groups:
3933 result = ctx->num_work_groups;
3934 break;
3935 case nir_intrinsic_load_local_invocation_index:
3936 result = visit_load_local_invocation_index(ctx);
3937 break;
3938 case nir_intrinsic_load_push_constant:
3939 result = visit_load_push_constant(ctx, instr);
3940 break;
3941 case nir_intrinsic_vulkan_resource_index:
3942 result = visit_vulkan_resource_index(ctx, instr);
3943 break;
3944 case nir_intrinsic_store_ssbo:
3945 visit_store_ssbo(ctx, instr);
3946 break;
3947 case nir_intrinsic_load_ssbo:
3948 result = visit_load_buffer(ctx, instr);
3949 break;
3950 case nir_intrinsic_ssbo_atomic_add:
3951 case nir_intrinsic_ssbo_atomic_imin:
3952 case nir_intrinsic_ssbo_atomic_umin:
3953 case nir_intrinsic_ssbo_atomic_imax:
3954 case nir_intrinsic_ssbo_atomic_umax:
3955 case nir_intrinsic_ssbo_atomic_and:
3956 case nir_intrinsic_ssbo_atomic_or:
3957 case nir_intrinsic_ssbo_atomic_xor:
3958 case nir_intrinsic_ssbo_atomic_exchange:
3959 case nir_intrinsic_ssbo_atomic_comp_swap:
3960 result = visit_atomic_ssbo(ctx, instr);
3961 break;
3962 case nir_intrinsic_load_ubo:
3963 result = visit_load_ubo_buffer(ctx, instr);
3964 break;
3965 case nir_intrinsic_get_buffer_size:
3966 result = visit_get_buffer_size(ctx, instr);
3967 break;
3968 case nir_intrinsic_load_var:
3969 result = visit_load_var(ctx, instr);
3970 break;
3971 case nir_intrinsic_store_var:
3972 visit_store_var(ctx, instr);
3973 break;
3974 case nir_intrinsic_image_load:
3975 result = visit_image_load(ctx, instr);
3976 break;
3977 case nir_intrinsic_image_store:
3978 visit_image_store(ctx, instr);
3979 break;
3980 case nir_intrinsic_image_atomic_add:
3981 case nir_intrinsic_image_atomic_min:
3982 case nir_intrinsic_image_atomic_max:
3983 case nir_intrinsic_image_atomic_and:
3984 case nir_intrinsic_image_atomic_or:
3985 case nir_intrinsic_image_atomic_xor:
3986 case nir_intrinsic_image_atomic_exchange:
3987 case nir_intrinsic_image_atomic_comp_swap:
3988 result = visit_image_atomic(ctx, instr);
3989 break;
3990 case nir_intrinsic_image_size:
3991 result = visit_image_size(ctx, instr);
3992 break;
3993 case nir_intrinsic_discard:
3994 ctx->shader_info->fs.can_discard = true;
3995 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3996 ctx->voidt,
3997 NULL, 0, AC_FUNC_ATTR_LEGACY);
3998 break;
3999 case nir_intrinsic_discard_if:
4000 emit_discard_if(ctx, instr);
4001 break;
4002 case nir_intrinsic_memory_barrier:
4003 emit_waitcnt(ctx, VM_CNT);
4004 break;
4005 case nir_intrinsic_barrier:
4006 emit_barrier(ctx);
4007 break;
4008 case nir_intrinsic_var_atomic_add:
4009 case nir_intrinsic_var_atomic_imin:
4010 case nir_intrinsic_var_atomic_umin:
4011 case nir_intrinsic_var_atomic_imax:
4012 case nir_intrinsic_var_atomic_umax:
4013 case nir_intrinsic_var_atomic_and:
4014 case nir_intrinsic_var_atomic_or:
4015 case nir_intrinsic_var_atomic_xor:
4016 case nir_intrinsic_var_atomic_exchange:
4017 case nir_intrinsic_var_atomic_comp_swap:
4018 result = visit_var_atomic(ctx, instr);
4019 break;
4020 case nir_intrinsic_interp_var_at_centroid:
4021 case nir_intrinsic_interp_var_at_sample:
4022 case nir_intrinsic_interp_var_at_offset:
4023 result = visit_interp(ctx, instr);
4024 break;
4025 case nir_intrinsic_emit_vertex:
4026 visit_emit_vertex(ctx, instr);
4027 break;
4028 case nir_intrinsic_end_primitive:
4029 visit_end_primitive(ctx, instr);
4030 break;
4031 case nir_intrinsic_load_tess_coord:
4032 result = visit_load_tess_coord(ctx, instr);
4033 break;
4034 case nir_intrinsic_load_patch_vertices_in:
4035 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
4036 break;
4037 default:
4038 fprintf(stderr, "Unknown intrinsic: ");
4039 nir_print_instr(&instr->instr, stderr);
4040 fprintf(stderr, "\n");
4041 break;
4042 }
4043 if (result) {
4044 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4045 }
4046 }
4047
4048 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
4049 nir_deref_var *deref,
4050 enum desc_type desc_type)
4051 {
4052 unsigned desc_set = deref->var->data.descriptor_set;
4053 LLVMValueRef list = ctx->descriptor_sets[desc_set];
4054 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4055 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
4056 unsigned offset = binding->offset;
4057 unsigned stride = binding->size;
4058 unsigned type_size;
4059 LLVMBuilderRef builder = ctx->builder;
4060 LLVMTypeRef type;
4061 LLVMValueRef index = NULL;
4062 unsigned constant_index = 0;
4063
4064 assert(deref->var->data.binding < layout->binding_count);
4065
4066 switch (desc_type) {
4067 case DESC_IMAGE:
4068 type = ctx->v8i32;
4069 type_size = 32;
4070 break;
4071 case DESC_FMASK:
4072 type = ctx->v8i32;
4073 offset += 32;
4074 type_size = 32;
4075 break;
4076 case DESC_SAMPLER:
4077 type = ctx->v4i32;
4078 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4079 offset += 64;
4080
4081 type_size = 16;
4082 break;
4083 case DESC_BUFFER:
4084 type = ctx->v4i32;
4085 type_size = 16;
4086 break;
4087 default:
4088 unreachable("invalid desc_type\n");
4089 }
4090
4091 if (deref->deref.child) {
4092 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
4093
4094 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4095 offset += child->base_offset * stride;
4096 if (child->deref_array_type == nir_deref_array_type_indirect) {
4097 index = get_src(ctx, child->indirect);
4098 }
4099
4100 constant_index = child->base_offset;
4101 }
4102 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
4103 (!index || binding->immutable_samplers_equal)) {
4104 if (binding->immutable_samplers_equal)
4105 constant_index = 0;
4106
4107 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4108
4109 LLVMValueRef constants[] = {
4110 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4111 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4112 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4113 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4114 };
4115 return ac_build_gather_values(&ctx->ac, constants, 4);
4116 }
4117
4118 assert(stride % type_size == 0);
4119
4120 if (!index)
4121 index = ctx->i32zero;
4122
4123 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4124
4125 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4126 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4127
4128 return ac_build_indexed_load_const(&ctx->ac, list, index);
4129 }
4130
4131 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4132 struct ac_image_args *args,
4133 nir_tex_instr *instr,
4134 nir_texop op,
4135 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4136 LLVMValueRef *param, unsigned count,
4137 unsigned dmask)
4138 {
4139 unsigned is_rect = 0;
4140 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4141
4142 if (op == nir_texop_lod)
4143 da = false;
4144 /* Pad to power of two vector */
4145 while (count < util_next_power_of_two(count))
4146 param[count++] = LLVMGetUndef(ctx->i32);
4147
4148 if (count > 1)
4149 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4150 else
4151 args->addr = param[0];
4152
4153 args->resource = res_ptr;
4154 args->sampler = samp_ptr;
4155
4156 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4157 args->addr = param[0];
4158 return;
4159 }
4160
4161 args->dmask = dmask;
4162 args->unorm = is_rect;
4163 args->da = da;
4164 }
4165
4166 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4167 *
4168 * SI-CI:
4169 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4170 * filtering manually. The driver sets img7 to a mask clearing
4171 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4172 * s_and_b32 samp0, samp0, img7
4173 *
4174 * VI:
4175 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4176 */
4177 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4178 LLVMValueRef res, LLVMValueRef samp)
4179 {
4180 LLVMBuilderRef builder = ctx->builder;
4181 LLVMValueRef img7, samp0;
4182
4183 if (ctx->options->chip_class >= VI)
4184 return samp;
4185
4186 img7 = LLVMBuildExtractElement(builder, res,
4187 LLVMConstInt(ctx->i32, 7, 0), "");
4188 samp0 = LLVMBuildExtractElement(builder, samp,
4189 LLVMConstInt(ctx->i32, 0, 0), "");
4190 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4191 return LLVMBuildInsertElement(builder, samp, samp0,
4192 LLVMConstInt(ctx->i32, 0, 0), "");
4193 }
4194
4195 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4196 nir_tex_instr *instr,
4197 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4198 LLVMValueRef *fmask_ptr)
4199 {
4200 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4201 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4202 else
4203 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4204 if (samp_ptr) {
4205 if (instr->sampler)
4206 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4207 else
4208 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4209 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4210 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4211 }
4212 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4213 instr->op == nir_texop_samples_identical))
4214 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4215 }
4216
4217 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4218 LLVMValueRef coord)
4219 {
4220 coord = to_float(ctx, coord);
4221 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4222 coord = to_integer(ctx, coord);
4223 return coord;
4224 }
4225
4226 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4227 {
4228 LLVMValueRef result = NULL;
4229 struct ac_image_args args = { 0 };
4230 unsigned dmask = 0xf;
4231 LLVMValueRef address[16];
4232 LLVMValueRef coords[5];
4233 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4234 LLVMValueRef bias = NULL, offsets = NULL;
4235 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4236 LLVMValueRef ddx = NULL, ddy = NULL;
4237 LLVMValueRef derivs[6];
4238 unsigned chan, count = 0;
4239 unsigned const_src = 0, num_deriv_comp = 0;
4240 bool lod_is_zero = false;
4241 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4242
4243 for (unsigned i = 0; i < instr->num_srcs; i++) {
4244 switch (instr->src[i].src_type) {
4245 case nir_tex_src_coord:
4246 coord = get_src(ctx, instr->src[i].src);
4247 break;
4248 case nir_tex_src_projector:
4249 break;
4250 case nir_tex_src_comparator:
4251 comparator = get_src(ctx, instr->src[i].src);
4252 break;
4253 case nir_tex_src_offset:
4254 offsets = get_src(ctx, instr->src[i].src);
4255 const_src = i;
4256 break;
4257 case nir_tex_src_bias:
4258 bias = get_src(ctx, instr->src[i].src);
4259 break;
4260 case nir_tex_src_lod: {
4261 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4262
4263 if (val && val->i32[0] == 0)
4264 lod_is_zero = true;
4265 lod = get_src(ctx, instr->src[i].src);
4266 break;
4267 }
4268 case nir_tex_src_ms_index:
4269 sample_index = get_src(ctx, instr->src[i].src);
4270 break;
4271 case nir_tex_src_ms_mcs:
4272 break;
4273 case nir_tex_src_ddx:
4274 ddx = get_src(ctx, instr->src[i].src);
4275 num_deriv_comp = instr->src[i].src.ssa->num_components;
4276 break;
4277 case nir_tex_src_ddy:
4278 ddy = get_src(ctx, instr->src[i].src);
4279 break;
4280 case nir_tex_src_texture_offset:
4281 case nir_tex_src_sampler_offset:
4282 case nir_tex_src_plane:
4283 default:
4284 break;
4285 }
4286 }
4287
4288 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4289 result = get_buffer_size(ctx, res_ptr, true);
4290 goto write_result;
4291 }
4292
4293 if (instr->op == nir_texop_texture_samples) {
4294 LLVMValueRef res, samples, is_msaa;
4295 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4296 samples = LLVMBuildExtractElement(ctx->builder, res,
4297 LLVMConstInt(ctx->i32, 3, false), "");
4298 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4299 LLVMConstInt(ctx->i32, 28, false), "");
4300 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4301 LLVMConstInt(ctx->i32, 0xe, false), "");
4302 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4303 LLVMConstInt(ctx->i32, 0xe, false), "");
4304
4305 samples = LLVMBuildLShr(ctx->builder, samples,
4306 LLVMConstInt(ctx->i32, 16, false), "");
4307 samples = LLVMBuildAnd(ctx->builder, samples,
4308 LLVMConstInt(ctx->i32, 0xf, false), "");
4309 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4310 samples, "");
4311 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4312 ctx->i32one, "");
4313 result = samples;
4314 goto write_result;
4315 }
4316
4317 if (coord)
4318 for (chan = 0; chan < instr->coord_components; chan++)
4319 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4320
4321 if (offsets && instr->op != nir_texop_txf) {
4322 LLVMValueRef offset[3], pack;
4323 for (chan = 0; chan < 3; ++chan)
4324 offset[chan] = ctx->i32zero;
4325
4326 args.offset = true;
4327 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4328 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4329 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4330 LLVMConstInt(ctx->i32, 0x3f, false), "");
4331 if (chan)
4332 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4333 LLVMConstInt(ctx->i32, chan * 8, false), "");
4334 }
4335 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4336 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4337 address[count++] = pack;
4338
4339 }
4340 /* pack LOD bias value */
4341 if (instr->op == nir_texop_txb && bias) {
4342 address[count++] = bias;
4343 }
4344
4345 /* Pack depth comparison value */
4346 if (instr->is_shadow && comparator) {
4347 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4348 }
4349
4350 /* pack derivatives */
4351 if (ddx || ddy) {
4352 switch (instr->sampler_dim) {
4353 case GLSL_SAMPLER_DIM_3D:
4354 case GLSL_SAMPLER_DIM_CUBE:
4355 num_deriv_comp = 3;
4356 break;
4357 case GLSL_SAMPLER_DIM_2D:
4358 default:
4359 num_deriv_comp = 2;
4360 break;
4361 case GLSL_SAMPLER_DIM_1D:
4362 num_deriv_comp = 1;
4363 break;
4364 }
4365
4366 for (unsigned i = 0; i < num_deriv_comp; i++) {
4367 derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
4368 derivs[num_deriv_comp + i] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
4369 }
4370 }
4371
4372 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4373 if (instr->is_array && instr->op != nir_texop_lod)
4374 coords[3] = apply_round_slice(ctx, coords[3]);
4375 for (chan = 0; chan < instr->coord_components; chan++)
4376 coords[chan] = to_float(ctx, coords[chan]);
4377 if (instr->coord_components == 3)
4378 coords[3] = LLVMGetUndef(ctx->f32);
4379 ac_prepare_cube_coords(&ctx->ac,
4380 instr->op == nir_texop_txd, instr->is_array,
4381 coords, derivs);
4382 if (num_deriv_comp)
4383 num_deriv_comp--;
4384 }
4385
4386 if (ddx || ddy) {
4387 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4388 address[count++] = derivs[i];
4389 }
4390
4391 /* Pack texture coordinates */
4392 if (coord) {
4393 address[count++] = coords[0];
4394 if (instr->coord_components > 1) {
4395 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4396 coords[1] = apply_round_slice(ctx, coords[1]);
4397 }
4398 address[count++] = coords[1];
4399 }
4400 if (instr->coord_components > 2) {
4401 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4402 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4403 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4404 instr->op != nir_texop_txf) {
4405 coords[2] = apply_round_slice(ctx, coords[2]);
4406 }
4407 address[count++] = coords[2];
4408 }
4409 }
4410
4411 /* Pack LOD */
4412 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4413 instr->op == nir_texop_txf)) {
4414 address[count++] = lod;
4415 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4416 address[count++] = sample_index;
4417 } else if(instr->op == nir_texop_txs) {
4418 count = 0;
4419 if (lod)
4420 address[count++] = lod;
4421 else
4422 address[count++] = ctx->i32zero;
4423 }
4424
4425 for (chan = 0; chan < count; chan++) {
4426 address[chan] = LLVMBuildBitCast(ctx->builder,
4427 address[chan], ctx->i32, "");
4428 }
4429
4430 if (instr->op == nir_texop_samples_identical) {
4431 LLVMValueRef txf_address[4];
4432 struct ac_image_args txf_args = { 0 };
4433 unsigned txf_count = count;
4434 memcpy(txf_address, address, sizeof(txf_address));
4435
4436 if (!instr->is_array)
4437 txf_address[2] = ctx->i32zero;
4438 txf_address[3] = ctx->i32zero;
4439
4440 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4441 fmask_ptr, NULL,
4442 txf_address, txf_count, 0xf);
4443
4444 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4445
4446 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4447 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
4448 goto write_result;
4449 }
4450
4451 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4452 instr->op != nir_texop_txs) {
4453 unsigned sample_chan = instr->is_array ? 3 : 2;
4454 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4455 address[0],
4456 address[1],
4457 instr->is_array ? address[2] : NULL,
4458 address[sample_chan],
4459 fmask_ptr);
4460 }
4461
4462 if (offsets && instr->op == nir_texop_txf) {
4463 nir_const_value *const_offset =
4464 nir_src_as_const_value(instr->src[const_src].src);
4465 int num_offsets = instr->src[const_src].src.ssa->num_components;
4466 assert(const_offset);
4467 num_offsets = MIN2(num_offsets, instr->coord_components);
4468 if (num_offsets > 2)
4469 address[2] = LLVMBuildAdd(ctx->builder,
4470 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4471 if (num_offsets > 1)
4472 address[1] = LLVMBuildAdd(ctx->builder,
4473 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4474 address[0] = LLVMBuildAdd(ctx->builder,
4475 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4476
4477 }
4478
4479 /* TODO TG4 support */
4480 if (instr->op == nir_texop_tg4) {
4481 if (instr->is_shadow)
4482 dmask = 1;
4483 else
4484 dmask = 1 << instr->component;
4485 }
4486 set_tex_fetch_args(ctx, &args, instr, instr->op,
4487 res_ptr, samp_ptr, address, count, dmask);
4488
4489 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4490
4491 if (instr->op == nir_texop_query_levels)
4492 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4493 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4494 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4495 else if (instr->op == nir_texop_txs &&
4496 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4497 instr->is_array) {
4498 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4499 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4500 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4501 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4502 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4503 } else if (instr->dest.ssa.num_components != 4)
4504 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4505
4506 write_result:
4507 if (result) {
4508 assert(instr->dest.is_ssa);
4509 result = to_integer(ctx, result);
4510 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4511 }
4512 }
4513
4514
4515 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4516 {
4517 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4518 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4519
4520 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4521 _mesa_hash_table_insert(ctx->phis, instr, result);
4522 }
4523
4524 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4525 nir_phi_instr *instr,
4526 LLVMValueRef llvm_phi)
4527 {
4528 nir_foreach_phi_src(src, instr) {
4529 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4530 LLVMValueRef llvm_src = get_src(ctx, src->src);
4531
4532 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4533 }
4534 }
4535
4536 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4537 {
4538 struct hash_entry *entry;
4539 hash_table_foreach(ctx->phis, entry) {
4540 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4541 (LLVMValueRef)entry->data);
4542 }
4543 }
4544
4545
4546 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4547 nir_ssa_undef_instr *instr)
4548 {
4549 unsigned num_components = instr->def.num_components;
4550 LLVMValueRef undef;
4551
4552 if (num_components == 1)
4553 undef = LLVMGetUndef(ctx->i32);
4554 else {
4555 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4556 }
4557 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4558 }
4559
4560 static void visit_jump(struct nir_to_llvm_context *ctx,
4561 nir_jump_instr *instr)
4562 {
4563 switch (instr->type) {
4564 case nir_jump_break:
4565 LLVMBuildBr(ctx->builder, ctx->break_block);
4566 LLVMClearInsertionPosition(ctx->builder);
4567 break;
4568 case nir_jump_continue:
4569 LLVMBuildBr(ctx->builder, ctx->continue_block);
4570 LLVMClearInsertionPosition(ctx->builder);
4571 break;
4572 default:
4573 fprintf(stderr, "Unknown NIR jump instr: ");
4574 nir_print_instr(&instr->instr, stderr);
4575 fprintf(stderr, "\n");
4576 abort();
4577 }
4578 }
4579
4580 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4581 struct exec_list *list);
4582
4583 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4584 {
4585 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4586 nir_foreach_instr(instr, block)
4587 {
4588 switch (instr->type) {
4589 case nir_instr_type_alu:
4590 visit_alu(ctx, nir_instr_as_alu(instr));
4591 break;
4592 case nir_instr_type_load_const:
4593 visit_load_const(ctx, nir_instr_as_load_const(instr));
4594 break;
4595 case nir_instr_type_intrinsic:
4596 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4597 break;
4598 case nir_instr_type_tex:
4599 visit_tex(ctx, nir_instr_as_tex(instr));
4600 break;
4601 case nir_instr_type_phi:
4602 visit_phi(ctx, nir_instr_as_phi(instr));
4603 break;
4604 case nir_instr_type_ssa_undef:
4605 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4606 break;
4607 case nir_instr_type_jump:
4608 visit_jump(ctx, nir_instr_as_jump(instr));
4609 break;
4610 default:
4611 fprintf(stderr, "Unknown NIR instr type: ");
4612 nir_print_instr(instr, stderr);
4613 fprintf(stderr, "\n");
4614 abort();
4615 }
4616 }
4617
4618 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4619 }
4620
4621 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4622 {
4623 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4624
4625 LLVMBasicBlockRef merge_block =
4626 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4627 LLVMBasicBlockRef if_block =
4628 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4629 LLVMBasicBlockRef else_block = merge_block;
4630 if (!exec_list_is_empty(&if_stmt->else_list))
4631 else_block = LLVMAppendBasicBlockInContext(
4632 ctx->context, ctx->main_function, "");
4633
4634 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4635 LLVMConstInt(ctx->i32, 0, false), "");
4636 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4637
4638 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4639 visit_cf_list(ctx, &if_stmt->then_list);
4640 if (LLVMGetInsertBlock(ctx->builder))
4641 LLVMBuildBr(ctx->builder, merge_block);
4642
4643 if (!exec_list_is_empty(&if_stmt->else_list)) {
4644 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4645 visit_cf_list(ctx, &if_stmt->else_list);
4646 if (LLVMGetInsertBlock(ctx->builder))
4647 LLVMBuildBr(ctx->builder, merge_block);
4648 }
4649
4650 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4651 }
4652
4653 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4654 {
4655 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4656 LLVMBasicBlockRef break_parent = ctx->break_block;
4657
4658 ctx->continue_block =
4659 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4660 ctx->break_block =
4661 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4662
4663 LLVMBuildBr(ctx->builder, ctx->continue_block);
4664 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4665 visit_cf_list(ctx, &loop->body);
4666
4667 if (LLVMGetInsertBlock(ctx->builder))
4668 LLVMBuildBr(ctx->builder, ctx->continue_block);
4669 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4670
4671 ctx->continue_block = continue_parent;
4672 ctx->break_block = break_parent;
4673 }
4674
4675 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4676 struct exec_list *list)
4677 {
4678 foreach_list_typed(nir_cf_node, node, node, list)
4679 {
4680 switch (node->type) {
4681 case nir_cf_node_block:
4682 visit_block(ctx, nir_cf_node_as_block(node));
4683 break;
4684
4685 case nir_cf_node_if:
4686 visit_if(ctx, nir_cf_node_as_if(node));
4687 break;
4688
4689 case nir_cf_node_loop:
4690 visit_loop(ctx, nir_cf_node_as_loop(node));
4691 break;
4692
4693 default:
4694 assert(0);
4695 }
4696 }
4697 }
4698
4699 static void
4700 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4701 struct nir_variable *variable)
4702 {
4703 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4704 LLVMValueRef t_offset;
4705 LLVMValueRef t_list;
4706 LLVMValueRef input;
4707 LLVMValueRef buffer_index;
4708 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4709 int idx = variable->data.location;
4710 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4711
4712 variable->data.driver_location = idx * 4;
4713
4714 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4715 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4716 ctx->start_instance, "");
4717 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4718 ctx->shader_info->vs.vgpr_comp_cnt);
4719 } else
4720 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4721 ctx->base_vertex, "");
4722
4723 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4724 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4725
4726 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4727
4728 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4729 buffer_index,
4730 LLVMConstInt(ctx->i32, 0, false),
4731 true);
4732
4733 for (unsigned chan = 0; chan < 4; chan++) {
4734 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4735 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4736 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4737 input, llvm_chan, ""));
4738 }
4739 }
4740 }
4741
4742 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4743 unsigned attr,
4744 LLVMValueRef interp_param,
4745 LLVMValueRef prim_mask,
4746 LLVMValueRef result[4])
4747 {
4748 LLVMValueRef attr_number;
4749 unsigned chan;
4750 LLVMValueRef i, j;
4751 bool interp = interp_param != NULL;
4752
4753 attr_number = LLVMConstInt(ctx->i32, attr, false);
4754
4755 /* fs.constant returns the param from the middle vertex, so it's not
4756 * really useful for flat shading. It's meant to be used for custom
4757 * interpolation (but the intrinsic can't fetch from the other two
4758 * vertices).
4759 *
4760 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4761 * to do the right thing. The only reason we use fs.constant is that
4762 * fs.interp cannot be used on integers, because they can be equal
4763 * to NaN.
4764 */
4765 if (interp) {
4766 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4767 LLVMVectorType(ctx->f32, 2), "");
4768
4769 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4770 ctx->i32zero, "");
4771 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4772 ctx->i32one, "");
4773 }
4774
4775 for (chan = 0; chan < 4; chan++) {
4776 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4777
4778 if (interp) {
4779 result[chan] = ac_build_fs_interp(&ctx->ac,
4780 llvm_chan,
4781 attr_number,
4782 prim_mask, i, j);
4783 } else {
4784 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4785 LLVMConstInt(ctx->i32, 2, false),
4786 llvm_chan,
4787 attr_number,
4788 prim_mask);
4789 }
4790 }
4791 }
4792
4793 static void
4794 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4795 struct nir_variable *variable)
4796 {
4797 int idx = variable->data.location;
4798 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4799 LLVMValueRef interp;
4800
4801 variable->data.driver_location = idx * 4;
4802 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4803
4804 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4805 unsigned interp_type;
4806 if (variable->data.sample) {
4807 interp_type = INTERP_SAMPLE;
4808 ctx->shader_info->fs.force_persample = true;
4809 } else if (variable->data.centroid)
4810 interp_type = INTERP_CENTROID;
4811 else
4812 interp_type = INTERP_CENTER;
4813
4814 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4815 } else
4816 interp = NULL;
4817
4818 for (unsigned i = 0; i < attrib_count; ++i)
4819 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4820
4821 }
4822
4823 static void
4824 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4825 struct nir_variable *variable)
4826 {
4827 switch (ctx->stage) {
4828 case MESA_SHADER_VERTEX:
4829 handle_vs_input_decl(ctx, variable);
4830 break;
4831 case MESA_SHADER_FRAGMENT:
4832 handle_fs_input_decl(ctx, variable);
4833 break;
4834 default:
4835 break;
4836 }
4837
4838 }
4839
4840 static void
4841 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4842 struct nir_shader *nir)
4843 {
4844 unsigned index = 0;
4845 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4846 LLVMValueRef interp_param;
4847 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4848
4849 if (!(ctx->input_mask & (1ull << i)))
4850 continue;
4851
4852 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4853 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4854 interp_param = *inputs;
4855 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4856 inputs);
4857
4858 if (!interp_param)
4859 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4860 ++index;
4861 } else if (i == VARYING_SLOT_POS) {
4862 for(int i = 0; i < 3; ++i)
4863 inputs[i] = ctx->frag_pos[i];
4864
4865 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4866 }
4867 }
4868 ctx->shader_info->fs.num_interp = index;
4869 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4870 ctx->shader_info->fs.has_pcoord = true;
4871 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4872 ctx->shader_info->fs.prim_id_input = true;
4873 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4874 ctx->shader_info->fs.layer_input = true;
4875 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4876 }
4877
4878 static LLVMValueRef
4879 ac_build_alloca(struct nir_to_llvm_context *ctx,
4880 LLVMTypeRef type,
4881 const char *name)
4882 {
4883 LLVMBuilderRef builder = ctx->builder;
4884 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4885 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4886 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4887 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4888 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4889 LLVMValueRef res;
4890
4891 if (first_instr) {
4892 LLVMPositionBuilderBefore(first_builder, first_instr);
4893 } else {
4894 LLVMPositionBuilderAtEnd(first_builder, first_block);
4895 }
4896
4897 res = LLVMBuildAlloca(first_builder, type, name);
4898 LLVMBuildStore(builder, LLVMConstNull(type), res);
4899
4900 LLVMDisposeBuilder(first_builder);
4901
4902 return res;
4903 }
4904
4905 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4906 LLVMTypeRef type,
4907 const char *name)
4908 {
4909 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4910 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4911 return ptr;
4912 }
4913
4914 static void
4915 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4916 struct nir_variable *variable)
4917 {
4918 int idx = variable->data.location + variable->data.index;
4919 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4920 uint64_t mask_attribs;
4921 variable->data.driver_location = idx * 4;
4922
4923 /* tess ctrl has it's own load/store paths for outputs */
4924 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4925 return;
4926
4927 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4928 if (ctx->stage == MESA_SHADER_VERTEX ||
4929 ctx->stage == MESA_SHADER_TESS_EVAL ||
4930 ctx->stage == MESA_SHADER_GEOMETRY) {
4931 if (idx == VARYING_SLOT_CLIP_DIST0) {
4932 int length = ctx->num_output_clips + ctx->num_output_culls;
4933 if (ctx->stage == MESA_SHADER_VERTEX) {
4934 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4935 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4936 }
4937 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4938 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4939 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4940 }
4941
4942 if (length > 4)
4943 attrib_count = 2;
4944 else
4945 attrib_count = 1;
4946 mask_attribs = 1ull << idx;
4947 }
4948 }
4949
4950 for (unsigned i = 0; i < attrib_count; ++i) {
4951 for (unsigned chan = 0; chan < 4; chan++) {
4952 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4953 si_build_alloca_undef(ctx, ctx->f32, "");
4954 }
4955 }
4956 ctx->output_mask |= mask_attribs;
4957 }
4958
4959 static void
4960 setup_locals(struct nir_to_llvm_context *ctx,
4961 struct nir_function *func)
4962 {
4963 int i, j;
4964 ctx->num_locals = 0;
4965 nir_foreach_variable(variable, &func->impl->locals) {
4966 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4967 variable->data.driver_location = ctx->num_locals * 4;
4968 ctx->num_locals += attrib_count;
4969 }
4970 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4971 if (!ctx->locals)
4972 return;
4973
4974 for (i = 0; i < ctx->num_locals; i++) {
4975 for (j = 0; j < 4; j++) {
4976 ctx->locals[i * 4 + j] =
4977 si_build_alloca_undef(ctx, ctx->f32, "temp");
4978 }
4979 }
4980 }
4981
4982 static LLVMValueRef
4983 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4984 {
4985 v = to_float(ctx, v);
4986 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4987 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4988 }
4989
4990
4991 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4992 LLVMValueRef src0, LLVMValueRef src1)
4993 {
4994 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4995 LLVMValueRef comp[2];
4996
4997 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4998 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4999 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5000 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5001 }
5002
5003 /* Initialize arguments for the shader export intrinsic */
5004 static void
5005 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5006 LLVMValueRef *values,
5007 unsigned target,
5008 struct ac_export_args *args)
5009 {
5010 /* Default is 0xf. Adjusted below depending on the format. */
5011 args->enabled_channels = 0xf;
5012
5013 /* Specify whether the EXEC mask represents the valid mask */
5014 args->valid_mask = 0;
5015
5016 /* Specify whether this is the last export */
5017 args->done = 0;
5018
5019 /* Specify the target we are exporting */
5020 args->target = target;
5021
5022 args->compr = false;
5023 args->out[0] = LLVMGetUndef(ctx->f32);
5024 args->out[1] = LLVMGetUndef(ctx->f32);
5025 args->out[2] = LLVMGetUndef(ctx->f32);
5026 args->out[3] = LLVMGetUndef(ctx->f32);
5027
5028 if (!values)
5029 return;
5030
5031 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5032 LLVMValueRef val[4];
5033 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5034 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5035 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5036
5037 switch(col_format) {
5038 case V_028714_SPI_SHADER_ZERO:
5039 args->enabled_channels = 0; /* writemask */
5040 args->target = V_008DFC_SQ_EXP_NULL;
5041 break;
5042
5043 case V_028714_SPI_SHADER_32_R:
5044 args->enabled_channels = 1;
5045 args->out[0] = values[0];
5046 break;
5047
5048 case V_028714_SPI_SHADER_32_GR:
5049 args->enabled_channels = 0x3;
5050 args->out[0] = values[0];
5051 args->out[1] = values[1];
5052 break;
5053
5054 case V_028714_SPI_SHADER_32_AR:
5055 args->enabled_channels = 0x9;
5056 args->out[0] = values[0];
5057 args->out[3] = values[3];
5058 break;
5059
5060 case V_028714_SPI_SHADER_FP16_ABGR:
5061 args->compr = 1;
5062
5063 for (unsigned chan = 0; chan < 2; chan++) {
5064 LLVMValueRef pack_args[2] = {
5065 values[2 * chan],
5066 values[2 * chan + 1]
5067 };
5068 LLVMValueRef packed;
5069
5070 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5071 args->out[chan] = packed;
5072 }
5073 break;
5074
5075 case V_028714_SPI_SHADER_UNORM16_ABGR:
5076 for (unsigned chan = 0; chan < 4; chan++) {
5077 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5078 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5079 LLVMConstReal(ctx->f32, 65535), "");
5080 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5081 LLVMConstReal(ctx->f32, 0.5), "");
5082 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5083 ctx->i32, "");
5084 }
5085
5086 args->compr = 1;
5087 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5088 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5089 break;
5090
5091 case V_028714_SPI_SHADER_SNORM16_ABGR:
5092 for (unsigned chan = 0; chan < 4; chan++) {
5093 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
5094 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5095 LLVMConstReal(ctx->f32, 32767), "");
5096
5097 /* If positive, add 0.5, else add -0.5. */
5098 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5099 LLVMBuildSelect(ctx->builder,
5100 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5101 val[chan], ctx->f32zero, ""),
5102 LLVMConstReal(ctx->f32, 0.5),
5103 LLVMConstReal(ctx->f32, -0.5), ""), "");
5104 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5105 }
5106
5107 args->compr = 1;
5108 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5109 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5110 break;
5111
5112 case V_028714_SPI_SHADER_UINT16_ABGR: {
5113 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5114
5115 for (unsigned chan = 0; chan < 4; chan++) {
5116 val[chan] = to_integer(ctx, values[chan]);
5117 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
5118 }
5119
5120 args->compr = 1;
5121 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5122 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5123 break;
5124 }
5125
5126 case V_028714_SPI_SHADER_SINT16_ABGR: {
5127 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5128 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5129
5130 /* Clamp. */
5131 for (unsigned chan = 0; chan < 4; chan++) {
5132 val[chan] = to_integer(ctx, values[chan]);
5133 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
5134 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
5135 }
5136
5137 args->compr = 1;
5138 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5139 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5140 break;
5141 }
5142
5143 default:
5144 case V_028714_SPI_SHADER_32_ABGR:
5145 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5146 break;
5147 }
5148 } else
5149 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5150
5151 for (unsigned i = 0; i < 4; ++i)
5152 args->out[i] = to_float(ctx, args->out[i]);
5153 }
5154
5155 static void
5156 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5157 struct ac_vs_output_info *outinfo)
5158 {
5159 uint32_t param_count = 0;
5160 unsigned target;
5161 unsigned pos_idx, num_pos_exports = 0;
5162 struct ac_export_args args, pos_args[4] = {};
5163 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5164 int i;
5165
5166 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5167 sizeof(outinfo->vs_output_param_offset));
5168
5169 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5170 LLVMValueRef slots[8];
5171 unsigned j;
5172
5173 if (outinfo->cull_dist_mask)
5174 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5175
5176 i = VARYING_SLOT_CLIP_DIST0;
5177 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5178 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5179 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5180
5181 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5182 slots[i] = LLVMGetUndef(ctx->f32);
5183
5184 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5185 target = V_008DFC_SQ_EXP_POS + 3;
5186 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5187 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5188 &args, sizeof(args));
5189 }
5190
5191 target = V_008DFC_SQ_EXP_POS + 2;
5192 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5193 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5194 &args, sizeof(args));
5195
5196 }
5197
5198 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5199 LLVMValueRef values[4];
5200 if (!(ctx->output_mask & (1ull << i)))
5201 continue;
5202
5203 for (unsigned j = 0; j < 4; j++)
5204 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5205 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5206
5207 if (i == VARYING_SLOT_POS) {
5208 target = V_008DFC_SQ_EXP_POS;
5209 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5210 continue;
5211 } else if (i == VARYING_SLOT_PSIZ) {
5212 outinfo->writes_pointsize = true;
5213 psize_value = values[0];
5214 continue;
5215 } else if (i == VARYING_SLOT_LAYER) {
5216 outinfo->writes_layer = true;
5217 layer_value = values[0];
5218 target = V_008DFC_SQ_EXP_PARAM + param_count;
5219 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5220 param_count++;
5221 } else if (i == VARYING_SLOT_VIEWPORT) {
5222 outinfo->writes_viewport_index = true;
5223 viewport_index_value = values[0];
5224 continue;
5225 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5226 target = V_008DFC_SQ_EXP_PARAM + param_count;
5227 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5228 param_count++;
5229 } else if (i >= VARYING_SLOT_VAR0) {
5230 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5231 target = V_008DFC_SQ_EXP_PARAM + param_count;
5232 outinfo->vs_output_param_offset[i] = param_count;
5233 param_count++;
5234 }
5235
5236 si_llvm_init_export_args(ctx, values, target, &args);
5237
5238 if (target >= V_008DFC_SQ_EXP_POS &&
5239 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5240 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5241 &args, sizeof(args));
5242 } else {
5243 ac_build_export(&ctx->ac, &args);
5244 }
5245 }
5246
5247 /* We need to add the position output manually if it's missing. */
5248 if (!pos_args[0].out[0]) {
5249 pos_args[0].enabled_channels = 0xf;
5250 pos_args[0].valid_mask = 0;
5251 pos_args[0].done = 0;
5252 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5253 pos_args[0].compr = 0;
5254 pos_args[0].out[0] = ctx->f32zero; /* X */
5255 pos_args[0].out[1] = ctx->f32zero; /* Y */
5256 pos_args[0].out[2] = ctx->f32zero; /* Z */
5257 pos_args[0].out[3] = ctx->f32one; /* W */
5258 }
5259
5260 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5261 (outinfo->writes_layer == true ? 4 : 0) |
5262 (outinfo->writes_viewport_index == true ? 8 : 0));
5263 if (mask) {
5264 pos_args[1].enabled_channels = mask;
5265 pos_args[1].valid_mask = 0;
5266 pos_args[1].done = 0;
5267 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5268 pos_args[1].compr = 0;
5269 pos_args[1].out[0] = ctx->f32zero; /* X */
5270 pos_args[1].out[1] = ctx->f32zero; /* Y */
5271 pos_args[1].out[2] = ctx->f32zero; /* Z */
5272 pos_args[1].out[3] = ctx->f32zero; /* W */
5273
5274 if (outinfo->writes_pointsize == true)
5275 pos_args[1].out[0] = psize_value;
5276 if (outinfo->writes_layer == true)
5277 pos_args[1].out[2] = layer_value;
5278 if (outinfo->writes_viewport_index == true)
5279 pos_args[1].out[3] = viewport_index_value;
5280 }
5281 for (i = 0; i < 4; i++) {
5282 if (pos_args[i].out[0])
5283 num_pos_exports++;
5284 }
5285
5286 pos_idx = 0;
5287 for (i = 0; i < 4; i++) {
5288 if (!pos_args[i].out[0])
5289 continue;
5290
5291 /* Specify the target we are exporting */
5292 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5293 if (pos_idx == num_pos_exports)
5294 pos_args[i].done = 1;
5295 ac_build_export(&ctx->ac, &pos_args[i]);
5296 }
5297
5298 outinfo->pos_exports = num_pos_exports;
5299 outinfo->param_exports = param_count;
5300 }
5301
5302 static void
5303 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5304 struct ac_es_output_info *outinfo)
5305 {
5306 int j;
5307 uint64_t max_output_written = 0;
5308 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5309 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5310 int param_index;
5311 int length = 4;
5312
5313 if (!(ctx->output_mask & (1ull << i)))
5314 continue;
5315
5316 if (i == VARYING_SLOT_CLIP_DIST0)
5317 length = ctx->num_output_clips + ctx->num_output_culls;
5318
5319 param_index = shader_io_get_unique_index(i);
5320
5321 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5322
5323 for (j = 0; j < length; j++) {
5324 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5325 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5326
5327 ac_build_buffer_store_dword(&ctx->ac,
5328 ctx->esgs_ring,
5329 out_val, 1,
5330 NULL, ctx->es2gs_offset,
5331 (4 * param_index + j) * 4,
5332 1, 1, true, true);
5333 }
5334 }
5335 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5336 }
5337
5338 static void
5339 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5340 {
5341 LLVMValueRef vertex_id = ctx->rel_auto_id;
5342 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5343 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5344 vertex_dw_stride, "");
5345
5346 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5347 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5348 int length = 4;
5349
5350 if (!(ctx->output_mask & (1ull << i)))
5351 continue;
5352
5353 if (i == VARYING_SLOT_CLIP_DIST0)
5354 length = ctx->num_output_clips + ctx->num_output_culls;
5355 int param = shader_io_get_unique_index(i);
5356 mark_tess_output(ctx, false, param);
5357 if (length > 4)
5358 mark_tess_output(ctx, false, param + 1);
5359 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5360 LLVMConstInt(ctx->i32, param * 4, false),
5361 "");
5362 for (unsigned j = 0; j < length; j++) {
5363 lds_store(ctx, dw_addr,
5364 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5365 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5366 }
5367 }
5368 }
5369
5370 struct ac_build_if_state
5371 {
5372 struct nir_to_llvm_context *ctx;
5373 LLVMValueRef condition;
5374 LLVMBasicBlockRef entry_block;
5375 LLVMBasicBlockRef true_block;
5376 LLVMBasicBlockRef false_block;
5377 LLVMBasicBlockRef merge_block;
5378 };
5379
5380 static LLVMBasicBlockRef
5381 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5382 {
5383 LLVMBasicBlockRef current_block;
5384 LLVMBasicBlockRef next_block;
5385 LLVMBasicBlockRef new_block;
5386
5387 /* get current basic block */
5388 current_block = LLVMGetInsertBlock(ctx->builder);
5389
5390 /* chqeck if there's another block after this one */
5391 next_block = LLVMGetNextBasicBlock(current_block);
5392 if (next_block) {
5393 /* insert the new block before the next block */
5394 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5395 }
5396 else {
5397 /* append new block after current block */
5398 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5399 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5400 }
5401 return new_block;
5402 }
5403
5404 static void
5405 ac_nir_build_if(struct ac_build_if_state *ifthen,
5406 struct nir_to_llvm_context *ctx,
5407 LLVMValueRef condition)
5408 {
5409 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5410
5411 memset(ifthen, 0, sizeof *ifthen);
5412 ifthen->ctx = ctx;
5413 ifthen->condition = condition;
5414 ifthen->entry_block = block;
5415
5416 /* create endif/merge basic block for the phi functions */
5417 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5418
5419 /* create/insert true_block before merge_block */
5420 ifthen->true_block =
5421 LLVMInsertBasicBlockInContext(ctx->context,
5422 ifthen->merge_block,
5423 "if-true-block");
5424
5425 /* successive code goes into the true block */
5426 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5427 }
5428
5429 /**
5430 * End a conditional.
5431 */
5432 static void
5433 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5434 {
5435 LLVMBuilderRef builder = ifthen->ctx->builder;
5436
5437 /* Insert branch to the merge block from current block */
5438 LLVMBuildBr(builder, ifthen->merge_block);
5439
5440 /*
5441 * Now patch in the various branch instructions.
5442 */
5443
5444 /* Insert the conditional branch instruction at the end of entry_block */
5445 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5446 if (ifthen->false_block) {
5447 /* we have an else clause */
5448 LLVMBuildCondBr(builder, ifthen->condition,
5449 ifthen->true_block, ifthen->false_block);
5450 }
5451 else {
5452 /* no else clause */
5453 LLVMBuildCondBr(builder, ifthen->condition,
5454 ifthen->true_block, ifthen->merge_block);
5455 }
5456
5457 /* Resume building code at end of the ifthen->merge_block */
5458 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5459 }
5460
5461 static void
5462 write_tess_factors(struct nir_to_llvm_context *ctx)
5463 {
5464 unsigned stride, outer_comps, inner_comps;
5465 struct ac_build_if_state if_ctx, inner_if_ctx;
5466 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5467 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5468 unsigned tess_inner_index, tess_outer_index;
5469 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5470 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5471 int i;
5472 emit_barrier(ctx);
5473
5474 switch (ctx->options->key.tcs.primitive_mode) {
5475 case GL_ISOLINES:
5476 stride = 2;
5477 outer_comps = 2;
5478 inner_comps = 0;
5479 break;
5480 case GL_TRIANGLES:
5481 stride = 4;
5482 outer_comps = 3;
5483 inner_comps = 1;
5484 break;
5485 case GL_QUADS:
5486 stride = 6;
5487 outer_comps = 4;
5488 inner_comps = 2;
5489 break;
5490 default:
5491 return;
5492 }
5493
5494 ac_nir_build_if(&if_ctx, ctx,
5495 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5496 invocation_id, ctx->i32zero, ""));
5497
5498 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5499 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5500
5501 mark_tess_output(ctx, true, tess_inner_index);
5502 mark_tess_output(ctx, true, tess_outer_index);
5503 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5504 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5505 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5506 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5507 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5508
5509 for (i = 0; i < 4; i++) {
5510 inner[i] = LLVMGetUndef(ctx->i32);
5511 outer[i] = LLVMGetUndef(ctx->i32);
5512 }
5513
5514 // LINES reverseal
5515 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5516 outer[0] = out[1] = lds_load(ctx, lds_outer);
5517 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5518 LLVMConstInt(ctx->i32, 1, false), "");
5519 outer[1] = out[0] = lds_load(ctx, lds_outer);
5520 } else {
5521 for (i = 0; i < outer_comps; i++) {
5522 outer[i] = out[i] =
5523 lds_load(ctx, lds_outer);
5524 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5525 LLVMConstInt(ctx->i32, 1, false), "");
5526 }
5527 for (i = 0; i < inner_comps; i++) {
5528 inner[i] = out[outer_comps+i] =
5529 lds_load(ctx, lds_inner);
5530 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5531 LLVMConstInt(ctx->i32, 1, false), "");
5532 }
5533 }
5534
5535 /* Convert the outputs to vectors for stores. */
5536 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5537 vec1 = NULL;
5538
5539 if (stride > 4)
5540 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5541
5542
5543 buffer = ctx->hs_ring_tess_factor;
5544 tf_base = ctx->tess_factor_offset;
5545 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5546 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5547
5548 ac_nir_build_if(&inner_if_ctx, ctx,
5549 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5550 rel_patch_id, ctx->i32zero, ""));
5551
5552 /* Store the dynamic HS control word. */
5553 ac_build_buffer_store_dword(&ctx->ac, buffer,
5554 LLVMConstInt(ctx->i32, 0x80000000, false),
5555 1, ctx->i32zero, tf_base,
5556 0, 1, 0, true, false);
5557 ac_nir_build_endif(&inner_if_ctx);
5558
5559 /* Store the tessellation factors. */
5560 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5561 MIN2(stride, 4), byteoffset, tf_base,
5562 4, 1, 0, true, false);
5563 if (vec1)
5564 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5565 stride - 4, byteoffset, tf_base,
5566 20, 1, 0, true, false);
5567
5568 //TODO store to offchip for TES to read - only if TES reads them
5569 if (1) {
5570 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5571 LLVMValueRef tf_inner_offset;
5572 unsigned param_outer, param_inner;
5573
5574 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5575 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5576 LLVMConstInt(ctx->i32, param_outer, 0));
5577
5578 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5579 util_next_power_of_two(outer_comps));
5580
5581 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5582 outer_comps, tf_outer_offset,
5583 ctx->oc_lds, 0, 1, 0, true, false);
5584 if (inner_comps) {
5585 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5586 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5587 LLVMConstInt(ctx->i32, param_inner, 0));
5588
5589 inner_vec = inner_comps == 1 ? inner[0] :
5590 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5591 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5592 inner_comps, tf_inner_offset,
5593 ctx->oc_lds, 0, 1, 0, true, false);
5594 }
5595 }
5596 ac_nir_build_endif(&if_ctx);
5597 }
5598
5599 static void
5600 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5601 {
5602 write_tess_factors(ctx);
5603 }
5604
5605 static bool
5606 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5607 LLVMValueRef *color, unsigned param, bool is_last,
5608 struct ac_export_args *args)
5609 {
5610 /* Export */
5611 si_llvm_init_export_args(ctx, color, param,
5612 args);
5613
5614 if (is_last) {
5615 args->valid_mask = 1; /* whether the EXEC mask is valid */
5616 args->done = 1; /* DONE bit */
5617 } else if (!args->enabled_channels)
5618 return false; /* unnecessary NULL export */
5619
5620 return true;
5621 }
5622
5623 static void
5624 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5625 LLVMValueRef depth, LLVMValueRef stencil,
5626 LLVMValueRef samplemask)
5627 {
5628 struct ac_export_args args;
5629
5630 args.enabled_channels = 0;
5631 args.valid_mask = 1;
5632 args.done = 1;
5633 args.target = V_008DFC_SQ_EXP_MRTZ;
5634 args.compr = false;
5635
5636 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5637 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5638 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5639 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5640
5641 if (depth) {
5642 args.out[0] = depth;
5643 args.enabled_channels |= 0x1;
5644 }
5645
5646 if (stencil) {
5647 args.out[1] = stencil;
5648 args.enabled_channels |= 0x2;
5649 }
5650
5651 if (samplemask) {
5652 args.out[2] = samplemask;
5653 args.enabled_channels |= 0x4;
5654 }
5655
5656 /* SI (except OLAND) has a bug that it only looks
5657 * at the X writemask component. */
5658 if (ctx->options->chip_class == SI &&
5659 ctx->options->family != CHIP_OLAND)
5660 args.enabled_channels |= 0x1;
5661
5662 ac_build_export(&ctx->ac, &args);
5663 }
5664
5665 static void
5666 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5667 {
5668 unsigned index = 0;
5669 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5670 struct ac_export_args color_args[8];
5671
5672 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5673 LLVMValueRef values[4];
5674
5675 if (!(ctx->output_mask & (1ull << i)))
5676 continue;
5677
5678 if (i == FRAG_RESULT_DEPTH) {
5679 ctx->shader_info->fs.writes_z = true;
5680 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
5681 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5682 } else if (i == FRAG_RESULT_STENCIL) {
5683 ctx->shader_info->fs.writes_stencil = true;
5684 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
5685 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5686 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5687 ctx->shader_info->fs.writes_sample_mask = true;
5688 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
5689 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5690 } else {
5691 bool last = false;
5692 for (unsigned j = 0; j < 4; j++)
5693 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5694 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5695
5696 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5697 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5698
5699 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5700 if (ret)
5701 index++;
5702 }
5703 }
5704
5705 for (unsigned i = 0; i < index; i++)
5706 ac_build_export(&ctx->ac, &color_args[i]);
5707 if (depth || stencil || samplemask)
5708 si_export_mrt_z(ctx, depth, stencil, samplemask);
5709 else if (!index) {
5710 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5711 ac_build_export(&ctx->ac, &color_args[0]);
5712 }
5713
5714 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5715 }
5716
5717 static void
5718 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5719 {
5720 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5721 }
5722
5723 static void
5724 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5725 {
5726 switch (ctx->stage) {
5727 case MESA_SHADER_VERTEX:
5728 if (ctx->options->key.vs.as_ls)
5729 handle_ls_outputs_post(ctx);
5730 else if (ctx->options->key.vs.as_es)
5731 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5732 else
5733 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5734 break;
5735 case MESA_SHADER_FRAGMENT:
5736 handle_fs_outputs_post(ctx);
5737 break;
5738 case MESA_SHADER_GEOMETRY:
5739 emit_gs_epilogue(ctx);
5740 break;
5741 case MESA_SHADER_TESS_CTRL:
5742 handle_tcs_outputs_post(ctx);
5743 break;
5744 case MESA_SHADER_TESS_EVAL:
5745 if (ctx->options->key.tes.as_es)
5746 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5747 else
5748 handle_vs_outputs_post(ctx, &ctx->shader_info->tes.outinfo);
5749 break;
5750 default:
5751 break;
5752 }
5753 }
5754
5755 static void
5756 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5757 struct nir_variable *variable, uint32_t *offset, int idx)
5758 {
5759 unsigned size = glsl_count_attribute_slots(variable->type, false);
5760 variable->data.driver_location = *offset;
5761 *offset += size;
5762 }
5763
5764 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5765 {
5766 LLVMPassManagerRef passmgr;
5767 /* Create the pass manager */
5768 passmgr = LLVMCreateFunctionPassManagerForModule(
5769 ctx->module);
5770
5771 /* This pass should eliminate all the load and store instructions */
5772 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5773
5774 /* Add some optimization passes */
5775 LLVMAddScalarReplAggregatesPass(passmgr);
5776 LLVMAddLICMPass(passmgr);
5777 LLVMAddAggressiveDCEPass(passmgr);
5778 LLVMAddCFGSimplificationPass(passmgr);
5779 LLVMAddInstructionCombiningPass(passmgr);
5780
5781 /* Run the pass */
5782 LLVMInitializeFunctionPassManager(passmgr);
5783 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5784 LLVMFinalizeFunctionPassManager(passmgr);
5785
5786 LLVMDisposeBuilder(ctx->builder);
5787 LLVMDisposePassManager(passmgr);
5788 }
5789
5790 static void
5791 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
5792 {
5793 struct ac_vs_output_info *outinfo;
5794
5795 if (ctx->stage == MESA_SHADER_FRAGMENT ||
5796 ctx->stage == MESA_SHADER_COMPUTE ||
5797 ctx->stage == MESA_SHADER_TESS_CTRL ||
5798 ctx->stage == MESA_SHADER_GEOMETRY)
5799 return;
5800
5801 if (ctx->stage == MESA_SHADER_VERTEX) {
5802 if (ctx->options->key.vs.as_ls ||
5803 ctx->options->key.vs.as_es)
5804 return;
5805 outinfo = &ctx->shader_info->vs.outinfo;
5806 }
5807
5808 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5809 if (ctx->options->key.vs.as_es)
5810 return;
5811 outinfo = &ctx->shader_info->tes.outinfo;
5812 }
5813
5814 ac_optimize_vs_outputs(&ctx->ac,
5815 ctx->main_function,
5816 outinfo->vs_output_param_offset,
5817 VARYING_SLOT_MAX,
5818 &outinfo->param_exports);
5819 }
5820
5821 static void
5822 ac_setup_rings(struct nir_to_llvm_context *ctx)
5823 {
5824 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5825 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5826 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5827 }
5828
5829 if (ctx->is_gs_copy_shader) {
5830 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5831 }
5832 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5833 LLVMValueRef tmp;
5834 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5835 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5836
5837 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5838
5839 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5840 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5841 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5842 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5843
5844 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5845 }
5846
5847 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5848 ctx->stage == MESA_SHADER_TESS_EVAL) {
5849 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5850 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5851 }
5852 }
5853
5854 static unsigned
5855 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
5856 struct nir_shader *nir)
5857 {
5858 switch (nir->stage) {
5859 case MESA_SHADER_TESS_CTRL:
5860 return chip_class >= CIK ? 128 : 64;
5861 case MESA_SHADER_GEOMETRY:
5862 return 64;
5863 case MESA_SHADER_COMPUTE:
5864 break;
5865 default:
5866 return 0;
5867 }
5868
5869 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
5870 nir->info.cs.local_size[1] *
5871 nir->info.cs.local_size[2];
5872 return max_workgroup_size;
5873 }
5874
5875 static
5876 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5877 struct nir_shader *nir,
5878 struct ac_shader_variant_info *shader_info,
5879 const struct ac_nir_compiler_options *options)
5880 {
5881 struct nir_to_llvm_context ctx = {0};
5882 struct nir_function *func;
5883 unsigned i;
5884 ctx.options = options;
5885 ctx.shader_info = shader_info;
5886 ctx.context = LLVMContextCreate();
5887 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5888
5889 ac_llvm_context_init(&ctx.ac, ctx.context);
5890 ctx.ac.module = ctx.module;
5891
5892 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5893
5894 memset(shader_info, 0, sizeof(*shader_info));
5895
5896 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5897
5898 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5899
5900 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5901 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5902 LLVMSetDataLayout(ctx.module, data_layout_str);
5903 LLVMDisposeTargetData(data_layout);
5904 LLVMDisposeMessage(data_layout_str);
5905
5906 setup_types(&ctx);
5907
5908 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5909 ctx.ac.builder = ctx.builder;
5910 ctx.stage = nir->stage;
5911 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
5912
5913 for (i = 0; i < AC_UD_MAX_SETS; i++)
5914 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5915 for (i = 0; i < AC_UD_MAX_UD; i++)
5916 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5917
5918 create_function(&ctx);
5919
5920 if (nir->stage == MESA_SHADER_COMPUTE) {
5921 int num_shared = 0;
5922 nir_foreach_variable(variable, &nir->shared)
5923 num_shared++;
5924 if (num_shared) {
5925 int idx = 0;
5926 uint32_t shared_size = 0;
5927 LLVMValueRef var;
5928 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5929 nir_foreach_variable(variable, &nir->shared) {
5930 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5931 idx++;
5932 }
5933
5934 shared_size *= 16;
5935 var = LLVMAddGlobalInAddressSpace(ctx.module,
5936 LLVMArrayType(ctx.i8, shared_size),
5937 "compute_lds",
5938 LOCAL_ADDR_SPACE);
5939 LLVMSetAlignment(var, 4);
5940 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5941 }
5942 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5943 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5944
5945 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
5946 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5947 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
5948 }
5949
5950 ac_setup_rings(&ctx);
5951
5952 nir_foreach_variable(variable, &nir->inputs)
5953 handle_shader_input_decl(&ctx, variable);
5954
5955 if (nir->stage == MESA_SHADER_FRAGMENT)
5956 handle_fs_inputs_pre(&ctx, nir);
5957
5958 ctx.num_output_clips = nir->info.clip_distance_array_size;
5959 ctx.num_output_culls = nir->info.cull_distance_array_size;
5960
5961 nir_foreach_variable(variable, &nir->outputs)
5962 handle_shader_output_decl(&ctx, variable);
5963
5964 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5965 _mesa_key_pointer_equal);
5966 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5967 _mesa_key_pointer_equal);
5968
5969 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5970
5971 setup_locals(&ctx, func);
5972
5973 visit_cf_list(&ctx, &func->impl->body);
5974 phi_post_pass(&ctx);
5975
5976 handle_shader_outputs_post(&ctx);
5977 LLVMBuildRetVoid(ctx.builder);
5978
5979 ac_llvm_finalize_module(&ctx);
5980
5981 ac_nir_eliminate_const_vs_outputs(&ctx);
5982 free(ctx.locals);
5983 ralloc_free(ctx.defs);
5984 ralloc_free(ctx.phis);
5985
5986 if (nir->stage == MESA_SHADER_GEOMETRY) {
5987 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
5988 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
5989 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5990 nir->info.gs.vertices_out;
5991 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
5992 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
5993 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
5994 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
5995 shader_info->vs.outputs_written = ctx.tess_outputs_written;
5996 }
5997
5998 return ctx.module;
5999 }
6000
6001 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6002 {
6003 unsigned *retval = (unsigned *)context;
6004 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6005 char *description = LLVMGetDiagInfoDescription(di);
6006
6007 if (severity == LLVMDSError) {
6008 *retval = 1;
6009 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6010 description);
6011 }
6012
6013 LLVMDisposeMessage(description);
6014 }
6015
6016 static unsigned ac_llvm_compile(LLVMModuleRef M,
6017 struct ac_shader_binary *binary,
6018 LLVMTargetMachineRef tm)
6019 {
6020 unsigned retval = 0;
6021 char *err;
6022 LLVMContextRef llvm_ctx;
6023 LLVMMemoryBufferRef out_buffer;
6024 unsigned buffer_size;
6025 const char *buffer_data;
6026 LLVMBool mem_err;
6027
6028 /* Setup Diagnostic Handler*/
6029 llvm_ctx = LLVMGetModuleContext(M);
6030
6031 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6032 &retval);
6033
6034 /* Compile IR*/
6035 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6036 &err, &out_buffer);
6037
6038 /* Process Errors/Warnings */
6039 if (mem_err) {
6040 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6041 free(err);
6042 retval = 1;
6043 goto out;
6044 }
6045
6046 /* Extract Shader Code*/
6047 buffer_size = LLVMGetBufferSize(out_buffer);
6048 buffer_data = LLVMGetBufferStart(out_buffer);
6049
6050 ac_elf_read(buffer_data, buffer_size, binary);
6051
6052 /* Clean up */
6053 LLVMDisposeMemoryBuffer(out_buffer);
6054
6055 out:
6056 return retval;
6057 }
6058
6059 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6060 LLVMModuleRef llvm_module,
6061 struct ac_shader_binary *binary,
6062 struct ac_shader_config *config,
6063 struct ac_shader_variant_info *shader_info,
6064 gl_shader_stage stage,
6065 bool dump_shader, bool supports_spill)
6066 {
6067 if (dump_shader)
6068 ac_dump_module(llvm_module);
6069
6070 memset(binary, 0, sizeof(*binary));
6071 int v = ac_llvm_compile(llvm_module, binary, tm);
6072 if (v) {
6073 fprintf(stderr, "compile failed\n");
6074 }
6075
6076 if (dump_shader)
6077 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6078
6079 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6080
6081 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6082 LLVMDisposeModule(llvm_module);
6083 LLVMContextDispose(ctx);
6084
6085 if (stage == MESA_SHADER_FRAGMENT) {
6086 shader_info->num_input_vgprs = 0;
6087 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6088 shader_info->num_input_vgprs += 2;
6089 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6090 shader_info->num_input_vgprs += 2;
6091 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6092 shader_info->num_input_vgprs += 2;
6093 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6094 shader_info->num_input_vgprs += 3;
6095 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6096 shader_info->num_input_vgprs += 2;
6097 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6098 shader_info->num_input_vgprs += 2;
6099 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6100 shader_info->num_input_vgprs += 2;
6101 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6102 shader_info->num_input_vgprs += 1;
6103 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6104 shader_info->num_input_vgprs += 1;
6105 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6106 shader_info->num_input_vgprs += 1;
6107 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6108 shader_info->num_input_vgprs += 1;
6109 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6110 shader_info->num_input_vgprs += 1;
6111 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6112 shader_info->num_input_vgprs += 1;
6113 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6114 shader_info->num_input_vgprs += 1;
6115 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6116 shader_info->num_input_vgprs += 1;
6117 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6118 shader_info->num_input_vgprs += 1;
6119 }
6120 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6121
6122 /* +3 for scratch wave offset and VCC */
6123 config->num_sgprs = MAX2(config->num_sgprs,
6124 shader_info->num_input_sgprs + 3);
6125 }
6126
6127 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6128 struct ac_shader_binary *binary,
6129 struct ac_shader_config *config,
6130 struct ac_shader_variant_info *shader_info,
6131 struct nir_shader *nir,
6132 const struct ac_nir_compiler_options *options,
6133 bool dump_shader)
6134 {
6135
6136 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6137 options);
6138
6139 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6140 switch (nir->stage) {
6141 case MESA_SHADER_COMPUTE:
6142 for (int i = 0; i < 3; ++i)
6143 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6144 break;
6145 case MESA_SHADER_FRAGMENT:
6146 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6147 break;
6148 case MESA_SHADER_GEOMETRY:
6149 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6150 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6151 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6152 shader_info->gs.invocations = nir->info.gs.invocations;
6153 break;
6154 case MESA_SHADER_TESS_EVAL:
6155 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6156 shader_info->tes.spacing = nir->info.tess.spacing;
6157 shader_info->tes.ccw = nir->info.tess.ccw;
6158 shader_info->tes.point_mode = nir->info.tess.point_mode;
6159 shader_info->tes.as_es = options->key.tes.as_es;
6160 break;
6161 case MESA_SHADER_TESS_CTRL:
6162 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6163 break;
6164 case MESA_SHADER_VERTEX:
6165 shader_info->vs.as_es = options->key.vs.as_es;
6166 shader_info->vs.as_ls = options->key.vs.as_ls;
6167 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6168 if (options->key.vs.as_ls)
6169 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6170 break;
6171 default:
6172 break;
6173 }
6174 }
6175
6176 static void
6177 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6178 {
6179 LLVMValueRef args[9];
6180 args[0] = ctx->gsvs_ring;
6181 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6182 args[3] = ctx->i32zero;
6183 args[4] = ctx->i32one; /* OFFEN */
6184 args[5] = ctx->i32zero; /* IDXEN */
6185 args[6] = ctx->i32one; /* GLC */
6186 args[7] = ctx->i32one; /* SLC */
6187 args[8] = ctx->i32zero; /* TFE */
6188
6189 int idx = 0;
6190
6191 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6192 int length = 4;
6193 int slot = idx;
6194 int slot_inc = 1;
6195 if (!(ctx->output_mask & (1ull << i)))
6196 continue;
6197
6198 if (i == VARYING_SLOT_CLIP_DIST0) {
6199 /* unpack clip and cull from a single set of slots */
6200 length = ctx->num_output_clips + ctx->num_output_culls;
6201 if (length > 4)
6202 slot_inc = 2;
6203 }
6204
6205 for (unsigned j = 0; j < length; j++) {
6206 LLVMValueRef value;
6207 args[2] = LLVMConstInt(ctx->i32,
6208 (slot * 4 + j) *
6209 ctx->gs_max_out_vertices * 16 * 4, false);
6210
6211 value = ac_build_intrinsic(&ctx->ac,
6212 "llvm.SI.buffer.load.dword.i32.i32",
6213 ctx->i32, args, 9,
6214 AC_FUNC_ATTR_READONLY |
6215 AC_FUNC_ATTR_LEGACY);
6216
6217 LLVMBuildStore(ctx->builder,
6218 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6219 }
6220 idx += slot_inc;
6221 }
6222 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
6223 }
6224
6225 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6226 struct nir_shader *geom_shader,
6227 struct ac_shader_binary *binary,
6228 struct ac_shader_config *config,
6229 struct ac_shader_variant_info *shader_info,
6230 const struct ac_nir_compiler_options *options,
6231 bool dump_shader)
6232 {
6233 struct nir_to_llvm_context ctx = {0};
6234 ctx.context = LLVMContextCreate();
6235 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6236 ctx.options = options;
6237 ctx.shader_info = shader_info;
6238
6239 ac_llvm_context_init(&ctx.ac, ctx.context);
6240 ctx.ac.module = ctx.module;
6241
6242 ctx.is_gs_copy_shader = true;
6243 LLVMSetTarget(ctx.module, "amdgcn--");
6244 setup_types(&ctx);
6245
6246 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6247 ctx.ac.builder = ctx.builder;
6248 ctx.stage = MESA_SHADER_VERTEX;
6249
6250 create_function(&ctx);
6251
6252 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6253 ac_setup_rings(&ctx);
6254
6255 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6256 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6257
6258 nir_foreach_variable(variable, &geom_shader->outputs)
6259 handle_shader_output_decl(&ctx, variable);
6260
6261 ac_gs_copy_shader_emit(&ctx);
6262
6263 LLVMBuildRetVoid(ctx.builder);
6264
6265 ac_llvm_finalize_module(&ctx);
6266
6267 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6268 MESA_SHADER_VERTEX,
6269 dump_shader, options->supports_spill);
6270 }