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radv: add sample mask input support
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef gsvs_ring_stride;
87 LLVMValueRef gsvs_num_entries;
88 LLVMValueRef gs2vs_offset;
89 LLVMValueRef gs_wave_id;
90 LLVMValueRef gs_vtx_offset[6];
91 LLVMValueRef gs_prim_id, gs_invocation_id;
92
93 LLVMValueRef esgs_ring;
94 LLVMValueRef gsvs_ring;
95
96 LLVMValueRef prim_mask;
97 LLVMValueRef sample_positions;
98 LLVMValueRef persp_sample, persp_center, persp_centroid;
99 LLVMValueRef linear_sample, linear_center, linear_centroid;
100 LLVMValueRef front_face;
101 LLVMValueRef ancillary;
102 LLVMValueRef sample_coverage;
103 LLVMValueRef frag_pos[4];
104
105 LLVMBasicBlockRef continue_block;
106 LLVMBasicBlockRef break_block;
107
108 LLVMTypeRef i1;
109 LLVMTypeRef i8;
110 LLVMTypeRef i16;
111 LLVMTypeRef i32;
112 LLVMTypeRef i64;
113 LLVMTypeRef v2i32;
114 LLVMTypeRef v3i32;
115 LLVMTypeRef v4i32;
116 LLVMTypeRef v8i32;
117 LLVMTypeRef f64;
118 LLVMTypeRef f32;
119 LLVMTypeRef f16;
120 LLVMTypeRef v2f32;
121 LLVMTypeRef v4f32;
122 LLVMTypeRef v16i8;
123 LLVMTypeRef voidt;
124
125 LLVMValueRef i32zero;
126 LLVMValueRef i32one;
127 LLVMValueRef f32zero;
128 LLVMValueRef f32one;
129 LLVMValueRef v4f32empty;
130
131 unsigned uniform_md_kind;
132 LLVMValueRef empty_md;
133 gl_shader_stage stage;
134
135 LLVMValueRef lds;
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
138
139 LLVMValueRef shared_memory;
140 uint64_t input_mask;
141 uint64_t output_mask;
142 int num_locals;
143 LLVMValueRef *locals;
144 bool has_ddxy;
145 uint8_t num_input_clips;
146 uint8_t num_input_culls;
147 uint8_t num_output_clips;
148 uint8_t num_output_culls;
149
150 bool has_ds_bpermute;
151
152 bool is_gs_copy_shader;
153 LLVMValueRef gs_next_vertex;
154 unsigned gs_max_out_vertices;
155 };
156
157 struct ac_tex_info {
158 LLVMValueRef args[12];
159 int arg_count;
160 LLVMTypeRef dst_type;
161 bool has_offset;
162 };
163
164 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
165 nir_deref_var *deref,
166 enum desc_type desc_type);
167 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
168 {
169 return (index * 4) + chan;
170 }
171
172 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
173 {
174 if (slot == VARYING_SLOT_POS)
175 return 0;
176 if (slot == VARYING_SLOT_PSIZ)
177 return 1;
178 if (slot == VARYING_SLOT_CLIP_DIST0 ||
179 slot == VARYING_SLOT_CULL_DIST0)
180 return 2;
181 if (slot == VARYING_SLOT_CLIP_DIST1 ||
182 slot == VARYING_SLOT_CULL_DIST1)
183 return 3;
184 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
185 return 4 + (slot - VARYING_SLOT_VAR0);
186 unreachable("illegal slot in get unique index\n");
187 }
188
189 static unsigned llvm_get_type_size(LLVMTypeRef type)
190 {
191 LLVMTypeKind kind = LLVMGetTypeKind(type);
192
193 switch (kind) {
194 case LLVMIntegerTypeKind:
195 return LLVMGetIntTypeWidth(type) / 8;
196 case LLVMFloatTypeKind:
197 return 4;
198 case LLVMPointerTypeKind:
199 return 8;
200 case LLVMVectorTypeKind:
201 return LLVMGetVectorSize(type) *
202 llvm_get_type_size(LLVMGetElementType(type));
203 default:
204 assert(0);
205 return 0;
206 }
207 }
208
209 static void set_llvm_calling_convention(LLVMValueRef func,
210 gl_shader_stage stage)
211 {
212 enum radeon_llvm_calling_convention calling_conv;
213
214 switch (stage) {
215 case MESA_SHADER_VERTEX:
216 case MESA_SHADER_TESS_CTRL:
217 case MESA_SHADER_TESS_EVAL:
218 calling_conv = RADEON_LLVM_AMDGPU_VS;
219 break;
220 case MESA_SHADER_GEOMETRY:
221 calling_conv = RADEON_LLVM_AMDGPU_GS;
222 break;
223 case MESA_SHADER_FRAGMENT:
224 calling_conv = RADEON_LLVM_AMDGPU_PS;
225 break;
226 case MESA_SHADER_COMPUTE:
227 calling_conv = RADEON_LLVM_AMDGPU_CS;
228 break;
229 default:
230 unreachable("Unhandle shader type");
231 }
232
233 LLVMSetFunctionCallConv(func, calling_conv);
234 }
235
236 static LLVMValueRef
237 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
238 LLVMBuilderRef builder, LLVMTypeRef *return_types,
239 unsigned num_return_elems, LLVMTypeRef *param_types,
240 unsigned param_count, unsigned array_params_mask,
241 unsigned sgpr_params, bool unsafe_math)
242 {
243 LLVMTypeRef main_function_type, ret_type;
244 LLVMBasicBlockRef main_function_body;
245
246 if (num_return_elems)
247 ret_type = LLVMStructTypeInContext(ctx, return_types,
248 num_return_elems, true);
249 else
250 ret_type = LLVMVoidTypeInContext(ctx);
251
252 /* Setup the function */
253 main_function_type =
254 LLVMFunctionType(ret_type, param_types, param_count, 0);
255 LLVMValueRef main_function =
256 LLVMAddFunction(module, "main", main_function_type);
257 main_function_body =
258 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
259 LLVMPositionBuilderAtEnd(builder, main_function_body);
260
261 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
262 for (unsigned i = 0; i < sgpr_params; ++i) {
263 if (array_params_mask & (1 << i)) {
264 LLVMValueRef P = LLVMGetParam(main_function, i);
265 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
266 ac_add_attr_dereferenceable(P, UINT64_MAX);
267 }
268 else {
269 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
270 }
271 }
272
273 if (unsafe_math) {
274 /* These were copied from some LLVM test. */
275 LLVMAddTargetDependentFunctionAttr(main_function,
276 "less-precise-fpmad",
277 "true");
278 LLVMAddTargetDependentFunctionAttr(main_function,
279 "no-infs-fp-math",
280 "true");
281 LLVMAddTargetDependentFunctionAttr(main_function,
282 "no-nans-fp-math",
283 "true");
284 LLVMAddTargetDependentFunctionAttr(main_function,
285 "unsafe-fp-math",
286 "true");
287 }
288 return main_function;
289 }
290
291 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
292 {
293 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
294 CONST_ADDR_SPACE);
295 }
296
297 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
298 int idx,
299 LLVMTypeRef type)
300 {
301 LLVMValueRef offset;
302 LLVMValueRef ptr;
303 int addr_space;
304
305 offset = LLVMConstInt(ctx->i32, idx, false);
306
307 ptr = ctx->shared_memory;
308 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
309 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
310 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
311 return ptr;
312 }
313
314 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
315 {
316 if (t == ctx->f16 || t == ctx->i16)
317 return ctx->i16;
318 else if (t == ctx->f32 || t == ctx->i32)
319 return ctx->i32;
320 else if (t == ctx->f64 || t == ctx->i64)
321 return ctx->i64;
322 else
323 unreachable("Unhandled integer size");
324 }
325
326 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
327 {
328 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
329 LLVMTypeRef elem_type = LLVMGetElementType(t);
330 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
331 LLVMGetVectorSize(t));
332 }
333 return to_integer_type_scalar(ctx, t);
334 }
335
336 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
337 {
338 LLVMTypeRef type = LLVMTypeOf(v);
339 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
340 }
341
342 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
343 {
344 if (t == ctx->i16 || t == ctx->f16)
345 return ctx->f16;
346 else if (t == ctx->i32 || t == ctx->f32)
347 return ctx->f32;
348 else if (t == ctx->i64 || t == ctx->f64)
349 return ctx->f64;
350 else
351 unreachable("Unhandled float size");
352 }
353
354 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
355 {
356 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
357 LLVMTypeRef elem_type = LLVMGetElementType(t);
358 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
359 LLVMGetVectorSize(t));
360 }
361 return to_float_type_scalar(ctx, t);
362 }
363
364 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
365 {
366 LLVMTypeRef type = LLVMTypeOf(v);
367 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
368 }
369
370 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
371 {
372 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
373 type = LLVMGetElementType(type);
374
375 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
376 return LLVMGetIntTypeWidth(type);
377
378 if (type == ctx->f16)
379 return 16;
380 if (type == ctx->f32)
381 return 32;
382 if (type == ctx->f64)
383 return 64;
384
385 unreachable("Unhandled type kind in get_elem_bits");
386 }
387
388 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
389 LLVMValueRef param, unsigned rshift,
390 unsigned bitwidth)
391 {
392 LLVMValueRef value = param;
393 if (rshift)
394 value = LLVMBuildLShr(ctx->builder, value,
395 LLVMConstInt(ctx->i32, rshift, false), "");
396
397 if (rshift + bitwidth < 32) {
398 unsigned mask = (1 << bitwidth) - 1;
399 value = LLVMBuildAnd(ctx->builder, value,
400 LLVMConstInt(ctx->i32, mask, false), "");
401 }
402 return value;
403 }
404
405 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
406 {
407 ud_info->sgpr_idx = sgpr_idx;
408 ud_info->num_sgprs = num_sgprs;
409 ud_info->indirect = false;
410 ud_info->indirect_offset = 0;
411 }
412
413 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
414 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
415 {
416 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
417 }
418
419 #if 0
420 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
421 uint32_t indirect_offset)
422 {
423 ud_info->sgpr_idx = sgpr_idx;
424 ud_info->num_sgprs = num_sgprs;
425 ud_info->indirect = true;
426 ud_info->indirect_offset = indirect_offset;
427 }
428 #endif
429
430 static void create_function(struct nir_to_llvm_context *ctx)
431 {
432 LLVMTypeRef arg_types[23];
433 unsigned arg_idx = 0;
434 unsigned array_params_mask = 0;
435 unsigned sgpr_count = 0, user_sgpr_count;
436 unsigned i;
437 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
438 unsigned user_sgpr_idx;
439 bool need_push_constants;
440 bool need_ring_offsets = false;
441
442 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
443 if (ctx->stage == MESA_SHADER_GEOMETRY ||
444 ctx->stage == MESA_SHADER_VERTEX ||
445 ctx->is_gs_copy_shader)
446 need_ring_offsets = true;
447
448 need_push_constants = true;
449 if (!ctx->options->layout)
450 need_push_constants = false;
451 else if (!ctx->options->layout->push_constant_size &&
452 !ctx->options->layout->dynamic_offset_count)
453 need_push_constants = false;
454
455 if (need_ring_offsets && !ctx->options->supports_spill) {
456 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
457 }
458
459 /* 1 for each descriptor set */
460 for (unsigned i = 0; i < num_sets; ++i) {
461 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
462 array_params_mask |= (1 << arg_idx);
463 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
464 }
465 }
466
467 if (need_push_constants) {
468 /* 1 for push constants and dynamic descriptors */
469 array_params_mask |= (1 << arg_idx);
470 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
471 }
472
473 switch (ctx->stage) {
474 case MESA_SHADER_COMPUTE:
475 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
476 user_sgpr_count = arg_idx;
477 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
478 arg_types[arg_idx++] = ctx->i32;
479 sgpr_count = arg_idx;
480
481 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
482 break;
483 case MESA_SHADER_VERTEX:
484 if (!ctx->is_gs_copy_shader) {
485 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
486 arg_types[arg_idx++] = ctx->i32; // base vertex
487 arg_types[arg_idx++] = ctx->i32; // start instance
488 arg_types[arg_idx++] = ctx->i32; // draw index
489 }
490 user_sgpr_count = arg_idx;
491 if (ctx->options->key.vs.as_es)
492 arg_types[arg_idx++] = ctx->i32; //es2gs offset
493 sgpr_count = arg_idx;
494 arg_types[arg_idx++] = ctx->i32; // vertex id
495 if (!ctx->is_gs_copy_shader) {
496 arg_types[arg_idx++] = ctx->i32; // rel auto id
497 arg_types[arg_idx++] = ctx->i32; // vs prim id
498 arg_types[arg_idx++] = ctx->i32; // instance id
499 }
500 break;
501 case MESA_SHADER_GEOMETRY:
502 arg_types[arg_idx++] = ctx->i32; // gsvs stride
503 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
504 user_sgpr_count = arg_idx;
505 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
506 arg_types[arg_idx++] = ctx->i32; // wave id
507 sgpr_count = arg_idx;
508 arg_types[arg_idx++] = ctx->i32; // vtx0
509 arg_types[arg_idx++] = ctx->i32; // vtx1
510 arg_types[arg_idx++] = ctx->i32; // prim id
511 arg_types[arg_idx++] = ctx->i32; // vtx2
512 arg_types[arg_idx++] = ctx->i32; // vtx3
513 arg_types[arg_idx++] = ctx->i32; // vtx4
514 arg_types[arg_idx++] = ctx->i32; // vtx5
515 arg_types[arg_idx++] = ctx->i32; // GS instance id
516 break;
517 case MESA_SHADER_FRAGMENT:
518 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
519 user_sgpr_count = arg_idx;
520 arg_types[arg_idx++] = ctx->i32; /* prim mask */
521 sgpr_count = arg_idx;
522 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
523 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
524 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
525 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
526 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
527 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
528 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
529 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
530 arg_types[arg_idx++] = ctx->f32; /* pos x float */
531 arg_types[arg_idx++] = ctx->f32; /* pos y float */
532 arg_types[arg_idx++] = ctx->f32; /* pos z float */
533 arg_types[arg_idx++] = ctx->f32; /* pos w float */
534 arg_types[arg_idx++] = ctx->i32; /* front face */
535 arg_types[arg_idx++] = ctx->i32; /* ancillary */
536 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
537 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
538 break;
539 default:
540 unreachable("Shader stage not implemented");
541 }
542
543 ctx->main_function = create_llvm_function(
544 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
545 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
546 set_llvm_calling_convention(ctx->main_function, ctx->stage);
547
548 ctx->shader_info->num_input_sgprs = 0;
549 ctx->shader_info->num_input_vgprs = 0;
550
551 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
552 for (i = 0; i < user_sgpr_count; i++)
553 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
554
555 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
556 for (; i < sgpr_count; i++)
557 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
558
559 if (ctx->stage != MESA_SHADER_FRAGMENT)
560 for (; i < arg_idx; ++i)
561 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
562
563 arg_idx = 0;
564 user_sgpr_idx = 0;
565
566 if (ctx->options->supports_spill || need_ring_offsets) {
567 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
568 user_sgpr_idx += 2;
569 if (ctx->options->supports_spill) {
570 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
571 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
572 NULL, 0, AC_FUNC_ATTR_READNONE);
573 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
574 const_array(ctx->v16i8, 8), "");
575 } else
576 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
577 }
578
579 for (unsigned i = 0; i < num_sets; ++i) {
580 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
581 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
582 user_sgpr_idx += 2;
583 ctx->descriptor_sets[i] =
584 LLVMGetParam(ctx->main_function, arg_idx++);
585 } else
586 ctx->descriptor_sets[i] = NULL;
587 }
588
589 if (need_push_constants) {
590 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
591 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
592 user_sgpr_idx += 2;
593 }
594
595 switch (ctx->stage) {
596 case MESA_SHADER_COMPUTE:
597 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
598 user_sgpr_idx += 3;
599 ctx->num_work_groups =
600 LLVMGetParam(ctx->main_function, arg_idx++);
601 ctx->workgroup_ids =
602 LLVMGetParam(ctx->main_function, arg_idx++);
603 ctx->tg_size =
604 LLVMGetParam(ctx->main_function, arg_idx++);
605 ctx->local_invocation_ids =
606 LLVMGetParam(ctx->main_function, arg_idx++);
607 break;
608 case MESA_SHADER_VERTEX:
609 if (!ctx->is_gs_copy_shader) {
610 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
611 user_sgpr_idx += 2;
612 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
613 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
614 user_sgpr_idx += 3;
615 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
616 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
617 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
618 }
619 if (ctx->options->key.vs.as_es)
620 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
621 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
622 if (!ctx->is_gs_copy_shader) {
623 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
624 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
625 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
626 }
627 break;
628 case MESA_SHADER_GEOMETRY:
629 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
630 user_sgpr_idx += 2;
631 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
632 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
633 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
635 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
636 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
638 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
639 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
640 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
641 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
642 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
643 break;
644 case MESA_SHADER_FRAGMENT:
645 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
646 user_sgpr_idx += 2;
647 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
648 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
651 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
652 arg_idx++;
653 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
655 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
656 arg_idx++; /* line stipple */
657 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
658 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
659 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
660 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
661 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
662 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
663 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
664 break;
665 default:
666 unreachable("Shader stage not implemented");
667 }
668 }
669
670 static void setup_types(struct nir_to_llvm_context *ctx)
671 {
672 LLVMValueRef args[4];
673
674 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
675 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
676 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
677 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
678 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
679 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
680 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
681 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
682 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
683 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
684 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
685 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
686 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
687 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
688 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
689 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
690
691 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
692 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
693 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
694 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
695
696 args[0] = ctx->f32zero;
697 args[1] = ctx->f32zero;
698 args[2] = ctx->f32zero;
699 args[3] = ctx->f32one;
700 ctx->v4f32empty = LLVMConstVector(args, 4);
701
702 ctx->uniform_md_kind =
703 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
704 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
705
706 args[0] = LLVMConstReal(ctx->f32, 2.5);
707 }
708
709 static int get_llvm_num_components(LLVMValueRef value)
710 {
711 LLVMTypeRef type = LLVMTypeOf(value);
712 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
713 ? LLVMGetVectorSize(type)
714 : 1;
715 return num_components;
716 }
717
718 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
719 LLVMValueRef value,
720 int index)
721 {
722 int count = get_llvm_num_components(value);
723
724 assert(index < count);
725 if (count == 1)
726 return value;
727
728 return LLVMBuildExtractElement(ctx->builder, value,
729 LLVMConstInt(ctx->i32, index, false), "");
730 }
731
732 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
733 LLVMValueRef value, unsigned count)
734 {
735 unsigned num_components = get_llvm_num_components(value);
736 if (count == num_components)
737 return value;
738
739 LLVMValueRef masks[] = {
740 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
741 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
742
743 if (count == 1)
744 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
745 "");
746
747 LLVMValueRef swizzle = LLVMConstVector(masks, count);
748 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
749 }
750
751 static void
752 build_store_values_extended(struct nir_to_llvm_context *ctx,
753 LLVMValueRef *values,
754 unsigned value_count,
755 unsigned value_stride,
756 LLVMValueRef vec)
757 {
758 LLVMBuilderRef builder = ctx->builder;
759 unsigned i;
760
761 if (value_count == 1) {
762 LLVMBuildStore(builder, vec, values[0]);
763 return;
764 }
765
766 for (i = 0; i < value_count; i++) {
767 LLVMValueRef ptr = values[i * value_stride];
768 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
769 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
770 LLVMBuildStore(builder, value, ptr);
771 }
772 }
773
774 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
775 nir_ssa_def *def)
776 {
777 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
778 if (def->num_components > 1) {
779 type = LLVMVectorType(type, def->num_components);
780 }
781 return type;
782 }
783
784 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
785 {
786 assert(src.is_ssa);
787 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
788 return (LLVMValueRef)entry->data;
789 }
790
791
792 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
793 struct nir_block *b)
794 {
795 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
796 return (LLVMBasicBlockRef)entry->data;
797 }
798
799 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
800 nir_alu_src src,
801 unsigned num_components)
802 {
803 LLVMValueRef value = get_src(ctx, src.src);
804 bool need_swizzle = false;
805
806 assert(value);
807 LLVMTypeRef type = LLVMTypeOf(value);
808 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
809 ? LLVMGetVectorSize(type)
810 : 1;
811
812 for (unsigned i = 0; i < num_components; ++i) {
813 assert(src.swizzle[i] < src_components);
814 if (src.swizzle[i] != i)
815 need_swizzle = true;
816 }
817
818 if (need_swizzle || num_components != src_components) {
819 LLVMValueRef masks[] = {
820 LLVMConstInt(ctx->i32, src.swizzle[0], false),
821 LLVMConstInt(ctx->i32, src.swizzle[1], false),
822 LLVMConstInt(ctx->i32, src.swizzle[2], false),
823 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
824
825 if (src_components > 1 && num_components == 1) {
826 value = LLVMBuildExtractElement(ctx->builder, value,
827 masks[0], "");
828 } else if (src_components == 1 && num_components > 1) {
829 LLVMValueRef values[] = {value, value, value, value};
830 value = ac_build_gather_values(&ctx->ac, values, num_components);
831 } else {
832 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
833 value = LLVMBuildShuffleVector(ctx->builder, value, value,
834 swizzle, "");
835 }
836 }
837 assert(!src.negate);
838 assert(!src.abs);
839 return value;
840 }
841
842 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
843 LLVMIntPredicate pred, LLVMValueRef src0,
844 LLVMValueRef src1)
845 {
846 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
847 return LLVMBuildSelect(ctx->builder, result,
848 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
849 LLVMConstInt(ctx->i32, 0, false), "");
850 }
851
852 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
853 LLVMRealPredicate pred, LLVMValueRef src0,
854 LLVMValueRef src1)
855 {
856 LLVMValueRef result;
857 src0 = to_float(ctx, src0);
858 src1 = to_float(ctx, src1);
859 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
860 return LLVMBuildSelect(ctx->builder, result,
861 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
862 LLVMConstInt(ctx->i32, 0, false), "");
863 }
864
865 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
866 const char *intrin,
867 LLVMTypeRef result_type,
868 LLVMValueRef src0)
869 {
870 char name[64];
871 LLVMValueRef params[] = {
872 to_float(ctx, src0),
873 };
874
875 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
876 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
877 }
878
879 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
880 const char *intrin,
881 LLVMTypeRef result_type,
882 LLVMValueRef src0, LLVMValueRef src1)
883 {
884 char name[64];
885 LLVMValueRef params[] = {
886 to_float(ctx, src0),
887 to_float(ctx, src1),
888 };
889
890 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
891 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
892 }
893
894 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
895 const char *intrin,
896 LLVMTypeRef result_type,
897 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
898 {
899 char name[64];
900 LLVMValueRef params[] = {
901 to_float(ctx, src0),
902 to_float(ctx, src1),
903 to_float(ctx, src2),
904 };
905
906 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
907 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
908 }
909
910 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
911 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
912 {
913 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
914 ctx->i32zero, "");
915 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
916 }
917
918 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
919 LLVMValueRef src0)
920 {
921 LLVMValueRef params[2] = {
922 src0,
923
924 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
925 * add special code to check for x=0. The reason is that
926 * the LLVM behavior for x=0 is different from what we
927 * need here.
928 *
929 * The hardware already implements the correct behavior.
930 */
931 LLVMConstInt(ctx->i32, 1, false),
932 };
933 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
934 }
935
936 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
937 LLVMValueRef src0)
938 {
939 return ac_emit_imsb(&ctx->ac, src0, ctx->i32);
940 }
941
942 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
943 LLVMValueRef src0)
944 {
945 return ac_emit_umsb(&ctx->ac, src0, ctx->i32);
946 }
947
948 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
949 LLVMIntPredicate pred,
950 LLVMValueRef src0, LLVMValueRef src1)
951 {
952 return LLVMBuildSelect(ctx->builder,
953 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
954 src0,
955 src1, "");
956
957 }
958 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
959 LLVMValueRef src0)
960 {
961 return emit_minmax_int(ctx, LLVMIntSGT, src0,
962 LLVMBuildNeg(ctx->builder, src0, ""));
963 }
964
965 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
966 LLVMValueRef src0)
967 {
968 LLVMValueRef cmp, val;
969
970 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
971 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
972 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
973 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
974 return val;
975 }
976
977 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
978 LLVMValueRef src0)
979 {
980 LLVMValueRef cmp, val;
981
982 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
983 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
984 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
985 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
986 return val;
987 }
988
989 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
990 LLVMValueRef src0)
991 {
992 const char *intr = "llvm.floor.f32";
993 LLVMValueRef fsrc0 = to_float(ctx, src0);
994 LLVMValueRef params[] = {
995 fsrc0,
996 };
997 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
998 ctx->f32, params, 1,
999 AC_FUNC_ATTR_READNONE);
1000 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1001 }
1002
1003 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1004 const char *intrin,
1005 LLVMValueRef src0, LLVMValueRef src1)
1006 {
1007 LLVMTypeRef ret_type;
1008 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1009 LLVMValueRef res;
1010 LLVMValueRef params[] = { src0, src1 };
1011 ret_type = LLVMStructTypeInContext(ctx->context, types,
1012 2, true);
1013
1014 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1015 params, 2, AC_FUNC_ATTR_READNONE);
1016
1017 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1018 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1019 return res;
1020 }
1021
1022 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1023 LLVMValueRef src0)
1024 {
1025 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1026 }
1027
1028 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1029 LLVMValueRef src0, LLVMValueRef src1)
1030 {
1031 LLVMValueRef dst64, result;
1032 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1033 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1034
1035 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1036 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1037 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1038 return result;
1039 }
1040
1041 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1042 LLVMValueRef src0, LLVMValueRef src1)
1043 {
1044 LLVMValueRef dst64, result;
1045 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1046 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1047
1048 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1049 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1050 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1051 return result;
1052 }
1053
1054 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1055 const char *intrin,
1056 LLVMValueRef srcs[3])
1057 {
1058 LLVMValueRef result;
1059 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1060 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1061
1062 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1063 return result;
1064 }
1065
1066 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1067 LLVMValueRef src0, LLVMValueRef src1,
1068 LLVMValueRef src2, LLVMValueRef src3)
1069 {
1070 LLVMValueRef bfi_args[3], result;
1071
1072 bfi_args[0] = LLVMBuildShl(ctx->builder,
1073 LLVMBuildSub(ctx->builder,
1074 LLVMBuildShl(ctx->builder,
1075 ctx->i32one,
1076 src3, ""),
1077 ctx->i32one, ""),
1078 src2, "");
1079 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1080 bfi_args[2] = src0;
1081
1082 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1083
1084 /* Calculate:
1085 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1086 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1087 */
1088 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1089 LLVMBuildAnd(ctx->builder, bfi_args[0],
1090 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1091
1092 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1093 return result;
1094 }
1095
1096 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1097 LLVMValueRef src0)
1098 {
1099 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1100 int i;
1101 LLVMValueRef comp[2];
1102
1103 src0 = to_float(ctx, src0);
1104 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1105 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1106 for (i = 0; i < 2; i++) {
1107 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1108 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1109 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1110 }
1111
1112 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1113 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1114
1115 return comp[0];
1116 }
1117
1118 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1119 LLVMValueRef src0)
1120 {
1121 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1122 LLVMValueRef temps[2], result, val;
1123 int i;
1124
1125 for (i = 0; i < 2; i++) {
1126 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1127 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1128 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1129 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1130 }
1131
1132 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1133 ctx->i32zero, "");
1134 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1135 ctx->i32one, "");
1136 return result;
1137 }
1138
1139 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1140 nir_op op,
1141 LLVMValueRef src0)
1142 {
1143 unsigned mask;
1144 int idx;
1145 LLVMValueRef result;
1146 ctx->has_ddxy = true;
1147
1148 if (!ctx->lds && !ctx->has_ds_bpermute)
1149 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1150 LLVMArrayType(ctx->i32, 64),
1151 "ddxy_lds", LOCAL_ADDR_SPACE);
1152
1153 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1154 mask = AC_TID_MASK_LEFT;
1155 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1156 mask = AC_TID_MASK_TOP;
1157 else
1158 mask = AC_TID_MASK_TOP_LEFT;
1159
1160 /* for DDX we want to next X pixel, DDY next Y pixel. */
1161 if (op == nir_op_fddx_fine ||
1162 op == nir_op_fddx_coarse ||
1163 op == nir_op_fddx)
1164 idx = 1;
1165 else
1166 idx = 2;
1167
1168 result = ac_emit_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1169 mask, idx, ctx->lds,
1170 src0);
1171 return result;
1172 }
1173
1174 /*
1175 * this takes an I,J coordinate pair,
1176 * and works out the X and Y derivatives.
1177 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1178 */
1179 static LLVMValueRef emit_ddxy_interp(
1180 struct nir_to_llvm_context *ctx,
1181 LLVMValueRef interp_ij)
1182 {
1183 LLVMValueRef result[4], a;
1184 unsigned i;
1185
1186 for (i = 0; i < 2; i++) {
1187 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1188 LLVMConstInt(ctx->i32, i, false), "");
1189 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1190 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1191 }
1192 return ac_build_gather_values(&ctx->ac, result, 4);
1193 }
1194
1195 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1196 {
1197 LLVMValueRef src[4], result = NULL;
1198 unsigned num_components = instr->dest.dest.ssa.num_components;
1199 unsigned src_components;
1200 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1201
1202 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1203 switch (instr->op) {
1204 case nir_op_vec2:
1205 case nir_op_vec3:
1206 case nir_op_vec4:
1207 src_components = 1;
1208 break;
1209 case nir_op_pack_half_2x16:
1210 src_components = 2;
1211 break;
1212 case nir_op_unpack_half_2x16:
1213 src_components = 1;
1214 break;
1215 default:
1216 src_components = num_components;
1217 break;
1218 }
1219 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1220 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1221
1222 switch (instr->op) {
1223 case nir_op_fmov:
1224 case nir_op_imov:
1225 result = src[0];
1226 break;
1227 case nir_op_fneg:
1228 src[0] = to_float(ctx, src[0]);
1229 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1230 break;
1231 case nir_op_ineg:
1232 result = LLVMBuildNeg(ctx->builder, src[0], "");
1233 break;
1234 case nir_op_inot:
1235 result = LLVMBuildNot(ctx->builder, src[0], "");
1236 break;
1237 case nir_op_iadd:
1238 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1239 break;
1240 case nir_op_fadd:
1241 src[0] = to_float(ctx, src[0]);
1242 src[1] = to_float(ctx, src[1]);
1243 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1244 break;
1245 case nir_op_fsub:
1246 src[0] = to_float(ctx, src[0]);
1247 src[1] = to_float(ctx, src[1]);
1248 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1249 break;
1250 case nir_op_isub:
1251 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1252 break;
1253 case nir_op_imul:
1254 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1255 break;
1256 case nir_op_imod:
1257 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1258 break;
1259 case nir_op_umod:
1260 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1261 break;
1262 case nir_op_fmod:
1263 src[0] = to_float(ctx, src[0]);
1264 src[1] = to_float(ctx, src[1]);
1265 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1266 result = emit_intrin_1f_param(ctx, "llvm.floor",
1267 to_float_type(ctx, def_type), result);
1268 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1269 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1270 break;
1271 case nir_op_frem:
1272 src[0] = to_float(ctx, src[0]);
1273 src[1] = to_float(ctx, src[1]);
1274 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1275 break;
1276 case nir_op_irem:
1277 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1278 break;
1279 case nir_op_idiv:
1280 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1281 break;
1282 case nir_op_udiv:
1283 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1284 break;
1285 case nir_op_fmul:
1286 src[0] = to_float(ctx, src[0]);
1287 src[1] = to_float(ctx, src[1]);
1288 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1289 break;
1290 case nir_op_fdiv:
1291 src[0] = to_float(ctx, src[0]);
1292 src[1] = to_float(ctx, src[1]);
1293 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1294 break;
1295 case nir_op_frcp:
1296 src[0] = to_float(ctx, src[0]);
1297 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1298 break;
1299 case nir_op_iand:
1300 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1301 break;
1302 case nir_op_ior:
1303 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1304 break;
1305 case nir_op_ixor:
1306 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1307 break;
1308 case nir_op_ishl:
1309 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1310 break;
1311 case nir_op_ishr:
1312 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1313 break;
1314 case nir_op_ushr:
1315 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1316 break;
1317 case nir_op_ilt:
1318 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1319 break;
1320 case nir_op_ine:
1321 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1322 break;
1323 case nir_op_ieq:
1324 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1325 break;
1326 case nir_op_ige:
1327 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1328 break;
1329 case nir_op_ult:
1330 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1331 break;
1332 case nir_op_uge:
1333 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1334 break;
1335 case nir_op_feq:
1336 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1337 break;
1338 case nir_op_fne:
1339 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1340 break;
1341 case nir_op_flt:
1342 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1343 break;
1344 case nir_op_fge:
1345 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1346 break;
1347 case nir_op_fabs:
1348 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1349 to_float_type(ctx, def_type), src[0]);
1350 break;
1351 case nir_op_iabs:
1352 result = emit_iabs(ctx, src[0]);
1353 break;
1354 case nir_op_imax:
1355 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1356 break;
1357 case nir_op_imin:
1358 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1359 break;
1360 case nir_op_umax:
1361 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1362 break;
1363 case nir_op_umin:
1364 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1365 break;
1366 case nir_op_isign:
1367 result = emit_isign(ctx, src[0]);
1368 break;
1369 case nir_op_fsign:
1370 src[0] = to_float(ctx, src[0]);
1371 result = emit_fsign(ctx, src[0]);
1372 break;
1373 case nir_op_ffloor:
1374 result = emit_intrin_1f_param(ctx, "llvm.floor",
1375 to_float_type(ctx, def_type), src[0]);
1376 break;
1377 case nir_op_ftrunc:
1378 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1379 to_float_type(ctx, def_type), src[0]);
1380 break;
1381 case nir_op_fceil:
1382 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1383 to_float_type(ctx, def_type), src[0]);
1384 break;
1385 case nir_op_fround_even:
1386 result = emit_intrin_1f_param(ctx, "llvm.rint",
1387 to_float_type(ctx, def_type),src[0]);
1388 break;
1389 case nir_op_ffract:
1390 result = emit_ffract(ctx, src[0]);
1391 break;
1392 case nir_op_fsin:
1393 result = emit_intrin_1f_param(ctx, "llvm.sin",
1394 to_float_type(ctx, def_type), src[0]);
1395 break;
1396 case nir_op_fcos:
1397 result = emit_intrin_1f_param(ctx, "llvm.cos",
1398 to_float_type(ctx, def_type), src[0]);
1399 break;
1400 case nir_op_fsqrt:
1401 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1402 to_float_type(ctx, def_type), src[0]);
1403 break;
1404 case nir_op_fexp2:
1405 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1406 to_float_type(ctx, def_type), src[0]);
1407 break;
1408 case nir_op_flog2:
1409 result = emit_intrin_1f_param(ctx, "llvm.log2",
1410 to_float_type(ctx, def_type), src[0]);
1411 break;
1412 case nir_op_frsq:
1413 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1414 to_float_type(ctx, def_type), src[0]);
1415 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1416 break;
1417 case nir_op_fpow:
1418 result = emit_intrin_2f_param(ctx, "llvm.pow",
1419 to_float_type(ctx, def_type), src[0], src[1]);
1420 break;
1421 case nir_op_fmax:
1422 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1423 to_float_type(ctx, def_type), src[0], src[1]);
1424 break;
1425 case nir_op_fmin:
1426 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1427 to_float_type(ctx, def_type), src[0], src[1]);
1428 break;
1429 case nir_op_ffma:
1430 result = emit_intrin_3f_param(ctx, "llvm.fma",
1431 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1432 break;
1433 case nir_op_ibitfield_extract:
1434 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1435 break;
1436 case nir_op_ubitfield_extract:
1437 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1438 break;
1439 case nir_op_bitfield_insert:
1440 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1441 break;
1442 case nir_op_bitfield_reverse:
1443 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1444 break;
1445 case nir_op_bit_count:
1446 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1447 break;
1448 case nir_op_vec2:
1449 case nir_op_vec3:
1450 case nir_op_vec4:
1451 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1452 src[i] = to_integer(ctx, src[i]);
1453 result = ac_build_gather_values(&ctx->ac, src, num_components);
1454 break;
1455 case nir_op_d2i:
1456 case nir_op_f2i:
1457 src[0] = to_float(ctx, src[0]);
1458 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1459 break;
1460 case nir_op_d2u:
1461 case nir_op_f2u:
1462 src[0] = to_float(ctx, src[0]);
1463 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1464 break;
1465 case nir_op_i2d:
1466 case nir_op_i2f:
1467 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1468 break;
1469 case nir_op_u2d:
1470 case nir_op_u2f:
1471 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1472 break;
1473 case nir_op_f2d:
1474 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1475 break;
1476 case nir_op_d2f:
1477 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1478 break;
1479 case nir_op_bcsel:
1480 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1481 break;
1482 case nir_op_find_lsb:
1483 result = emit_find_lsb(ctx, src[0]);
1484 break;
1485 case nir_op_ufind_msb:
1486 result = emit_ufind_msb(ctx, src[0]);
1487 break;
1488 case nir_op_ifind_msb:
1489 result = emit_ifind_msb(ctx, src[0]);
1490 break;
1491 case nir_op_uadd_carry:
1492 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1493 break;
1494 case nir_op_usub_borrow:
1495 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1496 break;
1497 case nir_op_b2f:
1498 result = emit_b2f(ctx, src[0]);
1499 break;
1500 case nir_op_fquantize2f16:
1501 src[0] = to_float(ctx, src[0]);
1502 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1503 /* need to convert back up to f32 */
1504 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1505 break;
1506 case nir_op_umul_high:
1507 result = emit_umul_high(ctx, src[0], src[1]);
1508 break;
1509 case nir_op_imul_high:
1510 result = emit_imul_high(ctx, src[0], src[1]);
1511 break;
1512 case nir_op_pack_half_2x16:
1513 result = emit_pack_half_2x16(ctx, src[0]);
1514 break;
1515 case nir_op_unpack_half_2x16:
1516 result = emit_unpack_half_2x16(ctx, src[0]);
1517 break;
1518 case nir_op_fddx:
1519 case nir_op_fddy:
1520 case nir_op_fddx_fine:
1521 case nir_op_fddy_fine:
1522 case nir_op_fddx_coarse:
1523 case nir_op_fddy_coarse:
1524 result = emit_ddxy(ctx, instr->op, src[0]);
1525 break;
1526 default:
1527 fprintf(stderr, "Unknown NIR alu instr: ");
1528 nir_print_instr(&instr->instr, stderr);
1529 fprintf(stderr, "\n");
1530 abort();
1531 }
1532
1533 if (result) {
1534 assert(instr->dest.dest.is_ssa);
1535 result = to_integer(ctx, result);
1536 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1537 result);
1538 }
1539 }
1540
1541 static void visit_load_const(struct nir_to_llvm_context *ctx,
1542 nir_load_const_instr *instr)
1543 {
1544 LLVMValueRef values[4], value = NULL;
1545 LLVMTypeRef element_type =
1546 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1547
1548 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1549 switch (instr->def.bit_size) {
1550 case 32:
1551 values[i] = LLVMConstInt(element_type,
1552 instr->value.u32[i], false);
1553 break;
1554 case 64:
1555 values[i] = LLVMConstInt(element_type,
1556 instr->value.u64[i], false);
1557 break;
1558 default:
1559 fprintf(stderr,
1560 "unsupported nir load_const bit_size: %d\n",
1561 instr->def.bit_size);
1562 abort();
1563 }
1564 }
1565 if (instr->def.num_components > 1) {
1566 value = LLVMConstVector(values, instr->def.num_components);
1567 } else
1568 value = values[0];
1569
1570 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1571 }
1572
1573 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1574 LLVMTypeRef type)
1575 {
1576 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1577 return LLVMBuildBitCast(ctx->builder, ptr,
1578 LLVMPointerType(type, addr_space), "");
1579 }
1580
1581 static LLVMValueRef
1582 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1583 {
1584 LLVMValueRef size =
1585 LLVMBuildExtractElement(ctx->builder, descriptor,
1586 LLVMConstInt(ctx->i32, 2, false), "");
1587
1588 /* VI only */
1589 if (ctx->options->chip_class >= VI && in_elements) {
1590 /* On VI, the descriptor contains the size in bytes,
1591 * but TXQ must return the size in elements.
1592 * The stride is always non-zero for resources using TXQ.
1593 */
1594 LLVMValueRef stride =
1595 LLVMBuildExtractElement(ctx->builder, descriptor,
1596 LLVMConstInt(ctx->i32, 1, false), "");
1597 stride = LLVMBuildLShr(ctx->builder, stride,
1598 LLVMConstInt(ctx->i32, 16, false), "");
1599 stride = LLVMBuildAnd(ctx->builder, stride,
1600 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1601
1602 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1603 }
1604 return size;
1605 }
1606
1607 /**
1608 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1609 * intrinsic names).
1610 */
1611 static void build_int_type_name(
1612 LLVMTypeRef type,
1613 char *buf, unsigned bufsize)
1614 {
1615 assert(bufsize >= 6);
1616
1617 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1618 snprintf(buf, bufsize, "v%ui32",
1619 LLVMGetVectorSize(type));
1620 else
1621 strcpy(buf, "i32");
1622 }
1623
1624 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1625 struct ac_tex_info *tinfo,
1626 nir_tex_instr *instr,
1627 const char *intr_name,
1628 unsigned coord_vgpr_index)
1629 {
1630 LLVMValueRef coord = tinfo->args[0];
1631 LLVMValueRef half_texel[2];
1632 int c;
1633
1634 //TODO Rect
1635 {
1636 LLVMValueRef txq_args[10];
1637 int txq_arg_count = 0;
1638 LLVMValueRef size;
1639 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1640 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1641 txq_args[txq_arg_count++] = tinfo->args[1];
1642 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1643 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1644 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1645 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1646 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1647 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1648 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1649 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1650 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1651 txq_args, txq_arg_count,
1652 AC_FUNC_ATTR_READNONE);
1653
1654 for (c = 0; c < 2; c++) {
1655 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1656 LLVMConstInt(ctx->i32, c, false), "");
1657 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1658 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1659 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1660 LLVMConstReal(ctx->f32, -0.5), "");
1661 }
1662 }
1663
1664 for (c = 0; c < 2; c++) {
1665 LLVMValueRef tmp;
1666 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1667 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1668 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1669 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1670 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1671 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1672 }
1673
1674 tinfo->args[0] = coord;
1675 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1676 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1677
1678 }
1679
1680 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1681 nir_tex_instr *instr,
1682 struct ac_tex_info *tinfo)
1683 {
1684 const char *name = "llvm.SI.image.sample";
1685 const char *infix = "";
1686 char intr_name[127];
1687 char type[64];
1688 bool is_shadow = instr->is_shadow;
1689 bool has_offset = tinfo->has_offset;
1690 switch (instr->op) {
1691 case nir_texop_txf:
1692 case nir_texop_txf_ms:
1693 case nir_texop_samples_identical:
1694 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1695 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1696 "llvm.SI.image.load.mip";
1697 is_shadow = false;
1698 has_offset = false;
1699 break;
1700 case nir_texop_txb:
1701 infix = ".b";
1702 break;
1703 case nir_texop_txl:
1704 infix = ".l";
1705 break;
1706 case nir_texop_txs:
1707 name = "llvm.SI.getresinfo";
1708 break;
1709 case nir_texop_query_levels:
1710 name = "llvm.SI.getresinfo";
1711 break;
1712 case nir_texop_tex:
1713 if (ctx->stage != MESA_SHADER_FRAGMENT)
1714 infix = ".lz";
1715 break;
1716 case nir_texop_txd:
1717 infix = ".d";
1718 break;
1719 case nir_texop_tg4:
1720 name = "llvm.SI.gather4";
1721 infix = ".lz";
1722 break;
1723 case nir_texop_lod:
1724 name = "llvm.SI.getlod";
1725 is_shadow = false;
1726 has_offset = false;
1727 break;
1728 default:
1729 break;
1730 }
1731
1732 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1733 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1734 has_offset ? ".o" : "", type);
1735
1736 if (instr->op == nir_texop_tg4) {
1737 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1738 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1739 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1740 (int)has_offset + (int)is_shadow);
1741 }
1742 }
1743 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1744 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1745
1746 }
1747
1748 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1749 nir_intrinsic_instr *instr)
1750 {
1751 LLVMValueRef index = get_src(ctx, instr->src[0]);
1752 unsigned desc_set = nir_intrinsic_desc_set(instr);
1753 unsigned binding = nir_intrinsic_binding(instr);
1754 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1755 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1756 unsigned base_offset = layout->binding[binding].offset;
1757 LLVMValueRef offset, stride;
1758
1759 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1760 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1761 desc_ptr = ctx->push_constants;
1762 base_offset = ctx->options->layout->push_constant_size;
1763 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1764 stride = LLVMConstInt(ctx->i32, 16, false);
1765 } else
1766 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1767
1768 offset = LLVMConstInt(ctx->i32, base_offset, false);
1769 index = LLVMBuildMul(ctx->builder, index, stride, "");
1770 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1771
1772 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1773 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1774 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1775
1776 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1777 }
1778
1779 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1780 nir_intrinsic_instr *instr)
1781 {
1782 LLVMValueRef ptr, addr;
1783
1784 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1785 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1786
1787 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1788 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1789
1790 return LLVMBuildLoad(ctx->builder, ptr, "");
1791 }
1792
1793 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1794 nir_intrinsic_instr *instr)
1795 {
1796 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1797
1798 return get_buffer_size(ctx, desc, false);
1799 }
1800 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1801 nir_intrinsic_instr *instr)
1802 {
1803 const char *store_name;
1804 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1805 LLVMTypeRef data_type = ctx->f32;
1806 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1807 int components_32bit = elem_size_mult * instr->num_components;
1808 unsigned writemask = nir_intrinsic_write_mask(instr);
1809 LLVMValueRef base_data, base_offset;
1810 LLVMValueRef params[6];
1811
1812 if (ctx->stage == MESA_SHADER_FRAGMENT)
1813 ctx->shader_info->fs.writes_memory = true;
1814
1815 params[1] = get_src(ctx, instr->src[1]);
1816 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1817 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1818 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1819
1820 if (components_32bit > 1)
1821 data_type = LLVMVectorType(ctx->f32, components_32bit);
1822
1823 base_data = to_float(ctx, src_data);
1824 base_data = trim_vector(ctx, base_data, instr->num_components);
1825 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1826 data_type, "");
1827 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1828 while (writemask) {
1829 int start, count;
1830 LLVMValueRef data;
1831 LLVMValueRef offset;
1832 LLVMValueRef tmp;
1833 u_bit_scan_consecutive_range(&writemask, &start, &count);
1834
1835 /* Due to an LLVM limitation, split 3-element writes
1836 * into a 2-element and a 1-element write. */
1837 if (count == 3) {
1838 writemask |= 1 << (start + 2);
1839 count = 2;
1840 }
1841
1842 start *= elem_size_mult;
1843 count *= elem_size_mult;
1844
1845 if (count > 4) {
1846 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1847 count = 4;
1848 }
1849
1850 if (count == 4) {
1851 store_name = "llvm.amdgcn.buffer.store.v4f32";
1852 data = base_data;
1853 } else if (count == 2) {
1854 tmp = LLVMBuildExtractElement(ctx->builder,
1855 base_data, LLVMConstInt(ctx->i32, start, false), "");
1856 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1857 ctx->i32zero, "");
1858
1859 tmp = LLVMBuildExtractElement(ctx->builder,
1860 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1861 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1862 ctx->i32one, "");
1863 store_name = "llvm.amdgcn.buffer.store.v2f32";
1864
1865 } else {
1866 assert(count == 1);
1867 if (get_llvm_num_components(base_data) > 1)
1868 data = LLVMBuildExtractElement(ctx->builder, base_data,
1869 LLVMConstInt(ctx->i32, start, false), "");
1870 else
1871 data = base_data;
1872 store_name = "llvm.amdgcn.buffer.store.f32";
1873 }
1874
1875 offset = base_offset;
1876 if (start != 0) {
1877 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1878 }
1879 params[0] = data;
1880 params[3] = offset;
1881 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1882 ctx->voidt, params, 6, 0);
1883 }
1884 }
1885
1886 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1887 nir_intrinsic_instr *instr)
1888 {
1889 const char *name;
1890 LLVMValueRef params[6];
1891 int arg_count = 0;
1892 if (ctx->stage == MESA_SHADER_FRAGMENT)
1893 ctx->shader_info->fs.writes_memory = true;
1894
1895 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1896 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1897 }
1898 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1899 params[arg_count++] = get_src(ctx, instr->src[0]);
1900 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1901 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1902 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1903
1904 switch (instr->intrinsic) {
1905 case nir_intrinsic_ssbo_atomic_add:
1906 name = "llvm.amdgcn.buffer.atomic.add";
1907 break;
1908 case nir_intrinsic_ssbo_atomic_imin:
1909 name = "llvm.amdgcn.buffer.atomic.smin";
1910 break;
1911 case nir_intrinsic_ssbo_atomic_umin:
1912 name = "llvm.amdgcn.buffer.atomic.umin";
1913 break;
1914 case nir_intrinsic_ssbo_atomic_imax:
1915 name = "llvm.amdgcn.buffer.atomic.smax";
1916 break;
1917 case nir_intrinsic_ssbo_atomic_umax:
1918 name = "llvm.amdgcn.buffer.atomic.umax";
1919 break;
1920 case nir_intrinsic_ssbo_atomic_and:
1921 name = "llvm.amdgcn.buffer.atomic.and";
1922 break;
1923 case nir_intrinsic_ssbo_atomic_or:
1924 name = "llvm.amdgcn.buffer.atomic.or";
1925 break;
1926 case nir_intrinsic_ssbo_atomic_xor:
1927 name = "llvm.amdgcn.buffer.atomic.xor";
1928 break;
1929 case nir_intrinsic_ssbo_atomic_exchange:
1930 name = "llvm.amdgcn.buffer.atomic.swap";
1931 break;
1932 case nir_intrinsic_ssbo_atomic_comp_swap:
1933 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1934 break;
1935 default:
1936 abort();
1937 }
1938
1939 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1940 }
1941
1942 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1943 nir_intrinsic_instr *instr)
1944 {
1945 LLVMValueRef results[2];
1946 int load_components;
1947 int num_components = instr->num_components;
1948 if (instr->dest.ssa.bit_size == 64)
1949 num_components *= 2;
1950
1951 for (int i = 0; i < num_components; i += load_components) {
1952 load_components = MIN2(num_components - i, 4);
1953 const char *load_name;
1954 LLVMTypeRef data_type = ctx->f32;
1955 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
1956 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
1957
1958 if (load_components == 3)
1959 data_type = LLVMVectorType(ctx->f32, 4);
1960 else if (load_components > 1)
1961 data_type = LLVMVectorType(ctx->f32, load_components);
1962
1963 if (load_components >= 3)
1964 load_name = "llvm.amdgcn.buffer.load.v4f32";
1965 else if (load_components == 2)
1966 load_name = "llvm.amdgcn.buffer.load.v2f32";
1967 else if (load_components == 1)
1968 load_name = "llvm.amdgcn.buffer.load.f32";
1969 else
1970 unreachable("unhandled number of components");
1971
1972 LLVMValueRef params[] = {
1973 get_src(ctx, instr->src[0]),
1974 LLVMConstInt(ctx->i32, 0, false),
1975 offset,
1976 LLVMConstInt(ctx->i1, 0, false),
1977 LLVMConstInt(ctx->i1, 0, false),
1978 };
1979
1980 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
1981
1982 }
1983
1984 LLVMValueRef ret = results[0];
1985 if (num_components > 4 || num_components == 3) {
1986 LLVMValueRef masks[] = {
1987 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1988 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
1989 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
1990 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
1991 };
1992
1993 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1994 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
1995 results[num_components > 4 ? 1 : 0], swizzle, "");
1996 }
1997
1998 return LLVMBuildBitCast(ctx->builder, ret,
1999 get_def_type(ctx, &instr->dest.ssa), "");
2000 }
2001
2002 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2003 nir_intrinsic_instr *instr)
2004 {
2005 LLVMValueRef results[8], ret;
2006 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2007 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2008 int num_components = instr->num_components;
2009
2010 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2011
2012 if (instr->dest.ssa.bit_size == 64)
2013 num_components *= 2;
2014
2015 for (unsigned i = 0; i < num_components; ++i) {
2016 LLVMValueRef params[] = {
2017 rsrc,
2018 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2019 offset, "")
2020 };
2021 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2022 params, 2, AC_FUNC_ATTR_READNONE);
2023 }
2024
2025
2026 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2027 return LLVMBuildBitCast(ctx->builder, ret,
2028 get_def_type(ctx, &instr->dest.ssa), "");
2029 }
2030
2031 static void
2032 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2033 bool vs_in, unsigned *vertex_index_out,
2034 unsigned *const_out, LLVMValueRef *indir_out)
2035 {
2036 unsigned const_offset = 0;
2037 LLVMValueRef offset = NULL;
2038
2039 if (vertex_index_out != NULL) {
2040 tail = tail->child;
2041 nir_deref_array *deref_array = nir_deref_as_array(tail);
2042 *vertex_index_out = deref_array->base_offset;
2043 }
2044
2045 while (tail->child != NULL) {
2046 const struct glsl_type *parent_type = tail->type;
2047 tail = tail->child;
2048
2049 if (tail->deref_type == nir_deref_type_array) {
2050 nir_deref_array *deref_array = nir_deref_as_array(tail);
2051 LLVMValueRef index, stride, local_offset;
2052 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2053
2054 const_offset += size * deref_array->base_offset;
2055 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2056 continue;
2057
2058 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2059 index = get_src(ctx, deref_array->indirect);
2060 stride = LLVMConstInt(ctx->i32, size, 0);
2061 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2062
2063 if (offset)
2064 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2065 else
2066 offset = local_offset;
2067 } else if (tail->deref_type == nir_deref_type_struct) {
2068 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2069
2070 for (unsigned i = 0; i < deref_struct->index; i++) {
2071 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2072 const_offset += glsl_count_attribute_slots(ft, vs_in);
2073 }
2074 } else
2075 unreachable("unsupported deref type");
2076
2077 }
2078
2079 if (const_offset && offset)
2080 offset = LLVMBuildAdd(ctx->builder, offset,
2081 LLVMConstInt(ctx->i32, const_offset, 0),
2082 "");
2083
2084 *const_out = const_offset;
2085 *indir_out = offset;
2086 }
2087
2088 static LLVMValueRef
2089 load_gs_input(struct nir_to_llvm_context *ctx,
2090 nir_intrinsic_instr *instr)
2091 {
2092 LLVMValueRef indir_index, vtx_offset;
2093 unsigned const_index;
2094 LLVMValueRef args[9];
2095 unsigned param, vtx_offset_param;
2096 LLVMValueRef value[4], result;
2097 unsigned vertex_index;
2098 unsigned cull_offset = 0;
2099 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2100 false, &vertex_index,
2101 &const_index, &indir_index);
2102 vtx_offset_param = vertex_index;
2103 assert(vtx_offset_param < 6);
2104 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2105 LLVMConstInt(ctx->i32, 4, false), "");
2106
2107 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2108 if (instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2109 cull_offset += ctx->num_input_clips;
2110 for (unsigned i = 0; i < instr->num_components; i++) {
2111
2112 args[0] = ctx->esgs_ring;
2113 args[1] = vtx_offset;
2114 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index + cull_offset) * 256, false);
2115 args[3] = ctx->i32zero;
2116 args[4] = ctx->i32one; /* OFFEN */
2117 args[5] = ctx->i32zero; /* IDXEN */
2118 args[6] = ctx->i32one; /* GLC */
2119 args[7] = ctx->i32zero; /* SLC */
2120 args[8] = ctx->i32zero; /* TFE */
2121
2122 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2123 ctx->i32, args, 9, AC_FUNC_ATTR_READONLY);
2124 }
2125 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2126
2127 return result;
2128 }
2129
2130 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2131 nir_intrinsic_instr *instr)
2132 {
2133 LLVMValueRef values[8];
2134 int idx = instr->variables[0]->var->data.driver_location;
2135 int ve = instr->dest.ssa.num_components;
2136 LLVMValueRef indir_index;
2137 LLVMValueRef ret;
2138 unsigned const_index;
2139 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2140 instr->variables[0]->var->data.mode == nir_var_shader_in;
2141 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2142 &const_index, &indir_index);
2143
2144 if (instr->dest.ssa.bit_size == 64)
2145 ve *= 2;
2146
2147 switch (instr->variables[0]->var->data.mode) {
2148 case nir_var_shader_in:
2149 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2150 return load_gs_input(ctx, instr);
2151 }
2152 for (unsigned chan = 0; chan < ve; chan++) {
2153 if (indir_index) {
2154 unsigned count = glsl_count_attribute_slots(
2155 instr->variables[0]->var->type,
2156 ctx->stage == MESA_SHADER_VERTEX);
2157 count -= chan / 4;
2158 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2159 &ctx->ac, ctx->inputs + idx + chan, count,
2160 4, false);
2161
2162 values[chan] = LLVMBuildExtractElement(ctx->builder,
2163 tmp_vec,
2164 indir_index, "");
2165 } else
2166 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2167 }
2168 break;
2169 case nir_var_local:
2170 for (unsigned chan = 0; chan < ve; chan++) {
2171 if (indir_index) {
2172 unsigned count = glsl_count_attribute_slots(
2173 instr->variables[0]->var->type, false);
2174 count -= chan / 4;
2175 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2176 &ctx->ac, ctx->locals + idx + chan, count,
2177 4, true);
2178
2179 values[chan] = LLVMBuildExtractElement(ctx->builder,
2180 tmp_vec,
2181 indir_index, "");
2182 } else {
2183 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2184 }
2185 }
2186 break;
2187 case nir_var_shader_out:
2188 for (unsigned chan = 0; chan < ve; chan++) {
2189 if (indir_index) {
2190 unsigned count = glsl_count_attribute_slots(
2191 instr->variables[0]->var->type, false);
2192 count -= chan / 4;
2193 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2194 &ctx->ac, ctx->outputs + idx + chan, count,
2195 4, true);
2196
2197 values[chan] = LLVMBuildExtractElement(ctx->builder,
2198 tmp_vec,
2199 indir_index, "");
2200 } else {
2201 values[chan] = LLVMBuildLoad(ctx->builder,
2202 ctx->outputs[idx + chan + const_index * 4],
2203 "");
2204 }
2205 }
2206 break;
2207 case nir_var_shared: {
2208 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2209 LLVMValueRef derived_ptr;
2210
2211 if (indir_index)
2212 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2213
2214 for (unsigned chan = 0; chan < ve; chan++) {
2215 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2216 if (indir_index)
2217 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2218 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2219
2220 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2221 }
2222 break;
2223 }
2224 default:
2225 unreachable("unhandle variable mode");
2226 }
2227 ret = ac_build_gather_values(&ctx->ac, values, ve);
2228 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2229 }
2230
2231 static void
2232 visit_store_var(struct nir_to_llvm_context *ctx,
2233 nir_intrinsic_instr *instr)
2234 {
2235 LLVMValueRef temp_ptr, value;
2236 int idx = instr->variables[0]->var->data.driver_location;
2237 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2238 int writemask = instr->const_index[0];
2239 LLVMValueRef indir_index;
2240 unsigned const_index;
2241 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2242 NULL, &const_index, &indir_index);
2243
2244 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2245 int old_writemask = writemask;
2246
2247 src = LLVMBuildBitCast(ctx->builder, src,
2248 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2249 "");
2250
2251 writemask = 0;
2252 for (unsigned chan = 0; chan < 4; chan++) {
2253 if (old_writemask & (1 << chan))
2254 writemask |= 3u << (2 * chan);
2255 }
2256 }
2257
2258 switch (instr->variables[0]->var->data.mode) {
2259 case nir_var_shader_out:
2260 for (unsigned chan = 0; chan < 8; chan++) {
2261 int stride = 4;
2262 if (!(writemask & (1 << chan)))
2263 continue;
2264
2265 value = llvm_extract_elem(ctx, src, chan);
2266
2267 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2268 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2269 stride = 1;
2270 if (indir_index) {
2271 unsigned count = glsl_count_attribute_slots(
2272 instr->variables[0]->var->type, false);
2273 count -= chan / 4;
2274 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2275 &ctx->ac, ctx->outputs + idx + chan, count,
2276 stride, true);
2277
2278 if (get_llvm_num_components(tmp_vec) > 1) {
2279 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2280 value, indir_index, "");
2281 } else
2282 tmp_vec = value;
2283 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2284 count, stride, tmp_vec);
2285
2286 } else {
2287 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2288
2289 LLVMBuildStore(ctx->builder, value, temp_ptr);
2290 }
2291 }
2292 break;
2293 case nir_var_local:
2294 for (unsigned chan = 0; chan < 8; chan++) {
2295 if (!(writemask & (1 << chan)))
2296 continue;
2297
2298 value = llvm_extract_elem(ctx, src, chan);
2299 if (indir_index) {
2300 unsigned count = glsl_count_attribute_slots(
2301 instr->variables[0]->var->type, false);
2302 count -= chan / 4;
2303 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2304 &ctx->ac, ctx->locals + idx + chan, count,
2305 4, true);
2306
2307 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2308 value, indir_index, "");
2309 build_store_values_extended(ctx, ctx->locals + idx + chan,
2310 count, 4, tmp_vec);
2311 } else {
2312 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2313
2314 LLVMBuildStore(ctx->builder, value, temp_ptr);
2315 }
2316 }
2317 break;
2318 case nir_var_shared: {
2319 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2320
2321 if (indir_index)
2322 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2323
2324 for (unsigned chan = 0; chan < 8; chan++) {
2325 if (!(writemask & (1 << chan)))
2326 continue;
2327 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2328 LLVMValueRef derived_ptr;
2329
2330 if (indir_index)
2331 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2332
2333 value = llvm_extract_elem(ctx, src, chan);
2334 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2335 LLVMBuildStore(ctx->builder,
2336 to_integer(ctx, value), derived_ptr);
2337 }
2338 break;
2339 }
2340 default:
2341 break;
2342 }
2343 }
2344
2345 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2346 {
2347 switch (dim) {
2348 case GLSL_SAMPLER_DIM_BUF:
2349 return 1;
2350 case GLSL_SAMPLER_DIM_1D:
2351 return array ? 2 : 1;
2352 case GLSL_SAMPLER_DIM_2D:
2353 return array ? 3 : 2;
2354 case GLSL_SAMPLER_DIM_MS:
2355 return array ? 4 : 3;
2356 case GLSL_SAMPLER_DIM_3D:
2357 case GLSL_SAMPLER_DIM_CUBE:
2358 return 3;
2359 case GLSL_SAMPLER_DIM_RECT:
2360 case GLSL_SAMPLER_DIM_SUBPASS:
2361 return 2;
2362 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2363 return 3;
2364 default:
2365 break;
2366 }
2367 return 0;
2368 }
2369
2370 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2371 nir_intrinsic_instr *instr)
2372 {
2373 const struct glsl_type *type = instr->variables[0]->var->type;
2374 if(instr->variables[0]->deref.child)
2375 type = instr->variables[0]->deref.child->type;
2376
2377 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2378 LLVMValueRef coords[4];
2379 LLVMValueRef masks[] = {
2380 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2381 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2382 };
2383 LLVMValueRef res;
2384 int count;
2385 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2386 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2387 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2388 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2389 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2390
2391 count = image_type_to_components_count(dim,
2392 glsl_sampler_type_is_array(type));
2393
2394 if (count == 1) {
2395 if (instr->src[0].ssa->num_components)
2396 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2397 else
2398 res = src0;
2399 } else {
2400 int chan;
2401 if (is_ms)
2402 count--;
2403 for (chan = 0; chan < count; ++chan) {
2404 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2405 }
2406
2407 if (add_frag_pos) {
2408 for (chan = 0; chan < count; ++chan)
2409 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2410 }
2411 if (is_ms) {
2412 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2413 count++;
2414 }
2415
2416 if (count == 3) {
2417 coords[3] = LLVMGetUndef(ctx->i32);
2418 count = 4;
2419 }
2420 res = ac_build_gather_values(&ctx->ac, coords, count);
2421 }
2422 return res;
2423 }
2424
2425 static void build_type_name_for_intr(
2426 LLVMTypeRef type,
2427 char *buf, unsigned bufsize)
2428 {
2429 LLVMTypeRef elem_type = type;
2430
2431 assert(bufsize >= 8);
2432
2433 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2434 int ret = snprintf(buf, bufsize, "v%u",
2435 LLVMGetVectorSize(type));
2436 if (ret < 0) {
2437 char *type_name = LLVMPrintTypeToString(type);
2438 fprintf(stderr, "Error building type name for: %s\n",
2439 type_name);
2440 return;
2441 }
2442 elem_type = LLVMGetElementType(type);
2443 buf += ret;
2444 bufsize -= ret;
2445 }
2446 switch (LLVMGetTypeKind(elem_type)) {
2447 default: break;
2448 case LLVMIntegerTypeKind:
2449 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2450 break;
2451 case LLVMFloatTypeKind:
2452 snprintf(buf, bufsize, "f32");
2453 break;
2454 case LLVMDoubleTypeKind:
2455 snprintf(buf, bufsize, "f64");
2456 break;
2457 }
2458 }
2459
2460 static void get_image_intr_name(const char *base_name,
2461 LLVMTypeRef data_type,
2462 LLVMTypeRef coords_type,
2463 LLVMTypeRef rsrc_type,
2464 char *out_name, unsigned out_len)
2465 {
2466 char coords_type_name[8];
2467
2468 build_type_name_for_intr(coords_type, coords_type_name,
2469 sizeof(coords_type_name));
2470
2471 if (HAVE_LLVM <= 0x0309) {
2472 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2473 } else {
2474 char data_type_name[8];
2475 char rsrc_type_name[8];
2476
2477 build_type_name_for_intr(data_type, data_type_name,
2478 sizeof(data_type_name));
2479 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2480 sizeof(rsrc_type_name));
2481 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2482 data_type_name, coords_type_name, rsrc_type_name);
2483 }
2484 }
2485
2486 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2487 nir_intrinsic_instr *instr)
2488 {
2489 LLVMValueRef params[7];
2490 LLVMValueRef res;
2491 char intrinsic_name[64];
2492 const nir_variable *var = instr->variables[0]->var;
2493 const struct glsl_type *type = var->type;
2494 if(instr->variables[0]->deref.child)
2495 type = instr->variables[0]->deref.child->type;
2496
2497 type = glsl_without_array(type);
2498 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2499 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2500 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2501 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2502 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2503 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2504 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2505 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2506 params, 5, 0);
2507
2508 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2509 res = to_integer(ctx, res);
2510 } else {
2511 bool is_da = glsl_sampler_type_is_array(type) ||
2512 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2513 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2514 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2515 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2516
2517 params[0] = get_image_coords(ctx, instr);
2518 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2519 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2520 if (HAVE_LLVM <= 0x0309) {
2521 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2522 params[4] = da;
2523 params[5] = glc;
2524 params[6] = slc;
2525 } else {
2526 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2527 params[3] = glc;
2528 params[4] = slc;
2529 params[5] = lwe;
2530 params[6] = da;
2531 }
2532
2533 get_image_intr_name("llvm.amdgcn.image.load",
2534 ctx->v4f32, /* vdata */
2535 LLVMTypeOf(params[0]), /* coords */
2536 LLVMTypeOf(params[1]), /* rsrc */
2537 intrinsic_name, sizeof(intrinsic_name));
2538
2539 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2540 params, 7, AC_FUNC_ATTR_READONLY);
2541 }
2542 return to_integer(ctx, res);
2543 }
2544
2545 static void visit_image_store(struct nir_to_llvm_context *ctx,
2546 nir_intrinsic_instr *instr)
2547 {
2548 LLVMValueRef params[8];
2549 char intrinsic_name[64];
2550 const nir_variable *var = instr->variables[0]->var;
2551 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2552 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2553 const struct glsl_type *type = glsl_without_array(var->type);
2554
2555 if (ctx->stage == MESA_SHADER_FRAGMENT)
2556 ctx->shader_info->fs.writes_memory = true;
2557
2558 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2559 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2560 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2561 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2562 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2563 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2564 params[4] = i1false; /* glc */
2565 params[5] = i1false; /* slc */
2566 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2567 params, 6, 0);
2568 } else {
2569 bool is_da = glsl_sampler_type_is_array(type) ||
2570 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2571 LLVMValueRef da = is_da ? i1true : i1false;
2572 LLVMValueRef glc = i1false;
2573 LLVMValueRef slc = i1false;
2574
2575 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2576 params[1] = get_image_coords(ctx, instr); /* coords */
2577 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2578 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2579 if (HAVE_LLVM <= 0x0309) {
2580 params[4] = i1false; /* r128 */
2581 params[5] = da;
2582 params[6] = glc;
2583 params[7] = slc;
2584 } else {
2585 LLVMValueRef lwe = i1false;
2586 params[4] = glc;
2587 params[5] = slc;
2588 params[6] = lwe;
2589 params[7] = da;
2590 }
2591
2592 get_image_intr_name("llvm.amdgcn.image.store",
2593 LLVMTypeOf(params[0]), /* vdata */
2594 LLVMTypeOf(params[1]), /* coords */
2595 LLVMTypeOf(params[2]), /* rsrc */
2596 intrinsic_name, sizeof(intrinsic_name));
2597
2598 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2599 params, 8, 0);
2600 }
2601
2602 }
2603
2604 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2605 nir_intrinsic_instr *instr)
2606 {
2607 LLVMValueRef params[6];
2608 int param_count = 0;
2609 const nir_variable *var = instr->variables[0]->var;
2610 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2611 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2612 const char *base_name = "llvm.amdgcn.image.atomic";
2613 const char *atomic_name;
2614 LLVMValueRef coords;
2615 char intrinsic_name[32], coords_type[8];
2616 const struct glsl_type *type = glsl_without_array(var->type);
2617
2618 if (ctx->stage == MESA_SHADER_FRAGMENT)
2619 ctx->shader_info->fs.writes_memory = true;
2620
2621 params[param_count++] = get_src(ctx, instr->src[2]);
2622 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2623 params[param_count++] = get_src(ctx, instr->src[3]);
2624
2625 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2626 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2627 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2628 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2629 params[param_count++] = ctx->i32zero; /* voffset */
2630 params[param_count++] = i1false; /* glc */
2631 params[param_count++] = i1false; /* slc */
2632 } else {
2633 bool da = glsl_sampler_type_is_array(type) ||
2634 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2635
2636 coords = params[param_count++] = get_image_coords(ctx, instr);
2637 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2638 params[param_count++] = i1false; /* r128 */
2639 params[param_count++] = da ? i1true : i1false; /* da */
2640 params[param_count++] = i1false; /* slc */
2641 }
2642
2643 switch (instr->intrinsic) {
2644 case nir_intrinsic_image_atomic_add:
2645 atomic_name = "add";
2646 break;
2647 case nir_intrinsic_image_atomic_min:
2648 atomic_name = "smin";
2649 break;
2650 case nir_intrinsic_image_atomic_max:
2651 atomic_name = "smax";
2652 break;
2653 case nir_intrinsic_image_atomic_and:
2654 atomic_name = "and";
2655 break;
2656 case nir_intrinsic_image_atomic_or:
2657 atomic_name = "or";
2658 break;
2659 case nir_intrinsic_image_atomic_xor:
2660 atomic_name = "xor";
2661 break;
2662 case nir_intrinsic_image_atomic_exchange:
2663 atomic_name = "swap";
2664 break;
2665 case nir_intrinsic_image_atomic_comp_swap:
2666 atomic_name = "cmpswap";
2667 break;
2668 default:
2669 abort();
2670 }
2671 build_int_type_name(LLVMTypeOf(coords),
2672 coords_type, sizeof(coords_type));
2673
2674 snprintf(intrinsic_name, sizeof(intrinsic_name),
2675 "%s.%s.%s", base_name, atomic_name, coords_type);
2676 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2677 }
2678
2679 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2680 nir_intrinsic_instr *instr)
2681 {
2682 LLVMValueRef res;
2683 LLVMValueRef params[10];
2684 const nir_variable *var = instr->variables[0]->var;
2685 const struct glsl_type *type = instr->variables[0]->var->type;
2686 bool da = glsl_sampler_type_is_array(var->type) ||
2687 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2688 if(instr->variables[0]->deref.child)
2689 type = instr->variables[0]->deref.child->type;
2690
2691 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2692 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2693 params[0] = ctx->i32zero;
2694 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2695 params[2] = LLVMConstInt(ctx->i32, 15, false);
2696 params[3] = ctx->i32zero;
2697 params[4] = ctx->i32zero;
2698 params[5] = da ? ctx->i32one : ctx->i32zero;
2699 params[6] = ctx->i32zero;
2700 params[7] = ctx->i32zero;
2701 params[8] = ctx->i32zero;
2702 params[9] = ctx->i32zero;
2703
2704 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2705 params, 10, AC_FUNC_ATTR_READNONE);
2706
2707 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2708 glsl_sampler_type_is_array(type)) {
2709 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2710 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2711 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2712 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2713 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2714 }
2715 return res;
2716 }
2717
2718 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2719 {
2720 LLVMValueRef args[1] = {
2721 LLVMConstInt(ctx->i32, 0xf70, false),
2722 };
2723 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2724 ctx->voidt, args, 1, 0);
2725 }
2726
2727 static void emit_barrier(struct nir_to_llvm_context *ctx)
2728 {
2729 // TODO tess
2730 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2731 ctx->voidt, NULL, 0, 0);
2732 }
2733
2734 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2735 nir_intrinsic_instr *instr)
2736 {
2737 LLVMValueRef cond;
2738 ctx->shader_info->fs.can_discard = true;
2739
2740 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2741 get_src(ctx, instr->src[0]),
2742 ctx->i32zero, "");
2743
2744 cond = LLVMBuildSelect(ctx->builder, cond,
2745 LLVMConstReal(ctx->f32, -1.0f),
2746 ctx->f32zero, "");
2747 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2748 ctx->voidt,
2749 &cond, 1, 0);
2750 }
2751
2752 static LLVMValueRef
2753 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2754 {
2755 LLVMValueRef result;
2756 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2757 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2758 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2759
2760 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2761 }
2762
2763 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2764 nir_intrinsic_instr *instr)
2765 {
2766 LLVMValueRef ptr, result;
2767 int idx = instr->variables[0]->var->data.driver_location;
2768 LLVMValueRef src = get_src(ctx, instr->src[0]);
2769 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2770
2771 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2772 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2773 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2774 ptr, src, src1,
2775 LLVMAtomicOrderingSequentiallyConsistent,
2776 LLVMAtomicOrderingSequentiallyConsistent,
2777 false);
2778 } else {
2779 LLVMAtomicRMWBinOp op;
2780 switch (instr->intrinsic) {
2781 case nir_intrinsic_var_atomic_add:
2782 op = LLVMAtomicRMWBinOpAdd;
2783 break;
2784 case nir_intrinsic_var_atomic_umin:
2785 op = LLVMAtomicRMWBinOpUMin;
2786 break;
2787 case nir_intrinsic_var_atomic_umax:
2788 op = LLVMAtomicRMWBinOpUMax;
2789 break;
2790 case nir_intrinsic_var_atomic_imin:
2791 op = LLVMAtomicRMWBinOpMin;
2792 break;
2793 case nir_intrinsic_var_atomic_imax:
2794 op = LLVMAtomicRMWBinOpMax;
2795 break;
2796 case nir_intrinsic_var_atomic_and:
2797 op = LLVMAtomicRMWBinOpAnd;
2798 break;
2799 case nir_intrinsic_var_atomic_or:
2800 op = LLVMAtomicRMWBinOpOr;
2801 break;
2802 case nir_intrinsic_var_atomic_xor:
2803 op = LLVMAtomicRMWBinOpXor;
2804 break;
2805 case nir_intrinsic_var_atomic_exchange:
2806 op = LLVMAtomicRMWBinOpXchg;
2807 break;
2808 default:
2809 return NULL;
2810 }
2811
2812 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2813 LLVMAtomicOrderingSequentiallyConsistent,
2814 false);
2815 }
2816 return result;
2817 }
2818
2819 #define INTERP_CENTER 0
2820 #define INTERP_CENTROID 1
2821 #define INTERP_SAMPLE 2
2822
2823 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2824 enum glsl_interp_mode interp, unsigned location)
2825 {
2826 switch (interp) {
2827 case INTERP_MODE_FLAT:
2828 default:
2829 return NULL;
2830 case INTERP_MODE_SMOOTH:
2831 case INTERP_MODE_NONE:
2832 if (location == INTERP_CENTER)
2833 return ctx->persp_center;
2834 else if (location == INTERP_CENTROID)
2835 return ctx->persp_centroid;
2836 else if (location == INTERP_SAMPLE)
2837 return ctx->persp_sample;
2838 break;
2839 case INTERP_MODE_NOPERSPECTIVE:
2840 if (location == INTERP_CENTER)
2841 return ctx->linear_center;
2842 else if (location == INTERP_CENTROID)
2843 return ctx->linear_centroid;
2844 else if (location == INTERP_SAMPLE)
2845 return ctx->linear_sample;
2846 break;
2847 }
2848 return NULL;
2849 }
2850
2851 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2852 LLVMValueRef sample_id)
2853 {
2854 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2855 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2856 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2857 LLVMValueRef result[2];
2858
2859 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2860 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2861
2862 return ac_build_gather_values(&ctx->ac, result, 2);
2863 }
2864
2865 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2866 {
2867 LLVMValueRef values[2];
2868
2869 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2870 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2871 return ac_build_gather_values(&ctx->ac, values, 2);
2872 }
2873
2874 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2875 nir_intrinsic_instr *instr)
2876 {
2877 LLVMValueRef result[2];
2878 LLVMValueRef interp_param, attr_number;
2879 unsigned location;
2880 unsigned chan;
2881 LLVMValueRef src_c0, src_c1;
2882 LLVMValueRef src0;
2883 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2884 switch (instr->intrinsic) {
2885 case nir_intrinsic_interp_var_at_centroid:
2886 location = INTERP_CENTROID;
2887 break;
2888 case nir_intrinsic_interp_var_at_sample:
2889 location = INTERP_SAMPLE;
2890 src0 = get_src(ctx, instr->src[0]);
2891 break;
2892 case nir_intrinsic_interp_var_at_offset:
2893 location = INTERP_CENTER;
2894 src0 = get_src(ctx, instr->src[0]);
2895 default:
2896 break;
2897 }
2898
2899 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2900 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2901 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2902 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2903 LLVMValueRef sample_position;
2904 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2905
2906 /* fetch sample ID */
2907 sample_position = load_sample_position(ctx, src0);
2908
2909 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2910 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2911 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2912 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2913 }
2914 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2915 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2916
2917 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
2918 LLVMValueRef ij_out[2];
2919 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2920
2921 /*
2922 * take the I then J parameters, and the DDX/Y for it, and
2923 * calculate the IJ inputs for the interpolator.
2924 * temp1 = ddx * offset/sample.x + I;
2925 * interp_param.I = ddy * offset/sample.y + temp1;
2926 * temp1 = ddx * offset/sample.x + J;
2927 * interp_param.J = ddy * offset/sample.y + temp1;
2928 */
2929 for (unsigned i = 0; i < 2; i++) {
2930 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
2931 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
2932 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
2933 ddxy_out, ix_ll, "");
2934 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
2935 ddxy_out, iy_ll, "");
2936 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
2937 interp_param, ix_ll, "");
2938 LLVMValueRef temp1, temp2;
2939
2940 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
2941 ctx->f32, "");
2942
2943 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
2944 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
2945
2946 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
2947 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
2948
2949 ij_out[i] = LLVMBuildBitCast(ctx->builder,
2950 temp2, ctx->i32, "");
2951 }
2952 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
2953
2954 }
2955
2956 for (chan = 0; chan < 2; chan++) {
2957 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
2958
2959 if (interp_param) {
2960 interp_param = LLVMBuildBitCast(ctx->builder,
2961 interp_param, LLVMVectorType(ctx->f32, 2), "");
2962 LLVMValueRef i = LLVMBuildExtractElement(
2963 ctx->builder, interp_param, ctx->i32zero, "");
2964 LLVMValueRef j = LLVMBuildExtractElement(
2965 ctx->builder, interp_param, ctx->i32one, "");
2966
2967 result[chan] = ac_build_fs_interp(&ctx->ac,
2968 llvm_chan, attr_number,
2969 ctx->prim_mask, i, j);
2970 } else {
2971 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2972 LLVMConstInt(ctx->i32, 2, false),
2973 llvm_chan, attr_number,
2974 ctx->prim_mask);
2975 }
2976 }
2977 return ac_build_gather_values(&ctx->ac, result, 2);
2978 }
2979
2980 static void
2981 visit_emit_vertex(struct nir_to_llvm_context *ctx,
2982 nir_intrinsic_instr *instr)
2983 {
2984 LLVMValueRef gs_next_vertex;
2985 LLVMValueRef can_emit, kill;
2986 int idx;
2987 int clip_cull_slot = -1;
2988 assert(instr->const_index[0] == 0);
2989 /* Write vertex attribute values to GSVS ring */
2990 gs_next_vertex = LLVMBuildLoad(ctx->builder,
2991 ctx->gs_next_vertex,
2992 "");
2993
2994 /* If this thread has already emitted the declared maximum number of
2995 * vertices, kill it: excessive vertex emissions are not supposed to
2996 * have any effect, and GS threads have no externally observable
2997 * effects other than emitting vertices.
2998 */
2999 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3000 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3001
3002 kill = LLVMBuildSelect(ctx->builder, can_emit,
3003 LLVMConstReal(ctx->f32, 1.0f),
3004 LLVMConstReal(ctx->f32, -1.0f), "");
3005 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3006 ctx->voidt, &kill, 1, 0);
3007
3008 /* loop num outputs */
3009 idx = 0;
3010 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3011 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3012 int length = 4;
3013 int start = 0;
3014 int slot = idx;
3015 int slot_inc = 1;
3016
3017 if (!(ctx->output_mask & (1ull << i)))
3018 continue;
3019
3020 if (i == VARYING_SLOT_CLIP_DIST1 ||
3021 i == VARYING_SLOT_CULL_DIST1)
3022 continue;
3023
3024 if (i == VARYING_SLOT_CLIP_DIST0 ||
3025 i == VARYING_SLOT_CULL_DIST0) {
3026 /* pack clip and cull into a single set of slots */
3027 if (clip_cull_slot == -1) {
3028 clip_cull_slot = idx;
3029 if (ctx->num_output_clips + ctx->num_output_culls > 4)
3030 slot_inc = 2;
3031 } else {
3032 slot = clip_cull_slot;
3033 slot_inc = 0;
3034 }
3035 if (i == VARYING_SLOT_CLIP_DIST0)
3036 length = ctx->num_output_clips;
3037 if (i == VARYING_SLOT_CULL_DIST0) {
3038 start = ctx->num_output_clips;
3039 length = ctx->num_output_culls;
3040 }
3041 }
3042 for (unsigned j = 0; j < length; j++) {
3043 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3044 out_ptr[j], "");
3045 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j + start) * ctx->gs_max_out_vertices, false);
3046 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3047 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3048
3049 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3050
3051 ac_build_tbuffer_store(&ctx->ac, ctx->gsvs_ring,
3052 out_val, 1,
3053 voffset, ctx->gs2vs_offset, 0,
3054 V_008F0C_BUF_DATA_FORMAT_32,
3055 V_008F0C_BUF_NUM_FORMAT_UINT,
3056 1, 0, 1, 1, 0);
3057 }
3058 idx += slot_inc;
3059 }
3060
3061 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3062 ctx->i32one, "");
3063 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3064
3065 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3066 }
3067
3068 static void
3069 visit_end_primitive(struct nir_to_llvm_context *ctx,
3070 nir_intrinsic_instr *instr)
3071 {
3072 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3073 }
3074
3075 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3076 nir_intrinsic_instr *instr)
3077 {
3078 LLVMValueRef result = NULL;
3079
3080 switch (instr->intrinsic) {
3081 case nir_intrinsic_load_work_group_id: {
3082 result = ctx->workgroup_ids;
3083 break;
3084 }
3085 case nir_intrinsic_load_base_vertex: {
3086 result = ctx->base_vertex;
3087 break;
3088 }
3089 case nir_intrinsic_load_vertex_id_zero_base: {
3090 result = ctx->vertex_id;
3091 break;
3092 }
3093 case nir_intrinsic_load_local_invocation_id: {
3094 result = ctx->local_invocation_ids;
3095 break;
3096 }
3097 case nir_intrinsic_load_base_instance:
3098 result = ctx->start_instance;
3099 break;
3100 case nir_intrinsic_load_draw_id:
3101 result = ctx->draw_index;
3102 break;
3103 case nir_intrinsic_load_invocation_id:
3104 result = ctx->gs_invocation_id;
3105 break;
3106 case nir_intrinsic_load_primitive_id:
3107 if (ctx->stage == MESA_SHADER_GEOMETRY)
3108 result = ctx->gs_prim_id;
3109 else
3110 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3111 break;
3112 case nir_intrinsic_load_sample_id:
3113 ctx->shader_info->fs.force_persample = true;
3114 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3115 break;
3116 case nir_intrinsic_load_sample_pos:
3117 ctx->shader_info->fs.force_persample = true;
3118 result = load_sample_pos(ctx);
3119 break;
3120 case nir_intrinsic_load_sample_mask_in:
3121 result = ctx->sample_coverage;
3122 break;
3123 case nir_intrinsic_load_front_face:
3124 result = ctx->front_face;
3125 break;
3126 case nir_intrinsic_load_instance_id:
3127 result = ctx->instance_id;
3128 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3129 ctx->shader_info->vs.vgpr_comp_cnt);
3130 break;
3131 case nir_intrinsic_load_num_work_groups:
3132 result = ctx->num_work_groups;
3133 break;
3134 case nir_intrinsic_load_local_invocation_index:
3135 result = visit_load_local_invocation_index(ctx);
3136 break;
3137 case nir_intrinsic_load_push_constant:
3138 result = visit_load_push_constant(ctx, instr);
3139 break;
3140 case nir_intrinsic_vulkan_resource_index:
3141 result = visit_vulkan_resource_index(ctx, instr);
3142 break;
3143 case nir_intrinsic_store_ssbo:
3144 visit_store_ssbo(ctx, instr);
3145 break;
3146 case nir_intrinsic_load_ssbo:
3147 result = visit_load_buffer(ctx, instr);
3148 break;
3149 case nir_intrinsic_ssbo_atomic_add:
3150 case nir_intrinsic_ssbo_atomic_imin:
3151 case nir_intrinsic_ssbo_atomic_umin:
3152 case nir_intrinsic_ssbo_atomic_imax:
3153 case nir_intrinsic_ssbo_atomic_umax:
3154 case nir_intrinsic_ssbo_atomic_and:
3155 case nir_intrinsic_ssbo_atomic_or:
3156 case nir_intrinsic_ssbo_atomic_xor:
3157 case nir_intrinsic_ssbo_atomic_exchange:
3158 case nir_intrinsic_ssbo_atomic_comp_swap:
3159 result = visit_atomic_ssbo(ctx, instr);
3160 break;
3161 case nir_intrinsic_load_ubo:
3162 result = visit_load_ubo_buffer(ctx, instr);
3163 break;
3164 case nir_intrinsic_get_buffer_size:
3165 result = visit_get_buffer_size(ctx, instr);
3166 break;
3167 case nir_intrinsic_load_var:
3168 result = visit_load_var(ctx, instr);
3169 break;
3170 case nir_intrinsic_store_var:
3171 visit_store_var(ctx, instr);
3172 break;
3173 case nir_intrinsic_image_load:
3174 result = visit_image_load(ctx, instr);
3175 break;
3176 case nir_intrinsic_image_store:
3177 visit_image_store(ctx, instr);
3178 break;
3179 case nir_intrinsic_image_atomic_add:
3180 case nir_intrinsic_image_atomic_min:
3181 case nir_intrinsic_image_atomic_max:
3182 case nir_intrinsic_image_atomic_and:
3183 case nir_intrinsic_image_atomic_or:
3184 case nir_intrinsic_image_atomic_xor:
3185 case nir_intrinsic_image_atomic_exchange:
3186 case nir_intrinsic_image_atomic_comp_swap:
3187 result = visit_image_atomic(ctx, instr);
3188 break;
3189 case nir_intrinsic_image_size:
3190 result = visit_image_size(ctx, instr);
3191 break;
3192 case nir_intrinsic_discard:
3193 ctx->shader_info->fs.can_discard = true;
3194 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3195 ctx->voidt,
3196 NULL, 0, 0);
3197 break;
3198 case nir_intrinsic_discard_if:
3199 emit_discard_if(ctx, instr);
3200 break;
3201 case nir_intrinsic_memory_barrier:
3202 emit_waitcnt(ctx);
3203 break;
3204 case nir_intrinsic_barrier:
3205 emit_barrier(ctx);
3206 break;
3207 case nir_intrinsic_var_atomic_add:
3208 case nir_intrinsic_var_atomic_imin:
3209 case nir_intrinsic_var_atomic_umin:
3210 case nir_intrinsic_var_atomic_imax:
3211 case nir_intrinsic_var_atomic_umax:
3212 case nir_intrinsic_var_atomic_and:
3213 case nir_intrinsic_var_atomic_or:
3214 case nir_intrinsic_var_atomic_xor:
3215 case nir_intrinsic_var_atomic_exchange:
3216 case nir_intrinsic_var_atomic_comp_swap:
3217 result = visit_var_atomic(ctx, instr);
3218 break;
3219 case nir_intrinsic_interp_var_at_centroid:
3220 case nir_intrinsic_interp_var_at_sample:
3221 case nir_intrinsic_interp_var_at_offset:
3222 result = visit_interp(ctx, instr);
3223 break;
3224 case nir_intrinsic_emit_vertex:
3225 visit_emit_vertex(ctx, instr);
3226 break;
3227 case nir_intrinsic_end_primitive:
3228 visit_end_primitive(ctx, instr);
3229 break;
3230 default:
3231 fprintf(stderr, "Unknown intrinsic: ");
3232 nir_print_instr(&instr->instr, stderr);
3233 fprintf(stderr, "\n");
3234 break;
3235 }
3236 if (result) {
3237 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3238 }
3239 }
3240
3241 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3242 nir_deref_var *deref,
3243 enum desc_type desc_type)
3244 {
3245 unsigned desc_set = deref->var->data.descriptor_set;
3246 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3247 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3248 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3249 unsigned offset = binding->offset;
3250 unsigned stride = binding->size;
3251 unsigned type_size;
3252 LLVMBuilderRef builder = ctx->builder;
3253 LLVMTypeRef type;
3254 LLVMValueRef index = NULL;
3255
3256 assert(deref->var->data.binding < layout->binding_count);
3257
3258 switch (desc_type) {
3259 case DESC_IMAGE:
3260 type = ctx->v8i32;
3261 type_size = 32;
3262 break;
3263 case DESC_FMASK:
3264 type = ctx->v8i32;
3265 offset += 32;
3266 type_size = 32;
3267 break;
3268 case DESC_SAMPLER:
3269 type = ctx->v4i32;
3270 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3271 offset += 64;
3272
3273 type_size = 16;
3274 break;
3275 case DESC_BUFFER:
3276 type = ctx->v4i32;
3277 type_size = 16;
3278 break;
3279 default:
3280 unreachable("invalid desc_type\n");
3281 }
3282
3283 if (deref->deref.child) {
3284 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3285
3286 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3287 offset += child->base_offset * stride;
3288 if (child->deref_array_type == nir_deref_array_type_indirect) {
3289 index = get_src(ctx, child->indirect);
3290 }
3291 }
3292
3293 assert(stride % type_size == 0);
3294
3295 if (!index)
3296 index = ctx->i32zero;
3297
3298 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3299
3300 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3301 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3302
3303 return ac_build_indexed_load_const(&ctx->ac, list, index);
3304 }
3305
3306 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3307 struct ac_tex_info *tinfo,
3308 nir_tex_instr *instr,
3309 nir_texop op,
3310 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3311 LLVMValueRef *param, unsigned count,
3312 unsigned dmask)
3313 {
3314 int num_args;
3315 unsigned is_rect = 0;
3316 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3317
3318 if (op == nir_texop_lod)
3319 da = false;
3320 /* Pad to power of two vector */
3321 while (count < util_next_power_of_two(count))
3322 param[count++] = LLVMGetUndef(ctx->i32);
3323
3324 if (count > 1)
3325 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3326 else
3327 tinfo->args[0] = param[0];
3328
3329 tinfo->args[1] = res_ptr;
3330 num_args = 2;
3331
3332 if (op == nir_texop_txf ||
3333 op == nir_texop_txf_ms ||
3334 op == nir_texop_query_levels ||
3335 op == nir_texop_texture_samples ||
3336 op == nir_texop_txs)
3337 tinfo->dst_type = ctx->v4i32;
3338 else {
3339 tinfo->dst_type = ctx->v4f32;
3340 tinfo->args[num_args++] = samp_ptr;
3341 }
3342
3343 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3344 tinfo->args[0] = res_ptr;
3345 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3346 tinfo->args[2] = param[0];
3347 tinfo->arg_count = 3;
3348 return;
3349 }
3350
3351 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3352 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3353 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3354 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3355 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3356 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3357 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3358 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3359
3360 tinfo->arg_count = num_args;
3361 }
3362
3363 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3364 *
3365 * SI-CI:
3366 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3367 * filtering manually. The driver sets img7 to a mask clearing
3368 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3369 * s_and_b32 samp0, samp0, img7
3370 *
3371 * VI:
3372 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3373 */
3374 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3375 LLVMValueRef res, LLVMValueRef samp)
3376 {
3377 LLVMBuilderRef builder = ctx->builder;
3378 LLVMValueRef img7, samp0;
3379
3380 if (ctx->options->chip_class >= VI)
3381 return samp;
3382
3383 img7 = LLVMBuildExtractElement(builder, res,
3384 LLVMConstInt(ctx->i32, 7, 0), "");
3385 samp0 = LLVMBuildExtractElement(builder, samp,
3386 LLVMConstInt(ctx->i32, 0, 0), "");
3387 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3388 return LLVMBuildInsertElement(builder, samp, samp0,
3389 LLVMConstInt(ctx->i32, 0, 0), "");
3390 }
3391
3392 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3393 nir_tex_instr *instr,
3394 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3395 LLVMValueRef *fmask_ptr)
3396 {
3397 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3398 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3399 else
3400 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3401 if (samp_ptr) {
3402 if (instr->sampler)
3403 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3404 else
3405 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3406 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3407 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3408 }
3409 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3410 instr->op == nir_texop_samples_identical))
3411 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3412 }
3413
3414 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3415 LLVMValueRef coord)
3416 {
3417 coord = to_float(ctx, coord);
3418 coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3419 coord = to_integer(ctx, coord);
3420 return coord;
3421 }
3422
3423 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3424 {
3425 LLVMValueRef result = NULL;
3426 struct ac_tex_info tinfo = { 0 };
3427 unsigned dmask = 0xf;
3428 LLVMValueRef address[16];
3429 LLVMValueRef coords[5];
3430 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3431 LLVMValueRef bias = NULL, offsets = NULL;
3432 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3433 LLVMValueRef ddx = NULL, ddy = NULL;
3434 LLVMValueRef derivs[6];
3435 unsigned chan, count = 0;
3436 unsigned const_src = 0, num_deriv_comp = 0;
3437
3438 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3439
3440 for (unsigned i = 0; i < instr->num_srcs; i++) {
3441 switch (instr->src[i].src_type) {
3442 case nir_tex_src_coord:
3443 coord = get_src(ctx, instr->src[i].src);
3444 break;
3445 case nir_tex_src_projector:
3446 break;
3447 case nir_tex_src_comparator:
3448 comparator = get_src(ctx, instr->src[i].src);
3449 break;
3450 case nir_tex_src_offset:
3451 offsets = get_src(ctx, instr->src[i].src);
3452 const_src = i;
3453 break;
3454 case nir_tex_src_bias:
3455 bias = get_src(ctx, instr->src[i].src);
3456 break;
3457 case nir_tex_src_lod:
3458 lod = get_src(ctx, instr->src[i].src);
3459 break;
3460 case nir_tex_src_ms_index:
3461 sample_index = get_src(ctx, instr->src[i].src);
3462 break;
3463 case nir_tex_src_ms_mcs:
3464 break;
3465 case nir_tex_src_ddx:
3466 ddx = get_src(ctx, instr->src[i].src);
3467 num_deriv_comp = instr->src[i].src.ssa->num_components;
3468 break;
3469 case nir_tex_src_ddy:
3470 ddy = get_src(ctx, instr->src[i].src);
3471 break;
3472 case nir_tex_src_texture_offset:
3473 case nir_tex_src_sampler_offset:
3474 case nir_tex_src_plane:
3475 default:
3476 break;
3477 }
3478 }
3479
3480 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3481 result = get_buffer_size(ctx, res_ptr, false);
3482 goto write_result;
3483 }
3484
3485 if (instr->op == nir_texop_texture_samples) {
3486 LLVMValueRef res, samples, is_msaa;
3487 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3488 samples = LLVMBuildExtractElement(ctx->builder, res,
3489 LLVMConstInt(ctx->i32, 3, false), "");
3490 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3491 LLVMConstInt(ctx->i32, 28, false), "");
3492 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3493 LLVMConstInt(ctx->i32, 0xe, false), "");
3494 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3495 LLVMConstInt(ctx->i32, 0xe, false), "");
3496
3497 samples = LLVMBuildLShr(ctx->builder, samples,
3498 LLVMConstInt(ctx->i32, 16, false), "");
3499 samples = LLVMBuildAnd(ctx->builder, samples,
3500 LLVMConstInt(ctx->i32, 0xf, false), "");
3501 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3502 samples, "");
3503 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3504 ctx->i32one, "");
3505 result = samples;
3506 goto write_result;
3507 }
3508
3509 if (coord)
3510 for (chan = 0; chan < instr->coord_components; chan++)
3511 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3512
3513 if (offsets && instr->op != nir_texop_txf) {
3514 LLVMValueRef offset[3], pack;
3515 for (chan = 0; chan < 3; ++chan)
3516 offset[chan] = ctx->i32zero;
3517
3518 tinfo.has_offset = true;
3519 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3520 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3521 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3522 LLVMConstInt(ctx->i32, 0x3f, false), "");
3523 if (chan)
3524 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3525 LLVMConstInt(ctx->i32, chan * 8, false), "");
3526 }
3527 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3528 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3529 address[count++] = pack;
3530
3531 }
3532 /* pack LOD bias value */
3533 if (instr->op == nir_texop_txb && bias) {
3534 address[count++] = bias;
3535 }
3536
3537 /* Pack depth comparison value */
3538 if (instr->is_shadow && comparator) {
3539 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3540 }
3541
3542 /* pack derivatives */
3543 if (ddx || ddy) {
3544 switch (instr->sampler_dim) {
3545 case GLSL_SAMPLER_DIM_3D:
3546 case GLSL_SAMPLER_DIM_CUBE:
3547 num_deriv_comp = 3;
3548 break;
3549 case GLSL_SAMPLER_DIM_2D:
3550 default:
3551 num_deriv_comp = 2;
3552 break;
3553 case GLSL_SAMPLER_DIM_1D:
3554 num_deriv_comp = 1;
3555 break;
3556 }
3557
3558 for (unsigned i = 0; i < num_deriv_comp; i++) {
3559 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3560 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3561 }
3562 }
3563
3564 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3565 for (chan = 0; chan < instr->coord_components; chan++)
3566 coords[chan] = to_float(ctx, coords[chan]);
3567 if (instr->coord_components == 3)
3568 coords[3] = LLVMGetUndef(ctx->f32);
3569 ac_prepare_cube_coords(&ctx->ac,
3570 instr->op == nir_texop_txd, instr->is_array,
3571 coords, derivs);
3572 if (num_deriv_comp)
3573 num_deriv_comp--;
3574 }
3575
3576 if (ddx || ddy) {
3577 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3578 address[count++] = derivs[i];
3579 }
3580
3581 /* Pack texture coordinates */
3582 if (coord) {
3583 address[count++] = coords[0];
3584 if (instr->coord_components > 1) {
3585 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3586 coords[1] = apply_round_slice(ctx, coords[1]);
3587 }
3588 address[count++] = coords[1];
3589 }
3590 if (instr->coord_components > 2) {
3591 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3592 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3593 coords[2] = apply_round_slice(ctx, coords[2]);
3594 }
3595 address[count++] = coords[2];
3596 }
3597 }
3598
3599 /* Pack LOD */
3600 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3601 address[count++] = lod;
3602 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3603 address[count++] = sample_index;
3604 } else if(instr->op == nir_texop_txs) {
3605 count = 0;
3606 if (lod)
3607 address[count++] = lod;
3608 else
3609 address[count++] = ctx->i32zero;
3610 }
3611
3612 for (chan = 0; chan < count; chan++) {
3613 address[chan] = LLVMBuildBitCast(ctx->builder,
3614 address[chan], ctx->i32, "");
3615 }
3616
3617 if (instr->op == nir_texop_samples_identical) {
3618 LLVMValueRef txf_address[4];
3619 struct ac_tex_info txf_info = { 0 };
3620 unsigned txf_count = count;
3621 memcpy(txf_address, address, sizeof(txf_address));
3622
3623 if (!instr->is_array)
3624 txf_address[2] = ctx->i32zero;
3625 txf_address[3] = ctx->i32zero;
3626
3627 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3628 fmask_ptr, NULL,
3629 txf_address, txf_count, 0xf);
3630
3631 result = build_tex_intrinsic(ctx, instr, &txf_info);
3632
3633 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3634 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3635 goto write_result;
3636 }
3637
3638 /* Adjust the sample index according to FMASK.
3639 *
3640 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3641 * which is the identity mapping. Each nibble says which physical sample
3642 * should be fetched to get that sample.
3643 *
3644 * For example, 0x11111100 means there are only 2 samples stored and
3645 * the second sample covers 3/4 of the pixel. When reading samples 0
3646 * and 1, return physical sample 0 (determined by the first two 0s
3647 * in FMASK), otherwise return physical sample 1.
3648 *
3649 * The sample index should be adjusted as follows:
3650 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3651 */
3652 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3653 instr->op != nir_texop_txs) {
3654 LLVMValueRef txf_address[4];
3655 struct ac_tex_info txf_info = { 0 };
3656 unsigned txf_count = count;
3657 memcpy(txf_address, address, sizeof(txf_address));
3658
3659 if (!instr->is_array)
3660 txf_address[2] = ctx->i32zero;
3661 txf_address[3] = ctx->i32zero;
3662
3663 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3664 fmask_ptr, NULL,
3665 txf_address, txf_count, 0xf);
3666
3667 result = build_tex_intrinsic(ctx, instr, &txf_info);
3668 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3669 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3670
3671 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3672 result,
3673 ctx->i32zero, "");
3674
3675 unsigned sample_chan = instr->is_array ? 3 : 2;
3676
3677 LLVMValueRef sample_index4 =
3678 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3679 LLVMValueRef shifted_fmask =
3680 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3681 LLVMValueRef final_sample =
3682 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3683
3684 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3685 * resource descriptor is 0 (invalid),
3686 */
3687 LLVMValueRef fmask_desc =
3688 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3689 ctx->v8i32, "");
3690
3691 LLVMValueRef fmask_word1 =
3692 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3693 ctx->i32one, "");
3694
3695 LLVMValueRef word1_is_nonzero =
3696 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3697 fmask_word1, ctx->i32zero, "");
3698
3699 /* Replace the MSAA sample index. */
3700 address[sample_chan] =
3701 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3702 final_sample, address[sample_chan], "");
3703 }
3704
3705 if (offsets && instr->op == nir_texop_txf) {
3706 nir_const_value *const_offset =
3707 nir_src_as_const_value(instr->src[const_src].src);
3708 int num_offsets = instr->src[const_src].src.ssa->num_components;
3709 assert(const_offset);
3710 num_offsets = MIN2(num_offsets, instr->coord_components);
3711 if (num_offsets > 2)
3712 address[2] = LLVMBuildAdd(ctx->builder,
3713 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3714 if (num_offsets > 1)
3715 address[1] = LLVMBuildAdd(ctx->builder,
3716 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3717 address[0] = LLVMBuildAdd(ctx->builder,
3718 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3719
3720 }
3721
3722 /* TODO TG4 support */
3723 if (instr->op == nir_texop_tg4) {
3724 if (instr->is_shadow)
3725 dmask = 1;
3726 else
3727 dmask = 1 << instr->component;
3728 }
3729 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3730 res_ptr, samp_ptr, address, count, dmask);
3731
3732 result = build_tex_intrinsic(ctx, instr, &tinfo);
3733
3734 if (instr->op == nir_texop_query_levels)
3735 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3736 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3737 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3738 else if (instr->op == nir_texop_txs &&
3739 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3740 instr->is_array) {
3741 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3742 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3743 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3744 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3745 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3746 } else if (instr->dest.ssa.num_components != 4)
3747 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3748
3749 write_result:
3750 if (result) {
3751 assert(instr->dest.is_ssa);
3752 result = to_integer(ctx, result);
3753 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3754 }
3755 }
3756
3757
3758 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3759 {
3760 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3761 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3762
3763 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3764 _mesa_hash_table_insert(ctx->phis, instr, result);
3765 }
3766
3767 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3768 nir_phi_instr *instr,
3769 LLVMValueRef llvm_phi)
3770 {
3771 nir_foreach_phi_src(src, instr) {
3772 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3773 LLVMValueRef llvm_src = get_src(ctx, src->src);
3774
3775 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3776 }
3777 }
3778
3779 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3780 {
3781 struct hash_entry *entry;
3782 hash_table_foreach(ctx->phis, entry) {
3783 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3784 (LLVMValueRef)entry->data);
3785 }
3786 }
3787
3788
3789 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3790 nir_ssa_undef_instr *instr)
3791 {
3792 unsigned num_components = instr->def.num_components;
3793 LLVMValueRef undef;
3794
3795 if (num_components == 1)
3796 undef = LLVMGetUndef(ctx->i32);
3797 else {
3798 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3799 }
3800 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3801 }
3802
3803 static void visit_jump(struct nir_to_llvm_context *ctx,
3804 nir_jump_instr *instr)
3805 {
3806 switch (instr->type) {
3807 case nir_jump_break:
3808 LLVMBuildBr(ctx->builder, ctx->break_block);
3809 LLVMClearInsertionPosition(ctx->builder);
3810 break;
3811 case nir_jump_continue:
3812 LLVMBuildBr(ctx->builder, ctx->continue_block);
3813 LLVMClearInsertionPosition(ctx->builder);
3814 break;
3815 default:
3816 fprintf(stderr, "Unknown NIR jump instr: ");
3817 nir_print_instr(&instr->instr, stderr);
3818 fprintf(stderr, "\n");
3819 abort();
3820 }
3821 }
3822
3823 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3824 struct exec_list *list);
3825
3826 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3827 {
3828 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3829 nir_foreach_instr(instr, block)
3830 {
3831 switch (instr->type) {
3832 case nir_instr_type_alu:
3833 visit_alu(ctx, nir_instr_as_alu(instr));
3834 break;
3835 case nir_instr_type_load_const:
3836 visit_load_const(ctx, nir_instr_as_load_const(instr));
3837 break;
3838 case nir_instr_type_intrinsic:
3839 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3840 break;
3841 case nir_instr_type_tex:
3842 visit_tex(ctx, nir_instr_as_tex(instr));
3843 break;
3844 case nir_instr_type_phi:
3845 visit_phi(ctx, nir_instr_as_phi(instr));
3846 break;
3847 case nir_instr_type_ssa_undef:
3848 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3849 break;
3850 case nir_instr_type_jump:
3851 visit_jump(ctx, nir_instr_as_jump(instr));
3852 break;
3853 default:
3854 fprintf(stderr, "Unknown NIR instr type: ");
3855 nir_print_instr(instr, stderr);
3856 fprintf(stderr, "\n");
3857 abort();
3858 }
3859 }
3860
3861 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3862 }
3863
3864 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3865 {
3866 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3867
3868 LLVMBasicBlockRef merge_block =
3869 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3870 LLVMBasicBlockRef if_block =
3871 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3872 LLVMBasicBlockRef else_block = merge_block;
3873 if (!exec_list_is_empty(&if_stmt->else_list))
3874 else_block = LLVMAppendBasicBlockInContext(
3875 ctx->context, ctx->main_function, "");
3876
3877 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3878 LLVMConstInt(ctx->i32, 0, false), "");
3879 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3880
3881 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3882 visit_cf_list(ctx, &if_stmt->then_list);
3883 if (LLVMGetInsertBlock(ctx->builder))
3884 LLVMBuildBr(ctx->builder, merge_block);
3885
3886 if (!exec_list_is_empty(&if_stmt->else_list)) {
3887 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3888 visit_cf_list(ctx, &if_stmt->else_list);
3889 if (LLVMGetInsertBlock(ctx->builder))
3890 LLVMBuildBr(ctx->builder, merge_block);
3891 }
3892
3893 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3894 }
3895
3896 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3897 {
3898 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3899 LLVMBasicBlockRef break_parent = ctx->break_block;
3900
3901 ctx->continue_block =
3902 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3903 ctx->break_block =
3904 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3905
3906 LLVMBuildBr(ctx->builder, ctx->continue_block);
3907 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3908 visit_cf_list(ctx, &loop->body);
3909
3910 if (LLVMGetInsertBlock(ctx->builder))
3911 LLVMBuildBr(ctx->builder, ctx->continue_block);
3912 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3913
3914 ctx->continue_block = continue_parent;
3915 ctx->break_block = break_parent;
3916 }
3917
3918 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3919 struct exec_list *list)
3920 {
3921 foreach_list_typed(nir_cf_node, node, node, list)
3922 {
3923 switch (node->type) {
3924 case nir_cf_node_block:
3925 visit_block(ctx, nir_cf_node_as_block(node));
3926 break;
3927
3928 case nir_cf_node_if:
3929 visit_if(ctx, nir_cf_node_as_if(node));
3930 break;
3931
3932 case nir_cf_node_loop:
3933 visit_loop(ctx, nir_cf_node_as_loop(node));
3934 break;
3935
3936 default:
3937 assert(0);
3938 }
3939 }
3940 }
3941
3942 static void
3943 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3944 struct nir_variable *variable)
3945 {
3946 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3947 LLVMValueRef t_offset;
3948 LLVMValueRef t_list;
3949 LLVMValueRef args[3];
3950 LLVMValueRef input;
3951 LLVMValueRef buffer_index;
3952 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3953 int idx = variable->data.location;
3954 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3955
3956 variable->data.driver_location = idx * 4;
3957
3958 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3959 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3960 ctx->start_instance, "");
3961 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3962 ctx->shader_info->vs.vgpr_comp_cnt);
3963 } else
3964 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3965 ctx->base_vertex, "");
3966
3967 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3968 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3969
3970 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
3971 args[0] = t_list;
3972 args[1] = LLVMConstInt(ctx->i32, 0, false);
3973 args[2] = buffer_index;
3974 input = ac_emit_llvm_intrinsic(&ctx->ac,
3975 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3976 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3977
3978 for (unsigned chan = 0; chan < 4; chan++) {
3979 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3980 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3981 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3982 input, llvm_chan, ""));
3983 }
3984 }
3985 }
3986
3987 static void
3988 handle_gs_input_decl(struct nir_to_llvm_context *ctx,
3989 struct nir_variable *variable)
3990 {
3991 int idx = variable->data.location;
3992
3993 if (idx == VARYING_SLOT_CLIP_DIST0 ||
3994 idx == VARYING_SLOT_CULL_DIST0) {
3995 int length = glsl_get_length(glsl_get_array_element(variable->type));
3996 if (idx == VARYING_SLOT_CLIP_DIST0)
3997 ctx->num_input_clips = length;
3998 else
3999 ctx->num_input_culls = length;
4000 }
4001 }
4002
4003 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4004 unsigned attr,
4005 LLVMValueRef interp_param,
4006 LLVMValueRef prim_mask,
4007 LLVMValueRef result[4])
4008 {
4009 LLVMValueRef attr_number;
4010 unsigned chan;
4011 LLVMValueRef i, j;
4012 bool interp = interp_param != NULL;
4013
4014 attr_number = LLVMConstInt(ctx->i32, attr, false);
4015
4016 /* fs.constant returns the param from the middle vertex, so it's not
4017 * really useful for flat shading. It's meant to be used for custom
4018 * interpolation (but the intrinsic can't fetch from the other two
4019 * vertices).
4020 *
4021 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4022 * to do the right thing. The only reason we use fs.constant is that
4023 * fs.interp cannot be used on integers, because they can be equal
4024 * to NaN.
4025 */
4026 if (interp) {
4027 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4028 LLVMVectorType(ctx->f32, 2), "");
4029
4030 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4031 ctx->i32zero, "");
4032 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4033 ctx->i32one, "");
4034 }
4035
4036 for (chan = 0; chan < 4; chan++) {
4037 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4038
4039 if (interp) {
4040 result[chan] = ac_build_fs_interp(&ctx->ac,
4041 llvm_chan,
4042 attr_number,
4043 prim_mask, i, j);
4044 } else {
4045 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4046 LLVMConstInt(ctx->i32, 2, false),
4047 llvm_chan,
4048 attr_number,
4049 prim_mask);
4050 }
4051 }
4052 }
4053
4054 static void
4055 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4056 struct nir_variable *variable)
4057 {
4058 int idx = variable->data.location;
4059 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4060 LLVMValueRef interp;
4061
4062 variable->data.driver_location = idx * 4;
4063 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4064
4065 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4066 unsigned interp_type;
4067 if (variable->data.sample) {
4068 interp_type = INTERP_SAMPLE;
4069 ctx->shader_info->fs.force_persample = true;
4070 } else if (variable->data.centroid)
4071 interp_type = INTERP_CENTROID;
4072 else
4073 interp_type = INTERP_CENTER;
4074
4075 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4076 } else
4077 interp = NULL;
4078
4079 for (unsigned i = 0; i < attrib_count; ++i)
4080 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4081
4082 }
4083
4084 static void
4085 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4086 struct nir_variable *variable)
4087 {
4088 switch (ctx->stage) {
4089 case MESA_SHADER_VERTEX:
4090 handle_vs_input_decl(ctx, variable);
4091 break;
4092 case MESA_SHADER_FRAGMENT:
4093 handle_fs_input_decl(ctx, variable);
4094 break;
4095 case MESA_SHADER_GEOMETRY:
4096 handle_gs_input_decl(ctx, variable);
4097 break;
4098 default:
4099 break;
4100 }
4101
4102 }
4103
4104 static void
4105 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4106 struct nir_shader *nir)
4107 {
4108 unsigned index = 0;
4109 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4110 LLVMValueRef interp_param;
4111 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4112
4113 if (!(ctx->input_mask & (1ull << i)))
4114 continue;
4115
4116 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4117 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4118 interp_param = *inputs;
4119 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4120 inputs);
4121
4122 if (!interp_param)
4123 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4124 ++index;
4125 } else if (i == VARYING_SLOT_POS) {
4126 for(int i = 0; i < 3; ++i)
4127 inputs[i] = ctx->frag_pos[i];
4128
4129 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4130 }
4131 }
4132 ctx->shader_info->fs.num_interp = index;
4133 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4134 ctx->shader_info->fs.has_pcoord = true;
4135 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4136 ctx->shader_info->fs.prim_id_input = true;
4137 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4138 ctx->shader_info->fs.layer_input = true;
4139 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4140 }
4141
4142 static LLVMValueRef
4143 ac_build_alloca(struct nir_to_llvm_context *ctx,
4144 LLVMTypeRef type,
4145 const char *name)
4146 {
4147 LLVMBuilderRef builder = ctx->builder;
4148 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4149 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4150 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4151 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4152 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4153 LLVMValueRef res;
4154
4155 if (first_instr) {
4156 LLVMPositionBuilderBefore(first_builder, first_instr);
4157 } else {
4158 LLVMPositionBuilderAtEnd(first_builder, first_block);
4159 }
4160
4161 res = LLVMBuildAlloca(first_builder, type, name);
4162 LLVMBuildStore(builder, LLVMConstNull(type), res);
4163
4164 LLVMDisposeBuilder(first_builder);
4165
4166 return res;
4167 }
4168
4169 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4170 LLVMTypeRef type,
4171 const char *name)
4172 {
4173 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4174 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4175 return ptr;
4176 }
4177
4178 static void
4179 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4180 struct nir_variable *variable)
4181 {
4182 int idx = variable->data.location + variable->data.index;
4183 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4184
4185 variable->data.driver_location = idx * 4;
4186
4187 if (ctx->stage == MESA_SHADER_VERTEX ||
4188 ctx->stage == MESA_SHADER_GEOMETRY) {
4189 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4190 idx == VARYING_SLOT_CULL_DIST0) {
4191 int length = glsl_get_length(variable->type);
4192 if (idx == VARYING_SLOT_CLIP_DIST0) {
4193 if (ctx->stage == MESA_SHADER_VERTEX)
4194 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4195 ctx->num_output_clips = length;
4196 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4197 if (ctx->stage == MESA_SHADER_VERTEX)
4198 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4199 ctx->num_output_culls = length;
4200 }
4201 if (length > 4)
4202 attrib_count = 2;
4203 else
4204 attrib_count = 1;
4205 }
4206 }
4207
4208 for (unsigned i = 0; i < attrib_count; ++i) {
4209 for (unsigned chan = 0; chan < 4; chan++) {
4210 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4211 si_build_alloca_undef(ctx, ctx->f32, "");
4212 }
4213 }
4214 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4215 }
4216
4217 static void
4218 setup_locals(struct nir_to_llvm_context *ctx,
4219 struct nir_function *func)
4220 {
4221 int i, j;
4222 ctx->num_locals = 0;
4223 nir_foreach_variable(variable, &func->impl->locals) {
4224 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4225 variable->data.driver_location = ctx->num_locals * 4;
4226 ctx->num_locals += attrib_count;
4227 }
4228 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4229 if (!ctx->locals)
4230 return;
4231
4232 for (i = 0; i < ctx->num_locals; i++) {
4233 for (j = 0; j < 4; j++) {
4234 ctx->locals[i * 4 + j] =
4235 si_build_alloca_undef(ctx, ctx->f32, "temp");
4236 }
4237 }
4238 }
4239
4240 static LLVMValueRef
4241 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4242 {
4243 v = to_float(ctx, v);
4244 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4245 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4246 }
4247
4248
4249 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4250 LLVMValueRef src0, LLVMValueRef src1)
4251 {
4252 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4253 LLVMValueRef comp[2];
4254
4255 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4256 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4257 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4258 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4259 }
4260
4261 /* Initialize arguments for the shader export intrinsic */
4262 static void
4263 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4264 LLVMValueRef *values,
4265 unsigned target,
4266 LLVMValueRef *args)
4267 {
4268 /* Default is 0xf. Adjusted below depending on the format. */
4269 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4270 /* Specify whether the EXEC mask represents the valid mask */
4271 args[1] = LLVMConstInt(ctx->i32, 0, false);
4272
4273 /* Specify whether this is the last export */
4274 args[2] = LLVMConstInt(ctx->i32, 0, false);
4275 /* Specify the target we are exporting */
4276 args[3] = LLVMConstInt(ctx->i32, target, false);
4277
4278 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4279 args[5] = LLVMGetUndef(ctx->f32);
4280 args[6] = LLVMGetUndef(ctx->f32);
4281 args[7] = LLVMGetUndef(ctx->f32);
4282 args[8] = LLVMGetUndef(ctx->f32);
4283
4284 if (!values)
4285 return;
4286
4287 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4288 LLVMValueRef val[4];
4289 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4290 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4291 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4292
4293 switch(col_format) {
4294 case V_028714_SPI_SHADER_ZERO:
4295 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4296 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4297 break;
4298
4299 case V_028714_SPI_SHADER_32_R:
4300 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4301 args[5] = values[0];
4302 break;
4303
4304 case V_028714_SPI_SHADER_32_GR:
4305 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4306 args[5] = values[0];
4307 args[6] = values[1];
4308 break;
4309
4310 case V_028714_SPI_SHADER_32_AR:
4311 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4312 args[5] = values[0];
4313 args[8] = values[3];
4314 break;
4315
4316 case V_028714_SPI_SHADER_FP16_ABGR:
4317 args[4] = ctx->i32one;
4318
4319 for (unsigned chan = 0; chan < 2; chan++) {
4320 LLVMValueRef pack_args[2] = {
4321 values[2 * chan],
4322 values[2 * chan + 1]
4323 };
4324 LLVMValueRef packed;
4325
4326 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4327 ctx->i32, pack_args, 2,
4328 AC_FUNC_ATTR_READNONE);
4329 args[chan + 5] = packed;
4330 }
4331 break;
4332
4333 case V_028714_SPI_SHADER_UNORM16_ABGR:
4334 for (unsigned chan = 0; chan < 4; chan++) {
4335 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4336 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4337 LLVMConstReal(ctx->f32, 65535), "");
4338 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4339 LLVMConstReal(ctx->f32, 0.5), "");
4340 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4341 ctx->i32, "");
4342 }
4343
4344 args[4] = ctx->i32one;
4345 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4346 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4347 break;
4348
4349 case V_028714_SPI_SHADER_SNORM16_ABGR:
4350 for (unsigned chan = 0; chan < 4; chan++) {
4351 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4352 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4353 LLVMConstReal(ctx->f32, 32767), "");
4354
4355 /* If positive, add 0.5, else add -0.5. */
4356 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4357 LLVMBuildSelect(ctx->builder,
4358 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4359 val[chan], ctx->f32zero, ""),
4360 LLVMConstReal(ctx->f32, 0.5),
4361 LLVMConstReal(ctx->f32, -0.5), ""), "");
4362 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4363 }
4364
4365 args[4] = ctx->i32one;
4366 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4367 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4368 break;
4369
4370 case V_028714_SPI_SHADER_UINT16_ABGR: {
4371 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4372
4373 for (unsigned chan = 0; chan < 4; chan++) {
4374 val[chan] = to_integer(ctx, values[chan]);
4375 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4376 }
4377
4378 args[4] = ctx->i32one;
4379 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4380 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4381 break;
4382 }
4383
4384 case V_028714_SPI_SHADER_SINT16_ABGR: {
4385 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4386 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4387
4388 /* Clamp. */
4389 for (unsigned chan = 0; chan < 4; chan++) {
4390 val[chan] = to_integer(ctx, values[chan]);
4391 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4392 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4393 }
4394
4395 args[4] = ctx->i32one;
4396 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4397 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4398 break;
4399 }
4400
4401 default:
4402 case V_028714_SPI_SHADER_32_ABGR:
4403 memcpy(&args[5], values, sizeof(values[0]) * 4);
4404 break;
4405 }
4406 } else
4407 memcpy(&args[5], values, sizeof(values[0]) * 4);
4408
4409 for (unsigned i = 5; i < 9; ++i)
4410 args[i] = to_float(ctx, args[i]);
4411 }
4412
4413 static void
4414 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4415 {
4416 uint32_t param_count = 0;
4417 unsigned target;
4418 unsigned pos_idx, num_pos_exports = 0;
4419 LLVMValueRef args[9];
4420 LLVMValueRef pos_args[4][9] = { { 0 } };
4421 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4422 int i;
4423 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4424 (1ull << VARYING_SLOT_CLIP_DIST1) |
4425 (1ull << VARYING_SLOT_CULL_DIST0) |
4426 (1ull << VARYING_SLOT_CULL_DIST1));
4427
4428 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4429 ctx->shader_info->vs.layer_output = 0xffffffff;
4430 if (clip_mask) {
4431 LLVMValueRef slots[8];
4432 unsigned j;
4433
4434 if (ctx->shader_info->vs.cull_dist_mask)
4435 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_output_clips;
4436
4437 i = VARYING_SLOT_CLIP_DIST0;
4438 for (j = 0; j < ctx->num_output_clips; j++)
4439 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4440 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4441 i = VARYING_SLOT_CULL_DIST0;
4442 for (j = 0; j < ctx->num_output_culls; j++)
4443 slots[ctx->num_output_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4444 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4445
4446 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
4447 slots[i] = LLVMGetUndef(ctx->f32);
4448
4449 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
4450 target = V_008DFC_SQ_EXP_POS + 3;
4451 si_llvm_init_export_args(ctx, &slots[4], target, args);
4452 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4453 args, sizeof(args));
4454 }
4455
4456 target = V_008DFC_SQ_EXP_POS + 2;
4457 si_llvm_init_export_args(ctx, &slots[0], target, args);
4458 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4459 args, sizeof(args));
4460
4461 }
4462
4463 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4464 LLVMValueRef values[4];
4465 if (!(ctx->output_mask & (1ull << i)))
4466 continue;
4467
4468 for (unsigned j = 0; j < 4; j++)
4469 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4470 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4471
4472 if (i == VARYING_SLOT_POS) {
4473 target = V_008DFC_SQ_EXP_POS;
4474 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4475 i == VARYING_SLOT_CLIP_DIST1 ||
4476 i == VARYING_SLOT_CULL_DIST0 ||
4477 i == VARYING_SLOT_CULL_DIST1) {
4478 continue;
4479 } else if (i == VARYING_SLOT_PSIZ) {
4480 ctx->shader_info->vs.writes_pointsize = true;
4481 psize_value = values[0];
4482 continue;
4483 } else if (i == VARYING_SLOT_LAYER) {
4484 ctx->shader_info->vs.writes_layer = true;
4485 layer_value = values[0];
4486 ctx->shader_info->vs.layer_output = param_count;
4487 target = V_008DFC_SQ_EXP_PARAM + param_count;
4488 param_count++;
4489 } else if (i == VARYING_SLOT_VIEWPORT) {
4490 ctx->shader_info->vs.writes_viewport_index = true;
4491 viewport_index_value = values[0];
4492 continue;
4493 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4494 ctx->shader_info->vs.prim_id_output = param_count;
4495 target = V_008DFC_SQ_EXP_PARAM + param_count;
4496 param_count++;
4497 } else if (i >= VARYING_SLOT_VAR0) {
4498 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4499 target = V_008DFC_SQ_EXP_PARAM + param_count;
4500 param_count++;
4501 }
4502
4503 si_llvm_init_export_args(ctx, values, target, args);
4504
4505 if (target >= V_008DFC_SQ_EXP_POS &&
4506 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4507 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4508 args, sizeof(args));
4509 } else {
4510 ac_emit_llvm_intrinsic(&ctx->ac,
4511 "llvm.SI.export",
4512 ctx->voidt,
4513 args, 9, 0);
4514 }
4515 }
4516
4517 /* We need to add the position output manually if it's missing. */
4518 if (!pos_args[0][0]) {
4519 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4520 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4521 pos_args[0][2] = ctx->i32zero; /* last export? */
4522 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4523 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4524 pos_args[0][5] = ctx->f32zero; /* X */
4525 pos_args[0][6] = ctx->f32zero; /* Y */
4526 pos_args[0][7] = ctx->f32zero; /* Z */
4527 pos_args[0][8] = ctx->f32one; /* W */
4528 }
4529
4530 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4531 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4532 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4533 if (mask) {
4534 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4535 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4536 pos_args[1][2] = ctx->i32zero; /* last export? */
4537 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4538 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4539 pos_args[1][5] = ctx->f32zero; /* X */
4540 pos_args[1][6] = ctx->f32zero; /* Y */
4541 pos_args[1][7] = ctx->f32zero; /* Z */
4542 pos_args[1][8] = ctx->f32zero; /* W */
4543
4544 if (ctx->shader_info->vs.writes_pointsize == true)
4545 pos_args[1][5] = psize_value;
4546 if (ctx->shader_info->vs.writes_layer == true)
4547 pos_args[1][7] = layer_value;
4548 if (ctx->shader_info->vs.writes_viewport_index == true)
4549 pos_args[1][8] = viewport_index_value;
4550 }
4551 for (i = 0; i < 4; i++) {
4552 if (pos_args[i][0])
4553 num_pos_exports++;
4554 }
4555
4556 pos_idx = 0;
4557 for (i = 0; i < 4; i++) {
4558 if (!pos_args[i][0])
4559 continue;
4560
4561 /* Specify the target we are exporting */
4562 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4563 if (pos_idx == num_pos_exports)
4564 pos_args[i][2] = ctx->i32one;
4565 ac_emit_llvm_intrinsic(&ctx->ac,
4566 "llvm.SI.export",
4567 ctx->voidt,
4568 pos_args[i], 9, 0);
4569 }
4570
4571 ctx->shader_info->vs.pos_exports = num_pos_exports;
4572 ctx->shader_info->vs.param_exports = param_count;
4573 }
4574
4575 static void
4576 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4577 {
4578 int j;
4579 uint64_t max_output_written = 0;
4580 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4581 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4582 int param_index;
4583 int length = 4;
4584 int start = 0;
4585 if (!(ctx->output_mask & (1ull << i)))
4586 continue;
4587
4588 if (i == VARYING_SLOT_CLIP_DIST0) {
4589 length = ctx->num_output_clips;
4590 } else if (i == VARYING_SLOT_CULL_DIST0) {
4591 start = ctx->num_output_clips;
4592 length = ctx->num_output_culls;
4593 }
4594 param_index = shader_io_get_unique_index(i);
4595
4596 if (param_index > max_output_written)
4597 max_output_written = param_index;
4598
4599 for (j = 0; j < length; j++) {
4600 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4601 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4602
4603 ac_build_tbuffer_store(&ctx->ac,
4604 ctx->esgs_ring,
4605 out_val, 1,
4606 LLVMGetUndef(ctx->i32), ctx->es2gs_offset,
4607 (4 * param_index + j + start) * 4,
4608 V_008F0C_BUF_DATA_FORMAT_32,
4609 V_008F0C_BUF_NUM_FORMAT_UINT,
4610 0, 0, 1, 1, 0);
4611 }
4612 }
4613 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4614 }
4615
4616 static void
4617 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4618 LLVMValueRef *color, unsigned param, bool is_last)
4619 {
4620 LLVMValueRef args[9];
4621 /* Export */
4622 si_llvm_init_export_args(ctx, color, param,
4623 args);
4624
4625 if (is_last) {
4626 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4627 args[2] = ctx->i32one; /* DONE bit */
4628 } else if (args[0] == ctx->i32zero)
4629 return; /* unnecessary NULL export */
4630
4631 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4632 ctx->voidt, args, 9, 0);
4633 }
4634
4635 static void
4636 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4637 LLVMValueRef depth, LLVMValueRef stencil,
4638 LLVMValueRef samplemask)
4639 {
4640 LLVMValueRef args[9];
4641 unsigned mask = 0;
4642 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4643 args[2] = ctx->i32one; /* DONE bit */
4644 /* Specify the target we are exporting */
4645 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4646
4647 args[4] = ctx->i32zero; /* COMP flag */
4648 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4649 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4650 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4651 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4652
4653 if (depth) {
4654 args[5] = depth;
4655 mask |= 0x1;
4656 }
4657
4658 if (stencil) {
4659 args[6] = stencil;
4660 mask |= 0x2;
4661 }
4662
4663 if (samplemask) {
4664 args[7] = samplemask;
4665 mask |= 0x04;
4666 }
4667
4668 /* SI (except OLAND) has a bug that it only looks
4669 * at the X writemask component. */
4670 if (ctx->options->chip_class == SI &&
4671 ctx->options->family != CHIP_OLAND)
4672 mask |= 0x01;
4673
4674 args[0] = LLVMConstInt(ctx->i32, mask, false);
4675 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4676 ctx->voidt, args, 9, 0);
4677 }
4678
4679 static void
4680 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4681 {
4682 unsigned index = 0;
4683 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4684
4685 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4686 LLVMValueRef values[4];
4687
4688 if (!(ctx->output_mask & (1ull << i)))
4689 continue;
4690
4691 if (i == FRAG_RESULT_DEPTH) {
4692 ctx->shader_info->fs.writes_z = true;
4693 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4694 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4695 } else if (i == FRAG_RESULT_STENCIL) {
4696 ctx->shader_info->fs.writes_stencil = true;
4697 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4698 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4699 } else {
4700 bool last = false;
4701 for (unsigned j = 0; j < 4; j++)
4702 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4703 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4704
4705 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4706 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4707
4708 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4709 index++;
4710 }
4711 }
4712
4713 if (depth || stencil)
4714 si_export_mrt_z(ctx, depth, stencil, samplemask);
4715 else if (!index)
4716 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4717
4718 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4719 }
4720
4721 static void
4722 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4723 {
4724 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4725 }
4726
4727 static void
4728 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4729 {
4730 switch (ctx->stage) {
4731 case MESA_SHADER_VERTEX:
4732 if (ctx->options->key.vs.as_es)
4733 handle_es_outputs_post(ctx);
4734 else
4735 handle_vs_outputs_post(ctx);
4736 break;
4737 case MESA_SHADER_FRAGMENT:
4738 handle_fs_outputs_post(ctx);
4739 break;
4740 case MESA_SHADER_GEOMETRY:
4741 emit_gs_epilogue(ctx);
4742 break;
4743 default:
4744 break;
4745 }
4746 }
4747
4748 static void
4749 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4750 struct nir_variable *variable, uint32_t *offset, int idx)
4751 {
4752 unsigned size = glsl_count_attribute_slots(variable->type, false);
4753 variable->data.driver_location = *offset;
4754 *offset += size;
4755 }
4756
4757 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4758 {
4759 LLVMPassManagerRef passmgr;
4760 /* Create the pass manager */
4761 passmgr = LLVMCreateFunctionPassManagerForModule(
4762 ctx->module);
4763
4764 /* This pass should eliminate all the load and store instructions */
4765 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4766
4767 /* Add some optimization passes */
4768 LLVMAddScalarReplAggregatesPass(passmgr);
4769 LLVMAddLICMPass(passmgr);
4770 LLVMAddAggressiveDCEPass(passmgr);
4771 LLVMAddCFGSimplificationPass(passmgr);
4772 LLVMAddInstructionCombiningPass(passmgr);
4773
4774 /* Run the pass */
4775 LLVMInitializeFunctionPassManager(passmgr);
4776 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4777 LLVMFinalizeFunctionPassManager(passmgr);
4778
4779 LLVMDisposeBuilder(ctx->builder);
4780 LLVMDisposePassManager(passmgr);
4781 }
4782
4783 static void
4784 ac_setup_rings(struct nir_to_llvm_context *ctx)
4785 {
4786 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4787 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4788 }
4789
4790 if (ctx->is_gs_copy_shader) {
4791 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4792 }
4793 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4794 LLVMValueRef tmp;
4795 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4796 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4797
4798 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4799
4800 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4801 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4802 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4803 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4804
4805 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4806 }
4807 }
4808
4809 static
4810 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4811 struct nir_shader *nir,
4812 struct ac_shader_variant_info *shader_info,
4813 const struct ac_nir_compiler_options *options)
4814 {
4815 struct nir_to_llvm_context ctx = {0};
4816 struct nir_function *func;
4817 unsigned i;
4818 ctx.options = options;
4819 ctx.shader_info = shader_info;
4820 ctx.context = LLVMContextCreate();
4821 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4822
4823 ac_llvm_context_init(&ctx.ac, ctx.context);
4824 ctx.ac.module = ctx.module;
4825
4826 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4827
4828 memset(shader_info, 0, sizeof(*shader_info));
4829
4830 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4831 setup_types(&ctx);
4832
4833 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4834 ctx.ac.builder = ctx.builder;
4835 ctx.stage = nir->stage;
4836
4837 for (i = 0; i < AC_UD_MAX_SETS; i++)
4838 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4839 for (i = 0; i < AC_UD_MAX_UD; i++)
4840 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4841
4842 create_function(&ctx);
4843
4844 if (nir->stage == MESA_SHADER_COMPUTE) {
4845 int num_shared = 0;
4846 nir_foreach_variable(variable, &nir->shared)
4847 num_shared++;
4848 if (num_shared) {
4849 int idx = 0;
4850 uint32_t shared_size = 0;
4851 LLVMValueRef var;
4852 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4853 nir_foreach_variable(variable, &nir->shared) {
4854 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4855 idx++;
4856 }
4857
4858 shared_size *= 16;
4859 var = LLVMAddGlobalInAddressSpace(ctx.module,
4860 LLVMArrayType(ctx.i8, shared_size),
4861 "compute_lds",
4862 LOCAL_ADDR_SPACE);
4863 LLVMSetAlignment(var, 4);
4864 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4865 }
4866 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4867 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4868
4869 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4870 }
4871
4872 ac_setup_rings(&ctx);
4873
4874 nir_foreach_variable(variable, &nir->inputs)
4875 handle_shader_input_decl(&ctx, variable);
4876
4877 if (nir->stage == MESA_SHADER_FRAGMENT)
4878 handle_fs_inputs_pre(&ctx, nir);
4879
4880 nir_foreach_variable(variable, &nir->outputs)
4881 handle_shader_output_decl(&ctx, variable);
4882
4883 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4884 _mesa_key_pointer_equal);
4885 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4886 _mesa_key_pointer_equal);
4887
4888 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4889
4890 setup_locals(&ctx, func);
4891
4892 visit_cf_list(&ctx, &func->impl->body);
4893 phi_post_pass(&ctx);
4894
4895 handle_shader_outputs_post(&ctx);
4896 LLVMBuildRetVoid(ctx.builder);
4897
4898 ac_llvm_finalize_module(&ctx);
4899 free(ctx.locals);
4900 ralloc_free(ctx.defs);
4901 ralloc_free(ctx.phis);
4902
4903 if (nir->stage == MESA_SHADER_GEOMETRY) {
4904 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4905 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4906 nir->info->gs.vertices_out;
4907 }
4908 return ctx.module;
4909 }
4910
4911 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4912 {
4913 unsigned *retval = (unsigned *)context;
4914 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4915 char *description = LLVMGetDiagInfoDescription(di);
4916
4917 if (severity == LLVMDSError) {
4918 *retval = 1;
4919 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4920 description);
4921 }
4922
4923 LLVMDisposeMessage(description);
4924 }
4925
4926 static unsigned ac_llvm_compile(LLVMModuleRef M,
4927 struct ac_shader_binary *binary,
4928 LLVMTargetMachineRef tm)
4929 {
4930 unsigned retval = 0;
4931 char *err;
4932 LLVMContextRef llvm_ctx;
4933 LLVMMemoryBufferRef out_buffer;
4934 unsigned buffer_size;
4935 const char *buffer_data;
4936 LLVMBool mem_err;
4937
4938 /* Setup Diagnostic Handler*/
4939 llvm_ctx = LLVMGetModuleContext(M);
4940
4941 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4942 &retval);
4943
4944 /* Compile IR*/
4945 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4946 &err, &out_buffer);
4947
4948 /* Process Errors/Warnings */
4949 if (mem_err) {
4950 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4951 free(err);
4952 retval = 1;
4953 goto out;
4954 }
4955
4956 /* Extract Shader Code*/
4957 buffer_size = LLVMGetBufferSize(out_buffer);
4958 buffer_data = LLVMGetBufferStart(out_buffer);
4959
4960 ac_elf_read(buffer_data, buffer_size, binary);
4961
4962 /* Clean up */
4963 LLVMDisposeMemoryBuffer(out_buffer);
4964
4965 out:
4966 return retval;
4967 }
4968
4969 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4970 LLVMModuleRef llvm_module,
4971 struct ac_shader_binary *binary,
4972 struct ac_shader_config *config,
4973 struct ac_shader_variant_info *shader_info,
4974 gl_shader_stage stage,
4975 bool dump_shader, bool supports_spill)
4976 {
4977 if (dump_shader)
4978 ac_dump_module(llvm_module);
4979
4980 memset(binary, 0, sizeof(*binary));
4981 int v = ac_llvm_compile(llvm_module, binary, tm);
4982 if (v) {
4983 fprintf(stderr, "compile failed\n");
4984 }
4985
4986 if (dump_shader)
4987 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4988
4989 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4990
4991 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4992 LLVMDisposeModule(llvm_module);
4993 LLVMContextDispose(ctx);
4994
4995 if (stage == MESA_SHADER_FRAGMENT) {
4996 shader_info->num_input_vgprs = 0;
4997 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4998 shader_info->num_input_vgprs += 2;
4999 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5000 shader_info->num_input_vgprs += 2;
5001 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5002 shader_info->num_input_vgprs += 2;
5003 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5004 shader_info->num_input_vgprs += 3;
5005 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5006 shader_info->num_input_vgprs += 2;
5007 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5008 shader_info->num_input_vgprs += 2;
5009 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5010 shader_info->num_input_vgprs += 2;
5011 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5012 shader_info->num_input_vgprs += 1;
5013 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5014 shader_info->num_input_vgprs += 1;
5015 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5016 shader_info->num_input_vgprs += 1;
5017 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5018 shader_info->num_input_vgprs += 1;
5019 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5020 shader_info->num_input_vgprs += 1;
5021 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5022 shader_info->num_input_vgprs += 1;
5023 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5024 shader_info->num_input_vgprs += 1;
5025 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5026 shader_info->num_input_vgprs += 1;
5027 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5028 shader_info->num_input_vgprs += 1;
5029 }
5030 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5031
5032 /* +3 for scratch wave offset and VCC */
5033 config->num_sgprs = MAX2(config->num_sgprs,
5034 shader_info->num_input_sgprs + 3);
5035 }
5036
5037 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5038 struct ac_shader_binary *binary,
5039 struct ac_shader_config *config,
5040 struct ac_shader_variant_info *shader_info,
5041 struct nir_shader *nir,
5042 const struct ac_nir_compiler_options *options,
5043 bool dump_shader)
5044 {
5045
5046 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5047 options);
5048
5049 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5050 switch (nir->stage) {
5051 case MESA_SHADER_COMPUTE:
5052 for (int i = 0; i < 3; ++i)
5053 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5054 break;
5055 case MESA_SHADER_FRAGMENT:
5056 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5057 break;
5058 case MESA_SHADER_GEOMETRY:
5059 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5060 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5061 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5062 shader_info->gs.invocations = nir->info->gs.invocations;
5063 break;
5064 case MESA_SHADER_VERTEX:
5065 shader_info->vs.as_es = options->key.vs.as_es;
5066 break;
5067 default:
5068 break;
5069 }
5070 }
5071
5072 static void
5073 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5074 {
5075 LLVMValueRef args[9];
5076 args[0] = ctx->gsvs_ring;
5077 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5078 args[3] = ctx->i32zero;
5079 args[4] = ctx->i32one; /* OFFEN */
5080 args[5] = ctx->i32zero; /* IDXEN */
5081 args[6] = ctx->i32one; /* GLC */
5082 args[7] = ctx->i32one; /* SLC */
5083 args[8] = ctx->i32zero; /* TFE */
5084
5085 int idx = 0;
5086 int clip_cull_slot = -1;
5087 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5088 int length = 4;
5089 int start = 0;
5090 int slot = idx;
5091 int slot_inc = 1;
5092 if (!(ctx->output_mask & (1ull << i)))
5093 continue;
5094
5095 if (i == VARYING_SLOT_CLIP_DIST1 ||
5096 i == VARYING_SLOT_CULL_DIST1)
5097 continue;
5098
5099 if (i == VARYING_SLOT_CLIP_DIST0 ||
5100 i == VARYING_SLOT_CULL_DIST0) {
5101 /* unpack clip and cull from a single set of slots */
5102 if (clip_cull_slot == -1) {
5103 clip_cull_slot = idx;
5104 if (ctx->num_output_clips + ctx->num_output_culls > 4)
5105 slot_inc = 2;
5106 } else {
5107 slot = clip_cull_slot;
5108 slot_inc = 0;
5109 }
5110 if (i == VARYING_SLOT_CLIP_DIST0)
5111 length = ctx->num_output_clips;
5112 if (i == VARYING_SLOT_CULL_DIST0) {
5113 start = ctx->num_output_clips;
5114 length = ctx->num_output_culls;
5115 }
5116 }
5117
5118 for (unsigned j = 0; j < length; j++) {
5119 LLVMValueRef value;
5120 args[2] = LLVMConstInt(ctx->i32,
5121 (slot * 4 + j + start) *
5122 ctx->gs_max_out_vertices * 16 * 4, false);
5123
5124 value = ac_emit_llvm_intrinsic(&ctx->ac,
5125 "llvm.SI.buffer.load.dword.i32.i32",
5126 ctx->i32, args, 9,
5127 AC_FUNC_ATTR_READONLY);
5128
5129 LLVMBuildStore(ctx->builder,
5130 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5131 }
5132 idx += slot_inc;
5133 }
5134 handle_vs_outputs_post(ctx);
5135 }
5136
5137 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5138 struct nir_shader *geom_shader,
5139 struct ac_shader_binary *binary,
5140 struct ac_shader_config *config,
5141 struct ac_shader_variant_info *shader_info,
5142 const struct ac_nir_compiler_options *options,
5143 bool dump_shader)
5144 {
5145 struct nir_to_llvm_context ctx = {0};
5146 ctx.context = LLVMContextCreate();
5147 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5148 ctx.options = options;
5149 ctx.shader_info = shader_info;
5150
5151 ac_llvm_context_init(&ctx.ac, ctx.context);
5152 ctx.ac.module = ctx.module;
5153
5154 ctx.is_gs_copy_shader = true;
5155 LLVMSetTarget(ctx.module, "amdgcn--");
5156 setup_types(&ctx);
5157
5158 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5159 ctx.ac.builder = ctx.builder;
5160 ctx.stage = MESA_SHADER_VERTEX;
5161
5162 create_function(&ctx);
5163
5164 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5165 ac_setup_rings(&ctx);
5166
5167 nir_foreach_variable(variable, &geom_shader->outputs)
5168 handle_shader_output_decl(&ctx, variable);
5169
5170 ac_gs_copy_shader_emit(&ctx);
5171
5172 LLVMBuildRetVoid(ctx.builder);
5173
5174 ac_llvm_finalize_module(&ctx);
5175
5176 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5177 MESA_SHADER_VERTEX,
5178 dump_shader, options->supports_spill);
5179 }