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ac/nir: pass ac_nir_context to SSBO intrinsic handlers
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct nir_to_llvm_context;
51
52 struct ac_nir_context {
53 struct ac_llvm_context ac;
54 struct ac_shader_abi *abi;
55
56 gl_shader_stage stage;
57
58 struct hash_table *defs;
59 struct hash_table *phis;
60 struct hash_table *vars;
61
62 LLVMValueRef main_function;
63 LLVMBasicBlockRef continue_block;
64 LLVMBasicBlockRef break_block;
65
66 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
67
68 int num_locals;
69 LLVMValueRef *locals;
70
71 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
72 };
73
74 struct nir_to_llvm_context {
75 struct ac_llvm_context ac;
76 const struct ac_nir_compiler_options *options;
77 struct ac_shader_variant_info *shader_info;
78 struct ac_shader_abi abi;
79 struct ac_nir_context *nir;
80
81 unsigned max_workgroup_size;
82 LLVMContextRef context;
83 LLVMModuleRef module;
84 LLVMBuilderRef builder;
85 LLVMValueRef main_function;
86
87 struct hash_table *defs;
88 struct hash_table *phis;
89
90 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
91 LLVMValueRef ring_offsets;
92 LLVMValueRef push_constants;
93 LLVMValueRef num_work_groups;
94 LLVMValueRef workgroup_ids;
95 LLVMValueRef local_invocation_ids;
96 LLVMValueRef tg_size;
97
98 LLVMValueRef vertex_buffers;
99 LLVMValueRef rel_auto_id;
100 LLVMValueRef vs_prim_id;
101 LLVMValueRef ls_out_layout;
102 LLVMValueRef es2gs_offset;
103
104 LLVMValueRef tcs_offchip_layout;
105 LLVMValueRef tcs_out_offsets;
106 LLVMValueRef tcs_out_layout;
107 LLVMValueRef tcs_in_layout;
108 LLVMValueRef oc_lds;
109 LLVMValueRef tess_factor_offset;
110 LLVMValueRef tcs_patch_id;
111 LLVMValueRef tcs_rel_ids;
112 LLVMValueRef tes_rel_patch_id;
113 LLVMValueRef tes_patch_id;
114 LLVMValueRef tes_u;
115 LLVMValueRef tes_v;
116
117 LLVMValueRef gsvs_ring_stride;
118 LLVMValueRef gsvs_num_entries;
119 LLVMValueRef gs2vs_offset;
120 LLVMValueRef gs_wave_id;
121 LLVMValueRef gs_vtx_offset[6];
122 LLVMValueRef gs_prim_id, gs_invocation_id;
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133 LLVMValueRef front_face;
134 LLVMValueRef ancillary;
135 LLVMValueRef sample_coverage;
136 LLVMValueRef frag_pos[4];
137
138 LLVMTypeRef i1;
139 LLVMTypeRef i8;
140 LLVMTypeRef i16;
141 LLVMTypeRef i32;
142 LLVMTypeRef i64;
143 LLVMTypeRef v2i32;
144 LLVMTypeRef v3i32;
145 LLVMTypeRef v4i32;
146 LLVMTypeRef v8i32;
147 LLVMTypeRef f64;
148 LLVMTypeRef f32;
149 LLVMTypeRef f16;
150 LLVMTypeRef v2f32;
151 LLVMTypeRef v4f32;
152 LLVMTypeRef voidt;
153
154 LLVMValueRef i1true;
155 LLVMValueRef i1false;
156 LLVMValueRef i32zero;
157 LLVMValueRef i32one;
158 LLVMValueRef f32zero;
159 LLVMValueRef f32one;
160 LLVMValueRef v4f32empty;
161
162 unsigned uniform_md_kind;
163 LLVMValueRef empty_md;
164 gl_shader_stage stage;
165
166 LLVMValueRef lds;
167 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
168
169 uint64_t input_mask;
170 uint64_t output_mask;
171 uint8_t num_output_clips;
172 uint8_t num_output_culls;
173
174 bool has_ds_bpermute;
175
176 bool is_gs_copy_shader;
177 LLVMValueRef gs_next_vertex;
178 unsigned gs_max_out_vertices;
179
180 unsigned tes_primitive_mode;
181 uint64_t tess_outputs_written;
182 uint64_t tess_patch_outputs_written;
183 };
184
185 static inline struct nir_to_llvm_context *
186 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
187 {
188 struct nir_to_llvm_context *ctx = NULL;
189 return container_of(abi, ctx, abi);
190 }
191
192 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
193 const nir_deref_var *deref,
194 enum ac_descriptor_type desc_type,
195 bool image, bool write);
196
197 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
198 {
199 return (index * 4) + chan;
200 }
201
202 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
203 {
204 /* handle patch indices separate */
205 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
206 return 0;
207 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
208 return 1;
209 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
210 return 2 + (slot - VARYING_SLOT_PATCH0);
211
212 if (slot == VARYING_SLOT_POS)
213 return 0;
214 if (slot == VARYING_SLOT_PSIZ)
215 return 1;
216 if (slot == VARYING_SLOT_CLIP_DIST0)
217 return 2;
218 /* 3 is reserved for clip dist as well */
219 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
220 return 4 + (slot - VARYING_SLOT_VAR0);
221 unreachable("illegal slot in get unique index\n");
222 }
223
224 static unsigned llvm_get_type_size(LLVMTypeRef type)
225 {
226 LLVMTypeKind kind = LLVMGetTypeKind(type);
227
228 switch (kind) {
229 case LLVMIntegerTypeKind:
230 return LLVMGetIntTypeWidth(type) / 8;
231 case LLVMFloatTypeKind:
232 return 4;
233 case LLVMPointerTypeKind:
234 return 8;
235 case LLVMVectorTypeKind:
236 return LLVMGetVectorSize(type) *
237 llvm_get_type_size(LLVMGetElementType(type));
238 default:
239 assert(0);
240 return 0;
241 }
242 }
243
244 static void set_llvm_calling_convention(LLVMValueRef func,
245 gl_shader_stage stage)
246 {
247 enum radeon_llvm_calling_convention calling_conv;
248
249 switch (stage) {
250 case MESA_SHADER_VERTEX:
251 case MESA_SHADER_TESS_CTRL:
252 case MESA_SHADER_TESS_EVAL:
253 calling_conv = RADEON_LLVM_AMDGPU_VS;
254 break;
255 case MESA_SHADER_GEOMETRY:
256 calling_conv = RADEON_LLVM_AMDGPU_GS;
257 break;
258 case MESA_SHADER_FRAGMENT:
259 calling_conv = RADEON_LLVM_AMDGPU_PS;
260 break;
261 case MESA_SHADER_COMPUTE:
262 calling_conv = RADEON_LLVM_AMDGPU_CS;
263 break;
264 default:
265 unreachable("Unhandle shader type");
266 }
267
268 LLVMSetFunctionCallConv(func, calling_conv);
269 }
270
271 #define MAX_ARGS 23
272 struct arg_info {
273 LLVMTypeRef types[MAX_ARGS];
274 LLVMValueRef *assign[MAX_ARGS];
275 unsigned array_params_mask;
276 uint8_t count;
277 uint8_t user_sgpr_count;
278 uint8_t sgpr_count;
279 uint8_t num_user_sgprs_used;
280 uint8_t num_sgprs_used;
281 uint8_t num_vgprs_used;
282 };
283
284 static inline void
285 add_argument(struct arg_info *info,
286 LLVMTypeRef type, LLVMValueRef *param_ptr)
287 {
288 assert(info->count < MAX_ARGS);
289 info->assign[info->count] = param_ptr;
290 info->types[info->count] = type;
291 info->count++;
292 }
293
294 static inline void
295 add_sgpr_argument(struct arg_info *info,
296 LLVMTypeRef type, LLVMValueRef *param_ptr)
297 {
298 add_argument(info, type, param_ptr);
299 info->num_sgprs_used += llvm_get_type_size(type) / 4;
300 info->sgpr_count++;
301 }
302
303 static inline void
304 add_user_sgpr_argument(struct arg_info *info,
305 LLVMTypeRef type,
306 LLVMValueRef *param_ptr)
307 {
308 add_sgpr_argument(info, type, param_ptr);
309 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
310 info->user_sgpr_count++;
311 }
312
313 static inline void
314 add_vgpr_argument(struct arg_info *info,
315 LLVMTypeRef type,
316 LLVMValueRef *param_ptr)
317 {
318 add_argument(info, type, param_ptr);
319 info->num_vgprs_used += llvm_get_type_size(type) / 4;
320 }
321
322 static inline void
323 add_user_sgpr_array_argument(struct arg_info *info,
324 LLVMTypeRef type,
325 LLVMValueRef *param_ptr)
326 {
327 info->array_params_mask |= (1 << info->count);
328 add_user_sgpr_argument(info, type, param_ptr);
329 }
330
331 static void assign_arguments(LLVMValueRef main_function,
332 struct arg_info *info)
333 {
334 unsigned i;
335 for (i = 0; i < info->count; i++) {
336 if (info->assign[i])
337 *info->assign[i] = LLVMGetParam(main_function, i);
338 }
339 }
340
341 static LLVMValueRef
342 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
343 LLVMBuilderRef builder, LLVMTypeRef *return_types,
344 unsigned num_return_elems,
345 struct arg_info *args,
346 unsigned max_workgroup_size,
347 bool unsafe_math)
348 {
349 LLVMTypeRef main_function_type, ret_type;
350 LLVMBasicBlockRef main_function_body;
351
352 if (num_return_elems)
353 ret_type = LLVMStructTypeInContext(ctx, return_types,
354 num_return_elems, true);
355 else
356 ret_type = LLVMVoidTypeInContext(ctx);
357
358 /* Setup the function */
359 main_function_type =
360 LLVMFunctionType(ret_type, args->types, args->count, 0);
361 LLVMValueRef main_function =
362 LLVMAddFunction(module, "main", main_function_type);
363 main_function_body =
364 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
365 LLVMPositionBuilderAtEnd(builder, main_function_body);
366
367 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
368 for (unsigned i = 0; i < args->sgpr_count; ++i) {
369 if (args->array_params_mask & (1 << i)) {
370 LLVMValueRef P = LLVMGetParam(main_function, i);
371 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
372 ac_add_attr_dereferenceable(P, UINT64_MAX);
373 }
374 else {
375 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
376 }
377 }
378
379 if (max_workgroup_size) {
380 ac_llvm_add_target_dep_function_attr(main_function,
381 "amdgpu-max-work-group-size",
382 max_workgroup_size);
383 }
384 if (unsafe_math) {
385 /* These were copied from some LLVM test. */
386 LLVMAddTargetDependentFunctionAttr(main_function,
387 "less-precise-fpmad",
388 "true");
389 LLVMAddTargetDependentFunctionAttr(main_function,
390 "no-infs-fp-math",
391 "true");
392 LLVMAddTargetDependentFunctionAttr(main_function,
393 "no-nans-fp-math",
394 "true");
395 LLVMAddTargetDependentFunctionAttr(main_function,
396 "unsafe-fp-math",
397 "true");
398 }
399 return main_function;
400 }
401
402 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
403 {
404 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
405 CONST_ADDR_SPACE);
406 }
407
408 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
409 {
410 if (t == ctx->f16 || t == ctx->i16)
411 return ctx->i16;
412 else if (t == ctx->f32 || t == ctx->i32)
413 return ctx->i32;
414 else if (t == ctx->f64 || t == ctx->i64)
415 return ctx->i64;
416 else
417 unreachable("Unhandled integer size");
418 }
419
420 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
421 {
422 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
423 LLVMTypeRef elem_type = LLVMGetElementType(t);
424 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
425 LLVMGetVectorSize(t));
426 }
427 return to_integer_type_scalar(ctx, t);
428 }
429
430 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
431 {
432 LLVMTypeRef type = LLVMTypeOf(v);
433 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
434 }
435
436 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
437 {
438 if (t == ctx->i16 || t == ctx->f16)
439 return ctx->f16;
440 else if (t == ctx->i32 || t == ctx->f32)
441 return ctx->f32;
442 else if (t == ctx->i64 || t == ctx->f64)
443 return ctx->f64;
444 else
445 unreachable("Unhandled float size");
446 }
447
448 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
449 {
450 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
451 LLVMTypeRef elem_type = LLVMGetElementType(t);
452 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
453 LLVMGetVectorSize(t));
454 }
455 return to_float_type_scalar(ctx, t);
456 }
457
458 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
459 {
460 LLVMTypeRef type = LLVMTypeOf(v);
461 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
462 }
463
464 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
465 {
466 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
467 type = LLVMGetElementType(type);
468
469 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
470 return LLVMGetIntTypeWidth(type);
471
472 if (type == ctx->f16)
473 return 16;
474 if (type == ctx->f32)
475 return 32;
476 if (type == ctx->f64)
477 return 64;
478
479 unreachable("Unhandled type kind in get_elem_bits");
480 }
481
482 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
483 LLVMValueRef param, unsigned rshift,
484 unsigned bitwidth)
485 {
486 LLVMValueRef value = param;
487 if (rshift)
488 value = LLVMBuildLShr(ctx->builder, value,
489 LLVMConstInt(ctx->i32, rshift, false), "");
490
491 if (rshift + bitwidth < 32) {
492 unsigned mask = (1 << bitwidth) - 1;
493 value = LLVMBuildAnd(ctx->builder, value,
494 LLVMConstInt(ctx->i32, mask, false), "");
495 }
496 return value;
497 }
498
499 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
500 {
501 switch (ctx->stage) {
502 case MESA_SHADER_TESS_CTRL:
503 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
504 case MESA_SHADER_TESS_EVAL:
505 return ctx->tes_rel_patch_id;
506 break;
507 default:
508 unreachable("Illegal stage");
509 }
510 }
511
512 /* Tessellation shaders pass outputs to the next shader using LDS.
513 *
514 * LS outputs = TCS inputs
515 * TCS outputs = TES inputs
516 *
517 * The LDS layout is:
518 * - TCS inputs for patch 0
519 * - TCS inputs for patch 1
520 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
521 * - ...
522 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
523 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
524 * - TCS outputs for patch 1
525 * - Per-patch TCS outputs for patch 1
526 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
527 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
528 * - ...
529 *
530 * All three shaders VS(LS), TCS, TES share the same LDS space.
531 */
532 static LLVMValueRef
533 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
534 {
535 if (ctx->stage == MESA_SHADER_VERTEX)
536 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
537 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
538 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
539 else {
540 assert(0);
541 return NULL;
542 }
543 }
544
545 static LLVMValueRef
546 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
547 {
548 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
549 }
550
551 static LLVMValueRef
552 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
553 {
554 return LLVMBuildMul(ctx->builder,
555 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
556 LLVMConstInt(ctx->i32, 4, false), "");
557 }
558
559 static LLVMValueRef
560 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
561 {
562 return LLVMBuildMul(ctx->builder,
563 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
564 LLVMConstInt(ctx->i32, 4, false), "");
565 }
566
567 static LLVMValueRef
568 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
569 {
570 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
571 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
572
573 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
574 }
575
576 static LLVMValueRef
577 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
578 {
579 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
580 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
581 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
582
583 return LLVMBuildAdd(ctx->builder, patch0_offset,
584 LLVMBuildMul(ctx->builder, patch_stride,
585 rel_patch_id, ""),
586 "");
587 }
588
589 static LLVMValueRef
590 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
591 {
592 LLVMValueRef patch0_patch_data_offset =
593 get_tcs_out_patch0_patch_data_offset(ctx);
594 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
595 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
596
597 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
598 LLVMBuildMul(ctx->builder, patch_stride,
599 rel_patch_id, ""),
600 "");
601 }
602
603 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
604 {
605 ud_info->sgpr_idx = *sgpr_idx;
606 ud_info->num_sgprs = num_sgprs;
607 ud_info->indirect = false;
608 ud_info->indirect_offset = 0;
609 *sgpr_idx += num_sgprs;
610 }
611
612 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
613 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
614 {
615 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
616 }
617
618
619 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
620 uint32_t indirect_offset)
621 {
622 ud_info->sgpr_idx = sgpr_idx;
623 ud_info->num_sgprs = num_sgprs;
624 ud_info->indirect = true;
625 ud_info->indirect_offset = indirect_offset;
626 }
627
628 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
629 {
630 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
631 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
632 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
633 "tess_lds");
634 }
635
636 struct user_sgpr_info {
637 bool need_ring_offsets;
638 uint8_t sgpr_count;
639 bool indirect_all_descriptor_sets;
640 };
641
642 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
643 struct user_sgpr_info *user_sgpr_info)
644 {
645 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
646
647 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
648 if (ctx->stage == MESA_SHADER_GEOMETRY ||
649 ctx->stage == MESA_SHADER_VERTEX ||
650 ctx->stage == MESA_SHADER_TESS_CTRL ||
651 ctx->stage == MESA_SHADER_TESS_EVAL ||
652 ctx->is_gs_copy_shader)
653 user_sgpr_info->need_ring_offsets = true;
654
655 if (ctx->stage == MESA_SHADER_FRAGMENT &&
656 ctx->shader_info->info.ps.needs_sample_positions)
657 user_sgpr_info->need_ring_offsets = true;
658
659 /* 2 user sgprs will nearly always be allocated for scratch/rings */
660 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
661 user_sgpr_info->sgpr_count += 2;
662 }
663
664 switch (ctx->stage) {
665 case MESA_SHADER_COMPUTE:
666 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
667 break;
668 case MESA_SHADER_FRAGMENT:
669 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
670 break;
671 case MESA_SHADER_VERTEX:
672 if (!ctx->is_gs_copy_shader) {
673 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
674 if (ctx->shader_info->info.vs.needs_draw_id) {
675 user_sgpr_info->sgpr_count += 3;
676 } else {
677 user_sgpr_info->sgpr_count += 2;
678 }
679 }
680 if (ctx->options->key.vs.as_ls)
681 user_sgpr_info->sgpr_count++;
682 break;
683 case MESA_SHADER_TESS_CTRL:
684 user_sgpr_info->sgpr_count += 4;
685 break;
686 case MESA_SHADER_TESS_EVAL:
687 user_sgpr_info->sgpr_count += 1;
688 break;
689 case MESA_SHADER_GEOMETRY:
690 user_sgpr_info->sgpr_count += 2;
691 break;
692 default:
693 break;
694 }
695
696 if (ctx->shader_info->info.needs_push_constants)
697 user_sgpr_info->sgpr_count += 2;
698
699 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
700 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
701 user_sgpr_info->sgpr_count += 2;
702 user_sgpr_info->indirect_all_descriptor_sets = true;
703 } else {
704 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
705 }
706 }
707
708 static void create_function(struct nir_to_llvm_context *ctx)
709 {
710 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
711 uint8_t user_sgpr_idx;
712 struct user_sgpr_info user_sgpr_info;
713 struct arg_info args = {};
714 LLVMValueRef desc_sets;
715
716 allocate_user_sgprs(ctx, &user_sgpr_info);
717 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
718 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
719 }
720
721 /* 1 for each descriptor set */
722 if (!user_sgpr_info.indirect_all_descriptor_sets) {
723 for (unsigned i = 0; i < num_sets; ++i) {
724 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
725 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
726 }
727 }
728 } else
729 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
730
731 if (ctx->shader_info->info.needs_push_constants) {
732 /* 1 for push constants and dynamic descriptors */
733 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
734 }
735
736 switch (ctx->stage) {
737 case MESA_SHADER_COMPUTE:
738 if (ctx->shader_info->info.cs.grid_components_used)
739 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
740 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
741 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
742 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
743 break;
744 case MESA_SHADER_VERTEX:
745 if (!ctx->is_gs_copy_shader) {
746 if (ctx->shader_info->info.vs.has_vertex_buffers)
747 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
748 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
749 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
750 if (ctx->shader_info->info.vs.needs_draw_id)
751 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
752 }
753 if (ctx->options->key.vs.as_es)
754 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
755 else if (ctx->options->key.vs.as_ls)
756 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
757 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
758 if (!ctx->is_gs_copy_shader) {
759 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
760 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
761 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
762 }
763 break;
764 case MESA_SHADER_TESS_CTRL:
765 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
766 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
767 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
768 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
769 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
770 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
771 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
772 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
773 break;
774 case MESA_SHADER_TESS_EVAL:
775 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
776 if (ctx->options->key.tes.as_es) {
777 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
778 add_sgpr_argument(&args, ctx->i32, NULL); //
779 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
780 } else {
781 add_sgpr_argument(&args, ctx->i32, NULL); //
782 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
783 }
784 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
785 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
786 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
787 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
788 break;
789 case MESA_SHADER_GEOMETRY:
790 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
791 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
792 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
793 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
796 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
797 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
798 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
799 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
800 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
801 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
802 break;
803 case MESA_SHADER_FRAGMENT:
804 if (ctx->shader_info->info.ps.needs_sample_positions)
805 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
806 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
807 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
808 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
809 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
810 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
811 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
812 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
813 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
814 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
815 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos x float */
816 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos y float */
817 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos z float */
818 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos w float */
819 add_vgpr_argument(&args, ctx->i32, &ctx->front_face); /* front face */
820 add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /* ancillary */
821 add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /* sample coverage */
822 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
823 break;
824 default:
825 unreachable("Shader stage not implemented");
826 }
827
828 ctx->main_function = create_llvm_function(
829 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
830 ctx->max_workgroup_size,
831 ctx->options->unsafe_math);
832 set_llvm_calling_convention(ctx->main_function, ctx->stage);
833
834
835 ctx->shader_info->num_input_vgprs = 0;
836 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
837 ctx->options->supports_spill ? 2 : 0;
838
839 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
840 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
841
842 if (ctx->stage != MESA_SHADER_FRAGMENT)
843 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
844
845 assign_arguments(ctx->main_function, &args);
846
847 user_sgpr_idx = 0;
848
849 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
850 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
851 if (ctx->options->supports_spill) {
852 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
853 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
854 NULL, 0, AC_FUNC_ATTR_READNONE);
855 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
856 const_array(ctx->v4i32, 16), "");
857 }
858 }
859
860 if (!user_sgpr_info.indirect_all_descriptor_sets) {
861 for (unsigned i = 0; i < num_sets; ++i) {
862 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
863 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
864 } else
865 ctx->descriptor_sets[i] = NULL;
866 }
867 } else {
868 uint32_t desc_sgpr_idx = user_sgpr_idx;
869 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
870
871 for (unsigned i = 0; i < num_sets; ++i) {
872 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
873 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
874 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
875
876 } else
877 ctx->descriptor_sets[i] = NULL;
878 }
879 ctx->shader_info->need_indirect_descriptor_sets = true;
880 }
881
882 if (ctx->shader_info->info.needs_push_constants) {
883 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
884 }
885
886 switch (ctx->stage) {
887 case MESA_SHADER_COMPUTE:
888 if (ctx->shader_info->info.cs.grid_components_used) {
889 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
890 }
891 break;
892 case MESA_SHADER_VERTEX:
893 if (!ctx->is_gs_copy_shader) {
894 if (ctx->shader_info->info.vs.has_vertex_buffers) {
895 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
896 }
897 unsigned vs_num = 2;
898 if (ctx->shader_info->info.vs.needs_draw_id)
899 vs_num++;
900
901 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
902 }
903 if (ctx->options->key.vs.as_ls) {
904 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
905 }
906 if (ctx->options->key.vs.as_ls)
907 declare_tess_lds(ctx);
908 break;
909 case MESA_SHADER_TESS_CTRL:
910 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
911 declare_tess_lds(ctx);
912 break;
913 case MESA_SHADER_TESS_EVAL:
914 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
915 break;
916 case MESA_SHADER_GEOMETRY:
917 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
918 break;
919 case MESA_SHADER_FRAGMENT:
920 if (ctx->shader_info->info.ps.needs_sample_positions) {
921 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
922 }
923 break;
924 default:
925 unreachable("Shader stage not implemented");
926 }
927 }
928
929 static void setup_types(struct nir_to_llvm_context *ctx)
930 {
931 LLVMValueRef args[4];
932
933 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
934 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
935 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
936 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
937 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
938 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
939 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
940 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
941 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
942 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
943 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
944 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
945 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
946 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
947 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
948
949 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
950 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
951 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
952 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
953 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
954 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
955
956 args[0] = ctx->f32zero;
957 args[1] = ctx->f32zero;
958 args[2] = ctx->f32zero;
959 args[3] = ctx->f32one;
960 ctx->v4f32empty = LLVMConstVector(args, 4);
961
962 ctx->uniform_md_kind =
963 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
964 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
965
966 args[0] = LLVMConstReal(ctx->f32, 2.5);
967 }
968
969 static int get_llvm_num_components(LLVMValueRef value)
970 {
971 LLVMTypeRef type = LLVMTypeOf(value);
972 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
973 ? LLVMGetVectorSize(type)
974 : 1;
975 return num_components;
976 }
977
978 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
979 LLVMValueRef value,
980 int index)
981 {
982 int count = get_llvm_num_components(value);
983
984 assert(index < count);
985 if (count == 1)
986 return value;
987
988 return LLVMBuildExtractElement(ac->builder, value,
989 LLVMConstInt(ac->i32, index, false), "");
990 }
991
992 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
993 LLVMValueRef value, unsigned count)
994 {
995 unsigned num_components = get_llvm_num_components(value);
996 if (count == num_components)
997 return value;
998
999 LLVMValueRef masks[] = {
1000 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1001 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1002
1003 if (count == 1)
1004 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1005 "");
1006
1007 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1008 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1009 }
1010
1011 static void
1012 build_store_values_extended(struct ac_llvm_context *ac,
1013 LLVMValueRef *values,
1014 unsigned value_count,
1015 unsigned value_stride,
1016 LLVMValueRef vec)
1017 {
1018 LLVMBuilderRef builder = ac->builder;
1019 unsigned i;
1020
1021 if (value_count == 1) {
1022 LLVMBuildStore(builder, vec, values[0]);
1023 return;
1024 }
1025
1026 for (i = 0; i < value_count; i++) {
1027 LLVMValueRef ptr = values[i * value_stride];
1028 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1029 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1030 LLVMBuildStore(builder, value, ptr);
1031 }
1032 }
1033
1034 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1035 const nir_ssa_def *def)
1036 {
1037 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1038 if (def->num_components > 1) {
1039 type = LLVMVectorType(type, def->num_components);
1040 }
1041 return type;
1042 }
1043
1044 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1045 {
1046 assert(src.is_ssa);
1047 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1048 return (LLVMValueRef)entry->data;
1049 }
1050
1051
1052 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1053 const struct nir_block *b)
1054 {
1055 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1056 return (LLVMBasicBlockRef)entry->data;
1057 }
1058
1059 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1060 nir_alu_src src,
1061 unsigned num_components)
1062 {
1063 LLVMValueRef value = get_src(ctx, src.src);
1064 bool need_swizzle = false;
1065
1066 assert(value);
1067 LLVMTypeRef type = LLVMTypeOf(value);
1068 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1069 ? LLVMGetVectorSize(type)
1070 : 1;
1071
1072 for (unsigned i = 0; i < num_components; ++i) {
1073 assert(src.swizzle[i] < src_components);
1074 if (src.swizzle[i] != i)
1075 need_swizzle = true;
1076 }
1077
1078 if (need_swizzle || num_components != src_components) {
1079 LLVMValueRef masks[] = {
1080 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1081 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1082 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1083 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1084
1085 if (src_components > 1 && num_components == 1) {
1086 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1087 masks[0], "");
1088 } else if (src_components == 1 && num_components > 1) {
1089 LLVMValueRef values[] = {value, value, value, value};
1090 value = ac_build_gather_values(&ctx->ac, values, num_components);
1091 } else {
1092 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1093 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1094 swizzle, "");
1095 }
1096 }
1097 assert(!src.negate);
1098 assert(!src.abs);
1099 return value;
1100 }
1101
1102 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1103 LLVMIntPredicate pred, LLVMValueRef src0,
1104 LLVMValueRef src1)
1105 {
1106 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1107 return LLVMBuildSelect(ctx->builder, result,
1108 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1109 LLVMConstInt(ctx->i32, 0, false), "");
1110 }
1111
1112 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1113 LLVMRealPredicate pred, LLVMValueRef src0,
1114 LLVMValueRef src1)
1115 {
1116 LLVMValueRef result;
1117 src0 = to_float(ctx, src0);
1118 src1 = to_float(ctx, src1);
1119 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1120 return LLVMBuildSelect(ctx->builder, result,
1121 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1122 LLVMConstInt(ctx->i32, 0, false), "");
1123 }
1124
1125 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1126 const char *intrin,
1127 LLVMTypeRef result_type,
1128 LLVMValueRef src0)
1129 {
1130 char name[64];
1131 LLVMValueRef params[] = {
1132 to_float(ctx, src0),
1133 };
1134
1135 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1136 get_elem_bits(ctx, result_type));
1137 assert(length < sizeof(name));
1138 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1139 }
1140
1141 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1142 const char *intrin,
1143 LLVMTypeRef result_type,
1144 LLVMValueRef src0, LLVMValueRef src1)
1145 {
1146 char name[64];
1147 LLVMValueRef params[] = {
1148 to_float(ctx, src0),
1149 to_float(ctx, src1),
1150 };
1151
1152 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1153 get_elem_bits(ctx, result_type));
1154 assert(length < sizeof(name));
1155 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1156 }
1157
1158 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1159 const char *intrin,
1160 LLVMTypeRef result_type,
1161 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1162 {
1163 char name[64];
1164 LLVMValueRef params[] = {
1165 to_float(ctx, src0),
1166 to_float(ctx, src1),
1167 to_float(ctx, src2),
1168 };
1169
1170 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1171 get_elem_bits(ctx, result_type));
1172 assert(length < sizeof(name));
1173 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1174 }
1175
1176 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1177 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1178 {
1179 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1180 ctx->i32_0, "");
1181 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1182 }
1183
1184 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1185 LLVMValueRef src0)
1186 {
1187 LLVMValueRef params[2] = {
1188 src0,
1189
1190 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1191 * add special code to check for x=0. The reason is that
1192 * the LLVM behavior for x=0 is different from what we
1193 * need here.
1194 *
1195 * The hardware already implements the correct behavior.
1196 */
1197 LLVMConstInt(ctx->i1, 1, false),
1198 };
1199 return ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1200 }
1201
1202 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1203 LLVMValueRef src0)
1204 {
1205 return ac_build_imsb(ctx, src0, ctx->i32);
1206 }
1207
1208 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1209 LLVMValueRef src0)
1210 {
1211 return ac_build_umsb(ctx, src0, ctx->i32);
1212 }
1213
1214 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1215 LLVMIntPredicate pred,
1216 LLVMValueRef src0, LLVMValueRef src1)
1217 {
1218 return LLVMBuildSelect(ctx->builder,
1219 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1220 src0,
1221 src1, "");
1222
1223 }
1224 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1225 LLVMValueRef src0)
1226 {
1227 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1228 LLVMBuildNeg(ctx->builder, src0, ""));
1229 }
1230
1231 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1232 LLVMValueRef src0)
1233 {
1234 LLVMValueRef cmp, val;
1235
1236 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1237 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1238 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1239 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1240 return val;
1241 }
1242
1243 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1244 LLVMValueRef src0)
1245 {
1246 LLVMValueRef cmp, val;
1247
1248 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1249 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1250 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1251 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1252 return val;
1253 }
1254
1255 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1256 LLVMValueRef src0)
1257 {
1258 const char *intr = "llvm.floor.f32";
1259 LLVMValueRef fsrc0 = to_float(ctx, src0);
1260 LLVMValueRef params[] = {
1261 fsrc0,
1262 };
1263 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1264 ctx->f32, params, 1,
1265 AC_FUNC_ATTR_READNONE);
1266 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1267 }
1268
1269 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1270 const char *intrin,
1271 LLVMValueRef src0, LLVMValueRef src1)
1272 {
1273 LLVMTypeRef ret_type;
1274 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1275 LLVMValueRef res;
1276 LLVMValueRef params[] = { src0, src1 };
1277 ret_type = LLVMStructTypeInContext(ctx->context, types,
1278 2, true);
1279
1280 res = ac_build_intrinsic(ctx, intrin, ret_type,
1281 params, 2, AC_FUNC_ATTR_READNONE);
1282
1283 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1284 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1285 return res;
1286 }
1287
1288 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1289 LLVMValueRef src0)
1290 {
1291 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1292 }
1293
1294 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1295 LLVMValueRef src0)
1296 {
1297 src0 = to_float(ctx, src0);
1298 return LLVMBuildSExt(ctx->builder,
1299 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1300 ctx->i32, "");
1301 }
1302
1303 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1304 LLVMValueRef src0)
1305 {
1306 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1307 }
1308
1309 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1310 LLVMValueRef src0)
1311 {
1312 return LLVMBuildSExt(ctx->builder,
1313 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1314 ctx->i32, "");
1315 }
1316
1317 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1318 LLVMValueRef src0)
1319 {
1320 LLVMValueRef result;
1321 LLVMValueRef cond;
1322
1323 src0 = to_float(&ctx->ac, src0);
1324 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1325
1326 /* TODO SI/CIK options here */
1327 if (ctx->options->chip_class >= VI) {
1328 LLVMValueRef args[2];
1329 /* Check if the result is a denormal - and flush to 0 if so. */
1330 args[0] = result;
1331 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1332 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1333 }
1334
1335 /* need to convert back up to f32 */
1336 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1337
1338 if (ctx->options->chip_class >= VI)
1339 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1340
1341 return result;
1342 }
1343
1344 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1345 LLVMValueRef src0, LLVMValueRef src1)
1346 {
1347 LLVMValueRef dst64, result;
1348 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1349 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1350
1351 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1352 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1353 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1354 return result;
1355 }
1356
1357 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1358 LLVMValueRef src0, LLVMValueRef src1)
1359 {
1360 LLVMValueRef dst64, result;
1361 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1362 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1363
1364 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1365 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1366 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1367 return result;
1368 }
1369
1370 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1371 bool is_signed,
1372 const LLVMValueRef srcs[3])
1373 {
1374 LLVMValueRef result;
1375 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1376
1377 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1378 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1379 return result;
1380 }
1381
1382 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1383 LLVMValueRef src0, LLVMValueRef src1,
1384 LLVMValueRef src2, LLVMValueRef src3)
1385 {
1386 LLVMValueRef bfi_args[3], result;
1387
1388 bfi_args[0] = LLVMBuildShl(ctx->builder,
1389 LLVMBuildSub(ctx->builder,
1390 LLVMBuildShl(ctx->builder,
1391 ctx->i32_1,
1392 src3, ""),
1393 ctx->i32_1, ""),
1394 src2, "");
1395 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1396 bfi_args[2] = src0;
1397
1398 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1399
1400 /* Calculate:
1401 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1402 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1403 */
1404 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1405 LLVMBuildAnd(ctx->builder, bfi_args[0],
1406 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1407
1408 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1409 return result;
1410 }
1411
1412 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1413 LLVMValueRef src0)
1414 {
1415 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1416 int i;
1417 LLVMValueRef comp[2];
1418
1419 src0 = to_float(ctx, src0);
1420 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1421 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1422 for (i = 0; i < 2; i++) {
1423 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1424 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1425 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1426 }
1427
1428 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1429 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1430
1431 return comp[0];
1432 }
1433
1434 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0)
1436 {
1437 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1438 LLVMValueRef temps[2], result, val;
1439 int i;
1440
1441 for (i = 0; i < 2; i++) {
1442 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1443 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1444 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1445 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1446 }
1447
1448 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1449 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1450 ctx->i32_0, "");
1451 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1452 ctx->i32_1, "");
1453 return result;
1454 }
1455
1456 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1457 nir_op op,
1458 LLVMValueRef src0)
1459 {
1460 unsigned mask;
1461 int idx;
1462 LLVMValueRef result;
1463
1464 if (!ctx->lds && !ctx->has_ds_bpermute)
1465 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1466 LLVMArrayType(ctx->i32, 64),
1467 "ddxy_lds", LOCAL_ADDR_SPACE);
1468
1469 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1470 mask = AC_TID_MASK_LEFT;
1471 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1472 mask = AC_TID_MASK_TOP;
1473 else
1474 mask = AC_TID_MASK_TOP_LEFT;
1475
1476 /* for DDX we want to next X pixel, DDY next Y pixel. */
1477 if (op == nir_op_fddx_fine ||
1478 op == nir_op_fddx_coarse ||
1479 op == nir_op_fddx)
1480 idx = 1;
1481 else
1482 idx = 2;
1483
1484 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1485 mask, idx, ctx->lds,
1486 src0);
1487 return result;
1488 }
1489
1490 /*
1491 * this takes an I,J coordinate pair,
1492 * and works out the X and Y derivatives.
1493 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1494 */
1495 static LLVMValueRef emit_ddxy_interp(
1496 struct nir_to_llvm_context *ctx,
1497 LLVMValueRef interp_ij)
1498 {
1499 LLVMValueRef result[4], a;
1500 unsigned i;
1501
1502 for (i = 0; i < 2; i++) {
1503 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1504 LLVMConstInt(ctx->i32, i, false), "");
1505 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1506 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1507 }
1508 return ac_build_gather_values(&ctx->ac, result, 4);
1509 }
1510
1511 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1512 {
1513 LLVMValueRef src[4], result = NULL;
1514 unsigned num_components = instr->dest.dest.ssa.num_components;
1515 unsigned src_components;
1516 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1517
1518 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1519 switch (instr->op) {
1520 case nir_op_vec2:
1521 case nir_op_vec3:
1522 case nir_op_vec4:
1523 src_components = 1;
1524 break;
1525 case nir_op_pack_half_2x16:
1526 src_components = 2;
1527 break;
1528 case nir_op_unpack_half_2x16:
1529 src_components = 1;
1530 break;
1531 default:
1532 src_components = num_components;
1533 break;
1534 }
1535 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1536 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1537
1538 switch (instr->op) {
1539 case nir_op_fmov:
1540 case nir_op_imov:
1541 result = src[0];
1542 break;
1543 case nir_op_fneg:
1544 src[0] = to_float(&ctx->ac, src[0]);
1545 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1546 break;
1547 case nir_op_ineg:
1548 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1549 break;
1550 case nir_op_inot:
1551 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1552 break;
1553 case nir_op_iadd:
1554 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1555 break;
1556 case nir_op_fadd:
1557 src[0] = to_float(&ctx->ac, src[0]);
1558 src[1] = to_float(&ctx->ac, src[1]);
1559 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1560 break;
1561 case nir_op_fsub:
1562 src[0] = to_float(&ctx->ac, src[0]);
1563 src[1] = to_float(&ctx->ac, src[1]);
1564 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1565 break;
1566 case nir_op_isub:
1567 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1568 break;
1569 case nir_op_imul:
1570 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1571 break;
1572 case nir_op_imod:
1573 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1574 break;
1575 case nir_op_umod:
1576 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1577 break;
1578 case nir_op_fmod:
1579 src[0] = to_float(&ctx->ac, src[0]);
1580 src[1] = to_float(&ctx->ac, src[1]);
1581 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1582 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1583 to_float_type(&ctx->ac, def_type), result);
1584 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1585 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1586 break;
1587 case nir_op_frem:
1588 src[0] = to_float(&ctx->ac, src[0]);
1589 src[1] = to_float(&ctx->ac, src[1]);
1590 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1591 break;
1592 case nir_op_irem:
1593 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1594 break;
1595 case nir_op_idiv:
1596 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1597 break;
1598 case nir_op_udiv:
1599 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1600 break;
1601 case nir_op_fmul:
1602 src[0] = to_float(&ctx->ac, src[0]);
1603 src[1] = to_float(&ctx->ac, src[1]);
1604 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1605 break;
1606 case nir_op_fdiv:
1607 src[0] = to_float(&ctx->ac, src[0]);
1608 src[1] = to_float(&ctx->ac, src[1]);
1609 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1610 break;
1611 case nir_op_frcp:
1612 src[0] = to_float(&ctx->ac, src[0]);
1613 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1614 break;
1615 case nir_op_iand:
1616 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1617 break;
1618 case nir_op_ior:
1619 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1620 break;
1621 case nir_op_ixor:
1622 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1623 break;
1624 case nir_op_ishl:
1625 result = LLVMBuildShl(ctx->ac.builder, src[0],
1626 LLVMBuildZExt(ctx->ac.builder, src[1],
1627 LLVMTypeOf(src[0]), ""),
1628 "");
1629 break;
1630 case nir_op_ishr:
1631 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1632 LLVMBuildZExt(ctx->ac.builder, src[1],
1633 LLVMTypeOf(src[0]), ""),
1634 "");
1635 break;
1636 case nir_op_ushr:
1637 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1638 LLVMBuildZExt(ctx->ac.builder, src[1],
1639 LLVMTypeOf(src[0]), ""),
1640 "");
1641 break;
1642 case nir_op_ilt:
1643 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1644 break;
1645 case nir_op_ine:
1646 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1647 break;
1648 case nir_op_ieq:
1649 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1650 break;
1651 case nir_op_ige:
1652 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1653 break;
1654 case nir_op_ult:
1655 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1656 break;
1657 case nir_op_uge:
1658 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1659 break;
1660 case nir_op_feq:
1661 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1662 break;
1663 case nir_op_fne:
1664 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1665 break;
1666 case nir_op_flt:
1667 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1668 break;
1669 case nir_op_fge:
1670 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1671 break;
1672 case nir_op_fabs:
1673 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1674 to_float_type(&ctx->ac, def_type), src[0]);
1675 break;
1676 case nir_op_iabs:
1677 result = emit_iabs(&ctx->ac, src[0]);
1678 break;
1679 case nir_op_imax:
1680 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1681 break;
1682 case nir_op_imin:
1683 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1684 break;
1685 case nir_op_umax:
1686 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1687 break;
1688 case nir_op_umin:
1689 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1690 break;
1691 case nir_op_isign:
1692 result = emit_isign(&ctx->ac, src[0]);
1693 break;
1694 case nir_op_fsign:
1695 src[0] = to_float(&ctx->ac, src[0]);
1696 result = emit_fsign(&ctx->ac, src[0]);
1697 break;
1698 case nir_op_ffloor:
1699 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1700 to_float_type(&ctx->ac, def_type), src[0]);
1701 break;
1702 case nir_op_ftrunc:
1703 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1704 to_float_type(&ctx->ac, def_type), src[0]);
1705 break;
1706 case nir_op_fceil:
1707 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1708 to_float_type(&ctx->ac, def_type), src[0]);
1709 break;
1710 case nir_op_fround_even:
1711 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1712 to_float_type(&ctx->ac, def_type),src[0]);
1713 break;
1714 case nir_op_ffract:
1715 result = emit_ffract(&ctx->ac, src[0]);
1716 break;
1717 case nir_op_fsin:
1718 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1719 to_float_type(&ctx->ac, def_type), src[0]);
1720 break;
1721 case nir_op_fcos:
1722 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1723 to_float_type(&ctx->ac, def_type), src[0]);
1724 break;
1725 case nir_op_fsqrt:
1726 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1727 to_float_type(&ctx->ac, def_type), src[0]);
1728 break;
1729 case nir_op_fexp2:
1730 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1731 to_float_type(&ctx->ac, def_type), src[0]);
1732 break;
1733 case nir_op_flog2:
1734 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1735 to_float_type(&ctx->ac, def_type), src[0]);
1736 break;
1737 case nir_op_frsq:
1738 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1739 to_float_type(&ctx->ac, def_type), src[0]);
1740 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1741 break;
1742 case nir_op_fpow:
1743 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1744 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1745 break;
1746 case nir_op_fmax:
1747 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1748 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1749 if (instr->dest.dest.ssa.bit_size == 32)
1750 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1751 to_float_type(&ctx->ac, def_type),
1752 result);
1753 break;
1754 case nir_op_fmin:
1755 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1756 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1757 if (instr->dest.dest.ssa.bit_size == 32)
1758 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1759 to_float_type(&ctx->ac, def_type),
1760 result);
1761 break;
1762 case nir_op_ffma:
1763 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1764 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1765 break;
1766 case nir_op_ibitfield_extract:
1767 result = emit_bitfield_extract(&ctx->ac, true, src);
1768 break;
1769 case nir_op_ubitfield_extract:
1770 result = emit_bitfield_extract(&ctx->ac, false, src);
1771 break;
1772 case nir_op_bitfield_insert:
1773 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1774 break;
1775 case nir_op_bitfield_reverse:
1776 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1777 break;
1778 case nir_op_bit_count:
1779 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1780 break;
1781 case nir_op_vec2:
1782 case nir_op_vec3:
1783 case nir_op_vec4:
1784 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1785 src[i] = to_integer(&ctx->ac, src[i]);
1786 result = ac_build_gather_values(&ctx->ac, src, num_components);
1787 break;
1788 case nir_op_f2i32:
1789 case nir_op_f2i64:
1790 src[0] = to_float(&ctx->ac, src[0]);
1791 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1792 break;
1793 case nir_op_f2u32:
1794 case nir_op_f2u64:
1795 src[0] = to_float(&ctx->ac, src[0]);
1796 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1797 break;
1798 case nir_op_i2f32:
1799 case nir_op_i2f64:
1800 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1801 break;
1802 case nir_op_u2f32:
1803 case nir_op_u2f64:
1804 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1805 break;
1806 case nir_op_f2f64:
1807 result = LLVMBuildFPExt(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1808 break;
1809 case nir_op_f2f32:
1810 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1811 break;
1812 case nir_op_u2u32:
1813 case nir_op_u2u64:
1814 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1815 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1816 else
1817 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1818 break;
1819 case nir_op_i2i32:
1820 case nir_op_i2i64:
1821 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1822 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1823 else
1824 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1825 break;
1826 case nir_op_bcsel:
1827 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1828 break;
1829 case nir_op_find_lsb:
1830 result = emit_find_lsb(&ctx->ac, src[0]);
1831 break;
1832 case nir_op_ufind_msb:
1833 result = emit_ufind_msb(&ctx->ac, src[0]);
1834 break;
1835 case nir_op_ifind_msb:
1836 result = emit_ifind_msb(&ctx->ac, src[0]);
1837 break;
1838 case nir_op_uadd_carry:
1839 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1840 break;
1841 case nir_op_usub_borrow:
1842 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1843 break;
1844 case nir_op_b2f:
1845 result = emit_b2f(&ctx->ac, src[0]);
1846 break;
1847 case nir_op_f2b:
1848 result = emit_f2b(&ctx->ac, src[0]);
1849 break;
1850 case nir_op_b2i:
1851 result = emit_b2i(&ctx->ac, src[0]);
1852 break;
1853 case nir_op_i2b:
1854 result = emit_i2b(&ctx->ac, src[0]);
1855 break;
1856 case nir_op_fquantize2f16:
1857 result = emit_f2f16(ctx->nctx, src[0]);
1858 break;
1859 case nir_op_umul_high:
1860 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1861 break;
1862 case nir_op_imul_high:
1863 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1864 break;
1865 case nir_op_pack_half_2x16:
1866 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1867 break;
1868 case nir_op_unpack_half_2x16:
1869 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1870 break;
1871 case nir_op_fddx:
1872 case nir_op_fddy:
1873 case nir_op_fddx_fine:
1874 case nir_op_fddy_fine:
1875 case nir_op_fddx_coarse:
1876 case nir_op_fddy_coarse:
1877 result = emit_ddxy(ctx->nctx, instr->op, src[0]);
1878 break;
1879
1880 case nir_op_unpack_64_2x32_split_x: {
1881 assert(instr->src[0].src.ssa->num_components == 1);
1882 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1883 LLVMVectorType(ctx->ac.i32, 2),
1884 "");
1885 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1886 ctx->ac.i32_0, "");
1887 break;
1888 }
1889
1890 case nir_op_unpack_64_2x32_split_y: {
1891 assert(instr->src[0].src.ssa->num_components == 1);
1892 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1893 LLVMVectorType(ctx->ac.i32, 2),
1894 "");
1895 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1896 ctx->ac.i32_0, "");
1897 break;
1898 }
1899
1900 case nir_op_pack_64_2x32_split: {
1901 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1902 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1903 src[0], ctx->ac.i32_0, "");
1904 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1905 src[1], ctx->ac.i32_1, "");
1906 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1907 break;
1908 }
1909
1910 default:
1911 fprintf(stderr, "Unknown NIR alu instr: ");
1912 nir_print_instr(&instr->instr, stderr);
1913 fprintf(stderr, "\n");
1914 abort();
1915 }
1916
1917 if (result) {
1918 assert(instr->dest.dest.is_ssa);
1919 result = to_integer(&ctx->ac, result);
1920 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1921 result);
1922 }
1923 }
1924
1925 static void visit_load_const(struct ac_nir_context *ctx,
1926 const nir_load_const_instr *instr)
1927 {
1928 LLVMValueRef values[4], value = NULL;
1929 LLVMTypeRef element_type =
1930 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1931
1932 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1933 switch (instr->def.bit_size) {
1934 case 32:
1935 values[i] = LLVMConstInt(element_type,
1936 instr->value.u32[i], false);
1937 break;
1938 case 64:
1939 values[i] = LLVMConstInt(element_type,
1940 instr->value.u64[i], false);
1941 break;
1942 default:
1943 fprintf(stderr,
1944 "unsupported nir load_const bit_size: %d\n",
1945 instr->def.bit_size);
1946 abort();
1947 }
1948 }
1949 if (instr->def.num_components > 1) {
1950 value = LLVMConstVector(values, instr->def.num_components);
1951 } else
1952 value = values[0];
1953
1954 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1955 }
1956
1957 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1958 LLVMTypeRef type)
1959 {
1960 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1961 return LLVMBuildBitCast(ctx->builder, ptr,
1962 LLVMPointerType(type, addr_space), "");
1963 }
1964
1965 static LLVMValueRef
1966 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1967 {
1968 LLVMValueRef size =
1969 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1970 LLVMConstInt(ctx->ac.i32, 2, false), "");
1971
1972 /* VI only */
1973 if (ctx->abi->chip_class >= VI && in_elements) {
1974 /* On VI, the descriptor contains the size in bytes,
1975 * but TXQ must return the size in elements.
1976 * The stride is always non-zero for resources using TXQ.
1977 */
1978 LLVMValueRef stride =
1979 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1980 LLVMConstInt(ctx->ac.i32, 1, false), "");
1981 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1982 LLVMConstInt(ctx->ac.i32, 16, false), "");
1983 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1984 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1985
1986 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1987 }
1988 return size;
1989 }
1990
1991 /**
1992 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1993 * intrinsic names).
1994 */
1995 static void build_int_type_name(
1996 LLVMTypeRef type,
1997 char *buf, unsigned bufsize)
1998 {
1999 assert(bufsize >= 6);
2000
2001 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2002 snprintf(buf, bufsize, "v%ui32",
2003 LLVMGetVectorSize(type));
2004 else
2005 strcpy(buf, "i32");
2006 }
2007
2008 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2009 struct ac_image_args *args,
2010 const nir_tex_instr *instr)
2011 {
2012 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2013 LLVMValueRef coord = args->addr;
2014 LLVMValueRef half_texel[2];
2015 LLVMValueRef compare_cube_wa;
2016 LLVMValueRef result;
2017 int c;
2018 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2019
2020 //TODO Rect
2021 {
2022 struct ac_image_args txq_args = { 0 };
2023
2024 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2025 txq_args.opcode = ac_image_get_resinfo;
2026 txq_args.dmask = 0xf;
2027 txq_args.addr = ctx->i32_0;
2028 txq_args.resource = args->resource;
2029 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2030
2031 for (c = 0; c < 2; c++) {
2032 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2033 LLVMConstInt(ctx->i32, c, false), "");
2034 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2035 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2036 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2037 LLVMConstReal(ctx->f32, -0.5), "");
2038 }
2039 }
2040
2041 LLVMValueRef orig_coords = args->addr;
2042
2043 for (c = 0; c < 2; c++) {
2044 LLVMValueRef tmp;
2045 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2046 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2047 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2048 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2049 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2050 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2051 }
2052
2053
2054 /*
2055 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2056 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2057 * workaround by sampling using a scaled type and converting.
2058 * This is taken from amdgpu-pro shaders.
2059 */
2060 /* NOTE this produces some ugly code compared to amdgpu-pro,
2061 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2062 * and then reads them back. -pro generates two selects,
2063 * one s_cmp for the descriptor rewriting
2064 * one v_cmp for the coordinate and result changes.
2065 */
2066 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2067 LLVMValueRef tmp, tmp2;
2068
2069 /* workaround 8/8/8/8 uint/sint cube gather bug */
2070 /* first detect it then change to a scaled read and f2i */
2071 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2072 tmp2 = tmp;
2073
2074 /* extract the DATA_FORMAT */
2075 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2076 LLVMConstInt(ctx->i32, 6, false), false);
2077
2078 /* is the DATA_FORMAT == 8_8_8_8 */
2079 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2080
2081 if (stype == GLSL_TYPE_UINT)
2082 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2083 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2084 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2085 else
2086 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2087 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2088 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2089
2090 /* replace the NUM FORMAT in the descriptor */
2091 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2092 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2093
2094 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2095
2096 /* don't modify the coordinates for this case */
2097 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2098 }
2099 args->addr = coord;
2100 result = ac_build_image_opcode(ctx, args);
2101
2102 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2103 LLVMValueRef tmp, tmp2;
2104
2105 /* if the cube workaround is in place, f2i the result. */
2106 for (c = 0; c < 4; c++) {
2107 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2108 if (stype == GLSL_TYPE_UINT)
2109 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2110 else
2111 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2112 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2113 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2114 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2115 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2116 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2117 }
2118 }
2119 return result;
2120 }
2121
2122 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2123 const nir_tex_instr *instr,
2124 bool lod_is_zero,
2125 struct ac_image_args *args)
2126 {
2127 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2128 return ac_build_buffer_load_format(&ctx->ac,
2129 args->resource,
2130 args->addr,
2131 LLVMConstInt(ctx->ac.i32, 0, false),
2132 true);
2133 }
2134
2135 args->opcode = ac_image_sample;
2136 args->compare = instr->is_shadow;
2137
2138 switch (instr->op) {
2139 case nir_texop_txf:
2140 case nir_texop_txf_ms:
2141 case nir_texop_samples_identical:
2142 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2143 args->compare = false;
2144 args->offset = false;
2145 break;
2146 case nir_texop_txb:
2147 args->bias = true;
2148 break;
2149 case nir_texop_txl:
2150 if (lod_is_zero)
2151 args->level_zero = true;
2152 else
2153 args->lod = true;
2154 break;
2155 case nir_texop_txs:
2156 case nir_texop_query_levels:
2157 args->opcode = ac_image_get_resinfo;
2158 break;
2159 case nir_texop_tex:
2160 if (ctx->stage != MESA_SHADER_FRAGMENT)
2161 args->level_zero = true;
2162 break;
2163 case nir_texop_txd:
2164 args->deriv = true;
2165 break;
2166 case nir_texop_tg4:
2167 args->opcode = ac_image_gather4;
2168 args->level_zero = true;
2169 break;
2170 case nir_texop_lod:
2171 args->opcode = ac_image_get_lod;
2172 args->compare = false;
2173 args->offset = false;
2174 break;
2175 default:
2176 break;
2177 }
2178
2179 if (instr->op == nir_texop_tg4) {
2180 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2181 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2182 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2183 }
2184 }
2185 return ac_build_image_opcode(&ctx->ac, args);
2186 }
2187
2188 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2189 nir_intrinsic_instr *instr)
2190 {
2191 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2192 unsigned desc_set = nir_intrinsic_desc_set(instr);
2193 unsigned binding = nir_intrinsic_binding(instr);
2194 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2195 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2196 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2197 unsigned base_offset = layout->binding[binding].offset;
2198 LLVMValueRef offset, stride;
2199
2200 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2201 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2202 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2203 layout->binding[binding].dynamic_offset_offset;
2204 desc_ptr = ctx->push_constants;
2205 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2206 stride = LLVMConstInt(ctx->i32, 16, false);
2207 } else
2208 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2209
2210 offset = LLVMConstInt(ctx->i32, base_offset, false);
2211 index = LLVMBuildMul(ctx->builder, index, stride, "");
2212 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2213
2214 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2215 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2216 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2217
2218 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2219 }
2220
2221 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2222 nir_intrinsic_instr *instr)
2223 {
2224 LLVMValueRef ptr, addr;
2225
2226 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2227 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2228
2229 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2230 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2231
2232 return LLVMBuildLoad(ctx->builder, ptr, "");
2233 }
2234
2235 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2236 const nir_intrinsic_instr *instr)
2237 {
2238 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2239
2240 return get_buffer_size(ctx, desc, false);
2241 }
2242 static void visit_store_ssbo(struct ac_nir_context *ctx,
2243 nir_intrinsic_instr *instr)
2244 {
2245 const char *store_name;
2246 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2247 LLVMTypeRef data_type = ctx->ac.f32;
2248 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2249 int components_32bit = elem_size_mult * instr->num_components;
2250 unsigned writemask = nir_intrinsic_write_mask(instr);
2251 LLVMValueRef base_data, base_offset;
2252 LLVMValueRef params[6];
2253 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2254
2255 params[1] = ctx->abi->load_ssbo(ctx->abi,
2256 get_src(ctx, instr->src[1]), true);
2257 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2258 params[4] = i1false; /* glc */
2259 params[5] = i1false; /* slc */
2260
2261 if (components_32bit > 1)
2262 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2263
2264 base_data = to_float(&ctx->ac, src_data);
2265 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2266 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2267 data_type, "");
2268 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2269 while (writemask) {
2270 int start, count;
2271 LLVMValueRef data;
2272 LLVMValueRef offset;
2273 LLVMValueRef tmp;
2274 u_bit_scan_consecutive_range(&writemask, &start, &count);
2275
2276 /* Due to an LLVM limitation, split 3-element writes
2277 * into a 2-element and a 1-element write. */
2278 if (count == 3) {
2279 writemask |= 1 << (start + 2);
2280 count = 2;
2281 }
2282
2283 start *= elem_size_mult;
2284 count *= elem_size_mult;
2285
2286 if (count > 4) {
2287 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2288 count = 4;
2289 }
2290
2291 if (count == 4) {
2292 store_name = "llvm.amdgcn.buffer.store.v4f32";
2293 data = base_data;
2294 } else if (count == 2) {
2295 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2296
2297 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2298 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2299 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2300 ctx->ac.i32_0, "");
2301
2302 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2303 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2304 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2305 ctx->ac.i32_1, "");
2306 store_name = "llvm.amdgcn.buffer.store.v2f32";
2307
2308 } else {
2309 assert(count == 1);
2310 if (get_llvm_num_components(base_data) > 1)
2311 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2312 LLVMConstInt(ctx->ac.i32, start, false), "");
2313 else
2314 data = base_data;
2315 store_name = "llvm.amdgcn.buffer.store.f32";
2316 }
2317
2318 offset = base_offset;
2319 if (start != 0) {
2320 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2321 }
2322 params[0] = data;
2323 params[3] = offset;
2324 ac_build_intrinsic(&ctx->ac, store_name,
2325 ctx->ac.voidt, params, 6, 0);
2326 }
2327 }
2328
2329 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2330 const nir_intrinsic_instr *instr)
2331 {
2332 const char *name;
2333 LLVMValueRef params[6];
2334 int arg_count = 0;
2335
2336 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2337 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2338 }
2339 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2340 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2341 get_src(ctx, instr->src[0]),
2342 true);
2343 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2344 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2345 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2346
2347 switch (instr->intrinsic) {
2348 case nir_intrinsic_ssbo_atomic_add:
2349 name = "llvm.amdgcn.buffer.atomic.add";
2350 break;
2351 case nir_intrinsic_ssbo_atomic_imin:
2352 name = "llvm.amdgcn.buffer.atomic.smin";
2353 break;
2354 case nir_intrinsic_ssbo_atomic_umin:
2355 name = "llvm.amdgcn.buffer.atomic.umin";
2356 break;
2357 case nir_intrinsic_ssbo_atomic_imax:
2358 name = "llvm.amdgcn.buffer.atomic.smax";
2359 break;
2360 case nir_intrinsic_ssbo_atomic_umax:
2361 name = "llvm.amdgcn.buffer.atomic.umax";
2362 break;
2363 case nir_intrinsic_ssbo_atomic_and:
2364 name = "llvm.amdgcn.buffer.atomic.and";
2365 break;
2366 case nir_intrinsic_ssbo_atomic_or:
2367 name = "llvm.amdgcn.buffer.atomic.or";
2368 break;
2369 case nir_intrinsic_ssbo_atomic_xor:
2370 name = "llvm.amdgcn.buffer.atomic.xor";
2371 break;
2372 case nir_intrinsic_ssbo_atomic_exchange:
2373 name = "llvm.amdgcn.buffer.atomic.swap";
2374 break;
2375 case nir_intrinsic_ssbo_atomic_comp_swap:
2376 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2377 break;
2378 default:
2379 abort();
2380 }
2381
2382 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2383 }
2384
2385 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2386 const nir_intrinsic_instr *instr)
2387 {
2388 LLVMValueRef results[2];
2389 int load_components;
2390 int num_components = instr->num_components;
2391 if (instr->dest.ssa.bit_size == 64)
2392 num_components *= 2;
2393
2394 for (int i = 0; i < num_components; i += load_components) {
2395 load_components = MIN2(num_components - i, 4);
2396 const char *load_name;
2397 LLVMTypeRef data_type = ctx->ac.f32;
2398 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2399 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2400
2401 if (load_components == 3)
2402 data_type = LLVMVectorType(ctx->ac.f32, 4);
2403 else if (load_components > 1)
2404 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2405
2406 if (load_components >= 3)
2407 load_name = "llvm.amdgcn.buffer.load.v4f32";
2408 else if (load_components == 2)
2409 load_name = "llvm.amdgcn.buffer.load.v2f32";
2410 else if (load_components == 1)
2411 load_name = "llvm.amdgcn.buffer.load.f32";
2412 else
2413 unreachable("unhandled number of components");
2414
2415 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2416 LLVMValueRef params[] = {
2417 ctx->abi->load_ssbo(ctx->abi,
2418 get_src(ctx, instr->src[0]),
2419 false),
2420 LLVMConstInt(ctx->ac.i32, 0, false),
2421 offset,
2422 i1false,
2423 i1false,
2424 };
2425
2426 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2427
2428 }
2429
2430 LLVMValueRef ret = results[0];
2431 if (num_components > 4 || num_components == 3) {
2432 LLVMValueRef masks[] = {
2433 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2434 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2435 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2436 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2437 };
2438
2439 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2440 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2441 results[num_components > 4 ? 1 : 0], swizzle, "");
2442 }
2443
2444 return LLVMBuildBitCast(ctx->ac.builder, ret,
2445 get_def_type(ctx, &instr->dest.ssa), "");
2446 }
2447
2448 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2449 const nir_intrinsic_instr *instr)
2450 {
2451 LLVMValueRef results[8], ret;
2452 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2453 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2454 int num_components = instr->num_components;
2455
2456 if (ctx->abi->load_ubo)
2457 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2458
2459 if (instr->dest.ssa.bit_size == 64)
2460 num_components *= 2;
2461
2462 for (unsigned i = 0; i < num_components; ++i) {
2463 LLVMValueRef params[] = {
2464 rsrc,
2465 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2466 offset, "")
2467 };
2468 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2469 params, 2,
2470 AC_FUNC_ATTR_READNONE |
2471 AC_FUNC_ATTR_LEGACY);
2472 }
2473
2474
2475 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2476 return LLVMBuildBitCast(ctx->ac.builder, ret,
2477 get_def_type(ctx, &instr->dest.ssa), "");
2478 }
2479
2480 static void
2481 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2482 bool vs_in, unsigned *vertex_index_out,
2483 LLVMValueRef *vertex_index_ref,
2484 unsigned *const_out, LLVMValueRef *indir_out)
2485 {
2486 unsigned const_offset = 0;
2487 nir_deref *tail = &deref->deref;
2488 LLVMValueRef offset = NULL;
2489
2490 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2491 tail = tail->child;
2492 nir_deref_array *deref_array = nir_deref_as_array(tail);
2493 if (vertex_index_out)
2494 *vertex_index_out = deref_array->base_offset;
2495
2496 if (vertex_index_ref) {
2497 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2498 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2499 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2500 }
2501 *vertex_index_ref = vtx;
2502 }
2503 }
2504
2505 if (deref->var->data.compact) {
2506 assert(tail->child->deref_type == nir_deref_type_array);
2507 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2508 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2509 /* We always lower indirect dereferences for "compact" array vars. */
2510 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2511
2512 const_offset = deref_array->base_offset;
2513 goto out;
2514 }
2515
2516 while (tail->child != NULL) {
2517 const struct glsl_type *parent_type = tail->type;
2518 tail = tail->child;
2519
2520 if (tail->deref_type == nir_deref_type_array) {
2521 nir_deref_array *deref_array = nir_deref_as_array(tail);
2522 LLVMValueRef index, stride, local_offset;
2523 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2524
2525 const_offset += size * deref_array->base_offset;
2526 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2527 continue;
2528
2529 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2530 index = get_src(ctx, deref_array->indirect);
2531 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2532 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2533
2534 if (offset)
2535 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2536 else
2537 offset = local_offset;
2538 } else if (tail->deref_type == nir_deref_type_struct) {
2539 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2540
2541 for (unsigned i = 0; i < deref_struct->index; i++) {
2542 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2543 const_offset += glsl_count_attribute_slots(ft, vs_in);
2544 }
2545 } else
2546 unreachable("unsupported deref type");
2547
2548 }
2549 out:
2550 if (const_offset && offset)
2551 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2552 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2553 "");
2554
2555 *const_out = const_offset;
2556 *indir_out = offset;
2557 }
2558
2559 static LLVMValueRef
2560 lds_load(struct nir_to_llvm_context *ctx,
2561 LLVMValueRef dw_addr)
2562 {
2563 LLVMValueRef value;
2564 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2565 return value;
2566 }
2567
2568 static void
2569 lds_store(struct nir_to_llvm_context *ctx,
2570 LLVMValueRef dw_addr, LLVMValueRef value)
2571 {
2572 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2573 ac_build_indexed_store(&ctx->ac, ctx->lds,
2574 dw_addr, value);
2575 }
2576
2577 /* The offchip buffer layout for TCS->TES is
2578 *
2579 * - attribute 0 of patch 0 vertex 0
2580 * - attribute 0 of patch 0 vertex 1
2581 * - attribute 0 of patch 0 vertex 2
2582 * ...
2583 * - attribute 0 of patch 1 vertex 0
2584 * - attribute 0 of patch 1 vertex 1
2585 * ...
2586 * - attribute 1 of patch 0 vertex 0
2587 * - attribute 1 of patch 0 vertex 1
2588 * ...
2589 * - per patch attribute 0 of patch 0
2590 * - per patch attribute 0 of patch 1
2591 * ...
2592 *
2593 * Note that every attribute has 4 components.
2594 */
2595 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2596 LLVMValueRef vertex_index,
2597 LLVMValueRef param_index)
2598 {
2599 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2600 LLVMValueRef param_stride, constant16;
2601 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2602
2603 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2604 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2605 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2606 num_patches, "");
2607
2608 constant16 = LLVMConstInt(ctx->i32, 16, false);
2609 if (vertex_index) {
2610 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2611 vertices_per_patch, "");
2612
2613 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2614 vertex_index, "");
2615
2616 param_stride = total_vertices;
2617 } else {
2618 base_addr = rel_patch_id;
2619 param_stride = num_patches;
2620 }
2621
2622 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2623 LLVMBuildMul(ctx->builder, param_index,
2624 param_stride, ""), "");
2625
2626 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2627
2628 if (!vertex_index) {
2629 LLVMValueRef patch_data_offset =
2630 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2631
2632 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2633 patch_data_offset, "");
2634 }
2635 return base_addr;
2636 }
2637
2638 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2639 unsigned param,
2640 unsigned const_index,
2641 bool is_compact,
2642 LLVMValueRef vertex_index,
2643 LLVMValueRef indir_index)
2644 {
2645 LLVMValueRef param_index;
2646
2647 if (indir_index)
2648 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2649 indir_index, "");
2650 else {
2651 if (const_index && !is_compact)
2652 param += const_index;
2653 param_index = LLVMConstInt(ctx->i32, param, false);
2654 }
2655 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2656 }
2657
2658 static void
2659 mark_tess_output(struct nir_to_llvm_context *ctx,
2660 bool is_patch, uint32_t param)
2661
2662 {
2663 if (is_patch) {
2664 ctx->tess_patch_outputs_written |= (1ull << param);
2665 } else
2666 ctx->tess_outputs_written |= (1ull << param);
2667 }
2668
2669 static LLVMValueRef
2670 get_dw_address(struct nir_to_llvm_context *ctx,
2671 LLVMValueRef dw_addr,
2672 unsigned param,
2673 unsigned const_index,
2674 bool compact_const_index,
2675 LLVMValueRef vertex_index,
2676 LLVMValueRef stride,
2677 LLVMValueRef indir_index)
2678
2679 {
2680
2681 if (vertex_index) {
2682 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2683 LLVMBuildMul(ctx->builder,
2684 vertex_index,
2685 stride, ""), "");
2686 }
2687
2688 if (indir_index)
2689 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2690 LLVMBuildMul(ctx->builder, indir_index,
2691 LLVMConstInt(ctx->i32, 4, false), ""), "");
2692 else if (const_index && !compact_const_index)
2693 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2694 LLVMConstInt(ctx->i32, const_index, false), "");
2695
2696 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2697 LLVMConstInt(ctx->i32, param * 4, false), "");
2698
2699 if (const_index && compact_const_index)
2700 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2701 LLVMConstInt(ctx->i32, const_index, false), "");
2702 return dw_addr;
2703 }
2704
2705 static LLVMValueRef
2706 load_tcs_input(struct nir_to_llvm_context *ctx,
2707 nir_intrinsic_instr *instr)
2708 {
2709 LLVMValueRef dw_addr, stride;
2710 unsigned const_index;
2711 LLVMValueRef vertex_index;
2712 LLVMValueRef indir_index;
2713 unsigned param;
2714 LLVMValueRef value[4], result;
2715 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2716 const bool is_compact = instr->variables[0]->var->data.compact;
2717 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2718 get_deref_offset(ctx->nir, instr->variables[0],
2719 false, NULL, per_vertex ? &vertex_index : NULL,
2720 &const_index, &indir_index);
2721
2722 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2723 dw_addr = get_tcs_in_current_patch_offset(ctx);
2724 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2725 indir_index);
2726
2727 for (unsigned i = 0; i < instr->num_components; i++) {
2728 value[i] = lds_load(ctx, dw_addr);
2729 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2730 ctx->i32one, "");
2731 }
2732 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2733 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2734 return result;
2735 }
2736
2737 static LLVMValueRef
2738 load_tcs_output(struct nir_to_llvm_context *ctx,
2739 nir_intrinsic_instr *instr)
2740 {
2741 LLVMValueRef dw_addr, stride;
2742 LLVMValueRef value[4], result;
2743 LLVMValueRef vertex_index = NULL;
2744 LLVMValueRef indir_index = NULL;
2745 unsigned const_index = 0;
2746 unsigned param;
2747 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2748 const bool is_compact = instr->variables[0]->var->data.compact;
2749 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2750 get_deref_offset(ctx->nir, instr->variables[0],
2751 false, NULL, per_vertex ? &vertex_index : NULL,
2752 &const_index, &indir_index);
2753
2754 if (!instr->variables[0]->var->data.patch) {
2755 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2756 dw_addr = get_tcs_out_current_patch_offset(ctx);
2757 } else {
2758 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2759 }
2760
2761 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2762 indir_index);
2763
2764 for (unsigned i = 0; i < instr->num_components; i++) {
2765 value[i] = lds_load(ctx, dw_addr);
2766 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2767 ctx->i32one, "");
2768 }
2769 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2770 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2771 return result;
2772 }
2773
2774 static void
2775 store_tcs_output(struct nir_to_llvm_context *ctx,
2776 nir_intrinsic_instr *instr,
2777 LLVMValueRef src,
2778 unsigned writemask)
2779 {
2780 LLVMValueRef stride, dw_addr;
2781 LLVMValueRef buf_addr = NULL;
2782 LLVMValueRef vertex_index = NULL;
2783 LLVMValueRef indir_index = NULL;
2784 unsigned const_index = 0;
2785 unsigned param;
2786 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2787 const bool is_compact = instr->variables[0]->var->data.compact;
2788
2789 get_deref_offset(ctx->nir, instr->variables[0],
2790 false, NULL, per_vertex ? &vertex_index : NULL,
2791 &const_index, &indir_index);
2792
2793 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2794 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2795 is_compact && const_index > 3) {
2796 const_index -= 3;
2797 param++;
2798 }
2799
2800 if (!instr->variables[0]->var->data.patch) {
2801 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2802 dw_addr = get_tcs_out_current_patch_offset(ctx);
2803 } else {
2804 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2805 }
2806
2807 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2808
2809 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2810 indir_index);
2811 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2812 vertex_index, indir_index);
2813
2814 unsigned base = is_compact ? const_index : 0;
2815 for (unsigned chan = 0; chan < 8; chan++) {
2816 bool is_tess_factor = false;
2817 if (!(writemask & (1 << chan)))
2818 continue;
2819 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2820
2821 lds_store(ctx, dw_addr, value);
2822
2823 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2824 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2825 is_tess_factor = true;
2826
2827 if (!is_tess_factor && writemask != 0xF)
2828 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2829 buf_addr, ctx->oc_lds,
2830 4 * (base + chan), 1, 0, true, false);
2831
2832 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2833 ctx->i32one, "");
2834 }
2835
2836 if (writemask == 0xF) {
2837 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2838 buf_addr, ctx->oc_lds,
2839 (base * 4), 1, 0, true, false);
2840 }
2841 }
2842
2843 static LLVMValueRef
2844 load_tes_input(struct nir_to_llvm_context *ctx,
2845 const nir_intrinsic_instr *instr)
2846 {
2847 LLVMValueRef buf_addr;
2848 LLVMValueRef result;
2849 LLVMValueRef vertex_index = NULL;
2850 LLVMValueRef indir_index = NULL;
2851 unsigned const_index = 0;
2852 unsigned param;
2853 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2854 const bool is_compact = instr->variables[0]->var->data.compact;
2855
2856 get_deref_offset(ctx->nir, instr->variables[0],
2857 false, NULL, per_vertex ? &vertex_index : NULL,
2858 &const_index, &indir_index);
2859 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2860 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2861 is_compact && const_index > 3) {
2862 const_index -= 3;
2863 param++;
2864 }
2865 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2866 is_compact, vertex_index, indir_index);
2867
2868 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2869 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2870 result = trim_vector(&ctx->ac, result, instr->num_components);
2871 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2872 return result;
2873 }
2874
2875 static LLVMValueRef
2876 load_gs_input(struct nir_to_llvm_context *ctx,
2877 nir_intrinsic_instr *instr)
2878 {
2879 LLVMValueRef indir_index, vtx_offset;
2880 unsigned const_index;
2881 LLVMValueRef args[9];
2882 unsigned param, vtx_offset_param;
2883 LLVMValueRef value[4], result;
2884 unsigned vertex_index;
2885 get_deref_offset(ctx->nir, instr->variables[0],
2886 false, &vertex_index, NULL,
2887 &const_index, &indir_index);
2888 vtx_offset_param = vertex_index;
2889 assert(vtx_offset_param < 6);
2890 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2891 LLVMConstInt(ctx->i32, 4, false), "");
2892
2893 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2894 for (unsigned i = 0; i < instr->num_components; i++) {
2895
2896 args[0] = ctx->esgs_ring;
2897 args[1] = vtx_offset;
2898 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2899 args[3] = ctx->i32zero;
2900 args[4] = ctx->i32one; /* OFFEN */
2901 args[5] = ctx->i32zero; /* IDXEN */
2902 args[6] = ctx->i32one; /* GLC */
2903 args[7] = ctx->i32zero; /* SLC */
2904 args[8] = ctx->i32zero; /* TFE */
2905
2906 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2907 ctx->i32, args, 9,
2908 AC_FUNC_ATTR_READONLY |
2909 AC_FUNC_ATTR_LEGACY);
2910 }
2911 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2912
2913 return result;
2914 }
2915
2916 static LLVMValueRef
2917 build_gep_for_deref(struct ac_nir_context *ctx,
2918 nir_deref_var *deref)
2919 {
2920 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2921 assert(entry->data);
2922 LLVMValueRef val = entry->data;
2923 nir_deref *tail = deref->deref.child;
2924 while (tail != NULL) {
2925 LLVMValueRef offset;
2926 switch (tail->deref_type) {
2927 case nir_deref_type_array: {
2928 nir_deref_array *array = nir_deref_as_array(tail);
2929 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2930 if (array->deref_array_type ==
2931 nir_deref_array_type_indirect) {
2932 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2933 get_src(ctx,
2934 array->indirect),
2935 "");
2936 }
2937 break;
2938 }
2939 case nir_deref_type_struct: {
2940 nir_deref_struct *deref_struct =
2941 nir_deref_as_struct(tail);
2942 offset = LLVMConstInt(ctx->ac.i32,
2943 deref_struct->index, 0);
2944 break;
2945 }
2946 default:
2947 unreachable("bad deref type");
2948 }
2949 val = ac_build_gep0(&ctx->ac, val, offset);
2950 tail = tail->child;
2951 }
2952 return val;
2953 }
2954
2955 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2956 nir_intrinsic_instr *instr)
2957 {
2958 LLVMValueRef values[8];
2959 int idx = instr->variables[0]->var->data.driver_location;
2960 int ve = instr->dest.ssa.num_components;
2961 LLVMValueRef indir_index;
2962 LLVMValueRef ret;
2963 unsigned const_index;
2964 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2965 instr->variables[0]->var->data.mode == nir_var_shader_in;
2966 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2967 &const_index, &indir_index);
2968
2969 if (instr->dest.ssa.bit_size == 64)
2970 ve *= 2;
2971
2972 switch (instr->variables[0]->var->data.mode) {
2973 case nir_var_shader_in:
2974 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2975 return load_tcs_input(ctx->nctx, instr);
2976 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2977 return load_tes_input(ctx->nctx, instr);
2978 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2979 return load_gs_input(ctx->nctx, instr);
2980 }
2981 for (unsigned chan = 0; chan < ve; chan++) {
2982 if (indir_index) {
2983 unsigned count = glsl_count_attribute_slots(
2984 instr->variables[0]->var->type,
2985 ctx->stage == MESA_SHADER_VERTEX);
2986 count -= chan / 4;
2987 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2988 &ctx->ac, ctx->abi->inputs + idx + chan, count,
2989 4, false);
2990
2991 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2992 tmp_vec,
2993 indir_index, "");
2994 } else
2995 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
2996 }
2997 break;
2998 case nir_var_local:
2999 for (unsigned chan = 0; chan < ve; chan++) {
3000 if (indir_index) {
3001 unsigned count = glsl_count_attribute_slots(
3002 instr->variables[0]->var->type, false);
3003 count -= chan / 4;
3004 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3005 &ctx->ac, ctx->locals + idx + chan, count,
3006 4, true);
3007
3008 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3009 tmp_vec,
3010 indir_index, "");
3011 } else {
3012 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3013 }
3014 }
3015 break;
3016 case nir_var_shared: {
3017 LLVMValueRef address = build_gep_for_deref(ctx,
3018 instr->variables[0]);
3019 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3020 return LLVMBuildBitCast(ctx->ac.builder, val,
3021 get_def_type(ctx, &instr->dest.ssa),
3022 "");
3023 }
3024 case nir_var_shader_out:
3025 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3026 return load_tcs_output(ctx->nctx, instr);
3027 for (unsigned chan = 0; chan < ve; chan++) {
3028 if (indir_index) {
3029 unsigned count = glsl_count_attribute_slots(
3030 instr->variables[0]->var->type, false);
3031 count -= chan / 4;
3032 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3033 &ctx->ac, ctx->outputs + idx + chan, count,
3034 4, true);
3035
3036 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3037 tmp_vec,
3038 indir_index, "");
3039 } else {
3040 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3041 ctx->outputs[idx + chan + const_index * 4],
3042 "");
3043 }
3044 }
3045 break;
3046 default:
3047 unreachable("unhandle variable mode");
3048 }
3049 ret = ac_build_gather_values(&ctx->ac, values, ve);
3050 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3051 }
3052
3053 static void
3054 visit_store_var(struct ac_nir_context *ctx,
3055 nir_intrinsic_instr *instr)
3056 {
3057 LLVMValueRef temp_ptr, value;
3058 int idx = instr->variables[0]->var->data.driver_location;
3059 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3060 int writemask = instr->const_index[0];
3061 LLVMValueRef indir_index;
3062 unsigned const_index;
3063 get_deref_offset(ctx, instr->variables[0], false,
3064 NULL, NULL, &const_index, &indir_index);
3065
3066 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3067 int old_writemask = writemask;
3068
3069 src = LLVMBuildBitCast(ctx->ac.builder, src,
3070 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3071 "");
3072
3073 writemask = 0;
3074 for (unsigned chan = 0; chan < 4; chan++) {
3075 if (old_writemask & (1 << chan))
3076 writemask |= 3u << (2 * chan);
3077 }
3078 }
3079
3080 switch (instr->variables[0]->var->data.mode) {
3081 case nir_var_shader_out:
3082
3083 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3084 store_tcs_output(ctx->nctx, instr, src, writemask);
3085 return;
3086 }
3087
3088 for (unsigned chan = 0; chan < 8; chan++) {
3089 int stride = 4;
3090 if (!(writemask & (1 << chan)))
3091 continue;
3092
3093 value = llvm_extract_elem(&ctx->ac, src, chan);
3094
3095 if (instr->variables[0]->var->data.compact)
3096 stride = 1;
3097 if (indir_index) {
3098 unsigned count = glsl_count_attribute_slots(
3099 instr->variables[0]->var->type, false);
3100 count -= chan / 4;
3101 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3102 &ctx->ac, ctx->outputs + idx + chan, count,
3103 stride, true);
3104
3105 if (get_llvm_num_components(tmp_vec) > 1) {
3106 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3107 value, indir_index, "");
3108 } else
3109 tmp_vec = value;
3110 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3111 count, stride, tmp_vec);
3112
3113 } else {
3114 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3115
3116 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3117 }
3118 }
3119 break;
3120 case nir_var_local:
3121 for (unsigned chan = 0; chan < 8; chan++) {
3122 if (!(writemask & (1 << chan)))
3123 continue;
3124
3125 value = llvm_extract_elem(&ctx->ac, src, chan);
3126 if (indir_index) {
3127 unsigned count = glsl_count_attribute_slots(
3128 instr->variables[0]->var->type, false);
3129 count -= chan / 4;
3130 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3131 &ctx->ac, ctx->locals + idx + chan, count,
3132 4, true);
3133
3134 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3135 value, indir_index, "");
3136 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3137 count, 4, tmp_vec);
3138 } else {
3139 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3140
3141 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3142 }
3143 }
3144 break;
3145 case nir_var_shared: {
3146 int writemask = instr->const_index[0];
3147 LLVMValueRef address = build_gep_for_deref(ctx,
3148 instr->variables[0]);
3149 LLVMValueRef val = get_src(ctx, instr->src[0]);
3150 unsigned components =
3151 glsl_get_vector_elements(
3152 nir_deref_tail(&instr->variables[0]->deref)->type);
3153 if (writemask == (1 << components) - 1) {
3154 val = LLVMBuildBitCast(
3155 ctx->ac.builder, val,
3156 LLVMGetElementType(LLVMTypeOf(address)), "");
3157 LLVMBuildStore(ctx->ac.builder, val, address);
3158 } else {
3159 for (unsigned chan = 0; chan < 4; chan++) {
3160 if (!(writemask & (1 << chan)))
3161 continue;
3162 LLVMValueRef ptr =
3163 LLVMBuildStructGEP(ctx->ac.builder,
3164 address, chan, "");
3165 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3166 chan);
3167 src = LLVMBuildBitCast(
3168 ctx->ac.builder, src,
3169 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3170 LLVMBuildStore(ctx->ac.builder, src, ptr);
3171 }
3172 }
3173 break;
3174 }
3175 default:
3176 break;
3177 }
3178 }
3179
3180 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3181 {
3182 switch (dim) {
3183 case GLSL_SAMPLER_DIM_BUF:
3184 return 1;
3185 case GLSL_SAMPLER_DIM_1D:
3186 return array ? 2 : 1;
3187 case GLSL_SAMPLER_DIM_2D:
3188 return array ? 3 : 2;
3189 case GLSL_SAMPLER_DIM_MS:
3190 return array ? 4 : 3;
3191 case GLSL_SAMPLER_DIM_3D:
3192 case GLSL_SAMPLER_DIM_CUBE:
3193 return 3;
3194 case GLSL_SAMPLER_DIM_RECT:
3195 case GLSL_SAMPLER_DIM_SUBPASS:
3196 return 2;
3197 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3198 return 3;
3199 default:
3200 break;
3201 }
3202 return 0;
3203 }
3204
3205
3206
3207 /* Adjust the sample index according to FMASK.
3208 *
3209 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3210 * which is the identity mapping. Each nibble says which physical sample
3211 * should be fetched to get that sample.
3212 *
3213 * For example, 0x11111100 means there are only 2 samples stored and
3214 * the second sample covers 3/4 of the pixel. When reading samples 0
3215 * and 1, return physical sample 0 (determined by the first two 0s
3216 * in FMASK), otherwise return physical sample 1.
3217 *
3218 * The sample index should be adjusted as follows:
3219 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3220 */
3221 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3222 LLVMValueRef coord_x, LLVMValueRef coord_y,
3223 LLVMValueRef coord_z,
3224 LLVMValueRef sample_index,
3225 LLVMValueRef fmask_desc_ptr)
3226 {
3227 LLVMValueRef fmask_load_address[4];
3228 LLVMValueRef res;
3229
3230 fmask_load_address[0] = coord_x;
3231 fmask_load_address[1] = coord_y;
3232 if (coord_z) {
3233 fmask_load_address[2] = coord_z;
3234 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3235 }
3236
3237 struct ac_image_args args = {0};
3238
3239 args.opcode = ac_image_load;
3240 args.da = coord_z ? true : false;
3241 args.resource = fmask_desc_ptr;
3242 args.dmask = 0xf;
3243 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3244
3245 res = ac_build_image_opcode(ctx, &args);
3246
3247 res = to_integer(ctx, res);
3248 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3249 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3250
3251 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3252 res,
3253 ctx->i32_0, "");
3254
3255 LLVMValueRef sample_index4 =
3256 LLVMBuildMul(ctx->builder, sample_index, four, "");
3257 LLVMValueRef shifted_fmask =
3258 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3259 LLVMValueRef final_sample =
3260 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3261
3262 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3263 * resource descriptor is 0 (invalid),
3264 */
3265 LLVMValueRef fmask_desc =
3266 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3267 ctx->v8i32, "");
3268
3269 LLVMValueRef fmask_word1 =
3270 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3271 ctx->i32_1, "");
3272
3273 LLVMValueRef word1_is_nonzero =
3274 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3275 fmask_word1, ctx->i32_0, "");
3276
3277 /* Replace the MSAA sample index. */
3278 sample_index =
3279 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3280 final_sample, sample_index, "");
3281 return sample_index;
3282 }
3283
3284 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3285 const nir_intrinsic_instr *instr)
3286 {
3287 const struct glsl_type *type = instr->variables[0]->var->type;
3288 if(instr->variables[0]->deref.child)
3289 type = instr->variables[0]->deref.child->type;
3290
3291 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3292 LLVMValueRef coords[4];
3293 LLVMValueRef masks[] = {
3294 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3295 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3296 };
3297 LLVMValueRef res;
3298 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3299
3300 int count;
3301 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3302 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3303 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3304 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3305 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3306
3307 count = image_type_to_components_count(dim,
3308 glsl_sampler_type_is_array(type));
3309
3310 if (is_ms) {
3311 LLVMValueRef fmask_load_address[3];
3312 int chan;
3313
3314 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3315 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3316 if (glsl_sampler_type_is_array(type))
3317 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3318 else
3319 fmask_load_address[2] = NULL;
3320 if (add_frag_pos) {
3321 for (chan = 0; chan < 2; ++chan)
3322 fmask_load_address[chan] = LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->nctx->frag_pos[chan], ctx->ac.i32, ""), "");
3323 }
3324 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3325 fmask_load_address[0],
3326 fmask_load_address[1],
3327 fmask_load_address[2],
3328 sample_index,
3329 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3330 }
3331 if (count == 1) {
3332 if (instr->src[0].ssa->num_components)
3333 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3334 else
3335 res = src0;
3336 } else {
3337 int chan;
3338 if (is_ms)
3339 count--;
3340 for (chan = 0; chan < count; ++chan) {
3341 coords[chan] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[chan], "");
3342 }
3343
3344 if (add_frag_pos) {
3345 for (chan = 0; chan < count; ++chan)
3346 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->nctx->frag_pos[chan], ctx->ac.i32, ""), "");
3347 }
3348 if (is_ms) {
3349 coords[count] = sample_index;
3350 count++;
3351 }
3352
3353 if (count == 3) {
3354 coords[3] = LLVMGetUndef(ctx->ac.i32);
3355 count = 4;
3356 }
3357 res = ac_build_gather_values(&ctx->ac, coords, count);
3358 }
3359 return res;
3360 }
3361
3362 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3363 const nir_intrinsic_instr *instr)
3364 {
3365 LLVMValueRef params[7];
3366 LLVMValueRef res;
3367 char intrinsic_name[64];
3368 const nir_variable *var = instr->variables[0]->var;
3369 const struct glsl_type *type = var->type;
3370 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3371 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3372
3373 if(instr->variables[0]->deref.child)
3374 type = instr->variables[0]->deref.child->type;
3375
3376 type = glsl_without_array(type);
3377 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3378 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3379 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3380 ctx->ac.i32_0, ""); /* vindex */
3381 params[2] = ctx->ac.i32_0; /* voffset */
3382 params[3] = i1false; /* glc */
3383 params[4] = i1false; /* slc */
3384 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3385 params, 5, 0);
3386
3387 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3388 res = to_integer(&ctx->ac, res);
3389 } else {
3390 bool is_da = glsl_sampler_type_is_array(type) ||
3391 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3392 LLVMValueRef da = is_da ? i1true : i1false;
3393 LLVMValueRef glc = i1false;
3394 LLVMValueRef slc = i1false;
3395
3396 params[0] = get_image_coords(ctx, instr);
3397 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3398 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3399 if (HAVE_LLVM <= 0x0309) {
3400 params[3] = i1false; /* r128 */
3401 params[4] = da;
3402 params[5] = glc;
3403 params[6] = slc;
3404 } else {
3405 LLVMValueRef lwe = i1false;
3406 params[3] = glc;
3407 params[4] = slc;
3408 params[5] = lwe;
3409 params[6] = da;
3410 }
3411
3412 ac_get_image_intr_name("llvm.amdgcn.image.load",
3413 ctx->ac.v4f32, /* vdata */
3414 LLVMTypeOf(params[0]), /* coords */
3415 LLVMTypeOf(params[1]), /* rsrc */
3416 intrinsic_name, sizeof(intrinsic_name));
3417
3418 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3419 params, 7, AC_FUNC_ATTR_READONLY);
3420 }
3421 return to_integer(&ctx->ac, res);
3422 }
3423
3424 static void visit_image_store(struct ac_nir_context *ctx,
3425 nir_intrinsic_instr *instr)
3426 {
3427 LLVMValueRef params[8];
3428 char intrinsic_name[64];
3429 const nir_variable *var = instr->variables[0]->var;
3430 const struct glsl_type *type = glsl_without_array(var->type);
3431 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3432 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3433 LLVMValueRef glc = i1false;
3434 bool force_glc = ctx->abi->chip_class == SI;
3435 if (force_glc)
3436 glc = i1true;
3437
3438 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3439 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3440 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3441 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3442 ctx->ac.i32_0, ""); /* vindex */
3443 params[3] = ctx->ac.i32_0; /* voffset */
3444 params[4] = glc; /* glc */
3445 params[5] = i1false; /* slc */
3446 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3447 params, 6, 0);
3448 } else {
3449 bool is_da = glsl_sampler_type_is_array(type) ||
3450 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3451 LLVMValueRef da = is_da ? i1true : i1false;
3452 LLVMValueRef slc = i1false;
3453
3454 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3455 params[1] = get_image_coords(ctx, instr); /* coords */
3456 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3457 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3458 if (HAVE_LLVM <= 0x0309) {
3459 params[4] = i1false; /* r128 */
3460 params[5] = da;
3461 params[6] = glc;
3462 params[7] = slc;
3463 } else {
3464 LLVMValueRef lwe = i1false;
3465 params[4] = glc;
3466 params[5] = slc;
3467 params[6] = lwe;
3468 params[7] = da;
3469 }
3470
3471 ac_get_image_intr_name("llvm.amdgcn.image.store",
3472 LLVMTypeOf(params[0]), /* vdata */
3473 LLVMTypeOf(params[1]), /* coords */
3474 LLVMTypeOf(params[2]), /* rsrc */
3475 intrinsic_name, sizeof(intrinsic_name));
3476
3477 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3478 params, 8, 0);
3479 }
3480
3481 }
3482
3483 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3484 const nir_intrinsic_instr *instr)
3485 {
3486 LLVMValueRef params[6];
3487 int param_count = 0;
3488 const nir_variable *var = instr->variables[0]->var;
3489
3490 const char *atomic_name;
3491 char intrinsic_name[41];
3492 const struct glsl_type *type = glsl_without_array(var->type);
3493 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3494 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3495 MAYBE_UNUSED int length;
3496
3497 switch (instr->intrinsic) {
3498 case nir_intrinsic_image_atomic_add:
3499 atomic_name = "add";
3500 break;
3501 case nir_intrinsic_image_atomic_min:
3502 atomic_name = "smin";
3503 break;
3504 case nir_intrinsic_image_atomic_max:
3505 atomic_name = "smax";
3506 break;
3507 case nir_intrinsic_image_atomic_and:
3508 atomic_name = "and";
3509 break;
3510 case nir_intrinsic_image_atomic_or:
3511 atomic_name = "or";
3512 break;
3513 case nir_intrinsic_image_atomic_xor:
3514 atomic_name = "xor";
3515 break;
3516 case nir_intrinsic_image_atomic_exchange:
3517 atomic_name = "swap";
3518 break;
3519 case nir_intrinsic_image_atomic_comp_swap:
3520 atomic_name = "cmpswap";
3521 break;
3522 default:
3523 abort();
3524 }
3525
3526 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3527 params[param_count++] = get_src(ctx, instr->src[3]);
3528 params[param_count++] = get_src(ctx, instr->src[2]);
3529
3530 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3531 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3532 true, true);
3533 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3534 ctx->ac.i32_0, ""); /* vindex */
3535 params[param_count++] = ctx->ac.i32_0; /* voffset */
3536 params[param_count++] = i1false; /* slc */
3537
3538 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3539 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3540 } else {
3541 char coords_type[8];
3542
3543 bool da = glsl_sampler_type_is_array(type) ||
3544 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3545
3546 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3547 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3548 true, true);
3549 params[param_count++] = i1false; /* r128 */
3550 params[param_count++] = da ? i1true : i1false; /* da */
3551 params[param_count++] = i1false; /* slc */
3552
3553 build_int_type_name(LLVMTypeOf(coords),
3554 coords_type, sizeof(coords_type));
3555
3556 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3557 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3558 }
3559
3560 assert(length < sizeof(intrinsic_name));
3561 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3562 }
3563
3564 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3565 const nir_intrinsic_instr *instr)
3566 {
3567 LLVMValueRef res;
3568 const nir_variable *var = instr->variables[0]->var;
3569 const struct glsl_type *type = instr->variables[0]->var->type;
3570 bool da = glsl_sampler_type_is_array(var->type) ||
3571 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3572 if(instr->variables[0]->deref.child)
3573 type = instr->variables[0]->deref.child->type;
3574
3575 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3576 return get_buffer_size(ctx,
3577 get_sampler_desc(ctx, instr->variables[0],
3578 AC_DESC_BUFFER, true, false), true);
3579
3580 struct ac_image_args args = { 0 };
3581
3582 args.da = da;
3583 args.dmask = 0xf;
3584 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3585 args.opcode = ac_image_get_resinfo;
3586 args.addr = ctx->ac.i32_0;
3587
3588 res = ac_build_image_opcode(&ctx->ac, &args);
3589
3590 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3591 glsl_sampler_type_is_array(type)) {
3592 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3593 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3594 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3595 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3596 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3597 }
3598 return res;
3599 }
3600
3601 #define NOOP_WAITCNT 0xf7f
3602 #define LGKM_CNT 0x07f
3603 #define VM_CNT 0xf70
3604
3605 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3606 unsigned simm16)
3607 {
3608 LLVMValueRef args[1] = {
3609 LLVMConstInt(ctx->i32, simm16, false),
3610 };
3611 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3612 ctx->voidt, args, 1, 0);
3613 }
3614
3615 static void emit_barrier(struct nir_to_llvm_context *ctx)
3616 {
3617 /* SI only (thanks to a hw bug workaround):
3618 * The real barrier instruction isn’t needed, because an entire patch
3619 * always fits into a single wave.
3620 */
3621 if (ctx->options->chip_class == SI &&
3622 ctx->stage == MESA_SHADER_TESS_CTRL) {
3623 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3624 return;
3625 }
3626 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3627 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3628 }
3629
3630 static void emit_discard_if(struct ac_nir_context *ctx,
3631 const nir_intrinsic_instr *instr)
3632 {
3633 LLVMValueRef cond;
3634
3635 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
3636 get_src(ctx, instr->src[0]),
3637 ctx->ac.i32_0, "");
3638
3639 cond = LLVMBuildSelect(ctx->ac.builder, cond,
3640 LLVMConstReal(ctx->ac.f32, -1.0f),
3641 ctx->ac.f32_0, "");
3642 ac_build_kill(&ctx->ac, cond);
3643 }
3644
3645 static LLVMValueRef
3646 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3647 {
3648 LLVMValueRef result;
3649 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3650 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3651 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3652
3653 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3654 }
3655
3656 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3657 const nir_intrinsic_instr *instr)
3658 {
3659 LLVMValueRef ptr, result;
3660 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3661 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3662
3663 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3664 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3665 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3666 ptr, src, src1,
3667 LLVMAtomicOrderingSequentiallyConsistent,
3668 LLVMAtomicOrderingSequentiallyConsistent,
3669 false);
3670 } else {
3671 LLVMAtomicRMWBinOp op;
3672 switch (instr->intrinsic) {
3673 case nir_intrinsic_var_atomic_add:
3674 op = LLVMAtomicRMWBinOpAdd;
3675 break;
3676 case nir_intrinsic_var_atomic_umin:
3677 op = LLVMAtomicRMWBinOpUMin;
3678 break;
3679 case nir_intrinsic_var_atomic_umax:
3680 op = LLVMAtomicRMWBinOpUMax;
3681 break;
3682 case nir_intrinsic_var_atomic_imin:
3683 op = LLVMAtomicRMWBinOpMin;
3684 break;
3685 case nir_intrinsic_var_atomic_imax:
3686 op = LLVMAtomicRMWBinOpMax;
3687 break;
3688 case nir_intrinsic_var_atomic_and:
3689 op = LLVMAtomicRMWBinOpAnd;
3690 break;
3691 case nir_intrinsic_var_atomic_or:
3692 op = LLVMAtomicRMWBinOpOr;
3693 break;
3694 case nir_intrinsic_var_atomic_xor:
3695 op = LLVMAtomicRMWBinOpXor;
3696 break;
3697 case nir_intrinsic_var_atomic_exchange:
3698 op = LLVMAtomicRMWBinOpXchg;
3699 break;
3700 default:
3701 return NULL;
3702 }
3703
3704 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3705 LLVMAtomicOrderingSequentiallyConsistent,
3706 false);
3707 }
3708 return result;
3709 }
3710
3711 #define INTERP_CENTER 0
3712 #define INTERP_CENTROID 1
3713 #define INTERP_SAMPLE 2
3714
3715 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3716 enum glsl_interp_mode interp, unsigned location)
3717 {
3718 switch (interp) {
3719 case INTERP_MODE_FLAT:
3720 default:
3721 return NULL;
3722 case INTERP_MODE_SMOOTH:
3723 case INTERP_MODE_NONE:
3724 if (location == INTERP_CENTER)
3725 return ctx->persp_center;
3726 else if (location == INTERP_CENTROID)
3727 return ctx->persp_centroid;
3728 else if (location == INTERP_SAMPLE)
3729 return ctx->persp_sample;
3730 break;
3731 case INTERP_MODE_NOPERSPECTIVE:
3732 if (location == INTERP_CENTER)
3733 return ctx->linear_center;
3734 else if (location == INTERP_CENTROID)
3735 return ctx->linear_centroid;
3736 else if (location == INTERP_SAMPLE)
3737 return ctx->linear_sample;
3738 break;
3739 }
3740 return NULL;
3741 }
3742
3743 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3744 LLVMValueRef sample_id)
3745 {
3746 LLVMValueRef result;
3747 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3748
3749 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3750 const_array(ctx->v2f32, 64), "");
3751
3752 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3753 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3754
3755 return result;
3756 }
3757
3758 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3759 {
3760 LLVMValueRef values[2];
3761
3762 values[0] = emit_ffract(&ctx->ac, ctx->frag_pos[0]);
3763 values[1] = emit_ffract(&ctx->ac, ctx->frag_pos[1]);
3764 return ac_build_gather_values(&ctx->ac, values, 2);
3765 }
3766
3767 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3768 const nir_intrinsic_instr *instr)
3769 {
3770 LLVMValueRef result[2];
3771 LLVMValueRef interp_param, attr_number;
3772 unsigned location;
3773 unsigned chan;
3774 LLVMValueRef src_c0, src_c1;
3775 LLVMValueRef src0;
3776 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3777 switch (instr->intrinsic) {
3778 case nir_intrinsic_interp_var_at_centroid:
3779 location = INTERP_CENTROID;
3780 break;
3781 case nir_intrinsic_interp_var_at_sample:
3782 case nir_intrinsic_interp_var_at_offset:
3783 location = INTERP_CENTER;
3784 src0 = get_src(ctx->nir, instr->src[0]);
3785 break;
3786 default:
3787 break;
3788 }
3789
3790 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3791 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3792 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3793 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3794 LLVMValueRef sample_position;
3795 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3796
3797 /* fetch sample ID */
3798 sample_position = load_sample_position(ctx, src0);
3799
3800 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3801 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3802 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3803 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3804 }
3805 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3806 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3807
3808 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3809 LLVMValueRef ij_out[2];
3810 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3811
3812 /*
3813 * take the I then J parameters, and the DDX/Y for it, and
3814 * calculate the IJ inputs for the interpolator.
3815 * temp1 = ddx * offset/sample.x + I;
3816 * interp_param.I = ddy * offset/sample.y + temp1;
3817 * temp1 = ddx * offset/sample.x + J;
3818 * interp_param.J = ddy * offset/sample.y + temp1;
3819 */
3820 for (unsigned i = 0; i < 2; i++) {
3821 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3822 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3823 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3824 ddxy_out, ix_ll, "");
3825 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3826 ddxy_out, iy_ll, "");
3827 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3828 interp_param, ix_ll, "");
3829 LLVMValueRef temp1, temp2;
3830
3831 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3832 ctx->f32, "");
3833
3834 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3835 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3836
3837 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3838 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3839
3840 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3841 temp2, ctx->i32, "");
3842 }
3843 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3844
3845 }
3846
3847 for (chan = 0; chan < 2; chan++) {
3848 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3849
3850 if (interp_param) {
3851 interp_param = LLVMBuildBitCast(ctx->builder,
3852 interp_param, LLVMVectorType(ctx->f32, 2), "");
3853 LLVMValueRef i = LLVMBuildExtractElement(
3854 ctx->builder, interp_param, ctx->i32zero, "");
3855 LLVMValueRef j = LLVMBuildExtractElement(
3856 ctx->builder, interp_param, ctx->i32one, "");
3857
3858 result[chan] = ac_build_fs_interp(&ctx->ac,
3859 llvm_chan, attr_number,
3860 ctx->prim_mask, i, j);
3861 } else {
3862 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3863 LLVMConstInt(ctx->i32, 2, false),
3864 llvm_chan, attr_number,
3865 ctx->prim_mask);
3866 }
3867 }
3868 return ac_build_gather_values(&ctx->ac, result, 2);
3869 }
3870
3871 static void
3872 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3873 const nir_intrinsic_instr *instr)
3874 {
3875 LLVMValueRef gs_next_vertex;
3876 LLVMValueRef can_emit, kill;
3877 int idx;
3878
3879 assert(instr->const_index[0] == 0);
3880 /* Write vertex attribute values to GSVS ring */
3881 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3882 ctx->gs_next_vertex,
3883 "");
3884
3885 /* If this thread has already emitted the declared maximum number of
3886 * vertices, kill it: excessive vertex emissions are not supposed to
3887 * have any effect, and GS threads have no externally observable
3888 * effects other than emitting vertices.
3889 */
3890 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3891 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3892
3893 kill = LLVMBuildSelect(ctx->builder, can_emit,
3894 LLVMConstReal(ctx->f32, 1.0f),
3895 LLVMConstReal(ctx->f32, -1.0f), "");
3896 ac_build_kill(&ctx->ac, kill);
3897
3898 /* loop num outputs */
3899 idx = 0;
3900 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3901 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3902 int length = 4;
3903 int slot = idx;
3904 int slot_inc = 1;
3905
3906 if (!(ctx->output_mask & (1ull << i)))
3907 continue;
3908
3909 if (i == VARYING_SLOT_CLIP_DIST0) {
3910 /* pack clip and cull into a single set of slots */
3911 length = ctx->num_output_clips + ctx->num_output_culls;
3912 if (length > 4)
3913 slot_inc = 2;
3914 }
3915 for (unsigned j = 0; j < length; j++) {
3916 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3917 out_ptr[j], "");
3918 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3919 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3920 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3921
3922 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3923
3924 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3925 out_val, 1,
3926 voffset, ctx->gs2vs_offset, 0,
3927 1, 1, true, true);
3928 }
3929 idx += slot_inc;
3930 }
3931
3932 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3933 ctx->i32one, "");
3934 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3935
3936 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3937 }
3938
3939 static void
3940 visit_end_primitive(struct nir_to_llvm_context *ctx,
3941 const nir_intrinsic_instr *instr)
3942 {
3943 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3944 }
3945
3946 static LLVMValueRef
3947 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3948 const nir_intrinsic_instr *instr)
3949 {
3950 LLVMValueRef coord[4] = {
3951 ctx->tes_u,
3952 ctx->tes_v,
3953 ctx->f32zero,
3954 ctx->f32zero,
3955 };
3956
3957 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3958 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3959 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3960
3961 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3962 return LLVMBuildBitCast(ctx->builder, result,
3963 get_def_type(ctx->nir, &instr->dest.ssa), "");
3964 }
3965
3966 static void visit_intrinsic(struct ac_nir_context *ctx,
3967 nir_intrinsic_instr *instr)
3968 {
3969 LLVMValueRef result = NULL;
3970
3971 switch (instr->intrinsic) {
3972 case nir_intrinsic_load_work_group_id: {
3973 result = ctx->nctx->workgroup_ids;
3974 break;
3975 }
3976 case nir_intrinsic_load_base_vertex: {
3977 result = ctx->abi->base_vertex;
3978 break;
3979 }
3980 case nir_intrinsic_load_vertex_id_zero_base: {
3981 result = ctx->abi->vertex_id;
3982 break;
3983 }
3984 case nir_intrinsic_load_local_invocation_id: {
3985 result = ctx->nctx->local_invocation_ids;
3986 break;
3987 }
3988 case nir_intrinsic_load_base_instance:
3989 result = ctx->abi->start_instance;
3990 break;
3991 case nir_intrinsic_load_draw_id:
3992 result = ctx->abi->draw_id;
3993 break;
3994 case nir_intrinsic_load_invocation_id:
3995 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3996 result = unpack_param(ctx->nctx, ctx->nctx->tcs_rel_ids, 8, 5);
3997 else
3998 result = ctx->nctx->gs_invocation_id;
3999 break;
4000 case nir_intrinsic_load_primitive_id:
4001 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4002 ctx->nctx->shader_info->gs.uses_prim_id = true;
4003 result = ctx->nctx->gs_prim_id;
4004 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4005 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4006 result = ctx->nctx->tcs_patch_id;
4007 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4008 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4009 result = ctx->nctx->tes_patch_id;
4010 } else
4011 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4012 break;
4013 case nir_intrinsic_load_sample_id:
4014 ctx->nctx->shader_info->fs.force_persample = true;
4015 result = unpack_param(ctx->nctx, ctx->nctx->ancillary, 8, 4);
4016 break;
4017 case nir_intrinsic_load_sample_pos:
4018 ctx->nctx->shader_info->fs.force_persample = true;
4019 result = load_sample_pos(ctx->nctx);
4020 break;
4021 case nir_intrinsic_load_sample_mask_in:
4022 result = ctx->nctx->sample_coverage;
4023 break;
4024 case nir_intrinsic_load_front_face:
4025 result = ctx->nctx->front_face;
4026 break;
4027 case nir_intrinsic_load_instance_id:
4028 result = ctx->abi->instance_id;
4029 break;
4030 case nir_intrinsic_load_num_work_groups:
4031 result = ctx->nctx->num_work_groups;
4032 break;
4033 case nir_intrinsic_load_local_invocation_index:
4034 result = visit_load_local_invocation_index(ctx->nctx);
4035 break;
4036 case nir_intrinsic_load_push_constant:
4037 result = visit_load_push_constant(ctx->nctx, instr);
4038 break;
4039 case nir_intrinsic_vulkan_resource_index:
4040 result = visit_vulkan_resource_index(ctx->nctx, instr);
4041 break;
4042 case nir_intrinsic_store_ssbo:
4043 visit_store_ssbo(ctx, instr);
4044 break;
4045 case nir_intrinsic_load_ssbo:
4046 result = visit_load_buffer(ctx, instr);
4047 break;
4048 case nir_intrinsic_ssbo_atomic_add:
4049 case nir_intrinsic_ssbo_atomic_imin:
4050 case nir_intrinsic_ssbo_atomic_umin:
4051 case nir_intrinsic_ssbo_atomic_imax:
4052 case nir_intrinsic_ssbo_atomic_umax:
4053 case nir_intrinsic_ssbo_atomic_and:
4054 case nir_intrinsic_ssbo_atomic_or:
4055 case nir_intrinsic_ssbo_atomic_xor:
4056 case nir_intrinsic_ssbo_atomic_exchange:
4057 case nir_intrinsic_ssbo_atomic_comp_swap:
4058 result = visit_atomic_ssbo(ctx, instr);
4059 break;
4060 case nir_intrinsic_load_ubo:
4061 result = visit_load_ubo_buffer(ctx, instr);
4062 break;
4063 case nir_intrinsic_get_buffer_size:
4064 result = visit_get_buffer_size(ctx, instr);
4065 break;
4066 case nir_intrinsic_load_var:
4067 result = visit_load_var(ctx, instr);
4068 break;
4069 case nir_intrinsic_store_var:
4070 visit_store_var(ctx, instr);
4071 break;
4072 case nir_intrinsic_image_load:
4073 result = visit_image_load(ctx, instr);
4074 break;
4075 case nir_intrinsic_image_store:
4076 visit_image_store(ctx, instr);
4077 break;
4078 case nir_intrinsic_image_atomic_add:
4079 case nir_intrinsic_image_atomic_min:
4080 case nir_intrinsic_image_atomic_max:
4081 case nir_intrinsic_image_atomic_and:
4082 case nir_intrinsic_image_atomic_or:
4083 case nir_intrinsic_image_atomic_xor:
4084 case nir_intrinsic_image_atomic_exchange:
4085 case nir_intrinsic_image_atomic_comp_swap:
4086 result = visit_image_atomic(ctx, instr);
4087 break;
4088 case nir_intrinsic_image_size:
4089 result = visit_image_size(ctx, instr);
4090 break;
4091 case nir_intrinsic_discard:
4092 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4093 LLVMVoidTypeInContext(ctx->ac.context),
4094 NULL, 0, AC_FUNC_ATTR_LEGACY);
4095 break;
4096 case nir_intrinsic_discard_if:
4097 emit_discard_if(ctx, instr);
4098 break;
4099 case nir_intrinsic_memory_barrier:
4100 emit_waitcnt(ctx->nctx, VM_CNT);
4101 break;
4102 case nir_intrinsic_barrier:
4103 emit_barrier(ctx->nctx);
4104 break;
4105 case nir_intrinsic_var_atomic_add:
4106 case nir_intrinsic_var_atomic_imin:
4107 case nir_intrinsic_var_atomic_umin:
4108 case nir_intrinsic_var_atomic_imax:
4109 case nir_intrinsic_var_atomic_umax:
4110 case nir_intrinsic_var_atomic_and:
4111 case nir_intrinsic_var_atomic_or:
4112 case nir_intrinsic_var_atomic_xor:
4113 case nir_intrinsic_var_atomic_exchange:
4114 case nir_intrinsic_var_atomic_comp_swap:
4115 result = visit_var_atomic(ctx->nctx, instr);
4116 break;
4117 case nir_intrinsic_interp_var_at_centroid:
4118 case nir_intrinsic_interp_var_at_sample:
4119 case nir_intrinsic_interp_var_at_offset:
4120 result = visit_interp(ctx->nctx, instr);
4121 break;
4122 case nir_intrinsic_emit_vertex:
4123 visit_emit_vertex(ctx->nctx, instr);
4124 break;
4125 case nir_intrinsic_end_primitive:
4126 visit_end_primitive(ctx->nctx, instr);
4127 break;
4128 case nir_intrinsic_load_tess_coord:
4129 result = visit_load_tess_coord(ctx->nctx, instr);
4130 break;
4131 case nir_intrinsic_load_patch_vertices_in:
4132 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4133 break;
4134 default:
4135 fprintf(stderr, "Unknown intrinsic: ");
4136 nir_print_instr(&instr->instr, stderr);
4137 fprintf(stderr, "\n");
4138 break;
4139 }
4140 if (result) {
4141 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4142 }
4143 }
4144
4145 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4146 LLVMValueRef buffer, bool write)
4147 {
4148 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4149
4150 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4151 ctx->shader_info->fs.writes_memory = true;
4152
4153 return buffer;
4154 }
4155
4156 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4157 unsigned descriptor_set,
4158 unsigned base_index,
4159 unsigned constant_index,
4160 LLVMValueRef index,
4161 enum ac_descriptor_type desc_type,
4162 bool image, bool write)
4163 {
4164 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4165 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4166 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4167 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4168 unsigned offset = binding->offset;
4169 unsigned stride = binding->size;
4170 unsigned type_size;
4171 LLVMBuilderRef builder = ctx->builder;
4172 LLVMTypeRef type;
4173
4174 assert(base_index < layout->binding_count);
4175
4176 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4177 ctx->shader_info->fs.writes_memory = true;
4178
4179 switch (desc_type) {
4180 case AC_DESC_IMAGE:
4181 type = ctx->v8i32;
4182 type_size = 32;
4183 break;
4184 case AC_DESC_FMASK:
4185 type = ctx->v8i32;
4186 offset += 32;
4187 type_size = 32;
4188 break;
4189 case AC_DESC_SAMPLER:
4190 type = ctx->v4i32;
4191 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4192 offset += 64;
4193
4194 type_size = 16;
4195 break;
4196 case AC_DESC_BUFFER:
4197 type = ctx->v4i32;
4198 type_size = 16;
4199 break;
4200 default:
4201 unreachable("invalid desc_type\n");
4202 }
4203
4204 offset += constant_index * stride;
4205
4206 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4207 (!index || binding->immutable_samplers_equal)) {
4208 if (binding->immutable_samplers_equal)
4209 constant_index = 0;
4210
4211 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4212
4213 LLVMValueRef constants[] = {
4214 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4215 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4216 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4217 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4218 };
4219 return ac_build_gather_values(&ctx->ac, constants, 4);
4220 }
4221
4222 assert(stride % type_size == 0);
4223
4224 if (!index)
4225 index = ctx->i32zero;
4226
4227 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4228
4229 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4230 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4231
4232 return ac_build_indexed_load_const(&ctx->ac, list, index);
4233 }
4234
4235 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4236 const nir_deref_var *deref,
4237 enum ac_descriptor_type desc_type,
4238 bool image, bool write)
4239 {
4240 LLVMValueRef index = NULL;
4241 unsigned constant_index = 0;
4242 const nir_deref *tail = &deref->deref;
4243
4244 while (tail->child) {
4245 const nir_deref_array *child = nir_deref_as_array(tail->child);
4246 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4247
4248 if (!array_size)
4249 array_size = 1;
4250
4251 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4252
4253 if (child->deref_array_type == nir_deref_array_type_indirect) {
4254 LLVMValueRef indirect = get_src(ctx, child->indirect);
4255
4256 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4257 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4258
4259 if (!index)
4260 index = indirect;
4261 else
4262 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4263 }
4264
4265 constant_index += child->base_offset * array_size;
4266
4267 tail = &child->deref;
4268 }
4269
4270 return ctx->abi->load_sampler_desc(ctx->abi,
4271 deref->var->data.descriptor_set,
4272 deref->var->data.binding,
4273 constant_index, index,
4274 desc_type, image, write);
4275 }
4276
4277 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4278 struct ac_image_args *args,
4279 const nir_tex_instr *instr,
4280 nir_texop op,
4281 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4282 LLVMValueRef *param, unsigned count,
4283 unsigned dmask)
4284 {
4285 unsigned is_rect = 0;
4286 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4287
4288 if (op == nir_texop_lod)
4289 da = false;
4290 /* Pad to power of two vector */
4291 while (count < util_next_power_of_two(count))
4292 param[count++] = LLVMGetUndef(ctx->i32);
4293
4294 if (count > 1)
4295 args->addr = ac_build_gather_values(ctx, param, count);
4296 else
4297 args->addr = param[0];
4298
4299 args->resource = res_ptr;
4300 args->sampler = samp_ptr;
4301
4302 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4303 args->addr = param[0];
4304 return;
4305 }
4306
4307 args->dmask = dmask;
4308 args->unorm = is_rect;
4309 args->da = da;
4310 }
4311
4312 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4313 *
4314 * SI-CI:
4315 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4316 * filtering manually. The driver sets img7 to a mask clearing
4317 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4318 * s_and_b32 samp0, samp0, img7
4319 *
4320 * VI:
4321 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4322 */
4323 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4324 LLVMValueRef res, LLVMValueRef samp)
4325 {
4326 LLVMBuilderRef builder = ctx->ac.builder;
4327 LLVMValueRef img7, samp0;
4328
4329 if (ctx->abi->chip_class >= VI)
4330 return samp;
4331
4332 img7 = LLVMBuildExtractElement(builder, res,
4333 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4334 samp0 = LLVMBuildExtractElement(builder, samp,
4335 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4336 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4337 return LLVMBuildInsertElement(builder, samp, samp0,
4338 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4339 }
4340
4341 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4342 nir_tex_instr *instr,
4343 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4344 LLVMValueRef *fmask_ptr)
4345 {
4346 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4347 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4348 else
4349 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4350 if (samp_ptr) {
4351 if (instr->sampler)
4352 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4353 else
4354 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4355 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4356 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4357 }
4358 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4359 instr->op == nir_texop_samples_identical))
4360 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4361 }
4362
4363 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4364 LLVMValueRef coord)
4365 {
4366 coord = to_float(ctx, coord);
4367 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4368 coord = to_integer(ctx, coord);
4369 return coord;
4370 }
4371
4372 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4373 {
4374 LLVMValueRef result = NULL;
4375 struct ac_image_args args = { 0 };
4376 unsigned dmask = 0xf;
4377 LLVMValueRef address[16];
4378 LLVMValueRef coords[5];
4379 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4380 LLVMValueRef bias = NULL, offsets = NULL;
4381 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4382 LLVMValueRef ddx = NULL, ddy = NULL;
4383 LLVMValueRef derivs[6];
4384 unsigned chan, count = 0;
4385 unsigned const_src = 0, num_deriv_comp = 0;
4386 bool lod_is_zero = false;
4387
4388 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4389
4390 for (unsigned i = 0; i < instr->num_srcs; i++) {
4391 switch (instr->src[i].src_type) {
4392 case nir_tex_src_coord:
4393 coord = get_src(ctx, instr->src[i].src);
4394 break;
4395 case nir_tex_src_projector:
4396 break;
4397 case nir_tex_src_comparator:
4398 comparator = get_src(ctx, instr->src[i].src);
4399 break;
4400 case nir_tex_src_offset:
4401 offsets = get_src(ctx, instr->src[i].src);
4402 const_src = i;
4403 break;
4404 case nir_tex_src_bias:
4405 bias = get_src(ctx, instr->src[i].src);
4406 break;
4407 case nir_tex_src_lod: {
4408 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4409
4410 if (val && val->i32[0] == 0)
4411 lod_is_zero = true;
4412 lod = get_src(ctx, instr->src[i].src);
4413 break;
4414 }
4415 case nir_tex_src_ms_index:
4416 sample_index = get_src(ctx, instr->src[i].src);
4417 break;
4418 case nir_tex_src_ms_mcs:
4419 break;
4420 case nir_tex_src_ddx:
4421 ddx = get_src(ctx, instr->src[i].src);
4422 num_deriv_comp = instr->src[i].src.ssa->num_components;
4423 break;
4424 case nir_tex_src_ddy:
4425 ddy = get_src(ctx, instr->src[i].src);
4426 break;
4427 case nir_tex_src_texture_offset:
4428 case nir_tex_src_sampler_offset:
4429 case nir_tex_src_plane:
4430 default:
4431 break;
4432 }
4433 }
4434
4435 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4436 result = get_buffer_size(ctx, res_ptr, true);
4437 goto write_result;
4438 }
4439
4440 if (instr->op == nir_texop_texture_samples) {
4441 LLVMValueRef res, samples, is_msaa;
4442 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4443 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4444 LLVMConstInt(ctx->ac.i32, 3, false), "");
4445 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4446 LLVMConstInt(ctx->ac.i32, 28, false), "");
4447 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4448 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4449 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4450 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4451
4452 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4453 LLVMConstInt(ctx->ac.i32, 16, false), "");
4454 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4455 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4456 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4457 samples, "");
4458 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4459 ctx->ac.i32_1, "");
4460 result = samples;
4461 goto write_result;
4462 }
4463
4464 if (coord)
4465 for (chan = 0; chan < instr->coord_components; chan++)
4466 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4467
4468 if (offsets && instr->op != nir_texop_txf) {
4469 LLVMValueRef offset[3], pack;
4470 for (chan = 0; chan < 3; ++chan)
4471 offset[chan] = ctx->ac.i32_0;
4472
4473 args.offset = true;
4474 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4475 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4476 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4477 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4478 if (chan)
4479 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4480 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4481 }
4482 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4483 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4484 address[count++] = pack;
4485
4486 }
4487 /* pack LOD bias value */
4488 if (instr->op == nir_texop_txb && bias) {
4489 address[count++] = bias;
4490 }
4491
4492 /* Pack depth comparison value */
4493 if (instr->is_shadow && comparator) {
4494 address[count++] = llvm_extract_elem(&ctx->ac, comparator, 0);
4495 }
4496
4497 /* pack derivatives */
4498 if (ddx || ddy) {
4499 switch (instr->sampler_dim) {
4500 case GLSL_SAMPLER_DIM_3D:
4501 case GLSL_SAMPLER_DIM_CUBE:
4502 num_deriv_comp = 3;
4503 break;
4504 case GLSL_SAMPLER_DIM_2D:
4505 default:
4506 num_deriv_comp = 2;
4507 break;
4508 case GLSL_SAMPLER_DIM_1D:
4509 num_deriv_comp = 1;
4510 break;
4511 }
4512
4513 for (unsigned i = 0; i < num_deriv_comp; i++) {
4514 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4515 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4516 }
4517 }
4518
4519 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4520 if (instr->is_array && instr->op != nir_texop_lod)
4521 coords[3] = apply_round_slice(&ctx->ac, coords[3]);
4522 for (chan = 0; chan < instr->coord_components; chan++)
4523 coords[chan] = to_float(&ctx->ac, coords[chan]);
4524 if (instr->coord_components == 3)
4525 coords[3] = LLVMGetUndef(ctx->ac.f32);
4526 ac_prepare_cube_coords(&ctx->ac,
4527 instr->op == nir_texop_txd, instr->is_array,
4528 coords, derivs);
4529 if (num_deriv_comp)
4530 num_deriv_comp--;
4531 }
4532
4533 if (ddx || ddy) {
4534 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4535 address[count++] = derivs[i];
4536 }
4537
4538 /* Pack texture coordinates */
4539 if (coord) {
4540 address[count++] = coords[0];
4541 if (instr->coord_components > 1) {
4542 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4543 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4544 }
4545 address[count++] = coords[1];
4546 }
4547 if (instr->coord_components > 2) {
4548 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4549 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4550 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4551 instr->op != nir_texop_txf) {
4552 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4553 }
4554 address[count++] = coords[2];
4555 }
4556 }
4557
4558 /* Pack LOD */
4559 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4560 instr->op == nir_texop_txf)) {
4561 address[count++] = lod;
4562 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4563 address[count++] = sample_index;
4564 } else if(instr->op == nir_texop_txs) {
4565 count = 0;
4566 if (lod)
4567 address[count++] = lod;
4568 else
4569 address[count++] = ctx->ac.i32_0;
4570 }
4571
4572 for (chan = 0; chan < count; chan++) {
4573 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4574 address[chan], ctx->ac.i32, "");
4575 }
4576
4577 if (instr->op == nir_texop_samples_identical) {
4578 LLVMValueRef txf_address[4];
4579 struct ac_image_args txf_args = { 0 };
4580 unsigned txf_count = count;
4581 memcpy(txf_address, address, sizeof(txf_address));
4582
4583 if (!instr->is_array)
4584 txf_address[2] = ctx->ac.i32_0;
4585 txf_address[3] = ctx->ac.i32_0;
4586
4587 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4588 fmask_ptr, NULL,
4589 txf_address, txf_count, 0xf);
4590
4591 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4592
4593 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4594 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4595 goto write_result;
4596 }
4597
4598 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4599 instr->op != nir_texop_txs) {
4600 unsigned sample_chan = instr->is_array ? 3 : 2;
4601 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4602 address[0],
4603 address[1],
4604 instr->is_array ? address[2] : NULL,
4605 address[sample_chan],
4606 fmask_ptr);
4607 }
4608
4609 if (offsets && instr->op == nir_texop_txf) {
4610 nir_const_value *const_offset =
4611 nir_src_as_const_value(instr->src[const_src].src);
4612 int num_offsets = instr->src[const_src].src.ssa->num_components;
4613 assert(const_offset);
4614 num_offsets = MIN2(num_offsets, instr->coord_components);
4615 if (num_offsets > 2)
4616 address[2] = LLVMBuildAdd(ctx->ac.builder,
4617 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4618 if (num_offsets > 1)
4619 address[1] = LLVMBuildAdd(ctx->ac.builder,
4620 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4621 address[0] = LLVMBuildAdd(ctx->ac.builder,
4622 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4623
4624 }
4625
4626 /* TODO TG4 support */
4627 if (instr->op == nir_texop_tg4) {
4628 if (instr->is_shadow)
4629 dmask = 1;
4630 else
4631 dmask = 1 << instr->component;
4632 }
4633 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4634 res_ptr, samp_ptr, address, count, dmask);
4635
4636 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4637
4638 if (instr->op == nir_texop_query_levels)
4639 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4640 else if (instr->is_shadow && instr->is_new_style_shadow &&
4641 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4642 instr->op != nir_texop_tg4)
4643 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4644 else if (instr->op == nir_texop_txs &&
4645 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4646 instr->is_array) {
4647 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4648 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4649 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4650 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4651 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4652 } else if (instr->dest.ssa.num_components != 4)
4653 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4654
4655 write_result:
4656 if (result) {
4657 assert(instr->dest.is_ssa);
4658 result = to_integer(&ctx->ac, result);
4659 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4660 }
4661 }
4662
4663
4664 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4665 {
4666 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4667 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4668
4669 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4670 _mesa_hash_table_insert(ctx->phis, instr, result);
4671 }
4672
4673 static void visit_post_phi(struct ac_nir_context *ctx,
4674 nir_phi_instr *instr,
4675 LLVMValueRef llvm_phi)
4676 {
4677 nir_foreach_phi_src(src, instr) {
4678 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4679 LLVMValueRef llvm_src = get_src(ctx, src->src);
4680
4681 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4682 }
4683 }
4684
4685 static void phi_post_pass(struct ac_nir_context *ctx)
4686 {
4687 struct hash_entry *entry;
4688 hash_table_foreach(ctx->phis, entry) {
4689 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4690 (LLVMValueRef)entry->data);
4691 }
4692 }
4693
4694
4695 static void visit_ssa_undef(struct ac_nir_context *ctx,
4696 const nir_ssa_undef_instr *instr)
4697 {
4698 unsigned num_components = instr->def.num_components;
4699 LLVMValueRef undef;
4700
4701 if (num_components == 1)
4702 undef = LLVMGetUndef(ctx->ac.i32);
4703 else {
4704 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4705 }
4706 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4707 }
4708
4709 static void visit_jump(struct ac_nir_context *ctx,
4710 const nir_jump_instr *instr)
4711 {
4712 switch (instr->type) {
4713 case nir_jump_break:
4714 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4715 LLVMClearInsertionPosition(ctx->ac.builder);
4716 break;
4717 case nir_jump_continue:
4718 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4719 LLVMClearInsertionPosition(ctx->ac.builder);
4720 break;
4721 default:
4722 fprintf(stderr, "Unknown NIR jump instr: ");
4723 nir_print_instr(&instr->instr, stderr);
4724 fprintf(stderr, "\n");
4725 abort();
4726 }
4727 }
4728
4729 static void visit_cf_list(struct ac_nir_context *ctx,
4730 struct exec_list *list);
4731
4732 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4733 {
4734 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4735 nir_foreach_instr(instr, block)
4736 {
4737 switch (instr->type) {
4738 case nir_instr_type_alu:
4739 visit_alu(ctx, nir_instr_as_alu(instr));
4740 break;
4741 case nir_instr_type_load_const:
4742 visit_load_const(ctx, nir_instr_as_load_const(instr));
4743 break;
4744 case nir_instr_type_intrinsic:
4745 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4746 break;
4747 case nir_instr_type_tex:
4748 visit_tex(ctx, nir_instr_as_tex(instr));
4749 break;
4750 case nir_instr_type_phi:
4751 visit_phi(ctx, nir_instr_as_phi(instr));
4752 break;
4753 case nir_instr_type_ssa_undef:
4754 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4755 break;
4756 case nir_instr_type_jump:
4757 visit_jump(ctx, nir_instr_as_jump(instr));
4758 break;
4759 default:
4760 fprintf(stderr, "Unknown NIR instr type: ");
4761 nir_print_instr(instr, stderr);
4762 fprintf(stderr, "\n");
4763 abort();
4764 }
4765 }
4766
4767 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4768 }
4769
4770 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4771 {
4772 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4773
4774 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4775 LLVMBasicBlockRef merge_block =
4776 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4777 LLVMBasicBlockRef if_block =
4778 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4779 LLVMBasicBlockRef else_block = merge_block;
4780 if (!exec_list_is_empty(&if_stmt->else_list))
4781 else_block = LLVMAppendBasicBlockInContext(
4782 ctx->ac.context, fn, "");
4783
4784 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4785 LLVMConstInt(ctx->ac.i32, 0, false), "");
4786 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4787
4788 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4789 visit_cf_list(ctx, &if_stmt->then_list);
4790 if (LLVMGetInsertBlock(ctx->ac.builder))
4791 LLVMBuildBr(ctx->ac.builder, merge_block);
4792
4793 if (!exec_list_is_empty(&if_stmt->else_list)) {
4794 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4795 visit_cf_list(ctx, &if_stmt->else_list);
4796 if (LLVMGetInsertBlock(ctx->ac.builder))
4797 LLVMBuildBr(ctx->ac.builder, merge_block);
4798 }
4799
4800 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4801 }
4802
4803 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4804 {
4805 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4806 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4807 LLVMBasicBlockRef break_parent = ctx->break_block;
4808
4809 ctx->continue_block =
4810 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4811 ctx->break_block =
4812 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4813
4814 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4815 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4816 visit_cf_list(ctx, &loop->body);
4817
4818 if (LLVMGetInsertBlock(ctx->ac.builder))
4819 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4820 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4821
4822 ctx->continue_block = continue_parent;
4823 ctx->break_block = break_parent;
4824 }
4825
4826 static void visit_cf_list(struct ac_nir_context *ctx,
4827 struct exec_list *list)
4828 {
4829 foreach_list_typed(nir_cf_node, node, node, list)
4830 {
4831 switch (node->type) {
4832 case nir_cf_node_block:
4833 visit_block(ctx, nir_cf_node_as_block(node));
4834 break;
4835
4836 case nir_cf_node_if:
4837 visit_if(ctx, nir_cf_node_as_if(node));
4838 break;
4839
4840 case nir_cf_node_loop:
4841 visit_loop(ctx, nir_cf_node_as_loop(node));
4842 break;
4843
4844 default:
4845 assert(0);
4846 }
4847 }
4848 }
4849
4850 static void
4851 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4852 struct nir_variable *variable)
4853 {
4854 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4855 LLVMValueRef t_offset;
4856 LLVMValueRef t_list;
4857 LLVMValueRef input;
4858 LLVMValueRef buffer_index;
4859 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4860 int idx = variable->data.location;
4861 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4862
4863 variable->data.driver_location = idx * 4;
4864
4865 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4866 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4867 ctx->abi.start_instance, "");
4868 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4869 ctx->shader_info->vs.vgpr_comp_cnt);
4870 } else
4871 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4872 ctx->abi.base_vertex, "");
4873
4874 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4875 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4876
4877 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4878
4879 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4880 buffer_index,
4881 LLVMConstInt(ctx->i32, 0, false),
4882 true);
4883
4884 for (unsigned chan = 0; chan < 4; chan++) {
4885 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4886 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4887 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4888 input, llvm_chan, ""));
4889 }
4890 }
4891 }
4892
4893 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4894 unsigned attr,
4895 LLVMValueRef interp_param,
4896 LLVMValueRef prim_mask,
4897 LLVMValueRef result[4])
4898 {
4899 LLVMValueRef attr_number;
4900 unsigned chan;
4901 LLVMValueRef i, j;
4902 bool interp = interp_param != NULL;
4903
4904 attr_number = LLVMConstInt(ctx->i32, attr, false);
4905
4906 /* fs.constant returns the param from the middle vertex, so it's not
4907 * really useful for flat shading. It's meant to be used for custom
4908 * interpolation (but the intrinsic can't fetch from the other two
4909 * vertices).
4910 *
4911 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4912 * to do the right thing. The only reason we use fs.constant is that
4913 * fs.interp cannot be used on integers, because they can be equal
4914 * to NaN.
4915 */
4916 if (interp) {
4917 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4918 LLVMVectorType(ctx->f32, 2), "");
4919
4920 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4921 ctx->i32zero, "");
4922 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4923 ctx->i32one, "");
4924 }
4925
4926 for (chan = 0; chan < 4; chan++) {
4927 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4928
4929 if (interp) {
4930 result[chan] = ac_build_fs_interp(&ctx->ac,
4931 llvm_chan,
4932 attr_number,
4933 prim_mask, i, j);
4934 } else {
4935 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4936 LLVMConstInt(ctx->i32, 2, false),
4937 llvm_chan,
4938 attr_number,
4939 prim_mask);
4940 }
4941 }
4942 }
4943
4944 static void
4945 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4946 struct nir_variable *variable)
4947 {
4948 int idx = variable->data.location;
4949 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4950 LLVMValueRef interp;
4951
4952 variable->data.driver_location = idx * 4;
4953 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4954
4955 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4956 unsigned interp_type;
4957 if (variable->data.sample) {
4958 interp_type = INTERP_SAMPLE;
4959 ctx->shader_info->fs.force_persample = true;
4960 } else if (variable->data.centroid)
4961 interp_type = INTERP_CENTROID;
4962 else
4963 interp_type = INTERP_CENTER;
4964
4965 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4966 } else
4967 interp = NULL;
4968
4969 for (unsigned i = 0; i < attrib_count; ++i)
4970 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4971
4972 }
4973
4974 static void
4975 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4976 struct nir_variable *variable)
4977 {
4978 switch (ctx->stage) {
4979 case MESA_SHADER_VERTEX:
4980 handle_vs_input_decl(ctx, variable);
4981 break;
4982 case MESA_SHADER_FRAGMENT:
4983 handle_fs_input_decl(ctx, variable);
4984 break;
4985 default:
4986 break;
4987 }
4988
4989 }
4990
4991 static void
4992 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4993 struct nir_shader *nir)
4994 {
4995 unsigned index = 0;
4996 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4997 LLVMValueRef interp_param;
4998 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4999
5000 if (!(ctx->input_mask & (1ull << i)))
5001 continue;
5002
5003 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5004 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5005 interp_param = *inputs;
5006 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5007 inputs);
5008
5009 if (!interp_param)
5010 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5011 ++index;
5012 } else if (i == VARYING_SLOT_POS) {
5013 for(int i = 0; i < 3; ++i)
5014 inputs[i] = ctx->frag_pos[i];
5015
5016 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
5017 }
5018 }
5019 ctx->shader_info->fs.num_interp = index;
5020 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5021 ctx->shader_info->fs.has_pcoord = true;
5022 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5023 ctx->shader_info->fs.prim_id_input = true;
5024 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5025 ctx->shader_info->fs.layer_input = true;
5026 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5027 }
5028
5029 static LLVMValueRef
5030 ac_build_alloca(struct ac_llvm_context *ac,
5031 LLVMTypeRef type,
5032 const char *name)
5033 {
5034 LLVMBuilderRef builder = ac->builder;
5035 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5036 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5037 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5038 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5039 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5040 LLVMValueRef res;
5041
5042 if (first_instr) {
5043 LLVMPositionBuilderBefore(first_builder, first_instr);
5044 } else {
5045 LLVMPositionBuilderAtEnd(first_builder, first_block);
5046 }
5047
5048 res = LLVMBuildAlloca(first_builder, type, name);
5049 LLVMBuildStore(builder, LLVMConstNull(type), res);
5050
5051 LLVMDisposeBuilder(first_builder);
5052
5053 return res;
5054 }
5055
5056 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5057 LLVMTypeRef type,
5058 const char *name)
5059 {
5060 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5061 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5062 return ptr;
5063 }
5064
5065 static void
5066 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5067 struct nir_variable *variable)
5068 {
5069 int idx = variable->data.location + variable->data.index;
5070 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5071 uint64_t mask_attribs;
5072
5073 variable->data.driver_location = idx * 4;
5074
5075 /* tess ctrl has it's own load/store paths for outputs */
5076 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5077 return;
5078
5079 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5080 if (ctx->stage == MESA_SHADER_VERTEX ||
5081 ctx->stage == MESA_SHADER_TESS_EVAL ||
5082 ctx->stage == MESA_SHADER_GEOMETRY) {
5083 if (idx == VARYING_SLOT_CLIP_DIST0) {
5084 int length = ctx->num_output_clips + ctx->num_output_culls;
5085 if (ctx->stage == MESA_SHADER_VERTEX) {
5086 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5087 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5088 }
5089 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5090 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5091 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5092 }
5093
5094 if (length > 4)
5095 attrib_count = 2;
5096 else
5097 attrib_count = 1;
5098 mask_attribs = 1ull << idx;
5099 }
5100 }
5101
5102 ctx->output_mask |= mask_attribs;
5103 }
5104
5105 static void
5106 handle_shader_output_decl(struct ac_nir_context *ctx,
5107 struct nir_shader *nir,
5108 struct nir_variable *variable)
5109 {
5110 unsigned output_loc = variable->data.driver_location / 4;
5111 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5112
5113 /* tess ctrl has it's own load/store paths for outputs */
5114 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5115 return;
5116
5117 if (ctx->stage == MESA_SHADER_VERTEX ||
5118 ctx->stage == MESA_SHADER_TESS_EVAL ||
5119 ctx->stage == MESA_SHADER_GEOMETRY) {
5120 int idx = variable->data.location + variable->data.index;
5121 if (idx == VARYING_SLOT_CLIP_DIST0) {
5122 int length = nir->info.clip_distance_array_size +
5123 nir->info.cull_distance_array_size;
5124
5125 if (length > 4)
5126 attrib_count = 2;
5127 else
5128 attrib_count = 1;
5129 }
5130 }
5131
5132 for (unsigned i = 0; i < attrib_count; ++i) {
5133 for (unsigned chan = 0; chan < 4; chan++) {
5134 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5135 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5136 }
5137 }
5138 }
5139
5140 static LLVMTypeRef
5141 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5142 enum glsl_base_type type)
5143 {
5144 switch (type) {
5145 case GLSL_TYPE_INT:
5146 case GLSL_TYPE_UINT:
5147 case GLSL_TYPE_BOOL:
5148 case GLSL_TYPE_SUBROUTINE:
5149 return ctx->i32;
5150 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5151 return ctx->f32;
5152 case GLSL_TYPE_INT64:
5153 case GLSL_TYPE_UINT64:
5154 return ctx->i64;
5155 case GLSL_TYPE_DOUBLE:
5156 return ctx->f64;
5157 default:
5158 unreachable("unknown GLSL type");
5159 }
5160 }
5161
5162 static LLVMTypeRef
5163 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5164 const struct glsl_type *type)
5165 {
5166 if (glsl_type_is_scalar(type)) {
5167 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5168 }
5169
5170 if (glsl_type_is_vector(type)) {
5171 return LLVMVectorType(
5172 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5173 glsl_get_vector_elements(type));
5174 }
5175
5176 if (glsl_type_is_matrix(type)) {
5177 return LLVMArrayType(
5178 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5179 glsl_get_matrix_columns(type));
5180 }
5181
5182 if (glsl_type_is_array(type)) {
5183 return LLVMArrayType(
5184 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5185 glsl_get_length(type));
5186 }
5187
5188 assert(glsl_type_is_struct(type));
5189
5190 LLVMTypeRef member_types[glsl_get_length(type)];
5191
5192 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5193 member_types[i] =
5194 glsl_to_llvm_type(ctx,
5195 glsl_get_struct_field(type, i));
5196 }
5197
5198 return LLVMStructTypeInContext(ctx->context, member_types,
5199 glsl_get_length(type), false);
5200 }
5201
5202 static void
5203 setup_locals(struct ac_nir_context *ctx,
5204 struct nir_function *func)
5205 {
5206 int i, j;
5207 ctx->num_locals = 0;
5208 nir_foreach_variable(variable, &func->impl->locals) {
5209 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5210 variable->data.driver_location = ctx->num_locals * 4;
5211 ctx->num_locals += attrib_count;
5212 }
5213 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5214 if (!ctx->locals)
5215 return;
5216
5217 for (i = 0; i < ctx->num_locals; i++) {
5218 for (j = 0; j < 4; j++) {
5219 ctx->locals[i * 4 + j] =
5220 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5221 }
5222 }
5223 }
5224
5225 static void
5226 setup_shared(struct ac_nir_context *ctx,
5227 struct nir_shader *nir)
5228 {
5229 nir_foreach_variable(variable, &nir->shared) {
5230 LLVMValueRef shared =
5231 LLVMAddGlobalInAddressSpace(
5232 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5233 variable->name ? variable->name : "",
5234 LOCAL_ADDR_SPACE);
5235 _mesa_hash_table_insert(ctx->vars, variable, shared);
5236 }
5237 }
5238
5239 static LLVMValueRef
5240 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5241 {
5242 v = to_float(ctx, v);
5243 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5244 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5245 }
5246
5247
5248 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5249 LLVMValueRef src0, LLVMValueRef src1)
5250 {
5251 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5252 LLVMValueRef comp[2];
5253
5254 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5255 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5256 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5257 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5258 }
5259
5260 /* Initialize arguments for the shader export intrinsic */
5261 static void
5262 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5263 LLVMValueRef *values,
5264 unsigned target,
5265 struct ac_export_args *args)
5266 {
5267 /* Default is 0xf. Adjusted below depending on the format. */
5268 args->enabled_channels = 0xf;
5269
5270 /* Specify whether the EXEC mask represents the valid mask */
5271 args->valid_mask = 0;
5272
5273 /* Specify whether this is the last export */
5274 args->done = 0;
5275
5276 /* Specify the target we are exporting */
5277 args->target = target;
5278
5279 args->compr = false;
5280 args->out[0] = LLVMGetUndef(ctx->f32);
5281 args->out[1] = LLVMGetUndef(ctx->f32);
5282 args->out[2] = LLVMGetUndef(ctx->f32);
5283 args->out[3] = LLVMGetUndef(ctx->f32);
5284
5285 if (!values)
5286 return;
5287
5288 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5289 LLVMValueRef val[4];
5290 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5291 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5292 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5293
5294 switch(col_format) {
5295 case V_028714_SPI_SHADER_ZERO:
5296 args->enabled_channels = 0; /* writemask */
5297 args->target = V_008DFC_SQ_EXP_NULL;
5298 break;
5299
5300 case V_028714_SPI_SHADER_32_R:
5301 args->enabled_channels = 1;
5302 args->out[0] = values[0];
5303 break;
5304
5305 case V_028714_SPI_SHADER_32_GR:
5306 args->enabled_channels = 0x3;
5307 args->out[0] = values[0];
5308 args->out[1] = values[1];
5309 break;
5310
5311 case V_028714_SPI_SHADER_32_AR:
5312 args->enabled_channels = 0x9;
5313 args->out[0] = values[0];
5314 args->out[3] = values[3];
5315 break;
5316
5317 case V_028714_SPI_SHADER_FP16_ABGR:
5318 args->compr = 1;
5319
5320 for (unsigned chan = 0; chan < 2; chan++) {
5321 LLVMValueRef pack_args[2] = {
5322 values[2 * chan],
5323 values[2 * chan + 1]
5324 };
5325 LLVMValueRef packed;
5326
5327 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5328 args->out[chan] = packed;
5329 }
5330 break;
5331
5332 case V_028714_SPI_SHADER_UNORM16_ABGR:
5333 for (unsigned chan = 0; chan < 4; chan++) {
5334 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5335 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5336 LLVMConstReal(ctx->f32, 65535), "");
5337 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5338 LLVMConstReal(ctx->f32, 0.5), "");
5339 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5340 ctx->i32, "");
5341 }
5342
5343 args->compr = 1;
5344 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5345 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5346 break;
5347
5348 case V_028714_SPI_SHADER_SNORM16_ABGR:
5349 for (unsigned chan = 0; chan < 4; chan++) {
5350 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5351 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5352 LLVMConstReal(ctx->f32, 32767), "");
5353
5354 /* If positive, add 0.5, else add -0.5. */
5355 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5356 LLVMBuildSelect(ctx->builder,
5357 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5358 val[chan], ctx->f32zero, ""),
5359 LLVMConstReal(ctx->f32, 0.5),
5360 LLVMConstReal(ctx->f32, -0.5), ""), "");
5361 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5362 }
5363
5364 args->compr = 1;
5365 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5366 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5367 break;
5368
5369 case V_028714_SPI_SHADER_UINT16_ABGR: {
5370 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5371
5372 for (unsigned chan = 0; chan < 4; chan++) {
5373 val[chan] = to_integer(&ctx->ac, values[chan]);
5374 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], max);
5375 }
5376
5377 args->compr = 1;
5378 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5379 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5380 break;
5381 }
5382
5383 case V_028714_SPI_SHADER_SINT16_ABGR: {
5384 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5385 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5386
5387 /* Clamp. */
5388 for (unsigned chan = 0; chan < 4; chan++) {
5389 val[chan] = to_integer(&ctx->ac, values[chan]);
5390 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], max);
5391 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], min);
5392 }
5393
5394 args->compr = 1;
5395 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5396 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5397 break;
5398 }
5399
5400 default:
5401 case V_028714_SPI_SHADER_32_ABGR:
5402 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5403 break;
5404 }
5405 } else
5406 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5407
5408 for (unsigned i = 0; i < 4; ++i)
5409 args->out[i] = to_float(&ctx->ac, args->out[i]);
5410 }
5411
5412 static void
5413 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5414 bool export_prim_id,
5415 struct ac_vs_output_info *outinfo)
5416 {
5417 uint32_t param_count = 0;
5418 unsigned target;
5419 unsigned pos_idx, num_pos_exports = 0;
5420 struct ac_export_args args, pos_args[4] = {};
5421 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5422 int i;
5423
5424 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5425 sizeof(outinfo->vs_output_param_offset));
5426
5427 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5428 LLVMValueRef slots[8];
5429 unsigned j;
5430
5431 if (outinfo->cull_dist_mask)
5432 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5433
5434 i = VARYING_SLOT_CLIP_DIST0;
5435 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5436 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5437 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5438
5439 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5440 slots[i] = LLVMGetUndef(ctx->f32);
5441
5442 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5443 target = V_008DFC_SQ_EXP_POS + 3;
5444 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5445 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5446 &args, sizeof(args));
5447 }
5448
5449 target = V_008DFC_SQ_EXP_POS + 2;
5450 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5451 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5452 &args, sizeof(args));
5453
5454 }
5455
5456 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5457 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5458 for (unsigned j = 0; j < 4; j++)
5459 pos_values[j] = LLVMBuildLoad(ctx->builder,
5460 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5461 }
5462 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5463
5464 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5465 outinfo->writes_pointsize = true;
5466 psize_value = LLVMBuildLoad(ctx->builder,
5467 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5468 }
5469
5470 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5471 outinfo->writes_layer = true;
5472 layer_value = LLVMBuildLoad(ctx->builder,
5473 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5474 }
5475
5476 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5477 outinfo->writes_viewport_index = true;
5478 viewport_index_value = LLVMBuildLoad(ctx->builder,
5479 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5480 }
5481
5482 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5483 (outinfo->writes_layer == true ? 4 : 0) |
5484 (outinfo->writes_viewport_index == true ? 8 : 0));
5485 if (mask) {
5486 pos_args[1].enabled_channels = mask;
5487 pos_args[1].valid_mask = 0;
5488 pos_args[1].done = 0;
5489 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5490 pos_args[1].compr = 0;
5491 pos_args[1].out[0] = ctx->f32zero; /* X */
5492 pos_args[1].out[1] = ctx->f32zero; /* Y */
5493 pos_args[1].out[2] = ctx->f32zero; /* Z */
5494 pos_args[1].out[3] = ctx->f32zero; /* W */
5495
5496 if (outinfo->writes_pointsize == true)
5497 pos_args[1].out[0] = psize_value;
5498 if (outinfo->writes_layer == true)
5499 pos_args[1].out[2] = layer_value;
5500 if (outinfo->writes_viewport_index == true)
5501 pos_args[1].out[3] = viewport_index_value;
5502 }
5503 for (i = 0; i < 4; i++) {
5504 if (pos_args[i].out[0])
5505 num_pos_exports++;
5506 }
5507
5508 pos_idx = 0;
5509 for (i = 0; i < 4; i++) {
5510 if (!pos_args[i].out[0])
5511 continue;
5512
5513 /* Specify the target we are exporting */
5514 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5515 if (pos_idx == num_pos_exports)
5516 pos_args[i].done = 1;
5517 ac_build_export(&ctx->ac, &pos_args[i]);
5518 }
5519
5520 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5521 LLVMValueRef values[4];
5522 if (!(ctx->output_mask & (1ull << i)))
5523 continue;
5524
5525 for (unsigned j = 0; j < 4; j++)
5526 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5527 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5528
5529 if (i == VARYING_SLOT_LAYER) {
5530 target = V_008DFC_SQ_EXP_PARAM + param_count;
5531 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5532 param_count++;
5533 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5534 target = V_008DFC_SQ_EXP_PARAM + param_count;
5535 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5536 param_count++;
5537 } else if (i >= VARYING_SLOT_VAR0) {
5538 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5539 target = V_008DFC_SQ_EXP_PARAM + param_count;
5540 outinfo->vs_output_param_offset[i] = param_count;
5541 param_count++;
5542 } else
5543 continue;
5544
5545 si_llvm_init_export_args(ctx, values, target, &args);
5546
5547 if (target >= V_008DFC_SQ_EXP_POS &&
5548 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5549 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5550 &args, sizeof(args));
5551 } else {
5552 ac_build_export(&ctx->ac, &args);
5553 }
5554 }
5555
5556 if (export_prim_id) {
5557 LLVMValueRef values[4];
5558 target = V_008DFC_SQ_EXP_PARAM + param_count;
5559 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5560 param_count++;
5561
5562 values[0] = ctx->vs_prim_id;
5563 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5564 ctx->shader_info->vs.vgpr_comp_cnt);
5565 for (unsigned j = 1; j < 4; j++)
5566 values[j] = ctx->f32zero;
5567 si_llvm_init_export_args(ctx, values, target, &args);
5568 ac_build_export(&ctx->ac, &args);
5569 outinfo->export_prim_id = true;
5570 }
5571
5572 outinfo->pos_exports = num_pos_exports;
5573 outinfo->param_exports = param_count;
5574 }
5575
5576 static void
5577 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5578 struct ac_es_output_info *outinfo)
5579 {
5580 int j;
5581 uint64_t max_output_written = 0;
5582 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5583 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5584 int param_index;
5585 int length = 4;
5586
5587 if (!(ctx->output_mask & (1ull << i)))
5588 continue;
5589
5590 if (i == VARYING_SLOT_CLIP_DIST0)
5591 length = ctx->num_output_clips + ctx->num_output_culls;
5592
5593 param_index = shader_io_get_unique_index(i);
5594
5595 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5596
5597 for (j = 0; j < length; j++) {
5598 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5599 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5600
5601 ac_build_buffer_store_dword(&ctx->ac,
5602 ctx->esgs_ring,
5603 out_val, 1,
5604 NULL, ctx->es2gs_offset,
5605 (4 * param_index + j) * 4,
5606 1, 1, true, true);
5607 }
5608 }
5609 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5610 }
5611
5612 static void
5613 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5614 {
5615 LLVMValueRef vertex_id = ctx->rel_auto_id;
5616 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5617 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5618 vertex_dw_stride, "");
5619
5620 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5621 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5622 int length = 4;
5623
5624 if (!(ctx->output_mask & (1ull << i)))
5625 continue;
5626
5627 if (i == VARYING_SLOT_CLIP_DIST0)
5628 length = ctx->num_output_clips + ctx->num_output_culls;
5629 int param = shader_io_get_unique_index(i);
5630 mark_tess_output(ctx, false, param);
5631 if (length > 4)
5632 mark_tess_output(ctx, false, param + 1);
5633 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5634 LLVMConstInt(ctx->i32, param * 4, false),
5635 "");
5636 for (unsigned j = 0; j < length; j++) {
5637 lds_store(ctx, dw_addr,
5638 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5639 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5640 }
5641 }
5642 }
5643
5644 struct ac_build_if_state
5645 {
5646 struct nir_to_llvm_context *ctx;
5647 LLVMValueRef condition;
5648 LLVMBasicBlockRef entry_block;
5649 LLVMBasicBlockRef true_block;
5650 LLVMBasicBlockRef false_block;
5651 LLVMBasicBlockRef merge_block;
5652 };
5653
5654 static LLVMBasicBlockRef
5655 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5656 {
5657 LLVMBasicBlockRef current_block;
5658 LLVMBasicBlockRef next_block;
5659 LLVMBasicBlockRef new_block;
5660
5661 /* get current basic block */
5662 current_block = LLVMGetInsertBlock(ctx->builder);
5663
5664 /* chqeck if there's another block after this one */
5665 next_block = LLVMGetNextBasicBlock(current_block);
5666 if (next_block) {
5667 /* insert the new block before the next block */
5668 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5669 }
5670 else {
5671 /* append new block after current block */
5672 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5673 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5674 }
5675 return new_block;
5676 }
5677
5678 static void
5679 ac_nir_build_if(struct ac_build_if_state *ifthen,
5680 struct nir_to_llvm_context *ctx,
5681 LLVMValueRef condition)
5682 {
5683 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5684
5685 memset(ifthen, 0, sizeof *ifthen);
5686 ifthen->ctx = ctx;
5687 ifthen->condition = condition;
5688 ifthen->entry_block = block;
5689
5690 /* create endif/merge basic block for the phi functions */
5691 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5692
5693 /* create/insert true_block before merge_block */
5694 ifthen->true_block =
5695 LLVMInsertBasicBlockInContext(ctx->context,
5696 ifthen->merge_block,
5697 "if-true-block");
5698
5699 /* successive code goes into the true block */
5700 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5701 }
5702
5703 /**
5704 * End a conditional.
5705 */
5706 static void
5707 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5708 {
5709 LLVMBuilderRef builder = ifthen->ctx->builder;
5710
5711 /* Insert branch to the merge block from current block */
5712 LLVMBuildBr(builder, ifthen->merge_block);
5713
5714 /*
5715 * Now patch in the various branch instructions.
5716 */
5717
5718 /* Insert the conditional branch instruction at the end of entry_block */
5719 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5720 if (ifthen->false_block) {
5721 /* we have an else clause */
5722 LLVMBuildCondBr(builder, ifthen->condition,
5723 ifthen->true_block, ifthen->false_block);
5724 }
5725 else {
5726 /* no else clause */
5727 LLVMBuildCondBr(builder, ifthen->condition,
5728 ifthen->true_block, ifthen->merge_block);
5729 }
5730
5731 /* Resume building code at end of the ifthen->merge_block */
5732 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5733 }
5734
5735 static void
5736 write_tess_factors(struct nir_to_llvm_context *ctx)
5737 {
5738 unsigned stride, outer_comps, inner_comps;
5739 struct ac_build_if_state if_ctx, inner_if_ctx;
5740 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5741 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5742 unsigned tess_inner_index, tess_outer_index;
5743 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5744 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5745 int i;
5746 emit_barrier(ctx);
5747
5748 switch (ctx->options->key.tcs.primitive_mode) {
5749 case GL_ISOLINES:
5750 stride = 2;
5751 outer_comps = 2;
5752 inner_comps = 0;
5753 break;
5754 case GL_TRIANGLES:
5755 stride = 4;
5756 outer_comps = 3;
5757 inner_comps = 1;
5758 break;
5759 case GL_QUADS:
5760 stride = 6;
5761 outer_comps = 4;
5762 inner_comps = 2;
5763 break;
5764 default:
5765 return;
5766 }
5767
5768 ac_nir_build_if(&if_ctx, ctx,
5769 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5770 invocation_id, ctx->i32zero, ""));
5771
5772 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5773 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5774
5775 mark_tess_output(ctx, true, tess_inner_index);
5776 mark_tess_output(ctx, true, tess_outer_index);
5777 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5778 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5779 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5780 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5781 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5782
5783 for (i = 0; i < 4; i++) {
5784 inner[i] = LLVMGetUndef(ctx->i32);
5785 outer[i] = LLVMGetUndef(ctx->i32);
5786 }
5787
5788 // LINES reverseal
5789 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5790 outer[0] = out[1] = lds_load(ctx, lds_outer);
5791 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5792 LLVMConstInt(ctx->i32, 1, false), "");
5793 outer[1] = out[0] = lds_load(ctx, lds_outer);
5794 } else {
5795 for (i = 0; i < outer_comps; i++) {
5796 outer[i] = out[i] =
5797 lds_load(ctx, lds_outer);
5798 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5799 LLVMConstInt(ctx->i32, 1, false), "");
5800 }
5801 for (i = 0; i < inner_comps; i++) {
5802 inner[i] = out[outer_comps+i] =
5803 lds_load(ctx, lds_inner);
5804 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5805 LLVMConstInt(ctx->i32, 1, false), "");
5806 }
5807 }
5808
5809 /* Convert the outputs to vectors for stores. */
5810 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5811 vec1 = NULL;
5812
5813 if (stride > 4)
5814 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5815
5816
5817 buffer = ctx->hs_ring_tess_factor;
5818 tf_base = ctx->tess_factor_offset;
5819 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5820 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5821
5822 ac_nir_build_if(&inner_if_ctx, ctx,
5823 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5824 rel_patch_id, ctx->i32zero, ""));
5825
5826 /* Store the dynamic HS control word. */
5827 ac_build_buffer_store_dword(&ctx->ac, buffer,
5828 LLVMConstInt(ctx->i32, 0x80000000, false),
5829 1, ctx->i32zero, tf_base,
5830 0, 1, 0, true, false);
5831 ac_nir_build_endif(&inner_if_ctx);
5832
5833 /* Store the tessellation factors. */
5834 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5835 MIN2(stride, 4), byteoffset, tf_base,
5836 4, 1, 0, true, false);
5837 if (vec1)
5838 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5839 stride - 4, byteoffset, tf_base,
5840 20, 1, 0, true, false);
5841
5842 //TODO store to offchip for TES to read - only if TES reads them
5843 if (1) {
5844 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5845 LLVMValueRef tf_inner_offset;
5846 unsigned param_outer, param_inner;
5847
5848 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5849 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5850 LLVMConstInt(ctx->i32, param_outer, 0));
5851
5852 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5853 util_next_power_of_two(outer_comps));
5854
5855 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5856 outer_comps, tf_outer_offset,
5857 ctx->oc_lds, 0, 1, 0, true, false);
5858 if (inner_comps) {
5859 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5860 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5861 LLVMConstInt(ctx->i32, param_inner, 0));
5862
5863 inner_vec = inner_comps == 1 ? inner[0] :
5864 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5865 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5866 inner_comps, tf_inner_offset,
5867 ctx->oc_lds, 0, 1, 0, true, false);
5868 }
5869 }
5870 ac_nir_build_endif(&if_ctx);
5871 }
5872
5873 static void
5874 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5875 {
5876 write_tess_factors(ctx);
5877 }
5878
5879 static bool
5880 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5881 LLVMValueRef *color, unsigned param, bool is_last,
5882 struct ac_export_args *args)
5883 {
5884 /* Export */
5885 si_llvm_init_export_args(ctx, color, param,
5886 args);
5887
5888 if (is_last) {
5889 args->valid_mask = 1; /* whether the EXEC mask is valid */
5890 args->done = 1; /* DONE bit */
5891 } else if (!args->enabled_channels)
5892 return false; /* unnecessary NULL export */
5893
5894 return true;
5895 }
5896
5897 static void
5898 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5899 LLVMValueRef depth, LLVMValueRef stencil,
5900 LLVMValueRef samplemask)
5901 {
5902 struct ac_export_args args;
5903
5904 args.enabled_channels = 0;
5905 args.valid_mask = 1;
5906 args.done = 1;
5907 args.target = V_008DFC_SQ_EXP_MRTZ;
5908 args.compr = false;
5909
5910 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5911 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5912 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5913 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5914
5915 if (depth) {
5916 args.out[0] = depth;
5917 args.enabled_channels |= 0x1;
5918 }
5919
5920 if (stencil) {
5921 args.out[1] = stencil;
5922 args.enabled_channels |= 0x2;
5923 }
5924
5925 if (samplemask) {
5926 args.out[2] = samplemask;
5927 args.enabled_channels |= 0x4;
5928 }
5929
5930 /* SI (except OLAND and HAINAN) has a bug that it only looks
5931 * at the X writemask component. */
5932 if (ctx->options->chip_class == SI &&
5933 ctx->options->family != CHIP_OLAND &&
5934 ctx->options->family != CHIP_HAINAN)
5935 args.enabled_channels |= 0x1;
5936
5937 ac_build_export(&ctx->ac, &args);
5938 }
5939
5940 static void
5941 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5942 {
5943 unsigned index = 0;
5944 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5945 struct ac_export_args color_args[8];
5946
5947 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5948 LLVMValueRef values[4];
5949
5950 if (!(ctx->output_mask & (1ull << i)))
5951 continue;
5952
5953 if (i == FRAG_RESULT_DEPTH) {
5954 ctx->shader_info->fs.writes_z = true;
5955 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5956 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5957 } else if (i == FRAG_RESULT_STENCIL) {
5958 ctx->shader_info->fs.writes_stencil = true;
5959 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5960 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5961 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5962 ctx->shader_info->fs.writes_sample_mask = true;
5963 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5964 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5965 } else {
5966 bool last = false;
5967 for (unsigned j = 0; j < 4; j++)
5968 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5969 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5970
5971 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5972 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5973
5974 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5975 if (ret)
5976 index++;
5977 }
5978 }
5979
5980 for (unsigned i = 0; i < index; i++)
5981 ac_build_export(&ctx->ac, &color_args[i]);
5982 if (depth || stencil || samplemask)
5983 si_export_mrt_z(ctx, depth, stencil, samplemask);
5984 else if (!index) {
5985 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5986 ac_build_export(&ctx->ac, &color_args[0]);
5987 }
5988
5989 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5990 }
5991
5992 static void
5993 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5994 {
5995 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5996 }
5997
5998 static void
5999 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6000 LLVMValueRef *addrs)
6001 {
6002 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6003
6004 switch (ctx->stage) {
6005 case MESA_SHADER_VERTEX:
6006 if (ctx->options->key.vs.as_ls)
6007 handle_ls_outputs_post(ctx);
6008 else if (ctx->options->key.vs.as_es)
6009 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6010 else
6011 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6012 &ctx->shader_info->vs.outinfo);
6013 break;
6014 case MESA_SHADER_FRAGMENT:
6015 handle_fs_outputs_post(ctx);
6016 break;
6017 case MESA_SHADER_GEOMETRY:
6018 emit_gs_epilogue(ctx);
6019 break;
6020 case MESA_SHADER_TESS_CTRL:
6021 handle_tcs_outputs_post(ctx);
6022 break;
6023 case MESA_SHADER_TESS_EVAL:
6024 if (ctx->options->key.tes.as_es)
6025 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6026 else
6027 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6028 &ctx->shader_info->tes.outinfo);
6029 break;
6030 default:
6031 break;
6032 }
6033 }
6034
6035 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6036 {
6037 LLVMPassManagerRef passmgr;
6038 /* Create the pass manager */
6039 passmgr = LLVMCreateFunctionPassManagerForModule(
6040 ctx->module);
6041
6042 /* This pass should eliminate all the load and store instructions */
6043 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6044
6045 /* Add some optimization passes */
6046 LLVMAddScalarReplAggregatesPass(passmgr);
6047 LLVMAddLICMPass(passmgr);
6048 LLVMAddAggressiveDCEPass(passmgr);
6049 LLVMAddCFGSimplificationPass(passmgr);
6050 LLVMAddInstructionCombiningPass(passmgr);
6051
6052 /* Run the pass */
6053 LLVMInitializeFunctionPassManager(passmgr);
6054 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6055 LLVMFinalizeFunctionPassManager(passmgr);
6056
6057 LLVMDisposeBuilder(ctx->builder);
6058 LLVMDisposePassManager(passmgr);
6059 }
6060
6061 static void
6062 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6063 {
6064 struct ac_vs_output_info *outinfo;
6065
6066 switch (ctx->stage) {
6067 case MESA_SHADER_FRAGMENT:
6068 case MESA_SHADER_COMPUTE:
6069 case MESA_SHADER_TESS_CTRL:
6070 case MESA_SHADER_GEOMETRY:
6071 return;
6072 case MESA_SHADER_VERTEX:
6073 if (ctx->options->key.vs.as_ls ||
6074 ctx->options->key.vs.as_es)
6075 return;
6076 outinfo = &ctx->shader_info->vs.outinfo;
6077 break;
6078 case MESA_SHADER_TESS_EVAL:
6079 if (ctx->options->key.vs.as_es)
6080 return;
6081 outinfo = &ctx->shader_info->tes.outinfo;
6082 break;
6083 default:
6084 unreachable("Unhandled shader type");
6085 }
6086
6087 ac_optimize_vs_outputs(&ctx->ac,
6088 ctx->main_function,
6089 outinfo->vs_output_param_offset,
6090 VARYING_SLOT_MAX,
6091 &outinfo->param_exports);
6092 }
6093
6094 static void
6095 ac_setup_rings(struct nir_to_llvm_context *ctx)
6096 {
6097 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6098 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6099 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6100 }
6101
6102 if (ctx->is_gs_copy_shader) {
6103 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6104 }
6105 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6106 LLVMValueRef tmp;
6107 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6108 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6109
6110 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6111
6112 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6113 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6114 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6115 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6116 }
6117
6118 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6119 ctx->stage == MESA_SHADER_TESS_EVAL) {
6120 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6121 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6122 }
6123 }
6124
6125 static unsigned
6126 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6127 const struct nir_shader *nir)
6128 {
6129 switch (nir->stage) {
6130 case MESA_SHADER_TESS_CTRL:
6131 return chip_class >= CIK ? 128 : 64;
6132 case MESA_SHADER_GEOMETRY:
6133 return 64;
6134 case MESA_SHADER_COMPUTE:
6135 break;
6136 default:
6137 return 0;
6138 }
6139
6140 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6141 nir->info.cs.local_size[1] *
6142 nir->info.cs.local_size[2];
6143 return max_workgroup_size;
6144 }
6145
6146 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6147 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6148 {
6149 struct ac_nir_context ctx = {};
6150 struct nir_function *func;
6151
6152 ctx.ac = *ac;
6153 ctx.abi = abi;
6154
6155 ctx.nctx = nctx;
6156 if (nctx)
6157 nctx->nir = &ctx;
6158
6159 ctx.stage = nir->stage;
6160
6161 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6162
6163 nir_foreach_variable(variable, &nir->outputs)
6164 handle_shader_output_decl(&ctx, nir, variable);
6165
6166 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6167 _mesa_key_pointer_equal);
6168 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6169 _mesa_key_pointer_equal);
6170 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6171 _mesa_key_pointer_equal);
6172
6173 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6174
6175 setup_locals(&ctx, func);
6176
6177 if (nir->stage == MESA_SHADER_COMPUTE)
6178 setup_shared(&ctx, nir);
6179
6180 visit_cf_list(&ctx, &func->impl->body);
6181 phi_post_pass(&ctx);
6182
6183 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6184 ctx.outputs);
6185
6186 free(ctx.locals);
6187 ralloc_free(ctx.defs);
6188 ralloc_free(ctx.phis);
6189 ralloc_free(ctx.vars);
6190
6191 if (nctx)
6192 nctx->nir = NULL;
6193 }
6194
6195 static
6196 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6197 struct nir_shader *nir,
6198 struct ac_shader_variant_info *shader_info,
6199 const struct ac_nir_compiler_options *options)
6200 {
6201 struct nir_to_llvm_context ctx = {0};
6202 unsigned i;
6203 ctx.options = options;
6204 ctx.shader_info = shader_info;
6205 ctx.context = LLVMContextCreate();
6206 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6207
6208 ac_llvm_context_init(&ctx.ac, ctx.context);
6209 ctx.ac.module = ctx.module;
6210
6211 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
6212
6213 memset(shader_info, 0, sizeof(*shader_info));
6214
6215 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6216
6217 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6218
6219 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6220 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6221 LLVMSetDataLayout(ctx.module, data_layout_str);
6222 LLVMDisposeTargetData(data_layout);
6223 LLVMDisposeMessage(data_layout_str);
6224
6225 setup_types(&ctx);
6226
6227 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6228 ctx.ac.builder = ctx.builder;
6229 ctx.stage = nir->stage;
6230 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6231
6232 for (i = 0; i < AC_UD_MAX_SETS; i++)
6233 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6234 for (i = 0; i < AC_UD_MAX_UD; i++)
6235 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6236
6237 create_function(&ctx);
6238
6239 if (nir->stage == MESA_SHADER_GEOMETRY) {
6240 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6241
6242 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6243 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6244 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6245 } else if (nir->stage == MESA_SHADER_VERTEX) {
6246 if (shader_info->info.vs.needs_instance_id) {
6247 ctx.shader_info->vs.vgpr_comp_cnt =
6248 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6249 }
6250 } else if (nir->stage == MESA_SHADER_FRAGMENT) {
6251 shader_info->fs.can_discard = nir->info.fs.uses_discard;
6252 }
6253
6254 ac_setup_rings(&ctx);
6255
6256 ctx.num_output_clips = nir->info.clip_distance_array_size;
6257 ctx.num_output_culls = nir->info.cull_distance_array_size;
6258
6259 nir_foreach_variable(variable, &nir->inputs)
6260 handle_shader_input_decl(&ctx, variable);
6261
6262 if (nir->stage == MESA_SHADER_FRAGMENT)
6263 handle_fs_inputs_pre(&ctx, nir);
6264
6265 ctx.abi.chip_class = options->chip_class;
6266 ctx.abi.inputs = &ctx.inputs[0];
6267 ctx.abi.emit_outputs = handle_shader_outputs_post;
6268 ctx.abi.load_ssbo = radv_load_ssbo;
6269 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6270
6271 nir_foreach_variable(variable, &nir->outputs)
6272 scan_shader_output_decl(&ctx, variable);
6273
6274 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6275
6276 LLVMBuildRetVoid(ctx.builder);
6277
6278 ac_llvm_finalize_module(&ctx);
6279
6280 ac_nir_eliminate_const_vs_outputs(&ctx);
6281
6282 if (nir->stage == MESA_SHADER_GEOMETRY) {
6283 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6284 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6285 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6286 nir->info.gs.vertices_out;
6287 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6288 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6289 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6290 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6291 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6292 }
6293
6294 return ctx.module;
6295 }
6296
6297 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6298 {
6299 unsigned *retval = (unsigned *)context;
6300 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6301 char *description = LLVMGetDiagInfoDescription(di);
6302
6303 if (severity == LLVMDSError) {
6304 *retval = 1;
6305 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6306 description);
6307 }
6308
6309 LLVMDisposeMessage(description);
6310 }
6311
6312 static unsigned ac_llvm_compile(LLVMModuleRef M,
6313 struct ac_shader_binary *binary,
6314 LLVMTargetMachineRef tm)
6315 {
6316 unsigned retval = 0;
6317 char *err;
6318 LLVMContextRef llvm_ctx;
6319 LLVMMemoryBufferRef out_buffer;
6320 unsigned buffer_size;
6321 const char *buffer_data;
6322 LLVMBool mem_err;
6323
6324 /* Setup Diagnostic Handler*/
6325 llvm_ctx = LLVMGetModuleContext(M);
6326
6327 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6328 &retval);
6329
6330 /* Compile IR*/
6331 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6332 &err, &out_buffer);
6333
6334 /* Process Errors/Warnings */
6335 if (mem_err) {
6336 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6337 free(err);
6338 retval = 1;
6339 goto out;
6340 }
6341
6342 /* Extract Shader Code*/
6343 buffer_size = LLVMGetBufferSize(out_buffer);
6344 buffer_data = LLVMGetBufferStart(out_buffer);
6345
6346 ac_elf_read(buffer_data, buffer_size, binary);
6347
6348 /* Clean up */
6349 LLVMDisposeMemoryBuffer(out_buffer);
6350
6351 out:
6352 return retval;
6353 }
6354
6355 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6356 LLVMModuleRef llvm_module,
6357 struct ac_shader_binary *binary,
6358 struct ac_shader_config *config,
6359 struct ac_shader_variant_info *shader_info,
6360 gl_shader_stage stage,
6361 bool dump_shader, bool supports_spill)
6362 {
6363 if (dump_shader)
6364 ac_dump_module(llvm_module);
6365
6366 memset(binary, 0, sizeof(*binary));
6367 int v = ac_llvm_compile(llvm_module, binary, tm);
6368 if (v) {
6369 fprintf(stderr, "compile failed\n");
6370 }
6371
6372 if (dump_shader)
6373 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6374
6375 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6376
6377 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6378 LLVMDisposeModule(llvm_module);
6379 LLVMContextDispose(ctx);
6380
6381 if (stage == MESA_SHADER_FRAGMENT) {
6382 shader_info->num_input_vgprs = 0;
6383 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6384 shader_info->num_input_vgprs += 2;
6385 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6386 shader_info->num_input_vgprs += 2;
6387 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6388 shader_info->num_input_vgprs += 2;
6389 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6390 shader_info->num_input_vgprs += 3;
6391 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6392 shader_info->num_input_vgprs += 2;
6393 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6394 shader_info->num_input_vgprs += 2;
6395 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6396 shader_info->num_input_vgprs += 2;
6397 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6398 shader_info->num_input_vgprs += 1;
6399 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6400 shader_info->num_input_vgprs += 1;
6401 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6402 shader_info->num_input_vgprs += 1;
6403 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6404 shader_info->num_input_vgprs += 1;
6405 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6406 shader_info->num_input_vgprs += 1;
6407 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6408 shader_info->num_input_vgprs += 1;
6409 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6410 shader_info->num_input_vgprs += 1;
6411 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6412 shader_info->num_input_vgprs += 1;
6413 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6414 shader_info->num_input_vgprs += 1;
6415 }
6416 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6417
6418 /* +3 for scratch wave offset and VCC */
6419 config->num_sgprs = MAX2(config->num_sgprs,
6420 shader_info->num_input_sgprs + 3);
6421 }
6422
6423 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6424 struct ac_shader_binary *binary,
6425 struct ac_shader_config *config,
6426 struct ac_shader_variant_info *shader_info,
6427 struct nir_shader *nir,
6428 const struct ac_nir_compiler_options *options,
6429 bool dump_shader)
6430 {
6431
6432 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6433 options);
6434
6435 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6436 switch (nir->stage) {
6437 case MESA_SHADER_COMPUTE:
6438 for (int i = 0; i < 3; ++i)
6439 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6440 break;
6441 case MESA_SHADER_FRAGMENT:
6442 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6443 break;
6444 case MESA_SHADER_GEOMETRY:
6445 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6446 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6447 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6448 shader_info->gs.invocations = nir->info.gs.invocations;
6449 break;
6450 case MESA_SHADER_TESS_EVAL:
6451 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6452 shader_info->tes.spacing = nir->info.tess.spacing;
6453 shader_info->tes.ccw = nir->info.tess.ccw;
6454 shader_info->tes.point_mode = nir->info.tess.point_mode;
6455 shader_info->tes.as_es = options->key.tes.as_es;
6456 break;
6457 case MESA_SHADER_TESS_CTRL:
6458 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6459 break;
6460 case MESA_SHADER_VERTEX:
6461 shader_info->vs.as_es = options->key.vs.as_es;
6462 shader_info->vs.as_ls = options->key.vs.as_ls;
6463 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6464 if (options->key.vs.as_ls)
6465 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6466 break;
6467 default:
6468 break;
6469 }
6470 }
6471
6472 static void
6473 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6474 {
6475 LLVMValueRef args[9];
6476 args[0] = ctx->gsvs_ring;
6477 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6478 args[3] = ctx->i32zero;
6479 args[4] = ctx->i32one; /* OFFEN */
6480 args[5] = ctx->i32zero; /* IDXEN */
6481 args[6] = ctx->i32one; /* GLC */
6482 args[7] = ctx->i32one; /* SLC */
6483 args[8] = ctx->i32zero; /* TFE */
6484
6485 int idx = 0;
6486
6487 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6488 int length = 4;
6489 int slot = idx;
6490 int slot_inc = 1;
6491 if (!(ctx->output_mask & (1ull << i)))
6492 continue;
6493
6494 if (i == VARYING_SLOT_CLIP_DIST0) {
6495 /* unpack clip and cull from a single set of slots */
6496 length = ctx->num_output_clips + ctx->num_output_culls;
6497 if (length > 4)
6498 slot_inc = 2;
6499 }
6500
6501 for (unsigned j = 0; j < length; j++) {
6502 LLVMValueRef value;
6503 args[2] = LLVMConstInt(ctx->i32,
6504 (slot * 4 + j) *
6505 ctx->gs_max_out_vertices * 16 * 4, false);
6506
6507 value = ac_build_intrinsic(&ctx->ac,
6508 "llvm.SI.buffer.load.dword.i32.i32",
6509 ctx->i32, args, 9,
6510 AC_FUNC_ATTR_READONLY |
6511 AC_FUNC_ATTR_LEGACY);
6512
6513 LLVMBuildStore(ctx->builder,
6514 to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6515 }
6516 idx += slot_inc;
6517 }
6518 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6519 }
6520
6521 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6522 struct nir_shader *geom_shader,
6523 struct ac_shader_binary *binary,
6524 struct ac_shader_config *config,
6525 struct ac_shader_variant_info *shader_info,
6526 const struct ac_nir_compiler_options *options,
6527 bool dump_shader)
6528 {
6529 struct nir_to_llvm_context ctx = {0};
6530 ctx.context = LLVMContextCreate();
6531 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6532 ctx.options = options;
6533 ctx.shader_info = shader_info;
6534
6535 ac_llvm_context_init(&ctx.ac, ctx.context);
6536 ctx.ac.module = ctx.module;
6537
6538 ctx.is_gs_copy_shader = true;
6539 LLVMSetTarget(ctx.module, "amdgcn--");
6540 setup_types(&ctx);
6541
6542 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6543 ctx.ac.builder = ctx.builder;
6544 ctx.stage = MESA_SHADER_VERTEX;
6545
6546 create_function(&ctx);
6547
6548 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6549 ac_setup_rings(&ctx);
6550
6551 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6552 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6553
6554 struct ac_nir_context nir_ctx = {};
6555 nir_ctx.ac = ctx.ac;
6556 nir_ctx.abi = &ctx.abi;
6557
6558 nir_ctx.nctx = &ctx;
6559 ctx.nir = &nir_ctx;
6560
6561 nir_foreach_variable(variable, &geom_shader->outputs) {
6562 scan_shader_output_decl(&ctx, variable);
6563 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6564 }
6565
6566 ac_gs_copy_shader_emit(&ctx);
6567
6568 ctx.nir = NULL;
6569
6570 LLVMBuildRetVoid(ctx.builder);
6571
6572 ac_llvm_finalize_module(&ctx);
6573
6574 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6575 MESA_SHADER_VERTEX,
6576 dump_shader, options->supports_spill);
6577 }