projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ac/nir_to_llvm: add support for nir_intrinsic_shared_atomic_*
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct ac_nir_context {
50 struct ac_llvm_context ac;
51 struct ac_shader_abi *abi;
52
53 gl_shader_stage stage;
54
55 struct hash_table *defs;
56 struct hash_table *phis;
57 struct hash_table *vars;
58
59 LLVMValueRef main_function;
60 LLVMBasicBlockRef continue_block;
61 LLVMBasicBlockRef break_block;
62
63 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
64
65 int num_locals;
66 LLVMValueRef *locals;
67 };
68
69 struct nir_to_llvm_context {
70 struct ac_llvm_context ac;
71 const struct ac_nir_compiler_options *options;
72 struct ac_shader_variant_info *shader_info;
73 struct ac_shader_abi abi;
74 struct ac_nir_context *nir;
75
76 unsigned max_workgroup_size;
77 LLVMContextRef context;
78 LLVMValueRef main_function;
79
80 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
81 LLVMValueRef ring_offsets;
82
83 LLVMValueRef vertex_buffers;
84 LLVMValueRef rel_auto_id;
85 LLVMValueRef vs_prim_id;
86 LLVMValueRef ls_out_layout;
87 LLVMValueRef es2gs_offset;
88
89 LLVMValueRef tcs_offchip_layout;
90 LLVMValueRef tcs_out_offsets;
91 LLVMValueRef tcs_out_layout;
92 LLVMValueRef tcs_in_layout;
93 LLVMValueRef oc_lds;
94 LLVMValueRef merged_wave_info;
95 LLVMValueRef tess_factor_offset;
96 LLVMValueRef tes_rel_patch_id;
97 LLVMValueRef tes_u;
98 LLVMValueRef tes_v;
99
100 LLVMValueRef gsvs_ring_stride;
101 LLVMValueRef gsvs_num_entries;
102 LLVMValueRef gs2vs_offset;
103 LLVMValueRef gs_wave_id;
104 LLVMValueRef gs_vtx_offset[6];
105
106 LLVMValueRef esgs_ring;
107 LLVMValueRef gsvs_ring;
108 LLVMValueRef hs_ring_tess_offchip;
109 LLVMValueRef hs_ring_tess_factor;
110
111 LLVMValueRef sample_pos_offset;
112 LLVMValueRef persp_sample, persp_center, persp_centroid;
113 LLVMValueRef linear_sample, linear_center, linear_centroid;
114
115 gl_shader_stage stage;
116
117 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
118
119 uint64_t input_mask;
120 uint64_t output_mask;
121 uint8_t num_output_clips;
122 uint8_t num_output_culls;
123
124 bool is_gs_copy_shader;
125 LLVMValueRef gs_next_vertex;
126 unsigned gs_max_out_vertices;
127
128 unsigned tes_primitive_mode;
129 uint64_t tess_outputs_written;
130 uint64_t tess_patch_outputs_written;
131
132 uint32_t tcs_patch_outputs_read;
133 uint64_t tcs_outputs_read;
134 };
135
136 static inline struct nir_to_llvm_context *
137 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
138 {
139 struct nir_to_llvm_context *ctx = NULL;
140 return container_of(abi, ctx, abi);
141 }
142
143 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
144 const nir_deref_var *deref,
145 enum ac_descriptor_type desc_type,
146 const nir_tex_instr *instr,
147 bool image, bool write);
148
149 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
150 {
151 return (index * 4) + chan;
152 }
153
154 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
155 {
156 /* handle patch indices separate */
157 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
158 return 0;
159 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
160 return 1;
161 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
162 return 2 + (slot - VARYING_SLOT_PATCH0);
163
164 if (slot == VARYING_SLOT_POS)
165 return 0;
166 if (slot == VARYING_SLOT_PSIZ)
167 return 1;
168 if (slot == VARYING_SLOT_CLIP_DIST0)
169 return 2;
170 /* 3 is reserved for clip dist as well */
171 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
172 return 4 + (slot - VARYING_SLOT_VAR0);
173 unreachable("illegal slot in get unique index\n");
174 }
175
176 static void set_llvm_calling_convention(LLVMValueRef func,
177 gl_shader_stage stage)
178 {
179 enum radeon_llvm_calling_convention calling_conv;
180
181 switch (stage) {
182 case MESA_SHADER_VERTEX:
183 case MESA_SHADER_TESS_EVAL:
184 calling_conv = RADEON_LLVM_AMDGPU_VS;
185 break;
186 case MESA_SHADER_GEOMETRY:
187 calling_conv = RADEON_LLVM_AMDGPU_GS;
188 break;
189 case MESA_SHADER_TESS_CTRL:
190 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
191 break;
192 case MESA_SHADER_FRAGMENT:
193 calling_conv = RADEON_LLVM_AMDGPU_PS;
194 break;
195 case MESA_SHADER_COMPUTE:
196 calling_conv = RADEON_LLVM_AMDGPU_CS;
197 break;
198 default:
199 unreachable("Unhandle shader type");
200 }
201
202 LLVMSetFunctionCallConv(func, calling_conv);
203 }
204
205 #define MAX_ARGS 23
206 struct arg_info {
207 LLVMTypeRef types[MAX_ARGS];
208 LLVMValueRef *assign[MAX_ARGS];
209 unsigned array_params_mask;
210 uint8_t count;
211 uint8_t sgpr_count;
212 uint8_t num_sgprs_used;
213 uint8_t num_vgprs_used;
214 };
215
216 enum ac_arg_regfile {
217 ARG_SGPR,
218 ARG_VGPR,
219 };
220
221 static void
222 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
223 LLVMValueRef *param_ptr)
224 {
225 assert(info->count < MAX_ARGS);
226
227 info->assign[info->count] = param_ptr;
228 info->types[info->count] = type;
229 info->count++;
230
231 if (regfile == ARG_SGPR) {
232 info->num_sgprs_used += ac_get_type_size(type) / 4;
233 info->sgpr_count++;
234 } else {
235 assert(regfile == ARG_VGPR);
236 info->num_vgprs_used += ac_get_type_size(type) / 4;
237 }
238 }
239
240 static inline void
241 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
242 {
243 info->array_params_mask |= (1 << info->count);
244 add_arg(info, ARG_SGPR, type, param_ptr);
245 }
246
247 static void assign_arguments(LLVMValueRef main_function,
248 struct arg_info *info)
249 {
250 unsigned i;
251 for (i = 0; i < info->count; i++) {
252 if (info->assign[i])
253 *info->assign[i] = LLVMGetParam(main_function, i);
254 }
255 }
256
257 static LLVMValueRef
258 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
259 LLVMBuilderRef builder, LLVMTypeRef *return_types,
260 unsigned num_return_elems,
261 struct arg_info *args,
262 unsigned max_workgroup_size,
263 bool unsafe_math)
264 {
265 LLVMTypeRef main_function_type, ret_type;
266 LLVMBasicBlockRef main_function_body;
267
268 if (num_return_elems)
269 ret_type = LLVMStructTypeInContext(ctx, return_types,
270 num_return_elems, true);
271 else
272 ret_type = LLVMVoidTypeInContext(ctx);
273
274 /* Setup the function */
275 main_function_type =
276 LLVMFunctionType(ret_type, args->types, args->count, 0);
277 LLVMValueRef main_function =
278 LLVMAddFunction(module, "main", main_function_type);
279 main_function_body =
280 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
281 LLVMPositionBuilderAtEnd(builder, main_function_body);
282
283 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
284 for (unsigned i = 0; i < args->sgpr_count; ++i) {
285 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
286
287 if (args->array_params_mask & (1 << i)) {
288 LLVMValueRef P = LLVMGetParam(main_function, i);
289 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
290 ac_add_attr_dereferenceable(P, UINT64_MAX);
291 }
292 }
293
294 if (max_workgroup_size) {
295 ac_llvm_add_target_dep_function_attr(main_function,
296 "amdgpu-max-work-group-size",
297 max_workgroup_size);
298 }
299 if (unsafe_math) {
300 /* These were copied from some LLVM test. */
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "less-precise-fpmad",
303 "true");
304 LLVMAddTargetDependentFunctionAttr(main_function,
305 "no-infs-fp-math",
306 "true");
307 LLVMAddTargetDependentFunctionAttr(main_function,
308 "no-nans-fp-math",
309 "true");
310 LLVMAddTargetDependentFunctionAttr(main_function,
311 "unsafe-fp-math",
312 "true");
313 LLVMAddTargetDependentFunctionAttr(main_function,
314 "no-signed-zeros-fp-math",
315 "true");
316 }
317 return main_function;
318 }
319
320 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
321 LLVMValueRef param, unsigned rshift,
322 unsigned bitwidth)
323 {
324 LLVMValueRef value = param;
325 if (rshift)
326 value = LLVMBuildLShr(ctx->builder, value,
327 LLVMConstInt(ctx->i32, rshift, false), "");
328
329 if (rshift + bitwidth < 32) {
330 unsigned mask = (1 << bitwidth) - 1;
331 value = LLVMBuildAnd(ctx->builder, value,
332 LLVMConstInt(ctx->i32, mask, false), "");
333 }
334 return value;
335 }
336
337 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
338 {
339 switch (ctx->stage) {
340 case MESA_SHADER_TESS_CTRL:
341 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
342 case MESA_SHADER_TESS_EVAL:
343 return ctx->tes_rel_patch_id;
344 break;
345 default:
346 unreachable("Illegal stage");
347 }
348 }
349
350 /* Tessellation shaders pass outputs to the next shader using LDS.
351 *
352 * LS outputs = TCS inputs
353 * TCS outputs = TES inputs
354 *
355 * The LDS layout is:
356 * - TCS inputs for patch 0
357 * - TCS inputs for patch 1
358 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
359 * - ...
360 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
361 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
362 * - TCS outputs for patch 1
363 * - Per-patch TCS outputs for patch 1
364 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
365 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
366 * - ...
367 *
368 * All three shaders VS(LS), TCS, TES share the same LDS space.
369 */
370 static LLVMValueRef
371 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
372 {
373 if (ctx->stage == MESA_SHADER_VERTEX)
374 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
375 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
376 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
377 else {
378 assert(0);
379 return NULL;
380 }
381 }
382
383 static LLVMValueRef
384 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
385 {
386 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
387 }
388
389 static LLVMValueRef
390 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
391 {
392 return LLVMBuildMul(ctx->ac.builder,
393 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
394 LLVMConstInt(ctx->ac.i32, 4, false), "");
395 }
396
397 static LLVMValueRef
398 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
399 {
400 return LLVMBuildMul(ctx->ac.builder,
401 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
402 LLVMConstInt(ctx->ac.i32, 4, false), "");
403 }
404
405 static LLVMValueRef
406 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
407 {
408 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
409 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
410
411 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
412 }
413
414 static LLVMValueRef
415 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
416 {
417 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
418 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
419 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
420
421 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
422 LLVMBuildMul(ctx->ac.builder, patch_stride,
423 rel_patch_id, ""),
424 "");
425 }
426
427 static LLVMValueRef
428 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
429 {
430 LLVMValueRef patch0_patch_data_offset =
431 get_tcs_out_patch0_patch_data_offset(ctx);
432 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
433 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
434
435 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
436 LLVMBuildMul(ctx->ac.builder, patch_stride,
437 rel_patch_id, ""),
438 "");
439 }
440
441 static void
442 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
443 uint32_t indirect_offset)
444 {
445 ud_info->sgpr_idx = *sgpr_idx;
446 ud_info->num_sgprs = num_sgprs;
447 ud_info->indirect = indirect_offset > 0;
448 ud_info->indirect_offset = indirect_offset;
449 *sgpr_idx += num_sgprs;
450 }
451
452 static void
453 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
454 uint8_t num_sgprs)
455 {
456 struct ac_userdata_info *ud_info =
457 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
458 assert(ud_info);
459
460 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
461 }
462
463 static void
464 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
465 uint32_t indirect_offset)
466 {
467 struct ac_userdata_info *ud_info =
468 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
469 assert(ud_info);
470
471 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
472 }
473
474 struct user_sgpr_info {
475 bool need_ring_offsets;
476 uint8_t sgpr_count;
477 bool indirect_all_descriptor_sets;
478 };
479
480 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
481 gl_shader_stage stage)
482 {
483 switch (stage) {
484 case MESA_SHADER_VERTEX:
485 if (ctx->shader_info->info.needs_multiview_view_index ||
486 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
487 return true;
488 break;
489 case MESA_SHADER_TESS_EVAL:
490 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
491 return true;
492 break;
493 case MESA_SHADER_GEOMETRY:
494 case MESA_SHADER_TESS_CTRL:
495 if (ctx->shader_info->info.needs_multiview_view_index)
496 return true;
497 break;
498 default:
499 break;
500 }
501 return false;
502 }
503
504 static uint8_t
505 count_vs_user_sgprs(struct nir_to_llvm_context *ctx)
506 {
507 uint8_t count = 0;
508
509 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
510 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
511
512 return count;
513 }
514
515 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
516 gl_shader_stage stage,
517 bool has_previous_stage,
518 gl_shader_stage previous_stage,
519 bool needs_view_index,
520 struct user_sgpr_info *user_sgpr_info)
521 {
522 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
523
524 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
525 if (stage == MESA_SHADER_GEOMETRY ||
526 stage == MESA_SHADER_VERTEX ||
527 stage == MESA_SHADER_TESS_CTRL ||
528 stage == MESA_SHADER_TESS_EVAL ||
529 ctx->is_gs_copy_shader)
530 user_sgpr_info->need_ring_offsets = true;
531
532 if (stage == MESA_SHADER_FRAGMENT &&
533 ctx->shader_info->info.ps.needs_sample_positions)
534 user_sgpr_info->need_ring_offsets = true;
535
536 /* 2 user sgprs will nearly always be allocated for scratch/rings */
537 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
538 user_sgpr_info->sgpr_count += 2;
539 }
540
541 switch (stage) {
542 case MESA_SHADER_COMPUTE:
543 if (ctx->shader_info->info.cs.uses_grid_size)
544 user_sgpr_info->sgpr_count += 3;
545 break;
546 case MESA_SHADER_FRAGMENT:
547 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
548 break;
549 case MESA_SHADER_VERTEX:
550 if (!ctx->is_gs_copy_shader)
551 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
552 if (ctx->options->key.vs.as_ls)
553 user_sgpr_info->sgpr_count++;
554 break;
555 case MESA_SHADER_TESS_CTRL:
556 if (has_previous_stage) {
557 if (previous_stage == MESA_SHADER_VERTEX)
558 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
559 user_sgpr_info->sgpr_count++;
560 }
561 user_sgpr_info->sgpr_count += 4;
562 break;
563 case MESA_SHADER_TESS_EVAL:
564 user_sgpr_info->sgpr_count += 1;
565 break;
566 case MESA_SHADER_GEOMETRY:
567 if (has_previous_stage) {
568 if (previous_stage == MESA_SHADER_VERTEX) {
569 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
570 } else {
571 user_sgpr_info->sgpr_count++;
572 }
573 }
574 user_sgpr_info->sgpr_count += 2;
575 break;
576 default:
577 break;
578 }
579
580 if (needs_view_index)
581 user_sgpr_info->sgpr_count++;
582
583 if (ctx->shader_info->info.loads_push_constants)
584 user_sgpr_info->sgpr_count += 2;
585
586 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
587 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
588
589 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
590 user_sgpr_info->sgpr_count += 2;
591 user_sgpr_info->indirect_all_descriptor_sets = true;
592 } else {
593 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
594 }
595 }
596
597 static void
598 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
599 gl_shader_stage stage,
600 bool has_previous_stage,
601 gl_shader_stage previous_stage,
602 const struct user_sgpr_info *user_sgpr_info,
603 struct arg_info *args,
604 LLVMValueRef *desc_sets)
605 {
606 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
607 unsigned num_sets = ctx->options->layout ?
608 ctx->options->layout->num_sets : 0;
609 unsigned stage_mask = 1 << stage;
610
611 if (has_previous_stage)
612 stage_mask |= 1 << previous_stage;
613
614 /* 1 for each descriptor set */
615 if (!user_sgpr_info->indirect_all_descriptor_sets) {
616 for (unsigned i = 0; i < num_sets; ++i) {
617 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
618 add_array_arg(args, type,
619 &ctx->descriptor_sets[i]);
620 }
621 }
622 } else {
623 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
624 }
625
626 if (ctx->shader_info->info.loads_push_constants) {
627 /* 1 for push constants and dynamic descriptors */
628 add_array_arg(args, type, &ctx->abi.push_constants);
629 }
630 }
631
632 static void
633 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
634 gl_shader_stage stage,
635 bool has_previous_stage,
636 gl_shader_stage previous_stage,
637 struct arg_info *args)
638 {
639 if (!ctx->is_gs_copy_shader &&
640 (stage == MESA_SHADER_VERTEX ||
641 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
642 if (ctx->shader_info->info.vs.has_vertex_buffers) {
643 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
644 &ctx->vertex_buffers);
645 }
646 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
647 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
648 if (ctx->shader_info->info.vs.needs_draw_id) {
649 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
650 }
651 }
652 }
653
654 static void
655 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
656 {
657 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
658 if (!ctx->is_gs_copy_shader) {
659 if (ctx->options->key.vs.as_ls) {
660 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
662 } else {
663 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
664 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
665 }
666 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
667 }
668 }
669
670 static void
671 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
672 {
673 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
674 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
675 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
676 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
677 }
678
679 static void
680 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
681 bool has_previous_stage, gl_shader_stage previous_stage,
682 const struct user_sgpr_info *user_sgpr_info,
683 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
684 {
685 unsigned num_sets = ctx->options->layout ?
686 ctx->options->layout->num_sets : 0;
687 unsigned stage_mask = 1 << stage;
688
689 if (has_previous_stage)
690 stage_mask |= 1 << previous_stage;
691
692 if (!user_sgpr_info->indirect_all_descriptor_sets) {
693 for (unsigned i = 0; i < num_sets; ++i) {
694 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
695 set_loc_desc(ctx, i, user_sgpr_idx, 0);
696 } else
697 ctx->descriptor_sets[i] = NULL;
698 }
699 } else {
700 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
701 user_sgpr_idx, 2);
702
703 for (unsigned i = 0; i < num_sets; ++i) {
704 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
705 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
706 ctx->descriptor_sets[i] =
707 ac_build_load_to_sgpr(&ctx->ac,
708 desc_sets,
709 LLVMConstInt(ctx->ac.i32, i, false));
710
711 } else
712 ctx->descriptor_sets[i] = NULL;
713 }
714 ctx->shader_info->need_indirect_descriptor_sets = true;
715 }
716
717 if (ctx->shader_info->info.loads_push_constants) {
718 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
719 }
720 }
721
722 static void
723 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
724 gl_shader_stage stage, bool has_previous_stage,
725 gl_shader_stage previous_stage,
726 uint8_t *user_sgpr_idx)
727 {
728 if (!ctx->is_gs_copy_shader &&
729 (stage == MESA_SHADER_VERTEX ||
730 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
731 if (ctx->shader_info->info.vs.has_vertex_buffers) {
732 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
733 user_sgpr_idx, 2);
734 }
735
736 unsigned vs_num = 2;
737 if (ctx->shader_info->info.vs.needs_draw_id)
738 vs_num++;
739
740 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
741 user_sgpr_idx, vs_num);
742 }
743 }
744
745 static void create_function(struct nir_to_llvm_context *ctx,
746 gl_shader_stage stage,
747 bool has_previous_stage,
748 gl_shader_stage previous_stage)
749 {
750 uint8_t user_sgpr_idx;
751 struct user_sgpr_info user_sgpr_info;
752 struct arg_info args = {};
753 LLVMValueRef desc_sets;
754 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
755 allocate_user_sgprs(ctx, stage, has_previous_stage,
756 previous_stage, needs_view_index, &user_sgpr_info);
757
758 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
759 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
760 &ctx->ring_offsets);
761 }
762
763 switch (stage) {
764 case MESA_SHADER_COMPUTE:
765 declare_global_input_sgprs(ctx, stage, has_previous_stage,
766 previous_stage, &user_sgpr_info,
767 &args, &desc_sets);
768
769 if (ctx->shader_info->info.cs.uses_grid_size) {
770 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
771 &ctx->abi.num_work_groups);
772 }
773
774 for (int i = 0; i < 3; i++) {
775 ctx->abi.workgroup_ids[i] = NULL;
776 if (ctx->shader_info->info.cs.uses_block_id[i]) {
777 add_arg(&args, ARG_SGPR, ctx->ac.i32,
778 &ctx->abi.workgroup_ids[i]);
779 }
780 }
781
782 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
783 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
784 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
785 &ctx->abi.local_invocation_ids);
786 break;
787 case MESA_SHADER_VERTEX:
788 declare_global_input_sgprs(ctx, stage, has_previous_stage,
789 previous_stage, &user_sgpr_info,
790 &args, &desc_sets);
791 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
792 previous_stage, &args);
793
794 if (needs_view_index)
795 add_arg(&args, ARG_SGPR, ctx->ac.i32,
796 &ctx->abi.view_index);
797 if (ctx->options->key.vs.as_es)
798 add_arg(&args, ARG_SGPR, ctx->ac.i32,
799 &ctx->es2gs_offset);
800 else if (ctx->options->key.vs.as_ls)
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->ls_out_layout);
803
804 declare_vs_input_vgprs(ctx, &args);
805 break;
806 case MESA_SHADER_TESS_CTRL:
807 if (has_previous_stage) {
808 // First 6 system regs
809 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
810 add_arg(&args, ARG_SGPR, ctx->ac.i32,
811 &ctx->merged_wave_info);
812 add_arg(&args, ARG_SGPR, ctx->ac.i32,
813 &ctx->tess_factor_offset);
814
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
816 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
817 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
818
819 declare_global_input_sgprs(ctx, stage,
820 has_previous_stage,
821 previous_stage,
822 &user_sgpr_info, &args,
823 &desc_sets);
824 declare_vs_specific_input_sgprs(ctx, stage,
825 has_previous_stage,
826 previous_stage, &args);
827
828 add_arg(&args, ARG_SGPR, ctx->ac.i32,
829 &ctx->ls_out_layout);
830
831 add_arg(&args, ARG_SGPR, ctx->ac.i32,
832 &ctx->tcs_offchip_layout);
833 add_arg(&args, ARG_SGPR, ctx->ac.i32,
834 &ctx->tcs_out_offsets);
835 add_arg(&args, ARG_SGPR, ctx->ac.i32,
836 &ctx->tcs_out_layout);
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_in_layout);
839 if (needs_view_index)
840 add_arg(&args, ARG_SGPR, ctx->ac.i32,
841 &ctx->abi.view_index);
842
843 add_arg(&args, ARG_VGPR, ctx->ac.i32,
844 &ctx->abi.tcs_patch_id);
845 add_arg(&args, ARG_VGPR, ctx->ac.i32,
846 &ctx->abi.tcs_rel_ids);
847
848 declare_vs_input_vgprs(ctx, &args);
849 } else {
850 declare_global_input_sgprs(ctx, stage,
851 has_previous_stage,
852 previous_stage,
853 &user_sgpr_info, &args,
854 &desc_sets);
855
856 add_arg(&args, ARG_SGPR, ctx->ac.i32,
857 &ctx->tcs_offchip_layout);
858 add_arg(&args, ARG_SGPR, ctx->ac.i32,
859 &ctx->tcs_out_offsets);
860 add_arg(&args, ARG_SGPR, ctx->ac.i32,
861 &ctx->tcs_out_layout);
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_in_layout);
864 if (needs_view_index)
865 add_arg(&args, ARG_SGPR, ctx->ac.i32,
866 &ctx->abi.view_index);
867
868 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
869 add_arg(&args, ARG_SGPR, ctx->ac.i32,
870 &ctx->tess_factor_offset);
871 add_arg(&args, ARG_VGPR, ctx->ac.i32,
872 &ctx->abi.tcs_patch_id);
873 add_arg(&args, ARG_VGPR, ctx->ac.i32,
874 &ctx->abi.tcs_rel_ids);
875 }
876 break;
877 case MESA_SHADER_TESS_EVAL:
878 declare_global_input_sgprs(ctx, stage, has_previous_stage,
879 previous_stage, &user_sgpr_info,
880 &args, &desc_sets);
881
882 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
883 if (needs_view_index)
884 add_arg(&args, ARG_SGPR, ctx->ac.i32,
885 &ctx->abi.view_index);
886
887 if (ctx->options->key.tes.as_es) {
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
889 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->es2gs_offset);
892 } else {
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895 }
896 declare_tes_input_vgprs(ctx, &args);
897 break;
898 case MESA_SHADER_GEOMETRY:
899 if (has_previous_stage) {
900 // First 6 system regs
901 add_arg(&args, ARG_SGPR, ctx->ac.i32,
902 &ctx->gs2vs_offset);
903 add_arg(&args, ARG_SGPR, ctx->ac.i32,
904 &ctx->merged_wave_info);
905 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
906
907 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
908 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
909 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
910
911 declare_global_input_sgprs(ctx, stage,
912 has_previous_stage,
913 previous_stage,
914 &user_sgpr_info, &args,
915 &desc_sets);
916
917 if (previous_stage == MESA_SHADER_TESS_EVAL) {
918 add_arg(&args, ARG_SGPR, ctx->ac.i32,
919 &ctx->tcs_offchip_layout);
920 } else {
921 declare_vs_specific_input_sgprs(ctx, stage,
922 has_previous_stage,
923 previous_stage,
924 &args);
925 }
926
927 add_arg(&args, ARG_SGPR, ctx->ac.i32,
928 &ctx->gsvs_ring_stride);
929 add_arg(&args, ARG_SGPR, ctx->ac.i32,
930 &ctx->gsvs_num_entries);
931 if (needs_view_index)
932 add_arg(&args, ARG_SGPR, ctx->ac.i32,
933 &ctx->abi.view_index);
934
935 add_arg(&args, ARG_VGPR, ctx->ac.i32,
936 &ctx->gs_vtx_offset[0]);
937 add_arg(&args, ARG_VGPR, ctx->ac.i32,
938 &ctx->gs_vtx_offset[2]);
939 add_arg(&args, ARG_VGPR, ctx->ac.i32,
940 &ctx->abi.gs_prim_id);
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->abi.gs_invocation_id);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[4]);
945
946 if (previous_stage == MESA_SHADER_VERTEX) {
947 declare_vs_input_vgprs(ctx, &args);
948 } else {
949 declare_tes_input_vgprs(ctx, &args);
950 }
951 } else {
952 declare_global_input_sgprs(ctx, stage,
953 has_previous_stage,
954 previous_stage,
955 &user_sgpr_info, &args,
956 &desc_sets);
957
958 add_arg(&args, ARG_SGPR, ctx->ac.i32,
959 &ctx->gsvs_ring_stride);
960 add_arg(&args, ARG_SGPR, ctx->ac.i32,
961 &ctx->gsvs_num_entries);
962 if (needs_view_index)
963 add_arg(&args, ARG_SGPR, ctx->ac.i32,
964 &ctx->abi.view_index);
965
966 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
967 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
968 add_arg(&args, ARG_VGPR, ctx->ac.i32,
969 &ctx->gs_vtx_offset[0]);
970 add_arg(&args, ARG_VGPR, ctx->ac.i32,
971 &ctx->gs_vtx_offset[1]);
972 add_arg(&args, ARG_VGPR, ctx->ac.i32,
973 &ctx->abi.gs_prim_id);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[2]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[3]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->gs_vtx_offset[4]);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[5]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->abi.gs_invocation_id);
984 }
985 break;
986 case MESA_SHADER_FRAGMENT:
987 declare_global_input_sgprs(ctx, stage, has_previous_stage,
988 previous_stage, &user_sgpr_info,
989 &args, &desc_sets);
990
991 if (ctx->shader_info->info.ps.needs_sample_positions)
992 add_arg(&args, ARG_SGPR, ctx->ac.i32,
993 &ctx->sample_pos_offset);
994
995 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
996 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
997 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
998 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
999 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1000 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1001 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1003 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1004 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1005 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1006 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1007 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1008 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1009 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1010 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1011 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1012 break;
1013 default:
1014 unreachable("Shader stage not implemented");
1015 }
1016
1017 ctx->main_function = create_llvm_function(
1018 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1019 ctx->max_workgroup_size,
1020 ctx->options->unsafe_math);
1021 set_llvm_calling_convention(ctx->main_function, stage);
1022
1023
1024 ctx->shader_info->num_input_vgprs = 0;
1025 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1026
1027 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1028
1029 if (ctx->stage != MESA_SHADER_FRAGMENT)
1030 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1031
1032 assign_arguments(ctx->main_function, &args);
1033
1034 user_sgpr_idx = 0;
1035
1036 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1037 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1038 &user_sgpr_idx, 2);
1039 if (ctx->options->supports_spill) {
1040 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1041 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1042 NULL, 0, AC_FUNC_ATTR_READNONE);
1043 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1044 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1045 }
1046 }
1047
1048 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1049 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1050 if (has_previous_stage)
1051 user_sgpr_idx = 0;
1052
1053 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1054 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1055
1056 switch (stage) {
1057 case MESA_SHADER_COMPUTE:
1058 if (ctx->shader_info->info.cs.uses_grid_size) {
1059 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1060 &user_sgpr_idx, 3);
1061 }
1062 break;
1063 case MESA_SHADER_VERTEX:
1064 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1065 previous_stage, &user_sgpr_idx);
1066 if (ctx->abi.view_index)
1067 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1068 if (ctx->options->key.vs.as_ls) {
1069 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1070 &user_sgpr_idx, 1);
1071 }
1072 if (ctx->options->key.vs.as_ls)
1073 ac_declare_lds_as_pointer(&ctx->ac);
1074 break;
1075 case MESA_SHADER_TESS_CTRL:
1076 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1077 previous_stage, &user_sgpr_idx);
1078 if (has_previous_stage)
1079 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1080 &user_sgpr_idx, 1);
1081 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1082 if (ctx->abi.view_index)
1083 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1084 ac_declare_lds_as_pointer(&ctx->ac);
1085 break;
1086 case MESA_SHADER_TESS_EVAL:
1087 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1088 if (ctx->abi.view_index)
1089 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1090 break;
1091 case MESA_SHADER_GEOMETRY:
1092 if (has_previous_stage) {
1093 if (previous_stage == MESA_SHADER_VERTEX)
1094 set_vs_specific_input_locs(ctx, stage,
1095 has_previous_stage,
1096 previous_stage,
1097 &user_sgpr_idx);
1098 else
1099 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1100 &user_sgpr_idx, 1);
1101 }
1102 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1103 &user_sgpr_idx, 2);
1104 if (ctx->abi.view_index)
1105 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1106 if (has_previous_stage)
1107 ac_declare_lds_as_pointer(&ctx->ac);
1108 break;
1109 case MESA_SHADER_FRAGMENT:
1110 if (ctx->shader_info->info.ps.needs_sample_positions) {
1111 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1112 &user_sgpr_idx, 1);
1113 }
1114 break;
1115 default:
1116 unreachable("Shader stage not implemented");
1117 }
1118
1119 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1120 }
1121
1122 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1123 LLVMValueRef value, unsigned count)
1124 {
1125 unsigned num_components = ac_get_llvm_num_components(value);
1126 if (count == num_components)
1127 return value;
1128
1129 LLVMValueRef masks[] = {
1130 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1131 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1132
1133 if (count == 1)
1134 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1135 "");
1136
1137 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1138 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1139 }
1140
1141 static void
1142 build_store_values_extended(struct ac_llvm_context *ac,
1143 LLVMValueRef *values,
1144 unsigned value_count,
1145 unsigned value_stride,
1146 LLVMValueRef vec)
1147 {
1148 LLVMBuilderRef builder = ac->builder;
1149 unsigned i;
1150
1151 for (i = 0; i < value_count; i++) {
1152 LLVMValueRef ptr = values[i * value_stride];
1153 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1154 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1155 LLVMBuildStore(builder, value, ptr);
1156 }
1157 }
1158
1159 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1160 const nir_ssa_def *def)
1161 {
1162 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1163 if (def->num_components > 1) {
1164 type = LLVMVectorType(type, def->num_components);
1165 }
1166 return type;
1167 }
1168
1169 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1170 {
1171 assert(src.is_ssa);
1172 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1173 return (LLVMValueRef)entry->data;
1174 }
1175
1176 static LLVMValueRef
1177 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1178 {
1179 LLVMValueRef ptr = get_src(ctx, src);
1180 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1181 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1182
1183 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1184 LLVMPointerType(ctx->ac.i32, addr_space), "");
1185 }
1186
1187 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1188 const struct nir_block *b)
1189 {
1190 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1191 return (LLVMBasicBlockRef)entry->data;
1192 }
1193
1194 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1195 nir_alu_src src,
1196 unsigned num_components)
1197 {
1198 LLVMValueRef value = get_src(ctx, src.src);
1199 bool need_swizzle = false;
1200
1201 assert(value);
1202 LLVMTypeRef type = LLVMTypeOf(value);
1203 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1204 ? LLVMGetVectorSize(type)
1205 : 1;
1206
1207 for (unsigned i = 0; i < num_components; ++i) {
1208 assert(src.swizzle[i] < src_components);
1209 if (src.swizzle[i] != i)
1210 need_swizzle = true;
1211 }
1212
1213 if (need_swizzle || num_components != src_components) {
1214 LLVMValueRef masks[] = {
1215 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1216 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1217 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1218 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1219
1220 if (src_components > 1 && num_components == 1) {
1221 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1222 masks[0], "");
1223 } else if (src_components == 1 && num_components > 1) {
1224 LLVMValueRef values[] = {value, value, value, value};
1225 value = ac_build_gather_values(&ctx->ac, values, num_components);
1226 } else {
1227 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1228 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1229 swizzle, "");
1230 }
1231 }
1232 assert(!src.negate);
1233 assert(!src.abs);
1234 return value;
1235 }
1236
1237 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1238 LLVMIntPredicate pred, LLVMValueRef src0,
1239 LLVMValueRef src1)
1240 {
1241 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1242 return LLVMBuildSelect(ctx->builder, result,
1243 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1244 ctx->i32_0, "");
1245 }
1246
1247 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1248 LLVMRealPredicate pred, LLVMValueRef src0,
1249 LLVMValueRef src1)
1250 {
1251 LLVMValueRef result;
1252 src0 = ac_to_float(ctx, src0);
1253 src1 = ac_to_float(ctx, src1);
1254 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1255 return LLVMBuildSelect(ctx->builder, result,
1256 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1257 ctx->i32_0, "");
1258 }
1259
1260 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1261 const char *intrin,
1262 LLVMTypeRef result_type,
1263 LLVMValueRef src0)
1264 {
1265 char name[64];
1266 LLVMValueRef params[] = {
1267 ac_to_float(ctx, src0),
1268 };
1269
1270 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1271 ac_get_elem_bits(ctx, result_type));
1272 assert(length < sizeof(name));
1273 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1274 }
1275
1276 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1277 const char *intrin,
1278 LLVMTypeRef result_type,
1279 LLVMValueRef src0, LLVMValueRef src1)
1280 {
1281 char name[64];
1282 LLVMValueRef params[] = {
1283 ac_to_float(ctx, src0),
1284 ac_to_float(ctx, src1),
1285 };
1286
1287 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1288 ac_get_elem_bits(ctx, result_type));
1289 assert(length < sizeof(name));
1290 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1291 }
1292
1293 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1294 const char *intrin,
1295 LLVMTypeRef result_type,
1296 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1297 {
1298 char name[64];
1299 LLVMValueRef params[] = {
1300 ac_to_float(ctx, src0),
1301 ac_to_float(ctx, src1),
1302 ac_to_float(ctx, src2),
1303 };
1304
1305 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1306 ac_get_elem_bits(ctx, result_type));
1307 assert(length < sizeof(name));
1308 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1309 }
1310
1311 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1312 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1313 {
1314 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1315 ctx->i32_0, "");
1316 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1317 }
1318
1319 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1320 LLVMIntPredicate pred,
1321 LLVMValueRef src0, LLVMValueRef src1)
1322 {
1323 return LLVMBuildSelect(ctx->builder,
1324 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1325 src0,
1326 src1, "");
1327
1328 }
1329 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1330 LLVMValueRef src0)
1331 {
1332 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1333 LLVMBuildNeg(ctx->builder, src0, ""));
1334 }
1335
1336 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1337 LLVMValueRef src0,
1338 unsigned bitsize)
1339 {
1340 LLVMValueRef cmp, val, zero, one;
1341 LLVMTypeRef type;
1342
1343 if (bitsize == 32) {
1344 type = ctx->f32;
1345 zero = ctx->f32_0;
1346 one = ctx->f32_1;
1347 } else {
1348 type = ctx->f64;
1349 zero = ctx->f64_0;
1350 one = ctx->f64_1;
1351 }
1352
1353 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1354 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1355 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1356 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1357 return val;
1358 }
1359
1360 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1361 LLVMValueRef src0, unsigned bitsize)
1362 {
1363 LLVMValueRef cmp, val, zero, one;
1364 LLVMTypeRef type;
1365
1366 if (bitsize == 32) {
1367 type = ctx->i32;
1368 zero = ctx->i32_0;
1369 one = ctx->i32_1;
1370 } else {
1371 type = ctx->i64;
1372 zero = ctx->i64_0;
1373 one = ctx->i64_1;
1374 }
1375
1376 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1377 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1378 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1379 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1380 return val;
1381 }
1382
1383 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1384 LLVMValueRef src0, unsigned bitsize)
1385 {
1386 LLVMTypeRef type;
1387 char *intr;
1388
1389 if (bitsize == 32) {
1390 intr = "llvm.floor.f32";
1391 type = ctx->f32;
1392 } else {
1393 intr = "llvm.floor.f64";
1394 type = ctx->f64;
1395 }
1396
1397 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1398 LLVMValueRef params[] = {
1399 fsrc0,
1400 };
1401 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1402 AC_FUNC_ATTR_READNONE);
1403 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1404 }
1405
1406 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1407 const char *intrin,
1408 LLVMValueRef src0, LLVMValueRef src1)
1409 {
1410 LLVMTypeRef ret_type;
1411 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1412 LLVMValueRef res;
1413 LLVMValueRef params[] = { src0, src1 };
1414 ret_type = LLVMStructTypeInContext(ctx->context, types,
1415 2, true);
1416
1417 res = ac_build_intrinsic(ctx, intrin, ret_type,
1418 params, 2, AC_FUNC_ATTR_READNONE);
1419
1420 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1421 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1422 return res;
1423 }
1424
1425 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1426 LLVMValueRef src0)
1427 {
1428 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1429 }
1430
1431 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1432 LLVMValueRef src0)
1433 {
1434 src0 = ac_to_float(ctx, src0);
1435 return LLVMBuildSExt(ctx->builder,
1436 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1437 ctx->i32, "");
1438 }
1439
1440 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1441 LLVMValueRef src0,
1442 unsigned bitsize)
1443 {
1444 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1445
1446 if (bitsize == 32)
1447 return result;
1448
1449 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1450 }
1451
1452 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1453 LLVMValueRef src0)
1454 {
1455 return LLVMBuildSExt(ctx->builder,
1456 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1457 ctx->i32, "");
1458 }
1459
1460 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1461 LLVMValueRef src0)
1462 {
1463 LLVMValueRef result;
1464 LLVMValueRef cond = NULL;
1465
1466 src0 = ac_to_float(ctx, src0);
1467 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1468
1469 if (ctx->chip_class >= VI) {
1470 LLVMValueRef args[2];
1471 /* Check if the result is a denormal - and flush to 0 if so. */
1472 args[0] = result;
1473 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1474 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1475 }
1476
1477 /* need to convert back up to f32 */
1478 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1479
1480 if (ctx->chip_class >= VI)
1481 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1482 else {
1483 /* for SI/CIK */
1484 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1485 * so compare the result and flush to 0 if it's smaller.
1486 */
1487 LLVMValueRef temp, cond2;
1488 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1489 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1490 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1491 temp, "");
1492 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1493 temp, ctx->f32_0, "");
1494 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1495 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1496 }
1497 return result;
1498 }
1499
1500 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1501 LLVMValueRef src0, LLVMValueRef src1)
1502 {
1503 LLVMValueRef dst64, result;
1504 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1505 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1506
1507 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1508 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1509 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1510 return result;
1511 }
1512
1513 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1514 LLVMValueRef src0, LLVMValueRef src1)
1515 {
1516 LLVMValueRef dst64, result;
1517 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1518 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1519
1520 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1521 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1522 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1523 return result;
1524 }
1525
1526 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1527 bool is_signed,
1528 const LLVMValueRef srcs[3])
1529 {
1530 LLVMValueRef result;
1531 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1532
1533 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1534 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1535 return result;
1536 }
1537
1538 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1539 LLVMValueRef src0, LLVMValueRef src1,
1540 LLVMValueRef src2, LLVMValueRef src3)
1541 {
1542 LLVMValueRef bfi_args[3], result;
1543
1544 bfi_args[0] = LLVMBuildShl(ctx->builder,
1545 LLVMBuildSub(ctx->builder,
1546 LLVMBuildShl(ctx->builder,
1547 ctx->i32_1,
1548 src3, ""),
1549 ctx->i32_1, ""),
1550 src2, "");
1551 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1552 bfi_args[2] = src0;
1553
1554 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1555
1556 /* Calculate:
1557 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1558 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1559 */
1560 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1561 LLVMBuildAnd(ctx->builder, bfi_args[0],
1562 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1563
1564 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1565 return result;
1566 }
1567
1568 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1569 LLVMValueRef src0)
1570 {
1571 LLVMValueRef comp[2];
1572
1573 src0 = ac_to_float(ctx, src0);
1574 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1575 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1576
1577 return ac_build_cvt_pkrtz_f16(ctx, comp);
1578 }
1579
1580 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1581 LLVMValueRef src0)
1582 {
1583 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1584 LLVMValueRef temps[2], result, val;
1585 int i;
1586
1587 for (i = 0; i < 2; i++) {
1588 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1589 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1590 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1591 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1592 }
1593
1594 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1595 ctx->i32_0, "");
1596 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1597 ctx->i32_1, "");
1598 return result;
1599 }
1600
1601 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1602 nir_op op,
1603 LLVMValueRef src0)
1604 {
1605 unsigned mask;
1606 int idx;
1607 LLVMValueRef result;
1608
1609 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1610 mask = AC_TID_MASK_LEFT;
1611 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1612 mask = AC_TID_MASK_TOP;
1613 else
1614 mask = AC_TID_MASK_TOP_LEFT;
1615
1616 /* for DDX we want to next X pixel, DDY next Y pixel. */
1617 if (op == nir_op_fddx_fine ||
1618 op == nir_op_fddx_coarse ||
1619 op == nir_op_fddx)
1620 idx = 1;
1621 else
1622 idx = 2;
1623
1624 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1625 return result;
1626 }
1627
1628 /*
1629 * this takes an I,J coordinate pair,
1630 * and works out the X and Y derivatives.
1631 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1632 */
1633 static LLVMValueRef emit_ddxy_interp(
1634 struct ac_nir_context *ctx,
1635 LLVMValueRef interp_ij)
1636 {
1637 LLVMValueRef result[4], a;
1638 unsigned i;
1639
1640 for (i = 0; i < 2; i++) {
1641 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1642 LLVMConstInt(ctx->ac.i32, i, false), "");
1643 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1644 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1645 }
1646 return ac_build_gather_values(&ctx->ac, result, 4);
1647 }
1648
1649 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1650 {
1651 LLVMValueRef src[4], result = NULL;
1652 unsigned num_components = instr->dest.dest.ssa.num_components;
1653 unsigned src_components;
1654 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1655
1656 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1657 switch (instr->op) {
1658 case nir_op_vec2:
1659 case nir_op_vec3:
1660 case nir_op_vec4:
1661 src_components = 1;
1662 break;
1663 case nir_op_pack_half_2x16:
1664 src_components = 2;
1665 break;
1666 case nir_op_unpack_half_2x16:
1667 src_components = 1;
1668 break;
1669 default:
1670 src_components = num_components;
1671 break;
1672 }
1673 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1674 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1675
1676 switch (instr->op) {
1677 case nir_op_fmov:
1678 case nir_op_imov:
1679 result = src[0];
1680 break;
1681 case nir_op_fneg:
1682 src[0] = ac_to_float(&ctx->ac, src[0]);
1683 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1684 break;
1685 case nir_op_ineg:
1686 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1687 break;
1688 case nir_op_inot:
1689 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1690 break;
1691 case nir_op_iadd:
1692 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1693 break;
1694 case nir_op_fadd:
1695 src[0] = ac_to_float(&ctx->ac, src[0]);
1696 src[1] = ac_to_float(&ctx->ac, src[1]);
1697 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1698 break;
1699 case nir_op_fsub:
1700 src[0] = ac_to_float(&ctx->ac, src[0]);
1701 src[1] = ac_to_float(&ctx->ac, src[1]);
1702 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1703 break;
1704 case nir_op_isub:
1705 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1706 break;
1707 case nir_op_imul:
1708 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1709 break;
1710 case nir_op_imod:
1711 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_umod:
1714 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_fmod:
1717 src[0] = ac_to_float(&ctx->ac, src[0]);
1718 src[1] = ac_to_float(&ctx->ac, src[1]);
1719 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1720 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1721 ac_to_float_type(&ctx->ac, def_type), result);
1722 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1723 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1724 break;
1725 case nir_op_frem:
1726 src[0] = ac_to_float(&ctx->ac, src[0]);
1727 src[1] = ac_to_float(&ctx->ac, src[1]);
1728 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1729 break;
1730 case nir_op_irem:
1731 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1732 break;
1733 case nir_op_idiv:
1734 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1735 break;
1736 case nir_op_udiv:
1737 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_fmul:
1740 src[0] = ac_to_float(&ctx->ac, src[0]);
1741 src[1] = ac_to_float(&ctx->ac, src[1]);
1742 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1743 break;
1744 case nir_op_frcp:
1745 src[0] = ac_to_float(&ctx->ac, src[0]);
1746 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1747 src[0]);
1748 break;
1749 case nir_op_iand:
1750 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1751 break;
1752 case nir_op_ior:
1753 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1754 break;
1755 case nir_op_ixor:
1756 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1757 break;
1758 case nir_op_ishl:
1759 result = LLVMBuildShl(ctx->ac.builder, src[0],
1760 LLVMBuildZExt(ctx->ac.builder, src[1],
1761 LLVMTypeOf(src[0]), ""),
1762 "");
1763 break;
1764 case nir_op_ishr:
1765 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1766 LLVMBuildZExt(ctx->ac.builder, src[1],
1767 LLVMTypeOf(src[0]), ""),
1768 "");
1769 break;
1770 case nir_op_ushr:
1771 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1772 LLVMBuildZExt(ctx->ac.builder, src[1],
1773 LLVMTypeOf(src[0]), ""),
1774 "");
1775 break;
1776 case nir_op_ilt:
1777 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1778 break;
1779 case nir_op_ine:
1780 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1781 break;
1782 case nir_op_ieq:
1783 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1784 break;
1785 case nir_op_ige:
1786 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1787 break;
1788 case nir_op_ult:
1789 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1790 break;
1791 case nir_op_uge:
1792 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1793 break;
1794 case nir_op_feq:
1795 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1796 break;
1797 case nir_op_fne:
1798 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1799 break;
1800 case nir_op_flt:
1801 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1802 break;
1803 case nir_op_fge:
1804 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1805 break;
1806 case nir_op_fabs:
1807 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1808 ac_to_float_type(&ctx->ac, def_type), src[0]);
1809 break;
1810 case nir_op_iabs:
1811 result = emit_iabs(&ctx->ac, src[0]);
1812 break;
1813 case nir_op_imax:
1814 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1815 break;
1816 case nir_op_imin:
1817 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1818 break;
1819 case nir_op_umax:
1820 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1821 break;
1822 case nir_op_umin:
1823 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1824 break;
1825 case nir_op_isign:
1826 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1827 break;
1828 case nir_op_fsign:
1829 src[0] = ac_to_float(&ctx->ac, src[0]);
1830 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1831 break;
1832 case nir_op_ffloor:
1833 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1834 ac_to_float_type(&ctx->ac, def_type), src[0]);
1835 break;
1836 case nir_op_ftrunc:
1837 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1838 ac_to_float_type(&ctx->ac, def_type), src[0]);
1839 break;
1840 case nir_op_fceil:
1841 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1842 ac_to_float_type(&ctx->ac, def_type), src[0]);
1843 break;
1844 case nir_op_fround_even:
1845 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1846 ac_to_float_type(&ctx->ac, def_type),src[0]);
1847 break;
1848 case nir_op_ffract:
1849 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1850 break;
1851 case nir_op_fsin:
1852 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1853 ac_to_float_type(&ctx->ac, def_type), src[0]);
1854 break;
1855 case nir_op_fcos:
1856 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1857 ac_to_float_type(&ctx->ac, def_type), src[0]);
1858 break;
1859 case nir_op_fsqrt:
1860 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1861 ac_to_float_type(&ctx->ac, def_type), src[0]);
1862 break;
1863 case nir_op_fexp2:
1864 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1865 ac_to_float_type(&ctx->ac, def_type), src[0]);
1866 break;
1867 case nir_op_flog2:
1868 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1869 ac_to_float_type(&ctx->ac, def_type), src[0]);
1870 break;
1871 case nir_op_frsq:
1872 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1873 ac_to_float_type(&ctx->ac, def_type), src[0]);
1874 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1875 result);
1876 break;
1877 case nir_op_fpow:
1878 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1879 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1880 break;
1881 case nir_op_fmax:
1882 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1883 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1884 if (ctx->ac.chip_class < GFX9 &&
1885 instr->dest.dest.ssa.bit_size == 32) {
1886 /* Only pre-GFX9 chips do not flush denorms. */
1887 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1888 ac_to_float_type(&ctx->ac, def_type),
1889 result);
1890 }
1891 break;
1892 case nir_op_fmin:
1893 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1894 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1895 if (ctx->ac.chip_class < GFX9 &&
1896 instr->dest.dest.ssa.bit_size == 32) {
1897 /* Only pre-GFX9 chips do not flush denorms. */
1898 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1899 ac_to_float_type(&ctx->ac, def_type),
1900 result);
1901 }
1902 break;
1903 case nir_op_ffma:
1904 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1905 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1906 break;
1907 case nir_op_ibitfield_extract:
1908 result = emit_bitfield_extract(&ctx->ac, true, src);
1909 break;
1910 case nir_op_ubitfield_extract:
1911 result = emit_bitfield_extract(&ctx->ac, false, src);
1912 break;
1913 case nir_op_bitfield_insert:
1914 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1915 break;
1916 case nir_op_bitfield_reverse:
1917 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1918 break;
1919 case nir_op_bit_count:
1920 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1921 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1922 else {
1923 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1924 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1925 }
1926 break;
1927 case nir_op_vec2:
1928 case nir_op_vec3:
1929 case nir_op_vec4:
1930 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1931 src[i] = ac_to_integer(&ctx->ac, src[i]);
1932 result = ac_build_gather_values(&ctx->ac, src, num_components);
1933 break;
1934 case nir_op_f2i32:
1935 case nir_op_f2i64:
1936 src[0] = ac_to_float(&ctx->ac, src[0]);
1937 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1938 break;
1939 case nir_op_f2u32:
1940 case nir_op_f2u64:
1941 src[0] = ac_to_float(&ctx->ac, src[0]);
1942 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1943 break;
1944 case nir_op_i2f32:
1945 case nir_op_i2f64:
1946 src[0] = ac_to_integer(&ctx->ac, src[0]);
1947 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1948 break;
1949 case nir_op_u2f32:
1950 case nir_op_u2f64:
1951 src[0] = ac_to_integer(&ctx->ac, src[0]);
1952 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1953 break;
1954 case nir_op_f2f64:
1955 src[0] = ac_to_float(&ctx->ac, src[0]);
1956 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1957 break;
1958 case nir_op_f2f32:
1959 src[0] = ac_to_float(&ctx->ac, src[0]);
1960 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1961 break;
1962 case nir_op_u2u32:
1963 case nir_op_u2u64:
1964 src[0] = ac_to_integer(&ctx->ac, src[0]);
1965 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1966 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1967 else
1968 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1969 break;
1970 case nir_op_i2i32:
1971 case nir_op_i2i64:
1972 src[0] = ac_to_integer(&ctx->ac, src[0]);
1973 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1974 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1975 else
1976 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1977 break;
1978 case nir_op_bcsel:
1979 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1980 break;
1981 case nir_op_find_lsb:
1982 src[0] = ac_to_integer(&ctx->ac, src[0]);
1983 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1984 break;
1985 case nir_op_ufind_msb:
1986 src[0] = ac_to_integer(&ctx->ac, src[0]);
1987 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1988 break;
1989 case nir_op_ifind_msb:
1990 src[0] = ac_to_integer(&ctx->ac, src[0]);
1991 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1992 break;
1993 case nir_op_uadd_carry:
1994 src[0] = ac_to_integer(&ctx->ac, src[0]);
1995 src[1] = ac_to_integer(&ctx->ac, src[1]);
1996 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1997 break;
1998 case nir_op_usub_borrow:
1999 src[0] = ac_to_integer(&ctx->ac, src[0]);
2000 src[1] = ac_to_integer(&ctx->ac, src[1]);
2001 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2002 break;
2003 case nir_op_b2f:
2004 result = emit_b2f(&ctx->ac, src[0]);
2005 break;
2006 case nir_op_f2b:
2007 result = emit_f2b(&ctx->ac, src[0]);
2008 break;
2009 case nir_op_b2i:
2010 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2011 break;
2012 case nir_op_i2b:
2013 src[0] = ac_to_integer(&ctx->ac, src[0]);
2014 result = emit_i2b(&ctx->ac, src[0]);
2015 break;
2016 case nir_op_fquantize2f16:
2017 result = emit_f2f16(&ctx->ac, src[0]);
2018 break;
2019 case nir_op_umul_high:
2020 src[0] = ac_to_integer(&ctx->ac, src[0]);
2021 src[1] = ac_to_integer(&ctx->ac, src[1]);
2022 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2023 break;
2024 case nir_op_imul_high:
2025 src[0] = ac_to_integer(&ctx->ac, src[0]);
2026 src[1] = ac_to_integer(&ctx->ac, src[1]);
2027 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2028 break;
2029 case nir_op_pack_half_2x16:
2030 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2031 break;
2032 case nir_op_unpack_half_2x16:
2033 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2034 break;
2035 case nir_op_fddx:
2036 case nir_op_fddy:
2037 case nir_op_fddx_fine:
2038 case nir_op_fddy_fine:
2039 case nir_op_fddx_coarse:
2040 case nir_op_fddy_coarse:
2041 result = emit_ddxy(ctx, instr->op, src[0]);
2042 break;
2043
2044 case nir_op_unpack_64_2x32_split_x: {
2045 assert(ac_get_llvm_num_components(src[0]) == 1);
2046 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2047 ctx->ac.v2i32,
2048 "");
2049 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2050 ctx->ac.i32_0, "");
2051 break;
2052 }
2053
2054 case nir_op_unpack_64_2x32_split_y: {
2055 assert(ac_get_llvm_num_components(src[0]) == 1);
2056 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2057 ctx->ac.v2i32,
2058 "");
2059 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2060 ctx->ac.i32_1, "");
2061 break;
2062 }
2063
2064 case nir_op_pack_64_2x32_split: {
2065 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2066 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2067 src[0], ctx->ac.i32_0, "");
2068 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2069 src[1], ctx->ac.i32_1, "");
2070 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2071 break;
2072 }
2073
2074 default:
2075 fprintf(stderr, "Unknown NIR alu instr: ");
2076 nir_print_instr(&instr->instr, stderr);
2077 fprintf(stderr, "\n");
2078 abort();
2079 }
2080
2081 if (result) {
2082 assert(instr->dest.dest.is_ssa);
2083 result = ac_to_integer(&ctx->ac, result);
2084 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2085 result);
2086 }
2087 }
2088
2089 static void visit_load_const(struct ac_nir_context *ctx,
2090 const nir_load_const_instr *instr)
2091 {
2092 LLVMValueRef values[4], value = NULL;
2093 LLVMTypeRef element_type =
2094 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2095
2096 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2097 switch (instr->def.bit_size) {
2098 case 32:
2099 values[i] = LLVMConstInt(element_type,
2100 instr->value.u32[i], false);
2101 break;
2102 case 64:
2103 values[i] = LLVMConstInt(element_type,
2104 instr->value.u64[i], false);
2105 break;
2106 default:
2107 fprintf(stderr,
2108 "unsupported nir load_const bit_size: %d\n",
2109 instr->def.bit_size);
2110 abort();
2111 }
2112 }
2113 if (instr->def.num_components > 1) {
2114 value = LLVMConstVector(values, instr->def.num_components);
2115 } else
2116 value = values[0];
2117
2118 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2119 }
2120
2121 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2122 LLVMTypeRef type)
2123 {
2124 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2125 return LLVMBuildBitCast(ctx->builder, ptr,
2126 LLVMPointerType(type, addr_space), "");
2127 }
2128
2129 static LLVMValueRef
2130 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2131 {
2132 LLVMValueRef size =
2133 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2134 LLVMConstInt(ctx->ac.i32, 2, false), "");
2135
2136 /* VI only */
2137 if (ctx->ac.chip_class == VI && in_elements) {
2138 /* On VI, the descriptor contains the size in bytes,
2139 * but TXQ must return the size in elements.
2140 * The stride is always non-zero for resources using TXQ.
2141 */
2142 LLVMValueRef stride =
2143 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2144 ctx->ac.i32_1, "");
2145 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2146 LLVMConstInt(ctx->ac.i32, 16, false), "");
2147 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2148 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2149
2150 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2151 }
2152 return size;
2153 }
2154
2155 /**
2156 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2157 * intrinsic names).
2158 */
2159 static void build_int_type_name(
2160 LLVMTypeRef type,
2161 char *buf, unsigned bufsize)
2162 {
2163 assert(bufsize >= 6);
2164
2165 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2166 snprintf(buf, bufsize, "v%ui32",
2167 LLVMGetVectorSize(type));
2168 else
2169 strcpy(buf, "i32");
2170 }
2171
2172 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2173 struct ac_image_args *args,
2174 const nir_tex_instr *instr)
2175 {
2176 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2177 LLVMValueRef coord = args->addr;
2178 LLVMValueRef half_texel[2];
2179 LLVMValueRef compare_cube_wa = NULL;
2180 LLVMValueRef result;
2181 int c;
2182 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2183
2184 //TODO Rect
2185 {
2186 struct ac_image_args txq_args = { 0 };
2187
2188 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2189 txq_args.opcode = ac_image_get_resinfo;
2190 txq_args.dmask = 0xf;
2191 txq_args.addr = ctx->i32_0;
2192 txq_args.resource = args->resource;
2193 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2194
2195 for (c = 0; c < 2; c++) {
2196 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2197 LLVMConstInt(ctx->i32, c, false), "");
2198 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2199 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2200 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2201 LLVMConstReal(ctx->f32, -0.5), "");
2202 }
2203 }
2204
2205 LLVMValueRef orig_coords = args->addr;
2206
2207 for (c = 0; c < 2; c++) {
2208 LLVMValueRef tmp;
2209 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2210 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2211 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2212 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2213 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2214 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2215 }
2216
2217
2218 /*
2219 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2220 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2221 * workaround by sampling using a scaled type and converting.
2222 * This is taken from amdgpu-pro shaders.
2223 */
2224 /* NOTE this produces some ugly code compared to amdgpu-pro,
2225 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2226 * and then reads them back. -pro generates two selects,
2227 * one s_cmp for the descriptor rewriting
2228 * one v_cmp for the coordinate and result changes.
2229 */
2230 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2231 LLVMValueRef tmp, tmp2;
2232
2233 /* workaround 8/8/8/8 uint/sint cube gather bug */
2234 /* first detect it then change to a scaled read and f2i */
2235 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2236 tmp2 = tmp;
2237
2238 /* extract the DATA_FORMAT */
2239 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2240 LLVMConstInt(ctx->i32, 6, false), false);
2241
2242 /* is the DATA_FORMAT == 8_8_8_8 */
2243 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2244
2245 if (stype == GLSL_TYPE_UINT)
2246 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2247 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2248 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2249 else
2250 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2251 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2252 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2253
2254 /* replace the NUM FORMAT in the descriptor */
2255 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2256 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2257
2258 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2259
2260 /* don't modify the coordinates for this case */
2261 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2262 }
2263 args->addr = coord;
2264 result = ac_build_image_opcode(ctx, args);
2265
2266 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2267 LLVMValueRef tmp, tmp2;
2268
2269 /* if the cube workaround is in place, f2i the result. */
2270 for (c = 0; c < 4; c++) {
2271 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2272 if (stype == GLSL_TYPE_UINT)
2273 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2274 else
2275 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2276 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2277 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2278 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2279 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2280 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2281 }
2282 }
2283 return result;
2284 }
2285
2286 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2287 const nir_tex_instr *instr,
2288 bool lod_is_zero,
2289 struct ac_image_args *args)
2290 {
2291 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2292 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2293
2294 return ac_build_buffer_load_format(&ctx->ac,
2295 args->resource,
2296 args->addr,
2297 ctx->ac.i32_0,
2298 util_last_bit(mask),
2299 false, true);
2300 }
2301
2302 args->opcode = ac_image_sample;
2303 args->compare = instr->is_shadow;
2304
2305 switch (instr->op) {
2306 case nir_texop_txf:
2307 case nir_texop_txf_ms:
2308 case nir_texop_samples_identical:
2309 args->opcode = lod_is_zero ||
2310 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2311 ac_image_load : ac_image_load_mip;
2312 args->compare = false;
2313 args->offset = false;
2314 break;
2315 case nir_texop_txb:
2316 args->bias = true;
2317 break;
2318 case nir_texop_txl:
2319 if (lod_is_zero)
2320 args->level_zero = true;
2321 else
2322 args->lod = true;
2323 break;
2324 case nir_texop_txs:
2325 case nir_texop_query_levels:
2326 args->opcode = ac_image_get_resinfo;
2327 break;
2328 case nir_texop_tex:
2329 if (ctx->stage != MESA_SHADER_FRAGMENT)
2330 args->level_zero = true;
2331 break;
2332 case nir_texop_txd:
2333 args->deriv = true;
2334 break;
2335 case nir_texop_tg4:
2336 args->opcode = ac_image_gather4;
2337 args->level_zero = true;
2338 break;
2339 case nir_texop_lod:
2340 args->opcode = ac_image_get_lod;
2341 args->compare = false;
2342 args->offset = false;
2343 break;
2344 default:
2345 break;
2346 }
2347
2348 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2349 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2350 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2351 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2352 }
2353 }
2354 return ac_build_image_opcode(&ctx->ac, args);
2355 }
2356
2357 static LLVMValueRef
2358 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2359 unsigned desc_set, unsigned binding)
2360 {
2361 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2362 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2363 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2364 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2365 unsigned base_offset = layout->binding[binding].offset;
2366 LLVMValueRef offset, stride;
2367
2368 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2369 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2370 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2371 layout->binding[binding].dynamic_offset_offset;
2372 desc_ptr = ctx->abi.push_constants;
2373 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2374 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2375 } else
2376 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2377
2378 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2379 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2380 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2381
2382 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2383 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2384 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2385
2386 return desc_ptr;
2387 }
2388
2389 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2390 nir_intrinsic_instr *instr)
2391 {
2392 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2393 LLVMValueRef index = get_src(ctx, instr->src[1]);
2394
2395 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2396 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2397 return result;
2398 }
2399
2400 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2401 nir_intrinsic_instr *instr)
2402 {
2403 LLVMValueRef ptr, addr;
2404
2405 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2406 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2407 get_src(ctx, instr->src[0]), "");
2408
2409 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2410 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2411
2412 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2413 }
2414
2415 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2416 const nir_intrinsic_instr *instr)
2417 {
2418 LLVMValueRef index = get_src(ctx, instr->src[0]);
2419
2420 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2421 }
2422
2423 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2424 {
2425 uint32_t new_mask = 0;
2426 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2427 if (mask & (1u << i))
2428 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2429 return new_mask;
2430 }
2431
2432 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2433 unsigned start, unsigned count)
2434 {
2435 LLVMTypeRef type = LLVMTypeOf(src);
2436
2437 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2438 assert(start == 0);
2439 assert(count == 1);
2440 return src;
2441 }
2442
2443 unsigned src_elements = LLVMGetVectorSize(type);
2444 assert(start < src_elements);
2445 assert(start + count <= src_elements);
2446
2447 if (start == 0 && count == src_elements)
2448 return src;
2449
2450 if (count == 1)
2451 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2452
2453 assert(count <= 8);
2454 LLVMValueRef indices[8];
2455 for (unsigned i = 0; i < count; ++i)
2456 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2457
2458 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2459 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2460 }
2461
2462 static void visit_store_ssbo(struct ac_nir_context *ctx,
2463 nir_intrinsic_instr *instr)
2464 {
2465 const char *store_name;
2466 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2467 LLVMTypeRef data_type = ctx->ac.f32;
2468 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2469 int components_32bit = elem_size_mult * instr->num_components;
2470 unsigned writemask = nir_intrinsic_write_mask(instr);
2471 LLVMValueRef base_data, base_offset;
2472 LLVMValueRef params[6];
2473
2474 params[1] = ctx->abi->load_ssbo(ctx->abi,
2475 get_src(ctx, instr->src[1]), true);
2476 params[2] = ctx->ac.i32_0; /* vindex */
2477 params[4] = ctx->ac.i1false; /* glc */
2478 params[5] = ctx->ac.i1false; /* slc */
2479
2480 if (components_32bit > 1)
2481 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2482
2483 writemask = widen_mask(writemask, elem_size_mult);
2484
2485 base_data = ac_to_float(&ctx->ac, src_data);
2486 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2487 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2488 data_type, "");
2489 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2490 while (writemask) {
2491 int start, count;
2492 LLVMValueRef data;
2493 LLVMValueRef offset;
2494
2495 u_bit_scan_consecutive_range(&writemask, &start, &count);
2496
2497 /* Due to an LLVM limitation, split 3-element writes
2498 * into a 2-element and a 1-element write. */
2499 if (count == 3) {
2500 writemask |= 1 << (start + 2);
2501 count = 2;
2502 }
2503
2504 if (count > 4) {
2505 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2506 count = 4;
2507 }
2508
2509 if (count == 4) {
2510 store_name = "llvm.amdgcn.buffer.store.v4f32";
2511 } else if (count == 2) {
2512 store_name = "llvm.amdgcn.buffer.store.v2f32";
2513
2514 } else {
2515 assert(count == 1);
2516 store_name = "llvm.amdgcn.buffer.store.f32";
2517 }
2518 data = extract_vector_range(&ctx->ac, base_data, start, count);
2519
2520 offset = base_offset;
2521 if (start != 0) {
2522 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2523 }
2524 params[0] = data;
2525 params[3] = offset;
2526 ac_build_intrinsic(&ctx->ac, store_name,
2527 ctx->ac.voidt, params, 6, 0);
2528 }
2529 }
2530
2531 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2532 const nir_intrinsic_instr *instr)
2533 {
2534 const char *name;
2535 LLVMValueRef params[6];
2536 int arg_count = 0;
2537
2538 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2539 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2540 }
2541 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2542 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2543 get_src(ctx, instr->src[0]),
2544 true);
2545 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2546 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2547 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2548
2549 switch (instr->intrinsic) {
2550 case nir_intrinsic_ssbo_atomic_add:
2551 name = "llvm.amdgcn.buffer.atomic.add";
2552 break;
2553 case nir_intrinsic_ssbo_atomic_imin:
2554 name = "llvm.amdgcn.buffer.atomic.smin";
2555 break;
2556 case nir_intrinsic_ssbo_atomic_umin:
2557 name = "llvm.amdgcn.buffer.atomic.umin";
2558 break;
2559 case nir_intrinsic_ssbo_atomic_imax:
2560 name = "llvm.amdgcn.buffer.atomic.smax";
2561 break;
2562 case nir_intrinsic_ssbo_atomic_umax:
2563 name = "llvm.amdgcn.buffer.atomic.umax";
2564 break;
2565 case nir_intrinsic_ssbo_atomic_and:
2566 name = "llvm.amdgcn.buffer.atomic.and";
2567 break;
2568 case nir_intrinsic_ssbo_atomic_or:
2569 name = "llvm.amdgcn.buffer.atomic.or";
2570 break;
2571 case nir_intrinsic_ssbo_atomic_xor:
2572 name = "llvm.amdgcn.buffer.atomic.xor";
2573 break;
2574 case nir_intrinsic_ssbo_atomic_exchange:
2575 name = "llvm.amdgcn.buffer.atomic.swap";
2576 break;
2577 case nir_intrinsic_ssbo_atomic_comp_swap:
2578 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2579 break;
2580 default:
2581 abort();
2582 }
2583
2584 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2585 }
2586
2587 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2588 const nir_intrinsic_instr *instr)
2589 {
2590 LLVMValueRef results[2];
2591 int load_components;
2592 int num_components = instr->num_components;
2593 if (instr->dest.ssa.bit_size == 64)
2594 num_components *= 2;
2595
2596 for (int i = 0; i < num_components; i += load_components) {
2597 load_components = MIN2(num_components - i, 4);
2598 const char *load_name;
2599 LLVMTypeRef data_type = ctx->ac.f32;
2600 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2601 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2602
2603 if (load_components == 3)
2604 data_type = LLVMVectorType(ctx->ac.f32, 4);
2605 else if (load_components > 1)
2606 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2607
2608 if (load_components >= 3)
2609 load_name = "llvm.amdgcn.buffer.load.v4f32";
2610 else if (load_components == 2)
2611 load_name = "llvm.amdgcn.buffer.load.v2f32";
2612 else if (load_components == 1)
2613 load_name = "llvm.amdgcn.buffer.load.f32";
2614 else
2615 unreachable("unhandled number of components");
2616
2617 LLVMValueRef params[] = {
2618 ctx->abi->load_ssbo(ctx->abi,
2619 get_src(ctx, instr->src[0]),
2620 false),
2621 ctx->ac.i32_0,
2622 offset,
2623 ctx->ac.i1false,
2624 ctx->ac.i1false,
2625 };
2626
2627 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2628 }
2629
2630 assume(results[0]);
2631 LLVMValueRef ret = results[0];
2632 if (num_components > 4 || num_components == 3) {
2633 LLVMValueRef masks[] = {
2634 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2635 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2636 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2637 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2638 };
2639
2640 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2641 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2642 results[num_components > 4 ? 1 : 0], swizzle, "");
2643 }
2644
2645 return LLVMBuildBitCast(ctx->ac.builder, ret,
2646 get_def_type(ctx, &instr->dest.ssa), "");
2647 }
2648
2649 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2650 const nir_intrinsic_instr *instr)
2651 {
2652 LLVMValueRef ret;
2653 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2654 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2655 int num_components = instr->num_components;
2656
2657 if (ctx->abi->load_ubo)
2658 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2659
2660 if (instr->dest.ssa.bit_size == 64)
2661 num_components *= 2;
2662
2663 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2664 NULL, 0, false, false, true, true);
2665 ret = trim_vector(&ctx->ac, ret, num_components);
2666 return LLVMBuildBitCast(ctx->ac.builder, ret,
2667 get_def_type(ctx, &instr->dest.ssa), "");
2668 }
2669
2670 static void
2671 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2672 bool vs_in, unsigned *vertex_index_out,
2673 LLVMValueRef *vertex_index_ref,
2674 unsigned *const_out, LLVMValueRef *indir_out)
2675 {
2676 unsigned const_offset = 0;
2677 nir_deref *tail = &deref->deref;
2678 LLVMValueRef offset = NULL;
2679
2680 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2681 tail = tail->child;
2682 nir_deref_array *deref_array = nir_deref_as_array(tail);
2683 if (vertex_index_out)
2684 *vertex_index_out = deref_array->base_offset;
2685
2686 if (vertex_index_ref) {
2687 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2688 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2689 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2690 }
2691 *vertex_index_ref = vtx;
2692 }
2693 }
2694
2695 if (deref->var->data.compact) {
2696 assert(tail->child->deref_type == nir_deref_type_array);
2697 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2698 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2699 /* We always lower indirect dereferences for "compact" array vars. */
2700 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2701
2702 const_offset = deref_array->base_offset;
2703 goto out;
2704 }
2705
2706 while (tail->child != NULL) {
2707 const struct glsl_type *parent_type = tail->type;
2708 tail = tail->child;
2709
2710 if (tail->deref_type == nir_deref_type_array) {
2711 nir_deref_array *deref_array = nir_deref_as_array(tail);
2712 LLVMValueRef index, stride, local_offset;
2713 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2714
2715 const_offset += size * deref_array->base_offset;
2716 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2717 continue;
2718
2719 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2720 index = get_src(ctx, deref_array->indirect);
2721 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2722 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2723
2724 if (offset)
2725 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2726 else
2727 offset = local_offset;
2728 } else if (tail->deref_type == nir_deref_type_struct) {
2729 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2730
2731 for (unsigned i = 0; i < deref_struct->index; i++) {
2732 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2733 const_offset += glsl_count_attribute_slots(ft, vs_in);
2734 }
2735 } else
2736 unreachable("unsupported deref type");
2737
2738 }
2739 out:
2740 if (const_offset && offset)
2741 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2742 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2743 "");
2744
2745 *const_out = const_offset;
2746 *indir_out = offset;
2747 }
2748
2749
2750 /* The offchip buffer layout for TCS->TES is
2751 *
2752 * - attribute 0 of patch 0 vertex 0
2753 * - attribute 0 of patch 0 vertex 1
2754 * - attribute 0 of patch 0 vertex 2
2755 * ...
2756 * - attribute 0 of patch 1 vertex 0
2757 * - attribute 0 of patch 1 vertex 1
2758 * ...
2759 * - attribute 1 of patch 0 vertex 0
2760 * - attribute 1 of patch 0 vertex 1
2761 * ...
2762 * - per patch attribute 0 of patch 0
2763 * - per patch attribute 0 of patch 1
2764 * ...
2765 *
2766 * Note that every attribute has 4 components.
2767 */
2768 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2769 LLVMValueRef vertex_index,
2770 LLVMValueRef param_index)
2771 {
2772 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2773 LLVMValueRef param_stride, constant16;
2774 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2775
2776 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2777 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2778 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2779 num_patches, "");
2780
2781 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2782 if (vertex_index) {
2783 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2784 vertices_per_patch, "");
2785
2786 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2787 vertex_index, "");
2788
2789 param_stride = total_vertices;
2790 } else {
2791 base_addr = rel_patch_id;
2792 param_stride = num_patches;
2793 }
2794
2795 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2796 LLVMBuildMul(ctx->ac.builder, param_index,
2797 param_stride, ""), "");
2798
2799 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2800
2801 if (!vertex_index) {
2802 LLVMValueRef patch_data_offset =
2803 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2804
2805 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2806 patch_data_offset, "");
2807 }
2808 return base_addr;
2809 }
2810
2811 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2812 unsigned param,
2813 unsigned const_index,
2814 bool is_compact,
2815 LLVMValueRef vertex_index,
2816 LLVMValueRef indir_index)
2817 {
2818 LLVMValueRef param_index;
2819
2820 if (indir_index)
2821 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2822 indir_index, "");
2823 else {
2824 if (const_index && !is_compact)
2825 param += const_index;
2826 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2827 }
2828 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2829 }
2830
2831 static void
2832 mark_tess_output(struct nir_to_llvm_context *ctx,
2833 bool is_patch, uint32_t param)
2834
2835 {
2836 if (is_patch) {
2837 ctx->tess_patch_outputs_written |= (1ull << param);
2838 } else
2839 ctx->tess_outputs_written |= (1ull << param);
2840 }
2841
2842 static LLVMValueRef
2843 get_dw_address(struct nir_to_llvm_context *ctx,
2844 LLVMValueRef dw_addr,
2845 unsigned param,
2846 unsigned const_index,
2847 bool compact_const_index,
2848 LLVMValueRef vertex_index,
2849 LLVMValueRef stride,
2850 LLVMValueRef indir_index)
2851
2852 {
2853
2854 if (vertex_index) {
2855 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2856 LLVMBuildMul(ctx->ac.builder,
2857 vertex_index,
2858 stride, ""), "");
2859 }
2860
2861 if (indir_index)
2862 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2863 LLVMBuildMul(ctx->ac.builder, indir_index,
2864 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2865 else if (const_index && !compact_const_index)
2866 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2867 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2868
2869 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2870 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2871
2872 if (const_index && compact_const_index)
2873 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2874 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2875 return dw_addr;
2876 }
2877
2878 static LLVMValueRef
2879 load_tcs_varyings(struct ac_shader_abi *abi,
2880 LLVMValueRef vertex_index,
2881 LLVMValueRef indir_index,
2882 unsigned const_index,
2883 unsigned location,
2884 unsigned driver_location,
2885 unsigned component,
2886 unsigned num_components,
2887 bool is_patch,
2888 bool is_compact,
2889 bool load_input)
2890 {
2891 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2892 LLVMValueRef dw_addr, stride;
2893 LLVMValueRef value[4], result;
2894 unsigned param = shader_io_get_unique_index(location);
2895
2896 if (load_input) {
2897 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2898 dw_addr = get_tcs_in_current_patch_offset(ctx);
2899 } else {
2900 if (!is_patch) {
2901 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2902 dw_addr = get_tcs_out_current_patch_offset(ctx);
2903 } else {
2904 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2905 stride = NULL;
2906 }
2907 }
2908
2909 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2910 indir_index);
2911
2912 for (unsigned i = 0; i < num_components + component; i++) {
2913 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2914 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2915 ctx->ac.i32_1, "");
2916 }
2917 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2918 return result;
2919 }
2920
2921 static void
2922 store_tcs_output(struct ac_shader_abi *abi,
2923 LLVMValueRef vertex_index,
2924 LLVMValueRef param_index,
2925 unsigned const_index,
2926 unsigned location,
2927 unsigned driver_location,
2928 LLVMValueRef src,
2929 unsigned component,
2930 bool is_patch,
2931 bool is_compact,
2932 unsigned writemask)
2933 {
2934 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2935 LLVMValueRef dw_addr;
2936 LLVMValueRef stride = NULL;
2937 LLVMValueRef buf_addr = NULL;
2938 unsigned param;
2939 bool store_lds = true;
2940
2941 if (is_patch) {
2942 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2943 store_lds = false;
2944 } else {
2945 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2946 store_lds = false;
2947 }
2948
2949 param = shader_io_get_unique_index(location);
2950 if (location == VARYING_SLOT_CLIP_DIST0 &&
2951 is_compact && const_index > 3) {
2952 const_index -= 3;
2953 param++;
2954 }
2955
2956 if (!is_patch) {
2957 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2958 dw_addr = get_tcs_out_current_patch_offset(ctx);
2959 } else {
2960 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2961 }
2962
2963 mark_tess_output(ctx, is_patch, param);
2964
2965 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2966 param_index);
2967 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2968 vertex_index, param_index);
2969
2970 bool is_tess_factor = false;
2971 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2972 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2973 is_tess_factor = true;
2974
2975 unsigned base = is_compact ? const_index : 0;
2976 for (unsigned chan = 0; chan < 8; chan++) {
2977 if (!(writemask & (1 << chan)))
2978 continue;
2979 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2980
2981 if (store_lds || is_tess_factor) {
2982 LLVMValueRef dw_addr_chan =
2983 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2984 LLVMConstInt(ctx->ac.i32, chan, false), "");
2985 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2986 }
2987
2988 if (!is_tess_factor && writemask != 0xF)
2989 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2990 buf_addr, ctx->oc_lds,
2991 4 * (base + chan), 1, 0, true, false);
2992 }
2993
2994 if (writemask == 0xF) {
2995 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2996 buf_addr, ctx->oc_lds,
2997 (base * 4), 1, 0, true, false);
2998 }
2999 }
3000
3001 static LLVMValueRef
3002 load_tes_input(struct ac_shader_abi *abi,
3003 LLVMValueRef vertex_index,
3004 LLVMValueRef param_index,
3005 unsigned const_index,
3006 unsigned location,
3007 unsigned driver_location,
3008 unsigned component,
3009 unsigned num_components,
3010 bool is_patch,
3011 bool is_compact,
3012 bool load_input)
3013 {
3014 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3015 LLVMValueRef buf_addr;
3016 LLVMValueRef result;
3017 unsigned param = shader_io_get_unique_index(location);
3018
3019 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3020 const_index -= 3;
3021 param++;
3022 }
3023
3024 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3025 is_compact, vertex_index, param_index);
3026
3027 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3028 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3029
3030 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3031 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3032 result = trim_vector(&ctx->ac, result, num_components);
3033 return result;
3034 }
3035
3036 static LLVMValueRef
3037 load_gs_input(struct ac_shader_abi *abi,
3038 unsigned location,
3039 unsigned driver_location,
3040 unsigned component,
3041 unsigned num_components,
3042 unsigned vertex_index,
3043 unsigned const_index,
3044 LLVMTypeRef type)
3045 {
3046 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3047 LLVMValueRef vtx_offset;
3048 unsigned param, vtx_offset_param;
3049 LLVMValueRef value[4], result;
3050
3051 vtx_offset_param = vertex_index;
3052 assert(vtx_offset_param < 6);
3053 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3054 LLVMConstInt(ctx->ac.i32, 4, false), "");
3055
3056 param = shader_io_get_unique_index(location);
3057
3058 for (unsigned i = component; i < num_components + component; i++) {
3059 if (ctx->ac.chip_class >= GFX9) {
3060 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3061 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3062 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3063 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3064 } else {
3065 LLVMValueRef soffset =
3066 LLVMConstInt(ctx->ac.i32,
3067 (param * 4 + i + const_index) * 256,
3068 false);
3069
3070 value[i] = ac_build_buffer_load(&ctx->ac,
3071 ctx->esgs_ring, 1,
3072 ctx->ac.i32_0,
3073 vtx_offset, soffset,
3074 0, 1, 0, true, false);
3075
3076 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3077 type, "");
3078 }
3079 }
3080 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3081 result = ac_to_integer(&ctx->ac, result);
3082 return result;
3083 }
3084
3085 static LLVMValueRef
3086 build_gep_for_deref(struct ac_nir_context *ctx,
3087 nir_deref_var *deref)
3088 {
3089 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3090 assert(entry->data);
3091 LLVMValueRef val = entry->data;
3092 nir_deref *tail = deref->deref.child;
3093 while (tail != NULL) {
3094 LLVMValueRef offset;
3095 switch (tail->deref_type) {
3096 case nir_deref_type_array: {
3097 nir_deref_array *array = nir_deref_as_array(tail);
3098 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3099 if (array->deref_array_type ==
3100 nir_deref_array_type_indirect) {
3101 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3102 get_src(ctx,
3103 array->indirect),
3104 "");
3105 }
3106 break;
3107 }
3108 case nir_deref_type_struct: {
3109 nir_deref_struct *deref_struct =
3110 nir_deref_as_struct(tail);
3111 offset = LLVMConstInt(ctx->ac.i32,
3112 deref_struct->index, 0);
3113 break;
3114 }
3115 default:
3116 unreachable("bad deref type");
3117 }
3118 val = ac_build_gep0(&ctx->ac, val, offset);
3119 tail = tail->child;
3120 }
3121 return val;
3122 }
3123
3124 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3125 nir_intrinsic_instr *instr,
3126 bool load_inputs)
3127 {
3128 LLVMValueRef result;
3129 LLVMValueRef vertex_index = NULL;
3130 LLVMValueRef indir_index = NULL;
3131 unsigned const_index = 0;
3132 unsigned location = instr->variables[0]->var->data.location;
3133 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3134 const bool is_patch = instr->variables[0]->var->data.patch;
3135 const bool is_compact = instr->variables[0]->var->data.compact;
3136
3137 get_deref_offset(ctx, instr->variables[0],
3138 false, NULL, is_patch ? NULL : &vertex_index,
3139 &const_index, &indir_index);
3140
3141 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3142 const_index, location, driver_location,
3143 instr->variables[0]->var->data.location_frac,
3144 instr->num_components,
3145 is_patch, is_compact, load_inputs);
3146 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3147 }
3148
3149 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3150 nir_intrinsic_instr *instr)
3151 {
3152 LLVMValueRef values[8];
3153 int idx = instr->variables[0]->var->data.driver_location;
3154 int ve = instr->dest.ssa.num_components;
3155 unsigned comp = instr->variables[0]->var->data.location_frac;
3156 LLVMValueRef indir_index;
3157 LLVMValueRef ret;
3158 unsigned const_index;
3159 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3160 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3161 instr->variables[0]->var->data.mode == nir_var_shader_in;
3162 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3163 &const_index, &indir_index);
3164
3165 if (instr->dest.ssa.bit_size == 64)
3166 ve *= 2;
3167
3168 switch (instr->variables[0]->var->data.mode) {
3169 case nir_var_shader_in:
3170 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3171 ctx->stage == MESA_SHADER_TESS_EVAL) {
3172 return load_tess_varyings(ctx, instr, true);
3173 }
3174
3175 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3176 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3177 LLVMValueRef indir_index;
3178 unsigned const_index, vertex_index;
3179 get_deref_offset(ctx, instr->variables[0],
3180 false, &vertex_index, NULL,
3181 &const_index, &indir_index);
3182
3183 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3184 instr->variables[0]->var->data.driver_location,
3185 instr->variables[0]->var->data.location_frac, ve,
3186 vertex_index, const_index, type);
3187 }
3188
3189 for (unsigned chan = comp; chan < ve + comp; chan++) {
3190 if (indir_index) {
3191 unsigned count = glsl_count_attribute_slots(
3192 instr->variables[0]->var->type,
3193 ctx->stage == MESA_SHADER_VERTEX);
3194 count -= chan / 4;
3195 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3196 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3197 stride, false, true);
3198
3199 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3200 tmp_vec,
3201 indir_index, "");
3202 } else
3203 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3204 }
3205 break;
3206 case nir_var_local:
3207 for (unsigned chan = 0; chan < ve; chan++) {
3208 if (indir_index) {
3209 unsigned count = glsl_count_attribute_slots(
3210 instr->variables[0]->var->type, false);
3211 count -= chan / 4;
3212 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3213 &ctx->ac, ctx->locals + idx + chan, count,
3214 stride, true, true);
3215
3216 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3217 tmp_vec,
3218 indir_index, "");
3219 } else {
3220 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3221 }
3222 }
3223 break;
3224 case nir_var_shared: {
3225 LLVMValueRef address = build_gep_for_deref(ctx,
3226 instr->variables[0]);
3227 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3228 return LLVMBuildBitCast(ctx->ac.builder, val,
3229 get_def_type(ctx, &instr->dest.ssa),
3230 "");
3231 }
3232 case nir_var_shader_out:
3233 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3234 return load_tess_varyings(ctx, instr, false);
3235 }
3236
3237 for (unsigned chan = comp; chan < ve + comp; chan++) {
3238 if (indir_index) {
3239 unsigned count = glsl_count_attribute_slots(
3240 instr->variables[0]->var->type, false);
3241 count -= chan / 4;
3242 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3243 &ctx->ac, ctx->outputs + idx + chan, count,
3244 stride, true, true);
3245
3246 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3247 tmp_vec,
3248 indir_index, "");
3249 } else {
3250 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3251 ctx->outputs[idx + chan + const_index * stride],
3252 "");
3253 }
3254 }
3255 break;
3256 default:
3257 unreachable("unhandle variable mode");
3258 }
3259 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3260 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3261 }
3262
3263 static void
3264 visit_store_var(struct ac_nir_context *ctx,
3265 nir_intrinsic_instr *instr)
3266 {
3267 LLVMValueRef temp_ptr, value;
3268 int idx = instr->variables[0]->var->data.driver_location;
3269 unsigned comp = instr->variables[0]->var->data.location_frac;
3270 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3271 int writemask = instr->const_index[0] << comp;
3272 LLVMValueRef indir_index;
3273 unsigned const_index;
3274 get_deref_offset(ctx, instr->variables[0], false,
3275 NULL, NULL, &const_index, &indir_index);
3276
3277 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3278
3279 src = LLVMBuildBitCast(ctx->ac.builder, src,
3280 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3281 "");
3282
3283 writemask = widen_mask(writemask, 2);
3284 }
3285
3286 switch (instr->variables[0]->var->data.mode) {
3287 case nir_var_shader_out:
3288
3289 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3290 LLVMValueRef vertex_index = NULL;
3291 LLVMValueRef indir_index = NULL;
3292 unsigned const_index = 0;
3293 const unsigned location = instr->variables[0]->var->data.location;
3294 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3295 const unsigned comp = instr->variables[0]->var->data.location_frac;
3296 const bool is_patch = instr->variables[0]->var->data.patch;
3297 const bool is_compact = instr->variables[0]->var->data.compact;
3298
3299 get_deref_offset(ctx, instr->variables[0],
3300 false, NULL, is_patch ? NULL : &vertex_index,
3301 &const_index, &indir_index);
3302
3303 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3304 const_index, location, driver_location,
3305 src, comp, is_patch, is_compact, writemask);
3306 return;
3307 }
3308
3309 for (unsigned chan = 0; chan < 8; chan++) {
3310 int stride = 4;
3311 if (!(writemask & (1 << chan)))
3312 continue;
3313
3314 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3315
3316 if (instr->variables[0]->var->data.compact)
3317 stride = 1;
3318 if (indir_index) {
3319 unsigned count = glsl_count_attribute_slots(
3320 instr->variables[0]->var->type, false);
3321 count -= chan / 4;
3322 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3323 &ctx->ac, ctx->outputs + idx + chan, count,
3324 stride, true, true);
3325
3326 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3327 value, indir_index, "");
3328 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3329 count, stride, tmp_vec);
3330
3331 } else {
3332 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3333
3334 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3335 }
3336 }
3337 break;
3338 case nir_var_local:
3339 for (unsigned chan = 0; chan < 8; chan++) {
3340 if (!(writemask & (1 << chan)))
3341 continue;
3342
3343 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3344 if (indir_index) {
3345 unsigned count = glsl_count_attribute_slots(
3346 instr->variables[0]->var->type, false);
3347 count -= chan / 4;
3348 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3349 &ctx->ac, ctx->locals + idx + chan, count,
3350 4, true, true);
3351
3352 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3353 value, indir_index, "");
3354 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3355 count, 4, tmp_vec);
3356 } else {
3357 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3358
3359 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3360 }
3361 }
3362 break;
3363 case nir_var_shared: {
3364 int writemask = instr->const_index[0];
3365 LLVMValueRef address = build_gep_for_deref(ctx,
3366 instr->variables[0]);
3367 LLVMValueRef val = get_src(ctx, instr->src[0]);
3368 unsigned components =
3369 glsl_get_vector_elements(
3370 nir_deref_tail(&instr->variables[0]->deref)->type);
3371 if (writemask == (1 << components) - 1) {
3372 val = LLVMBuildBitCast(
3373 ctx->ac.builder, val,
3374 LLVMGetElementType(LLVMTypeOf(address)), "");
3375 LLVMBuildStore(ctx->ac.builder, val, address);
3376 } else {
3377 for (unsigned chan = 0; chan < 4; chan++) {
3378 if (!(writemask & (1 << chan)))
3379 continue;
3380 LLVMValueRef ptr =
3381 LLVMBuildStructGEP(ctx->ac.builder,
3382 address, chan, "");
3383 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3384 chan);
3385 src = LLVMBuildBitCast(
3386 ctx->ac.builder, src,
3387 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3388 LLVMBuildStore(ctx->ac.builder, src, ptr);
3389 }
3390 }
3391 break;
3392 }
3393 default:
3394 break;
3395 }
3396 }
3397
3398 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3399 {
3400 switch (dim) {
3401 case GLSL_SAMPLER_DIM_BUF:
3402 return 1;
3403 case GLSL_SAMPLER_DIM_1D:
3404 return array ? 2 : 1;
3405 case GLSL_SAMPLER_DIM_2D:
3406 return array ? 3 : 2;
3407 case GLSL_SAMPLER_DIM_MS:
3408 return array ? 4 : 3;
3409 case GLSL_SAMPLER_DIM_3D:
3410 case GLSL_SAMPLER_DIM_CUBE:
3411 return 3;
3412 case GLSL_SAMPLER_DIM_RECT:
3413 case GLSL_SAMPLER_DIM_SUBPASS:
3414 return 2;
3415 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3416 return 3;
3417 default:
3418 break;
3419 }
3420 return 0;
3421 }
3422
3423
3424
3425 /* Adjust the sample index according to FMASK.
3426 *
3427 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3428 * which is the identity mapping. Each nibble says which physical sample
3429 * should be fetched to get that sample.
3430 *
3431 * For example, 0x11111100 means there are only 2 samples stored and
3432 * the second sample covers 3/4 of the pixel. When reading samples 0
3433 * and 1, return physical sample 0 (determined by the first two 0s
3434 * in FMASK), otherwise return physical sample 1.
3435 *
3436 * The sample index should be adjusted as follows:
3437 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3438 */
3439 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3440 LLVMValueRef coord_x, LLVMValueRef coord_y,
3441 LLVMValueRef coord_z,
3442 LLVMValueRef sample_index,
3443 LLVMValueRef fmask_desc_ptr)
3444 {
3445 LLVMValueRef fmask_load_address[4];
3446 LLVMValueRef res;
3447
3448 fmask_load_address[0] = coord_x;
3449 fmask_load_address[1] = coord_y;
3450 if (coord_z) {
3451 fmask_load_address[2] = coord_z;
3452 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3453 }
3454
3455 struct ac_image_args args = {0};
3456
3457 args.opcode = ac_image_load;
3458 args.da = coord_z ? true : false;
3459 args.resource = fmask_desc_ptr;
3460 args.dmask = 0xf;
3461 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3462
3463 res = ac_build_image_opcode(ctx, &args);
3464
3465 res = ac_to_integer(ctx, res);
3466 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3467 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3468
3469 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3470 res,
3471 ctx->i32_0, "");
3472
3473 LLVMValueRef sample_index4 =
3474 LLVMBuildMul(ctx->builder, sample_index, four, "");
3475 LLVMValueRef shifted_fmask =
3476 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3477 LLVMValueRef final_sample =
3478 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3479
3480 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3481 * resource descriptor is 0 (invalid),
3482 */
3483 LLVMValueRef fmask_desc =
3484 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3485 ctx->v8i32, "");
3486
3487 LLVMValueRef fmask_word1 =
3488 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3489 ctx->i32_1, "");
3490
3491 LLVMValueRef word1_is_nonzero =
3492 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3493 fmask_word1, ctx->i32_0, "");
3494
3495 /* Replace the MSAA sample index. */
3496 sample_index =
3497 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3498 final_sample, sample_index, "");
3499 return sample_index;
3500 }
3501
3502 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3503 const nir_intrinsic_instr *instr)
3504 {
3505 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3506
3507 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3508 LLVMValueRef coords[4];
3509 LLVMValueRef masks[] = {
3510 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3511 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3512 };
3513 LLVMValueRef res;
3514 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3515
3516 int count;
3517 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3518 bool is_array = glsl_sampler_type_is_array(type);
3519 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3520 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3521 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3522 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3523 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3524 count = image_type_to_components_count(dim, is_array);
3525
3526 if (is_ms) {
3527 LLVMValueRef fmask_load_address[3];
3528 int chan;
3529
3530 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3531 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3532 if (is_array)
3533 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3534 else
3535 fmask_load_address[2] = NULL;
3536 if (add_frag_pos) {
3537 for (chan = 0; chan < 2; ++chan)
3538 fmask_load_address[chan] =
3539 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3540 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3541 ctx->ac.i32, ""), "");
3542 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3543 }
3544 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3545 fmask_load_address[0],
3546 fmask_load_address[1],
3547 fmask_load_address[2],
3548 sample_index,
3549 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3550 }
3551 if (count == 1 && !gfx9_1d) {
3552 if (instr->src[0].ssa->num_components)
3553 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3554 else
3555 res = src0;
3556 } else {
3557 int chan;
3558 if (is_ms)
3559 count--;
3560 for (chan = 0; chan < count; ++chan) {
3561 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3562 }
3563 if (add_frag_pos) {
3564 for (chan = 0; chan < 2; ++chan)
3565 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3566 ctx->ac.i32, ""), "");
3567 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3568 count++;
3569 }
3570
3571 if (gfx9_1d) {
3572 if (is_array) {
3573 coords[2] = coords[1];
3574 coords[1] = ctx->ac.i32_0;
3575 } else
3576 coords[1] = ctx->ac.i32_0;
3577 count++;
3578 }
3579
3580 if (is_ms) {
3581 coords[count] = sample_index;
3582 count++;
3583 }
3584
3585 if (count == 3) {
3586 coords[3] = LLVMGetUndef(ctx->ac.i32);
3587 count = 4;
3588 }
3589 res = ac_build_gather_values(&ctx->ac, coords, count);
3590 }
3591 return res;
3592 }
3593
3594 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3595 const nir_intrinsic_instr *instr)
3596 {
3597 LLVMValueRef params[7];
3598 LLVMValueRef res;
3599 char intrinsic_name[64];
3600 const nir_variable *var = instr->variables[0]->var;
3601 const struct glsl_type *type = var->type;
3602
3603 if(instr->variables[0]->deref.child)
3604 type = instr->variables[0]->deref.child->type;
3605
3606 type = glsl_without_array(type);
3607
3608 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3609 if (dim == GLSL_SAMPLER_DIM_BUF) {
3610 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3611 unsigned num_channels = util_last_bit(mask);
3612 LLVMValueRef rsrc, vindex;
3613
3614 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3615 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3616 ctx->ac.i32_0, "");
3617
3618 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3619 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3620 ctx->ac.i32_0, num_channels,
3621 false, false);
3622 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3623
3624 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3625 res = ac_to_integer(&ctx->ac, res);
3626 } else {
3627 bool is_da = glsl_sampler_type_is_array(type) ||
3628 dim == GLSL_SAMPLER_DIM_CUBE ||
3629 dim == GLSL_SAMPLER_DIM_3D ||
3630 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3631 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3632 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3633 LLVMValueRef glc = ctx->ac.i1false;
3634 LLVMValueRef slc = ctx->ac.i1false;
3635
3636 params[0] = get_image_coords(ctx, instr);
3637 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3638 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3639 params[3] = glc;
3640 params[4] = slc;
3641 params[5] = ctx->ac.i1false;
3642 params[6] = da;
3643
3644 ac_get_image_intr_name("llvm.amdgcn.image.load",
3645 ctx->ac.v4f32, /* vdata */
3646 LLVMTypeOf(params[0]), /* coords */
3647 LLVMTypeOf(params[1]), /* rsrc */
3648 intrinsic_name, sizeof(intrinsic_name));
3649
3650 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3651 params, 7, AC_FUNC_ATTR_READONLY);
3652 }
3653 return ac_to_integer(&ctx->ac, res);
3654 }
3655
3656 static void visit_image_store(struct ac_nir_context *ctx,
3657 nir_intrinsic_instr *instr)
3658 {
3659 LLVMValueRef params[8];
3660 char intrinsic_name[64];
3661 const nir_variable *var = instr->variables[0]->var;
3662 const struct glsl_type *type = glsl_without_array(var->type);
3663 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3664 LLVMValueRef glc = ctx->ac.i1false;
3665 bool force_glc = ctx->ac.chip_class == SI;
3666 if (force_glc)
3667 glc = ctx->ac.i1true;
3668
3669 if (dim == GLSL_SAMPLER_DIM_BUF) {
3670 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3671 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3672 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3673 ctx->ac.i32_0, ""); /* vindex */
3674 params[3] = ctx->ac.i32_0; /* voffset */
3675 params[4] = glc; /* glc */
3676 params[5] = ctx->ac.i1false; /* slc */
3677 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3678 params, 6, 0);
3679 } else {
3680 bool is_da = glsl_sampler_type_is_array(type) ||
3681 dim == GLSL_SAMPLER_DIM_CUBE ||
3682 dim == GLSL_SAMPLER_DIM_3D;
3683 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3684 LLVMValueRef slc = ctx->ac.i1false;
3685
3686 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3687 params[1] = get_image_coords(ctx, instr); /* coords */
3688 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3689 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3690 params[4] = glc;
3691 params[5] = slc;
3692 params[6] = ctx->ac.i1false;
3693 params[7] = da;
3694
3695 ac_get_image_intr_name("llvm.amdgcn.image.store",
3696 LLVMTypeOf(params[0]), /* vdata */
3697 LLVMTypeOf(params[1]), /* coords */
3698 LLVMTypeOf(params[2]), /* rsrc */
3699 intrinsic_name, sizeof(intrinsic_name));
3700
3701 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3702 params, 8, 0);
3703 }
3704
3705 }
3706
3707 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3708 const nir_intrinsic_instr *instr)
3709 {
3710 LLVMValueRef params[7];
3711 int param_count = 0;
3712 const nir_variable *var = instr->variables[0]->var;
3713
3714 const char *atomic_name;
3715 char intrinsic_name[41];
3716 const struct glsl_type *type = glsl_without_array(var->type);
3717 MAYBE_UNUSED int length;
3718
3719 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3720
3721 switch (instr->intrinsic) {
3722 case nir_intrinsic_image_atomic_add:
3723 atomic_name = "add";
3724 break;
3725 case nir_intrinsic_image_atomic_min:
3726 atomic_name = is_unsigned ? "umin" : "smin";
3727 break;
3728 case nir_intrinsic_image_atomic_max:
3729 atomic_name = is_unsigned ? "umax" : "smax";
3730 break;
3731 case nir_intrinsic_image_atomic_and:
3732 atomic_name = "and";
3733 break;
3734 case nir_intrinsic_image_atomic_or:
3735 atomic_name = "or";
3736 break;
3737 case nir_intrinsic_image_atomic_xor:
3738 atomic_name = "xor";
3739 break;
3740 case nir_intrinsic_image_atomic_exchange:
3741 atomic_name = "swap";
3742 break;
3743 case nir_intrinsic_image_atomic_comp_swap:
3744 atomic_name = "cmpswap";
3745 break;
3746 default:
3747 abort();
3748 }
3749
3750 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3751 params[param_count++] = get_src(ctx, instr->src[3]);
3752 params[param_count++] = get_src(ctx, instr->src[2]);
3753
3754 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3755 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3756 NULL, true, true);
3757 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3758 ctx->ac.i32_0, ""); /* vindex */
3759 params[param_count++] = ctx->ac.i32_0; /* voffset */
3760 params[param_count++] = ctx->ac.i1false; /* slc */
3761
3762 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3763 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3764 } else {
3765 char coords_type[8];
3766
3767 bool da = glsl_sampler_type_is_array(type) ||
3768 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3769
3770 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3771 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3772 NULL, true, true);
3773 params[param_count++] = ctx->ac.i1false; /* r128 */
3774 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3775 params[param_count++] = ctx->ac.i1false; /* slc */
3776
3777 build_int_type_name(LLVMTypeOf(coords),
3778 coords_type, sizeof(coords_type));
3779
3780 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3781 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3782 }
3783
3784 assert(length < sizeof(intrinsic_name));
3785 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3786 }
3787
3788 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3789 const nir_intrinsic_instr *instr)
3790 {
3791 LLVMValueRef res;
3792 const nir_variable *var = instr->variables[0]->var;
3793 const struct glsl_type *type = instr->variables[0]->var->type;
3794 bool da = glsl_sampler_type_is_array(var->type) ||
3795 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE ||
3796 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_3D;
3797 if(instr->variables[0]->deref.child)
3798 type = instr->variables[0]->deref.child->type;
3799
3800 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3801 return get_buffer_size(ctx,
3802 get_sampler_desc(ctx, instr->variables[0],
3803 AC_DESC_BUFFER, NULL, true, false), true);
3804
3805 struct ac_image_args args = { 0 };
3806
3807 args.da = da;
3808 args.dmask = 0xf;
3809 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3810 args.opcode = ac_image_get_resinfo;
3811 args.addr = ctx->ac.i32_0;
3812
3813 res = ac_build_image_opcode(&ctx->ac, &args);
3814
3815 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3816
3817 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3818 glsl_sampler_type_is_array(type)) {
3819 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3820 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3821 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3822 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3823 }
3824 if (ctx->ac.chip_class >= GFX9 &&
3825 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3826 glsl_sampler_type_is_array(type)) {
3827 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3828 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3829 ctx->ac.i32_1, "");
3830
3831 }
3832 return res;
3833 }
3834
3835 #define NOOP_WAITCNT 0xf7f
3836 #define LGKM_CNT 0x07f
3837 #define VM_CNT 0xf70
3838
3839 static void emit_membar(struct ac_llvm_context *ac,
3840 const nir_intrinsic_instr *instr)
3841 {
3842 unsigned waitcnt = NOOP_WAITCNT;
3843
3844 switch (instr->intrinsic) {
3845 case nir_intrinsic_memory_barrier:
3846 case nir_intrinsic_group_memory_barrier:
3847 waitcnt &= VM_CNT & LGKM_CNT;
3848 break;
3849 case nir_intrinsic_memory_barrier_atomic_counter:
3850 case nir_intrinsic_memory_barrier_buffer:
3851 case nir_intrinsic_memory_barrier_image:
3852 waitcnt &= VM_CNT;
3853 break;
3854 case nir_intrinsic_memory_barrier_shared:
3855 waitcnt &= LGKM_CNT;
3856 break;
3857 default:
3858 break;
3859 }
3860 if (waitcnt != NOOP_WAITCNT)
3861 ac_build_waitcnt(ac, waitcnt);
3862 }
3863
3864 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3865 {
3866 /* SI only (thanks to a hw bug workaround):
3867 * The real barrier instruction isn’t needed, because an entire patch
3868 * always fits into a single wave.
3869 */
3870 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3871 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3872 return;
3873 }
3874 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3875 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3876 }
3877
3878 static void emit_discard(struct ac_nir_context *ctx,
3879 const nir_intrinsic_instr *instr)
3880 {
3881 LLVMValueRef cond;
3882
3883 if (instr->intrinsic == nir_intrinsic_discard_if) {
3884 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3885 get_src(ctx, instr->src[0]),
3886 ctx->ac.i32_0, "");
3887 } else {
3888 assert(instr->intrinsic == nir_intrinsic_discard);
3889 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3890 }
3891
3892 ac_build_kill_if_false(&ctx->ac, cond);
3893 }
3894
3895 static LLVMValueRef
3896 visit_load_helper_invocation(struct ac_nir_context *ctx)
3897 {
3898 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3899 "llvm.amdgcn.ps.live",
3900 ctx->ac.i1, NULL, 0,
3901 AC_FUNC_ATTR_READNONE);
3902 result = LLVMBuildNot(ctx->ac.builder, result, "");
3903 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3904 }
3905
3906 static LLVMValueRef
3907 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3908 {
3909 LLVMValueRef result;
3910 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3911 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3912 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3913
3914 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3915 }
3916
3917 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3918 const nir_intrinsic_instr *instr,
3919 LLVMValueRef ptr)
3920 {
3921 LLVMValueRef result;
3922 LLVMValueRef src = get_src(ctx, instr->src[0]);
3923
3924 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3925 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3926 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3927 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3928 ptr, src, src1,
3929 LLVMAtomicOrderingSequentiallyConsistent,
3930 LLVMAtomicOrderingSequentiallyConsistent,
3931 false);
3932 } else {
3933 LLVMAtomicRMWBinOp op;
3934 switch (instr->intrinsic) {
3935 case nir_intrinsic_var_atomic_add:
3936 case nir_intrinsic_shared_atomic_add:
3937 op = LLVMAtomicRMWBinOpAdd;
3938 break;
3939 case nir_intrinsic_var_atomic_umin:
3940 case nir_intrinsic_shared_atomic_umin:
3941 op = LLVMAtomicRMWBinOpUMin;
3942 break;
3943 case nir_intrinsic_var_atomic_umax:
3944 case nir_intrinsic_shared_atomic_umax:
3945 op = LLVMAtomicRMWBinOpUMax;
3946 break;
3947 case nir_intrinsic_var_atomic_imin:
3948 case nir_intrinsic_shared_atomic_imin:
3949 op = LLVMAtomicRMWBinOpMin;
3950 break;
3951 case nir_intrinsic_var_atomic_imax:
3952 case nir_intrinsic_shared_atomic_imax:
3953 op = LLVMAtomicRMWBinOpMax;
3954 break;
3955 case nir_intrinsic_var_atomic_and:
3956 case nir_intrinsic_shared_atomic_and:
3957 op = LLVMAtomicRMWBinOpAnd;
3958 break;
3959 case nir_intrinsic_var_atomic_or:
3960 case nir_intrinsic_shared_atomic_or:
3961 op = LLVMAtomicRMWBinOpOr;
3962 break;
3963 case nir_intrinsic_var_atomic_xor:
3964 case nir_intrinsic_shared_atomic_xor:
3965 op = LLVMAtomicRMWBinOpXor;
3966 break;
3967 case nir_intrinsic_var_atomic_exchange:
3968 case nir_intrinsic_shared_atomic_exchange:
3969 op = LLVMAtomicRMWBinOpXchg;
3970 break;
3971 default:
3972 return NULL;
3973 }
3974
3975 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
3976 LLVMAtomicOrderingSequentiallyConsistent,
3977 false);
3978 }
3979 return result;
3980 }
3981
3982 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
3983 enum glsl_interp_mode interp, unsigned location)
3984 {
3985 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3986
3987 switch (interp) {
3988 case INTERP_MODE_FLAT:
3989 default:
3990 return NULL;
3991 case INTERP_MODE_SMOOTH:
3992 case INTERP_MODE_NONE:
3993 if (location == INTERP_CENTER)
3994 return ctx->persp_center;
3995 else if (location == INTERP_CENTROID)
3996 return ctx->persp_centroid;
3997 else if (location == INTERP_SAMPLE)
3998 return ctx->persp_sample;
3999 break;
4000 case INTERP_MODE_NOPERSPECTIVE:
4001 if (location == INTERP_CENTER)
4002 return ctx->linear_center;
4003 else if (location == INTERP_CENTROID)
4004 return ctx->linear_centroid;
4005 else if (location == INTERP_SAMPLE)
4006 return ctx->linear_sample;
4007 break;
4008 }
4009 return NULL;
4010 }
4011
4012 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4013 LLVMValueRef sample_id)
4014 {
4015 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4016
4017 LLVMValueRef result;
4018 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4019
4020 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4021 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4022
4023 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4024 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4025
4026 return result;
4027 }
4028
4029 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4030 {
4031 LLVMValueRef values[2];
4032
4033 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4034 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4035 return ac_build_gather_values(&ctx->ac, values, 2);
4036 }
4037
4038 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4039 {
4040 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4041 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4042 ctx->options->key.fs.log2_num_samples :
4043 ctx->options->key.fs.log2_ps_iter_samples;
4044
4045 /* The bit pattern matches that used by fixed function fragment
4046 * processing. */
4047 static const uint16_t ps_iter_masks[] = {
4048 0xffff, /* not used */
4049 0x5555,
4050 0x1111,
4051 0x0101,
4052 0x0001,
4053 };
4054 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4055
4056 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4057
4058 LLVMValueRef result, sample_id;
4059 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4060 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4061 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4062 return result;
4063 }
4064
4065 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4066 const nir_intrinsic_instr *instr)
4067 {
4068 LLVMValueRef result[4];
4069 LLVMValueRef interp_param, attr_number;
4070 unsigned location;
4071 unsigned chan;
4072 LLVMValueRef src_c0 = NULL;
4073 LLVMValueRef src_c1 = NULL;
4074 LLVMValueRef src0 = NULL;
4075 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4076 switch (instr->intrinsic) {
4077 case nir_intrinsic_interp_var_at_centroid:
4078 location = INTERP_CENTROID;
4079 break;
4080 case nir_intrinsic_interp_var_at_sample:
4081 case nir_intrinsic_interp_var_at_offset:
4082 location = INTERP_CENTER;
4083 src0 = get_src(ctx, instr->src[0]);
4084 break;
4085 default:
4086 break;
4087 }
4088
4089 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4090 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4091 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4092 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4093 LLVMValueRef sample_position;
4094 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4095
4096 /* fetch sample ID */
4097 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4098
4099 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4100 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4101 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4102 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4103 }
4104 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4105 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4106
4107 if (location == INTERP_CENTER) {
4108 LLVMValueRef ij_out[2];
4109 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4110
4111 /*
4112 * take the I then J parameters, and the DDX/Y for it, and
4113 * calculate the IJ inputs for the interpolator.
4114 * temp1 = ddx * offset/sample.x + I;
4115 * interp_param.I = ddy * offset/sample.y + temp1;
4116 * temp1 = ddx * offset/sample.x + J;
4117 * interp_param.J = ddy * offset/sample.y + temp1;
4118 */
4119 for (unsigned i = 0; i < 2; i++) {
4120 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4121 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4122 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4123 ddxy_out, ix_ll, "");
4124 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4125 ddxy_out, iy_ll, "");
4126 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4127 interp_param, ix_ll, "");
4128 LLVMValueRef temp1, temp2;
4129
4130 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4131 ctx->ac.f32, "");
4132
4133 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4134 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4135
4136 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4137 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4138
4139 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4140 temp2, ctx->ac.i32, "");
4141 }
4142 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4143
4144 }
4145
4146 for (chan = 0; chan < 4; chan++) {
4147 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4148
4149 if (interp_param) {
4150 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4151 interp_param, ctx->ac.v2f32, "");
4152 LLVMValueRef i = LLVMBuildExtractElement(
4153 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4154 LLVMValueRef j = LLVMBuildExtractElement(
4155 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4156
4157 result[chan] = ac_build_fs_interp(&ctx->ac,
4158 llvm_chan, attr_number,
4159 ctx->abi->prim_mask, i, j);
4160 } else {
4161 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4162 LLVMConstInt(ctx->ac.i32, 2, false),
4163 llvm_chan, attr_number,
4164 ctx->abi->prim_mask);
4165 }
4166 }
4167 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4168 instr->variables[0]->var->data.location_frac);
4169 }
4170
4171 static void
4172 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4173 {
4174 LLVMValueRef gs_next_vertex;
4175 LLVMValueRef can_emit;
4176 int idx;
4177 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4178
4179 assert(stream == 0);
4180
4181 /* Write vertex attribute values to GSVS ring */
4182 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4183 ctx->gs_next_vertex,
4184 "");
4185
4186 /* If this thread has already emitted the declared maximum number of
4187 * vertices, kill it: excessive vertex emissions are not supposed to
4188 * have any effect, and GS threads have no externally observable
4189 * effects other than emitting vertices.
4190 */
4191 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4192 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4193 ac_build_kill_if_false(&ctx->ac, can_emit);
4194
4195 /* loop num outputs */
4196 idx = 0;
4197 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4198 LLVMValueRef *out_ptr = &addrs[i * 4];
4199 int length = 4;
4200 int slot = idx;
4201 int slot_inc = 1;
4202
4203 if (!(ctx->output_mask & (1ull << i)))
4204 continue;
4205
4206 if (i == VARYING_SLOT_CLIP_DIST0) {
4207 /* pack clip and cull into a single set of slots */
4208 length = ctx->num_output_clips + ctx->num_output_culls;
4209 if (length > 4)
4210 slot_inc = 2;
4211 }
4212 for (unsigned j = 0; j < length; j++) {
4213 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4214 out_ptr[j], "");
4215 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4216 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4217 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4218
4219 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4220
4221 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4222 out_val, 1,
4223 voffset, ctx->gs2vs_offset, 0,
4224 1, 1, true, true);
4225 }
4226 idx += slot_inc;
4227 }
4228
4229 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4230 ctx->ac.i32_1, "");
4231 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4232
4233 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4234 }
4235
4236 static void
4237 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4238 {
4239 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4240 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4241 }
4242
4243 static LLVMValueRef
4244 load_tess_coord(struct ac_shader_abi *abi)
4245 {
4246 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4247
4248 LLVMValueRef coord[4] = {
4249 ctx->tes_u,
4250 ctx->tes_v,
4251 ctx->ac.f32_0,
4252 ctx->ac.f32_0,
4253 };
4254
4255 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4256 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4257 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4258
4259 return ac_build_gather_values(&ctx->ac, coord, 3);
4260 }
4261
4262 static LLVMValueRef
4263 load_patch_vertices_in(struct ac_shader_abi *abi)
4264 {
4265 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4266 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4267 }
4268
4269 static void visit_intrinsic(struct ac_nir_context *ctx,
4270 nir_intrinsic_instr *instr)
4271 {
4272 LLVMValueRef result = NULL;
4273
4274 switch (instr->intrinsic) {
4275 case nir_intrinsic_ballot:
4276 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4277 break;
4278 case nir_intrinsic_read_invocation:
4279 case nir_intrinsic_read_first_invocation: {
4280 LLVMValueRef args[2];
4281
4282 /* Value */
4283 args[0] = get_src(ctx, instr->src[0]);
4284
4285 unsigned num_args;
4286 const char *intr_name;
4287 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4288 num_args = 2;
4289 intr_name = "llvm.amdgcn.readlane";
4290
4291 /* Invocation */
4292 args[1] = get_src(ctx, instr->src[1]);
4293 } else {
4294 num_args = 1;
4295 intr_name = "llvm.amdgcn.readfirstlane";
4296 }
4297
4298 /* We currently have no other way to prevent LLVM from lifting the icmp
4299 * calls to a dominating basic block.
4300 */
4301 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4302
4303 result = ac_build_intrinsic(&ctx->ac, intr_name,
4304 ctx->ac.i32, args, num_args,
4305 AC_FUNC_ATTR_READNONE |
4306 AC_FUNC_ATTR_CONVERGENT);
4307 break;
4308 }
4309 case nir_intrinsic_load_subgroup_invocation:
4310 result = ac_get_thread_id(&ctx->ac);
4311 break;
4312 case nir_intrinsic_load_work_group_id: {
4313 LLVMValueRef values[3];
4314
4315 for (int i = 0; i < 3; i++) {
4316 values[i] = ctx->abi->workgroup_ids[i] ?
4317 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4318 }
4319
4320 result = ac_build_gather_values(&ctx->ac, values, 3);
4321 break;
4322 }
4323 case nir_intrinsic_load_base_vertex: {
4324 result = ctx->abi->base_vertex;
4325 break;
4326 }
4327 case nir_intrinsic_load_local_group_size:
4328 result = ctx->abi->load_local_group_size(ctx->abi);
4329 break;
4330 case nir_intrinsic_load_vertex_id_zero_base: {
4331 result = ctx->abi->vertex_id;
4332 break;
4333 }
4334 case nir_intrinsic_load_local_invocation_id: {
4335 result = ctx->abi->local_invocation_ids;
4336 break;
4337 }
4338 case nir_intrinsic_load_base_instance:
4339 result = ctx->abi->start_instance;
4340 break;
4341 case nir_intrinsic_load_draw_id:
4342 result = ctx->abi->draw_id;
4343 break;
4344 case nir_intrinsic_load_view_index:
4345 result = ctx->abi->view_index;
4346 break;
4347 case nir_intrinsic_load_invocation_id:
4348 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4349 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4350 else
4351 result = ctx->abi->gs_invocation_id;
4352 break;
4353 case nir_intrinsic_load_primitive_id:
4354 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4355 result = ctx->abi->gs_prim_id;
4356 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4357 result = ctx->abi->tcs_patch_id;
4358 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4359 result = ctx->abi->tes_patch_id;
4360 } else
4361 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4362 break;
4363 case nir_intrinsic_load_sample_id:
4364 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4365 break;
4366 case nir_intrinsic_load_sample_pos:
4367 result = load_sample_pos(ctx);
4368 break;
4369 case nir_intrinsic_load_sample_mask_in:
4370 result = ctx->abi->load_sample_mask_in(ctx->abi);
4371 break;
4372 case nir_intrinsic_load_frag_coord: {
4373 LLVMValueRef values[4] = {
4374 ctx->abi->frag_pos[0],
4375 ctx->abi->frag_pos[1],
4376 ctx->abi->frag_pos[2],
4377 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4378 };
4379 result = ac_build_gather_values(&ctx->ac, values, 4);
4380 break;
4381 }
4382 case nir_intrinsic_load_front_face:
4383 result = ctx->abi->front_face;
4384 break;
4385 case nir_intrinsic_load_helper_invocation:
4386 result = visit_load_helper_invocation(ctx);
4387 break;
4388 case nir_intrinsic_load_instance_id:
4389 result = ctx->abi->instance_id;
4390 break;
4391 case nir_intrinsic_load_num_work_groups:
4392 result = ctx->abi->num_work_groups;
4393 break;
4394 case nir_intrinsic_load_local_invocation_index:
4395 result = visit_load_local_invocation_index(ctx);
4396 break;
4397 case nir_intrinsic_load_push_constant:
4398 result = visit_load_push_constant(ctx, instr);
4399 break;
4400 case nir_intrinsic_vulkan_resource_index: {
4401 LLVMValueRef index = get_src(ctx, instr->src[0]);
4402 unsigned desc_set = nir_intrinsic_desc_set(instr);
4403 unsigned binding = nir_intrinsic_binding(instr);
4404
4405 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4406 binding);
4407 break;
4408 }
4409 case nir_intrinsic_vulkan_resource_reindex:
4410 result = visit_vulkan_resource_reindex(ctx, instr);
4411 break;
4412 case nir_intrinsic_store_ssbo:
4413 visit_store_ssbo(ctx, instr);
4414 break;
4415 case nir_intrinsic_load_ssbo:
4416 result = visit_load_buffer(ctx, instr);
4417 break;
4418 case nir_intrinsic_ssbo_atomic_add:
4419 case nir_intrinsic_ssbo_atomic_imin:
4420 case nir_intrinsic_ssbo_atomic_umin:
4421 case nir_intrinsic_ssbo_atomic_imax:
4422 case nir_intrinsic_ssbo_atomic_umax:
4423 case nir_intrinsic_ssbo_atomic_and:
4424 case nir_intrinsic_ssbo_atomic_or:
4425 case nir_intrinsic_ssbo_atomic_xor:
4426 case nir_intrinsic_ssbo_atomic_exchange:
4427 case nir_intrinsic_ssbo_atomic_comp_swap:
4428 result = visit_atomic_ssbo(ctx, instr);
4429 break;
4430 case nir_intrinsic_load_ubo:
4431 result = visit_load_ubo_buffer(ctx, instr);
4432 break;
4433 case nir_intrinsic_get_buffer_size:
4434 result = visit_get_buffer_size(ctx, instr);
4435 break;
4436 case nir_intrinsic_load_var:
4437 result = visit_load_var(ctx, instr);
4438 break;
4439 case nir_intrinsic_store_var:
4440 visit_store_var(ctx, instr);
4441 break;
4442 case nir_intrinsic_image_load:
4443 result = visit_image_load(ctx, instr);
4444 break;
4445 case nir_intrinsic_image_store:
4446 visit_image_store(ctx, instr);
4447 break;
4448 case nir_intrinsic_image_atomic_add:
4449 case nir_intrinsic_image_atomic_min:
4450 case nir_intrinsic_image_atomic_max:
4451 case nir_intrinsic_image_atomic_and:
4452 case nir_intrinsic_image_atomic_or:
4453 case nir_intrinsic_image_atomic_xor:
4454 case nir_intrinsic_image_atomic_exchange:
4455 case nir_intrinsic_image_atomic_comp_swap:
4456 result = visit_image_atomic(ctx, instr);
4457 break;
4458 case nir_intrinsic_image_size:
4459 result = visit_image_size(ctx, instr);
4460 break;
4461 case nir_intrinsic_shader_clock:
4462 result = ac_build_shader_clock(&ctx->ac);
4463 break;
4464 case nir_intrinsic_discard:
4465 case nir_intrinsic_discard_if:
4466 emit_discard(ctx, instr);
4467 break;
4468 case nir_intrinsic_memory_barrier:
4469 case nir_intrinsic_group_memory_barrier:
4470 case nir_intrinsic_memory_barrier_atomic_counter:
4471 case nir_intrinsic_memory_barrier_buffer:
4472 case nir_intrinsic_memory_barrier_image:
4473 case nir_intrinsic_memory_barrier_shared:
4474 emit_membar(&ctx->ac, instr);
4475 break;
4476 case nir_intrinsic_barrier:
4477 emit_barrier(&ctx->ac, ctx->stage);
4478 break;
4479 case nir_intrinsic_shared_atomic_add:
4480 case nir_intrinsic_shared_atomic_imin:
4481 case nir_intrinsic_shared_atomic_umin:
4482 case nir_intrinsic_shared_atomic_imax:
4483 case nir_intrinsic_shared_atomic_umax:
4484 case nir_intrinsic_shared_atomic_and:
4485 case nir_intrinsic_shared_atomic_or:
4486 case nir_intrinsic_shared_atomic_xor:
4487 case nir_intrinsic_shared_atomic_exchange:
4488 case nir_intrinsic_shared_atomic_comp_swap: {
4489 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
4490 result = visit_var_atomic(ctx, instr, ptr);
4491 break;
4492 }
4493 case nir_intrinsic_var_atomic_add:
4494 case nir_intrinsic_var_atomic_imin:
4495 case nir_intrinsic_var_atomic_umin:
4496 case nir_intrinsic_var_atomic_imax:
4497 case nir_intrinsic_var_atomic_umax:
4498 case nir_intrinsic_var_atomic_and:
4499 case nir_intrinsic_var_atomic_or:
4500 case nir_intrinsic_var_atomic_xor:
4501 case nir_intrinsic_var_atomic_exchange:
4502 case nir_intrinsic_var_atomic_comp_swap: {
4503 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4504 result = visit_var_atomic(ctx, instr, ptr);
4505 break;
4506 }
4507 case nir_intrinsic_interp_var_at_centroid:
4508 case nir_intrinsic_interp_var_at_sample:
4509 case nir_intrinsic_interp_var_at_offset:
4510 result = visit_interp(ctx, instr);
4511 break;
4512 case nir_intrinsic_emit_vertex:
4513 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->outputs);
4514 break;
4515 case nir_intrinsic_end_primitive:
4516 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4517 break;
4518 case nir_intrinsic_load_tess_coord:
4519 result = ctx->abi->load_tess_coord(ctx->abi);
4520 break;
4521 case nir_intrinsic_load_tess_level_outer:
4522 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4523 break;
4524 case nir_intrinsic_load_tess_level_inner:
4525 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4526 break;
4527 case nir_intrinsic_load_patch_vertices_in:
4528 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4529 break;
4530 case nir_intrinsic_vote_all: {
4531 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4532 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4533 break;
4534 }
4535 case nir_intrinsic_vote_any: {
4536 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4537 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4538 break;
4539 }
4540 case nir_intrinsic_vote_eq: {
4541 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4542 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4543 break;
4544 }
4545 default:
4546 fprintf(stderr, "Unknown intrinsic: ");
4547 nir_print_instr(&instr->instr, stderr);
4548 fprintf(stderr, "\n");
4549 break;
4550 }
4551 if (result) {
4552 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4553 }
4554 }
4555
4556 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4557 LLVMValueRef buffer_ptr, bool write)
4558 {
4559 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4560 LLVMValueRef result;
4561
4562 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4563
4564 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4565 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4566
4567 return result;
4568 }
4569
4570 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4571 {
4572 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4573 LLVMValueRef result;
4574
4575 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4576
4577 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4578 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4579
4580 return result;
4581 }
4582
4583 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4584 unsigned descriptor_set,
4585 unsigned base_index,
4586 unsigned constant_index,
4587 LLVMValueRef index,
4588 enum ac_descriptor_type desc_type,
4589 bool image, bool write)
4590 {
4591 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4592 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4593 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4594 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4595 unsigned offset = binding->offset;
4596 unsigned stride = binding->size;
4597 unsigned type_size;
4598 LLVMBuilderRef builder = ctx->ac.builder;
4599 LLVMTypeRef type;
4600
4601 assert(base_index < layout->binding_count);
4602
4603 switch (desc_type) {
4604 case AC_DESC_IMAGE:
4605 type = ctx->ac.v8i32;
4606 type_size = 32;
4607 break;
4608 case AC_DESC_FMASK:
4609 type = ctx->ac.v8i32;
4610 offset += 32;
4611 type_size = 32;
4612 break;
4613 case AC_DESC_SAMPLER:
4614 type = ctx->ac.v4i32;
4615 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4616 offset += 64;
4617
4618 type_size = 16;
4619 break;
4620 case AC_DESC_BUFFER:
4621 type = ctx->ac.v4i32;
4622 type_size = 16;
4623 break;
4624 default:
4625 unreachable("invalid desc_type\n");
4626 }
4627
4628 offset += constant_index * stride;
4629
4630 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4631 (!index || binding->immutable_samplers_equal)) {
4632 if (binding->immutable_samplers_equal)
4633 constant_index = 0;
4634
4635 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4636
4637 LLVMValueRef constants[] = {
4638 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4639 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4640 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4641 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4642 };
4643 return ac_build_gather_values(&ctx->ac, constants, 4);
4644 }
4645
4646 assert(stride % type_size == 0);
4647
4648 if (!index)
4649 index = ctx->ac.i32_0;
4650
4651 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4652
4653 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4654 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4655
4656 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4657 }
4658
4659 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4660 const nir_deref_var *deref,
4661 enum ac_descriptor_type desc_type,
4662 const nir_tex_instr *tex_instr,
4663 bool image, bool write)
4664 {
4665 LLVMValueRef index = NULL;
4666 unsigned constant_index = 0;
4667 unsigned descriptor_set;
4668 unsigned base_index;
4669
4670 if (!deref) {
4671 assert(tex_instr && !image);
4672 descriptor_set = 0;
4673 base_index = tex_instr->sampler_index;
4674 } else {
4675 const nir_deref *tail = &deref->deref;
4676 while (tail->child) {
4677 const nir_deref_array *child = nir_deref_as_array(tail->child);
4678 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4679
4680 if (!array_size)
4681 array_size = 1;
4682
4683 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4684
4685 if (child->deref_array_type == nir_deref_array_type_indirect) {
4686 LLVMValueRef indirect = get_src(ctx, child->indirect);
4687
4688 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4689 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4690
4691 if (!index)
4692 index = indirect;
4693 else
4694 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4695 }
4696
4697 constant_index += child->base_offset * array_size;
4698
4699 tail = &child->deref;
4700 }
4701 descriptor_set = deref->var->data.descriptor_set;
4702 base_index = deref->var->data.binding;
4703 }
4704
4705 return ctx->abi->load_sampler_desc(ctx->abi,
4706 descriptor_set,
4707 base_index,
4708 constant_index, index,
4709 desc_type, image, write);
4710 }
4711
4712 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4713 struct ac_image_args *args,
4714 const nir_tex_instr *instr,
4715 nir_texop op,
4716 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4717 LLVMValueRef *param, unsigned count,
4718 unsigned dmask)
4719 {
4720 unsigned is_rect = 0;
4721 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4722
4723 if (op == nir_texop_lod)
4724 da = false;
4725 /* Pad to power of two vector */
4726 while (count < util_next_power_of_two(count))
4727 param[count++] = LLVMGetUndef(ctx->i32);
4728
4729 if (count > 1)
4730 args->addr = ac_build_gather_values(ctx, param, count);
4731 else
4732 args->addr = param[0];
4733
4734 args->resource = res_ptr;
4735 args->sampler = samp_ptr;
4736
4737 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4738 args->addr = param[0];
4739 return;
4740 }
4741
4742 args->dmask = dmask;
4743 args->unorm = is_rect;
4744 args->da = da;
4745 }
4746
4747 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4748 *
4749 * SI-CI:
4750 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4751 * filtering manually. The driver sets img7 to a mask clearing
4752 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4753 * s_and_b32 samp0, samp0, img7
4754 *
4755 * VI:
4756 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4757 */
4758 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4759 LLVMValueRef res, LLVMValueRef samp)
4760 {
4761 LLVMBuilderRef builder = ctx->ac.builder;
4762 LLVMValueRef img7, samp0;
4763
4764 if (ctx->ac.chip_class >= VI)
4765 return samp;
4766
4767 img7 = LLVMBuildExtractElement(builder, res,
4768 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4769 samp0 = LLVMBuildExtractElement(builder, samp,
4770 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4771 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4772 return LLVMBuildInsertElement(builder, samp, samp0,
4773 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4774 }
4775
4776 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4777 nir_tex_instr *instr,
4778 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4779 LLVMValueRef *fmask_ptr)
4780 {
4781 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4782 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4783 else
4784 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4785 if (samp_ptr) {
4786 if (instr->sampler)
4787 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4788 else
4789 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4790 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4791 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4792 }
4793 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4794 instr->op == nir_texop_samples_identical))
4795 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4796 }
4797
4798 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4799 LLVMValueRef coord)
4800 {
4801 coord = ac_to_float(ctx, coord);
4802 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4803 coord = ac_to_integer(ctx, coord);
4804 return coord;
4805 }
4806
4807 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4808 {
4809 LLVMValueRef result = NULL;
4810 struct ac_image_args args = { 0 };
4811 unsigned dmask = 0xf;
4812 LLVMValueRef address[16];
4813 LLVMValueRef coords[5];
4814 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4815 LLVMValueRef bias = NULL, offsets = NULL;
4816 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4817 LLVMValueRef ddx = NULL, ddy = NULL;
4818 LLVMValueRef derivs[6];
4819 unsigned chan, count = 0;
4820 unsigned const_src = 0, num_deriv_comp = 0;
4821 bool lod_is_zero = false;
4822
4823 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4824
4825 for (unsigned i = 0; i < instr->num_srcs; i++) {
4826 switch (instr->src[i].src_type) {
4827 case nir_tex_src_coord:
4828 coord = get_src(ctx, instr->src[i].src);
4829 break;
4830 case nir_tex_src_projector:
4831 break;
4832 case nir_tex_src_comparator:
4833 comparator = get_src(ctx, instr->src[i].src);
4834 break;
4835 case nir_tex_src_offset:
4836 offsets = get_src(ctx, instr->src[i].src);
4837 const_src = i;
4838 break;
4839 case nir_tex_src_bias:
4840 bias = get_src(ctx, instr->src[i].src);
4841 break;
4842 case nir_tex_src_lod: {
4843 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4844
4845 if (val && val->i32[0] == 0)
4846 lod_is_zero = true;
4847 lod = get_src(ctx, instr->src[i].src);
4848 break;
4849 }
4850 case nir_tex_src_ms_index:
4851 sample_index = get_src(ctx, instr->src[i].src);
4852 break;
4853 case nir_tex_src_ms_mcs:
4854 break;
4855 case nir_tex_src_ddx:
4856 ddx = get_src(ctx, instr->src[i].src);
4857 num_deriv_comp = instr->src[i].src.ssa->num_components;
4858 break;
4859 case nir_tex_src_ddy:
4860 ddy = get_src(ctx, instr->src[i].src);
4861 break;
4862 case nir_tex_src_texture_offset:
4863 case nir_tex_src_sampler_offset:
4864 case nir_tex_src_plane:
4865 default:
4866 break;
4867 }
4868 }
4869
4870 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4871 result = get_buffer_size(ctx, res_ptr, true);
4872 goto write_result;
4873 }
4874
4875 if (instr->op == nir_texop_texture_samples) {
4876 LLVMValueRef res, samples, is_msaa;
4877 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4878 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4879 LLVMConstInt(ctx->ac.i32, 3, false), "");
4880 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4881 LLVMConstInt(ctx->ac.i32, 28, false), "");
4882 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4883 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4884 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4885 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4886
4887 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4888 LLVMConstInt(ctx->ac.i32, 16, false), "");
4889 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4890 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4891 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4892 samples, "");
4893 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4894 ctx->ac.i32_1, "");
4895 result = samples;
4896 goto write_result;
4897 }
4898
4899 if (coord)
4900 for (chan = 0; chan < instr->coord_components; chan++)
4901 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4902
4903 if (offsets && instr->op != nir_texop_txf) {
4904 LLVMValueRef offset[3], pack;
4905 for (chan = 0; chan < 3; ++chan)
4906 offset[chan] = ctx->ac.i32_0;
4907
4908 args.offset = true;
4909 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4910 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4911 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4912 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4913 if (chan)
4914 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4915 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4916 }
4917 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4918 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4919 address[count++] = pack;
4920
4921 }
4922 /* pack LOD bias value */
4923 if (instr->op == nir_texop_txb && bias) {
4924 address[count++] = bias;
4925 }
4926
4927 /* Pack depth comparison value */
4928 if (instr->is_shadow && comparator) {
4929 LLVMValueRef z = ac_to_float(&ctx->ac,
4930 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4931
4932 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4933 * so the depth comparison value isn't clamped for Z16 and
4934 * Z24 anymore. Do it manually here.
4935 *
4936 * It's unnecessary if the original texture format was
4937 * Z32_FLOAT, but we don't know that here.
4938 */
4939 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4940 z = ac_build_clamp(&ctx->ac, z);
4941
4942 address[count++] = z;
4943 }
4944
4945 /* pack derivatives */
4946 if (ddx || ddy) {
4947 int num_src_deriv_channels, num_dest_deriv_channels;
4948 switch (instr->sampler_dim) {
4949 case GLSL_SAMPLER_DIM_3D:
4950 case GLSL_SAMPLER_DIM_CUBE:
4951 num_deriv_comp = 3;
4952 num_src_deriv_channels = 3;
4953 num_dest_deriv_channels = 3;
4954 break;
4955 case GLSL_SAMPLER_DIM_2D:
4956 default:
4957 num_src_deriv_channels = 2;
4958 num_dest_deriv_channels = 2;
4959 num_deriv_comp = 2;
4960 break;
4961 case GLSL_SAMPLER_DIM_1D:
4962 num_src_deriv_channels = 1;
4963 if (ctx->ac.chip_class >= GFX9) {
4964 num_dest_deriv_channels = 2;
4965 num_deriv_comp = 2;
4966 } else {
4967 num_dest_deriv_channels = 1;
4968 num_deriv_comp = 1;
4969 }
4970 break;
4971 }
4972
4973 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4974 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4975 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4976 }
4977 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4978 derivs[i] = ctx->ac.f32_0;
4979 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4980 }
4981 }
4982
4983 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4984 for (chan = 0; chan < instr->coord_components; chan++)
4985 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4986 if (instr->coord_components == 3)
4987 coords[3] = LLVMGetUndef(ctx->ac.f32);
4988 ac_prepare_cube_coords(&ctx->ac,
4989 instr->op == nir_texop_txd, instr->is_array,
4990 instr->op == nir_texop_lod, coords, derivs);
4991 if (num_deriv_comp)
4992 num_deriv_comp--;
4993 }
4994
4995 if (ddx || ddy) {
4996 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4997 address[count++] = derivs[i];
4998 }
4999
5000 /* Pack texture coordinates */
5001 if (coord) {
5002 address[count++] = coords[0];
5003 if (instr->coord_components > 1) {
5004 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5005 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5006 }
5007 address[count++] = coords[1];
5008 }
5009 if (instr->coord_components > 2) {
5010 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5011 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
5012 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
5013 instr->op != nir_texop_txf) {
5014 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5015 }
5016 address[count++] = coords[2];
5017 }
5018
5019 if (ctx->ac.chip_class >= GFX9) {
5020 LLVMValueRef filler;
5021 if (instr->op == nir_texop_txf)
5022 filler = ctx->ac.i32_0;
5023 else
5024 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5025
5026 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5027 /* No nir_texop_lod, because it does not take a slice
5028 * even with array textures. */
5029 if (instr->is_array && instr->op != nir_texop_lod ) {
5030 address[count] = address[count - 1];
5031 address[count - 1] = filler;
5032 count++;
5033 } else
5034 address[count++] = filler;
5035 }
5036 }
5037 }
5038
5039 /* Pack LOD */
5040 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5041 instr->op == nir_texop_txf)) {
5042 address[count++] = lod;
5043 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5044 address[count++] = sample_index;
5045 } else if(instr->op == nir_texop_txs) {
5046 count = 0;
5047 if (lod)
5048 address[count++] = lod;
5049 else
5050 address[count++] = ctx->ac.i32_0;
5051 }
5052
5053 for (chan = 0; chan < count; chan++) {
5054 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5055 address[chan], ctx->ac.i32, "");
5056 }
5057
5058 if (instr->op == nir_texop_samples_identical) {
5059 LLVMValueRef txf_address[4];
5060 struct ac_image_args txf_args = { 0 };
5061 unsigned txf_count = count;
5062 memcpy(txf_address, address, sizeof(txf_address));
5063
5064 if (!instr->is_array)
5065 txf_address[2] = ctx->ac.i32_0;
5066 txf_address[3] = ctx->ac.i32_0;
5067
5068 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5069 fmask_ptr, NULL,
5070 txf_address, txf_count, 0xf);
5071
5072 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5073
5074 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5075 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5076 goto write_result;
5077 }
5078
5079 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5080 instr->op != nir_texop_txs) {
5081 unsigned sample_chan = instr->is_array ? 3 : 2;
5082 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5083 address[0],
5084 address[1],
5085 instr->is_array ? address[2] : NULL,
5086 address[sample_chan],
5087 fmask_ptr);
5088 }
5089
5090 if (offsets && instr->op == nir_texop_txf) {
5091 nir_const_value *const_offset =
5092 nir_src_as_const_value(instr->src[const_src].src);
5093 int num_offsets = instr->src[const_src].src.ssa->num_components;
5094 assert(const_offset);
5095 num_offsets = MIN2(num_offsets, instr->coord_components);
5096 if (num_offsets > 2)
5097 address[2] = LLVMBuildAdd(ctx->ac.builder,
5098 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5099 if (num_offsets > 1)
5100 address[1] = LLVMBuildAdd(ctx->ac.builder,
5101 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5102 address[0] = LLVMBuildAdd(ctx->ac.builder,
5103 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5104
5105 }
5106
5107 /* TODO TG4 support */
5108 if (instr->op == nir_texop_tg4) {
5109 if (instr->is_shadow)
5110 dmask = 1;
5111 else
5112 dmask = 1 << instr->component;
5113 }
5114 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5115 res_ptr, samp_ptr, address, count, dmask);
5116
5117 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5118
5119 if (instr->op == nir_texop_query_levels)
5120 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5121 else if (instr->is_shadow && instr->is_new_style_shadow &&
5122 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5123 instr->op != nir_texop_tg4)
5124 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5125 else if (instr->op == nir_texop_txs &&
5126 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5127 instr->is_array) {
5128 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5129 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5130 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5131 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5132 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5133 } else if (ctx->ac.chip_class >= GFX9 &&
5134 instr->op == nir_texop_txs &&
5135 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5136 instr->is_array) {
5137 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5138 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5139 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5140 ctx->ac.i32_1, "");
5141 } else if (instr->dest.ssa.num_components != 4)
5142 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5143
5144 write_result:
5145 if (result) {
5146 assert(instr->dest.is_ssa);
5147 result = ac_to_integer(&ctx->ac, result);
5148 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5149 }
5150 }
5151
5152
5153 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5154 {
5155 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5156 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5157
5158 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5159 _mesa_hash_table_insert(ctx->phis, instr, result);
5160 }
5161
5162 static void visit_post_phi(struct ac_nir_context *ctx,
5163 nir_phi_instr *instr,
5164 LLVMValueRef llvm_phi)
5165 {
5166 nir_foreach_phi_src(src, instr) {
5167 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5168 LLVMValueRef llvm_src = get_src(ctx, src->src);
5169
5170 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5171 }
5172 }
5173
5174 static void phi_post_pass(struct ac_nir_context *ctx)
5175 {
5176 struct hash_entry *entry;
5177 hash_table_foreach(ctx->phis, entry) {
5178 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5179 (LLVMValueRef)entry->data);
5180 }
5181 }
5182
5183
5184 static void visit_ssa_undef(struct ac_nir_context *ctx,
5185 const nir_ssa_undef_instr *instr)
5186 {
5187 unsigned num_components = instr->def.num_components;
5188 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5189 LLVMValueRef undef;
5190
5191 if (num_components == 1)
5192 undef = LLVMGetUndef(type);
5193 else {
5194 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5195 }
5196 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5197 }
5198
5199 static void visit_jump(struct ac_nir_context *ctx,
5200 const nir_jump_instr *instr)
5201 {
5202 switch (instr->type) {
5203 case nir_jump_break:
5204 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5205 LLVMClearInsertionPosition(ctx->ac.builder);
5206 break;
5207 case nir_jump_continue:
5208 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5209 LLVMClearInsertionPosition(ctx->ac.builder);
5210 break;
5211 default:
5212 fprintf(stderr, "Unknown NIR jump instr: ");
5213 nir_print_instr(&instr->instr, stderr);
5214 fprintf(stderr, "\n");
5215 abort();
5216 }
5217 }
5218
5219 static void visit_cf_list(struct ac_nir_context *ctx,
5220 struct exec_list *list);
5221
5222 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5223 {
5224 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5225 nir_foreach_instr(instr, block)
5226 {
5227 switch (instr->type) {
5228 case nir_instr_type_alu:
5229 visit_alu(ctx, nir_instr_as_alu(instr));
5230 break;
5231 case nir_instr_type_load_const:
5232 visit_load_const(ctx, nir_instr_as_load_const(instr));
5233 break;
5234 case nir_instr_type_intrinsic:
5235 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5236 break;
5237 case nir_instr_type_tex:
5238 visit_tex(ctx, nir_instr_as_tex(instr));
5239 break;
5240 case nir_instr_type_phi:
5241 visit_phi(ctx, nir_instr_as_phi(instr));
5242 break;
5243 case nir_instr_type_ssa_undef:
5244 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5245 break;
5246 case nir_instr_type_jump:
5247 visit_jump(ctx, nir_instr_as_jump(instr));
5248 break;
5249 default:
5250 fprintf(stderr, "Unknown NIR instr type: ");
5251 nir_print_instr(instr, stderr);
5252 fprintf(stderr, "\n");
5253 abort();
5254 }
5255 }
5256
5257 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5258 }
5259
5260 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5261 {
5262 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5263
5264 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5265 LLVMBasicBlockRef merge_block =
5266 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5267 LLVMBasicBlockRef if_block =
5268 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5269 LLVMBasicBlockRef else_block = merge_block;
5270 if (!exec_list_is_empty(&if_stmt->else_list))
5271 else_block = LLVMAppendBasicBlockInContext(
5272 ctx->ac.context, fn, "");
5273
5274 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5275 ctx->ac.i32_0, "");
5276 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5277
5278 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5279 visit_cf_list(ctx, &if_stmt->then_list);
5280 if (LLVMGetInsertBlock(ctx->ac.builder))
5281 LLVMBuildBr(ctx->ac.builder, merge_block);
5282
5283 if (!exec_list_is_empty(&if_stmt->else_list)) {
5284 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5285 visit_cf_list(ctx, &if_stmt->else_list);
5286 if (LLVMGetInsertBlock(ctx->ac.builder))
5287 LLVMBuildBr(ctx->ac.builder, merge_block);
5288 }
5289
5290 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5291 }
5292
5293 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5294 {
5295 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5296 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5297 LLVMBasicBlockRef break_parent = ctx->break_block;
5298
5299 ctx->continue_block =
5300 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5301 ctx->break_block =
5302 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5303
5304 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5305 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5306 visit_cf_list(ctx, &loop->body);
5307
5308 if (LLVMGetInsertBlock(ctx->ac.builder))
5309 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5310 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5311
5312 ctx->continue_block = continue_parent;
5313 ctx->break_block = break_parent;
5314 }
5315
5316 static void visit_cf_list(struct ac_nir_context *ctx,
5317 struct exec_list *list)
5318 {
5319 foreach_list_typed(nir_cf_node, node, node, list)
5320 {
5321 switch (node->type) {
5322 case nir_cf_node_block:
5323 visit_block(ctx, nir_cf_node_as_block(node));
5324 break;
5325
5326 case nir_cf_node_if:
5327 visit_if(ctx, nir_cf_node_as_if(node));
5328 break;
5329
5330 case nir_cf_node_loop:
5331 visit_loop(ctx, nir_cf_node_as_loop(node));
5332 break;
5333
5334 default:
5335 assert(0);
5336 }
5337 }
5338 }
5339
5340 static void
5341 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5342 struct nir_variable *variable)
5343 {
5344 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5345 LLVMValueRef t_offset;
5346 LLVMValueRef t_list;
5347 LLVMValueRef input;
5348 LLVMValueRef buffer_index;
5349 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5350 int idx = variable->data.location;
5351 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5352 uint8_t input_usage_mask =
5353 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5354 unsigned num_channels = util_last_bit(input_usage_mask);
5355
5356 variable->data.driver_location = idx * 4;
5357
5358 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5359 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5360 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5361 ctx->abi.start_instance, "");
5362 if (ctx->options->key.vs.as_ls) {
5363 ctx->shader_info->vs.vgpr_comp_cnt =
5364 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5365 } else {
5366 ctx->shader_info->vs.vgpr_comp_cnt =
5367 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5368 }
5369 } else
5370 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5371 ctx->abi.base_vertex, "");
5372 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5373
5374 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5375
5376 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5377 buffer_index,
5378 ctx->ac.i32_0,
5379 num_channels, false, true);
5380
5381 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5382
5383 for (unsigned chan = 0; chan < 4; chan++) {
5384 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5385 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5386 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5387 input, llvm_chan, ""));
5388 }
5389 }
5390 }
5391
5392 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5393 unsigned attr,
5394 LLVMValueRef interp_param,
5395 LLVMValueRef prim_mask,
5396 LLVMValueRef result[4])
5397 {
5398 LLVMValueRef attr_number;
5399 unsigned chan;
5400 LLVMValueRef i, j;
5401 bool interp = interp_param != NULL;
5402
5403 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5404
5405 /* fs.constant returns the param from the middle vertex, so it's not
5406 * really useful for flat shading. It's meant to be used for custom
5407 * interpolation (but the intrinsic can't fetch from the other two
5408 * vertices).
5409 *
5410 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5411 * to do the right thing. The only reason we use fs.constant is that
5412 * fs.interp cannot be used on integers, because they can be equal
5413 * to NaN.
5414 */
5415 if (interp) {
5416 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5417 ctx->ac.v2f32, "");
5418
5419 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5420 ctx->ac.i32_0, "");
5421 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5422 ctx->ac.i32_1, "");
5423 }
5424
5425 for (chan = 0; chan < 4; chan++) {
5426 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5427
5428 if (interp) {
5429 result[chan] = ac_build_fs_interp(&ctx->ac,
5430 llvm_chan,
5431 attr_number,
5432 prim_mask, i, j);
5433 } else {
5434 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5435 LLVMConstInt(ctx->ac.i32, 2, false),
5436 llvm_chan,
5437 attr_number,
5438 prim_mask);
5439 }
5440 }
5441 }
5442
5443 static void
5444 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5445 struct nir_variable *variable)
5446 {
5447 int idx = variable->data.location;
5448 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5449 LLVMValueRef interp;
5450
5451 variable->data.driver_location = idx * 4;
5452 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5453
5454 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5455 unsigned interp_type;
5456 if (variable->data.sample) {
5457 interp_type = INTERP_SAMPLE;
5458 ctx->shader_info->info.ps.force_persample = true;
5459 } else if (variable->data.centroid)
5460 interp_type = INTERP_CENTROID;
5461 else
5462 interp_type = INTERP_CENTER;
5463
5464 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5465 } else
5466 interp = NULL;
5467
5468 for (unsigned i = 0; i < attrib_count; ++i)
5469 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5470
5471 }
5472
5473 static void
5474 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5475 struct nir_shader *nir) {
5476 nir_foreach_variable(variable, &nir->inputs)
5477 handle_vs_input_decl(ctx, variable);
5478 }
5479
5480 static void
5481 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5482 struct nir_shader *nir)
5483 {
5484 if (!ctx->options->key.fs.multisample)
5485 return;
5486
5487 bool uses_center = false;
5488 bool uses_centroid = false;
5489 nir_foreach_variable(variable, &nir->inputs) {
5490 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5491 variable->data.sample)
5492 continue;
5493
5494 if (variable->data.centroid)
5495 uses_centroid = true;
5496 else
5497 uses_center = true;
5498 }
5499
5500 if (uses_center && uses_centroid) {
5501 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5502 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5503 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5504 }
5505 }
5506
5507 static void
5508 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5509 struct nir_shader *nir)
5510 {
5511 prepare_interp_optimize(ctx, nir);
5512
5513 nir_foreach_variable(variable, &nir->inputs)
5514 handle_fs_input_decl(ctx, variable);
5515
5516 unsigned index = 0;
5517
5518 if (ctx->shader_info->info.ps.uses_input_attachments ||
5519 ctx->shader_info->info.needs_multiview_view_index)
5520 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5521
5522 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5523 LLVMValueRef interp_param;
5524 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5525
5526 if (!(ctx->input_mask & (1ull << i)))
5527 continue;
5528
5529 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5530 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5531 interp_param = *inputs;
5532 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5533 inputs);
5534
5535 if (!interp_param)
5536 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5537 ++index;
5538 } else if (i == VARYING_SLOT_POS) {
5539 for(int i = 0; i < 3; ++i)
5540 inputs[i] = ctx->abi.frag_pos[i];
5541
5542 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5543 ctx->abi.frag_pos[3]);
5544 }
5545 }
5546 ctx->shader_info->fs.num_interp = index;
5547 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5548 ctx->shader_info->fs.has_pcoord = true;
5549 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5550 ctx->shader_info->fs.prim_id_input = true;
5551 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5552 ctx->shader_info->fs.layer_input = true;
5553 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5554
5555 if (ctx->shader_info->info.needs_multiview_view_index)
5556 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5557 }
5558
5559 static LLVMValueRef
5560 ac_build_alloca(struct ac_llvm_context *ac,
5561 LLVMTypeRef type,
5562 const char *name)
5563 {
5564 LLVMBuilderRef builder = ac->builder;
5565 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5566 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5567 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5568 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5569 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5570 LLVMValueRef res;
5571
5572 if (first_instr) {
5573 LLVMPositionBuilderBefore(first_builder, first_instr);
5574 } else {
5575 LLVMPositionBuilderAtEnd(first_builder, first_block);
5576 }
5577
5578 res = LLVMBuildAlloca(first_builder, type, name);
5579 LLVMBuildStore(builder, LLVMConstNull(type), res);
5580
5581 LLVMDisposeBuilder(first_builder);
5582
5583 return res;
5584 }
5585
5586 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5587 LLVMTypeRef type,
5588 const char *name)
5589 {
5590 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5591 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5592 return ptr;
5593 }
5594
5595 static void
5596 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5597 struct nir_variable *variable,
5598 struct nir_shader *shader,
5599 gl_shader_stage stage)
5600 {
5601 int idx = variable->data.location + variable->data.index;
5602 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5603 uint64_t mask_attribs;
5604
5605 variable->data.driver_location = idx * 4;
5606
5607 /* tess ctrl has it's own load/store paths for outputs */
5608 if (stage == MESA_SHADER_TESS_CTRL)
5609 return;
5610
5611 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5612 if (stage == MESA_SHADER_VERTEX ||
5613 stage == MESA_SHADER_TESS_EVAL ||
5614 stage == MESA_SHADER_GEOMETRY) {
5615 if (idx == VARYING_SLOT_CLIP_DIST0) {
5616 int length = shader->info.clip_distance_array_size +
5617 shader->info.cull_distance_array_size;
5618 if (stage == MESA_SHADER_VERTEX) {
5619 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5620 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5621 }
5622 if (stage == MESA_SHADER_TESS_EVAL) {
5623 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5624 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5625 }
5626
5627 if (length > 4)
5628 attrib_count = 2;
5629 else
5630 attrib_count = 1;
5631 mask_attribs = 1ull << idx;
5632 }
5633 }
5634
5635 ctx->output_mask |= mask_attribs;
5636 }
5637
5638 static void
5639 handle_shader_output_decl(struct ac_nir_context *ctx,
5640 struct nir_shader *nir,
5641 struct nir_variable *variable)
5642 {
5643 unsigned output_loc = variable->data.driver_location / 4;
5644 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5645
5646 /* tess ctrl has it's own load/store paths for outputs */
5647 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5648 return;
5649
5650 if (ctx->stage == MESA_SHADER_VERTEX ||
5651 ctx->stage == MESA_SHADER_TESS_EVAL ||
5652 ctx->stage == MESA_SHADER_GEOMETRY) {
5653 int idx = variable->data.location + variable->data.index;
5654 if (idx == VARYING_SLOT_CLIP_DIST0) {
5655 int length = nir->info.clip_distance_array_size +
5656 nir->info.cull_distance_array_size;
5657
5658 if (length > 4)
5659 attrib_count = 2;
5660 else
5661 attrib_count = 1;
5662 }
5663 }
5664
5665 for (unsigned i = 0; i < attrib_count; ++i) {
5666 for (unsigned chan = 0; chan < 4; chan++) {
5667 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5668 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5669 }
5670 }
5671 }
5672
5673 static LLVMTypeRef
5674 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5675 enum glsl_base_type type)
5676 {
5677 switch (type) {
5678 case GLSL_TYPE_INT:
5679 case GLSL_TYPE_UINT:
5680 case GLSL_TYPE_BOOL:
5681 case GLSL_TYPE_SUBROUTINE:
5682 return ac->i32;
5683 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5684 return ac->f32;
5685 case GLSL_TYPE_INT64:
5686 case GLSL_TYPE_UINT64:
5687 return ac->i64;
5688 case GLSL_TYPE_DOUBLE:
5689 return ac->f64;
5690 default:
5691 unreachable("unknown GLSL type");
5692 }
5693 }
5694
5695 static LLVMTypeRef
5696 glsl_to_llvm_type(struct ac_llvm_context *ac,
5697 const struct glsl_type *type)
5698 {
5699 if (glsl_type_is_scalar(type)) {
5700 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5701 }
5702
5703 if (glsl_type_is_vector(type)) {
5704 return LLVMVectorType(
5705 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5706 glsl_get_vector_elements(type));
5707 }
5708
5709 if (glsl_type_is_matrix(type)) {
5710 return LLVMArrayType(
5711 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5712 glsl_get_matrix_columns(type));
5713 }
5714
5715 if (glsl_type_is_array(type)) {
5716 return LLVMArrayType(
5717 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5718 glsl_get_length(type));
5719 }
5720
5721 assert(glsl_type_is_struct(type));
5722
5723 LLVMTypeRef member_types[glsl_get_length(type)];
5724
5725 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5726 member_types[i] =
5727 glsl_to_llvm_type(ac,
5728 glsl_get_struct_field(type, i));
5729 }
5730
5731 return LLVMStructTypeInContext(ac->context, member_types,
5732 glsl_get_length(type), false);
5733 }
5734
5735 static void
5736 setup_locals(struct ac_nir_context *ctx,
5737 struct nir_function *func)
5738 {
5739 int i, j;
5740 ctx->num_locals = 0;
5741 nir_foreach_variable(variable, &func->impl->locals) {
5742 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5743 variable->data.driver_location = ctx->num_locals * 4;
5744 variable->data.location_frac = 0;
5745 ctx->num_locals += attrib_count;
5746 }
5747 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5748 if (!ctx->locals)
5749 return;
5750
5751 for (i = 0; i < ctx->num_locals; i++) {
5752 for (j = 0; j < 4; j++) {
5753 ctx->locals[i * 4 + j] =
5754 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5755 }
5756 }
5757 }
5758
5759 static void
5760 setup_shared(struct ac_nir_context *ctx,
5761 struct nir_shader *nir)
5762 {
5763 nir_foreach_variable(variable, &nir->shared) {
5764 LLVMValueRef shared =
5765 LLVMAddGlobalInAddressSpace(
5766 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5767 variable->name ? variable->name : "",
5768 AC_LOCAL_ADDR_SPACE);
5769 _mesa_hash_table_insert(ctx->vars, variable, shared);
5770 }
5771 }
5772
5773 /* Initialize arguments for the shader export intrinsic */
5774 static void
5775 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5776 LLVMValueRef *values,
5777 unsigned target,
5778 struct ac_export_args *args)
5779 {
5780 /* Default is 0xf. Adjusted below depending on the format. */
5781 args->enabled_channels = 0xf;
5782
5783 /* Specify whether the EXEC mask represents the valid mask */
5784 args->valid_mask = 0;
5785
5786 /* Specify whether this is the last export */
5787 args->done = 0;
5788
5789 /* Specify the target we are exporting */
5790 args->target = target;
5791
5792 args->compr = false;
5793 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5794 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5795 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5796 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5797
5798 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5799 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5800 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5801 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5802 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5803 unsigned chan;
5804
5805 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5806 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5807 unsigned bits, bool hi) = NULL;
5808
5809 switch(col_format) {
5810 case V_028714_SPI_SHADER_ZERO:
5811 args->enabled_channels = 0; /* writemask */
5812 args->target = V_008DFC_SQ_EXP_NULL;
5813 break;
5814
5815 case V_028714_SPI_SHADER_32_R:
5816 args->enabled_channels = 1;
5817 args->out[0] = values[0];
5818 break;
5819
5820 case V_028714_SPI_SHADER_32_GR:
5821 args->enabled_channels = 0x3;
5822 args->out[0] = values[0];
5823 args->out[1] = values[1];
5824 break;
5825
5826 case V_028714_SPI_SHADER_32_AR:
5827 args->enabled_channels = 0x9;
5828 args->out[0] = values[0];
5829 args->out[3] = values[3];
5830 break;
5831
5832 case V_028714_SPI_SHADER_FP16_ABGR:
5833 packf = ac_build_cvt_pkrtz_f16;
5834 break;
5835
5836 case V_028714_SPI_SHADER_UNORM16_ABGR:
5837 packf = ac_build_cvt_pknorm_u16;
5838 break;
5839
5840 case V_028714_SPI_SHADER_SNORM16_ABGR:
5841 packf = ac_build_cvt_pknorm_i16;
5842 break;
5843
5844 case V_028714_SPI_SHADER_UINT16_ABGR:
5845 packi = ac_build_cvt_pk_u16;
5846 break;
5847
5848 case V_028714_SPI_SHADER_SINT16_ABGR:
5849 packi = ac_build_cvt_pk_i16;
5850 break;
5851
5852 default:
5853 case V_028714_SPI_SHADER_32_ABGR:
5854 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5855 break;
5856 }
5857
5858 /* Pack f16 or norm_i16/u16. */
5859 if (packf) {
5860 for (chan = 0; chan < 2; chan++) {
5861 LLVMValueRef pack_args[2] = {
5862 values[2 * chan],
5863 values[2 * chan + 1]
5864 };
5865 LLVMValueRef packed;
5866
5867 packed = packf(&ctx->ac, pack_args);
5868 args->out[chan] = ac_to_float(&ctx->ac, packed);
5869 }
5870 args->compr = 1; /* COMPR flag */
5871 }
5872
5873 /* Pack i16/u16. */
5874 if (packi) {
5875 for (chan = 0; chan < 2; chan++) {
5876 LLVMValueRef pack_args[2] = {
5877 ac_to_integer(&ctx->ac, values[2 * chan]),
5878 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5879 };
5880 LLVMValueRef packed;
5881
5882 packed = packi(&ctx->ac, pack_args,
5883 is_int8 ? 8 : is_int10 ? 10 : 16,
5884 chan == 1);
5885 args->out[chan] = ac_to_float(&ctx->ac, packed);
5886 }
5887 args->compr = 1; /* COMPR flag */
5888 }
5889 return;
5890 }
5891
5892 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5893
5894 for (unsigned i = 0; i < 4; ++i)
5895 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5896 }
5897
5898 static void
5899 radv_export_param(struct nir_to_llvm_context *ctx, unsigned index,
5900 LLVMValueRef *values)
5901 {
5902 struct ac_export_args args;
5903
5904 si_llvm_init_export_args(ctx, values,
5905 V_008DFC_SQ_EXP_PARAM + index, &args);
5906 ac_build_export(&ctx->ac, &args);
5907 }
5908
5909 static LLVMValueRef
5910 radv_load_output(struct nir_to_llvm_context *ctx, unsigned index, unsigned chan)
5911 {
5912 LLVMValueRef output =
5913 ctx->nir->outputs[radeon_llvm_reg_index_soa(index, chan)];
5914
5915 return LLVMBuildLoad(ctx->ac.builder, output, "");
5916 }
5917
5918 static void
5919 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5920 bool export_prim_id,
5921 struct ac_vs_output_info *outinfo)
5922 {
5923 uint32_t param_count = 0;
5924 unsigned target;
5925 unsigned pos_idx, num_pos_exports = 0;
5926 struct ac_export_args args, pos_args[4] = {};
5927 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5928 int i;
5929
5930 if (ctx->options->key.has_multiview_view_index) {
5931 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5932 if(!*tmp_out) {
5933 for(unsigned i = 0; i < 4; ++i)
5934 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5935 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5936 }
5937
5938 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
5939 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5940 }
5941
5942 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5943 sizeof(outinfo->vs_output_param_offset));
5944
5945 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5946 LLVMValueRef slots[8];
5947 unsigned j;
5948
5949 if (outinfo->cull_dist_mask)
5950 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5951
5952 i = VARYING_SLOT_CLIP_DIST0;
5953 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5954 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
5955
5956 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5957 slots[i] = LLVMGetUndef(ctx->ac.f32);
5958
5959 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5960 target = V_008DFC_SQ_EXP_POS + 3;
5961 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5962 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5963 &args, sizeof(args));
5964 }
5965
5966 target = V_008DFC_SQ_EXP_POS + 2;
5967 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5968 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5969 &args, sizeof(args));
5970
5971 }
5972
5973 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5974 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5975 for (unsigned j = 0; j < 4; j++)
5976 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
5977 }
5978 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5979
5980 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5981 outinfo->writes_pointsize = true;
5982 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
5983 }
5984
5985 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5986 outinfo->writes_layer = true;
5987 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
5988 }
5989
5990 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5991 outinfo->writes_viewport_index = true;
5992 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
5993 }
5994
5995 if (outinfo->writes_pointsize ||
5996 outinfo->writes_layer ||
5997 outinfo->writes_viewport_index) {
5998 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5999 (outinfo->writes_layer == true ? 4 : 0));
6000 pos_args[1].valid_mask = 0;
6001 pos_args[1].done = 0;
6002 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6003 pos_args[1].compr = 0;
6004 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6005 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6006 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6007 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6008
6009 if (outinfo->writes_pointsize == true)
6010 pos_args[1].out[0] = psize_value;
6011 if (outinfo->writes_layer == true)
6012 pos_args[1].out[2] = layer_value;
6013 if (outinfo->writes_viewport_index == true) {
6014 if (ctx->options->chip_class >= GFX9) {
6015 /* GFX9 has the layer in out.z[10:0] and the viewport
6016 * index in out.z[19:16].
6017 */
6018 LLVMValueRef v = viewport_index_value;
6019 v = ac_to_integer(&ctx->ac, v);
6020 v = LLVMBuildShl(ctx->ac.builder, v,
6021 LLVMConstInt(ctx->ac.i32, 16, false),
6022 "");
6023 v = LLVMBuildOr(ctx->ac.builder, v,
6024 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6025
6026 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6027 pos_args[1].enabled_channels |= 1 << 2;
6028 } else {
6029 pos_args[1].out[3] = viewport_index_value;
6030 pos_args[1].enabled_channels |= 1 << 3;
6031 }
6032 }
6033 }
6034 for (i = 0; i < 4; i++) {
6035 if (pos_args[i].out[0])
6036 num_pos_exports++;
6037 }
6038
6039 pos_idx = 0;
6040 for (i = 0; i < 4; i++) {
6041 if (!pos_args[i].out[0])
6042 continue;
6043
6044 /* Specify the target we are exporting */
6045 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6046 if (pos_idx == num_pos_exports)
6047 pos_args[i].done = 1;
6048 ac_build_export(&ctx->ac, &pos_args[i]);
6049 }
6050
6051 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6052 LLVMValueRef values[4];
6053 if (!(ctx->output_mask & (1ull << i)))
6054 continue;
6055
6056 if (i != VARYING_SLOT_LAYER &&
6057 i != VARYING_SLOT_PRIMITIVE_ID &&
6058 i < VARYING_SLOT_VAR0)
6059 continue;
6060
6061 for (unsigned j = 0; j < 4; j++)
6062 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6063
6064 radv_export_param(ctx, param_count, values);
6065
6066 outinfo->vs_output_param_offset[i] = param_count++;
6067 }
6068
6069 if (export_prim_id) {
6070 LLVMValueRef values[4];
6071
6072 values[0] = ctx->vs_prim_id;
6073 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6074 ctx->shader_info->vs.vgpr_comp_cnt);
6075 for (unsigned j = 1; j < 4; j++)
6076 values[j] = ctx->ac.f32_0;
6077
6078 radv_export_param(ctx, param_count, values);
6079
6080 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6081 outinfo->export_prim_id = true;
6082 }
6083
6084 outinfo->pos_exports = num_pos_exports;
6085 outinfo->param_exports = param_count;
6086 }
6087
6088 static void
6089 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6090 struct ac_es_output_info *outinfo)
6091 {
6092 int j;
6093 uint64_t max_output_written = 0;
6094 LLVMValueRef lds_base = NULL;
6095
6096 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6097 int param_index;
6098 int length = 4;
6099
6100 if (!(ctx->output_mask & (1ull << i)))
6101 continue;
6102
6103 if (i == VARYING_SLOT_CLIP_DIST0)
6104 length = ctx->num_output_clips + ctx->num_output_culls;
6105
6106 param_index = shader_io_get_unique_index(i);
6107
6108 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6109 }
6110
6111 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6112
6113 if (ctx->ac.chip_class >= GFX9) {
6114 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6115 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6116 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6117 LLVMConstInt(ctx->ac.i32, 24, false),
6118 LLVMConstInt(ctx->ac.i32, 4, false), false);
6119 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6120 LLVMBuildMul(ctx->ac.builder, wave_idx,
6121 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6122 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6123 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6124 }
6125
6126 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6127 LLVMValueRef dw_addr = NULL;
6128 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6129 int param_index;
6130 int length = 4;
6131
6132 if (!(ctx->output_mask & (1ull << i)))
6133 continue;
6134
6135 if (i == VARYING_SLOT_CLIP_DIST0)
6136 length = ctx->num_output_clips + ctx->num_output_culls;
6137
6138 param_index = shader_io_get_unique_index(i);
6139
6140 if (lds_base) {
6141 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6142 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6143 "");
6144 }
6145 for (j = 0; j < length; j++) {
6146 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6147 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6148
6149 if (ctx->ac.chip_class >= GFX9) {
6150 ac_lds_store(&ctx->ac, dw_addr,
6151 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6152 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6153 } else {
6154 ac_build_buffer_store_dword(&ctx->ac,
6155 ctx->esgs_ring,
6156 out_val, 1,
6157 NULL, ctx->es2gs_offset,
6158 (4 * param_index + j) * 4,
6159 1, 1, true, true);
6160 }
6161 }
6162 }
6163 }
6164
6165 static void
6166 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6167 {
6168 LLVMValueRef vertex_id = ctx->rel_auto_id;
6169 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6170 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6171 vertex_dw_stride, "");
6172
6173 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6174 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6175 int length = 4;
6176
6177 if (!(ctx->output_mask & (1ull << i)))
6178 continue;
6179
6180 if (i == VARYING_SLOT_CLIP_DIST0)
6181 length = ctx->num_output_clips + ctx->num_output_culls;
6182 int param = shader_io_get_unique_index(i);
6183 mark_tess_output(ctx, false, param);
6184 if (length > 4)
6185 mark_tess_output(ctx, false, param + 1);
6186 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6187 LLVMConstInt(ctx->ac.i32, param * 4, false),
6188 "");
6189 for (unsigned j = 0; j < length; j++) {
6190 ac_lds_store(&ctx->ac, dw_addr,
6191 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6192 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6193 }
6194 }
6195 }
6196
6197 struct ac_build_if_state
6198 {
6199 struct nir_to_llvm_context *ctx;
6200 LLVMValueRef condition;
6201 LLVMBasicBlockRef entry_block;
6202 LLVMBasicBlockRef true_block;
6203 LLVMBasicBlockRef false_block;
6204 LLVMBasicBlockRef merge_block;
6205 };
6206
6207 static LLVMBasicBlockRef
6208 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6209 {
6210 LLVMBasicBlockRef current_block;
6211 LLVMBasicBlockRef next_block;
6212 LLVMBasicBlockRef new_block;
6213
6214 /* get current basic block */
6215 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6216
6217 /* chqeck if there's another block after this one */
6218 next_block = LLVMGetNextBasicBlock(current_block);
6219 if (next_block) {
6220 /* insert the new block before the next block */
6221 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6222 }
6223 else {
6224 /* append new block after current block */
6225 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6226 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6227 }
6228 return new_block;
6229 }
6230
6231 static void
6232 ac_nir_build_if(struct ac_build_if_state *ifthen,
6233 struct nir_to_llvm_context *ctx,
6234 LLVMValueRef condition)
6235 {
6236 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6237
6238 memset(ifthen, 0, sizeof *ifthen);
6239 ifthen->ctx = ctx;
6240 ifthen->condition = condition;
6241 ifthen->entry_block = block;
6242
6243 /* create endif/merge basic block for the phi functions */
6244 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6245
6246 /* create/insert true_block before merge_block */
6247 ifthen->true_block =
6248 LLVMInsertBasicBlockInContext(ctx->context,
6249 ifthen->merge_block,
6250 "if-true-block");
6251
6252 /* successive code goes into the true block */
6253 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6254 }
6255
6256 /**
6257 * End a conditional.
6258 */
6259 static void
6260 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6261 {
6262 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6263
6264 /* Insert branch to the merge block from current block */
6265 LLVMBuildBr(builder, ifthen->merge_block);
6266
6267 /*
6268 * Now patch in the various branch instructions.
6269 */
6270
6271 /* Insert the conditional branch instruction at the end of entry_block */
6272 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6273 if (ifthen->false_block) {
6274 /* we have an else clause */
6275 LLVMBuildCondBr(builder, ifthen->condition,
6276 ifthen->true_block, ifthen->false_block);
6277 }
6278 else {
6279 /* no else clause */
6280 LLVMBuildCondBr(builder, ifthen->condition,
6281 ifthen->true_block, ifthen->merge_block);
6282 }
6283
6284 /* Resume building code at end of the ifthen->merge_block */
6285 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6286 }
6287
6288 static void
6289 write_tess_factors(struct nir_to_llvm_context *ctx)
6290 {
6291 unsigned stride, outer_comps, inner_comps;
6292 struct ac_build_if_state if_ctx, inner_if_ctx;
6293 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6294 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6295 unsigned tess_inner_index, tess_outer_index;
6296 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6297 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6298 int i;
6299 emit_barrier(&ctx->ac, ctx->stage);
6300
6301 switch (ctx->options->key.tcs.primitive_mode) {
6302 case GL_ISOLINES:
6303 stride = 2;
6304 outer_comps = 2;
6305 inner_comps = 0;
6306 break;
6307 case GL_TRIANGLES:
6308 stride = 4;
6309 outer_comps = 3;
6310 inner_comps = 1;
6311 break;
6312 case GL_QUADS:
6313 stride = 6;
6314 outer_comps = 4;
6315 inner_comps = 2;
6316 break;
6317 default:
6318 return;
6319 }
6320
6321 ac_nir_build_if(&if_ctx, ctx,
6322 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6323 invocation_id, ctx->ac.i32_0, ""));
6324
6325 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6326 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6327
6328 mark_tess_output(ctx, true, tess_inner_index);
6329 mark_tess_output(ctx, true, tess_outer_index);
6330 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6331 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6332 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6333 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6334 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6335
6336 for (i = 0; i < 4; i++) {
6337 inner[i] = LLVMGetUndef(ctx->ac.i32);
6338 outer[i] = LLVMGetUndef(ctx->ac.i32);
6339 }
6340
6341 // LINES reverseal
6342 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6343 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6344 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6345 ctx->ac.i32_1, "");
6346 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6347 } else {
6348 for (i = 0; i < outer_comps; i++) {
6349 outer[i] = out[i] =
6350 ac_lds_load(&ctx->ac, lds_outer);
6351 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6352 ctx->ac.i32_1, "");
6353 }
6354 for (i = 0; i < inner_comps; i++) {
6355 inner[i] = out[outer_comps+i] =
6356 ac_lds_load(&ctx->ac, lds_inner);
6357 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6358 ctx->ac.i32_1, "");
6359 }
6360 }
6361
6362 /* Convert the outputs to vectors for stores. */
6363 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6364 vec1 = NULL;
6365
6366 if (stride > 4)
6367 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6368
6369
6370 buffer = ctx->hs_ring_tess_factor;
6371 tf_base = ctx->tess_factor_offset;
6372 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6373 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6374 unsigned tf_offset = 0;
6375
6376 if (ctx->options->chip_class <= VI) {
6377 ac_nir_build_if(&inner_if_ctx, ctx,
6378 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6379 rel_patch_id, ctx->ac.i32_0, ""));
6380
6381 /* Store the dynamic HS control word. */
6382 ac_build_buffer_store_dword(&ctx->ac, buffer,
6383 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6384 1, ctx->ac.i32_0, tf_base,
6385 0, 1, 0, true, false);
6386 tf_offset += 4;
6387
6388 ac_nir_build_endif(&inner_if_ctx);
6389 }
6390
6391 /* Store the tessellation factors. */
6392 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6393 MIN2(stride, 4), byteoffset, tf_base,
6394 tf_offset, 1, 0, true, false);
6395 if (vec1)
6396 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6397 stride - 4, byteoffset, tf_base,
6398 16 + tf_offset, 1, 0, true, false);
6399
6400 //store to offchip for TES to read - only if TES reads them
6401 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6402 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6403 LLVMValueRef tf_inner_offset;
6404 unsigned param_outer, param_inner;
6405
6406 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6407 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6408 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6409
6410 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6411 util_next_power_of_two(outer_comps));
6412
6413 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6414 outer_comps, tf_outer_offset,
6415 ctx->oc_lds, 0, 1, 0, true, false);
6416 if (inner_comps) {
6417 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6418 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6419 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6420
6421 inner_vec = inner_comps == 1 ? inner[0] :
6422 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6423 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6424 inner_comps, tf_inner_offset,
6425 ctx->oc_lds, 0, 1, 0, true, false);
6426 }
6427 }
6428 ac_nir_build_endif(&if_ctx);
6429 }
6430
6431 static void
6432 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6433 {
6434 write_tess_factors(ctx);
6435 }
6436
6437 static bool
6438 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6439 LLVMValueRef *color, unsigned index, bool is_last,
6440 struct ac_export_args *args)
6441 {
6442 /* Export */
6443 si_llvm_init_export_args(ctx, color,
6444 V_008DFC_SQ_EXP_MRT + index, args);
6445
6446 if (is_last) {
6447 args->valid_mask = 1; /* whether the EXEC mask is valid */
6448 args->done = 1; /* DONE bit */
6449 } else if (!args->enabled_channels)
6450 return false; /* unnecessary NULL export */
6451
6452 return true;
6453 }
6454
6455 static void
6456 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6457 LLVMValueRef depth, LLVMValueRef stencil,
6458 LLVMValueRef samplemask)
6459 {
6460 struct ac_export_args args;
6461
6462 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6463
6464 ac_build_export(&ctx->ac, &args);
6465 }
6466
6467 static void
6468 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6469 {
6470 unsigned index = 0;
6471 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6472 struct ac_export_args color_args[8];
6473
6474 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6475 LLVMValueRef values[4];
6476 bool last = false;
6477
6478 if (!(ctx->output_mask & (1ull << i)))
6479 continue;
6480
6481 if (i < FRAG_RESULT_DATA0)
6482 continue;
6483
6484 for (unsigned j = 0; j < 4; j++)
6485 values[j] = ac_to_float(&ctx->ac,
6486 radv_load_output(ctx, i, j));
6487
6488 if (!ctx->shader_info->info.ps.writes_z &&
6489 !ctx->shader_info->info.ps.writes_stencil &&
6490 !ctx->shader_info->info.ps.writes_sample_mask)
6491 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6492
6493 bool ret = si_export_mrt_color(ctx, values,
6494 i - FRAG_RESULT_DATA0,
6495 last, &color_args[index]);
6496 if (ret)
6497 index++;
6498 }
6499
6500 /* Process depth, stencil, samplemask. */
6501 if (ctx->shader_info->info.ps.writes_z) {
6502 depth = ac_to_float(&ctx->ac,
6503 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6504 }
6505 if (ctx->shader_info->info.ps.writes_stencil) {
6506 stencil = ac_to_float(&ctx->ac,
6507 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6508 }
6509 if (ctx->shader_info->info.ps.writes_sample_mask) {
6510 samplemask = ac_to_float(&ctx->ac,
6511 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6512 }
6513
6514 /* Export PS outputs. */
6515 for (unsigned i = 0; i < index; i++)
6516 ac_build_export(&ctx->ac, &color_args[i]);
6517
6518 if (depth || stencil || samplemask)
6519 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6520 else if (!index)
6521 ac_build_export_null(&ctx->ac);
6522 }
6523
6524 static void
6525 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6526 {
6527 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6528 }
6529
6530 static void
6531 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6532 LLVMValueRef *addrs)
6533 {
6534 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6535
6536 switch (ctx->stage) {
6537 case MESA_SHADER_VERTEX:
6538 if (ctx->options->key.vs.as_ls)
6539 handle_ls_outputs_post(ctx);
6540 else if (ctx->options->key.vs.as_es)
6541 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6542 else
6543 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6544 &ctx->shader_info->vs.outinfo);
6545 break;
6546 case MESA_SHADER_FRAGMENT:
6547 handle_fs_outputs_post(ctx);
6548 break;
6549 case MESA_SHADER_GEOMETRY:
6550 emit_gs_epilogue(ctx);
6551 break;
6552 case MESA_SHADER_TESS_CTRL:
6553 handle_tcs_outputs_post(ctx);
6554 break;
6555 case MESA_SHADER_TESS_EVAL:
6556 if (ctx->options->key.tes.as_es)
6557 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6558 else
6559 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6560 &ctx->shader_info->tes.outinfo);
6561 break;
6562 default:
6563 break;
6564 }
6565 }
6566
6567 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6568 {
6569 LLVMPassManagerRef passmgr;
6570 /* Create the pass manager */
6571 passmgr = LLVMCreateFunctionPassManagerForModule(
6572 ctx->ac.module);
6573
6574 /* This pass should eliminate all the load and store instructions */
6575 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6576
6577 /* Add some optimization passes */
6578 LLVMAddScalarReplAggregatesPass(passmgr);
6579 LLVMAddLICMPass(passmgr);
6580 LLVMAddAggressiveDCEPass(passmgr);
6581 LLVMAddCFGSimplificationPass(passmgr);
6582 LLVMAddInstructionCombiningPass(passmgr);
6583
6584 /* Run the pass */
6585 LLVMInitializeFunctionPassManager(passmgr);
6586 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6587 LLVMFinalizeFunctionPassManager(passmgr);
6588
6589 LLVMDisposeBuilder(ctx->ac.builder);
6590 LLVMDisposePassManager(passmgr);
6591 }
6592
6593 static void
6594 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6595 {
6596 struct ac_vs_output_info *outinfo;
6597
6598 switch (ctx->stage) {
6599 case MESA_SHADER_FRAGMENT:
6600 case MESA_SHADER_COMPUTE:
6601 case MESA_SHADER_TESS_CTRL:
6602 case MESA_SHADER_GEOMETRY:
6603 return;
6604 case MESA_SHADER_VERTEX:
6605 if (ctx->options->key.vs.as_ls ||
6606 ctx->options->key.vs.as_es)
6607 return;
6608 outinfo = &ctx->shader_info->vs.outinfo;
6609 break;
6610 case MESA_SHADER_TESS_EVAL:
6611 if (ctx->options->key.vs.as_es)
6612 return;
6613 outinfo = &ctx->shader_info->tes.outinfo;
6614 break;
6615 default:
6616 unreachable("Unhandled shader type");
6617 }
6618
6619 ac_optimize_vs_outputs(&ctx->ac,
6620 ctx->main_function,
6621 outinfo->vs_output_param_offset,
6622 VARYING_SLOT_MAX,
6623 &outinfo->param_exports);
6624 }
6625
6626 static void
6627 ac_setup_rings(struct nir_to_llvm_context *ctx)
6628 {
6629 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6630 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6631 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6632 }
6633
6634 if (ctx->is_gs_copy_shader) {
6635 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6636 }
6637 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6638 LLVMValueRef tmp;
6639 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6640 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6641
6642 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6643
6644 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6645 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6646 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6647 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6648 }
6649
6650 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6651 ctx->stage == MESA_SHADER_TESS_EVAL) {
6652 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6653 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6654 }
6655 }
6656
6657 static unsigned
6658 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6659 const struct nir_shader *nir)
6660 {
6661 switch (nir->info.stage) {
6662 case MESA_SHADER_TESS_CTRL:
6663 return chip_class >= CIK ? 128 : 64;
6664 case MESA_SHADER_GEOMETRY:
6665 return chip_class >= GFX9 ? 128 : 64;
6666 case MESA_SHADER_COMPUTE:
6667 break;
6668 default:
6669 return 0;
6670 }
6671
6672 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6673 nir->info.cs.local_size[1] *
6674 nir->info.cs.local_size[2];
6675 return max_workgroup_size;
6676 }
6677
6678 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6679 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6680 {
6681 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6682 LLVMConstInt(ctx->ac.i32, 8, false),
6683 LLVMConstInt(ctx->ac.i32, 8, false), false);
6684 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6685 ctx->ac.i32_0, "");
6686 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6687 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6688 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6689 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6690 }
6691
6692 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6693 {
6694 for(int i = 5; i >= 0; --i) {
6695 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6696 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6697 LLVMConstInt(ctx->ac.i32, 16, false), false);
6698 }
6699
6700 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6701 LLVMConstInt(ctx->ac.i32, 16, false),
6702 LLVMConstInt(ctx->ac.i32, 8, false), false);
6703 }
6704
6705 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6706 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6707 {
6708 struct ac_nir_context ctx = {};
6709 struct nir_function *func;
6710
6711 ctx.ac = *ac;
6712 ctx.abi = abi;
6713
6714 if (nctx)
6715 nctx->nir = &ctx;
6716
6717 ctx.stage = nir->info.stage;
6718
6719 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6720
6721 nir_foreach_variable(variable, &nir->outputs)
6722 handle_shader_output_decl(&ctx, nir, variable);
6723
6724 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6725 _mesa_key_pointer_equal);
6726 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6727 _mesa_key_pointer_equal);
6728 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6729 _mesa_key_pointer_equal);
6730
6731 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6732
6733 setup_locals(&ctx, func);
6734
6735 if (nir->info.stage == MESA_SHADER_COMPUTE)
6736 setup_shared(&ctx, nir);
6737
6738 visit_cf_list(&ctx, &func->impl->body);
6739 phi_post_pass(&ctx);
6740
6741 if (nir->info.stage != MESA_SHADER_COMPUTE)
6742 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6743 ctx.outputs);
6744
6745 free(ctx.locals);
6746 ralloc_free(ctx.defs);
6747 ralloc_free(ctx.phis);
6748 ralloc_free(ctx.vars);
6749
6750 if (nctx)
6751 nctx->nir = NULL;
6752 }
6753
6754 static
6755 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6756 struct nir_shader *const *shaders,
6757 int shader_count,
6758 struct ac_shader_variant_info *shader_info,
6759 const struct ac_nir_compiler_options *options)
6760 {
6761 struct nir_to_llvm_context ctx = {0};
6762 unsigned i;
6763 ctx.options = options;
6764 ctx.shader_info = shader_info;
6765 ctx.context = LLVMContextCreate();
6766
6767 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6768 options->family);
6769 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6770 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6771
6772 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6773 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6774 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6775 LLVMDisposeTargetData(data_layout);
6776 LLVMDisposeMessage(data_layout_str);
6777
6778 enum ac_float_mode float_mode =
6779 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6780 AC_FLOAT_MODE_DEFAULT;
6781
6782 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6783
6784 memset(shader_info, 0, sizeof(*shader_info));
6785
6786 for(int i = 0; i < shader_count; ++i)
6787 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6788
6789 for (i = 0; i < AC_UD_MAX_SETS; i++)
6790 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6791 for (i = 0; i < AC_UD_MAX_UD; i++)
6792 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6793
6794 ctx.max_workgroup_size = 0;
6795 for (int i = 0; i < shader_count; ++i) {
6796 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6797 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6798 shaders[i]));
6799 }
6800
6801 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6802 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6803
6804 ctx.abi.inputs = &ctx.inputs[0];
6805 ctx.abi.emit_outputs = handle_shader_outputs_post;
6806 ctx.abi.emit_vertex = visit_emit_vertex;
6807 ctx.abi.load_ubo = radv_load_ubo;
6808 ctx.abi.load_ssbo = radv_load_ssbo;
6809 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6810 ctx.abi.load_resource = radv_load_resource;
6811 ctx.abi.clamp_shadow_reference = false;
6812
6813 if (shader_count >= 2)
6814 ac_init_exec_full_mask(&ctx.ac);
6815
6816 if (ctx.ac.chip_class == GFX9 &&
6817 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6818 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6819
6820 for(int i = 0; i < shader_count; ++i) {
6821 ctx.stage = shaders[i]->info.stage;
6822 ctx.output_mask = 0;
6823 ctx.tess_outputs_written = 0;
6824 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6825 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6826
6827 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6828 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6829 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6830 ctx.abi.load_inputs = load_gs_input;
6831 ctx.abi.emit_primitive = visit_end_primitive;
6832 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6833 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6834 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6835 ctx.abi.load_tess_varyings = load_tcs_varyings;
6836 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6837 ctx.abi.store_tcs_outputs = store_tcs_output;
6838 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6839 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6840 ctx.abi.load_tess_varyings = load_tes_input;
6841 ctx.abi.load_tess_coord = load_tess_coord;
6842 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6843 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6844 if (shader_info->info.vs.needs_instance_id) {
6845 if (ctx.options->key.vs.as_ls) {
6846 ctx.shader_info->vs.vgpr_comp_cnt =
6847 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6848 } else {
6849 ctx.shader_info->vs.vgpr_comp_cnt =
6850 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6851 }
6852 }
6853 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6854 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6855 ctx.abi.lookup_interp_param = lookup_interp_param;
6856 ctx.abi.load_sample_position = load_sample_position;
6857 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6858 }
6859
6860 if (i)
6861 emit_barrier(&ctx.ac, ctx.stage);
6862
6863 ac_setup_rings(&ctx);
6864
6865 LLVMBasicBlockRef merge_block;
6866 if (shader_count >= 2) {
6867 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6868 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6869 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6870
6871 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6872 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6873 LLVMConstInt(ctx.ac.i32, 8, false), false);
6874 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6875 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6876 thread_id, count, "");
6877 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6878
6879 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6880 }
6881
6882 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6883 handle_fs_inputs(&ctx, shaders[i]);
6884 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6885 handle_vs_inputs(&ctx, shaders[i]);
6886 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6887 prepare_gs_input_vgprs(&ctx);
6888
6889 nir_foreach_variable(variable, &shaders[i]->outputs)
6890 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6891
6892 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6893
6894 if (shader_count >= 2) {
6895 LLVMBuildBr(ctx.ac.builder, merge_block);
6896 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6897 }
6898
6899 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6900 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6901 shaders[i]->info.cull_distance_array_size > 4;
6902 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6903 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6904 shaders[i]->info.gs.vertices_out;
6905 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6906 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6907 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6908 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6909 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6910 }
6911 }
6912
6913 LLVMBuildRetVoid(ctx.ac.builder);
6914
6915 if (options->dump_preoptir)
6916 ac_dump_module(ctx.ac.module);
6917
6918 ac_llvm_finalize_module(&ctx);
6919
6920 if (shader_count == 1)
6921 ac_nir_eliminate_const_vs_outputs(&ctx);
6922
6923 return ctx.ac.module;
6924 }
6925
6926 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6927 {
6928 unsigned *retval = (unsigned *)context;
6929 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6930 char *description = LLVMGetDiagInfoDescription(di);
6931
6932 if (severity == LLVMDSError) {
6933 *retval = 1;
6934 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6935 description);
6936 }
6937
6938 LLVMDisposeMessage(description);
6939 }
6940
6941 static unsigned ac_llvm_compile(LLVMModuleRef M,
6942 struct ac_shader_binary *binary,
6943 LLVMTargetMachineRef tm)
6944 {
6945 unsigned retval = 0;
6946 char *err;
6947 LLVMContextRef llvm_ctx;
6948 LLVMMemoryBufferRef out_buffer;
6949 unsigned buffer_size;
6950 const char *buffer_data;
6951 LLVMBool mem_err;
6952
6953 /* Setup Diagnostic Handler*/
6954 llvm_ctx = LLVMGetModuleContext(M);
6955
6956 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6957 &retval);
6958
6959 /* Compile IR*/
6960 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6961 &err, &out_buffer);
6962
6963 /* Process Errors/Warnings */
6964 if (mem_err) {
6965 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6966 free(err);
6967 retval = 1;
6968 goto out;
6969 }
6970
6971 /* Extract Shader Code*/
6972 buffer_size = LLVMGetBufferSize(out_buffer);
6973 buffer_data = LLVMGetBufferStart(out_buffer);
6974
6975 ac_elf_read(buffer_data, buffer_size, binary);
6976
6977 /* Clean up */
6978 LLVMDisposeMemoryBuffer(out_buffer);
6979
6980 out:
6981 return retval;
6982 }
6983
6984 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6985 LLVMModuleRef llvm_module,
6986 struct ac_shader_binary *binary,
6987 struct ac_shader_config *config,
6988 struct ac_shader_variant_info *shader_info,
6989 gl_shader_stage stage,
6990 bool dump_shader, bool supports_spill)
6991 {
6992 if (dump_shader)
6993 ac_dump_module(llvm_module);
6994
6995 memset(binary, 0, sizeof(*binary));
6996 int v = ac_llvm_compile(llvm_module, binary, tm);
6997 if (v) {
6998 fprintf(stderr, "compile failed\n");
6999 }
7000
7001 if (dump_shader)
7002 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7003
7004 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7005
7006 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7007 LLVMDisposeModule(llvm_module);
7008 LLVMContextDispose(ctx);
7009
7010 if (stage == MESA_SHADER_FRAGMENT) {
7011 shader_info->num_input_vgprs = 0;
7012 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7013 shader_info->num_input_vgprs += 2;
7014 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7015 shader_info->num_input_vgprs += 2;
7016 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7017 shader_info->num_input_vgprs += 2;
7018 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7019 shader_info->num_input_vgprs += 3;
7020 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7021 shader_info->num_input_vgprs += 2;
7022 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7023 shader_info->num_input_vgprs += 2;
7024 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7025 shader_info->num_input_vgprs += 2;
7026 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7027 shader_info->num_input_vgprs += 1;
7028 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7029 shader_info->num_input_vgprs += 1;
7030 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7031 shader_info->num_input_vgprs += 1;
7032 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7033 shader_info->num_input_vgprs += 1;
7034 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7035 shader_info->num_input_vgprs += 1;
7036 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7037 shader_info->num_input_vgprs += 1;
7038 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7039 shader_info->num_input_vgprs += 1;
7040 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7041 shader_info->num_input_vgprs += 1;
7042 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7043 shader_info->num_input_vgprs += 1;
7044 }
7045 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7046
7047 /* +3 for scratch wave offset and VCC */
7048 config->num_sgprs = MAX2(config->num_sgprs,
7049 shader_info->num_input_sgprs + 3);
7050
7051 /* Enable 64-bit and 16-bit denormals, because there is no performance
7052 * cost.
7053 *
7054 * If denormals are enabled, all floating-point output modifiers are
7055 * ignored.
7056 *
7057 * Don't enable denormals for 32-bit floats, because:
7058 * - Floating-point output modifiers would be ignored by the hw.
7059 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7060 * have to stop using those.
7061 * - SI & CI would be very slow.
7062 */
7063 config->float_mode |= V_00B028_FP_64_DENORMS;
7064 }
7065
7066 static void
7067 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7068 {
7069 switch (nir->info.stage) {
7070 case MESA_SHADER_COMPUTE:
7071 for (int i = 0; i < 3; ++i)
7072 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7073 break;
7074 case MESA_SHADER_FRAGMENT:
7075 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7076 break;
7077 case MESA_SHADER_GEOMETRY:
7078 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7079 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7080 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7081 shader_info->gs.invocations = nir->info.gs.invocations;
7082 break;
7083 case MESA_SHADER_TESS_EVAL:
7084 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7085 shader_info->tes.spacing = nir->info.tess.spacing;
7086 shader_info->tes.ccw = nir->info.tess.ccw;
7087 shader_info->tes.point_mode = nir->info.tess.point_mode;
7088 shader_info->tes.as_es = options->key.tes.as_es;
7089 break;
7090 case MESA_SHADER_TESS_CTRL:
7091 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7092 break;
7093 case MESA_SHADER_VERTEX:
7094 shader_info->vs.as_es = options->key.vs.as_es;
7095 shader_info->vs.as_ls = options->key.vs.as_ls;
7096 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7097 if (options->key.vs.as_ls)
7098 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7099 break;
7100 default:
7101 break;
7102 }
7103 }
7104
7105 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7106 struct ac_shader_binary *binary,
7107 struct ac_shader_config *config,
7108 struct ac_shader_variant_info *shader_info,
7109 struct nir_shader *const *nir,
7110 int nir_count,
7111 const struct ac_nir_compiler_options *options,
7112 bool dump_shader)
7113 {
7114
7115 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7116 options);
7117
7118 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7119 for (int i = 0; i < nir_count; ++i)
7120 ac_fill_shader_info(shader_info, nir[i], options);
7121
7122 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7123 if (options->chip_class == GFX9) {
7124 if (nir_count == 2 &&
7125 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7126 shader_info->gs.es_type = nir[0]->info.stage;
7127 }
7128 }
7129 }
7130
7131 static void
7132 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7133 {
7134 LLVMValueRef vtx_offset =
7135 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7136 LLVMConstInt(ctx->ac.i32, 4, false), "");
7137 int idx = 0;
7138
7139 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7140 int length = 4;
7141 int slot = idx;
7142 int slot_inc = 1;
7143 if (!(ctx->output_mask & (1ull << i)))
7144 continue;
7145
7146 if (i == VARYING_SLOT_CLIP_DIST0) {
7147 /* unpack clip and cull from a single set of slots */
7148 length = ctx->num_output_clips + ctx->num_output_culls;
7149 if (length > 4)
7150 slot_inc = 2;
7151 }
7152
7153 for (unsigned j = 0; j < length; j++) {
7154 LLVMValueRef value, soffset;
7155
7156 soffset = LLVMConstInt(ctx->ac.i32,
7157 (slot * 4 + j) *
7158 ctx->gs_max_out_vertices * 16 * 4, false);
7159
7160 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7161 1, ctx->ac.i32_0,
7162 vtx_offset, soffset,
7163 0, 1, 1, true, false);
7164
7165 LLVMBuildStore(ctx->ac.builder,
7166 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7167 }
7168 idx += slot_inc;
7169 }
7170 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7171 }
7172
7173 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7174 struct nir_shader *geom_shader,
7175 struct ac_shader_binary *binary,
7176 struct ac_shader_config *config,
7177 struct ac_shader_variant_info *shader_info,
7178 const struct ac_nir_compiler_options *options,
7179 bool dump_shader)
7180 {
7181 struct nir_to_llvm_context ctx = {0};
7182 ctx.context = LLVMContextCreate();
7183 ctx.options = options;
7184 ctx.shader_info = shader_info;
7185
7186 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7187 options->family);
7188 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7189
7190 ctx.is_gs_copy_shader = true;
7191 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7192
7193 enum ac_float_mode float_mode =
7194 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7195 AC_FLOAT_MODE_DEFAULT;
7196
7197 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7198 ctx.stage = MESA_SHADER_VERTEX;
7199
7200 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7201
7202 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7203 ac_setup_rings(&ctx);
7204
7205 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7206 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7207
7208 struct ac_nir_context nir_ctx = {};
7209 nir_ctx.ac = ctx.ac;
7210 nir_ctx.abi = &ctx.abi;
7211
7212 ctx.nir = &nir_ctx;
7213
7214 nir_foreach_variable(variable, &geom_shader->outputs) {
7215 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7216 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7217 }
7218
7219 ac_gs_copy_shader_emit(&ctx);
7220
7221 ctx.nir = NULL;
7222
7223 LLVMBuildRetVoid(ctx.ac.builder);
7224
7225 ac_llvm_finalize_module(&ctx);
7226
7227 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7228 MESA_SHADER_VERTEX,
7229 dump_shader, options->supports_spill);
7230 }