2 * Copyright © 2016 Bas Nieuwenhuizen
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
37 enum radeon_llvm_calling_convention
{
38 RADEON_LLVM_AMDGPU_VS
= 87,
39 RADEON_LLVM_AMDGPU_GS
= 88,
40 RADEON_LLVM_AMDGPU_PS
= 89,
41 RADEON_LLVM_AMDGPU_CS
= 90,
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
57 struct nir_to_llvm_context
;
59 struct ac_nir_context
{
60 struct ac_llvm_context ac
;
61 struct ac_shader_abi
*abi
;
63 gl_shader_stage stage
;
65 struct hash_table
*defs
;
66 struct hash_table
*phis
;
67 struct hash_table
*vars
;
69 LLVMValueRef main_function
;
70 LLVMBasicBlockRef continue_block
;
71 LLVMBasicBlockRef break_block
;
73 LLVMValueRef outputs
[RADEON_LLVM_MAX_OUTPUTS
* 4];
78 struct nir_to_llvm_context
*nctx
; /* TODO get rid of this */
81 struct nir_to_llvm_context
{
82 struct ac_llvm_context ac
;
83 const struct ac_nir_compiler_options
*options
;
84 struct ac_shader_variant_info
*shader_info
;
85 struct ac_shader_abi abi
;
86 struct ac_nir_context
*nir
;
88 unsigned max_workgroup_size
;
89 LLVMContextRef context
;
91 LLVMBuilderRef builder
;
92 LLVMValueRef main_function
;
94 struct hash_table
*defs
;
95 struct hash_table
*phis
;
97 LLVMValueRef descriptor_sets
[AC_UD_MAX_SETS
];
98 LLVMValueRef ring_offsets
;
99 LLVMValueRef push_constants
;
100 LLVMValueRef num_work_groups
;
101 LLVMValueRef workgroup_ids
;
102 LLVMValueRef local_invocation_ids
;
103 LLVMValueRef tg_size
;
105 LLVMValueRef vertex_buffers
;
106 LLVMValueRef rel_auto_id
;
107 LLVMValueRef vs_prim_id
;
108 LLVMValueRef ls_out_layout
;
109 LLVMValueRef es2gs_offset
;
111 LLVMValueRef tcs_offchip_layout
;
112 LLVMValueRef tcs_out_offsets
;
113 LLVMValueRef tcs_out_layout
;
114 LLVMValueRef tcs_in_layout
;
116 LLVMValueRef tess_factor_offset
;
117 LLVMValueRef tcs_patch_id
;
118 LLVMValueRef tcs_rel_ids
;
119 LLVMValueRef tes_rel_patch_id
;
120 LLVMValueRef tes_patch_id
;
124 LLVMValueRef gsvs_ring_stride
;
125 LLVMValueRef gsvs_num_entries
;
126 LLVMValueRef gs2vs_offset
;
127 LLVMValueRef gs_wave_id
;
128 LLVMValueRef gs_vtx_offset
[6];
129 LLVMValueRef gs_prim_id
, gs_invocation_id
;
131 LLVMValueRef esgs_ring
;
132 LLVMValueRef gsvs_ring
;
133 LLVMValueRef hs_ring_tess_offchip
;
134 LLVMValueRef hs_ring_tess_factor
;
136 LLVMValueRef prim_mask
;
137 LLVMValueRef sample_pos_offset
;
138 LLVMValueRef persp_sample
, persp_center
, persp_centroid
;
139 LLVMValueRef linear_sample
, linear_center
, linear_centroid
;
140 LLVMValueRef front_face
;
141 LLVMValueRef ancillary
;
142 LLVMValueRef sample_coverage
;
143 LLVMValueRef frag_pos
[4];
162 LLVMValueRef i1false
;
163 LLVMValueRef i32zero
;
165 LLVMValueRef f32zero
;
167 LLVMValueRef v4f32empty
;
169 unsigned uniform_md_kind
;
170 LLVMValueRef empty_md
;
171 gl_shader_stage stage
;
174 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
177 uint64_t output_mask
;
178 uint8_t num_output_clips
;
179 uint8_t num_output_culls
;
181 bool has_ds_bpermute
;
183 bool is_gs_copy_shader
;
184 LLVMValueRef gs_next_vertex
;
185 unsigned gs_max_out_vertices
;
187 unsigned tes_primitive_mode
;
188 uint64_t tess_outputs_written
;
189 uint64_t tess_patch_outputs_written
;
192 static inline struct nir_to_llvm_context
*
193 nir_to_llvm_context_from_abi(struct ac_shader_abi
*abi
)
195 struct nir_to_llvm_context
*ctx
= NULL
;
196 return container_of(abi
, ctx
, abi
);
199 static LLVMValueRef
get_sampler_desc(struct nir_to_llvm_context
*ctx
,
200 const nir_deref_var
*deref
,
201 enum desc_type desc_type
);
202 static unsigned radeon_llvm_reg_index_soa(unsigned index
, unsigned chan
)
204 return (index
* 4) + chan
;
207 static unsigned shader_io_get_unique_index(gl_varying_slot slot
)
209 /* handle patch indices separate */
210 if (slot
== VARYING_SLOT_TESS_LEVEL_OUTER
)
212 if (slot
== VARYING_SLOT_TESS_LEVEL_INNER
)
214 if (slot
>= VARYING_SLOT_PATCH0
&& slot
<= VARYING_SLOT_TESS_MAX
)
215 return 2 + (slot
- VARYING_SLOT_PATCH0
);
217 if (slot
== VARYING_SLOT_POS
)
219 if (slot
== VARYING_SLOT_PSIZ
)
221 if (slot
== VARYING_SLOT_CLIP_DIST0
)
223 /* 3 is reserved for clip dist as well */
224 if (slot
>= VARYING_SLOT_VAR0
&& slot
<= VARYING_SLOT_VAR31
)
225 return 4 + (slot
- VARYING_SLOT_VAR0
);
226 unreachable("illegal slot in get unique index\n");
229 static unsigned llvm_get_type_size(LLVMTypeRef type
)
231 LLVMTypeKind kind
= LLVMGetTypeKind(type
);
234 case LLVMIntegerTypeKind
:
235 return LLVMGetIntTypeWidth(type
) / 8;
236 case LLVMFloatTypeKind
:
238 case LLVMPointerTypeKind
:
240 case LLVMVectorTypeKind
:
241 return LLVMGetVectorSize(type
) *
242 llvm_get_type_size(LLVMGetElementType(type
));
249 static void set_llvm_calling_convention(LLVMValueRef func
,
250 gl_shader_stage stage
)
252 enum radeon_llvm_calling_convention calling_conv
;
255 case MESA_SHADER_VERTEX
:
256 case MESA_SHADER_TESS_CTRL
:
257 case MESA_SHADER_TESS_EVAL
:
258 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
260 case MESA_SHADER_GEOMETRY
:
261 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
263 case MESA_SHADER_FRAGMENT
:
264 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
266 case MESA_SHADER_COMPUTE
:
267 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
270 unreachable("Unhandle shader type");
273 LLVMSetFunctionCallConv(func
, calling_conv
);
278 LLVMTypeRef types
[MAX_ARGS
];
279 LLVMValueRef
*assign
[MAX_ARGS
];
280 unsigned array_params_mask
;
282 uint8_t user_sgpr_count
;
284 uint8_t num_user_sgprs_used
;
285 uint8_t num_sgprs_used
;
286 uint8_t num_vgprs_used
;
290 add_argument(struct arg_info
*info
,
291 LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
293 assert(info
->count
< MAX_ARGS
);
294 info
->assign
[info
->count
] = param_ptr
;
295 info
->types
[info
->count
] = type
;
300 add_sgpr_argument(struct arg_info
*info
,
301 LLVMTypeRef type
, LLVMValueRef
*param_ptr
)
303 add_argument(info
, type
, param_ptr
);
304 info
->num_sgprs_used
+= llvm_get_type_size(type
) / 4;
309 add_user_sgpr_argument(struct arg_info
*info
,
311 LLVMValueRef
*param_ptr
)
313 add_sgpr_argument(info
, type
, param_ptr
);
314 info
->num_user_sgprs_used
+= llvm_get_type_size(type
) / 4;
315 info
->user_sgpr_count
++;
319 add_vgpr_argument(struct arg_info
*info
,
321 LLVMValueRef
*param_ptr
)
323 add_argument(info
, type
, param_ptr
);
324 info
->num_vgprs_used
+= llvm_get_type_size(type
) / 4;
328 add_user_sgpr_array_argument(struct arg_info
*info
,
330 LLVMValueRef
*param_ptr
)
332 info
->array_params_mask
|= (1 << info
->count
);
333 add_user_sgpr_argument(info
, type
, param_ptr
);
336 static void assign_arguments(LLVMValueRef main_function
,
337 struct arg_info
*info
)
340 for (i
= 0; i
< info
->count
; i
++) {
342 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
347 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
348 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
349 unsigned num_return_elems
,
350 struct arg_info
*args
,
351 unsigned max_workgroup_size
,
354 LLVMTypeRef main_function_type
, ret_type
;
355 LLVMBasicBlockRef main_function_body
;
357 if (num_return_elems
)
358 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
359 num_return_elems
, true);
361 ret_type
= LLVMVoidTypeInContext(ctx
);
363 /* Setup the function */
365 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
366 LLVMValueRef main_function
=
367 LLVMAddFunction(module
, "main", main_function_type
);
369 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
370 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
372 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
373 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
374 if (args
->array_params_mask
& (1 << i
)) {
375 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
376 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_BYVAL
);
377 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
380 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
384 if (max_workgroup_size
) {
385 ac_llvm_add_target_dep_function_attr(main_function
,
386 "amdgpu-max-work-group-size",
390 /* These were copied from some LLVM test. */
391 LLVMAddTargetDependentFunctionAttr(main_function
,
392 "less-precise-fpmad",
394 LLVMAddTargetDependentFunctionAttr(main_function
,
397 LLVMAddTargetDependentFunctionAttr(main_function
,
400 LLVMAddTargetDependentFunctionAttr(main_function
,
404 return main_function
;
407 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
409 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
413 static LLVMTypeRef
to_integer_type_scalar(struct ac_llvm_context
*ctx
, LLVMTypeRef t
)
415 if (t
== ctx
->f16
|| t
== ctx
->i16
)
417 else if (t
== ctx
->f32
|| t
== ctx
->i32
)
419 else if (t
== ctx
->f64
|| t
== ctx
->i64
)
422 unreachable("Unhandled integer size");
425 static LLVMTypeRef
to_integer_type(struct ac_llvm_context
*ctx
, LLVMTypeRef t
)
427 if (LLVMGetTypeKind(t
) == LLVMVectorTypeKind
) {
428 LLVMTypeRef elem_type
= LLVMGetElementType(t
);
429 return LLVMVectorType(to_integer_type_scalar(ctx
, elem_type
),
430 LLVMGetVectorSize(t
));
432 return to_integer_type_scalar(ctx
, t
);
435 static LLVMValueRef
to_integer(struct ac_llvm_context
*ctx
, LLVMValueRef v
)
437 LLVMTypeRef type
= LLVMTypeOf(v
);
438 return LLVMBuildBitCast(ctx
->builder
, v
, to_integer_type(ctx
, type
), "");
441 static LLVMTypeRef
to_float_type_scalar(struct ac_llvm_context
*ctx
, LLVMTypeRef t
)
443 if (t
== ctx
->i16
|| t
== ctx
->f16
)
445 else if (t
== ctx
->i32
|| t
== ctx
->f32
)
447 else if (t
== ctx
->i64
|| t
== ctx
->f64
)
450 unreachable("Unhandled float size");
453 static LLVMTypeRef
to_float_type(struct ac_llvm_context
*ctx
, LLVMTypeRef t
)
455 if (LLVMGetTypeKind(t
) == LLVMVectorTypeKind
) {
456 LLVMTypeRef elem_type
= LLVMGetElementType(t
);
457 return LLVMVectorType(to_float_type_scalar(ctx
, elem_type
),
458 LLVMGetVectorSize(t
));
460 return to_float_type_scalar(ctx
, t
);
463 static LLVMValueRef
to_float(struct ac_llvm_context
*ctx
, LLVMValueRef v
)
465 LLVMTypeRef type
= LLVMTypeOf(v
);
466 return LLVMBuildBitCast(ctx
->builder
, v
, to_float_type(ctx
, type
), "");
469 static int get_elem_bits(struct ac_llvm_context
*ctx
, LLVMTypeRef type
)
471 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
472 type
= LLVMGetElementType(type
);
474 if (LLVMGetTypeKind(type
) == LLVMIntegerTypeKind
)
475 return LLVMGetIntTypeWidth(type
);
477 if (type
== ctx
->f16
)
479 if (type
== ctx
->f32
)
481 if (type
== ctx
->f64
)
484 unreachable("Unhandled type kind in get_elem_bits");
487 static LLVMValueRef
unpack_param(struct nir_to_llvm_context
*ctx
,
488 LLVMValueRef param
, unsigned rshift
,
491 LLVMValueRef value
= param
;
493 value
= LLVMBuildLShr(ctx
->builder
, value
,
494 LLVMConstInt(ctx
->i32
, rshift
, false), "");
496 if (rshift
+ bitwidth
< 32) {
497 unsigned mask
= (1 << bitwidth
) - 1;
498 value
= LLVMBuildAnd(ctx
->builder
, value
,
499 LLVMConstInt(ctx
->i32
, mask
, false), "");
504 static LLVMValueRef
get_rel_patch_id(struct nir_to_llvm_context
*ctx
)
506 switch (ctx
->stage
) {
507 case MESA_SHADER_TESS_CTRL
:
508 return unpack_param(ctx
, ctx
->tcs_rel_ids
, 0, 8);
509 case MESA_SHADER_TESS_EVAL
:
510 return ctx
->tes_rel_patch_id
;
513 unreachable("Illegal stage");
517 /* Tessellation shaders pass outputs to the next shader using LDS.
519 * LS outputs = TCS inputs
520 * TCS outputs = TES inputs
523 * - TCS inputs for patch 0
524 * - TCS inputs for patch 1
525 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
527 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
528 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
529 * - TCS outputs for patch 1
530 * - Per-patch TCS outputs for patch 1
531 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
532 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
535 * All three shaders VS(LS), TCS, TES share the same LDS space.
538 get_tcs_in_patch_stride(struct nir_to_llvm_context
*ctx
)
540 if (ctx
->stage
== MESA_SHADER_VERTEX
)
541 return unpack_param(ctx
, ctx
->ls_out_layout
, 0, 13);
542 else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
543 return unpack_param(ctx
, ctx
->tcs_in_layout
, 0, 13);
551 get_tcs_out_patch_stride(struct nir_to_llvm_context
*ctx
)
553 return unpack_param(ctx
, ctx
->tcs_out_layout
, 0, 13);
557 get_tcs_out_patch0_offset(struct nir_to_llvm_context
*ctx
)
559 return LLVMBuildMul(ctx
->builder
,
560 unpack_param(ctx
, ctx
->tcs_out_offsets
, 0, 16),
561 LLVMConstInt(ctx
->i32
, 4, false), "");
565 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context
*ctx
)
567 return LLVMBuildMul(ctx
->builder
,
568 unpack_param(ctx
, ctx
->tcs_out_offsets
, 16, 16),
569 LLVMConstInt(ctx
->i32
, 4, false), "");
573 get_tcs_in_current_patch_offset(struct nir_to_llvm_context
*ctx
)
575 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
576 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
578 return LLVMBuildMul(ctx
->builder
, patch_stride
, rel_patch_id
, "");
582 get_tcs_out_current_patch_offset(struct nir_to_llvm_context
*ctx
)
584 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
585 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
586 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
588 return LLVMBuildAdd(ctx
->builder
, patch0_offset
,
589 LLVMBuildMul(ctx
->builder
, patch_stride
,
595 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context
*ctx
)
597 LLVMValueRef patch0_patch_data_offset
=
598 get_tcs_out_patch0_patch_data_offset(ctx
);
599 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
600 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
602 return LLVMBuildAdd(ctx
->builder
, patch0_patch_data_offset
,
603 LLVMBuildMul(ctx
->builder
, patch_stride
,
608 static void set_userdata_location(struct ac_userdata_info
*ud_info
, uint8_t *sgpr_idx
, uint8_t num_sgprs
)
610 ud_info
->sgpr_idx
= *sgpr_idx
;
611 ud_info
->num_sgprs
= num_sgprs
;
612 ud_info
->indirect
= false;
613 ud_info
->indirect_offset
= 0;
614 *sgpr_idx
+= num_sgprs
;
617 static void set_userdata_location_shader(struct nir_to_llvm_context
*ctx
,
618 int idx
, uint8_t *sgpr_idx
, uint8_t num_sgprs
)
620 set_userdata_location(&ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
], sgpr_idx
, num_sgprs
);
624 static void set_userdata_location_indirect(struct ac_userdata_info
*ud_info
, uint8_t sgpr_idx
, uint8_t num_sgprs
,
625 uint32_t indirect_offset
)
627 ud_info
->sgpr_idx
= sgpr_idx
;
628 ud_info
->num_sgprs
= num_sgprs
;
629 ud_info
->indirect
= true;
630 ud_info
->indirect_offset
= indirect_offset
;
633 static void declare_tess_lds(struct nir_to_llvm_context
*ctx
)
635 unsigned lds_size
= ctx
->options
->chip_class
>= CIK
? 65536 : 32768;
636 ctx
->lds
= LLVMBuildIntToPtr(ctx
->builder
, ctx
->i32zero
,
637 LLVMPointerType(LLVMArrayType(ctx
->i32
, lds_size
/ 4), LOCAL_ADDR_SPACE
),
641 struct user_sgpr_info
{
642 bool need_ring_offsets
;
644 bool indirect_all_descriptor_sets
;
647 static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx
,
648 struct user_sgpr_info
*user_sgpr_info
)
650 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
652 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
653 if (ctx
->stage
== MESA_SHADER_GEOMETRY
||
654 ctx
->stage
== MESA_SHADER_VERTEX
||
655 ctx
->stage
== MESA_SHADER_TESS_CTRL
||
656 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
657 ctx
->is_gs_copy_shader
)
658 user_sgpr_info
->need_ring_offsets
= true;
660 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&&
661 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
662 user_sgpr_info
->need_ring_offsets
= true;
664 /* 2 user sgprs will nearly always be allocated for scratch/rings */
665 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
666 user_sgpr_info
->sgpr_count
+= 2;
669 switch (ctx
->stage
) {
670 case MESA_SHADER_COMPUTE
:
671 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.cs
.grid_components_used
;
673 case MESA_SHADER_FRAGMENT
:
674 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
676 case MESA_SHADER_VERTEX
:
677 if (!ctx
->is_gs_copy_shader
) {
678 user_sgpr_info
->sgpr_count
+= ctx
->shader_info
->info
.vs
.has_vertex_buffers
? 2 : 0;
679 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
680 user_sgpr_info
->sgpr_count
+= 3;
682 user_sgpr_info
->sgpr_count
+= 2;
685 if (ctx
->options
->key
.vs
.as_ls
)
686 user_sgpr_info
->sgpr_count
++;
688 case MESA_SHADER_TESS_CTRL
:
689 user_sgpr_info
->sgpr_count
+= 4;
691 case MESA_SHADER_TESS_EVAL
:
692 user_sgpr_info
->sgpr_count
+= 1;
694 case MESA_SHADER_GEOMETRY
:
695 user_sgpr_info
->sgpr_count
+= 2;
701 if (ctx
->shader_info
->info
.needs_push_constants
)
702 user_sgpr_info
->sgpr_count
+= 2;
704 uint32_t remaining_sgprs
= 16 - user_sgpr_info
->sgpr_count
;
705 if (remaining_sgprs
/ 2 < util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
)) {
706 user_sgpr_info
->sgpr_count
+= 2;
707 user_sgpr_info
->indirect_all_descriptor_sets
= true;
709 user_sgpr_info
->sgpr_count
+= util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
) * 2;
713 static void create_function(struct nir_to_llvm_context
*ctx
)
715 unsigned num_sets
= ctx
->options
->layout
? ctx
->options
->layout
->num_sets
: 0;
716 uint8_t user_sgpr_idx
;
717 struct user_sgpr_info user_sgpr_info
;
718 struct arg_info args
= {};
719 LLVMValueRef desc_sets
;
721 allocate_user_sgprs(ctx
, &user_sgpr_info
);
722 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
723 add_user_sgpr_argument(&args
, const_array(ctx
->v4i32
, 16), &ctx
->ring_offsets
); /* address of rings */
726 /* 1 for each descriptor set */
727 if (!user_sgpr_info
.indirect_all_descriptor_sets
) {
728 for (unsigned i
= 0; i
< num_sets
; ++i
) {
729 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& (1 << ctx
->stage
)) {
730 add_user_sgpr_array_argument(&args
, const_array(ctx
->i8
, 1024 * 1024), &ctx
->descriptor_sets
[i
]);
734 add_user_sgpr_array_argument(&args
, const_array(const_array(ctx
->i8
, 1024 * 1024), 32), &desc_sets
);
736 if (ctx
->shader_info
->info
.needs_push_constants
) {
737 /* 1 for push constants and dynamic descriptors */
738 add_user_sgpr_array_argument(&args
, const_array(ctx
->i8
, 1024 * 1024), &ctx
->push_constants
);
741 switch (ctx
->stage
) {
742 case MESA_SHADER_COMPUTE
:
743 if (ctx
->shader_info
->info
.cs
.grid_components_used
)
744 add_user_sgpr_argument(&args
, LLVMVectorType(ctx
->i32
, ctx
->shader_info
->info
.cs
.grid_components_used
), &ctx
->num_work_groups
); /* grid size */
745 add_sgpr_argument(&args
, LLVMVectorType(ctx
->i32
, 3), &ctx
->workgroup_ids
);
746 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->tg_size
);
747 add_vgpr_argument(&args
, LLVMVectorType(ctx
->i32
, 3), &ctx
->local_invocation_ids
);
749 case MESA_SHADER_VERTEX
:
750 if (!ctx
->is_gs_copy_shader
) {
751 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
752 add_user_sgpr_argument(&args
, const_array(ctx
->v4i32
, 16), &ctx
->vertex_buffers
); /* vertex buffers */
753 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.base_vertex
); // base vertex
754 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.start_instance
);// start instance
755 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
756 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.draw_id
); // draw id
758 if (ctx
->options
->key
.vs
.as_es
)
759 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->es2gs_offset
); // es2gs offset
760 else if (ctx
->options
->key
.vs
.as_ls
)
761 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->ls_out_layout
); // ls out layout
762 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.vertex_id
); // vertex id
763 if (!ctx
->is_gs_copy_shader
) {
764 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->rel_auto_id
); // rel auto id
765 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->vs_prim_id
); // vs prim id
766 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->abi
.instance_id
); // instance id
769 case MESA_SHADER_TESS_CTRL
:
770 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
771 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_out_offsets
); // tcs out offsets
772 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_out_layout
); // tcs out layout
773 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_in_layout
); // tcs in layout
774 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->oc_lds
); // param oc lds
775 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->tess_factor_offset
); // tess factor offset
776 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_patch_id
); // patch id
777 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_rel_ids
); // rel ids;
779 case MESA_SHADER_TESS_EVAL
:
780 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->tcs_offchip_layout
); // tcs offchip layout
781 if (ctx
->options
->key
.tes
.as_es
) {
782 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->oc_lds
); // OC LDS
783 add_sgpr_argument(&args
, ctx
->i32
, NULL
); //
784 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->es2gs_offset
); // es2gs offset
786 add_sgpr_argument(&args
, ctx
->i32
, NULL
); //
787 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->oc_lds
); // OC LDS
789 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->tes_u
); // tes_u
790 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->tes_v
); // tes_v
791 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->tes_rel_patch_id
); // tes rel patch id
792 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->tes_patch_id
); // tes patch id
794 case MESA_SHADER_GEOMETRY
:
795 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->gsvs_ring_stride
); // gsvs stride
796 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->gsvs_num_entries
); // gsvs num entires
797 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->gs2vs_offset
); // gs2vs offset
798 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->gs_wave_id
); // wave id
799 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[0]); // vtx0
800 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[1]); // vtx1
801 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_prim_id
); // prim id
802 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[2]);
803 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[3]);
804 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[4]);
805 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_vtx_offset
[5]);
806 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->gs_invocation_id
);
808 case MESA_SHADER_FRAGMENT
:
809 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
)
810 add_user_sgpr_argument(&args
, ctx
->i32
, &ctx
->sample_pos_offset
); /* sample position offset */
811 add_sgpr_argument(&args
, ctx
->i32
, &ctx
->prim_mask
); /* prim mask */
812 add_vgpr_argument(&args
, ctx
->v2i32
, &ctx
->persp_sample
); /* persp sample */
813 add_vgpr_argument(&args
, ctx
->v2i32
, &ctx
->persp_center
); /* persp center */
814 add_vgpr_argument(&args
, ctx
->v2i32
, &ctx
->persp_centroid
); /* persp centroid */
815 add_vgpr_argument(&args
, ctx
->v3i32
, NULL
); /* persp pull model */
816 add_vgpr_argument(&args
, ctx
->v2i32
, &ctx
->linear_sample
); /* linear sample */
817 add_vgpr_argument(&args
, ctx
->v2i32
, &ctx
->linear_center
); /* linear center */
818 add_vgpr_argument(&args
, ctx
->v2i32
, &ctx
->linear_centroid
); /* linear centroid */
819 add_vgpr_argument(&args
, ctx
->f32
, NULL
); /* line stipple tex */
820 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->frag_pos
[0]); /* pos x float */
821 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->frag_pos
[1]); /* pos y float */
822 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->frag_pos
[2]); /* pos z float */
823 add_vgpr_argument(&args
, ctx
->f32
, &ctx
->frag_pos
[3]); /* pos w float */
824 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->front_face
); /* front face */
825 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->ancillary
); /* ancillary */
826 add_vgpr_argument(&args
, ctx
->i32
, &ctx
->sample_coverage
); /* sample coverage */
827 add_vgpr_argument(&args
, ctx
->i32
, NULL
); /* fixed pt */
830 unreachable("Shader stage not implemented");
833 ctx
->main_function
= create_llvm_function(
834 ctx
->context
, ctx
->module
, ctx
->builder
, NULL
, 0, &args
,
835 ctx
->max_workgroup_size
,
836 ctx
->options
->unsafe_math
);
837 set_llvm_calling_convention(ctx
->main_function
, ctx
->stage
);
840 ctx
->shader_info
->num_input_vgprs
= 0;
841 ctx
->shader_info
->num_input_sgprs
= ctx
->shader_info
->num_user_sgprs
=
842 ctx
->options
->supports_spill
? 2 : 0;
844 ctx
->shader_info
->num_user_sgprs
+= args
.num_user_sgprs_used
;
845 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
847 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
848 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
850 assign_arguments(ctx
->main_function
, &args
);
854 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
855 set_userdata_location_shader(ctx
, AC_UD_SCRATCH_RING_OFFSETS
, &user_sgpr_idx
, 2);
856 if (ctx
->options
->supports_spill
) {
857 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
858 LLVMPointerType(ctx
->i8
, CONST_ADDR_SPACE
),
859 NULL
, 0, AC_FUNC_ATTR_READNONE
);
860 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->builder
, ctx
->ring_offsets
,
861 const_array(ctx
->v4i32
, 16), "");
865 if (!user_sgpr_info
.indirect_all_descriptor_sets
) {
866 for (unsigned i
= 0; i
< num_sets
; ++i
) {
867 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& (1 << ctx
->stage
)) {
868 set_userdata_location(&ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[i
], &user_sgpr_idx
, 2);
870 ctx
->descriptor_sets
[i
] = NULL
;
873 uint32_t desc_sgpr_idx
= user_sgpr_idx
;
874 set_userdata_location_shader(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
, &user_sgpr_idx
, 2);
876 for (unsigned i
= 0; i
< num_sets
; ++i
) {
877 if (ctx
->options
->layout
->set
[i
].layout
->shader_stages
& (1 << ctx
->stage
)) {
878 set_userdata_location_indirect(&ctx
->shader_info
->user_sgprs_locs
.descriptor_sets
[i
], desc_sgpr_idx
, 2, i
* 8);
879 ctx
->descriptor_sets
[i
] = ac_build_indexed_load_const(&ctx
->ac
, desc_sets
, LLVMConstInt(ctx
->i32
, i
, false));
882 ctx
->descriptor_sets
[i
] = NULL
;
884 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
887 if (ctx
->shader_info
->info
.needs_push_constants
) {
888 set_userdata_location_shader(ctx
, AC_UD_PUSH_CONSTANTS
, &user_sgpr_idx
, 2);
891 switch (ctx
->stage
) {
892 case MESA_SHADER_COMPUTE
:
893 if (ctx
->shader_info
->info
.cs
.grid_components_used
) {
894 set_userdata_location_shader(ctx
, AC_UD_CS_GRID_SIZE
, &user_sgpr_idx
, ctx
->shader_info
->info
.cs
.grid_components_used
);
897 case MESA_SHADER_VERTEX
:
898 if (!ctx
->is_gs_copy_shader
) {
899 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
900 set_userdata_location_shader(ctx
, AC_UD_VS_VERTEX_BUFFERS
, &user_sgpr_idx
, 2);
903 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
906 set_userdata_location_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
, &user_sgpr_idx
, vs_num
);
908 if (ctx
->options
->key
.vs
.as_ls
) {
909 set_userdata_location_shader(ctx
, AC_UD_VS_LS_TCS_IN_LAYOUT
, &user_sgpr_idx
, 1);
911 if (ctx
->options
->key
.vs
.as_ls
)
912 declare_tess_lds(ctx
);
914 case MESA_SHADER_TESS_CTRL
:
915 set_userdata_location_shader(ctx
, AC_UD_TCS_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 4);
916 declare_tess_lds(ctx
);
918 case MESA_SHADER_TESS_EVAL
:
919 set_userdata_location_shader(ctx
, AC_UD_TES_OFFCHIP_LAYOUT
, &user_sgpr_idx
, 1);
921 case MESA_SHADER_GEOMETRY
:
922 set_userdata_location_shader(ctx
, AC_UD_GS_VS_RING_STRIDE_ENTRIES
, &user_sgpr_idx
, 2);
924 case MESA_SHADER_FRAGMENT
:
925 if (ctx
->shader_info
->info
.ps
.needs_sample_positions
) {
926 set_userdata_location_shader(ctx
, AC_UD_PS_SAMPLE_POS_OFFSET
, &user_sgpr_idx
, 1);
930 unreachable("Shader stage not implemented");
934 static void setup_types(struct nir_to_llvm_context
*ctx
)
936 LLVMValueRef args
[4];
938 ctx
->voidt
= LLVMVoidTypeInContext(ctx
->context
);
939 ctx
->i1
= LLVMIntTypeInContext(ctx
->context
, 1);
940 ctx
->i8
= LLVMIntTypeInContext(ctx
->context
, 8);
941 ctx
->i16
= LLVMIntTypeInContext(ctx
->context
, 16);
942 ctx
->i32
= LLVMIntTypeInContext(ctx
->context
, 32);
943 ctx
->i64
= LLVMIntTypeInContext(ctx
->context
, 64);
944 ctx
->v2i32
= LLVMVectorType(ctx
->i32
, 2);
945 ctx
->v3i32
= LLVMVectorType(ctx
->i32
, 3);
946 ctx
->v4i32
= LLVMVectorType(ctx
->i32
, 4);
947 ctx
->v8i32
= LLVMVectorType(ctx
->i32
, 8);
948 ctx
->f32
= LLVMFloatTypeInContext(ctx
->context
);
949 ctx
->f16
= LLVMHalfTypeInContext(ctx
->context
);
950 ctx
->f64
= LLVMDoubleTypeInContext(ctx
->context
);
951 ctx
->v2f32
= LLVMVectorType(ctx
->f32
, 2);
952 ctx
->v4f32
= LLVMVectorType(ctx
->f32
, 4);
954 ctx
->i1false
= LLVMConstInt(ctx
->i1
, 0, false);
955 ctx
->i1true
= LLVMConstInt(ctx
->i1
, 1, false);
956 ctx
->i32zero
= LLVMConstInt(ctx
->i32
, 0, false);
957 ctx
->i32one
= LLVMConstInt(ctx
->i32
, 1, false);
958 ctx
->f32zero
= LLVMConstReal(ctx
->f32
, 0.0);
959 ctx
->f32one
= LLVMConstReal(ctx
->f32
, 1.0);
961 args
[0] = ctx
->f32zero
;
962 args
[1] = ctx
->f32zero
;
963 args
[2] = ctx
->f32zero
;
964 args
[3] = ctx
->f32one
;
965 ctx
->v4f32empty
= LLVMConstVector(args
, 4);
967 ctx
->uniform_md_kind
=
968 LLVMGetMDKindIDInContext(ctx
->context
, "amdgpu.uniform", 14);
969 ctx
->empty_md
= LLVMMDNodeInContext(ctx
->context
, NULL
, 0);
971 args
[0] = LLVMConstReal(ctx
->f32
, 2.5);
974 static int get_llvm_num_components(LLVMValueRef value
)
976 LLVMTypeRef type
= LLVMTypeOf(value
);
977 unsigned num_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
978 ? LLVMGetVectorSize(type
)
980 return num_components
;
983 static LLVMValueRef
llvm_extract_elem(struct nir_to_llvm_context
*ctx
,
987 int count
= get_llvm_num_components(value
);
989 assert(index
< count
);
993 return LLVMBuildExtractElement(ctx
->builder
, value
,
994 LLVMConstInt(ctx
->i32
, index
, false), "");
997 static LLVMValueRef
trim_vector(struct nir_to_llvm_context
*ctx
,
998 LLVMValueRef value
, unsigned count
)
1000 unsigned num_components
= get_llvm_num_components(value
);
1001 if (count
== num_components
)
1004 LLVMValueRef masks
[] = {
1005 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
1006 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false)};
1009 return LLVMBuildExtractElement(ctx
->builder
, value
, masks
[0],
1012 LLVMValueRef swizzle
= LLVMConstVector(masks
, count
);
1013 return LLVMBuildShuffleVector(ctx
->builder
, value
, value
, swizzle
, "");
1017 build_store_values_extended(struct nir_to_llvm_context
*ctx
,
1018 LLVMValueRef
*values
,
1019 unsigned value_count
,
1020 unsigned value_stride
,
1023 LLVMBuilderRef builder
= ctx
->builder
;
1026 if (value_count
== 1) {
1027 LLVMBuildStore(builder
, vec
, values
[0]);
1031 for (i
= 0; i
< value_count
; i
++) {
1032 LLVMValueRef ptr
= values
[i
* value_stride
];
1033 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, i
, false);
1034 LLVMValueRef value
= LLVMBuildExtractElement(builder
, vec
, index
, "");
1035 LLVMBuildStore(builder
, value
, ptr
);
1039 static LLVMTypeRef
get_def_type(struct ac_nir_context
*ctx
,
1040 const nir_ssa_def
*def
)
1042 LLVMTypeRef type
= LLVMIntTypeInContext(ctx
->ac
.context
, def
->bit_size
);
1043 if (def
->num_components
> 1) {
1044 type
= LLVMVectorType(type
, def
->num_components
);
1049 static LLVMValueRef
get_src(struct ac_nir_context
*nir
, nir_src src
)
1052 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, src
.ssa
);
1053 return (LLVMValueRef
)entry
->data
;
1057 static LLVMBasicBlockRef
get_block(struct ac_nir_context
*nir
,
1058 const struct nir_block
*b
)
1060 struct hash_entry
*entry
= _mesa_hash_table_search(nir
->defs
, b
);
1061 return (LLVMBasicBlockRef
)entry
->data
;
1064 static LLVMValueRef
get_alu_src(struct ac_nir_context
*ctx
,
1066 unsigned num_components
)
1068 LLVMValueRef value
= get_src(ctx
, src
.src
);
1069 bool need_swizzle
= false;
1072 LLVMTypeRef type
= LLVMTypeOf(value
);
1073 unsigned src_components
= LLVMGetTypeKind(type
) == LLVMVectorTypeKind
1074 ? LLVMGetVectorSize(type
)
1077 for (unsigned i
= 0; i
< num_components
; ++i
) {
1078 assert(src
.swizzle
[i
] < src_components
);
1079 if (src
.swizzle
[i
] != i
)
1080 need_swizzle
= true;
1083 if (need_swizzle
|| num_components
!= src_components
) {
1084 LLVMValueRef masks
[] = {
1085 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[0], false),
1086 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[1], false),
1087 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[2], false),
1088 LLVMConstInt(ctx
->ac
.i32
, src
.swizzle
[3], false)};
1090 if (src_components
> 1 && num_components
== 1) {
1091 value
= LLVMBuildExtractElement(ctx
->ac
.builder
, value
,
1093 } else if (src_components
== 1 && num_components
> 1) {
1094 LLVMValueRef values
[] = {value
, value
, value
, value
};
1095 value
= ac_build_gather_values(&ctx
->ac
, values
, num_components
);
1097 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
1098 value
= LLVMBuildShuffleVector(ctx
->ac
.builder
, value
, value
,
1102 assert(!src
.negate
);
1107 static LLVMValueRef
emit_int_cmp(struct ac_llvm_context
*ctx
,
1108 LLVMIntPredicate pred
, LLVMValueRef src0
,
1111 LLVMValueRef result
= LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, "");
1112 return LLVMBuildSelect(ctx
->builder
, result
,
1113 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1114 LLVMConstInt(ctx
->i32
, 0, false), "");
1117 static LLVMValueRef
emit_float_cmp(struct ac_llvm_context
*ctx
,
1118 LLVMRealPredicate pred
, LLVMValueRef src0
,
1121 LLVMValueRef result
;
1122 src0
= to_float(ctx
, src0
);
1123 src1
= to_float(ctx
, src1
);
1124 result
= LLVMBuildFCmp(ctx
->builder
, pred
, src0
, src1
, "");
1125 return LLVMBuildSelect(ctx
->builder
, result
,
1126 LLVMConstInt(ctx
->i32
, 0xFFFFFFFF, false),
1127 LLVMConstInt(ctx
->i32
, 0, false), "");
1130 static LLVMValueRef
emit_intrin_1f_param(struct ac_llvm_context
*ctx
,
1132 LLVMTypeRef result_type
,
1136 LLVMValueRef params
[] = {
1137 to_float(ctx
, src0
),
1140 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1141 get_elem_bits(ctx
, result_type
));
1142 assert(length
< sizeof(name
));
1143 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 1, AC_FUNC_ATTR_READNONE
);
1146 static LLVMValueRef
emit_intrin_2f_param(struct ac_llvm_context
*ctx
,
1148 LLVMTypeRef result_type
,
1149 LLVMValueRef src0
, LLVMValueRef src1
)
1152 LLVMValueRef params
[] = {
1153 to_float(ctx
, src0
),
1154 to_float(ctx
, src1
),
1157 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1158 get_elem_bits(ctx
, result_type
));
1159 assert(length
< sizeof(name
));
1160 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 2, AC_FUNC_ATTR_READNONE
);
1163 static LLVMValueRef
emit_intrin_3f_param(struct ac_llvm_context
*ctx
,
1165 LLVMTypeRef result_type
,
1166 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1169 LLVMValueRef params
[] = {
1170 to_float(ctx
, src0
),
1171 to_float(ctx
, src1
),
1172 to_float(ctx
, src2
),
1175 MAYBE_UNUSED
const int length
= snprintf(name
, sizeof(name
), "%s.f%d", intrin
,
1176 get_elem_bits(ctx
, result_type
));
1177 assert(length
< sizeof(name
));
1178 return ac_build_intrinsic(ctx
, name
, result_type
, params
, 3, AC_FUNC_ATTR_READNONE
);
1181 static LLVMValueRef
emit_bcsel(struct ac_llvm_context
*ctx
,
1182 LLVMValueRef src0
, LLVMValueRef src1
, LLVMValueRef src2
)
1184 LLVMValueRef v
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
,
1186 return LLVMBuildSelect(ctx
->builder
, v
, src1
, src2
, "");
1189 static LLVMValueRef
emit_find_lsb(struct ac_llvm_context
*ctx
,
1192 LLVMValueRef params
[2] = {
1195 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1196 * add special code to check for x=0. The reason is that
1197 * the LLVM behavior for x=0 is different from what we
1200 * The hardware already implements the correct behavior.
1202 LLVMConstInt(ctx
->i1
, 1, false),
1204 return ac_build_intrinsic(ctx
, "llvm.cttz.i32", ctx
->i32
, params
, 2, AC_FUNC_ATTR_READNONE
);
1207 static LLVMValueRef
emit_ifind_msb(struct ac_llvm_context
*ctx
,
1210 return ac_build_imsb(ctx
, src0
, ctx
->i32
);
1213 static LLVMValueRef
emit_ufind_msb(struct ac_llvm_context
*ctx
,
1216 return ac_build_umsb(ctx
, src0
, ctx
->i32
);
1219 static LLVMValueRef
emit_minmax_int(struct ac_llvm_context
*ctx
,
1220 LLVMIntPredicate pred
,
1221 LLVMValueRef src0
, LLVMValueRef src1
)
1223 return LLVMBuildSelect(ctx
->builder
,
1224 LLVMBuildICmp(ctx
->builder
, pred
, src0
, src1
, ""),
1229 static LLVMValueRef
emit_iabs(struct ac_llvm_context
*ctx
,
1232 return emit_minmax_int(ctx
, LLVMIntSGT
, src0
,
1233 LLVMBuildNeg(ctx
->builder
, src0
, ""));
1236 static LLVMValueRef
emit_fsign(struct ac_llvm_context
*ctx
,
1239 LLVMValueRef cmp
, val
;
1241 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGT
, src0
, ctx
->f32_0
, "");
1242 val
= LLVMBuildSelect(ctx
->builder
, cmp
, ctx
->f32_1
, src0
, "");
1243 cmp
= LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
, val
, ctx
->f32_0
, "");
1244 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstReal(ctx
->f32
, -1.0), "");
1248 static LLVMValueRef
emit_isign(struct ac_llvm_context
*ctx
,
1251 LLVMValueRef cmp
, val
;
1253 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGT
, src0
, ctx
->i32_0
, "");
1254 val
= LLVMBuildSelect(ctx
->builder
, cmp
, ctx
->i32_1
, src0
, "");
1255 cmp
= LLVMBuildICmp(ctx
->builder
, LLVMIntSGE
, val
, ctx
->i32_0
, "");
1256 val
= LLVMBuildSelect(ctx
->builder
, cmp
, val
, LLVMConstInt(ctx
->i32
, -1, true), "");
1260 static LLVMValueRef
emit_ffract(struct ac_llvm_context
*ctx
,
1263 const char *intr
= "llvm.floor.f32";
1264 LLVMValueRef fsrc0
= to_float(ctx
, src0
);
1265 LLVMValueRef params
[] = {
1268 LLVMValueRef floor
= ac_build_intrinsic(ctx
, intr
,
1269 ctx
->f32
, params
, 1,
1270 AC_FUNC_ATTR_READNONE
);
1271 return LLVMBuildFSub(ctx
->builder
, fsrc0
, floor
, "");
1274 static LLVMValueRef
emit_uint_carry(struct ac_llvm_context
*ctx
,
1276 LLVMValueRef src0
, LLVMValueRef src1
)
1278 LLVMTypeRef ret_type
;
1279 LLVMTypeRef types
[] = { ctx
->i32
, ctx
->i1
};
1281 LLVMValueRef params
[] = { src0
, src1
};
1282 ret_type
= LLVMStructTypeInContext(ctx
->context
, types
,
1285 res
= ac_build_intrinsic(ctx
, intrin
, ret_type
,
1286 params
, 2, AC_FUNC_ATTR_READNONE
);
1288 res
= LLVMBuildExtractValue(ctx
->builder
, res
, 1, "");
1289 res
= LLVMBuildZExt(ctx
->builder
, res
, ctx
->i32
, "");
1293 static LLVMValueRef
emit_b2f(struct ac_llvm_context
*ctx
,
1296 return LLVMBuildAnd(ctx
->builder
, src0
, LLVMBuildBitCast(ctx
->builder
, LLVMConstReal(ctx
->f32
, 1.0), ctx
->i32
, ""), "");
1299 static LLVMValueRef
emit_f2b(struct ac_llvm_context
*ctx
,
1302 src0
= to_float(ctx
, src0
);
1303 return LLVMBuildSExt(ctx
->builder
,
1304 LLVMBuildFCmp(ctx
->builder
, LLVMRealUNE
, src0
, ctx
->f32_0
, ""),
1308 static LLVMValueRef
emit_b2i(struct ac_llvm_context
*ctx
,
1311 return LLVMBuildAnd(ctx
->builder
, src0
, ctx
->i32_1
, "");
1314 static LLVMValueRef
emit_i2b(struct ac_llvm_context
*ctx
,
1317 return LLVMBuildSExt(ctx
->builder
,
1318 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
, src0
, ctx
->i32_0
, ""),
1322 static LLVMValueRef
emit_f2f16(struct nir_to_llvm_context
*ctx
,
1325 LLVMValueRef result
;
1328 src0
= to_float(&ctx
->ac
, src0
);
1329 result
= LLVMBuildFPTrunc(ctx
->builder
, src0
, ctx
->f16
, "");
1331 /* TODO SI/CIK options here */
1332 if (ctx
->options
->chip_class
>= VI
) {
1333 LLVMValueRef args
[2];
1334 /* Check if the result is a denormal - and flush to 0 if so. */
1336 args
[1] = LLVMConstInt(ctx
->i32
, N_SUBNORMAL
| P_SUBNORMAL
, false);
1337 cond
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.class.f16", ctx
->i1
, args
, 2, AC_FUNC_ATTR_READNONE
);
1340 /* need to convert back up to f32 */
1341 result
= LLVMBuildFPExt(ctx
->builder
, result
, ctx
->f32
, "");
1343 if (ctx
->options
->chip_class
>= VI
)
1344 result
= LLVMBuildSelect(ctx
->builder
, cond
, ctx
->f32zero
, result
, "");
1349 static LLVMValueRef
emit_umul_high(struct ac_llvm_context
*ctx
,
1350 LLVMValueRef src0
, LLVMValueRef src1
)
1352 LLVMValueRef dst64
, result
;
1353 src0
= LLVMBuildZExt(ctx
->builder
, src0
, ctx
->i64
, "");
1354 src1
= LLVMBuildZExt(ctx
->builder
, src1
, ctx
->i64
, "");
1356 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1357 dst64
= LLVMBuildLShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1358 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1362 static LLVMValueRef
emit_imul_high(struct ac_llvm_context
*ctx
,
1363 LLVMValueRef src0
, LLVMValueRef src1
)
1365 LLVMValueRef dst64
, result
;
1366 src0
= LLVMBuildSExt(ctx
->builder
, src0
, ctx
->i64
, "");
1367 src1
= LLVMBuildSExt(ctx
->builder
, src1
, ctx
->i64
, "");
1369 dst64
= LLVMBuildMul(ctx
->builder
, src0
, src1
, "");
1370 dst64
= LLVMBuildAShr(ctx
->builder
, dst64
, LLVMConstInt(ctx
->i64
, 32, false), "");
1371 result
= LLVMBuildTrunc(ctx
->builder
, dst64
, ctx
->i32
, "");
1375 static LLVMValueRef
emit_bitfield_extract(struct ac_llvm_context
*ctx
,
1377 const LLVMValueRef srcs
[3])
1379 LLVMValueRef result
;
1380 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, srcs
[2], LLVMConstInt(ctx
->i32
, 32, false), "");
1382 result
= ac_build_bfe(ctx
, srcs
[0], srcs
[1], srcs
[2], is_signed
);
1383 result
= LLVMBuildSelect(ctx
->builder
, icond
, srcs
[0], result
, "");
1387 static LLVMValueRef
emit_bitfield_insert(struct ac_llvm_context
*ctx
,
1388 LLVMValueRef src0
, LLVMValueRef src1
,
1389 LLVMValueRef src2
, LLVMValueRef src3
)
1391 LLVMValueRef bfi_args
[3], result
;
1393 bfi_args
[0] = LLVMBuildShl(ctx
->builder
,
1394 LLVMBuildSub(ctx
->builder
,
1395 LLVMBuildShl(ctx
->builder
,
1400 bfi_args
[1] = LLVMBuildShl(ctx
->builder
, src1
, src2
, "");
1403 LLVMValueRef icond
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, src3
, LLVMConstInt(ctx
->i32
, 32, false), "");
1406 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1407 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1409 result
= LLVMBuildXor(ctx
->builder
, bfi_args
[2],
1410 LLVMBuildAnd(ctx
->builder
, bfi_args
[0],
1411 LLVMBuildXor(ctx
->builder
, bfi_args
[1], bfi_args
[2], ""), ""), "");
1413 result
= LLVMBuildSelect(ctx
->builder
, icond
, src1
, result
, "");
1417 static LLVMValueRef
emit_pack_half_2x16(struct ac_llvm_context
*ctx
,
1420 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1422 LLVMValueRef comp
[2];
1424 src0
= to_float(ctx
, src0
);
1425 comp
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_0
, "");
1426 comp
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32_1
, "");
1427 for (i
= 0; i
< 2; i
++) {
1428 comp
[i
] = LLVMBuildFPTrunc(ctx
->builder
, comp
[i
], ctx
->f16
, "");
1429 comp
[i
] = LLVMBuildBitCast(ctx
->builder
, comp
[i
], ctx
->i16
, "");
1430 comp
[i
] = LLVMBuildZExt(ctx
->builder
, comp
[i
], ctx
->i32
, "");
1433 comp
[1] = LLVMBuildShl(ctx
->builder
, comp
[1], const16
, "");
1434 comp
[0] = LLVMBuildOr(ctx
->builder
, comp
[0], comp
[1], "");
1439 static LLVMValueRef
emit_unpack_half_2x16(struct ac_llvm_context
*ctx
,
1442 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
1443 LLVMValueRef temps
[2], result
, val
;
1446 for (i
= 0; i
< 2; i
++) {
1447 val
= i
== 1 ? LLVMBuildLShr(ctx
->builder
, src0
, const16
, "") : src0
;
1448 val
= LLVMBuildTrunc(ctx
->builder
, val
, ctx
->i16
, "");
1449 val
= LLVMBuildBitCast(ctx
->builder
, val
, ctx
->f16
, "");
1450 temps
[i
] = LLVMBuildFPExt(ctx
->builder
, val
, ctx
->f32
, "");
1453 LLVMTypeRef v2f32
= LLVMVectorType(ctx
->f32
, 2);
1454 result
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(v2f32
), temps
[0],
1456 result
= LLVMBuildInsertElement(ctx
->builder
, result
, temps
[1],
1461 static LLVMValueRef
emit_ddxy(struct nir_to_llvm_context
*ctx
,
1467 LLVMValueRef result
;
1469 if (!ctx
->lds
&& !ctx
->has_ds_bpermute
)
1470 ctx
->lds
= LLVMAddGlobalInAddressSpace(ctx
->module
,
1471 LLVMArrayType(ctx
->i32
, 64),
1472 "ddxy_lds", LOCAL_ADDR_SPACE
);
1474 if (op
== nir_op_fddx_fine
|| op
== nir_op_fddx
)
1475 mask
= AC_TID_MASK_LEFT
;
1476 else if (op
== nir_op_fddy_fine
|| op
== nir_op_fddy
)
1477 mask
= AC_TID_MASK_TOP
;
1479 mask
= AC_TID_MASK_TOP_LEFT
;
1481 /* for DDX we want to next X pixel, DDY next Y pixel. */
1482 if (op
== nir_op_fddx_fine
||
1483 op
== nir_op_fddx_coarse
||
1489 result
= ac_build_ddxy(&ctx
->ac
, ctx
->has_ds_bpermute
,
1490 mask
, idx
, ctx
->lds
,
1496 * this takes an I,J coordinate pair,
1497 * and works out the X and Y derivatives.
1498 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1500 static LLVMValueRef
emit_ddxy_interp(
1501 struct nir_to_llvm_context
*ctx
,
1502 LLVMValueRef interp_ij
)
1504 LLVMValueRef result
[4], a
;
1507 for (i
= 0; i
< 2; i
++) {
1508 a
= LLVMBuildExtractElement(ctx
->builder
, interp_ij
,
1509 LLVMConstInt(ctx
->i32
, i
, false), "");
1510 result
[i
] = emit_ddxy(ctx
, nir_op_fddx
, a
);
1511 result
[2+i
] = emit_ddxy(ctx
, nir_op_fddy
, a
);
1513 return ac_build_gather_values(&ctx
->ac
, result
, 4);
1516 static void visit_alu(struct ac_nir_context
*ctx
, const nir_alu_instr
*instr
)
1518 LLVMValueRef src
[4], result
= NULL
;
1519 unsigned num_components
= instr
->dest
.dest
.ssa
.num_components
;
1520 unsigned src_components
;
1521 LLVMTypeRef def_type
= get_def_type(ctx
, &instr
->dest
.dest
.ssa
);
1523 assert(nir_op_infos
[instr
->op
].num_inputs
<= ARRAY_SIZE(src
));
1524 switch (instr
->op
) {
1530 case nir_op_pack_half_2x16
:
1533 case nir_op_unpack_half_2x16
:
1537 src_components
= num_components
;
1540 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1541 src
[i
] = get_alu_src(ctx
, instr
->src
[i
], src_components
);
1543 switch (instr
->op
) {
1549 src
[0] = to_float(&ctx
->ac
, src
[0]);
1550 result
= LLVMBuildFNeg(ctx
->ac
.builder
, src
[0], "");
1553 result
= LLVMBuildNeg(ctx
->ac
.builder
, src
[0], "");
1556 result
= LLVMBuildNot(ctx
->ac
.builder
, src
[0], "");
1559 result
= LLVMBuildAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1562 src
[0] = to_float(&ctx
->ac
, src
[0]);
1563 src
[1] = to_float(&ctx
->ac
, src
[1]);
1564 result
= LLVMBuildFAdd(ctx
->ac
.builder
, src
[0], src
[1], "");
1567 src
[0] = to_float(&ctx
->ac
, src
[0]);
1568 src
[1] = to_float(&ctx
->ac
, src
[1]);
1569 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1572 result
= LLVMBuildSub(ctx
->ac
.builder
, src
[0], src
[1], "");
1575 result
= LLVMBuildMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1578 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1581 result
= LLVMBuildURem(ctx
->ac
.builder
, src
[0], src
[1], "");
1584 src
[0] = to_float(&ctx
->ac
, src
[0]);
1585 src
[1] = to_float(&ctx
->ac
, src
[1]);
1586 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1587 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1588 to_float_type(&ctx
->ac
, def_type
), result
);
1589 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[1] , result
, "");
1590 result
= LLVMBuildFSub(ctx
->ac
.builder
, src
[0], result
, "");
1593 src
[0] = to_float(&ctx
->ac
, src
[0]);
1594 src
[1] = to_float(&ctx
->ac
, src
[1]);
1595 result
= LLVMBuildFRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1598 result
= LLVMBuildSRem(ctx
->ac
.builder
, src
[0], src
[1], "");
1601 result
= LLVMBuildSDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1604 result
= LLVMBuildUDiv(ctx
->ac
.builder
, src
[0], src
[1], "");
1607 src
[0] = to_float(&ctx
->ac
, src
[0]);
1608 src
[1] = to_float(&ctx
->ac
, src
[1]);
1609 result
= LLVMBuildFMul(ctx
->ac
.builder
, src
[0], src
[1], "");
1612 src
[0] = to_float(&ctx
->ac
, src
[0]);
1613 src
[1] = to_float(&ctx
->ac
, src
[1]);
1614 result
= ac_build_fdiv(&ctx
->ac
, src
[0], src
[1]);
1617 src
[0] = to_float(&ctx
->ac
, src
[0]);
1618 result
= ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, src
[0]);
1621 result
= LLVMBuildAnd(ctx
->ac
.builder
, src
[0], src
[1], "");
1624 result
= LLVMBuildOr(ctx
->ac
.builder
, src
[0], src
[1], "");
1627 result
= LLVMBuildXor(ctx
->ac
.builder
, src
[0], src
[1], "");
1630 result
= LLVMBuildShl(ctx
->ac
.builder
, src
[0],
1631 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1632 LLVMTypeOf(src
[0]), ""),
1636 result
= LLVMBuildAShr(ctx
->ac
.builder
, src
[0],
1637 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1638 LLVMTypeOf(src
[0]), ""),
1642 result
= LLVMBuildLShr(ctx
->ac
.builder
, src
[0],
1643 LLVMBuildZExt(ctx
->ac
.builder
, src
[1],
1644 LLVMTypeOf(src
[0]), ""),
1648 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1651 result
= emit_int_cmp(&ctx
->ac
, LLVMIntNE
, src
[0], src
[1]);
1654 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, src
[0], src
[1]);
1657 result
= emit_int_cmp(&ctx
->ac
, LLVMIntSGE
, src
[0], src
[1]);
1660 result
= emit_int_cmp(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1663 result
= emit_int_cmp(&ctx
->ac
, LLVMIntUGE
, src
[0], src
[1]);
1666 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUEQ
, src
[0], src
[1]);
1669 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUNE
, src
[0], src
[1]);
1672 result
= emit_float_cmp(&ctx
->ac
, LLVMRealULT
, src
[0], src
[1]);
1675 result
= emit_float_cmp(&ctx
->ac
, LLVMRealUGE
, src
[0], src
[1]);
1678 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.fabs",
1679 to_float_type(&ctx
->ac
, def_type
), src
[0]);
1682 result
= emit_iabs(&ctx
->ac
, src
[0]);
1685 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, src
[0], src
[1]);
1688 result
= emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, src
[0], src
[1]);
1691 result
= emit_minmax_int(&ctx
->ac
, LLVMIntUGT
, src
[0], src
[1]);
1694 result
= emit_minmax_int(&ctx
->ac
, LLVMIntULT
, src
[0], src
[1]);
1697 result
= emit_isign(&ctx
->ac
, src
[0]);
1700 src
[0] = to_float(&ctx
->ac
, src
[0]);
1701 result
= emit_fsign(&ctx
->ac
, src
[0]);
1704 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.floor",
1705 to_float_type(&ctx
->ac
, def_type
), src
[0]);
1708 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.trunc",
1709 to_float_type(&ctx
->ac
, def_type
), src
[0]);
1712 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.ceil",
1713 to_float_type(&ctx
->ac
, def_type
), src
[0]);
1715 case nir_op_fround_even
:
1716 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.rint",
1717 to_float_type(&ctx
->ac
, def_type
),src
[0]);
1720 result
= emit_ffract(&ctx
->ac
, src
[0]);
1723 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sin",
1724 to_float_type(&ctx
->ac
, def_type
), src
[0]);
1727 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.cos",
1728 to_float_type(&ctx
->ac
, def_type
), src
[0]);
1731 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1732 to_float_type(&ctx
->ac
, def_type
), src
[0]);
1735 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.exp2",
1736 to_float_type(&ctx
->ac
, def_type
), src
[0]);
1739 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.log2",
1740 to_float_type(&ctx
->ac
, def_type
), src
[0]);
1743 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.sqrt",
1744 to_float_type(&ctx
->ac
, def_type
), src
[0]);
1745 result
= ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, result
);
1748 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.pow",
1749 to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1752 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.maxnum",
1753 to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1754 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1755 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1756 to_float_type(&ctx
->ac
, def_type
),
1760 result
= emit_intrin_2f_param(&ctx
->ac
, "llvm.minnum",
1761 to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1]);
1762 if (instr
->dest
.dest
.ssa
.bit_size
== 32)
1763 result
= emit_intrin_1f_param(&ctx
->ac
, "llvm.canonicalize",
1764 to_float_type(&ctx
->ac
, def_type
),
1768 result
= emit_intrin_3f_param(&ctx
->ac
, "llvm.fma",
1769 to_float_type(&ctx
->ac
, def_type
), src
[0], src
[1], src
[2]);
1771 case nir_op_ibitfield_extract
:
1772 result
= emit_bitfield_extract(&ctx
->ac
, true, src
);
1774 case nir_op_ubitfield_extract
:
1775 result
= emit_bitfield_extract(&ctx
->ac
, false, src
);
1777 case nir_op_bitfield_insert
:
1778 result
= emit_bitfield_insert(&ctx
->ac
, src
[0], src
[1], src
[2], src
[3]);
1780 case nir_op_bitfield_reverse
:
1781 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.bitreverse.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1783 case nir_op_bit_count
:
1784 result
= ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i32", ctx
->ac
.i32
, src
, 1, AC_FUNC_ATTR_READNONE
);
1789 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1790 src
[i
] = to_integer(&ctx
->ac
, src
[i
]);
1791 result
= ac_build_gather_values(&ctx
->ac
, src
, num_components
);
1795 src
[0] = to_float(&ctx
->ac
, src
[0]);
1796 result
= LLVMBuildFPToSI(ctx
->ac
.builder
, src
[0], def_type
, "");
1800 src
[0] = to_float(&ctx
->ac
, src
[0]);
1801 result
= LLVMBuildFPToUI(ctx
->ac
.builder
, src
[0], def_type
, "");
1805 result
= LLVMBuildSIToFP(ctx
->ac
.builder
, src
[0], to_float_type(&ctx
->ac
, def_type
), "");
1809 result
= LLVMBuildUIToFP(ctx
->ac
.builder
, src
[0], to_float_type(&ctx
->ac
, def_type
), "");
1812 result
= LLVMBuildFPExt(ctx
->ac
.builder
, src
[0], to_float_type(&ctx
->ac
, def_type
), "");
1815 result
= LLVMBuildFPTrunc(ctx
->ac
.builder
, src
[0], to_float_type(&ctx
->ac
, def_type
), "");
1819 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1820 result
= LLVMBuildZExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1822 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1826 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
[0])) < get_elem_bits(&ctx
->ac
, def_type
))
1827 result
= LLVMBuildSExt(ctx
->ac
.builder
, src
[0], def_type
, "");
1829 result
= LLVMBuildTrunc(ctx
->ac
.builder
, src
[0], def_type
, "");
1832 result
= emit_bcsel(&ctx
->ac
, src
[0], src
[1], src
[2]);
1834 case nir_op_find_lsb
:
1835 result
= emit_find_lsb(&ctx
->ac
, src
[0]);
1837 case nir_op_ufind_msb
:
1838 result
= emit_ufind_msb(&ctx
->ac
, src
[0]);
1840 case nir_op_ifind_msb
:
1841 result
= emit_ifind_msb(&ctx
->ac
, src
[0]);
1843 case nir_op_uadd_carry
:
1844 result
= emit_uint_carry(&ctx
->ac
, "llvm.uadd.with.overflow.i32", src
[0], src
[1]);
1846 case nir_op_usub_borrow
:
1847 result
= emit_uint_carry(&ctx
->ac
, "llvm.usub.with.overflow.i32", src
[0], src
[1]);
1850 result
= emit_b2f(&ctx
->ac
, src
[0]);
1853 result
= emit_f2b(&ctx
->ac
, src
[0]);
1856 result
= emit_b2i(&ctx
->ac
, src
[0]);
1859 result
= emit_i2b(&ctx
->ac
, src
[0]);
1861 case nir_op_fquantize2f16
:
1862 result
= emit_f2f16(ctx
->nctx
, src
[0]);
1864 case nir_op_umul_high
:
1865 result
= emit_umul_high(&ctx
->ac
, src
[0], src
[1]);
1867 case nir_op_imul_high
:
1868 result
= emit_imul_high(&ctx
->ac
, src
[0], src
[1]);
1870 case nir_op_pack_half_2x16
:
1871 result
= emit_pack_half_2x16(&ctx
->ac
, src
[0]);
1873 case nir_op_unpack_half_2x16
:
1874 result
= emit_unpack_half_2x16(&ctx
->ac
, src
[0]);
1878 case nir_op_fddx_fine
:
1879 case nir_op_fddy_fine
:
1880 case nir_op_fddx_coarse
:
1881 case nir_op_fddy_coarse
:
1882 result
= emit_ddxy(ctx
->nctx
, instr
->op
, src
[0]);
1885 case nir_op_unpack_64_2x32_split_x
: {
1886 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
1887 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
1888 LLVMVectorType(ctx
->ac
.i32
, 2),
1890 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
1895 case nir_op_unpack_64_2x32_split_y
: {
1896 assert(instr
->src
[0].src
.ssa
->num_components
== 1);
1897 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, src
[0],
1898 LLVMVectorType(ctx
->ac
.i32
, 2),
1900 result
= LLVMBuildExtractElement(ctx
->ac
.builder
, tmp
,
1905 case nir_op_pack_64_2x32_split
: {
1906 LLVMValueRef tmp
= LLVMGetUndef(LLVMVectorType(ctx
->ac
.i32
, 2));
1907 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
1908 src
[0], ctx
->ac
.i32_0
, "");
1909 tmp
= LLVMBuildInsertElement(ctx
->ac
.builder
, tmp
,
1910 src
[1], ctx
->ac
.i32_1
, "");
1911 result
= LLVMBuildBitCast(ctx
->ac
.builder
, tmp
, ctx
->ac
.i64
, "");
1916 fprintf(stderr
, "Unknown NIR alu instr: ");
1917 nir_print_instr(&instr
->instr
, stderr
);
1918 fprintf(stderr
, "\n");
1923 assert(instr
->dest
.dest
.is_ssa
);
1924 result
= to_integer(&ctx
->ac
, result
);
1925 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.dest
.ssa
,
1930 static void visit_load_const(struct ac_nir_context
*ctx
,
1931 const nir_load_const_instr
*instr
)
1933 LLVMValueRef values
[4], value
= NULL
;
1934 LLVMTypeRef element_type
=
1935 LLVMIntTypeInContext(ctx
->ac
.context
, instr
->def
.bit_size
);
1937 for (unsigned i
= 0; i
< instr
->def
.num_components
; ++i
) {
1938 switch (instr
->def
.bit_size
) {
1940 values
[i
] = LLVMConstInt(element_type
,
1941 instr
->value
.u32
[i
], false);
1944 values
[i
] = LLVMConstInt(element_type
,
1945 instr
->value
.u64
[i
], false);
1949 "unsupported nir load_const bit_size: %d\n",
1950 instr
->def
.bit_size
);
1954 if (instr
->def
.num_components
> 1) {
1955 value
= LLVMConstVector(values
, instr
->def
.num_components
);
1959 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, value
);
1962 static LLVMValueRef
cast_ptr(struct nir_to_llvm_context
*ctx
, LLVMValueRef ptr
,
1965 int addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
1966 return LLVMBuildBitCast(ctx
->builder
, ptr
,
1967 LLVMPointerType(type
, addr_space
), "");
1971 get_buffer_size(struct nir_to_llvm_context
*ctx
, LLVMValueRef descriptor
, bool in_elements
)
1974 LLVMBuildExtractElement(ctx
->builder
, descriptor
,
1975 LLVMConstInt(ctx
->i32
, 2, false), "");
1978 if (ctx
->options
->chip_class
>= VI
&& in_elements
) {
1979 /* On VI, the descriptor contains the size in bytes,
1980 * but TXQ must return the size in elements.
1981 * The stride is always non-zero for resources using TXQ.
1983 LLVMValueRef stride
=
1984 LLVMBuildExtractElement(ctx
->builder
, descriptor
,
1985 LLVMConstInt(ctx
->i32
, 1, false), "");
1986 stride
= LLVMBuildLShr(ctx
->builder
, stride
,
1987 LLVMConstInt(ctx
->i32
, 16, false), "");
1988 stride
= LLVMBuildAnd(ctx
->builder
, stride
,
1989 LLVMConstInt(ctx
->i32
, 0x3fff, false), "");
1991 size
= LLVMBuildUDiv(ctx
->builder
, size
, stride
, "");
1997 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2000 static void build_int_type_name(
2002 char *buf
, unsigned bufsize
)
2004 assert(bufsize
>= 6);
2006 if (LLVMGetTypeKind(type
) == LLVMVectorTypeKind
)
2007 snprintf(buf
, bufsize
, "v%ui32",
2008 LLVMGetVectorSize(type
));
2013 static LLVMValueRef
radv_lower_gather4_integer(struct nir_to_llvm_context
*ctx
,
2014 struct ac_image_args
*args
,
2015 const nir_tex_instr
*instr
)
2017 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2018 LLVMValueRef coord
= args
->addr
;
2019 LLVMValueRef half_texel
[2];
2020 LLVMValueRef compare_cube_wa
;
2021 LLVMValueRef result
;
2023 unsigned coord_vgpr_index
= (unsigned)args
->offset
+ (unsigned)args
->compare
;
2027 struct ac_image_args txq_args
= { 0 };
2029 txq_args
.da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
2030 txq_args
.opcode
= ac_image_get_resinfo
;
2031 txq_args
.dmask
= 0xf;
2032 txq_args
.addr
= ctx
->i32zero
;
2033 txq_args
.resource
= args
->resource
;
2034 LLVMValueRef size
= ac_build_image_opcode(&ctx
->ac
, &txq_args
);
2036 for (c
= 0; c
< 2; c
++) {
2037 half_texel
[c
] = LLVMBuildExtractElement(ctx
->builder
, size
,
2038 LLVMConstInt(ctx
->i32
, c
, false), "");
2039 half_texel
[c
] = LLVMBuildUIToFP(ctx
->builder
, half_texel
[c
], ctx
->f32
, "");
2040 half_texel
[c
] = ac_build_fdiv(&ctx
->ac
, ctx
->f32one
, half_texel
[c
]);
2041 half_texel
[c
] = LLVMBuildFMul(ctx
->builder
, half_texel
[c
],
2042 LLVMConstReal(ctx
->f32
, -0.5), "");
2046 LLVMValueRef orig_coords
= args
->addr
;
2048 for (c
= 0; c
< 2; c
++) {
2050 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
2051 tmp
= LLVMBuildExtractElement(ctx
->builder
, coord
, index
, "");
2052 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2053 tmp
= LLVMBuildFAdd(ctx
->builder
, tmp
, half_texel
[c
], "");
2054 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2055 coord
= LLVMBuildInsertElement(ctx
->builder
, coord
, tmp
, index
, "");
2060 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2061 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2062 * workaround by sampling using a scaled type and converting.
2063 * This is taken from amdgpu-pro shaders.
2065 /* NOTE this produces some ugly code compared to amdgpu-pro,
2066 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2067 * and then reads them back. -pro generates two selects,
2068 * one s_cmp for the descriptor rewriting
2069 * one v_cmp for the coordinate and result changes.
2071 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2072 LLVMValueRef tmp
, tmp2
;
2074 /* workaround 8/8/8/8 uint/sint cube gather bug */
2075 /* first detect it then change to a scaled read and f2i */
2076 tmp
= LLVMBuildExtractElement(ctx
->builder
, args
->resource
, ctx
->i32one
, "");
2079 /* extract the DATA_FORMAT */
2080 tmp
= ac_build_bfe(&ctx
->ac
, tmp
, LLVMConstInt(ctx
->i32
, 20, false),
2081 LLVMConstInt(ctx
->i32
, 6, false), false);
2083 /* is the DATA_FORMAT == 8_8_8_8 */
2084 compare_cube_wa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, tmp
, LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false), "");
2086 if (stype
== GLSL_TYPE_UINT
)
2087 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2088 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0x8000000, false),
2089 LLVMConstInt(ctx
->i32
, 0x10000000, false), "");
2091 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2092 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, LLVMConstInt(ctx
->i32
, 0xc000000, false),
2093 LLVMConstInt(ctx
->i32
, 0x14000000, false), "");
2095 /* replace the NUM FORMAT in the descriptor */
2096 tmp2
= LLVMBuildAnd(ctx
->builder
, tmp2
, LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false), "");
2097 tmp2
= LLVMBuildOr(ctx
->builder
, tmp2
, tmp
, "");
2099 args
->resource
= LLVMBuildInsertElement(ctx
->builder
, args
->resource
, tmp2
, ctx
->i32one
, "");
2101 /* don't modify the coordinates for this case */
2102 coord
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, orig_coords
, coord
, "");
2105 result
= ac_build_image_opcode(&ctx
->ac
, args
);
2107 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
2108 LLVMValueRef tmp
, tmp2
;
2110 /* if the cube workaround is in place, f2i the result. */
2111 for (c
= 0; c
< 4; c
++) {
2112 tmp
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, c
, false), "");
2113 if (stype
== GLSL_TYPE_UINT
)
2114 tmp2
= LLVMBuildFPToUI(ctx
->builder
, tmp
, ctx
->i32
, "");
2116 tmp2
= LLVMBuildFPToSI(ctx
->builder
, tmp
, ctx
->i32
, "");
2117 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->i32
, "");
2118 tmp2
= LLVMBuildBitCast(ctx
->builder
, tmp2
, ctx
->i32
, "");
2119 tmp
= LLVMBuildSelect(ctx
->builder
, compare_cube_wa
, tmp2
, tmp
, "");
2120 tmp
= LLVMBuildBitCast(ctx
->builder
, tmp
, ctx
->f32
, "");
2121 result
= LLVMBuildInsertElement(ctx
->builder
, result
, tmp
, LLVMConstInt(ctx
->i32
, c
, false), "");
2127 static LLVMValueRef
build_tex_intrinsic(struct nir_to_llvm_context
*ctx
,
2128 const nir_tex_instr
*instr
,
2130 struct ac_image_args
*args
)
2132 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
2133 return ac_build_buffer_load_format(&ctx
->ac
,
2136 LLVMConstInt(ctx
->i32
, 0, false),
2140 args
->opcode
= ac_image_sample
;
2141 args
->compare
= instr
->is_shadow
;
2143 switch (instr
->op
) {
2145 case nir_texop_txf_ms
:
2146 case nir_texop_samples_identical
:
2147 args
->opcode
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
? ac_image_load
: ac_image_load_mip
;
2148 args
->compare
= false;
2149 args
->offset
= false;
2156 args
->level_zero
= true;
2161 case nir_texop_query_levels
:
2162 args
->opcode
= ac_image_get_resinfo
;
2165 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
2166 args
->level_zero
= true;
2172 args
->opcode
= ac_image_gather4
;
2173 args
->level_zero
= true;
2176 args
->opcode
= ac_image_get_lod
;
2177 args
->compare
= false;
2178 args
->offset
= false;
2184 if (instr
->op
== nir_texop_tg4
) {
2185 enum glsl_base_type stype
= glsl_get_sampler_result_type(instr
->texture
->var
->type
);
2186 if (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
) {
2187 return radv_lower_gather4_integer(ctx
, args
, instr
);
2190 return ac_build_image_opcode(&ctx
->ac
, args
);
2193 static LLVMValueRef
visit_vulkan_resource_index(struct nir_to_llvm_context
*ctx
,
2194 nir_intrinsic_instr
*instr
)
2196 LLVMValueRef index
= get_src(ctx
->nir
, instr
->src
[0]);
2197 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
2198 unsigned binding
= nir_intrinsic_binding(instr
);
2199 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
2200 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
2201 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
2202 unsigned base_offset
= layout
->binding
[binding
].offset
;
2203 LLVMValueRef offset
, stride
;
2205 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
2206 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
2207 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
2208 layout
->binding
[binding
].dynamic_offset_offset
;
2209 desc_ptr
= ctx
->push_constants
;
2210 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
2211 stride
= LLVMConstInt(ctx
->i32
, 16, false);
2213 stride
= LLVMConstInt(ctx
->i32
, layout
->binding
[binding
].size
, false);
2215 offset
= LLVMConstInt(ctx
->i32
, base_offset
, false);
2216 index
= LLVMBuildMul(ctx
->builder
, index
, stride
, "");
2217 offset
= LLVMBuildAdd(ctx
->builder
, offset
, index
, "");
2219 desc_ptr
= ac_build_gep0(&ctx
->ac
, desc_ptr
, offset
);
2220 desc_ptr
= cast_ptr(ctx
, desc_ptr
, ctx
->v4i32
);
2221 LLVMSetMetadata(desc_ptr
, ctx
->uniform_md_kind
, ctx
->empty_md
);
2223 return LLVMBuildLoad(ctx
->builder
, desc_ptr
, "");
2226 static LLVMValueRef
visit_load_push_constant(struct nir_to_llvm_context
*ctx
,
2227 nir_intrinsic_instr
*instr
)
2229 LLVMValueRef ptr
, addr
;
2231 addr
= LLVMConstInt(ctx
->i32
, nir_intrinsic_base(instr
), 0);
2232 addr
= LLVMBuildAdd(ctx
->builder
, addr
, get_src(ctx
->nir
, instr
->src
[0]), "");
2234 ptr
= ac_build_gep0(&ctx
->ac
, ctx
->push_constants
, addr
);
2235 ptr
= cast_ptr(ctx
, ptr
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
));
2237 return LLVMBuildLoad(ctx
->builder
, ptr
, "");
2240 static LLVMValueRef
visit_get_buffer_size(struct nir_to_llvm_context
*ctx
,
2241 const nir_intrinsic_instr
*instr
)
2243 LLVMValueRef desc
= get_src(ctx
->nir
, instr
->src
[0]);
2245 return get_buffer_size(ctx
, desc
, false);
2247 static void visit_store_ssbo(struct nir_to_llvm_context
*ctx
,
2248 nir_intrinsic_instr
*instr
)
2250 const char *store_name
;
2251 LLVMValueRef src_data
= get_src(ctx
->nir
, instr
->src
[0]);
2252 LLVMTypeRef data_type
= ctx
->f32
;
2253 int elem_size_mult
= get_elem_bits(&ctx
->ac
, LLVMTypeOf(src_data
)) / 32;
2254 int components_32bit
= elem_size_mult
* instr
->num_components
;
2255 unsigned writemask
= nir_intrinsic_write_mask(instr
);
2256 LLVMValueRef base_data
, base_offset
;
2257 LLVMValueRef params
[6];
2259 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2260 ctx
->shader_info
->fs
.writes_memory
= true;
2262 params
[1] = get_src(ctx
->nir
, instr
->src
[1]);
2263 params
[2] = LLVMConstInt(ctx
->i32
, 0, false); /* vindex */
2264 params
[4] = ctx
->i1false
; /* glc */
2265 params
[5] = ctx
->i1false
; /* slc */
2267 if (components_32bit
> 1)
2268 data_type
= LLVMVectorType(ctx
->f32
, components_32bit
);
2270 base_data
= to_float(&ctx
->ac
, src_data
);
2271 base_data
= trim_vector(ctx
, base_data
, instr
->num_components
);
2272 base_data
= LLVMBuildBitCast(ctx
->builder
, base_data
,
2274 base_offset
= get_src(ctx
->nir
, instr
->src
[2]); /* voffset */
2278 LLVMValueRef offset
;
2280 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
2282 /* Due to an LLVM limitation, split 3-element writes
2283 * into a 2-element and a 1-element write. */
2285 writemask
|= 1 << (start
+ 2);
2289 start
*= elem_size_mult
;
2290 count
*= elem_size_mult
;
2293 writemask
|= ((1u << (count
- 4)) - 1u) << (start
+ 4);
2298 store_name
= "llvm.amdgcn.buffer.store.v4f32";
2300 } else if (count
== 2) {
2301 tmp
= LLVMBuildExtractElement(ctx
->builder
,
2302 base_data
, LLVMConstInt(ctx
->i32
, start
, false), "");
2303 data
= LLVMBuildInsertElement(ctx
->builder
, LLVMGetUndef(ctx
->v2f32
), tmp
,
2306 tmp
= LLVMBuildExtractElement(ctx
->builder
,
2307 base_data
, LLVMConstInt(ctx
->i32
, start
+ 1, false), "");
2308 data
= LLVMBuildInsertElement(ctx
->builder
, data
, tmp
,
2310 store_name
= "llvm.amdgcn.buffer.store.v2f32";
2314 if (get_llvm_num_components(base_data
) > 1)
2315 data
= LLVMBuildExtractElement(ctx
->builder
, base_data
,
2316 LLVMConstInt(ctx
->i32
, start
, false), "");
2319 store_name
= "llvm.amdgcn.buffer.store.f32";
2322 offset
= base_offset
;
2324 offset
= LLVMBuildAdd(ctx
->builder
, offset
, LLVMConstInt(ctx
->i32
, start
* 4, false), "");
2328 ac_build_intrinsic(&ctx
->ac
, store_name
,
2329 ctx
->voidt
, params
, 6, 0);
2333 static LLVMValueRef
visit_atomic_ssbo(struct nir_to_llvm_context
*ctx
,
2334 const nir_intrinsic_instr
*instr
)
2337 LLVMValueRef params
[6];
2339 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2340 ctx
->shader_info
->fs
.writes_memory
= true;
2342 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
) {
2343 params
[arg_count
++] = llvm_extract_elem(ctx
, get_src(ctx
->nir
, instr
->src
[3]), 0);
2345 params
[arg_count
++] = llvm_extract_elem(ctx
, get_src(ctx
->nir
, instr
->src
[2]), 0);
2346 params
[arg_count
++] = get_src(ctx
->nir
, instr
->src
[0]);
2347 params
[arg_count
++] = LLVMConstInt(ctx
->i32
, 0, false); /* vindex */
2348 params
[arg_count
++] = get_src(ctx
->nir
, instr
->src
[1]); /* voffset */
2349 params
[arg_count
++] = ctx
->i1false
; /* slc */
2351 switch (instr
->intrinsic
) {
2352 case nir_intrinsic_ssbo_atomic_add
:
2353 name
= "llvm.amdgcn.buffer.atomic.add";
2355 case nir_intrinsic_ssbo_atomic_imin
:
2356 name
= "llvm.amdgcn.buffer.atomic.smin";
2358 case nir_intrinsic_ssbo_atomic_umin
:
2359 name
= "llvm.amdgcn.buffer.atomic.umin";
2361 case nir_intrinsic_ssbo_atomic_imax
:
2362 name
= "llvm.amdgcn.buffer.atomic.smax";
2364 case nir_intrinsic_ssbo_atomic_umax
:
2365 name
= "llvm.amdgcn.buffer.atomic.umax";
2367 case nir_intrinsic_ssbo_atomic_and
:
2368 name
= "llvm.amdgcn.buffer.atomic.and";
2370 case nir_intrinsic_ssbo_atomic_or
:
2371 name
= "llvm.amdgcn.buffer.atomic.or";
2373 case nir_intrinsic_ssbo_atomic_xor
:
2374 name
= "llvm.amdgcn.buffer.atomic.xor";
2376 case nir_intrinsic_ssbo_atomic_exchange
:
2377 name
= "llvm.amdgcn.buffer.atomic.swap";
2379 case nir_intrinsic_ssbo_atomic_comp_swap
:
2380 name
= "llvm.amdgcn.buffer.atomic.cmpswap";
2386 return ac_build_intrinsic(&ctx
->ac
, name
, ctx
->i32
, params
, arg_count
, 0);
2389 static LLVMValueRef
visit_load_buffer(struct nir_to_llvm_context
*ctx
,
2390 const nir_intrinsic_instr
*instr
)
2392 LLVMValueRef results
[2];
2393 int load_components
;
2394 int num_components
= instr
->num_components
;
2395 if (instr
->dest
.ssa
.bit_size
== 64)
2396 num_components
*= 2;
2398 for (int i
= 0; i
< num_components
; i
+= load_components
) {
2399 load_components
= MIN2(num_components
- i
, 4);
2400 const char *load_name
;
2401 LLVMTypeRef data_type
= ctx
->f32
;
2402 LLVMValueRef offset
= LLVMConstInt(ctx
->i32
, i
* 4, false);
2403 offset
= LLVMBuildAdd(ctx
->builder
, get_src(ctx
->nir
, instr
->src
[1]), offset
, "");
2405 if (load_components
== 3)
2406 data_type
= LLVMVectorType(ctx
->f32
, 4);
2407 else if (load_components
> 1)
2408 data_type
= LLVMVectorType(ctx
->f32
, load_components
);
2410 if (load_components
>= 3)
2411 load_name
= "llvm.amdgcn.buffer.load.v4f32";
2412 else if (load_components
== 2)
2413 load_name
= "llvm.amdgcn.buffer.load.v2f32";
2414 else if (load_components
== 1)
2415 load_name
= "llvm.amdgcn.buffer.load.f32";
2417 unreachable("unhandled number of components");
2419 LLVMValueRef params
[] = {
2420 get_src(ctx
->nir
, instr
->src
[0]),
2421 LLVMConstInt(ctx
->i32
, 0, false),
2427 results
[i
] = ac_build_intrinsic(&ctx
->ac
, load_name
, data_type
, params
, 5, 0);
2431 LLVMValueRef ret
= results
[0];
2432 if (num_components
> 4 || num_components
== 3) {
2433 LLVMValueRef masks
[] = {
2434 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
2435 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false),
2436 LLVMConstInt(ctx
->i32
, 4, false), LLVMConstInt(ctx
->i32
, 5, false),
2437 LLVMConstInt(ctx
->i32
, 6, false), LLVMConstInt(ctx
->i32
, 7, false)
2440 LLVMValueRef swizzle
= LLVMConstVector(masks
, num_components
);
2441 ret
= LLVMBuildShuffleVector(ctx
->builder
, results
[0],
2442 results
[num_components
> 4 ? 1 : 0], swizzle
, "");
2445 return LLVMBuildBitCast(ctx
->builder
, ret
,
2446 get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2449 static LLVMValueRef
visit_load_ubo_buffer(struct nir_to_llvm_context
*ctx
,
2450 const nir_intrinsic_instr
*instr
)
2452 LLVMValueRef results
[8], ret
;
2453 LLVMValueRef rsrc
= get_src(ctx
->nir
, instr
->src
[0]);
2454 LLVMValueRef offset
= get_src(ctx
->nir
, instr
->src
[1]);
2455 int num_components
= instr
->num_components
;
2457 if (instr
->dest
.ssa
.bit_size
== 64)
2458 num_components
*= 2;
2460 for (unsigned i
= 0; i
< num_components
; ++i
) {
2461 LLVMValueRef params
[] = {
2463 LLVMBuildAdd(ctx
->builder
, LLVMConstInt(ctx
->i32
, 4 * i
, 0),
2466 results
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.load.const.v4i32", ctx
->f32
,
2468 AC_FUNC_ATTR_READNONE
|
2469 AC_FUNC_ATTR_LEGACY
);
2473 ret
= ac_build_gather_values(&ctx
->ac
, results
, instr
->num_components
);
2474 return LLVMBuildBitCast(ctx
->builder
, ret
,
2475 get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2479 radv_get_deref_offset(struct nir_to_llvm_context
*ctx
, nir_deref_var
*deref
,
2480 bool vs_in
, unsigned *vertex_index_out
,
2481 LLVMValueRef
*vertex_index_ref
,
2482 unsigned *const_out
, LLVMValueRef
*indir_out
)
2484 unsigned const_offset
= 0;
2485 nir_deref
*tail
= &deref
->deref
;
2486 LLVMValueRef offset
= NULL
;
2488 if (vertex_index_out
!= NULL
|| vertex_index_ref
!= NULL
) {
2490 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2491 if (vertex_index_out
)
2492 *vertex_index_out
= deref_array
->base_offset
;
2494 if (vertex_index_ref
) {
2495 LLVMValueRef vtx
= LLVMConstInt(ctx
->i32
, deref_array
->base_offset
, false);
2496 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
2497 vtx
= LLVMBuildAdd(ctx
->builder
, vtx
, get_src(ctx
->nir
, deref_array
->indirect
), "");
2499 *vertex_index_ref
= vtx
;
2503 if (deref
->var
->data
.compact
) {
2504 assert(tail
->child
->deref_type
== nir_deref_type_array
);
2505 assert(glsl_type_is_scalar(glsl_without_array(deref
->var
->type
)));
2506 nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
2507 /* We always lower indirect dereferences for "compact" array vars. */
2508 assert(deref_array
->deref_array_type
== nir_deref_array_type_direct
);
2510 const_offset
= deref_array
->base_offset
;
2514 while (tail
->child
!= NULL
) {
2515 const struct glsl_type
*parent_type
= tail
->type
;
2518 if (tail
->deref_type
== nir_deref_type_array
) {
2519 nir_deref_array
*deref_array
= nir_deref_as_array(tail
);
2520 LLVMValueRef index
, stride
, local_offset
;
2521 unsigned size
= glsl_count_attribute_slots(tail
->type
, vs_in
);
2523 const_offset
+= size
* deref_array
->base_offset
;
2524 if (deref_array
->deref_array_type
== nir_deref_array_type_direct
)
2527 assert(deref_array
->deref_array_type
== nir_deref_array_type_indirect
);
2528 index
= get_src(ctx
->nir
, deref_array
->indirect
);
2529 stride
= LLVMConstInt(ctx
->i32
, size
, 0);
2530 local_offset
= LLVMBuildMul(ctx
->builder
, stride
, index
, "");
2533 offset
= LLVMBuildAdd(ctx
->builder
, offset
, local_offset
, "");
2535 offset
= local_offset
;
2536 } else if (tail
->deref_type
== nir_deref_type_struct
) {
2537 nir_deref_struct
*deref_struct
= nir_deref_as_struct(tail
);
2539 for (unsigned i
= 0; i
< deref_struct
->index
; i
++) {
2540 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
2541 const_offset
+= glsl_count_attribute_slots(ft
, vs_in
);
2544 unreachable("unsupported deref type");
2548 if (const_offset
&& offset
)
2549 offset
= LLVMBuildAdd(ctx
->builder
, offset
,
2550 LLVMConstInt(ctx
->i32
, const_offset
, 0),
2553 *const_out
= const_offset
;
2554 *indir_out
= offset
;
2558 lds_load(struct nir_to_llvm_context
*ctx
,
2559 LLVMValueRef dw_addr
)
2562 value
= ac_build_indexed_load(&ctx
->ac
, ctx
->lds
, dw_addr
, false);
2567 lds_store(struct nir_to_llvm_context
*ctx
,
2568 LLVMValueRef dw_addr
, LLVMValueRef value
)
2570 value
= LLVMBuildBitCast(ctx
->builder
, value
, ctx
->i32
, "");
2571 ac_build_indexed_store(&ctx
->ac
, ctx
->lds
,
2575 /* The offchip buffer layout for TCS->TES is
2577 * - attribute 0 of patch 0 vertex 0
2578 * - attribute 0 of patch 0 vertex 1
2579 * - attribute 0 of patch 0 vertex 2
2581 * - attribute 0 of patch 1 vertex 0
2582 * - attribute 0 of patch 1 vertex 1
2584 * - attribute 1 of patch 0 vertex 0
2585 * - attribute 1 of patch 0 vertex 1
2587 * - per patch attribute 0 of patch 0
2588 * - per patch attribute 0 of patch 1
2591 * Note that every attribute has 4 components.
2593 static LLVMValueRef
get_tcs_tes_buffer_address(struct nir_to_llvm_context
*ctx
,
2594 LLVMValueRef vertex_index
,
2595 LLVMValueRef param_index
)
2597 LLVMValueRef base_addr
, vertices_per_patch
, num_patches
, total_vertices
;
2598 LLVMValueRef param_stride
, constant16
;
2599 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
2601 vertices_per_patch
= unpack_param(ctx
, ctx
->tcs_offchip_layout
, 9, 6);
2602 num_patches
= unpack_param(ctx
, ctx
->tcs_offchip_layout
, 0, 9);
2603 total_vertices
= LLVMBuildMul(ctx
->builder
, vertices_per_patch
,
2606 constant16
= LLVMConstInt(ctx
->i32
, 16, false);
2608 base_addr
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
2609 vertices_per_patch
, "");
2611 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2614 param_stride
= total_vertices
;
2616 base_addr
= rel_patch_id
;
2617 param_stride
= num_patches
;
2620 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2621 LLVMBuildMul(ctx
->builder
, param_index
,
2622 param_stride
, ""), "");
2624 base_addr
= LLVMBuildMul(ctx
->builder
, base_addr
, constant16
, "");
2626 if (!vertex_index
) {
2627 LLVMValueRef patch_data_offset
=
2628 unpack_param(ctx
, ctx
->tcs_offchip_layout
, 16, 16);
2630 base_addr
= LLVMBuildAdd(ctx
->builder
, base_addr
,
2631 patch_data_offset
, "");
2636 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct nir_to_llvm_context
*ctx
,
2638 unsigned const_index
,
2640 LLVMValueRef vertex_index
,
2641 LLVMValueRef indir_index
)
2643 LLVMValueRef param_index
;
2646 param_index
= LLVMBuildAdd(ctx
->builder
, LLVMConstInt(ctx
->i32
, param
, false),
2649 if (const_index
&& !is_compact
)
2650 param
+= const_index
;
2651 param_index
= LLVMConstInt(ctx
->i32
, param
, false);
2653 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
2657 mark_tess_output(struct nir_to_llvm_context
*ctx
,
2658 bool is_patch
, uint32_t param
)
2662 ctx
->tess_patch_outputs_written
|= (1ull << param
);
2664 ctx
->tess_outputs_written
|= (1ull << param
);
2668 get_dw_address(struct nir_to_llvm_context
*ctx
,
2669 LLVMValueRef dw_addr
,
2671 unsigned const_index
,
2672 bool compact_const_index
,
2673 LLVMValueRef vertex_index
,
2674 LLVMValueRef stride
,
2675 LLVMValueRef indir_index
)
2680 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2681 LLVMBuildMul(ctx
->builder
,
2687 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2688 LLVMBuildMul(ctx
->builder
, indir_index
,
2689 LLVMConstInt(ctx
->i32
, 4, false), ""), "");
2690 else if (const_index
&& !compact_const_index
)
2691 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2692 LLVMConstInt(ctx
->i32
, const_index
, false), "");
2694 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2695 LLVMConstInt(ctx
->i32
, param
* 4, false), "");
2697 if (const_index
&& compact_const_index
)
2698 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2699 LLVMConstInt(ctx
->i32
, const_index
, false), "");
2704 load_tcs_input(struct nir_to_llvm_context
*ctx
,
2705 nir_intrinsic_instr
*instr
)
2707 LLVMValueRef dw_addr
, stride
;
2708 unsigned const_index
;
2709 LLVMValueRef vertex_index
;
2710 LLVMValueRef indir_index
;
2712 LLVMValueRef value
[4], result
;
2713 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2714 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2715 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2716 radv_get_deref_offset(ctx
, instr
->variables
[0],
2717 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2718 &const_index
, &indir_index
);
2720 stride
= unpack_param(ctx
, ctx
->tcs_in_layout
, 13, 8);
2721 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
2722 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2725 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2726 value
[i
] = lds_load(ctx
, dw_addr
);
2727 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2730 result
= ac_build_gather_values(&ctx
->ac
, value
, instr
->num_components
);
2731 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2736 load_tcs_output(struct nir_to_llvm_context
*ctx
,
2737 nir_intrinsic_instr
*instr
)
2739 LLVMValueRef dw_addr
, stride
;
2740 LLVMValueRef value
[4], result
;
2741 LLVMValueRef vertex_index
= NULL
;
2742 LLVMValueRef indir_index
= NULL
;
2743 unsigned const_index
= 0;
2745 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2746 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2747 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2748 radv_get_deref_offset(ctx
, instr
->variables
[0],
2749 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2750 &const_index
, &indir_index
);
2752 if (!instr
->variables
[0]->var
->data
.patch
) {
2753 stride
= unpack_param(ctx
, ctx
->tcs_out_layout
, 13, 8);
2754 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2756 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2759 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2762 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2763 value
[i
] = lds_load(ctx
, dw_addr
);
2764 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2767 result
= ac_build_gather_values(&ctx
->ac
, value
, instr
->num_components
);
2768 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2773 store_tcs_output(struct nir_to_llvm_context
*ctx
,
2774 nir_intrinsic_instr
*instr
,
2778 LLVMValueRef stride
, dw_addr
;
2779 LLVMValueRef buf_addr
= NULL
;
2780 LLVMValueRef vertex_index
= NULL
;
2781 LLVMValueRef indir_index
= NULL
;
2782 unsigned const_index
= 0;
2784 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2785 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2787 radv_get_deref_offset(ctx
, instr
->variables
[0],
2788 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2789 &const_index
, &indir_index
);
2791 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2792 if (instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_CLIP_DIST0
&&
2793 is_compact
&& const_index
> 3) {
2798 if (!instr
->variables
[0]->var
->data
.patch
) {
2799 stride
= unpack_param(ctx
, ctx
->tcs_out_layout
, 13, 8);
2800 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
2802 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
2805 mark_tess_output(ctx
, instr
->variables
[0]->var
->data
.patch
, param
);
2807 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
2809 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
2810 vertex_index
, indir_index
);
2812 unsigned base
= is_compact
? const_index
: 0;
2813 for (unsigned chan
= 0; chan
< 8; chan
++) {
2814 bool is_tess_factor
= false;
2815 if (!(writemask
& (1 << chan
)))
2817 LLVMValueRef value
= llvm_extract_elem(ctx
, src
, chan
);
2819 lds_store(ctx
, dw_addr
, value
);
2821 if (instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_TESS_LEVEL_INNER
||
2822 instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
2823 is_tess_factor
= true;
2825 if (!is_tess_factor
&& writemask
!= 0xF)
2826 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
2827 buf_addr
, ctx
->oc_lds
,
2828 4 * (base
+ chan
), 1, 0, true, false);
2830 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
,
2834 if (writemask
== 0xF) {
2835 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
2836 buf_addr
, ctx
->oc_lds
,
2837 (base
* 4), 1, 0, true, false);
2842 load_tes_input(struct nir_to_llvm_context
*ctx
,
2843 const nir_intrinsic_instr
*instr
)
2845 LLVMValueRef buf_addr
;
2846 LLVMValueRef result
;
2847 LLVMValueRef vertex_index
= NULL
;
2848 LLVMValueRef indir_index
= NULL
;
2849 unsigned const_index
= 0;
2851 const bool per_vertex
= nir_is_per_vertex_io(instr
->variables
[0]->var
, ctx
->stage
);
2852 const bool is_compact
= instr
->variables
[0]->var
->data
.compact
;
2854 radv_get_deref_offset(ctx
, instr
->variables
[0],
2855 false, NULL
, per_vertex
? &vertex_index
: NULL
,
2856 &const_index
, &indir_index
);
2857 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2858 if (instr
->variables
[0]->var
->data
.location
== VARYING_SLOT_CLIP_DIST0
&&
2859 is_compact
&& const_index
> 3) {
2863 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
2864 is_compact
, vertex_index
, indir_index
);
2866 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, instr
->num_components
, NULL
,
2867 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, 1, 0, true, false);
2868 result
= trim_vector(ctx
, result
, instr
->num_components
);
2869 result
= LLVMBuildBitCast(ctx
->builder
, result
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
2874 load_gs_input(struct nir_to_llvm_context
*ctx
,
2875 nir_intrinsic_instr
*instr
)
2877 LLVMValueRef indir_index
, vtx_offset
;
2878 unsigned const_index
;
2879 LLVMValueRef args
[9];
2880 unsigned param
, vtx_offset_param
;
2881 LLVMValueRef value
[4], result
;
2882 unsigned vertex_index
;
2883 radv_get_deref_offset(ctx
, instr
->variables
[0],
2884 false, &vertex_index
, NULL
,
2885 &const_index
, &indir_index
);
2886 vtx_offset_param
= vertex_index
;
2887 assert(vtx_offset_param
< 6);
2888 vtx_offset
= LLVMBuildMul(ctx
->builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
2889 LLVMConstInt(ctx
->i32
, 4, false), "");
2891 param
= shader_io_get_unique_index(instr
->variables
[0]->var
->data
.location
);
2892 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2894 args
[0] = ctx
->esgs_ring
;
2895 args
[1] = vtx_offset
;
2896 args
[2] = LLVMConstInt(ctx
->i32
, (param
* 4 + i
+ const_index
) * 256, false);
2897 args
[3] = ctx
->i32zero
;
2898 args
[4] = ctx
->i32one
; /* OFFEN */
2899 args
[5] = ctx
->i32zero
; /* IDXEN */
2900 args
[6] = ctx
->i32one
; /* GLC */
2901 args
[7] = ctx
->i32zero
; /* SLC */
2902 args
[8] = ctx
->i32zero
; /* TFE */
2904 value
[i
] = ac_build_intrinsic(&ctx
->ac
, "llvm.SI.buffer.load.dword.i32.i32",
2906 AC_FUNC_ATTR_READONLY
|
2907 AC_FUNC_ATTR_LEGACY
);
2909 result
= ac_build_gather_values(&ctx
->ac
, value
, instr
->num_components
);
2915 build_gep_for_deref(struct ac_nir_context
*ctx
,
2916 nir_deref_var
*deref
)
2918 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->vars
, deref
->var
);
2919 assert(entry
->data
);
2920 LLVMValueRef val
= entry
->data
;
2921 nir_deref
*tail
= deref
->deref
.child
;
2922 while (tail
!= NULL
) {
2923 LLVMValueRef offset
;
2924 switch (tail
->deref_type
) {
2925 case nir_deref_type_array
: {
2926 nir_deref_array
*array
= nir_deref_as_array(tail
);
2927 offset
= LLVMConstInt(ctx
->ac
.i32
, array
->base_offset
, 0);
2928 if (array
->deref_array_type
==
2929 nir_deref_array_type_indirect
) {
2930 offset
= LLVMBuildAdd(ctx
->ac
.builder
, offset
,
2937 case nir_deref_type_struct
: {
2938 nir_deref_struct
*deref_struct
=
2939 nir_deref_as_struct(tail
);
2940 offset
= LLVMConstInt(ctx
->ac
.i32
,
2941 deref_struct
->index
, 0);
2945 unreachable("bad deref type");
2947 val
= ac_build_gep0(&ctx
->ac
, val
, offset
);
2953 static LLVMValueRef
visit_load_var(struct nir_to_llvm_context
*ctx
,
2954 nir_intrinsic_instr
*instr
)
2956 LLVMValueRef values
[8];
2957 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
2958 int ve
= instr
->dest
.ssa
.num_components
;
2959 LLVMValueRef indir_index
;
2961 unsigned const_index
;
2962 bool vs_in
= ctx
->stage
== MESA_SHADER_VERTEX
&&
2963 instr
->variables
[0]->var
->data
.mode
== nir_var_shader_in
;
2964 radv_get_deref_offset(ctx
, instr
->variables
[0], vs_in
, NULL
, NULL
,
2965 &const_index
, &indir_index
);
2967 if (instr
->dest
.ssa
.bit_size
== 64)
2970 switch (instr
->variables
[0]->var
->data
.mode
) {
2971 case nir_var_shader_in
:
2972 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
2973 return load_tcs_input(ctx
, instr
);
2974 if (ctx
->stage
== MESA_SHADER_TESS_EVAL
)
2975 return load_tes_input(ctx
, instr
);
2976 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
2977 return load_gs_input(ctx
, instr
);
2979 for (unsigned chan
= 0; chan
< ve
; chan
++) {
2981 unsigned count
= glsl_count_attribute_slots(
2982 instr
->variables
[0]->var
->type
,
2983 ctx
->stage
== MESA_SHADER_VERTEX
);
2985 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
2986 &ctx
->ac
, ctx
->inputs
+ idx
+ chan
, count
,
2989 values
[chan
] = LLVMBuildExtractElement(ctx
->builder
,
2993 values
[chan
] = ctx
->inputs
[idx
+ chan
+ const_index
* 4];
2997 for (unsigned chan
= 0; chan
< ve
; chan
++) {
2999 unsigned count
= glsl_count_attribute_slots(
3000 instr
->variables
[0]->var
->type
, false);
3002 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3003 &ctx
->ac
, ctx
->nir
->locals
+ idx
+ chan
, count
,
3006 values
[chan
] = LLVMBuildExtractElement(ctx
->builder
,
3010 values
[chan
] = LLVMBuildLoad(ctx
->builder
, ctx
->nir
->locals
[idx
+ chan
+ const_index
* 4], "");
3014 case nir_var_shared
: {
3015 LLVMValueRef address
= build_gep_for_deref(ctx
->nir
,
3016 instr
->variables
[0]);
3017 LLVMValueRef val
= LLVMBuildLoad(ctx
->builder
, address
, "");
3018 return LLVMBuildBitCast(ctx
->builder
, val
,
3019 get_def_type(ctx
->nir
, &instr
->dest
.ssa
),
3022 case nir_var_shader_out
:
3023 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
3024 return load_tcs_output(ctx
, instr
);
3025 for (unsigned chan
= 0; chan
< ve
; chan
++) {
3027 unsigned count
= glsl_count_attribute_slots(
3028 instr
->variables
[0]->var
->type
, false);
3030 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3031 &ctx
->ac
, ctx
->nir
->outputs
+ idx
+ chan
, count
,
3034 values
[chan
] = LLVMBuildExtractElement(ctx
->builder
,
3038 values
[chan
] = LLVMBuildLoad(ctx
->builder
,
3039 ctx
->nir
->outputs
[idx
+ chan
+ const_index
* 4],
3045 unreachable("unhandle variable mode");
3047 ret
= ac_build_gather_values(&ctx
->ac
, values
, ve
);
3048 return LLVMBuildBitCast(ctx
->builder
, ret
, get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
3052 visit_store_var(struct nir_to_llvm_context
*ctx
,
3053 nir_intrinsic_instr
*instr
)
3055 LLVMValueRef temp_ptr
, value
;
3056 int idx
= instr
->variables
[0]->var
->data
.driver_location
;
3057 LLVMValueRef src
= to_float(&ctx
->ac
, get_src(ctx
->nir
, instr
->src
[0]));
3058 int writemask
= instr
->const_index
[0];
3059 LLVMValueRef indir_index
;
3060 unsigned const_index
;
3061 radv_get_deref_offset(ctx
, instr
->variables
[0], false,
3062 NULL
, NULL
, &const_index
, &indir_index
);
3064 if (get_elem_bits(&ctx
->ac
, LLVMTypeOf(src
)) == 64) {
3065 int old_writemask
= writemask
;
3067 src
= LLVMBuildBitCast(ctx
->builder
, src
,
3068 LLVMVectorType(ctx
->f32
, get_llvm_num_components(src
) * 2),
3072 for (unsigned chan
= 0; chan
< 4; chan
++) {
3073 if (old_writemask
& (1 << chan
))
3074 writemask
|= 3u << (2 * chan
);
3078 switch (instr
->variables
[0]->var
->data
.mode
) {
3079 case nir_var_shader_out
:
3081 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3082 store_tcs_output(ctx
, instr
, src
, writemask
);
3086 for (unsigned chan
= 0; chan
< 8; chan
++) {
3088 if (!(writemask
& (1 << chan
)))
3091 value
= llvm_extract_elem(ctx
, src
, chan
);
3093 if (instr
->variables
[0]->var
->data
.compact
)
3096 unsigned count
= glsl_count_attribute_slots(
3097 instr
->variables
[0]->var
->type
, false);
3099 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3100 &ctx
->ac
, ctx
->nir
->outputs
+ idx
+ chan
, count
,
3103 if (get_llvm_num_components(tmp_vec
) > 1) {
3104 tmp_vec
= LLVMBuildInsertElement(ctx
->builder
, tmp_vec
,
3105 value
, indir_index
, "");
3108 build_store_values_extended(ctx
, ctx
->nir
->outputs
+ idx
+ chan
,
3109 count
, stride
, tmp_vec
);
3112 temp_ptr
= ctx
->nir
->outputs
[idx
+ chan
+ const_index
* stride
];
3114 LLVMBuildStore(ctx
->builder
, value
, temp_ptr
);
3119 for (unsigned chan
= 0; chan
< 8; chan
++) {
3120 if (!(writemask
& (1 << chan
)))
3123 value
= llvm_extract_elem(ctx
, src
, chan
);
3125 unsigned count
= glsl_count_attribute_slots(
3126 instr
->variables
[0]->var
->type
, false);
3128 LLVMValueRef tmp_vec
= ac_build_gather_values_extended(
3129 &ctx
->ac
, ctx
->nir
->locals
+ idx
+ chan
, count
,
3132 tmp_vec
= LLVMBuildInsertElement(ctx
->builder
, tmp_vec
,
3133 value
, indir_index
, "");
3134 build_store_values_extended(ctx
, ctx
->nir
->locals
+ idx
+ chan
,
3137 temp_ptr
= ctx
->nir
->locals
[idx
+ chan
+ const_index
* 4];
3139 LLVMBuildStore(ctx
->builder
, value
, temp_ptr
);
3143 case nir_var_shared
: {
3144 int writemask
= instr
->const_index
[0];
3145 LLVMValueRef address
= build_gep_for_deref(ctx
->nir
,
3146 instr
->variables
[0]);
3147 LLVMValueRef val
= get_src(ctx
->nir
, instr
->src
[0]);
3148 unsigned components
=
3149 glsl_get_vector_elements(
3150 nir_deref_tail(&instr
->variables
[0]->deref
)->type
);
3151 if (writemask
== (1 << components
) - 1) {
3152 val
= LLVMBuildBitCast(
3154 LLVMGetElementType(LLVMTypeOf(address
)), "");
3155 LLVMBuildStore(ctx
->builder
, val
, address
);
3157 for (unsigned chan
= 0; chan
< 4; chan
++) {
3158 if (!(writemask
& (1 << chan
)))
3161 LLVMBuildStructGEP(ctx
->builder
,
3163 LLVMValueRef src
= llvm_extract_elem(ctx
, val
,
3165 src
= LLVMBuildBitCast(
3167 LLVMGetElementType(LLVMTypeOf(ptr
)), "");
3168 LLVMBuildStore(ctx
->builder
, src
, ptr
);
3178 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3181 case GLSL_SAMPLER_DIM_BUF
:
3183 case GLSL_SAMPLER_DIM_1D
:
3184 return array
? 2 : 1;
3185 case GLSL_SAMPLER_DIM_2D
:
3186 return array
? 3 : 2;
3187 case GLSL_SAMPLER_DIM_MS
:
3188 return array
? 4 : 3;
3189 case GLSL_SAMPLER_DIM_3D
:
3190 case GLSL_SAMPLER_DIM_CUBE
:
3192 case GLSL_SAMPLER_DIM_RECT
:
3193 case GLSL_SAMPLER_DIM_SUBPASS
:
3195 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3205 /* Adjust the sample index according to FMASK.
3207 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3208 * which is the identity mapping. Each nibble says which physical sample
3209 * should be fetched to get that sample.
3211 * For example, 0x11111100 means there are only 2 samples stored and
3212 * the second sample covers 3/4 of the pixel. When reading samples 0
3213 * and 1, return physical sample 0 (determined by the first two 0s
3214 * in FMASK), otherwise return physical sample 1.
3216 * The sample index should be adjusted as follows:
3217 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3219 static LLVMValueRef
adjust_sample_index_using_fmask(struct nir_to_llvm_context
*ctx
,
3220 LLVMValueRef coord_x
, LLVMValueRef coord_y
,
3221 LLVMValueRef coord_z
,
3222 LLVMValueRef sample_index
,
3223 LLVMValueRef fmask_desc_ptr
)
3225 LLVMValueRef fmask_load_address
[4];
3228 fmask_load_address
[0] = coord_x
;
3229 fmask_load_address
[1] = coord_y
;
3231 fmask_load_address
[2] = coord_z
;
3232 fmask_load_address
[3] = LLVMGetUndef(ctx
->i32
);
3235 struct ac_image_args args
= {0};
3237 args
.opcode
= ac_image_load
;
3238 args
.da
= coord_z
? true : false;
3239 args
.resource
= fmask_desc_ptr
;
3241 args
.addr
= ac_build_gather_values(&ctx
->ac
, fmask_load_address
, coord_z
? 4 : 2);
3243 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3245 res
= to_integer(&ctx
->ac
, res
);
3246 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, false);
3247 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xf, false);
3249 LLVMValueRef fmask
= LLVMBuildExtractElement(ctx
->builder
,
3253 LLVMValueRef sample_index4
=
3254 LLVMBuildMul(ctx
->builder
, sample_index
, four
, "");
3255 LLVMValueRef shifted_fmask
=
3256 LLVMBuildLShr(ctx
->builder
, fmask
, sample_index4
, "");
3257 LLVMValueRef final_sample
=
3258 LLVMBuildAnd(ctx
->builder
, shifted_fmask
, F
, "");
3260 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3261 * resource descriptor is 0 (invalid),
3263 LLVMValueRef fmask_desc
=
3264 LLVMBuildBitCast(ctx
->builder
, fmask_desc_ptr
,
3267 LLVMValueRef fmask_word1
=
3268 LLVMBuildExtractElement(ctx
->builder
, fmask_desc
,
3271 LLVMValueRef word1_is_nonzero
=
3272 LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3273 fmask_word1
, ctx
->i32zero
, "");
3275 /* Replace the MSAA sample index. */
3277 LLVMBuildSelect(ctx
->builder
, word1_is_nonzero
,
3278 final_sample
, sample_index
, "");
3279 return sample_index
;
3282 static LLVMValueRef
get_image_coords(struct nir_to_llvm_context
*ctx
,
3283 const nir_intrinsic_instr
*instr
)
3285 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3286 if(instr
->variables
[0]->deref
.child
)
3287 type
= instr
->variables
[0]->deref
.child
->type
;
3289 LLVMValueRef src0
= get_src(ctx
->nir
, instr
->src
[0]);
3290 LLVMValueRef coords
[4];
3291 LLVMValueRef masks
[] = {
3292 LLVMConstInt(ctx
->i32
, 0, false), LLVMConstInt(ctx
->i32
, 1, false),
3293 LLVMConstInt(ctx
->i32
, 2, false), LLVMConstInt(ctx
->i32
, 3, false),
3296 LLVMValueRef sample_index
= llvm_extract_elem(ctx
, get_src(ctx
->nir
, instr
->src
[1]), 0);
3299 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3300 bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
3301 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3302 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
||
3303 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3305 count
= image_type_to_components_count(dim
,
3306 glsl_sampler_type_is_array(type
));
3309 LLVMValueRef fmask_load_address
[3];
3312 fmask_load_address
[0] = LLVMBuildExtractElement(ctx
->builder
, src0
, masks
[0], "");
3313 fmask_load_address
[1] = LLVMBuildExtractElement(ctx
->builder
, src0
, masks
[1], "");
3314 if (glsl_sampler_type_is_array(type
))
3315 fmask_load_address
[2] = LLVMBuildExtractElement(ctx
->builder
, src0
, masks
[2], "");
3317 fmask_load_address
[2] = NULL
;
3319 for (chan
= 0; chan
< 2; ++chan
)
3320 fmask_load_address
[chan
] = LLVMBuildAdd(ctx
->builder
, fmask_load_address
[chan
], LLVMBuildFPToUI(ctx
->builder
, ctx
->frag_pos
[chan
], ctx
->i32
, ""), "");
3322 sample_index
= adjust_sample_index_using_fmask(ctx
,
3323 fmask_load_address
[0],
3324 fmask_load_address
[1],
3325 fmask_load_address
[2],
3327 get_sampler_desc(ctx
, instr
->variables
[0], DESC_FMASK
));
3330 if (instr
->src
[0].ssa
->num_components
)
3331 res
= LLVMBuildExtractElement(ctx
->builder
, src0
, masks
[0], "");
3338 for (chan
= 0; chan
< count
; ++chan
) {
3339 coords
[chan
] = LLVMBuildExtractElement(ctx
->builder
, src0
, masks
[chan
], "");
3343 for (chan
= 0; chan
< count
; ++chan
)
3344 coords
[chan
] = LLVMBuildAdd(ctx
->builder
, coords
[chan
], LLVMBuildFPToUI(ctx
->builder
, ctx
->frag_pos
[chan
], ctx
->i32
, ""), "");
3347 coords
[count
] = sample_index
;
3352 coords
[3] = LLVMGetUndef(ctx
->i32
);
3355 res
= ac_build_gather_values(&ctx
->ac
, coords
, count
);
3360 static LLVMValueRef
visit_image_load(struct nir_to_llvm_context
*ctx
,
3361 const nir_intrinsic_instr
*instr
)
3363 LLVMValueRef params
[7];
3365 char intrinsic_name
[64];
3366 const nir_variable
*var
= instr
->variables
[0]->var
;
3367 const struct glsl_type
*type
= var
->type
;
3368 if(instr
->variables
[0]->deref
.child
)
3369 type
= instr
->variables
[0]->deref
.child
->type
;
3371 type
= glsl_without_array(type
);
3372 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3373 params
[0] = get_sampler_desc(ctx
, instr
->variables
[0], DESC_BUFFER
);
3374 params
[1] = LLVMBuildExtractElement(ctx
->builder
, get_src(ctx
->nir
, instr
->src
[0]),
3375 LLVMConstInt(ctx
->i32
, 0, false), ""); /* vindex */
3376 params
[2] = LLVMConstInt(ctx
->i32
, 0, false); /* voffset */
3377 params
[3] = ctx
->i1false
; /* glc */
3378 params
[4] = ctx
->i1false
; /* slc */
3379 res
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.load.format.v4f32", ctx
->v4f32
,
3382 res
= trim_vector(ctx
, res
, instr
->dest
.ssa
.num_components
);
3383 res
= to_integer(&ctx
->ac
, res
);
3385 bool is_da
= glsl_sampler_type_is_array(type
) ||
3386 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3387 LLVMValueRef da
= is_da
? ctx
->i1true
: ctx
->i1false
;
3388 LLVMValueRef glc
= ctx
->i1false
;
3389 LLVMValueRef slc
= ctx
->i1false
;
3391 params
[0] = get_image_coords(ctx
, instr
);
3392 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], DESC_IMAGE
);
3393 params
[2] = LLVMConstInt(ctx
->i32
, 15, false); /* dmask */
3394 if (HAVE_LLVM
<= 0x0309) {
3395 params
[3] = ctx
->i1false
; /* r128 */
3400 LLVMValueRef lwe
= ctx
->i1false
;
3407 ac_get_image_intr_name("llvm.amdgcn.image.load",
3408 ctx
->v4f32
, /* vdata */
3409 LLVMTypeOf(params
[0]), /* coords */
3410 LLVMTypeOf(params
[1]), /* rsrc */
3411 intrinsic_name
, sizeof(intrinsic_name
));
3413 res
= ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->v4f32
,
3414 params
, 7, AC_FUNC_ATTR_READONLY
);
3416 return to_integer(&ctx
->ac
, res
);
3419 static void visit_image_store(struct nir_to_llvm_context
*ctx
,
3420 nir_intrinsic_instr
*instr
)
3422 LLVMValueRef params
[8];
3423 char intrinsic_name
[64];
3424 const nir_variable
*var
= instr
->variables
[0]->var
;
3425 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3426 LLVMValueRef glc
= ctx
->i1false
;
3427 bool force_glc
= ctx
->options
->chip_class
== SI
;
3430 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
3431 ctx
->shader_info
->fs
.writes_memory
= true;
3433 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3434 params
[0] = to_float(&ctx
->ac
, get_src(ctx
->nir
, instr
->src
[2])); /* data */
3435 params
[1] = get_sampler_desc(ctx
, instr
->variables
[0], DESC_BUFFER
);
3436 params
[2] = LLVMBuildExtractElement(ctx
->builder
, get_src(ctx
->nir
, instr
->src
[0]),
3437 LLVMConstInt(ctx
->i32
, 0, false), ""); /* vindex */
3438 params
[3] = LLVMConstInt(ctx
->i32
, 0, false); /* voffset */
3439 params
[4] = glc
; /* glc */
3440 params
[5] = ctx
->i1false
; /* slc */
3441 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32", ctx
->voidt
,
3444 bool is_da
= glsl_sampler_type_is_array(type
) ||
3445 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3446 LLVMValueRef da
= is_da
? ctx
->i1true
: ctx
->i1false
;
3447 LLVMValueRef slc
= ctx
->i1false
;
3449 params
[0] = to_float(&ctx
->ac
, get_src(ctx
->nir
, instr
->src
[2]));
3450 params
[1] = get_image_coords(ctx
, instr
); /* coords */
3451 params
[2] = get_sampler_desc(ctx
, instr
->variables
[0], DESC_IMAGE
);
3452 params
[3] = LLVMConstInt(ctx
->i32
, 15, false); /* dmask */
3453 if (HAVE_LLVM
<= 0x0309) {
3454 params
[4] = ctx
->i1false
; /* r128 */
3459 LLVMValueRef lwe
= ctx
->i1false
;
3466 ac_get_image_intr_name("llvm.amdgcn.image.store",
3467 LLVMTypeOf(params
[0]), /* vdata */
3468 LLVMTypeOf(params
[1]), /* coords */
3469 LLVMTypeOf(params
[2]), /* rsrc */
3470 intrinsic_name
, sizeof(intrinsic_name
));
3472 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->voidt
,
3478 static LLVMValueRef
visit_image_atomic(struct nir_to_llvm_context
*ctx
,
3479 const nir_intrinsic_instr
*instr
)
3481 LLVMValueRef params
[6];
3482 int param_count
= 0;
3483 const nir_variable
*var
= instr
->variables
[0]->var
;
3485 const char *atomic_name
;
3486 char intrinsic_name
[41];
3487 const struct glsl_type
*type
= glsl_without_array(var
->type
);
3488 MAYBE_UNUSED
int length
;
3490 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
3491 ctx
->shader_info
->fs
.writes_memory
= true;
3493 switch (instr
->intrinsic
) {
3494 case nir_intrinsic_image_atomic_add
:
3495 atomic_name
= "add";
3497 case nir_intrinsic_image_atomic_min
:
3498 atomic_name
= "smin";
3500 case nir_intrinsic_image_atomic_max
:
3501 atomic_name
= "smax";
3503 case nir_intrinsic_image_atomic_and
:
3504 atomic_name
= "and";
3506 case nir_intrinsic_image_atomic_or
:
3509 case nir_intrinsic_image_atomic_xor
:
3510 atomic_name
= "xor";
3512 case nir_intrinsic_image_atomic_exchange
:
3513 atomic_name
= "swap";
3515 case nir_intrinsic_image_atomic_comp_swap
:
3516 atomic_name
= "cmpswap";
3522 if (instr
->intrinsic
== nir_intrinsic_image_atomic_comp_swap
)
3523 params
[param_count
++] = get_src(ctx
->nir
, instr
->src
[3]);
3524 params
[param_count
++] = get_src(ctx
->nir
, instr
->src
[2]);
3526 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
3527 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], DESC_BUFFER
);
3528 params
[param_count
++] = LLVMBuildExtractElement(ctx
->builder
, get_src(ctx
->nir
, instr
->src
[0]),
3529 LLVMConstInt(ctx
->i32
, 0, false), ""); /* vindex */
3530 params
[param_count
++] = ctx
->i32zero
; /* voffset */
3531 params
[param_count
++] = ctx
->i1false
; /* slc */
3533 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3534 "llvm.amdgcn.buffer.atomic.%s", atomic_name
);
3536 char coords_type
[8];
3538 bool da
= glsl_sampler_type_is_array(type
) ||
3539 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
;
3541 LLVMValueRef coords
= params
[param_count
++] = get_image_coords(ctx
, instr
);
3542 params
[param_count
++] = get_sampler_desc(ctx
, instr
->variables
[0], DESC_IMAGE
);
3543 params
[param_count
++] = ctx
->i1false
; /* r128 */
3544 params
[param_count
++] = da
? ctx
->i1true
: ctx
->i1false
; /* da */
3545 params
[param_count
++] = ctx
->i1false
; /* slc */
3547 build_int_type_name(LLVMTypeOf(coords
),
3548 coords_type
, sizeof(coords_type
));
3550 length
= snprintf(intrinsic_name
, sizeof(intrinsic_name
),
3551 "llvm.amdgcn.image.atomic.%s.%s", atomic_name
, coords_type
);
3554 assert(length
< sizeof(intrinsic_name
));
3555 return ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->i32
, params
, param_count
, 0);
3558 static LLVMValueRef
visit_image_size(struct nir_to_llvm_context
*ctx
,
3559 const nir_intrinsic_instr
*instr
)
3562 const nir_variable
*var
= instr
->variables
[0]->var
;
3563 const struct glsl_type
*type
= instr
->variables
[0]->var
->type
;
3564 bool da
= glsl_sampler_type_is_array(var
->type
) ||
3565 glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_CUBE
;
3566 if(instr
->variables
[0]->deref
.child
)
3567 type
= instr
->variables
[0]->deref
.child
->type
;
3569 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
)
3570 return get_buffer_size(ctx
, get_sampler_desc(ctx
, instr
->variables
[0], DESC_BUFFER
), true);
3572 struct ac_image_args args
= { 0 };
3576 args
.resource
= get_sampler_desc(ctx
, instr
->variables
[0], DESC_IMAGE
);
3577 args
.opcode
= ac_image_get_resinfo
;
3578 args
.addr
= ctx
->i32zero
;
3580 res
= ac_build_image_opcode(&ctx
->ac
, &args
);
3582 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
3583 glsl_sampler_type_is_array(type
)) {
3584 LLVMValueRef two
= LLVMConstInt(ctx
->i32
, 2, false);
3585 LLVMValueRef six
= LLVMConstInt(ctx
->i32
, 6, false);
3586 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->builder
, res
, two
, "");
3587 z
= LLVMBuildSDiv(ctx
->builder
, z
, six
, "");
3588 res
= LLVMBuildInsertElement(ctx
->builder
, res
, z
, two
, "");
3593 #define NOOP_WAITCNT 0xf7f
3594 #define LGKM_CNT 0x07f
3595 #define VM_CNT 0xf70
3597 static void emit_waitcnt(struct nir_to_llvm_context
*ctx
,
3600 LLVMValueRef args
[1] = {
3601 LLVMConstInt(ctx
->i32
, simm16
, false),
3603 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.s.waitcnt",
3604 ctx
->voidt
, args
, 1, 0);
3607 static void emit_barrier(struct nir_to_llvm_context
*ctx
)
3609 /* SI only (thanks to a hw bug workaround):
3610 * The real barrier instruction isn’t needed, because an entire patch
3611 * always fits into a single wave.
3613 if (ctx
->options
->chip_class
== SI
&&
3614 ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3615 emit_waitcnt(ctx
, LGKM_CNT
& VM_CNT
);
3618 ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.s.barrier",
3619 ctx
->voidt
, NULL
, 0, AC_FUNC_ATTR_CONVERGENT
);
3622 static void emit_discard_if(struct nir_to_llvm_context
*ctx
,
3623 const nir_intrinsic_instr
*instr
)
3626 ctx
->shader_info
->fs
.can_discard
= true;
3628 cond
= LLVMBuildICmp(ctx
->builder
, LLVMIntNE
,
3629 get_src(ctx
->nir
, instr
->src
[0]),
3632 cond
= LLVMBuildSelect(ctx
->builder
, cond
,
3633 LLVMConstReal(ctx
->f32
, -1.0f
),
3635 ac_build_kill(&ctx
->ac
, cond
);
3639 visit_load_local_invocation_index(struct nir_to_llvm_context
*ctx
)
3641 LLVMValueRef result
;
3642 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
->ac
);
3643 result
= LLVMBuildAnd(ctx
->builder
, ctx
->tg_size
,
3644 LLVMConstInt(ctx
->i32
, 0xfc0, false), "");
3646 return LLVMBuildAdd(ctx
->builder
, result
, thread_id
, "");
3649 static LLVMValueRef
visit_var_atomic(struct nir_to_llvm_context
*ctx
,
3650 const nir_intrinsic_instr
*instr
)
3652 LLVMValueRef ptr
, result
;
3653 LLVMValueRef src
= get_src(ctx
->nir
, instr
->src
[0]);
3654 ptr
= build_gep_for_deref(ctx
->nir
, instr
->variables
[0]);
3656 if (instr
->intrinsic
== nir_intrinsic_var_atomic_comp_swap
) {
3657 LLVMValueRef src1
= get_src(ctx
->nir
, instr
->src
[1]);
3658 result
= LLVMBuildAtomicCmpXchg(ctx
->builder
,
3660 LLVMAtomicOrderingSequentiallyConsistent
,
3661 LLVMAtomicOrderingSequentiallyConsistent
,
3664 LLVMAtomicRMWBinOp op
;
3665 switch (instr
->intrinsic
) {
3666 case nir_intrinsic_var_atomic_add
:
3667 op
= LLVMAtomicRMWBinOpAdd
;
3669 case nir_intrinsic_var_atomic_umin
:
3670 op
= LLVMAtomicRMWBinOpUMin
;
3672 case nir_intrinsic_var_atomic_umax
:
3673 op
= LLVMAtomicRMWBinOpUMax
;
3675 case nir_intrinsic_var_atomic_imin
:
3676 op
= LLVMAtomicRMWBinOpMin
;
3678 case nir_intrinsic_var_atomic_imax
:
3679 op
= LLVMAtomicRMWBinOpMax
;
3681 case nir_intrinsic_var_atomic_and
:
3682 op
= LLVMAtomicRMWBinOpAnd
;
3684 case nir_intrinsic_var_atomic_or
:
3685 op
= LLVMAtomicRMWBinOpOr
;
3687 case nir_intrinsic_var_atomic_xor
:
3688 op
= LLVMAtomicRMWBinOpXor
;
3690 case nir_intrinsic_var_atomic_exchange
:
3691 op
= LLVMAtomicRMWBinOpXchg
;
3697 result
= LLVMBuildAtomicRMW(ctx
->builder
, op
, ptr
, to_integer(&ctx
->ac
, src
),
3698 LLVMAtomicOrderingSequentiallyConsistent
,
3704 #define INTERP_CENTER 0
3705 #define INTERP_CENTROID 1
3706 #define INTERP_SAMPLE 2
3708 static LLVMValueRef
lookup_interp_param(struct nir_to_llvm_context
*ctx
,
3709 enum glsl_interp_mode interp
, unsigned location
)
3712 case INTERP_MODE_FLAT
:
3715 case INTERP_MODE_SMOOTH
:
3716 case INTERP_MODE_NONE
:
3717 if (location
== INTERP_CENTER
)
3718 return ctx
->persp_center
;
3719 else if (location
== INTERP_CENTROID
)
3720 return ctx
->persp_centroid
;
3721 else if (location
== INTERP_SAMPLE
)
3722 return ctx
->persp_sample
;
3724 case INTERP_MODE_NOPERSPECTIVE
:
3725 if (location
== INTERP_CENTER
)
3726 return ctx
->linear_center
;
3727 else if (location
== INTERP_CENTROID
)
3728 return ctx
->linear_centroid
;
3729 else if (location
== INTERP_SAMPLE
)
3730 return ctx
->linear_sample
;
3736 static LLVMValueRef
load_sample_position(struct nir_to_llvm_context
*ctx
,
3737 LLVMValueRef sample_id
)
3739 LLVMValueRef result
;
3740 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_PS_SAMPLE_POSITIONS
, false));
3742 ptr
= LLVMBuildBitCast(ctx
->builder
, ptr
,
3743 const_array(ctx
->v2f32
, 64), "");
3745 sample_id
= LLVMBuildAdd(ctx
->builder
, sample_id
, ctx
->sample_pos_offset
, "");
3746 result
= ac_build_indexed_load(&ctx
->ac
, ptr
, sample_id
, false);
3751 static LLVMValueRef
load_sample_pos(struct nir_to_llvm_context
*ctx
)
3753 LLVMValueRef values
[2];
3755 values
[0] = emit_ffract(&ctx
->ac
, ctx
->frag_pos
[0]);
3756 values
[1] = emit_ffract(&ctx
->ac
, ctx
->frag_pos
[1]);
3757 return ac_build_gather_values(&ctx
->ac
, values
, 2);
3760 static LLVMValueRef
visit_interp(struct nir_to_llvm_context
*ctx
,
3761 const nir_intrinsic_instr
*instr
)
3763 LLVMValueRef result
[2];
3764 LLVMValueRef interp_param
, attr_number
;
3767 LLVMValueRef src_c0
, src_c1
;
3769 int input_index
= instr
->variables
[0]->var
->data
.location
- VARYING_SLOT_VAR0
;
3770 switch (instr
->intrinsic
) {
3771 case nir_intrinsic_interp_var_at_centroid
:
3772 location
= INTERP_CENTROID
;
3774 case nir_intrinsic_interp_var_at_sample
:
3775 case nir_intrinsic_interp_var_at_offset
:
3776 location
= INTERP_CENTER
;
3777 src0
= get_src(ctx
->nir
, instr
->src
[0]);
3783 if (instr
->intrinsic
== nir_intrinsic_interp_var_at_offset
) {
3784 src_c0
= to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32zero
, ""));
3785 src_c1
= to_float(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
, src0
, ctx
->i32one
, ""));
3786 } else if (instr
->intrinsic
== nir_intrinsic_interp_var_at_sample
) {
3787 LLVMValueRef sample_position
;
3788 LLVMValueRef halfval
= LLVMConstReal(ctx
->f32
, 0.5f
);
3790 /* fetch sample ID */
3791 sample_position
= load_sample_position(ctx
, src0
);
3793 src_c0
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->i32zero
, "");
3794 src_c0
= LLVMBuildFSub(ctx
->builder
, src_c0
, halfval
, "");
3795 src_c1
= LLVMBuildExtractElement(ctx
->builder
, sample_position
, ctx
->i32one
, "");
3796 src_c1
= LLVMBuildFSub(ctx
->builder
, src_c1
, halfval
, "");
3798 interp_param
= lookup_interp_param(ctx
, instr
->variables
[0]->var
->data
.interpolation
, location
);
3799 attr_number
= LLVMConstInt(ctx
->i32
, input_index
, false);
3801 if (location
== INTERP_SAMPLE
|| location
== INTERP_CENTER
) {
3802 LLVMValueRef ij_out
[2];
3803 LLVMValueRef ddxy_out
= emit_ddxy_interp(ctx
, interp_param
);
3806 * take the I then J parameters, and the DDX/Y for it, and
3807 * calculate the IJ inputs for the interpolator.
3808 * temp1 = ddx * offset/sample.x + I;
3809 * interp_param.I = ddy * offset/sample.y + temp1;
3810 * temp1 = ddx * offset/sample.x + J;
3811 * interp_param.J = ddy * offset/sample.y + temp1;
3813 for (unsigned i
= 0; i
< 2; i
++) {
3814 LLVMValueRef ix_ll
= LLVMConstInt(ctx
->i32
, i
, false);
3815 LLVMValueRef iy_ll
= LLVMConstInt(ctx
->i32
, i
+ 2, false);
3816 LLVMValueRef ddx_el
= LLVMBuildExtractElement(ctx
->builder
,
3817 ddxy_out
, ix_ll
, "");
3818 LLVMValueRef ddy_el
= LLVMBuildExtractElement(ctx
->builder
,
3819 ddxy_out
, iy_ll
, "");
3820 LLVMValueRef interp_el
= LLVMBuildExtractElement(ctx
->builder
,
3821 interp_param
, ix_ll
, "");
3822 LLVMValueRef temp1
, temp2
;
3824 interp_el
= LLVMBuildBitCast(ctx
->builder
, interp_el
,
3827 temp1
= LLVMBuildFMul(ctx
->builder
, ddx_el
, src_c0
, "");
3828 temp1
= LLVMBuildFAdd(ctx
->builder
, temp1
, interp_el
, "");
3830 temp2
= LLVMBuildFMul(ctx
->builder
, ddy_el
, src_c1
, "");
3831 temp2
= LLVMBuildFAdd(ctx
->builder
, temp2
, temp1
, "");
3833 ij_out
[i
] = LLVMBuildBitCast(ctx
->builder
,
3834 temp2
, ctx
->i32
, "");
3836 interp_param
= ac_build_gather_values(&ctx
->ac
, ij_out
, 2);
3840 for (chan
= 0; chan
< 2; chan
++) {
3841 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->i32
, chan
, false);
3844 interp_param
= LLVMBuildBitCast(ctx
->builder
,
3845 interp_param
, LLVMVectorType(ctx
->f32
, 2), "");
3846 LLVMValueRef i
= LLVMBuildExtractElement(
3847 ctx
->builder
, interp_param
, ctx
->i32zero
, "");
3848 LLVMValueRef j
= LLVMBuildExtractElement(
3849 ctx
->builder
, interp_param
, ctx
->i32one
, "");
3851 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
3852 llvm_chan
, attr_number
,
3853 ctx
->prim_mask
, i
, j
);
3855 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
3856 LLVMConstInt(ctx
->i32
, 2, false),
3857 llvm_chan
, attr_number
,
3861 return ac_build_gather_values(&ctx
->ac
, result
, 2);
3865 visit_emit_vertex(struct nir_to_llvm_context
*ctx
,
3866 const nir_intrinsic_instr
*instr
)
3868 LLVMValueRef gs_next_vertex
;
3869 LLVMValueRef can_emit
, kill
;
3872 assert(instr
->const_index
[0] == 0);
3873 /* Write vertex attribute values to GSVS ring */
3874 gs_next_vertex
= LLVMBuildLoad(ctx
->builder
,
3875 ctx
->gs_next_vertex
,
3878 /* If this thread has already emitted the declared maximum number of
3879 * vertices, kill it: excessive vertex emissions are not supposed to
3880 * have any effect, and GS threads have no externally observable
3881 * effects other than emitting vertices.
3883 can_emit
= LLVMBuildICmp(ctx
->builder
, LLVMIntULT
, gs_next_vertex
,
3884 LLVMConstInt(ctx
->i32
, ctx
->gs_max_out_vertices
, false), "");
3886 kill
= LLVMBuildSelect(ctx
->builder
, can_emit
,
3887 LLVMConstReal(ctx
->f32
, 1.0f
),
3888 LLVMConstReal(ctx
->f32
, -1.0f
), "");
3889 ac_build_kill(&ctx
->ac
, kill
);
3891 /* loop num outputs */
3893 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
3894 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
3899 if (!(ctx
->output_mask
& (1ull << i
)))
3902 if (i
== VARYING_SLOT_CLIP_DIST0
) {
3903 /* pack clip and cull into a single set of slots */
3904 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
3908 for (unsigned j
= 0; j
< length
; j
++) {
3909 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
,
3911 LLVMValueRef voffset
= LLVMConstInt(ctx
->i32
, (slot
* 4 + j
) * ctx
->gs_max_out_vertices
, false);
3912 voffset
= LLVMBuildAdd(ctx
->builder
, voffset
, gs_next_vertex
, "");
3913 voffset
= LLVMBuildMul(ctx
->builder
, voffset
, LLVMConstInt(ctx
->i32
, 4, false), "");
3915 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->i32
, "");
3917 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->gsvs_ring
,
3919 voffset
, ctx
->gs2vs_offset
, 0,
3925 gs_next_vertex
= LLVMBuildAdd(ctx
->builder
, gs_next_vertex
,
3927 LLVMBuildStore(ctx
->builder
, gs_next_vertex
, ctx
->gs_next_vertex
);
3929 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
3933 visit_end_primitive(struct nir_to_llvm_context
*ctx
,
3934 const nir_intrinsic_instr
*instr
)
3936 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (0 << 8), ctx
->gs_wave_id
);
3940 visit_load_tess_coord(struct nir_to_llvm_context
*ctx
,
3941 const nir_intrinsic_instr
*instr
)
3943 LLVMValueRef coord
[4] = {
3950 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
3951 coord
[2] = LLVMBuildFSub(ctx
->builder
, ctx
->f32one
,
3952 LLVMBuildFAdd(ctx
->builder
, coord
[0], coord
[1], ""), "");
3954 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, coord
, instr
->num_components
);
3955 return LLVMBuildBitCast(ctx
->builder
, result
,
3956 get_def_type(ctx
->nir
, &instr
->dest
.ssa
), "");
3959 static void visit_intrinsic(struct ac_nir_context
*ctx
,
3960 nir_intrinsic_instr
*instr
)
3962 LLVMValueRef result
= NULL
;
3964 switch (instr
->intrinsic
) {
3965 case nir_intrinsic_load_work_group_id
: {
3966 result
= ctx
->nctx
->workgroup_ids
;
3969 case nir_intrinsic_load_base_vertex
: {
3970 result
= ctx
->abi
->base_vertex
;
3973 case nir_intrinsic_load_vertex_id_zero_base
: {
3974 result
= ctx
->abi
->vertex_id
;
3977 case nir_intrinsic_load_local_invocation_id
: {
3978 result
= ctx
->nctx
->local_invocation_ids
;
3981 case nir_intrinsic_load_base_instance
:
3982 result
= ctx
->abi
->start_instance
;
3984 case nir_intrinsic_load_draw_id
:
3985 result
= ctx
->abi
->draw_id
;
3987 case nir_intrinsic_load_invocation_id
:
3988 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
3989 result
= unpack_param(ctx
->nctx
, ctx
->nctx
->tcs_rel_ids
, 8, 5);
3991 result
= ctx
->nctx
->gs_invocation_id
;
3993 case nir_intrinsic_load_primitive_id
:
3994 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3995 ctx
->nctx
->shader_info
->gs
.uses_prim_id
= true;
3996 result
= ctx
->nctx
->gs_prim_id
;
3997 } else if (ctx
->stage
== MESA_SHADER_TESS_CTRL
) {
3998 ctx
->nctx
->shader_info
->tcs
.uses_prim_id
= true;
3999 result
= ctx
->nctx
->tcs_patch_id
;
4000 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4001 ctx
->nctx
->shader_info
->tcs
.uses_prim_id
= true;
4002 result
= ctx
->nctx
->tes_patch_id
;
4004 fprintf(stderr
, "Unknown primitive id intrinsic: %d", ctx
->stage
);
4006 case nir_intrinsic_load_sample_id
:
4007 ctx
->nctx
->shader_info
->fs
.force_persample
= true;
4008 result
= unpack_param(ctx
->nctx
, ctx
->nctx
->ancillary
, 8, 4);
4010 case nir_intrinsic_load_sample_pos
:
4011 ctx
->nctx
->shader_info
->fs
.force_persample
= true;
4012 result
= load_sample_pos(ctx
->nctx
);
4014 case nir_intrinsic_load_sample_mask_in
:
4015 result
= ctx
->nctx
->sample_coverage
;
4017 case nir_intrinsic_load_front_face
:
4018 result
= ctx
->nctx
->front_face
;
4020 case nir_intrinsic_load_instance_id
:
4021 result
= ctx
->abi
->instance_id
;
4022 ctx
->nctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(3,
4023 ctx
->nctx
->shader_info
->vs
.vgpr_comp_cnt
);
4025 case nir_intrinsic_load_num_work_groups
:
4026 result
= ctx
->nctx
->num_work_groups
;
4028 case nir_intrinsic_load_local_invocation_index
:
4029 result
= visit_load_local_invocation_index(ctx
->nctx
);
4031 case nir_intrinsic_load_push_constant
:
4032 result
= visit_load_push_constant(ctx
->nctx
, instr
);
4034 case nir_intrinsic_vulkan_resource_index
:
4035 result
= visit_vulkan_resource_index(ctx
->nctx
, instr
);
4037 case nir_intrinsic_store_ssbo
:
4038 visit_store_ssbo(ctx
->nctx
, instr
);
4040 case nir_intrinsic_load_ssbo
:
4041 result
= visit_load_buffer(ctx
->nctx
, instr
);
4043 case nir_intrinsic_ssbo_atomic_add
:
4044 case nir_intrinsic_ssbo_atomic_imin
:
4045 case nir_intrinsic_ssbo_atomic_umin
:
4046 case nir_intrinsic_ssbo_atomic_imax
:
4047 case nir_intrinsic_ssbo_atomic_umax
:
4048 case nir_intrinsic_ssbo_atomic_and
:
4049 case nir_intrinsic_ssbo_atomic_or
:
4050 case nir_intrinsic_ssbo_atomic_xor
:
4051 case nir_intrinsic_ssbo_atomic_exchange
:
4052 case nir_intrinsic_ssbo_atomic_comp_swap
:
4053 result
= visit_atomic_ssbo(ctx
->nctx
, instr
);
4055 case nir_intrinsic_load_ubo
:
4056 result
= visit_load_ubo_buffer(ctx
->nctx
, instr
);
4058 case nir_intrinsic_get_buffer_size
:
4059 result
= visit_get_buffer_size(ctx
->nctx
, instr
);
4061 case nir_intrinsic_load_var
:
4062 result
= visit_load_var(ctx
->nctx
, instr
);
4064 case nir_intrinsic_store_var
:
4065 visit_store_var(ctx
->nctx
, instr
);
4067 case nir_intrinsic_image_load
:
4068 result
= visit_image_load(ctx
->nctx
, instr
);
4070 case nir_intrinsic_image_store
:
4071 visit_image_store(ctx
->nctx
, instr
);
4073 case nir_intrinsic_image_atomic_add
:
4074 case nir_intrinsic_image_atomic_min
:
4075 case nir_intrinsic_image_atomic_max
:
4076 case nir_intrinsic_image_atomic_and
:
4077 case nir_intrinsic_image_atomic_or
:
4078 case nir_intrinsic_image_atomic_xor
:
4079 case nir_intrinsic_image_atomic_exchange
:
4080 case nir_intrinsic_image_atomic_comp_swap
:
4081 result
= visit_image_atomic(ctx
->nctx
, instr
);
4083 case nir_intrinsic_image_size
:
4084 result
= visit_image_size(ctx
->nctx
, instr
);
4086 case nir_intrinsic_discard
:
4087 ctx
->nctx
->shader_info
->fs
.can_discard
= true;
4088 ac_build_intrinsic(&ctx
->ac
, "llvm.AMDGPU.kilp",
4089 LLVMVoidTypeInContext(ctx
->ac
.context
),
4090 NULL
, 0, AC_FUNC_ATTR_LEGACY
);
4092 case nir_intrinsic_discard_if
:
4093 emit_discard_if(ctx
->nctx
, instr
);
4095 case nir_intrinsic_memory_barrier
:
4096 emit_waitcnt(ctx
->nctx
, VM_CNT
);
4098 case nir_intrinsic_barrier
:
4099 emit_barrier(ctx
->nctx
);
4101 case nir_intrinsic_var_atomic_add
:
4102 case nir_intrinsic_var_atomic_imin
:
4103 case nir_intrinsic_var_atomic_umin
:
4104 case nir_intrinsic_var_atomic_imax
:
4105 case nir_intrinsic_var_atomic_umax
:
4106 case nir_intrinsic_var_atomic_and
:
4107 case nir_intrinsic_var_atomic_or
:
4108 case nir_intrinsic_var_atomic_xor
:
4109 case nir_intrinsic_var_atomic_exchange
:
4110 case nir_intrinsic_var_atomic_comp_swap
:
4111 result
= visit_var_atomic(ctx
->nctx
, instr
);
4113 case nir_intrinsic_interp_var_at_centroid
:
4114 case nir_intrinsic_interp_var_at_sample
:
4115 case nir_intrinsic_interp_var_at_offset
:
4116 result
= visit_interp(ctx
->nctx
, instr
);
4118 case nir_intrinsic_emit_vertex
:
4119 visit_emit_vertex(ctx
->nctx
, instr
);
4121 case nir_intrinsic_end_primitive
:
4122 visit_end_primitive(ctx
->nctx
, instr
);
4124 case nir_intrinsic_load_tess_coord
:
4125 result
= visit_load_tess_coord(ctx
->nctx
, instr
);
4127 case nir_intrinsic_load_patch_vertices_in
:
4128 result
= LLVMConstInt(ctx
->ac
.i32
, ctx
->nctx
->options
->key
.tcs
.input_vertices
, false);
4131 fprintf(stderr
, "Unknown intrinsic: ");
4132 nir_print_instr(&instr
->instr
, stderr
);
4133 fprintf(stderr
, "\n");
4137 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4141 static LLVMValueRef
get_sampler_desc(struct nir_to_llvm_context
*ctx
,
4142 const nir_deref_var
*deref
,
4143 enum desc_type desc_type
)
4145 unsigned desc_set
= deref
->var
->data
.descriptor_set
;
4146 LLVMValueRef list
= ctx
->descriptor_sets
[desc_set
];
4147 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4148 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ deref
->var
->data
.binding
;
4149 unsigned offset
= binding
->offset
;
4150 unsigned stride
= binding
->size
;
4152 LLVMBuilderRef builder
= ctx
->builder
;
4154 LLVMValueRef index
= NULL
;
4155 unsigned constant_index
= 0;
4157 assert(deref
->var
->data
.binding
< layout
->binding_count
);
4159 switch (desc_type
) {
4171 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4181 unreachable("invalid desc_type\n");
4184 if (deref
->deref
.child
) {
4185 const nir_deref_array
*child
=
4186 (const nir_deref_array
*)deref
->deref
.child
;
4188 assert(child
->deref_array_type
!= nir_deref_array_type_wildcard
);
4189 offset
+= child
->base_offset
* stride
;
4190 if (child
->deref_array_type
== nir_deref_array_type_indirect
) {
4191 index
= get_src(ctx
->nir
, child
->indirect
);
4194 constant_index
= child
->base_offset
;
4196 if (desc_type
== DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4197 (!index
|| binding
->immutable_samplers_equal
)) {
4198 if (binding
->immutable_samplers_equal
)
4201 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4203 LLVMValueRef constants
[] = {
4204 LLVMConstInt(ctx
->i32
, samplers
[constant_index
* 4 + 0], 0),
4205 LLVMConstInt(ctx
->i32
, samplers
[constant_index
* 4 + 1], 0),
4206 LLVMConstInt(ctx
->i32
, samplers
[constant_index
* 4 + 2], 0),
4207 LLVMConstInt(ctx
->i32
, samplers
[constant_index
* 4 + 3], 0),
4209 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
4212 assert(stride
% type_size
== 0);
4215 index
= ctx
->i32zero
;
4217 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, stride
/ type_size
, 0), "");
4219 list
= ac_build_gep0(&ctx
->ac
, list
, LLVMConstInt(ctx
->i32
, offset
, 0));
4220 list
= LLVMBuildPointerCast(builder
, list
, const_array(type
, 0), "");
4222 return ac_build_indexed_load_const(&ctx
->ac
, list
, index
);
4225 static void set_tex_fetch_args(struct nir_to_llvm_context
*ctx
,
4226 struct ac_image_args
*args
,
4227 const nir_tex_instr
*instr
,
4229 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
4230 LLVMValueRef
*param
, unsigned count
,
4233 unsigned is_rect
= 0;
4234 bool da
= instr
->is_array
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
4236 if (op
== nir_texop_lod
)
4238 /* Pad to power of two vector */
4239 while (count
< util_next_power_of_two(count
))
4240 param
[count
++] = LLVMGetUndef(ctx
->i32
);
4243 args
->addr
= ac_build_gather_values(&ctx
->ac
, param
, count
);
4245 args
->addr
= param
[0];
4247 args
->resource
= res_ptr
;
4248 args
->sampler
= samp_ptr
;
4250 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
&& op
== nir_texop_txf
) {
4251 args
->addr
= param
[0];
4255 args
->dmask
= dmask
;
4256 args
->unorm
= is_rect
;
4260 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4263 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4264 * filtering manually. The driver sets img7 to a mask clearing
4265 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4266 * s_and_b32 samp0, samp0, img7
4269 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4271 static LLVMValueRef
sici_fix_sampler_aniso(struct nir_to_llvm_context
*ctx
,
4272 LLVMValueRef res
, LLVMValueRef samp
)
4274 LLVMBuilderRef builder
= ctx
->builder
;
4275 LLVMValueRef img7
, samp0
;
4277 if (ctx
->options
->chip_class
>= VI
)
4280 img7
= LLVMBuildExtractElement(builder
, res
,
4281 LLVMConstInt(ctx
->i32
, 7, 0), "");
4282 samp0
= LLVMBuildExtractElement(builder
, samp
,
4283 LLVMConstInt(ctx
->i32
, 0, 0), "");
4284 samp0
= LLVMBuildAnd(builder
, samp0
, img7
, "");
4285 return LLVMBuildInsertElement(builder
, samp
, samp0
,
4286 LLVMConstInt(ctx
->i32
, 0, 0), "");
4289 static void tex_fetch_ptrs(struct nir_to_llvm_context
*ctx
,
4290 nir_tex_instr
*instr
,
4291 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
4292 LLVMValueRef
*fmask_ptr
)
4294 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4295 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, DESC_BUFFER
);
4297 *res_ptr
= get_sampler_desc(ctx
, instr
->texture
, DESC_IMAGE
);
4300 *samp_ptr
= get_sampler_desc(ctx
, instr
->sampler
, DESC_SAMPLER
);
4302 *samp_ptr
= get_sampler_desc(ctx
, instr
->texture
, DESC_SAMPLER
);
4303 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
)
4304 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
4306 if (fmask_ptr
&& !instr
->sampler
&& (instr
->op
== nir_texop_txf_ms
||
4307 instr
->op
== nir_texop_samples_identical
))
4308 *fmask_ptr
= get_sampler_desc(ctx
, instr
->texture
, DESC_FMASK
);
4311 static LLVMValueRef
apply_round_slice(struct nir_to_llvm_context
*ctx
,
4314 coord
= to_float(&ctx
->ac
, coord
);
4315 coord
= ac_build_intrinsic(&ctx
->ac
, "llvm.rint.f32", ctx
->f32
, &coord
, 1, 0);
4316 coord
= to_integer(&ctx
->ac
, coord
);
4320 static void visit_tex(struct nir_to_llvm_context
*ctx
, nir_tex_instr
*instr
)
4322 LLVMValueRef result
= NULL
;
4323 struct ac_image_args args
= { 0 };
4324 unsigned dmask
= 0xf;
4325 LLVMValueRef address
[16];
4326 LLVMValueRef coords
[5];
4327 LLVMValueRef coord
= NULL
, lod
= NULL
, comparator
= NULL
;
4328 LLVMValueRef bias
= NULL
, offsets
= NULL
;
4329 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
, sample_index
= NULL
;
4330 LLVMValueRef ddx
= NULL
, ddy
= NULL
;
4331 LLVMValueRef derivs
[6];
4332 unsigned chan
, count
= 0;
4333 unsigned const_src
= 0, num_deriv_comp
= 0;
4334 bool lod_is_zero
= false;
4335 tex_fetch_ptrs(ctx
, instr
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
4337 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4338 switch (instr
->src
[i
].src_type
) {
4339 case nir_tex_src_coord
:
4340 coord
= get_src(ctx
->nir
, instr
->src
[i
].src
);
4342 case nir_tex_src_projector
:
4344 case nir_tex_src_comparator
:
4345 comparator
= get_src(ctx
->nir
, instr
->src
[i
].src
);
4347 case nir_tex_src_offset
:
4348 offsets
= get_src(ctx
->nir
, instr
->src
[i
].src
);
4351 case nir_tex_src_bias
:
4352 bias
= get_src(ctx
->nir
, instr
->src
[i
].src
);
4354 case nir_tex_src_lod
: {
4355 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
4357 if (val
&& val
->i32
[0] == 0)
4359 lod
= get_src(ctx
->nir
, instr
->src
[i
].src
);
4362 case nir_tex_src_ms_index
:
4363 sample_index
= get_src(ctx
->nir
, instr
->src
[i
].src
);
4365 case nir_tex_src_ms_mcs
:
4367 case nir_tex_src_ddx
:
4368 ddx
= get_src(ctx
->nir
, instr
->src
[i
].src
);
4369 num_deriv_comp
= instr
->src
[i
].src
.ssa
->num_components
;
4371 case nir_tex_src_ddy
:
4372 ddy
= get_src(ctx
->nir
, instr
->src
[i
].src
);
4374 case nir_tex_src_texture_offset
:
4375 case nir_tex_src_sampler_offset
:
4376 case nir_tex_src_plane
:
4382 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
4383 result
= get_buffer_size(ctx
, res_ptr
, true);
4387 if (instr
->op
== nir_texop_texture_samples
) {
4388 LLVMValueRef res
, samples
, is_msaa
;
4389 res
= LLVMBuildBitCast(ctx
->builder
, res_ptr
, ctx
->v8i32
, "");
4390 samples
= LLVMBuildExtractElement(ctx
->builder
, res
,
4391 LLVMConstInt(ctx
->i32
, 3, false), "");
4392 is_msaa
= LLVMBuildLShr(ctx
->builder
, samples
,
4393 LLVMConstInt(ctx
->i32
, 28, false), "");
4394 is_msaa
= LLVMBuildAnd(ctx
->builder
, is_msaa
,
4395 LLVMConstInt(ctx
->i32
, 0xe, false), "");
4396 is_msaa
= LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
, is_msaa
,
4397 LLVMConstInt(ctx
->i32
, 0xe, false), "");
4399 samples
= LLVMBuildLShr(ctx
->builder
, samples
,
4400 LLVMConstInt(ctx
->i32
, 16, false), "");
4401 samples
= LLVMBuildAnd(ctx
->builder
, samples
,
4402 LLVMConstInt(ctx
->i32
, 0xf, false), "");
4403 samples
= LLVMBuildShl(ctx
->builder
, ctx
->i32one
,
4405 samples
= LLVMBuildSelect(ctx
->builder
, is_msaa
, samples
,
4412 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4413 coords
[chan
] = llvm_extract_elem(ctx
, coord
, chan
);
4415 if (offsets
&& instr
->op
!= nir_texop_txf
) {
4416 LLVMValueRef offset
[3], pack
;
4417 for (chan
= 0; chan
< 3; ++chan
)
4418 offset
[chan
] = ctx
->i32zero
;
4421 for (chan
= 0; chan
< get_llvm_num_components(offsets
); chan
++) {
4422 offset
[chan
] = llvm_extract_elem(ctx
, offsets
, chan
);
4423 offset
[chan
] = LLVMBuildAnd(ctx
->builder
, offset
[chan
],
4424 LLVMConstInt(ctx
->i32
, 0x3f, false), "");
4426 offset
[chan
] = LLVMBuildShl(ctx
->builder
, offset
[chan
],
4427 LLVMConstInt(ctx
->i32
, chan
* 8, false), "");
4429 pack
= LLVMBuildOr(ctx
->builder
, offset
[0], offset
[1], "");
4430 pack
= LLVMBuildOr(ctx
->builder
, pack
, offset
[2], "");
4431 address
[count
++] = pack
;
4434 /* pack LOD bias value */
4435 if (instr
->op
== nir_texop_txb
&& bias
) {
4436 address
[count
++] = bias
;
4439 /* Pack depth comparison value */
4440 if (instr
->is_shadow
&& comparator
) {
4441 address
[count
++] = llvm_extract_elem(ctx
, comparator
, 0);
4444 /* pack derivatives */
4446 switch (instr
->sampler_dim
) {
4447 case GLSL_SAMPLER_DIM_3D
:
4448 case GLSL_SAMPLER_DIM_CUBE
:
4451 case GLSL_SAMPLER_DIM_2D
:
4455 case GLSL_SAMPLER_DIM_1D
:
4460 for (unsigned i
= 0; i
< num_deriv_comp
; i
++) {
4461 derivs
[i
] = to_float(&ctx
->ac
, llvm_extract_elem(ctx
, ddx
, i
));
4462 derivs
[num_deriv_comp
+ i
] = to_float(&ctx
->ac
, llvm_extract_elem(ctx
, ddy
, i
));
4466 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& coord
) {
4467 if (instr
->is_array
&& instr
->op
!= nir_texop_lod
)
4468 coords
[3] = apply_round_slice(ctx
, coords
[3]);
4469 for (chan
= 0; chan
< instr
->coord_components
; chan
++)
4470 coords
[chan
] = to_float(&ctx
->ac
, coords
[chan
]);
4471 if (instr
->coord_components
== 3)
4472 coords
[3] = LLVMGetUndef(ctx
->f32
);
4473 ac_prepare_cube_coords(&ctx
->ac
,
4474 instr
->op
== nir_texop_txd
, instr
->is_array
,
4481 for (unsigned i
= 0; i
< num_deriv_comp
* 2; i
++)
4482 address
[count
++] = derivs
[i
];
4485 /* Pack texture coordinates */
4487 address
[count
++] = coords
[0];
4488 if (instr
->coord_components
> 1) {
4489 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& instr
->is_array
&& instr
->op
!= nir_texop_txf
) {
4490 coords
[1] = apply_round_slice(ctx
, coords
[1]);
4492 address
[count
++] = coords
[1];
4494 if (instr
->coord_components
> 2) {
4495 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4496 if (instr
->sampler_dim
!= GLSL_SAMPLER_DIM_3D
&&
4497 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_CUBE
&&
4498 instr
->op
!= nir_texop_txf
) {
4499 coords
[2] = apply_round_slice(ctx
, coords
[2]);
4501 address
[count
++] = coords
[2];
4506 if (lod
&& ((instr
->op
== nir_texop_txl
&& !lod_is_zero
) ||
4507 instr
->op
== nir_texop_txf
)) {
4508 address
[count
++] = lod
;
4509 } else if (instr
->op
== nir_texop_txf_ms
&& sample_index
) {
4510 address
[count
++] = sample_index
;
4511 } else if(instr
->op
== nir_texop_txs
) {
4514 address
[count
++] = lod
;
4516 address
[count
++] = ctx
->i32zero
;
4519 for (chan
= 0; chan
< count
; chan
++) {
4520 address
[chan
] = LLVMBuildBitCast(ctx
->builder
,
4521 address
[chan
], ctx
->i32
, "");
4524 if (instr
->op
== nir_texop_samples_identical
) {
4525 LLVMValueRef txf_address
[4];
4526 struct ac_image_args txf_args
= { 0 };
4527 unsigned txf_count
= count
;
4528 memcpy(txf_address
, address
, sizeof(txf_address
));
4530 if (!instr
->is_array
)
4531 txf_address
[2] = ctx
->i32zero
;
4532 txf_address
[3] = ctx
->i32zero
;
4534 set_tex_fetch_args(ctx
, &txf_args
, instr
, nir_texop_txf
,
4536 txf_address
, txf_count
, 0xf);
4538 result
= build_tex_intrinsic(ctx
, instr
, false, &txf_args
);
4540 result
= LLVMBuildExtractElement(ctx
->builder
, result
, ctx
->i32zero
, "");
4541 result
= emit_int_cmp(&ctx
->ac
, LLVMIntEQ
, result
, ctx
->i32zero
);
4545 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
&&
4546 instr
->op
!= nir_texop_txs
) {
4547 unsigned sample_chan
= instr
->is_array
? 3 : 2;
4548 address
[sample_chan
] = adjust_sample_index_using_fmask(ctx
,
4551 instr
->is_array
? address
[2] : NULL
,
4552 address
[sample_chan
],
4556 if (offsets
&& instr
->op
== nir_texop_txf
) {
4557 nir_const_value
*const_offset
=
4558 nir_src_as_const_value(instr
->src
[const_src
].src
);
4559 int num_offsets
= instr
->src
[const_src
].src
.ssa
->num_components
;
4560 assert(const_offset
);
4561 num_offsets
= MIN2(num_offsets
, instr
->coord_components
);
4562 if (num_offsets
> 2)
4563 address
[2] = LLVMBuildAdd(ctx
->builder
,
4564 address
[2], LLVMConstInt(ctx
->i32
, const_offset
->i32
[2], false), "");
4565 if (num_offsets
> 1)
4566 address
[1] = LLVMBuildAdd(ctx
->builder
,
4567 address
[1], LLVMConstInt(ctx
->i32
, const_offset
->i32
[1], false), "");
4568 address
[0] = LLVMBuildAdd(ctx
->builder
,
4569 address
[0], LLVMConstInt(ctx
->i32
, const_offset
->i32
[0], false), "");
4573 /* TODO TG4 support */
4574 if (instr
->op
== nir_texop_tg4
) {
4575 if (instr
->is_shadow
)
4578 dmask
= 1 << instr
->component
;
4580 set_tex_fetch_args(ctx
, &args
, instr
, instr
->op
,
4581 res_ptr
, samp_ptr
, address
, count
, dmask
);
4583 result
= build_tex_intrinsic(ctx
, instr
, lod_is_zero
, &args
);
4585 if (instr
->op
== nir_texop_query_levels
)
4586 result
= LLVMBuildExtractElement(ctx
->builder
, result
, LLVMConstInt(ctx
->i32
, 3, false), "");
4587 else if (instr
->is_shadow
&& instr
->op
!= nir_texop_txs
&& instr
->op
!= nir_texop_lod
&& instr
->op
!= nir_texop_tg4
)
4588 result
= LLVMBuildExtractElement(ctx
->builder
, result
, ctx
->i32zero
, "");
4589 else if (instr
->op
== nir_texop_txs
&&
4590 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
4592 LLVMValueRef two
= LLVMConstInt(ctx
->i32
, 2, false);
4593 LLVMValueRef six
= LLVMConstInt(ctx
->i32
, 6, false);
4594 LLVMValueRef z
= LLVMBuildExtractElement(ctx
->builder
, result
, two
, "");
4595 z
= LLVMBuildSDiv(ctx
->builder
, z
, six
, "");
4596 result
= LLVMBuildInsertElement(ctx
->builder
, result
, z
, two
, "");
4597 } else if (instr
->dest
.ssa
.num_components
!= 4)
4598 result
= trim_vector(ctx
, result
, instr
->dest
.ssa
.num_components
);
4602 assert(instr
->dest
.is_ssa
);
4603 result
= to_integer(&ctx
->ac
, result
);
4604 _mesa_hash_table_insert(ctx
->nir
->defs
, &instr
->dest
.ssa
, result
);
4609 static void visit_phi(struct ac_nir_context
*ctx
, nir_phi_instr
*instr
)
4611 LLVMTypeRef type
= get_def_type(ctx
, &instr
->dest
.ssa
);
4612 LLVMValueRef result
= LLVMBuildPhi(ctx
->ac
.builder
, type
, "");
4614 _mesa_hash_table_insert(ctx
->defs
, &instr
->dest
.ssa
, result
);
4615 _mesa_hash_table_insert(ctx
->phis
, instr
, result
);
4618 static void visit_post_phi(struct ac_nir_context
*ctx
,
4619 nir_phi_instr
*instr
,
4620 LLVMValueRef llvm_phi
)
4622 nir_foreach_phi_src(src
, instr
) {
4623 LLVMBasicBlockRef block
= get_block(ctx
, src
->pred
);
4624 LLVMValueRef llvm_src
= get_src(ctx
, src
->src
);
4626 LLVMAddIncoming(llvm_phi
, &llvm_src
, &block
, 1);
4630 static void phi_post_pass(struct ac_nir_context
*ctx
)
4632 struct hash_entry
*entry
;
4633 hash_table_foreach(ctx
->phis
, entry
) {
4634 visit_post_phi(ctx
, (nir_phi_instr
*)entry
->key
,
4635 (LLVMValueRef
)entry
->data
);
4640 static void visit_ssa_undef(struct ac_nir_context
*ctx
,
4641 const nir_ssa_undef_instr
*instr
)
4643 unsigned num_components
= instr
->def
.num_components
;
4646 if (num_components
== 1)
4647 undef
= LLVMGetUndef(ctx
->ac
.i32
);
4649 undef
= LLVMGetUndef(LLVMVectorType(ctx
->ac
.i32
, num_components
));
4651 _mesa_hash_table_insert(ctx
->defs
, &instr
->def
, undef
);
4654 static void visit_jump(struct ac_nir_context
*ctx
,
4655 const nir_jump_instr
*instr
)
4657 switch (instr
->type
) {
4658 case nir_jump_break
:
4659 LLVMBuildBr(ctx
->ac
.builder
, ctx
->break_block
);
4660 LLVMClearInsertionPosition(ctx
->ac
.builder
);
4662 case nir_jump_continue
:
4663 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
4664 LLVMClearInsertionPosition(ctx
->ac
.builder
);
4667 fprintf(stderr
, "Unknown NIR jump instr: ");
4668 nir_print_instr(&instr
->instr
, stderr
);
4669 fprintf(stderr
, "\n");
4674 static void visit_cf_list(struct ac_nir_context
*ctx
,
4675 struct exec_list
*list
);
4677 static void visit_block(struct ac_nir_context
*ctx
, nir_block
*block
)
4679 LLVMBasicBlockRef llvm_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
4680 nir_foreach_instr(instr
, block
)
4682 switch (instr
->type
) {
4683 case nir_instr_type_alu
:
4684 visit_alu(ctx
, nir_instr_as_alu(instr
));
4686 case nir_instr_type_load_const
:
4687 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
4689 case nir_instr_type_intrinsic
:
4690 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
4692 case nir_instr_type_tex
:
4693 visit_tex(ctx
->nctx
, nir_instr_as_tex(instr
));
4695 case nir_instr_type_phi
:
4696 visit_phi(ctx
, nir_instr_as_phi(instr
));
4698 case nir_instr_type_ssa_undef
:
4699 visit_ssa_undef(ctx
, nir_instr_as_ssa_undef(instr
));
4701 case nir_instr_type_jump
:
4702 visit_jump(ctx
, nir_instr_as_jump(instr
));
4705 fprintf(stderr
, "Unknown NIR instr type: ");
4706 nir_print_instr(instr
, stderr
);
4707 fprintf(stderr
, "\n");
4712 _mesa_hash_table_insert(ctx
->defs
, block
, llvm_block
);
4715 static void visit_if(struct ac_nir_context
*ctx
, nir_if
*if_stmt
)
4717 LLVMValueRef value
= get_src(ctx
, if_stmt
->condition
);
4719 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
4720 LLVMBasicBlockRef merge_block
=
4721 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
4722 LLVMBasicBlockRef if_block
=
4723 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
4724 LLVMBasicBlockRef else_block
= merge_block
;
4725 if (!exec_list_is_empty(&if_stmt
->else_list
))
4726 else_block
= LLVMAppendBasicBlockInContext(
4727 ctx
->ac
.context
, fn
, "");
4729 LLVMValueRef cond
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
, value
,
4730 LLVMConstInt(ctx
->ac
.i32
, 0, false), "");
4731 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, if_block
, else_block
);
4733 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, if_block
);
4734 visit_cf_list(ctx
, &if_stmt
->then_list
);
4735 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
4736 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
4738 if (!exec_list_is_empty(&if_stmt
->else_list
)) {
4739 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, else_block
);
4740 visit_cf_list(ctx
, &if_stmt
->else_list
);
4741 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
4742 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
4745 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
4748 static void visit_loop(struct ac_nir_context
*ctx
, nir_loop
*loop
)
4750 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
4751 LLVMBasicBlockRef continue_parent
= ctx
->continue_block
;
4752 LLVMBasicBlockRef break_parent
= ctx
->break_block
;
4754 ctx
->continue_block
=
4755 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
4757 LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
4759 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
4760 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->continue_block
);
4761 visit_cf_list(ctx
, &loop
->body
);
4763 if (LLVMGetInsertBlock(ctx
->ac
.builder
))
4764 LLVMBuildBr(ctx
->ac
.builder
, ctx
->continue_block
);
4765 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ctx
->break_block
);
4767 ctx
->continue_block
= continue_parent
;
4768 ctx
->break_block
= break_parent
;
4771 static void visit_cf_list(struct ac_nir_context
*ctx
,
4772 struct exec_list
*list
)
4774 foreach_list_typed(nir_cf_node
, node
, node
, list
)
4776 switch (node
->type
) {
4777 case nir_cf_node_block
:
4778 visit_block(ctx
, nir_cf_node_as_block(node
));
4781 case nir_cf_node_if
:
4782 visit_if(ctx
, nir_cf_node_as_if(node
));
4785 case nir_cf_node_loop
:
4786 visit_loop(ctx
, nir_cf_node_as_loop(node
));
4796 handle_vs_input_decl(struct nir_to_llvm_context
*ctx
,
4797 struct nir_variable
*variable
)
4799 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
4800 LLVMValueRef t_offset
;
4801 LLVMValueRef t_list
;
4803 LLVMValueRef buffer_index
;
4804 int index
= variable
->data
.location
- VERT_ATTRIB_GENERIC0
;
4805 int idx
= variable
->data
.location
;
4806 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
4808 variable
->data
.driver_location
= idx
* 4;
4810 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << index
)) {
4811 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.instance_id
,
4812 ctx
->abi
.start_instance
, "");
4813 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(3,
4814 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
4816 buffer_index
= LLVMBuildAdd(ctx
->builder
, ctx
->abi
.vertex_id
,
4817 ctx
->abi
.base_vertex
, "");
4819 for (unsigned i
= 0; i
< attrib_count
; ++i
, ++idx
) {
4820 t_offset
= LLVMConstInt(ctx
->i32
, index
+ i
, false);
4822 t_list
= ac_build_indexed_load_const(&ctx
->ac
, t_list_ptr
, t_offset
);
4824 input
= ac_build_buffer_load_format(&ctx
->ac
, t_list
,
4826 LLVMConstInt(ctx
->i32
, 0, false),
4829 for (unsigned chan
= 0; chan
< 4; chan
++) {
4830 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->i32
, chan
, false);
4831 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
, chan
)] =
4832 to_integer(&ctx
->ac
, LLVMBuildExtractElement(ctx
->builder
,
4833 input
, llvm_chan
, ""));
4838 static void interp_fs_input(struct nir_to_llvm_context
*ctx
,
4840 LLVMValueRef interp_param
,
4841 LLVMValueRef prim_mask
,
4842 LLVMValueRef result
[4])
4844 LLVMValueRef attr_number
;
4847 bool interp
= interp_param
!= NULL
;
4849 attr_number
= LLVMConstInt(ctx
->i32
, attr
, false);
4851 /* fs.constant returns the param from the middle vertex, so it's not
4852 * really useful for flat shading. It's meant to be used for custom
4853 * interpolation (but the intrinsic can't fetch from the other two
4856 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4857 * to do the right thing. The only reason we use fs.constant is that
4858 * fs.interp cannot be used on integers, because they can be equal
4862 interp_param
= LLVMBuildBitCast(ctx
->builder
, interp_param
,
4863 LLVMVectorType(ctx
->f32
, 2), "");
4865 i
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
4867 j
= LLVMBuildExtractElement(ctx
->builder
, interp_param
,
4871 for (chan
= 0; chan
< 4; chan
++) {
4872 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->i32
, chan
, false);
4875 result
[chan
] = ac_build_fs_interp(&ctx
->ac
,
4880 result
[chan
] = ac_build_fs_interp_mov(&ctx
->ac
,
4881 LLVMConstInt(ctx
->i32
, 2, false),
4890 handle_fs_input_decl(struct nir_to_llvm_context
*ctx
,
4891 struct nir_variable
*variable
)
4893 int idx
= variable
->data
.location
;
4894 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
4895 LLVMValueRef interp
;
4897 variable
->data
.driver_location
= idx
* 4;
4898 ctx
->input_mask
|= ((1ull << attrib_count
) - 1) << variable
->data
.location
;
4900 if (glsl_get_base_type(glsl_without_array(variable
->type
)) == GLSL_TYPE_FLOAT
) {
4901 unsigned interp_type
;
4902 if (variable
->data
.sample
) {
4903 interp_type
= INTERP_SAMPLE
;
4904 ctx
->shader_info
->fs
.force_persample
= true;
4905 } else if (variable
->data
.centroid
)
4906 interp_type
= INTERP_CENTROID
;
4908 interp_type
= INTERP_CENTER
;
4910 interp
= lookup_interp_param(ctx
, variable
->data
.interpolation
, interp_type
);
4914 for (unsigned i
= 0; i
< attrib_count
; ++i
)
4915 ctx
->inputs
[radeon_llvm_reg_index_soa(idx
+ i
, 0)] = interp
;
4920 handle_shader_input_decl(struct nir_to_llvm_context
*ctx
,
4921 struct nir_variable
*variable
)
4923 switch (ctx
->stage
) {
4924 case MESA_SHADER_VERTEX
:
4925 handle_vs_input_decl(ctx
, variable
);
4927 case MESA_SHADER_FRAGMENT
:
4928 handle_fs_input_decl(ctx
, variable
);
4937 handle_fs_inputs_pre(struct nir_to_llvm_context
*ctx
,
4938 struct nir_shader
*nir
)
4941 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_INPUTS
; ++i
) {
4942 LLVMValueRef interp_param
;
4943 LLVMValueRef
*inputs
= ctx
->inputs
+radeon_llvm_reg_index_soa(i
, 0);
4945 if (!(ctx
->input_mask
& (1ull << i
)))
4948 if (i
>= VARYING_SLOT_VAR0
|| i
== VARYING_SLOT_PNTC
||
4949 i
== VARYING_SLOT_PRIMITIVE_ID
|| i
== VARYING_SLOT_LAYER
) {
4950 interp_param
= *inputs
;
4951 interp_fs_input(ctx
, index
, interp_param
, ctx
->prim_mask
,
4955 ctx
->shader_info
->fs
.flat_shaded_mask
|= 1u << index
;
4957 } else if (i
== VARYING_SLOT_POS
) {
4958 for(int i
= 0; i
< 3; ++i
)
4959 inputs
[i
] = ctx
->frag_pos
[i
];
4961 inputs
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->f32one
, ctx
->frag_pos
[3]);
4964 ctx
->shader_info
->fs
.num_interp
= index
;
4965 if (ctx
->input_mask
& (1 << VARYING_SLOT_PNTC
))
4966 ctx
->shader_info
->fs
.has_pcoord
= true;
4967 if (ctx
->input_mask
& (1 << VARYING_SLOT_PRIMITIVE_ID
))
4968 ctx
->shader_info
->fs
.prim_id_input
= true;
4969 if (ctx
->input_mask
& (1 << VARYING_SLOT_LAYER
))
4970 ctx
->shader_info
->fs
.layer_input
= true;
4971 ctx
->shader_info
->fs
.input_mask
= ctx
->input_mask
>> VARYING_SLOT_VAR0
;
4975 ac_build_alloca(struct ac_llvm_context
*ac
,
4979 LLVMBuilderRef builder
= ac
->builder
;
4980 LLVMBasicBlockRef current_block
= LLVMGetInsertBlock(builder
);
4981 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
4982 LLVMBasicBlockRef first_block
= LLVMGetEntryBasicBlock(function
);
4983 LLVMValueRef first_instr
= LLVMGetFirstInstruction(first_block
);
4984 LLVMBuilderRef first_builder
= LLVMCreateBuilderInContext(ac
->context
);
4988 LLVMPositionBuilderBefore(first_builder
, first_instr
);
4990 LLVMPositionBuilderAtEnd(first_builder
, first_block
);
4993 res
= LLVMBuildAlloca(first_builder
, type
, name
);
4994 LLVMBuildStore(builder
, LLVMConstNull(type
), res
);
4996 LLVMDisposeBuilder(first_builder
);
5001 static LLVMValueRef
si_build_alloca_undef(struct ac_llvm_context
*ac
,
5005 LLVMValueRef ptr
= ac_build_alloca(ac
, type
, name
);
5006 LLVMBuildStore(ac
->builder
, LLVMGetUndef(type
), ptr
);
5011 scan_shader_output_decl(struct nir_to_llvm_context
*ctx
,
5012 struct nir_variable
*variable
)
5014 int idx
= variable
->data
.location
+ variable
->data
.index
;
5015 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5016 uint64_t mask_attribs
;
5018 variable
->data
.driver_location
= idx
* 4;
5020 /* tess ctrl has it's own load/store paths for outputs */
5021 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5024 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
5025 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5026 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5027 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5028 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5029 int length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5030 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
5031 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << ctx
->num_output_clips
) - 1;
5032 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << ctx
->num_output_culls
) - 1;
5034 if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
5035 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << ctx
->num_output_clips
) - 1;
5036 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << ctx
->num_output_culls
) - 1;
5043 mask_attribs
= 1ull << idx
;
5047 ctx
->output_mask
|= mask_attribs
;
5051 handle_shader_output_decl(struct ac_nir_context
*ctx
,
5052 struct nir_shader
*nir
,
5053 struct nir_variable
*variable
)
5055 unsigned output_loc
= variable
->data
.driver_location
/ 4;
5056 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5058 /* tess ctrl has it's own load/store paths for outputs */
5059 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
5062 if (ctx
->stage
== MESA_SHADER_VERTEX
||
5063 ctx
->stage
== MESA_SHADER_TESS_EVAL
||
5064 ctx
->stage
== MESA_SHADER_GEOMETRY
) {
5065 int idx
= variable
->data
.location
+ variable
->data
.index
;
5066 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
5067 int length
= nir
->info
.clip_distance_array_size
+
5068 nir
->info
.cull_distance_array_size
;
5077 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
5078 for (unsigned chan
= 0; chan
< 4; chan
++) {
5079 ctx
->outputs
[radeon_llvm_reg_index_soa(output_loc
+ i
, chan
)] =
5080 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
5086 glsl_base_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5087 enum glsl_base_type type
)
5091 case GLSL_TYPE_UINT
:
5092 case GLSL_TYPE_BOOL
:
5093 case GLSL_TYPE_SUBROUTINE
:
5095 case GLSL_TYPE_FLOAT
: /* TODO handle mediump */
5097 case GLSL_TYPE_INT64
:
5098 case GLSL_TYPE_UINT64
:
5100 case GLSL_TYPE_DOUBLE
:
5103 unreachable("unknown GLSL type");
5108 glsl_to_llvm_type(struct nir_to_llvm_context
*ctx
,
5109 const struct glsl_type
*type
)
5111 if (glsl_type_is_scalar(type
)) {
5112 return glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
));
5115 if (glsl_type_is_vector(type
)) {
5116 return LLVMVectorType(
5117 glsl_base_to_llvm_type(ctx
, glsl_get_base_type(type
)),
5118 glsl_get_vector_elements(type
));
5121 if (glsl_type_is_matrix(type
)) {
5122 return LLVMArrayType(
5123 glsl_to_llvm_type(ctx
, glsl_get_column_type(type
)),
5124 glsl_get_matrix_columns(type
));
5127 if (glsl_type_is_array(type
)) {
5128 return LLVMArrayType(
5129 glsl_to_llvm_type(ctx
, glsl_get_array_element(type
)),
5130 glsl_get_length(type
));
5133 assert(glsl_type_is_struct(type
));
5135 LLVMTypeRef member_types
[glsl_get_length(type
)];
5137 for (unsigned i
= 0; i
< glsl_get_length(type
); i
++) {
5139 glsl_to_llvm_type(ctx
,
5140 glsl_get_struct_field(type
, i
));
5143 return LLVMStructTypeInContext(ctx
->context
, member_types
,
5144 glsl_get_length(type
), false);
5148 setup_locals(struct ac_nir_context
*ctx
,
5149 struct nir_function
*func
)
5152 ctx
->num_locals
= 0;
5153 nir_foreach_variable(variable
, &func
->impl
->locals
) {
5154 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
5155 variable
->data
.driver_location
= ctx
->num_locals
* 4;
5156 ctx
->num_locals
+= attrib_count
;
5158 ctx
->locals
= malloc(4 * ctx
->num_locals
* sizeof(LLVMValueRef
));
5162 for (i
= 0; i
< ctx
->num_locals
; i
++) {
5163 for (j
= 0; j
< 4; j
++) {
5164 ctx
->locals
[i
* 4 + j
] =
5165 si_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "temp");
5171 setup_shared(struct ac_nir_context
*ctx
,
5172 struct nir_shader
*nir
)
5174 nir_foreach_variable(variable
, &nir
->shared
) {
5175 LLVMValueRef shared
=
5176 LLVMAddGlobalInAddressSpace(
5177 ctx
->ac
.module
, glsl_to_llvm_type(ctx
->nctx
, variable
->type
),
5178 variable
->name
? variable
->name
: "",
5180 _mesa_hash_table_insert(ctx
->vars
, variable
, shared
);
5185 emit_float_saturate(struct ac_llvm_context
*ctx
, LLVMValueRef v
, float lo
, float hi
)
5187 v
= to_float(ctx
, v
);
5188 v
= emit_intrin_2f_param(ctx
, "llvm.maxnum.f32", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, lo
));
5189 return emit_intrin_2f_param(ctx
, "llvm.minnum.f32", ctx
->f32
, v
, LLVMConstReal(ctx
->f32
, hi
));
5193 static LLVMValueRef
emit_pack_int16(struct nir_to_llvm_context
*ctx
,
5194 LLVMValueRef src0
, LLVMValueRef src1
)
5196 LLVMValueRef const16
= LLVMConstInt(ctx
->i32
, 16, false);
5197 LLVMValueRef comp
[2];
5199 comp
[0] = LLVMBuildAnd(ctx
->builder
, src0
, LLVMConstInt(ctx
-> i32
, 65535, 0), "");
5200 comp
[1] = LLVMBuildAnd(ctx
->builder
, src1
, LLVMConstInt(ctx
-> i32
, 65535, 0), "");
5201 comp
[1] = LLVMBuildShl(ctx
->builder
, comp
[1], const16
, "");
5202 return LLVMBuildOr(ctx
->builder
, comp
[0], comp
[1], "");
5205 /* Initialize arguments for the shader export intrinsic */
5207 si_llvm_init_export_args(struct nir_to_llvm_context
*ctx
,
5208 LLVMValueRef
*values
,
5210 struct ac_export_args
*args
)
5212 /* Default is 0xf. Adjusted below depending on the format. */
5213 args
->enabled_channels
= 0xf;
5215 /* Specify whether the EXEC mask represents the valid mask */
5216 args
->valid_mask
= 0;
5218 /* Specify whether this is the last export */
5221 /* Specify the target we are exporting */
5222 args
->target
= target
;
5224 args
->compr
= false;
5225 args
->out
[0] = LLVMGetUndef(ctx
->f32
);
5226 args
->out
[1] = LLVMGetUndef(ctx
->f32
);
5227 args
->out
[2] = LLVMGetUndef(ctx
->f32
);
5228 args
->out
[3] = LLVMGetUndef(ctx
->f32
);
5233 if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& target
>= V_008DFC_SQ_EXP_MRT
) {
5234 LLVMValueRef val
[4];
5235 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
5236 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
5237 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
5239 switch(col_format
) {
5240 case V_028714_SPI_SHADER_ZERO
:
5241 args
->enabled_channels
= 0; /* writemask */
5242 args
->target
= V_008DFC_SQ_EXP_NULL
;
5245 case V_028714_SPI_SHADER_32_R
:
5246 args
->enabled_channels
= 1;
5247 args
->out
[0] = values
[0];
5250 case V_028714_SPI_SHADER_32_GR
:
5251 args
->enabled_channels
= 0x3;
5252 args
->out
[0] = values
[0];
5253 args
->out
[1] = values
[1];
5256 case V_028714_SPI_SHADER_32_AR
:
5257 args
->enabled_channels
= 0x9;
5258 args
->out
[0] = values
[0];
5259 args
->out
[3] = values
[3];
5262 case V_028714_SPI_SHADER_FP16_ABGR
:
5265 for (unsigned chan
= 0; chan
< 2; chan
++) {
5266 LLVMValueRef pack_args
[2] = {
5268 values
[2 * chan
+ 1]
5270 LLVMValueRef packed
;
5272 packed
= ac_build_cvt_pkrtz_f16(&ctx
->ac
, pack_args
);
5273 args
->out
[chan
] = packed
;
5277 case V_028714_SPI_SHADER_UNORM16_ABGR
:
5278 for (unsigned chan
= 0; chan
< 4; chan
++) {
5279 val
[chan
] = ac_build_clamp(&ctx
->ac
, values
[chan
]);
5280 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5281 LLVMConstReal(ctx
->f32
, 65535), "");
5282 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5283 LLVMConstReal(ctx
->f32
, 0.5), "");
5284 val
[chan
] = LLVMBuildFPToUI(ctx
->builder
, val
[chan
],
5289 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5290 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5293 case V_028714_SPI_SHADER_SNORM16_ABGR
:
5294 for (unsigned chan
= 0; chan
< 4; chan
++) {
5295 val
[chan
] = emit_float_saturate(&ctx
->ac
, values
[chan
], -1, 1);
5296 val
[chan
] = LLVMBuildFMul(ctx
->builder
, val
[chan
],
5297 LLVMConstReal(ctx
->f32
, 32767), "");
5299 /* If positive, add 0.5, else add -0.5. */
5300 val
[chan
] = LLVMBuildFAdd(ctx
->builder
, val
[chan
],
5301 LLVMBuildSelect(ctx
->builder
,
5302 LLVMBuildFCmp(ctx
->builder
, LLVMRealOGE
,
5303 val
[chan
], ctx
->f32zero
, ""),
5304 LLVMConstReal(ctx
->f32
, 0.5),
5305 LLVMConstReal(ctx
->f32
, -0.5), ""), "");
5306 val
[chan
] = LLVMBuildFPToSI(ctx
->builder
, val
[chan
], ctx
->i32
, "");
5310 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5311 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5314 case V_028714_SPI_SHADER_UINT16_ABGR
: {
5315 LLVMValueRef max
= LLVMConstInt(ctx
->i32
, is_int8
? 255 : 65535, 0);
5317 for (unsigned chan
= 0; chan
< 4; chan
++) {
5318 val
[chan
] = to_integer(&ctx
->ac
, values
[chan
]);
5319 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntULT
, val
[chan
], max
);
5323 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5324 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5328 case V_028714_SPI_SHADER_SINT16_ABGR
: {
5329 LLVMValueRef max
= LLVMConstInt(ctx
->i32
, is_int8
? 127 : 32767, 0);
5330 LLVMValueRef min
= LLVMConstInt(ctx
->i32
, is_int8
? -128 : -32768, 0);
5333 for (unsigned chan
= 0; chan
< 4; chan
++) {
5334 val
[chan
] = to_integer(&ctx
->ac
, values
[chan
]);
5335 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSLT
, val
[chan
], max
);
5336 val
[chan
] = emit_minmax_int(&ctx
->ac
, LLVMIntSGT
, val
[chan
], min
);
5340 args
->out
[0] = emit_pack_int16(ctx
, val
[0], val
[1]);
5341 args
->out
[1] = emit_pack_int16(ctx
, val
[2], val
[3]);
5346 case V_028714_SPI_SHADER_32_ABGR
:
5347 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5351 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
5353 for (unsigned i
= 0; i
< 4; ++i
)
5354 args
->out
[i
] = to_float(&ctx
->ac
, args
->out
[i
]);
5358 handle_vs_outputs_post(struct nir_to_llvm_context
*ctx
,
5359 bool export_prim_id
,
5360 struct ac_vs_output_info
*outinfo
)
5362 uint32_t param_count
= 0;
5364 unsigned pos_idx
, num_pos_exports
= 0;
5365 struct ac_export_args args
, pos_args
[4] = {};
5366 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
5369 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
5370 sizeof(outinfo
->vs_output_param_offset
));
5372 if (ctx
->output_mask
& (1ull << VARYING_SLOT_CLIP_DIST0
)) {
5373 LLVMValueRef slots
[8];
5376 if (outinfo
->cull_dist_mask
)
5377 outinfo
->cull_dist_mask
<<= ctx
->num_output_clips
;
5379 i
= VARYING_SLOT_CLIP_DIST0
;
5380 for (j
= 0; j
< ctx
->num_output_clips
+ ctx
->num_output_culls
; j
++)
5381 slots
[j
] = to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5382 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5384 for (i
= ctx
->num_output_clips
+ ctx
->num_output_culls
; i
< 8; i
++)
5385 slots
[i
] = LLVMGetUndef(ctx
->f32
);
5387 if (ctx
->num_output_clips
+ ctx
->num_output_culls
> 4) {
5388 target
= V_008DFC_SQ_EXP_POS
+ 3;
5389 si_llvm_init_export_args(ctx
, &slots
[4], target
, &args
);
5390 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5391 &args
, sizeof(args
));
5394 target
= V_008DFC_SQ_EXP_POS
+ 2;
5395 si_llvm_init_export_args(ctx
, &slots
[0], target
, &args
);
5396 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5397 &args
, sizeof(args
));
5401 LLVMValueRef pos_values
[4] = {ctx
->f32zero
, ctx
->f32zero
, ctx
->f32zero
, ctx
->f32one
};
5402 if (ctx
->output_mask
& (1ull << VARYING_SLOT_POS
)) {
5403 for (unsigned j
= 0; j
< 4; j
++)
5404 pos_values
[j
] = LLVMBuildLoad(ctx
->builder
,
5405 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_POS
, j
)], "");
5407 si_llvm_init_export_args(ctx
, pos_values
, V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
5409 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
5410 outinfo
->writes_pointsize
= true;
5411 psize_value
= LLVMBuildLoad(ctx
->builder
,
5412 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ
, 0)], "");
5415 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
5416 outinfo
->writes_layer
= true;
5417 layer_value
= LLVMBuildLoad(ctx
->builder
,
5418 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)], "");
5421 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
5422 outinfo
->writes_viewport_index
= true;
5423 viewport_index_value
= LLVMBuildLoad(ctx
->builder
,
5424 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT
, 0)], "");
5427 uint32_t mask
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
5428 (outinfo
->writes_layer
== true ? 4 : 0) |
5429 (outinfo
->writes_viewport_index
== true ? 8 : 0));
5431 pos_args
[1].enabled_channels
= mask
;
5432 pos_args
[1].valid_mask
= 0;
5433 pos_args
[1].done
= 0;
5434 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
5435 pos_args
[1].compr
= 0;
5436 pos_args
[1].out
[0] = ctx
->f32zero
; /* X */
5437 pos_args
[1].out
[1] = ctx
->f32zero
; /* Y */
5438 pos_args
[1].out
[2] = ctx
->f32zero
; /* Z */
5439 pos_args
[1].out
[3] = ctx
->f32zero
; /* W */
5441 if (outinfo
->writes_pointsize
== true)
5442 pos_args
[1].out
[0] = psize_value
;
5443 if (outinfo
->writes_layer
== true)
5444 pos_args
[1].out
[2] = layer_value
;
5445 if (outinfo
->writes_viewport_index
== true)
5446 pos_args
[1].out
[3] = viewport_index_value
;
5448 for (i
= 0; i
< 4; i
++) {
5449 if (pos_args
[i
].out
[0])
5454 for (i
= 0; i
< 4; i
++) {
5455 if (!pos_args
[i
].out
[0])
5458 /* Specify the target we are exporting */
5459 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
5460 if (pos_idx
== num_pos_exports
)
5461 pos_args
[i
].done
= 1;
5462 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
5465 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5466 LLVMValueRef values
[4];
5467 if (!(ctx
->output_mask
& (1ull << i
)))
5470 for (unsigned j
= 0; j
< 4; j
++)
5471 values
[j
] = to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5472 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5474 if (i
== VARYING_SLOT_LAYER
) {
5475 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5476 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = param_count
;
5478 } else if (i
== VARYING_SLOT_PRIMITIVE_ID
) {
5479 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5480 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
5482 } else if (i
>= VARYING_SLOT_VAR0
) {
5483 outinfo
->export_mask
|= 1u << (i
- VARYING_SLOT_VAR0
);
5484 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5485 outinfo
->vs_output_param_offset
[i
] = param_count
;
5490 si_llvm_init_export_args(ctx
, values
, target
, &args
);
5492 if (target
>= V_008DFC_SQ_EXP_POS
&&
5493 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
5494 memcpy(&pos_args
[target
- V_008DFC_SQ_EXP_POS
],
5495 &args
, sizeof(args
));
5497 ac_build_export(&ctx
->ac
, &args
);
5501 if (export_prim_id
) {
5502 LLVMValueRef values
[4];
5503 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
5504 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
;
5507 values
[0] = ctx
->vs_prim_id
;
5508 ctx
->shader_info
->vs
.vgpr_comp_cnt
= MAX2(2,
5509 ctx
->shader_info
->vs
.vgpr_comp_cnt
);
5510 for (unsigned j
= 1; j
< 4; j
++)
5511 values
[j
] = ctx
->f32zero
;
5512 si_llvm_init_export_args(ctx
, values
, target
, &args
);
5513 ac_build_export(&ctx
->ac
, &args
);
5514 outinfo
->export_prim_id
= true;
5517 outinfo
->pos_exports
= num_pos_exports
;
5518 outinfo
->param_exports
= param_count
;
5522 handle_es_outputs_post(struct nir_to_llvm_context
*ctx
,
5523 struct ac_es_output_info
*outinfo
)
5526 uint64_t max_output_written
= 0;
5527 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5528 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
5532 if (!(ctx
->output_mask
& (1ull << i
)))
5535 if (i
== VARYING_SLOT_CLIP_DIST0
)
5536 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5538 param_index
= shader_io_get_unique_index(i
);
5540 max_output_written
= MAX2(param_index
+ (length
> 4), max_output_written
);
5542 for (j
= 0; j
< length
; j
++) {
5543 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], "");
5544 out_val
= LLVMBuildBitCast(ctx
->builder
, out_val
, ctx
->i32
, "");
5546 ac_build_buffer_store_dword(&ctx
->ac
,
5549 NULL
, ctx
->es2gs_offset
,
5550 (4 * param_index
+ j
) * 4,
5554 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
5558 handle_ls_outputs_post(struct nir_to_llvm_context
*ctx
)
5560 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
5561 LLVMValueRef vertex_dw_stride
= unpack_param(ctx
, ctx
->ls_out_layout
, 13, 8);
5562 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->builder
, vertex_id
,
5563 vertex_dw_stride
, "");
5565 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5566 LLVMValueRef
*out_ptr
= &ctx
->nir
->outputs
[i
* 4];
5569 if (!(ctx
->output_mask
& (1ull << i
)))
5572 if (i
== VARYING_SLOT_CLIP_DIST0
)
5573 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
5574 int param
= shader_io_get_unique_index(i
);
5575 mark_tess_output(ctx
, false, param
);
5577 mark_tess_output(ctx
, false, param
+ 1);
5578 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->builder
, base_dw_addr
,
5579 LLVMConstInt(ctx
->i32
, param
* 4, false),
5581 for (unsigned j
= 0; j
< length
; j
++) {
5582 lds_store(ctx
, dw_addr
,
5583 LLVMBuildLoad(ctx
->builder
, out_ptr
[j
], ""));
5584 dw_addr
= LLVMBuildAdd(ctx
->builder
, dw_addr
, ctx
->i32one
, "");
5589 struct ac_build_if_state
5591 struct nir_to_llvm_context
*ctx
;
5592 LLVMValueRef condition
;
5593 LLVMBasicBlockRef entry_block
;
5594 LLVMBasicBlockRef true_block
;
5595 LLVMBasicBlockRef false_block
;
5596 LLVMBasicBlockRef merge_block
;
5599 static LLVMBasicBlockRef
5600 ac_build_insert_new_block(struct nir_to_llvm_context
*ctx
, const char *name
)
5602 LLVMBasicBlockRef current_block
;
5603 LLVMBasicBlockRef next_block
;
5604 LLVMBasicBlockRef new_block
;
5606 /* get current basic block */
5607 current_block
= LLVMGetInsertBlock(ctx
->builder
);
5609 /* chqeck if there's another block after this one */
5610 next_block
= LLVMGetNextBasicBlock(current_block
);
5612 /* insert the new block before the next block */
5613 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
5616 /* append new block after current block */
5617 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
5618 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
5624 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
5625 struct nir_to_llvm_context
*ctx
,
5626 LLVMValueRef condition
)
5628 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->builder
);
5630 memset(ifthen
, 0, sizeof *ifthen
);
5632 ifthen
->condition
= condition
;
5633 ifthen
->entry_block
= block
;
5635 /* create endif/merge basic block for the phi functions */
5636 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
5638 /* create/insert true_block before merge_block */
5639 ifthen
->true_block
=
5640 LLVMInsertBasicBlockInContext(ctx
->context
,
5641 ifthen
->merge_block
,
5644 /* successive code goes into the true block */
5645 LLVMPositionBuilderAtEnd(ctx
->builder
, ifthen
->true_block
);
5649 * End a conditional.
5652 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
5654 LLVMBuilderRef builder
= ifthen
->ctx
->builder
;
5656 /* Insert branch to the merge block from current block */
5657 LLVMBuildBr(builder
, ifthen
->merge_block
);
5660 * Now patch in the various branch instructions.
5663 /* Insert the conditional branch instruction at the end of entry_block */
5664 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
5665 if (ifthen
->false_block
) {
5666 /* we have an else clause */
5667 LLVMBuildCondBr(builder
, ifthen
->condition
,
5668 ifthen
->true_block
, ifthen
->false_block
);
5671 /* no else clause */
5672 LLVMBuildCondBr(builder
, ifthen
->condition
,
5673 ifthen
->true_block
, ifthen
->merge_block
);
5676 /* Resume building code at end of the ifthen->merge_block */
5677 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
5681 write_tess_factors(struct nir_to_llvm_context
*ctx
)
5683 unsigned stride
, outer_comps
, inner_comps
;
5684 struct ac_build_if_state if_ctx
, inner_if_ctx
;
5685 LLVMValueRef invocation_id
= unpack_param(ctx
, ctx
->tcs_rel_ids
, 8, 5);
5686 LLVMValueRef rel_patch_id
= unpack_param(ctx
, ctx
->tcs_rel_ids
, 0, 8);
5687 unsigned tess_inner_index
, tess_outer_index
;
5688 LLVMValueRef lds_base
, lds_inner
, lds_outer
, byteoffset
, buffer
;
5689 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
5693 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
5713 ac_nir_build_if(&if_ctx
, ctx
,
5714 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
5715 invocation_id
, ctx
->i32zero
, ""));
5717 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
5718 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
5720 mark_tess_output(ctx
, true, tess_inner_index
);
5721 mark_tess_output(ctx
, true, tess_outer_index
);
5722 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
5723 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_base
,
5724 LLVMConstInt(ctx
->i32
, tess_inner_index
* 4, false), "");
5725 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_base
,
5726 LLVMConstInt(ctx
->i32
, tess_outer_index
* 4, false), "");
5728 for (i
= 0; i
< 4; i
++) {
5729 inner
[i
] = LLVMGetUndef(ctx
->i32
);
5730 outer
[i
] = LLVMGetUndef(ctx
->i32
);
5734 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
5735 outer
[0] = out
[1] = lds_load(ctx
, lds_outer
);
5736 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
5737 LLVMConstInt(ctx
->i32
, 1, false), "");
5738 outer
[1] = out
[0] = lds_load(ctx
, lds_outer
);
5740 for (i
= 0; i
< outer_comps
; i
++) {
5742 lds_load(ctx
, lds_outer
);
5743 lds_outer
= LLVMBuildAdd(ctx
->builder
, lds_outer
,
5744 LLVMConstInt(ctx
->i32
, 1, false), "");
5746 for (i
= 0; i
< inner_comps
; i
++) {
5747 inner
[i
] = out
[outer_comps
+i
] =
5748 lds_load(ctx
, lds_inner
);
5749 lds_inner
= LLVMBuildAdd(ctx
->builder
, lds_inner
,
5750 LLVMConstInt(ctx
->i32
, 1, false), "");
5754 /* Convert the outputs to vectors for stores. */
5755 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
5759 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
5762 buffer
= ctx
->hs_ring_tess_factor
;
5763 tf_base
= ctx
->tess_factor_offset
;
5764 byteoffset
= LLVMBuildMul(ctx
->builder
, rel_patch_id
,
5765 LLVMConstInt(ctx
->i32
, 4 * stride
, false), "");
5767 ac_nir_build_if(&inner_if_ctx
, ctx
,
5768 LLVMBuildICmp(ctx
->builder
, LLVMIntEQ
,
5769 rel_patch_id
, ctx
->i32zero
, ""));
5771 /* Store the dynamic HS control word. */
5772 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
5773 LLVMConstInt(ctx
->i32
, 0x80000000, false),
5774 1, ctx
->i32zero
, tf_base
,
5775 0, 1, 0, true, false);
5776 ac_nir_build_endif(&inner_if_ctx
);
5778 /* Store the tessellation factors. */
5779 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
5780 MIN2(stride
, 4), byteoffset
, tf_base
,
5781 4, 1, 0, true, false);
5783 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
5784 stride
- 4, byteoffset
, tf_base
,
5785 20, 1, 0, true, false);
5787 //TODO store to offchip for TES to read - only if TES reads them
5789 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
5790 LLVMValueRef tf_inner_offset
;
5791 unsigned param_outer
, param_inner
;
5793 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
5794 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
5795 LLVMConstInt(ctx
->i32
, param_outer
, 0));
5797 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
5798 util_next_power_of_two(outer_comps
));
5800 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
5801 outer_comps
, tf_outer_offset
,
5802 ctx
->oc_lds
, 0, 1, 0, true, false);
5804 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
5805 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
5806 LLVMConstInt(ctx
->i32
, param_inner
, 0));
5808 inner_vec
= inner_comps
== 1 ? inner
[0] :
5809 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
5810 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
5811 inner_comps
, tf_inner_offset
,
5812 ctx
->oc_lds
, 0, 1, 0, true, false);
5815 ac_nir_build_endif(&if_ctx
);
5819 handle_tcs_outputs_post(struct nir_to_llvm_context
*ctx
)
5821 write_tess_factors(ctx
);
5825 si_export_mrt_color(struct nir_to_llvm_context
*ctx
,
5826 LLVMValueRef
*color
, unsigned param
, bool is_last
,
5827 struct ac_export_args
*args
)
5830 si_llvm_init_export_args(ctx
, color
, param
,
5834 args
->valid_mask
= 1; /* whether the EXEC mask is valid */
5835 args
->done
= 1; /* DONE bit */
5836 } else if (!args
->enabled_channels
)
5837 return false; /* unnecessary NULL export */
5843 si_export_mrt_z(struct nir_to_llvm_context
*ctx
,
5844 LLVMValueRef depth
, LLVMValueRef stencil
,
5845 LLVMValueRef samplemask
)
5847 struct ac_export_args args
;
5849 args
.enabled_channels
= 0;
5850 args
.valid_mask
= 1;
5852 args
.target
= V_008DFC_SQ_EXP_MRTZ
;
5855 args
.out
[0] = LLVMGetUndef(ctx
->f32
); /* R, depth */
5856 args
.out
[1] = LLVMGetUndef(ctx
->f32
); /* G, stencil test val[0:7], stencil op val[8:15] */
5857 args
.out
[2] = LLVMGetUndef(ctx
->f32
); /* B, sample mask */
5858 args
.out
[3] = LLVMGetUndef(ctx
->f32
); /* A, alpha to mask */
5861 args
.out
[0] = depth
;
5862 args
.enabled_channels
|= 0x1;
5866 args
.out
[1] = stencil
;
5867 args
.enabled_channels
|= 0x2;
5871 args
.out
[2] = samplemask
;
5872 args
.enabled_channels
|= 0x4;
5875 /* SI (except OLAND and HAINAN) has a bug that it only looks
5876 * at the X writemask component. */
5877 if (ctx
->options
->chip_class
== SI
&&
5878 ctx
->options
->family
!= CHIP_OLAND
&&
5879 ctx
->options
->family
!= CHIP_HAINAN
)
5880 args
.enabled_channels
|= 0x1;
5882 ac_build_export(&ctx
->ac
, &args
);
5886 handle_fs_outputs_post(struct nir_to_llvm_context
*ctx
)
5889 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
5890 struct ac_export_args color_args
[8];
5892 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
5893 LLVMValueRef values
[4];
5895 if (!(ctx
->output_mask
& (1ull << i
)))
5898 if (i
== FRAG_RESULT_DEPTH
) {
5899 ctx
->shader_info
->fs
.writes_z
= true;
5900 depth
= to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5901 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
5902 } else if (i
== FRAG_RESULT_STENCIL
) {
5903 ctx
->shader_info
->fs
.writes_stencil
= true;
5904 stencil
= to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5905 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
5906 } else if (i
== FRAG_RESULT_SAMPLE_MASK
) {
5907 ctx
->shader_info
->fs
.writes_sample_mask
= true;
5908 samplemask
= to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5909 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, 0)], ""));
5912 for (unsigned j
= 0; j
< 4; j
++)
5913 values
[j
] = to_float(&ctx
->ac
, LLVMBuildLoad(ctx
->builder
,
5914 ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)], ""));
5916 if (!ctx
->shader_info
->fs
.writes_z
&& !ctx
->shader_info
->fs
.writes_stencil
&& !ctx
->shader_info
->fs
.writes_sample_mask
)
5917 last
= ctx
->output_mask
<= ((1ull << (i
+ 1)) - 1);
5919 bool ret
= si_export_mrt_color(ctx
, values
, V_008DFC_SQ_EXP_MRT
+ (i
- FRAG_RESULT_DATA0
), last
, &color_args
[index
]);
5925 for (unsigned i
= 0; i
< index
; i
++)
5926 ac_build_export(&ctx
->ac
, &color_args
[i
]);
5927 if (depth
|| stencil
|| samplemask
)
5928 si_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
5930 si_export_mrt_color(ctx
, NULL
, V_008DFC_SQ_EXP_NULL
, true, &color_args
[0]);
5931 ac_build_export(&ctx
->ac
, &color_args
[0]);
5934 ctx
->shader_info
->fs
.output_mask
= index
? ((1ull << index
) - 1) : 0;
5938 emit_gs_epilogue(struct nir_to_llvm_context
*ctx
)
5940 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
5944 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
5945 LLVMValueRef
*addrs
)
5947 struct nir_to_llvm_context
*ctx
= nir_to_llvm_context_from_abi(abi
);
5949 switch (ctx
->stage
) {
5950 case MESA_SHADER_VERTEX
:
5951 if (ctx
->options
->key
.vs
.as_ls
)
5952 handle_ls_outputs_post(ctx
);
5953 else if (ctx
->options
->key
.vs
.as_es
)
5954 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
5956 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs
.export_prim_id
,
5957 &ctx
->shader_info
->vs
.outinfo
);
5959 case MESA_SHADER_FRAGMENT
:
5960 handle_fs_outputs_post(ctx
);
5962 case MESA_SHADER_GEOMETRY
:
5963 emit_gs_epilogue(ctx
);
5965 case MESA_SHADER_TESS_CTRL
:
5966 handle_tcs_outputs_post(ctx
);
5968 case MESA_SHADER_TESS_EVAL
:
5969 if (ctx
->options
->key
.tes
.as_es
)
5970 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
5972 handle_vs_outputs_post(ctx
, ctx
->options
->key
.tes
.export_prim_id
,
5973 &ctx
->shader_info
->tes
.outinfo
);
5980 static void ac_llvm_finalize_module(struct nir_to_llvm_context
* ctx
)
5982 LLVMPassManagerRef passmgr
;
5983 /* Create the pass manager */
5984 passmgr
= LLVMCreateFunctionPassManagerForModule(
5987 /* This pass should eliminate all the load and store instructions */
5988 LLVMAddPromoteMemoryToRegisterPass(passmgr
);
5990 /* Add some optimization passes */
5991 LLVMAddScalarReplAggregatesPass(passmgr
);
5992 LLVMAddLICMPass(passmgr
);
5993 LLVMAddAggressiveDCEPass(passmgr
);
5994 LLVMAddCFGSimplificationPass(passmgr
);
5995 LLVMAddInstructionCombiningPass(passmgr
);
5998 LLVMInitializeFunctionPassManager(passmgr
);
5999 LLVMRunFunctionPassManager(passmgr
, ctx
->main_function
);
6000 LLVMFinalizeFunctionPassManager(passmgr
);
6002 LLVMDisposeBuilder(ctx
->builder
);
6003 LLVMDisposePassManager(passmgr
);
6007 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context
*ctx
)
6009 struct ac_vs_output_info
*outinfo
;
6011 switch (ctx
->stage
) {
6012 case MESA_SHADER_FRAGMENT
:
6013 case MESA_SHADER_COMPUTE
:
6014 case MESA_SHADER_TESS_CTRL
:
6015 case MESA_SHADER_GEOMETRY
:
6017 case MESA_SHADER_VERTEX
:
6018 if (ctx
->options
->key
.vs
.as_ls
||
6019 ctx
->options
->key
.vs
.as_es
)
6021 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
6023 case MESA_SHADER_TESS_EVAL
:
6024 if (ctx
->options
->key
.vs
.as_es
)
6026 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
6029 unreachable("Unhandled shader type");
6032 ac_optimize_vs_outputs(&ctx
->ac
,
6034 outinfo
->vs_output_param_offset
,
6036 &outinfo
->param_exports
);
6040 ac_setup_rings(struct nir_to_llvm_context
*ctx
)
6042 if ((ctx
->stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs
.as_es
) ||
6043 (ctx
->stage
== MESA_SHADER_TESS_EVAL
&& ctx
->options
->key
.tes
.as_es
)) {
6044 ctx
->esgs_ring
= ac_build_indexed_load_const(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_ESGS_VS
, false));
6047 if (ctx
->is_gs_copy_shader
) {
6048 ctx
->gsvs_ring
= ac_build_indexed_load_const(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_GSVS_VS
, false));
6050 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
6052 ctx
->esgs_ring
= ac_build_indexed_load_const(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_ESGS_GS
, false));
6053 ctx
->gsvs_ring
= ac_build_indexed_load_const(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_GSVS_GS
, false));
6055 ctx
->gsvs_ring
= LLVMBuildBitCast(ctx
->builder
, ctx
->gsvs_ring
, ctx
->v4i32
, "");
6057 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->gsvs_num_entries
, LLVMConstInt(ctx
->i32
, 2, false), "");
6058 tmp
= LLVMBuildExtractElement(ctx
->builder
, ctx
->gsvs_ring
, ctx
->i32one
, "");
6059 tmp
= LLVMBuildOr(ctx
->builder
, tmp
, ctx
->gsvs_ring_stride
, "");
6060 ctx
->gsvs_ring
= LLVMBuildInsertElement(ctx
->builder
, ctx
->gsvs_ring
, tmp
, ctx
->i32one
, "");
6063 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
6064 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
6065 ctx
->hs_ring_tess_offchip
= ac_build_indexed_load_const(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_HS_TESS_OFFCHIP
, false));
6066 ctx
->hs_ring_tess_factor
= ac_build_indexed_load_const(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->i32
, RING_HS_TESS_FACTOR
, false));
6071 ac_nir_get_max_workgroup_size(enum chip_class chip_class
,
6072 const struct nir_shader
*nir
)
6074 switch (nir
->stage
) {
6075 case MESA_SHADER_TESS_CTRL
:
6076 return chip_class
>= CIK
? 128 : 64;
6077 case MESA_SHADER_GEOMETRY
:
6079 case MESA_SHADER_COMPUTE
:
6085 unsigned max_workgroup_size
= nir
->info
.cs
.local_size
[0] *
6086 nir
->info
.cs
.local_size
[1] *
6087 nir
->info
.cs
.local_size
[2];
6088 return max_workgroup_size
;
6091 void ac_nir_translate(struct ac_llvm_context
*ac
, struct ac_shader_abi
*abi
,
6092 struct nir_shader
*nir
, struct nir_to_llvm_context
*nctx
)
6094 struct ac_nir_context ctx
= {};
6095 struct nir_function
*func
;
6104 ctx
.stage
= nir
->stage
;
6106 ctx
.main_function
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
6108 nir_foreach_variable(variable
, &nir
->outputs
)
6109 handle_shader_output_decl(&ctx
, nir
, variable
);
6111 ctx
.defs
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6112 _mesa_key_pointer_equal
);
6113 ctx
.phis
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6114 _mesa_key_pointer_equal
);
6115 ctx
.vars
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
6116 _mesa_key_pointer_equal
);
6118 func
= (struct nir_function
*)exec_list_get_head(&nir
->functions
);
6120 setup_locals(&ctx
, func
);
6122 if (nir
->stage
== MESA_SHADER_COMPUTE
)
6123 setup_shared(&ctx
, nir
);
6125 visit_cf_list(&ctx
, &func
->impl
->body
);
6126 phi_post_pass(&ctx
);
6128 ctx
.abi
->emit_outputs(ctx
.abi
, RADEON_LLVM_MAX_OUTPUTS
,
6132 ralloc_free(ctx
.defs
);
6133 ralloc_free(ctx
.phis
);
6134 ralloc_free(ctx
.vars
);
6141 LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm
,
6142 struct nir_shader
*nir
,
6143 struct ac_shader_variant_info
*shader_info
,
6144 const struct ac_nir_compiler_options
*options
)
6146 struct nir_to_llvm_context ctx
= {0};
6148 ctx
.options
= options
;
6149 ctx
.shader_info
= shader_info
;
6150 ctx
.context
= LLVMContextCreate();
6151 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6153 ac_llvm_context_init(&ctx
.ac
, ctx
.context
);
6154 ctx
.ac
.module
= ctx
.module
;
6156 ctx
.has_ds_bpermute
= ctx
.options
->chip_class
>= VI
;
6158 memset(shader_info
, 0, sizeof(*shader_info
));
6160 ac_nir_shader_info_pass(nir
, options
, &shader_info
->info
);
6162 LLVMSetTarget(ctx
.module
, options
->supports_spill
? "amdgcn-mesa-mesa3d" : "amdgcn--");
6164 LLVMTargetDataRef data_layout
= LLVMCreateTargetDataLayout(tm
);
6165 char *data_layout_str
= LLVMCopyStringRepOfTargetData(data_layout
);
6166 LLVMSetDataLayout(ctx
.module
, data_layout_str
);
6167 LLVMDisposeTargetData(data_layout
);
6168 LLVMDisposeMessage(data_layout_str
);
6172 ctx
.builder
= LLVMCreateBuilderInContext(ctx
.context
);
6173 ctx
.ac
.builder
= ctx
.builder
;
6174 ctx
.stage
= nir
->stage
;
6175 ctx
.max_workgroup_size
= ac_nir_get_max_workgroup_size(ctx
.options
->chip_class
, nir
);
6177 for (i
= 0; i
< AC_UD_MAX_SETS
; i
++)
6178 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
6179 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
6180 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
6182 create_function(&ctx
);
6184 if (nir
->stage
== MESA_SHADER_GEOMETRY
) {
6185 ctx
.gs_next_vertex
= ac_build_alloca(&ctx
.ac
, ctx
.i32
, "gs_next_vertex");
6187 ctx
.gs_max_out_vertices
= nir
->info
.gs
.vertices_out
;
6188 } else if (nir
->stage
== MESA_SHADER_TESS_EVAL
) {
6189 ctx
.tes_primitive_mode
= nir
->info
.tess
.primitive_mode
;
6192 ac_setup_rings(&ctx
);
6194 ctx
.num_output_clips
= nir
->info
.clip_distance_array_size
;
6195 ctx
.num_output_culls
= nir
->info
.cull_distance_array_size
;
6197 nir_foreach_variable(variable
, &nir
->inputs
)
6198 handle_shader_input_decl(&ctx
, variable
);
6200 if (nir
->stage
== MESA_SHADER_FRAGMENT
)
6201 handle_fs_inputs_pre(&ctx
, nir
);
6203 ctx
.abi
.inputs
= &ctx
.inputs
[0];
6204 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
6206 nir_foreach_variable(variable
, &nir
->outputs
)
6207 scan_shader_output_decl(&ctx
, variable
);
6209 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, nir
, &ctx
);
6211 LLVMBuildRetVoid(ctx
.builder
);
6213 ac_llvm_finalize_module(&ctx
);
6215 ac_nir_eliminate_const_vs_outputs(&ctx
);
6217 if (nir
->stage
== MESA_SHADER_GEOMETRY
) {
6218 unsigned addclip
= ctx
.num_output_clips
+ ctx
.num_output_culls
> 4;
6219 shader_info
->gs
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
6220 shader_info
->gs
.max_gsvs_emit_size
= shader_info
->gs
.gsvs_vertex_size
*
6221 nir
->info
.gs
.vertices_out
;
6222 } else if (nir
->stage
== MESA_SHADER_TESS_CTRL
) {
6223 shader_info
->tcs
.outputs_written
= ctx
.tess_outputs_written
;
6224 shader_info
->tcs
.patch_outputs_written
= ctx
.tess_patch_outputs_written
;
6225 } else if (nir
->stage
== MESA_SHADER_VERTEX
&& ctx
.options
->key
.vs
.as_ls
) {
6226 shader_info
->vs
.outputs_written
= ctx
.tess_outputs_written
;
6232 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
6234 unsigned *retval
= (unsigned *)context
;
6235 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
6236 char *description
= LLVMGetDiagInfoDescription(di
);
6238 if (severity
== LLVMDSError
) {
6240 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
6244 LLVMDisposeMessage(description
);
6247 static unsigned ac_llvm_compile(LLVMModuleRef M
,
6248 struct ac_shader_binary
*binary
,
6249 LLVMTargetMachineRef tm
)
6251 unsigned retval
= 0;
6253 LLVMContextRef llvm_ctx
;
6254 LLVMMemoryBufferRef out_buffer
;
6255 unsigned buffer_size
;
6256 const char *buffer_data
;
6259 /* Setup Diagnostic Handler*/
6260 llvm_ctx
= LLVMGetModuleContext(M
);
6262 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
6266 mem_err
= LLVMTargetMachineEmitToMemoryBuffer(tm
, M
, LLVMObjectFile
,
6269 /* Process Errors/Warnings */
6271 fprintf(stderr
, "%s: %s", __FUNCTION__
, err
);
6277 /* Extract Shader Code*/
6278 buffer_size
= LLVMGetBufferSize(out_buffer
);
6279 buffer_data
= LLVMGetBufferStart(out_buffer
);
6281 ac_elf_read(buffer_data
, buffer_size
, binary
);
6284 LLVMDisposeMemoryBuffer(out_buffer
);
6290 static void ac_compile_llvm_module(LLVMTargetMachineRef tm
,
6291 LLVMModuleRef llvm_module
,
6292 struct ac_shader_binary
*binary
,
6293 struct ac_shader_config
*config
,
6294 struct ac_shader_variant_info
*shader_info
,
6295 gl_shader_stage stage
,
6296 bool dump_shader
, bool supports_spill
)
6299 ac_dump_module(llvm_module
);
6301 memset(binary
, 0, sizeof(*binary
));
6302 int v
= ac_llvm_compile(llvm_module
, binary
, tm
);
6304 fprintf(stderr
, "compile failed\n");
6308 fprintf(stderr
, "disasm:\n%s\n", binary
->disasm_string
);
6310 ac_shader_binary_read_config(binary
, config
, 0, supports_spill
);
6312 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
6313 LLVMDisposeModule(llvm_module
);
6314 LLVMContextDispose(ctx
);
6316 if (stage
== MESA_SHADER_FRAGMENT
) {
6317 shader_info
->num_input_vgprs
= 0;
6318 if (G_0286CC_PERSP_SAMPLE_ENA(config
->spi_ps_input_addr
))
6319 shader_info
->num_input_vgprs
+= 2;
6320 if (G_0286CC_PERSP_CENTER_ENA(config
->spi_ps_input_addr
))
6321 shader_info
->num_input_vgprs
+= 2;
6322 if (G_0286CC_PERSP_CENTROID_ENA(config
->spi_ps_input_addr
))
6323 shader_info
->num_input_vgprs
+= 2;
6324 if (G_0286CC_PERSP_PULL_MODEL_ENA(config
->spi_ps_input_addr
))
6325 shader_info
->num_input_vgprs
+= 3;
6326 if (G_0286CC_LINEAR_SAMPLE_ENA(config
->spi_ps_input_addr
))
6327 shader_info
->num_input_vgprs
+= 2;
6328 if (G_0286CC_LINEAR_CENTER_ENA(config
->spi_ps_input_addr
))
6329 shader_info
->num_input_vgprs
+= 2;
6330 if (G_0286CC_LINEAR_CENTROID_ENA(config
->spi_ps_input_addr
))
6331 shader_info
->num_input_vgprs
+= 2;
6332 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config
->spi_ps_input_addr
))
6333 shader_info
->num_input_vgprs
+= 1;
6334 if (G_0286CC_POS_X_FLOAT_ENA(config
->spi_ps_input_addr
))
6335 shader_info
->num_input_vgprs
+= 1;
6336 if (G_0286CC_POS_Y_FLOAT_ENA(config
->spi_ps_input_addr
))
6337 shader_info
->num_input_vgprs
+= 1;
6338 if (G_0286CC_POS_Z_FLOAT_ENA(config
->spi_ps_input_addr
))
6339 shader_info
->num_input_vgprs
+= 1;
6340 if (G_0286CC_POS_W_FLOAT_ENA(config
->spi_ps_input_addr
))
6341 shader_info
->num_input_vgprs
+= 1;
6342 if (G_0286CC_FRONT_FACE_ENA(config
->spi_ps_input_addr
))
6343 shader_info
->num_input_vgprs
+= 1;
6344 if (G_0286CC_ANCILLARY_ENA(config
->spi_ps_input_addr
))
6345 shader_info
->num_input_vgprs
+= 1;
6346 if (G_0286CC_SAMPLE_COVERAGE_ENA(config
->spi_ps_input_addr
))
6347 shader_info
->num_input_vgprs
+= 1;
6348 if (G_0286CC_POS_FIXED_PT_ENA(config
->spi_ps_input_addr
))
6349 shader_info
->num_input_vgprs
+= 1;
6351 config
->num_vgprs
= MAX2(config
->num_vgprs
, shader_info
->num_input_vgprs
);
6353 /* +3 for scratch wave offset and VCC */
6354 config
->num_sgprs
= MAX2(config
->num_sgprs
,
6355 shader_info
->num_input_sgprs
+ 3);
6358 void ac_compile_nir_shader(LLVMTargetMachineRef tm
,
6359 struct ac_shader_binary
*binary
,
6360 struct ac_shader_config
*config
,
6361 struct ac_shader_variant_info
*shader_info
,
6362 struct nir_shader
*nir
,
6363 const struct ac_nir_compiler_options
*options
,
6367 LLVMModuleRef llvm_module
= ac_translate_nir_to_llvm(tm
, nir
, shader_info
,
6370 ac_compile_llvm_module(tm
, llvm_module
, binary
, config
, shader_info
, nir
->stage
, dump_shader
, options
->supports_spill
);
6371 switch (nir
->stage
) {
6372 case MESA_SHADER_COMPUTE
:
6373 for (int i
= 0; i
< 3; ++i
)
6374 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
6376 case MESA_SHADER_FRAGMENT
:
6377 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
6379 case MESA_SHADER_GEOMETRY
:
6380 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
6381 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
6382 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
6383 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
6385 case MESA_SHADER_TESS_EVAL
:
6386 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
6387 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
6388 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
6389 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
6390 shader_info
->tes
.as_es
= options
->key
.tes
.as_es
;
6392 case MESA_SHADER_TESS_CTRL
:
6393 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
6395 case MESA_SHADER_VERTEX
:
6396 shader_info
->vs
.as_es
= options
->key
.vs
.as_es
;
6397 shader_info
->vs
.as_ls
= options
->key
.vs
.as_ls
;
6398 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6399 if (options
->key
.vs
.as_ls
)
6400 shader_info
->vs
.vgpr_comp_cnt
= MAX2(1, shader_info
->vs
.vgpr_comp_cnt
);
6408 ac_gs_copy_shader_emit(struct nir_to_llvm_context
*ctx
)
6410 LLVMValueRef args
[9];
6411 args
[0] = ctx
->gsvs_ring
;
6412 args
[1] = LLVMBuildMul(ctx
->builder
, ctx
->abi
.vertex_id
, LLVMConstInt(ctx
->i32
, 4, false), "");
6413 args
[3] = ctx
->i32zero
;
6414 args
[4] = ctx
->i32one
; /* OFFEN */
6415 args
[5] = ctx
->i32zero
; /* IDXEN */
6416 args
[6] = ctx
->i32one
; /* GLC */
6417 args
[7] = ctx
->i32one
; /* SLC */
6418 args
[8] = ctx
->i32zero
; /* TFE */
6422 for (unsigned i
= 0; i
< RADEON_LLVM_MAX_OUTPUTS
; ++i
) {
6426 if (!(ctx
->output_mask
& (1ull << i
)))
6429 if (i
== VARYING_SLOT_CLIP_DIST0
) {
6430 /* unpack clip and cull from a single set of slots */
6431 length
= ctx
->num_output_clips
+ ctx
->num_output_culls
;
6436 for (unsigned j
= 0; j
< length
; j
++) {
6438 args
[2] = LLVMConstInt(ctx
->i32
,
6440 ctx
->gs_max_out_vertices
* 16 * 4, false);
6442 value
= ac_build_intrinsic(&ctx
->ac
,
6443 "llvm.SI.buffer.load.dword.i32.i32",
6445 AC_FUNC_ATTR_READONLY
|
6446 AC_FUNC_ATTR_LEGACY
);
6448 LLVMBuildStore(ctx
->builder
,
6449 to_float(&ctx
->ac
, value
), ctx
->nir
->outputs
[radeon_llvm_reg_index_soa(i
, j
)]);
6453 handle_vs_outputs_post(ctx
, false, &ctx
->shader_info
->vs
.outinfo
);
6456 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm
,
6457 struct nir_shader
*geom_shader
,
6458 struct ac_shader_binary
*binary
,
6459 struct ac_shader_config
*config
,
6460 struct ac_shader_variant_info
*shader_info
,
6461 const struct ac_nir_compiler_options
*options
,
6464 struct nir_to_llvm_context ctx
= {0};
6465 ctx
.context
= LLVMContextCreate();
6466 ctx
.module
= LLVMModuleCreateWithNameInContext("shader", ctx
.context
);
6467 ctx
.options
= options
;
6468 ctx
.shader_info
= shader_info
;
6470 ac_llvm_context_init(&ctx
.ac
, ctx
.context
);
6471 ctx
.ac
.module
= ctx
.module
;
6473 ctx
.is_gs_copy_shader
= true;
6474 LLVMSetTarget(ctx
.module
, "amdgcn--");
6477 ctx
.builder
= LLVMCreateBuilderInContext(ctx
.context
);
6478 ctx
.ac
.builder
= ctx
.builder
;
6479 ctx
.stage
= MESA_SHADER_VERTEX
;
6481 create_function(&ctx
);
6483 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
6484 ac_setup_rings(&ctx
);
6486 ctx
.num_output_clips
= geom_shader
->info
.clip_distance_array_size
;
6487 ctx
.num_output_culls
= geom_shader
->info
.cull_distance_array_size
;
6489 struct ac_nir_context nir_ctx
= {};
6490 nir_ctx
.ac
= ctx
.ac
;
6491 nir_ctx
.abi
= &ctx
.abi
;
6493 nir_ctx
.nctx
= &ctx
;
6496 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
6497 scan_shader_output_decl(&ctx
, variable
);
6498 handle_shader_output_decl(&nir_ctx
, geom_shader
, variable
);
6501 ac_gs_copy_shader_emit(&ctx
);
6505 LLVMBuildRetVoid(ctx
.builder
);
6507 ac_llvm_finalize_module(&ctx
);
6509 ac_compile_llvm_module(tm
, ctx
.module
, binary
, config
, shader_info
,
6511 dump_shader
, options
->supports_spill
);