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radv: start allocating user sgprs
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83 LLVMValueRef ls_out_layout;
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef tcs_offchip_layout;
87 LLVMValueRef tcs_out_offsets;
88 LLVMValueRef tcs_out_layout;
89 LLVMValueRef tcs_in_layout;
90 LLVMValueRef oc_lds;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tcs_patch_id;
93 LLVMValueRef tcs_rel_ids;
94 LLVMValueRef tes_rel_patch_id;
95 LLVMValueRef tes_patch_id;
96 LLVMValueRef tes_u;
97 LLVMValueRef tes_v;
98
99 LLVMValueRef gsvs_ring_stride;
100 LLVMValueRef gsvs_num_entries;
101 LLVMValueRef gs2vs_offset;
102 LLVMValueRef gs_wave_id;
103 LLVMValueRef gs_vtx_offset[6];
104 LLVMValueRef gs_prim_id, gs_invocation_id;
105
106 LLVMValueRef esgs_ring;
107 LLVMValueRef gsvs_ring;
108 LLVMValueRef hs_ring_tess_offchip;
109 LLVMValueRef hs_ring_tess_factor;
110
111 LLVMValueRef prim_mask;
112 LLVMValueRef sample_pos_offset;
113 LLVMValueRef persp_sample, persp_center, persp_centroid;
114 LLVMValueRef linear_sample, linear_center, linear_centroid;
115 LLVMValueRef front_face;
116 LLVMValueRef ancillary;
117 LLVMValueRef sample_coverage;
118 LLVMValueRef frag_pos[4];
119
120 LLVMBasicBlockRef continue_block;
121 LLVMBasicBlockRef break_block;
122
123 LLVMTypeRef i1;
124 LLVMTypeRef i8;
125 LLVMTypeRef i16;
126 LLVMTypeRef i32;
127 LLVMTypeRef i64;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v3i32;
130 LLVMTypeRef v4i32;
131 LLVMTypeRef v8i32;
132 LLVMTypeRef f64;
133 LLVMTypeRef f32;
134 LLVMTypeRef f16;
135 LLVMTypeRef v2f32;
136 LLVMTypeRef v4f32;
137 LLVMTypeRef v16i8;
138 LLVMTypeRef voidt;
139
140 LLVMValueRef i1true;
141 LLVMValueRef i1false;
142 LLVMValueRef i32zero;
143 LLVMValueRef i32one;
144 LLVMValueRef f32zero;
145 LLVMValueRef f32one;
146 LLVMValueRef v4f32empty;
147
148 unsigned uniform_md_kind;
149 LLVMValueRef empty_md;
150 gl_shader_stage stage;
151
152 LLVMValueRef lds;
153 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
154 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
155
156 LLVMValueRef shared_memory;
157 uint64_t input_mask;
158 uint64_t output_mask;
159 int num_locals;
160 LLVMValueRef *locals;
161 bool has_ddxy;
162 uint8_t num_output_clips;
163 uint8_t num_output_culls;
164
165 bool has_ds_bpermute;
166
167 bool is_gs_copy_shader;
168 LLVMValueRef gs_next_vertex;
169 unsigned gs_max_out_vertices;
170
171 unsigned tes_primitive_mode;
172 uint64_t tess_outputs_written;
173 uint64_t tess_patch_outputs_written;
174 };
175
176 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
177 nir_deref_var *deref,
178 enum desc_type desc_type);
179 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
180 {
181 return (index * 4) + chan;
182 }
183
184 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
185 {
186 /* handle patch indices separate */
187 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
188 return 0;
189 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
190 return 1;
191 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
192 return 2 + (slot - VARYING_SLOT_PATCH0);
193
194 if (slot == VARYING_SLOT_POS)
195 return 0;
196 if (slot == VARYING_SLOT_PSIZ)
197 return 1;
198 if (slot == VARYING_SLOT_CLIP_DIST0)
199 return 2;
200 /* 3 is reserved for clip dist as well */
201 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
202 return 4 + (slot - VARYING_SLOT_VAR0);
203 unreachable("illegal slot in get unique index\n");
204 }
205
206 static unsigned llvm_get_type_size(LLVMTypeRef type)
207 {
208 LLVMTypeKind kind = LLVMGetTypeKind(type);
209
210 switch (kind) {
211 case LLVMIntegerTypeKind:
212 return LLVMGetIntTypeWidth(type) / 8;
213 case LLVMFloatTypeKind:
214 return 4;
215 case LLVMPointerTypeKind:
216 return 8;
217 case LLVMVectorTypeKind:
218 return LLVMGetVectorSize(type) *
219 llvm_get_type_size(LLVMGetElementType(type));
220 default:
221 assert(0);
222 return 0;
223 }
224 }
225
226 static void set_llvm_calling_convention(LLVMValueRef func,
227 gl_shader_stage stage)
228 {
229 enum radeon_llvm_calling_convention calling_conv;
230
231 switch (stage) {
232 case MESA_SHADER_VERTEX:
233 case MESA_SHADER_TESS_CTRL:
234 case MESA_SHADER_TESS_EVAL:
235 calling_conv = RADEON_LLVM_AMDGPU_VS;
236 break;
237 case MESA_SHADER_GEOMETRY:
238 calling_conv = RADEON_LLVM_AMDGPU_GS;
239 break;
240 case MESA_SHADER_FRAGMENT:
241 calling_conv = RADEON_LLVM_AMDGPU_PS;
242 break;
243 case MESA_SHADER_COMPUTE:
244 calling_conv = RADEON_LLVM_AMDGPU_CS;
245 break;
246 default:
247 unreachable("Unhandle shader type");
248 }
249
250 LLVMSetFunctionCallConv(func, calling_conv);
251 }
252
253 static LLVMValueRef
254 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
255 LLVMBuilderRef builder, LLVMTypeRef *return_types,
256 unsigned num_return_elems, LLVMTypeRef *param_types,
257 unsigned param_count, unsigned array_params_mask,
258 unsigned sgpr_params, bool unsafe_math)
259 {
260 LLVMTypeRef main_function_type, ret_type;
261 LLVMBasicBlockRef main_function_body;
262
263 if (num_return_elems)
264 ret_type = LLVMStructTypeInContext(ctx, return_types,
265 num_return_elems, true);
266 else
267 ret_type = LLVMVoidTypeInContext(ctx);
268
269 /* Setup the function */
270 main_function_type =
271 LLVMFunctionType(ret_type, param_types, param_count, 0);
272 LLVMValueRef main_function =
273 LLVMAddFunction(module, "main", main_function_type);
274 main_function_body =
275 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
276 LLVMPositionBuilderAtEnd(builder, main_function_body);
277
278 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
279 for (unsigned i = 0; i < sgpr_params; ++i) {
280 if (array_params_mask & (1 << i)) {
281 LLVMValueRef P = LLVMGetParam(main_function, i);
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
283 ac_add_attr_dereferenceable(P, UINT64_MAX);
284 }
285 else {
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
287 }
288 }
289
290 if (unsafe_math) {
291 /* These were copied from some LLVM test. */
292 LLVMAddTargetDependentFunctionAttr(main_function,
293 "less-precise-fpmad",
294 "true");
295 LLVMAddTargetDependentFunctionAttr(main_function,
296 "no-infs-fp-math",
297 "true");
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "no-nans-fp-math",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "unsafe-fp-math",
303 "true");
304 }
305 return main_function;
306 }
307
308 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
309 {
310 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
311 CONST_ADDR_SPACE);
312 }
313
314 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
315 int idx,
316 LLVMTypeRef type)
317 {
318 LLVMValueRef offset;
319 LLVMValueRef ptr;
320 int addr_space;
321
322 offset = LLVMConstInt(ctx->i32, idx * 16, false);
323
324 ptr = ctx->shared_memory;
325 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
326 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
327 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
328 return ptr;
329 }
330
331 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
332 {
333 if (t == ctx->f16 || t == ctx->i16)
334 return ctx->i16;
335 else if (t == ctx->f32 || t == ctx->i32)
336 return ctx->i32;
337 else if (t == ctx->f64 || t == ctx->i64)
338 return ctx->i64;
339 else
340 unreachable("Unhandled integer size");
341 }
342
343 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
344 {
345 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
346 LLVMTypeRef elem_type = LLVMGetElementType(t);
347 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
348 LLVMGetVectorSize(t));
349 }
350 return to_integer_type_scalar(ctx, t);
351 }
352
353 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
354 {
355 LLVMTypeRef type = LLVMTypeOf(v);
356 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
357 }
358
359 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
360 {
361 if (t == ctx->i16 || t == ctx->f16)
362 return ctx->f16;
363 else if (t == ctx->i32 || t == ctx->f32)
364 return ctx->f32;
365 else if (t == ctx->i64 || t == ctx->f64)
366 return ctx->f64;
367 else
368 unreachable("Unhandled float size");
369 }
370
371 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
372 {
373 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
374 LLVMTypeRef elem_type = LLVMGetElementType(t);
375 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
376 LLVMGetVectorSize(t));
377 }
378 return to_float_type_scalar(ctx, t);
379 }
380
381 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
382 {
383 LLVMTypeRef type = LLVMTypeOf(v);
384 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
385 }
386
387 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
388 {
389 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
390 type = LLVMGetElementType(type);
391
392 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
393 return LLVMGetIntTypeWidth(type);
394
395 if (type == ctx->f16)
396 return 16;
397 if (type == ctx->f32)
398 return 32;
399 if (type == ctx->f64)
400 return 64;
401
402 unreachable("Unhandled type kind in get_elem_bits");
403 }
404
405 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
406 LLVMValueRef param, unsigned rshift,
407 unsigned bitwidth)
408 {
409 LLVMValueRef value = param;
410 if (rshift)
411 value = LLVMBuildLShr(ctx->builder, value,
412 LLVMConstInt(ctx->i32, rshift, false), "");
413
414 if (rshift + bitwidth < 32) {
415 unsigned mask = (1 << bitwidth) - 1;
416 value = LLVMBuildAnd(ctx->builder, value,
417 LLVMConstInt(ctx->i32, mask, false), "");
418 }
419 return value;
420 }
421
422 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
423 {
424 switch (ctx->stage) {
425 case MESA_SHADER_TESS_CTRL:
426 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
427 case MESA_SHADER_TESS_EVAL:
428 return ctx->tes_rel_patch_id;
429 break;
430 default:
431 unreachable("Illegal stage");
432 }
433 }
434
435 /* Tessellation shaders pass outputs to the next shader using LDS.
436 *
437 * LS outputs = TCS inputs
438 * TCS outputs = TES inputs
439 *
440 * The LDS layout is:
441 * - TCS inputs for patch 0
442 * - TCS inputs for patch 1
443 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
444 * - ...
445 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
446 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
447 * - TCS outputs for patch 1
448 * - Per-patch TCS outputs for patch 1
449 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
450 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
451 * - ...
452 *
453 * All three shaders VS(LS), TCS, TES share the same LDS space.
454 */
455 static LLVMValueRef
456 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
457 {
458 if (ctx->stage == MESA_SHADER_VERTEX)
459 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
460 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
461 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
462 else {
463 assert(0);
464 return NULL;
465 }
466 }
467
468 static LLVMValueRef
469 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
470 {
471 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
472 }
473
474 static LLVMValueRef
475 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
476 {
477 return LLVMBuildMul(ctx->builder,
478 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
479 LLVMConstInt(ctx->i32, 4, false), "");
480 }
481
482 static LLVMValueRef
483 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
484 {
485 return LLVMBuildMul(ctx->builder,
486 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
487 LLVMConstInt(ctx->i32, 4, false), "");
488 }
489
490 static LLVMValueRef
491 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
494 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
495
496 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
497 }
498
499 static LLVMValueRef
500 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
501 {
502 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
503 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
504 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
505
506 return LLVMBuildAdd(ctx->builder, patch0_offset,
507 LLVMBuildMul(ctx->builder, patch_stride,
508 rel_patch_id, ""),
509 "");
510 }
511
512 static LLVMValueRef
513 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
514 {
515 LLVMValueRef patch0_patch_data_offset =
516 get_tcs_out_patch0_patch_data_offset(ctx);
517 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
518 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
519
520 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
521 LLVMBuildMul(ctx->builder, patch_stride,
522 rel_patch_id, ""),
523 "");
524 }
525
526 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
527 {
528 ud_info->sgpr_idx = sgpr_idx;
529 ud_info->num_sgprs = num_sgprs;
530 ud_info->indirect = false;
531 ud_info->indirect_offset = 0;
532 }
533
534 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
535 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
536 {
537 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
538 }
539
540 #if 0
541 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
542 uint32_t indirect_offset)
543 {
544 ud_info->sgpr_idx = sgpr_idx;
545 ud_info->num_sgprs = num_sgprs;
546 ud_info->indirect = true;
547 ud_info->indirect_offset = indirect_offset;
548 }
549 #endif
550
551 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
552 {
553 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
554 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
555 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
556 "tess_lds");
557 }
558
559 struct user_sgpr_info {
560 bool need_ring_offsets;
561 uint8_t sgpr_count;
562 };
563
564 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
565 struct user_sgpr_info *user_sgpr_info)
566 {
567 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
568
569 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
570 if (ctx->stage == MESA_SHADER_GEOMETRY ||
571 ctx->stage == MESA_SHADER_VERTEX ||
572 ctx->stage == MESA_SHADER_TESS_CTRL ||
573 ctx->stage == MESA_SHADER_TESS_EVAL ||
574 ctx->is_gs_copy_shader)
575 user_sgpr_info->need_ring_offsets = true;
576
577 if (ctx->stage == MESA_SHADER_FRAGMENT &&
578 ctx->shader_info->info.ps.needs_sample_positions)
579 user_sgpr_info->need_ring_offsets = true;
580
581 /* 2 user sgprs will nearly always be allocated for scratch/rings */
582 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
583 user_sgpr_info->sgpr_count += 2;
584 }
585
586 switch (ctx->stage) {
587 case MESA_SHADER_COMPUTE:
588 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
589 break;
590 case MESA_SHADER_FRAGMENT:
591 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
592 break;
593 case MESA_SHADER_VERTEX:
594 if (!ctx->is_gs_copy_shader) {
595 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
596 if (ctx->shader_info->info.vs.needs_draw_id) {
597 user_sgpr_info->sgpr_count += 3;
598 } else {
599 user_sgpr_info->sgpr_count += 2;
600 }
601 }
602 if (ctx->options->key.vs.as_ls)
603 user_sgpr_info->sgpr_count++;
604 break;
605 case MESA_SHADER_TESS_CTRL:
606 user_sgpr_info->sgpr_count += 4;
607 break;
608 case MESA_SHADER_TESS_EVAL:
609 user_sgpr_info->sgpr_count += 1;
610 break;
611 case MESA_SHADER_GEOMETRY:
612 user_sgpr_info->sgpr_count += 2;
613 break;
614 default:
615 break;
616 }
617
618 if (ctx->shader_info->info.needs_push_constants)
619 user_sgpr_info->sgpr_count += 2;
620
621 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
622 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
623 fprintf(stderr, "radv: TODO: add support for indirect sgprs\n");
624 /* need to add support for indirect descriptor sets */
625 assert(0);
626 } else {
627 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
628 }
629 }
630
631 static void create_function(struct nir_to_llvm_context *ctx)
632 {
633 LLVMTypeRef arg_types[23];
634 unsigned arg_idx = 0;
635 unsigned array_params_mask = 0;
636 unsigned sgpr_count = 0, user_sgpr_count;
637 unsigned i;
638 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
639 unsigned user_sgpr_idx;
640 struct user_sgpr_info user_sgpr_info;
641
642 allocate_user_sgprs(ctx, &user_sgpr_info);
643 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
644 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* address of rings */
645 }
646
647 /* 1 for each descriptor set */
648 for (unsigned i = 0; i < num_sets; ++i) {
649 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
650 array_params_mask |= (1 << arg_idx);
651 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
652 }
653 }
654
655 if (ctx->shader_info->info.needs_push_constants) {
656 /* 1 for push constants and dynamic descriptors */
657 array_params_mask |= (1 << arg_idx);
658 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
659 }
660
661 switch (ctx->stage) {
662 case MESA_SHADER_COMPUTE:
663 if (ctx->shader_info->info.cs.grid_components_used)
664 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used); /* grid size */
665 user_sgpr_count = arg_idx;
666 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
667 arg_types[arg_idx++] = ctx->i32;
668 sgpr_count = arg_idx;
669
670 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
671 break;
672 case MESA_SHADER_VERTEX:
673 if (!ctx->is_gs_copy_shader) {
674 if (ctx->shader_info->info.vs.has_vertex_buffers)
675 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
676 arg_types[arg_idx++] = ctx->i32; // base vertex
677 arg_types[arg_idx++] = ctx->i32; // start instance
678 if (ctx->shader_info->info.vs.needs_draw_id)
679 arg_types[arg_idx++] = ctx->i32; // draw index
680 }
681 user_sgpr_count = arg_idx;
682 if (ctx->options->key.vs.as_es)
683 arg_types[arg_idx++] = ctx->i32; //es2gs offset
684 else if (ctx->options->key.vs.as_ls) {
685 arg_types[arg_idx++] = ctx->i32; //ls out layout
686 user_sgpr_count++;
687 }
688 sgpr_count = arg_idx;
689 arg_types[arg_idx++] = ctx->i32; // vertex id
690 if (!ctx->is_gs_copy_shader) {
691 arg_types[arg_idx++] = ctx->i32; // rel auto id
692 arg_types[arg_idx++] = ctx->i32; // vs prim id
693 arg_types[arg_idx++] = ctx->i32; // instance id
694 }
695 break;
696 case MESA_SHADER_TESS_CTRL:
697 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
698 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
699 arg_types[arg_idx++] = ctx->i32; // tcs out layout
700 arg_types[arg_idx++] = ctx->i32; // tcs in layout
701 user_sgpr_count = arg_idx;
702 arg_types[arg_idx++] = ctx->i32; // param oc lds
703 arg_types[arg_idx++] = ctx->i32; // tess factor offset
704 sgpr_count = arg_idx;
705 arg_types[arg_idx++] = ctx->i32; // patch id
706 arg_types[arg_idx++] = ctx->i32; // rel ids;
707 break;
708 case MESA_SHADER_TESS_EVAL:
709 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
710 user_sgpr_count = arg_idx;
711 if (ctx->options->key.tes.as_es) {
712 arg_types[arg_idx++] = ctx->i32; // OC LDS
713 arg_types[arg_idx++] = ctx->i32; //
714 arg_types[arg_idx++] = ctx->i32; // es2gs offset
715 } else {
716 arg_types[arg_idx++] = ctx->i32; //
717 arg_types[arg_idx++] = ctx->i32; // OC LDS
718 }
719 sgpr_count = arg_idx;
720 arg_types[arg_idx++] = ctx->f32; // tes_u
721 arg_types[arg_idx++] = ctx->f32; // tes_v
722 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
723 arg_types[arg_idx++] = ctx->i32; // tes patch id
724 break;
725 case MESA_SHADER_GEOMETRY:
726 arg_types[arg_idx++] = ctx->i32; // gsvs stride
727 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
728 user_sgpr_count = arg_idx;
729 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
730 arg_types[arg_idx++] = ctx->i32; // wave id
731 sgpr_count = arg_idx;
732 arg_types[arg_idx++] = ctx->i32; // vtx0
733 arg_types[arg_idx++] = ctx->i32; // vtx1
734 arg_types[arg_idx++] = ctx->i32; // prim id
735 arg_types[arg_idx++] = ctx->i32; // vtx2
736 arg_types[arg_idx++] = ctx->i32; // vtx3
737 arg_types[arg_idx++] = ctx->i32; // vtx4
738 arg_types[arg_idx++] = ctx->i32; // vtx5
739 arg_types[arg_idx++] = ctx->i32; // GS instance id
740 break;
741 case MESA_SHADER_FRAGMENT:
742 if (ctx->shader_info->info.ps.needs_sample_positions)
743 arg_types[arg_idx++] = ctx->i32; /* sample position offset */
744 user_sgpr_count = arg_idx;
745 arg_types[arg_idx++] = ctx->i32; /* prim mask */
746 sgpr_count = arg_idx;
747 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
748 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
749 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
750 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
751 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
752 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
753 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
754 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
755 arg_types[arg_idx++] = ctx->f32; /* pos x float */
756 arg_types[arg_idx++] = ctx->f32; /* pos y float */
757 arg_types[arg_idx++] = ctx->f32; /* pos z float */
758 arg_types[arg_idx++] = ctx->f32; /* pos w float */
759 arg_types[arg_idx++] = ctx->i32; /* front face */
760 arg_types[arg_idx++] = ctx->i32; /* ancillary */
761 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
762 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
763 break;
764 default:
765 unreachable("Shader stage not implemented");
766 }
767
768 ctx->main_function = create_llvm_function(
769 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
770 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
771 set_llvm_calling_convention(ctx->main_function, ctx->stage);
772
773 ctx->shader_info->num_input_sgprs = 0;
774 ctx->shader_info->num_input_vgprs = 0;
775
776 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
777 for (i = 0; i < user_sgpr_count; i++)
778 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
779
780 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
781 for (; i < sgpr_count; i++)
782 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
783
784 if (ctx->stage != MESA_SHADER_FRAGMENT)
785 for (; i < arg_idx; ++i)
786 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
787
788 arg_idx = 0;
789 user_sgpr_idx = 0;
790
791 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
792 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
793 user_sgpr_idx += 2;
794 if (ctx->options->supports_spill) {
795 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
796 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
797 NULL, 0, AC_FUNC_ATTR_READNONE);
798 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
799 const_array(ctx->v16i8, 16), "");
800 } else
801 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
802 }
803
804 for (unsigned i = 0; i < num_sets; ++i) {
805 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
806 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
807 user_sgpr_idx += 2;
808 ctx->descriptor_sets[i] =
809 LLVMGetParam(ctx->main_function, arg_idx++);
810 } else
811 ctx->descriptor_sets[i] = NULL;
812 }
813
814 if (ctx->shader_info->info.needs_push_constants) {
815 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
816 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
817 user_sgpr_idx += 2;
818 }
819
820 switch (ctx->stage) {
821 case MESA_SHADER_COMPUTE:
822 if (ctx->shader_info->info.cs.grid_components_used) {
823 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
824 user_sgpr_idx += ctx->shader_info->info.cs.grid_components_used;
825 ctx->num_work_groups =
826 LLVMGetParam(ctx->main_function, arg_idx++);
827 }
828 ctx->workgroup_ids =
829 LLVMGetParam(ctx->main_function, arg_idx++);
830 ctx->tg_size =
831 LLVMGetParam(ctx->main_function, arg_idx++);
832 ctx->local_invocation_ids =
833 LLVMGetParam(ctx->main_function, arg_idx++);
834 break;
835 case MESA_SHADER_VERTEX:
836 if (!ctx->is_gs_copy_shader) {
837 if (ctx->shader_info->info.vs.has_vertex_buffers) {
838 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
839 user_sgpr_idx += 2;
840 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
841 }
842 unsigned vs_num = 2;
843 if (ctx->shader_info->info.vs.needs_draw_id)
844 vs_num++;
845
846 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
847 user_sgpr_idx += vs_num;
848
849 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
850 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
851 if (ctx->shader_info->info.vs.needs_draw_id)
852 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
853 }
854 if (ctx->options->key.vs.as_es)
855 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
856 else if (ctx->options->key.vs.as_ls) {
857 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, user_sgpr_idx, 1);
858 user_sgpr_idx += 1;
859 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
860 }
861 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
862 if (!ctx->is_gs_copy_shader) {
863 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
864 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
865 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
866 }
867 if (ctx->options->key.vs.as_ls)
868 declare_tess_lds(ctx);
869 break;
870 case MESA_SHADER_TESS_CTRL:
871 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
872 user_sgpr_idx += 4;
873 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
874 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
875 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
876 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
877 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
878 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
879 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
880 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
881
882 declare_tess_lds(ctx);
883 break;
884 case MESA_SHADER_TESS_EVAL:
885 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
886 user_sgpr_idx += 1;
887 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
888 if (ctx->options->key.tes.as_es) {
889 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
890 arg_idx++;
891 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
892 } else {
893 arg_idx++;
894 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
895 }
896 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
897 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
898 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
899 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
900 break;
901 case MESA_SHADER_GEOMETRY:
902 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
903 user_sgpr_idx += 2;
904 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
905 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
906 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
907 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
908 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
909 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
910 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
911 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
912 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
913 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
914 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
915 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
916 break;
917 case MESA_SHADER_FRAGMENT:
918 if (ctx->shader_info->info.ps.needs_sample_positions) {
919 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, user_sgpr_idx, 1);
920 user_sgpr_idx += 1;
921 ctx->sample_pos_offset = LLVMGetParam(ctx->main_function, arg_idx++);
922 }
923 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
924 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
925 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
926 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
927 arg_idx++;
928 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
929 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
930 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
931 arg_idx++; /* line stipple */
932 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
933 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
934 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
935 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
936 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
937 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
938 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
939 break;
940 default:
941 unreachable("Shader stage not implemented");
942 }
943 }
944
945 static void setup_types(struct nir_to_llvm_context *ctx)
946 {
947 LLVMValueRef args[4];
948
949 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
950 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
951 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
952 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
953 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
954 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
955 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
956 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
957 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
958 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
959 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
960 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
961 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
962 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
963 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
964 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
965
966 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
967 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
968 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
969 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
970 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
971 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
972
973 args[0] = ctx->f32zero;
974 args[1] = ctx->f32zero;
975 args[2] = ctx->f32zero;
976 args[3] = ctx->f32one;
977 ctx->v4f32empty = LLVMConstVector(args, 4);
978
979 ctx->uniform_md_kind =
980 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
981 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
982
983 args[0] = LLVMConstReal(ctx->f32, 2.5);
984 }
985
986 static int get_llvm_num_components(LLVMValueRef value)
987 {
988 LLVMTypeRef type = LLVMTypeOf(value);
989 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
990 ? LLVMGetVectorSize(type)
991 : 1;
992 return num_components;
993 }
994
995 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
996 LLVMValueRef value,
997 int index)
998 {
999 int count = get_llvm_num_components(value);
1000
1001 assert(index < count);
1002 if (count == 1)
1003 return value;
1004
1005 return LLVMBuildExtractElement(ctx->builder, value,
1006 LLVMConstInt(ctx->i32, index, false), "");
1007 }
1008
1009 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
1010 LLVMValueRef value, unsigned count)
1011 {
1012 unsigned num_components = get_llvm_num_components(value);
1013 if (count == num_components)
1014 return value;
1015
1016 LLVMValueRef masks[] = {
1017 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1018 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1019
1020 if (count == 1)
1021 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1022 "");
1023
1024 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1025 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1026 }
1027
1028 static void
1029 build_store_values_extended(struct nir_to_llvm_context *ctx,
1030 LLVMValueRef *values,
1031 unsigned value_count,
1032 unsigned value_stride,
1033 LLVMValueRef vec)
1034 {
1035 LLVMBuilderRef builder = ctx->builder;
1036 unsigned i;
1037
1038 if (value_count == 1) {
1039 LLVMBuildStore(builder, vec, values[0]);
1040 return;
1041 }
1042
1043 for (i = 0; i < value_count; i++) {
1044 LLVMValueRef ptr = values[i * value_stride];
1045 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
1046 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1047 LLVMBuildStore(builder, value, ptr);
1048 }
1049 }
1050
1051 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
1052 nir_ssa_def *def)
1053 {
1054 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
1055 if (def->num_components > 1) {
1056 type = LLVMVectorType(type, def->num_components);
1057 }
1058 return type;
1059 }
1060
1061 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
1062 {
1063 assert(src.is_ssa);
1064 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1065 return (LLVMValueRef)entry->data;
1066 }
1067
1068
1069 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1070 struct nir_block *b)
1071 {
1072 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1073 return (LLVMBasicBlockRef)entry->data;
1074 }
1075
1076 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1077 nir_alu_src src,
1078 unsigned num_components)
1079 {
1080 LLVMValueRef value = get_src(ctx, src.src);
1081 bool need_swizzle = false;
1082
1083 assert(value);
1084 LLVMTypeRef type = LLVMTypeOf(value);
1085 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1086 ? LLVMGetVectorSize(type)
1087 : 1;
1088
1089 for (unsigned i = 0; i < num_components; ++i) {
1090 assert(src.swizzle[i] < src_components);
1091 if (src.swizzle[i] != i)
1092 need_swizzle = true;
1093 }
1094
1095 if (need_swizzle || num_components != src_components) {
1096 LLVMValueRef masks[] = {
1097 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1098 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1099 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1100 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1101
1102 if (src_components > 1 && num_components == 1) {
1103 value = LLVMBuildExtractElement(ctx->builder, value,
1104 masks[0], "");
1105 } else if (src_components == 1 && num_components > 1) {
1106 LLVMValueRef values[] = {value, value, value, value};
1107 value = ac_build_gather_values(&ctx->ac, values, num_components);
1108 } else {
1109 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1110 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1111 swizzle, "");
1112 }
1113 }
1114 assert(!src.negate);
1115 assert(!src.abs);
1116 return value;
1117 }
1118
1119 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
1120 LLVMIntPredicate pred, LLVMValueRef src0,
1121 LLVMValueRef src1)
1122 {
1123 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1124 return LLVMBuildSelect(ctx->builder, result,
1125 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1126 LLVMConstInt(ctx->i32, 0, false), "");
1127 }
1128
1129 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
1130 LLVMRealPredicate pred, LLVMValueRef src0,
1131 LLVMValueRef src1)
1132 {
1133 LLVMValueRef result;
1134 src0 = to_float(ctx, src0);
1135 src1 = to_float(ctx, src1);
1136 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1137 return LLVMBuildSelect(ctx->builder, result,
1138 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1139 LLVMConstInt(ctx->i32, 0, false), "");
1140 }
1141
1142 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
1143 const char *intrin,
1144 LLVMTypeRef result_type,
1145 LLVMValueRef src0)
1146 {
1147 char name[64];
1148 LLVMValueRef params[] = {
1149 to_float(ctx, src0),
1150 };
1151
1152 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1153 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1154 }
1155
1156 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
1157 const char *intrin,
1158 LLVMTypeRef result_type,
1159 LLVMValueRef src0, LLVMValueRef src1)
1160 {
1161 char name[64];
1162 LLVMValueRef params[] = {
1163 to_float(ctx, src0),
1164 to_float(ctx, src1),
1165 };
1166
1167 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1168 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1169 }
1170
1171 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
1172 const char *intrin,
1173 LLVMTypeRef result_type,
1174 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1175 {
1176 char name[64];
1177 LLVMValueRef params[] = {
1178 to_float(ctx, src0),
1179 to_float(ctx, src1),
1180 to_float(ctx, src2),
1181 };
1182
1183 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1184 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1185 }
1186
1187 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
1188 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1189 {
1190 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1191 ctx->i32zero, "");
1192 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1193 }
1194
1195 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1196 LLVMValueRef src0)
1197 {
1198 LLVMValueRef params[2] = {
1199 src0,
1200
1201 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1202 * add special code to check for x=0. The reason is that
1203 * the LLVM behavior for x=0 is different from what we
1204 * need here.
1205 *
1206 * The hardware already implements the correct behavior.
1207 */
1208 LLVMConstInt(ctx->i32, 1, false),
1209 };
1210 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1211 }
1212
1213 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1214 LLVMValueRef src0)
1215 {
1216 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1217 }
1218
1219 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1220 LLVMValueRef src0)
1221 {
1222 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1223 }
1224
1225 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1226 LLVMIntPredicate pred,
1227 LLVMValueRef src0, LLVMValueRef src1)
1228 {
1229 return LLVMBuildSelect(ctx->builder,
1230 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1231 src0,
1232 src1, "");
1233
1234 }
1235 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1236 LLVMValueRef src0)
1237 {
1238 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1239 LLVMBuildNeg(ctx->builder, src0, ""));
1240 }
1241
1242 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1243 LLVMValueRef src0)
1244 {
1245 LLVMValueRef cmp, val;
1246
1247 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1248 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1249 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1250 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1251 return val;
1252 }
1253
1254 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1255 LLVMValueRef src0)
1256 {
1257 LLVMValueRef cmp, val;
1258
1259 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1260 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1261 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1262 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1263 return val;
1264 }
1265
1266 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1267 LLVMValueRef src0)
1268 {
1269 const char *intr = "llvm.floor.f32";
1270 LLVMValueRef fsrc0 = to_float(ctx, src0);
1271 LLVMValueRef params[] = {
1272 fsrc0,
1273 };
1274 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1275 ctx->f32, params, 1,
1276 AC_FUNC_ATTR_READNONE);
1277 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1278 }
1279
1280 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1281 const char *intrin,
1282 LLVMValueRef src0, LLVMValueRef src1)
1283 {
1284 LLVMTypeRef ret_type;
1285 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1286 LLVMValueRef res;
1287 LLVMValueRef params[] = { src0, src1 };
1288 ret_type = LLVMStructTypeInContext(ctx->context, types,
1289 2, true);
1290
1291 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1292 params, 2, AC_FUNC_ATTR_READNONE);
1293
1294 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1295 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1296 return res;
1297 }
1298
1299 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1300 LLVMValueRef src0)
1301 {
1302 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1303 }
1304
1305 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1306 LLVMValueRef src0, LLVMValueRef src1)
1307 {
1308 LLVMValueRef dst64, result;
1309 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1310 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1311
1312 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1313 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1314 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1315 return result;
1316 }
1317
1318 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1319 LLVMValueRef src0, LLVMValueRef src1)
1320 {
1321 LLVMValueRef dst64, result;
1322 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1323 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1324
1325 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1326 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1327 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1328 return result;
1329 }
1330
1331 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1332 bool is_signed,
1333 LLVMValueRef srcs[3])
1334 {
1335 LLVMValueRef result;
1336 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1337
1338 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1339 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1340 return result;
1341 }
1342
1343 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1344 LLVMValueRef src0, LLVMValueRef src1,
1345 LLVMValueRef src2, LLVMValueRef src3)
1346 {
1347 LLVMValueRef bfi_args[3], result;
1348
1349 bfi_args[0] = LLVMBuildShl(ctx->builder,
1350 LLVMBuildSub(ctx->builder,
1351 LLVMBuildShl(ctx->builder,
1352 ctx->i32one,
1353 src3, ""),
1354 ctx->i32one, ""),
1355 src2, "");
1356 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1357 bfi_args[2] = src0;
1358
1359 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1360
1361 /* Calculate:
1362 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1363 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1364 */
1365 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1366 LLVMBuildAnd(ctx->builder, bfi_args[0],
1367 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1368
1369 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1370 return result;
1371 }
1372
1373 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1374 LLVMValueRef src0)
1375 {
1376 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1377 int i;
1378 LLVMValueRef comp[2];
1379
1380 src0 = to_float(ctx, src0);
1381 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1382 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1383 for (i = 0; i < 2; i++) {
1384 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1385 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1386 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1387 }
1388
1389 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1390 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1391
1392 return comp[0];
1393 }
1394
1395 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1396 LLVMValueRef src0)
1397 {
1398 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1399 LLVMValueRef temps[2], result, val;
1400 int i;
1401
1402 for (i = 0; i < 2; i++) {
1403 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1404 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1405 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1406 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1407 }
1408
1409 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1410 ctx->i32zero, "");
1411 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1412 ctx->i32one, "");
1413 return result;
1414 }
1415
1416 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1417 nir_op op,
1418 LLVMValueRef src0)
1419 {
1420 unsigned mask;
1421 int idx;
1422 LLVMValueRef result;
1423 ctx->has_ddxy = true;
1424
1425 if (!ctx->lds && !ctx->has_ds_bpermute)
1426 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1427 LLVMArrayType(ctx->i32, 64),
1428 "ddxy_lds", LOCAL_ADDR_SPACE);
1429
1430 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1431 mask = AC_TID_MASK_LEFT;
1432 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1433 mask = AC_TID_MASK_TOP;
1434 else
1435 mask = AC_TID_MASK_TOP_LEFT;
1436
1437 /* for DDX we want to next X pixel, DDY next Y pixel. */
1438 if (op == nir_op_fddx_fine ||
1439 op == nir_op_fddx_coarse ||
1440 op == nir_op_fddx)
1441 idx = 1;
1442 else
1443 idx = 2;
1444
1445 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1446 mask, idx, ctx->lds,
1447 src0);
1448 return result;
1449 }
1450
1451 /*
1452 * this takes an I,J coordinate pair,
1453 * and works out the X and Y derivatives.
1454 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1455 */
1456 static LLVMValueRef emit_ddxy_interp(
1457 struct nir_to_llvm_context *ctx,
1458 LLVMValueRef interp_ij)
1459 {
1460 LLVMValueRef result[4], a;
1461 unsigned i;
1462
1463 for (i = 0; i < 2; i++) {
1464 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1465 LLVMConstInt(ctx->i32, i, false), "");
1466 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1467 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1468 }
1469 return ac_build_gather_values(&ctx->ac, result, 4);
1470 }
1471
1472 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1473 {
1474 LLVMValueRef src[4], result = NULL;
1475 unsigned num_components = instr->dest.dest.ssa.num_components;
1476 unsigned src_components;
1477 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1478
1479 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1480 switch (instr->op) {
1481 case nir_op_vec2:
1482 case nir_op_vec3:
1483 case nir_op_vec4:
1484 src_components = 1;
1485 break;
1486 case nir_op_pack_half_2x16:
1487 src_components = 2;
1488 break;
1489 case nir_op_unpack_half_2x16:
1490 src_components = 1;
1491 break;
1492 default:
1493 src_components = num_components;
1494 break;
1495 }
1496 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1497 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1498
1499 switch (instr->op) {
1500 case nir_op_fmov:
1501 case nir_op_imov:
1502 result = src[0];
1503 break;
1504 case nir_op_fneg:
1505 src[0] = to_float(ctx, src[0]);
1506 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1507 break;
1508 case nir_op_ineg:
1509 result = LLVMBuildNeg(ctx->builder, src[0], "");
1510 break;
1511 case nir_op_inot:
1512 result = LLVMBuildNot(ctx->builder, src[0], "");
1513 break;
1514 case nir_op_iadd:
1515 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1516 break;
1517 case nir_op_fadd:
1518 src[0] = to_float(ctx, src[0]);
1519 src[1] = to_float(ctx, src[1]);
1520 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1521 break;
1522 case nir_op_fsub:
1523 src[0] = to_float(ctx, src[0]);
1524 src[1] = to_float(ctx, src[1]);
1525 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1526 break;
1527 case nir_op_isub:
1528 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1529 break;
1530 case nir_op_imul:
1531 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1532 break;
1533 case nir_op_imod:
1534 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1535 break;
1536 case nir_op_umod:
1537 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1538 break;
1539 case nir_op_fmod:
1540 src[0] = to_float(ctx, src[0]);
1541 src[1] = to_float(ctx, src[1]);
1542 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1543 result = emit_intrin_1f_param(ctx, "llvm.floor",
1544 to_float_type(ctx, def_type), result);
1545 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1546 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1547 break;
1548 case nir_op_frem:
1549 src[0] = to_float(ctx, src[0]);
1550 src[1] = to_float(ctx, src[1]);
1551 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1552 break;
1553 case nir_op_irem:
1554 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1555 break;
1556 case nir_op_idiv:
1557 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1558 break;
1559 case nir_op_udiv:
1560 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1561 break;
1562 case nir_op_fmul:
1563 src[0] = to_float(ctx, src[0]);
1564 src[1] = to_float(ctx, src[1]);
1565 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1566 break;
1567 case nir_op_fdiv:
1568 src[0] = to_float(ctx, src[0]);
1569 src[1] = to_float(ctx, src[1]);
1570 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1571 break;
1572 case nir_op_frcp:
1573 src[0] = to_float(ctx, src[0]);
1574 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1575 break;
1576 case nir_op_iand:
1577 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1578 break;
1579 case nir_op_ior:
1580 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1581 break;
1582 case nir_op_ixor:
1583 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1584 break;
1585 case nir_op_ishl:
1586 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1587 break;
1588 case nir_op_ishr:
1589 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1590 break;
1591 case nir_op_ushr:
1592 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1593 break;
1594 case nir_op_ilt:
1595 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1596 break;
1597 case nir_op_ine:
1598 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1599 break;
1600 case nir_op_ieq:
1601 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1602 break;
1603 case nir_op_ige:
1604 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1605 break;
1606 case nir_op_ult:
1607 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1608 break;
1609 case nir_op_uge:
1610 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1611 break;
1612 case nir_op_feq:
1613 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1614 break;
1615 case nir_op_fne:
1616 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1617 break;
1618 case nir_op_flt:
1619 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1620 break;
1621 case nir_op_fge:
1622 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1623 break;
1624 case nir_op_fabs:
1625 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1626 to_float_type(ctx, def_type), src[0]);
1627 break;
1628 case nir_op_iabs:
1629 result = emit_iabs(ctx, src[0]);
1630 break;
1631 case nir_op_imax:
1632 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1633 break;
1634 case nir_op_imin:
1635 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1636 break;
1637 case nir_op_umax:
1638 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1639 break;
1640 case nir_op_umin:
1641 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1642 break;
1643 case nir_op_isign:
1644 result = emit_isign(ctx, src[0]);
1645 break;
1646 case nir_op_fsign:
1647 src[0] = to_float(ctx, src[0]);
1648 result = emit_fsign(ctx, src[0]);
1649 break;
1650 case nir_op_ffloor:
1651 result = emit_intrin_1f_param(ctx, "llvm.floor",
1652 to_float_type(ctx, def_type), src[0]);
1653 break;
1654 case nir_op_ftrunc:
1655 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1656 to_float_type(ctx, def_type), src[0]);
1657 break;
1658 case nir_op_fceil:
1659 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1660 to_float_type(ctx, def_type), src[0]);
1661 break;
1662 case nir_op_fround_even:
1663 result = emit_intrin_1f_param(ctx, "llvm.rint",
1664 to_float_type(ctx, def_type),src[0]);
1665 break;
1666 case nir_op_ffract:
1667 result = emit_ffract(ctx, src[0]);
1668 break;
1669 case nir_op_fsin:
1670 result = emit_intrin_1f_param(ctx, "llvm.sin",
1671 to_float_type(ctx, def_type), src[0]);
1672 break;
1673 case nir_op_fcos:
1674 result = emit_intrin_1f_param(ctx, "llvm.cos",
1675 to_float_type(ctx, def_type), src[0]);
1676 break;
1677 case nir_op_fsqrt:
1678 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1679 to_float_type(ctx, def_type), src[0]);
1680 break;
1681 case nir_op_fexp2:
1682 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1683 to_float_type(ctx, def_type), src[0]);
1684 break;
1685 case nir_op_flog2:
1686 result = emit_intrin_1f_param(ctx, "llvm.log2",
1687 to_float_type(ctx, def_type), src[0]);
1688 break;
1689 case nir_op_frsq:
1690 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1691 to_float_type(ctx, def_type), src[0]);
1692 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1693 break;
1694 case nir_op_fpow:
1695 result = emit_intrin_2f_param(ctx, "llvm.pow",
1696 to_float_type(ctx, def_type), src[0], src[1]);
1697 break;
1698 case nir_op_fmax:
1699 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1700 to_float_type(ctx, def_type), src[0], src[1]);
1701 break;
1702 case nir_op_fmin:
1703 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1704 to_float_type(ctx, def_type), src[0], src[1]);
1705 break;
1706 case nir_op_ffma:
1707 result = emit_intrin_3f_param(ctx, "llvm.fma",
1708 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1709 break;
1710 case nir_op_ibitfield_extract:
1711 result = emit_bitfield_extract(ctx, true, src);
1712 break;
1713 case nir_op_ubitfield_extract:
1714 result = emit_bitfield_extract(ctx, false, src);
1715 break;
1716 case nir_op_bitfield_insert:
1717 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1718 break;
1719 case nir_op_bitfield_reverse:
1720 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1721 break;
1722 case nir_op_bit_count:
1723 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1724 break;
1725 case nir_op_vec2:
1726 case nir_op_vec3:
1727 case nir_op_vec4:
1728 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1729 src[i] = to_integer(ctx, src[i]);
1730 result = ac_build_gather_values(&ctx->ac, src, num_components);
1731 break;
1732 case nir_op_f2i32:
1733 case nir_op_f2i64:
1734 src[0] = to_float(ctx, src[0]);
1735 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1736 break;
1737 case nir_op_f2u32:
1738 case nir_op_f2u64:
1739 src[0] = to_float(ctx, src[0]);
1740 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1741 break;
1742 case nir_op_i2f32:
1743 case nir_op_i2f64:
1744 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1745 break;
1746 case nir_op_u2f32:
1747 case nir_op_u2f64:
1748 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1749 break;
1750 case nir_op_f2f64:
1751 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1752 break;
1753 case nir_op_f2f32:
1754 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1755 break;
1756 case nir_op_u2u32:
1757 case nir_op_u2u64:
1758 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1759 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1760 else
1761 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1762 break;
1763 case nir_op_i2i32:
1764 case nir_op_i2i64:
1765 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1766 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1767 else
1768 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1769 break;
1770 case nir_op_bcsel:
1771 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1772 break;
1773 case nir_op_find_lsb:
1774 result = emit_find_lsb(ctx, src[0]);
1775 break;
1776 case nir_op_ufind_msb:
1777 result = emit_ufind_msb(ctx, src[0]);
1778 break;
1779 case nir_op_ifind_msb:
1780 result = emit_ifind_msb(ctx, src[0]);
1781 break;
1782 case nir_op_uadd_carry:
1783 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1784 break;
1785 case nir_op_usub_borrow:
1786 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1787 break;
1788 case nir_op_b2f:
1789 result = emit_b2f(ctx, src[0]);
1790 break;
1791 case nir_op_fquantize2f16:
1792 src[0] = to_float(ctx, src[0]);
1793 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1794 /* need to convert back up to f32 */
1795 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1796 break;
1797 case nir_op_umul_high:
1798 result = emit_umul_high(ctx, src[0], src[1]);
1799 break;
1800 case nir_op_imul_high:
1801 result = emit_imul_high(ctx, src[0], src[1]);
1802 break;
1803 case nir_op_pack_half_2x16:
1804 result = emit_pack_half_2x16(ctx, src[0]);
1805 break;
1806 case nir_op_unpack_half_2x16:
1807 result = emit_unpack_half_2x16(ctx, src[0]);
1808 break;
1809 case nir_op_fddx:
1810 case nir_op_fddy:
1811 case nir_op_fddx_fine:
1812 case nir_op_fddy_fine:
1813 case nir_op_fddx_coarse:
1814 case nir_op_fddy_coarse:
1815 result = emit_ddxy(ctx, instr->op, src[0]);
1816 break;
1817 default:
1818 fprintf(stderr, "Unknown NIR alu instr: ");
1819 nir_print_instr(&instr->instr, stderr);
1820 fprintf(stderr, "\n");
1821 abort();
1822 }
1823
1824 if (result) {
1825 assert(instr->dest.dest.is_ssa);
1826 result = to_integer(ctx, result);
1827 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1828 result);
1829 }
1830 }
1831
1832 static void visit_load_const(struct nir_to_llvm_context *ctx,
1833 nir_load_const_instr *instr)
1834 {
1835 LLVMValueRef values[4], value = NULL;
1836 LLVMTypeRef element_type =
1837 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1838
1839 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1840 switch (instr->def.bit_size) {
1841 case 32:
1842 values[i] = LLVMConstInt(element_type,
1843 instr->value.u32[i], false);
1844 break;
1845 case 64:
1846 values[i] = LLVMConstInt(element_type,
1847 instr->value.u64[i], false);
1848 break;
1849 default:
1850 fprintf(stderr,
1851 "unsupported nir load_const bit_size: %d\n",
1852 instr->def.bit_size);
1853 abort();
1854 }
1855 }
1856 if (instr->def.num_components > 1) {
1857 value = LLVMConstVector(values, instr->def.num_components);
1858 } else
1859 value = values[0];
1860
1861 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1862 }
1863
1864 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1865 LLVMTypeRef type)
1866 {
1867 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1868 return LLVMBuildBitCast(ctx->builder, ptr,
1869 LLVMPointerType(type, addr_space), "");
1870 }
1871
1872 static LLVMValueRef
1873 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1874 {
1875 LLVMValueRef size =
1876 LLVMBuildExtractElement(ctx->builder, descriptor,
1877 LLVMConstInt(ctx->i32, 2, false), "");
1878
1879 /* VI only */
1880 if (ctx->options->chip_class >= VI && in_elements) {
1881 /* On VI, the descriptor contains the size in bytes,
1882 * but TXQ must return the size in elements.
1883 * The stride is always non-zero for resources using TXQ.
1884 */
1885 LLVMValueRef stride =
1886 LLVMBuildExtractElement(ctx->builder, descriptor,
1887 LLVMConstInt(ctx->i32, 1, false), "");
1888 stride = LLVMBuildLShr(ctx->builder, stride,
1889 LLVMConstInt(ctx->i32, 16, false), "");
1890 stride = LLVMBuildAnd(ctx->builder, stride,
1891 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1892
1893 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1894 }
1895 return size;
1896 }
1897
1898 /**
1899 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1900 * intrinsic names).
1901 */
1902 static void build_int_type_name(
1903 LLVMTypeRef type,
1904 char *buf, unsigned bufsize)
1905 {
1906 assert(bufsize >= 6);
1907
1908 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1909 snprintf(buf, bufsize, "v%ui32",
1910 LLVMGetVectorSize(type));
1911 else
1912 strcpy(buf, "i32");
1913 }
1914
1915 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1916 struct ac_image_args *args,
1917 nir_tex_instr *instr)
1918 {
1919 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1920 LLVMValueRef coord = args->addr;
1921 LLVMValueRef half_texel[2];
1922 LLVMValueRef compare_cube_wa;
1923 LLVMValueRef result;
1924 int c;
1925 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1926
1927 //TODO Rect
1928 {
1929 struct ac_image_args txq_args = { 0 };
1930
1931 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1932 txq_args.opcode = ac_image_get_resinfo;
1933 txq_args.dmask = 0xf;
1934 txq_args.addr = ctx->i32zero;
1935 txq_args.resource = args->resource;
1936 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1937
1938 for (c = 0; c < 2; c++) {
1939 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1940 LLVMConstInt(ctx->i32, c, false), "");
1941 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1942 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1943 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1944 LLVMConstReal(ctx->f32, -0.5), "");
1945 }
1946 }
1947
1948 LLVMValueRef orig_coords = args->addr;
1949
1950 for (c = 0; c < 2; c++) {
1951 LLVMValueRef tmp;
1952 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1953 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1954 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1955 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1956 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1957 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1958 }
1959
1960
1961 /*
1962 * Apparantly cube has issue with integer types that the workaround doesn't solve,
1963 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
1964 * workaround by sampling using a scaled type and converting.
1965 * This is taken from amdgpu-pro shaders.
1966 */
1967 /* NOTE this produces some ugly code compared to amdgpu-pro,
1968 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
1969 * and then reads them back. -pro generates two selects,
1970 * one s_cmp for the descriptor rewriting
1971 * one v_cmp for the coordinate and result changes.
1972 */
1973 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1974 LLVMValueRef tmp, tmp2;
1975
1976 /* workaround 8/8/8/8 uint/sint cube gather bug */
1977 /* first detect it then change to a scaled read and f2i */
1978 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
1979 tmp2 = tmp;
1980
1981 /* extract the DATA_FORMAT */
1982 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
1983 LLVMConstInt(ctx->i32, 6, false), false);
1984
1985 /* is the DATA_FORMAT == 8_8_8_8 */
1986 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
1987
1988 if (stype == GLSL_TYPE_UINT)
1989 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
1990 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
1991 LLVMConstInt(ctx->i32, 0x10000000, false), "");
1992 else
1993 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
1994 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
1995 LLVMConstInt(ctx->i32, 0x14000000, false), "");
1996
1997 /* replace the NUM FORMAT in the descriptor */
1998 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
1999 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2000
2001 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
2002
2003 /* don't modify the coordinates for this case */
2004 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2005 }
2006 args->addr = coord;
2007 result = ac_build_image_opcode(&ctx->ac, args);
2008
2009 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2010 LLVMValueRef tmp, tmp2;
2011
2012 /* if the cube workaround is in place, f2i the result. */
2013 for (c = 0; c < 4; c++) {
2014 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2015 if (stype == GLSL_TYPE_UINT)
2016 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2017 else
2018 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2019 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2020 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2021 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2022 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2023 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2024 }
2025 }
2026 return result;
2027 }
2028
2029 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
2030 nir_tex_instr *instr,
2031 struct ac_image_args *args)
2032 {
2033 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2034 return ac_build_buffer_load_format(&ctx->ac,
2035 args->resource,
2036 args->addr,
2037 LLVMConstInt(ctx->i32, 0, false),
2038 true);
2039 }
2040
2041 args->opcode = ac_image_sample;
2042 args->compare = instr->is_shadow;
2043
2044 switch (instr->op) {
2045 case nir_texop_txf:
2046 case nir_texop_txf_ms:
2047 case nir_texop_samples_identical:
2048 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2049 args->compare = false;
2050 args->offset = false;
2051 break;
2052 case nir_texop_txb:
2053 args->bias = true;
2054 break;
2055 case nir_texop_txl:
2056 args->lod = true;
2057 break;
2058 case nir_texop_txs:
2059 case nir_texop_query_levels:
2060 args->opcode = ac_image_get_resinfo;
2061 break;
2062 case nir_texop_tex:
2063 if (ctx->stage != MESA_SHADER_FRAGMENT)
2064 args->level_zero = true;
2065 break;
2066 case nir_texop_txd:
2067 args->deriv = true;
2068 break;
2069 case nir_texop_tg4:
2070 args->opcode = ac_image_gather4;
2071 args->level_zero = true;
2072 break;
2073 case nir_texop_lod:
2074 args->opcode = ac_image_get_lod;
2075 args->compare = false;
2076 args->offset = false;
2077 break;
2078 default:
2079 break;
2080 }
2081
2082 if (instr->op == nir_texop_tg4) {
2083 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2084 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2085 return radv_lower_gather4_integer(ctx, args, instr);
2086 }
2087 }
2088 return ac_build_image_opcode(&ctx->ac, args);
2089 }
2090
2091 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2092 nir_intrinsic_instr *instr)
2093 {
2094 LLVMValueRef index = get_src(ctx, instr->src[0]);
2095 unsigned desc_set = nir_intrinsic_desc_set(instr);
2096 unsigned binding = nir_intrinsic_binding(instr);
2097 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2098 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2099 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2100 unsigned base_offset = layout->binding[binding].offset;
2101 LLVMValueRef offset, stride;
2102
2103 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2104 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2105 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2106 layout->binding[binding].dynamic_offset_offset;
2107 desc_ptr = ctx->push_constants;
2108 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2109 stride = LLVMConstInt(ctx->i32, 16, false);
2110 } else
2111 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2112
2113 offset = LLVMConstInt(ctx->i32, base_offset, false);
2114 index = LLVMBuildMul(ctx->builder, index, stride, "");
2115 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2116
2117 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2118 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2119 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2120
2121 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2122 }
2123
2124 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2125 nir_intrinsic_instr *instr)
2126 {
2127 LLVMValueRef ptr, addr;
2128
2129 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2130 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2131
2132 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2133 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2134
2135 return LLVMBuildLoad(ctx->builder, ptr, "");
2136 }
2137
2138 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2139 nir_intrinsic_instr *instr)
2140 {
2141 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2142
2143 return get_buffer_size(ctx, desc, false);
2144 }
2145 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2146 nir_intrinsic_instr *instr)
2147 {
2148 const char *store_name;
2149 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2150 LLVMTypeRef data_type = ctx->f32;
2151 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2152 int components_32bit = elem_size_mult * instr->num_components;
2153 unsigned writemask = nir_intrinsic_write_mask(instr);
2154 LLVMValueRef base_data, base_offset;
2155 LLVMValueRef params[6];
2156
2157 if (ctx->stage == MESA_SHADER_FRAGMENT)
2158 ctx->shader_info->fs.writes_memory = true;
2159
2160 params[1] = get_src(ctx, instr->src[1]);
2161 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2162 params[4] = ctx->i1false; /* glc */
2163 params[5] = ctx->i1false; /* slc */
2164
2165 if (components_32bit > 1)
2166 data_type = LLVMVectorType(ctx->f32, components_32bit);
2167
2168 base_data = to_float(ctx, src_data);
2169 base_data = trim_vector(ctx, base_data, instr->num_components);
2170 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2171 data_type, "");
2172 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2173 while (writemask) {
2174 int start, count;
2175 LLVMValueRef data;
2176 LLVMValueRef offset;
2177 LLVMValueRef tmp;
2178 u_bit_scan_consecutive_range(&writemask, &start, &count);
2179
2180 /* Due to an LLVM limitation, split 3-element writes
2181 * into a 2-element and a 1-element write. */
2182 if (count == 3) {
2183 writemask |= 1 << (start + 2);
2184 count = 2;
2185 }
2186
2187 start *= elem_size_mult;
2188 count *= elem_size_mult;
2189
2190 if (count > 4) {
2191 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2192 count = 4;
2193 }
2194
2195 if (count == 4) {
2196 store_name = "llvm.amdgcn.buffer.store.v4f32";
2197 data = base_data;
2198 } else if (count == 2) {
2199 tmp = LLVMBuildExtractElement(ctx->builder,
2200 base_data, LLVMConstInt(ctx->i32, start, false), "");
2201 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2202 ctx->i32zero, "");
2203
2204 tmp = LLVMBuildExtractElement(ctx->builder,
2205 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2206 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2207 ctx->i32one, "");
2208 store_name = "llvm.amdgcn.buffer.store.v2f32";
2209
2210 } else {
2211 assert(count == 1);
2212 if (get_llvm_num_components(base_data) > 1)
2213 data = LLVMBuildExtractElement(ctx->builder, base_data,
2214 LLVMConstInt(ctx->i32, start, false), "");
2215 else
2216 data = base_data;
2217 store_name = "llvm.amdgcn.buffer.store.f32";
2218 }
2219
2220 offset = base_offset;
2221 if (start != 0) {
2222 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2223 }
2224 params[0] = data;
2225 params[3] = offset;
2226 ac_build_intrinsic(&ctx->ac, store_name,
2227 ctx->voidt, params, 6, 0);
2228 }
2229 }
2230
2231 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2232 nir_intrinsic_instr *instr)
2233 {
2234 const char *name;
2235 LLVMValueRef params[6];
2236 int arg_count = 0;
2237 if (ctx->stage == MESA_SHADER_FRAGMENT)
2238 ctx->shader_info->fs.writes_memory = true;
2239
2240 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2241 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2242 }
2243 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2244 params[arg_count++] = get_src(ctx, instr->src[0]);
2245 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2246 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2247 params[arg_count++] = ctx->i1false; /* slc */
2248
2249 switch (instr->intrinsic) {
2250 case nir_intrinsic_ssbo_atomic_add:
2251 name = "llvm.amdgcn.buffer.atomic.add";
2252 break;
2253 case nir_intrinsic_ssbo_atomic_imin:
2254 name = "llvm.amdgcn.buffer.atomic.smin";
2255 break;
2256 case nir_intrinsic_ssbo_atomic_umin:
2257 name = "llvm.amdgcn.buffer.atomic.umin";
2258 break;
2259 case nir_intrinsic_ssbo_atomic_imax:
2260 name = "llvm.amdgcn.buffer.atomic.smax";
2261 break;
2262 case nir_intrinsic_ssbo_atomic_umax:
2263 name = "llvm.amdgcn.buffer.atomic.umax";
2264 break;
2265 case nir_intrinsic_ssbo_atomic_and:
2266 name = "llvm.amdgcn.buffer.atomic.and";
2267 break;
2268 case nir_intrinsic_ssbo_atomic_or:
2269 name = "llvm.amdgcn.buffer.atomic.or";
2270 break;
2271 case nir_intrinsic_ssbo_atomic_xor:
2272 name = "llvm.amdgcn.buffer.atomic.xor";
2273 break;
2274 case nir_intrinsic_ssbo_atomic_exchange:
2275 name = "llvm.amdgcn.buffer.atomic.swap";
2276 break;
2277 case nir_intrinsic_ssbo_atomic_comp_swap:
2278 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2279 break;
2280 default:
2281 abort();
2282 }
2283
2284 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2285 }
2286
2287 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2288 nir_intrinsic_instr *instr)
2289 {
2290 LLVMValueRef results[2];
2291 int load_components;
2292 int num_components = instr->num_components;
2293 if (instr->dest.ssa.bit_size == 64)
2294 num_components *= 2;
2295
2296 for (int i = 0; i < num_components; i += load_components) {
2297 load_components = MIN2(num_components - i, 4);
2298 const char *load_name;
2299 LLVMTypeRef data_type = ctx->f32;
2300 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2301 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2302
2303 if (load_components == 3)
2304 data_type = LLVMVectorType(ctx->f32, 4);
2305 else if (load_components > 1)
2306 data_type = LLVMVectorType(ctx->f32, load_components);
2307
2308 if (load_components >= 3)
2309 load_name = "llvm.amdgcn.buffer.load.v4f32";
2310 else if (load_components == 2)
2311 load_name = "llvm.amdgcn.buffer.load.v2f32";
2312 else if (load_components == 1)
2313 load_name = "llvm.amdgcn.buffer.load.f32";
2314 else
2315 unreachable("unhandled number of components");
2316
2317 LLVMValueRef params[] = {
2318 get_src(ctx, instr->src[0]),
2319 LLVMConstInt(ctx->i32, 0, false),
2320 offset,
2321 ctx->i1false,
2322 ctx->i1false,
2323 };
2324
2325 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2326
2327 }
2328
2329 LLVMValueRef ret = results[0];
2330 if (num_components > 4 || num_components == 3) {
2331 LLVMValueRef masks[] = {
2332 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2333 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2334 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2335 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2336 };
2337
2338 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2339 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2340 results[num_components > 4 ? 1 : 0], swizzle, "");
2341 }
2342
2343 return LLVMBuildBitCast(ctx->builder, ret,
2344 get_def_type(ctx, &instr->dest.ssa), "");
2345 }
2346
2347 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2348 nir_intrinsic_instr *instr)
2349 {
2350 LLVMValueRef results[8], ret;
2351 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2352 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2353 int num_components = instr->num_components;
2354
2355 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2356
2357 if (instr->dest.ssa.bit_size == 64)
2358 num_components *= 2;
2359
2360 for (unsigned i = 0; i < num_components; ++i) {
2361 LLVMValueRef params[] = {
2362 rsrc,
2363 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2364 offset, "")
2365 };
2366 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2367 params, 2,
2368 AC_FUNC_ATTR_READNONE |
2369 AC_FUNC_ATTR_LEGACY);
2370 }
2371
2372
2373 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2374 return LLVMBuildBitCast(ctx->builder, ret,
2375 get_def_type(ctx, &instr->dest.ssa), "");
2376 }
2377
2378 static void
2379 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2380 bool vs_in, unsigned *vertex_index_out,
2381 LLVMValueRef *vertex_index_ref,
2382 unsigned *const_out, LLVMValueRef *indir_out)
2383 {
2384 unsigned const_offset = 0;
2385 nir_deref *tail = &deref->deref;
2386 LLVMValueRef offset = NULL;
2387
2388 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2389 tail = tail->child;
2390 nir_deref_array *deref_array = nir_deref_as_array(tail);
2391 if (vertex_index_out)
2392 *vertex_index_out = deref_array->base_offset;
2393
2394 if (vertex_index_ref) {
2395 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2396 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2397 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2398 }
2399 *vertex_index_ref = vtx;
2400 }
2401 }
2402
2403 if (deref->var->data.compact) {
2404 assert(tail->child->deref_type == nir_deref_type_array);
2405 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2406 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2407 /* We always lower indirect dereferences for "compact" array vars. */
2408 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2409
2410 const_offset = deref_array->base_offset;
2411 goto out;
2412 }
2413
2414 while (tail->child != NULL) {
2415 const struct glsl_type *parent_type = tail->type;
2416 tail = tail->child;
2417
2418 if (tail->deref_type == nir_deref_type_array) {
2419 nir_deref_array *deref_array = nir_deref_as_array(tail);
2420 LLVMValueRef index, stride, local_offset;
2421 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2422
2423 const_offset += size * deref_array->base_offset;
2424 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2425 continue;
2426
2427 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2428 index = get_src(ctx, deref_array->indirect);
2429 stride = LLVMConstInt(ctx->i32, size, 0);
2430 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2431
2432 if (offset)
2433 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2434 else
2435 offset = local_offset;
2436 } else if (tail->deref_type == nir_deref_type_struct) {
2437 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2438
2439 for (unsigned i = 0; i < deref_struct->index; i++) {
2440 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2441 const_offset += glsl_count_attribute_slots(ft, vs_in);
2442 }
2443 } else
2444 unreachable("unsupported deref type");
2445
2446 }
2447 out:
2448 if (const_offset && offset)
2449 offset = LLVMBuildAdd(ctx->builder, offset,
2450 LLVMConstInt(ctx->i32, const_offset, 0),
2451 "");
2452
2453 *const_out = const_offset;
2454 *indir_out = offset;
2455 }
2456
2457 static LLVMValueRef
2458 lds_load(struct nir_to_llvm_context *ctx,
2459 LLVMValueRef dw_addr)
2460 {
2461 LLVMValueRef value;
2462 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2463 return value;
2464 }
2465
2466 static void
2467 lds_store(struct nir_to_llvm_context *ctx,
2468 LLVMValueRef dw_addr, LLVMValueRef value)
2469 {
2470 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2471 ac_build_indexed_store(&ctx->ac, ctx->lds,
2472 dw_addr, value);
2473 }
2474
2475 /* The offchip buffer layout for TCS->TES is
2476 *
2477 * - attribute 0 of patch 0 vertex 0
2478 * - attribute 0 of patch 0 vertex 1
2479 * - attribute 0 of patch 0 vertex 2
2480 * ...
2481 * - attribute 0 of patch 1 vertex 0
2482 * - attribute 0 of patch 1 vertex 1
2483 * ...
2484 * - attribute 1 of patch 0 vertex 0
2485 * - attribute 1 of patch 0 vertex 1
2486 * ...
2487 * - per patch attribute 0 of patch 0
2488 * - per patch attribute 0 of patch 1
2489 * ...
2490 *
2491 * Note that every attribute has 4 components.
2492 */
2493 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2494 LLVMValueRef vertex_index,
2495 LLVMValueRef param_index)
2496 {
2497 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2498 LLVMValueRef param_stride, constant16;
2499 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2500
2501 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2502 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2503 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2504 num_patches, "");
2505
2506 constant16 = LLVMConstInt(ctx->i32, 16, false);
2507 if (vertex_index) {
2508 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2509 vertices_per_patch, "");
2510
2511 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2512 vertex_index, "");
2513
2514 param_stride = total_vertices;
2515 } else {
2516 base_addr = rel_patch_id;
2517 param_stride = num_patches;
2518 }
2519
2520 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2521 LLVMBuildMul(ctx->builder, param_index,
2522 param_stride, ""), "");
2523
2524 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2525
2526 if (!vertex_index) {
2527 LLVMValueRef patch_data_offset =
2528 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2529
2530 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2531 patch_data_offset, "");
2532 }
2533 return base_addr;
2534 }
2535
2536 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2537 unsigned param,
2538 unsigned const_index,
2539 bool is_compact,
2540 LLVMValueRef vertex_index,
2541 LLVMValueRef indir_index)
2542 {
2543 LLVMValueRef param_index;
2544
2545 if (indir_index)
2546 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2547 indir_index, "");
2548 else {
2549 if (const_index && !is_compact)
2550 param += const_index;
2551 param_index = LLVMConstInt(ctx->i32, param, false);
2552 }
2553 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2554 }
2555
2556 static void
2557 mark_tess_output(struct nir_to_llvm_context *ctx,
2558 bool is_patch, uint32_t param)
2559
2560 {
2561 if (is_patch) {
2562 ctx->tess_patch_outputs_written |= (1ull << param);
2563 } else
2564 ctx->tess_outputs_written |= (1ull << param);
2565 }
2566
2567 static LLVMValueRef
2568 get_dw_address(struct nir_to_llvm_context *ctx,
2569 LLVMValueRef dw_addr,
2570 unsigned param,
2571 unsigned const_index,
2572 bool compact_const_index,
2573 LLVMValueRef vertex_index,
2574 LLVMValueRef stride,
2575 LLVMValueRef indir_index)
2576
2577 {
2578
2579 if (vertex_index) {
2580 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2581 LLVMBuildMul(ctx->builder,
2582 vertex_index,
2583 stride, ""), "");
2584 }
2585
2586 if (indir_index)
2587 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2588 LLVMBuildMul(ctx->builder, indir_index,
2589 LLVMConstInt(ctx->i32, 4, false), ""), "");
2590 else if (const_index && !compact_const_index)
2591 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2592 LLVMConstInt(ctx->i32, const_index, false), "");
2593
2594 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2595 LLVMConstInt(ctx->i32, param * 4, false), "");
2596
2597 if (const_index && compact_const_index)
2598 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2599 LLVMConstInt(ctx->i32, const_index, false), "");
2600 return dw_addr;
2601 }
2602
2603 static LLVMValueRef
2604 load_tcs_input(struct nir_to_llvm_context *ctx,
2605 nir_intrinsic_instr *instr)
2606 {
2607 LLVMValueRef dw_addr, stride;
2608 unsigned const_index;
2609 LLVMValueRef vertex_index;
2610 LLVMValueRef indir_index;
2611 unsigned param;
2612 LLVMValueRef value[4], result;
2613 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2614 const bool is_compact = instr->variables[0]->var->data.compact;
2615 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2616 radv_get_deref_offset(ctx, instr->variables[0],
2617 false, NULL, per_vertex ? &vertex_index : NULL,
2618 &const_index, &indir_index);
2619
2620 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2621 dw_addr = get_tcs_in_current_patch_offset(ctx);
2622 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2623 indir_index);
2624
2625 for (unsigned i = 0; i < instr->num_components; i++) {
2626 value[i] = lds_load(ctx, dw_addr);
2627 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2628 ctx->i32one, "");
2629 }
2630 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2631 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2632 return result;
2633 }
2634
2635 static LLVMValueRef
2636 load_tcs_output(struct nir_to_llvm_context *ctx,
2637 nir_intrinsic_instr *instr)
2638 {
2639 LLVMValueRef dw_addr, stride;
2640 LLVMValueRef value[4], result;
2641 LLVMValueRef vertex_index = NULL;
2642 LLVMValueRef indir_index = NULL;
2643 unsigned const_index = 0;
2644 unsigned param;
2645 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2646 const bool is_compact = instr->variables[0]->var->data.compact;
2647 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2648 radv_get_deref_offset(ctx, instr->variables[0],
2649 false, NULL, per_vertex ? &vertex_index : NULL,
2650 &const_index, &indir_index);
2651
2652 if (!instr->variables[0]->var->data.patch) {
2653 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2654 dw_addr = get_tcs_out_current_patch_offset(ctx);
2655 } else {
2656 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2657 }
2658
2659 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2660 indir_index);
2661
2662 for (unsigned i = 0; i < instr->num_components; i++) {
2663 value[i] = lds_load(ctx, dw_addr);
2664 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2665 ctx->i32one, "");
2666 }
2667 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2668 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2669 return result;
2670 }
2671
2672 static void
2673 store_tcs_output(struct nir_to_llvm_context *ctx,
2674 nir_intrinsic_instr *instr,
2675 LLVMValueRef src,
2676 unsigned writemask)
2677 {
2678 LLVMValueRef stride, dw_addr;
2679 LLVMValueRef buf_addr = NULL;
2680 LLVMValueRef vertex_index = NULL;
2681 LLVMValueRef indir_index = NULL;
2682 unsigned const_index = 0;
2683 unsigned param;
2684 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2685 const bool is_compact = instr->variables[0]->var->data.compact;
2686
2687 radv_get_deref_offset(ctx, instr->variables[0],
2688 false, NULL, per_vertex ? &vertex_index : NULL,
2689 &const_index, &indir_index);
2690
2691 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2692 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2693 is_compact && const_index > 3) {
2694 const_index -= 3;
2695 param++;
2696 }
2697
2698 if (!instr->variables[0]->var->data.patch) {
2699 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2700 dw_addr = get_tcs_out_current_patch_offset(ctx);
2701 } else {
2702 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2703 }
2704
2705 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2706
2707 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2708 indir_index);
2709 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2710 vertex_index, indir_index);
2711
2712 unsigned base = is_compact ? const_index : 0;
2713 for (unsigned chan = 0; chan < 8; chan++) {
2714 bool is_tess_factor = false;
2715 if (!(writemask & (1 << chan)))
2716 continue;
2717 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2718
2719 lds_store(ctx, dw_addr, value);
2720
2721 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2722 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2723 is_tess_factor = true;
2724
2725 if (!is_tess_factor && writemask != 0xF)
2726 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2727 buf_addr, ctx->oc_lds,
2728 4 * (base + chan), 1, 0, true, false);
2729
2730 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2731 ctx->i32one, "");
2732 }
2733
2734 if (writemask == 0xF) {
2735 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2736 buf_addr, ctx->oc_lds,
2737 (base * 4), 1, 0, true, false);
2738 }
2739 }
2740
2741 static LLVMValueRef
2742 load_tes_input(struct nir_to_llvm_context *ctx,
2743 nir_intrinsic_instr *instr)
2744 {
2745 LLVMValueRef buf_addr;
2746 LLVMValueRef result;
2747 LLVMValueRef vertex_index = NULL;
2748 LLVMValueRef indir_index = NULL;
2749 unsigned const_index = 0;
2750 unsigned param;
2751 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2752 const bool is_compact = instr->variables[0]->var->data.compact;
2753
2754 radv_get_deref_offset(ctx, instr->variables[0],
2755 false, NULL, per_vertex ? &vertex_index : NULL,
2756 &const_index, &indir_index);
2757 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2758 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2759 is_compact && const_index > 3) {
2760 const_index -= 3;
2761 param++;
2762 }
2763 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2764 is_compact, vertex_index, indir_index);
2765
2766 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2767 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true);
2768 result = trim_vector(ctx, result, instr->num_components);
2769 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2770 return result;
2771 }
2772
2773 static LLVMValueRef
2774 load_gs_input(struct nir_to_llvm_context *ctx,
2775 nir_intrinsic_instr *instr)
2776 {
2777 LLVMValueRef indir_index, vtx_offset;
2778 unsigned const_index;
2779 LLVMValueRef args[9];
2780 unsigned param, vtx_offset_param;
2781 LLVMValueRef value[4], result;
2782 unsigned vertex_index;
2783 radv_get_deref_offset(ctx, instr->variables[0],
2784 false, &vertex_index, NULL,
2785 &const_index, &indir_index);
2786 vtx_offset_param = vertex_index;
2787 assert(vtx_offset_param < 6);
2788 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2789 LLVMConstInt(ctx->i32, 4, false), "");
2790
2791 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2792 for (unsigned i = 0; i < instr->num_components; i++) {
2793
2794 args[0] = ctx->esgs_ring;
2795 args[1] = vtx_offset;
2796 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2797 args[3] = ctx->i32zero;
2798 args[4] = ctx->i32one; /* OFFEN */
2799 args[5] = ctx->i32zero; /* IDXEN */
2800 args[6] = ctx->i32one; /* GLC */
2801 args[7] = ctx->i32zero; /* SLC */
2802 args[8] = ctx->i32zero; /* TFE */
2803
2804 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2805 ctx->i32, args, 9,
2806 AC_FUNC_ATTR_READONLY |
2807 AC_FUNC_ATTR_LEGACY);
2808 }
2809 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2810
2811 return result;
2812 }
2813
2814 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2815 nir_intrinsic_instr *instr)
2816 {
2817 LLVMValueRef values[8];
2818 int idx = instr->variables[0]->var->data.driver_location;
2819 int ve = instr->dest.ssa.num_components;
2820 LLVMValueRef indir_index;
2821 LLVMValueRef ret;
2822 unsigned const_index;
2823 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2824 instr->variables[0]->var->data.mode == nir_var_shader_in;
2825 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2826 &const_index, &indir_index);
2827
2828 if (instr->dest.ssa.bit_size == 64)
2829 ve *= 2;
2830
2831 switch (instr->variables[0]->var->data.mode) {
2832 case nir_var_shader_in:
2833 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2834 return load_tcs_input(ctx, instr);
2835 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2836 return load_tes_input(ctx, instr);
2837 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2838 return load_gs_input(ctx, instr);
2839 }
2840 for (unsigned chan = 0; chan < ve; chan++) {
2841 if (indir_index) {
2842 unsigned count = glsl_count_attribute_slots(
2843 instr->variables[0]->var->type,
2844 ctx->stage == MESA_SHADER_VERTEX);
2845 count -= chan / 4;
2846 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2847 &ctx->ac, ctx->inputs + idx + chan, count,
2848 4, false);
2849
2850 values[chan] = LLVMBuildExtractElement(ctx->builder,
2851 tmp_vec,
2852 indir_index, "");
2853 } else
2854 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2855 }
2856 break;
2857 case nir_var_local:
2858 for (unsigned chan = 0; chan < ve; chan++) {
2859 if (indir_index) {
2860 unsigned count = glsl_count_attribute_slots(
2861 instr->variables[0]->var->type, false);
2862 count -= chan / 4;
2863 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2864 &ctx->ac, ctx->locals + idx + chan, count,
2865 4, true);
2866
2867 values[chan] = LLVMBuildExtractElement(ctx->builder,
2868 tmp_vec,
2869 indir_index, "");
2870 } else {
2871 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2872 }
2873 }
2874 break;
2875 case nir_var_shader_out:
2876 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2877 return load_tcs_output(ctx, instr);
2878 for (unsigned chan = 0; chan < ve; chan++) {
2879 if (indir_index) {
2880 unsigned count = glsl_count_attribute_slots(
2881 instr->variables[0]->var->type, false);
2882 count -= chan / 4;
2883 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2884 &ctx->ac, ctx->outputs + idx + chan, count,
2885 4, true);
2886
2887 values[chan] = LLVMBuildExtractElement(ctx->builder,
2888 tmp_vec,
2889 indir_index, "");
2890 } else {
2891 values[chan] = LLVMBuildLoad(ctx->builder,
2892 ctx->outputs[idx + chan + const_index * 4],
2893 "");
2894 }
2895 }
2896 break;
2897 case nir_var_shared: {
2898 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2899 LLVMValueRef derived_ptr;
2900
2901 if (indir_index)
2902 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2903
2904 for (unsigned chan = 0; chan < ve; chan++) {
2905 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2906 if (indir_index)
2907 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2908 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2909
2910 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2911 }
2912 break;
2913 }
2914 default:
2915 unreachable("unhandle variable mode");
2916 }
2917 ret = ac_build_gather_values(&ctx->ac, values, ve);
2918 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2919 }
2920
2921 static void
2922 visit_store_var(struct nir_to_llvm_context *ctx,
2923 nir_intrinsic_instr *instr)
2924 {
2925 LLVMValueRef temp_ptr, value;
2926 int idx = instr->variables[0]->var->data.driver_location;
2927 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2928 int writemask = instr->const_index[0];
2929 LLVMValueRef indir_index;
2930 unsigned const_index;
2931 radv_get_deref_offset(ctx, instr->variables[0], false,
2932 NULL, NULL, &const_index, &indir_index);
2933
2934 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2935 int old_writemask = writemask;
2936
2937 src = LLVMBuildBitCast(ctx->builder, src,
2938 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2939 "");
2940
2941 writemask = 0;
2942 for (unsigned chan = 0; chan < 4; chan++) {
2943 if (old_writemask & (1 << chan))
2944 writemask |= 3u << (2 * chan);
2945 }
2946 }
2947
2948 switch (instr->variables[0]->var->data.mode) {
2949 case nir_var_shader_out:
2950
2951 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
2952 store_tcs_output(ctx, instr, src, writemask);
2953 return;
2954 }
2955
2956 for (unsigned chan = 0; chan < 8; chan++) {
2957 int stride = 4;
2958 if (!(writemask & (1 << chan)))
2959 continue;
2960
2961 value = llvm_extract_elem(ctx, src, chan);
2962
2963 if (instr->variables[0]->var->data.compact)
2964 stride = 1;
2965 if (indir_index) {
2966 unsigned count = glsl_count_attribute_slots(
2967 instr->variables[0]->var->type, false);
2968 count -= chan / 4;
2969 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2970 &ctx->ac, ctx->outputs + idx + chan, count,
2971 stride, true);
2972
2973 if (get_llvm_num_components(tmp_vec) > 1) {
2974 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2975 value, indir_index, "");
2976 } else
2977 tmp_vec = value;
2978 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2979 count, stride, tmp_vec);
2980
2981 } else {
2982 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2983
2984 LLVMBuildStore(ctx->builder, value, temp_ptr);
2985 }
2986 }
2987 break;
2988 case nir_var_local:
2989 for (unsigned chan = 0; chan < 8; chan++) {
2990 if (!(writemask & (1 << chan)))
2991 continue;
2992
2993 value = llvm_extract_elem(ctx, src, chan);
2994 if (indir_index) {
2995 unsigned count = glsl_count_attribute_slots(
2996 instr->variables[0]->var->type, false);
2997 count -= chan / 4;
2998 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2999 &ctx->ac, ctx->locals + idx + chan, count,
3000 4, true);
3001
3002 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3003 value, indir_index, "");
3004 build_store_values_extended(ctx, ctx->locals + idx + chan,
3005 count, 4, tmp_vec);
3006 } else {
3007 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3008
3009 LLVMBuildStore(ctx->builder, value, temp_ptr);
3010 }
3011 }
3012 break;
3013 case nir_var_shared: {
3014 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3015
3016 if (indir_index)
3017 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
3018
3019 for (unsigned chan = 0; chan < 8; chan++) {
3020 if (!(writemask & (1 << chan)))
3021 continue;
3022 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
3023 LLVMValueRef derived_ptr;
3024
3025 if (indir_index)
3026 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
3027
3028 value = llvm_extract_elem(ctx, src, chan);
3029 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
3030 LLVMBuildStore(ctx->builder,
3031 to_integer(ctx, value), derived_ptr);
3032 }
3033 break;
3034 }
3035 default:
3036 break;
3037 }
3038 }
3039
3040 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3041 {
3042 switch (dim) {
3043 case GLSL_SAMPLER_DIM_BUF:
3044 return 1;
3045 case GLSL_SAMPLER_DIM_1D:
3046 return array ? 2 : 1;
3047 case GLSL_SAMPLER_DIM_2D:
3048 return array ? 3 : 2;
3049 case GLSL_SAMPLER_DIM_MS:
3050 return array ? 4 : 3;
3051 case GLSL_SAMPLER_DIM_3D:
3052 case GLSL_SAMPLER_DIM_CUBE:
3053 return 3;
3054 case GLSL_SAMPLER_DIM_RECT:
3055 case GLSL_SAMPLER_DIM_SUBPASS:
3056 return 2;
3057 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3058 return 3;
3059 default:
3060 break;
3061 }
3062 return 0;
3063 }
3064
3065
3066
3067 /* Adjust the sample index according to FMASK.
3068 *
3069 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3070 * which is the identity mapping. Each nibble says which physical sample
3071 * should be fetched to get that sample.
3072 *
3073 * For example, 0x11111100 means there are only 2 samples stored and
3074 * the second sample covers 3/4 of the pixel. When reading samples 0
3075 * and 1, return physical sample 0 (determined by the first two 0s
3076 * in FMASK), otherwise return physical sample 1.
3077 *
3078 * The sample index should be adjusted as follows:
3079 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3080 */
3081 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3082 LLVMValueRef coord_x, LLVMValueRef coord_y,
3083 LLVMValueRef coord_z,
3084 LLVMValueRef sample_index,
3085 LLVMValueRef fmask_desc_ptr)
3086 {
3087 LLVMValueRef fmask_load_address[4];
3088 LLVMValueRef res;
3089
3090 fmask_load_address[0] = coord_x;
3091 fmask_load_address[1] = coord_y;
3092 if (coord_z) {
3093 fmask_load_address[2] = coord_z;
3094 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3095 }
3096
3097 struct ac_image_args args = {0};
3098
3099 args.opcode = ac_image_load;
3100 args.da = coord_z ? true : false;
3101 args.resource = fmask_desc_ptr;
3102 args.dmask = 0xf;
3103 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3104
3105 res = ac_build_image_opcode(&ctx->ac, &args);
3106
3107 res = to_integer(ctx, res);
3108 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3109 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3110
3111 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3112 res,
3113 ctx->i32zero, "");
3114
3115 LLVMValueRef sample_index4 =
3116 LLVMBuildMul(ctx->builder, sample_index, four, "");
3117 LLVMValueRef shifted_fmask =
3118 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3119 LLVMValueRef final_sample =
3120 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3121
3122 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3123 * resource descriptor is 0 (invalid),
3124 */
3125 LLVMValueRef fmask_desc =
3126 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3127 ctx->v8i32, "");
3128
3129 LLVMValueRef fmask_word1 =
3130 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3131 ctx->i32one, "");
3132
3133 LLVMValueRef word1_is_nonzero =
3134 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3135 fmask_word1, ctx->i32zero, "");
3136
3137 /* Replace the MSAA sample index. */
3138 sample_index =
3139 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3140 final_sample, sample_index, "");
3141 return sample_index;
3142 }
3143
3144 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3145 nir_intrinsic_instr *instr)
3146 {
3147 const struct glsl_type *type = instr->variables[0]->var->type;
3148 if(instr->variables[0]->deref.child)
3149 type = instr->variables[0]->deref.child->type;
3150
3151 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3152 LLVMValueRef coords[4];
3153 LLVMValueRef masks[] = {
3154 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3155 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3156 };
3157 LLVMValueRef res;
3158 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3159
3160 int count;
3161 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3162 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3163 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3164 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3165 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3166
3167 count = image_type_to_components_count(dim,
3168 glsl_sampler_type_is_array(type));
3169
3170 if (is_ms) {
3171 LLVMValueRef fmask_load_address[3];
3172 int chan;
3173
3174 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3175 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3176 if (glsl_sampler_type_is_array(type))
3177 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3178 else
3179 fmask_load_address[2] = NULL;
3180 if (add_frag_pos) {
3181 for (chan = 0; chan < 2; ++chan)
3182 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3183 }
3184 sample_index = adjust_sample_index_using_fmask(ctx,
3185 fmask_load_address[0],
3186 fmask_load_address[1],
3187 fmask_load_address[2],
3188 sample_index,
3189 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3190 }
3191 if (count == 1) {
3192 if (instr->src[0].ssa->num_components)
3193 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3194 else
3195 res = src0;
3196 } else {
3197 int chan;
3198 if (is_ms)
3199 count--;
3200 for (chan = 0; chan < count; ++chan) {
3201 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3202 }
3203
3204 if (add_frag_pos) {
3205 for (chan = 0; chan < count; ++chan)
3206 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3207 }
3208 if (is_ms) {
3209 coords[count] = sample_index;
3210 count++;
3211 }
3212
3213 if (count == 3) {
3214 coords[3] = LLVMGetUndef(ctx->i32);
3215 count = 4;
3216 }
3217 res = ac_build_gather_values(&ctx->ac, coords, count);
3218 }
3219 return res;
3220 }
3221
3222 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3223 nir_intrinsic_instr *instr)
3224 {
3225 LLVMValueRef params[7];
3226 LLVMValueRef res;
3227 char intrinsic_name[64];
3228 const nir_variable *var = instr->variables[0]->var;
3229 const struct glsl_type *type = var->type;
3230 if(instr->variables[0]->deref.child)
3231 type = instr->variables[0]->deref.child->type;
3232
3233 type = glsl_without_array(type);
3234 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3235 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3236 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3237 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3238 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3239 params[3] = ctx->i1false; /* glc */
3240 params[4] = ctx->i1false; /* slc */
3241 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3242 params, 5, 0);
3243
3244 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3245 res = to_integer(ctx, res);
3246 } else {
3247 bool is_da = glsl_sampler_type_is_array(type) ||
3248 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3249 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3250 LLVMValueRef glc = ctx->i1false;
3251 LLVMValueRef slc = ctx->i1false;
3252
3253 params[0] = get_image_coords(ctx, instr);
3254 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3255 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3256 if (HAVE_LLVM <= 0x0309) {
3257 params[3] = ctx->i1false; /* r128 */
3258 params[4] = da;
3259 params[5] = glc;
3260 params[6] = slc;
3261 } else {
3262 LLVMValueRef lwe = ctx->i1false;
3263 params[3] = glc;
3264 params[4] = slc;
3265 params[5] = lwe;
3266 params[6] = da;
3267 }
3268
3269 ac_get_image_intr_name("llvm.amdgcn.image.load",
3270 ctx->v4f32, /* vdata */
3271 LLVMTypeOf(params[0]), /* coords */
3272 LLVMTypeOf(params[1]), /* rsrc */
3273 intrinsic_name, sizeof(intrinsic_name));
3274
3275 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3276 params, 7, AC_FUNC_ATTR_READONLY);
3277 }
3278 return to_integer(ctx, res);
3279 }
3280
3281 static void visit_image_store(struct nir_to_llvm_context *ctx,
3282 nir_intrinsic_instr *instr)
3283 {
3284 LLVMValueRef params[8];
3285 char intrinsic_name[64];
3286 const nir_variable *var = instr->variables[0]->var;
3287 const struct glsl_type *type = glsl_without_array(var->type);
3288
3289 if (ctx->stage == MESA_SHADER_FRAGMENT)
3290 ctx->shader_info->fs.writes_memory = true;
3291
3292 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3293 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
3294 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3295 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3296 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3297 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3298 params[4] = ctx->i1false; /* glc */
3299 params[5] = ctx->i1false; /* slc */
3300 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3301 params, 6, 0);
3302 } else {
3303 bool is_da = glsl_sampler_type_is_array(type) ||
3304 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3305 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3306 LLVMValueRef glc = ctx->i1false;
3307 LLVMValueRef slc = ctx->i1false;
3308
3309 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
3310 params[1] = get_image_coords(ctx, instr); /* coords */
3311 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3312 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3313 if (HAVE_LLVM <= 0x0309) {
3314 params[4] = ctx->i1false; /* r128 */
3315 params[5] = da;
3316 params[6] = glc;
3317 params[7] = slc;
3318 } else {
3319 LLVMValueRef lwe = ctx->i1false;
3320 params[4] = glc;
3321 params[5] = slc;
3322 params[6] = lwe;
3323 params[7] = da;
3324 }
3325
3326 ac_get_image_intr_name("llvm.amdgcn.image.store",
3327 LLVMTypeOf(params[0]), /* vdata */
3328 LLVMTypeOf(params[1]), /* coords */
3329 LLVMTypeOf(params[2]), /* rsrc */
3330 intrinsic_name, sizeof(intrinsic_name));
3331
3332 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3333 params, 8, 0);
3334 }
3335
3336 }
3337
3338 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3339 nir_intrinsic_instr *instr)
3340 {
3341 LLVMValueRef params[6];
3342 int param_count = 0;
3343 const nir_variable *var = instr->variables[0]->var;
3344
3345 const char *base_name = "llvm.amdgcn.image.atomic";
3346 const char *atomic_name;
3347 LLVMValueRef coords;
3348 char intrinsic_name[32], coords_type[8];
3349 const struct glsl_type *type = glsl_without_array(var->type);
3350
3351 if (ctx->stage == MESA_SHADER_FRAGMENT)
3352 ctx->shader_info->fs.writes_memory = true;
3353
3354 params[param_count++] = get_src(ctx, instr->src[2]);
3355 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3356 params[param_count++] = get_src(ctx, instr->src[3]);
3357
3358 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3359 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3360 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3361 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3362 params[param_count++] = ctx->i32zero; /* voffset */
3363 params[param_count++] = ctx->i1false; /* glc */
3364 params[param_count++] = ctx->i1false; /* slc */
3365 } else {
3366 bool da = glsl_sampler_type_is_array(type) ||
3367 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3368
3369 coords = params[param_count++] = get_image_coords(ctx, instr);
3370 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3371 params[param_count++] = ctx->i1false; /* r128 */
3372 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3373 params[param_count++] = ctx->i1false; /* slc */
3374 }
3375
3376 switch (instr->intrinsic) {
3377 case nir_intrinsic_image_atomic_add:
3378 atomic_name = "add";
3379 break;
3380 case nir_intrinsic_image_atomic_min:
3381 atomic_name = "smin";
3382 break;
3383 case nir_intrinsic_image_atomic_max:
3384 atomic_name = "smax";
3385 break;
3386 case nir_intrinsic_image_atomic_and:
3387 atomic_name = "and";
3388 break;
3389 case nir_intrinsic_image_atomic_or:
3390 atomic_name = "or";
3391 break;
3392 case nir_intrinsic_image_atomic_xor:
3393 atomic_name = "xor";
3394 break;
3395 case nir_intrinsic_image_atomic_exchange:
3396 atomic_name = "swap";
3397 break;
3398 case nir_intrinsic_image_atomic_comp_swap:
3399 atomic_name = "cmpswap";
3400 break;
3401 default:
3402 abort();
3403 }
3404 build_int_type_name(LLVMTypeOf(coords),
3405 coords_type, sizeof(coords_type));
3406
3407 snprintf(intrinsic_name, sizeof(intrinsic_name),
3408 "%s.%s.%s", base_name, atomic_name, coords_type);
3409 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3410 }
3411
3412 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3413 nir_intrinsic_instr *instr)
3414 {
3415 LLVMValueRef res;
3416 const nir_variable *var = instr->variables[0]->var;
3417 const struct glsl_type *type = instr->variables[0]->var->type;
3418 bool da = glsl_sampler_type_is_array(var->type) ||
3419 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3420 if(instr->variables[0]->deref.child)
3421 type = instr->variables[0]->deref.child->type;
3422
3423 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3424 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3425
3426 struct ac_image_args args = { 0 };
3427
3428 args.da = da;
3429 args.dmask = 0xf;
3430 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3431 args.opcode = ac_image_get_resinfo;
3432 args.addr = ctx->i32zero;
3433
3434 res = ac_build_image_opcode(&ctx->ac, &args);
3435
3436 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3437 glsl_sampler_type_is_array(type)) {
3438 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3439 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3440 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3441 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3442 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3443 }
3444 return res;
3445 }
3446
3447 #define NOOP_WAITCNT 0xf7f
3448 #define LGKM_CNT 0x07f
3449 #define VM_CNT 0xf70
3450
3451 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3452 unsigned simm16)
3453 {
3454 LLVMValueRef args[1] = {
3455 LLVMConstInt(ctx->i32, simm16, false),
3456 };
3457 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3458 ctx->voidt, args, 1, 0);
3459 }
3460
3461 static void emit_barrier(struct nir_to_llvm_context *ctx)
3462 {
3463 /* SI only (thanks to a hw bug workaround):
3464 * The real barrier instruction isn’t needed, because an entire patch
3465 * always fits into a single wave.
3466 */
3467 if (ctx->options->chip_class == SI &&
3468 ctx->stage == MESA_SHADER_TESS_CTRL) {
3469 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3470 return;
3471 }
3472 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3473 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3474 }
3475
3476 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3477 nir_intrinsic_instr *instr)
3478 {
3479 LLVMValueRef cond;
3480 ctx->shader_info->fs.can_discard = true;
3481
3482 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3483 get_src(ctx, instr->src[0]),
3484 ctx->i32zero, "");
3485
3486 cond = LLVMBuildSelect(ctx->builder, cond,
3487 LLVMConstReal(ctx->f32, -1.0f),
3488 ctx->f32zero, "");
3489 ac_build_kill(&ctx->ac, cond);
3490 }
3491
3492 static LLVMValueRef
3493 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3494 {
3495 LLVMValueRef result;
3496 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3497 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3498 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3499
3500 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3501 }
3502
3503 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3504 nir_intrinsic_instr *instr)
3505 {
3506 LLVMValueRef ptr, result;
3507 int idx = instr->variables[0]->var->data.driver_location;
3508 LLVMValueRef src = get_src(ctx, instr->src[0]);
3509 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3510
3511 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3512 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3513 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3514 ptr, src, src1,
3515 LLVMAtomicOrderingSequentiallyConsistent,
3516 LLVMAtomicOrderingSequentiallyConsistent,
3517 false);
3518 } else {
3519 LLVMAtomicRMWBinOp op;
3520 switch (instr->intrinsic) {
3521 case nir_intrinsic_var_atomic_add:
3522 op = LLVMAtomicRMWBinOpAdd;
3523 break;
3524 case nir_intrinsic_var_atomic_umin:
3525 op = LLVMAtomicRMWBinOpUMin;
3526 break;
3527 case nir_intrinsic_var_atomic_umax:
3528 op = LLVMAtomicRMWBinOpUMax;
3529 break;
3530 case nir_intrinsic_var_atomic_imin:
3531 op = LLVMAtomicRMWBinOpMin;
3532 break;
3533 case nir_intrinsic_var_atomic_imax:
3534 op = LLVMAtomicRMWBinOpMax;
3535 break;
3536 case nir_intrinsic_var_atomic_and:
3537 op = LLVMAtomicRMWBinOpAnd;
3538 break;
3539 case nir_intrinsic_var_atomic_or:
3540 op = LLVMAtomicRMWBinOpOr;
3541 break;
3542 case nir_intrinsic_var_atomic_xor:
3543 op = LLVMAtomicRMWBinOpXor;
3544 break;
3545 case nir_intrinsic_var_atomic_exchange:
3546 op = LLVMAtomicRMWBinOpXchg;
3547 break;
3548 default:
3549 return NULL;
3550 }
3551
3552 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3553 LLVMAtomicOrderingSequentiallyConsistent,
3554 false);
3555 }
3556 return result;
3557 }
3558
3559 #define INTERP_CENTER 0
3560 #define INTERP_CENTROID 1
3561 #define INTERP_SAMPLE 2
3562
3563 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3564 enum glsl_interp_mode interp, unsigned location)
3565 {
3566 switch (interp) {
3567 case INTERP_MODE_FLAT:
3568 default:
3569 return NULL;
3570 case INTERP_MODE_SMOOTH:
3571 case INTERP_MODE_NONE:
3572 if (location == INTERP_CENTER)
3573 return ctx->persp_center;
3574 else if (location == INTERP_CENTROID)
3575 return ctx->persp_centroid;
3576 else if (location == INTERP_SAMPLE)
3577 return ctx->persp_sample;
3578 break;
3579 case INTERP_MODE_NOPERSPECTIVE:
3580 if (location == INTERP_CENTER)
3581 return ctx->linear_center;
3582 else if (location == INTERP_CENTROID)
3583 return ctx->linear_centroid;
3584 else if (location == INTERP_SAMPLE)
3585 return ctx->linear_sample;
3586 break;
3587 }
3588 return NULL;
3589 }
3590
3591 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3592 LLVMValueRef sample_id)
3593 {
3594 LLVMValueRef result;
3595 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3596
3597 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3598 const_array(ctx->v2f32, 64), "");
3599
3600 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3601 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3602
3603 return result;
3604 }
3605
3606 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3607 {
3608 LLVMValueRef values[2];
3609
3610 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3611 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3612 return ac_build_gather_values(&ctx->ac, values, 2);
3613 }
3614
3615 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3616 nir_intrinsic_instr *instr)
3617 {
3618 LLVMValueRef result[2];
3619 LLVMValueRef interp_param, attr_number;
3620 unsigned location;
3621 unsigned chan;
3622 LLVMValueRef src_c0, src_c1;
3623 LLVMValueRef src0;
3624 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3625 switch (instr->intrinsic) {
3626 case nir_intrinsic_interp_var_at_centroid:
3627 location = INTERP_CENTROID;
3628 break;
3629 case nir_intrinsic_interp_var_at_sample:
3630 case nir_intrinsic_interp_var_at_offset:
3631 location = INTERP_CENTER;
3632 src0 = get_src(ctx, instr->src[0]);
3633 break;
3634 default:
3635 break;
3636 }
3637
3638 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3639 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3640 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3641 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3642 LLVMValueRef sample_position;
3643 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3644
3645 /* fetch sample ID */
3646 sample_position = load_sample_position(ctx, src0);
3647
3648 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3649 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3650 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3651 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3652 }
3653 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3654 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3655
3656 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3657 LLVMValueRef ij_out[2];
3658 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3659
3660 /*
3661 * take the I then J parameters, and the DDX/Y for it, and
3662 * calculate the IJ inputs for the interpolator.
3663 * temp1 = ddx * offset/sample.x + I;
3664 * interp_param.I = ddy * offset/sample.y + temp1;
3665 * temp1 = ddx * offset/sample.x + J;
3666 * interp_param.J = ddy * offset/sample.y + temp1;
3667 */
3668 for (unsigned i = 0; i < 2; i++) {
3669 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3670 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3671 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3672 ddxy_out, ix_ll, "");
3673 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3674 ddxy_out, iy_ll, "");
3675 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3676 interp_param, ix_ll, "");
3677 LLVMValueRef temp1, temp2;
3678
3679 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3680 ctx->f32, "");
3681
3682 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3683 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3684
3685 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3686 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3687
3688 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3689 temp2, ctx->i32, "");
3690 }
3691 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3692
3693 }
3694
3695 for (chan = 0; chan < 2; chan++) {
3696 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3697
3698 if (interp_param) {
3699 interp_param = LLVMBuildBitCast(ctx->builder,
3700 interp_param, LLVMVectorType(ctx->f32, 2), "");
3701 LLVMValueRef i = LLVMBuildExtractElement(
3702 ctx->builder, interp_param, ctx->i32zero, "");
3703 LLVMValueRef j = LLVMBuildExtractElement(
3704 ctx->builder, interp_param, ctx->i32one, "");
3705
3706 result[chan] = ac_build_fs_interp(&ctx->ac,
3707 llvm_chan, attr_number,
3708 ctx->prim_mask, i, j);
3709 } else {
3710 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3711 LLVMConstInt(ctx->i32, 2, false),
3712 llvm_chan, attr_number,
3713 ctx->prim_mask);
3714 }
3715 }
3716 return ac_build_gather_values(&ctx->ac, result, 2);
3717 }
3718
3719 static void
3720 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3721 nir_intrinsic_instr *instr)
3722 {
3723 LLVMValueRef gs_next_vertex;
3724 LLVMValueRef can_emit, kill;
3725 int idx;
3726
3727 assert(instr->const_index[0] == 0);
3728 /* Write vertex attribute values to GSVS ring */
3729 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3730 ctx->gs_next_vertex,
3731 "");
3732
3733 /* If this thread has already emitted the declared maximum number of
3734 * vertices, kill it: excessive vertex emissions are not supposed to
3735 * have any effect, and GS threads have no externally observable
3736 * effects other than emitting vertices.
3737 */
3738 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3739 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3740
3741 kill = LLVMBuildSelect(ctx->builder, can_emit,
3742 LLVMConstReal(ctx->f32, 1.0f),
3743 LLVMConstReal(ctx->f32, -1.0f), "");
3744 ac_build_kill(&ctx->ac, kill);
3745
3746 /* loop num outputs */
3747 idx = 0;
3748 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3749 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3750 int length = 4;
3751 int slot = idx;
3752 int slot_inc = 1;
3753
3754 if (!(ctx->output_mask & (1ull << i)))
3755 continue;
3756
3757 if (i == VARYING_SLOT_CLIP_DIST0) {
3758 /* pack clip and cull into a single set of slots */
3759 length = ctx->num_output_clips + ctx->num_output_culls;
3760 if (length > 4)
3761 slot_inc = 2;
3762 }
3763 for (unsigned j = 0; j < length; j++) {
3764 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3765 out_ptr[j], "");
3766 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3767 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3768 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3769
3770 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3771
3772 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3773 out_val, 1,
3774 voffset, ctx->gs2vs_offset, 0,
3775 1, 1, true, true);
3776 }
3777 idx += slot_inc;
3778 }
3779
3780 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3781 ctx->i32one, "");
3782 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3783
3784 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3785 }
3786
3787 static void
3788 visit_end_primitive(struct nir_to_llvm_context *ctx,
3789 nir_intrinsic_instr *instr)
3790 {
3791 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3792 }
3793
3794 static LLVMValueRef
3795 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3796 nir_intrinsic_instr *instr)
3797 {
3798 LLVMValueRef coord[4] = {
3799 ctx->tes_u,
3800 ctx->tes_v,
3801 ctx->f32zero,
3802 ctx->f32zero,
3803 };
3804
3805 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3806 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3807 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3808
3809 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3810 return LLVMBuildBitCast(ctx->builder, result,
3811 get_def_type(ctx, &instr->dest.ssa), "");
3812 }
3813
3814 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3815 nir_intrinsic_instr *instr)
3816 {
3817 LLVMValueRef result = NULL;
3818
3819 switch (instr->intrinsic) {
3820 case nir_intrinsic_load_work_group_id: {
3821 result = ctx->workgroup_ids;
3822 break;
3823 }
3824 case nir_intrinsic_load_base_vertex: {
3825 result = ctx->base_vertex;
3826 break;
3827 }
3828 case nir_intrinsic_load_vertex_id_zero_base: {
3829 result = ctx->vertex_id;
3830 break;
3831 }
3832 case nir_intrinsic_load_local_invocation_id: {
3833 result = ctx->local_invocation_ids;
3834 break;
3835 }
3836 case nir_intrinsic_load_base_instance:
3837 result = ctx->start_instance;
3838 break;
3839 case nir_intrinsic_load_draw_id:
3840 result = ctx->draw_index;
3841 break;
3842 case nir_intrinsic_load_invocation_id:
3843 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3844 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3845 else
3846 result = ctx->gs_invocation_id;
3847 break;
3848 case nir_intrinsic_load_primitive_id:
3849 if (ctx->stage == MESA_SHADER_GEOMETRY)
3850 result = ctx->gs_prim_id;
3851 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
3852 result = ctx->tcs_patch_id;
3853 else if (ctx->stage == MESA_SHADER_TESS_EVAL)
3854 result = ctx->tes_patch_id;
3855 else
3856 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3857 break;
3858 case nir_intrinsic_load_sample_id:
3859 ctx->shader_info->fs.force_persample = true;
3860 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3861 break;
3862 case nir_intrinsic_load_sample_pos:
3863 ctx->shader_info->fs.force_persample = true;
3864 result = load_sample_pos(ctx);
3865 break;
3866 case nir_intrinsic_load_sample_mask_in:
3867 result = ctx->sample_coverage;
3868 break;
3869 case nir_intrinsic_load_front_face:
3870 result = ctx->front_face;
3871 break;
3872 case nir_intrinsic_load_instance_id:
3873 result = ctx->instance_id;
3874 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3875 ctx->shader_info->vs.vgpr_comp_cnt);
3876 break;
3877 case nir_intrinsic_load_num_work_groups:
3878 result = ctx->num_work_groups;
3879 break;
3880 case nir_intrinsic_load_local_invocation_index:
3881 result = visit_load_local_invocation_index(ctx);
3882 break;
3883 case nir_intrinsic_load_push_constant:
3884 result = visit_load_push_constant(ctx, instr);
3885 break;
3886 case nir_intrinsic_vulkan_resource_index:
3887 result = visit_vulkan_resource_index(ctx, instr);
3888 break;
3889 case nir_intrinsic_store_ssbo:
3890 visit_store_ssbo(ctx, instr);
3891 break;
3892 case nir_intrinsic_load_ssbo:
3893 result = visit_load_buffer(ctx, instr);
3894 break;
3895 case nir_intrinsic_ssbo_atomic_add:
3896 case nir_intrinsic_ssbo_atomic_imin:
3897 case nir_intrinsic_ssbo_atomic_umin:
3898 case nir_intrinsic_ssbo_atomic_imax:
3899 case nir_intrinsic_ssbo_atomic_umax:
3900 case nir_intrinsic_ssbo_atomic_and:
3901 case nir_intrinsic_ssbo_atomic_or:
3902 case nir_intrinsic_ssbo_atomic_xor:
3903 case nir_intrinsic_ssbo_atomic_exchange:
3904 case nir_intrinsic_ssbo_atomic_comp_swap:
3905 result = visit_atomic_ssbo(ctx, instr);
3906 break;
3907 case nir_intrinsic_load_ubo:
3908 result = visit_load_ubo_buffer(ctx, instr);
3909 break;
3910 case nir_intrinsic_get_buffer_size:
3911 result = visit_get_buffer_size(ctx, instr);
3912 break;
3913 case nir_intrinsic_load_var:
3914 result = visit_load_var(ctx, instr);
3915 break;
3916 case nir_intrinsic_store_var:
3917 visit_store_var(ctx, instr);
3918 break;
3919 case nir_intrinsic_image_load:
3920 result = visit_image_load(ctx, instr);
3921 break;
3922 case nir_intrinsic_image_store:
3923 visit_image_store(ctx, instr);
3924 break;
3925 case nir_intrinsic_image_atomic_add:
3926 case nir_intrinsic_image_atomic_min:
3927 case nir_intrinsic_image_atomic_max:
3928 case nir_intrinsic_image_atomic_and:
3929 case nir_intrinsic_image_atomic_or:
3930 case nir_intrinsic_image_atomic_xor:
3931 case nir_intrinsic_image_atomic_exchange:
3932 case nir_intrinsic_image_atomic_comp_swap:
3933 result = visit_image_atomic(ctx, instr);
3934 break;
3935 case nir_intrinsic_image_size:
3936 result = visit_image_size(ctx, instr);
3937 break;
3938 case nir_intrinsic_discard:
3939 ctx->shader_info->fs.can_discard = true;
3940 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3941 ctx->voidt,
3942 NULL, 0, AC_FUNC_ATTR_LEGACY);
3943 break;
3944 case nir_intrinsic_discard_if:
3945 emit_discard_if(ctx, instr);
3946 break;
3947 case nir_intrinsic_memory_barrier:
3948 emit_waitcnt(ctx, VM_CNT);
3949 break;
3950 case nir_intrinsic_barrier:
3951 emit_barrier(ctx);
3952 break;
3953 case nir_intrinsic_var_atomic_add:
3954 case nir_intrinsic_var_atomic_imin:
3955 case nir_intrinsic_var_atomic_umin:
3956 case nir_intrinsic_var_atomic_imax:
3957 case nir_intrinsic_var_atomic_umax:
3958 case nir_intrinsic_var_atomic_and:
3959 case nir_intrinsic_var_atomic_or:
3960 case nir_intrinsic_var_atomic_xor:
3961 case nir_intrinsic_var_atomic_exchange:
3962 case nir_intrinsic_var_atomic_comp_swap:
3963 result = visit_var_atomic(ctx, instr);
3964 break;
3965 case nir_intrinsic_interp_var_at_centroid:
3966 case nir_intrinsic_interp_var_at_sample:
3967 case nir_intrinsic_interp_var_at_offset:
3968 result = visit_interp(ctx, instr);
3969 break;
3970 case nir_intrinsic_emit_vertex:
3971 visit_emit_vertex(ctx, instr);
3972 break;
3973 case nir_intrinsic_end_primitive:
3974 visit_end_primitive(ctx, instr);
3975 break;
3976 case nir_intrinsic_load_tess_coord:
3977 result = visit_load_tess_coord(ctx, instr);
3978 break;
3979 case nir_intrinsic_load_patch_vertices_in:
3980 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
3981 break;
3982 default:
3983 fprintf(stderr, "Unknown intrinsic: ");
3984 nir_print_instr(&instr->instr, stderr);
3985 fprintf(stderr, "\n");
3986 break;
3987 }
3988 if (result) {
3989 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3990 }
3991 }
3992
3993 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3994 nir_deref_var *deref,
3995 enum desc_type desc_type)
3996 {
3997 unsigned desc_set = deref->var->data.descriptor_set;
3998 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3999 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4000 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
4001 unsigned offset = binding->offset;
4002 unsigned stride = binding->size;
4003 unsigned type_size;
4004 LLVMBuilderRef builder = ctx->builder;
4005 LLVMTypeRef type;
4006 LLVMValueRef index = NULL;
4007 unsigned constant_index = 0;
4008
4009 assert(deref->var->data.binding < layout->binding_count);
4010
4011 switch (desc_type) {
4012 case DESC_IMAGE:
4013 type = ctx->v8i32;
4014 type_size = 32;
4015 break;
4016 case DESC_FMASK:
4017 type = ctx->v8i32;
4018 offset += 32;
4019 type_size = 32;
4020 break;
4021 case DESC_SAMPLER:
4022 type = ctx->v4i32;
4023 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4024 offset += 64;
4025
4026 type_size = 16;
4027 break;
4028 case DESC_BUFFER:
4029 type = ctx->v4i32;
4030 type_size = 16;
4031 break;
4032 default:
4033 unreachable("invalid desc_type\n");
4034 }
4035
4036 if (deref->deref.child) {
4037 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
4038
4039 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4040 offset += child->base_offset * stride;
4041 if (child->deref_array_type == nir_deref_array_type_indirect) {
4042 index = get_src(ctx, child->indirect);
4043 }
4044
4045 constant_index = child->base_offset;
4046 }
4047 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
4048 (!index || binding->immutable_samplers_equal)) {
4049 if (binding->immutable_samplers_equal)
4050 constant_index = 0;
4051
4052 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4053
4054 LLVMValueRef constants[] = {
4055 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4056 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4057 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4058 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4059 };
4060 return ac_build_gather_values(&ctx->ac, constants, 4);
4061 }
4062
4063 assert(stride % type_size == 0);
4064
4065 if (!index)
4066 index = ctx->i32zero;
4067
4068 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4069
4070 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4071 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4072
4073 return ac_build_indexed_load_const(&ctx->ac, list, index);
4074 }
4075
4076 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4077 struct ac_image_args *args,
4078 nir_tex_instr *instr,
4079 nir_texop op,
4080 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4081 LLVMValueRef *param, unsigned count,
4082 unsigned dmask)
4083 {
4084 unsigned is_rect = 0;
4085 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4086
4087 if (op == nir_texop_lod)
4088 da = false;
4089 /* Pad to power of two vector */
4090 while (count < util_next_power_of_two(count))
4091 param[count++] = LLVMGetUndef(ctx->i32);
4092
4093 if (count > 1)
4094 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4095 else
4096 args->addr = param[0];
4097
4098 args->resource = res_ptr;
4099 args->sampler = samp_ptr;
4100
4101 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4102 args->addr = param[0];
4103 return;
4104 }
4105
4106 args->dmask = dmask;
4107 args->unorm = is_rect;
4108 args->da = da;
4109 }
4110
4111 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4112 *
4113 * SI-CI:
4114 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4115 * filtering manually. The driver sets img7 to a mask clearing
4116 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4117 * s_and_b32 samp0, samp0, img7
4118 *
4119 * VI:
4120 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4121 */
4122 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4123 LLVMValueRef res, LLVMValueRef samp)
4124 {
4125 LLVMBuilderRef builder = ctx->builder;
4126 LLVMValueRef img7, samp0;
4127
4128 if (ctx->options->chip_class >= VI)
4129 return samp;
4130
4131 img7 = LLVMBuildExtractElement(builder, res,
4132 LLVMConstInt(ctx->i32, 7, 0), "");
4133 samp0 = LLVMBuildExtractElement(builder, samp,
4134 LLVMConstInt(ctx->i32, 0, 0), "");
4135 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4136 return LLVMBuildInsertElement(builder, samp, samp0,
4137 LLVMConstInt(ctx->i32, 0, 0), "");
4138 }
4139
4140 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4141 nir_tex_instr *instr,
4142 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4143 LLVMValueRef *fmask_ptr)
4144 {
4145 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4146 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4147 else
4148 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4149 if (samp_ptr) {
4150 if (instr->sampler)
4151 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4152 else
4153 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4154 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4155 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4156 }
4157 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4158 instr->op == nir_texop_samples_identical))
4159 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4160 }
4161
4162 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4163 LLVMValueRef coord)
4164 {
4165 coord = to_float(ctx, coord);
4166 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4167 coord = to_integer(ctx, coord);
4168 return coord;
4169 }
4170
4171 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4172 {
4173 LLVMValueRef result = NULL;
4174 struct ac_image_args args = { 0 };
4175 unsigned dmask = 0xf;
4176 LLVMValueRef address[16];
4177 LLVMValueRef coords[5];
4178 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4179 LLVMValueRef bias = NULL, offsets = NULL;
4180 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4181 LLVMValueRef ddx = NULL, ddy = NULL;
4182 LLVMValueRef derivs[6];
4183 unsigned chan, count = 0;
4184 unsigned const_src = 0, num_deriv_comp = 0;
4185
4186 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4187
4188 for (unsigned i = 0; i < instr->num_srcs; i++) {
4189 switch (instr->src[i].src_type) {
4190 case nir_tex_src_coord:
4191 coord = get_src(ctx, instr->src[i].src);
4192 break;
4193 case nir_tex_src_projector:
4194 break;
4195 case nir_tex_src_comparator:
4196 comparator = get_src(ctx, instr->src[i].src);
4197 break;
4198 case nir_tex_src_offset:
4199 offsets = get_src(ctx, instr->src[i].src);
4200 const_src = i;
4201 break;
4202 case nir_tex_src_bias:
4203 bias = get_src(ctx, instr->src[i].src);
4204 break;
4205 case nir_tex_src_lod:
4206 lod = get_src(ctx, instr->src[i].src);
4207 break;
4208 case nir_tex_src_ms_index:
4209 sample_index = get_src(ctx, instr->src[i].src);
4210 break;
4211 case nir_tex_src_ms_mcs:
4212 break;
4213 case nir_tex_src_ddx:
4214 ddx = get_src(ctx, instr->src[i].src);
4215 num_deriv_comp = instr->src[i].src.ssa->num_components;
4216 break;
4217 case nir_tex_src_ddy:
4218 ddy = get_src(ctx, instr->src[i].src);
4219 break;
4220 case nir_tex_src_texture_offset:
4221 case nir_tex_src_sampler_offset:
4222 case nir_tex_src_plane:
4223 default:
4224 break;
4225 }
4226 }
4227
4228 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4229 result = get_buffer_size(ctx, res_ptr, true);
4230 goto write_result;
4231 }
4232
4233 if (instr->op == nir_texop_texture_samples) {
4234 LLVMValueRef res, samples, is_msaa;
4235 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4236 samples = LLVMBuildExtractElement(ctx->builder, res,
4237 LLVMConstInt(ctx->i32, 3, false), "");
4238 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4239 LLVMConstInt(ctx->i32, 28, false), "");
4240 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4241 LLVMConstInt(ctx->i32, 0xe, false), "");
4242 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4243 LLVMConstInt(ctx->i32, 0xe, false), "");
4244
4245 samples = LLVMBuildLShr(ctx->builder, samples,
4246 LLVMConstInt(ctx->i32, 16, false), "");
4247 samples = LLVMBuildAnd(ctx->builder, samples,
4248 LLVMConstInt(ctx->i32, 0xf, false), "");
4249 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4250 samples, "");
4251 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4252 ctx->i32one, "");
4253 result = samples;
4254 goto write_result;
4255 }
4256
4257 if (coord)
4258 for (chan = 0; chan < instr->coord_components; chan++)
4259 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4260
4261 if (offsets && instr->op != nir_texop_txf) {
4262 LLVMValueRef offset[3], pack;
4263 for (chan = 0; chan < 3; ++chan)
4264 offset[chan] = ctx->i32zero;
4265
4266 args.offset = true;
4267 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4268 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4269 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4270 LLVMConstInt(ctx->i32, 0x3f, false), "");
4271 if (chan)
4272 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4273 LLVMConstInt(ctx->i32, chan * 8, false), "");
4274 }
4275 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4276 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4277 address[count++] = pack;
4278
4279 }
4280 /* pack LOD bias value */
4281 if (instr->op == nir_texop_txb && bias) {
4282 address[count++] = bias;
4283 }
4284
4285 /* Pack depth comparison value */
4286 if (instr->is_shadow && comparator) {
4287 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4288 }
4289
4290 /* pack derivatives */
4291 if (ddx || ddy) {
4292 switch (instr->sampler_dim) {
4293 case GLSL_SAMPLER_DIM_3D:
4294 case GLSL_SAMPLER_DIM_CUBE:
4295 num_deriv_comp = 3;
4296 break;
4297 case GLSL_SAMPLER_DIM_2D:
4298 default:
4299 num_deriv_comp = 2;
4300 break;
4301 case GLSL_SAMPLER_DIM_1D:
4302 num_deriv_comp = 1;
4303 break;
4304 }
4305
4306 for (unsigned i = 0; i < num_deriv_comp; i++) {
4307 derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
4308 derivs[num_deriv_comp + i] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
4309 }
4310 }
4311
4312 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4313 if (instr->is_array && instr->op != nir_texop_lod)
4314 coords[3] = apply_round_slice(ctx, coords[3]);
4315 for (chan = 0; chan < instr->coord_components; chan++)
4316 coords[chan] = to_float(ctx, coords[chan]);
4317 if (instr->coord_components == 3)
4318 coords[3] = LLVMGetUndef(ctx->f32);
4319 ac_prepare_cube_coords(&ctx->ac,
4320 instr->op == nir_texop_txd, instr->is_array,
4321 coords, derivs);
4322 if (num_deriv_comp)
4323 num_deriv_comp--;
4324 }
4325
4326 if (ddx || ddy) {
4327 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4328 address[count++] = derivs[i];
4329 }
4330
4331 /* Pack texture coordinates */
4332 if (coord) {
4333 address[count++] = coords[0];
4334 if (instr->coord_components > 1) {
4335 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4336 coords[1] = apply_round_slice(ctx, coords[1]);
4337 }
4338 address[count++] = coords[1];
4339 }
4340 if (instr->coord_components > 2) {
4341 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4342 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4343 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4344 instr->op != nir_texop_txf) {
4345 coords[2] = apply_round_slice(ctx, coords[2]);
4346 }
4347 address[count++] = coords[2];
4348 }
4349 }
4350
4351 /* Pack LOD */
4352 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
4353 address[count++] = lod;
4354 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4355 address[count++] = sample_index;
4356 } else if(instr->op == nir_texop_txs) {
4357 count = 0;
4358 if (lod)
4359 address[count++] = lod;
4360 else
4361 address[count++] = ctx->i32zero;
4362 }
4363
4364 for (chan = 0; chan < count; chan++) {
4365 address[chan] = LLVMBuildBitCast(ctx->builder,
4366 address[chan], ctx->i32, "");
4367 }
4368
4369 if (instr->op == nir_texop_samples_identical) {
4370 LLVMValueRef txf_address[4];
4371 struct ac_image_args txf_args = { 0 };
4372 unsigned txf_count = count;
4373 memcpy(txf_address, address, sizeof(txf_address));
4374
4375 if (!instr->is_array)
4376 txf_address[2] = ctx->i32zero;
4377 txf_address[3] = ctx->i32zero;
4378
4379 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4380 fmask_ptr, NULL,
4381 txf_address, txf_count, 0xf);
4382
4383 result = build_tex_intrinsic(ctx, instr, &txf_args);
4384
4385 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4386 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
4387 goto write_result;
4388 }
4389
4390 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4391 instr->op != nir_texop_txs) {
4392 unsigned sample_chan = instr->is_array ? 3 : 2;
4393 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4394 address[0],
4395 address[1],
4396 instr->is_array ? address[2] : NULL,
4397 address[sample_chan],
4398 fmask_ptr);
4399 }
4400
4401 if (offsets && instr->op == nir_texop_txf) {
4402 nir_const_value *const_offset =
4403 nir_src_as_const_value(instr->src[const_src].src);
4404 int num_offsets = instr->src[const_src].src.ssa->num_components;
4405 assert(const_offset);
4406 num_offsets = MIN2(num_offsets, instr->coord_components);
4407 if (num_offsets > 2)
4408 address[2] = LLVMBuildAdd(ctx->builder,
4409 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4410 if (num_offsets > 1)
4411 address[1] = LLVMBuildAdd(ctx->builder,
4412 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4413 address[0] = LLVMBuildAdd(ctx->builder,
4414 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4415
4416 }
4417
4418 /* TODO TG4 support */
4419 if (instr->op == nir_texop_tg4) {
4420 if (instr->is_shadow)
4421 dmask = 1;
4422 else
4423 dmask = 1 << instr->component;
4424 }
4425 set_tex_fetch_args(ctx, &args, instr, instr->op,
4426 res_ptr, samp_ptr, address, count, dmask);
4427
4428 result = build_tex_intrinsic(ctx, instr, &args);
4429
4430 if (instr->op == nir_texop_query_levels)
4431 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4432 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4433 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4434 else if (instr->op == nir_texop_txs &&
4435 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4436 instr->is_array) {
4437 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4438 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4439 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4440 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4441 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4442 } else if (instr->dest.ssa.num_components != 4)
4443 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4444
4445 write_result:
4446 if (result) {
4447 assert(instr->dest.is_ssa);
4448 result = to_integer(ctx, result);
4449 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4450 }
4451 }
4452
4453
4454 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4455 {
4456 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4457 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4458
4459 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4460 _mesa_hash_table_insert(ctx->phis, instr, result);
4461 }
4462
4463 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4464 nir_phi_instr *instr,
4465 LLVMValueRef llvm_phi)
4466 {
4467 nir_foreach_phi_src(src, instr) {
4468 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4469 LLVMValueRef llvm_src = get_src(ctx, src->src);
4470
4471 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4472 }
4473 }
4474
4475 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4476 {
4477 struct hash_entry *entry;
4478 hash_table_foreach(ctx->phis, entry) {
4479 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4480 (LLVMValueRef)entry->data);
4481 }
4482 }
4483
4484
4485 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4486 nir_ssa_undef_instr *instr)
4487 {
4488 unsigned num_components = instr->def.num_components;
4489 LLVMValueRef undef;
4490
4491 if (num_components == 1)
4492 undef = LLVMGetUndef(ctx->i32);
4493 else {
4494 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4495 }
4496 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4497 }
4498
4499 static void visit_jump(struct nir_to_llvm_context *ctx,
4500 nir_jump_instr *instr)
4501 {
4502 switch (instr->type) {
4503 case nir_jump_break:
4504 LLVMBuildBr(ctx->builder, ctx->break_block);
4505 LLVMClearInsertionPosition(ctx->builder);
4506 break;
4507 case nir_jump_continue:
4508 LLVMBuildBr(ctx->builder, ctx->continue_block);
4509 LLVMClearInsertionPosition(ctx->builder);
4510 break;
4511 default:
4512 fprintf(stderr, "Unknown NIR jump instr: ");
4513 nir_print_instr(&instr->instr, stderr);
4514 fprintf(stderr, "\n");
4515 abort();
4516 }
4517 }
4518
4519 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4520 struct exec_list *list);
4521
4522 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4523 {
4524 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4525 nir_foreach_instr(instr, block)
4526 {
4527 switch (instr->type) {
4528 case nir_instr_type_alu:
4529 visit_alu(ctx, nir_instr_as_alu(instr));
4530 break;
4531 case nir_instr_type_load_const:
4532 visit_load_const(ctx, nir_instr_as_load_const(instr));
4533 break;
4534 case nir_instr_type_intrinsic:
4535 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4536 break;
4537 case nir_instr_type_tex:
4538 visit_tex(ctx, nir_instr_as_tex(instr));
4539 break;
4540 case nir_instr_type_phi:
4541 visit_phi(ctx, nir_instr_as_phi(instr));
4542 break;
4543 case nir_instr_type_ssa_undef:
4544 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4545 break;
4546 case nir_instr_type_jump:
4547 visit_jump(ctx, nir_instr_as_jump(instr));
4548 break;
4549 default:
4550 fprintf(stderr, "Unknown NIR instr type: ");
4551 nir_print_instr(instr, stderr);
4552 fprintf(stderr, "\n");
4553 abort();
4554 }
4555 }
4556
4557 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4558 }
4559
4560 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4561 {
4562 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4563
4564 LLVMBasicBlockRef merge_block =
4565 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4566 LLVMBasicBlockRef if_block =
4567 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4568 LLVMBasicBlockRef else_block = merge_block;
4569 if (!exec_list_is_empty(&if_stmt->else_list))
4570 else_block = LLVMAppendBasicBlockInContext(
4571 ctx->context, ctx->main_function, "");
4572
4573 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4574 LLVMConstInt(ctx->i32, 0, false), "");
4575 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4576
4577 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4578 visit_cf_list(ctx, &if_stmt->then_list);
4579 if (LLVMGetInsertBlock(ctx->builder))
4580 LLVMBuildBr(ctx->builder, merge_block);
4581
4582 if (!exec_list_is_empty(&if_stmt->else_list)) {
4583 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4584 visit_cf_list(ctx, &if_stmt->else_list);
4585 if (LLVMGetInsertBlock(ctx->builder))
4586 LLVMBuildBr(ctx->builder, merge_block);
4587 }
4588
4589 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4590 }
4591
4592 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4593 {
4594 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4595 LLVMBasicBlockRef break_parent = ctx->break_block;
4596
4597 ctx->continue_block =
4598 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4599 ctx->break_block =
4600 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4601
4602 LLVMBuildBr(ctx->builder, ctx->continue_block);
4603 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4604 visit_cf_list(ctx, &loop->body);
4605
4606 if (LLVMGetInsertBlock(ctx->builder))
4607 LLVMBuildBr(ctx->builder, ctx->continue_block);
4608 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4609
4610 ctx->continue_block = continue_parent;
4611 ctx->break_block = break_parent;
4612 }
4613
4614 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4615 struct exec_list *list)
4616 {
4617 foreach_list_typed(nir_cf_node, node, node, list)
4618 {
4619 switch (node->type) {
4620 case nir_cf_node_block:
4621 visit_block(ctx, nir_cf_node_as_block(node));
4622 break;
4623
4624 case nir_cf_node_if:
4625 visit_if(ctx, nir_cf_node_as_if(node));
4626 break;
4627
4628 case nir_cf_node_loop:
4629 visit_loop(ctx, nir_cf_node_as_loop(node));
4630 break;
4631
4632 default:
4633 assert(0);
4634 }
4635 }
4636 }
4637
4638 static void
4639 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4640 struct nir_variable *variable)
4641 {
4642 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4643 LLVMValueRef t_offset;
4644 LLVMValueRef t_list;
4645 LLVMValueRef input;
4646 LLVMValueRef buffer_index;
4647 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4648 int idx = variable->data.location;
4649 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4650
4651 variable->data.driver_location = idx * 4;
4652
4653 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4654 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4655 ctx->start_instance, "");
4656 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4657 ctx->shader_info->vs.vgpr_comp_cnt);
4658 } else
4659 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4660 ctx->base_vertex, "");
4661
4662 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4663 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4664
4665 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4666
4667 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4668 buffer_index,
4669 LLVMConstInt(ctx->i32, 0, false),
4670 true);
4671
4672 for (unsigned chan = 0; chan < 4; chan++) {
4673 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4674 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4675 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4676 input, llvm_chan, ""));
4677 }
4678 }
4679 }
4680
4681 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4682 unsigned attr,
4683 LLVMValueRef interp_param,
4684 LLVMValueRef prim_mask,
4685 LLVMValueRef result[4])
4686 {
4687 LLVMValueRef attr_number;
4688 unsigned chan;
4689 LLVMValueRef i, j;
4690 bool interp = interp_param != NULL;
4691
4692 attr_number = LLVMConstInt(ctx->i32, attr, false);
4693
4694 /* fs.constant returns the param from the middle vertex, so it's not
4695 * really useful for flat shading. It's meant to be used for custom
4696 * interpolation (but the intrinsic can't fetch from the other two
4697 * vertices).
4698 *
4699 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4700 * to do the right thing. The only reason we use fs.constant is that
4701 * fs.interp cannot be used on integers, because they can be equal
4702 * to NaN.
4703 */
4704 if (interp) {
4705 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4706 LLVMVectorType(ctx->f32, 2), "");
4707
4708 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4709 ctx->i32zero, "");
4710 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4711 ctx->i32one, "");
4712 }
4713
4714 for (chan = 0; chan < 4; chan++) {
4715 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4716
4717 if (interp) {
4718 result[chan] = ac_build_fs_interp(&ctx->ac,
4719 llvm_chan,
4720 attr_number,
4721 prim_mask, i, j);
4722 } else {
4723 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4724 LLVMConstInt(ctx->i32, 2, false),
4725 llvm_chan,
4726 attr_number,
4727 prim_mask);
4728 }
4729 }
4730 }
4731
4732 static void
4733 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4734 struct nir_variable *variable)
4735 {
4736 int idx = variable->data.location;
4737 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4738 LLVMValueRef interp;
4739
4740 variable->data.driver_location = idx * 4;
4741 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4742
4743 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4744 unsigned interp_type;
4745 if (variable->data.sample) {
4746 interp_type = INTERP_SAMPLE;
4747 ctx->shader_info->fs.force_persample = true;
4748 } else if (variable->data.centroid)
4749 interp_type = INTERP_CENTROID;
4750 else
4751 interp_type = INTERP_CENTER;
4752
4753 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4754 } else
4755 interp = NULL;
4756
4757 for (unsigned i = 0; i < attrib_count; ++i)
4758 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4759
4760 }
4761
4762 static void
4763 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4764 struct nir_variable *variable)
4765 {
4766 switch (ctx->stage) {
4767 case MESA_SHADER_VERTEX:
4768 handle_vs_input_decl(ctx, variable);
4769 break;
4770 case MESA_SHADER_FRAGMENT:
4771 handle_fs_input_decl(ctx, variable);
4772 break;
4773 default:
4774 break;
4775 }
4776
4777 }
4778
4779 static void
4780 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4781 struct nir_shader *nir)
4782 {
4783 unsigned index = 0;
4784 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4785 LLVMValueRef interp_param;
4786 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4787
4788 if (!(ctx->input_mask & (1ull << i)))
4789 continue;
4790
4791 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4792 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4793 interp_param = *inputs;
4794 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4795 inputs);
4796
4797 if (!interp_param)
4798 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4799 ++index;
4800 } else if (i == VARYING_SLOT_POS) {
4801 for(int i = 0; i < 3; ++i)
4802 inputs[i] = ctx->frag_pos[i];
4803
4804 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4805 }
4806 }
4807 ctx->shader_info->fs.num_interp = index;
4808 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4809 ctx->shader_info->fs.has_pcoord = true;
4810 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4811 ctx->shader_info->fs.prim_id_input = true;
4812 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4813 ctx->shader_info->fs.layer_input = true;
4814 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4815 }
4816
4817 static LLVMValueRef
4818 ac_build_alloca(struct nir_to_llvm_context *ctx,
4819 LLVMTypeRef type,
4820 const char *name)
4821 {
4822 LLVMBuilderRef builder = ctx->builder;
4823 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4824 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4825 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4826 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4827 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4828 LLVMValueRef res;
4829
4830 if (first_instr) {
4831 LLVMPositionBuilderBefore(first_builder, first_instr);
4832 } else {
4833 LLVMPositionBuilderAtEnd(first_builder, first_block);
4834 }
4835
4836 res = LLVMBuildAlloca(first_builder, type, name);
4837 LLVMBuildStore(builder, LLVMConstNull(type), res);
4838
4839 LLVMDisposeBuilder(first_builder);
4840
4841 return res;
4842 }
4843
4844 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4845 LLVMTypeRef type,
4846 const char *name)
4847 {
4848 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4849 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4850 return ptr;
4851 }
4852
4853 static void
4854 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4855 struct nir_variable *variable)
4856 {
4857 int idx = variable->data.location + variable->data.index;
4858 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4859 uint64_t mask_attribs;
4860 variable->data.driver_location = idx * 4;
4861
4862 /* tess ctrl has it's own load/store paths for outputs */
4863 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4864 return;
4865
4866 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4867 if (ctx->stage == MESA_SHADER_VERTEX ||
4868 ctx->stage == MESA_SHADER_TESS_EVAL ||
4869 ctx->stage == MESA_SHADER_GEOMETRY) {
4870 if (idx == VARYING_SLOT_CLIP_DIST0) {
4871 int length = ctx->num_output_clips + ctx->num_output_culls;
4872 if (ctx->stage == MESA_SHADER_VERTEX) {
4873 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4874 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4875 }
4876 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4877 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4878 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4879 }
4880
4881 if (length > 4)
4882 attrib_count = 2;
4883 else
4884 attrib_count = 1;
4885 mask_attribs = 1ull << idx;
4886 }
4887 }
4888
4889 for (unsigned i = 0; i < attrib_count; ++i) {
4890 for (unsigned chan = 0; chan < 4; chan++) {
4891 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4892 si_build_alloca_undef(ctx, ctx->f32, "");
4893 }
4894 }
4895 ctx->output_mask |= mask_attribs;
4896 }
4897
4898 static void
4899 setup_locals(struct nir_to_llvm_context *ctx,
4900 struct nir_function *func)
4901 {
4902 int i, j;
4903 ctx->num_locals = 0;
4904 nir_foreach_variable(variable, &func->impl->locals) {
4905 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4906 variable->data.driver_location = ctx->num_locals * 4;
4907 ctx->num_locals += attrib_count;
4908 }
4909 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4910 if (!ctx->locals)
4911 return;
4912
4913 for (i = 0; i < ctx->num_locals; i++) {
4914 for (j = 0; j < 4; j++) {
4915 ctx->locals[i * 4 + j] =
4916 si_build_alloca_undef(ctx, ctx->f32, "temp");
4917 }
4918 }
4919 }
4920
4921 static LLVMValueRef
4922 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4923 {
4924 v = to_float(ctx, v);
4925 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4926 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4927 }
4928
4929
4930 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4931 LLVMValueRef src0, LLVMValueRef src1)
4932 {
4933 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4934 LLVMValueRef comp[2];
4935
4936 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4937 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4938 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4939 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4940 }
4941
4942 /* Initialize arguments for the shader export intrinsic */
4943 static void
4944 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4945 LLVMValueRef *values,
4946 unsigned target,
4947 struct ac_export_args *args)
4948 {
4949 /* Default is 0xf. Adjusted below depending on the format. */
4950 args->enabled_channels = 0xf;
4951
4952 /* Specify whether the EXEC mask represents the valid mask */
4953 args->valid_mask = 0;
4954
4955 /* Specify whether this is the last export */
4956 args->done = 0;
4957
4958 /* Specify the target we are exporting */
4959 args->target = target;
4960
4961 args->compr = false;
4962 args->out[0] = LLVMGetUndef(ctx->f32);
4963 args->out[1] = LLVMGetUndef(ctx->f32);
4964 args->out[2] = LLVMGetUndef(ctx->f32);
4965 args->out[3] = LLVMGetUndef(ctx->f32);
4966
4967 if (!values)
4968 return;
4969
4970 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4971 LLVMValueRef val[4];
4972 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4973 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4974 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4975
4976 switch(col_format) {
4977 case V_028714_SPI_SHADER_ZERO:
4978 args->enabled_channels = 0; /* writemask */
4979 args->target = V_008DFC_SQ_EXP_NULL;
4980 break;
4981
4982 case V_028714_SPI_SHADER_32_R:
4983 args->enabled_channels = 1;
4984 args->out[0] = values[0];
4985 break;
4986
4987 case V_028714_SPI_SHADER_32_GR:
4988 args->enabled_channels = 0x3;
4989 args->out[0] = values[0];
4990 args->out[1] = values[1];
4991 break;
4992
4993 case V_028714_SPI_SHADER_32_AR:
4994 args->enabled_channels = 0x9;
4995 args->out[0] = values[0];
4996 args->out[3] = values[3];
4997 break;
4998
4999 case V_028714_SPI_SHADER_FP16_ABGR:
5000 args->compr = 1;
5001
5002 for (unsigned chan = 0; chan < 2; chan++) {
5003 LLVMValueRef pack_args[2] = {
5004 values[2 * chan],
5005 values[2 * chan + 1]
5006 };
5007 LLVMValueRef packed;
5008
5009 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5010 args->out[chan] = packed;
5011 }
5012 break;
5013
5014 case V_028714_SPI_SHADER_UNORM16_ABGR:
5015 for (unsigned chan = 0; chan < 4; chan++) {
5016 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5017 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5018 LLVMConstReal(ctx->f32, 65535), "");
5019 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5020 LLVMConstReal(ctx->f32, 0.5), "");
5021 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5022 ctx->i32, "");
5023 }
5024
5025 args->compr = 1;
5026 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5027 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5028 break;
5029
5030 case V_028714_SPI_SHADER_SNORM16_ABGR:
5031 for (unsigned chan = 0; chan < 4; chan++) {
5032 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
5033 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5034 LLVMConstReal(ctx->f32, 32767), "");
5035
5036 /* If positive, add 0.5, else add -0.5. */
5037 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5038 LLVMBuildSelect(ctx->builder,
5039 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5040 val[chan], ctx->f32zero, ""),
5041 LLVMConstReal(ctx->f32, 0.5),
5042 LLVMConstReal(ctx->f32, -0.5), ""), "");
5043 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5044 }
5045
5046 args->compr = 1;
5047 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5048 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5049 break;
5050
5051 case V_028714_SPI_SHADER_UINT16_ABGR: {
5052 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5053
5054 for (unsigned chan = 0; chan < 4; chan++) {
5055 val[chan] = to_integer(ctx, values[chan]);
5056 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
5057 }
5058
5059 args->compr = 1;
5060 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5061 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5062 break;
5063 }
5064
5065 case V_028714_SPI_SHADER_SINT16_ABGR: {
5066 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5067 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5068
5069 /* Clamp. */
5070 for (unsigned chan = 0; chan < 4; chan++) {
5071 val[chan] = to_integer(ctx, values[chan]);
5072 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
5073 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
5074 }
5075
5076 args->compr = 1;
5077 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5078 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5079 break;
5080 }
5081
5082 default:
5083 case V_028714_SPI_SHADER_32_ABGR:
5084 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5085 break;
5086 }
5087 } else
5088 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5089
5090 for (unsigned i = 0; i < 4; ++i)
5091 args->out[i] = to_float(ctx, args->out[i]);
5092 }
5093
5094 static void
5095 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5096 struct ac_vs_output_info *outinfo)
5097 {
5098 uint32_t param_count = 0;
5099 unsigned target;
5100 unsigned pos_idx, num_pos_exports = 0;
5101 struct ac_export_args args, pos_args[4] = {};
5102 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5103 int i;
5104
5105 outinfo->prim_id_output = 0xffffffff;
5106 outinfo->layer_output = 0xffffffff;
5107 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5108 LLVMValueRef slots[8];
5109 unsigned j;
5110
5111 if (outinfo->cull_dist_mask)
5112 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5113
5114 i = VARYING_SLOT_CLIP_DIST0;
5115 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5116 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5117 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5118
5119 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5120 slots[i] = LLVMGetUndef(ctx->f32);
5121
5122 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5123 target = V_008DFC_SQ_EXP_POS + 3;
5124 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5125 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5126 &args, sizeof(args));
5127 }
5128
5129 target = V_008DFC_SQ_EXP_POS + 2;
5130 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5131 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5132 &args, sizeof(args));
5133
5134 }
5135
5136 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5137 LLVMValueRef values[4];
5138 if (!(ctx->output_mask & (1ull << i)))
5139 continue;
5140
5141 for (unsigned j = 0; j < 4; j++)
5142 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5143 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5144
5145 if (i == VARYING_SLOT_POS) {
5146 target = V_008DFC_SQ_EXP_POS;
5147 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5148 continue;
5149 } else if (i == VARYING_SLOT_PSIZ) {
5150 outinfo->writes_pointsize = true;
5151 psize_value = values[0];
5152 continue;
5153 } else if (i == VARYING_SLOT_LAYER) {
5154 outinfo->writes_layer = true;
5155 layer_value = values[0];
5156 outinfo->layer_output = param_count;
5157 target = V_008DFC_SQ_EXP_PARAM + param_count;
5158 param_count++;
5159 } else if (i == VARYING_SLOT_VIEWPORT) {
5160 outinfo->writes_viewport_index = true;
5161 viewport_index_value = values[0];
5162 continue;
5163 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5164 outinfo->prim_id_output = param_count;
5165 target = V_008DFC_SQ_EXP_PARAM + param_count;
5166 param_count++;
5167 } else if (i >= VARYING_SLOT_VAR0) {
5168 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5169 target = V_008DFC_SQ_EXP_PARAM + param_count;
5170 param_count++;
5171 }
5172
5173 si_llvm_init_export_args(ctx, values, target, &args);
5174
5175 if (target >= V_008DFC_SQ_EXP_POS &&
5176 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5177 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5178 &args, sizeof(args));
5179 } else {
5180 ac_build_export(&ctx->ac, &args);
5181 }
5182 }
5183
5184 /* We need to add the position output manually if it's missing. */
5185 if (!pos_args[0].out[0]) {
5186 pos_args[0].enabled_channels = 0xf;
5187 pos_args[0].valid_mask = 0;
5188 pos_args[0].done = 0;
5189 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5190 pos_args[0].compr = 0;
5191 pos_args[0].out[0] = ctx->f32zero; /* X */
5192 pos_args[0].out[1] = ctx->f32zero; /* Y */
5193 pos_args[0].out[2] = ctx->f32zero; /* Z */
5194 pos_args[0].out[3] = ctx->f32one; /* W */
5195 }
5196
5197 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5198 (outinfo->writes_layer == true ? 4 : 0) |
5199 (outinfo->writes_viewport_index == true ? 8 : 0));
5200 if (mask) {
5201 pos_args[1].enabled_channels = mask;
5202 pos_args[1].valid_mask = 0;
5203 pos_args[1].done = 0;
5204 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5205 pos_args[1].compr = 0;
5206 pos_args[1].out[0] = ctx->f32zero; /* X */
5207 pos_args[1].out[1] = ctx->f32zero; /* Y */
5208 pos_args[1].out[2] = ctx->f32zero; /* Z */
5209 pos_args[1].out[3] = ctx->f32zero; /* W */
5210
5211 if (outinfo->writes_pointsize == true)
5212 pos_args[1].out[0] = psize_value;
5213 if (outinfo->writes_layer == true)
5214 pos_args[1].out[2] = layer_value;
5215 if (outinfo->writes_viewport_index == true)
5216 pos_args[1].out[3] = viewport_index_value;
5217 }
5218 for (i = 0; i < 4; i++) {
5219 if (pos_args[i].out[0])
5220 num_pos_exports++;
5221 }
5222
5223 pos_idx = 0;
5224 for (i = 0; i < 4; i++) {
5225 if (!pos_args[i].out[0])
5226 continue;
5227
5228 /* Specify the target we are exporting */
5229 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5230 if (pos_idx == num_pos_exports)
5231 pos_args[i].done = 1;
5232 ac_build_export(&ctx->ac, &pos_args[i]);
5233 }
5234
5235 outinfo->pos_exports = num_pos_exports;
5236 outinfo->param_exports = param_count;
5237 }
5238
5239 static void
5240 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5241 struct ac_es_output_info *outinfo)
5242 {
5243 int j;
5244 uint64_t max_output_written = 0;
5245 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5246 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5247 int param_index;
5248 int length = 4;
5249
5250 if (!(ctx->output_mask & (1ull << i)))
5251 continue;
5252
5253 if (i == VARYING_SLOT_CLIP_DIST0)
5254 length = ctx->num_output_clips + ctx->num_output_culls;
5255
5256 param_index = shader_io_get_unique_index(i);
5257
5258 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5259
5260 for (j = 0; j < length; j++) {
5261 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5262 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5263
5264 ac_build_buffer_store_dword(&ctx->ac,
5265 ctx->esgs_ring,
5266 out_val, 1,
5267 NULL, ctx->es2gs_offset,
5268 (4 * param_index + j) * 4,
5269 1, 1, true, true);
5270 }
5271 }
5272 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5273 }
5274
5275 static void
5276 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5277 {
5278 LLVMValueRef vertex_id = ctx->rel_auto_id;
5279 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5280 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5281 vertex_dw_stride, "");
5282
5283 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5284 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5285 int length = 4;
5286
5287 if (!(ctx->output_mask & (1ull << i)))
5288 continue;
5289
5290 if (i == VARYING_SLOT_CLIP_DIST0)
5291 length = ctx->num_output_clips + ctx->num_output_culls;
5292 int param = shader_io_get_unique_index(i);
5293 mark_tess_output(ctx, false, param);
5294 if (length > 4)
5295 mark_tess_output(ctx, false, param + 1);
5296 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5297 LLVMConstInt(ctx->i32, param * 4, false),
5298 "");
5299 for (unsigned j = 0; j < length; j++) {
5300 lds_store(ctx, dw_addr,
5301 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5302 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5303 }
5304 }
5305 }
5306
5307 struct ac_build_if_state
5308 {
5309 struct nir_to_llvm_context *ctx;
5310 LLVMValueRef condition;
5311 LLVMBasicBlockRef entry_block;
5312 LLVMBasicBlockRef true_block;
5313 LLVMBasicBlockRef false_block;
5314 LLVMBasicBlockRef merge_block;
5315 };
5316
5317 static LLVMBasicBlockRef
5318 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5319 {
5320 LLVMBasicBlockRef current_block;
5321 LLVMBasicBlockRef next_block;
5322 LLVMBasicBlockRef new_block;
5323
5324 /* get current basic block */
5325 current_block = LLVMGetInsertBlock(ctx->builder);
5326
5327 /* chqeck if there's another block after this one */
5328 next_block = LLVMGetNextBasicBlock(current_block);
5329 if (next_block) {
5330 /* insert the new block before the next block */
5331 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5332 }
5333 else {
5334 /* append new block after current block */
5335 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5336 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5337 }
5338 return new_block;
5339 }
5340
5341 static void
5342 ac_nir_build_if(struct ac_build_if_state *ifthen,
5343 struct nir_to_llvm_context *ctx,
5344 LLVMValueRef condition)
5345 {
5346 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5347
5348 memset(ifthen, 0, sizeof *ifthen);
5349 ifthen->ctx = ctx;
5350 ifthen->condition = condition;
5351 ifthen->entry_block = block;
5352
5353 /* create endif/merge basic block for the phi functions */
5354 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5355
5356 /* create/insert true_block before merge_block */
5357 ifthen->true_block =
5358 LLVMInsertBasicBlockInContext(ctx->context,
5359 ifthen->merge_block,
5360 "if-true-block");
5361
5362 /* successive code goes into the true block */
5363 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5364 }
5365
5366 /**
5367 * End a conditional.
5368 */
5369 static void
5370 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5371 {
5372 LLVMBuilderRef builder = ifthen->ctx->builder;
5373
5374 /* Insert branch to the merge block from current block */
5375 LLVMBuildBr(builder, ifthen->merge_block);
5376
5377 /*
5378 * Now patch in the various branch instructions.
5379 */
5380
5381 /* Insert the conditional branch instruction at the end of entry_block */
5382 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5383 if (ifthen->false_block) {
5384 /* we have an else clause */
5385 LLVMBuildCondBr(builder, ifthen->condition,
5386 ifthen->true_block, ifthen->false_block);
5387 }
5388 else {
5389 /* no else clause */
5390 LLVMBuildCondBr(builder, ifthen->condition,
5391 ifthen->true_block, ifthen->merge_block);
5392 }
5393
5394 /* Resume building code at end of the ifthen->merge_block */
5395 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5396 }
5397
5398 static void
5399 write_tess_factors(struct nir_to_llvm_context *ctx)
5400 {
5401 unsigned stride, outer_comps, inner_comps;
5402 struct ac_build_if_state if_ctx, inner_if_ctx;
5403 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5404 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5405 unsigned tess_inner_index, tess_outer_index;
5406 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5407 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5408 int i;
5409 emit_barrier(ctx);
5410
5411 switch (ctx->options->key.tcs.primitive_mode) {
5412 case GL_ISOLINES:
5413 stride = 2;
5414 outer_comps = 2;
5415 inner_comps = 0;
5416 break;
5417 case GL_TRIANGLES:
5418 stride = 4;
5419 outer_comps = 3;
5420 inner_comps = 1;
5421 break;
5422 case GL_QUADS:
5423 stride = 6;
5424 outer_comps = 4;
5425 inner_comps = 2;
5426 break;
5427 default:
5428 return;
5429 }
5430
5431 ac_nir_build_if(&if_ctx, ctx,
5432 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5433 invocation_id, ctx->i32zero, ""));
5434
5435 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5436 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5437
5438 mark_tess_output(ctx, true, tess_inner_index);
5439 mark_tess_output(ctx, true, tess_outer_index);
5440 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5441 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5442 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5443 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5444 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5445
5446 for (i = 0; i < 4; i++) {
5447 inner[i] = LLVMGetUndef(ctx->i32);
5448 outer[i] = LLVMGetUndef(ctx->i32);
5449 }
5450
5451 // LINES reverseal
5452 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5453 outer[0] = out[1] = lds_load(ctx, lds_outer);
5454 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5455 LLVMConstInt(ctx->i32, 1, false), "");
5456 outer[1] = out[0] = lds_load(ctx, lds_outer);
5457 } else {
5458 for (i = 0; i < outer_comps; i++) {
5459 outer[i] = out[i] =
5460 lds_load(ctx, lds_outer);
5461 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5462 LLVMConstInt(ctx->i32, 1, false), "");
5463 }
5464 for (i = 0; i < inner_comps; i++) {
5465 inner[i] = out[outer_comps+i] =
5466 lds_load(ctx, lds_inner);
5467 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5468 LLVMConstInt(ctx->i32, 1, false), "");
5469 }
5470 }
5471
5472 /* Convert the outputs to vectors for stores. */
5473 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5474 vec1 = NULL;
5475
5476 if (stride > 4)
5477 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5478
5479
5480 buffer = ctx->hs_ring_tess_factor;
5481 tf_base = ctx->tess_factor_offset;
5482 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5483 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5484
5485 ac_nir_build_if(&inner_if_ctx, ctx,
5486 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5487 rel_patch_id, ctx->i32zero, ""));
5488
5489 /* Store the dynamic HS control word. */
5490 ac_build_buffer_store_dword(&ctx->ac, buffer,
5491 LLVMConstInt(ctx->i32, 0x80000000, false),
5492 1, ctx->i32zero, tf_base,
5493 0, 1, 0, true, false);
5494 ac_nir_build_endif(&inner_if_ctx);
5495
5496 /* Store the tessellation factors. */
5497 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5498 MIN2(stride, 4), byteoffset, tf_base,
5499 4, 1, 0, true, false);
5500 if (vec1)
5501 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5502 stride - 4, byteoffset, tf_base,
5503 20, 1, 0, true, false);
5504
5505 //TODO store to offchip for TES to read - only if TES reads them
5506 if (1) {
5507 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5508 LLVMValueRef tf_inner_offset;
5509 unsigned param_outer, param_inner;
5510
5511 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5512 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5513 LLVMConstInt(ctx->i32, param_outer, 0));
5514
5515 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5516 util_next_power_of_two(outer_comps));
5517
5518 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5519 outer_comps, tf_outer_offset,
5520 ctx->oc_lds, 0, 1, 0, true, false);
5521 if (inner_comps) {
5522 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5523 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5524 LLVMConstInt(ctx->i32, param_inner, 0));
5525
5526 inner_vec = inner_comps == 1 ? inner[0] :
5527 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5528 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5529 inner_comps, tf_inner_offset,
5530 ctx->oc_lds, 0, 1, 0, true, false);
5531 }
5532 }
5533 ac_nir_build_endif(&if_ctx);
5534 }
5535
5536 static void
5537 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5538 {
5539 write_tess_factors(ctx);
5540 }
5541
5542 static void
5543 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5544 LLVMValueRef *color, unsigned param, bool is_last)
5545 {
5546
5547 struct ac_export_args args;
5548
5549 /* Export */
5550 si_llvm_init_export_args(ctx, color, param,
5551 &args);
5552
5553 if (is_last) {
5554 args.valid_mask = 1; /* whether the EXEC mask is valid */
5555 args.done = 1; /* DONE bit */
5556 } else if (!args.enabled_channels)
5557 return; /* unnecessary NULL export */
5558
5559 ac_build_export(&ctx->ac, &args);
5560 }
5561
5562 static void
5563 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5564 LLVMValueRef depth, LLVMValueRef stencil,
5565 LLVMValueRef samplemask)
5566 {
5567 struct ac_export_args args;
5568
5569 args.enabled_channels = 0;
5570 args.valid_mask = 1;
5571 args.done = 1;
5572 args.target = V_008DFC_SQ_EXP_MRTZ;
5573 args.compr = false;
5574
5575 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5576 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5577 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5578 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5579
5580 if (depth) {
5581 args.out[0] = depth;
5582 args.enabled_channels |= 0x1;
5583 }
5584
5585 if (stencil) {
5586 args.out[1] = stencil;
5587 args.enabled_channels |= 0x2;
5588 }
5589
5590 if (samplemask) {
5591 args.out[2] = samplemask;
5592 args.enabled_channels |= 0x4;
5593 }
5594
5595 /* SI (except OLAND) has a bug that it only looks
5596 * at the X writemask component. */
5597 if (ctx->options->chip_class == SI &&
5598 ctx->options->family != CHIP_OLAND)
5599 args.enabled_channels |= 0x1;
5600
5601 ac_build_export(&ctx->ac, &args);
5602 }
5603
5604 static void
5605 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5606 {
5607 unsigned index = 0;
5608 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5609
5610 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5611 LLVMValueRef values[4];
5612
5613 if (!(ctx->output_mask & (1ull << i)))
5614 continue;
5615
5616 if (i == FRAG_RESULT_DEPTH) {
5617 ctx->shader_info->fs.writes_z = true;
5618 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
5619 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5620 } else if (i == FRAG_RESULT_STENCIL) {
5621 ctx->shader_info->fs.writes_stencil = true;
5622 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
5623 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5624 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5625 ctx->shader_info->fs.writes_sample_mask = true;
5626 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
5627 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5628 } else {
5629 bool last = false;
5630 for (unsigned j = 0; j < 4; j++)
5631 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5632 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5633
5634 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5635 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5636
5637 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
5638 index++;
5639 }
5640 }
5641
5642 if (depth || stencil || samplemask)
5643 si_export_mrt_z(ctx, depth, stencil, samplemask);
5644 else if (!index)
5645 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
5646
5647 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5648 }
5649
5650 static void
5651 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5652 {
5653 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5654 }
5655
5656 static void
5657 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5658 {
5659 switch (ctx->stage) {
5660 case MESA_SHADER_VERTEX:
5661 if (ctx->options->key.vs.as_ls)
5662 handle_ls_outputs_post(ctx);
5663 else if (ctx->options->key.vs.as_es)
5664 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5665 else
5666 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5667 break;
5668 case MESA_SHADER_FRAGMENT:
5669 handle_fs_outputs_post(ctx);
5670 break;
5671 case MESA_SHADER_GEOMETRY:
5672 emit_gs_epilogue(ctx);
5673 break;
5674 case MESA_SHADER_TESS_CTRL:
5675 handle_tcs_outputs_post(ctx);
5676 break;
5677 case MESA_SHADER_TESS_EVAL:
5678 if (ctx->options->key.tes.as_es)
5679 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5680 else
5681 handle_vs_outputs_post(ctx, &ctx->shader_info->tes.outinfo);
5682 break;
5683 default:
5684 break;
5685 }
5686 }
5687
5688 static void
5689 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5690 struct nir_variable *variable, uint32_t *offset, int idx)
5691 {
5692 unsigned size = glsl_count_attribute_slots(variable->type, false);
5693 variable->data.driver_location = *offset;
5694 *offset += size;
5695 }
5696
5697 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5698 {
5699 LLVMPassManagerRef passmgr;
5700 /* Create the pass manager */
5701 passmgr = LLVMCreateFunctionPassManagerForModule(
5702 ctx->module);
5703
5704 /* This pass should eliminate all the load and store instructions */
5705 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5706
5707 /* Add some optimization passes */
5708 LLVMAddScalarReplAggregatesPass(passmgr);
5709 LLVMAddLICMPass(passmgr);
5710 LLVMAddAggressiveDCEPass(passmgr);
5711 LLVMAddCFGSimplificationPass(passmgr);
5712 LLVMAddInstructionCombiningPass(passmgr);
5713
5714 /* Run the pass */
5715 LLVMInitializeFunctionPassManager(passmgr);
5716 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5717 LLVMFinalizeFunctionPassManager(passmgr);
5718
5719 LLVMDisposeBuilder(ctx->builder);
5720 LLVMDisposePassManager(passmgr);
5721 }
5722
5723 static void
5724 ac_setup_rings(struct nir_to_llvm_context *ctx)
5725 {
5726 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5727 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5728 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5729 }
5730
5731 if (ctx->is_gs_copy_shader) {
5732 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5733 }
5734 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5735 LLVMValueRef tmp;
5736 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5737 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5738
5739 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5740
5741 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5742 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5743 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5744 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5745
5746 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5747 }
5748
5749 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5750 ctx->stage == MESA_SHADER_TESS_EVAL) {
5751 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5752 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5753 }
5754 }
5755
5756 static
5757 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5758 struct nir_shader *nir,
5759 struct ac_shader_variant_info *shader_info,
5760 const struct ac_nir_compiler_options *options)
5761 {
5762 struct nir_to_llvm_context ctx = {0};
5763 struct nir_function *func;
5764 unsigned i;
5765 ctx.options = options;
5766 ctx.shader_info = shader_info;
5767 ctx.context = LLVMContextCreate();
5768 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5769
5770 ac_llvm_context_init(&ctx.ac, ctx.context);
5771 ctx.ac.module = ctx.module;
5772
5773 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5774
5775 memset(shader_info, 0, sizeof(*shader_info));
5776
5777 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5778
5779 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5780
5781 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5782 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5783 LLVMSetDataLayout(ctx.module, data_layout_str);
5784 LLVMDisposeTargetData(data_layout);
5785 LLVMDisposeMessage(data_layout_str);
5786
5787 setup_types(&ctx);
5788
5789 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5790 ctx.ac.builder = ctx.builder;
5791 ctx.stage = nir->stage;
5792
5793 for (i = 0; i < AC_UD_MAX_SETS; i++)
5794 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5795 for (i = 0; i < AC_UD_MAX_UD; i++)
5796 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5797
5798 create_function(&ctx);
5799
5800 if (nir->stage == MESA_SHADER_COMPUTE) {
5801 int num_shared = 0;
5802 nir_foreach_variable(variable, &nir->shared)
5803 num_shared++;
5804 if (num_shared) {
5805 int idx = 0;
5806 uint32_t shared_size = 0;
5807 LLVMValueRef var;
5808 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5809 nir_foreach_variable(variable, &nir->shared) {
5810 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5811 idx++;
5812 }
5813
5814 shared_size *= 16;
5815 var = LLVMAddGlobalInAddressSpace(ctx.module,
5816 LLVMArrayType(ctx.i8, shared_size),
5817 "compute_lds",
5818 LOCAL_ADDR_SPACE);
5819 LLVMSetAlignment(var, 4);
5820 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5821 }
5822 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5823 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5824
5825 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
5826 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5827 ctx.tes_primitive_mode = nir->info->tess.primitive_mode;
5828 }
5829
5830 ac_setup_rings(&ctx);
5831
5832 nir_foreach_variable(variable, &nir->inputs)
5833 handle_shader_input_decl(&ctx, variable);
5834
5835 if (nir->stage == MESA_SHADER_FRAGMENT)
5836 handle_fs_inputs_pre(&ctx, nir);
5837
5838 ctx.num_output_clips = nir->info->clip_distance_array_size;
5839 ctx.num_output_culls = nir->info->cull_distance_array_size;
5840
5841 nir_foreach_variable(variable, &nir->outputs)
5842 handle_shader_output_decl(&ctx, variable);
5843
5844 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5845 _mesa_key_pointer_equal);
5846 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5847 _mesa_key_pointer_equal);
5848
5849 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5850
5851 setup_locals(&ctx, func);
5852
5853 visit_cf_list(&ctx, &func->impl->body);
5854 phi_post_pass(&ctx);
5855
5856 handle_shader_outputs_post(&ctx);
5857 LLVMBuildRetVoid(ctx.builder);
5858
5859 ac_llvm_finalize_module(&ctx);
5860 free(ctx.locals);
5861 ralloc_free(ctx.defs);
5862 ralloc_free(ctx.phis);
5863
5864 if (nir->stage == MESA_SHADER_GEOMETRY) {
5865 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
5866 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
5867 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5868 nir->info->gs.vertices_out;
5869 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
5870 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
5871 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
5872 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
5873 shader_info->vs.outputs_written = ctx.tess_outputs_written;
5874 }
5875
5876 return ctx.module;
5877 }
5878
5879 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
5880 {
5881 unsigned *retval = (unsigned *)context;
5882 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5883 char *description = LLVMGetDiagInfoDescription(di);
5884
5885 if (severity == LLVMDSError) {
5886 *retval = 1;
5887 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5888 description);
5889 }
5890
5891 LLVMDisposeMessage(description);
5892 }
5893
5894 static unsigned ac_llvm_compile(LLVMModuleRef M,
5895 struct ac_shader_binary *binary,
5896 LLVMTargetMachineRef tm)
5897 {
5898 unsigned retval = 0;
5899 char *err;
5900 LLVMContextRef llvm_ctx;
5901 LLVMMemoryBufferRef out_buffer;
5902 unsigned buffer_size;
5903 const char *buffer_data;
5904 LLVMBool mem_err;
5905
5906 /* Setup Diagnostic Handler*/
5907 llvm_ctx = LLVMGetModuleContext(M);
5908
5909 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5910 &retval);
5911
5912 /* Compile IR*/
5913 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5914 &err, &out_buffer);
5915
5916 /* Process Errors/Warnings */
5917 if (mem_err) {
5918 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5919 free(err);
5920 retval = 1;
5921 goto out;
5922 }
5923
5924 /* Extract Shader Code*/
5925 buffer_size = LLVMGetBufferSize(out_buffer);
5926 buffer_data = LLVMGetBufferStart(out_buffer);
5927
5928 ac_elf_read(buffer_data, buffer_size, binary);
5929
5930 /* Clean up */
5931 LLVMDisposeMemoryBuffer(out_buffer);
5932
5933 out:
5934 return retval;
5935 }
5936
5937 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5938 LLVMModuleRef llvm_module,
5939 struct ac_shader_binary *binary,
5940 struct ac_shader_config *config,
5941 struct ac_shader_variant_info *shader_info,
5942 gl_shader_stage stage,
5943 bool dump_shader, bool supports_spill)
5944 {
5945 if (dump_shader)
5946 ac_dump_module(llvm_module);
5947
5948 memset(binary, 0, sizeof(*binary));
5949 int v = ac_llvm_compile(llvm_module, binary, tm);
5950 if (v) {
5951 fprintf(stderr, "compile failed\n");
5952 }
5953
5954 if (dump_shader)
5955 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5956
5957 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5958
5959 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5960 LLVMDisposeModule(llvm_module);
5961 LLVMContextDispose(ctx);
5962
5963 if (stage == MESA_SHADER_FRAGMENT) {
5964 shader_info->num_input_vgprs = 0;
5965 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5966 shader_info->num_input_vgprs += 2;
5967 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5968 shader_info->num_input_vgprs += 2;
5969 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5970 shader_info->num_input_vgprs += 2;
5971 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5972 shader_info->num_input_vgprs += 3;
5973 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5974 shader_info->num_input_vgprs += 2;
5975 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5976 shader_info->num_input_vgprs += 2;
5977 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5978 shader_info->num_input_vgprs += 2;
5979 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5980 shader_info->num_input_vgprs += 1;
5981 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5982 shader_info->num_input_vgprs += 1;
5983 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5984 shader_info->num_input_vgprs += 1;
5985 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5986 shader_info->num_input_vgprs += 1;
5987 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5988 shader_info->num_input_vgprs += 1;
5989 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5990 shader_info->num_input_vgprs += 1;
5991 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5992 shader_info->num_input_vgprs += 1;
5993 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5994 shader_info->num_input_vgprs += 1;
5995 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5996 shader_info->num_input_vgprs += 1;
5997 }
5998 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5999
6000 /* +3 for scratch wave offset and VCC */
6001 config->num_sgprs = MAX2(config->num_sgprs,
6002 shader_info->num_input_sgprs + 3);
6003 }
6004
6005 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6006 struct ac_shader_binary *binary,
6007 struct ac_shader_config *config,
6008 struct ac_shader_variant_info *shader_info,
6009 struct nir_shader *nir,
6010 const struct ac_nir_compiler_options *options,
6011 bool dump_shader)
6012 {
6013
6014 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6015 options);
6016
6017 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6018 switch (nir->stage) {
6019 case MESA_SHADER_COMPUTE:
6020 for (int i = 0; i < 3; ++i)
6021 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
6022 break;
6023 case MESA_SHADER_FRAGMENT:
6024 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
6025 break;
6026 case MESA_SHADER_GEOMETRY:
6027 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
6028 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
6029 shader_info->gs.output_prim = nir->info->gs.output_primitive;
6030 shader_info->gs.invocations = nir->info->gs.invocations;
6031 break;
6032 case MESA_SHADER_TESS_EVAL:
6033 shader_info->tes.primitive_mode = nir->info->tess.primitive_mode;
6034 shader_info->tes.spacing = nir->info->tess.spacing;
6035 shader_info->tes.ccw = nir->info->tess.ccw;
6036 shader_info->tes.point_mode = nir->info->tess.point_mode;
6037 shader_info->tes.as_es = options->key.tes.as_es;
6038 break;
6039 case MESA_SHADER_TESS_CTRL:
6040 shader_info->tcs.tcs_vertices_out = nir->info->tess.tcs_vertices_out;
6041 break;
6042 case MESA_SHADER_VERTEX:
6043 shader_info->vs.as_es = options->key.vs.as_es;
6044 shader_info->vs.as_ls = options->key.vs.as_ls;
6045 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6046 if (options->key.vs.as_ls)
6047 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6048 break;
6049 default:
6050 break;
6051 }
6052 }
6053
6054 static void
6055 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6056 {
6057 LLVMValueRef args[9];
6058 args[0] = ctx->gsvs_ring;
6059 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6060 args[3] = ctx->i32zero;
6061 args[4] = ctx->i32one; /* OFFEN */
6062 args[5] = ctx->i32zero; /* IDXEN */
6063 args[6] = ctx->i32one; /* GLC */
6064 args[7] = ctx->i32one; /* SLC */
6065 args[8] = ctx->i32zero; /* TFE */
6066
6067 int idx = 0;
6068
6069 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6070 int length = 4;
6071 int slot = idx;
6072 int slot_inc = 1;
6073 if (!(ctx->output_mask & (1ull << i)))
6074 continue;
6075
6076 if (i == VARYING_SLOT_CLIP_DIST0) {
6077 /* unpack clip and cull from a single set of slots */
6078 length = ctx->num_output_clips + ctx->num_output_culls;
6079 if (length > 4)
6080 slot_inc = 2;
6081 }
6082
6083 for (unsigned j = 0; j < length; j++) {
6084 LLVMValueRef value;
6085 args[2] = LLVMConstInt(ctx->i32,
6086 (slot * 4 + j) *
6087 ctx->gs_max_out_vertices * 16 * 4, false);
6088
6089 value = ac_build_intrinsic(&ctx->ac,
6090 "llvm.SI.buffer.load.dword.i32.i32",
6091 ctx->i32, args, 9,
6092 AC_FUNC_ATTR_READONLY |
6093 AC_FUNC_ATTR_LEGACY);
6094
6095 LLVMBuildStore(ctx->builder,
6096 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6097 }
6098 idx += slot_inc;
6099 }
6100 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
6101 }
6102
6103 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6104 struct nir_shader *geom_shader,
6105 struct ac_shader_binary *binary,
6106 struct ac_shader_config *config,
6107 struct ac_shader_variant_info *shader_info,
6108 const struct ac_nir_compiler_options *options,
6109 bool dump_shader)
6110 {
6111 struct nir_to_llvm_context ctx = {0};
6112 ctx.context = LLVMContextCreate();
6113 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6114 ctx.options = options;
6115 ctx.shader_info = shader_info;
6116
6117 ac_llvm_context_init(&ctx.ac, ctx.context);
6118 ctx.ac.module = ctx.module;
6119
6120 ctx.is_gs_copy_shader = true;
6121 LLVMSetTarget(ctx.module, "amdgcn--");
6122 setup_types(&ctx);
6123
6124 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6125 ctx.ac.builder = ctx.builder;
6126 ctx.stage = MESA_SHADER_VERTEX;
6127
6128 create_function(&ctx);
6129
6130 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
6131 ac_setup_rings(&ctx);
6132
6133 ctx.num_output_clips = geom_shader->info->clip_distance_array_size;
6134 ctx.num_output_culls = geom_shader->info->cull_distance_array_size;
6135
6136 nir_foreach_variable(variable, &geom_shader->outputs)
6137 handle_shader_output_decl(&ctx, variable);
6138
6139 ac_gs_copy_shader_emit(&ctx);
6140
6141 LLVMBuildRetVoid(ctx.builder);
6142
6143 ac_llvm_finalize_module(&ctx);
6144
6145 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6146 MESA_SHADER_VERTEX,
6147 dump_shader, options->supports_spill);
6148 }