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ac/nir: Add loading from LDS for merged GS.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef merged_wave_info;
112 LLVMValueRef tess_factor_offset;
113 LLVMValueRef tcs_patch_id;
114 LLVMValueRef tcs_rel_ids;
115 LLVMValueRef tes_rel_patch_id;
116 LLVMValueRef tes_patch_id;
117 LLVMValueRef tes_u;
118 LLVMValueRef tes_v;
119
120 LLVMValueRef gsvs_ring_stride;
121 LLVMValueRef gsvs_num_entries;
122 LLVMValueRef gs2vs_offset;
123 LLVMValueRef gs_wave_id;
124 LLVMValueRef gs_vtx_offset[6];
125 LLVMValueRef gs_prim_id, gs_invocation_id;
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 LLVMTypeRef i1;
138 LLVMTypeRef i8;
139 LLVMTypeRef i16;
140 LLVMTypeRef i32;
141 LLVMTypeRef i64;
142 LLVMTypeRef v2i32;
143 LLVMTypeRef v3i32;
144 LLVMTypeRef v4i32;
145 LLVMTypeRef v8i32;
146 LLVMTypeRef f64;
147 LLVMTypeRef f32;
148 LLVMTypeRef f16;
149 LLVMTypeRef v2f32;
150 LLVMTypeRef v4f32;
151 LLVMTypeRef voidt;
152
153 LLVMValueRef i1true;
154 LLVMValueRef i1false;
155 LLVMValueRef i32zero;
156 LLVMValueRef i32one;
157 LLVMValueRef f32zero;
158 LLVMValueRef f32one;
159 LLVMValueRef v4f32empty;
160
161 unsigned uniform_md_kind;
162 LLVMValueRef empty_md;
163 gl_shader_stage stage;
164
165 LLVMValueRef lds;
166 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
167
168 uint64_t input_mask;
169 uint64_t output_mask;
170 uint8_t num_output_clips;
171 uint8_t num_output_culls;
172
173 bool is_gs_copy_shader;
174 LLVMValueRef gs_next_vertex;
175 unsigned gs_max_out_vertices;
176
177 unsigned tes_primitive_mode;
178 uint64_t tess_outputs_written;
179 uint64_t tess_patch_outputs_written;
180 };
181
182 static inline struct nir_to_llvm_context *
183 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
184 {
185 struct nir_to_llvm_context *ctx = NULL;
186 return container_of(abi, ctx, abi);
187 }
188
189 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
190 const nir_deref_var *deref,
191 enum ac_descriptor_type desc_type,
192 bool image, bool write);
193
194 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
195 {
196 return (index * 4) + chan;
197 }
198
199 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
200 {
201 /* handle patch indices separate */
202 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
203 return 0;
204 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
205 return 1;
206 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
207 return 2 + (slot - VARYING_SLOT_PATCH0);
208
209 if (slot == VARYING_SLOT_POS)
210 return 0;
211 if (slot == VARYING_SLOT_PSIZ)
212 return 1;
213 if (slot == VARYING_SLOT_CLIP_DIST0)
214 return 2;
215 /* 3 is reserved for clip dist as well */
216 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
217 return 4 + (slot - VARYING_SLOT_VAR0);
218 unreachable("illegal slot in get unique index\n");
219 }
220
221 static void set_llvm_calling_convention(LLVMValueRef func,
222 gl_shader_stage stage)
223 {
224 enum radeon_llvm_calling_convention calling_conv;
225
226 switch (stage) {
227 case MESA_SHADER_VERTEX:
228 case MESA_SHADER_TESS_EVAL:
229 calling_conv = RADEON_LLVM_AMDGPU_VS;
230 break;
231 case MESA_SHADER_GEOMETRY:
232 calling_conv = RADEON_LLVM_AMDGPU_GS;
233 break;
234 case MESA_SHADER_TESS_CTRL:
235 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
236 break;
237 case MESA_SHADER_FRAGMENT:
238 calling_conv = RADEON_LLVM_AMDGPU_PS;
239 break;
240 case MESA_SHADER_COMPUTE:
241 calling_conv = RADEON_LLVM_AMDGPU_CS;
242 break;
243 default:
244 unreachable("Unhandle shader type");
245 }
246
247 LLVMSetFunctionCallConv(func, calling_conv);
248 }
249
250 #define MAX_ARGS 23
251 struct arg_info {
252 LLVMTypeRef types[MAX_ARGS];
253 LLVMValueRef *assign[MAX_ARGS];
254 unsigned array_params_mask;
255 uint8_t count;
256 uint8_t user_sgpr_count;
257 uint8_t sgpr_count;
258 uint8_t num_user_sgprs_used;
259 uint8_t num_sgprs_used;
260 uint8_t num_vgprs_used;
261 };
262
263 static inline void
264 add_argument(struct arg_info *info,
265 LLVMTypeRef type, LLVMValueRef *param_ptr)
266 {
267 assert(info->count < MAX_ARGS);
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271 }
272
273 static inline void
274 add_sgpr_argument(struct arg_info *info,
275 LLVMTypeRef type, LLVMValueRef *param_ptr)
276 {
277 add_argument(info, type, param_ptr);
278 info->num_sgprs_used += ac_get_type_size(type) / 4;
279 info->sgpr_count++;
280 }
281
282 static inline void
283 add_user_sgpr_argument(struct arg_info *info,
284 LLVMTypeRef type,
285 LLVMValueRef *param_ptr)
286 {
287 add_sgpr_argument(info, type, param_ptr);
288 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
289 info->user_sgpr_count++;
290 }
291
292 static inline void
293 add_vgpr_argument(struct arg_info *info,
294 LLVMTypeRef type,
295 LLVMValueRef *param_ptr)
296 {
297 add_argument(info, type, param_ptr);
298 info->num_vgprs_used += ac_get_type_size(type) / 4;
299 }
300
301 static inline void
302 add_user_sgpr_array_argument(struct arg_info *info,
303 LLVMTypeRef type,
304 LLVMValueRef *param_ptr)
305 {
306 info->array_params_mask |= (1 << info->count);
307 add_user_sgpr_argument(info, type, param_ptr);
308 }
309
310 static void assign_arguments(LLVMValueRef main_function,
311 struct arg_info *info)
312 {
313 unsigned i;
314 for (i = 0; i < info->count; i++) {
315 if (info->assign[i])
316 *info->assign[i] = LLVMGetParam(main_function, i);
317 }
318 }
319
320 static LLVMValueRef
321 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
322 LLVMBuilderRef builder, LLVMTypeRef *return_types,
323 unsigned num_return_elems,
324 struct arg_info *args,
325 unsigned max_workgroup_size,
326 bool unsafe_math)
327 {
328 LLVMTypeRef main_function_type, ret_type;
329 LLVMBasicBlockRef main_function_body;
330
331 if (num_return_elems)
332 ret_type = LLVMStructTypeInContext(ctx, return_types,
333 num_return_elems, true);
334 else
335 ret_type = LLVMVoidTypeInContext(ctx);
336
337 /* Setup the function */
338 main_function_type =
339 LLVMFunctionType(ret_type, args->types, args->count, 0);
340 LLVMValueRef main_function =
341 LLVMAddFunction(module, "main", main_function_type);
342 main_function_body =
343 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
344 LLVMPositionBuilderAtEnd(builder, main_function_body);
345
346 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
347 for (unsigned i = 0; i < args->sgpr_count; ++i) {
348 if (args->array_params_mask & (1 << i)) {
349 LLVMValueRef P = LLVMGetParam(main_function, i);
350 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
351 ac_add_attr_dereferenceable(P, UINT64_MAX);
352 }
353 else {
354 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
355 }
356 }
357
358 if (max_workgroup_size) {
359 ac_llvm_add_target_dep_function_attr(main_function,
360 "amdgpu-max-work-group-size",
361 max_workgroup_size);
362 }
363 if (unsafe_math) {
364 /* These were copied from some LLVM test. */
365 LLVMAddTargetDependentFunctionAttr(main_function,
366 "less-precise-fpmad",
367 "true");
368 LLVMAddTargetDependentFunctionAttr(main_function,
369 "no-infs-fp-math",
370 "true");
371 LLVMAddTargetDependentFunctionAttr(main_function,
372 "no-nans-fp-math",
373 "true");
374 LLVMAddTargetDependentFunctionAttr(main_function,
375 "unsafe-fp-math",
376 "true");
377 }
378 return main_function;
379 }
380
381 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
382 {
383 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
384 CONST_ADDR_SPACE);
385 }
386
387 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
388 {
389 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
390 type = LLVMGetElementType(type);
391
392 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
393 return LLVMGetIntTypeWidth(type);
394
395 if (type == ctx->f16)
396 return 16;
397 if (type == ctx->f32)
398 return 32;
399 if (type == ctx->f64)
400 return 64;
401
402 unreachable("Unhandled type kind in get_elem_bits");
403 }
404
405 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
406 LLVMValueRef param, unsigned rshift,
407 unsigned bitwidth)
408 {
409 LLVMValueRef value = param;
410 if (rshift)
411 value = LLVMBuildLShr(ctx->builder, value,
412 LLVMConstInt(ctx->i32, rshift, false), "");
413
414 if (rshift + bitwidth < 32) {
415 unsigned mask = (1 << bitwidth) - 1;
416 value = LLVMBuildAnd(ctx->builder, value,
417 LLVMConstInt(ctx->i32, mask, false), "");
418 }
419 return value;
420 }
421
422 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
423 {
424 switch (ctx->stage) {
425 case MESA_SHADER_TESS_CTRL:
426 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
427 case MESA_SHADER_TESS_EVAL:
428 return ctx->tes_rel_patch_id;
429 break;
430 default:
431 unreachable("Illegal stage");
432 }
433 }
434
435 /* Tessellation shaders pass outputs to the next shader using LDS.
436 *
437 * LS outputs = TCS inputs
438 * TCS outputs = TES inputs
439 *
440 * The LDS layout is:
441 * - TCS inputs for patch 0
442 * - TCS inputs for patch 1
443 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
444 * - ...
445 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
446 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
447 * - TCS outputs for patch 1
448 * - Per-patch TCS outputs for patch 1
449 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
450 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
451 * - ...
452 *
453 * All three shaders VS(LS), TCS, TES share the same LDS space.
454 */
455 static LLVMValueRef
456 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
457 {
458 if (ctx->stage == MESA_SHADER_VERTEX)
459 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
460 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
461 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
462 else {
463 assert(0);
464 return NULL;
465 }
466 }
467
468 static LLVMValueRef
469 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
470 {
471 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
472 }
473
474 static LLVMValueRef
475 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
476 {
477 return LLVMBuildMul(ctx->builder,
478 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
479 LLVMConstInt(ctx->i32, 4, false), "");
480 }
481
482 static LLVMValueRef
483 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
484 {
485 return LLVMBuildMul(ctx->builder,
486 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
487 LLVMConstInt(ctx->i32, 4, false), "");
488 }
489
490 static LLVMValueRef
491 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
494 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
495
496 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
497 }
498
499 static LLVMValueRef
500 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
501 {
502 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
503 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
504 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
505
506 return LLVMBuildAdd(ctx->builder, patch0_offset,
507 LLVMBuildMul(ctx->builder, patch_stride,
508 rel_patch_id, ""),
509 "");
510 }
511
512 static LLVMValueRef
513 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
514 {
515 LLVMValueRef patch0_patch_data_offset =
516 get_tcs_out_patch0_patch_data_offset(ctx);
517 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
518 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
519
520 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
521 LLVMBuildMul(ctx->builder, patch_stride,
522 rel_patch_id, ""),
523 "");
524 }
525
526 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
527 {
528 ud_info->sgpr_idx = *sgpr_idx;
529 ud_info->num_sgprs = num_sgprs;
530 ud_info->indirect = false;
531 ud_info->indirect_offset = 0;
532 *sgpr_idx += num_sgprs;
533 }
534
535 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
536 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
537 {
538 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
539 }
540
541
542 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
543 uint32_t indirect_offset)
544 {
545 ud_info->sgpr_idx = sgpr_idx;
546 ud_info->num_sgprs = num_sgprs;
547 ud_info->indirect = true;
548 ud_info->indirect_offset = indirect_offset;
549 }
550
551 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
552 {
553 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
554 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
555 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
556 "tess_lds");
557 }
558
559 struct user_sgpr_info {
560 bool need_ring_offsets;
561 uint8_t sgpr_count;
562 bool indirect_all_descriptor_sets;
563 };
564
565 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
566 struct user_sgpr_info *user_sgpr_info)
567 {
568 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
569
570 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
571 if (ctx->stage == MESA_SHADER_GEOMETRY ||
572 ctx->stage == MESA_SHADER_VERTEX ||
573 ctx->stage == MESA_SHADER_TESS_CTRL ||
574 ctx->stage == MESA_SHADER_TESS_EVAL ||
575 ctx->is_gs_copy_shader)
576 user_sgpr_info->need_ring_offsets = true;
577
578 if (ctx->stage == MESA_SHADER_FRAGMENT &&
579 ctx->shader_info->info.ps.needs_sample_positions)
580 user_sgpr_info->need_ring_offsets = true;
581
582 /* 2 user sgprs will nearly always be allocated for scratch/rings */
583 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
584 user_sgpr_info->sgpr_count += 2;
585 }
586
587 switch (ctx->stage) {
588 case MESA_SHADER_COMPUTE:
589 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
590 break;
591 case MESA_SHADER_FRAGMENT:
592 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
593 break;
594 case MESA_SHADER_VERTEX:
595 if (!ctx->is_gs_copy_shader) {
596 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
597 if (ctx->shader_info->info.vs.needs_draw_id) {
598 user_sgpr_info->sgpr_count += 3;
599 } else {
600 user_sgpr_info->sgpr_count += 2;
601 }
602 }
603 if (ctx->options->key.vs.as_ls)
604 user_sgpr_info->sgpr_count++;
605 break;
606 case MESA_SHADER_TESS_CTRL:
607 user_sgpr_info->sgpr_count += 4;
608 break;
609 case MESA_SHADER_TESS_EVAL:
610 user_sgpr_info->sgpr_count += 1;
611 break;
612 case MESA_SHADER_GEOMETRY:
613 user_sgpr_info->sgpr_count += 2;
614 break;
615 default:
616 break;
617 }
618
619 if (ctx->shader_info->info.needs_push_constants)
620 user_sgpr_info->sgpr_count += 2;
621
622 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
623 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
624 user_sgpr_info->sgpr_count += 2;
625 user_sgpr_info->indirect_all_descriptor_sets = true;
626 } else {
627 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
628 }
629 }
630
631 static void
632 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
633 gl_shader_stage stage,
634 bool has_previous_stage,
635 gl_shader_stage previous_stage,
636 const struct user_sgpr_info *user_sgpr_info,
637 struct arg_info *args,
638 LLVMValueRef *desc_sets)
639 {
640 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
641 unsigned stage_mask = 1 << stage;
642 if (has_previous_stage)
643 stage_mask |= 1 << previous_stage;
644
645 /* 1 for each descriptor set */
646 if (!user_sgpr_info->indirect_all_descriptor_sets) {
647 for (unsigned i = 0; i < num_sets; ++i) {
648 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
649 add_user_sgpr_array_argument(args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
650 }
651 }
652 } else
653 add_user_sgpr_array_argument(args, const_array(const_array(ctx->i8, 1024 * 1024), 32), desc_sets);
654
655 if (ctx->shader_info->info.needs_push_constants) {
656 /* 1 for push constants and dynamic descriptors */
657 add_user_sgpr_array_argument(args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
658 }
659 }
660
661 static void
662 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
663 gl_shader_stage stage,
664 bool has_previous_stage,
665 gl_shader_stage previous_stage,
666 const struct user_sgpr_info *user_sgpr_info,
667 LLVMValueRef desc_sets,
668 uint8_t *user_sgpr_idx)
669 {
670 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
671 unsigned stage_mask = 1 << stage;
672 if (has_previous_stage)
673 stage_mask |= 1 << previous_stage;
674
675 if (!user_sgpr_info->indirect_all_descriptor_sets) {
676 for (unsigned i = 0; i < num_sets; ++i) {
677 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
678 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
679 } else
680 ctx->descriptor_sets[i] = NULL;
681 }
682 } else {
683 uint32_t desc_sgpr_idx = *user_sgpr_idx;
684 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
685
686 for (unsigned i = 0; i < num_sets; ++i) {
687 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
688 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
689 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
690
691 } else
692 ctx->descriptor_sets[i] = NULL;
693 }
694 ctx->shader_info->need_indirect_descriptor_sets = true;
695 }
696
697 if (ctx->shader_info->info.needs_push_constants) {
698 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
699 }
700 }
701
702 static void
703 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
704 gl_shader_stage stage,
705 bool has_previous_stage,
706 gl_shader_stage previous_stage,
707 struct arg_info *args)
708 {
709 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
710 if (ctx->shader_info->info.vs.has_vertex_buffers)
711 add_user_sgpr_argument(args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
712 add_user_sgpr_argument(args, ctx->i32, &ctx->abi.base_vertex); // base vertex
713 add_user_sgpr_argument(args, ctx->i32, &ctx->abi.start_instance);// start instance
714 if (ctx->shader_info->info.vs.needs_draw_id)
715 add_user_sgpr_argument(args, ctx->i32, &ctx->abi.draw_id); // draw id
716 }
717 }
718
719 static void
720 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
721 gl_shader_stage stage,
722 bool has_previous_stage,
723 gl_shader_stage previous_stage,
724 uint8_t *user_sgpr_idx)
725 {
726 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
727 if (ctx->shader_info->info.vs.has_vertex_buffers) {
728 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
729 }
730 unsigned vs_num = 2;
731 if (ctx->shader_info->info.vs.needs_draw_id)
732 vs_num++;
733
734 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
735 }
736 }
737
738
739 static void create_function(struct nir_to_llvm_context *ctx,
740 gl_shader_stage stage,
741 bool has_previous_stage,
742 gl_shader_stage previous_stage)
743 {
744 uint8_t user_sgpr_idx;
745 struct user_sgpr_info user_sgpr_info;
746 struct arg_info args = {};
747 LLVMValueRef desc_sets;
748
749 allocate_user_sgprs(ctx, &user_sgpr_info);
750
751 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
752 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
753 }
754
755 switch (stage) {
756 case MESA_SHADER_COMPUTE:
757 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
758 if (ctx->shader_info->info.cs.grid_components_used)
759 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
760 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
761 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
762 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
763 break;
764 case MESA_SHADER_VERTEX:
765 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
766 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
767 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
768 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
769 if (ctx->options->key.vs.as_es)
770 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
771 else if (ctx->options->key.vs.as_ls)
772 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
773 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
774 if (!ctx->is_gs_copy_shader) {
775 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
776 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
777 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
778 }
779 break;
780 case MESA_SHADER_TESS_CTRL:
781 if (has_previous_stage) {
782 // First 6 system regs
783 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
784 add_sgpr_argument(&args, ctx->i32, &ctx->merged_wave_info); // merged wave info
785 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
786
787 add_sgpr_argument(&args, ctx->i32, NULL); // scratch offset
788 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
789 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
790
791 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
792 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
793 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
794
795 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
796 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
797 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
798 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
799 if (ctx->shader_info->info.needs_multiview_view_index)
800 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
801
802 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
803 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
804 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
805 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
806 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
807 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
808 } else {
809 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
810 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
811 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
812 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
813 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
814 if (ctx->shader_info->info.needs_multiview_view_index)
815 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
816 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
817 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
818 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
819 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
820 }
821 break;
822 case MESA_SHADER_TESS_EVAL:
823 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
824 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
825 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
826 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
827 if (ctx->options->key.tes.as_es) {
828 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
829 add_sgpr_argument(&args, ctx->i32, NULL); //
830 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
831 } else {
832 add_sgpr_argument(&args, ctx->i32, NULL); //
833 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
834 }
835 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
836 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
837 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
838 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
839 break;
840 case MESA_SHADER_GEOMETRY:
841 if (has_previous_stage) {
842 // First 6 system regs
843 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // tess factor offset
844 add_sgpr_argument(&args, ctx->i32, &ctx->merged_wave_info); // merged wave info
845 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
846
847 add_sgpr_argument(&args, ctx->i32, NULL); // scratch offset
848 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
849 add_sgpr_argument(&args, ctx->i32, NULL); // unknown
850
851 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
852 if (previous_stage == MESA_SHADER_TESS_EVAL)
853 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
854 else
855 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
856 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
857 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
858 if (ctx->shader_info->info.needs_multiview_view_index)
859 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
860
861 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx01
862 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]); // vtx23
863 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
864 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
865 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
866
867 if (previous_stage == MESA_SHADER_VERTEX) {
868 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
869 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
870 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
871 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
872 } else {
873 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
874 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
875 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
876 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
877 }
878 } else {
879 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
880 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
881 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
882 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
883 if (ctx->shader_info->info.needs_multiview_view_index)
884 add_user_sgpr_argument(&args, ctx->i32, &ctx->view_index);
885 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
886 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
887 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
888 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
889 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
890 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
891 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
892 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
893 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
894 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
895 }
896 break;
897 case MESA_SHADER_FRAGMENT:
898 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
899 if (ctx->shader_info->info.ps.needs_sample_positions)
900 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
901 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
902 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
903 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
904 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
905 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
906 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
907 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
908 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
909 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
910 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */
911 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */
912 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */
913 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */
914 add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /* front face */
915 add_vgpr_argument(&args, ctx->i32, &ctx->abi.ancillary); /* ancillary */
916 add_vgpr_argument(&args, ctx->i32, &ctx->abi.sample_coverage); /* sample coverage */
917 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
918 break;
919 default:
920 unreachable("Shader stage not implemented");
921 }
922
923 ctx->main_function = create_llvm_function(
924 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
925 ctx->max_workgroup_size,
926 ctx->options->unsafe_math);
927 set_llvm_calling_convention(ctx->main_function, stage);
928
929
930 ctx->shader_info->num_input_vgprs = 0;
931 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
932
933 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
934
935 if (ctx->stage != MESA_SHADER_FRAGMENT)
936 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
937
938 assign_arguments(ctx->main_function, &args);
939
940 user_sgpr_idx = 0;
941
942 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
943 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
944 if (ctx->options->supports_spill) {
945 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
946 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
947 NULL, 0, AC_FUNC_ATTR_READNONE);
948 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
949 const_array(ctx->v4i32, 16), "");
950 }
951 }
952
953 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
954 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
955 if (has_previous_stage)
956 user_sgpr_idx = 0;
957
958 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
959
960 switch (stage) {
961 case MESA_SHADER_COMPUTE:
962 if (ctx->shader_info->info.cs.grid_components_used) {
963 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
964 }
965 break;
966 case MESA_SHADER_VERTEX:
967 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
968 if (ctx->view_index)
969 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
970 if (ctx->options->key.vs.as_ls) {
971 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
972 }
973 if (ctx->options->key.vs.as_ls)
974 declare_tess_lds(ctx);
975 break;
976 case MESA_SHADER_TESS_CTRL:
977 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
978 if (has_previous_stage)
979 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
980 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
981 if (ctx->view_index)
982 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
983 declare_tess_lds(ctx);
984 break;
985 case MESA_SHADER_TESS_EVAL:
986 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
987 if (ctx->view_index)
988 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
989 break;
990 case MESA_SHADER_GEOMETRY:
991 if (has_previous_stage) {
992 if (previous_stage == MESA_SHADER_VERTEX)
993 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
994 else
995 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
996 }
997 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
998 if (ctx->view_index)
999 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1000 if (has_previous_stage)
1001 declare_tess_lds(ctx);
1002 break;
1003 case MESA_SHADER_FRAGMENT:
1004 if (ctx->shader_info->info.ps.needs_sample_positions) {
1005 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
1006 }
1007 break;
1008 default:
1009 unreachable("Shader stage not implemented");
1010 }
1011
1012 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1013 }
1014
1015 static void setup_types(struct nir_to_llvm_context *ctx)
1016 {
1017 LLVMValueRef args[4];
1018
1019 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
1020 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
1021 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
1022 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
1023 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
1024 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
1025 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
1026 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
1027 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
1028 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
1029 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
1030 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
1031 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
1032 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
1033 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
1034
1035 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
1036 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
1037 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
1038 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
1039 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
1040 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
1041
1042 args[0] = ctx->f32zero;
1043 args[1] = ctx->f32zero;
1044 args[2] = ctx->f32zero;
1045 args[3] = ctx->f32one;
1046 ctx->v4f32empty = LLVMConstVector(args, 4);
1047
1048 ctx->uniform_md_kind =
1049 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
1050 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
1051
1052 args[0] = LLVMConstReal(ctx->f32, 2.5);
1053 }
1054
1055 static int get_llvm_num_components(LLVMValueRef value)
1056 {
1057 LLVMTypeRef type = LLVMTypeOf(value);
1058 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1059 ? LLVMGetVectorSize(type)
1060 : 1;
1061 return num_components;
1062 }
1063
1064 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1065 LLVMValueRef value,
1066 int index)
1067 {
1068 int count = get_llvm_num_components(value);
1069
1070 assert(index < count);
1071 if (count == 1)
1072 return value;
1073
1074 return LLVMBuildExtractElement(ac->builder, value,
1075 LLVMConstInt(ac->i32, index, false), "");
1076 }
1077
1078 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1079 LLVMValueRef value, unsigned count)
1080 {
1081 unsigned num_components = get_llvm_num_components(value);
1082 if (count == num_components)
1083 return value;
1084
1085 LLVMValueRef masks[] = {
1086 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1087 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1088
1089 if (count == 1)
1090 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1091 "");
1092
1093 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1094 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1095 }
1096
1097 static void
1098 build_store_values_extended(struct ac_llvm_context *ac,
1099 LLVMValueRef *values,
1100 unsigned value_count,
1101 unsigned value_stride,
1102 LLVMValueRef vec)
1103 {
1104 LLVMBuilderRef builder = ac->builder;
1105 unsigned i;
1106
1107 for (i = 0; i < value_count; i++) {
1108 LLVMValueRef ptr = values[i * value_stride];
1109 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1110 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1111 LLVMBuildStore(builder, value, ptr);
1112 }
1113 }
1114
1115 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1116 const nir_ssa_def *def)
1117 {
1118 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1119 if (def->num_components > 1) {
1120 type = LLVMVectorType(type, def->num_components);
1121 }
1122 return type;
1123 }
1124
1125 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1126 {
1127 assert(src.is_ssa);
1128 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1129 return (LLVMValueRef)entry->data;
1130 }
1131
1132
1133 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1134 const struct nir_block *b)
1135 {
1136 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1137 return (LLVMBasicBlockRef)entry->data;
1138 }
1139
1140 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1141 nir_alu_src src,
1142 unsigned num_components)
1143 {
1144 LLVMValueRef value = get_src(ctx, src.src);
1145 bool need_swizzle = false;
1146
1147 assert(value);
1148 LLVMTypeRef type = LLVMTypeOf(value);
1149 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1150 ? LLVMGetVectorSize(type)
1151 : 1;
1152
1153 for (unsigned i = 0; i < num_components; ++i) {
1154 assert(src.swizzle[i] < src_components);
1155 if (src.swizzle[i] != i)
1156 need_swizzle = true;
1157 }
1158
1159 if (need_swizzle || num_components != src_components) {
1160 LLVMValueRef masks[] = {
1161 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1162 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1163 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1164 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1165
1166 if (src_components > 1 && num_components == 1) {
1167 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1168 masks[0], "");
1169 } else if (src_components == 1 && num_components > 1) {
1170 LLVMValueRef values[] = {value, value, value, value};
1171 value = ac_build_gather_values(&ctx->ac, values, num_components);
1172 } else {
1173 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1174 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1175 swizzle, "");
1176 }
1177 }
1178 assert(!src.negate);
1179 assert(!src.abs);
1180 return value;
1181 }
1182
1183 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1184 LLVMIntPredicate pred, LLVMValueRef src0,
1185 LLVMValueRef src1)
1186 {
1187 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1188 return LLVMBuildSelect(ctx->builder, result,
1189 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1190 LLVMConstInt(ctx->i32, 0, false), "");
1191 }
1192
1193 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1194 LLVMRealPredicate pred, LLVMValueRef src0,
1195 LLVMValueRef src1)
1196 {
1197 LLVMValueRef result;
1198 src0 = ac_to_float(ctx, src0);
1199 src1 = ac_to_float(ctx, src1);
1200 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1201 return LLVMBuildSelect(ctx->builder, result,
1202 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1203 LLVMConstInt(ctx->i32, 0, false), "");
1204 }
1205
1206 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1207 const char *intrin,
1208 LLVMTypeRef result_type,
1209 LLVMValueRef src0)
1210 {
1211 char name[64];
1212 LLVMValueRef params[] = {
1213 ac_to_float(ctx, src0),
1214 };
1215
1216 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1217 get_elem_bits(ctx, result_type));
1218 assert(length < sizeof(name));
1219 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1220 }
1221
1222 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1223 const char *intrin,
1224 LLVMTypeRef result_type,
1225 LLVMValueRef src0, LLVMValueRef src1)
1226 {
1227 char name[64];
1228 LLVMValueRef params[] = {
1229 ac_to_float(ctx, src0),
1230 ac_to_float(ctx, src1),
1231 };
1232
1233 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1234 get_elem_bits(ctx, result_type));
1235 assert(length < sizeof(name));
1236 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1237 }
1238
1239 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1240 const char *intrin,
1241 LLVMTypeRef result_type,
1242 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1243 {
1244 char name[64];
1245 LLVMValueRef params[] = {
1246 ac_to_float(ctx, src0),
1247 ac_to_float(ctx, src1),
1248 ac_to_float(ctx, src2),
1249 };
1250
1251 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1252 get_elem_bits(ctx, result_type));
1253 assert(length < sizeof(name));
1254 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1255 }
1256
1257 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1258 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1259 {
1260 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1261 ctx->i32_0, "");
1262 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1263 }
1264
1265 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1266 LLVMValueRef src0)
1267 {
1268 LLVMValueRef params[2] = {
1269 src0,
1270
1271 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1272 * add special code to check for x=0. The reason is that
1273 * the LLVM behavior for x=0 is different from what we
1274 * need here.
1275 *
1276 * The hardware already implements the correct behavior.
1277 */
1278 LLVMConstInt(ctx->i1, 1, false),
1279 };
1280
1281 LLVMValueRef lsb = ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32,
1282 params, 2,
1283 AC_FUNC_ATTR_READNONE);
1284
1285 /* TODO: We need an intrinsic to skip this conditional. */
1286 /* Check for zero: */
1287 return LLVMBuildSelect(ctx->builder, LLVMBuildICmp(ctx->builder,
1288 LLVMIntEQ, src0,
1289 ctx->i32_0, ""),
1290 LLVMConstInt(ctx->i32, -1, 0), lsb, "");
1291 }
1292
1293 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1294 LLVMValueRef src0)
1295 {
1296 return ac_build_imsb(ctx, src0, ctx->i32);
1297 }
1298
1299 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1300 LLVMValueRef src0)
1301 {
1302 return ac_build_umsb(ctx, src0, ctx->i32);
1303 }
1304
1305 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1306 LLVMIntPredicate pred,
1307 LLVMValueRef src0, LLVMValueRef src1)
1308 {
1309 return LLVMBuildSelect(ctx->builder,
1310 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1311 src0,
1312 src1, "");
1313
1314 }
1315 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1316 LLVMValueRef src0)
1317 {
1318 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1319 LLVMBuildNeg(ctx->builder, src0, ""));
1320 }
1321
1322 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1323 LLVMValueRef src0)
1324 {
1325 LLVMValueRef cmp, val;
1326
1327 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1328 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1329 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1330 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1331 return val;
1332 }
1333
1334 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1335 LLVMValueRef src0)
1336 {
1337 LLVMValueRef cmp, val;
1338
1339 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1340 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1341 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1342 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1343 return val;
1344 }
1345
1346 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1347 LLVMValueRef src0)
1348 {
1349 const char *intr = "llvm.floor.f32";
1350 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1351 LLVMValueRef params[] = {
1352 fsrc0,
1353 };
1354 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1355 ctx->f32, params, 1,
1356 AC_FUNC_ATTR_READNONE);
1357 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1358 }
1359
1360 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1361 const char *intrin,
1362 LLVMValueRef src0, LLVMValueRef src1)
1363 {
1364 LLVMTypeRef ret_type;
1365 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1366 LLVMValueRef res;
1367 LLVMValueRef params[] = { src0, src1 };
1368 ret_type = LLVMStructTypeInContext(ctx->context, types,
1369 2, true);
1370
1371 res = ac_build_intrinsic(ctx, intrin, ret_type,
1372 params, 2, AC_FUNC_ATTR_READNONE);
1373
1374 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1375 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1376 return res;
1377 }
1378
1379 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1380 LLVMValueRef src0)
1381 {
1382 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1383 }
1384
1385 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1386 LLVMValueRef src0)
1387 {
1388 src0 = ac_to_float(ctx, src0);
1389 return LLVMBuildSExt(ctx->builder,
1390 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1391 ctx->i32, "");
1392 }
1393
1394 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1395 LLVMValueRef src0)
1396 {
1397 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1398 }
1399
1400 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1401 LLVMValueRef src0)
1402 {
1403 return LLVMBuildSExt(ctx->builder,
1404 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1405 ctx->i32, "");
1406 }
1407
1408 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1409 LLVMValueRef src0)
1410 {
1411 LLVMValueRef result;
1412 LLVMValueRef cond = NULL;
1413
1414 src0 = ac_to_float(&ctx->ac, src0);
1415 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1416
1417 if (ctx->options->chip_class >= VI) {
1418 LLVMValueRef args[2];
1419 /* Check if the result is a denormal - and flush to 0 if so. */
1420 args[0] = result;
1421 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1422 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1423 }
1424
1425 /* need to convert back up to f32 */
1426 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1427
1428 if (ctx->options->chip_class >= VI)
1429 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1430 else {
1431 /* for SI/CIK */
1432 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1433 * so compare the result and flush to 0 if it's smaller.
1434 */
1435 LLVMValueRef temp, cond2;
1436 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1437 ctx->f32, result);
1438 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1439 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1440 temp, "");
1441 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1442 temp, ctx->f32zero, "");
1443 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1444 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1445 }
1446 return result;
1447 }
1448
1449 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1450 LLVMValueRef src0, LLVMValueRef src1)
1451 {
1452 LLVMValueRef dst64, result;
1453 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1454 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1455
1456 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1457 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1458 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1459 return result;
1460 }
1461
1462 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1463 LLVMValueRef src0, LLVMValueRef src1)
1464 {
1465 LLVMValueRef dst64, result;
1466 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1467 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1468
1469 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1470 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1471 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1472 return result;
1473 }
1474
1475 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1476 bool is_signed,
1477 const LLVMValueRef srcs[3])
1478 {
1479 LLVMValueRef result;
1480 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1481
1482 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1483 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1484 return result;
1485 }
1486
1487 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1488 LLVMValueRef src0, LLVMValueRef src1,
1489 LLVMValueRef src2, LLVMValueRef src3)
1490 {
1491 LLVMValueRef bfi_args[3], result;
1492
1493 bfi_args[0] = LLVMBuildShl(ctx->builder,
1494 LLVMBuildSub(ctx->builder,
1495 LLVMBuildShl(ctx->builder,
1496 ctx->i32_1,
1497 src3, ""),
1498 ctx->i32_1, ""),
1499 src2, "");
1500 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1501 bfi_args[2] = src0;
1502
1503 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1504
1505 /* Calculate:
1506 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1507 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1508 */
1509 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1510 LLVMBuildAnd(ctx->builder, bfi_args[0],
1511 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1512
1513 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1514 return result;
1515 }
1516
1517 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1518 LLVMValueRef src0)
1519 {
1520 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1521 int i;
1522 LLVMValueRef comp[2];
1523
1524 src0 = ac_to_float(ctx, src0);
1525 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1526 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1527 for (i = 0; i < 2; i++) {
1528 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1529 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1530 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1531 }
1532
1533 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1534 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1535
1536 return comp[0];
1537 }
1538
1539 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1540 LLVMValueRef src0)
1541 {
1542 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1543 LLVMValueRef temps[2], result, val;
1544 int i;
1545
1546 for (i = 0; i < 2; i++) {
1547 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1548 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1549 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1550 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1551 }
1552
1553 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1554 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1555 ctx->i32_0, "");
1556 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1557 ctx->i32_1, "");
1558 return result;
1559 }
1560
1561 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1562 nir_op op,
1563 LLVMValueRef src0)
1564 {
1565 unsigned mask;
1566 int idx;
1567 LLVMValueRef result;
1568
1569 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1570 mask = AC_TID_MASK_LEFT;
1571 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1572 mask = AC_TID_MASK_TOP;
1573 else
1574 mask = AC_TID_MASK_TOP_LEFT;
1575
1576 /* for DDX we want to next X pixel, DDY next Y pixel. */
1577 if (op == nir_op_fddx_fine ||
1578 op == nir_op_fddx_coarse ||
1579 op == nir_op_fddx)
1580 idx = 1;
1581 else
1582 idx = 2;
1583
1584 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1585 return result;
1586 }
1587
1588 /*
1589 * this takes an I,J coordinate pair,
1590 * and works out the X and Y derivatives.
1591 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1592 */
1593 static LLVMValueRef emit_ddxy_interp(
1594 struct ac_nir_context *ctx,
1595 LLVMValueRef interp_ij)
1596 {
1597 LLVMValueRef result[4], a;
1598 unsigned i;
1599
1600 for (i = 0; i < 2; i++) {
1601 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1602 LLVMConstInt(ctx->ac.i32, i, false), "");
1603 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1604 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1605 }
1606 return ac_build_gather_values(&ctx->ac, result, 4);
1607 }
1608
1609 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1610 {
1611 LLVMValueRef src[4], result = NULL;
1612 unsigned num_components = instr->dest.dest.ssa.num_components;
1613 unsigned src_components;
1614 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1615
1616 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1617 switch (instr->op) {
1618 case nir_op_vec2:
1619 case nir_op_vec3:
1620 case nir_op_vec4:
1621 src_components = 1;
1622 break;
1623 case nir_op_pack_half_2x16:
1624 src_components = 2;
1625 break;
1626 case nir_op_unpack_half_2x16:
1627 src_components = 1;
1628 break;
1629 default:
1630 src_components = num_components;
1631 break;
1632 }
1633 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1634 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1635
1636 switch (instr->op) {
1637 case nir_op_fmov:
1638 case nir_op_imov:
1639 result = src[0];
1640 break;
1641 case nir_op_fneg:
1642 src[0] = ac_to_float(&ctx->ac, src[0]);
1643 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1644 break;
1645 case nir_op_ineg:
1646 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1647 break;
1648 case nir_op_inot:
1649 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1650 break;
1651 case nir_op_iadd:
1652 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1653 break;
1654 case nir_op_fadd:
1655 src[0] = ac_to_float(&ctx->ac, src[0]);
1656 src[1] = ac_to_float(&ctx->ac, src[1]);
1657 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1658 break;
1659 case nir_op_fsub:
1660 src[0] = ac_to_float(&ctx->ac, src[0]);
1661 src[1] = ac_to_float(&ctx->ac, src[1]);
1662 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1663 break;
1664 case nir_op_isub:
1665 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1666 break;
1667 case nir_op_imul:
1668 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1669 break;
1670 case nir_op_imod:
1671 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1672 break;
1673 case nir_op_umod:
1674 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1675 break;
1676 case nir_op_fmod:
1677 src[0] = ac_to_float(&ctx->ac, src[0]);
1678 src[1] = ac_to_float(&ctx->ac, src[1]);
1679 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1680 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1681 ac_to_float_type(&ctx->ac, def_type), result);
1682 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1683 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1684 break;
1685 case nir_op_frem:
1686 src[0] = ac_to_float(&ctx->ac, src[0]);
1687 src[1] = ac_to_float(&ctx->ac, src[1]);
1688 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_irem:
1691 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1692 break;
1693 case nir_op_idiv:
1694 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_udiv:
1697 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1698 break;
1699 case nir_op_fmul:
1700 src[0] = ac_to_float(&ctx->ac, src[0]);
1701 src[1] = ac_to_float(&ctx->ac, src[1]);
1702 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1703 break;
1704 case nir_op_fdiv:
1705 src[0] = ac_to_float(&ctx->ac, src[0]);
1706 src[1] = ac_to_float(&ctx->ac, src[1]);
1707 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1708 break;
1709 case nir_op_frcp:
1710 src[0] = ac_to_float(&ctx->ac, src[0]);
1711 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1712 break;
1713 case nir_op_iand:
1714 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_ior:
1717 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_ixor:
1720 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1721 break;
1722 case nir_op_ishl:
1723 result = LLVMBuildShl(ctx->ac.builder, src[0],
1724 LLVMBuildZExt(ctx->ac.builder, src[1],
1725 LLVMTypeOf(src[0]), ""),
1726 "");
1727 break;
1728 case nir_op_ishr:
1729 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1730 LLVMBuildZExt(ctx->ac.builder, src[1],
1731 LLVMTypeOf(src[0]), ""),
1732 "");
1733 break;
1734 case nir_op_ushr:
1735 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1736 LLVMBuildZExt(ctx->ac.builder, src[1],
1737 LLVMTypeOf(src[0]), ""),
1738 "");
1739 break;
1740 case nir_op_ilt:
1741 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1742 break;
1743 case nir_op_ine:
1744 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1745 break;
1746 case nir_op_ieq:
1747 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1748 break;
1749 case nir_op_ige:
1750 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1751 break;
1752 case nir_op_ult:
1753 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1754 break;
1755 case nir_op_uge:
1756 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1757 break;
1758 case nir_op_feq:
1759 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1760 break;
1761 case nir_op_fne:
1762 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1763 break;
1764 case nir_op_flt:
1765 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1766 break;
1767 case nir_op_fge:
1768 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1769 break;
1770 case nir_op_fabs:
1771 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1772 ac_to_float_type(&ctx->ac, def_type), src[0]);
1773 break;
1774 case nir_op_iabs:
1775 result = emit_iabs(&ctx->ac, src[0]);
1776 break;
1777 case nir_op_imax:
1778 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1779 break;
1780 case nir_op_imin:
1781 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1782 break;
1783 case nir_op_umax:
1784 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1785 break;
1786 case nir_op_umin:
1787 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1788 break;
1789 case nir_op_isign:
1790 result = emit_isign(&ctx->ac, src[0]);
1791 break;
1792 case nir_op_fsign:
1793 src[0] = ac_to_float(&ctx->ac, src[0]);
1794 result = emit_fsign(&ctx->ac, src[0]);
1795 break;
1796 case nir_op_ffloor:
1797 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1798 ac_to_float_type(&ctx->ac, def_type), src[0]);
1799 break;
1800 case nir_op_ftrunc:
1801 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1802 ac_to_float_type(&ctx->ac, def_type), src[0]);
1803 break;
1804 case nir_op_fceil:
1805 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1806 ac_to_float_type(&ctx->ac, def_type), src[0]);
1807 break;
1808 case nir_op_fround_even:
1809 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1810 ac_to_float_type(&ctx->ac, def_type),src[0]);
1811 break;
1812 case nir_op_ffract:
1813 result = emit_ffract(&ctx->ac, src[0]);
1814 break;
1815 case nir_op_fsin:
1816 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1817 ac_to_float_type(&ctx->ac, def_type), src[0]);
1818 break;
1819 case nir_op_fcos:
1820 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1821 ac_to_float_type(&ctx->ac, def_type), src[0]);
1822 break;
1823 case nir_op_fsqrt:
1824 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1825 ac_to_float_type(&ctx->ac, def_type), src[0]);
1826 break;
1827 case nir_op_fexp2:
1828 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1829 ac_to_float_type(&ctx->ac, def_type), src[0]);
1830 break;
1831 case nir_op_flog2:
1832 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1833 ac_to_float_type(&ctx->ac, def_type), src[0]);
1834 break;
1835 case nir_op_frsq:
1836 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1837 ac_to_float_type(&ctx->ac, def_type), src[0]);
1838 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1839 break;
1840 case nir_op_fpow:
1841 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1842 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1843 break;
1844 case nir_op_fmax:
1845 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1846 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1847 if (instr->dest.dest.ssa.bit_size == 32)
1848 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1849 ac_to_float_type(&ctx->ac, def_type),
1850 result);
1851 break;
1852 case nir_op_fmin:
1853 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1854 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1855 if (instr->dest.dest.ssa.bit_size == 32)
1856 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1857 ac_to_float_type(&ctx->ac, def_type),
1858 result);
1859 break;
1860 case nir_op_ffma:
1861 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1862 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1863 break;
1864 case nir_op_ibitfield_extract:
1865 result = emit_bitfield_extract(&ctx->ac, true, src);
1866 break;
1867 case nir_op_ubitfield_extract:
1868 result = emit_bitfield_extract(&ctx->ac, false, src);
1869 break;
1870 case nir_op_bitfield_insert:
1871 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1872 break;
1873 case nir_op_bitfield_reverse:
1874 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1875 break;
1876 case nir_op_bit_count:
1877 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1878 break;
1879 case nir_op_vec2:
1880 case nir_op_vec3:
1881 case nir_op_vec4:
1882 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1883 src[i] = ac_to_integer(&ctx->ac, src[i]);
1884 result = ac_build_gather_values(&ctx->ac, src, num_components);
1885 break;
1886 case nir_op_f2i32:
1887 case nir_op_f2i64:
1888 src[0] = ac_to_float(&ctx->ac, src[0]);
1889 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1890 break;
1891 case nir_op_f2u32:
1892 case nir_op_f2u64:
1893 src[0] = ac_to_float(&ctx->ac, src[0]);
1894 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1895 break;
1896 case nir_op_i2f32:
1897 case nir_op_i2f64:
1898 src[0] = ac_to_integer(&ctx->ac, src[0]);
1899 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1900 break;
1901 case nir_op_u2f32:
1902 case nir_op_u2f64:
1903 src[0] = ac_to_integer(&ctx->ac, src[0]);
1904 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1905 break;
1906 case nir_op_f2f64:
1907 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1908 break;
1909 case nir_op_f2f32:
1910 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1911 break;
1912 case nir_op_u2u32:
1913 case nir_op_u2u64:
1914 src[0] = ac_to_integer(&ctx->ac, src[0]);
1915 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1916 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1917 else
1918 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1919 break;
1920 case nir_op_i2i32:
1921 case nir_op_i2i64:
1922 src[0] = ac_to_integer(&ctx->ac, src[0]);
1923 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1924 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1925 else
1926 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1927 break;
1928 case nir_op_bcsel:
1929 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1930 break;
1931 case nir_op_find_lsb:
1932 src[0] = ac_to_integer(&ctx->ac, src[0]);
1933 result = emit_find_lsb(&ctx->ac, src[0]);
1934 break;
1935 case nir_op_ufind_msb:
1936 src[0] = ac_to_integer(&ctx->ac, src[0]);
1937 result = emit_ufind_msb(&ctx->ac, src[0]);
1938 break;
1939 case nir_op_ifind_msb:
1940 src[0] = ac_to_integer(&ctx->ac, src[0]);
1941 result = emit_ifind_msb(&ctx->ac, src[0]);
1942 break;
1943 case nir_op_uadd_carry:
1944 src[0] = ac_to_integer(&ctx->ac, src[0]);
1945 src[1] = ac_to_integer(&ctx->ac, src[1]);
1946 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1947 break;
1948 case nir_op_usub_borrow:
1949 src[0] = ac_to_integer(&ctx->ac, src[0]);
1950 src[1] = ac_to_integer(&ctx->ac, src[1]);
1951 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1952 break;
1953 case nir_op_b2f:
1954 result = emit_b2f(&ctx->ac, src[0]);
1955 break;
1956 case nir_op_f2b:
1957 result = emit_f2b(&ctx->ac, src[0]);
1958 break;
1959 case nir_op_b2i:
1960 result = emit_b2i(&ctx->ac, src[0]);
1961 break;
1962 case nir_op_i2b:
1963 src[0] = ac_to_integer(&ctx->ac, src[0]);
1964 result = emit_i2b(&ctx->ac, src[0]);
1965 break;
1966 case nir_op_fquantize2f16:
1967 result = emit_f2f16(ctx->nctx, src[0]);
1968 break;
1969 case nir_op_umul_high:
1970 src[0] = ac_to_integer(&ctx->ac, src[0]);
1971 src[1] = ac_to_integer(&ctx->ac, src[1]);
1972 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1973 break;
1974 case nir_op_imul_high:
1975 src[0] = ac_to_integer(&ctx->ac, src[0]);
1976 src[1] = ac_to_integer(&ctx->ac, src[1]);
1977 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1978 break;
1979 case nir_op_pack_half_2x16:
1980 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1981 break;
1982 case nir_op_unpack_half_2x16:
1983 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1984 break;
1985 case nir_op_fddx:
1986 case nir_op_fddy:
1987 case nir_op_fddx_fine:
1988 case nir_op_fddy_fine:
1989 case nir_op_fddx_coarse:
1990 case nir_op_fddy_coarse:
1991 result = emit_ddxy(ctx, instr->op, src[0]);
1992 break;
1993
1994 case nir_op_unpack_64_2x32_split_x: {
1995 assert(instr->src[0].src.ssa->num_components == 1);
1996 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1997 LLVMVectorType(ctx->ac.i32, 2),
1998 "");
1999 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2000 ctx->ac.i32_0, "");
2001 break;
2002 }
2003
2004 case nir_op_unpack_64_2x32_split_y: {
2005 assert(instr->src[0].src.ssa->num_components == 1);
2006 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2007 LLVMVectorType(ctx->ac.i32, 2),
2008 "");
2009 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2010 ctx->ac.i32_1, "");
2011 break;
2012 }
2013
2014 case nir_op_pack_64_2x32_split: {
2015 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
2016 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2017 src[0], ctx->ac.i32_0, "");
2018 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2019 src[1], ctx->ac.i32_1, "");
2020 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2021 break;
2022 }
2023
2024 default:
2025 fprintf(stderr, "Unknown NIR alu instr: ");
2026 nir_print_instr(&instr->instr, stderr);
2027 fprintf(stderr, "\n");
2028 abort();
2029 }
2030
2031 if (result) {
2032 assert(instr->dest.dest.is_ssa);
2033 result = ac_to_integer(&ctx->ac, result);
2034 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2035 result);
2036 }
2037 }
2038
2039 static void visit_load_const(struct ac_nir_context *ctx,
2040 const nir_load_const_instr *instr)
2041 {
2042 LLVMValueRef values[4], value = NULL;
2043 LLVMTypeRef element_type =
2044 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2045
2046 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2047 switch (instr->def.bit_size) {
2048 case 32:
2049 values[i] = LLVMConstInt(element_type,
2050 instr->value.u32[i], false);
2051 break;
2052 case 64:
2053 values[i] = LLVMConstInt(element_type,
2054 instr->value.u64[i], false);
2055 break;
2056 default:
2057 fprintf(stderr,
2058 "unsupported nir load_const bit_size: %d\n",
2059 instr->def.bit_size);
2060 abort();
2061 }
2062 }
2063 if (instr->def.num_components > 1) {
2064 value = LLVMConstVector(values, instr->def.num_components);
2065 } else
2066 value = values[0];
2067
2068 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2069 }
2070
2071 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2072 LLVMTypeRef type)
2073 {
2074 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2075 return LLVMBuildBitCast(ctx->builder, ptr,
2076 LLVMPointerType(type, addr_space), "");
2077 }
2078
2079 static LLVMValueRef
2080 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2081 {
2082 LLVMValueRef size =
2083 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2084 LLVMConstInt(ctx->ac.i32, 2, false), "");
2085
2086 /* VI only */
2087 if (ctx->ac.chip_class == VI && in_elements) {
2088 /* On VI, the descriptor contains the size in bytes,
2089 * but TXQ must return the size in elements.
2090 * The stride is always non-zero for resources using TXQ.
2091 */
2092 LLVMValueRef stride =
2093 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2094 LLVMConstInt(ctx->ac.i32, 1, false), "");
2095 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2096 LLVMConstInt(ctx->ac.i32, 16, false), "");
2097 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2098 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2099
2100 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2101 }
2102 return size;
2103 }
2104
2105 /**
2106 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2107 * intrinsic names).
2108 */
2109 static void build_int_type_name(
2110 LLVMTypeRef type,
2111 char *buf, unsigned bufsize)
2112 {
2113 assert(bufsize >= 6);
2114
2115 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2116 snprintf(buf, bufsize, "v%ui32",
2117 LLVMGetVectorSize(type));
2118 else
2119 strcpy(buf, "i32");
2120 }
2121
2122 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2123 struct ac_image_args *args,
2124 const nir_tex_instr *instr)
2125 {
2126 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2127 LLVMValueRef coord = args->addr;
2128 LLVMValueRef half_texel[2];
2129 LLVMValueRef compare_cube_wa = NULL;
2130 LLVMValueRef result;
2131 int c;
2132 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2133
2134 //TODO Rect
2135 {
2136 struct ac_image_args txq_args = { 0 };
2137
2138 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2139 txq_args.opcode = ac_image_get_resinfo;
2140 txq_args.dmask = 0xf;
2141 txq_args.addr = ctx->i32_0;
2142 txq_args.resource = args->resource;
2143 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2144
2145 for (c = 0; c < 2; c++) {
2146 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2147 LLVMConstInt(ctx->i32, c, false), "");
2148 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2149 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2150 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2151 LLVMConstReal(ctx->f32, -0.5), "");
2152 }
2153 }
2154
2155 LLVMValueRef orig_coords = args->addr;
2156
2157 for (c = 0; c < 2; c++) {
2158 LLVMValueRef tmp;
2159 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2160 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2161 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2162 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2163 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2164 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2165 }
2166
2167
2168 /*
2169 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2170 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2171 * workaround by sampling using a scaled type and converting.
2172 * This is taken from amdgpu-pro shaders.
2173 */
2174 /* NOTE this produces some ugly code compared to amdgpu-pro,
2175 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2176 * and then reads them back. -pro generates two selects,
2177 * one s_cmp for the descriptor rewriting
2178 * one v_cmp for the coordinate and result changes.
2179 */
2180 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2181 LLVMValueRef tmp, tmp2;
2182
2183 /* workaround 8/8/8/8 uint/sint cube gather bug */
2184 /* first detect it then change to a scaled read and f2i */
2185 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2186 tmp2 = tmp;
2187
2188 /* extract the DATA_FORMAT */
2189 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2190 LLVMConstInt(ctx->i32, 6, false), false);
2191
2192 /* is the DATA_FORMAT == 8_8_8_8 */
2193 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2194
2195 if (stype == GLSL_TYPE_UINT)
2196 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2197 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2198 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2199 else
2200 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2201 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2202 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2203
2204 /* replace the NUM FORMAT in the descriptor */
2205 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2206 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2207
2208 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2209
2210 /* don't modify the coordinates for this case */
2211 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2212 }
2213 args->addr = coord;
2214 result = ac_build_image_opcode(ctx, args);
2215
2216 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2217 LLVMValueRef tmp, tmp2;
2218
2219 /* if the cube workaround is in place, f2i the result. */
2220 for (c = 0; c < 4; c++) {
2221 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2222 if (stype == GLSL_TYPE_UINT)
2223 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2224 else
2225 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2226 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2227 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2228 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2229 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2230 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2231 }
2232 }
2233 return result;
2234 }
2235
2236 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2237 const nir_tex_instr *instr,
2238 bool lod_is_zero,
2239 struct ac_image_args *args)
2240 {
2241 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2242 return ac_build_buffer_load_format(&ctx->ac,
2243 args->resource,
2244 args->addr,
2245 LLVMConstInt(ctx->ac.i32, 0, false),
2246 true);
2247 }
2248
2249 args->opcode = ac_image_sample;
2250 args->compare = instr->is_shadow;
2251
2252 switch (instr->op) {
2253 case nir_texop_txf:
2254 case nir_texop_txf_ms:
2255 case nir_texop_samples_identical:
2256 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2257 args->compare = false;
2258 args->offset = false;
2259 break;
2260 case nir_texop_txb:
2261 args->bias = true;
2262 break;
2263 case nir_texop_txl:
2264 if (lod_is_zero)
2265 args->level_zero = true;
2266 else
2267 args->lod = true;
2268 break;
2269 case nir_texop_txs:
2270 case nir_texop_query_levels:
2271 args->opcode = ac_image_get_resinfo;
2272 break;
2273 case nir_texop_tex:
2274 if (ctx->stage != MESA_SHADER_FRAGMENT)
2275 args->level_zero = true;
2276 break;
2277 case nir_texop_txd:
2278 args->deriv = true;
2279 break;
2280 case nir_texop_tg4:
2281 args->opcode = ac_image_gather4;
2282 args->level_zero = true;
2283 break;
2284 case nir_texop_lod:
2285 args->opcode = ac_image_get_lod;
2286 args->compare = false;
2287 args->offset = false;
2288 break;
2289 default:
2290 break;
2291 }
2292
2293 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2294 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2295 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2296 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2297 }
2298 }
2299 return ac_build_image_opcode(&ctx->ac, args);
2300 }
2301
2302 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2303 nir_intrinsic_instr *instr)
2304 {
2305 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2306 unsigned desc_set = nir_intrinsic_desc_set(instr);
2307 unsigned binding = nir_intrinsic_binding(instr);
2308 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2309 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2310 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2311 unsigned base_offset = layout->binding[binding].offset;
2312 LLVMValueRef offset, stride;
2313
2314 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2315 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2316 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2317 layout->binding[binding].dynamic_offset_offset;
2318 desc_ptr = ctx->push_constants;
2319 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2320 stride = LLVMConstInt(ctx->i32, 16, false);
2321 } else
2322 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2323
2324 offset = LLVMConstInt(ctx->i32, base_offset, false);
2325 index = LLVMBuildMul(ctx->builder, index, stride, "");
2326 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2327
2328 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2329 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2330 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2331
2332 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2333 }
2334
2335 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2336 nir_intrinsic_instr *instr)
2337 {
2338 LLVMValueRef ptr, addr;
2339
2340 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2341 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2342
2343 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2344 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2345
2346 return LLVMBuildLoad(ctx->builder, ptr, "");
2347 }
2348
2349 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2350 const nir_intrinsic_instr *instr)
2351 {
2352 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2353
2354 return get_buffer_size(ctx, desc, false);
2355 }
2356 static void visit_store_ssbo(struct ac_nir_context *ctx,
2357 nir_intrinsic_instr *instr)
2358 {
2359 const char *store_name;
2360 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2361 LLVMTypeRef data_type = ctx->ac.f32;
2362 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2363 int components_32bit = elem_size_mult * instr->num_components;
2364 unsigned writemask = nir_intrinsic_write_mask(instr);
2365 LLVMValueRef base_data, base_offset;
2366 LLVMValueRef params[6];
2367 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2368
2369 params[1] = ctx->abi->load_ssbo(ctx->abi,
2370 get_src(ctx, instr->src[1]), true);
2371 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2372 params[4] = i1false; /* glc */
2373 params[5] = i1false; /* slc */
2374
2375 if (components_32bit > 1)
2376 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2377
2378 base_data = ac_to_float(&ctx->ac, src_data);
2379 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2380 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2381 data_type, "");
2382 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2383 while (writemask) {
2384 int start, count;
2385 LLVMValueRef data;
2386 LLVMValueRef offset;
2387 LLVMValueRef tmp;
2388 u_bit_scan_consecutive_range(&writemask, &start, &count);
2389
2390 /* Due to an LLVM limitation, split 3-element writes
2391 * into a 2-element and a 1-element write. */
2392 if (count == 3) {
2393 writemask |= 1 << (start + 2);
2394 count = 2;
2395 }
2396
2397 start *= elem_size_mult;
2398 count *= elem_size_mult;
2399
2400 if (count > 4) {
2401 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2402 count = 4;
2403 }
2404
2405 if (count == 4) {
2406 store_name = "llvm.amdgcn.buffer.store.v4f32";
2407 data = base_data;
2408 } else if (count == 2) {
2409 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2410
2411 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2412 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2413 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2414 ctx->ac.i32_0, "");
2415
2416 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2417 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2418 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2419 ctx->ac.i32_1, "");
2420 store_name = "llvm.amdgcn.buffer.store.v2f32";
2421
2422 } else {
2423 assert(count == 1);
2424 if (get_llvm_num_components(base_data) > 1)
2425 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2426 LLVMConstInt(ctx->ac.i32, start, false), "");
2427 else
2428 data = base_data;
2429 store_name = "llvm.amdgcn.buffer.store.f32";
2430 }
2431
2432 offset = base_offset;
2433 if (start != 0) {
2434 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2435 }
2436 params[0] = data;
2437 params[3] = offset;
2438 ac_build_intrinsic(&ctx->ac, store_name,
2439 ctx->ac.voidt, params, 6, 0);
2440 }
2441 }
2442
2443 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2444 const nir_intrinsic_instr *instr)
2445 {
2446 const char *name;
2447 LLVMValueRef params[6];
2448 int arg_count = 0;
2449
2450 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2451 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2452 }
2453 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2454 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2455 get_src(ctx, instr->src[0]),
2456 true);
2457 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2458 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2459 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2460
2461 switch (instr->intrinsic) {
2462 case nir_intrinsic_ssbo_atomic_add:
2463 name = "llvm.amdgcn.buffer.atomic.add";
2464 break;
2465 case nir_intrinsic_ssbo_atomic_imin:
2466 name = "llvm.amdgcn.buffer.atomic.smin";
2467 break;
2468 case nir_intrinsic_ssbo_atomic_umin:
2469 name = "llvm.amdgcn.buffer.atomic.umin";
2470 break;
2471 case nir_intrinsic_ssbo_atomic_imax:
2472 name = "llvm.amdgcn.buffer.atomic.smax";
2473 break;
2474 case nir_intrinsic_ssbo_atomic_umax:
2475 name = "llvm.amdgcn.buffer.atomic.umax";
2476 break;
2477 case nir_intrinsic_ssbo_atomic_and:
2478 name = "llvm.amdgcn.buffer.atomic.and";
2479 break;
2480 case nir_intrinsic_ssbo_atomic_or:
2481 name = "llvm.amdgcn.buffer.atomic.or";
2482 break;
2483 case nir_intrinsic_ssbo_atomic_xor:
2484 name = "llvm.amdgcn.buffer.atomic.xor";
2485 break;
2486 case nir_intrinsic_ssbo_atomic_exchange:
2487 name = "llvm.amdgcn.buffer.atomic.swap";
2488 break;
2489 case nir_intrinsic_ssbo_atomic_comp_swap:
2490 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2491 break;
2492 default:
2493 abort();
2494 }
2495
2496 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2497 }
2498
2499 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2500 const nir_intrinsic_instr *instr)
2501 {
2502 LLVMValueRef results[2];
2503 int load_components;
2504 int num_components = instr->num_components;
2505 if (instr->dest.ssa.bit_size == 64)
2506 num_components *= 2;
2507
2508 for (int i = 0; i < num_components; i += load_components) {
2509 load_components = MIN2(num_components - i, 4);
2510 const char *load_name;
2511 LLVMTypeRef data_type = ctx->ac.f32;
2512 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2513 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2514
2515 if (load_components == 3)
2516 data_type = LLVMVectorType(ctx->ac.f32, 4);
2517 else if (load_components > 1)
2518 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2519
2520 if (load_components >= 3)
2521 load_name = "llvm.amdgcn.buffer.load.v4f32";
2522 else if (load_components == 2)
2523 load_name = "llvm.amdgcn.buffer.load.v2f32";
2524 else if (load_components == 1)
2525 load_name = "llvm.amdgcn.buffer.load.f32";
2526 else
2527 unreachable("unhandled number of components");
2528
2529 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
2530 LLVMValueRef params[] = {
2531 ctx->abi->load_ssbo(ctx->abi,
2532 get_src(ctx, instr->src[0]),
2533 false),
2534 LLVMConstInt(ctx->ac.i32, 0, false),
2535 offset,
2536 i1false,
2537 i1false,
2538 };
2539
2540 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2541
2542 }
2543
2544 LLVMValueRef ret = results[0];
2545 if (num_components > 4 || num_components == 3) {
2546 LLVMValueRef masks[] = {
2547 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2548 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2549 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2550 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2551 };
2552
2553 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2554 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2555 results[num_components > 4 ? 1 : 0], swizzle, "");
2556 }
2557
2558 return LLVMBuildBitCast(ctx->ac.builder, ret,
2559 get_def_type(ctx, &instr->dest.ssa), "");
2560 }
2561
2562 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2563 const nir_intrinsic_instr *instr)
2564 {
2565 LLVMValueRef results[8], ret;
2566 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2567 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2568 int num_components = instr->num_components;
2569
2570 if (ctx->abi->load_ubo)
2571 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2572
2573 if (instr->dest.ssa.bit_size == 64)
2574 num_components *= 2;
2575
2576 for (unsigned i = 0; i < num_components; ++i) {
2577 LLVMValueRef params[] = {
2578 rsrc,
2579 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2580 offset, "")
2581 };
2582 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2583 params, 2,
2584 AC_FUNC_ATTR_READNONE |
2585 AC_FUNC_ATTR_LEGACY);
2586 }
2587
2588
2589 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2590 return LLVMBuildBitCast(ctx->ac.builder, ret,
2591 get_def_type(ctx, &instr->dest.ssa), "");
2592 }
2593
2594 static void
2595 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2596 bool vs_in, unsigned *vertex_index_out,
2597 LLVMValueRef *vertex_index_ref,
2598 unsigned *const_out, LLVMValueRef *indir_out)
2599 {
2600 unsigned const_offset = 0;
2601 nir_deref *tail = &deref->deref;
2602 LLVMValueRef offset = NULL;
2603
2604 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2605 tail = tail->child;
2606 nir_deref_array *deref_array = nir_deref_as_array(tail);
2607 if (vertex_index_out)
2608 *vertex_index_out = deref_array->base_offset;
2609
2610 if (vertex_index_ref) {
2611 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2612 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2613 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2614 }
2615 *vertex_index_ref = vtx;
2616 }
2617 }
2618
2619 if (deref->var->data.compact) {
2620 assert(tail->child->deref_type == nir_deref_type_array);
2621 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2622 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2623 /* We always lower indirect dereferences for "compact" array vars. */
2624 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2625
2626 const_offset = deref_array->base_offset;
2627 goto out;
2628 }
2629
2630 while (tail->child != NULL) {
2631 const struct glsl_type *parent_type = tail->type;
2632 tail = tail->child;
2633
2634 if (tail->deref_type == nir_deref_type_array) {
2635 nir_deref_array *deref_array = nir_deref_as_array(tail);
2636 LLVMValueRef index, stride, local_offset;
2637 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2638
2639 const_offset += size * deref_array->base_offset;
2640 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2641 continue;
2642
2643 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2644 index = get_src(ctx, deref_array->indirect);
2645 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2646 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2647
2648 if (offset)
2649 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2650 else
2651 offset = local_offset;
2652 } else if (tail->deref_type == nir_deref_type_struct) {
2653 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2654
2655 for (unsigned i = 0; i < deref_struct->index; i++) {
2656 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2657 const_offset += glsl_count_attribute_slots(ft, vs_in);
2658 }
2659 } else
2660 unreachable("unsupported deref type");
2661
2662 }
2663 out:
2664 if (const_offset && offset)
2665 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2666 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2667 "");
2668
2669 *const_out = const_offset;
2670 *indir_out = offset;
2671 }
2672
2673 static LLVMValueRef
2674 lds_load(struct nir_to_llvm_context *ctx,
2675 LLVMValueRef dw_addr)
2676 {
2677 LLVMValueRef value;
2678 value = ac_build_load(&ctx->ac, ctx->lds, dw_addr);
2679 return value;
2680 }
2681
2682 static void
2683 lds_store(struct nir_to_llvm_context *ctx,
2684 LLVMValueRef dw_addr, LLVMValueRef value)
2685 {
2686 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2687 ac_build_indexed_store(&ctx->ac, ctx->lds,
2688 dw_addr, value);
2689 }
2690
2691 /* The offchip buffer layout for TCS->TES is
2692 *
2693 * - attribute 0 of patch 0 vertex 0
2694 * - attribute 0 of patch 0 vertex 1
2695 * - attribute 0 of patch 0 vertex 2
2696 * ...
2697 * - attribute 0 of patch 1 vertex 0
2698 * - attribute 0 of patch 1 vertex 1
2699 * ...
2700 * - attribute 1 of patch 0 vertex 0
2701 * - attribute 1 of patch 0 vertex 1
2702 * ...
2703 * - per patch attribute 0 of patch 0
2704 * - per patch attribute 0 of patch 1
2705 * ...
2706 *
2707 * Note that every attribute has 4 components.
2708 */
2709 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2710 LLVMValueRef vertex_index,
2711 LLVMValueRef param_index)
2712 {
2713 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2714 LLVMValueRef param_stride, constant16;
2715 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2716
2717 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2718 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2719 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2720 num_patches, "");
2721
2722 constant16 = LLVMConstInt(ctx->i32, 16, false);
2723 if (vertex_index) {
2724 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2725 vertices_per_patch, "");
2726
2727 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2728 vertex_index, "");
2729
2730 param_stride = total_vertices;
2731 } else {
2732 base_addr = rel_patch_id;
2733 param_stride = num_patches;
2734 }
2735
2736 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2737 LLVMBuildMul(ctx->builder, param_index,
2738 param_stride, ""), "");
2739
2740 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2741
2742 if (!vertex_index) {
2743 LLVMValueRef patch_data_offset =
2744 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2745
2746 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2747 patch_data_offset, "");
2748 }
2749 return base_addr;
2750 }
2751
2752 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2753 unsigned param,
2754 unsigned const_index,
2755 bool is_compact,
2756 LLVMValueRef vertex_index,
2757 LLVMValueRef indir_index)
2758 {
2759 LLVMValueRef param_index;
2760
2761 if (indir_index)
2762 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2763 indir_index, "");
2764 else {
2765 if (const_index && !is_compact)
2766 param += const_index;
2767 param_index = LLVMConstInt(ctx->i32, param, false);
2768 }
2769 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2770 }
2771
2772 static void
2773 mark_tess_output(struct nir_to_llvm_context *ctx,
2774 bool is_patch, uint32_t param)
2775
2776 {
2777 if (is_patch) {
2778 ctx->tess_patch_outputs_written |= (1ull << param);
2779 } else
2780 ctx->tess_outputs_written |= (1ull << param);
2781 }
2782
2783 static LLVMValueRef
2784 get_dw_address(struct nir_to_llvm_context *ctx,
2785 LLVMValueRef dw_addr,
2786 unsigned param,
2787 unsigned const_index,
2788 bool compact_const_index,
2789 LLVMValueRef vertex_index,
2790 LLVMValueRef stride,
2791 LLVMValueRef indir_index)
2792
2793 {
2794
2795 if (vertex_index) {
2796 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2797 LLVMBuildMul(ctx->builder,
2798 vertex_index,
2799 stride, ""), "");
2800 }
2801
2802 if (indir_index)
2803 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2804 LLVMBuildMul(ctx->builder, indir_index,
2805 LLVMConstInt(ctx->i32, 4, false), ""), "");
2806 else if (const_index && !compact_const_index)
2807 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2808 LLVMConstInt(ctx->i32, const_index, false), "");
2809
2810 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2811 LLVMConstInt(ctx->i32, param * 4, false), "");
2812
2813 if (const_index && compact_const_index)
2814 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2815 LLVMConstInt(ctx->i32, const_index, false), "");
2816 return dw_addr;
2817 }
2818
2819 static LLVMValueRef
2820 load_tcs_input(struct nir_to_llvm_context *ctx,
2821 nir_intrinsic_instr *instr)
2822 {
2823 LLVMValueRef dw_addr, stride;
2824 unsigned const_index;
2825 LLVMValueRef vertex_index;
2826 LLVMValueRef indir_index;
2827 unsigned param;
2828 LLVMValueRef value[4], result;
2829 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2830 const bool is_compact = instr->variables[0]->var->data.compact;
2831 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2832 get_deref_offset(ctx->nir, instr->variables[0],
2833 false, NULL, per_vertex ? &vertex_index : NULL,
2834 &const_index, &indir_index);
2835
2836 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2837 dw_addr = get_tcs_in_current_patch_offset(ctx);
2838 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2839 indir_index);
2840
2841 for (unsigned i = 0; i < instr->num_components; i++) {
2842 value[i] = lds_load(ctx, dw_addr);
2843 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2844 ctx->i32one, "");
2845 }
2846 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2847 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2848 return result;
2849 }
2850
2851 static LLVMValueRef
2852 load_tcs_output(struct nir_to_llvm_context *ctx,
2853 nir_intrinsic_instr *instr)
2854 {
2855 LLVMValueRef dw_addr;
2856 LLVMValueRef stride = NULL;
2857 LLVMValueRef value[4], result;
2858 LLVMValueRef vertex_index = NULL;
2859 LLVMValueRef indir_index = NULL;
2860 unsigned const_index = 0;
2861 unsigned param;
2862 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2863 const bool is_compact = instr->variables[0]->var->data.compact;
2864 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2865 get_deref_offset(ctx->nir, instr->variables[0],
2866 false, NULL, per_vertex ? &vertex_index : NULL,
2867 &const_index, &indir_index);
2868
2869 if (!instr->variables[0]->var->data.patch) {
2870 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2871 dw_addr = get_tcs_out_current_patch_offset(ctx);
2872 } else {
2873 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2874 }
2875
2876 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2877 indir_index);
2878
2879 for (unsigned i = 0; i < instr->num_components; i++) {
2880 value[i] = lds_load(ctx, dw_addr);
2881 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2882 ctx->i32one, "");
2883 }
2884 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2885 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2886 return result;
2887 }
2888
2889 static void
2890 store_tcs_output(struct nir_to_llvm_context *ctx,
2891 nir_intrinsic_instr *instr,
2892 LLVMValueRef src,
2893 unsigned writemask)
2894 {
2895 LLVMValueRef dw_addr;
2896 LLVMValueRef stride = NULL;
2897 LLVMValueRef buf_addr = NULL;
2898 LLVMValueRef vertex_index = NULL;
2899 LLVMValueRef indir_index = NULL;
2900 unsigned const_index = 0;
2901 unsigned param;
2902 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2903 const bool is_compact = instr->variables[0]->var->data.compact;
2904
2905 get_deref_offset(ctx->nir, instr->variables[0],
2906 false, NULL, per_vertex ? &vertex_index : NULL,
2907 &const_index, &indir_index);
2908
2909 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2910 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2911 is_compact && const_index > 3) {
2912 const_index -= 3;
2913 param++;
2914 }
2915
2916 if (!instr->variables[0]->var->data.patch) {
2917 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2918 dw_addr = get_tcs_out_current_patch_offset(ctx);
2919 } else {
2920 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2921 }
2922
2923 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2924
2925 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2926 indir_index);
2927 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2928 vertex_index, indir_index);
2929
2930 bool is_tess_factor = false;
2931 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2932 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2933 is_tess_factor = true;
2934
2935 unsigned base = is_compact ? const_index : 0;
2936 for (unsigned chan = 0; chan < 8; chan++) {
2937 if (!(writemask & (1 << chan)))
2938 continue;
2939 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2940
2941 lds_store(ctx, dw_addr, value);
2942
2943 if (!is_tess_factor && writemask != 0xF)
2944 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2945 buf_addr, ctx->oc_lds,
2946 4 * (base + chan), 1, 0, true, false);
2947
2948 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2949 ctx->i32one, "");
2950 }
2951
2952 if (writemask == 0xF) {
2953 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2954 buf_addr, ctx->oc_lds,
2955 (base * 4), 1, 0, true, false);
2956 }
2957 }
2958
2959 static LLVMValueRef
2960 load_tes_input(struct nir_to_llvm_context *ctx,
2961 const nir_intrinsic_instr *instr)
2962 {
2963 LLVMValueRef buf_addr;
2964 LLVMValueRef result;
2965 LLVMValueRef vertex_index = NULL;
2966 LLVMValueRef indir_index = NULL;
2967 unsigned const_index = 0;
2968 unsigned param;
2969 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2970 const bool is_compact = instr->variables[0]->var->data.compact;
2971
2972 get_deref_offset(ctx->nir, instr->variables[0],
2973 false, NULL, per_vertex ? &vertex_index : NULL,
2974 &const_index, &indir_index);
2975 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2976 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2977 is_compact && const_index > 3) {
2978 const_index -= 3;
2979 param++;
2980 }
2981 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2982 is_compact, vertex_index, indir_index);
2983
2984 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2985 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2986 result = trim_vector(&ctx->ac, result, instr->num_components);
2987 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2988 return result;
2989 }
2990
2991 static LLVMValueRef
2992 load_gs_input(struct nir_to_llvm_context *ctx,
2993 nir_intrinsic_instr *instr)
2994 {
2995 LLVMValueRef indir_index, vtx_offset;
2996 unsigned const_index;
2997 LLVMValueRef args[9];
2998 unsigned param, vtx_offset_param;
2999 LLVMValueRef value[4], result;
3000 unsigned vertex_index;
3001 get_deref_offset(ctx->nir, instr->variables[0],
3002 false, &vertex_index, NULL,
3003 &const_index, &indir_index);
3004 vtx_offset_param = vertex_index;
3005 assert(vtx_offset_param < 6);
3006 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3007 LLVMConstInt(ctx->i32, 4, false), "");
3008
3009 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
3010 for (unsigned i = 0; i < instr->num_components; i++) {
3011 if (ctx->ac.chip_class >= GFX9) {
3012 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3013 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3014 LLVMConstInt(ctx->ac.i32, param * 4 + i, 0), "");
3015 value[i] = lds_load(ctx, dw_addr);
3016 } else {
3017 args[0] = ctx->esgs_ring;
3018 args[1] = vtx_offset;
3019 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
3020 args[3] = ctx->i32zero;
3021 args[4] = ctx->i32one; /* OFFEN */
3022 args[5] = ctx->i32zero; /* IDXEN */
3023 args[6] = ctx->i32one; /* GLC */
3024 args[7] = ctx->i32zero; /* SLC */
3025 args[8] = ctx->i32zero; /* TFE */
3026
3027 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3028 ctx->i32, args, 9,
3029 AC_FUNC_ATTR_READONLY |
3030 AC_FUNC_ATTR_LEGACY);
3031 }
3032 }
3033 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
3034
3035 return result;
3036 }
3037
3038 static LLVMValueRef
3039 build_gep_for_deref(struct ac_nir_context *ctx,
3040 nir_deref_var *deref)
3041 {
3042 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3043 assert(entry->data);
3044 LLVMValueRef val = entry->data;
3045 nir_deref *tail = deref->deref.child;
3046 while (tail != NULL) {
3047 LLVMValueRef offset;
3048 switch (tail->deref_type) {
3049 case nir_deref_type_array: {
3050 nir_deref_array *array = nir_deref_as_array(tail);
3051 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3052 if (array->deref_array_type ==
3053 nir_deref_array_type_indirect) {
3054 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3055 get_src(ctx,
3056 array->indirect),
3057 "");
3058 }
3059 break;
3060 }
3061 case nir_deref_type_struct: {
3062 nir_deref_struct *deref_struct =
3063 nir_deref_as_struct(tail);
3064 offset = LLVMConstInt(ctx->ac.i32,
3065 deref_struct->index, 0);
3066 break;
3067 }
3068 default:
3069 unreachable("bad deref type");
3070 }
3071 val = ac_build_gep0(&ctx->ac, val, offset);
3072 tail = tail->child;
3073 }
3074 return val;
3075 }
3076
3077 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3078 nir_intrinsic_instr *instr)
3079 {
3080 LLVMValueRef values[8];
3081 int idx = instr->variables[0]->var->data.driver_location;
3082 int ve = instr->dest.ssa.num_components;
3083 LLVMValueRef indir_index;
3084 LLVMValueRef ret;
3085 unsigned const_index;
3086 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3087 instr->variables[0]->var->data.mode == nir_var_shader_in;
3088 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3089 &const_index, &indir_index);
3090
3091 if (instr->dest.ssa.bit_size == 64)
3092 ve *= 2;
3093
3094 switch (instr->variables[0]->var->data.mode) {
3095 case nir_var_shader_in:
3096 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3097 return load_tcs_input(ctx->nctx, instr);
3098 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3099 return load_tes_input(ctx->nctx, instr);
3100 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3101 return load_gs_input(ctx->nctx, instr);
3102 }
3103 for (unsigned chan = 0; chan < ve; chan++) {
3104 if (indir_index) {
3105 unsigned count = glsl_count_attribute_slots(
3106 instr->variables[0]->var->type,
3107 ctx->stage == MESA_SHADER_VERTEX);
3108 count -= chan / 4;
3109 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3110 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3111 4, false, true);
3112
3113 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3114 tmp_vec,
3115 indir_index, "");
3116 } else
3117 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3118 }
3119 break;
3120 case nir_var_local:
3121 for (unsigned chan = 0; chan < ve; chan++) {
3122 if (indir_index) {
3123 unsigned count = glsl_count_attribute_slots(
3124 instr->variables[0]->var->type, false);
3125 count -= chan / 4;
3126 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3127 &ctx->ac, ctx->locals + idx + chan, count,
3128 4, true, true);
3129
3130 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3131 tmp_vec,
3132 indir_index, "");
3133 } else {
3134 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3135 }
3136 }
3137 break;
3138 case nir_var_shared: {
3139 LLVMValueRef address = build_gep_for_deref(ctx,
3140 instr->variables[0]);
3141 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3142 return LLVMBuildBitCast(ctx->ac.builder, val,
3143 get_def_type(ctx, &instr->dest.ssa),
3144 "");
3145 }
3146 case nir_var_shader_out:
3147 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3148 return load_tcs_output(ctx->nctx, instr);
3149 for (unsigned chan = 0; chan < ve; chan++) {
3150 if (indir_index) {
3151 unsigned count = glsl_count_attribute_slots(
3152 instr->variables[0]->var->type, false);
3153 count -= chan / 4;
3154 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3155 &ctx->ac, ctx->outputs + idx + chan, count,
3156 4, true, true);
3157
3158 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3159 tmp_vec,
3160 indir_index, "");
3161 } else {
3162 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3163 ctx->outputs[idx + chan + const_index * 4],
3164 "");
3165 }
3166 }
3167 break;
3168 default:
3169 unreachable("unhandle variable mode");
3170 }
3171 ret = ac_build_gather_values(&ctx->ac, values, ve);
3172 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3173 }
3174
3175 static void
3176 visit_store_var(struct ac_nir_context *ctx,
3177 nir_intrinsic_instr *instr)
3178 {
3179 LLVMValueRef temp_ptr, value;
3180 int idx = instr->variables[0]->var->data.driver_location;
3181 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3182 int writemask = instr->const_index[0];
3183 LLVMValueRef indir_index;
3184 unsigned const_index;
3185 get_deref_offset(ctx, instr->variables[0], false,
3186 NULL, NULL, &const_index, &indir_index);
3187
3188 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3189 int old_writemask = writemask;
3190
3191 src = LLVMBuildBitCast(ctx->ac.builder, src,
3192 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3193 "");
3194
3195 writemask = 0;
3196 for (unsigned chan = 0; chan < 4; chan++) {
3197 if (old_writemask & (1 << chan))
3198 writemask |= 3u << (2 * chan);
3199 }
3200 }
3201
3202 switch (instr->variables[0]->var->data.mode) {
3203 case nir_var_shader_out:
3204
3205 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3206 store_tcs_output(ctx->nctx, instr, src, writemask);
3207 return;
3208 }
3209
3210 for (unsigned chan = 0; chan < 8; chan++) {
3211 int stride = 4;
3212 if (!(writemask & (1 << chan)))
3213 continue;
3214
3215 value = llvm_extract_elem(&ctx->ac, src, chan);
3216
3217 if (instr->variables[0]->var->data.compact)
3218 stride = 1;
3219 if (indir_index) {
3220 unsigned count = glsl_count_attribute_slots(
3221 instr->variables[0]->var->type, false);
3222 count -= chan / 4;
3223 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3224 &ctx->ac, ctx->outputs + idx + chan, count,
3225 stride, true, true);
3226
3227 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3228 value, indir_index, "");
3229 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3230 count, stride, tmp_vec);
3231
3232 } else {
3233 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3234
3235 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3236 }
3237 }
3238 break;
3239 case nir_var_local:
3240 for (unsigned chan = 0; chan < 8; chan++) {
3241 if (!(writemask & (1 << chan)))
3242 continue;
3243
3244 value = llvm_extract_elem(&ctx->ac, src, chan);
3245 if (indir_index) {
3246 unsigned count = glsl_count_attribute_slots(
3247 instr->variables[0]->var->type, false);
3248 count -= chan / 4;
3249 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3250 &ctx->ac, ctx->locals + idx + chan, count,
3251 4, true, true);
3252
3253 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3254 value, indir_index, "");
3255 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3256 count, 4, tmp_vec);
3257 } else {
3258 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3259
3260 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3261 }
3262 }
3263 break;
3264 case nir_var_shared: {
3265 int writemask = instr->const_index[0];
3266 LLVMValueRef address = build_gep_for_deref(ctx,
3267 instr->variables[0]);
3268 LLVMValueRef val = get_src(ctx, instr->src[0]);
3269 unsigned components =
3270 glsl_get_vector_elements(
3271 nir_deref_tail(&instr->variables[0]->deref)->type);
3272 if (writemask == (1 << components) - 1) {
3273 val = LLVMBuildBitCast(
3274 ctx->ac.builder, val,
3275 LLVMGetElementType(LLVMTypeOf(address)), "");
3276 LLVMBuildStore(ctx->ac.builder, val, address);
3277 } else {
3278 for (unsigned chan = 0; chan < 4; chan++) {
3279 if (!(writemask & (1 << chan)))
3280 continue;
3281 LLVMValueRef ptr =
3282 LLVMBuildStructGEP(ctx->ac.builder,
3283 address, chan, "");
3284 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3285 chan);
3286 src = LLVMBuildBitCast(
3287 ctx->ac.builder, src,
3288 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3289 LLVMBuildStore(ctx->ac.builder, src, ptr);
3290 }
3291 }
3292 break;
3293 }
3294 default:
3295 break;
3296 }
3297 }
3298
3299 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3300 {
3301 switch (dim) {
3302 case GLSL_SAMPLER_DIM_BUF:
3303 return 1;
3304 case GLSL_SAMPLER_DIM_1D:
3305 return array ? 2 : 1;
3306 case GLSL_SAMPLER_DIM_2D:
3307 return array ? 3 : 2;
3308 case GLSL_SAMPLER_DIM_MS:
3309 return array ? 4 : 3;
3310 case GLSL_SAMPLER_DIM_3D:
3311 case GLSL_SAMPLER_DIM_CUBE:
3312 return 3;
3313 case GLSL_SAMPLER_DIM_RECT:
3314 case GLSL_SAMPLER_DIM_SUBPASS:
3315 return 2;
3316 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3317 return 3;
3318 default:
3319 break;
3320 }
3321 return 0;
3322 }
3323
3324
3325
3326 /* Adjust the sample index according to FMASK.
3327 *
3328 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3329 * which is the identity mapping. Each nibble says which physical sample
3330 * should be fetched to get that sample.
3331 *
3332 * For example, 0x11111100 means there are only 2 samples stored and
3333 * the second sample covers 3/4 of the pixel. When reading samples 0
3334 * and 1, return physical sample 0 (determined by the first two 0s
3335 * in FMASK), otherwise return physical sample 1.
3336 *
3337 * The sample index should be adjusted as follows:
3338 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3339 */
3340 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3341 LLVMValueRef coord_x, LLVMValueRef coord_y,
3342 LLVMValueRef coord_z,
3343 LLVMValueRef sample_index,
3344 LLVMValueRef fmask_desc_ptr)
3345 {
3346 LLVMValueRef fmask_load_address[4];
3347 LLVMValueRef res;
3348
3349 fmask_load_address[0] = coord_x;
3350 fmask_load_address[1] = coord_y;
3351 if (coord_z) {
3352 fmask_load_address[2] = coord_z;
3353 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3354 }
3355
3356 struct ac_image_args args = {0};
3357
3358 args.opcode = ac_image_load;
3359 args.da = coord_z ? true : false;
3360 args.resource = fmask_desc_ptr;
3361 args.dmask = 0xf;
3362 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3363
3364 res = ac_build_image_opcode(ctx, &args);
3365
3366 res = ac_to_integer(ctx, res);
3367 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3368 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3369
3370 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3371 res,
3372 ctx->i32_0, "");
3373
3374 LLVMValueRef sample_index4 =
3375 LLVMBuildMul(ctx->builder, sample_index, four, "");
3376 LLVMValueRef shifted_fmask =
3377 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3378 LLVMValueRef final_sample =
3379 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3380
3381 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3382 * resource descriptor is 0 (invalid),
3383 */
3384 LLVMValueRef fmask_desc =
3385 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3386 ctx->v8i32, "");
3387
3388 LLVMValueRef fmask_word1 =
3389 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3390 ctx->i32_1, "");
3391
3392 LLVMValueRef word1_is_nonzero =
3393 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3394 fmask_word1, ctx->i32_0, "");
3395
3396 /* Replace the MSAA sample index. */
3397 sample_index =
3398 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3399 final_sample, sample_index, "");
3400 return sample_index;
3401 }
3402
3403 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3404 const nir_intrinsic_instr *instr)
3405 {
3406 const struct glsl_type *type = instr->variables[0]->var->type;
3407 if(instr->variables[0]->deref.child)
3408 type = instr->variables[0]->deref.child->type;
3409
3410 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3411 LLVMValueRef coords[4];
3412 LLVMValueRef masks[] = {
3413 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3414 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3415 };
3416 LLVMValueRef res;
3417 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3418
3419 int count;
3420 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3421 bool is_array = glsl_sampler_type_is_array(type);
3422 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3423 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3424 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3425 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3426 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3427 count = image_type_to_components_count(dim, is_array);
3428
3429 if (is_ms) {
3430 LLVMValueRef fmask_load_address[3];
3431 int chan;
3432
3433 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3434 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3435 if (is_array)
3436 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3437 else
3438 fmask_load_address[2] = NULL;
3439 if (add_frag_pos) {
3440 for (chan = 0; chan < 2; ++chan)
3441 fmask_load_address[chan] =
3442 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3443 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3444 ctx->ac.i32, ""), "");
3445 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3446 }
3447 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3448 fmask_load_address[0],
3449 fmask_load_address[1],
3450 fmask_load_address[2],
3451 sample_index,
3452 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3453 }
3454 if (count == 1 && !gfx9_1d) {
3455 if (instr->src[0].ssa->num_components)
3456 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3457 else
3458 res = src0;
3459 } else {
3460 int chan;
3461 if (is_ms)
3462 count--;
3463 for (chan = 0; chan < count; ++chan) {
3464 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3465 }
3466 if (add_frag_pos) {
3467 for (chan = 0; chan < 2; ++chan)
3468 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3469 ctx->ac.i32, ""), "");
3470 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3471 count++;
3472 }
3473
3474 if (gfx9_1d) {
3475 if (is_array) {
3476 coords[2] = coords[1];
3477 coords[1] = ctx->ac.i32_0;
3478 } else
3479 coords[1] = ctx->ac.i32_0;
3480 count++;
3481 }
3482
3483 if (is_ms) {
3484 coords[count] = sample_index;
3485 count++;
3486 }
3487
3488 if (count == 3) {
3489 coords[3] = LLVMGetUndef(ctx->ac.i32);
3490 count = 4;
3491 }
3492 res = ac_build_gather_values(&ctx->ac, coords, count);
3493 }
3494 return res;
3495 }
3496
3497 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3498 const nir_intrinsic_instr *instr)
3499 {
3500 LLVMValueRef params[7];
3501 LLVMValueRef res;
3502 char intrinsic_name[64];
3503 const nir_variable *var = instr->variables[0]->var;
3504 const struct glsl_type *type = var->type;
3505 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3506 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3507
3508 if(instr->variables[0]->deref.child)
3509 type = instr->variables[0]->deref.child->type;
3510
3511 type = glsl_without_array(type);
3512 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3513 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3514 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3515 ctx->ac.i32_0, ""); /* vindex */
3516 params[2] = ctx->ac.i32_0; /* voffset */
3517 params[3] = i1false; /* glc */
3518 params[4] = i1false; /* slc */
3519 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3520 params, 5, 0);
3521
3522 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3523 res = ac_to_integer(&ctx->ac, res);
3524 } else {
3525 bool is_da = glsl_sampler_type_is_array(type) ||
3526 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3527 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3528 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3529 LLVMValueRef da = is_da ? i1true : i1false;
3530 LLVMValueRef glc = i1false;
3531 LLVMValueRef slc = i1false;
3532
3533 params[0] = get_image_coords(ctx, instr);
3534 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3535 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3536 if (HAVE_LLVM <= 0x0309) {
3537 params[3] = i1false; /* r128 */
3538 params[4] = da;
3539 params[5] = glc;
3540 params[6] = slc;
3541 } else {
3542 LLVMValueRef lwe = i1false;
3543 params[3] = glc;
3544 params[4] = slc;
3545 params[5] = lwe;
3546 params[6] = da;
3547 }
3548
3549 ac_get_image_intr_name("llvm.amdgcn.image.load",
3550 ctx->ac.v4f32, /* vdata */
3551 LLVMTypeOf(params[0]), /* coords */
3552 LLVMTypeOf(params[1]), /* rsrc */
3553 intrinsic_name, sizeof(intrinsic_name));
3554
3555 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3556 params, 7, AC_FUNC_ATTR_READONLY);
3557 }
3558 return ac_to_integer(&ctx->ac, res);
3559 }
3560
3561 static void visit_image_store(struct ac_nir_context *ctx,
3562 nir_intrinsic_instr *instr)
3563 {
3564 LLVMValueRef params[8];
3565 char intrinsic_name[64];
3566 const nir_variable *var = instr->variables[0]->var;
3567 const struct glsl_type *type = glsl_without_array(var->type);
3568 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3569 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3570 LLVMValueRef glc = i1false;
3571 bool force_glc = ctx->ac.chip_class == SI;
3572 if (force_glc)
3573 glc = i1true;
3574
3575 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3576 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3577 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3578 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3579 ctx->ac.i32_0, ""); /* vindex */
3580 params[3] = ctx->ac.i32_0; /* voffset */
3581 params[4] = glc; /* glc */
3582 params[5] = i1false; /* slc */
3583 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3584 params, 6, 0);
3585 } else {
3586 bool is_da = glsl_sampler_type_is_array(type) ||
3587 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3588 LLVMValueRef da = is_da ? i1true : i1false;
3589 LLVMValueRef slc = i1false;
3590
3591 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3592 params[1] = get_image_coords(ctx, instr); /* coords */
3593 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3594 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3595 if (HAVE_LLVM <= 0x0309) {
3596 params[4] = i1false; /* r128 */
3597 params[5] = da;
3598 params[6] = glc;
3599 params[7] = slc;
3600 } else {
3601 LLVMValueRef lwe = i1false;
3602 params[4] = glc;
3603 params[5] = slc;
3604 params[6] = lwe;
3605 params[7] = da;
3606 }
3607
3608 ac_get_image_intr_name("llvm.amdgcn.image.store",
3609 LLVMTypeOf(params[0]), /* vdata */
3610 LLVMTypeOf(params[1]), /* coords */
3611 LLVMTypeOf(params[2]), /* rsrc */
3612 intrinsic_name, sizeof(intrinsic_name));
3613
3614 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3615 params, 8, 0);
3616 }
3617
3618 }
3619
3620 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3621 const nir_intrinsic_instr *instr)
3622 {
3623 LLVMValueRef params[7];
3624 int param_count = 0;
3625 const nir_variable *var = instr->variables[0]->var;
3626
3627 const char *atomic_name;
3628 char intrinsic_name[41];
3629 const struct glsl_type *type = glsl_without_array(var->type);
3630 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3631 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3632 MAYBE_UNUSED int length;
3633
3634 switch (instr->intrinsic) {
3635 case nir_intrinsic_image_atomic_add:
3636 atomic_name = "add";
3637 break;
3638 case nir_intrinsic_image_atomic_min:
3639 atomic_name = "smin";
3640 break;
3641 case nir_intrinsic_image_atomic_max:
3642 atomic_name = "smax";
3643 break;
3644 case nir_intrinsic_image_atomic_and:
3645 atomic_name = "and";
3646 break;
3647 case nir_intrinsic_image_atomic_or:
3648 atomic_name = "or";
3649 break;
3650 case nir_intrinsic_image_atomic_xor:
3651 atomic_name = "xor";
3652 break;
3653 case nir_intrinsic_image_atomic_exchange:
3654 atomic_name = "swap";
3655 break;
3656 case nir_intrinsic_image_atomic_comp_swap:
3657 atomic_name = "cmpswap";
3658 break;
3659 default:
3660 abort();
3661 }
3662
3663 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3664 params[param_count++] = get_src(ctx, instr->src[3]);
3665 params[param_count++] = get_src(ctx, instr->src[2]);
3666
3667 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3668 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3669 true, true);
3670 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3671 ctx->ac.i32_0, ""); /* vindex */
3672 params[param_count++] = ctx->ac.i32_0; /* voffset */
3673 params[param_count++] = i1false; /* slc */
3674
3675 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3676 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3677 } else {
3678 char coords_type[8];
3679
3680 bool da = glsl_sampler_type_is_array(type) ||
3681 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3682
3683 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3684 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3685 true, true);
3686 params[param_count++] = i1false; /* r128 */
3687 params[param_count++] = da ? i1true : i1false; /* da */
3688 params[param_count++] = i1false; /* slc */
3689
3690 build_int_type_name(LLVMTypeOf(coords),
3691 coords_type, sizeof(coords_type));
3692
3693 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3694 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3695 }
3696
3697 assert(length < sizeof(intrinsic_name));
3698 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3699 }
3700
3701 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3702 const nir_intrinsic_instr *instr)
3703 {
3704 LLVMValueRef res;
3705 const nir_variable *var = instr->variables[0]->var;
3706 const struct glsl_type *type = instr->variables[0]->var->type;
3707 bool da = glsl_sampler_type_is_array(var->type) ||
3708 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3709 if(instr->variables[0]->deref.child)
3710 type = instr->variables[0]->deref.child->type;
3711
3712 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3713 return get_buffer_size(ctx,
3714 get_sampler_desc(ctx, instr->variables[0],
3715 AC_DESC_BUFFER, true, false), true);
3716
3717 struct ac_image_args args = { 0 };
3718
3719 args.da = da;
3720 args.dmask = 0xf;
3721 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3722 args.opcode = ac_image_get_resinfo;
3723 args.addr = ctx->ac.i32_0;
3724
3725 res = ac_build_image_opcode(&ctx->ac, &args);
3726
3727 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3728
3729 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3730 glsl_sampler_type_is_array(type)) {
3731 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3732 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3733 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3734 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3735 }
3736 if (ctx->ac.chip_class >= GFX9 &&
3737 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3738 glsl_sampler_type_is_array(type)) {
3739 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3740 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3741 ctx->ac.i32_1, "");
3742
3743 }
3744 return res;
3745 }
3746
3747 #define NOOP_WAITCNT 0xf7f
3748 #define LGKM_CNT 0x07f
3749 #define VM_CNT 0xf70
3750
3751 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3752 unsigned simm16)
3753 {
3754 LLVMValueRef args[1] = {
3755 LLVMConstInt(ctx->i32, simm16, false),
3756 };
3757 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3758 ctx->voidt, args, 1, 0);
3759 }
3760
3761 static void emit_barrier(struct nir_to_llvm_context *ctx)
3762 {
3763 /* SI only (thanks to a hw bug workaround):
3764 * The real barrier instruction isn’t needed, because an entire patch
3765 * always fits into a single wave.
3766 */
3767 if (ctx->options->chip_class == SI &&
3768 ctx->stage == MESA_SHADER_TESS_CTRL) {
3769 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3770 return;
3771 }
3772 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3773 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3774 }
3775
3776 static void emit_discard_if(struct ac_nir_context *ctx,
3777 const nir_intrinsic_instr *instr)
3778 {
3779 LLVMValueRef cond;
3780
3781 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
3782 get_src(ctx, instr->src[0]),
3783 ctx->ac.i32_0, "");
3784
3785 cond = LLVMBuildSelect(ctx->ac.builder, cond,
3786 LLVMConstReal(ctx->ac.f32, -1.0f),
3787 ctx->ac.f32_0, "");
3788 ac_build_kill(&ctx->ac, cond);
3789 }
3790
3791 static LLVMValueRef
3792 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3793 {
3794 LLVMValueRef result;
3795 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3796 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3797 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3798
3799 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3800 }
3801
3802 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3803 const nir_intrinsic_instr *instr)
3804 {
3805 LLVMValueRef ptr, result;
3806 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3807 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3808
3809 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3810 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3811 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3812 ptr, src, src1,
3813 LLVMAtomicOrderingSequentiallyConsistent,
3814 LLVMAtomicOrderingSequentiallyConsistent,
3815 false);
3816 } else {
3817 LLVMAtomicRMWBinOp op;
3818 switch (instr->intrinsic) {
3819 case nir_intrinsic_var_atomic_add:
3820 op = LLVMAtomicRMWBinOpAdd;
3821 break;
3822 case nir_intrinsic_var_atomic_umin:
3823 op = LLVMAtomicRMWBinOpUMin;
3824 break;
3825 case nir_intrinsic_var_atomic_umax:
3826 op = LLVMAtomicRMWBinOpUMax;
3827 break;
3828 case nir_intrinsic_var_atomic_imin:
3829 op = LLVMAtomicRMWBinOpMin;
3830 break;
3831 case nir_intrinsic_var_atomic_imax:
3832 op = LLVMAtomicRMWBinOpMax;
3833 break;
3834 case nir_intrinsic_var_atomic_and:
3835 op = LLVMAtomicRMWBinOpAnd;
3836 break;
3837 case nir_intrinsic_var_atomic_or:
3838 op = LLVMAtomicRMWBinOpOr;
3839 break;
3840 case nir_intrinsic_var_atomic_xor:
3841 op = LLVMAtomicRMWBinOpXor;
3842 break;
3843 case nir_intrinsic_var_atomic_exchange:
3844 op = LLVMAtomicRMWBinOpXchg;
3845 break;
3846 default:
3847 return NULL;
3848 }
3849
3850 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3851 LLVMAtomicOrderingSequentiallyConsistent,
3852 false);
3853 }
3854 return result;
3855 }
3856
3857 #define INTERP_CENTER 0
3858 #define INTERP_CENTROID 1
3859 #define INTERP_SAMPLE 2
3860
3861 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3862 enum glsl_interp_mode interp, unsigned location)
3863 {
3864 switch (interp) {
3865 case INTERP_MODE_FLAT:
3866 default:
3867 return NULL;
3868 case INTERP_MODE_SMOOTH:
3869 case INTERP_MODE_NONE:
3870 if (location == INTERP_CENTER)
3871 return ctx->persp_center;
3872 else if (location == INTERP_CENTROID)
3873 return ctx->persp_centroid;
3874 else if (location == INTERP_SAMPLE)
3875 return ctx->persp_sample;
3876 break;
3877 case INTERP_MODE_NOPERSPECTIVE:
3878 if (location == INTERP_CENTER)
3879 return ctx->linear_center;
3880 else if (location == INTERP_CENTROID)
3881 return ctx->linear_centroid;
3882 else if (location == INTERP_SAMPLE)
3883 return ctx->linear_sample;
3884 break;
3885 }
3886 return NULL;
3887 }
3888
3889 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3890 LLVMValueRef sample_id)
3891 {
3892 LLVMValueRef result;
3893 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3894
3895 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3896 const_array(ctx->v2f32, 64), "");
3897
3898 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3899 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3900
3901 return result;
3902 }
3903
3904 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3905 {
3906 LLVMValueRef values[2];
3907
3908 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3909 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3910 return ac_build_gather_values(&ctx->ac, values, 2);
3911 }
3912
3913 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3914 const nir_intrinsic_instr *instr)
3915 {
3916 LLVMValueRef result[2];
3917 LLVMValueRef interp_param, attr_number;
3918 unsigned location;
3919 unsigned chan;
3920 LLVMValueRef src_c0 = NULL;
3921 LLVMValueRef src_c1 = NULL;
3922 LLVMValueRef src0 = NULL;
3923 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3924 switch (instr->intrinsic) {
3925 case nir_intrinsic_interp_var_at_centroid:
3926 location = INTERP_CENTROID;
3927 break;
3928 case nir_intrinsic_interp_var_at_sample:
3929 case nir_intrinsic_interp_var_at_offset:
3930 location = INTERP_CENTER;
3931 src0 = get_src(ctx->nir, instr->src[0]);
3932 break;
3933 default:
3934 break;
3935 }
3936
3937 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3938 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3939 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3940 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3941 LLVMValueRef sample_position;
3942 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3943
3944 /* fetch sample ID */
3945 sample_position = load_sample_position(ctx, src0);
3946
3947 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3948 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3949 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3950 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3951 }
3952 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3953 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3954
3955 if (location == INTERP_CENTER) {
3956 LLVMValueRef ij_out[2];
3957 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3958
3959 /*
3960 * take the I then J parameters, and the DDX/Y for it, and
3961 * calculate the IJ inputs for the interpolator.
3962 * temp1 = ddx * offset/sample.x + I;
3963 * interp_param.I = ddy * offset/sample.y + temp1;
3964 * temp1 = ddx * offset/sample.x + J;
3965 * interp_param.J = ddy * offset/sample.y + temp1;
3966 */
3967 for (unsigned i = 0; i < 2; i++) {
3968 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3969 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3970 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3971 ddxy_out, ix_ll, "");
3972 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3973 ddxy_out, iy_ll, "");
3974 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3975 interp_param, ix_ll, "");
3976 LLVMValueRef temp1, temp2;
3977
3978 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3979 ctx->f32, "");
3980
3981 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3982 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3983
3984 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3985 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3986
3987 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3988 temp2, ctx->i32, "");
3989 }
3990 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3991
3992 }
3993
3994 for (chan = 0; chan < 2; chan++) {
3995 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3996
3997 if (interp_param) {
3998 interp_param = LLVMBuildBitCast(ctx->builder,
3999 interp_param, LLVMVectorType(ctx->f32, 2), "");
4000 LLVMValueRef i = LLVMBuildExtractElement(
4001 ctx->builder, interp_param, ctx->i32zero, "");
4002 LLVMValueRef j = LLVMBuildExtractElement(
4003 ctx->builder, interp_param, ctx->i32one, "");
4004
4005 result[chan] = ac_build_fs_interp(&ctx->ac,
4006 llvm_chan, attr_number,
4007 ctx->prim_mask, i, j);
4008 } else {
4009 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4010 LLVMConstInt(ctx->i32, 2, false),
4011 llvm_chan, attr_number,
4012 ctx->prim_mask);
4013 }
4014 }
4015 return ac_build_gather_values(&ctx->ac, result, 2);
4016 }
4017
4018 static void
4019 visit_emit_vertex(struct nir_to_llvm_context *ctx,
4020 const nir_intrinsic_instr *instr)
4021 {
4022 LLVMValueRef gs_next_vertex;
4023 LLVMValueRef can_emit, kill;
4024 int idx;
4025
4026 assert(instr->const_index[0] == 0);
4027 /* Write vertex attribute values to GSVS ring */
4028 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4029 ctx->gs_next_vertex,
4030 "");
4031
4032 /* If this thread has already emitted the declared maximum number of
4033 * vertices, kill it: excessive vertex emissions are not supposed to
4034 * have any effect, and GS threads have no externally observable
4035 * effects other than emitting vertices.
4036 */
4037 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4038 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
4039
4040 kill = LLVMBuildSelect(ctx->builder, can_emit,
4041 LLVMConstReal(ctx->f32, 1.0f),
4042 LLVMConstReal(ctx->f32, -1.0f), "");
4043 ac_build_kill(&ctx->ac, kill);
4044
4045 /* loop num outputs */
4046 idx = 0;
4047 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4048 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
4049 int length = 4;
4050 int slot = idx;
4051 int slot_inc = 1;
4052
4053 if (!(ctx->output_mask & (1ull << i)))
4054 continue;
4055
4056 if (i == VARYING_SLOT_CLIP_DIST0) {
4057 /* pack clip and cull into a single set of slots */
4058 length = ctx->num_output_clips + ctx->num_output_culls;
4059 if (length > 4)
4060 slot_inc = 2;
4061 }
4062 for (unsigned j = 0; j < length; j++) {
4063 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4064 out_ptr[j], "");
4065 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4066 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4067 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
4068
4069 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4070
4071 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4072 out_val, 1,
4073 voffset, ctx->gs2vs_offset, 0,
4074 1, 1, true, true);
4075 }
4076 idx += slot_inc;
4077 }
4078
4079 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4080 ctx->i32one, "");
4081 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4082
4083 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4084 }
4085
4086 static void
4087 visit_end_primitive(struct nir_to_llvm_context *ctx,
4088 const nir_intrinsic_instr *instr)
4089 {
4090 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4091 }
4092
4093 static LLVMValueRef
4094 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4095 const nir_intrinsic_instr *instr)
4096 {
4097 LLVMValueRef coord[4] = {
4098 ctx->tes_u,
4099 ctx->tes_v,
4100 ctx->f32zero,
4101 ctx->f32zero,
4102 };
4103
4104 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4105 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
4106 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4107
4108 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4109 return LLVMBuildBitCast(ctx->builder, result,
4110 get_def_type(ctx->nir, &instr->dest.ssa), "");
4111 }
4112
4113 static void visit_intrinsic(struct ac_nir_context *ctx,
4114 nir_intrinsic_instr *instr)
4115 {
4116 LLVMValueRef result = NULL;
4117
4118 switch (instr->intrinsic) {
4119 case nir_intrinsic_load_work_group_id: {
4120 result = ctx->nctx->workgroup_ids;
4121 break;
4122 }
4123 case nir_intrinsic_load_base_vertex: {
4124 result = ctx->abi->base_vertex;
4125 break;
4126 }
4127 case nir_intrinsic_load_vertex_id_zero_base: {
4128 result = ctx->abi->vertex_id;
4129 break;
4130 }
4131 case nir_intrinsic_load_local_invocation_id: {
4132 result = ctx->nctx->local_invocation_ids;
4133 break;
4134 }
4135 case nir_intrinsic_load_base_instance:
4136 result = ctx->abi->start_instance;
4137 break;
4138 case nir_intrinsic_load_draw_id:
4139 result = ctx->abi->draw_id;
4140 break;
4141 case nir_intrinsic_load_view_index:
4142 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4143 break;
4144 case nir_intrinsic_load_invocation_id:
4145 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4146 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4147 else
4148 result = ctx->nctx->gs_invocation_id;
4149 break;
4150 case nir_intrinsic_load_primitive_id:
4151 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4152 ctx->nctx->shader_info->gs.uses_prim_id = true;
4153 result = ctx->nctx->gs_prim_id;
4154 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4155 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4156 result = ctx->nctx->tcs_patch_id;
4157 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4158 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4159 result = ctx->nctx->tes_patch_id;
4160 } else
4161 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4162 break;
4163 case nir_intrinsic_load_sample_id:
4164 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4165 break;
4166 case nir_intrinsic_load_sample_pos:
4167 result = load_sample_pos(ctx);
4168 break;
4169 case nir_intrinsic_load_sample_mask_in:
4170 result = ctx->abi->sample_coverage;
4171 break;
4172 case nir_intrinsic_load_frag_coord: {
4173 LLVMValueRef values[4] = {
4174 ctx->abi->frag_pos[0],
4175 ctx->abi->frag_pos[1],
4176 ctx->abi->frag_pos[2],
4177 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4178 };
4179 result = ac_build_gather_values(&ctx->ac, values, 4);
4180 break;
4181 }
4182 case nir_intrinsic_load_front_face:
4183 result = ctx->abi->front_face;
4184 break;
4185 case nir_intrinsic_load_instance_id:
4186 result = ctx->abi->instance_id;
4187 break;
4188 case nir_intrinsic_load_num_work_groups:
4189 result = ctx->nctx->num_work_groups;
4190 break;
4191 case nir_intrinsic_load_local_invocation_index:
4192 result = visit_load_local_invocation_index(ctx->nctx);
4193 break;
4194 case nir_intrinsic_load_push_constant:
4195 result = visit_load_push_constant(ctx->nctx, instr);
4196 break;
4197 case nir_intrinsic_vulkan_resource_index:
4198 result = visit_vulkan_resource_index(ctx->nctx, instr);
4199 break;
4200 case nir_intrinsic_store_ssbo:
4201 visit_store_ssbo(ctx, instr);
4202 break;
4203 case nir_intrinsic_load_ssbo:
4204 result = visit_load_buffer(ctx, instr);
4205 break;
4206 case nir_intrinsic_ssbo_atomic_add:
4207 case nir_intrinsic_ssbo_atomic_imin:
4208 case nir_intrinsic_ssbo_atomic_umin:
4209 case nir_intrinsic_ssbo_atomic_imax:
4210 case nir_intrinsic_ssbo_atomic_umax:
4211 case nir_intrinsic_ssbo_atomic_and:
4212 case nir_intrinsic_ssbo_atomic_or:
4213 case nir_intrinsic_ssbo_atomic_xor:
4214 case nir_intrinsic_ssbo_atomic_exchange:
4215 case nir_intrinsic_ssbo_atomic_comp_swap:
4216 result = visit_atomic_ssbo(ctx, instr);
4217 break;
4218 case nir_intrinsic_load_ubo:
4219 result = visit_load_ubo_buffer(ctx, instr);
4220 break;
4221 case nir_intrinsic_get_buffer_size:
4222 result = visit_get_buffer_size(ctx, instr);
4223 break;
4224 case nir_intrinsic_load_var:
4225 result = visit_load_var(ctx, instr);
4226 break;
4227 case nir_intrinsic_store_var:
4228 visit_store_var(ctx, instr);
4229 break;
4230 case nir_intrinsic_image_load:
4231 result = visit_image_load(ctx, instr);
4232 break;
4233 case nir_intrinsic_image_store:
4234 visit_image_store(ctx, instr);
4235 break;
4236 case nir_intrinsic_image_atomic_add:
4237 case nir_intrinsic_image_atomic_min:
4238 case nir_intrinsic_image_atomic_max:
4239 case nir_intrinsic_image_atomic_and:
4240 case nir_intrinsic_image_atomic_or:
4241 case nir_intrinsic_image_atomic_xor:
4242 case nir_intrinsic_image_atomic_exchange:
4243 case nir_intrinsic_image_atomic_comp_swap:
4244 result = visit_image_atomic(ctx, instr);
4245 break;
4246 case nir_intrinsic_image_size:
4247 result = visit_image_size(ctx, instr);
4248 break;
4249 case nir_intrinsic_discard:
4250 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4251 LLVMVoidTypeInContext(ctx->ac.context),
4252 NULL, 0, AC_FUNC_ATTR_LEGACY);
4253 break;
4254 case nir_intrinsic_discard_if:
4255 emit_discard_if(ctx, instr);
4256 break;
4257 case nir_intrinsic_memory_barrier:
4258 emit_waitcnt(ctx->nctx, VM_CNT);
4259 break;
4260 case nir_intrinsic_barrier:
4261 emit_barrier(ctx->nctx);
4262 break;
4263 case nir_intrinsic_var_atomic_add:
4264 case nir_intrinsic_var_atomic_imin:
4265 case nir_intrinsic_var_atomic_umin:
4266 case nir_intrinsic_var_atomic_imax:
4267 case nir_intrinsic_var_atomic_umax:
4268 case nir_intrinsic_var_atomic_and:
4269 case nir_intrinsic_var_atomic_or:
4270 case nir_intrinsic_var_atomic_xor:
4271 case nir_intrinsic_var_atomic_exchange:
4272 case nir_intrinsic_var_atomic_comp_swap:
4273 result = visit_var_atomic(ctx->nctx, instr);
4274 break;
4275 case nir_intrinsic_interp_var_at_centroid:
4276 case nir_intrinsic_interp_var_at_sample:
4277 case nir_intrinsic_interp_var_at_offset:
4278 result = visit_interp(ctx->nctx, instr);
4279 break;
4280 case nir_intrinsic_emit_vertex:
4281 visit_emit_vertex(ctx->nctx, instr);
4282 break;
4283 case nir_intrinsic_end_primitive:
4284 visit_end_primitive(ctx->nctx, instr);
4285 break;
4286 case nir_intrinsic_load_tess_coord:
4287 result = visit_load_tess_coord(ctx->nctx, instr);
4288 break;
4289 case nir_intrinsic_load_patch_vertices_in:
4290 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4291 break;
4292 default:
4293 fprintf(stderr, "Unknown intrinsic: ");
4294 nir_print_instr(&instr->instr, stderr);
4295 fprintf(stderr, "\n");
4296 break;
4297 }
4298 if (result) {
4299 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4300 }
4301 }
4302
4303 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4304 LLVMValueRef buffer, bool write)
4305 {
4306 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4307
4308 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4309 ctx->shader_info->fs.writes_memory = true;
4310
4311 return buffer;
4312 }
4313
4314 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4315 unsigned descriptor_set,
4316 unsigned base_index,
4317 unsigned constant_index,
4318 LLVMValueRef index,
4319 enum ac_descriptor_type desc_type,
4320 bool image, bool write)
4321 {
4322 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4323 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4324 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4325 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4326 unsigned offset = binding->offset;
4327 unsigned stride = binding->size;
4328 unsigned type_size;
4329 LLVMBuilderRef builder = ctx->builder;
4330 LLVMTypeRef type;
4331
4332 assert(base_index < layout->binding_count);
4333
4334 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4335 ctx->shader_info->fs.writes_memory = true;
4336
4337 switch (desc_type) {
4338 case AC_DESC_IMAGE:
4339 type = ctx->v8i32;
4340 type_size = 32;
4341 break;
4342 case AC_DESC_FMASK:
4343 type = ctx->v8i32;
4344 offset += 32;
4345 type_size = 32;
4346 break;
4347 case AC_DESC_SAMPLER:
4348 type = ctx->v4i32;
4349 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4350 offset += 64;
4351
4352 type_size = 16;
4353 break;
4354 case AC_DESC_BUFFER:
4355 type = ctx->v4i32;
4356 type_size = 16;
4357 break;
4358 default:
4359 unreachable("invalid desc_type\n");
4360 }
4361
4362 offset += constant_index * stride;
4363
4364 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4365 (!index || binding->immutable_samplers_equal)) {
4366 if (binding->immutable_samplers_equal)
4367 constant_index = 0;
4368
4369 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4370
4371 LLVMValueRef constants[] = {
4372 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4373 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4374 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4375 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4376 };
4377 return ac_build_gather_values(&ctx->ac, constants, 4);
4378 }
4379
4380 assert(stride % type_size == 0);
4381
4382 if (!index)
4383 index = ctx->i32zero;
4384
4385 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4386
4387 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4388 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4389
4390 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4391 }
4392
4393 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4394 const nir_deref_var *deref,
4395 enum ac_descriptor_type desc_type,
4396 bool image, bool write)
4397 {
4398 LLVMValueRef index = NULL;
4399 unsigned constant_index = 0;
4400 const nir_deref *tail = &deref->deref;
4401
4402 while (tail->child) {
4403 const nir_deref_array *child = nir_deref_as_array(tail->child);
4404 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4405
4406 if (!array_size)
4407 array_size = 1;
4408
4409 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4410
4411 if (child->deref_array_type == nir_deref_array_type_indirect) {
4412 LLVMValueRef indirect = get_src(ctx, child->indirect);
4413
4414 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4415 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4416
4417 if (!index)
4418 index = indirect;
4419 else
4420 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4421 }
4422
4423 constant_index += child->base_offset * array_size;
4424
4425 tail = &child->deref;
4426 }
4427
4428 return ctx->abi->load_sampler_desc(ctx->abi,
4429 deref->var->data.descriptor_set,
4430 deref->var->data.binding,
4431 constant_index, index,
4432 desc_type, image, write);
4433 }
4434
4435 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4436 struct ac_image_args *args,
4437 const nir_tex_instr *instr,
4438 nir_texop op,
4439 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4440 LLVMValueRef *param, unsigned count,
4441 unsigned dmask)
4442 {
4443 unsigned is_rect = 0;
4444 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4445
4446 if (op == nir_texop_lod)
4447 da = false;
4448 /* Pad to power of two vector */
4449 while (count < util_next_power_of_two(count))
4450 param[count++] = LLVMGetUndef(ctx->i32);
4451
4452 if (count > 1)
4453 args->addr = ac_build_gather_values(ctx, param, count);
4454 else
4455 args->addr = param[0];
4456
4457 args->resource = res_ptr;
4458 args->sampler = samp_ptr;
4459
4460 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4461 args->addr = param[0];
4462 return;
4463 }
4464
4465 args->dmask = dmask;
4466 args->unorm = is_rect;
4467 args->da = da;
4468 }
4469
4470 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4471 *
4472 * SI-CI:
4473 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4474 * filtering manually. The driver sets img7 to a mask clearing
4475 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4476 * s_and_b32 samp0, samp0, img7
4477 *
4478 * VI:
4479 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4480 */
4481 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4482 LLVMValueRef res, LLVMValueRef samp)
4483 {
4484 LLVMBuilderRef builder = ctx->ac.builder;
4485 LLVMValueRef img7, samp0;
4486
4487 if (ctx->ac.chip_class >= VI)
4488 return samp;
4489
4490 img7 = LLVMBuildExtractElement(builder, res,
4491 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4492 samp0 = LLVMBuildExtractElement(builder, samp,
4493 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4494 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4495 return LLVMBuildInsertElement(builder, samp, samp0,
4496 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4497 }
4498
4499 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4500 nir_tex_instr *instr,
4501 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4502 LLVMValueRef *fmask_ptr)
4503 {
4504 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4505 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4506 else
4507 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4508 if (samp_ptr) {
4509 if (instr->sampler)
4510 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4511 else
4512 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4513 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4514 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4515 }
4516 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4517 instr->op == nir_texop_samples_identical))
4518 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4519 }
4520
4521 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4522 LLVMValueRef coord)
4523 {
4524 coord = ac_to_float(ctx, coord);
4525 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4526 coord = ac_to_integer(ctx, coord);
4527 return coord;
4528 }
4529
4530 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4531 {
4532 LLVMValueRef result = NULL;
4533 struct ac_image_args args = { 0 };
4534 unsigned dmask = 0xf;
4535 LLVMValueRef address[16];
4536 LLVMValueRef coords[5];
4537 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4538 LLVMValueRef bias = NULL, offsets = NULL;
4539 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4540 LLVMValueRef ddx = NULL, ddy = NULL;
4541 LLVMValueRef derivs[6];
4542 unsigned chan, count = 0;
4543 unsigned const_src = 0, num_deriv_comp = 0;
4544 bool lod_is_zero = false;
4545
4546 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4547
4548 for (unsigned i = 0; i < instr->num_srcs; i++) {
4549 switch (instr->src[i].src_type) {
4550 case nir_tex_src_coord:
4551 coord = get_src(ctx, instr->src[i].src);
4552 break;
4553 case nir_tex_src_projector:
4554 break;
4555 case nir_tex_src_comparator:
4556 comparator = get_src(ctx, instr->src[i].src);
4557 break;
4558 case nir_tex_src_offset:
4559 offsets = get_src(ctx, instr->src[i].src);
4560 const_src = i;
4561 break;
4562 case nir_tex_src_bias:
4563 bias = get_src(ctx, instr->src[i].src);
4564 break;
4565 case nir_tex_src_lod: {
4566 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4567
4568 if (val && val->i32[0] == 0)
4569 lod_is_zero = true;
4570 lod = get_src(ctx, instr->src[i].src);
4571 break;
4572 }
4573 case nir_tex_src_ms_index:
4574 sample_index = get_src(ctx, instr->src[i].src);
4575 break;
4576 case nir_tex_src_ms_mcs:
4577 break;
4578 case nir_tex_src_ddx:
4579 ddx = get_src(ctx, instr->src[i].src);
4580 num_deriv_comp = instr->src[i].src.ssa->num_components;
4581 break;
4582 case nir_tex_src_ddy:
4583 ddy = get_src(ctx, instr->src[i].src);
4584 break;
4585 case nir_tex_src_texture_offset:
4586 case nir_tex_src_sampler_offset:
4587 case nir_tex_src_plane:
4588 default:
4589 break;
4590 }
4591 }
4592
4593 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4594 result = get_buffer_size(ctx, res_ptr, true);
4595 goto write_result;
4596 }
4597
4598 if (instr->op == nir_texop_texture_samples) {
4599 LLVMValueRef res, samples, is_msaa;
4600 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4601 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4602 LLVMConstInt(ctx->ac.i32, 3, false), "");
4603 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4604 LLVMConstInt(ctx->ac.i32, 28, false), "");
4605 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4606 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4607 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4608 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4609
4610 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4611 LLVMConstInt(ctx->ac.i32, 16, false), "");
4612 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4613 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4614 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4615 samples, "");
4616 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4617 ctx->ac.i32_1, "");
4618 result = samples;
4619 goto write_result;
4620 }
4621
4622 if (coord)
4623 for (chan = 0; chan < instr->coord_components; chan++)
4624 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4625
4626 if (offsets && instr->op != nir_texop_txf) {
4627 LLVMValueRef offset[3], pack;
4628 for (chan = 0; chan < 3; ++chan)
4629 offset[chan] = ctx->ac.i32_0;
4630
4631 args.offset = true;
4632 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4633 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4634 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4635 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4636 if (chan)
4637 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4638 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4639 }
4640 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4641 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4642 address[count++] = pack;
4643
4644 }
4645 /* pack LOD bias value */
4646 if (instr->op == nir_texop_txb && bias) {
4647 address[count++] = bias;
4648 }
4649
4650 /* Pack depth comparison value */
4651 if (instr->is_shadow && comparator) {
4652 LLVMValueRef z = ac_to_float(&ctx->ac,
4653 llvm_extract_elem(&ctx->ac, comparator, 0));
4654
4655 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4656 * so the depth comparison value isn't clamped for Z16 and
4657 * Z24 anymore. Do it manually here.
4658 *
4659 * It's unnecessary if the original texture format was
4660 * Z32_FLOAT, but we don't know that here.
4661 */
4662 if (ctx->ac.chip_class == VI)
4663 z = ac_build_clamp(&ctx->ac, z);
4664
4665 address[count++] = z;
4666 }
4667
4668 /* pack derivatives */
4669 if (ddx || ddy) {
4670 int num_src_deriv_channels, num_dest_deriv_channels;
4671 switch (instr->sampler_dim) {
4672 case GLSL_SAMPLER_DIM_3D:
4673 case GLSL_SAMPLER_DIM_CUBE:
4674 num_deriv_comp = 3;
4675 num_src_deriv_channels = 3;
4676 num_dest_deriv_channels = 3;
4677 break;
4678 case GLSL_SAMPLER_DIM_2D:
4679 default:
4680 num_src_deriv_channels = 2;
4681 num_dest_deriv_channels = 2;
4682 num_deriv_comp = 2;
4683 break;
4684 case GLSL_SAMPLER_DIM_1D:
4685 num_src_deriv_channels = 1;
4686 if (ctx->ac.chip_class >= GFX9) {
4687 num_dest_deriv_channels = 2;
4688 num_deriv_comp = 2;
4689 } else {
4690 num_dest_deriv_channels = 1;
4691 num_deriv_comp = 1;
4692 }
4693 break;
4694 }
4695
4696 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4697 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4698 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4699 }
4700 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4701 derivs[i] = ctx->ac.f32_0;
4702 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4703 }
4704 }
4705
4706 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4707 for (chan = 0; chan < instr->coord_components; chan++)
4708 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4709 if (instr->coord_components == 3)
4710 coords[3] = LLVMGetUndef(ctx->ac.f32);
4711 ac_prepare_cube_coords(&ctx->ac,
4712 instr->op == nir_texop_txd, instr->is_array,
4713 instr->op == nir_texop_lod, coords, derivs);
4714 if (num_deriv_comp)
4715 num_deriv_comp--;
4716 }
4717
4718 if (ddx || ddy) {
4719 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4720 address[count++] = derivs[i];
4721 }
4722
4723 /* Pack texture coordinates */
4724 if (coord) {
4725 address[count++] = coords[0];
4726 if (instr->coord_components > 1) {
4727 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4728 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4729 }
4730 address[count++] = coords[1];
4731 }
4732 if (instr->coord_components > 2) {
4733 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4734 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4735 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4736 instr->op != nir_texop_txf) {
4737 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4738 }
4739 address[count++] = coords[2];
4740 }
4741
4742 if (ctx->ac.chip_class >= GFX9) {
4743 LLVMValueRef filler;
4744 if (instr->op == nir_texop_txf)
4745 filler = ctx->ac.i32_0;
4746 else
4747 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4748
4749 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4750 if (instr->is_array) {
4751 address[count] = address[count - 1];
4752 address[count - 1] = filler;
4753 count++;
4754 } else
4755 address[count++] = filler;
4756 }
4757 }
4758 }
4759
4760 /* Pack LOD */
4761 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4762 instr->op == nir_texop_txf)) {
4763 address[count++] = lod;
4764 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4765 address[count++] = sample_index;
4766 } else if(instr->op == nir_texop_txs) {
4767 count = 0;
4768 if (lod)
4769 address[count++] = lod;
4770 else
4771 address[count++] = ctx->ac.i32_0;
4772 }
4773
4774 for (chan = 0; chan < count; chan++) {
4775 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4776 address[chan], ctx->ac.i32, "");
4777 }
4778
4779 if (instr->op == nir_texop_samples_identical) {
4780 LLVMValueRef txf_address[4];
4781 struct ac_image_args txf_args = { 0 };
4782 unsigned txf_count = count;
4783 memcpy(txf_address, address, sizeof(txf_address));
4784
4785 if (!instr->is_array)
4786 txf_address[2] = ctx->ac.i32_0;
4787 txf_address[3] = ctx->ac.i32_0;
4788
4789 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4790 fmask_ptr, NULL,
4791 txf_address, txf_count, 0xf);
4792
4793 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4794
4795 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4796 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4797 goto write_result;
4798 }
4799
4800 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4801 instr->op != nir_texop_txs) {
4802 unsigned sample_chan = instr->is_array ? 3 : 2;
4803 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4804 address[0],
4805 address[1],
4806 instr->is_array ? address[2] : NULL,
4807 address[sample_chan],
4808 fmask_ptr);
4809 }
4810
4811 if (offsets && instr->op == nir_texop_txf) {
4812 nir_const_value *const_offset =
4813 nir_src_as_const_value(instr->src[const_src].src);
4814 int num_offsets = instr->src[const_src].src.ssa->num_components;
4815 assert(const_offset);
4816 num_offsets = MIN2(num_offsets, instr->coord_components);
4817 if (num_offsets > 2)
4818 address[2] = LLVMBuildAdd(ctx->ac.builder,
4819 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4820 if (num_offsets > 1)
4821 address[1] = LLVMBuildAdd(ctx->ac.builder,
4822 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4823 address[0] = LLVMBuildAdd(ctx->ac.builder,
4824 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4825
4826 }
4827
4828 /* TODO TG4 support */
4829 if (instr->op == nir_texop_tg4) {
4830 if (instr->is_shadow)
4831 dmask = 1;
4832 else
4833 dmask = 1 << instr->component;
4834 }
4835 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4836 res_ptr, samp_ptr, address, count, dmask);
4837
4838 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4839
4840 if (instr->op == nir_texop_query_levels)
4841 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4842 else if (instr->is_shadow && instr->is_new_style_shadow &&
4843 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4844 instr->op != nir_texop_tg4)
4845 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4846 else if (instr->op == nir_texop_txs &&
4847 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4848 instr->is_array) {
4849 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4850 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4851 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4852 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4853 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4854 } else if (ctx->ac.chip_class >= GFX9 &&
4855 instr->op == nir_texop_txs &&
4856 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4857 instr->is_array) {
4858 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4859 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4860 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4861 ctx->ac.i32_1, "");
4862 } else if (instr->dest.ssa.num_components != 4)
4863 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4864
4865 write_result:
4866 if (result) {
4867 assert(instr->dest.is_ssa);
4868 result = ac_to_integer(&ctx->ac, result);
4869 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4870 }
4871 }
4872
4873
4874 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4875 {
4876 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4877 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4878
4879 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4880 _mesa_hash_table_insert(ctx->phis, instr, result);
4881 }
4882
4883 static void visit_post_phi(struct ac_nir_context *ctx,
4884 nir_phi_instr *instr,
4885 LLVMValueRef llvm_phi)
4886 {
4887 nir_foreach_phi_src(src, instr) {
4888 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4889 LLVMValueRef llvm_src = get_src(ctx, src->src);
4890
4891 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4892 }
4893 }
4894
4895 static void phi_post_pass(struct ac_nir_context *ctx)
4896 {
4897 struct hash_entry *entry;
4898 hash_table_foreach(ctx->phis, entry) {
4899 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4900 (LLVMValueRef)entry->data);
4901 }
4902 }
4903
4904
4905 static void visit_ssa_undef(struct ac_nir_context *ctx,
4906 const nir_ssa_undef_instr *instr)
4907 {
4908 unsigned num_components = instr->def.num_components;
4909 LLVMValueRef undef;
4910
4911 if (num_components == 1)
4912 undef = LLVMGetUndef(ctx->ac.i32);
4913 else {
4914 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4915 }
4916 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4917 }
4918
4919 static void visit_jump(struct ac_nir_context *ctx,
4920 const nir_jump_instr *instr)
4921 {
4922 switch (instr->type) {
4923 case nir_jump_break:
4924 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4925 LLVMClearInsertionPosition(ctx->ac.builder);
4926 break;
4927 case nir_jump_continue:
4928 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4929 LLVMClearInsertionPosition(ctx->ac.builder);
4930 break;
4931 default:
4932 fprintf(stderr, "Unknown NIR jump instr: ");
4933 nir_print_instr(&instr->instr, stderr);
4934 fprintf(stderr, "\n");
4935 abort();
4936 }
4937 }
4938
4939 static void visit_cf_list(struct ac_nir_context *ctx,
4940 struct exec_list *list);
4941
4942 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4943 {
4944 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4945 nir_foreach_instr(instr, block)
4946 {
4947 switch (instr->type) {
4948 case nir_instr_type_alu:
4949 visit_alu(ctx, nir_instr_as_alu(instr));
4950 break;
4951 case nir_instr_type_load_const:
4952 visit_load_const(ctx, nir_instr_as_load_const(instr));
4953 break;
4954 case nir_instr_type_intrinsic:
4955 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4956 break;
4957 case nir_instr_type_tex:
4958 visit_tex(ctx, nir_instr_as_tex(instr));
4959 break;
4960 case nir_instr_type_phi:
4961 visit_phi(ctx, nir_instr_as_phi(instr));
4962 break;
4963 case nir_instr_type_ssa_undef:
4964 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4965 break;
4966 case nir_instr_type_jump:
4967 visit_jump(ctx, nir_instr_as_jump(instr));
4968 break;
4969 default:
4970 fprintf(stderr, "Unknown NIR instr type: ");
4971 nir_print_instr(instr, stderr);
4972 fprintf(stderr, "\n");
4973 abort();
4974 }
4975 }
4976
4977 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4978 }
4979
4980 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4981 {
4982 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4983
4984 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4985 LLVMBasicBlockRef merge_block =
4986 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4987 LLVMBasicBlockRef if_block =
4988 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4989 LLVMBasicBlockRef else_block = merge_block;
4990 if (!exec_list_is_empty(&if_stmt->else_list))
4991 else_block = LLVMAppendBasicBlockInContext(
4992 ctx->ac.context, fn, "");
4993
4994 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4995 LLVMConstInt(ctx->ac.i32, 0, false), "");
4996 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4997
4998 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4999 visit_cf_list(ctx, &if_stmt->then_list);
5000 if (LLVMGetInsertBlock(ctx->ac.builder))
5001 LLVMBuildBr(ctx->ac.builder, merge_block);
5002
5003 if (!exec_list_is_empty(&if_stmt->else_list)) {
5004 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5005 visit_cf_list(ctx, &if_stmt->else_list);
5006 if (LLVMGetInsertBlock(ctx->ac.builder))
5007 LLVMBuildBr(ctx->ac.builder, merge_block);
5008 }
5009
5010 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5011 }
5012
5013 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5014 {
5015 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5016 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5017 LLVMBasicBlockRef break_parent = ctx->break_block;
5018
5019 ctx->continue_block =
5020 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5021 ctx->break_block =
5022 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5023
5024 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5025 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5026 visit_cf_list(ctx, &loop->body);
5027
5028 if (LLVMGetInsertBlock(ctx->ac.builder))
5029 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5030 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5031
5032 ctx->continue_block = continue_parent;
5033 ctx->break_block = break_parent;
5034 }
5035
5036 static void visit_cf_list(struct ac_nir_context *ctx,
5037 struct exec_list *list)
5038 {
5039 foreach_list_typed(nir_cf_node, node, node, list)
5040 {
5041 switch (node->type) {
5042 case nir_cf_node_block:
5043 visit_block(ctx, nir_cf_node_as_block(node));
5044 break;
5045
5046 case nir_cf_node_if:
5047 visit_if(ctx, nir_cf_node_as_if(node));
5048 break;
5049
5050 case nir_cf_node_loop:
5051 visit_loop(ctx, nir_cf_node_as_loop(node));
5052 break;
5053
5054 default:
5055 assert(0);
5056 }
5057 }
5058 }
5059
5060 static void
5061 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5062 struct nir_variable *variable)
5063 {
5064 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5065 LLVMValueRef t_offset;
5066 LLVMValueRef t_list;
5067 LLVMValueRef input;
5068 LLVMValueRef buffer_index;
5069 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5070 int idx = variable->data.location;
5071 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5072
5073 variable->data.driver_location = idx * 4;
5074
5075 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5076 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5077 ctx->abi.start_instance, "");
5078 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5079 ctx->shader_info->vs.vgpr_comp_cnt);
5080 } else
5081 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5082 ctx->abi.base_vertex, "");
5083
5084 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5085 t_offset = LLVMConstInt(ctx->i32, index + i, false);
5086
5087 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5088
5089 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5090 buffer_index,
5091 LLVMConstInt(ctx->i32, 0, false),
5092 true);
5093
5094 for (unsigned chan = 0; chan < 4; chan++) {
5095 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
5096 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5097 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5098 input, llvm_chan, ""));
5099 }
5100 }
5101 }
5102
5103 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5104 unsigned attr,
5105 LLVMValueRef interp_param,
5106 LLVMValueRef prim_mask,
5107 LLVMValueRef result[4])
5108 {
5109 LLVMValueRef attr_number;
5110 unsigned chan;
5111 LLVMValueRef i, j;
5112 bool interp = interp_param != NULL;
5113
5114 attr_number = LLVMConstInt(ctx->i32, attr, false);
5115
5116 /* fs.constant returns the param from the middle vertex, so it's not
5117 * really useful for flat shading. It's meant to be used for custom
5118 * interpolation (but the intrinsic can't fetch from the other two
5119 * vertices).
5120 *
5121 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5122 * to do the right thing. The only reason we use fs.constant is that
5123 * fs.interp cannot be used on integers, because they can be equal
5124 * to NaN.
5125 */
5126 if (interp) {
5127 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5128 LLVMVectorType(ctx->f32, 2), "");
5129
5130 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5131 ctx->i32zero, "");
5132 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5133 ctx->i32one, "");
5134 }
5135
5136 for (chan = 0; chan < 4; chan++) {
5137 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
5138
5139 if (interp) {
5140 result[chan] = ac_build_fs_interp(&ctx->ac,
5141 llvm_chan,
5142 attr_number,
5143 prim_mask, i, j);
5144 } else {
5145 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5146 LLVMConstInt(ctx->i32, 2, false),
5147 llvm_chan,
5148 attr_number,
5149 prim_mask);
5150 }
5151 }
5152 }
5153
5154 static void
5155 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5156 struct nir_variable *variable)
5157 {
5158 int idx = variable->data.location;
5159 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5160 LLVMValueRef interp;
5161
5162 variable->data.driver_location = idx * 4;
5163 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5164
5165 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5166 unsigned interp_type;
5167 if (variable->data.sample) {
5168 interp_type = INTERP_SAMPLE;
5169 ctx->shader_info->info.ps.force_persample = true;
5170 } else if (variable->data.centroid)
5171 interp_type = INTERP_CENTROID;
5172 else
5173 interp_type = INTERP_CENTER;
5174
5175 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5176 } else
5177 interp = NULL;
5178
5179 for (unsigned i = 0; i < attrib_count; ++i)
5180 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5181
5182 }
5183
5184 static void
5185 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5186 struct nir_shader *nir) {
5187 nir_foreach_variable(variable, &nir->inputs)
5188 handle_vs_input_decl(ctx, variable);
5189 }
5190
5191 static void
5192 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5193 struct nir_shader *nir)
5194 {
5195 if (!ctx->options->key.fs.multisample)
5196 return;
5197
5198 bool uses_center = false;
5199 bool uses_centroid = false;
5200 nir_foreach_variable(variable, &nir->inputs) {
5201 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5202 variable->data.sample)
5203 continue;
5204
5205 if (variable->data.centroid)
5206 uses_centroid = true;
5207 else
5208 uses_center = true;
5209 }
5210
5211 if (uses_center && uses_centroid) {
5212 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5213 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5214 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5215 }
5216 }
5217
5218 static void
5219 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5220 struct nir_shader *nir)
5221 {
5222 prepare_interp_optimize(ctx, nir);
5223
5224 nir_foreach_variable(variable, &nir->inputs)
5225 handle_fs_input_decl(ctx, variable);
5226
5227 unsigned index = 0;
5228
5229 if (ctx->shader_info->info.ps.uses_input_attachments ||
5230 ctx->shader_info->info.needs_multiview_view_index)
5231 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5232
5233 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5234 LLVMValueRef interp_param;
5235 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5236
5237 if (!(ctx->input_mask & (1ull << i)))
5238 continue;
5239
5240 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5241 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5242 interp_param = *inputs;
5243 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5244 inputs);
5245
5246 if (!interp_param)
5247 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5248 ++index;
5249 } else if (i == VARYING_SLOT_POS) {
5250 for(int i = 0; i < 3; ++i)
5251 inputs[i] = ctx->abi.frag_pos[i];
5252
5253 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one,
5254 ctx->abi.frag_pos[3]);
5255 }
5256 }
5257 ctx->shader_info->fs.num_interp = index;
5258 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5259 ctx->shader_info->fs.has_pcoord = true;
5260 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5261 ctx->shader_info->fs.prim_id_input = true;
5262 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5263 ctx->shader_info->fs.layer_input = true;
5264 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5265
5266 if (ctx->shader_info->info.needs_multiview_view_index)
5267 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5268 }
5269
5270 static LLVMValueRef
5271 ac_build_alloca(struct ac_llvm_context *ac,
5272 LLVMTypeRef type,
5273 const char *name)
5274 {
5275 LLVMBuilderRef builder = ac->builder;
5276 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5277 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5278 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5279 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5280 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5281 LLVMValueRef res;
5282
5283 if (first_instr) {
5284 LLVMPositionBuilderBefore(first_builder, first_instr);
5285 } else {
5286 LLVMPositionBuilderAtEnd(first_builder, first_block);
5287 }
5288
5289 res = LLVMBuildAlloca(first_builder, type, name);
5290 LLVMBuildStore(builder, LLVMConstNull(type), res);
5291
5292 LLVMDisposeBuilder(first_builder);
5293
5294 return res;
5295 }
5296
5297 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5298 LLVMTypeRef type,
5299 const char *name)
5300 {
5301 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5302 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5303 return ptr;
5304 }
5305
5306 static void
5307 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5308 struct nir_variable *variable,
5309 struct nir_shader *shader,
5310 gl_shader_stage stage)
5311 {
5312 int idx = variable->data.location + variable->data.index;
5313 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5314 uint64_t mask_attribs;
5315
5316 variable->data.driver_location = idx * 4;
5317
5318 /* tess ctrl has it's own load/store paths for outputs */
5319 if (stage == MESA_SHADER_TESS_CTRL)
5320 return;
5321
5322 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5323 if (stage == MESA_SHADER_VERTEX ||
5324 stage == MESA_SHADER_TESS_EVAL ||
5325 stage == MESA_SHADER_GEOMETRY) {
5326 if (idx == VARYING_SLOT_CLIP_DIST0) {
5327 int length = shader->info.clip_distance_array_size +
5328 shader->info.cull_distance_array_size;
5329 if (stage == MESA_SHADER_VERTEX) {
5330 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5331 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5332 }
5333 if (stage == MESA_SHADER_TESS_EVAL) {
5334 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5335 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5336 }
5337
5338 if (length > 4)
5339 attrib_count = 2;
5340 else
5341 attrib_count = 1;
5342 mask_attribs = 1ull << idx;
5343 }
5344 }
5345
5346 ctx->output_mask |= mask_attribs;
5347 }
5348
5349 static void
5350 handle_shader_output_decl(struct ac_nir_context *ctx,
5351 struct nir_shader *nir,
5352 struct nir_variable *variable)
5353 {
5354 unsigned output_loc = variable->data.driver_location / 4;
5355 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5356
5357 /* tess ctrl has it's own load/store paths for outputs */
5358 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5359 return;
5360
5361 if (ctx->stage == MESA_SHADER_VERTEX ||
5362 ctx->stage == MESA_SHADER_TESS_EVAL ||
5363 ctx->stage == MESA_SHADER_GEOMETRY) {
5364 int idx = variable->data.location + variable->data.index;
5365 if (idx == VARYING_SLOT_CLIP_DIST0) {
5366 int length = nir->info.clip_distance_array_size +
5367 nir->info.cull_distance_array_size;
5368
5369 if (length > 4)
5370 attrib_count = 2;
5371 else
5372 attrib_count = 1;
5373 }
5374 }
5375
5376 for (unsigned i = 0; i < attrib_count; ++i) {
5377 for (unsigned chan = 0; chan < 4; chan++) {
5378 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5379 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5380 }
5381 }
5382 }
5383
5384 static LLVMTypeRef
5385 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5386 enum glsl_base_type type)
5387 {
5388 switch (type) {
5389 case GLSL_TYPE_INT:
5390 case GLSL_TYPE_UINT:
5391 case GLSL_TYPE_BOOL:
5392 case GLSL_TYPE_SUBROUTINE:
5393 return ctx->i32;
5394 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5395 return ctx->f32;
5396 case GLSL_TYPE_INT64:
5397 case GLSL_TYPE_UINT64:
5398 return ctx->i64;
5399 case GLSL_TYPE_DOUBLE:
5400 return ctx->f64;
5401 default:
5402 unreachable("unknown GLSL type");
5403 }
5404 }
5405
5406 static LLVMTypeRef
5407 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5408 const struct glsl_type *type)
5409 {
5410 if (glsl_type_is_scalar(type)) {
5411 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5412 }
5413
5414 if (glsl_type_is_vector(type)) {
5415 return LLVMVectorType(
5416 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5417 glsl_get_vector_elements(type));
5418 }
5419
5420 if (glsl_type_is_matrix(type)) {
5421 return LLVMArrayType(
5422 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5423 glsl_get_matrix_columns(type));
5424 }
5425
5426 if (glsl_type_is_array(type)) {
5427 return LLVMArrayType(
5428 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5429 glsl_get_length(type));
5430 }
5431
5432 assert(glsl_type_is_struct(type));
5433
5434 LLVMTypeRef member_types[glsl_get_length(type)];
5435
5436 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5437 member_types[i] =
5438 glsl_to_llvm_type(ctx,
5439 glsl_get_struct_field(type, i));
5440 }
5441
5442 return LLVMStructTypeInContext(ctx->context, member_types,
5443 glsl_get_length(type), false);
5444 }
5445
5446 static void
5447 setup_locals(struct ac_nir_context *ctx,
5448 struct nir_function *func)
5449 {
5450 int i, j;
5451 ctx->num_locals = 0;
5452 nir_foreach_variable(variable, &func->impl->locals) {
5453 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5454 variable->data.driver_location = ctx->num_locals * 4;
5455 ctx->num_locals += attrib_count;
5456 }
5457 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5458 if (!ctx->locals)
5459 return;
5460
5461 for (i = 0; i < ctx->num_locals; i++) {
5462 for (j = 0; j < 4; j++) {
5463 ctx->locals[i * 4 + j] =
5464 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5465 }
5466 }
5467 }
5468
5469 static void
5470 setup_shared(struct ac_nir_context *ctx,
5471 struct nir_shader *nir)
5472 {
5473 nir_foreach_variable(variable, &nir->shared) {
5474 LLVMValueRef shared =
5475 LLVMAddGlobalInAddressSpace(
5476 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5477 variable->name ? variable->name : "",
5478 LOCAL_ADDR_SPACE);
5479 _mesa_hash_table_insert(ctx->vars, variable, shared);
5480 }
5481 }
5482
5483 static LLVMValueRef
5484 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5485 {
5486 v = ac_to_float(ctx, v);
5487 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5488 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5489 }
5490
5491
5492 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5493 LLVMValueRef src0, LLVMValueRef src1)
5494 {
5495 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5496 LLVMValueRef comp[2];
5497
5498 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5499 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5500 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5501 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5502 }
5503
5504 /* Initialize arguments for the shader export intrinsic */
5505 static void
5506 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5507 LLVMValueRef *values,
5508 unsigned target,
5509 struct ac_export_args *args)
5510 {
5511 /* Default is 0xf. Adjusted below depending on the format. */
5512 args->enabled_channels = 0xf;
5513
5514 /* Specify whether the EXEC mask represents the valid mask */
5515 args->valid_mask = 0;
5516
5517 /* Specify whether this is the last export */
5518 args->done = 0;
5519
5520 /* Specify the target we are exporting */
5521 args->target = target;
5522
5523 args->compr = false;
5524 args->out[0] = LLVMGetUndef(ctx->f32);
5525 args->out[1] = LLVMGetUndef(ctx->f32);
5526 args->out[2] = LLVMGetUndef(ctx->f32);
5527 args->out[3] = LLVMGetUndef(ctx->f32);
5528
5529 if (!values)
5530 return;
5531
5532 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5533 LLVMValueRef val[4];
5534 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5535 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5536 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5537 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5538
5539 switch(col_format) {
5540 case V_028714_SPI_SHADER_ZERO:
5541 args->enabled_channels = 0; /* writemask */
5542 args->target = V_008DFC_SQ_EXP_NULL;
5543 break;
5544
5545 case V_028714_SPI_SHADER_32_R:
5546 args->enabled_channels = 1;
5547 args->out[0] = values[0];
5548 break;
5549
5550 case V_028714_SPI_SHADER_32_GR:
5551 args->enabled_channels = 0x3;
5552 args->out[0] = values[0];
5553 args->out[1] = values[1];
5554 break;
5555
5556 case V_028714_SPI_SHADER_32_AR:
5557 args->enabled_channels = 0x9;
5558 args->out[0] = values[0];
5559 args->out[3] = values[3];
5560 break;
5561
5562 case V_028714_SPI_SHADER_FP16_ABGR:
5563 args->compr = 1;
5564
5565 for (unsigned chan = 0; chan < 2; chan++) {
5566 LLVMValueRef pack_args[2] = {
5567 values[2 * chan],
5568 values[2 * chan + 1]
5569 };
5570 LLVMValueRef packed;
5571
5572 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5573 args->out[chan] = packed;
5574 }
5575 break;
5576
5577 case V_028714_SPI_SHADER_UNORM16_ABGR:
5578 for (unsigned chan = 0; chan < 4; chan++) {
5579 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5580 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5581 LLVMConstReal(ctx->f32, 65535), "");
5582 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5583 LLVMConstReal(ctx->f32, 0.5), "");
5584 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5585 ctx->i32, "");
5586 }
5587
5588 args->compr = 1;
5589 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5590 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5591 break;
5592
5593 case V_028714_SPI_SHADER_SNORM16_ABGR:
5594 for (unsigned chan = 0; chan < 4; chan++) {
5595 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5596 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5597 LLVMConstReal(ctx->f32, 32767), "");
5598
5599 /* If positive, add 0.5, else add -0.5. */
5600 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5601 LLVMBuildSelect(ctx->builder,
5602 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5603 val[chan], ctx->f32zero, ""),
5604 LLVMConstReal(ctx->f32, 0.5),
5605 LLVMConstReal(ctx->f32, -0.5), ""), "");
5606 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5607 }
5608
5609 args->compr = 1;
5610 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5611 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5612 break;
5613
5614 case V_028714_SPI_SHADER_UINT16_ABGR: {
5615 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5616 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5617 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
5618
5619 for (unsigned chan = 0; chan < 4; chan++) {
5620 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5621 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5622 }
5623
5624 args->compr = 1;
5625 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5626 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5627 break;
5628 }
5629
5630 case V_028714_SPI_SHADER_SINT16_ABGR: {
5631 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
5632 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5633 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
5634 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5635 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->i32one;
5636 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
5637
5638 /* Clamp. */
5639 for (unsigned chan = 0; chan < 4; chan++) {
5640 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5641 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5642 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5643 }
5644
5645 args->compr = 1;
5646 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5647 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5648 break;
5649 }
5650
5651 default:
5652 case V_028714_SPI_SHADER_32_ABGR:
5653 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5654 break;
5655 }
5656 } else
5657 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5658
5659 for (unsigned i = 0; i < 4; ++i)
5660 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5661 }
5662
5663 static void
5664 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5665 bool export_prim_id,
5666 struct ac_vs_output_info *outinfo)
5667 {
5668 uint32_t param_count = 0;
5669 unsigned target;
5670 unsigned pos_idx, num_pos_exports = 0;
5671 struct ac_export_args args, pos_args[4] = {};
5672 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5673 int i;
5674
5675 if (ctx->options->key.has_multiview_view_index) {
5676 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5677 if(!*tmp_out) {
5678 for(unsigned i = 0; i < 4; ++i)
5679 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5680 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5681 }
5682
5683 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5684 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5685 }
5686
5687 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5688 sizeof(outinfo->vs_output_param_offset));
5689
5690 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5691 LLVMValueRef slots[8];
5692 unsigned j;
5693
5694 if (outinfo->cull_dist_mask)
5695 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5696
5697 i = VARYING_SLOT_CLIP_DIST0;
5698 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5699 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5700 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5701
5702 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5703 slots[i] = LLVMGetUndef(ctx->f32);
5704
5705 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5706 target = V_008DFC_SQ_EXP_POS + 3;
5707 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5708 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5709 &args, sizeof(args));
5710 }
5711
5712 target = V_008DFC_SQ_EXP_POS + 2;
5713 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5714 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5715 &args, sizeof(args));
5716
5717 }
5718
5719 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5720 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5721 for (unsigned j = 0; j < 4; j++)
5722 pos_values[j] = LLVMBuildLoad(ctx->builder,
5723 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5724 }
5725 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5726
5727 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5728 outinfo->writes_pointsize = true;
5729 psize_value = LLVMBuildLoad(ctx->builder,
5730 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5731 }
5732
5733 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5734 outinfo->writes_layer = true;
5735 layer_value = LLVMBuildLoad(ctx->builder,
5736 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5737 }
5738
5739 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5740 outinfo->writes_viewport_index = true;
5741 viewport_index_value = LLVMBuildLoad(ctx->builder,
5742 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5743 }
5744
5745 if (outinfo->writes_pointsize ||
5746 outinfo->writes_layer ||
5747 outinfo->writes_viewport_index) {
5748 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5749 (outinfo->writes_layer == true ? 4 : 0));
5750 pos_args[1].valid_mask = 0;
5751 pos_args[1].done = 0;
5752 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5753 pos_args[1].compr = 0;
5754 pos_args[1].out[0] = ctx->f32zero; /* X */
5755 pos_args[1].out[1] = ctx->f32zero; /* Y */
5756 pos_args[1].out[2] = ctx->f32zero; /* Z */
5757 pos_args[1].out[3] = ctx->f32zero; /* W */
5758
5759 if (outinfo->writes_pointsize == true)
5760 pos_args[1].out[0] = psize_value;
5761 if (outinfo->writes_layer == true)
5762 pos_args[1].out[2] = layer_value;
5763 if (outinfo->writes_viewport_index == true) {
5764 if (ctx->options->chip_class >= GFX9) {
5765 /* GFX9 has the layer in out.z[10:0] and the viewport
5766 * index in out.z[19:16].
5767 */
5768 LLVMValueRef v = viewport_index_value;
5769 v = ac_to_integer(&ctx->ac, v);
5770 v = LLVMBuildShl(ctx->builder, v,
5771 LLVMConstInt(ctx->i32, 16, false),
5772 "");
5773 v = LLVMBuildOr(ctx->builder, v,
5774 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5775
5776 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5777 pos_args[1].enabled_channels |= 1 << 2;
5778 } else {
5779 pos_args[1].out[3] = viewport_index_value;
5780 pos_args[1].enabled_channels |= 1 << 3;
5781 }
5782 }
5783 }
5784 for (i = 0; i < 4; i++) {
5785 if (pos_args[i].out[0])
5786 num_pos_exports++;
5787 }
5788
5789 pos_idx = 0;
5790 for (i = 0; i < 4; i++) {
5791 if (!pos_args[i].out[0])
5792 continue;
5793
5794 /* Specify the target we are exporting */
5795 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5796 if (pos_idx == num_pos_exports)
5797 pos_args[i].done = 1;
5798 ac_build_export(&ctx->ac, &pos_args[i]);
5799 }
5800
5801 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5802 LLVMValueRef values[4];
5803 if (!(ctx->output_mask & (1ull << i)))
5804 continue;
5805
5806 for (unsigned j = 0; j < 4; j++)
5807 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5808 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5809
5810 if (i == VARYING_SLOT_LAYER) {
5811 target = V_008DFC_SQ_EXP_PARAM + param_count;
5812 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5813 param_count++;
5814 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5815 target = V_008DFC_SQ_EXP_PARAM + param_count;
5816 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5817 param_count++;
5818 } else if (i >= VARYING_SLOT_VAR0) {
5819 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5820 target = V_008DFC_SQ_EXP_PARAM + param_count;
5821 outinfo->vs_output_param_offset[i] = param_count;
5822 param_count++;
5823 } else
5824 continue;
5825
5826 si_llvm_init_export_args(ctx, values, target, &args);
5827
5828 if (target >= V_008DFC_SQ_EXP_POS &&
5829 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5830 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5831 &args, sizeof(args));
5832 } else {
5833 ac_build_export(&ctx->ac, &args);
5834 }
5835 }
5836
5837 if (export_prim_id) {
5838 LLVMValueRef values[4];
5839 target = V_008DFC_SQ_EXP_PARAM + param_count;
5840 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5841 param_count++;
5842
5843 values[0] = ctx->vs_prim_id;
5844 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5845 ctx->shader_info->vs.vgpr_comp_cnt);
5846 for (unsigned j = 1; j < 4; j++)
5847 values[j] = ctx->f32zero;
5848 si_llvm_init_export_args(ctx, values, target, &args);
5849 ac_build_export(&ctx->ac, &args);
5850 outinfo->export_prim_id = true;
5851 }
5852
5853 outinfo->pos_exports = num_pos_exports;
5854 outinfo->param_exports = param_count;
5855 }
5856
5857 static void
5858 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5859 struct ac_es_output_info *outinfo)
5860 {
5861 int j;
5862 uint64_t max_output_written = 0;
5863 LLVMValueRef lds_base = NULL;
5864
5865 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5866 int param_index;
5867 int length = 4;
5868
5869 if (!(ctx->output_mask & (1ull << i)))
5870 continue;
5871
5872 if (i == VARYING_SLOT_CLIP_DIST0)
5873 length = ctx->num_output_clips + ctx->num_output_culls;
5874
5875 param_index = shader_io_get_unique_index(i);
5876
5877 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5878 }
5879
5880 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5881
5882 if (ctx->ac.chip_class >= GFX9) {
5883 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5884 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5885 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5886 LLVMConstInt(ctx->ac.i32, 24, false),
5887 LLVMConstInt(ctx->ac.i32, 4, false), false);
5888 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5889 LLVMBuildMul(ctx->ac.builder, wave_idx,
5890 LLVMConstInt(ctx->i32, 64, false), ""), "");
5891 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5892 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
5893 }
5894
5895 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5896 LLVMValueRef dw_addr;
5897 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5898 int param_index;
5899 int length = 4;
5900
5901 if (!(ctx->output_mask & (1ull << i)))
5902 continue;
5903
5904 if (i == VARYING_SLOT_CLIP_DIST0)
5905 length = ctx->num_output_clips + ctx->num_output_culls;
5906
5907 param_index = shader_io_get_unique_index(i);
5908
5909 if (lds_base) {
5910 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5911 LLVMConstInt(ctx->i32, param_index * 4, false),
5912 "");
5913 }
5914 for (j = 0; j < length; j++) {
5915 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5916 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5917
5918 if (ctx->ac.chip_class >= GFX9) {
5919 lds_store(ctx, dw_addr,
5920 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5921 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5922 } else {
5923 ac_build_buffer_store_dword(&ctx->ac,
5924 ctx->esgs_ring,
5925 out_val, 1,
5926 NULL, ctx->es2gs_offset,
5927 (4 * param_index + j) * 4,
5928 1, 1, true, true);
5929 }
5930 }
5931 }
5932 }
5933
5934 static void
5935 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5936 {
5937 LLVMValueRef vertex_id = ctx->rel_auto_id;
5938 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5939 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5940 vertex_dw_stride, "");
5941
5942 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5943 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5944 int length = 4;
5945
5946 if (!(ctx->output_mask & (1ull << i)))
5947 continue;
5948
5949 if (i == VARYING_SLOT_CLIP_DIST0)
5950 length = ctx->num_output_clips + ctx->num_output_culls;
5951 int param = shader_io_get_unique_index(i);
5952 mark_tess_output(ctx, false, param);
5953 if (length > 4)
5954 mark_tess_output(ctx, false, param + 1);
5955 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5956 LLVMConstInt(ctx->i32, param * 4, false),
5957 "");
5958 for (unsigned j = 0; j < length; j++) {
5959 lds_store(ctx, dw_addr,
5960 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5961 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5962 }
5963 }
5964 }
5965
5966 struct ac_build_if_state
5967 {
5968 struct nir_to_llvm_context *ctx;
5969 LLVMValueRef condition;
5970 LLVMBasicBlockRef entry_block;
5971 LLVMBasicBlockRef true_block;
5972 LLVMBasicBlockRef false_block;
5973 LLVMBasicBlockRef merge_block;
5974 };
5975
5976 static LLVMBasicBlockRef
5977 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5978 {
5979 LLVMBasicBlockRef current_block;
5980 LLVMBasicBlockRef next_block;
5981 LLVMBasicBlockRef new_block;
5982
5983 /* get current basic block */
5984 current_block = LLVMGetInsertBlock(ctx->builder);
5985
5986 /* chqeck if there's another block after this one */
5987 next_block = LLVMGetNextBasicBlock(current_block);
5988 if (next_block) {
5989 /* insert the new block before the next block */
5990 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5991 }
5992 else {
5993 /* append new block after current block */
5994 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5995 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5996 }
5997 return new_block;
5998 }
5999
6000 static void
6001 ac_nir_build_if(struct ac_build_if_state *ifthen,
6002 struct nir_to_llvm_context *ctx,
6003 LLVMValueRef condition)
6004 {
6005 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6006
6007 memset(ifthen, 0, sizeof *ifthen);
6008 ifthen->ctx = ctx;
6009 ifthen->condition = condition;
6010 ifthen->entry_block = block;
6011
6012 /* create endif/merge basic block for the phi functions */
6013 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6014
6015 /* create/insert true_block before merge_block */
6016 ifthen->true_block =
6017 LLVMInsertBasicBlockInContext(ctx->context,
6018 ifthen->merge_block,
6019 "if-true-block");
6020
6021 /* successive code goes into the true block */
6022 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6023 }
6024
6025 /**
6026 * End a conditional.
6027 */
6028 static void
6029 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6030 {
6031 LLVMBuilderRef builder = ifthen->ctx->builder;
6032
6033 /* Insert branch to the merge block from current block */
6034 LLVMBuildBr(builder, ifthen->merge_block);
6035
6036 /*
6037 * Now patch in the various branch instructions.
6038 */
6039
6040 /* Insert the conditional branch instruction at the end of entry_block */
6041 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6042 if (ifthen->false_block) {
6043 /* we have an else clause */
6044 LLVMBuildCondBr(builder, ifthen->condition,
6045 ifthen->true_block, ifthen->false_block);
6046 }
6047 else {
6048 /* no else clause */
6049 LLVMBuildCondBr(builder, ifthen->condition,
6050 ifthen->true_block, ifthen->merge_block);
6051 }
6052
6053 /* Resume building code at end of the ifthen->merge_block */
6054 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6055 }
6056
6057 static void
6058 write_tess_factors(struct nir_to_llvm_context *ctx)
6059 {
6060 unsigned stride, outer_comps, inner_comps;
6061 struct ac_build_if_state if_ctx, inner_if_ctx;
6062 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
6063 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
6064 unsigned tess_inner_index, tess_outer_index;
6065 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6066 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6067 int i;
6068 emit_barrier(ctx);
6069
6070 switch (ctx->options->key.tcs.primitive_mode) {
6071 case GL_ISOLINES:
6072 stride = 2;
6073 outer_comps = 2;
6074 inner_comps = 0;
6075 break;
6076 case GL_TRIANGLES:
6077 stride = 4;
6078 outer_comps = 3;
6079 inner_comps = 1;
6080 break;
6081 case GL_QUADS:
6082 stride = 6;
6083 outer_comps = 4;
6084 inner_comps = 2;
6085 break;
6086 default:
6087 return;
6088 }
6089
6090 ac_nir_build_if(&if_ctx, ctx,
6091 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6092 invocation_id, ctx->i32zero, ""));
6093
6094 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6095 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6096
6097 mark_tess_output(ctx, true, tess_inner_index);
6098 mark_tess_output(ctx, true, tess_outer_index);
6099 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6100 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6101 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
6102 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6103 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
6104
6105 for (i = 0; i < 4; i++) {
6106 inner[i] = LLVMGetUndef(ctx->i32);
6107 outer[i] = LLVMGetUndef(ctx->i32);
6108 }
6109
6110 // LINES reverseal
6111 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6112 outer[0] = out[1] = lds_load(ctx, lds_outer);
6113 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6114 LLVMConstInt(ctx->i32, 1, false), "");
6115 outer[1] = out[0] = lds_load(ctx, lds_outer);
6116 } else {
6117 for (i = 0; i < outer_comps; i++) {
6118 outer[i] = out[i] =
6119 lds_load(ctx, lds_outer);
6120 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6121 LLVMConstInt(ctx->i32, 1, false), "");
6122 }
6123 for (i = 0; i < inner_comps; i++) {
6124 inner[i] = out[outer_comps+i] =
6125 lds_load(ctx, lds_inner);
6126 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6127 LLVMConstInt(ctx->i32, 1, false), "");
6128 }
6129 }
6130
6131 /* Convert the outputs to vectors for stores. */
6132 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6133 vec1 = NULL;
6134
6135 if (stride > 4)
6136 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6137
6138
6139 buffer = ctx->hs_ring_tess_factor;
6140 tf_base = ctx->tess_factor_offset;
6141 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6142 LLVMConstInt(ctx->i32, 4 * stride, false), "");
6143 unsigned tf_offset = 0;
6144
6145 if (ctx->options->chip_class <= VI) {
6146 ac_nir_build_if(&inner_if_ctx, ctx,
6147 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6148 rel_patch_id, ctx->i32zero, ""));
6149
6150 /* Store the dynamic HS control word. */
6151 ac_build_buffer_store_dword(&ctx->ac, buffer,
6152 LLVMConstInt(ctx->i32, 0x80000000, false),
6153 1, ctx->i32zero, tf_base,
6154 0, 1, 0, true, false);
6155 tf_offset += 4;
6156
6157 ac_nir_build_endif(&inner_if_ctx);
6158 }
6159
6160 /* Store the tessellation factors. */
6161 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6162 MIN2(stride, 4), byteoffset, tf_base,
6163 tf_offset, 1, 0, true, false);
6164 if (vec1)
6165 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6166 stride - 4, byteoffset, tf_base,
6167 16 + tf_offset, 1, 0, true, false);
6168
6169 //TODO store to offchip for TES to read - only if TES reads them
6170 if (1) {
6171 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6172 LLVMValueRef tf_inner_offset;
6173 unsigned param_outer, param_inner;
6174
6175 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6176 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6177 LLVMConstInt(ctx->i32, param_outer, 0));
6178
6179 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6180 util_next_power_of_two(outer_comps));
6181
6182 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6183 outer_comps, tf_outer_offset,
6184 ctx->oc_lds, 0, 1, 0, true, false);
6185 if (inner_comps) {
6186 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6187 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6188 LLVMConstInt(ctx->i32, param_inner, 0));
6189
6190 inner_vec = inner_comps == 1 ? inner[0] :
6191 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6192 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6193 inner_comps, tf_inner_offset,
6194 ctx->oc_lds, 0, 1, 0, true, false);
6195 }
6196 }
6197 ac_nir_build_endif(&if_ctx);
6198 }
6199
6200 static void
6201 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6202 {
6203 write_tess_factors(ctx);
6204 }
6205
6206 static bool
6207 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6208 LLVMValueRef *color, unsigned param, bool is_last,
6209 struct ac_export_args *args)
6210 {
6211 /* Export */
6212 si_llvm_init_export_args(ctx, color, param,
6213 args);
6214
6215 if (is_last) {
6216 args->valid_mask = 1; /* whether the EXEC mask is valid */
6217 args->done = 1; /* DONE bit */
6218 } else if (!args->enabled_channels)
6219 return false; /* unnecessary NULL export */
6220
6221 return true;
6222 }
6223
6224 static void
6225 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6226 LLVMValueRef depth, LLVMValueRef stencil,
6227 LLVMValueRef samplemask)
6228 {
6229 struct ac_export_args args;
6230
6231 args.enabled_channels = 0;
6232 args.valid_mask = 1;
6233 args.done = 1;
6234 args.target = V_008DFC_SQ_EXP_MRTZ;
6235 args.compr = false;
6236
6237 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
6238 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6239 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
6240 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
6241
6242 if (depth) {
6243 args.out[0] = depth;
6244 args.enabled_channels |= 0x1;
6245 }
6246
6247 if (stencil) {
6248 args.out[1] = stencil;
6249 args.enabled_channels |= 0x2;
6250 }
6251
6252 if (samplemask) {
6253 args.out[2] = samplemask;
6254 args.enabled_channels |= 0x4;
6255 }
6256
6257 /* SI (except OLAND and HAINAN) has a bug that it only looks
6258 * at the X writemask component. */
6259 if (ctx->options->chip_class == SI &&
6260 ctx->options->family != CHIP_OLAND &&
6261 ctx->options->family != CHIP_HAINAN)
6262 args.enabled_channels |= 0x1;
6263
6264 ac_build_export(&ctx->ac, &args);
6265 }
6266
6267 static void
6268 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6269 {
6270 unsigned index = 0;
6271 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6272 struct ac_export_args color_args[8];
6273
6274 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6275 LLVMValueRef values[4];
6276
6277 if (!(ctx->output_mask & (1ull << i)))
6278 continue;
6279
6280 if (i == FRAG_RESULT_DEPTH) {
6281 ctx->shader_info->fs.writes_z = true;
6282 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6283 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6284 } else if (i == FRAG_RESULT_STENCIL) {
6285 ctx->shader_info->fs.writes_stencil = true;
6286 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6287 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6288 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6289 ctx->shader_info->fs.writes_sample_mask = true;
6290 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6291 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6292 } else {
6293 bool last = false;
6294 for (unsigned j = 0; j < 4; j++)
6295 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6296 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6297
6298 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6299 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6300
6301 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6302 if (ret)
6303 index++;
6304 }
6305 }
6306
6307 for (unsigned i = 0; i < index; i++)
6308 ac_build_export(&ctx->ac, &color_args[i]);
6309 if (depth || stencil || samplemask)
6310 si_export_mrt_z(ctx, depth, stencil, samplemask);
6311 else if (!index) {
6312 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6313 ac_build_export(&ctx->ac, &color_args[0]);
6314 }
6315
6316 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6317 }
6318
6319 static void
6320 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6321 {
6322 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6323 }
6324
6325 static void
6326 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6327 LLVMValueRef *addrs)
6328 {
6329 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6330
6331 switch (ctx->stage) {
6332 case MESA_SHADER_VERTEX:
6333 if (ctx->options->key.vs.as_ls)
6334 handle_ls_outputs_post(ctx);
6335 else if (ctx->options->key.vs.as_es)
6336 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6337 else
6338 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6339 &ctx->shader_info->vs.outinfo);
6340 break;
6341 case MESA_SHADER_FRAGMENT:
6342 handle_fs_outputs_post(ctx);
6343 break;
6344 case MESA_SHADER_GEOMETRY:
6345 emit_gs_epilogue(ctx);
6346 break;
6347 case MESA_SHADER_TESS_CTRL:
6348 handle_tcs_outputs_post(ctx);
6349 break;
6350 case MESA_SHADER_TESS_EVAL:
6351 if (ctx->options->key.tes.as_es)
6352 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6353 else
6354 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6355 &ctx->shader_info->tes.outinfo);
6356 break;
6357 default:
6358 break;
6359 }
6360 }
6361
6362 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6363 {
6364 LLVMPassManagerRef passmgr;
6365 /* Create the pass manager */
6366 passmgr = LLVMCreateFunctionPassManagerForModule(
6367 ctx->module);
6368
6369 /* This pass should eliminate all the load and store instructions */
6370 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6371
6372 /* Add some optimization passes */
6373 LLVMAddScalarReplAggregatesPass(passmgr);
6374 LLVMAddLICMPass(passmgr);
6375 LLVMAddAggressiveDCEPass(passmgr);
6376 LLVMAddCFGSimplificationPass(passmgr);
6377 LLVMAddInstructionCombiningPass(passmgr);
6378
6379 /* Run the pass */
6380 LLVMInitializeFunctionPassManager(passmgr);
6381 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6382 LLVMFinalizeFunctionPassManager(passmgr);
6383
6384 LLVMDisposeBuilder(ctx->builder);
6385 LLVMDisposePassManager(passmgr);
6386 }
6387
6388 static void
6389 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6390 {
6391 struct ac_vs_output_info *outinfo;
6392
6393 switch (ctx->stage) {
6394 case MESA_SHADER_FRAGMENT:
6395 case MESA_SHADER_COMPUTE:
6396 case MESA_SHADER_TESS_CTRL:
6397 case MESA_SHADER_GEOMETRY:
6398 return;
6399 case MESA_SHADER_VERTEX:
6400 if (ctx->options->key.vs.as_ls ||
6401 ctx->options->key.vs.as_es)
6402 return;
6403 outinfo = &ctx->shader_info->vs.outinfo;
6404 break;
6405 case MESA_SHADER_TESS_EVAL:
6406 if (ctx->options->key.vs.as_es)
6407 return;
6408 outinfo = &ctx->shader_info->tes.outinfo;
6409 break;
6410 default:
6411 unreachable("Unhandled shader type");
6412 }
6413
6414 ac_optimize_vs_outputs(&ctx->ac,
6415 ctx->main_function,
6416 outinfo->vs_output_param_offset,
6417 VARYING_SLOT_MAX,
6418 &outinfo->param_exports);
6419 }
6420
6421 static void
6422 ac_setup_rings(struct nir_to_llvm_context *ctx)
6423 {
6424 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6425 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6426 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6427 }
6428
6429 if (ctx->is_gs_copy_shader) {
6430 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6431 }
6432 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6433 LLVMValueRef tmp;
6434 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6435 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6436
6437 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6438
6439 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6440 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6441 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6442 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6443 }
6444
6445 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6446 ctx->stage == MESA_SHADER_TESS_EVAL) {
6447 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6448 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6449 }
6450 }
6451
6452 static unsigned
6453 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6454 const struct nir_shader *nir)
6455 {
6456 switch (nir->stage) {
6457 case MESA_SHADER_TESS_CTRL:
6458 return chip_class >= CIK ? 128 : 64;
6459 case MESA_SHADER_GEOMETRY:
6460 return 64;
6461 case MESA_SHADER_COMPUTE:
6462 break;
6463 default:
6464 return 0;
6465 }
6466
6467 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6468 nir->info.cs.local_size[1] *
6469 nir->info.cs.local_size[2];
6470 return max_workgroup_size;
6471 }
6472
6473 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6474 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6475 {
6476 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6477 LLVMConstInt(ctx->ac.i32, 8, false),
6478 LLVMConstInt(ctx->ac.i32, 8, false), false);
6479 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6480 LLVMConstInt(ctx->ac.i32, 0, false), "");
6481 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6482 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6483 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6484 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6485 }
6486
6487 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6488 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6489 {
6490 struct ac_nir_context ctx = {};
6491 struct nir_function *func;
6492
6493 ctx.ac = *ac;
6494 ctx.abi = abi;
6495
6496 ctx.nctx = nctx;
6497 if (nctx)
6498 nctx->nir = &ctx;
6499
6500 ctx.stage = nir->stage;
6501
6502 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6503
6504 nir_foreach_variable(variable, &nir->outputs)
6505 handle_shader_output_decl(&ctx, nir, variable);
6506
6507 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6508 _mesa_key_pointer_equal);
6509 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6510 _mesa_key_pointer_equal);
6511 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6512 _mesa_key_pointer_equal);
6513
6514 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6515
6516 setup_locals(&ctx, func);
6517
6518 if (nir->stage == MESA_SHADER_COMPUTE)
6519 setup_shared(&ctx, nir);
6520
6521 visit_cf_list(&ctx, &func->impl->body);
6522 phi_post_pass(&ctx);
6523
6524 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6525 ctx.outputs);
6526
6527 free(ctx.locals);
6528 ralloc_free(ctx.defs);
6529 ralloc_free(ctx.phis);
6530 ralloc_free(ctx.vars);
6531
6532 if (nctx)
6533 nctx->nir = NULL;
6534 }
6535
6536 static
6537 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6538 struct nir_shader *const *shaders,
6539 int shader_count,
6540 struct ac_shader_variant_info *shader_info,
6541 const struct ac_nir_compiler_options *options)
6542 {
6543 struct nir_to_llvm_context ctx = {0};
6544 unsigned i;
6545 ctx.options = options;
6546 ctx.shader_info = shader_info;
6547 ctx.context = LLVMContextCreate();
6548 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6549
6550 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6551 ctx.ac.module = ctx.module;
6552 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6553
6554 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6555 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6556 LLVMSetDataLayout(ctx.module, data_layout_str);
6557 LLVMDisposeTargetData(data_layout);
6558 LLVMDisposeMessage(data_layout_str);
6559
6560 setup_types(&ctx);
6561 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6562 ctx.ac.builder = ctx.builder;
6563
6564 memset(shader_info, 0, sizeof(*shader_info));
6565
6566 for(int i = 0; i < shader_count; ++i)
6567 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6568
6569 for (i = 0; i < AC_UD_MAX_SETS; i++)
6570 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6571 for (i = 0; i < AC_UD_MAX_UD; i++)
6572 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6573
6574 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, shaders[0]);
6575
6576 create_function(&ctx, shaders[shader_count - 1]->stage, shader_count >= 2,
6577 shader_count >= 2 ? shaders[shader_count - 2]->stage : MESA_SHADER_VERTEX);
6578
6579 ctx.abi.inputs = &ctx.inputs[0];
6580 ctx.abi.emit_outputs = handle_shader_outputs_post;
6581 ctx.abi.load_ssbo = radv_load_ssbo;
6582 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6583
6584 if (shader_count >= 2)
6585 ac_init_exec_full_mask(&ctx.ac);
6586
6587 if (ctx.ac.chip_class == GFX9 &&
6588 shaders[shader_count - 1]->stage == MESA_SHADER_TESS_CTRL)
6589 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6590
6591 for(int i = 0; i < shader_count; ++i) {
6592 ctx.stage = shaders[i]->stage;
6593 ctx.output_mask = 0;
6594 ctx.tess_outputs_written = 0;
6595 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6596 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6597
6598 if (shaders[i]->stage == MESA_SHADER_GEOMETRY) {
6599 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6600
6601 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6602 } else if (shaders[i]->stage == MESA_SHADER_TESS_EVAL) {
6603 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6604 } else if (shaders[i]->stage == MESA_SHADER_VERTEX) {
6605 if (shader_info->info.vs.needs_instance_id) {
6606 ctx.shader_info->vs.vgpr_comp_cnt =
6607 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6608 }
6609 } else if (shaders[i]->stage == MESA_SHADER_FRAGMENT) {
6610 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6611 }
6612
6613 if (i)
6614 emit_barrier(&ctx);
6615
6616 ac_setup_rings(&ctx);
6617
6618 LLVMBasicBlockRef merge_block;
6619 if (shader_count >= 2) {
6620 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6621 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6622 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6623
6624 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6625 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6626 LLVMConstInt(ctx.ac.i32, 8, false), false);
6627 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6628 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6629 thread_id, count, "");
6630 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6631
6632 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6633 }
6634
6635 if (shaders[i]->stage == MESA_SHADER_FRAGMENT)
6636 handle_fs_inputs(&ctx, shaders[i]);
6637 else if(shaders[i]->stage == MESA_SHADER_VERTEX)
6638 handle_vs_inputs(&ctx, shaders[i]);
6639
6640 nir_foreach_variable(variable, &shaders[i]->outputs)
6641 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->stage);
6642
6643 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6644
6645 if (shader_count >= 2) {
6646 LLVMBuildBr(ctx.ac.builder, merge_block);
6647 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6648 }
6649
6650 if (shaders[i]->stage == MESA_SHADER_GEOMETRY) {
6651 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6652 shaders[i]->info.cull_distance_array_size > 4;
6653 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6654 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6655 shaders[i]->info.gs.vertices_out;
6656 } else if (shaders[i]->stage == MESA_SHADER_TESS_CTRL) {
6657 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6658 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6659 } else if (shaders[i]->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6660 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6661 }
6662 }
6663
6664 LLVMBuildRetVoid(ctx.builder);
6665
6666 ac_llvm_finalize_module(&ctx);
6667
6668 if (shader_count == 1)
6669 ac_nir_eliminate_const_vs_outputs(&ctx);
6670
6671 return ctx.module;
6672 }
6673
6674 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6675 {
6676 unsigned *retval = (unsigned *)context;
6677 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6678 char *description = LLVMGetDiagInfoDescription(di);
6679
6680 if (severity == LLVMDSError) {
6681 *retval = 1;
6682 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6683 description);
6684 }
6685
6686 LLVMDisposeMessage(description);
6687 }
6688
6689 static unsigned ac_llvm_compile(LLVMModuleRef M,
6690 struct ac_shader_binary *binary,
6691 LLVMTargetMachineRef tm)
6692 {
6693 unsigned retval = 0;
6694 char *err;
6695 LLVMContextRef llvm_ctx;
6696 LLVMMemoryBufferRef out_buffer;
6697 unsigned buffer_size;
6698 const char *buffer_data;
6699 LLVMBool mem_err;
6700
6701 /* Setup Diagnostic Handler*/
6702 llvm_ctx = LLVMGetModuleContext(M);
6703
6704 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6705 &retval);
6706
6707 /* Compile IR*/
6708 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6709 &err, &out_buffer);
6710
6711 /* Process Errors/Warnings */
6712 if (mem_err) {
6713 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6714 free(err);
6715 retval = 1;
6716 goto out;
6717 }
6718
6719 /* Extract Shader Code*/
6720 buffer_size = LLVMGetBufferSize(out_buffer);
6721 buffer_data = LLVMGetBufferStart(out_buffer);
6722
6723 ac_elf_read(buffer_data, buffer_size, binary);
6724
6725 /* Clean up */
6726 LLVMDisposeMemoryBuffer(out_buffer);
6727
6728 out:
6729 return retval;
6730 }
6731
6732 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6733 LLVMModuleRef llvm_module,
6734 struct ac_shader_binary *binary,
6735 struct ac_shader_config *config,
6736 struct ac_shader_variant_info *shader_info,
6737 gl_shader_stage stage,
6738 bool dump_shader, bool supports_spill)
6739 {
6740 if (dump_shader)
6741 ac_dump_module(llvm_module);
6742
6743 memset(binary, 0, sizeof(*binary));
6744 int v = ac_llvm_compile(llvm_module, binary, tm);
6745 if (v) {
6746 fprintf(stderr, "compile failed\n");
6747 }
6748
6749 if (dump_shader)
6750 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6751
6752 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6753
6754 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6755 LLVMDisposeModule(llvm_module);
6756 LLVMContextDispose(ctx);
6757
6758 if (stage == MESA_SHADER_FRAGMENT) {
6759 shader_info->num_input_vgprs = 0;
6760 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6761 shader_info->num_input_vgprs += 2;
6762 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6763 shader_info->num_input_vgprs += 2;
6764 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6765 shader_info->num_input_vgprs += 2;
6766 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6767 shader_info->num_input_vgprs += 3;
6768 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6769 shader_info->num_input_vgprs += 2;
6770 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6771 shader_info->num_input_vgprs += 2;
6772 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6773 shader_info->num_input_vgprs += 2;
6774 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6775 shader_info->num_input_vgprs += 1;
6776 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6777 shader_info->num_input_vgprs += 1;
6778 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6779 shader_info->num_input_vgprs += 1;
6780 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6781 shader_info->num_input_vgprs += 1;
6782 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6783 shader_info->num_input_vgprs += 1;
6784 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6785 shader_info->num_input_vgprs += 1;
6786 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6787 shader_info->num_input_vgprs += 1;
6788 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6789 shader_info->num_input_vgprs += 1;
6790 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6791 shader_info->num_input_vgprs += 1;
6792 }
6793 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6794
6795 /* +3 for scratch wave offset and VCC */
6796 config->num_sgprs = MAX2(config->num_sgprs,
6797 shader_info->num_input_sgprs + 3);
6798 }
6799
6800 static void
6801 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6802 {
6803 switch (nir->stage) {
6804 case MESA_SHADER_COMPUTE:
6805 for (int i = 0; i < 3; ++i)
6806 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6807 break;
6808 case MESA_SHADER_FRAGMENT:
6809 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6810 break;
6811 case MESA_SHADER_GEOMETRY:
6812 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6813 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6814 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6815 shader_info->gs.invocations = nir->info.gs.invocations;
6816 break;
6817 case MESA_SHADER_TESS_EVAL:
6818 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6819 shader_info->tes.spacing = nir->info.tess.spacing;
6820 shader_info->tes.ccw = nir->info.tess.ccw;
6821 shader_info->tes.point_mode = nir->info.tess.point_mode;
6822 shader_info->tes.as_es = options->key.tes.as_es;
6823 break;
6824 case MESA_SHADER_TESS_CTRL:
6825 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6826 break;
6827 case MESA_SHADER_VERTEX:
6828 shader_info->vs.as_es = options->key.vs.as_es;
6829 shader_info->vs.as_ls = options->key.vs.as_ls;
6830 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6831 if (options->key.vs.as_ls)
6832 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6833 break;
6834 default:
6835 break;
6836 }
6837 }
6838
6839 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6840 struct ac_shader_binary *binary,
6841 struct ac_shader_config *config,
6842 struct ac_shader_variant_info *shader_info,
6843 struct nir_shader *const *nir,
6844 int nir_count,
6845 const struct ac_nir_compiler_options *options,
6846 bool dump_shader)
6847 {
6848
6849 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6850 options);
6851
6852 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->stage, dump_shader, options->supports_spill);
6853 for (int i = 0; i < nir_count; ++i)
6854 ac_fill_shader_info(shader_info, nir[i], options);
6855 }
6856
6857 static void
6858 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6859 {
6860 LLVMValueRef args[9];
6861 args[0] = ctx->gsvs_ring;
6862 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6863 args[3] = ctx->i32zero;
6864 args[4] = ctx->i32one; /* OFFEN */
6865 args[5] = ctx->i32zero; /* IDXEN */
6866 args[6] = ctx->i32one; /* GLC */
6867 args[7] = ctx->i32one; /* SLC */
6868 args[8] = ctx->i32zero; /* TFE */
6869
6870 int idx = 0;
6871
6872 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6873 int length = 4;
6874 int slot = idx;
6875 int slot_inc = 1;
6876 if (!(ctx->output_mask & (1ull << i)))
6877 continue;
6878
6879 if (i == VARYING_SLOT_CLIP_DIST0) {
6880 /* unpack clip and cull from a single set of slots */
6881 length = ctx->num_output_clips + ctx->num_output_culls;
6882 if (length > 4)
6883 slot_inc = 2;
6884 }
6885
6886 for (unsigned j = 0; j < length; j++) {
6887 LLVMValueRef value;
6888 args[2] = LLVMConstInt(ctx->i32,
6889 (slot * 4 + j) *
6890 ctx->gs_max_out_vertices * 16 * 4, false);
6891
6892 value = ac_build_intrinsic(&ctx->ac,
6893 "llvm.SI.buffer.load.dword.i32.i32",
6894 ctx->i32, args, 9,
6895 AC_FUNC_ATTR_READONLY |
6896 AC_FUNC_ATTR_LEGACY);
6897
6898 LLVMBuildStore(ctx->builder,
6899 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6900 }
6901 idx += slot_inc;
6902 }
6903 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6904 }
6905
6906 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6907 struct nir_shader *geom_shader,
6908 struct ac_shader_binary *binary,
6909 struct ac_shader_config *config,
6910 struct ac_shader_variant_info *shader_info,
6911 const struct ac_nir_compiler_options *options,
6912 bool dump_shader)
6913 {
6914 struct nir_to_llvm_context ctx = {0};
6915 ctx.context = LLVMContextCreate();
6916 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6917 ctx.options = options;
6918 ctx.shader_info = shader_info;
6919
6920 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6921 ctx.ac.module = ctx.module;
6922
6923 ctx.is_gs_copy_shader = true;
6924 LLVMSetTarget(ctx.module, "amdgcn--");
6925 setup_types(&ctx);
6926
6927 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6928 ctx.ac.builder = ctx.builder;
6929 ctx.stage = MESA_SHADER_VERTEX;
6930
6931 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6932
6933 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6934 ac_setup_rings(&ctx);
6935
6936 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6937 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6938
6939 struct ac_nir_context nir_ctx = {};
6940 nir_ctx.ac = ctx.ac;
6941 nir_ctx.abi = &ctx.abi;
6942
6943 nir_ctx.nctx = &ctx;
6944 ctx.nir = &nir_ctx;
6945
6946 nir_foreach_variable(variable, &geom_shader->outputs) {
6947 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6948 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6949 }
6950
6951 ac_gs_copy_shader_emit(&ctx);
6952
6953 ctx.nir = NULL;
6954
6955 LLVMBuildRetVoid(ctx.builder);
6956
6957 ac_llvm_finalize_module(&ctx);
6958
6959 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6960 MESA_SHADER_VERTEX,
6961 dump_shader, options->supports_spill);
6962 }