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ac/nir: remove emission of nir_op_fpow
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 uint32_t tcs_vertices_per_patch;
131 };
132
133 static inline struct radv_shader_context *
134 radv_shader_context_from_abi(struct ac_shader_abi *abi)
135 {
136 struct radv_shader_context *ctx = NULL;
137 return container_of(abi, ctx, abi);
138 }
139
140 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
141 const nir_deref_var *deref,
142 enum ac_descriptor_type desc_type,
143 const nir_tex_instr *instr,
144 bool image, bool write);
145
146 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
147 {
148 return (index * 4) + chan;
149 }
150
151 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
152 {
153 /* handle patch indices separate */
154 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
155 return 0;
156 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
157 return 1;
158 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
159 return 2 + (slot - VARYING_SLOT_PATCH0);
160
161 if (slot == VARYING_SLOT_POS)
162 return 0;
163 if (slot == VARYING_SLOT_PSIZ)
164 return 1;
165 if (slot == VARYING_SLOT_CLIP_DIST0)
166 return 2;
167 /* 3 is reserved for clip dist as well */
168 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
169 return 4 + (slot - VARYING_SLOT_VAR0);
170 unreachable("illegal slot in get unique index\n");
171 }
172
173 static void set_llvm_calling_convention(LLVMValueRef func,
174 gl_shader_stage stage)
175 {
176 enum radeon_llvm_calling_convention calling_conv;
177
178 switch (stage) {
179 case MESA_SHADER_VERTEX:
180 case MESA_SHADER_TESS_EVAL:
181 calling_conv = RADEON_LLVM_AMDGPU_VS;
182 break;
183 case MESA_SHADER_GEOMETRY:
184 calling_conv = RADEON_LLVM_AMDGPU_GS;
185 break;
186 case MESA_SHADER_TESS_CTRL:
187 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
188 break;
189 case MESA_SHADER_FRAGMENT:
190 calling_conv = RADEON_LLVM_AMDGPU_PS;
191 break;
192 case MESA_SHADER_COMPUTE:
193 calling_conv = RADEON_LLVM_AMDGPU_CS;
194 break;
195 default:
196 unreachable("Unhandle shader type");
197 }
198
199 LLVMSetFunctionCallConv(func, calling_conv);
200 }
201
202 #define MAX_ARGS 23
203 struct arg_info {
204 LLVMTypeRef types[MAX_ARGS];
205 LLVMValueRef *assign[MAX_ARGS];
206 unsigned array_params_mask;
207 uint8_t count;
208 uint8_t sgpr_count;
209 uint8_t num_sgprs_used;
210 uint8_t num_vgprs_used;
211 };
212
213 enum ac_arg_regfile {
214 ARG_SGPR,
215 ARG_VGPR,
216 };
217
218 static void
219 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
220 LLVMValueRef *param_ptr)
221 {
222 assert(info->count < MAX_ARGS);
223
224 info->assign[info->count] = param_ptr;
225 info->types[info->count] = type;
226 info->count++;
227
228 if (regfile == ARG_SGPR) {
229 info->num_sgprs_used += ac_get_type_size(type) / 4;
230 info->sgpr_count++;
231 } else {
232 assert(regfile == ARG_VGPR);
233 info->num_vgprs_used += ac_get_type_size(type) / 4;
234 }
235 }
236
237 static inline void
238 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
239 {
240 info->array_params_mask |= (1 << info->count);
241 add_arg(info, ARG_SGPR, type, param_ptr);
242 }
243
244 static void assign_arguments(LLVMValueRef main_function,
245 struct arg_info *info)
246 {
247 unsigned i;
248 for (i = 0; i < info->count; i++) {
249 if (info->assign[i])
250 *info->assign[i] = LLVMGetParam(main_function, i);
251 }
252 }
253
254 static LLVMValueRef
255 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
256 LLVMBuilderRef builder, LLVMTypeRef *return_types,
257 unsigned num_return_elems,
258 struct arg_info *args,
259 unsigned max_workgroup_size,
260 bool unsafe_math)
261 {
262 LLVMTypeRef main_function_type, ret_type;
263 LLVMBasicBlockRef main_function_body;
264
265 if (num_return_elems)
266 ret_type = LLVMStructTypeInContext(ctx, return_types,
267 num_return_elems, true);
268 else
269 ret_type = LLVMVoidTypeInContext(ctx);
270
271 /* Setup the function */
272 main_function_type =
273 LLVMFunctionType(ret_type, args->types, args->count, 0);
274 LLVMValueRef main_function =
275 LLVMAddFunction(module, "main", main_function_type);
276 main_function_body =
277 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
278 LLVMPositionBuilderAtEnd(builder, main_function_body);
279
280 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
281 for (unsigned i = 0; i < args->sgpr_count; ++i) {
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
283
284 if (args->array_params_mask & (1 << i)) {
285 LLVMValueRef P = LLVMGetParam(main_function, i);
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
287 ac_add_attr_dereferenceable(P, UINT64_MAX);
288 }
289 }
290
291 if (max_workgroup_size) {
292 ac_llvm_add_target_dep_function_attr(main_function,
293 "amdgpu-max-work-group-size",
294 max_workgroup_size);
295 }
296 if (unsafe_math) {
297 /* These were copied from some LLVM test. */
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "less-precise-fpmad",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "no-infs-fp-math",
303 "true");
304 LLVMAddTargetDependentFunctionAttr(main_function,
305 "no-nans-fp-math",
306 "true");
307 LLVMAddTargetDependentFunctionAttr(main_function,
308 "unsafe-fp-math",
309 "true");
310 LLVMAddTargetDependentFunctionAttr(main_function,
311 "no-signed-zeros-fp-math",
312 "true");
313 }
314 return main_function;
315 }
316
317 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
318 LLVMValueRef param, unsigned rshift,
319 unsigned bitwidth)
320 {
321 LLVMValueRef value = param;
322 if (rshift)
323 value = LLVMBuildLShr(ctx->builder, value,
324 LLVMConstInt(ctx->i32, rshift, false), "");
325
326 if (rshift + bitwidth < 32) {
327 unsigned mask = (1 << bitwidth) - 1;
328 value = LLVMBuildAnd(ctx->builder, value,
329 LLVMConstInt(ctx->i32, mask, false), "");
330 }
331 return value;
332 }
333
334 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
335 {
336 switch (ctx->stage) {
337 case MESA_SHADER_TESS_CTRL:
338 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
339 case MESA_SHADER_TESS_EVAL:
340 return ctx->tes_rel_patch_id;
341 break;
342 default:
343 unreachable("Illegal stage");
344 }
345 }
346
347 /* Tessellation shaders pass outputs to the next shader using LDS.
348 *
349 * LS outputs = TCS inputs
350 * TCS outputs = TES inputs
351 *
352 * The LDS layout is:
353 * - TCS inputs for patch 0
354 * - TCS inputs for patch 1
355 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
356 * - ...
357 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
358 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
359 * - TCS outputs for patch 1
360 * - Per-patch TCS outputs for patch 1
361 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
362 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
363 * - ...
364 *
365 * All three shaders VS(LS), TCS, TES share the same LDS space.
366 */
367 static LLVMValueRef
368 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
369 {
370 if (ctx->stage == MESA_SHADER_VERTEX)
371 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
372 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
373 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
374 else {
375 assert(0);
376 return NULL;
377 }
378 }
379
380 static LLVMValueRef
381 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
382 {
383 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
384 }
385
386 static LLVMValueRef
387 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
388 {
389 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
390 }
391
392 static LLVMValueRef
393 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
394 {
395 return LLVMBuildMul(ctx->ac.builder,
396 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
397 LLVMConstInt(ctx->ac.i32, 4, false), "");
398 }
399
400 static LLVMValueRef
401 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
402 {
403 return LLVMBuildMul(ctx->ac.builder,
404 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
405 LLVMConstInt(ctx->ac.i32, 4, false), "");
406 }
407
408 static LLVMValueRef
409 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
410 {
411 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
412 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
413
414 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
415 }
416
417 static LLVMValueRef
418 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
419 {
420 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
421 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
422 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
423
424 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
425 LLVMBuildMul(ctx->ac.builder, patch_stride,
426 rel_patch_id, ""),
427 "");
428 }
429
430 static LLVMValueRef
431 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
432 {
433 LLVMValueRef patch0_patch_data_offset =
434 get_tcs_out_patch0_patch_data_offset(ctx);
435 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
436 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
437
438 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
439 LLVMBuildMul(ctx->ac.builder, patch_stride,
440 rel_patch_id, ""),
441 "");
442 }
443
444 static void
445 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
446 uint32_t indirect_offset)
447 {
448 ud_info->sgpr_idx = *sgpr_idx;
449 ud_info->num_sgprs = num_sgprs;
450 ud_info->indirect = indirect_offset > 0;
451 ud_info->indirect_offset = indirect_offset;
452 *sgpr_idx += num_sgprs;
453 }
454
455 static void
456 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
457 uint8_t num_sgprs)
458 {
459 struct ac_userdata_info *ud_info =
460 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
461 assert(ud_info);
462
463 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
464 }
465
466 static void
467 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
468 uint32_t indirect_offset)
469 {
470 struct ac_userdata_info *ud_info =
471 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
472 assert(ud_info);
473
474 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
475 }
476
477 struct user_sgpr_info {
478 bool need_ring_offsets;
479 uint8_t sgpr_count;
480 bool indirect_all_descriptor_sets;
481 };
482
483 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
484 gl_shader_stage stage)
485 {
486 switch (stage) {
487 case MESA_SHADER_VERTEX:
488 if (ctx->shader_info->info.needs_multiview_view_index ||
489 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
490 return true;
491 break;
492 case MESA_SHADER_TESS_EVAL:
493 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
494 return true;
495 break;
496 case MESA_SHADER_GEOMETRY:
497 case MESA_SHADER_TESS_CTRL:
498 if (ctx->shader_info->info.needs_multiview_view_index)
499 return true;
500 break;
501 default:
502 break;
503 }
504 return false;
505 }
506
507 static uint8_t
508 count_vs_user_sgprs(struct radv_shader_context *ctx)
509 {
510 uint8_t count = 0;
511
512 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
513 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
514
515 return count;
516 }
517
518 static void allocate_user_sgprs(struct radv_shader_context *ctx,
519 gl_shader_stage stage,
520 bool has_previous_stage,
521 gl_shader_stage previous_stage,
522 bool needs_view_index,
523 struct user_sgpr_info *user_sgpr_info)
524 {
525 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
526
527 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
528 if (stage == MESA_SHADER_GEOMETRY ||
529 stage == MESA_SHADER_VERTEX ||
530 stage == MESA_SHADER_TESS_CTRL ||
531 stage == MESA_SHADER_TESS_EVAL ||
532 ctx->is_gs_copy_shader)
533 user_sgpr_info->need_ring_offsets = true;
534
535 if (stage == MESA_SHADER_FRAGMENT &&
536 ctx->shader_info->info.ps.needs_sample_positions)
537 user_sgpr_info->need_ring_offsets = true;
538
539 /* 2 user sgprs will nearly always be allocated for scratch/rings */
540 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
541 user_sgpr_info->sgpr_count += 2;
542 }
543
544 switch (stage) {
545 case MESA_SHADER_COMPUTE:
546 if (ctx->shader_info->info.cs.uses_grid_size)
547 user_sgpr_info->sgpr_count += 3;
548 break;
549 case MESA_SHADER_FRAGMENT:
550 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
551 break;
552 case MESA_SHADER_VERTEX:
553 if (!ctx->is_gs_copy_shader)
554 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
555 if (ctx->options->key.vs.as_ls)
556 user_sgpr_info->sgpr_count++;
557 break;
558 case MESA_SHADER_TESS_CTRL:
559 if (has_previous_stage) {
560 if (previous_stage == MESA_SHADER_VERTEX)
561 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
562 user_sgpr_info->sgpr_count++;
563 }
564 user_sgpr_info->sgpr_count += 4;
565 break;
566 case MESA_SHADER_TESS_EVAL:
567 user_sgpr_info->sgpr_count += 1;
568 break;
569 case MESA_SHADER_GEOMETRY:
570 if (has_previous_stage) {
571 if (previous_stage == MESA_SHADER_VERTEX) {
572 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
573 } else {
574 user_sgpr_info->sgpr_count++;
575 }
576 }
577 user_sgpr_info->sgpr_count += 2;
578 break;
579 default:
580 break;
581 }
582
583 if (needs_view_index)
584 user_sgpr_info->sgpr_count++;
585
586 if (ctx->shader_info->info.loads_push_constants)
587 user_sgpr_info->sgpr_count += 2;
588
589 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
590 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
591
592 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
593 user_sgpr_info->sgpr_count += 2;
594 user_sgpr_info->indirect_all_descriptor_sets = true;
595 } else {
596 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
597 }
598 }
599
600 static void
601 declare_global_input_sgprs(struct radv_shader_context *ctx,
602 gl_shader_stage stage,
603 bool has_previous_stage,
604 gl_shader_stage previous_stage,
605 const struct user_sgpr_info *user_sgpr_info,
606 struct arg_info *args,
607 LLVMValueRef *desc_sets)
608 {
609 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
610 unsigned num_sets = ctx->options->layout ?
611 ctx->options->layout->num_sets : 0;
612 unsigned stage_mask = 1 << stage;
613
614 if (has_previous_stage)
615 stage_mask |= 1 << previous_stage;
616
617 /* 1 for each descriptor set */
618 if (!user_sgpr_info->indirect_all_descriptor_sets) {
619 for (unsigned i = 0; i < num_sets; ++i) {
620 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
621 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
622 add_array_arg(args, type,
623 &ctx->descriptor_sets[i]);
624 }
625 }
626 } else {
627 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
628 }
629
630 if (ctx->shader_info->info.loads_push_constants) {
631 /* 1 for push constants and dynamic descriptors */
632 add_array_arg(args, type, &ctx->abi.push_constants);
633 }
634 }
635
636 static void
637 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
638 gl_shader_stage stage,
639 bool has_previous_stage,
640 gl_shader_stage previous_stage,
641 struct arg_info *args)
642 {
643 if (!ctx->is_gs_copy_shader &&
644 (stage == MESA_SHADER_VERTEX ||
645 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
646 if (ctx->shader_info->info.vs.has_vertex_buffers) {
647 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
648 &ctx->vertex_buffers);
649 }
650 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
651 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
652 if (ctx->shader_info->info.vs.needs_draw_id) {
653 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
654 }
655 }
656 }
657
658 static void
659 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
660 {
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
662 if (!ctx->is_gs_copy_shader) {
663 if (ctx->options->key.vs.as_ls) {
664 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
665 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
666 } else {
667 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
668 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
669 }
670 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
671 }
672 }
673
674 static void
675 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
676 {
677 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
678 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
679 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
680 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
681 }
682
683 static void
684 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
685 bool has_previous_stage, gl_shader_stage previous_stage,
686 const struct user_sgpr_info *user_sgpr_info,
687 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
688 {
689 unsigned num_sets = ctx->options->layout ?
690 ctx->options->layout->num_sets : 0;
691 unsigned stage_mask = 1 << stage;
692
693 if (has_previous_stage)
694 stage_mask |= 1 << previous_stage;
695
696 if (!user_sgpr_info->indirect_all_descriptor_sets) {
697 for (unsigned i = 0; i < num_sets; ++i) {
698 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
699 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
700 set_loc_desc(ctx, i, user_sgpr_idx, 0);
701 } else
702 ctx->descriptor_sets[i] = NULL;
703 }
704 } else {
705 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
706 user_sgpr_idx, 2);
707
708 for (unsigned i = 0; i < num_sets; ++i) {
709 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
710 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
712 ctx->descriptor_sets[i] =
713 ac_build_load_to_sgpr(&ctx->ac,
714 desc_sets,
715 LLVMConstInt(ctx->ac.i32, i, false));
716
717 } else
718 ctx->descriptor_sets[i] = NULL;
719 }
720 ctx->shader_info->need_indirect_descriptor_sets = true;
721 }
722
723 if (ctx->shader_info->info.loads_push_constants) {
724 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
725 }
726 }
727
728 static void
729 set_vs_specific_input_locs(struct radv_shader_context *ctx,
730 gl_shader_stage stage, bool has_previous_stage,
731 gl_shader_stage previous_stage,
732 uint8_t *user_sgpr_idx)
733 {
734 if (!ctx->is_gs_copy_shader &&
735 (stage == MESA_SHADER_VERTEX ||
736 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
737 if (ctx->shader_info->info.vs.has_vertex_buffers) {
738 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
739 user_sgpr_idx, 2);
740 }
741
742 unsigned vs_num = 2;
743 if (ctx->shader_info->info.vs.needs_draw_id)
744 vs_num++;
745
746 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
747 user_sgpr_idx, vs_num);
748 }
749 }
750
751 static void create_function(struct radv_shader_context *ctx,
752 gl_shader_stage stage,
753 bool has_previous_stage,
754 gl_shader_stage previous_stage)
755 {
756 uint8_t user_sgpr_idx;
757 struct user_sgpr_info user_sgpr_info;
758 struct arg_info args = {};
759 LLVMValueRef desc_sets;
760 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
761 allocate_user_sgprs(ctx, stage, has_previous_stage,
762 previous_stage, needs_view_index, &user_sgpr_info);
763
764 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
765 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
766 &ctx->ring_offsets);
767 }
768
769 switch (stage) {
770 case MESA_SHADER_COMPUTE:
771 declare_global_input_sgprs(ctx, stage, has_previous_stage,
772 previous_stage, &user_sgpr_info,
773 &args, &desc_sets);
774
775 if (ctx->shader_info->info.cs.uses_grid_size) {
776 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
777 &ctx->abi.num_work_groups);
778 }
779
780 for (int i = 0; i < 3; i++) {
781 ctx->abi.workgroup_ids[i] = NULL;
782 if (ctx->shader_info->info.cs.uses_block_id[i]) {
783 add_arg(&args, ARG_SGPR, ctx->ac.i32,
784 &ctx->abi.workgroup_ids[i]);
785 }
786 }
787
788 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
789 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
790 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
791 &ctx->abi.local_invocation_ids);
792 break;
793 case MESA_SHADER_VERTEX:
794 declare_global_input_sgprs(ctx, stage, has_previous_stage,
795 previous_stage, &user_sgpr_info,
796 &args, &desc_sets);
797 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &args);
799
800 if (needs_view_index)
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->abi.view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (needs_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->abi.view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->abi.tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (needs_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->abi.view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->abi.tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (needs_view_index)
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->abi.view_index);
892
893 if (ctx->options->key.tes.as_es) {
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->es2gs_offset);
898 } else {
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 }
902 declare_tes_input_vgprs(ctx, &args);
903 break;
904 case MESA_SHADER_GEOMETRY:
905 if (has_previous_stage) {
906 // First 6 system regs
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->gs2vs_offset);
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->merged_wave_info);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
912
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
916
917 declare_global_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &user_sgpr_info, &args,
921 &desc_sets);
922
923 if (previous_stage == MESA_SHADER_TESS_EVAL) {
924 add_arg(&args, ARG_SGPR, ctx->ac.i32,
925 &ctx->tcs_offchip_layout);
926 } else {
927 declare_vs_specific_input_sgprs(ctx, stage,
928 has_previous_stage,
929 previous_stage,
930 &args);
931 }
932
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->gsvs_ring_stride);
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_num_entries);
937 if (needs_view_index)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->abi.view_index);
940
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->gs_vtx_offset[0]);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[2]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->abi.gs_prim_id);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_invocation_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[4]);
951
952 if (previous_stage == MESA_SHADER_VERTEX) {
953 declare_vs_input_vgprs(ctx, &args);
954 } else {
955 declare_tes_input_vgprs(ctx, &args);
956 }
957 } else {
958 declare_global_input_sgprs(ctx, stage,
959 has_previous_stage,
960 previous_stage,
961 &user_sgpr_info, &args,
962 &desc_sets);
963
964 add_arg(&args, ARG_SGPR, ctx->ac.i32,
965 &ctx->gsvs_ring_stride);
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_num_entries);
968 if (needs_view_index)
969 add_arg(&args, ARG_SGPR, ctx->ac.i32,
970 &ctx->abi.view_index);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
973 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[0]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[1]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->abi.gs_prim_id);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[2]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[3]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[4]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[5]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->abi.gs_invocation_id);
990 }
991 break;
992 case MESA_SHADER_FRAGMENT:
993 declare_global_input_sgprs(ctx, stage, has_previous_stage,
994 previous_stage, &user_sgpr_info,
995 &args, &desc_sets);
996
997 if (ctx->shader_info->info.ps.needs_sample_positions)
998 add_arg(&args, ARG_SGPR, ctx->ac.i32,
999 &ctx->sample_pos_offset);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1018 break;
1019 default:
1020 unreachable("Shader stage not implemented");
1021 }
1022
1023 ctx->main_function = create_llvm_function(
1024 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1025 ctx->max_workgroup_size,
1026 ctx->options->unsafe_math);
1027 set_llvm_calling_convention(ctx->main_function, stage);
1028
1029
1030 ctx->shader_info->num_input_vgprs = 0;
1031 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1032
1033 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1034
1035 if (ctx->stage != MESA_SHADER_FRAGMENT)
1036 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1037
1038 assign_arguments(ctx->main_function, &args);
1039
1040 user_sgpr_idx = 0;
1041
1042 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1043 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1044 &user_sgpr_idx, 2);
1045 if (ctx->options->supports_spill) {
1046 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1048 NULL, 0, AC_FUNC_ATTR_READNONE);
1049 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1050 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1051 }
1052 }
1053
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage)
1057 user_sgpr_idx = 0;
1058
1059 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1060 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1061
1062 switch (stage) {
1063 case MESA_SHADER_COMPUTE:
1064 if (ctx->shader_info->info.cs.uses_grid_size) {
1065 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1066 &user_sgpr_idx, 3);
1067 }
1068 break;
1069 case MESA_SHADER_VERTEX:
1070 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1071 previous_stage, &user_sgpr_idx);
1072 if (ctx->abi.view_index)
1073 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1074 if (ctx->options->key.vs.as_ls) {
1075 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1076 &user_sgpr_idx, 1);
1077 }
1078 break;
1079 case MESA_SHADER_TESS_CTRL:
1080 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1081 previous_stage, &user_sgpr_idx);
1082 if (has_previous_stage)
1083 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1084 &user_sgpr_idx, 1);
1085 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1086 if (ctx->abi.view_index)
1087 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1088 break;
1089 case MESA_SHADER_TESS_EVAL:
1090 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1091 if (ctx->abi.view_index)
1092 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1093 break;
1094 case MESA_SHADER_GEOMETRY:
1095 if (has_previous_stage) {
1096 if (previous_stage == MESA_SHADER_VERTEX)
1097 set_vs_specific_input_locs(ctx, stage,
1098 has_previous_stage,
1099 previous_stage,
1100 &user_sgpr_idx);
1101 else
1102 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1103 &user_sgpr_idx, 1);
1104 }
1105 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1106 &user_sgpr_idx, 2);
1107 if (ctx->abi.view_index)
1108 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1109 break;
1110 case MESA_SHADER_FRAGMENT:
1111 if (ctx->shader_info->info.ps.needs_sample_positions) {
1112 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1113 &user_sgpr_idx, 1);
1114 }
1115 break;
1116 default:
1117 unreachable("Shader stage not implemented");
1118 }
1119
1120 if (stage == MESA_SHADER_TESS_CTRL ||
1121 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1122 /* GFX9 has the ESGS ring buffer in LDS. */
1123 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1124 ac_declare_lds_as_pointer(&ctx->ac);
1125 }
1126
1127 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1128 }
1129
1130 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1131 LLVMValueRef value, unsigned count)
1132 {
1133 unsigned num_components = ac_get_llvm_num_components(value);
1134 if (count == num_components)
1135 return value;
1136
1137 LLVMValueRef masks[] = {
1138 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1139 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1140
1141 if (count == 1)
1142 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1143 "");
1144
1145 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1146 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1147 }
1148
1149 static void
1150 build_store_values_extended(struct ac_llvm_context *ac,
1151 LLVMValueRef *values,
1152 unsigned value_count,
1153 unsigned value_stride,
1154 LLVMValueRef vec)
1155 {
1156 LLVMBuilderRef builder = ac->builder;
1157 unsigned i;
1158
1159 for (i = 0; i < value_count; i++) {
1160 LLVMValueRef ptr = values[i * value_stride];
1161 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1162 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1163 LLVMBuildStore(builder, value, ptr);
1164 }
1165 }
1166
1167 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1168 const nir_ssa_def *def)
1169 {
1170 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1171 if (def->num_components > 1) {
1172 type = LLVMVectorType(type, def->num_components);
1173 }
1174 return type;
1175 }
1176
1177 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1178 {
1179 assert(src.is_ssa);
1180 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1181 return (LLVMValueRef)entry->data;
1182 }
1183
1184 static LLVMValueRef
1185 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1186 {
1187 LLVMValueRef ptr = get_src(ctx, src);
1188 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1189 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1190
1191 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1192 LLVMPointerType(ctx->ac.i32, addr_space), "");
1193 }
1194
1195 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1196 const struct nir_block *b)
1197 {
1198 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1199 return (LLVMBasicBlockRef)entry->data;
1200 }
1201
1202 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1203 nir_alu_src src,
1204 unsigned num_components)
1205 {
1206 LLVMValueRef value = get_src(ctx, src.src);
1207 bool need_swizzle = false;
1208
1209 assert(value);
1210 LLVMTypeRef type = LLVMTypeOf(value);
1211 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1212 ? LLVMGetVectorSize(type)
1213 : 1;
1214
1215 for (unsigned i = 0; i < num_components; ++i) {
1216 assert(src.swizzle[i] < src_components);
1217 if (src.swizzle[i] != i)
1218 need_swizzle = true;
1219 }
1220
1221 if (need_swizzle || num_components != src_components) {
1222 LLVMValueRef masks[] = {
1223 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1224 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1225 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1226 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1227
1228 if (src_components > 1 && num_components == 1) {
1229 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1230 masks[0], "");
1231 } else if (src_components == 1 && num_components > 1) {
1232 LLVMValueRef values[] = {value, value, value, value};
1233 value = ac_build_gather_values(&ctx->ac, values, num_components);
1234 } else {
1235 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1236 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1237 swizzle, "");
1238 }
1239 }
1240 assert(!src.negate);
1241 assert(!src.abs);
1242 return value;
1243 }
1244
1245 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1246 LLVMIntPredicate pred, LLVMValueRef src0,
1247 LLVMValueRef src1)
1248 {
1249 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1250 return LLVMBuildSelect(ctx->builder, result,
1251 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1252 ctx->i32_0, "");
1253 }
1254
1255 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1256 LLVMRealPredicate pred, LLVMValueRef src0,
1257 LLVMValueRef src1)
1258 {
1259 LLVMValueRef result;
1260 src0 = ac_to_float(ctx, src0);
1261 src1 = ac_to_float(ctx, src1);
1262 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1263 return LLVMBuildSelect(ctx->builder, result,
1264 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1265 ctx->i32_0, "");
1266 }
1267
1268 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1269 const char *intrin,
1270 LLVMTypeRef result_type,
1271 LLVMValueRef src0)
1272 {
1273 char name[64];
1274 LLVMValueRef params[] = {
1275 ac_to_float(ctx, src0),
1276 };
1277
1278 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1279 ac_get_elem_bits(ctx, result_type));
1280 assert(length < sizeof(name));
1281 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1282 }
1283
1284 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1285 const char *intrin,
1286 LLVMTypeRef result_type,
1287 LLVMValueRef src0, LLVMValueRef src1)
1288 {
1289 char name[64];
1290 LLVMValueRef params[] = {
1291 ac_to_float(ctx, src0),
1292 ac_to_float(ctx, src1),
1293 };
1294
1295 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1296 ac_get_elem_bits(ctx, result_type));
1297 assert(length < sizeof(name));
1298 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1299 }
1300
1301 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1302 const char *intrin,
1303 LLVMTypeRef result_type,
1304 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1305 {
1306 char name[64];
1307 LLVMValueRef params[] = {
1308 ac_to_float(ctx, src0),
1309 ac_to_float(ctx, src1),
1310 ac_to_float(ctx, src2),
1311 };
1312
1313 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1314 ac_get_elem_bits(ctx, result_type));
1315 assert(length < sizeof(name));
1316 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1317 }
1318
1319 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1320 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1321 {
1322 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1323 ctx->i32_0, "");
1324 return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
1325 ac_to_integer(ctx, src2), "");
1326 }
1327
1328 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1329 LLVMIntPredicate pred,
1330 LLVMValueRef src0, LLVMValueRef src1)
1331 {
1332 return LLVMBuildSelect(ctx->builder,
1333 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1334 src0,
1335 src1, "");
1336
1337 }
1338 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1339 LLVMValueRef src0)
1340 {
1341 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1342 LLVMBuildNeg(ctx->builder, src0, ""));
1343 }
1344
1345 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1346 LLVMValueRef src0,
1347 unsigned bitsize)
1348 {
1349 LLVMValueRef cmp, val, zero, one;
1350 LLVMTypeRef type;
1351
1352 if (bitsize == 32) {
1353 type = ctx->f32;
1354 zero = ctx->f32_0;
1355 one = ctx->f32_1;
1356 } else {
1357 type = ctx->f64;
1358 zero = ctx->f64_0;
1359 one = ctx->f64_1;
1360 }
1361
1362 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1363 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1364 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1365 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1366 return val;
1367 }
1368
1369 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1370 LLVMValueRef src0, unsigned bitsize)
1371 {
1372 LLVMValueRef cmp, val, zero, one;
1373 LLVMTypeRef type;
1374
1375 if (bitsize == 32) {
1376 type = ctx->i32;
1377 zero = ctx->i32_0;
1378 one = ctx->i32_1;
1379 } else {
1380 type = ctx->i64;
1381 zero = ctx->i64_0;
1382 one = ctx->i64_1;
1383 }
1384
1385 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1386 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1387 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1388 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1389 return val;
1390 }
1391
1392 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1393 LLVMValueRef src0, unsigned bitsize)
1394 {
1395 LLVMTypeRef type;
1396 char *intr;
1397
1398 if (bitsize == 32) {
1399 intr = "llvm.floor.f32";
1400 type = ctx->f32;
1401 } else {
1402 intr = "llvm.floor.f64";
1403 type = ctx->f64;
1404 }
1405
1406 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1407 LLVMValueRef params[] = {
1408 fsrc0,
1409 };
1410 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1411 AC_FUNC_ATTR_READNONE);
1412 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1413 }
1414
1415 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1416 const char *intrin,
1417 LLVMValueRef src0, LLVMValueRef src1)
1418 {
1419 LLVMTypeRef ret_type;
1420 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1421 LLVMValueRef res;
1422 LLVMValueRef params[] = { src0, src1 };
1423 ret_type = LLVMStructTypeInContext(ctx->context, types,
1424 2, true);
1425
1426 res = ac_build_intrinsic(ctx, intrin, ret_type,
1427 params, 2, AC_FUNC_ATTR_READNONE);
1428
1429 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1430 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1431 return res;
1432 }
1433
1434 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0)
1436 {
1437 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1438 }
1439
1440 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1441 LLVMValueRef src0)
1442 {
1443 src0 = ac_to_float(ctx, src0);
1444 return LLVMBuildSExt(ctx->builder,
1445 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1446 ctx->i32, "");
1447 }
1448
1449 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1450 LLVMValueRef src0,
1451 unsigned bitsize)
1452 {
1453 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1454
1455 if (bitsize == 32)
1456 return result;
1457
1458 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1459 }
1460
1461 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1462 LLVMValueRef src0)
1463 {
1464 return LLVMBuildSExt(ctx->builder,
1465 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1466 ctx->i32, "");
1467 }
1468
1469 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1470 LLVMValueRef src0)
1471 {
1472 LLVMValueRef result;
1473 LLVMValueRef cond = NULL;
1474
1475 src0 = ac_to_float(ctx, src0);
1476 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1477
1478 if (ctx->chip_class >= VI) {
1479 LLVMValueRef args[2];
1480 /* Check if the result is a denormal - and flush to 0 if so. */
1481 args[0] = result;
1482 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1483 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1484 }
1485
1486 /* need to convert back up to f32 */
1487 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1488
1489 if (ctx->chip_class >= VI)
1490 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1491 else {
1492 /* for SI/CIK */
1493 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1494 * so compare the result and flush to 0 if it's smaller.
1495 */
1496 LLVMValueRef temp, cond2;
1497 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1498 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1499 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1500 temp, "");
1501 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1502 temp, ctx->f32_0, "");
1503 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1504 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1505 }
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1510 LLVMValueRef src0, LLVMValueRef src1)
1511 {
1512 LLVMValueRef dst64, result;
1513 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1514 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1515
1516 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1517 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1518 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1519 return result;
1520 }
1521
1522 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1523 LLVMValueRef src0, LLVMValueRef src1)
1524 {
1525 LLVMValueRef dst64, result;
1526 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1527 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1528
1529 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1530 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1531 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1532 return result;
1533 }
1534
1535 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1536 bool is_signed,
1537 const LLVMValueRef srcs[3])
1538 {
1539 LLVMValueRef result;
1540 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1541
1542 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1543 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1544 return result;
1545 }
1546
1547 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1548 LLVMValueRef src0, LLVMValueRef src1,
1549 LLVMValueRef src2, LLVMValueRef src3)
1550 {
1551 LLVMValueRef bfi_args[3], result;
1552
1553 bfi_args[0] = LLVMBuildShl(ctx->builder,
1554 LLVMBuildSub(ctx->builder,
1555 LLVMBuildShl(ctx->builder,
1556 ctx->i32_1,
1557 src3, ""),
1558 ctx->i32_1, ""),
1559 src2, "");
1560 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1561 bfi_args[2] = src0;
1562
1563 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1564
1565 /* Calculate:
1566 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1567 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1568 */
1569 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1570 LLVMBuildAnd(ctx->builder, bfi_args[0],
1571 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1572
1573 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1574 return result;
1575 }
1576
1577 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1578 LLVMValueRef src0)
1579 {
1580 LLVMValueRef comp[2];
1581
1582 src0 = ac_to_float(ctx, src0);
1583 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1584 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1585
1586 return ac_build_cvt_pkrtz_f16(ctx, comp);
1587 }
1588
1589 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1590 LLVMValueRef src0)
1591 {
1592 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1593 LLVMValueRef temps[2], result, val;
1594 int i;
1595
1596 for (i = 0; i < 2; i++) {
1597 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1598 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1599 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1600 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1601 }
1602
1603 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1604 ctx->i32_0, "");
1605 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1606 ctx->i32_1, "");
1607 return result;
1608 }
1609
1610 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1611 nir_op op,
1612 LLVMValueRef src0)
1613 {
1614 unsigned mask;
1615 int idx;
1616 LLVMValueRef result;
1617
1618 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1619 mask = AC_TID_MASK_LEFT;
1620 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1621 mask = AC_TID_MASK_TOP;
1622 else
1623 mask = AC_TID_MASK_TOP_LEFT;
1624
1625 /* for DDX we want to next X pixel, DDY next Y pixel. */
1626 if (op == nir_op_fddx_fine ||
1627 op == nir_op_fddx_coarse ||
1628 op == nir_op_fddx)
1629 idx = 1;
1630 else
1631 idx = 2;
1632
1633 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1634 return result;
1635 }
1636
1637 /*
1638 * this takes an I,J coordinate pair,
1639 * and works out the X and Y derivatives.
1640 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1641 */
1642 static LLVMValueRef emit_ddxy_interp(
1643 struct ac_nir_context *ctx,
1644 LLVMValueRef interp_ij)
1645 {
1646 LLVMValueRef result[4], a;
1647 unsigned i;
1648
1649 for (i = 0; i < 2; i++) {
1650 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1651 LLVMConstInt(ctx->ac.i32, i, false), "");
1652 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1653 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1654 }
1655 return ac_build_gather_values(&ctx->ac, result, 4);
1656 }
1657
1658 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1659 {
1660 LLVMValueRef src[4], result = NULL;
1661 unsigned num_components = instr->dest.dest.ssa.num_components;
1662 unsigned src_components;
1663 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1664
1665 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1666 switch (instr->op) {
1667 case nir_op_vec2:
1668 case nir_op_vec3:
1669 case nir_op_vec4:
1670 src_components = 1;
1671 break;
1672 case nir_op_pack_half_2x16:
1673 src_components = 2;
1674 break;
1675 case nir_op_unpack_half_2x16:
1676 src_components = 1;
1677 break;
1678 default:
1679 src_components = num_components;
1680 break;
1681 }
1682 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1683 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1684
1685 switch (instr->op) {
1686 case nir_op_fmov:
1687 case nir_op_imov:
1688 result = src[0];
1689 break;
1690 case nir_op_fneg:
1691 src[0] = ac_to_float(&ctx->ac, src[0]);
1692 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1693 break;
1694 case nir_op_ineg:
1695 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1696 break;
1697 case nir_op_inot:
1698 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1699 break;
1700 case nir_op_iadd:
1701 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_fadd:
1704 src[0] = ac_to_float(&ctx->ac, src[0]);
1705 src[1] = ac_to_float(&ctx->ac, src[1]);
1706 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1707 break;
1708 case nir_op_fsub:
1709 src[0] = ac_to_float(&ctx->ac, src[0]);
1710 src[1] = ac_to_float(&ctx->ac, src[1]);
1711 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1712 break;
1713 case nir_op_isub:
1714 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1715 break;
1716 case nir_op_imul:
1717 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1718 break;
1719 case nir_op_imod:
1720 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1721 break;
1722 case nir_op_umod:
1723 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1724 break;
1725 case nir_op_fmod:
1726 src[0] = ac_to_float(&ctx->ac, src[0]);
1727 src[1] = ac_to_float(&ctx->ac, src[1]);
1728 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1729 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1730 ac_to_float_type(&ctx->ac, def_type), result);
1731 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1732 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1733 break;
1734 case nir_op_frem:
1735 src[0] = ac_to_float(&ctx->ac, src[0]);
1736 src[1] = ac_to_float(&ctx->ac, src[1]);
1737 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1738 break;
1739 case nir_op_irem:
1740 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1741 break;
1742 case nir_op_idiv:
1743 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1744 break;
1745 case nir_op_udiv:
1746 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1747 break;
1748 case nir_op_fmul:
1749 src[0] = ac_to_float(&ctx->ac, src[0]);
1750 src[1] = ac_to_float(&ctx->ac, src[1]);
1751 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1752 break;
1753 case nir_op_frcp:
1754 src[0] = ac_to_float(&ctx->ac, src[0]);
1755 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1756 src[0]);
1757 break;
1758 case nir_op_iand:
1759 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1760 break;
1761 case nir_op_ior:
1762 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1763 break;
1764 case nir_op_ixor:
1765 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1766 break;
1767 case nir_op_ishl:
1768 result = LLVMBuildShl(ctx->ac.builder, src[0],
1769 LLVMBuildZExt(ctx->ac.builder, src[1],
1770 LLVMTypeOf(src[0]), ""),
1771 "");
1772 break;
1773 case nir_op_ishr:
1774 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1775 LLVMBuildZExt(ctx->ac.builder, src[1],
1776 LLVMTypeOf(src[0]), ""),
1777 "");
1778 break;
1779 case nir_op_ushr:
1780 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1781 LLVMBuildZExt(ctx->ac.builder, src[1],
1782 LLVMTypeOf(src[0]), ""),
1783 "");
1784 break;
1785 case nir_op_ilt:
1786 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1787 break;
1788 case nir_op_ine:
1789 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1790 break;
1791 case nir_op_ieq:
1792 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1793 break;
1794 case nir_op_ige:
1795 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1796 break;
1797 case nir_op_ult:
1798 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1799 break;
1800 case nir_op_uge:
1801 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1802 break;
1803 case nir_op_feq:
1804 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1805 break;
1806 case nir_op_fne:
1807 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1808 break;
1809 case nir_op_flt:
1810 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1811 break;
1812 case nir_op_fge:
1813 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1814 break;
1815 case nir_op_fabs:
1816 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1817 ac_to_float_type(&ctx->ac, def_type), src[0]);
1818 break;
1819 case nir_op_iabs:
1820 result = emit_iabs(&ctx->ac, src[0]);
1821 break;
1822 case nir_op_imax:
1823 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1824 break;
1825 case nir_op_imin:
1826 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1827 break;
1828 case nir_op_umax:
1829 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1830 break;
1831 case nir_op_umin:
1832 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1833 break;
1834 case nir_op_isign:
1835 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1836 break;
1837 case nir_op_fsign:
1838 src[0] = ac_to_float(&ctx->ac, src[0]);
1839 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1840 break;
1841 case nir_op_ffloor:
1842 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1843 ac_to_float_type(&ctx->ac, def_type), src[0]);
1844 break;
1845 case nir_op_ftrunc:
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1847 ac_to_float_type(&ctx->ac, def_type), src[0]);
1848 break;
1849 case nir_op_fceil:
1850 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1851 ac_to_float_type(&ctx->ac, def_type), src[0]);
1852 break;
1853 case nir_op_fround_even:
1854 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1855 ac_to_float_type(&ctx->ac, def_type),src[0]);
1856 break;
1857 case nir_op_ffract:
1858 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1859 break;
1860 case nir_op_fsin:
1861 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1862 ac_to_float_type(&ctx->ac, def_type), src[0]);
1863 break;
1864 case nir_op_fcos:
1865 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1866 ac_to_float_type(&ctx->ac, def_type), src[0]);
1867 break;
1868 case nir_op_fsqrt:
1869 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1870 ac_to_float_type(&ctx->ac, def_type), src[0]);
1871 break;
1872 case nir_op_fexp2:
1873 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1874 ac_to_float_type(&ctx->ac, def_type), src[0]);
1875 break;
1876 case nir_op_flog2:
1877 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1878 ac_to_float_type(&ctx->ac, def_type), src[0]);
1879 break;
1880 case nir_op_frsq:
1881 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1882 ac_to_float_type(&ctx->ac, def_type), src[0]);
1883 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1884 result);
1885 break;
1886 case nir_op_fmax:
1887 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1888 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1889 if (ctx->ac.chip_class < GFX9 &&
1890 instr->dest.dest.ssa.bit_size == 32) {
1891 /* Only pre-GFX9 chips do not flush denorms. */
1892 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1893 ac_to_float_type(&ctx->ac, def_type),
1894 result);
1895 }
1896 break;
1897 case nir_op_fmin:
1898 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1899 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1900 if (ctx->ac.chip_class < GFX9 &&
1901 instr->dest.dest.ssa.bit_size == 32) {
1902 /* Only pre-GFX9 chips do not flush denorms. */
1903 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1904 ac_to_float_type(&ctx->ac, def_type),
1905 result);
1906 }
1907 break;
1908 case nir_op_ffma:
1909 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1910 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1911 break;
1912 case nir_op_ibitfield_extract:
1913 result = emit_bitfield_extract(&ctx->ac, true, src);
1914 break;
1915 case nir_op_ubitfield_extract:
1916 result = emit_bitfield_extract(&ctx->ac, false, src);
1917 break;
1918 case nir_op_bitfield_insert:
1919 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1920 break;
1921 case nir_op_bitfield_reverse:
1922 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1923 break;
1924 case nir_op_bit_count:
1925 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1926 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1927 else {
1928 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1929 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1930 }
1931 break;
1932 case nir_op_vec2:
1933 case nir_op_vec3:
1934 case nir_op_vec4:
1935 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1936 src[i] = ac_to_integer(&ctx->ac, src[i]);
1937 result = ac_build_gather_values(&ctx->ac, src, num_components);
1938 break;
1939 case nir_op_f2i32:
1940 case nir_op_f2i64:
1941 src[0] = ac_to_float(&ctx->ac, src[0]);
1942 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1943 break;
1944 case nir_op_f2u32:
1945 case nir_op_f2u64:
1946 src[0] = ac_to_float(&ctx->ac, src[0]);
1947 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1948 break;
1949 case nir_op_i2f32:
1950 case nir_op_i2f64:
1951 src[0] = ac_to_integer(&ctx->ac, src[0]);
1952 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1953 break;
1954 case nir_op_u2f32:
1955 case nir_op_u2f64:
1956 src[0] = ac_to_integer(&ctx->ac, src[0]);
1957 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1958 break;
1959 case nir_op_f2f64:
1960 src[0] = ac_to_float(&ctx->ac, src[0]);
1961 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1962 break;
1963 case nir_op_f2f32:
1964 src[0] = ac_to_float(&ctx->ac, src[0]);
1965 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1966 break;
1967 case nir_op_u2u32:
1968 case nir_op_u2u64:
1969 src[0] = ac_to_integer(&ctx->ac, src[0]);
1970 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1971 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1972 else
1973 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1974 break;
1975 case nir_op_i2i32:
1976 case nir_op_i2i64:
1977 src[0] = ac_to_integer(&ctx->ac, src[0]);
1978 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1979 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1980 else
1981 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1982 break;
1983 case nir_op_bcsel:
1984 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1985 break;
1986 case nir_op_find_lsb:
1987 src[0] = ac_to_integer(&ctx->ac, src[0]);
1988 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1989 break;
1990 case nir_op_ufind_msb:
1991 src[0] = ac_to_integer(&ctx->ac, src[0]);
1992 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1993 break;
1994 case nir_op_ifind_msb:
1995 src[0] = ac_to_integer(&ctx->ac, src[0]);
1996 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1997 break;
1998 case nir_op_uadd_carry:
1999 src[0] = ac_to_integer(&ctx->ac, src[0]);
2000 src[1] = ac_to_integer(&ctx->ac, src[1]);
2001 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
2002 break;
2003 case nir_op_usub_borrow:
2004 src[0] = ac_to_integer(&ctx->ac, src[0]);
2005 src[1] = ac_to_integer(&ctx->ac, src[1]);
2006 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2007 break;
2008 case nir_op_b2f:
2009 result = emit_b2f(&ctx->ac, src[0]);
2010 break;
2011 case nir_op_f2b:
2012 result = emit_f2b(&ctx->ac, src[0]);
2013 break;
2014 case nir_op_b2i:
2015 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2016 break;
2017 case nir_op_i2b:
2018 src[0] = ac_to_integer(&ctx->ac, src[0]);
2019 result = emit_i2b(&ctx->ac, src[0]);
2020 break;
2021 case nir_op_fquantize2f16:
2022 result = emit_f2f16(&ctx->ac, src[0]);
2023 break;
2024 case nir_op_umul_high:
2025 src[0] = ac_to_integer(&ctx->ac, src[0]);
2026 src[1] = ac_to_integer(&ctx->ac, src[1]);
2027 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2028 break;
2029 case nir_op_imul_high:
2030 src[0] = ac_to_integer(&ctx->ac, src[0]);
2031 src[1] = ac_to_integer(&ctx->ac, src[1]);
2032 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2033 break;
2034 case nir_op_pack_half_2x16:
2035 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2036 break;
2037 case nir_op_unpack_half_2x16:
2038 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2039 break;
2040 case nir_op_fddx:
2041 case nir_op_fddy:
2042 case nir_op_fddx_fine:
2043 case nir_op_fddy_fine:
2044 case nir_op_fddx_coarse:
2045 case nir_op_fddy_coarse:
2046 result = emit_ddxy(ctx, instr->op, src[0]);
2047 break;
2048
2049 case nir_op_unpack_64_2x32_split_x: {
2050 assert(ac_get_llvm_num_components(src[0]) == 1);
2051 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2052 ctx->ac.v2i32,
2053 "");
2054 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2055 ctx->ac.i32_0, "");
2056 break;
2057 }
2058
2059 case nir_op_unpack_64_2x32_split_y: {
2060 assert(ac_get_llvm_num_components(src[0]) == 1);
2061 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2062 ctx->ac.v2i32,
2063 "");
2064 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2065 ctx->ac.i32_1, "");
2066 break;
2067 }
2068
2069 case nir_op_pack_64_2x32_split: {
2070 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2071 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2072 src[0], ctx->ac.i32_0, "");
2073 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2074 src[1], ctx->ac.i32_1, "");
2075 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2076 break;
2077 }
2078
2079 default:
2080 fprintf(stderr, "Unknown NIR alu instr: ");
2081 nir_print_instr(&instr->instr, stderr);
2082 fprintf(stderr, "\n");
2083 abort();
2084 }
2085
2086 if (result) {
2087 assert(instr->dest.dest.is_ssa);
2088 result = ac_to_integer(&ctx->ac, result);
2089 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2090 result);
2091 }
2092 }
2093
2094 static void visit_load_const(struct ac_nir_context *ctx,
2095 const nir_load_const_instr *instr)
2096 {
2097 LLVMValueRef values[4], value = NULL;
2098 LLVMTypeRef element_type =
2099 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2100
2101 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2102 switch (instr->def.bit_size) {
2103 case 32:
2104 values[i] = LLVMConstInt(element_type,
2105 instr->value.u32[i], false);
2106 break;
2107 case 64:
2108 values[i] = LLVMConstInt(element_type,
2109 instr->value.u64[i], false);
2110 break;
2111 default:
2112 fprintf(stderr,
2113 "unsupported nir load_const bit_size: %d\n",
2114 instr->def.bit_size);
2115 abort();
2116 }
2117 }
2118 if (instr->def.num_components > 1) {
2119 value = LLVMConstVector(values, instr->def.num_components);
2120 } else
2121 value = values[0];
2122
2123 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2124 }
2125
2126 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2127 LLVMTypeRef type)
2128 {
2129 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2130 return LLVMBuildBitCast(ctx->builder, ptr,
2131 LLVMPointerType(type, addr_space), "");
2132 }
2133
2134 static LLVMValueRef
2135 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2136 {
2137 LLVMValueRef size =
2138 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2139 LLVMConstInt(ctx->ac.i32, 2, false), "");
2140
2141 /* VI only */
2142 if (ctx->ac.chip_class == VI && in_elements) {
2143 /* On VI, the descriptor contains the size in bytes,
2144 * but TXQ must return the size in elements.
2145 * The stride is always non-zero for resources using TXQ.
2146 */
2147 LLVMValueRef stride =
2148 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2149 ctx->ac.i32_1, "");
2150 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2151 LLVMConstInt(ctx->ac.i32, 16, false), "");
2152 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2153 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2154
2155 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2156 }
2157 return size;
2158 }
2159
2160 /**
2161 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2162 * intrinsic names).
2163 */
2164 static void build_int_type_name(
2165 LLVMTypeRef type,
2166 char *buf, unsigned bufsize)
2167 {
2168 assert(bufsize >= 6);
2169
2170 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2171 snprintf(buf, bufsize, "v%ui32",
2172 LLVMGetVectorSize(type));
2173 else
2174 strcpy(buf, "i32");
2175 }
2176
2177 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2178 struct ac_image_args *args,
2179 const nir_tex_instr *instr)
2180 {
2181 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2182 LLVMValueRef coord = args->addr;
2183 LLVMValueRef half_texel[2];
2184 LLVMValueRef compare_cube_wa = NULL;
2185 LLVMValueRef result;
2186 int c;
2187 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2188
2189 //TODO Rect
2190 {
2191 struct ac_image_args txq_args = { 0 };
2192
2193 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2194 txq_args.opcode = ac_image_get_resinfo;
2195 txq_args.dmask = 0xf;
2196 txq_args.addr = ctx->i32_0;
2197 txq_args.resource = args->resource;
2198 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2199
2200 for (c = 0; c < 2; c++) {
2201 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2202 LLVMConstInt(ctx->i32, c, false), "");
2203 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2204 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2205 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2206 LLVMConstReal(ctx->f32, -0.5), "");
2207 }
2208 }
2209
2210 LLVMValueRef orig_coords = args->addr;
2211
2212 for (c = 0; c < 2; c++) {
2213 LLVMValueRef tmp;
2214 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2215 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2216 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2217 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2218 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2219 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2220 }
2221
2222
2223 /*
2224 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2225 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2226 * workaround by sampling using a scaled type and converting.
2227 * This is taken from amdgpu-pro shaders.
2228 */
2229 /* NOTE this produces some ugly code compared to amdgpu-pro,
2230 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2231 * and then reads them back. -pro generates two selects,
2232 * one s_cmp for the descriptor rewriting
2233 * one v_cmp for the coordinate and result changes.
2234 */
2235 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2236 LLVMValueRef tmp, tmp2;
2237
2238 /* workaround 8/8/8/8 uint/sint cube gather bug */
2239 /* first detect it then change to a scaled read and f2i */
2240 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2241 tmp2 = tmp;
2242
2243 /* extract the DATA_FORMAT */
2244 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2245 LLVMConstInt(ctx->i32, 6, false), false);
2246
2247 /* is the DATA_FORMAT == 8_8_8_8 */
2248 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2249
2250 if (stype == GLSL_TYPE_UINT)
2251 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2252 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2253 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2254 else
2255 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2256 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2257 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2258
2259 /* replace the NUM FORMAT in the descriptor */
2260 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2261 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2262
2263 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2264
2265 /* don't modify the coordinates for this case */
2266 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2267 }
2268 args->addr = coord;
2269 result = ac_build_image_opcode(ctx, args);
2270
2271 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2272 LLVMValueRef tmp, tmp2;
2273
2274 /* if the cube workaround is in place, f2i the result. */
2275 for (c = 0; c < 4; c++) {
2276 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2277 if (stype == GLSL_TYPE_UINT)
2278 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2279 else
2280 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2281 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2282 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2283 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2284 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2285 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2286 }
2287 }
2288 return result;
2289 }
2290
2291 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2292 const nir_tex_instr *instr,
2293 bool lod_is_zero,
2294 struct ac_image_args *args)
2295 {
2296 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2297 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2298
2299 return ac_build_buffer_load_format(&ctx->ac,
2300 args->resource,
2301 args->addr,
2302 ctx->ac.i32_0,
2303 util_last_bit(mask),
2304 false, true);
2305 }
2306
2307 args->opcode = ac_image_sample;
2308 args->compare = instr->is_shadow;
2309
2310 switch (instr->op) {
2311 case nir_texop_txf:
2312 case nir_texop_txf_ms:
2313 case nir_texop_samples_identical:
2314 args->opcode = lod_is_zero ||
2315 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2316 ac_image_load : ac_image_load_mip;
2317 args->compare = false;
2318 args->offset = false;
2319 break;
2320 case nir_texop_txb:
2321 args->bias = true;
2322 break;
2323 case nir_texop_txl:
2324 if (lod_is_zero)
2325 args->level_zero = true;
2326 else
2327 args->lod = true;
2328 break;
2329 case nir_texop_txs:
2330 case nir_texop_query_levels:
2331 args->opcode = ac_image_get_resinfo;
2332 break;
2333 case nir_texop_tex:
2334 if (ctx->stage != MESA_SHADER_FRAGMENT)
2335 args->level_zero = true;
2336 break;
2337 case nir_texop_txd:
2338 args->deriv = true;
2339 break;
2340 case nir_texop_tg4:
2341 args->opcode = ac_image_gather4;
2342 args->level_zero = true;
2343 break;
2344 case nir_texop_lod:
2345 args->opcode = ac_image_get_lod;
2346 args->compare = false;
2347 args->offset = false;
2348 break;
2349 default:
2350 break;
2351 }
2352
2353 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2354 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2355 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2356 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2357 }
2358 }
2359 return ac_build_image_opcode(&ctx->ac, args);
2360 }
2361
2362 static LLVMValueRef
2363 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2364 unsigned desc_set, unsigned binding)
2365 {
2366 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2367 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2368 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2369 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2370 unsigned base_offset = layout->binding[binding].offset;
2371 LLVMValueRef offset, stride;
2372
2373 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2374 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2375 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2376 layout->binding[binding].dynamic_offset_offset;
2377 desc_ptr = ctx->abi.push_constants;
2378 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2379 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2380 } else
2381 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2382
2383 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2384 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2385 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2386
2387 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2388 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2389 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2390
2391 return desc_ptr;
2392 }
2393
2394 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2395 nir_intrinsic_instr *instr)
2396 {
2397 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2398 LLVMValueRef index = get_src(ctx, instr->src[1]);
2399
2400 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2401 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2402 return result;
2403 }
2404
2405 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2406 nir_intrinsic_instr *instr)
2407 {
2408 LLVMValueRef ptr, addr;
2409
2410 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2411 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2412 get_src(ctx, instr->src[0]), "");
2413
2414 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2415 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2416
2417 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2418 }
2419
2420 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2421 const nir_intrinsic_instr *instr)
2422 {
2423 LLVMValueRef index = get_src(ctx, instr->src[0]);
2424
2425 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2426 }
2427
2428 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2429 {
2430 uint32_t new_mask = 0;
2431 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2432 if (mask & (1u << i))
2433 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2434 return new_mask;
2435 }
2436
2437 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2438 unsigned start, unsigned count)
2439 {
2440 LLVMTypeRef type = LLVMTypeOf(src);
2441
2442 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2443 assert(start == 0);
2444 assert(count == 1);
2445 return src;
2446 }
2447
2448 unsigned src_elements = LLVMGetVectorSize(type);
2449 assert(start < src_elements);
2450 assert(start + count <= src_elements);
2451
2452 if (start == 0 && count == src_elements)
2453 return src;
2454
2455 if (count == 1)
2456 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2457
2458 assert(count <= 8);
2459 LLVMValueRef indices[8];
2460 for (unsigned i = 0; i < count; ++i)
2461 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2462
2463 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2464 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2465 }
2466
2467 static void visit_store_ssbo(struct ac_nir_context *ctx,
2468 nir_intrinsic_instr *instr)
2469 {
2470 const char *store_name;
2471 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2472 LLVMTypeRef data_type = ctx->ac.f32;
2473 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2474 int components_32bit = elem_size_mult * instr->num_components;
2475 unsigned writemask = nir_intrinsic_write_mask(instr);
2476 LLVMValueRef base_data, base_offset;
2477 LLVMValueRef params[6];
2478
2479 params[1] = ctx->abi->load_ssbo(ctx->abi,
2480 get_src(ctx, instr->src[1]), true);
2481 params[2] = ctx->ac.i32_0; /* vindex */
2482 params[4] = ctx->ac.i1false; /* glc */
2483 params[5] = ctx->ac.i1false; /* slc */
2484
2485 if (components_32bit > 1)
2486 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2487
2488 writemask = widen_mask(writemask, elem_size_mult);
2489
2490 base_data = ac_to_float(&ctx->ac, src_data);
2491 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2492 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2493 data_type, "");
2494 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2495 while (writemask) {
2496 int start, count;
2497 LLVMValueRef data;
2498 LLVMValueRef offset;
2499
2500 u_bit_scan_consecutive_range(&writemask, &start, &count);
2501
2502 /* Due to an LLVM limitation, split 3-element writes
2503 * into a 2-element and a 1-element write. */
2504 if (count == 3) {
2505 writemask |= 1 << (start + 2);
2506 count = 2;
2507 }
2508
2509 if (count > 4) {
2510 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2511 count = 4;
2512 }
2513
2514 if (count == 4) {
2515 store_name = "llvm.amdgcn.buffer.store.v4f32";
2516 } else if (count == 2) {
2517 store_name = "llvm.amdgcn.buffer.store.v2f32";
2518
2519 } else {
2520 assert(count == 1);
2521 store_name = "llvm.amdgcn.buffer.store.f32";
2522 }
2523 data = extract_vector_range(&ctx->ac, base_data, start, count);
2524
2525 offset = base_offset;
2526 if (start != 0) {
2527 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2528 }
2529 params[0] = data;
2530 params[3] = offset;
2531 ac_build_intrinsic(&ctx->ac, store_name,
2532 ctx->ac.voidt, params, 6, 0);
2533 }
2534 }
2535
2536 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2537 const nir_intrinsic_instr *instr)
2538 {
2539 const char *name;
2540 LLVMValueRef params[6];
2541 int arg_count = 0;
2542
2543 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2544 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2545 }
2546 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2547 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2548 get_src(ctx, instr->src[0]),
2549 true);
2550 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2551 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2552 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2553
2554 switch (instr->intrinsic) {
2555 case nir_intrinsic_ssbo_atomic_add:
2556 name = "llvm.amdgcn.buffer.atomic.add";
2557 break;
2558 case nir_intrinsic_ssbo_atomic_imin:
2559 name = "llvm.amdgcn.buffer.atomic.smin";
2560 break;
2561 case nir_intrinsic_ssbo_atomic_umin:
2562 name = "llvm.amdgcn.buffer.atomic.umin";
2563 break;
2564 case nir_intrinsic_ssbo_atomic_imax:
2565 name = "llvm.amdgcn.buffer.atomic.smax";
2566 break;
2567 case nir_intrinsic_ssbo_atomic_umax:
2568 name = "llvm.amdgcn.buffer.atomic.umax";
2569 break;
2570 case nir_intrinsic_ssbo_atomic_and:
2571 name = "llvm.amdgcn.buffer.atomic.and";
2572 break;
2573 case nir_intrinsic_ssbo_atomic_or:
2574 name = "llvm.amdgcn.buffer.atomic.or";
2575 break;
2576 case nir_intrinsic_ssbo_atomic_xor:
2577 name = "llvm.amdgcn.buffer.atomic.xor";
2578 break;
2579 case nir_intrinsic_ssbo_atomic_exchange:
2580 name = "llvm.amdgcn.buffer.atomic.swap";
2581 break;
2582 case nir_intrinsic_ssbo_atomic_comp_swap:
2583 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2584 break;
2585 default:
2586 abort();
2587 }
2588
2589 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2590 }
2591
2592 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2593 const nir_intrinsic_instr *instr)
2594 {
2595 LLVMValueRef results[2];
2596 int load_components;
2597 int num_components = instr->num_components;
2598 if (instr->dest.ssa.bit_size == 64)
2599 num_components *= 2;
2600
2601 for (int i = 0; i < num_components; i += load_components) {
2602 load_components = MIN2(num_components - i, 4);
2603 const char *load_name;
2604 LLVMTypeRef data_type = ctx->ac.f32;
2605 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2606 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2607
2608 if (load_components == 3)
2609 data_type = LLVMVectorType(ctx->ac.f32, 4);
2610 else if (load_components > 1)
2611 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2612
2613 if (load_components >= 3)
2614 load_name = "llvm.amdgcn.buffer.load.v4f32";
2615 else if (load_components == 2)
2616 load_name = "llvm.amdgcn.buffer.load.v2f32";
2617 else if (load_components == 1)
2618 load_name = "llvm.amdgcn.buffer.load.f32";
2619 else
2620 unreachable("unhandled number of components");
2621
2622 LLVMValueRef params[] = {
2623 ctx->abi->load_ssbo(ctx->abi,
2624 get_src(ctx, instr->src[0]),
2625 false),
2626 ctx->ac.i32_0,
2627 offset,
2628 ctx->ac.i1false,
2629 ctx->ac.i1false,
2630 };
2631
2632 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2633 }
2634
2635 assume(results[0]);
2636 LLVMValueRef ret = results[0];
2637 if (num_components > 4 || num_components == 3) {
2638 LLVMValueRef masks[] = {
2639 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2640 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2641 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2642 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2643 };
2644
2645 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2646 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2647 results[num_components > 4 ? 1 : 0], swizzle, "");
2648 }
2649
2650 return LLVMBuildBitCast(ctx->ac.builder, ret,
2651 get_def_type(ctx, &instr->dest.ssa), "");
2652 }
2653
2654 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2655 const nir_intrinsic_instr *instr)
2656 {
2657 LLVMValueRef ret;
2658 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2659 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2660 int num_components = instr->num_components;
2661
2662 if (ctx->abi->load_ubo)
2663 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2664
2665 if (instr->dest.ssa.bit_size == 64)
2666 num_components *= 2;
2667
2668 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2669 NULL, 0, false, false, true, true);
2670 ret = trim_vector(&ctx->ac, ret, num_components);
2671 return LLVMBuildBitCast(ctx->ac.builder, ret,
2672 get_def_type(ctx, &instr->dest.ssa), "");
2673 }
2674
2675 static void
2676 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2677 bool vs_in, unsigned *vertex_index_out,
2678 LLVMValueRef *vertex_index_ref,
2679 unsigned *const_out, LLVMValueRef *indir_out)
2680 {
2681 unsigned const_offset = 0;
2682 nir_deref *tail = &deref->deref;
2683 LLVMValueRef offset = NULL;
2684
2685 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2686 tail = tail->child;
2687 nir_deref_array *deref_array = nir_deref_as_array(tail);
2688 if (vertex_index_out)
2689 *vertex_index_out = deref_array->base_offset;
2690
2691 if (vertex_index_ref) {
2692 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2693 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2694 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2695 }
2696 *vertex_index_ref = vtx;
2697 }
2698 }
2699
2700 if (deref->var->data.compact) {
2701 assert(tail->child->deref_type == nir_deref_type_array);
2702 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2703 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2704 /* We always lower indirect dereferences for "compact" array vars. */
2705 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2706
2707 const_offset = deref_array->base_offset;
2708 goto out;
2709 }
2710
2711 while (tail->child != NULL) {
2712 const struct glsl_type *parent_type = tail->type;
2713 tail = tail->child;
2714
2715 if (tail->deref_type == nir_deref_type_array) {
2716 nir_deref_array *deref_array = nir_deref_as_array(tail);
2717 LLVMValueRef index, stride, local_offset;
2718 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2719
2720 const_offset += size * deref_array->base_offset;
2721 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2722 continue;
2723
2724 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2725 index = get_src(ctx, deref_array->indirect);
2726 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2727 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2728
2729 if (offset)
2730 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2731 else
2732 offset = local_offset;
2733 } else if (tail->deref_type == nir_deref_type_struct) {
2734 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2735
2736 for (unsigned i = 0; i < deref_struct->index; i++) {
2737 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2738 const_offset += glsl_count_attribute_slots(ft, vs_in);
2739 }
2740 } else
2741 unreachable("unsupported deref type");
2742
2743 }
2744 out:
2745 if (const_offset && offset)
2746 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2747 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2748 "");
2749
2750 *const_out = const_offset;
2751 *indir_out = offset;
2752 }
2753
2754
2755 /* The offchip buffer layout for TCS->TES is
2756 *
2757 * - attribute 0 of patch 0 vertex 0
2758 * - attribute 0 of patch 0 vertex 1
2759 * - attribute 0 of patch 0 vertex 2
2760 * ...
2761 * - attribute 0 of patch 1 vertex 0
2762 * - attribute 0 of patch 1 vertex 1
2763 * ...
2764 * - attribute 1 of patch 0 vertex 0
2765 * - attribute 1 of patch 0 vertex 1
2766 * ...
2767 * - per patch attribute 0 of patch 0
2768 * - per patch attribute 0 of patch 1
2769 * ...
2770 *
2771 * Note that every attribute has 4 components.
2772 */
2773 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2774 LLVMValueRef vertex_index,
2775 LLVMValueRef param_index)
2776 {
2777 LLVMValueRef base_addr, vertices_per_patch, num_patches;
2778 LLVMValueRef param_stride, constant16;
2779 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2780
2781 vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
2782 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2783
2784 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2785 if (vertex_index) {
2786 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2787 vertices_per_patch, "");
2788
2789 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2790 vertex_index, "");
2791
2792 param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2793 num_patches, "");
2794 } else {
2795 base_addr = rel_patch_id;
2796 param_stride = num_patches;
2797 }
2798
2799 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2800 LLVMBuildMul(ctx->ac.builder, param_index,
2801 param_stride, ""), "");
2802
2803 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2804
2805 if (!vertex_index) {
2806 LLVMValueRef patch_data_offset =
2807 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2808
2809 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2810 patch_data_offset, "");
2811 }
2812 return base_addr;
2813 }
2814
2815 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2816 unsigned param,
2817 unsigned const_index,
2818 bool is_compact,
2819 LLVMValueRef vertex_index,
2820 LLVMValueRef indir_index)
2821 {
2822 LLVMValueRef param_index;
2823
2824 if (indir_index)
2825 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2826 indir_index, "");
2827 else {
2828 if (const_index && !is_compact)
2829 param += const_index;
2830 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2831 }
2832 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2833 }
2834
2835 static void
2836 mark_tess_output(struct radv_shader_context *ctx,
2837 bool is_patch, uint32_t param)
2838
2839 {
2840 if (is_patch) {
2841 ctx->tess_patch_outputs_written |= (1ull << param);
2842 } else
2843 ctx->tess_outputs_written |= (1ull << param);
2844 }
2845
2846 static LLVMValueRef
2847 get_dw_address(struct radv_shader_context *ctx,
2848 LLVMValueRef dw_addr,
2849 unsigned param,
2850 unsigned const_index,
2851 bool compact_const_index,
2852 LLVMValueRef vertex_index,
2853 LLVMValueRef stride,
2854 LLVMValueRef indir_index)
2855
2856 {
2857
2858 if (vertex_index) {
2859 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2860 LLVMBuildMul(ctx->ac.builder,
2861 vertex_index,
2862 stride, ""), "");
2863 }
2864
2865 if (indir_index)
2866 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2867 LLVMBuildMul(ctx->ac.builder, indir_index,
2868 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2869 else if (const_index && !compact_const_index)
2870 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2871 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2872
2873 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2874 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2875
2876 if (const_index && compact_const_index)
2877 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2878 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2879 return dw_addr;
2880 }
2881
2882 static LLVMValueRef
2883 load_tcs_varyings(struct ac_shader_abi *abi,
2884 LLVMTypeRef type,
2885 LLVMValueRef vertex_index,
2886 LLVMValueRef indir_index,
2887 unsigned const_index,
2888 unsigned location,
2889 unsigned driver_location,
2890 unsigned component,
2891 unsigned num_components,
2892 bool is_patch,
2893 bool is_compact,
2894 bool load_input)
2895 {
2896 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2897 LLVMValueRef dw_addr, stride;
2898 LLVMValueRef value[4], result;
2899 unsigned param = shader_io_get_unique_index(location);
2900
2901 if (load_input) {
2902 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2903 dw_addr = get_tcs_in_current_patch_offset(ctx);
2904 } else {
2905 if (!is_patch) {
2906 stride = get_tcs_out_vertex_stride(ctx);
2907 dw_addr = get_tcs_out_current_patch_offset(ctx);
2908 } else {
2909 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2910 stride = NULL;
2911 }
2912 }
2913
2914 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2915 indir_index);
2916
2917 for (unsigned i = 0; i < num_components + component; i++) {
2918 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2919 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2920 ctx->ac.i32_1, "");
2921 }
2922 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2923 return result;
2924 }
2925
2926 static void
2927 store_tcs_output(struct ac_shader_abi *abi,
2928 LLVMValueRef vertex_index,
2929 LLVMValueRef param_index,
2930 unsigned const_index,
2931 unsigned location,
2932 unsigned driver_location,
2933 LLVMValueRef src,
2934 unsigned component,
2935 bool is_patch,
2936 bool is_compact,
2937 unsigned writemask)
2938 {
2939 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2940 LLVMValueRef dw_addr;
2941 LLVMValueRef stride = NULL;
2942 LLVMValueRef buf_addr = NULL;
2943 unsigned param;
2944 bool store_lds = true;
2945
2946 if (is_patch) {
2947 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2948 store_lds = false;
2949 } else {
2950 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2951 store_lds = false;
2952 }
2953
2954 param = shader_io_get_unique_index(location);
2955 if (location == VARYING_SLOT_CLIP_DIST0 &&
2956 is_compact && const_index > 3) {
2957 const_index -= 3;
2958 param++;
2959 }
2960
2961 if (!is_patch) {
2962 stride = get_tcs_out_vertex_stride(ctx);
2963 dw_addr = get_tcs_out_current_patch_offset(ctx);
2964 } else {
2965 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2966 }
2967
2968 mark_tess_output(ctx, is_patch, param);
2969
2970 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2971 param_index);
2972 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2973 vertex_index, param_index);
2974
2975 bool is_tess_factor = false;
2976 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2977 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2978 is_tess_factor = true;
2979
2980 unsigned base = is_compact ? const_index : 0;
2981 for (unsigned chan = 0; chan < 8; chan++) {
2982 if (!(writemask & (1 << chan)))
2983 continue;
2984 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2985
2986 if (store_lds || is_tess_factor) {
2987 LLVMValueRef dw_addr_chan =
2988 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2989 LLVMConstInt(ctx->ac.i32, chan, false), "");
2990 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2991 }
2992
2993 if (!is_tess_factor && writemask != 0xF)
2994 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2995 buf_addr, ctx->oc_lds,
2996 4 * (base + chan), 1, 0, true, false);
2997 }
2998
2999 if (writemask == 0xF) {
3000 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
3001 buf_addr, ctx->oc_lds,
3002 (base * 4), 1, 0, true, false);
3003 }
3004 }
3005
3006 static LLVMValueRef
3007 load_tes_input(struct ac_shader_abi *abi,
3008 LLVMTypeRef type,
3009 LLVMValueRef vertex_index,
3010 LLVMValueRef param_index,
3011 unsigned const_index,
3012 unsigned location,
3013 unsigned driver_location,
3014 unsigned component,
3015 unsigned num_components,
3016 bool is_patch,
3017 bool is_compact,
3018 bool load_input)
3019 {
3020 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3021 LLVMValueRef buf_addr;
3022 LLVMValueRef result;
3023 unsigned param = shader_io_get_unique_index(location);
3024
3025 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3026 const_index -= 3;
3027 param++;
3028 }
3029
3030 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3031 is_compact, vertex_index, param_index);
3032
3033 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3034 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3035
3036 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3037 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3038 result = trim_vector(&ctx->ac, result, num_components);
3039 return result;
3040 }
3041
3042 static LLVMValueRef
3043 load_gs_input(struct ac_shader_abi *abi,
3044 unsigned location,
3045 unsigned driver_location,
3046 unsigned component,
3047 unsigned num_components,
3048 unsigned vertex_index,
3049 unsigned const_index,
3050 LLVMTypeRef type)
3051 {
3052 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3053 LLVMValueRef vtx_offset;
3054 unsigned param, vtx_offset_param;
3055 LLVMValueRef value[4], result;
3056
3057 vtx_offset_param = vertex_index;
3058 assert(vtx_offset_param < 6);
3059 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3060 LLVMConstInt(ctx->ac.i32, 4, false), "");
3061
3062 param = shader_io_get_unique_index(location);
3063
3064 for (unsigned i = component; i < num_components + component; i++) {
3065 if (ctx->ac.chip_class >= GFX9) {
3066 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3067 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3068 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3069 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3070 } else {
3071 LLVMValueRef soffset =
3072 LLVMConstInt(ctx->ac.i32,
3073 (param * 4 + i + const_index) * 256,
3074 false);
3075
3076 value[i] = ac_build_buffer_load(&ctx->ac,
3077 ctx->esgs_ring, 1,
3078 ctx->ac.i32_0,
3079 vtx_offset, soffset,
3080 0, 1, 0, true, false);
3081
3082 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3083 type, "");
3084 }
3085 }
3086 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3087 result = ac_to_integer(&ctx->ac, result);
3088 return result;
3089 }
3090
3091 static LLVMValueRef
3092 build_gep_for_deref(struct ac_nir_context *ctx,
3093 nir_deref_var *deref)
3094 {
3095 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3096 assert(entry->data);
3097 LLVMValueRef val = entry->data;
3098 nir_deref *tail = deref->deref.child;
3099 while (tail != NULL) {
3100 LLVMValueRef offset;
3101 switch (tail->deref_type) {
3102 case nir_deref_type_array: {
3103 nir_deref_array *array = nir_deref_as_array(tail);
3104 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3105 if (array->deref_array_type ==
3106 nir_deref_array_type_indirect) {
3107 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3108 get_src(ctx,
3109 array->indirect),
3110 "");
3111 }
3112 break;
3113 }
3114 case nir_deref_type_struct: {
3115 nir_deref_struct *deref_struct =
3116 nir_deref_as_struct(tail);
3117 offset = LLVMConstInt(ctx->ac.i32,
3118 deref_struct->index, 0);
3119 break;
3120 }
3121 default:
3122 unreachable("bad deref type");
3123 }
3124 val = ac_build_gep0(&ctx->ac, val, offset);
3125 tail = tail->child;
3126 }
3127 return val;
3128 }
3129
3130 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3131 nir_intrinsic_instr *instr,
3132 bool load_inputs)
3133 {
3134 LLVMValueRef result;
3135 LLVMValueRef vertex_index = NULL;
3136 LLVMValueRef indir_index = NULL;
3137 unsigned const_index = 0;
3138 unsigned location = instr->variables[0]->var->data.location;
3139 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3140 const bool is_patch = instr->variables[0]->var->data.patch;
3141 const bool is_compact = instr->variables[0]->var->data.compact;
3142
3143 get_deref_offset(ctx, instr->variables[0],
3144 false, NULL, is_patch ? NULL : &vertex_index,
3145 &const_index, &indir_index);
3146
3147 LLVMTypeRef dest_type = get_def_type(ctx, &instr->dest.ssa);
3148
3149 LLVMTypeRef src_component_type;
3150 if (LLVMGetTypeKind(dest_type) == LLVMVectorTypeKind)
3151 src_component_type = LLVMGetElementType(dest_type);
3152 else
3153 src_component_type = dest_type;
3154
3155 result = ctx->abi->load_tess_varyings(ctx->abi, src_component_type,
3156 vertex_index, indir_index,
3157 const_index, location, driver_location,
3158 instr->variables[0]->var->data.location_frac,
3159 instr->num_components,
3160 is_patch, is_compact, load_inputs);
3161 return LLVMBuildBitCast(ctx->ac.builder, result, dest_type, "");
3162 }
3163
3164 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3165 nir_intrinsic_instr *instr)
3166 {
3167 LLVMValueRef values[8];
3168 int idx = instr->variables[0]->var->data.driver_location;
3169 int ve = instr->dest.ssa.num_components;
3170 unsigned comp = instr->variables[0]->var->data.location_frac;
3171 LLVMValueRef indir_index;
3172 LLVMValueRef ret;
3173 unsigned const_index;
3174 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3175 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3176 instr->variables[0]->var->data.mode == nir_var_shader_in;
3177 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3178 &const_index, &indir_index);
3179
3180 if (instr->dest.ssa.bit_size == 64)
3181 ve *= 2;
3182
3183 switch (instr->variables[0]->var->data.mode) {
3184 case nir_var_shader_in:
3185 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3186 ctx->stage == MESA_SHADER_TESS_EVAL) {
3187 return load_tess_varyings(ctx, instr, true);
3188 }
3189
3190 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3191 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3192 LLVMValueRef indir_index;
3193 unsigned const_index, vertex_index;
3194 get_deref_offset(ctx, instr->variables[0],
3195 false, &vertex_index, NULL,
3196 &const_index, &indir_index);
3197
3198 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3199 instr->variables[0]->var->data.driver_location,
3200 instr->variables[0]->var->data.location_frac, ve,
3201 vertex_index, const_index, type);
3202 }
3203
3204 for (unsigned chan = comp; chan < ve + comp; chan++) {
3205 if (indir_index) {
3206 unsigned count = glsl_count_attribute_slots(
3207 instr->variables[0]->var->type,
3208 ctx->stage == MESA_SHADER_VERTEX);
3209 count -= chan / 4;
3210 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3211 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3212 stride, false, true);
3213
3214 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3215 tmp_vec,
3216 indir_index, "");
3217 } else
3218 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3219 }
3220 break;
3221 case nir_var_local:
3222 for (unsigned chan = 0; chan < ve; chan++) {
3223 if (indir_index) {
3224 unsigned count = glsl_count_attribute_slots(
3225 instr->variables[0]->var->type, false);
3226 count -= chan / 4;
3227 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3228 &ctx->ac, ctx->locals + idx + chan, count,
3229 stride, true, true);
3230
3231 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3232 tmp_vec,
3233 indir_index, "");
3234 } else {
3235 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3236 }
3237 }
3238 break;
3239 case nir_var_shared: {
3240 LLVMValueRef address = build_gep_for_deref(ctx,
3241 instr->variables[0]);
3242 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3243 return LLVMBuildBitCast(ctx->ac.builder, val,
3244 get_def_type(ctx, &instr->dest.ssa),
3245 "");
3246 }
3247 case nir_var_shader_out:
3248 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3249 return load_tess_varyings(ctx, instr, false);
3250 }
3251
3252 for (unsigned chan = comp; chan < ve + comp; chan++) {
3253 if (indir_index) {
3254 unsigned count = glsl_count_attribute_slots(
3255 instr->variables[0]->var->type, false);
3256 count -= chan / 4;
3257 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3258 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3259 stride, true, true);
3260
3261 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3262 tmp_vec,
3263 indir_index, "");
3264 } else {
3265 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3266 ctx->abi->outputs[idx + chan + const_index * stride],
3267 "");
3268 }
3269 }
3270 break;
3271 default:
3272 unreachable("unhandle variable mode");
3273 }
3274 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3275 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3276 }
3277
3278 static void
3279 visit_store_var(struct ac_nir_context *ctx,
3280 nir_intrinsic_instr *instr)
3281 {
3282 LLVMValueRef temp_ptr, value;
3283 int idx = instr->variables[0]->var->data.driver_location;
3284 unsigned comp = instr->variables[0]->var->data.location_frac;
3285 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3286 int writemask = instr->const_index[0] << comp;
3287 LLVMValueRef indir_index;
3288 unsigned const_index;
3289 get_deref_offset(ctx, instr->variables[0], false,
3290 NULL, NULL, &const_index, &indir_index);
3291
3292 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3293
3294 src = LLVMBuildBitCast(ctx->ac.builder, src,
3295 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3296 "");
3297
3298 writemask = widen_mask(writemask, 2);
3299 }
3300
3301 switch (instr->variables[0]->var->data.mode) {
3302 case nir_var_shader_out:
3303
3304 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3305 LLVMValueRef vertex_index = NULL;
3306 LLVMValueRef indir_index = NULL;
3307 unsigned const_index = 0;
3308 const unsigned location = instr->variables[0]->var->data.location;
3309 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3310 const unsigned comp = instr->variables[0]->var->data.location_frac;
3311 const bool is_patch = instr->variables[0]->var->data.patch;
3312 const bool is_compact = instr->variables[0]->var->data.compact;
3313
3314 get_deref_offset(ctx, instr->variables[0],
3315 false, NULL, is_patch ? NULL : &vertex_index,
3316 &const_index, &indir_index);
3317
3318 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3319 const_index, location, driver_location,
3320 src, comp, is_patch, is_compact, writemask);
3321 return;
3322 }
3323
3324 for (unsigned chan = 0; chan < 8; chan++) {
3325 int stride = 4;
3326 if (!(writemask & (1 << chan)))
3327 continue;
3328
3329 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3330
3331 if (instr->variables[0]->var->data.compact)
3332 stride = 1;
3333 if (indir_index) {
3334 unsigned count = glsl_count_attribute_slots(
3335 instr->variables[0]->var->type, false);
3336 count -= chan / 4;
3337 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3338 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3339 stride, true, true);
3340
3341 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3342 value, indir_index, "");
3343 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3344 count, stride, tmp_vec);
3345
3346 } else {
3347 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3348
3349 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3350 }
3351 }
3352 break;
3353 case nir_var_local:
3354 for (unsigned chan = 0; chan < 8; chan++) {
3355 if (!(writemask & (1 << chan)))
3356 continue;
3357
3358 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3359 if (indir_index) {
3360 unsigned count = glsl_count_attribute_slots(
3361 instr->variables[0]->var->type, false);
3362 count -= chan / 4;
3363 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3364 &ctx->ac, ctx->locals + idx + chan, count,
3365 4, true, true);
3366
3367 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3368 value, indir_index, "");
3369 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3370 count, 4, tmp_vec);
3371 } else {
3372 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3373
3374 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3375 }
3376 }
3377 break;
3378 case nir_var_shared: {
3379 int writemask = instr->const_index[0];
3380 LLVMValueRef address = build_gep_for_deref(ctx,
3381 instr->variables[0]);
3382 LLVMValueRef val = get_src(ctx, instr->src[0]);
3383 unsigned components =
3384 glsl_get_vector_elements(
3385 nir_deref_tail(&instr->variables[0]->deref)->type);
3386 if (writemask == (1 << components) - 1) {
3387 val = LLVMBuildBitCast(
3388 ctx->ac.builder, val,
3389 LLVMGetElementType(LLVMTypeOf(address)), "");
3390 LLVMBuildStore(ctx->ac.builder, val, address);
3391 } else {
3392 for (unsigned chan = 0; chan < 4; chan++) {
3393 if (!(writemask & (1 << chan)))
3394 continue;
3395 LLVMValueRef ptr =
3396 LLVMBuildStructGEP(ctx->ac.builder,
3397 address, chan, "");
3398 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3399 chan);
3400 src = LLVMBuildBitCast(
3401 ctx->ac.builder, src,
3402 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3403 LLVMBuildStore(ctx->ac.builder, src, ptr);
3404 }
3405 }
3406 break;
3407 }
3408 default:
3409 break;
3410 }
3411 }
3412
3413 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3414 {
3415 switch (dim) {
3416 case GLSL_SAMPLER_DIM_BUF:
3417 return 1;
3418 case GLSL_SAMPLER_DIM_1D:
3419 return array ? 2 : 1;
3420 case GLSL_SAMPLER_DIM_2D:
3421 return array ? 3 : 2;
3422 case GLSL_SAMPLER_DIM_MS:
3423 return array ? 4 : 3;
3424 case GLSL_SAMPLER_DIM_3D:
3425 case GLSL_SAMPLER_DIM_CUBE:
3426 return 3;
3427 case GLSL_SAMPLER_DIM_RECT:
3428 case GLSL_SAMPLER_DIM_SUBPASS:
3429 return 2;
3430 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3431 return 3;
3432 default:
3433 break;
3434 }
3435 return 0;
3436 }
3437
3438 static bool
3439 glsl_is_array_image(const struct glsl_type *type)
3440 {
3441 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3442
3443 if (glsl_sampler_type_is_array(type))
3444 return true;
3445
3446 return dim == GLSL_SAMPLER_DIM_CUBE ||
3447 dim == GLSL_SAMPLER_DIM_3D ||
3448 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3449 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3450 }
3451
3452
3453 /* Adjust the sample index according to FMASK.
3454 *
3455 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3456 * which is the identity mapping. Each nibble says which physical sample
3457 * should be fetched to get that sample.
3458 *
3459 * For example, 0x11111100 means there are only 2 samples stored and
3460 * the second sample covers 3/4 of the pixel. When reading samples 0
3461 * and 1, return physical sample 0 (determined by the first two 0s
3462 * in FMASK), otherwise return physical sample 1.
3463 *
3464 * The sample index should be adjusted as follows:
3465 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3466 */
3467 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3468 LLVMValueRef coord_x, LLVMValueRef coord_y,
3469 LLVMValueRef coord_z,
3470 LLVMValueRef sample_index,
3471 LLVMValueRef fmask_desc_ptr)
3472 {
3473 LLVMValueRef fmask_load_address[4];
3474 LLVMValueRef res;
3475
3476 fmask_load_address[0] = coord_x;
3477 fmask_load_address[1] = coord_y;
3478 if (coord_z) {
3479 fmask_load_address[2] = coord_z;
3480 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3481 }
3482
3483 struct ac_image_args args = {0};
3484
3485 args.opcode = ac_image_load;
3486 args.da = coord_z ? true : false;
3487 args.resource = fmask_desc_ptr;
3488 args.dmask = 0xf;
3489 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3490
3491 res = ac_build_image_opcode(ctx, &args);
3492
3493 res = ac_to_integer(ctx, res);
3494 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3495 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3496
3497 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3498 res,
3499 ctx->i32_0, "");
3500
3501 LLVMValueRef sample_index4 =
3502 LLVMBuildMul(ctx->builder, sample_index, four, "");
3503 LLVMValueRef shifted_fmask =
3504 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3505 LLVMValueRef final_sample =
3506 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3507
3508 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3509 * resource descriptor is 0 (invalid),
3510 */
3511 LLVMValueRef fmask_desc =
3512 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3513 ctx->v8i32, "");
3514
3515 LLVMValueRef fmask_word1 =
3516 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3517 ctx->i32_1, "");
3518
3519 LLVMValueRef word1_is_nonzero =
3520 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3521 fmask_word1, ctx->i32_0, "");
3522
3523 /* Replace the MSAA sample index. */
3524 sample_index =
3525 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3526 final_sample, sample_index, "");
3527 return sample_index;
3528 }
3529
3530 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3531 const nir_intrinsic_instr *instr)
3532 {
3533 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3534
3535 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3536 LLVMValueRef coords[4];
3537 LLVMValueRef masks[] = {
3538 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3539 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3540 };
3541 LLVMValueRef res;
3542 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3543
3544 int count;
3545 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3546 bool is_array = glsl_sampler_type_is_array(type);
3547 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3548 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3549 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3550 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3551 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3552 count = image_type_to_components_count(dim, is_array);
3553
3554 if (is_ms) {
3555 LLVMValueRef fmask_load_address[3];
3556 int chan;
3557
3558 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3559 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3560 if (is_array)
3561 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3562 else
3563 fmask_load_address[2] = NULL;
3564 if (add_frag_pos) {
3565 for (chan = 0; chan < 2; ++chan)
3566 fmask_load_address[chan] =
3567 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3568 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3569 ctx->ac.i32, ""), "");
3570 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3571 }
3572 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3573 fmask_load_address[0],
3574 fmask_load_address[1],
3575 fmask_load_address[2],
3576 sample_index,
3577 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3578 }
3579 if (count == 1 && !gfx9_1d) {
3580 if (instr->src[0].ssa->num_components)
3581 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3582 else
3583 res = src0;
3584 } else {
3585 int chan;
3586 if (is_ms)
3587 count--;
3588 for (chan = 0; chan < count; ++chan) {
3589 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3590 }
3591 if (add_frag_pos) {
3592 for (chan = 0; chan < 2; ++chan)
3593 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3594 ctx->ac.i32, ""), "");
3595 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3596 count++;
3597 }
3598
3599 if (gfx9_1d) {
3600 if (is_array) {
3601 coords[2] = coords[1];
3602 coords[1] = ctx->ac.i32_0;
3603 } else
3604 coords[1] = ctx->ac.i32_0;
3605 count++;
3606 }
3607
3608 if (is_ms) {
3609 coords[count] = sample_index;
3610 count++;
3611 }
3612
3613 if (count == 3) {
3614 coords[3] = LLVMGetUndef(ctx->ac.i32);
3615 count = 4;
3616 }
3617 res = ac_build_gather_values(&ctx->ac, coords, count);
3618 }
3619 return res;
3620 }
3621
3622 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3623 const nir_intrinsic_instr *instr)
3624 {
3625 LLVMValueRef params[7];
3626 LLVMValueRef res;
3627 char intrinsic_name[64];
3628 const nir_variable *var = instr->variables[0]->var;
3629 const struct glsl_type *type = var->type;
3630
3631 if(instr->variables[0]->deref.child)
3632 type = instr->variables[0]->deref.child->type;
3633
3634 type = glsl_without_array(type);
3635
3636 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3637 if (dim == GLSL_SAMPLER_DIM_BUF) {
3638 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3639 unsigned num_channels = util_last_bit(mask);
3640 LLVMValueRef rsrc, vindex;
3641
3642 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3643 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3644 ctx->ac.i32_0, "");
3645
3646 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3647 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3648 ctx->ac.i32_0, num_channels,
3649 false, false);
3650 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3651
3652 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3653 res = ac_to_integer(&ctx->ac, res);
3654 } else {
3655 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3656 LLVMValueRef slc = ctx->ac.i1false;
3657
3658 params[0] = get_image_coords(ctx, instr);
3659 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3660 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3661 params[3] = (var->data.image._volatile || var->data.image.coherent) ?
3662 ctx->ac.i1true : ctx->ac.i1false;
3663 params[4] = slc;
3664 params[5] = ctx->ac.i1false;
3665 params[6] = da;
3666
3667 ac_get_image_intr_name("llvm.amdgcn.image.load",
3668 ctx->ac.v4f32, /* vdata */
3669 LLVMTypeOf(params[0]), /* coords */
3670 LLVMTypeOf(params[1]), /* rsrc */
3671 intrinsic_name, sizeof(intrinsic_name));
3672
3673 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3674 params, 7, AC_FUNC_ATTR_READONLY);
3675 }
3676 return ac_to_integer(&ctx->ac, res);
3677 }
3678
3679 static void visit_image_store(struct ac_nir_context *ctx,
3680 nir_intrinsic_instr *instr)
3681 {
3682 LLVMValueRef params[8];
3683 char intrinsic_name[64];
3684 const nir_variable *var = instr->variables[0]->var;
3685 const struct glsl_type *type = glsl_without_array(var->type);
3686 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3687 LLVMValueRef glc = ctx->ac.i1false;
3688 bool force_glc = ctx->ac.chip_class == SI;
3689 if (force_glc)
3690 glc = ctx->ac.i1true;
3691
3692 if (dim == GLSL_SAMPLER_DIM_BUF) {
3693 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3694 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3695 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3696 ctx->ac.i32_0, ""); /* vindex */
3697 params[3] = ctx->ac.i32_0; /* voffset */
3698 params[4] = glc; /* glc */
3699 params[5] = ctx->ac.i1false; /* slc */
3700 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3701 params, 6, 0);
3702 } else {
3703 LLVMValueRef da = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false;
3704 LLVMValueRef slc = ctx->ac.i1false;
3705
3706 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3707 params[1] = get_image_coords(ctx, instr); /* coords */
3708 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3709 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3710 params[4] = (force_glc || var->data.image._volatile || var->data.image.coherent) ?
3711 ctx->ac.i1true : ctx->ac.i1false;
3712 params[5] = slc;
3713 params[6] = ctx->ac.i1false;
3714 params[7] = da;
3715
3716 ac_get_image_intr_name("llvm.amdgcn.image.store",
3717 LLVMTypeOf(params[0]), /* vdata */
3718 LLVMTypeOf(params[1]), /* coords */
3719 LLVMTypeOf(params[2]), /* rsrc */
3720 intrinsic_name, sizeof(intrinsic_name));
3721
3722 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3723 params, 8, 0);
3724 }
3725
3726 }
3727
3728 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3729 const nir_intrinsic_instr *instr)
3730 {
3731 LLVMValueRef params[7];
3732 int param_count = 0;
3733 const nir_variable *var = instr->variables[0]->var;
3734
3735 const char *atomic_name;
3736 char intrinsic_name[41];
3737 const struct glsl_type *type = glsl_without_array(var->type);
3738 MAYBE_UNUSED int length;
3739
3740 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3741
3742 switch (instr->intrinsic) {
3743 case nir_intrinsic_image_atomic_add:
3744 atomic_name = "add";
3745 break;
3746 case nir_intrinsic_image_atomic_min:
3747 atomic_name = is_unsigned ? "umin" : "smin";
3748 break;
3749 case nir_intrinsic_image_atomic_max:
3750 atomic_name = is_unsigned ? "umax" : "smax";
3751 break;
3752 case nir_intrinsic_image_atomic_and:
3753 atomic_name = "and";
3754 break;
3755 case nir_intrinsic_image_atomic_or:
3756 atomic_name = "or";
3757 break;
3758 case nir_intrinsic_image_atomic_xor:
3759 atomic_name = "xor";
3760 break;
3761 case nir_intrinsic_image_atomic_exchange:
3762 atomic_name = "swap";
3763 break;
3764 case nir_intrinsic_image_atomic_comp_swap:
3765 atomic_name = "cmpswap";
3766 break;
3767 default:
3768 abort();
3769 }
3770
3771 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3772 params[param_count++] = get_src(ctx, instr->src[3]);
3773 params[param_count++] = get_src(ctx, instr->src[2]);
3774
3775 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3776 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3777 NULL, true, true);
3778 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3779 ctx->ac.i32_0, ""); /* vindex */
3780 params[param_count++] = ctx->ac.i32_0; /* voffset */
3781 params[param_count++] = ctx->ac.i1false; /* slc */
3782
3783 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3784 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3785 } else {
3786 char coords_type[8];
3787
3788 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3789 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3790 NULL, true, true);
3791 params[param_count++] = ctx->ac.i1false; /* r128 */
3792 params[param_count++] = glsl_is_array_image(type) ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3793 params[param_count++] = ctx->ac.i1false; /* slc */
3794
3795 build_int_type_name(LLVMTypeOf(coords),
3796 coords_type, sizeof(coords_type));
3797
3798 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3799 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3800 }
3801
3802 assert(length < sizeof(intrinsic_name));
3803 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3804 }
3805
3806 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3807 const nir_intrinsic_instr *instr)
3808 {
3809 const nir_variable *var = instr->variables[0]->var;
3810 const struct glsl_type *type = glsl_without_array(var->type);
3811
3812 struct ac_image_args args = { 0 };
3813 args.da = glsl_is_array_image(type);
3814 args.dmask = 0xf;
3815 args.resource = get_sampler_desc(ctx, instr->variables[0],
3816 AC_DESC_IMAGE, NULL, true, false);
3817 args.opcode = ac_image_get_resinfo;
3818 args.addr = ctx->ac.i32_0;
3819
3820 return ac_build_image_opcode(&ctx->ac, &args);
3821 }
3822
3823 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3824 const nir_intrinsic_instr *instr)
3825 {
3826 LLVMValueRef res;
3827 const nir_variable *var = instr->variables[0]->var;
3828 const struct glsl_type *type = glsl_without_array(var->type);
3829
3830 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3831 return get_buffer_size(ctx,
3832 get_sampler_desc(ctx, instr->variables[0],
3833 AC_DESC_BUFFER, NULL, true, false), true);
3834
3835 struct ac_image_args args = { 0 };
3836
3837 args.da = glsl_is_array_image(type);
3838 args.dmask = 0xf;
3839 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3840 args.opcode = ac_image_get_resinfo;
3841 args.addr = ctx->ac.i32_0;
3842
3843 res = ac_build_image_opcode(&ctx->ac, &args);
3844
3845 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3846
3847 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3848 glsl_sampler_type_is_array(type)) {
3849 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3850 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3851 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3852 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3853 }
3854 if (ctx->ac.chip_class >= GFX9 &&
3855 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3856 glsl_sampler_type_is_array(type)) {
3857 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3858 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3859 ctx->ac.i32_1, "");
3860
3861 }
3862 return res;
3863 }
3864
3865 #define NOOP_WAITCNT 0xf7f
3866 #define LGKM_CNT 0x07f
3867 #define VM_CNT 0xf70
3868
3869 static void emit_membar(struct ac_llvm_context *ac,
3870 const nir_intrinsic_instr *instr)
3871 {
3872 unsigned waitcnt = NOOP_WAITCNT;
3873
3874 switch (instr->intrinsic) {
3875 case nir_intrinsic_memory_barrier:
3876 case nir_intrinsic_group_memory_barrier:
3877 waitcnt &= VM_CNT & LGKM_CNT;
3878 break;
3879 case nir_intrinsic_memory_barrier_atomic_counter:
3880 case nir_intrinsic_memory_barrier_buffer:
3881 case nir_intrinsic_memory_barrier_image:
3882 waitcnt &= VM_CNT;
3883 break;
3884 case nir_intrinsic_memory_barrier_shared:
3885 waitcnt &= LGKM_CNT;
3886 break;
3887 default:
3888 break;
3889 }
3890 if (waitcnt != NOOP_WAITCNT)
3891 ac_build_waitcnt(ac, waitcnt);
3892 }
3893
3894 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3895 {
3896 /* SI only (thanks to a hw bug workaround):
3897 * The real barrier instruction isn’t needed, because an entire patch
3898 * always fits into a single wave.
3899 */
3900 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3901 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3902 return;
3903 }
3904 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3905 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3906 }
3907
3908 static void emit_discard(struct ac_nir_context *ctx,
3909 const nir_intrinsic_instr *instr)
3910 {
3911 LLVMValueRef cond;
3912
3913 if (instr->intrinsic == nir_intrinsic_discard_if) {
3914 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3915 get_src(ctx, instr->src[0]),
3916 ctx->ac.i32_0, "");
3917 } else {
3918 assert(instr->intrinsic == nir_intrinsic_discard);
3919 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3920 }
3921
3922 ac_build_kill_if_false(&ctx->ac, cond);
3923 }
3924
3925 static LLVMValueRef
3926 visit_load_helper_invocation(struct ac_nir_context *ctx)
3927 {
3928 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3929 "llvm.amdgcn.ps.live",
3930 ctx->ac.i1, NULL, 0,
3931 AC_FUNC_ATTR_READNONE);
3932 result = LLVMBuildNot(ctx->ac.builder, result, "");
3933 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3934 }
3935
3936 static LLVMValueRef
3937 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3938 {
3939 LLVMValueRef result;
3940 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3941 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3942 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3943
3944 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3945 }
3946
3947 static LLVMValueRef
3948 visit_load_shared(struct ac_nir_context *ctx,
3949 const nir_intrinsic_instr *instr)
3950 {
3951 LLVMValueRef values[4], derived_ptr, index, ret;
3952
3953 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3954
3955 for (int chan = 0; chan < instr->num_components; chan++) {
3956 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3957 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3958 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3959 }
3960
3961 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3962 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3963 }
3964
3965 static void
3966 visit_store_shared(struct ac_nir_context *ctx,
3967 const nir_intrinsic_instr *instr)
3968 {
3969 LLVMValueRef derived_ptr, data,index;
3970 LLVMBuilderRef builder = ctx->ac.builder;
3971
3972 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3973 LLVMValueRef src = get_src(ctx, instr->src[0]);
3974
3975 int writemask = nir_intrinsic_write_mask(instr);
3976 for (int chan = 0; chan < 4; chan++) {
3977 if (!(writemask & (1 << chan))) {
3978 continue;
3979 }
3980 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3981 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3982 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3983 LLVMBuildStore(builder, data, derived_ptr);
3984 }
3985 }
3986
3987 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3988 const nir_intrinsic_instr *instr,
3989 LLVMValueRef ptr)
3990 {
3991 LLVMValueRef result;
3992 LLVMValueRef src = get_src(ctx, instr->src[0]);
3993
3994 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3995 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3996 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3997 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3998 ptr, src, src1,
3999 LLVMAtomicOrderingSequentiallyConsistent,
4000 LLVMAtomicOrderingSequentiallyConsistent,
4001 false);
4002 } else {
4003 LLVMAtomicRMWBinOp op;
4004 switch (instr->intrinsic) {
4005 case nir_intrinsic_var_atomic_add:
4006 case nir_intrinsic_shared_atomic_add:
4007 op = LLVMAtomicRMWBinOpAdd;
4008 break;
4009 case nir_intrinsic_var_atomic_umin:
4010 case nir_intrinsic_shared_atomic_umin:
4011 op = LLVMAtomicRMWBinOpUMin;
4012 break;
4013 case nir_intrinsic_var_atomic_umax:
4014 case nir_intrinsic_shared_atomic_umax:
4015 op = LLVMAtomicRMWBinOpUMax;
4016 break;
4017 case nir_intrinsic_var_atomic_imin:
4018 case nir_intrinsic_shared_atomic_imin:
4019 op = LLVMAtomicRMWBinOpMin;
4020 break;
4021 case nir_intrinsic_var_atomic_imax:
4022 case nir_intrinsic_shared_atomic_imax:
4023 op = LLVMAtomicRMWBinOpMax;
4024 break;
4025 case nir_intrinsic_var_atomic_and:
4026 case nir_intrinsic_shared_atomic_and:
4027 op = LLVMAtomicRMWBinOpAnd;
4028 break;
4029 case nir_intrinsic_var_atomic_or:
4030 case nir_intrinsic_shared_atomic_or:
4031 op = LLVMAtomicRMWBinOpOr;
4032 break;
4033 case nir_intrinsic_var_atomic_xor:
4034 case nir_intrinsic_shared_atomic_xor:
4035 op = LLVMAtomicRMWBinOpXor;
4036 break;
4037 case nir_intrinsic_var_atomic_exchange:
4038 case nir_intrinsic_shared_atomic_exchange:
4039 op = LLVMAtomicRMWBinOpXchg;
4040 break;
4041 default:
4042 return NULL;
4043 }
4044
4045 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4046 LLVMAtomicOrderingSequentiallyConsistent,
4047 false);
4048 }
4049 return result;
4050 }
4051
4052 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4053 enum glsl_interp_mode interp, unsigned location)
4054 {
4055 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4056
4057 switch (interp) {
4058 case INTERP_MODE_FLAT:
4059 default:
4060 return NULL;
4061 case INTERP_MODE_SMOOTH:
4062 case INTERP_MODE_NONE:
4063 if (location == INTERP_CENTER)
4064 return ctx->persp_center;
4065 else if (location == INTERP_CENTROID)
4066 return ctx->persp_centroid;
4067 else if (location == INTERP_SAMPLE)
4068 return ctx->persp_sample;
4069 break;
4070 case INTERP_MODE_NOPERSPECTIVE:
4071 if (location == INTERP_CENTER)
4072 return ctx->linear_center;
4073 else if (location == INTERP_CENTROID)
4074 return ctx->linear_centroid;
4075 else if (location == INTERP_SAMPLE)
4076 return ctx->linear_sample;
4077 break;
4078 }
4079 return NULL;
4080 }
4081
4082 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4083 LLVMValueRef sample_id)
4084 {
4085 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4086
4087 LLVMValueRef result;
4088 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4089
4090 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4091 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4092
4093 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4094 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4095
4096 return result;
4097 }
4098
4099 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4100 {
4101 LLVMValueRef values[2];
4102
4103 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4104 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4105 return ac_build_gather_values(&ctx->ac, values, 2);
4106 }
4107
4108 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4109 {
4110 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4111 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4112 ctx->options->key.fs.log2_num_samples :
4113 ctx->options->key.fs.log2_ps_iter_samples;
4114
4115 /* The bit pattern matches that used by fixed function fragment
4116 * processing. */
4117 static const uint16_t ps_iter_masks[] = {
4118 0xffff, /* not used */
4119 0x5555,
4120 0x1111,
4121 0x0101,
4122 0x0001,
4123 };
4124 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4125
4126 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4127
4128 LLVMValueRef result, sample_id;
4129 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4130 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4131 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4132 return result;
4133 }
4134
4135 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4136 const nir_intrinsic_instr *instr)
4137 {
4138 LLVMValueRef result[4];
4139 LLVMValueRef interp_param, attr_number;
4140 unsigned location;
4141 unsigned chan;
4142 LLVMValueRef src_c0 = NULL;
4143 LLVMValueRef src_c1 = NULL;
4144 LLVMValueRef src0 = NULL;
4145 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4146 switch (instr->intrinsic) {
4147 case nir_intrinsic_interp_var_at_centroid:
4148 location = INTERP_CENTROID;
4149 break;
4150 case nir_intrinsic_interp_var_at_sample:
4151 case nir_intrinsic_interp_var_at_offset:
4152 location = INTERP_CENTER;
4153 src0 = get_src(ctx, instr->src[0]);
4154 break;
4155 default:
4156 break;
4157 }
4158
4159 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4160 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4161 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4162 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4163 LLVMValueRef sample_position;
4164 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4165
4166 /* fetch sample ID */
4167 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4168
4169 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4170 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4171 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4172 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4173 }
4174 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4175 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4176
4177 if (location == INTERP_CENTER) {
4178 LLVMValueRef ij_out[2];
4179 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4180
4181 /*
4182 * take the I then J parameters, and the DDX/Y for it, and
4183 * calculate the IJ inputs for the interpolator.
4184 * temp1 = ddx * offset/sample.x + I;
4185 * interp_param.I = ddy * offset/sample.y + temp1;
4186 * temp1 = ddx * offset/sample.x + J;
4187 * interp_param.J = ddy * offset/sample.y + temp1;
4188 */
4189 for (unsigned i = 0; i < 2; i++) {
4190 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4191 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4192 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4193 ddxy_out, ix_ll, "");
4194 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4195 ddxy_out, iy_ll, "");
4196 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4197 interp_param, ix_ll, "");
4198 LLVMValueRef temp1, temp2;
4199
4200 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4201 ctx->ac.f32, "");
4202
4203 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4204 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4205
4206 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4207 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4208
4209 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4210 temp2, ctx->ac.i32, "");
4211 }
4212 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4213
4214 }
4215
4216 for (chan = 0; chan < 4; chan++) {
4217 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4218
4219 if (interp_param) {
4220 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4221 interp_param, ctx->ac.v2f32, "");
4222 LLVMValueRef i = LLVMBuildExtractElement(
4223 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4224 LLVMValueRef j = LLVMBuildExtractElement(
4225 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4226
4227 result[chan] = ac_build_fs_interp(&ctx->ac,
4228 llvm_chan, attr_number,
4229 ctx->abi->prim_mask, i, j);
4230 } else {
4231 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4232 LLVMConstInt(ctx->ac.i32, 2, false),
4233 llvm_chan, attr_number,
4234 ctx->abi->prim_mask);
4235 }
4236 }
4237 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4238 instr->variables[0]->var->data.location_frac);
4239 }
4240
4241 static void
4242 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4243 {
4244 LLVMValueRef gs_next_vertex;
4245 LLVMValueRef can_emit;
4246 int idx;
4247 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4248
4249 assert(stream == 0);
4250
4251 /* Write vertex attribute values to GSVS ring */
4252 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4253 ctx->gs_next_vertex,
4254 "");
4255
4256 /* If this thread has already emitted the declared maximum number of
4257 * vertices, kill it: excessive vertex emissions are not supposed to
4258 * have any effect, and GS threads have no externally observable
4259 * effects other than emitting vertices.
4260 */
4261 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4262 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4263 ac_build_kill_if_false(&ctx->ac, can_emit);
4264
4265 /* loop num outputs */
4266 idx = 0;
4267 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4268 LLVMValueRef *out_ptr = &addrs[i * 4];
4269 int length = 4;
4270 int slot = idx;
4271 int slot_inc = 1;
4272
4273 if (!(ctx->output_mask & (1ull << i)))
4274 continue;
4275
4276 if (i == VARYING_SLOT_CLIP_DIST0) {
4277 /* pack clip and cull into a single set of slots */
4278 length = ctx->num_output_clips + ctx->num_output_culls;
4279 if (length > 4)
4280 slot_inc = 2;
4281 }
4282 for (unsigned j = 0; j < length; j++) {
4283 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4284 out_ptr[j], "");
4285 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4286 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4287 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4288
4289 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4290
4291 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4292 out_val, 1,
4293 voffset, ctx->gs2vs_offset, 0,
4294 1, 1, true, true);
4295 }
4296 idx += slot_inc;
4297 }
4298
4299 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4300 ctx->ac.i32_1, "");
4301 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4302
4303 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4304 }
4305
4306 static void
4307 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4308 {
4309 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4310 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4311 }
4312
4313 static LLVMValueRef
4314 load_tess_coord(struct ac_shader_abi *abi)
4315 {
4316 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4317
4318 LLVMValueRef coord[4] = {
4319 ctx->tes_u,
4320 ctx->tes_v,
4321 ctx->ac.f32_0,
4322 ctx->ac.f32_0,
4323 };
4324
4325 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4326 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4327 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4328
4329 return ac_build_gather_values(&ctx->ac, coord, 3);
4330 }
4331
4332 static LLVMValueRef
4333 load_patch_vertices_in(struct ac_shader_abi *abi)
4334 {
4335 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4336 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4337 }
4338
4339 static void visit_intrinsic(struct ac_nir_context *ctx,
4340 nir_intrinsic_instr *instr)
4341 {
4342 LLVMValueRef result = NULL;
4343
4344 switch (instr->intrinsic) {
4345 case nir_intrinsic_ballot:
4346 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4347 break;
4348 case nir_intrinsic_read_invocation:
4349 case nir_intrinsic_read_first_invocation: {
4350 LLVMValueRef args[2];
4351
4352 /* Value */
4353 args[0] = get_src(ctx, instr->src[0]);
4354
4355 unsigned num_args;
4356 const char *intr_name;
4357 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4358 num_args = 2;
4359 intr_name = "llvm.amdgcn.readlane";
4360
4361 /* Invocation */
4362 args[1] = get_src(ctx, instr->src[1]);
4363 } else {
4364 num_args = 1;
4365 intr_name = "llvm.amdgcn.readfirstlane";
4366 }
4367
4368 /* We currently have no other way to prevent LLVM from lifting the icmp
4369 * calls to a dominating basic block.
4370 */
4371 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4372
4373 result = ac_build_intrinsic(&ctx->ac, intr_name,
4374 ctx->ac.i32, args, num_args,
4375 AC_FUNC_ATTR_READNONE |
4376 AC_FUNC_ATTR_CONVERGENT);
4377 break;
4378 }
4379 case nir_intrinsic_load_subgroup_invocation:
4380 result = ac_get_thread_id(&ctx->ac);
4381 break;
4382 case nir_intrinsic_load_work_group_id: {
4383 LLVMValueRef values[3];
4384
4385 for (int i = 0; i < 3; i++) {
4386 values[i] = ctx->abi->workgroup_ids[i] ?
4387 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4388 }
4389
4390 result = ac_build_gather_values(&ctx->ac, values, 3);
4391 break;
4392 }
4393 case nir_intrinsic_load_base_vertex: {
4394 result = ctx->abi->base_vertex;
4395 break;
4396 }
4397 case nir_intrinsic_load_local_group_size:
4398 result = ctx->abi->load_local_group_size(ctx->abi);
4399 break;
4400 case nir_intrinsic_load_vertex_id_zero_base: {
4401 result = ctx->abi->vertex_id;
4402 break;
4403 }
4404 case nir_intrinsic_load_local_invocation_id: {
4405 result = ctx->abi->local_invocation_ids;
4406 break;
4407 }
4408 case nir_intrinsic_load_base_instance:
4409 result = ctx->abi->start_instance;
4410 break;
4411 case nir_intrinsic_load_draw_id:
4412 result = ctx->abi->draw_id;
4413 break;
4414 case nir_intrinsic_load_view_index:
4415 result = ctx->abi->view_index;
4416 break;
4417 case nir_intrinsic_load_invocation_id:
4418 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4419 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4420 else
4421 result = ctx->abi->gs_invocation_id;
4422 break;
4423 case nir_intrinsic_load_primitive_id:
4424 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4425 result = ctx->abi->gs_prim_id;
4426 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4427 result = ctx->abi->tcs_patch_id;
4428 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4429 result = ctx->abi->tes_patch_id;
4430 } else
4431 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4432 break;
4433 case nir_intrinsic_load_sample_id:
4434 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4435 break;
4436 case nir_intrinsic_load_sample_pos:
4437 result = load_sample_pos(ctx);
4438 break;
4439 case nir_intrinsic_load_sample_mask_in:
4440 result = ctx->abi->load_sample_mask_in(ctx->abi);
4441 break;
4442 case nir_intrinsic_load_frag_coord: {
4443 LLVMValueRef values[4] = {
4444 ctx->abi->frag_pos[0],
4445 ctx->abi->frag_pos[1],
4446 ctx->abi->frag_pos[2],
4447 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4448 };
4449 result = ac_build_gather_values(&ctx->ac, values, 4);
4450 break;
4451 }
4452 case nir_intrinsic_load_front_face:
4453 result = ctx->abi->front_face;
4454 break;
4455 case nir_intrinsic_load_helper_invocation:
4456 result = visit_load_helper_invocation(ctx);
4457 break;
4458 case nir_intrinsic_load_instance_id:
4459 result = ctx->abi->instance_id;
4460 break;
4461 case nir_intrinsic_load_num_work_groups:
4462 result = ctx->abi->num_work_groups;
4463 break;
4464 case nir_intrinsic_load_local_invocation_index:
4465 result = visit_load_local_invocation_index(ctx);
4466 break;
4467 case nir_intrinsic_load_push_constant:
4468 result = visit_load_push_constant(ctx, instr);
4469 break;
4470 case nir_intrinsic_vulkan_resource_index: {
4471 LLVMValueRef index = get_src(ctx, instr->src[0]);
4472 unsigned desc_set = nir_intrinsic_desc_set(instr);
4473 unsigned binding = nir_intrinsic_binding(instr);
4474
4475 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4476 binding);
4477 break;
4478 }
4479 case nir_intrinsic_vulkan_resource_reindex:
4480 result = visit_vulkan_resource_reindex(ctx, instr);
4481 break;
4482 case nir_intrinsic_store_ssbo:
4483 visit_store_ssbo(ctx, instr);
4484 break;
4485 case nir_intrinsic_load_ssbo:
4486 result = visit_load_buffer(ctx, instr);
4487 break;
4488 case nir_intrinsic_ssbo_atomic_add:
4489 case nir_intrinsic_ssbo_atomic_imin:
4490 case nir_intrinsic_ssbo_atomic_umin:
4491 case nir_intrinsic_ssbo_atomic_imax:
4492 case nir_intrinsic_ssbo_atomic_umax:
4493 case nir_intrinsic_ssbo_atomic_and:
4494 case nir_intrinsic_ssbo_atomic_or:
4495 case nir_intrinsic_ssbo_atomic_xor:
4496 case nir_intrinsic_ssbo_atomic_exchange:
4497 case nir_intrinsic_ssbo_atomic_comp_swap:
4498 result = visit_atomic_ssbo(ctx, instr);
4499 break;
4500 case nir_intrinsic_load_ubo:
4501 result = visit_load_ubo_buffer(ctx, instr);
4502 break;
4503 case nir_intrinsic_get_buffer_size:
4504 result = visit_get_buffer_size(ctx, instr);
4505 break;
4506 case nir_intrinsic_load_var:
4507 result = visit_load_var(ctx, instr);
4508 break;
4509 case nir_intrinsic_store_var:
4510 visit_store_var(ctx, instr);
4511 break;
4512 case nir_intrinsic_load_shared:
4513 result = visit_load_shared(ctx, instr);
4514 break;
4515 case nir_intrinsic_store_shared:
4516 visit_store_shared(ctx, instr);
4517 break;
4518 case nir_intrinsic_image_samples:
4519 result = visit_image_samples(ctx, instr);
4520 break;
4521 case nir_intrinsic_image_load:
4522 result = visit_image_load(ctx, instr);
4523 break;
4524 case nir_intrinsic_image_store:
4525 visit_image_store(ctx, instr);
4526 break;
4527 case nir_intrinsic_image_atomic_add:
4528 case nir_intrinsic_image_atomic_min:
4529 case nir_intrinsic_image_atomic_max:
4530 case nir_intrinsic_image_atomic_and:
4531 case nir_intrinsic_image_atomic_or:
4532 case nir_intrinsic_image_atomic_xor:
4533 case nir_intrinsic_image_atomic_exchange:
4534 case nir_intrinsic_image_atomic_comp_swap:
4535 result = visit_image_atomic(ctx, instr);
4536 break;
4537 case nir_intrinsic_image_size:
4538 result = visit_image_size(ctx, instr);
4539 break;
4540 case nir_intrinsic_shader_clock:
4541 result = ac_build_shader_clock(&ctx->ac);
4542 break;
4543 case nir_intrinsic_discard:
4544 case nir_intrinsic_discard_if:
4545 emit_discard(ctx, instr);
4546 break;
4547 case nir_intrinsic_memory_barrier:
4548 case nir_intrinsic_group_memory_barrier:
4549 case nir_intrinsic_memory_barrier_atomic_counter:
4550 case nir_intrinsic_memory_barrier_buffer:
4551 case nir_intrinsic_memory_barrier_image:
4552 case nir_intrinsic_memory_barrier_shared:
4553 emit_membar(&ctx->ac, instr);
4554 break;
4555 case nir_intrinsic_barrier:
4556 emit_barrier(&ctx->ac, ctx->stage);
4557 break;
4558 case nir_intrinsic_shared_atomic_add:
4559 case nir_intrinsic_shared_atomic_imin:
4560 case nir_intrinsic_shared_atomic_umin:
4561 case nir_intrinsic_shared_atomic_imax:
4562 case nir_intrinsic_shared_atomic_umax:
4563 case nir_intrinsic_shared_atomic_and:
4564 case nir_intrinsic_shared_atomic_or:
4565 case nir_intrinsic_shared_atomic_xor:
4566 case nir_intrinsic_shared_atomic_exchange:
4567 case nir_intrinsic_shared_atomic_comp_swap: {
4568 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
4569 result = visit_var_atomic(ctx, instr, ptr);
4570 break;
4571 }
4572 case nir_intrinsic_var_atomic_add:
4573 case nir_intrinsic_var_atomic_imin:
4574 case nir_intrinsic_var_atomic_umin:
4575 case nir_intrinsic_var_atomic_imax:
4576 case nir_intrinsic_var_atomic_umax:
4577 case nir_intrinsic_var_atomic_and:
4578 case nir_intrinsic_var_atomic_or:
4579 case nir_intrinsic_var_atomic_xor:
4580 case nir_intrinsic_var_atomic_exchange:
4581 case nir_intrinsic_var_atomic_comp_swap: {
4582 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4583 result = visit_var_atomic(ctx, instr, ptr);
4584 break;
4585 }
4586 case nir_intrinsic_interp_var_at_centroid:
4587 case nir_intrinsic_interp_var_at_sample:
4588 case nir_intrinsic_interp_var_at_offset:
4589 result = visit_interp(ctx, instr);
4590 break;
4591 case nir_intrinsic_emit_vertex:
4592 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4593 break;
4594 case nir_intrinsic_end_primitive:
4595 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4596 break;
4597 case nir_intrinsic_load_tess_coord:
4598 result = ctx->abi->load_tess_coord(ctx->abi);
4599 break;
4600 case nir_intrinsic_load_tess_level_outer:
4601 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4602 break;
4603 case nir_intrinsic_load_tess_level_inner:
4604 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4605 break;
4606 case nir_intrinsic_load_patch_vertices_in:
4607 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4608 break;
4609 case nir_intrinsic_vote_all: {
4610 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4611 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4612 break;
4613 }
4614 case nir_intrinsic_vote_any: {
4615 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4616 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4617 break;
4618 }
4619 case nir_intrinsic_vote_eq: {
4620 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4621 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4622 break;
4623 }
4624 default:
4625 fprintf(stderr, "Unknown intrinsic: ");
4626 nir_print_instr(&instr->instr, stderr);
4627 fprintf(stderr, "\n");
4628 break;
4629 }
4630 if (result) {
4631 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4632 }
4633 }
4634
4635 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4636 LLVMValueRef buffer_ptr, bool write)
4637 {
4638 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4639 LLVMValueRef result;
4640
4641 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4642
4643 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4644 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4645
4646 return result;
4647 }
4648
4649 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4650 {
4651 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4652 LLVMValueRef result;
4653
4654 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4655
4656 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4657 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4658
4659 return result;
4660 }
4661
4662 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4663 unsigned descriptor_set,
4664 unsigned base_index,
4665 unsigned constant_index,
4666 LLVMValueRef index,
4667 enum ac_descriptor_type desc_type,
4668 bool image, bool write)
4669 {
4670 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4671 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4672 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4673 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4674 unsigned offset = binding->offset;
4675 unsigned stride = binding->size;
4676 unsigned type_size;
4677 LLVMBuilderRef builder = ctx->ac.builder;
4678 LLVMTypeRef type;
4679
4680 assert(base_index < layout->binding_count);
4681
4682 switch (desc_type) {
4683 case AC_DESC_IMAGE:
4684 type = ctx->ac.v8i32;
4685 type_size = 32;
4686 break;
4687 case AC_DESC_FMASK:
4688 type = ctx->ac.v8i32;
4689 offset += 32;
4690 type_size = 32;
4691 break;
4692 case AC_DESC_SAMPLER:
4693 type = ctx->ac.v4i32;
4694 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4695 offset += 64;
4696
4697 type_size = 16;
4698 break;
4699 case AC_DESC_BUFFER:
4700 type = ctx->ac.v4i32;
4701 type_size = 16;
4702 break;
4703 default:
4704 unreachable("invalid desc_type\n");
4705 }
4706
4707 offset += constant_index * stride;
4708
4709 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4710 (!index || binding->immutable_samplers_equal)) {
4711 if (binding->immutable_samplers_equal)
4712 constant_index = 0;
4713
4714 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4715
4716 LLVMValueRef constants[] = {
4717 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4718 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4719 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4720 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4721 };
4722 return ac_build_gather_values(&ctx->ac, constants, 4);
4723 }
4724
4725 assert(stride % type_size == 0);
4726
4727 if (!index)
4728 index = ctx->ac.i32_0;
4729
4730 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4731
4732 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4733 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4734
4735 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4736 }
4737
4738 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4739 const nir_deref_var *deref,
4740 enum ac_descriptor_type desc_type,
4741 const nir_tex_instr *tex_instr,
4742 bool image, bool write)
4743 {
4744 LLVMValueRef index = NULL;
4745 unsigned constant_index = 0;
4746 unsigned descriptor_set;
4747 unsigned base_index;
4748
4749 if (!deref) {
4750 assert(tex_instr && !image);
4751 descriptor_set = 0;
4752 base_index = tex_instr->sampler_index;
4753 } else {
4754 const nir_deref *tail = &deref->deref;
4755 while (tail->child) {
4756 const nir_deref_array *child = nir_deref_as_array(tail->child);
4757 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4758
4759 if (!array_size)
4760 array_size = 1;
4761
4762 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4763
4764 if (child->deref_array_type == nir_deref_array_type_indirect) {
4765 LLVMValueRef indirect = get_src(ctx, child->indirect);
4766
4767 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4768 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4769
4770 if (!index)
4771 index = indirect;
4772 else
4773 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4774 }
4775
4776 constant_index += child->base_offset * array_size;
4777
4778 tail = &child->deref;
4779 }
4780 descriptor_set = deref->var->data.descriptor_set;
4781 base_index = deref->var->data.binding;
4782 }
4783
4784 return ctx->abi->load_sampler_desc(ctx->abi,
4785 descriptor_set,
4786 base_index,
4787 constant_index, index,
4788 desc_type, image, write);
4789 }
4790
4791 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4792 struct ac_image_args *args,
4793 const nir_tex_instr *instr,
4794 nir_texop op,
4795 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4796 LLVMValueRef *param, unsigned count,
4797 unsigned dmask)
4798 {
4799 unsigned is_rect = 0;
4800 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4801
4802 if (op == nir_texop_lod)
4803 da = false;
4804 /* Pad to power of two vector */
4805 while (count < util_next_power_of_two(count))
4806 param[count++] = LLVMGetUndef(ctx->i32);
4807
4808 if (count > 1)
4809 args->addr = ac_build_gather_values(ctx, param, count);
4810 else
4811 args->addr = param[0];
4812
4813 args->resource = res_ptr;
4814 args->sampler = samp_ptr;
4815
4816 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4817 args->addr = param[0];
4818 return;
4819 }
4820
4821 args->dmask = dmask;
4822 args->unorm = is_rect;
4823 args->da = da;
4824 }
4825
4826 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4827 *
4828 * SI-CI:
4829 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4830 * filtering manually. The driver sets img7 to a mask clearing
4831 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4832 * s_and_b32 samp0, samp0, img7
4833 *
4834 * VI:
4835 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4836 */
4837 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4838 LLVMValueRef res, LLVMValueRef samp)
4839 {
4840 LLVMBuilderRef builder = ctx->ac.builder;
4841 LLVMValueRef img7, samp0;
4842
4843 if (ctx->ac.chip_class >= VI)
4844 return samp;
4845
4846 img7 = LLVMBuildExtractElement(builder, res,
4847 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4848 samp0 = LLVMBuildExtractElement(builder, samp,
4849 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4850 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4851 return LLVMBuildInsertElement(builder, samp, samp0,
4852 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4853 }
4854
4855 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4856 nir_tex_instr *instr,
4857 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4858 LLVMValueRef *fmask_ptr)
4859 {
4860 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4861 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4862 else
4863 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4864 if (samp_ptr) {
4865 if (instr->sampler)
4866 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4867 else
4868 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4869 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4870 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4871 }
4872 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4873 instr->op == nir_texop_samples_identical))
4874 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4875 }
4876
4877 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4878 LLVMValueRef coord)
4879 {
4880 coord = ac_to_float(ctx, coord);
4881 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4882 coord = ac_to_integer(ctx, coord);
4883 return coord;
4884 }
4885
4886 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4887 {
4888 LLVMValueRef result = NULL;
4889 struct ac_image_args args = { 0 };
4890 unsigned dmask = 0xf;
4891 LLVMValueRef address[16];
4892 LLVMValueRef coords[5];
4893 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4894 LLVMValueRef bias = NULL, offsets = NULL;
4895 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4896 LLVMValueRef ddx = NULL, ddy = NULL;
4897 LLVMValueRef derivs[6];
4898 unsigned chan, count = 0;
4899 unsigned const_src = 0, num_deriv_comp = 0;
4900 bool lod_is_zero = false;
4901
4902 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4903
4904 for (unsigned i = 0; i < instr->num_srcs; i++) {
4905 switch (instr->src[i].src_type) {
4906 case nir_tex_src_coord:
4907 coord = get_src(ctx, instr->src[i].src);
4908 break;
4909 case nir_tex_src_projector:
4910 break;
4911 case nir_tex_src_comparator:
4912 comparator = get_src(ctx, instr->src[i].src);
4913 break;
4914 case nir_tex_src_offset:
4915 offsets = get_src(ctx, instr->src[i].src);
4916 const_src = i;
4917 break;
4918 case nir_tex_src_bias:
4919 bias = get_src(ctx, instr->src[i].src);
4920 break;
4921 case nir_tex_src_lod: {
4922 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4923
4924 if (val && val->i32[0] == 0)
4925 lod_is_zero = true;
4926 lod = get_src(ctx, instr->src[i].src);
4927 break;
4928 }
4929 case nir_tex_src_ms_index:
4930 sample_index = get_src(ctx, instr->src[i].src);
4931 break;
4932 case nir_tex_src_ms_mcs:
4933 break;
4934 case nir_tex_src_ddx:
4935 ddx = get_src(ctx, instr->src[i].src);
4936 num_deriv_comp = instr->src[i].src.ssa->num_components;
4937 break;
4938 case nir_tex_src_ddy:
4939 ddy = get_src(ctx, instr->src[i].src);
4940 break;
4941 case nir_tex_src_texture_offset:
4942 case nir_tex_src_sampler_offset:
4943 case nir_tex_src_plane:
4944 default:
4945 break;
4946 }
4947 }
4948
4949 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4950 result = get_buffer_size(ctx, res_ptr, true);
4951 goto write_result;
4952 }
4953
4954 if (instr->op == nir_texop_texture_samples) {
4955 LLVMValueRef res, samples, is_msaa;
4956 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4957 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4958 LLVMConstInt(ctx->ac.i32, 3, false), "");
4959 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4960 LLVMConstInt(ctx->ac.i32, 28, false), "");
4961 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4962 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4963 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4964 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4965
4966 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4967 LLVMConstInt(ctx->ac.i32, 16, false), "");
4968 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4969 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4970 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4971 samples, "");
4972 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4973 ctx->ac.i32_1, "");
4974 result = samples;
4975 goto write_result;
4976 }
4977
4978 if (coord)
4979 for (chan = 0; chan < instr->coord_components; chan++)
4980 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4981
4982 if (offsets && instr->op != nir_texop_txf) {
4983 LLVMValueRef offset[3], pack;
4984 for (chan = 0; chan < 3; ++chan)
4985 offset[chan] = ctx->ac.i32_0;
4986
4987 args.offset = true;
4988 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4989 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4990 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4991 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4992 if (chan)
4993 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4994 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4995 }
4996 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4997 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4998 address[count++] = pack;
4999
5000 }
5001 /* pack LOD bias value */
5002 if (instr->op == nir_texop_txb && bias) {
5003 address[count++] = bias;
5004 }
5005
5006 /* Pack depth comparison value */
5007 if (instr->is_shadow && comparator) {
5008 LLVMValueRef z = ac_to_float(&ctx->ac,
5009 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
5010
5011 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
5012 * so the depth comparison value isn't clamped for Z16 and
5013 * Z24 anymore. Do it manually here.
5014 *
5015 * It's unnecessary if the original texture format was
5016 * Z32_FLOAT, but we don't know that here.
5017 */
5018 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5019 z = ac_build_clamp(&ctx->ac, z);
5020
5021 address[count++] = z;
5022 }
5023
5024 /* pack derivatives */
5025 if (ddx || ddy) {
5026 int num_src_deriv_channels, num_dest_deriv_channels;
5027 switch (instr->sampler_dim) {
5028 case GLSL_SAMPLER_DIM_3D:
5029 case GLSL_SAMPLER_DIM_CUBE:
5030 num_deriv_comp = 3;
5031 num_src_deriv_channels = 3;
5032 num_dest_deriv_channels = 3;
5033 break;
5034 case GLSL_SAMPLER_DIM_2D:
5035 default:
5036 num_src_deriv_channels = 2;
5037 num_dest_deriv_channels = 2;
5038 num_deriv_comp = 2;
5039 break;
5040 case GLSL_SAMPLER_DIM_1D:
5041 num_src_deriv_channels = 1;
5042 if (ctx->ac.chip_class >= GFX9) {
5043 num_dest_deriv_channels = 2;
5044 num_deriv_comp = 2;
5045 } else {
5046 num_dest_deriv_channels = 1;
5047 num_deriv_comp = 1;
5048 }
5049 break;
5050 }
5051
5052 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5053 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5054 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5055 }
5056 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5057 derivs[i] = ctx->ac.f32_0;
5058 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5059 }
5060 }
5061
5062 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5063 for (chan = 0; chan < instr->coord_components; chan++)
5064 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5065 if (instr->coord_components == 3)
5066 coords[3] = LLVMGetUndef(ctx->ac.f32);
5067 ac_prepare_cube_coords(&ctx->ac,
5068 instr->op == nir_texop_txd, instr->is_array,
5069 instr->op == nir_texop_lod, coords, derivs);
5070 if (num_deriv_comp)
5071 num_deriv_comp--;
5072 }
5073
5074 if (ddx || ddy) {
5075 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5076 address[count++] = derivs[i];
5077 }
5078
5079 /* Pack texture coordinates */
5080 if (coord) {
5081 address[count++] = coords[0];
5082 if (instr->coord_components > 1) {
5083 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5084 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5085 }
5086 address[count++] = coords[1];
5087 }
5088 if (instr->coord_components > 2) {
5089 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5090 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
5091 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
5092 instr->op != nir_texop_txf) {
5093 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5094 }
5095 address[count++] = coords[2];
5096 }
5097
5098 if (ctx->ac.chip_class >= GFX9) {
5099 LLVMValueRef filler;
5100 if (instr->op == nir_texop_txf)
5101 filler = ctx->ac.i32_0;
5102 else
5103 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5104
5105 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5106 /* No nir_texop_lod, because it does not take a slice
5107 * even with array textures. */
5108 if (instr->is_array && instr->op != nir_texop_lod ) {
5109 address[count] = address[count - 1];
5110 address[count - 1] = filler;
5111 count++;
5112 } else
5113 address[count++] = filler;
5114 }
5115 }
5116 }
5117
5118 /* Pack LOD */
5119 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5120 instr->op == nir_texop_txf)) {
5121 address[count++] = lod;
5122 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5123 address[count++] = sample_index;
5124 } else if(instr->op == nir_texop_txs) {
5125 count = 0;
5126 if (lod)
5127 address[count++] = lod;
5128 else
5129 address[count++] = ctx->ac.i32_0;
5130 }
5131
5132 for (chan = 0; chan < count; chan++) {
5133 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5134 address[chan], ctx->ac.i32, "");
5135 }
5136
5137 if (instr->op == nir_texop_samples_identical) {
5138 LLVMValueRef txf_address[4];
5139 struct ac_image_args txf_args = { 0 };
5140 unsigned txf_count = count;
5141 memcpy(txf_address, address, sizeof(txf_address));
5142
5143 if (!instr->is_array)
5144 txf_address[2] = ctx->ac.i32_0;
5145 txf_address[3] = ctx->ac.i32_0;
5146
5147 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5148 fmask_ptr, NULL,
5149 txf_address, txf_count, 0xf);
5150
5151 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5152
5153 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5154 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5155 goto write_result;
5156 }
5157
5158 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5159 instr->op != nir_texop_txs) {
5160 unsigned sample_chan = instr->is_array ? 3 : 2;
5161 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5162 address[0],
5163 address[1],
5164 instr->is_array ? address[2] : NULL,
5165 address[sample_chan],
5166 fmask_ptr);
5167 }
5168
5169 if (offsets && instr->op == nir_texop_txf) {
5170 nir_const_value *const_offset =
5171 nir_src_as_const_value(instr->src[const_src].src);
5172 int num_offsets = instr->src[const_src].src.ssa->num_components;
5173 assert(const_offset);
5174 num_offsets = MIN2(num_offsets, instr->coord_components);
5175 if (num_offsets > 2)
5176 address[2] = LLVMBuildAdd(ctx->ac.builder,
5177 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5178 if (num_offsets > 1)
5179 address[1] = LLVMBuildAdd(ctx->ac.builder,
5180 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5181 address[0] = LLVMBuildAdd(ctx->ac.builder,
5182 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5183
5184 }
5185
5186 /* TODO TG4 support */
5187 if (instr->op == nir_texop_tg4) {
5188 if (instr->is_shadow)
5189 dmask = 1;
5190 else
5191 dmask = 1 << instr->component;
5192 }
5193 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5194 res_ptr, samp_ptr, address, count, dmask);
5195
5196 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5197
5198 if (instr->op == nir_texop_query_levels)
5199 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5200 else if (instr->is_shadow && instr->is_new_style_shadow &&
5201 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5202 instr->op != nir_texop_tg4)
5203 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5204 else if (instr->op == nir_texop_txs &&
5205 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5206 instr->is_array) {
5207 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5208 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5209 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5210 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5211 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5212 } else if (ctx->ac.chip_class >= GFX9 &&
5213 instr->op == nir_texop_txs &&
5214 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5215 instr->is_array) {
5216 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5217 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5218 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5219 ctx->ac.i32_1, "");
5220 } else if (instr->dest.ssa.num_components != 4)
5221 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5222
5223 write_result:
5224 if (result) {
5225 assert(instr->dest.is_ssa);
5226 result = ac_to_integer(&ctx->ac, result);
5227 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5228 }
5229 }
5230
5231
5232 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5233 {
5234 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5235 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5236
5237 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5238 _mesa_hash_table_insert(ctx->phis, instr, result);
5239 }
5240
5241 static void visit_post_phi(struct ac_nir_context *ctx,
5242 nir_phi_instr *instr,
5243 LLVMValueRef llvm_phi)
5244 {
5245 nir_foreach_phi_src(src, instr) {
5246 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5247 LLVMValueRef llvm_src = get_src(ctx, src->src);
5248
5249 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5250 }
5251 }
5252
5253 static void phi_post_pass(struct ac_nir_context *ctx)
5254 {
5255 struct hash_entry *entry;
5256 hash_table_foreach(ctx->phis, entry) {
5257 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5258 (LLVMValueRef)entry->data);
5259 }
5260 }
5261
5262
5263 static void visit_ssa_undef(struct ac_nir_context *ctx,
5264 const nir_ssa_undef_instr *instr)
5265 {
5266 unsigned num_components = instr->def.num_components;
5267 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5268 LLVMValueRef undef;
5269
5270 if (num_components == 1)
5271 undef = LLVMGetUndef(type);
5272 else {
5273 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5274 }
5275 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5276 }
5277
5278 static void visit_jump(struct ac_nir_context *ctx,
5279 const nir_jump_instr *instr)
5280 {
5281 switch (instr->type) {
5282 case nir_jump_break:
5283 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5284 LLVMClearInsertionPosition(ctx->ac.builder);
5285 break;
5286 case nir_jump_continue:
5287 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5288 LLVMClearInsertionPosition(ctx->ac.builder);
5289 break;
5290 default:
5291 fprintf(stderr, "Unknown NIR jump instr: ");
5292 nir_print_instr(&instr->instr, stderr);
5293 fprintf(stderr, "\n");
5294 abort();
5295 }
5296 }
5297
5298 static void visit_cf_list(struct ac_nir_context *ctx,
5299 struct exec_list *list);
5300
5301 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5302 {
5303 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5304 nir_foreach_instr(instr, block)
5305 {
5306 switch (instr->type) {
5307 case nir_instr_type_alu:
5308 visit_alu(ctx, nir_instr_as_alu(instr));
5309 break;
5310 case nir_instr_type_load_const:
5311 visit_load_const(ctx, nir_instr_as_load_const(instr));
5312 break;
5313 case nir_instr_type_intrinsic:
5314 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5315 break;
5316 case nir_instr_type_tex:
5317 visit_tex(ctx, nir_instr_as_tex(instr));
5318 break;
5319 case nir_instr_type_phi:
5320 visit_phi(ctx, nir_instr_as_phi(instr));
5321 break;
5322 case nir_instr_type_ssa_undef:
5323 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5324 break;
5325 case nir_instr_type_jump:
5326 visit_jump(ctx, nir_instr_as_jump(instr));
5327 break;
5328 default:
5329 fprintf(stderr, "Unknown NIR instr type: ");
5330 nir_print_instr(instr, stderr);
5331 fprintf(stderr, "\n");
5332 abort();
5333 }
5334 }
5335
5336 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5337 }
5338
5339 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5340 {
5341 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5342
5343 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5344 LLVMBasicBlockRef merge_block =
5345 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5346 LLVMBasicBlockRef if_block =
5347 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5348 LLVMBasicBlockRef else_block = merge_block;
5349 if (!exec_list_is_empty(&if_stmt->else_list))
5350 else_block = LLVMAppendBasicBlockInContext(
5351 ctx->ac.context, fn, "");
5352
5353 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5354 ctx->ac.i32_0, "");
5355 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5356
5357 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5358 visit_cf_list(ctx, &if_stmt->then_list);
5359 if (LLVMGetInsertBlock(ctx->ac.builder))
5360 LLVMBuildBr(ctx->ac.builder, merge_block);
5361
5362 if (!exec_list_is_empty(&if_stmt->else_list)) {
5363 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5364 visit_cf_list(ctx, &if_stmt->else_list);
5365 if (LLVMGetInsertBlock(ctx->ac.builder))
5366 LLVMBuildBr(ctx->ac.builder, merge_block);
5367 }
5368
5369 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5370 }
5371
5372 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5373 {
5374 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5375 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5376 LLVMBasicBlockRef break_parent = ctx->break_block;
5377
5378 ctx->continue_block =
5379 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5380 ctx->break_block =
5381 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5382
5383 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5384 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5385 visit_cf_list(ctx, &loop->body);
5386
5387 if (LLVMGetInsertBlock(ctx->ac.builder))
5388 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5389 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5390
5391 ctx->continue_block = continue_parent;
5392 ctx->break_block = break_parent;
5393 }
5394
5395 static void visit_cf_list(struct ac_nir_context *ctx,
5396 struct exec_list *list)
5397 {
5398 foreach_list_typed(nir_cf_node, node, node, list)
5399 {
5400 switch (node->type) {
5401 case nir_cf_node_block:
5402 visit_block(ctx, nir_cf_node_as_block(node));
5403 break;
5404
5405 case nir_cf_node_if:
5406 visit_if(ctx, nir_cf_node_as_if(node));
5407 break;
5408
5409 case nir_cf_node_loop:
5410 visit_loop(ctx, nir_cf_node_as_loop(node));
5411 break;
5412
5413 default:
5414 assert(0);
5415 }
5416 }
5417 }
5418
5419 static void
5420 handle_vs_input_decl(struct radv_shader_context *ctx,
5421 struct nir_variable *variable)
5422 {
5423 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5424 LLVMValueRef t_offset;
5425 LLVMValueRef t_list;
5426 LLVMValueRef input;
5427 LLVMValueRef buffer_index;
5428 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5429 int idx = variable->data.location;
5430 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5431 uint8_t input_usage_mask =
5432 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5433 unsigned num_channels = util_last_bit(input_usage_mask);
5434
5435 variable->data.driver_location = idx * 4;
5436
5437 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5438 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5439 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5440 ctx->abi.start_instance, "");
5441 if (ctx->options->key.vs.as_ls) {
5442 ctx->shader_info->vs.vgpr_comp_cnt =
5443 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5444 } else {
5445 ctx->shader_info->vs.vgpr_comp_cnt =
5446 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5447 }
5448 } else
5449 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5450 ctx->abi.base_vertex, "");
5451 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5452
5453 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5454
5455 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5456 buffer_index,
5457 ctx->ac.i32_0,
5458 num_channels, false, true);
5459
5460 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5461
5462 for (unsigned chan = 0; chan < 4; chan++) {
5463 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5464 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5465 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5466 input, llvm_chan, ""));
5467 }
5468 }
5469 }
5470
5471 static void interp_fs_input(struct radv_shader_context *ctx,
5472 unsigned attr,
5473 LLVMValueRef interp_param,
5474 LLVMValueRef prim_mask,
5475 LLVMValueRef result[4])
5476 {
5477 LLVMValueRef attr_number;
5478 unsigned chan;
5479 LLVMValueRef i, j;
5480 bool interp = interp_param != NULL;
5481
5482 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5483
5484 /* fs.constant returns the param from the middle vertex, so it's not
5485 * really useful for flat shading. It's meant to be used for custom
5486 * interpolation (but the intrinsic can't fetch from the other two
5487 * vertices).
5488 *
5489 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5490 * to do the right thing. The only reason we use fs.constant is that
5491 * fs.interp cannot be used on integers, because they can be equal
5492 * to NaN.
5493 */
5494 if (interp) {
5495 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5496 ctx->ac.v2f32, "");
5497
5498 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5499 ctx->ac.i32_0, "");
5500 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5501 ctx->ac.i32_1, "");
5502 }
5503
5504 for (chan = 0; chan < 4; chan++) {
5505 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5506
5507 if (interp) {
5508 result[chan] = ac_build_fs_interp(&ctx->ac,
5509 llvm_chan,
5510 attr_number,
5511 prim_mask, i, j);
5512 } else {
5513 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5514 LLVMConstInt(ctx->ac.i32, 2, false),
5515 llvm_chan,
5516 attr_number,
5517 prim_mask);
5518 }
5519 }
5520 }
5521
5522 static void
5523 handle_fs_input_decl(struct radv_shader_context *ctx,
5524 struct nir_variable *variable)
5525 {
5526 int idx = variable->data.location;
5527 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5528 LLVMValueRef interp;
5529
5530 variable->data.driver_location = idx * 4;
5531 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5532
5533 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5534 unsigned interp_type;
5535 if (variable->data.sample)
5536 interp_type = INTERP_SAMPLE;
5537 else if (variable->data.centroid)
5538 interp_type = INTERP_CENTROID;
5539 else
5540 interp_type = INTERP_CENTER;
5541
5542 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5543 } else
5544 interp = NULL;
5545
5546 for (unsigned i = 0; i < attrib_count; ++i)
5547 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5548
5549 }
5550
5551 static void
5552 handle_vs_inputs(struct radv_shader_context *ctx,
5553 struct nir_shader *nir) {
5554 nir_foreach_variable(variable, &nir->inputs)
5555 handle_vs_input_decl(ctx, variable);
5556 }
5557
5558 static void
5559 prepare_interp_optimize(struct radv_shader_context *ctx,
5560 struct nir_shader *nir)
5561 {
5562 if (!ctx->options->key.fs.multisample)
5563 return;
5564
5565 bool uses_center = false;
5566 bool uses_centroid = false;
5567 nir_foreach_variable(variable, &nir->inputs) {
5568 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5569 variable->data.sample)
5570 continue;
5571
5572 if (variable->data.centroid)
5573 uses_centroid = true;
5574 else
5575 uses_center = true;
5576 }
5577
5578 if (uses_center && uses_centroid) {
5579 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5580 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5581 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5582 }
5583 }
5584
5585 static void
5586 handle_fs_inputs(struct radv_shader_context *ctx,
5587 struct nir_shader *nir)
5588 {
5589 prepare_interp_optimize(ctx, nir);
5590
5591 nir_foreach_variable(variable, &nir->inputs)
5592 handle_fs_input_decl(ctx, variable);
5593
5594 unsigned index = 0;
5595
5596 if (ctx->shader_info->info.ps.uses_input_attachments ||
5597 ctx->shader_info->info.needs_multiview_view_index)
5598 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5599
5600 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5601 LLVMValueRef interp_param;
5602 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5603
5604 if (!(ctx->input_mask & (1ull << i)))
5605 continue;
5606
5607 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5608 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5609 interp_param = *inputs;
5610 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5611 inputs);
5612
5613 if (!interp_param)
5614 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5615 ++index;
5616 } else if (i == VARYING_SLOT_POS) {
5617 for(int i = 0; i < 3; ++i)
5618 inputs[i] = ctx->abi.frag_pos[i];
5619
5620 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5621 ctx->abi.frag_pos[3]);
5622 }
5623 }
5624 ctx->shader_info->fs.num_interp = index;
5625 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5626 ctx->shader_info->fs.has_pcoord = true;
5627 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5628 ctx->shader_info->fs.prim_id_input = true;
5629 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5630 ctx->shader_info->fs.layer_input = true;
5631 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5632
5633 if (ctx->shader_info->info.needs_multiview_view_index)
5634 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5635 }
5636
5637 static LLVMValueRef
5638 ac_build_alloca(struct ac_llvm_context *ac,
5639 LLVMTypeRef type,
5640 const char *name)
5641 {
5642 LLVMBuilderRef builder = ac->builder;
5643 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5644 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5645 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5646 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5647 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5648 LLVMValueRef res;
5649
5650 if (first_instr) {
5651 LLVMPositionBuilderBefore(first_builder, first_instr);
5652 } else {
5653 LLVMPositionBuilderAtEnd(first_builder, first_block);
5654 }
5655
5656 res = LLVMBuildAlloca(first_builder, type, name);
5657 LLVMBuildStore(builder, LLVMConstNull(type), res);
5658
5659 LLVMDisposeBuilder(first_builder);
5660
5661 return res;
5662 }
5663
5664 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5665 LLVMTypeRef type,
5666 const char *name)
5667 {
5668 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5669 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5670 return ptr;
5671 }
5672
5673 static void
5674 scan_shader_output_decl(struct radv_shader_context *ctx,
5675 struct nir_variable *variable,
5676 struct nir_shader *shader,
5677 gl_shader_stage stage)
5678 {
5679 int idx = variable->data.location + variable->data.index;
5680 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5681 uint64_t mask_attribs;
5682
5683 variable->data.driver_location = idx * 4;
5684
5685 /* tess ctrl has it's own load/store paths for outputs */
5686 if (stage == MESA_SHADER_TESS_CTRL)
5687 return;
5688
5689 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5690 if (stage == MESA_SHADER_VERTEX ||
5691 stage == MESA_SHADER_TESS_EVAL ||
5692 stage == MESA_SHADER_GEOMETRY) {
5693 if (idx == VARYING_SLOT_CLIP_DIST0) {
5694 int length = shader->info.clip_distance_array_size +
5695 shader->info.cull_distance_array_size;
5696 if (stage == MESA_SHADER_VERTEX) {
5697 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5698 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5699 }
5700 if (stage == MESA_SHADER_TESS_EVAL) {
5701 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5702 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5703 }
5704
5705 if (length > 4)
5706 attrib_count = 2;
5707 else
5708 attrib_count = 1;
5709 mask_attribs = 1ull << idx;
5710 }
5711 }
5712
5713 ctx->output_mask |= mask_attribs;
5714 }
5715
5716 static void
5717 handle_shader_output_decl(struct ac_nir_context *ctx,
5718 struct nir_shader *nir,
5719 struct nir_variable *variable)
5720 {
5721 unsigned output_loc = variable->data.driver_location / 4;
5722 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5723
5724 /* tess ctrl has it's own load/store paths for outputs */
5725 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5726 return;
5727
5728 if (ctx->stage == MESA_SHADER_VERTEX ||
5729 ctx->stage == MESA_SHADER_TESS_EVAL ||
5730 ctx->stage == MESA_SHADER_GEOMETRY) {
5731 int idx = variable->data.location + variable->data.index;
5732 if (idx == VARYING_SLOT_CLIP_DIST0) {
5733 int length = nir->info.clip_distance_array_size +
5734 nir->info.cull_distance_array_size;
5735
5736 if (length > 4)
5737 attrib_count = 2;
5738 else
5739 attrib_count = 1;
5740 }
5741 }
5742
5743 for (unsigned i = 0; i < attrib_count; ++i) {
5744 for (unsigned chan = 0; chan < 4; chan++) {
5745 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5746 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5747 }
5748 }
5749 }
5750
5751 static LLVMTypeRef
5752 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5753 enum glsl_base_type type)
5754 {
5755 switch (type) {
5756 case GLSL_TYPE_INT:
5757 case GLSL_TYPE_UINT:
5758 case GLSL_TYPE_BOOL:
5759 case GLSL_TYPE_SUBROUTINE:
5760 return ac->i32;
5761 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5762 return ac->f32;
5763 case GLSL_TYPE_INT64:
5764 case GLSL_TYPE_UINT64:
5765 return ac->i64;
5766 case GLSL_TYPE_DOUBLE:
5767 return ac->f64;
5768 default:
5769 unreachable("unknown GLSL type");
5770 }
5771 }
5772
5773 static LLVMTypeRef
5774 glsl_to_llvm_type(struct ac_llvm_context *ac,
5775 const struct glsl_type *type)
5776 {
5777 if (glsl_type_is_scalar(type)) {
5778 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5779 }
5780
5781 if (glsl_type_is_vector(type)) {
5782 return LLVMVectorType(
5783 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5784 glsl_get_vector_elements(type));
5785 }
5786
5787 if (glsl_type_is_matrix(type)) {
5788 return LLVMArrayType(
5789 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5790 glsl_get_matrix_columns(type));
5791 }
5792
5793 if (glsl_type_is_array(type)) {
5794 return LLVMArrayType(
5795 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5796 glsl_get_length(type));
5797 }
5798
5799 assert(glsl_type_is_struct(type));
5800
5801 LLVMTypeRef member_types[glsl_get_length(type)];
5802
5803 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5804 member_types[i] =
5805 glsl_to_llvm_type(ac,
5806 glsl_get_struct_field(type, i));
5807 }
5808
5809 return LLVMStructTypeInContext(ac->context, member_types,
5810 glsl_get_length(type), false);
5811 }
5812
5813 static void
5814 setup_locals(struct ac_nir_context *ctx,
5815 struct nir_function *func)
5816 {
5817 int i, j;
5818 ctx->num_locals = 0;
5819 nir_foreach_variable(variable, &func->impl->locals) {
5820 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5821 variable->data.driver_location = ctx->num_locals * 4;
5822 variable->data.location_frac = 0;
5823 ctx->num_locals += attrib_count;
5824 }
5825 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5826 if (!ctx->locals)
5827 return;
5828
5829 for (i = 0; i < ctx->num_locals; i++) {
5830 for (j = 0; j < 4; j++) {
5831 ctx->locals[i * 4 + j] =
5832 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5833 }
5834 }
5835 }
5836
5837 static void
5838 setup_shared(struct ac_nir_context *ctx,
5839 struct nir_shader *nir)
5840 {
5841 nir_foreach_variable(variable, &nir->shared) {
5842 LLVMValueRef shared =
5843 LLVMAddGlobalInAddressSpace(
5844 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5845 variable->name ? variable->name : "",
5846 AC_LOCAL_ADDR_SPACE);
5847 _mesa_hash_table_insert(ctx->vars, variable, shared);
5848 }
5849 }
5850
5851 /* Initialize arguments for the shader export intrinsic */
5852 static void
5853 si_llvm_init_export_args(struct radv_shader_context *ctx,
5854 LLVMValueRef *values,
5855 unsigned target,
5856 struct ac_export_args *args)
5857 {
5858 /* Default is 0xf. Adjusted below depending on the format. */
5859 args->enabled_channels = 0xf;
5860
5861 /* Specify whether the EXEC mask represents the valid mask */
5862 args->valid_mask = 0;
5863
5864 /* Specify whether this is the last export */
5865 args->done = 0;
5866
5867 /* Specify the target we are exporting */
5868 args->target = target;
5869
5870 args->compr = false;
5871 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5872 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5873 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5874 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5875
5876 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5877 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5878 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5879 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5880 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5881 unsigned chan;
5882
5883 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5884 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5885 unsigned bits, bool hi) = NULL;
5886
5887 switch(col_format) {
5888 case V_028714_SPI_SHADER_ZERO:
5889 args->enabled_channels = 0; /* writemask */
5890 args->target = V_008DFC_SQ_EXP_NULL;
5891 break;
5892
5893 case V_028714_SPI_SHADER_32_R:
5894 args->enabled_channels = 1;
5895 args->out[0] = values[0];
5896 break;
5897
5898 case V_028714_SPI_SHADER_32_GR:
5899 args->enabled_channels = 0x3;
5900 args->out[0] = values[0];
5901 args->out[1] = values[1];
5902 break;
5903
5904 case V_028714_SPI_SHADER_32_AR:
5905 args->enabled_channels = 0x9;
5906 args->out[0] = values[0];
5907 args->out[3] = values[3];
5908 break;
5909
5910 case V_028714_SPI_SHADER_FP16_ABGR:
5911 packf = ac_build_cvt_pkrtz_f16;
5912 break;
5913
5914 case V_028714_SPI_SHADER_UNORM16_ABGR:
5915 packf = ac_build_cvt_pknorm_u16;
5916 break;
5917
5918 case V_028714_SPI_SHADER_SNORM16_ABGR:
5919 packf = ac_build_cvt_pknorm_i16;
5920 break;
5921
5922 case V_028714_SPI_SHADER_UINT16_ABGR:
5923 packi = ac_build_cvt_pk_u16;
5924 break;
5925
5926 case V_028714_SPI_SHADER_SINT16_ABGR:
5927 packi = ac_build_cvt_pk_i16;
5928 break;
5929
5930 default:
5931 case V_028714_SPI_SHADER_32_ABGR:
5932 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5933 break;
5934 }
5935
5936 /* Pack f16 or norm_i16/u16. */
5937 if (packf) {
5938 for (chan = 0; chan < 2; chan++) {
5939 LLVMValueRef pack_args[2] = {
5940 values[2 * chan],
5941 values[2 * chan + 1]
5942 };
5943 LLVMValueRef packed;
5944
5945 packed = packf(&ctx->ac, pack_args);
5946 args->out[chan] = ac_to_float(&ctx->ac, packed);
5947 }
5948 args->compr = 1; /* COMPR flag */
5949 }
5950
5951 /* Pack i16/u16. */
5952 if (packi) {
5953 for (chan = 0; chan < 2; chan++) {
5954 LLVMValueRef pack_args[2] = {
5955 ac_to_integer(&ctx->ac, values[2 * chan]),
5956 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5957 };
5958 LLVMValueRef packed;
5959
5960 packed = packi(&ctx->ac, pack_args,
5961 is_int8 ? 8 : is_int10 ? 10 : 16,
5962 chan == 1);
5963 args->out[chan] = ac_to_float(&ctx->ac, packed);
5964 }
5965 args->compr = 1; /* COMPR flag */
5966 }
5967 return;
5968 }
5969
5970 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5971
5972 for (unsigned i = 0; i < 4; ++i)
5973 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5974 }
5975
5976 static void
5977 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5978 LLVMValueRef *values)
5979 {
5980 struct ac_export_args args;
5981
5982 si_llvm_init_export_args(ctx, values,
5983 V_008DFC_SQ_EXP_PARAM + index, &args);
5984 ac_build_export(&ctx->ac, &args);
5985 }
5986
5987 static LLVMValueRef
5988 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5989 {
5990 LLVMValueRef output =
5991 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5992
5993 return LLVMBuildLoad(ctx->ac.builder, output, "");
5994 }
5995
5996 static void
5997 handle_vs_outputs_post(struct radv_shader_context *ctx,
5998 bool export_prim_id,
5999 struct ac_vs_output_info *outinfo)
6000 {
6001 uint32_t param_count = 0;
6002 unsigned target;
6003 unsigned pos_idx, num_pos_exports = 0;
6004 struct ac_export_args args, pos_args[4] = {};
6005 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
6006 int i;
6007
6008 if (ctx->options->key.has_multiview_view_index) {
6009 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
6010 if(!*tmp_out) {
6011 for(unsigned i = 0; i < 4; ++i)
6012 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
6013 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
6014 }
6015
6016 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
6017 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
6018 }
6019
6020 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6021 sizeof(outinfo->vs_output_param_offset));
6022
6023 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
6024 LLVMValueRef slots[8];
6025 unsigned j;
6026
6027 if (outinfo->cull_dist_mask)
6028 outinfo->cull_dist_mask <<= ctx->num_output_clips;
6029
6030 i = VARYING_SLOT_CLIP_DIST0;
6031 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
6032 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6033
6034 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
6035 slots[i] = LLVMGetUndef(ctx->ac.f32);
6036
6037 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
6038 target = V_008DFC_SQ_EXP_POS + 3;
6039 si_llvm_init_export_args(ctx, &slots[4], target, &args);
6040 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6041 &args, sizeof(args));
6042 }
6043
6044 target = V_008DFC_SQ_EXP_POS + 2;
6045 si_llvm_init_export_args(ctx, &slots[0], target, &args);
6046 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6047 &args, sizeof(args));
6048
6049 }
6050
6051 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6052 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6053 for (unsigned j = 0; j < 4; j++)
6054 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6055 }
6056 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6057
6058 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6059 outinfo->writes_pointsize = true;
6060 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6061 }
6062
6063 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6064 outinfo->writes_layer = true;
6065 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6066 }
6067
6068 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6069 outinfo->writes_viewport_index = true;
6070 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6071 }
6072
6073 if (outinfo->writes_pointsize ||
6074 outinfo->writes_layer ||
6075 outinfo->writes_viewport_index) {
6076 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6077 (outinfo->writes_layer == true ? 4 : 0));
6078 pos_args[1].valid_mask = 0;
6079 pos_args[1].done = 0;
6080 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6081 pos_args[1].compr = 0;
6082 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6083 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6084 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6085 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6086
6087 if (outinfo->writes_pointsize == true)
6088 pos_args[1].out[0] = psize_value;
6089 if (outinfo->writes_layer == true)
6090 pos_args[1].out[2] = layer_value;
6091 if (outinfo->writes_viewport_index == true) {
6092 if (ctx->options->chip_class >= GFX9) {
6093 /* GFX9 has the layer in out.z[10:0] and the viewport
6094 * index in out.z[19:16].
6095 */
6096 LLVMValueRef v = viewport_index_value;
6097 v = ac_to_integer(&ctx->ac, v);
6098 v = LLVMBuildShl(ctx->ac.builder, v,
6099 LLVMConstInt(ctx->ac.i32, 16, false),
6100 "");
6101 v = LLVMBuildOr(ctx->ac.builder, v,
6102 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6103
6104 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6105 pos_args[1].enabled_channels |= 1 << 2;
6106 } else {
6107 pos_args[1].out[3] = viewport_index_value;
6108 pos_args[1].enabled_channels |= 1 << 3;
6109 }
6110 }
6111 }
6112 for (i = 0; i < 4; i++) {
6113 if (pos_args[i].out[0])
6114 num_pos_exports++;
6115 }
6116
6117 pos_idx = 0;
6118 for (i = 0; i < 4; i++) {
6119 if (!pos_args[i].out[0])
6120 continue;
6121
6122 /* Specify the target we are exporting */
6123 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6124 if (pos_idx == num_pos_exports)
6125 pos_args[i].done = 1;
6126 ac_build_export(&ctx->ac, &pos_args[i]);
6127 }
6128
6129 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6130 LLVMValueRef values[4];
6131 if (!(ctx->output_mask & (1ull << i)))
6132 continue;
6133
6134 if (i != VARYING_SLOT_LAYER &&
6135 i != VARYING_SLOT_PRIMITIVE_ID &&
6136 i < VARYING_SLOT_VAR0)
6137 continue;
6138
6139 for (unsigned j = 0; j < 4; j++)
6140 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6141
6142 radv_export_param(ctx, param_count, values);
6143
6144 outinfo->vs_output_param_offset[i] = param_count++;
6145 }
6146
6147 if (export_prim_id) {
6148 LLVMValueRef values[4];
6149
6150 values[0] = ctx->vs_prim_id;
6151 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6152 ctx->shader_info->vs.vgpr_comp_cnt);
6153 for (unsigned j = 1; j < 4; j++)
6154 values[j] = ctx->ac.f32_0;
6155
6156 radv_export_param(ctx, param_count, values);
6157
6158 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6159 outinfo->export_prim_id = true;
6160 }
6161
6162 outinfo->pos_exports = num_pos_exports;
6163 outinfo->param_exports = param_count;
6164 }
6165
6166 static void
6167 handle_es_outputs_post(struct radv_shader_context *ctx,
6168 struct ac_es_output_info *outinfo)
6169 {
6170 int j;
6171 uint64_t max_output_written = 0;
6172 LLVMValueRef lds_base = NULL;
6173
6174 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6175 int param_index;
6176 int length = 4;
6177
6178 if (!(ctx->output_mask & (1ull << i)))
6179 continue;
6180
6181 if (i == VARYING_SLOT_CLIP_DIST0)
6182 length = ctx->num_output_clips + ctx->num_output_culls;
6183
6184 param_index = shader_io_get_unique_index(i);
6185
6186 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6187 }
6188
6189 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6190
6191 if (ctx->ac.chip_class >= GFX9) {
6192 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6193 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6194 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6195 LLVMConstInt(ctx->ac.i32, 24, false),
6196 LLVMConstInt(ctx->ac.i32, 4, false), false);
6197 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6198 LLVMBuildMul(ctx->ac.builder, wave_idx,
6199 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6200 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6201 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6202 }
6203
6204 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6205 LLVMValueRef dw_addr = NULL;
6206 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6207 int param_index;
6208 int length = 4;
6209
6210 if (!(ctx->output_mask & (1ull << i)))
6211 continue;
6212
6213 if (i == VARYING_SLOT_CLIP_DIST0)
6214 length = ctx->num_output_clips + ctx->num_output_culls;
6215
6216 param_index = shader_io_get_unique_index(i);
6217
6218 if (lds_base) {
6219 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6220 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6221 "");
6222 }
6223 for (j = 0; j < length; j++) {
6224 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6225 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6226
6227 if (ctx->ac.chip_class >= GFX9) {
6228 ac_lds_store(&ctx->ac, dw_addr,
6229 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6230 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6231 } else {
6232 ac_build_buffer_store_dword(&ctx->ac,
6233 ctx->esgs_ring,
6234 out_val, 1,
6235 NULL, ctx->es2gs_offset,
6236 (4 * param_index + j) * 4,
6237 1, 1, true, true);
6238 }
6239 }
6240 }
6241 }
6242
6243 static void
6244 handle_ls_outputs_post(struct radv_shader_context *ctx)
6245 {
6246 LLVMValueRef vertex_id = ctx->rel_auto_id;
6247 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6248 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6249 vertex_dw_stride, "");
6250
6251 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6252 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6253 int length = 4;
6254
6255 if (!(ctx->output_mask & (1ull << i)))
6256 continue;
6257
6258 if (i == VARYING_SLOT_CLIP_DIST0)
6259 length = ctx->num_output_clips + ctx->num_output_culls;
6260 int param = shader_io_get_unique_index(i);
6261 mark_tess_output(ctx, false, param);
6262 if (length > 4)
6263 mark_tess_output(ctx, false, param + 1);
6264 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6265 LLVMConstInt(ctx->ac.i32, param * 4, false),
6266 "");
6267 for (unsigned j = 0; j < length; j++) {
6268 ac_lds_store(&ctx->ac, dw_addr,
6269 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6270 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6271 }
6272 }
6273 }
6274
6275 struct ac_build_if_state
6276 {
6277 struct radv_shader_context *ctx;
6278 LLVMValueRef condition;
6279 LLVMBasicBlockRef entry_block;
6280 LLVMBasicBlockRef true_block;
6281 LLVMBasicBlockRef false_block;
6282 LLVMBasicBlockRef merge_block;
6283 };
6284
6285 static LLVMBasicBlockRef
6286 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6287 {
6288 LLVMBasicBlockRef current_block;
6289 LLVMBasicBlockRef next_block;
6290 LLVMBasicBlockRef new_block;
6291
6292 /* get current basic block */
6293 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6294
6295 /* chqeck if there's another block after this one */
6296 next_block = LLVMGetNextBasicBlock(current_block);
6297 if (next_block) {
6298 /* insert the new block before the next block */
6299 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6300 }
6301 else {
6302 /* append new block after current block */
6303 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6304 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6305 }
6306 return new_block;
6307 }
6308
6309 static void
6310 ac_nir_build_if(struct ac_build_if_state *ifthen,
6311 struct radv_shader_context *ctx,
6312 LLVMValueRef condition)
6313 {
6314 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6315
6316 memset(ifthen, 0, sizeof *ifthen);
6317 ifthen->ctx = ctx;
6318 ifthen->condition = condition;
6319 ifthen->entry_block = block;
6320
6321 /* create endif/merge basic block for the phi functions */
6322 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6323
6324 /* create/insert true_block before merge_block */
6325 ifthen->true_block =
6326 LLVMInsertBasicBlockInContext(ctx->context,
6327 ifthen->merge_block,
6328 "if-true-block");
6329
6330 /* successive code goes into the true block */
6331 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6332 }
6333
6334 /**
6335 * End a conditional.
6336 */
6337 static void
6338 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6339 {
6340 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6341
6342 /* Insert branch to the merge block from current block */
6343 LLVMBuildBr(builder, ifthen->merge_block);
6344
6345 /*
6346 * Now patch in the various branch instructions.
6347 */
6348
6349 /* Insert the conditional branch instruction at the end of entry_block */
6350 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6351 if (ifthen->false_block) {
6352 /* we have an else clause */
6353 LLVMBuildCondBr(builder, ifthen->condition,
6354 ifthen->true_block, ifthen->false_block);
6355 }
6356 else {
6357 /* no else clause */
6358 LLVMBuildCondBr(builder, ifthen->condition,
6359 ifthen->true_block, ifthen->merge_block);
6360 }
6361
6362 /* Resume building code at end of the ifthen->merge_block */
6363 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6364 }
6365
6366 static void
6367 write_tess_factors(struct radv_shader_context *ctx)
6368 {
6369 unsigned stride, outer_comps, inner_comps;
6370 struct ac_build_if_state if_ctx, inner_if_ctx;
6371 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6372 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6373 unsigned tess_inner_index = 0, tess_outer_index;
6374 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
6375 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6376 int i;
6377 emit_barrier(&ctx->ac, ctx->stage);
6378
6379 switch (ctx->options->key.tcs.primitive_mode) {
6380 case GL_ISOLINES:
6381 stride = 2;
6382 outer_comps = 2;
6383 inner_comps = 0;
6384 break;
6385 case GL_TRIANGLES:
6386 stride = 4;
6387 outer_comps = 3;
6388 inner_comps = 1;
6389 break;
6390 case GL_QUADS:
6391 stride = 6;
6392 outer_comps = 4;
6393 inner_comps = 2;
6394 break;
6395 default:
6396 return;
6397 }
6398
6399 ac_nir_build_if(&if_ctx, ctx,
6400 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6401 invocation_id, ctx->ac.i32_0, ""));
6402
6403 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6404
6405 if (inner_comps) {
6406 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6407 mark_tess_output(ctx, true, tess_inner_index);
6408 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6409 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6410 }
6411
6412 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6413 mark_tess_output(ctx, true, tess_outer_index);
6414 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6415 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6416
6417 for (i = 0; i < 4; i++) {
6418 inner[i] = LLVMGetUndef(ctx->ac.i32);
6419 outer[i] = LLVMGetUndef(ctx->ac.i32);
6420 }
6421
6422 // LINES reverseal
6423 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6424 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6425 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6426 ctx->ac.i32_1, "");
6427 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6428 } else {
6429 for (i = 0; i < outer_comps; i++) {
6430 outer[i] = out[i] =
6431 ac_lds_load(&ctx->ac, lds_outer);
6432 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6433 ctx->ac.i32_1, "");
6434 }
6435 for (i = 0; i < inner_comps; i++) {
6436 inner[i] = out[outer_comps+i] =
6437 ac_lds_load(&ctx->ac, lds_inner);
6438 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6439 ctx->ac.i32_1, "");
6440 }
6441 }
6442
6443 /* Convert the outputs to vectors for stores. */
6444 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6445 vec1 = NULL;
6446
6447 if (stride > 4)
6448 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6449
6450
6451 buffer = ctx->hs_ring_tess_factor;
6452 tf_base = ctx->tess_factor_offset;
6453 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6454 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6455 unsigned tf_offset = 0;
6456
6457 if (ctx->options->chip_class <= VI) {
6458 ac_nir_build_if(&inner_if_ctx, ctx,
6459 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6460 rel_patch_id, ctx->ac.i32_0, ""));
6461
6462 /* Store the dynamic HS control word. */
6463 ac_build_buffer_store_dword(&ctx->ac, buffer,
6464 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6465 1, ctx->ac.i32_0, tf_base,
6466 0, 1, 0, true, false);
6467 tf_offset += 4;
6468
6469 ac_nir_build_endif(&inner_if_ctx);
6470 }
6471
6472 /* Store the tessellation factors. */
6473 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6474 MIN2(stride, 4), byteoffset, tf_base,
6475 tf_offset, 1, 0, true, false);
6476 if (vec1)
6477 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6478 stride - 4, byteoffset, tf_base,
6479 16 + tf_offset, 1, 0, true, false);
6480
6481 //store to offchip for TES to read - only if TES reads them
6482 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6483 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6484 LLVMValueRef tf_inner_offset;
6485 unsigned param_outer, param_inner;
6486
6487 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6488 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6489 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6490
6491 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6492 util_next_power_of_two(outer_comps));
6493
6494 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6495 outer_comps, tf_outer_offset,
6496 ctx->oc_lds, 0, 1, 0, true, false);
6497 if (inner_comps) {
6498 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6499 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6500 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6501
6502 inner_vec = inner_comps == 1 ? inner[0] :
6503 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6504 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6505 inner_comps, tf_inner_offset,
6506 ctx->oc_lds, 0, 1, 0, true, false);
6507 }
6508 }
6509 ac_nir_build_endif(&if_ctx);
6510 }
6511
6512 static void
6513 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6514 {
6515 write_tess_factors(ctx);
6516 }
6517
6518 static bool
6519 si_export_mrt_color(struct radv_shader_context *ctx,
6520 LLVMValueRef *color, unsigned index, bool is_last,
6521 struct ac_export_args *args)
6522 {
6523 /* Export */
6524 si_llvm_init_export_args(ctx, color,
6525 V_008DFC_SQ_EXP_MRT + index, args);
6526
6527 if (is_last) {
6528 args->valid_mask = 1; /* whether the EXEC mask is valid */
6529 args->done = 1; /* DONE bit */
6530 } else if (!args->enabled_channels)
6531 return false; /* unnecessary NULL export */
6532
6533 return true;
6534 }
6535
6536 static void
6537 radv_export_mrt_z(struct radv_shader_context *ctx,
6538 LLVMValueRef depth, LLVMValueRef stencil,
6539 LLVMValueRef samplemask)
6540 {
6541 struct ac_export_args args;
6542
6543 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6544
6545 ac_build_export(&ctx->ac, &args);
6546 }
6547
6548 static void
6549 handle_fs_outputs_post(struct radv_shader_context *ctx)
6550 {
6551 unsigned index = 0;
6552 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6553 struct ac_export_args color_args[8];
6554
6555 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6556 LLVMValueRef values[4];
6557 bool last = false;
6558
6559 if (!(ctx->output_mask & (1ull << i)))
6560 continue;
6561
6562 if (i < FRAG_RESULT_DATA0)
6563 continue;
6564
6565 for (unsigned j = 0; j < 4; j++)
6566 values[j] = ac_to_float(&ctx->ac,
6567 radv_load_output(ctx, i, j));
6568
6569 if (!ctx->shader_info->info.ps.writes_z &&
6570 !ctx->shader_info->info.ps.writes_stencil &&
6571 !ctx->shader_info->info.ps.writes_sample_mask)
6572 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6573
6574 bool ret = si_export_mrt_color(ctx, values,
6575 i - FRAG_RESULT_DATA0,
6576 last, &color_args[index]);
6577 if (ret)
6578 index++;
6579 }
6580
6581 /* Process depth, stencil, samplemask. */
6582 if (ctx->shader_info->info.ps.writes_z) {
6583 depth = ac_to_float(&ctx->ac,
6584 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6585 }
6586 if (ctx->shader_info->info.ps.writes_stencil) {
6587 stencil = ac_to_float(&ctx->ac,
6588 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6589 }
6590 if (ctx->shader_info->info.ps.writes_sample_mask) {
6591 samplemask = ac_to_float(&ctx->ac,
6592 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6593 }
6594
6595 /* Export PS outputs. */
6596 for (unsigned i = 0; i < index; i++)
6597 ac_build_export(&ctx->ac, &color_args[i]);
6598
6599 if (depth || stencil || samplemask)
6600 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6601 else if (!index)
6602 ac_build_export_null(&ctx->ac);
6603 }
6604
6605 static void
6606 emit_gs_epilogue(struct radv_shader_context *ctx)
6607 {
6608 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6609 }
6610
6611 static void
6612 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6613 LLVMValueRef *addrs)
6614 {
6615 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6616
6617 switch (ctx->stage) {
6618 case MESA_SHADER_VERTEX:
6619 if (ctx->options->key.vs.as_ls)
6620 handle_ls_outputs_post(ctx);
6621 else if (ctx->options->key.vs.as_es)
6622 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6623 else
6624 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6625 &ctx->shader_info->vs.outinfo);
6626 break;
6627 case MESA_SHADER_FRAGMENT:
6628 handle_fs_outputs_post(ctx);
6629 break;
6630 case MESA_SHADER_GEOMETRY:
6631 emit_gs_epilogue(ctx);
6632 break;
6633 case MESA_SHADER_TESS_CTRL:
6634 handle_tcs_outputs_post(ctx);
6635 break;
6636 case MESA_SHADER_TESS_EVAL:
6637 if (ctx->options->key.tes.as_es)
6638 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6639 else
6640 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6641 &ctx->shader_info->tes.outinfo);
6642 break;
6643 default:
6644 break;
6645 }
6646 }
6647
6648 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6649 {
6650 LLVMPassManagerRef passmgr;
6651 /* Create the pass manager */
6652 passmgr = LLVMCreateFunctionPassManagerForModule(
6653 ctx->ac.module);
6654
6655 /* This pass should eliminate all the load and store instructions */
6656 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6657
6658 /* Add some optimization passes */
6659 LLVMAddScalarReplAggregatesPass(passmgr);
6660 LLVMAddLICMPass(passmgr);
6661 LLVMAddAggressiveDCEPass(passmgr);
6662 LLVMAddCFGSimplificationPass(passmgr);
6663 LLVMAddInstructionCombiningPass(passmgr);
6664
6665 /* Run the pass */
6666 LLVMInitializeFunctionPassManager(passmgr);
6667 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6668 LLVMFinalizeFunctionPassManager(passmgr);
6669
6670 LLVMDisposeBuilder(ctx->ac.builder);
6671 LLVMDisposePassManager(passmgr);
6672 }
6673
6674 static void
6675 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6676 {
6677 struct ac_vs_output_info *outinfo;
6678
6679 switch (ctx->stage) {
6680 case MESA_SHADER_FRAGMENT:
6681 case MESA_SHADER_COMPUTE:
6682 case MESA_SHADER_TESS_CTRL:
6683 case MESA_SHADER_GEOMETRY:
6684 return;
6685 case MESA_SHADER_VERTEX:
6686 if (ctx->options->key.vs.as_ls ||
6687 ctx->options->key.vs.as_es)
6688 return;
6689 outinfo = &ctx->shader_info->vs.outinfo;
6690 break;
6691 case MESA_SHADER_TESS_EVAL:
6692 if (ctx->options->key.vs.as_es)
6693 return;
6694 outinfo = &ctx->shader_info->tes.outinfo;
6695 break;
6696 default:
6697 unreachable("Unhandled shader type");
6698 }
6699
6700 ac_optimize_vs_outputs(&ctx->ac,
6701 ctx->main_function,
6702 outinfo->vs_output_param_offset,
6703 VARYING_SLOT_MAX,
6704 &outinfo->param_exports);
6705 }
6706
6707 static void
6708 ac_setup_rings(struct radv_shader_context *ctx)
6709 {
6710 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6711 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6712 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6713 }
6714
6715 if (ctx->is_gs_copy_shader) {
6716 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6717 }
6718 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6719 LLVMValueRef tmp;
6720 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6721 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6722
6723 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6724
6725 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6726 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6727 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6728 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6729 }
6730
6731 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6732 ctx->stage == MESA_SHADER_TESS_EVAL) {
6733 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6734 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6735 }
6736 }
6737
6738 static unsigned
6739 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6740 const struct nir_shader *nir)
6741 {
6742 switch (nir->info.stage) {
6743 case MESA_SHADER_TESS_CTRL:
6744 return chip_class >= CIK ? 128 : 64;
6745 case MESA_SHADER_GEOMETRY:
6746 return chip_class >= GFX9 ? 128 : 64;
6747 case MESA_SHADER_COMPUTE:
6748 break;
6749 default:
6750 return 0;
6751 }
6752
6753 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6754 nir->info.cs.local_size[1] *
6755 nir->info.cs.local_size[2];
6756 return max_workgroup_size;
6757 }
6758
6759 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6760 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6761 {
6762 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6763 LLVMConstInt(ctx->ac.i32, 8, false),
6764 LLVMConstInt(ctx->ac.i32, 8, false), false);
6765 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6766 ctx->ac.i32_0, "");
6767 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6768 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6769 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6770 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6771 }
6772
6773 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6774 {
6775 for(int i = 5; i >= 0; --i) {
6776 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6777 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6778 LLVMConstInt(ctx->ac.i32, 16, false), false);
6779 }
6780
6781 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6782 LLVMConstInt(ctx->ac.i32, 16, false),
6783 LLVMConstInt(ctx->ac.i32, 8, false), false);
6784 }
6785
6786 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6787 struct nir_shader *nir)
6788 {
6789 struct ac_nir_context ctx = {};
6790 struct nir_function *func;
6791
6792 ctx.ac = *ac;
6793 ctx.abi = abi;
6794
6795 ctx.stage = nir->info.stage;
6796
6797 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6798
6799 nir_foreach_variable(variable, &nir->outputs)
6800 handle_shader_output_decl(&ctx, nir, variable);
6801
6802 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6803 _mesa_key_pointer_equal);
6804 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6805 _mesa_key_pointer_equal);
6806 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6807 _mesa_key_pointer_equal);
6808
6809 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6810
6811 setup_locals(&ctx, func);
6812
6813 if (nir->info.stage == MESA_SHADER_COMPUTE)
6814 setup_shared(&ctx, nir);
6815
6816 visit_cf_list(&ctx, &func->impl->body);
6817 phi_post_pass(&ctx);
6818
6819 if (nir->info.stage != MESA_SHADER_COMPUTE)
6820 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6821 ctx.abi->outputs);
6822
6823 free(ctx.locals);
6824 ralloc_free(ctx.defs);
6825 ralloc_free(ctx.phis);
6826 ralloc_free(ctx.vars);
6827 }
6828
6829 static
6830 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6831 struct nir_shader *const *shaders,
6832 int shader_count,
6833 struct ac_shader_variant_info *shader_info,
6834 const struct ac_nir_compiler_options *options)
6835 {
6836 struct radv_shader_context ctx = {0};
6837 unsigned i;
6838 ctx.options = options;
6839 ctx.shader_info = shader_info;
6840 ctx.context = LLVMContextCreate();
6841
6842 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6843 options->family);
6844 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6845 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6846
6847 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6848 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6849 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6850 LLVMDisposeTargetData(data_layout);
6851 LLVMDisposeMessage(data_layout_str);
6852
6853 enum ac_float_mode float_mode =
6854 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6855 AC_FLOAT_MODE_DEFAULT;
6856
6857 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6858
6859 memset(shader_info, 0, sizeof(*shader_info));
6860
6861 for(int i = 0; i < shader_count; ++i)
6862 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6863
6864 for (i = 0; i < AC_UD_MAX_SETS; i++)
6865 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6866 for (i = 0; i < AC_UD_MAX_UD; i++)
6867 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6868
6869 ctx.max_workgroup_size = 0;
6870 for (int i = 0; i < shader_count; ++i) {
6871 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6872 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6873 shaders[i]));
6874 }
6875
6876 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6877 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6878
6879 ctx.abi.inputs = &ctx.inputs[0];
6880 ctx.abi.emit_outputs = handle_shader_outputs_post;
6881 ctx.abi.emit_vertex = visit_emit_vertex;
6882 ctx.abi.load_ubo = radv_load_ubo;
6883 ctx.abi.load_ssbo = radv_load_ssbo;
6884 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6885 ctx.abi.load_resource = radv_load_resource;
6886 ctx.abi.clamp_shadow_reference = false;
6887
6888 if (shader_count >= 2)
6889 ac_init_exec_full_mask(&ctx.ac);
6890
6891 if (ctx.ac.chip_class == GFX9 &&
6892 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6893 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6894
6895 for(int i = 0; i < shader_count; ++i) {
6896 ctx.stage = shaders[i]->info.stage;
6897 ctx.output_mask = 0;
6898 ctx.tess_outputs_written = 0;
6899 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6900 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6901
6902 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6903 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6904 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6905 ctx.abi.load_inputs = load_gs_input;
6906 ctx.abi.emit_primitive = visit_end_primitive;
6907 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6908 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6909 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6910 ctx.abi.load_tess_varyings = load_tcs_varyings;
6911 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6912 ctx.abi.store_tcs_outputs = store_tcs_output;
6913 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6914 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6915 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6916 ctx.abi.load_tess_varyings = load_tes_input;
6917 ctx.abi.load_tess_coord = load_tess_coord;
6918 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6919 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
6920 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6921 if (shader_info->info.vs.needs_instance_id) {
6922 if (ctx.options->key.vs.as_ls) {
6923 ctx.shader_info->vs.vgpr_comp_cnt =
6924 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6925 } else {
6926 ctx.shader_info->vs.vgpr_comp_cnt =
6927 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6928 }
6929 }
6930 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6931 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6932 ctx.abi.lookup_interp_param = lookup_interp_param;
6933 ctx.abi.load_sample_position = load_sample_position;
6934 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6935 }
6936
6937 if (i)
6938 emit_barrier(&ctx.ac, ctx.stage);
6939
6940 ac_setup_rings(&ctx);
6941
6942 LLVMBasicBlockRef merge_block;
6943 if (shader_count >= 2) {
6944 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6945 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6946 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6947
6948 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6949 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6950 LLVMConstInt(ctx.ac.i32, 8, false), false);
6951 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6952 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6953 thread_id, count, "");
6954 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6955
6956 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6957 }
6958
6959 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6960 handle_fs_inputs(&ctx, shaders[i]);
6961 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6962 handle_vs_inputs(&ctx, shaders[i]);
6963 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6964 prepare_gs_input_vgprs(&ctx);
6965
6966 nir_foreach_variable(variable, &shaders[i]->outputs)
6967 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6968
6969 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6970
6971 if (shader_count >= 2) {
6972 LLVMBuildBr(ctx.ac.builder, merge_block);
6973 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6974 }
6975
6976 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6977 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6978 shaders[i]->info.cull_distance_array_size > 4;
6979 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6980 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6981 shaders[i]->info.gs.vertices_out;
6982 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6983 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6984 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6985 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6986 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6987 }
6988 }
6989
6990 LLVMBuildRetVoid(ctx.ac.builder);
6991
6992 if (options->dump_preoptir)
6993 ac_dump_module(ctx.ac.module);
6994
6995 ac_llvm_finalize_module(&ctx);
6996
6997 if (shader_count == 1)
6998 ac_nir_eliminate_const_vs_outputs(&ctx);
6999
7000 return ctx.ac.module;
7001 }
7002
7003 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
7004 {
7005 unsigned *retval = (unsigned *)context;
7006 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
7007 char *description = LLVMGetDiagInfoDescription(di);
7008
7009 if (severity == LLVMDSError) {
7010 *retval = 1;
7011 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
7012 description);
7013 }
7014
7015 LLVMDisposeMessage(description);
7016 }
7017
7018 static unsigned ac_llvm_compile(LLVMModuleRef M,
7019 struct ac_shader_binary *binary,
7020 LLVMTargetMachineRef tm)
7021 {
7022 unsigned retval = 0;
7023 char *err;
7024 LLVMContextRef llvm_ctx;
7025 LLVMMemoryBufferRef out_buffer;
7026 unsigned buffer_size;
7027 const char *buffer_data;
7028 LLVMBool mem_err;
7029
7030 /* Setup Diagnostic Handler*/
7031 llvm_ctx = LLVMGetModuleContext(M);
7032
7033 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
7034 &retval);
7035
7036 /* Compile IR*/
7037 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
7038 &err, &out_buffer);
7039
7040 /* Process Errors/Warnings */
7041 if (mem_err) {
7042 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7043 free(err);
7044 retval = 1;
7045 goto out;
7046 }
7047
7048 /* Extract Shader Code*/
7049 buffer_size = LLVMGetBufferSize(out_buffer);
7050 buffer_data = LLVMGetBufferStart(out_buffer);
7051
7052 ac_elf_read(buffer_data, buffer_size, binary);
7053
7054 /* Clean up */
7055 LLVMDisposeMemoryBuffer(out_buffer);
7056
7057 out:
7058 return retval;
7059 }
7060
7061 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7062 LLVMModuleRef llvm_module,
7063 struct ac_shader_binary *binary,
7064 struct ac_shader_config *config,
7065 struct ac_shader_variant_info *shader_info,
7066 gl_shader_stage stage,
7067 bool dump_shader, bool supports_spill)
7068 {
7069 if (dump_shader)
7070 ac_dump_module(llvm_module);
7071
7072 memset(binary, 0, sizeof(*binary));
7073 int v = ac_llvm_compile(llvm_module, binary, tm);
7074 if (v) {
7075 fprintf(stderr, "compile failed\n");
7076 }
7077
7078 if (dump_shader)
7079 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7080
7081 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7082
7083 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7084 LLVMDisposeModule(llvm_module);
7085 LLVMContextDispose(ctx);
7086
7087 if (stage == MESA_SHADER_FRAGMENT) {
7088 shader_info->num_input_vgprs = 0;
7089 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7090 shader_info->num_input_vgprs += 2;
7091 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7092 shader_info->num_input_vgprs += 2;
7093 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7094 shader_info->num_input_vgprs += 2;
7095 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7096 shader_info->num_input_vgprs += 3;
7097 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7098 shader_info->num_input_vgprs += 2;
7099 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7100 shader_info->num_input_vgprs += 2;
7101 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7102 shader_info->num_input_vgprs += 2;
7103 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7104 shader_info->num_input_vgprs += 1;
7105 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7106 shader_info->num_input_vgprs += 1;
7107 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7108 shader_info->num_input_vgprs += 1;
7109 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7110 shader_info->num_input_vgprs += 1;
7111 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7112 shader_info->num_input_vgprs += 1;
7113 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7114 shader_info->num_input_vgprs += 1;
7115 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7116 shader_info->num_input_vgprs += 1;
7117 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7118 shader_info->num_input_vgprs += 1;
7119 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7120 shader_info->num_input_vgprs += 1;
7121 }
7122 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7123
7124 /* +3 for scratch wave offset and VCC */
7125 config->num_sgprs = MAX2(config->num_sgprs,
7126 shader_info->num_input_sgprs + 3);
7127
7128 /* Enable 64-bit and 16-bit denormals, because there is no performance
7129 * cost.
7130 *
7131 * If denormals are enabled, all floating-point output modifiers are
7132 * ignored.
7133 *
7134 * Don't enable denormals for 32-bit floats, because:
7135 * - Floating-point output modifiers would be ignored by the hw.
7136 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7137 * have to stop using those.
7138 * - SI & CI would be very slow.
7139 */
7140 config->float_mode |= V_00B028_FP_64_DENORMS;
7141 }
7142
7143 static void
7144 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7145 {
7146 switch (nir->info.stage) {
7147 case MESA_SHADER_COMPUTE:
7148 for (int i = 0; i < 3; ++i)
7149 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7150 break;
7151 case MESA_SHADER_FRAGMENT:
7152 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7153 break;
7154 case MESA_SHADER_GEOMETRY:
7155 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7156 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7157 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7158 shader_info->gs.invocations = nir->info.gs.invocations;
7159 break;
7160 case MESA_SHADER_TESS_EVAL:
7161 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7162 shader_info->tes.spacing = nir->info.tess.spacing;
7163 shader_info->tes.ccw = nir->info.tess.ccw;
7164 shader_info->tes.point_mode = nir->info.tess.point_mode;
7165 shader_info->tes.as_es = options->key.tes.as_es;
7166 break;
7167 case MESA_SHADER_TESS_CTRL:
7168 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7169 break;
7170 case MESA_SHADER_VERTEX:
7171 shader_info->vs.as_es = options->key.vs.as_es;
7172 shader_info->vs.as_ls = options->key.vs.as_ls;
7173 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7174 if (options->key.vs.as_ls)
7175 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7176 break;
7177 default:
7178 break;
7179 }
7180 }
7181
7182 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7183 struct ac_shader_binary *binary,
7184 struct ac_shader_config *config,
7185 struct ac_shader_variant_info *shader_info,
7186 struct nir_shader *const *nir,
7187 int nir_count,
7188 const struct ac_nir_compiler_options *options,
7189 bool dump_shader)
7190 {
7191
7192 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7193 options);
7194
7195 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7196 for (int i = 0; i < nir_count; ++i)
7197 ac_fill_shader_info(shader_info, nir[i], options);
7198
7199 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7200 if (options->chip_class == GFX9) {
7201 if (nir_count == 2 &&
7202 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7203 shader_info->gs.es_type = nir[0]->info.stage;
7204 }
7205 }
7206 }
7207
7208 static void
7209 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7210 {
7211 LLVMValueRef vtx_offset =
7212 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7213 LLVMConstInt(ctx->ac.i32, 4, false), "");
7214 int idx = 0;
7215
7216 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7217 int length = 4;
7218 int slot = idx;
7219 int slot_inc = 1;
7220 if (!(ctx->output_mask & (1ull << i)))
7221 continue;
7222
7223 if (i == VARYING_SLOT_CLIP_DIST0) {
7224 /* unpack clip and cull from a single set of slots */
7225 length = ctx->num_output_clips + ctx->num_output_culls;
7226 if (length > 4)
7227 slot_inc = 2;
7228 }
7229
7230 for (unsigned j = 0; j < length; j++) {
7231 LLVMValueRef value, soffset;
7232
7233 soffset = LLVMConstInt(ctx->ac.i32,
7234 (slot * 4 + j) *
7235 ctx->gs_max_out_vertices * 16 * 4, false);
7236
7237 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7238 1, ctx->ac.i32_0,
7239 vtx_offset, soffset,
7240 0, 1, 1, true, false);
7241
7242 LLVMBuildStore(ctx->ac.builder,
7243 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7244 }
7245 idx += slot_inc;
7246 }
7247 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7248 }
7249
7250 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7251 struct nir_shader *geom_shader,
7252 struct ac_shader_binary *binary,
7253 struct ac_shader_config *config,
7254 struct ac_shader_variant_info *shader_info,
7255 const struct ac_nir_compiler_options *options,
7256 bool dump_shader)
7257 {
7258 struct radv_shader_context ctx = {0};
7259 ctx.context = LLVMContextCreate();
7260 ctx.options = options;
7261 ctx.shader_info = shader_info;
7262
7263 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7264 options->family);
7265 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7266
7267 ctx.is_gs_copy_shader = true;
7268 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7269
7270 enum ac_float_mode float_mode =
7271 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7272 AC_FLOAT_MODE_DEFAULT;
7273
7274 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7275 ctx.stage = MESA_SHADER_VERTEX;
7276
7277 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7278
7279 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7280 ac_setup_rings(&ctx);
7281
7282 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7283 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7284
7285 struct ac_nir_context nir_ctx = {};
7286 nir_ctx.ac = ctx.ac;
7287 nir_ctx.abi = &ctx.abi;
7288
7289 nir_foreach_variable(variable, &geom_shader->outputs) {
7290 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7291 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7292 }
7293
7294 ac_gs_copy_shader_emit(&ctx);
7295
7296 LLVMBuildRetVoid(ctx.ac.builder);
7297
7298 ac_llvm_finalize_module(&ctx);
7299
7300 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7301 MESA_SHADER_VERTEX,
7302 dump_shader, options->supports_spill);
7303 }