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radeonsi: move building llvm.SI.load.const into ac_build_buffer_load
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 #include "ac_exp_param.h"
35
36 enum radeon_llvm_calling_convention {
37 RADEON_LLVM_AMDGPU_VS = 87,
38 RADEON_LLVM_AMDGPU_GS = 88,
39 RADEON_LLVM_AMDGPU_PS = 89,
40 RADEON_LLVM_AMDGPU_CS = 90,
41 };
42
43 #define CONST_ADDR_SPACE 2
44 #define LOCAL_ADDR_SPACE 3
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 enum desc_type {
50 DESC_IMAGE,
51 DESC_FMASK,
52 DESC_SAMPLER,
53 DESC_BUFFER,
54 };
55
56 struct nir_to_llvm_context {
57 struct ac_llvm_context ac;
58 const struct ac_nir_compiler_options *options;
59 struct ac_shader_variant_info *shader_info;
60
61 LLVMContextRef context;
62 LLVMModuleRef module;
63 LLVMBuilderRef builder;
64 LLVMValueRef main_function;
65
66 struct hash_table *defs;
67 struct hash_table *phis;
68
69 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
70 LLVMValueRef ring_offsets;
71 LLVMValueRef push_constants;
72 LLVMValueRef num_work_groups;
73 LLVMValueRef workgroup_ids;
74 LLVMValueRef local_invocation_ids;
75 LLVMValueRef tg_size;
76
77 LLVMValueRef vertex_buffers;
78 LLVMValueRef base_vertex;
79 LLVMValueRef start_instance;
80 LLVMValueRef draw_index;
81 LLVMValueRef vertex_id;
82 LLVMValueRef rel_auto_id;
83 LLVMValueRef vs_prim_id;
84 LLVMValueRef instance_id;
85 LLVMValueRef ls_out_layout;
86 LLVMValueRef es2gs_offset;
87
88 LLVMValueRef tcs_offchip_layout;
89 LLVMValueRef tcs_out_offsets;
90 LLVMValueRef tcs_out_layout;
91 LLVMValueRef tcs_in_layout;
92 LLVMValueRef oc_lds;
93 LLVMValueRef tess_factor_offset;
94 LLVMValueRef tcs_patch_id;
95 LLVMValueRef tcs_rel_ids;
96 LLVMValueRef tes_rel_patch_id;
97 LLVMValueRef tes_patch_id;
98 LLVMValueRef tes_u;
99 LLVMValueRef tes_v;
100
101 LLVMValueRef gsvs_ring_stride;
102 LLVMValueRef gsvs_num_entries;
103 LLVMValueRef gs2vs_offset;
104 LLVMValueRef gs_wave_id;
105 LLVMValueRef gs_vtx_offset[6];
106 LLVMValueRef gs_prim_id, gs_invocation_id;
107
108 LLVMValueRef esgs_ring;
109 LLVMValueRef gsvs_ring;
110 LLVMValueRef hs_ring_tess_offchip;
111 LLVMValueRef hs_ring_tess_factor;
112
113 LLVMValueRef prim_mask;
114 LLVMValueRef sample_pos_offset;
115 LLVMValueRef persp_sample, persp_center, persp_centroid;
116 LLVMValueRef linear_sample, linear_center, linear_centroid;
117 LLVMValueRef front_face;
118 LLVMValueRef ancillary;
119 LLVMValueRef sample_coverage;
120 LLVMValueRef frag_pos[4];
121
122 LLVMBasicBlockRef continue_block;
123 LLVMBasicBlockRef break_block;
124
125 LLVMTypeRef i1;
126 LLVMTypeRef i8;
127 LLVMTypeRef i16;
128 LLVMTypeRef i32;
129 LLVMTypeRef i64;
130 LLVMTypeRef v2i32;
131 LLVMTypeRef v3i32;
132 LLVMTypeRef v4i32;
133 LLVMTypeRef v8i32;
134 LLVMTypeRef f64;
135 LLVMTypeRef f32;
136 LLVMTypeRef f16;
137 LLVMTypeRef v2f32;
138 LLVMTypeRef v4f32;
139 LLVMTypeRef v16i8;
140 LLVMTypeRef voidt;
141
142 LLVMValueRef i1true;
143 LLVMValueRef i1false;
144 LLVMValueRef i32zero;
145 LLVMValueRef i32one;
146 LLVMValueRef f32zero;
147 LLVMValueRef f32one;
148 LLVMValueRef v4f32empty;
149
150 unsigned uniform_md_kind;
151 LLVMValueRef empty_md;
152 gl_shader_stage stage;
153
154 LLVMValueRef lds;
155 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
156 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
157
158 LLVMValueRef shared_memory;
159 uint64_t input_mask;
160 uint64_t output_mask;
161 int num_locals;
162 LLVMValueRef *locals;
163 bool has_ddxy;
164 uint8_t num_output_clips;
165 uint8_t num_output_culls;
166
167 bool has_ds_bpermute;
168
169 bool is_gs_copy_shader;
170 LLVMValueRef gs_next_vertex;
171 unsigned gs_max_out_vertices;
172
173 unsigned tes_primitive_mode;
174 uint64_t tess_outputs_written;
175 uint64_t tess_patch_outputs_written;
176 };
177
178 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
179 nir_deref_var *deref,
180 enum desc_type desc_type);
181 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
182 {
183 return (index * 4) + chan;
184 }
185
186 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
187 {
188 /* handle patch indices separate */
189 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
190 return 0;
191 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
192 return 1;
193 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
194 return 2 + (slot - VARYING_SLOT_PATCH0);
195
196 if (slot == VARYING_SLOT_POS)
197 return 0;
198 if (slot == VARYING_SLOT_PSIZ)
199 return 1;
200 if (slot == VARYING_SLOT_CLIP_DIST0)
201 return 2;
202 /* 3 is reserved for clip dist as well */
203 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
204 return 4 + (slot - VARYING_SLOT_VAR0);
205 unreachable("illegal slot in get unique index\n");
206 }
207
208 static unsigned llvm_get_type_size(LLVMTypeRef type)
209 {
210 LLVMTypeKind kind = LLVMGetTypeKind(type);
211
212 switch (kind) {
213 case LLVMIntegerTypeKind:
214 return LLVMGetIntTypeWidth(type) / 8;
215 case LLVMFloatTypeKind:
216 return 4;
217 case LLVMPointerTypeKind:
218 return 8;
219 case LLVMVectorTypeKind:
220 return LLVMGetVectorSize(type) *
221 llvm_get_type_size(LLVMGetElementType(type));
222 default:
223 assert(0);
224 return 0;
225 }
226 }
227
228 static void set_llvm_calling_convention(LLVMValueRef func,
229 gl_shader_stage stage)
230 {
231 enum radeon_llvm_calling_convention calling_conv;
232
233 switch (stage) {
234 case MESA_SHADER_VERTEX:
235 case MESA_SHADER_TESS_CTRL:
236 case MESA_SHADER_TESS_EVAL:
237 calling_conv = RADEON_LLVM_AMDGPU_VS;
238 break;
239 case MESA_SHADER_GEOMETRY:
240 calling_conv = RADEON_LLVM_AMDGPU_GS;
241 break;
242 case MESA_SHADER_FRAGMENT:
243 calling_conv = RADEON_LLVM_AMDGPU_PS;
244 break;
245 case MESA_SHADER_COMPUTE:
246 calling_conv = RADEON_LLVM_AMDGPU_CS;
247 break;
248 default:
249 unreachable("Unhandle shader type");
250 }
251
252 LLVMSetFunctionCallConv(func, calling_conv);
253 }
254
255 static LLVMValueRef
256 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
257 LLVMBuilderRef builder, LLVMTypeRef *return_types,
258 unsigned num_return_elems, LLVMTypeRef *param_types,
259 unsigned param_count, unsigned array_params_mask,
260 unsigned sgpr_params, bool unsafe_math)
261 {
262 LLVMTypeRef main_function_type, ret_type;
263 LLVMBasicBlockRef main_function_body;
264
265 if (num_return_elems)
266 ret_type = LLVMStructTypeInContext(ctx, return_types,
267 num_return_elems, true);
268 else
269 ret_type = LLVMVoidTypeInContext(ctx);
270
271 /* Setup the function */
272 main_function_type =
273 LLVMFunctionType(ret_type, param_types, param_count, 0);
274 LLVMValueRef main_function =
275 LLVMAddFunction(module, "main", main_function_type);
276 main_function_body =
277 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
278 LLVMPositionBuilderAtEnd(builder, main_function_body);
279
280 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
281 for (unsigned i = 0; i < sgpr_params; ++i) {
282 if (array_params_mask & (1 << i)) {
283 LLVMValueRef P = LLVMGetParam(main_function, i);
284 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
285 ac_add_attr_dereferenceable(P, UINT64_MAX);
286 }
287 else {
288 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
289 }
290 }
291
292 if (unsafe_math) {
293 /* These were copied from some LLVM test. */
294 LLVMAddTargetDependentFunctionAttr(main_function,
295 "less-precise-fpmad",
296 "true");
297 LLVMAddTargetDependentFunctionAttr(main_function,
298 "no-infs-fp-math",
299 "true");
300 LLVMAddTargetDependentFunctionAttr(main_function,
301 "no-nans-fp-math",
302 "true");
303 LLVMAddTargetDependentFunctionAttr(main_function,
304 "unsafe-fp-math",
305 "true");
306 }
307 return main_function;
308 }
309
310 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
311 {
312 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
313 CONST_ADDR_SPACE);
314 }
315
316 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
317 int idx,
318 LLVMTypeRef type)
319 {
320 LLVMValueRef offset;
321 LLVMValueRef ptr;
322 int addr_space;
323
324 offset = LLVMConstInt(ctx->i32, idx * 16, false);
325
326 ptr = ctx->shared_memory;
327 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
328 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
329 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
330 return ptr;
331 }
332
333 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
334 {
335 if (t == ctx->f16 || t == ctx->i16)
336 return ctx->i16;
337 else if (t == ctx->f32 || t == ctx->i32)
338 return ctx->i32;
339 else if (t == ctx->f64 || t == ctx->i64)
340 return ctx->i64;
341 else
342 unreachable("Unhandled integer size");
343 }
344
345 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
346 {
347 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
348 LLVMTypeRef elem_type = LLVMGetElementType(t);
349 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
350 LLVMGetVectorSize(t));
351 }
352 return to_integer_type_scalar(ctx, t);
353 }
354
355 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
356 {
357 LLVMTypeRef type = LLVMTypeOf(v);
358 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
359 }
360
361 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
362 {
363 if (t == ctx->i16 || t == ctx->f16)
364 return ctx->f16;
365 else if (t == ctx->i32 || t == ctx->f32)
366 return ctx->f32;
367 else if (t == ctx->i64 || t == ctx->f64)
368 return ctx->f64;
369 else
370 unreachable("Unhandled float size");
371 }
372
373 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
374 {
375 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
376 LLVMTypeRef elem_type = LLVMGetElementType(t);
377 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
378 LLVMGetVectorSize(t));
379 }
380 return to_float_type_scalar(ctx, t);
381 }
382
383 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
384 {
385 LLVMTypeRef type = LLVMTypeOf(v);
386 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
387 }
388
389 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
390 {
391 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
392 type = LLVMGetElementType(type);
393
394 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
395 return LLVMGetIntTypeWidth(type);
396
397 if (type == ctx->f16)
398 return 16;
399 if (type == ctx->f32)
400 return 32;
401 if (type == ctx->f64)
402 return 64;
403
404 unreachable("Unhandled type kind in get_elem_bits");
405 }
406
407 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
408 LLVMValueRef param, unsigned rshift,
409 unsigned bitwidth)
410 {
411 LLVMValueRef value = param;
412 if (rshift)
413 value = LLVMBuildLShr(ctx->builder, value,
414 LLVMConstInt(ctx->i32, rshift, false), "");
415
416 if (rshift + bitwidth < 32) {
417 unsigned mask = (1 << bitwidth) - 1;
418 value = LLVMBuildAnd(ctx->builder, value,
419 LLVMConstInt(ctx->i32, mask, false), "");
420 }
421 return value;
422 }
423
424 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
425 {
426 switch (ctx->stage) {
427 case MESA_SHADER_TESS_CTRL:
428 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
429 case MESA_SHADER_TESS_EVAL:
430 return ctx->tes_rel_patch_id;
431 break;
432 default:
433 unreachable("Illegal stage");
434 }
435 }
436
437 /* Tessellation shaders pass outputs to the next shader using LDS.
438 *
439 * LS outputs = TCS inputs
440 * TCS outputs = TES inputs
441 *
442 * The LDS layout is:
443 * - TCS inputs for patch 0
444 * - TCS inputs for patch 1
445 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
446 * - ...
447 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
448 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
449 * - TCS outputs for patch 1
450 * - Per-patch TCS outputs for patch 1
451 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
452 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
453 * - ...
454 *
455 * All three shaders VS(LS), TCS, TES share the same LDS space.
456 */
457 static LLVMValueRef
458 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
459 {
460 if (ctx->stage == MESA_SHADER_VERTEX)
461 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
462 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
463 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
464 else {
465 assert(0);
466 return NULL;
467 }
468 }
469
470 static LLVMValueRef
471 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
472 {
473 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
474 }
475
476 static LLVMValueRef
477 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
478 {
479 return LLVMBuildMul(ctx->builder,
480 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
481 LLVMConstInt(ctx->i32, 4, false), "");
482 }
483
484 static LLVMValueRef
485 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
486 {
487 return LLVMBuildMul(ctx->builder,
488 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
489 LLVMConstInt(ctx->i32, 4, false), "");
490 }
491
492 static LLVMValueRef
493 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
494 {
495 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
496 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
497
498 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
499 }
500
501 static LLVMValueRef
502 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
503 {
504 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
505 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
506 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
507
508 return LLVMBuildAdd(ctx->builder, patch0_offset,
509 LLVMBuildMul(ctx->builder, patch_stride,
510 rel_patch_id, ""),
511 "");
512 }
513
514 static LLVMValueRef
515 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
516 {
517 LLVMValueRef patch0_patch_data_offset =
518 get_tcs_out_patch0_patch_data_offset(ctx);
519 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
520 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
521
522 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
523 LLVMBuildMul(ctx->builder, patch_stride,
524 rel_patch_id, ""),
525 "");
526 }
527
528 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
529 {
530 ud_info->sgpr_idx = sgpr_idx;
531 ud_info->num_sgprs = num_sgprs;
532 ud_info->indirect = false;
533 ud_info->indirect_offset = 0;
534 }
535
536 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
537 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
538 {
539 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
540 }
541
542
543 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
544 uint32_t indirect_offset)
545 {
546 ud_info->sgpr_idx = sgpr_idx;
547 ud_info->num_sgprs = num_sgprs;
548 ud_info->indirect = true;
549 ud_info->indirect_offset = indirect_offset;
550 }
551
552 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
553 {
554 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
555 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
556 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
557 "tess_lds");
558 }
559
560 struct user_sgpr_info {
561 bool need_ring_offsets;
562 uint8_t sgpr_count;
563 bool indirect_all_descriptor_sets;
564 };
565
566 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
567 struct user_sgpr_info *user_sgpr_info)
568 {
569 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
570
571 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
572 if (ctx->stage == MESA_SHADER_GEOMETRY ||
573 ctx->stage == MESA_SHADER_VERTEX ||
574 ctx->stage == MESA_SHADER_TESS_CTRL ||
575 ctx->stage == MESA_SHADER_TESS_EVAL ||
576 ctx->is_gs_copy_shader)
577 user_sgpr_info->need_ring_offsets = true;
578
579 if (ctx->stage == MESA_SHADER_FRAGMENT &&
580 ctx->shader_info->info.ps.needs_sample_positions)
581 user_sgpr_info->need_ring_offsets = true;
582
583 /* 2 user sgprs will nearly always be allocated for scratch/rings */
584 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
585 user_sgpr_info->sgpr_count += 2;
586 }
587
588 switch (ctx->stage) {
589 case MESA_SHADER_COMPUTE:
590 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
591 break;
592 case MESA_SHADER_FRAGMENT:
593 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
594 break;
595 case MESA_SHADER_VERTEX:
596 if (!ctx->is_gs_copy_shader) {
597 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
598 if (ctx->shader_info->info.vs.needs_draw_id) {
599 user_sgpr_info->sgpr_count += 3;
600 } else {
601 user_sgpr_info->sgpr_count += 2;
602 }
603 }
604 if (ctx->options->key.vs.as_ls)
605 user_sgpr_info->sgpr_count++;
606 break;
607 case MESA_SHADER_TESS_CTRL:
608 user_sgpr_info->sgpr_count += 4;
609 break;
610 case MESA_SHADER_TESS_EVAL:
611 user_sgpr_info->sgpr_count += 1;
612 break;
613 case MESA_SHADER_GEOMETRY:
614 user_sgpr_info->sgpr_count += 2;
615 break;
616 default:
617 break;
618 }
619
620 if (ctx->shader_info->info.needs_push_constants)
621 user_sgpr_info->sgpr_count += 2;
622
623 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
624 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
625 user_sgpr_info->sgpr_count += 2;
626 user_sgpr_info->indirect_all_descriptor_sets = true;
627 } else {
628 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
629 }
630 }
631
632 static void create_function(struct nir_to_llvm_context *ctx)
633 {
634 LLVMTypeRef arg_types[23];
635 unsigned arg_idx = 0;
636 unsigned array_params_mask = 0;
637 unsigned sgpr_count = 0, user_sgpr_count;
638 unsigned i;
639 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
640 unsigned user_sgpr_idx;
641 struct user_sgpr_info user_sgpr_info;
642
643 allocate_user_sgprs(ctx, &user_sgpr_info);
644 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
645 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* address of rings */
646 }
647
648 /* 1 for each descriptor set */
649 if (!user_sgpr_info.indirect_all_descriptor_sets) {
650 for (unsigned i = 0; i < num_sets; ++i) {
651 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
652 array_params_mask |= (1 << arg_idx);
653 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
654 }
655 }
656 } else {
657 array_params_mask |= (1 << arg_idx);
658 arg_types[arg_idx++] = const_array(const_array(ctx->i8, 1024 * 1024), 32);
659 }
660
661 if (ctx->shader_info->info.needs_push_constants) {
662 /* 1 for push constants and dynamic descriptors */
663 array_params_mask |= (1 << arg_idx);
664 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
665 }
666
667 switch (ctx->stage) {
668 case MESA_SHADER_COMPUTE:
669 if (ctx->shader_info->info.cs.grid_components_used)
670 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used); /* grid size */
671 user_sgpr_count = arg_idx;
672 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
673 arg_types[arg_idx++] = ctx->i32;
674 sgpr_count = arg_idx;
675
676 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
677 break;
678 case MESA_SHADER_VERTEX:
679 if (!ctx->is_gs_copy_shader) {
680 if (ctx->shader_info->info.vs.has_vertex_buffers)
681 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
682 arg_types[arg_idx++] = ctx->i32; // base vertex
683 arg_types[arg_idx++] = ctx->i32; // start instance
684 if (ctx->shader_info->info.vs.needs_draw_id)
685 arg_types[arg_idx++] = ctx->i32; // draw index
686 }
687 user_sgpr_count = arg_idx;
688 if (ctx->options->key.vs.as_es)
689 arg_types[arg_idx++] = ctx->i32; //es2gs offset
690 else if (ctx->options->key.vs.as_ls) {
691 arg_types[arg_idx++] = ctx->i32; //ls out layout
692 user_sgpr_count++;
693 }
694 sgpr_count = arg_idx;
695 arg_types[arg_idx++] = ctx->i32; // vertex id
696 if (!ctx->is_gs_copy_shader) {
697 arg_types[arg_idx++] = ctx->i32; // rel auto id
698 arg_types[arg_idx++] = ctx->i32; // vs prim id
699 arg_types[arg_idx++] = ctx->i32; // instance id
700 }
701 break;
702 case MESA_SHADER_TESS_CTRL:
703 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
704 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
705 arg_types[arg_idx++] = ctx->i32; // tcs out layout
706 arg_types[arg_idx++] = ctx->i32; // tcs in layout
707 user_sgpr_count = arg_idx;
708 arg_types[arg_idx++] = ctx->i32; // param oc lds
709 arg_types[arg_idx++] = ctx->i32; // tess factor offset
710 sgpr_count = arg_idx;
711 arg_types[arg_idx++] = ctx->i32; // patch id
712 arg_types[arg_idx++] = ctx->i32; // rel ids;
713 break;
714 case MESA_SHADER_TESS_EVAL:
715 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
716 user_sgpr_count = arg_idx;
717 if (ctx->options->key.tes.as_es) {
718 arg_types[arg_idx++] = ctx->i32; // OC LDS
719 arg_types[arg_idx++] = ctx->i32; //
720 arg_types[arg_idx++] = ctx->i32; // es2gs offset
721 } else {
722 arg_types[arg_idx++] = ctx->i32; //
723 arg_types[arg_idx++] = ctx->i32; // OC LDS
724 }
725 sgpr_count = arg_idx;
726 arg_types[arg_idx++] = ctx->f32; // tes_u
727 arg_types[arg_idx++] = ctx->f32; // tes_v
728 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
729 arg_types[arg_idx++] = ctx->i32; // tes patch id
730 break;
731 case MESA_SHADER_GEOMETRY:
732 arg_types[arg_idx++] = ctx->i32; // gsvs stride
733 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
734 user_sgpr_count = arg_idx;
735 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
736 arg_types[arg_idx++] = ctx->i32; // wave id
737 sgpr_count = arg_idx;
738 arg_types[arg_idx++] = ctx->i32; // vtx0
739 arg_types[arg_idx++] = ctx->i32; // vtx1
740 arg_types[arg_idx++] = ctx->i32; // prim id
741 arg_types[arg_idx++] = ctx->i32; // vtx2
742 arg_types[arg_idx++] = ctx->i32; // vtx3
743 arg_types[arg_idx++] = ctx->i32; // vtx4
744 arg_types[arg_idx++] = ctx->i32; // vtx5
745 arg_types[arg_idx++] = ctx->i32; // GS instance id
746 break;
747 case MESA_SHADER_FRAGMENT:
748 if (ctx->shader_info->info.ps.needs_sample_positions)
749 arg_types[arg_idx++] = ctx->i32; /* sample position offset */
750 user_sgpr_count = arg_idx;
751 arg_types[arg_idx++] = ctx->i32; /* prim mask */
752 sgpr_count = arg_idx;
753 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
754 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
755 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
756 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
757 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
758 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
759 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
760 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
761 arg_types[arg_idx++] = ctx->f32; /* pos x float */
762 arg_types[arg_idx++] = ctx->f32; /* pos y float */
763 arg_types[arg_idx++] = ctx->f32; /* pos z float */
764 arg_types[arg_idx++] = ctx->f32; /* pos w float */
765 arg_types[arg_idx++] = ctx->i32; /* front face */
766 arg_types[arg_idx++] = ctx->i32; /* ancillary */
767 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
768 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
769 break;
770 default:
771 unreachable("Shader stage not implemented");
772 }
773
774 ctx->main_function = create_llvm_function(
775 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
776 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
777 set_llvm_calling_convention(ctx->main_function, ctx->stage);
778
779 ctx->shader_info->num_input_sgprs = 0;
780 ctx->shader_info->num_input_vgprs = 0;
781
782 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
783 for (i = 0; i < user_sgpr_count; i++)
784 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
785
786 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
787 for (; i < sgpr_count; i++)
788 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
789
790 if (ctx->stage != MESA_SHADER_FRAGMENT)
791 for (; i < arg_idx; ++i)
792 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
793
794 arg_idx = 0;
795 user_sgpr_idx = 0;
796
797 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
798 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
799 user_sgpr_idx += 2;
800 if (ctx->options->supports_spill) {
801 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
802 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
803 NULL, 0, AC_FUNC_ATTR_READNONE);
804 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
805 const_array(ctx->v16i8, 16), "");
806 } else
807 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
808 }
809
810 if (!user_sgpr_info.indirect_all_descriptor_sets) {
811 for (unsigned i = 0; i < num_sets; ++i) {
812 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
813 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
814 user_sgpr_idx += 2;
815 ctx->descriptor_sets[i] =
816 LLVMGetParam(ctx->main_function, arg_idx++);
817 } else
818 ctx->descriptor_sets[i] = NULL;
819 }
820 } else {
821 uint32_t desc_sgpr_idx = user_sgpr_idx;
822 LLVMValueRef desc_sets = LLVMGetParam(ctx->main_function, arg_idx++);
823 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
824 user_sgpr_idx += 2;
825
826 for (unsigned i = 0; i < num_sets; ++i) {
827 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
828 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
829 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
830
831 } else
832 ctx->descriptor_sets[i] = NULL;
833 }
834 ctx->shader_info->need_indirect_descriptor_sets = true;
835 }
836
837 if (ctx->shader_info->info.needs_push_constants) {
838 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
839 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
840 user_sgpr_idx += 2;
841 }
842
843 switch (ctx->stage) {
844 case MESA_SHADER_COMPUTE:
845 if (ctx->shader_info->info.cs.grid_components_used) {
846 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
847 user_sgpr_idx += ctx->shader_info->info.cs.grid_components_used;
848 ctx->num_work_groups =
849 LLVMGetParam(ctx->main_function, arg_idx++);
850 }
851 ctx->workgroup_ids =
852 LLVMGetParam(ctx->main_function, arg_idx++);
853 ctx->tg_size =
854 LLVMGetParam(ctx->main_function, arg_idx++);
855 ctx->local_invocation_ids =
856 LLVMGetParam(ctx->main_function, arg_idx++);
857 break;
858 case MESA_SHADER_VERTEX:
859 if (!ctx->is_gs_copy_shader) {
860 if (ctx->shader_info->info.vs.has_vertex_buffers) {
861 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
862 user_sgpr_idx += 2;
863 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
864 }
865 unsigned vs_num = 2;
866 if (ctx->shader_info->info.vs.needs_draw_id)
867 vs_num++;
868
869 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
870 user_sgpr_idx += vs_num;
871
872 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
873 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
874 if (ctx->shader_info->info.vs.needs_draw_id)
875 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
876 }
877 if (ctx->options->key.vs.as_es)
878 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
879 else if (ctx->options->key.vs.as_ls) {
880 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, user_sgpr_idx, 1);
881 user_sgpr_idx += 1;
882 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
883 }
884 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
885 if (!ctx->is_gs_copy_shader) {
886 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
887 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
888 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
889 }
890 if (ctx->options->key.vs.as_ls)
891 declare_tess_lds(ctx);
892 break;
893 case MESA_SHADER_TESS_CTRL:
894 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
895 user_sgpr_idx += 4;
896 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
897 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
898 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
899 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
900 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
901 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
902 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
903 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
904
905 declare_tess_lds(ctx);
906 break;
907 case MESA_SHADER_TESS_EVAL:
908 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
909 user_sgpr_idx += 1;
910 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
911 if (ctx->options->key.tes.as_es) {
912 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
913 arg_idx++;
914 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
915 } else {
916 arg_idx++;
917 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
918 }
919 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
920 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
921 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
922 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
923 break;
924 case MESA_SHADER_GEOMETRY:
925 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
926 user_sgpr_idx += 2;
927 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
928 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
929 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
930 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
931 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
932 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
933 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
934 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
935 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
936 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
937 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
938 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
939 break;
940 case MESA_SHADER_FRAGMENT:
941 if (ctx->shader_info->info.ps.needs_sample_positions) {
942 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, user_sgpr_idx, 1);
943 user_sgpr_idx += 1;
944 ctx->sample_pos_offset = LLVMGetParam(ctx->main_function, arg_idx++);
945 }
946 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
947 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
948 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
949 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
950 arg_idx++;
951 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
952 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
953 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
954 arg_idx++; /* line stipple */
955 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
956 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
957 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
958 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
959 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
960 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
961 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
962 break;
963 default:
964 unreachable("Shader stage not implemented");
965 }
966 }
967
968 static void setup_types(struct nir_to_llvm_context *ctx)
969 {
970 LLVMValueRef args[4];
971
972 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
973 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
974 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
975 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
976 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
977 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
978 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
979 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
980 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
981 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
982 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
983 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
984 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
985 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
986 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
987 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
988
989 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
990 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
991 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
992 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
993 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
994 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
995
996 args[0] = ctx->f32zero;
997 args[1] = ctx->f32zero;
998 args[2] = ctx->f32zero;
999 args[3] = ctx->f32one;
1000 ctx->v4f32empty = LLVMConstVector(args, 4);
1001
1002 ctx->uniform_md_kind =
1003 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
1004 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
1005
1006 args[0] = LLVMConstReal(ctx->f32, 2.5);
1007 }
1008
1009 static int get_llvm_num_components(LLVMValueRef value)
1010 {
1011 LLVMTypeRef type = LLVMTypeOf(value);
1012 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1013 ? LLVMGetVectorSize(type)
1014 : 1;
1015 return num_components;
1016 }
1017
1018 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
1019 LLVMValueRef value,
1020 int index)
1021 {
1022 int count = get_llvm_num_components(value);
1023
1024 assert(index < count);
1025 if (count == 1)
1026 return value;
1027
1028 return LLVMBuildExtractElement(ctx->builder, value,
1029 LLVMConstInt(ctx->i32, index, false), "");
1030 }
1031
1032 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
1033 LLVMValueRef value, unsigned count)
1034 {
1035 unsigned num_components = get_llvm_num_components(value);
1036 if (count == num_components)
1037 return value;
1038
1039 LLVMValueRef masks[] = {
1040 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1041 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1042
1043 if (count == 1)
1044 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1045 "");
1046
1047 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1048 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1049 }
1050
1051 static void
1052 build_store_values_extended(struct nir_to_llvm_context *ctx,
1053 LLVMValueRef *values,
1054 unsigned value_count,
1055 unsigned value_stride,
1056 LLVMValueRef vec)
1057 {
1058 LLVMBuilderRef builder = ctx->builder;
1059 unsigned i;
1060
1061 if (value_count == 1) {
1062 LLVMBuildStore(builder, vec, values[0]);
1063 return;
1064 }
1065
1066 for (i = 0; i < value_count; i++) {
1067 LLVMValueRef ptr = values[i * value_stride];
1068 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
1069 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1070 LLVMBuildStore(builder, value, ptr);
1071 }
1072 }
1073
1074 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
1075 nir_ssa_def *def)
1076 {
1077 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
1078 if (def->num_components > 1) {
1079 type = LLVMVectorType(type, def->num_components);
1080 }
1081 return type;
1082 }
1083
1084 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
1085 {
1086 assert(src.is_ssa);
1087 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1088 return (LLVMValueRef)entry->data;
1089 }
1090
1091
1092 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1093 struct nir_block *b)
1094 {
1095 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1096 return (LLVMBasicBlockRef)entry->data;
1097 }
1098
1099 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1100 nir_alu_src src,
1101 unsigned num_components)
1102 {
1103 LLVMValueRef value = get_src(ctx, src.src);
1104 bool need_swizzle = false;
1105
1106 assert(value);
1107 LLVMTypeRef type = LLVMTypeOf(value);
1108 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1109 ? LLVMGetVectorSize(type)
1110 : 1;
1111
1112 for (unsigned i = 0; i < num_components; ++i) {
1113 assert(src.swizzle[i] < src_components);
1114 if (src.swizzle[i] != i)
1115 need_swizzle = true;
1116 }
1117
1118 if (need_swizzle || num_components != src_components) {
1119 LLVMValueRef masks[] = {
1120 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1121 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1122 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1123 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1124
1125 if (src_components > 1 && num_components == 1) {
1126 value = LLVMBuildExtractElement(ctx->builder, value,
1127 masks[0], "");
1128 } else if (src_components == 1 && num_components > 1) {
1129 LLVMValueRef values[] = {value, value, value, value};
1130 value = ac_build_gather_values(&ctx->ac, values, num_components);
1131 } else {
1132 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1133 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1134 swizzle, "");
1135 }
1136 }
1137 assert(!src.negate);
1138 assert(!src.abs);
1139 return value;
1140 }
1141
1142 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
1143 LLVMIntPredicate pred, LLVMValueRef src0,
1144 LLVMValueRef src1)
1145 {
1146 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1147 return LLVMBuildSelect(ctx->builder, result,
1148 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1149 LLVMConstInt(ctx->i32, 0, false), "");
1150 }
1151
1152 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
1153 LLVMRealPredicate pred, LLVMValueRef src0,
1154 LLVMValueRef src1)
1155 {
1156 LLVMValueRef result;
1157 src0 = to_float(ctx, src0);
1158 src1 = to_float(ctx, src1);
1159 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1160 return LLVMBuildSelect(ctx->builder, result,
1161 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1162 LLVMConstInt(ctx->i32, 0, false), "");
1163 }
1164
1165 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
1166 const char *intrin,
1167 LLVMTypeRef result_type,
1168 LLVMValueRef src0)
1169 {
1170 char name[64];
1171 LLVMValueRef params[] = {
1172 to_float(ctx, src0),
1173 };
1174
1175 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1176 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1177 }
1178
1179 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
1180 const char *intrin,
1181 LLVMTypeRef result_type,
1182 LLVMValueRef src0, LLVMValueRef src1)
1183 {
1184 char name[64];
1185 LLVMValueRef params[] = {
1186 to_float(ctx, src0),
1187 to_float(ctx, src1),
1188 };
1189
1190 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1191 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1192 }
1193
1194 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
1195 const char *intrin,
1196 LLVMTypeRef result_type,
1197 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1198 {
1199 char name[64];
1200 LLVMValueRef params[] = {
1201 to_float(ctx, src0),
1202 to_float(ctx, src1),
1203 to_float(ctx, src2),
1204 };
1205
1206 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1207 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1208 }
1209
1210 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
1211 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1212 {
1213 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1214 ctx->i32zero, "");
1215 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1216 }
1217
1218 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1219 LLVMValueRef src0)
1220 {
1221 LLVMValueRef params[2] = {
1222 src0,
1223
1224 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1225 * add special code to check for x=0. The reason is that
1226 * the LLVM behavior for x=0 is different from what we
1227 * need here.
1228 *
1229 * The hardware already implements the correct behavior.
1230 */
1231 LLVMConstInt(ctx->i32, 1, false),
1232 };
1233 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1234 }
1235
1236 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1237 LLVMValueRef src0)
1238 {
1239 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1240 }
1241
1242 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1243 LLVMValueRef src0)
1244 {
1245 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1246 }
1247
1248 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1249 LLVMIntPredicate pred,
1250 LLVMValueRef src0, LLVMValueRef src1)
1251 {
1252 return LLVMBuildSelect(ctx->builder,
1253 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1254 src0,
1255 src1, "");
1256
1257 }
1258 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1259 LLVMValueRef src0)
1260 {
1261 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1262 LLVMBuildNeg(ctx->builder, src0, ""));
1263 }
1264
1265 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1266 LLVMValueRef src0)
1267 {
1268 LLVMValueRef cmp, val;
1269
1270 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1271 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1272 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1273 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1274 return val;
1275 }
1276
1277 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1278 LLVMValueRef src0)
1279 {
1280 LLVMValueRef cmp, val;
1281
1282 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1283 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1284 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1285 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1286 return val;
1287 }
1288
1289 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1290 LLVMValueRef src0)
1291 {
1292 const char *intr = "llvm.floor.f32";
1293 LLVMValueRef fsrc0 = to_float(ctx, src0);
1294 LLVMValueRef params[] = {
1295 fsrc0,
1296 };
1297 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1298 ctx->f32, params, 1,
1299 AC_FUNC_ATTR_READNONE);
1300 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1301 }
1302
1303 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1304 const char *intrin,
1305 LLVMValueRef src0, LLVMValueRef src1)
1306 {
1307 LLVMTypeRef ret_type;
1308 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1309 LLVMValueRef res;
1310 LLVMValueRef params[] = { src0, src1 };
1311 ret_type = LLVMStructTypeInContext(ctx->context, types,
1312 2, true);
1313
1314 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1315 params, 2, AC_FUNC_ATTR_READNONE);
1316
1317 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1318 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1319 return res;
1320 }
1321
1322 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1323 LLVMValueRef src0)
1324 {
1325 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1326 }
1327
1328 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1329 LLVMValueRef src0)
1330 {
1331 LLVMValueRef result;
1332 LLVMValueRef cond;
1333
1334 src0 = to_float(ctx, src0);
1335 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1336
1337 /* TODO SI/CIK options here */
1338 if (ctx->options->chip_class >= VI) {
1339 LLVMValueRef args[2];
1340 /* Check if the result is a denormal - and flush to 0 if so. */
1341 args[0] = result;
1342 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1343 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1344 }
1345
1346 /* need to convert back up to f32 */
1347 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1348
1349 if (ctx->options->chip_class >= VI)
1350 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1351
1352 return result;
1353 }
1354
1355 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1356 LLVMValueRef src0, LLVMValueRef src1)
1357 {
1358 LLVMValueRef dst64, result;
1359 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1360 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1361
1362 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1363 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1364 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1365 return result;
1366 }
1367
1368 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1369 LLVMValueRef src0, LLVMValueRef src1)
1370 {
1371 LLVMValueRef dst64, result;
1372 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1373 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1374
1375 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1376 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1377 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1378 return result;
1379 }
1380
1381 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1382 bool is_signed,
1383 LLVMValueRef srcs[3])
1384 {
1385 LLVMValueRef result;
1386 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1387
1388 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1389 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1390 return result;
1391 }
1392
1393 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1394 LLVMValueRef src0, LLVMValueRef src1,
1395 LLVMValueRef src2, LLVMValueRef src3)
1396 {
1397 LLVMValueRef bfi_args[3], result;
1398
1399 bfi_args[0] = LLVMBuildShl(ctx->builder,
1400 LLVMBuildSub(ctx->builder,
1401 LLVMBuildShl(ctx->builder,
1402 ctx->i32one,
1403 src3, ""),
1404 ctx->i32one, ""),
1405 src2, "");
1406 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1407 bfi_args[2] = src0;
1408
1409 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1410
1411 /* Calculate:
1412 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1413 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1414 */
1415 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1416 LLVMBuildAnd(ctx->builder, bfi_args[0],
1417 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1418
1419 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1420 return result;
1421 }
1422
1423 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1424 LLVMValueRef src0)
1425 {
1426 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1427 int i;
1428 LLVMValueRef comp[2];
1429
1430 src0 = to_float(ctx, src0);
1431 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1432 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1433 for (i = 0; i < 2; i++) {
1434 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1435 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1436 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1437 }
1438
1439 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1440 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1441
1442 return comp[0];
1443 }
1444
1445 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1446 LLVMValueRef src0)
1447 {
1448 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1449 LLVMValueRef temps[2], result, val;
1450 int i;
1451
1452 for (i = 0; i < 2; i++) {
1453 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1454 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1455 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1456 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1457 }
1458
1459 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1460 ctx->i32zero, "");
1461 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1462 ctx->i32one, "");
1463 return result;
1464 }
1465
1466 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1467 nir_op op,
1468 LLVMValueRef src0)
1469 {
1470 unsigned mask;
1471 int idx;
1472 LLVMValueRef result;
1473 ctx->has_ddxy = true;
1474
1475 if (!ctx->lds && !ctx->has_ds_bpermute)
1476 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1477 LLVMArrayType(ctx->i32, 64),
1478 "ddxy_lds", LOCAL_ADDR_SPACE);
1479
1480 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1481 mask = AC_TID_MASK_LEFT;
1482 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1483 mask = AC_TID_MASK_TOP;
1484 else
1485 mask = AC_TID_MASK_TOP_LEFT;
1486
1487 /* for DDX we want to next X pixel, DDY next Y pixel. */
1488 if (op == nir_op_fddx_fine ||
1489 op == nir_op_fddx_coarse ||
1490 op == nir_op_fddx)
1491 idx = 1;
1492 else
1493 idx = 2;
1494
1495 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1496 mask, idx, ctx->lds,
1497 src0);
1498 return result;
1499 }
1500
1501 /*
1502 * this takes an I,J coordinate pair,
1503 * and works out the X and Y derivatives.
1504 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1505 */
1506 static LLVMValueRef emit_ddxy_interp(
1507 struct nir_to_llvm_context *ctx,
1508 LLVMValueRef interp_ij)
1509 {
1510 LLVMValueRef result[4], a;
1511 unsigned i;
1512
1513 for (i = 0; i < 2; i++) {
1514 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1515 LLVMConstInt(ctx->i32, i, false), "");
1516 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1517 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1518 }
1519 return ac_build_gather_values(&ctx->ac, result, 4);
1520 }
1521
1522 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1523 {
1524 LLVMValueRef src[4], result = NULL;
1525 unsigned num_components = instr->dest.dest.ssa.num_components;
1526 unsigned src_components;
1527 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1528
1529 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1530 switch (instr->op) {
1531 case nir_op_vec2:
1532 case nir_op_vec3:
1533 case nir_op_vec4:
1534 src_components = 1;
1535 break;
1536 case nir_op_pack_half_2x16:
1537 src_components = 2;
1538 break;
1539 case nir_op_unpack_half_2x16:
1540 src_components = 1;
1541 break;
1542 default:
1543 src_components = num_components;
1544 break;
1545 }
1546 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1547 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1548
1549 switch (instr->op) {
1550 case nir_op_fmov:
1551 case nir_op_imov:
1552 result = src[0];
1553 break;
1554 case nir_op_fneg:
1555 src[0] = to_float(ctx, src[0]);
1556 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1557 break;
1558 case nir_op_ineg:
1559 result = LLVMBuildNeg(ctx->builder, src[0], "");
1560 break;
1561 case nir_op_inot:
1562 result = LLVMBuildNot(ctx->builder, src[0], "");
1563 break;
1564 case nir_op_iadd:
1565 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1566 break;
1567 case nir_op_fadd:
1568 src[0] = to_float(ctx, src[0]);
1569 src[1] = to_float(ctx, src[1]);
1570 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1571 break;
1572 case nir_op_fsub:
1573 src[0] = to_float(ctx, src[0]);
1574 src[1] = to_float(ctx, src[1]);
1575 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1576 break;
1577 case nir_op_isub:
1578 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1579 break;
1580 case nir_op_imul:
1581 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1582 break;
1583 case nir_op_imod:
1584 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1585 break;
1586 case nir_op_umod:
1587 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1588 break;
1589 case nir_op_fmod:
1590 src[0] = to_float(ctx, src[0]);
1591 src[1] = to_float(ctx, src[1]);
1592 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1593 result = emit_intrin_1f_param(ctx, "llvm.floor",
1594 to_float_type(ctx, def_type), result);
1595 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1596 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1597 break;
1598 case nir_op_frem:
1599 src[0] = to_float(ctx, src[0]);
1600 src[1] = to_float(ctx, src[1]);
1601 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1602 break;
1603 case nir_op_irem:
1604 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1605 break;
1606 case nir_op_idiv:
1607 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1608 break;
1609 case nir_op_udiv:
1610 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1611 break;
1612 case nir_op_fmul:
1613 src[0] = to_float(ctx, src[0]);
1614 src[1] = to_float(ctx, src[1]);
1615 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1616 break;
1617 case nir_op_fdiv:
1618 src[0] = to_float(ctx, src[0]);
1619 src[1] = to_float(ctx, src[1]);
1620 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1621 break;
1622 case nir_op_frcp:
1623 src[0] = to_float(ctx, src[0]);
1624 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1625 break;
1626 case nir_op_iand:
1627 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1628 break;
1629 case nir_op_ior:
1630 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1631 break;
1632 case nir_op_ixor:
1633 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1634 break;
1635 case nir_op_ishl:
1636 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1637 break;
1638 case nir_op_ishr:
1639 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1640 break;
1641 case nir_op_ushr:
1642 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1643 break;
1644 case nir_op_ilt:
1645 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1646 break;
1647 case nir_op_ine:
1648 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1649 break;
1650 case nir_op_ieq:
1651 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1652 break;
1653 case nir_op_ige:
1654 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1655 break;
1656 case nir_op_ult:
1657 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1658 break;
1659 case nir_op_uge:
1660 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1661 break;
1662 case nir_op_feq:
1663 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1664 break;
1665 case nir_op_fne:
1666 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1667 break;
1668 case nir_op_flt:
1669 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1670 break;
1671 case nir_op_fge:
1672 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1673 break;
1674 case nir_op_fabs:
1675 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1676 to_float_type(ctx, def_type), src[0]);
1677 break;
1678 case nir_op_iabs:
1679 result = emit_iabs(ctx, src[0]);
1680 break;
1681 case nir_op_imax:
1682 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1683 break;
1684 case nir_op_imin:
1685 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1686 break;
1687 case nir_op_umax:
1688 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1689 break;
1690 case nir_op_umin:
1691 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1692 break;
1693 case nir_op_isign:
1694 result = emit_isign(ctx, src[0]);
1695 break;
1696 case nir_op_fsign:
1697 src[0] = to_float(ctx, src[0]);
1698 result = emit_fsign(ctx, src[0]);
1699 break;
1700 case nir_op_ffloor:
1701 result = emit_intrin_1f_param(ctx, "llvm.floor",
1702 to_float_type(ctx, def_type), src[0]);
1703 break;
1704 case nir_op_ftrunc:
1705 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1706 to_float_type(ctx, def_type), src[0]);
1707 break;
1708 case nir_op_fceil:
1709 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1710 to_float_type(ctx, def_type), src[0]);
1711 break;
1712 case nir_op_fround_even:
1713 result = emit_intrin_1f_param(ctx, "llvm.rint",
1714 to_float_type(ctx, def_type),src[0]);
1715 break;
1716 case nir_op_ffract:
1717 result = emit_ffract(ctx, src[0]);
1718 break;
1719 case nir_op_fsin:
1720 result = emit_intrin_1f_param(ctx, "llvm.sin",
1721 to_float_type(ctx, def_type), src[0]);
1722 break;
1723 case nir_op_fcos:
1724 result = emit_intrin_1f_param(ctx, "llvm.cos",
1725 to_float_type(ctx, def_type), src[0]);
1726 break;
1727 case nir_op_fsqrt:
1728 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1729 to_float_type(ctx, def_type), src[0]);
1730 break;
1731 case nir_op_fexp2:
1732 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1733 to_float_type(ctx, def_type), src[0]);
1734 break;
1735 case nir_op_flog2:
1736 result = emit_intrin_1f_param(ctx, "llvm.log2",
1737 to_float_type(ctx, def_type), src[0]);
1738 break;
1739 case nir_op_frsq:
1740 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1741 to_float_type(ctx, def_type), src[0]);
1742 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1743 break;
1744 case nir_op_fpow:
1745 result = emit_intrin_2f_param(ctx, "llvm.pow",
1746 to_float_type(ctx, def_type), src[0], src[1]);
1747 break;
1748 case nir_op_fmax:
1749 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1750 to_float_type(ctx, def_type), src[0], src[1]);
1751 if (instr->dest.dest.ssa.bit_size == 32)
1752 result = emit_intrin_1f_param(ctx, "llvm.canonicalize",
1753 to_float_type(ctx, def_type),
1754 result);
1755 break;
1756 case nir_op_fmin:
1757 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1758 to_float_type(ctx, def_type), src[0], src[1]);
1759 if (instr->dest.dest.ssa.bit_size == 32)
1760 result = emit_intrin_1f_param(ctx, "llvm.canonicalize",
1761 to_float_type(ctx, def_type),
1762 result);
1763 break;
1764 case nir_op_ffma:
1765 result = emit_intrin_3f_param(ctx, "llvm.fma",
1766 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1767 break;
1768 case nir_op_ibitfield_extract:
1769 result = emit_bitfield_extract(ctx, true, src);
1770 break;
1771 case nir_op_ubitfield_extract:
1772 result = emit_bitfield_extract(ctx, false, src);
1773 break;
1774 case nir_op_bitfield_insert:
1775 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1776 break;
1777 case nir_op_bitfield_reverse:
1778 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1779 break;
1780 case nir_op_bit_count:
1781 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1782 break;
1783 case nir_op_vec2:
1784 case nir_op_vec3:
1785 case nir_op_vec4:
1786 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1787 src[i] = to_integer(ctx, src[i]);
1788 result = ac_build_gather_values(&ctx->ac, src, num_components);
1789 break;
1790 case nir_op_f2i32:
1791 case nir_op_f2i64:
1792 src[0] = to_float(ctx, src[0]);
1793 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1794 break;
1795 case nir_op_f2u32:
1796 case nir_op_f2u64:
1797 src[0] = to_float(ctx, src[0]);
1798 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1799 break;
1800 case nir_op_i2f32:
1801 case nir_op_i2f64:
1802 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1803 break;
1804 case nir_op_u2f32:
1805 case nir_op_u2f64:
1806 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1807 break;
1808 case nir_op_f2f64:
1809 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1810 break;
1811 case nir_op_f2f32:
1812 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1813 break;
1814 case nir_op_u2u32:
1815 case nir_op_u2u64:
1816 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1817 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1818 else
1819 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1820 break;
1821 case nir_op_i2i32:
1822 case nir_op_i2i64:
1823 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1824 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1825 else
1826 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1827 break;
1828 case nir_op_bcsel:
1829 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1830 break;
1831 case nir_op_find_lsb:
1832 result = emit_find_lsb(ctx, src[0]);
1833 break;
1834 case nir_op_ufind_msb:
1835 result = emit_ufind_msb(ctx, src[0]);
1836 break;
1837 case nir_op_ifind_msb:
1838 result = emit_ifind_msb(ctx, src[0]);
1839 break;
1840 case nir_op_uadd_carry:
1841 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1842 break;
1843 case nir_op_usub_borrow:
1844 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1845 break;
1846 case nir_op_b2f:
1847 result = emit_b2f(ctx, src[0]);
1848 break;
1849 case nir_op_fquantize2f16:
1850 result = emit_f2f16(ctx, src[0]);
1851 break;
1852 case nir_op_umul_high:
1853 result = emit_umul_high(ctx, src[0], src[1]);
1854 break;
1855 case nir_op_imul_high:
1856 result = emit_imul_high(ctx, src[0], src[1]);
1857 break;
1858 case nir_op_pack_half_2x16:
1859 result = emit_pack_half_2x16(ctx, src[0]);
1860 break;
1861 case nir_op_unpack_half_2x16:
1862 result = emit_unpack_half_2x16(ctx, src[0]);
1863 break;
1864 case nir_op_fddx:
1865 case nir_op_fddy:
1866 case nir_op_fddx_fine:
1867 case nir_op_fddy_fine:
1868 case nir_op_fddx_coarse:
1869 case nir_op_fddy_coarse:
1870 result = emit_ddxy(ctx, instr->op, src[0]);
1871 break;
1872 default:
1873 fprintf(stderr, "Unknown NIR alu instr: ");
1874 nir_print_instr(&instr->instr, stderr);
1875 fprintf(stderr, "\n");
1876 abort();
1877 }
1878
1879 if (result) {
1880 assert(instr->dest.dest.is_ssa);
1881 result = to_integer(ctx, result);
1882 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1883 result);
1884 }
1885 }
1886
1887 static void visit_load_const(struct nir_to_llvm_context *ctx,
1888 nir_load_const_instr *instr)
1889 {
1890 LLVMValueRef values[4], value = NULL;
1891 LLVMTypeRef element_type =
1892 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1893
1894 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1895 switch (instr->def.bit_size) {
1896 case 32:
1897 values[i] = LLVMConstInt(element_type,
1898 instr->value.u32[i], false);
1899 break;
1900 case 64:
1901 values[i] = LLVMConstInt(element_type,
1902 instr->value.u64[i], false);
1903 break;
1904 default:
1905 fprintf(stderr,
1906 "unsupported nir load_const bit_size: %d\n",
1907 instr->def.bit_size);
1908 abort();
1909 }
1910 }
1911 if (instr->def.num_components > 1) {
1912 value = LLVMConstVector(values, instr->def.num_components);
1913 } else
1914 value = values[0];
1915
1916 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1917 }
1918
1919 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1920 LLVMTypeRef type)
1921 {
1922 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1923 return LLVMBuildBitCast(ctx->builder, ptr,
1924 LLVMPointerType(type, addr_space), "");
1925 }
1926
1927 static LLVMValueRef
1928 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1929 {
1930 LLVMValueRef size =
1931 LLVMBuildExtractElement(ctx->builder, descriptor,
1932 LLVMConstInt(ctx->i32, 2, false), "");
1933
1934 /* VI only */
1935 if (ctx->options->chip_class >= VI && in_elements) {
1936 /* On VI, the descriptor contains the size in bytes,
1937 * but TXQ must return the size in elements.
1938 * The stride is always non-zero for resources using TXQ.
1939 */
1940 LLVMValueRef stride =
1941 LLVMBuildExtractElement(ctx->builder, descriptor,
1942 LLVMConstInt(ctx->i32, 1, false), "");
1943 stride = LLVMBuildLShr(ctx->builder, stride,
1944 LLVMConstInt(ctx->i32, 16, false), "");
1945 stride = LLVMBuildAnd(ctx->builder, stride,
1946 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1947
1948 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1949 }
1950 return size;
1951 }
1952
1953 /**
1954 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1955 * intrinsic names).
1956 */
1957 static void build_int_type_name(
1958 LLVMTypeRef type,
1959 char *buf, unsigned bufsize)
1960 {
1961 assert(bufsize >= 6);
1962
1963 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1964 snprintf(buf, bufsize, "v%ui32",
1965 LLVMGetVectorSize(type));
1966 else
1967 strcpy(buf, "i32");
1968 }
1969
1970 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1971 struct ac_image_args *args,
1972 nir_tex_instr *instr)
1973 {
1974 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1975 LLVMValueRef coord = args->addr;
1976 LLVMValueRef half_texel[2];
1977 LLVMValueRef compare_cube_wa;
1978 LLVMValueRef result;
1979 int c;
1980 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1981
1982 //TODO Rect
1983 {
1984 struct ac_image_args txq_args = { 0 };
1985
1986 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1987 txq_args.opcode = ac_image_get_resinfo;
1988 txq_args.dmask = 0xf;
1989 txq_args.addr = ctx->i32zero;
1990 txq_args.resource = args->resource;
1991 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1992
1993 for (c = 0; c < 2; c++) {
1994 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1995 LLVMConstInt(ctx->i32, c, false), "");
1996 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1997 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1998 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1999 LLVMConstReal(ctx->f32, -0.5), "");
2000 }
2001 }
2002
2003 LLVMValueRef orig_coords = args->addr;
2004
2005 for (c = 0; c < 2; c++) {
2006 LLVMValueRef tmp;
2007 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2008 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2009 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2010 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2011 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2012 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2013 }
2014
2015
2016 /*
2017 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2018 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2019 * workaround by sampling using a scaled type and converting.
2020 * This is taken from amdgpu-pro shaders.
2021 */
2022 /* NOTE this produces some ugly code compared to amdgpu-pro,
2023 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2024 * and then reads them back. -pro generates two selects,
2025 * one s_cmp for the descriptor rewriting
2026 * one v_cmp for the coordinate and result changes.
2027 */
2028 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2029 LLVMValueRef tmp, tmp2;
2030
2031 /* workaround 8/8/8/8 uint/sint cube gather bug */
2032 /* first detect it then change to a scaled read and f2i */
2033 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
2034 tmp2 = tmp;
2035
2036 /* extract the DATA_FORMAT */
2037 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
2038 LLVMConstInt(ctx->i32, 6, false), false);
2039
2040 /* is the DATA_FORMAT == 8_8_8_8 */
2041 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2042
2043 if (stype == GLSL_TYPE_UINT)
2044 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2045 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2046 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2047 else
2048 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2049 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2050 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2051
2052 /* replace the NUM FORMAT in the descriptor */
2053 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2054 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2055
2056 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
2057
2058 /* don't modify the coordinates for this case */
2059 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2060 }
2061 args->addr = coord;
2062 result = ac_build_image_opcode(&ctx->ac, args);
2063
2064 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2065 LLVMValueRef tmp, tmp2;
2066
2067 /* if the cube workaround is in place, f2i the result. */
2068 for (c = 0; c < 4; c++) {
2069 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2070 if (stype == GLSL_TYPE_UINT)
2071 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2072 else
2073 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2074 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2075 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2076 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2077 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2078 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2079 }
2080 }
2081 return result;
2082 }
2083
2084 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
2085 nir_tex_instr *instr,
2086 bool lod_is_zero,
2087 struct ac_image_args *args)
2088 {
2089 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2090 return ac_build_buffer_load_format(&ctx->ac,
2091 args->resource,
2092 args->addr,
2093 LLVMConstInt(ctx->i32, 0, false),
2094 true);
2095 }
2096
2097 args->opcode = ac_image_sample;
2098 args->compare = instr->is_shadow;
2099
2100 switch (instr->op) {
2101 case nir_texop_txf:
2102 case nir_texop_txf_ms:
2103 case nir_texop_samples_identical:
2104 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2105 args->compare = false;
2106 args->offset = false;
2107 break;
2108 case nir_texop_txb:
2109 args->bias = true;
2110 break;
2111 case nir_texop_txl:
2112 if (lod_is_zero)
2113 args->level_zero = true;
2114 else
2115 args->lod = true;
2116 break;
2117 case nir_texop_txs:
2118 case nir_texop_query_levels:
2119 args->opcode = ac_image_get_resinfo;
2120 break;
2121 case nir_texop_tex:
2122 if (ctx->stage != MESA_SHADER_FRAGMENT)
2123 args->level_zero = true;
2124 break;
2125 case nir_texop_txd:
2126 args->deriv = true;
2127 break;
2128 case nir_texop_tg4:
2129 args->opcode = ac_image_gather4;
2130 args->level_zero = true;
2131 break;
2132 case nir_texop_lod:
2133 args->opcode = ac_image_get_lod;
2134 args->compare = false;
2135 args->offset = false;
2136 break;
2137 default:
2138 break;
2139 }
2140
2141 if (instr->op == nir_texop_tg4) {
2142 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2143 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2144 return radv_lower_gather4_integer(ctx, args, instr);
2145 }
2146 }
2147 return ac_build_image_opcode(&ctx->ac, args);
2148 }
2149
2150 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2151 nir_intrinsic_instr *instr)
2152 {
2153 LLVMValueRef index = get_src(ctx, instr->src[0]);
2154 unsigned desc_set = nir_intrinsic_desc_set(instr);
2155 unsigned binding = nir_intrinsic_binding(instr);
2156 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2157 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2158 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2159 unsigned base_offset = layout->binding[binding].offset;
2160 LLVMValueRef offset, stride;
2161
2162 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2163 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2164 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2165 layout->binding[binding].dynamic_offset_offset;
2166 desc_ptr = ctx->push_constants;
2167 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2168 stride = LLVMConstInt(ctx->i32, 16, false);
2169 } else
2170 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2171
2172 offset = LLVMConstInt(ctx->i32, base_offset, false);
2173 index = LLVMBuildMul(ctx->builder, index, stride, "");
2174 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2175
2176 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2177 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2178 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2179
2180 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2181 }
2182
2183 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2184 nir_intrinsic_instr *instr)
2185 {
2186 LLVMValueRef ptr, addr;
2187
2188 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2189 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2190
2191 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2192 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2193
2194 return LLVMBuildLoad(ctx->builder, ptr, "");
2195 }
2196
2197 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2198 nir_intrinsic_instr *instr)
2199 {
2200 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2201
2202 return get_buffer_size(ctx, desc, false);
2203 }
2204 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2205 nir_intrinsic_instr *instr)
2206 {
2207 const char *store_name;
2208 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2209 LLVMTypeRef data_type = ctx->f32;
2210 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2211 int components_32bit = elem_size_mult * instr->num_components;
2212 unsigned writemask = nir_intrinsic_write_mask(instr);
2213 LLVMValueRef base_data, base_offset;
2214 LLVMValueRef params[6];
2215
2216 if (ctx->stage == MESA_SHADER_FRAGMENT)
2217 ctx->shader_info->fs.writes_memory = true;
2218
2219 params[1] = get_src(ctx, instr->src[1]);
2220 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2221 params[4] = ctx->i1false; /* glc */
2222 params[5] = ctx->i1false; /* slc */
2223
2224 if (components_32bit > 1)
2225 data_type = LLVMVectorType(ctx->f32, components_32bit);
2226
2227 base_data = to_float(ctx, src_data);
2228 base_data = trim_vector(ctx, base_data, instr->num_components);
2229 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2230 data_type, "");
2231 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2232 while (writemask) {
2233 int start, count;
2234 LLVMValueRef data;
2235 LLVMValueRef offset;
2236 LLVMValueRef tmp;
2237 u_bit_scan_consecutive_range(&writemask, &start, &count);
2238
2239 /* Due to an LLVM limitation, split 3-element writes
2240 * into a 2-element and a 1-element write. */
2241 if (count == 3) {
2242 writemask |= 1 << (start + 2);
2243 count = 2;
2244 }
2245
2246 start *= elem_size_mult;
2247 count *= elem_size_mult;
2248
2249 if (count > 4) {
2250 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2251 count = 4;
2252 }
2253
2254 if (count == 4) {
2255 store_name = "llvm.amdgcn.buffer.store.v4f32";
2256 data = base_data;
2257 } else if (count == 2) {
2258 tmp = LLVMBuildExtractElement(ctx->builder,
2259 base_data, LLVMConstInt(ctx->i32, start, false), "");
2260 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2261 ctx->i32zero, "");
2262
2263 tmp = LLVMBuildExtractElement(ctx->builder,
2264 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2265 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2266 ctx->i32one, "");
2267 store_name = "llvm.amdgcn.buffer.store.v2f32";
2268
2269 } else {
2270 assert(count == 1);
2271 if (get_llvm_num_components(base_data) > 1)
2272 data = LLVMBuildExtractElement(ctx->builder, base_data,
2273 LLVMConstInt(ctx->i32, start, false), "");
2274 else
2275 data = base_data;
2276 store_name = "llvm.amdgcn.buffer.store.f32";
2277 }
2278
2279 offset = base_offset;
2280 if (start != 0) {
2281 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2282 }
2283 params[0] = data;
2284 params[3] = offset;
2285 ac_build_intrinsic(&ctx->ac, store_name,
2286 ctx->voidt, params, 6, 0);
2287 }
2288 }
2289
2290 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2291 nir_intrinsic_instr *instr)
2292 {
2293 const char *name;
2294 LLVMValueRef params[6];
2295 int arg_count = 0;
2296 if (ctx->stage == MESA_SHADER_FRAGMENT)
2297 ctx->shader_info->fs.writes_memory = true;
2298
2299 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2300 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2301 }
2302 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2303 params[arg_count++] = get_src(ctx, instr->src[0]);
2304 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2305 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2306 params[arg_count++] = ctx->i1false; /* slc */
2307
2308 switch (instr->intrinsic) {
2309 case nir_intrinsic_ssbo_atomic_add:
2310 name = "llvm.amdgcn.buffer.atomic.add";
2311 break;
2312 case nir_intrinsic_ssbo_atomic_imin:
2313 name = "llvm.amdgcn.buffer.atomic.smin";
2314 break;
2315 case nir_intrinsic_ssbo_atomic_umin:
2316 name = "llvm.amdgcn.buffer.atomic.umin";
2317 break;
2318 case nir_intrinsic_ssbo_atomic_imax:
2319 name = "llvm.amdgcn.buffer.atomic.smax";
2320 break;
2321 case nir_intrinsic_ssbo_atomic_umax:
2322 name = "llvm.amdgcn.buffer.atomic.umax";
2323 break;
2324 case nir_intrinsic_ssbo_atomic_and:
2325 name = "llvm.amdgcn.buffer.atomic.and";
2326 break;
2327 case nir_intrinsic_ssbo_atomic_or:
2328 name = "llvm.amdgcn.buffer.atomic.or";
2329 break;
2330 case nir_intrinsic_ssbo_atomic_xor:
2331 name = "llvm.amdgcn.buffer.atomic.xor";
2332 break;
2333 case nir_intrinsic_ssbo_atomic_exchange:
2334 name = "llvm.amdgcn.buffer.atomic.swap";
2335 break;
2336 case nir_intrinsic_ssbo_atomic_comp_swap:
2337 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2338 break;
2339 default:
2340 abort();
2341 }
2342
2343 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2344 }
2345
2346 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2347 nir_intrinsic_instr *instr)
2348 {
2349 LLVMValueRef results[2];
2350 int load_components;
2351 int num_components = instr->num_components;
2352 if (instr->dest.ssa.bit_size == 64)
2353 num_components *= 2;
2354
2355 for (int i = 0; i < num_components; i += load_components) {
2356 load_components = MIN2(num_components - i, 4);
2357 const char *load_name;
2358 LLVMTypeRef data_type = ctx->f32;
2359 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2360 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2361
2362 if (load_components == 3)
2363 data_type = LLVMVectorType(ctx->f32, 4);
2364 else if (load_components > 1)
2365 data_type = LLVMVectorType(ctx->f32, load_components);
2366
2367 if (load_components >= 3)
2368 load_name = "llvm.amdgcn.buffer.load.v4f32";
2369 else if (load_components == 2)
2370 load_name = "llvm.amdgcn.buffer.load.v2f32";
2371 else if (load_components == 1)
2372 load_name = "llvm.amdgcn.buffer.load.f32";
2373 else
2374 unreachable("unhandled number of components");
2375
2376 LLVMValueRef params[] = {
2377 get_src(ctx, instr->src[0]),
2378 LLVMConstInt(ctx->i32, 0, false),
2379 offset,
2380 ctx->i1false,
2381 ctx->i1false,
2382 };
2383
2384 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2385
2386 }
2387
2388 LLVMValueRef ret = results[0];
2389 if (num_components > 4 || num_components == 3) {
2390 LLVMValueRef masks[] = {
2391 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2392 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2393 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2394 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2395 };
2396
2397 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2398 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2399 results[num_components > 4 ? 1 : 0], swizzle, "");
2400 }
2401
2402 return LLVMBuildBitCast(ctx->builder, ret,
2403 get_def_type(ctx, &instr->dest.ssa), "");
2404 }
2405
2406 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2407 nir_intrinsic_instr *instr)
2408 {
2409 LLVMValueRef results[8], ret;
2410 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2411 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2412 int num_components = instr->num_components;
2413
2414 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2415
2416 if (instr->dest.ssa.bit_size == 64)
2417 num_components *= 2;
2418
2419 for (unsigned i = 0; i < num_components; ++i) {
2420 LLVMValueRef params[] = {
2421 rsrc,
2422 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2423 offset, "")
2424 };
2425 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2426 params, 2,
2427 AC_FUNC_ATTR_READNONE |
2428 AC_FUNC_ATTR_LEGACY);
2429 }
2430
2431
2432 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2433 return LLVMBuildBitCast(ctx->builder, ret,
2434 get_def_type(ctx, &instr->dest.ssa), "");
2435 }
2436
2437 static void
2438 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2439 bool vs_in, unsigned *vertex_index_out,
2440 LLVMValueRef *vertex_index_ref,
2441 unsigned *const_out, LLVMValueRef *indir_out)
2442 {
2443 unsigned const_offset = 0;
2444 nir_deref *tail = &deref->deref;
2445 LLVMValueRef offset = NULL;
2446
2447 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2448 tail = tail->child;
2449 nir_deref_array *deref_array = nir_deref_as_array(tail);
2450 if (vertex_index_out)
2451 *vertex_index_out = deref_array->base_offset;
2452
2453 if (vertex_index_ref) {
2454 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2455 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2456 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2457 }
2458 *vertex_index_ref = vtx;
2459 }
2460 }
2461
2462 if (deref->var->data.compact) {
2463 assert(tail->child->deref_type == nir_deref_type_array);
2464 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2465 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2466 /* We always lower indirect dereferences for "compact" array vars. */
2467 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2468
2469 const_offset = deref_array->base_offset;
2470 goto out;
2471 }
2472
2473 while (tail->child != NULL) {
2474 const struct glsl_type *parent_type = tail->type;
2475 tail = tail->child;
2476
2477 if (tail->deref_type == nir_deref_type_array) {
2478 nir_deref_array *deref_array = nir_deref_as_array(tail);
2479 LLVMValueRef index, stride, local_offset;
2480 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2481
2482 const_offset += size * deref_array->base_offset;
2483 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2484 continue;
2485
2486 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2487 index = get_src(ctx, deref_array->indirect);
2488 stride = LLVMConstInt(ctx->i32, size, 0);
2489 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2490
2491 if (offset)
2492 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2493 else
2494 offset = local_offset;
2495 } else if (tail->deref_type == nir_deref_type_struct) {
2496 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2497
2498 for (unsigned i = 0; i < deref_struct->index; i++) {
2499 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2500 const_offset += glsl_count_attribute_slots(ft, vs_in);
2501 }
2502 } else
2503 unreachable("unsupported deref type");
2504
2505 }
2506 out:
2507 if (const_offset && offset)
2508 offset = LLVMBuildAdd(ctx->builder, offset,
2509 LLVMConstInt(ctx->i32, const_offset, 0),
2510 "");
2511
2512 *const_out = const_offset;
2513 *indir_out = offset;
2514 }
2515
2516 static LLVMValueRef
2517 lds_load(struct nir_to_llvm_context *ctx,
2518 LLVMValueRef dw_addr)
2519 {
2520 LLVMValueRef value;
2521 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2522 return value;
2523 }
2524
2525 static void
2526 lds_store(struct nir_to_llvm_context *ctx,
2527 LLVMValueRef dw_addr, LLVMValueRef value)
2528 {
2529 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2530 ac_build_indexed_store(&ctx->ac, ctx->lds,
2531 dw_addr, value);
2532 }
2533
2534 /* The offchip buffer layout for TCS->TES is
2535 *
2536 * - attribute 0 of patch 0 vertex 0
2537 * - attribute 0 of patch 0 vertex 1
2538 * - attribute 0 of patch 0 vertex 2
2539 * ...
2540 * - attribute 0 of patch 1 vertex 0
2541 * - attribute 0 of patch 1 vertex 1
2542 * ...
2543 * - attribute 1 of patch 0 vertex 0
2544 * - attribute 1 of patch 0 vertex 1
2545 * ...
2546 * - per patch attribute 0 of patch 0
2547 * - per patch attribute 0 of patch 1
2548 * ...
2549 *
2550 * Note that every attribute has 4 components.
2551 */
2552 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2553 LLVMValueRef vertex_index,
2554 LLVMValueRef param_index)
2555 {
2556 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2557 LLVMValueRef param_stride, constant16;
2558 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2559
2560 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2561 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2562 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2563 num_patches, "");
2564
2565 constant16 = LLVMConstInt(ctx->i32, 16, false);
2566 if (vertex_index) {
2567 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2568 vertices_per_patch, "");
2569
2570 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2571 vertex_index, "");
2572
2573 param_stride = total_vertices;
2574 } else {
2575 base_addr = rel_patch_id;
2576 param_stride = num_patches;
2577 }
2578
2579 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2580 LLVMBuildMul(ctx->builder, param_index,
2581 param_stride, ""), "");
2582
2583 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2584
2585 if (!vertex_index) {
2586 LLVMValueRef patch_data_offset =
2587 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2588
2589 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2590 patch_data_offset, "");
2591 }
2592 return base_addr;
2593 }
2594
2595 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2596 unsigned param,
2597 unsigned const_index,
2598 bool is_compact,
2599 LLVMValueRef vertex_index,
2600 LLVMValueRef indir_index)
2601 {
2602 LLVMValueRef param_index;
2603
2604 if (indir_index)
2605 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2606 indir_index, "");
2607 else {
2608 if (const_index && !is_compact)
2609 param += const_index;
2610 param_index = LLVMConstInt(ctx->i32, param, false);
2611 }
2612 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2613 }
2614
2615 static void
2616 mark_tess_output(struct nir_to_llvm_context *ctx,
2617 bool is_patch, uint32_t param)
2618
2619 {
2620 if (is_patch) {
2621 ctx->tess_patch_outputs_written |= (1ull << param);
2622 } else
2623 ctx->tess_outputs_written |= (1ull << param);
2624 }
2625
2626 static LLVMValueRef
2627 get_dw_address(struct nir_to_llvm_context *ctx,
2628 LLVMValueRef dw_addr,
2629 unsigned param,
2630 unsigned const_index,
2631 bool compact_const_index,
2632 LLVMValueRef vertex_index,
2633 LLVMValueRef stride,
2634 LLVMValueRef indir_index)
2635
2636 {
2637
2638 if (vertex_index) {
2639 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2640 LLVMBuildMul(ctx->builder,
2641 vertex_index,
2642 stride, ""), "");
2643 }
2644
2645 if (indir_index)
2646 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2647 LLVMBuildMul(ctx->builder, indir_index,
2648 LLVMConstInt(ctx->i32, 4, false), ""), "");
2649 else if (const_index && !compact_const_index)
2650 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2651 LLVMConstInt(ctx->i32, const_index, false), "");
2652
2653 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2654 LLVMConstInt(ctx->i32, param * 4, false), "");
2655
2656 if (const_index && compact_const_index)
2657 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2658 LLVMConstInt(ctx->i32, const_index, false), "");
2659 return dw_addr;
2660 }
2661
2662 static LLVMValueRef
2663 load_tcs_input(struct nir_to_llvm_context *ctx,
2664 nir_intrinsic_instr *instr)
2665 {
2666 LLVMValueRef dw_addr, stride;
2667 unsigned const_index;
2668 LLVMValueRef vertex_index;
2669 LLVMValueRef indir_index;
2670 unsigned param;
2671 LLVMValueRef value[4], result;
2672 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2673 const bool is_compact = instr->variables[0]->var->data.compact;
2674 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2675 radv_get_deref_offset(ctx, instr->variables[0],
2676 false, NULL, per_vertex ? &vertex_index : NULL,
2677 &const_index, &indir_index);
2678
2679 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2680 dw_addr = get_tcs_in_current_patch_offset(ctx);
2681 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2682 indir_index);
2683
2684 for (unsigned i = 0; i < instr->num_components; i++) {
2685 value[i] = lds_load(ctx, dw_addr);
2686 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2687 ctx->i32one, "");
2688 }
2689 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2690 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2691 return result;
2692 }
2693
2694 static LLVMValueRef
2695 load_tcs_output(struct nir_to_llvm_context *ctx,
2696 nir_intrinsic_instr *instr)
2697 {
2698 LLVMValueRef dw_addr, stride;
2699 LLVMValueRef value[4], result;
2700 LLVMValueRef vertex_index = NULL;
2701 LLVMValueRef indir_index = NULL;
2702 unsigned const_index = 0;
2703 unsigned param;
2704 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2705 const bool is_compact = instr->variables[0]->var->data.compact;
2706 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2707 radv_get_deref_offset(ctx, instr->variables[0],
2708 false, NULL, per_vertex ? &vertex_index : NULL,
2709 &const_index, &indir_index);
2710
2711 if (!instr->variables[0]->var->data.patch) {
2712 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2713 dw_addr = get_tcs_out_current_patch_offset(ctx);
2714 } else {
2715 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2716 }
2717
2718 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2719 indir_index);
2720
2721 for (unsigned i = 0; i < instr->num_components; i++) {
2722 value[i] = lds_load(ctx, dw_addr);
2723 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2724 ctx->i32one, "");
2725 }
2726 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2727 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2728 return result;
2729 }
2730
2731 static void
2732 store_tcs_output(struct nir_to_llvm_context *ctx,
2733 nir_intrinsic_instr *instr,
2734 LLVMValueRef src,
2735 unsigned writemask)
2736 {
2737 LLVMValueRef stride, dw_addr;
2738 LLVMValueRef buf_addr = NULL;
2739 LLVMValueRef vertex_index = NULL;
2740 LLVMValueRef indir_index = NULL;
2741 unsigned const_index = 0;
2742 unsigned param;
2743 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2744 const bool is_compact = instr->variables[0]->var->data.compact;
2745
2746 radv_get_deref_offset(ctx, instr->variables[0],
2747 false, NULL, per_vertex ? &vertex_index : NULL,
2748 &const_index, &indir_index);
2749
2750 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2751 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2752 is_compact && const_index > 3) {
2753 const_index -= 3;
2754 param++;
2755 }
2756
2757 if (!instr->variables[0]->var->data.patch) {
2758 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2759 dw_addr = get_tcs_out_current_patch_offset(ctx);
2760 } else {
2761 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2762 }
2763
2764 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2765
2766 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2767 indir_index);
2768 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2769 vertex_index, indir_index);
2770
2771 unsigned base = is_compact ? const_index : 0;
2772 for (unsigned chan = 0; chan < 8; chan++) {
2773 bool is_tess_factor = false;
2774 if (!(writemask & (1 << chan)))
2775 continue;
2776 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2777
2778 lds_store(ctx, dw_addr, value);
2779
2780 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2781 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2782 is_tess_factor = true;
2783
2784 if (!is_tess_factor && writemask != 0xF)
2785 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2786 buf_addr, ctx->oc_lds,
2787 4 * (base + chan), 1, 0, true, false);
2788
2789 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2790 ctx->i32one, "");
2791 }
2792
2793 if (writemask == 0xF) {
2794 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2795 buf_addr, ctx->oc_lds,
2796 (base * 4), 1, 0, true, false);
2797 }
2798 }
2799
2800 static LLVMValueRef
2801 load_tes_input(struct nir_to_llvm_context *ctx,
2802 nir_intrinsic_instr *instr)
2803 {
2804 LLVMValueRef buf_addr;
2805 LLVMValueRef result;
2806 LLVMValueRef vertex_index = NULL;
2807 LLVMValueRef indir_index = NULL;
2808 unsigned const_index = 0;
2809 unsigned param;
2810 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2811 const bool is_compact = instr->variables[0]->var->data.compact;
2812
2813 radv_get_deref_offset(ctx, instr->variables[0],
2814 false, NULL, per_vertex ? &vertex_index : NULL,
2815 &const_index, &indir_index);
2816 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2817 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2818 is_compact && const_index > 3) {
2819 const_index -= 3;
2820 param++;
2821 }
2822 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2823 is_compact, vertex_index, indir_index);
2824
2825 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2826 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2827 result = trim_vector(ctx, result, instr->num_components);
2828 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2829 return result;
2830 }
2831
2832 static LLVMValueRef
2833 load_gs_input(struct nir_to_llvm_context *ctx,
2834 nir_intrinsic_instr *instr)
2835 {
2836 LLVMValueRef indir_index, vtx_offset;
2837 unsigned const_index;
2838 LLVMValueRef args[9];
2839 unsigned param, vtx_offset_param;
2840 LLVMValueRef value[4], result;
2841 unsigned vertex_index;
2842 radv_get_deref_offset(ctx, instr->variables[0],
2843 false, &vertex_index, NULL,
2844 &const_index, &indir_index);
2845 vtx_offset_param = vertex_index;
2846 assert(vtx_offset_param < 6);
2847 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2848 LLVMConstInt(ctx->i32, 4, false), "");
2849
2850 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2851 for (unsigned i = 0; i < instr->num_components; i++) {
2852
2853 args[0] = ctx->esgs_ring;
2854 args[1] = vtx_offset;
2855 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2856 args[3] = ctx->i32zero;
2857 args[4] = ctx->i32one; /* OFFEN */
2858 args[5] = ctx->i32zero; /* IDXEN */
2859 args[6] = ctx->i32one; /* GLC */
2860 args[7] = ctx->i32zero; /* SLC */
2861 args[8] = ctx->i32zero; /* TFE */
2862
2863 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2864 ctx->i32, args, 9,
2865 AC_FUNC_ATTR_READONLY |
2866 AC_FUNC_ATTR_LEGACY);
2867 }
2868 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2869
2870 return result;
2871 }
2872
2873 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2874 nir_intrinsic_instr *instr)
2875 {
2876 LLVMValueRef values[8];
2877 int idx = instr->variables[0]->var->data.driver_location;
2878 int ve = instr->dest.ssa.num_components;
2879 LLVMValueRef indir_index;
2880 LLVMValueRef ret;
2881 unsigned const_index;
2882 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2883 instr->variables[0]->var->data.mode == nir_var_shader_in;
2884 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2885 &const_index, &indir_index);
2886
2887 if (instr->dest.ssa.bit_size == 64)
2888 ve *= 2;
2889
2890 switch (instr->variables[0]->var->data.mode) {
2891 case nir_var_shader_in:
2892 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2893 return load_tcs_input(ctx, instr);
2894 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2895 return load_tes_input(ctx, instr);
2896 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2897 return load_gs_input(ctx, instr);
2898 }
2899 for (unsigned chan = 0; chan < ve; chan++) {
2900 if (indir_index) {
2901 unsigned count = glsl_count_attribute_slots(
2902 instr->variables[0]->var->type,
2903 ctx->stage == MESA_SHADER_VERTEX);
2904 count -= chan / 4;
2905 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2906 &ctx->ac, ctx->inputs + idx + chan, count,
2907 4, false);
2908
2909 values[chan] = LLVMBuildExtractElement(ctx->builder,
2910 tmp_vec,
2911 indir_index, "");
2912 } else
2913 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2914 }
2915 break;
2916 case nir_var_local:
2917 for (unsigned chan = 0; chan < ve; chan++) {
2918 if (indir_index) {
2919 unsigned count = glsl_count_attribute_slots(
2920 instr->variables[0]->var->type, false);
2921 count -= chan / 4;
2922 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2923 &ctx->ac, ctx->locals + idx + chan, count,
2924 4, true);
2925
2926 values[chan] = LLVMBuildExtractElement(ctx->builder,
2927 tmp_vec,
2928 indir_index, "");
2929 } else {
2930 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2931 }
2932 }
2933 break;
2934 case nir_var_shader_out:
2935 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2936 return load_tcs_output(ctx, instr);
2937 for (unsigned chan = 0; chan < ve; chan++) {
2938 if (indir_index) {
2939 unsigned count = glsl_count_attribute_slots(
2940 instr->variables[0]->var->type, false);
2941 count -= chan / 4;
2942 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2943 &ctx->ac, ctx->outputs + idx + chan, count,
2944 4, true);
2945
2946 values[chan] = LLVMBuildExtractElement(ctx->builder,
2947 tmp_vec,
2948 indir_index, "");
2949 } else {
2950 values[chan] = LLVMBuildLoad(ctx->builder,
2951 ctx->outputs[idx + chan + const_index * 4],
2952 "");
2953 }
2954 }
2955 break;
2956 case nir_var_shared: {
2957 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2958 LLVMValueRef derived_ptr;
2959
2960 if (indir_index)
2961 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2962
2963 for (unsigned chan = 0; chan < ve; chan++) {
2964 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2965 if (indir_index)
2966 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2967 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2968
2969 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2970 }
2971 break;
2972 }
2973 default:
2974 unreachable("unhandle variable mode");
2975 }
2976 ret = ac_build_gather_values(&ctx->ac, values, ve);
2977 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2978 }
2979
2980 static void
2981 visit_store_var(struct nir_to_llvm_context *ctx,
2982 nir_intrinsic_instr *instr)
2983 {
2984 LLVMValueRef temp_ptr, value;
2985 int idx = instr->variables[0]->var->data.driver_location;
2986 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2987 int writemask = instr->const_index[0];
2988 LLVMValueRef indir_index;
2989 unsigned const_index;
2990 radv_get_deref_offset(ctx, instr->variables[0], false,
2991 NULL, NULL, &const_index, &indir_index);
2992
2993 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2994 int old_writemask = writemask;
2995
2996 src = LLVMBuildBitCast(ctx->builder, src,
2997 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2998 "");
2999
3000 writemask = 0;
3001 for (unsigned chan = 0; chan < 4; chan++) {
3002 if (old_writemask & (1 << chan))
3003 writemask |= 3u << (2 * chan);
3004 }
3005 }
3006
3007 switch (instr->variables[0]->var->data.mode) {
3008 case nir_var_shader_out:
3009
3010 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3011 store_tcs_output(ctx, instr, src, writemask);
3012 return;
3013 }
3014
3015 for (unsigned chan = 0; chan < 8; chan++) {
3016 int stride = 4;
3017 if (!(writemask & (1 << chan)))
3018 continue;
3019
3020 value = llvm_extract_elem(ctx, src, chan);
3021
3022 if (instr->variables[0]->var->data.compact)
3023 stride = 1;
3024 if (indir_index) {
3025 unsigned count = glsl_count_attribute_slots(
3026 instr->variables[0]->var->type, false);
3027 count -= chan / 4;
3028 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3029 &ctx->ac, ctx->outputs + idx + chan, count,
3030 stride, true);
3031
3032 if (get_llvm_num_components(tmp_vec) > 1) {
3033 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3034 value, indir_index, "");
3035 } else
3036 tmp_vec = value;
3037 build_store_values_extended(ctx, ctx->outputs + idx + chan,
3038 count, stride, tmp_vec);
3039
3040 } else {
3041 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3042
3043 LLVMBuildStore(ctx->builder, value, temp_ptr);
3044 }
3045 }
3046 break;
3047 case nir_var_local:
3048 for (unsigned chan = 0; chan < 8; chan++) {
3049 if (!(writemask & (1 << chan)))
3050 continue;
3051
3052 value = llvm_extract_elem(ctx, src, chan);
3053 if (indir_index) {
3054 unsigned count = glsl_count_attribute_slots(
3055 instr->variables[0]->var->type, false);
3056 count -= chan / 4;
3057 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3058 &ctx->ac, ctx->locals + idx + chan, count,
3059 4, true);
3060
3061 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3062 value, indir_index, "");
3063 build_store_values_extended(ctx, ctx->locals + idx + chan,
3064 count, 4, tmp_vec);
3065 } else {
3066 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3067
3068 LLVMBuildStore(ctx->builder, value, temp_ptr);
3069 }
3070 }
3071 break;
3072 case nir_var_shared: {
3073 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3074
3075 if (indir_index)
3076 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
3077
3078 for (unsigned chan = 0; chan < 8; chan++) {
3079 if (!(writemask & (1 << chan)))
3080 continue;
3081 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
3082 LLVMValueRef derived_ptr;
3083
3084 if (indir_index)
3085 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
3086
3087 value = llvm_extract_elem(ctx, src, chan);
3088 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
3089 LLVMBuildStore(ctx->builder,
3090 to_integer(ctx, value), derived_ptr);
3091 }
3092 break;
3093 }
3094 default:
3095 break;
3096 }
3097 }
3098
3099 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3100 {
3101 switch (dim) {
3102 case GLSL_SAMPLER_DIM_BUF:
3103 return 1;
3104 case GLSL_SAMPLER_DIM_1D:
3105 return array ? 2 : 1;
3106 case GLSL_SAMPLER_DIM_2D:
3107 return array ? 3 : 2;
3108 case GLSL_SAMPLER_DIM_MS:
3109 return array ? 4 : 3;
3110 case GLSL_SAMPLER_DIM_3D:
3111 case GLSL_SAMPLER_DIM_CUBE:
3112 return 3;
3113 case GLSL_SAMPLER_DIM_RECT:
3114 case GLSL_SAMPLER_DIM_SUBPASS:
3115 return 2;
3116 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3117 return 3;
3118 default:
3119 break;
3120 }
3121 return 0;
3122 }
3123
3124
3125
3126 /* Adjust the sample index according to FMASK.
3127 *
3128 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3129 * which is the identity mapping. Each nibble says which physical sample
3130 * should be fetched to get that sample.
3131 *
3132 * For example, 0x11111100 means there are only 2 samples stored and
3133 * the second sample covers 3/4 of the pixel. When reading samples 0
3134 * and 1, return physical sample 0 (determined by the first two 0s
3135 * in FMASK), otherwise return physical sample 1.
3136 *
3137 * The sample index should be adjusted as follows:
3138 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3139 */
3140 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3141 LLVMValueRef coord_x, LLVMValueRef coord_y,
3142 LLVMValueRef coord_z,
3143 LLVMValueRef sample_index,
3144 LLVMValueRef fmask_desc_ptr)
3145 {
3146 LLVMValueRef fmask_load_address[4];
3147 LLVMValueRef res;
3148
3149 fmask_load_address[0] = coord_x;
3150 fmask_load_address[1] = coord_y;
3151 if (coord_z) {
3152 fmask_load_address[2] = coord_z;
3153 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3154 }
3155
3156 struct ac_image_args args = {0};
3157
3158 args.opcode = ac_image_load;
3159 args.da = coord_z ? true : false;
3160 args.resource = fmask_desc_ptr;
3161 args.dmask = 0xf;
3162 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3163
3164 res = ac_build_image_opcode(&ctx->ac, &args);
3165
3166 res = to_integer(ctx, res);
3167 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3168 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3169
3170 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3171 res,
3172 ctx->i32zero, "");
3173
3174 LLVMValueRef sample_index4 =
3175 LLVMBuildMul(ctx->builder, sample_index, four, "");
3176 LLVMValueRef shifted_fmask =
3177 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3178 LLVMValueRef final_sample =
3179 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3180
3181 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3182 * resource descriptor is 0 (invalid),
3183 */
3184 LLVMValueRef fmask_desc =
3185 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3186 ctx->v8i32, "");
3187
3188 LLVMValueRef fmask_word1 =
3189 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3190 ctx->i32one, "");
3191
3192 LLVMValueRef word1_is_nonzero =
3193 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3194 fmask_word1, ctx->i32zero, "");
3195
3196 /* Replace the MSAA sample index. */
3197 sample_index =
3198 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3199 final_sample, sample_index, "");
3200 return sample_index;
3201 }
3202
3203 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3204 nir_intrinsic_instr *instr)
3205 {
3206 const struct glsl_type *type = instr->variables[0]->var->type;
3207 if(instr->variables[0]->deref.child)
3208 type = instr->variables[0]->deref.child->type;
3209
3210 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3211 LLVMValueRef coords[4];
3212 LLVMValueRef masks[] = {
3213 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3214 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3215 };
3216 LLVMValueRef res;
3217 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3218
3219 int count;
3220 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3221 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3222 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3223 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3224 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3225
3226 count = image_type_to_components_count(dim,
3227 glsl_sampler_type_is_array(type));
3228
3229 if (is_ms) {
3230 LLVMValueRef fmask_load_address[3];
3231 int chan;
3232
3233 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3234 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3235 if (glsl_sampler_type_is_array(type))
3236 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3237 else
3238 fmask_load_address[2] = NULL;
3239 if (add_frag_pos) {
3240 for (chan = 0; chan < 2; ++chan)
3241 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3242 }
3243 sample_index = adjust_sample_index_using_fmask(ctx,
3244 fmask_load_address[0],
3245 fmask_load_address[1],
3246 fmask_load_address[2],
3247 sample_index,
3248 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3249 }
3250 if (count == 1) {
3251 if (instr->src[0].ssa->num_components)
3252 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3253 else
3254 res = src0;
3255 } else {
3256 int chan;
3257 if (is_ms)
3258 count--;
3259 for (chan = 0; chan < count; ++chan) {
3260 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3261 }
3262
3263 if (add_frag_pos) {
3264 for (chan = 0; chan < count; ++chan)
3265 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3266 }
3267 if (is_ms) {
3268 coords[count] = sample_index;
3269 count++;
3270 }
3271
3272 if (count == 3) {
3273 coords[3] = LLVMGetUndef(ctx->i32);
3274 count = 4;
3275 }
3276 res = ac_build_gather_values(&ctx->ac, coords, count);
3277 }
3278 return res;
3279 }
3280
3281 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3282 nir_intrinsic_instr *instr)
3283 {
3284 LLVMValueRef params[7];
3285 LLVMValueRef res;
3286 char intrinsic_name[64];
3287 const nir_variable *var = instr->variables[0]->var;
3288 const struct glsl_type *type = var->type;
3289 if(instr->variables[0]->deref.child)
3290 type = instr->variables[0]->deref.child->type;
3291
3292 type = glsl_without_array(type);
3293 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3294 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3295 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3296 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3297 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3298 params[3] = ctx->i1false; /* glc */
3299 params[4] = ctx->i1false; /* slc */
3300 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3301 params, 5, 0);
3302
3303 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3304 res = to_integer(ctx, res);
3305 } else {
3306 bool is_da = glsl_sampler_type_is_array(type) ||
3307 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3308 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3309 LLVMValueRef glc = ctx->i1false;
3310 LLVMValueRef slc = ctx->i1false;
3311
3312 params[0] = get_image_coords(ctx, instr);
3313 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3314 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3315 if (HAVE_LLVM <= 0x0309) {
3316 params[3] = ctx->i1false; /* r128 */
3317 params[4] = da;
3318 params[5] = glc;
3319 params[6] = slc;
3320 } else {
3321 LLVMValueRef lwe = ctx->i1false;
3322 params[3] = glc;
3323 params[4] = slc;
3324 params[5] = lwe;
3325 params[6] = da;
3326 }
3327
3328 ac_get_image_intr_name("llvm.amdgcn.image.load",
3329 ctx->v4f32, /* vdata */
3330 LLVMTypeOf(params[0]), /* coords */
3331 LLVMTypeOf(params[1]), /* rsrc */
3332 intrinsic_name, sizeof(intrinsic_name));
3333
3334 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3335 params, 7, AC_FUNC_ATTR_READONLY);
3336 }
3337 return to_integer(ctx, res);
3338 }
3339
3340 static void visit_image_store(struct nir_to_llvm_context *ctx,
3341 nir_intrinsic_instr *instr)
3342 {
3343 LLVMValueRef params[8];
3344 char intrinsic_name[64];
3345 const nir_variable *var = instr->variables[0]->var;
3346 const struct glsl_type *type = glsl_without_array(var->type);
3347
3348 if (ctx->stage == MESA_SHADER_FRAGMENT)
3349 ctx->shader_info->fs.writes_memory = true;
3350
3351 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3352 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
3353 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3354 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3355 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3356 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3357 params[4] = ctx->i1false; /* glc */
3358 params[5] = ctx->i1false; /* slc */
3359 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3360 params, 6, 0);
3361 } else {
3362 bool is_da = glsl_sampler_type_is_array(type) ||
3363 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3364 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3365 LLVMValueRef glc = ctx->i1false;
3366 LLVMValueRef slc = ctx->i1false;
3367
3368 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
3369 params[1] = get_image_coords(ctx, instr); /* coords */
3370 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3371 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3372 if (HAVE_LLVM <= 0x0309) {
3373 params[4] = ctx->i1false; /* r128 */
3374 params[5] = da;
3375 params[6] = glc;
3376 params[7] = slc;
3377 } else {
3378 LLVMValueRef lwe = ctx->i1false;
3379 params[4] = glc;
3380 params[5] = slc;
3381 params[6] = lwe;
3382 params[7] = da;
3383 }
3384
3385 ac_get_image_intr_name("llvm.amdgcn.image.store",
3386 LLVMTypeOf(params[0]), /* vdata */
3387 LLVMTypeOf(params[1]), /* coords */
3388 LLVMTypeOf(params[2]), /* rsrc */
3389 intrinsic_name, sizeof(intrinsic_name));
3390
3391 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3392 params, 8, 0);
3393 }
3394
3395 }
3396
3397 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3398 nir_intrinsic_instr *instr)
3399 {
3400 LLVMValueRef params[6];
3401 int param_count = 0;
3402 const nir_variable *var = instr->variables[0]->var;
3403
3404 const char *base_name = "llvm.amdgcn.image.atomic";
3405 const char *atomic_name;
3406 LLVMValueRef coords;
3407 char intrinsic_name[32], coords_type[8];
3408 const struct glsl_type *type = glsl_without_array(var->type);
3409
3410 if (ctx->stage == MESA_SHADER_FRAGMENT)
3411 ctx->shader_info->fs.writes_memory = true;
3412
3413 params[param_count++] = get_src(ctx, instr->src[2]);
3414 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3415 params[param_count++] = get_src(ctx, instr->src[3]);
3416
3417 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3418 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3419 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3420 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3421 params[param_count++] = ctx->i32zero; /* voffset */
3422 params[param_count++] = ctx->i1false; /* glc */
3423 params[param_count++] = ctx->i1false; /* slc */
3424 } else {
3425 bool da = glsl_sampler_type_is_array(type) ||
3426 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3427
3428 coords = params[param_count++] = get_image_coords(ctx, instr);
3429 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3430 params[param_count++] = ctx->i1false; /* r128 */
3431 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3432 params[param_count++] = ctx->i1false; /* slc */
3433 }
3434
3435 switch (instr->intrinsic) {
3436 case nir_intrinsic_image_atomic_add:
3437 atomic_name = "add";
3438 break;
3439 case nir_intrinsic_image_atomic_min:
3440 atomic_name = "smin";
3441 break;
3442 case nir_intrinsic_image_atomic_max:
3443 atomic_name = "smax";
3444 break;
3445 case nir_intrinsic_image_atomic_and:
3446 atomic_name = "and";
3447 break;
3448 case nir_intrinsic_image_atomic_or:
3449 atomic_name = "or";
3450 break;
3451 case nir_intrinsic_image_atomic_xor:
3452 atomic_name = "xor";
3453 break;
3454 case nir_intrinsic_image_atomic_exchange:
3455 atomic_name = "swap";
3456 break;
3457 case nir_intrinsic_image_atomic_comp_swap:
3458 atomic_name = "cmpswap";
3459 break;
3460 default:
3461 abort();
3462 }
3463 build_int_type_name(LLVMTypeOf(coords),
3464 coords_type, sizeof(coords_type));
3465
3466 snprintf(intrinsic_name, sizeof(intrinsic_name),
3467 "%s.%s.%s", base_name, atomic_name, coords_type);
3468 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3469 }
3470
3471 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3472 nir_intrinsic_instr *instr)
3473 {
3474 LLVMValueRef res;
3475 const nir_variable *var = instr->variables[0]->var;
3476 const struct glsl_type *type = instr->variables[0]->var->type;
3477 bool da = glsl_sampler_type_is_array(var->type) ||
3478 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3479 if(instr->variables[0]->deref.child)
3480 type = instr->variables[0]->deref.child->type;
3481
3482 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3483 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3484
3485 struct ac_image_args args = { 0 };
3486
3487 args.da = da;
3488 args.dmask = 0xf;
3489 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3490 args.opcode = ac_image_get_resinfo;
3491 args.addr = ctx->i32zero;
3492
3493 res = ac_build_image_opcode(&ctx->ac, &args);
3494
3495 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3496 glsl_sampler_type_is_array(type)) {
3497 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3498 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3499 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3500 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3501 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3502 }
3503 return res;
3504 }
3505
3506 #define NOOP_WAITCNT 0xf7f
3507 #define LGKM_CNT 0x07f
3508 #define VM_CNT 0xf70
3509
3510 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3511 unsigned simm16)
3512 {
3513 LLVMValueRef args[1] = {
3514 LLVMConstInt(ctx->i32, simm16, false),
3515 };
3516 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3517 ctx->voidt, args, 1, 0);
3518 }
3519
3520 static void emit_barrier(struct nir_to_llvm_context *ctx)
3521 {
3522 /* SI only (thanks to a hw bug workaround):
3523 * The real barrier instruction isn’t needed, because an entire patch
3524 * always fits into a single wave.
3525 */
3526 if (ctx->options->chip_class == SI &&
3527 ctx->stage == MESA_SHADER_TESS_CTRL) {
3528 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3529 return;
3530 }
3531 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3532 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3533 }
3534
3535 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3536 nir_intrinsic_instr *instr)
3537 {
3538 LLVMValueRef cond;
3539 ctx->shader_info->fs.can_discard = true;
3540
3541 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3542 get_src(ctx, instr->src[0]),
3543 ctx->i32zero, "");
3544
3545 cond = LLVMBuildSelect(ctx->builder, cond,
3546 LLVMConstReal(ctx->f32, -1.0f),
3547 ctx->f32zero, "");
3548 ac_build_kill(&ctx->ac, cond);
3549 }
3550
3551 static LLVMValueRef
3552 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3553 {
3554 LLVMValueRef result;
3555 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3556 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3557 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3558
3559 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3560 }
3561
3562 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3563 nir_intrinsic_instr *instr)
3564 {
3565 LLVMValueRef ptr, result;
3566 int idx = instr->variables[0]->var->data.driver_location;
3567 LLVMValueRef src = get_src(ctx, instr->src[0]);
3568 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3569
3570 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3571 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3572 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3573 ptr, src, src1,
3574 LLVMAtomicOrderingSequentiallyConsistent,
3575 LLVMAtomicOrderingSequentiallyConsistent,
3576 false);
3577 } else {
3578 LLVMAtomicRMWBinOp op;
3579 switch (instr->intrinsic) {
3580 case nir_intrinsic_var_atomic_add:
3581 op = LLVMAtomicRMWBinOpAdd;
3582 break;
3583 case nir_intrinsic_var_atomic_umin:
3584 op = LLVMAtomicRMWBinOpUMin;
3585 break;
3586 case nir_intrinsic_var_atomic_umax:
3587 op = LLVMAtomicRMWBinOpUMax;
3588 break;
3589 case nir_intrinsic_var_atomic_imin:
3590 op = LLVMAtomicRMWBinOpMin;
3591 break;
3592 case nir_intrinsic_var_atomic_imax:
3593 op = LLVMAtomicRMWBinOpMax;
3594 break;
3595 case nir_intrinsic_var_atomic_and:
3596 op = LLVMAtomicRMWBinOpAnd;
3597 break;
3598 case nir_intrinsic_var_atomic_or:
3599 op = LLVMAtomicRMWBinOpOr;
3600 break;
3601 case nir_intrinsic_var_atomic_xor:
3602 op = LLVMAtomicRMWBinOpXor;
3603 break;
3604 case nir_intrinsic_var_atomic_exchange:
3605 op = LLVMAtomicRMWBinOpXchg;
3606 break;
3607 default:
3608 return NULL;
3609 }
3610
3611 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3612 LLVMAtomicOrderingSequentiallyConsistent,
3613 false);
3614 }
3615 return result;
3616 }
3617
3618 #define INTERP_CENTER 0
3619 #define INTERP_CENTROID 1
3620 #define INTERP_SAMPLE 2
3621
3622 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3623 enum glsl_interp_mode interp, unsigned location)
3624 {
3625 switch (interp) {
3626 case INTERP_MODE_FLAT:
3627 default:
3628 return NULL;
3629 case INTERP_MODE_SMOOTH:
3630 case INTERP_MODE_NONE:
3631 if (location == INTERP_CENTER)
3632 return ctx->persp_center;
3633 else if (location == INTERP_CENTROID)
3634 return ctx->persp_centroid;
3635 else if (location == INTERP_SAMPLE)
3636 return ctx->persp_sample;
3637 break;
3638 case INTERP_MODE_NOPERSPECTIVE:
3639 if (location == INTERP_CENTER)
3640 return ctx->linear_center;
3641 else if (location == INTERP_CENTROID)
3642 return ctx->linear_centroid;
3643 else if (location == INTERP_SAMPLE)
3644 return ctx->linear_sample;
3645 break;
3646 }
3647 return NULL;
3648 }
3649
3650 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3651 LLVMValueRef sample_id)
3652 {
3653 LLVMValueRef result;
3654 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3655
3656 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3657 const_array(ctx->v2f32, 64), "");
3658
3659 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3660 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3661
3662 return result;
3663 }
3664
3665 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3666 {
3667 LLVMValueRef values[2];
3668
3669 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3670 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3671 return ac_build_gather_values(&ctx->ac, values, 2);
3672 }
3673
3674 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3675 nir_intrinsic_instr *instr)
3676 {
3677 LLVMValueRef result[2];
3678 LLVMValueRef interp_param, attr_number;
3679 unsigned location;
3680 unsigned chan;
3681 LLVMValueRef src_c0, src_c1;
3682 LLVMValueRef src0;
3683 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3684 switch (instr->intrinsic) {
3685 case nir_intrinsic_interp_var_at_centroid:
3686 location = INTERP_CENTROID;
3687 break;
3688 case nir_intrinsic_interp_var_at_sample:
3689 case nir_intrinsic_interp_var_at_offset:
3690 location = INTERP_CENTER;
3691 src0 = get_src(ctx, instr->src[0]);
3692 break;
3693 default:
3694 break;
3695 }
3696
3697 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3698 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3699 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3700 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3701 LLVMValueRef sample_position;
3702 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3703
3704 /* fetch sample ID */
3705 sample_position = load_sample_position(ctx, src0);
3706
3707 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3708 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3709 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3710 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3711 }
3712 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3713 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3714
3715 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3716 LLVMValueRef ij_out[2];
3717 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3718
3719 /*
3720 * take the I then J parameters, and the DDX/Y for it, and
3721 * calculate the IJ inputs for the interpolator.
3722 * temp1 = ddx * offset/sample.x + I;
3723 * interp_param.I = ddy * offset/sample.y + temp1;
3724 * temp1 = ddx * offset/sample.x + J;
3725 * interp_param.J = ddy * offset/sample.y + temp1;
3726 */
3727 for (unsigned i = 0; i < 2; i++) {
3728 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3729 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3730 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3731 ddxy_out, ix_ll, "");
3732 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3733 ddxy_out, iy_ll, "");
3734 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3735 interp_param, ix_ll, "");
3736 LLVMValueRef temp1, temp2;
3737
3738 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3739 ctx->f32, "");
3740
3741 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3742 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3743
3744 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3745 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3746
3747 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3748 temp2, ctx->i32, "");
3749 }
3750 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3751
3752 }
3753
3754 for (chan = 0; chan < 2; chan++) {
3755 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3756
3757 if (interp_param) {
3758 interp_param = LLVMBuildBitCast(ctx->builder,
3759 interp_param, LLVMVectorType(ctx->f32, 2), "");
3760 LLVMValueRef i = LLVMBuildExtractElement(
3761 ctx->builder, interp_param, ctx->i32zero, "");
3762 LLVMValueRef j = LLVMBuildExtractElement(
3763 ctx->builder, interp_param, ctx->i32one, "");
3764
3765 result[chan] = ac_build_fs_interp(&ctx->ac,
3766 llvm_chan, attr_number,
3767 ctx->prim_mask, i, j);
3768 } else {
3769 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3770 LLVMConstInt(ctx->i32, 2, false),
3771 llvm_chan, attr_number,
3772 ctx->prim_mask);
3773 }
3774 }
3775 return ac_build_gather_values(&ctx->ac, result, 2);
3776 }
3777
3778 static void
3779 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3780 nir_intrinsic_instr *instr)
3781 {
3782 LLVMValueRef gs_next_vertex;
3783 LLVMValueRef can_emit, kill;
3784 int idx;
3785
3786 assert(instr->const_index[0] == 0);
3787 /* Write vertex attribute values to GSVS ring */
3788 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3789 ctx->gs_next_vertex,
3790 "");
3791
3792 /* If this thread has already emitted the declared maximum number of
3793 * vertices, kill it: excessive vertex emissions are not supposed to
3794 * have any effect, and GS threads have no externally observable
3795 * effects other than emitting vertices.
3796 */
3797 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3798 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3799
3800 kill = LLVMBuildSelect(ctx->builder, can_emit,
3801 LLVMConstReal(ctx->f32, 1.0f),
3802 LLVMConstReal(ctx->f32, -1.0f), "");
3803 ac_build_kill(&ctx->ac, kill);
3804
3805 /* loop num outputs */
3806 idx = 0;
3807 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3808 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3809 int length = 4;
3810 int slot = idx;
3811 int slot_inc = 1;
3812
3813 if (!(ctx->output_mask & (1ull << i)))
3814 continue;
3815
3816 if (i == VARYING_SLOT_CLIP_DIST0) {
3817 /* pack clip and cull into a single set of slots */
3818 length = ctx->num_output_clips + ctx->num_output_culls;
3819 if (length > 4)
3820 slot_inc = 2;
3821 }
3822 for (unsigned j = 0; j < length; j++) {
3823 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3824 out_ptr[j], "");
3825 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3826 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3827 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3828
3829 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3830
3831 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3832 out_val, 1,
3833 voffset, ctx->gs2vs_offset, 0,
3834 1, 1, true, true);
3835 }
3836 idx += slot_inc;
3837 }
3838
3839 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3840 ctx->i32one, "");
3841 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3842
3843 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3844 }
3845
3846 static void
3847 visit_end_primitive(struct nir_to_llvm_context *ctx,
3848 nir_intrinsic_instr *instr)
3849 {
3850 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3851 }
3852
3853 static LLVMValueRef
3854 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3855 nir_intrinsic_instr *instr)
3856 {
3857 LLVMValueRef coord[4] = {
3858 ctx->tes_u,
3859 ctx->tes_v,
3860 ctx->f32zero,
3861 ctx->f32zero,
3862 };
3863
3864 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3865 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3866 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3867
3868 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3869 return LLVMBuildBitCast(ctx->builder, result,
3870 get_def_type(ctx, &instr->dest.ssa), "");
3871 }
3872
3873 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3874 nir_intrinsic_instr *instr)
3875 {
3876 LLVMValueRef result = NULL;
3877
3878 switch (instr->intrinsic) {
3879 case nir_intrinsic_load_work_group_id: {
3880 result = ctx->workgroup_ids;
3881 break;
3882 }
3883 case nir_intrinsic_load_base_vertex: {
3884 result = ctx->base_vertex;
3885 break;
3886 }
3887 case nir_intrinsic_load_vertex_id_zero_base: {
3888 result = ctx->vertex_id;
3889 break;
3890 }
3891 case nir_intrinsic_load_local_invocation_id: {
3892 result = ctx->local_invocation_ids;
3893 break;
3894 }
3895 case nir_intrinsic_load_base_instance:
3896 result = ctx->start_instance;
3897 break;
3898 case nir_intrinsic_load_draw_id:
3899 result = ctx->draw_index;
3900 break;
3901 case nir_intrinsic_load_invocation_id:
3902 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3903 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3904 else
3905 result = ctx->gs_invocation_id;
3906 break;
3907 case nir_intrinsic_load_primitive_id:
3908 if (ctx->stage == MESA_SHADER_GEOMETRY)
3909 result = ctx->gs_prim_id;
3910 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
3911 result = ctx->tcs_patch_id;
3912 else if (ctx->stage == MESA_SHADER_TESS_EVAL)
3913 result = ctx->tes_patch_id;
3914 else
3915 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3916 break;
3917 case nir_intrinsic_load_sample_id:
3918 ctx->shader_info->fs.force_persample = true;
3919 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3920 break;
3921 case nir_intrinsic_load_sample_pos:
3922 ctx->shader_info->fs.force_persample = true;
3923 result = load_sample_pos(ctx);
3924 break;
3925 case nir_intrinsic_load_sample_mask_in:
3926 result = ctx->sample_coverage;
3927 break;
3928 case nir_intrinsic_load_front_face:
3929 result = ctx->front_face;
3930 break;
3931 case nir_intrinsic_load_instance_id:
3932 result = ctx->instance_id;
3933 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3934 ctx->shader_info->vs.vgpr_comp_cnt);
3935 break;
3936 case nir_intrinsic_load_num_work_groups:
3937 result = ctx->num_work_groups;
3938 break;
3939 case nir_intrinsic_load_local_invocation_index:
3940 result = visit_load_local_invocation_index(ctx);
3941 break;
3942 case nir_intrinsic_load_push_constant:
3943 result = visit_load_push_constant(ctx, instr);
3944 break;
3945 case nir_intrinsic_vulkan_resource_index:
3946 result = visit_vulkan_resource_index(ctx, instr);
3947 break;
3948 case nir_intrinsic_store_ssbo:
3949 visit_store_ssbo(ctx, instr);
3950 break;
3951 case nir_intrinsic_load_ssbo:
3952 result = visit_load_buffer(ctx, instr);
3953 break;
3954 case nir_intrinsic_ssbo_atomic_add:
3955 case nir_intrinsic_ssbo_atomic_imin:
3956 case nir_intrinsic_ssbo_atomic_umin:
3957 case nir_intrinsic_ssbo_atomic_imax:
3958 case nir_intrinsic_ssbo_atomic_umax:
3959 case nir_intrinsic_ssbo_atomic_and:
3960 case nir_intrinsic_ssbo_atomic_or:
3961 case nir_intrinsic_ssbo_atomic_xor:
3962 case nir_intrinsic_ssbo_atomic_exchange:
3963 case nir_intrinsic_ssbo_atomic_comp_swap:
3964 result = visit_atomic_ssbo(ctx, instr);
3965 break;
3966 case nir_intrinsic_load_ubo:
3967 result = visit_load_ubo_buffer(ctx, instr);
3968 break;
3969 case nir_intrinsic_get_buffer_size:
3970 result = visit_get_buffer_size(ctx, instr);
3971 break;
3972 case nir_intrinsic_load_var:
3973 result = visit_load_var(ctx, instr);
3974 break;
3975 case nir_intrinsic_store_var:
3976 visit_store_var(ctx, instr);
3977 break;
3978 case nir_intrinsic_image_load:
3979 result = visit_image_load(ctx, instr);
3980 break;
3981 case nir_intrinsic_image_store:
3982 visit_image_store(ctx, instr);
3983 break;
3984 case nir_intrinsic_image_atomic_add:
3985 case nir_intrinsic_image_atomic_min:
3986 case nir_intrinsic_image_atomic_max:
3987 case nir_intrinsic_image_atomic_and:
3988 case nir_intrinsic_image_atomic_or:
3989 case nir_intrinsic_image_atomic_xor:
3990 case nir_intrinsic_image_atomic_exchange:
3991 case nir_intrinsic_image_atomic_comp_swap:
3992 result = visit_image_atomic(ctx, instr);
3993 break;
3994 case nir_intrinsic_image_size:
3995 result = visit_image_size(ctx, instr);
3996 break;
3997 case nir_intrinsic_discard:
3998 ctx->shader_info->fs.can_discard = true;
3999 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4000 ctx->voidt,
4001 NULL, 0, AC_FUNC_ATTR_LEGACY);
4002 break;
4003 case nir_intrinsic_discard_if:
4004 emit_discard_if(ctx, instr);
4005 break;
4006 case nir_intrinsic_memory_barrier:
4007 emit_waitcnt(ctx, VM_CNT);
4008 break;
4009 case nir_intrinsic_barrier:
4010 emit_barrier(ctx);
4011 break;
4012 case nir_intrinsic_var_atomic_add:
4013 case nir_intrinsic_var_atomic_imin:
4014 case nir_intrinsic_var_atomic_umin:
4015 case nir_intrinsic_var_atomic_imax:
4016 case nir_intrinsic_var_atomic_umax:
4017 case nir_intrinsic_var_atomic_and:
4018 case nir_intrinsic_var_atomic_or:
4019 case nir_intrinsic_var_atomic_xor:
4020 case nir_intrinsic_var_atomic_exchange:
4021 case nir_intrinsic_var_atomic_comp_swap:
4022 result = visit_var_atomic(ctx, instr);
4023 break;
4024 case nir_intrinsic_interp_var_at_centroid:
4025 case nir_intrinsic_interp_var_at_sample:
4026 case nir_intrinsic_interp_var_at_offset:
4027 result = visit_interp(ctx, instr);
4028 break;
4029 case nir_intrinsic_emit_vertex:
4030 visit_emit_vertex(ctx, instr);
4031 break;
4032 case nir_intrinsic_end_primitive:
4033 visit_end_primitive(ctx, instr);
4034 break;
4035 case nir_intrinsic_load_tess_coord:
4036 result = visit_load_tess_coord(ctx, instr);
4037 break;
4038 case nir_intrinsic_load_patch_vertices_in:
4039 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
4040 break;
4041 default:
4042 fprintf(stderr, "Unknown intrinsic: ");
4043 nir_print_instr(&instr->instr, stderr);
4044 fprintf(stderr, "\n");
4045 break;
4046 }
4047 if (result) {
4048 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4049 }
4050 }
4051
4052 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
4053 nir_deref_var *deref,
4054 enum desc_type desc_type)
4055 {
4056 unsigned desc_set = deref->var->data.descriptor_set;
4057 LLVMValueRef list = ctx->descriptor_sets[desc_set];
4058 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4059 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
4060 unsigned offset = binding->offset;
4061 unsigned stride = binding->size;
4062 unsigned type_size;
4063 LLVMBuilderRef builder = ctx->builder;
4064 LLVMTypeRef type;
4065 LLVMValueRef index = NULL;
4066 unsigned constant_index = 0;
4067
4068 assert(deref->var->data.binding < layout->binding_count);
4069
4070 switch (desc_type) {
4071 case DESC_IMAGE:
4072 type = ctx->v8i32;
4073 type_size = 32;
4074 break;
4075 case DESC_FMASK:
4076 type = ctx->v8i32;
4077 offset += 32;
4078 type_size = 32;
4079 break;
4080 case DESC_SAMPLER:
4081 type = ctx->v4i32;
4082 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4083 offset += 64;
4084
4085 type_size = 16;
4086 break;
4087 case DESC_BUFFER:
4088 type = ctx->v4i32;
4089 type_size = 16;
4090 break;
4091 default:
4092 unreachable("invalid desc_type\n");
4093 }
4094
4095 if (deref->deref.child) {
4096 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
4097
4098 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4099 offset += child->base_offset * stride;
4100 if (child->deref_array_type == nir_deref_array_type_indirect) {
4101 index = get_src(ctx, child->indirect);
4102 }
4103
4104 constant_index = child->base_offset;
4105 }
4106 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
4107 (!index || binding->immutable_samplers_equal)) {
4108 if (binding->immutable_samplers_equal)
4109 constant_index = 0;
4110
4111 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4112
4113 LLVMValueRef constants[] = {
4114 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4115 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4116 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4117 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4118 };
4119 return ac_build_gather_values(&ctx->ac, constants, 4);
4120 }
4121
4122 assert(stride % type_size == 0);
4123
4124 if (!index)
4125 index = ctx->i32zero;
4126
4127 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4128
4129 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4130 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4131
4132 return ac_build_indexed_load_const(&ctx->ac, list, index);
4133 }
4134
4135 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4136 struct ac_image_args *args,
4137 nir_tex_instr *instr,
4138 nir_texop op,
4139 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4140 LLVMValueRef *param, unsigned count,
4141 unsigned dmask)
4142 {
4143 unsigned is_rect = 0;
4144 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4145
4146 if (op == nir_texop_lod)
4147 da = false;
4148 /* Pad to power of two vector */
4149 while (count < util_next_power_of_two(count))
4150 param[count++] = LLVMGetUndef(ctx->i32);
4151
4152 if (count > 1)
4153 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4154 else
4155 args->addr = param[0];
4156
4157 args->resource = res_ptr;
4158 args->sampler = samp_ptr;
4159
4160 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4161 args->addr = param[0];
4162 return;
4163 }
4164
4165 args->dmask = dmask;
4166 args->unorm = is_rect;
4167 args->da = da;
4168 }
4169
4170 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4171 *
4172 * SI-CI:
4173 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4174 * filtering manually. The driver sets img7 to a mask clearing
4175 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4176 * s_and_b32 samp0, samp0, img7
4177 *
4178 * VI:
4179 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4180 */
4181 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4182 LLVMValueRef res, LLVMValueRef samp)
4183 {
4184 LLVMBuilderRef builder = ctx->builder;
4185 LLVMValueRef img7, samp0;
4186
4187 if (ctx->options->chip_class >= VI)
4188 return samp;
4189
4190 img7 = LLVMBuildExtractElement(builder, res,
4191 LLVMConstInt(ctx->i32, 7, 0), "");
4192 samp0 = LLVMBuildExtractElement(builder, samp,
4193 LLVMConstInt(ctx->i32, 0, 0), "");
4194 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4195 return LLVMBuildInsertElement(builder, samp, samp0,
4196 LLVMConstInt(ctx->i32, 0, 0), "");
4197 }
4198
4199 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4200 nir_tex_instr *instr,
4201 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4202 LLVMValueRef *fmask_ptr)
4203 {
4204 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4205 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4206 else
4207 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4208 if (samp_ptr) {
4209 if (instr->sampler)
4210 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4211 else
4212 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4213 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4214 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4215 }
4216 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4217 instr->op == nir_texop_samples_identical))
4218 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4219 }
4220
4221 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4222 LLVMValueRef coord)
4223 {
4224 coord = to_float(ctx, coord);
4225 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4226 coord = to_integer(ctx, coord);
4227 return coord;
4228 }
4229
4230 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4231 {
4232 LLVMValueRef result = NULL;
4233 struct ac_image_args args = { 0 };
4234 unsigned dmask = 0xf;
4235 LLVMValueRef address[16];
4236 LLVMValueRef coords[5];
4237 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4238 LLVMValueRef bias = NULL, offsets = NULL;
4239 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4240 LLVMValueRef ddx = NULL, ddy = NULL;
4241 LLVMValueRef derivs[6];
4242 unsigned chan, count = 0;
4243 unsigned const_src = 0, num_deriv_comp = 0;
4244 bool lod_is_zero = false;
4245 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4246
4247 for (unsigned i = 0; i < instr->num_srcs; i++) {
4248 switch (instr->src[i].src_type) {
4249 case nir_tex_src_coord:
4250 coord = get_src(ctx, instr->src[i].src);
4251 break;
4252 case nir_tex_src_projector:
4253 break;
4254 case nir_tex_src_comparator:
4255 comparator = get_src(ctx, instr->src[i].src);
4256 break;
4257 case nir_tex_src_offset:
4258 offsets = get_src(ctx, instr->src[i].src);
4259 const_src = i;
4260 break;
4261 case nir_tex_src_bias:
4262 bias = get_src(ctx, instr->src[i].src);
4263 break;
4264 case nir_tex_src_lod: {
4265 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4266
4267 if (val && val->i32[0] == 0)
4268 lod_is_zero = true;
4269 lod = get_src(ctx, instr->src[i].src);
4270 break;
4271 }
4272 case nir_tex_src_ms_index:
4273 sample_index = get_src(ctx, instr->src[i].src);
4274 break;
4275 case nir_tex_src_ms_mcs:
4276 break;
4277 case nir_tex_src_ddx:
4278 ddx = get_src(ctx, instr->src[i].src);
4279 num_deriv_comp = instr->src[i].src.ssa->num_components;
4280 break;
4281 case nir_tex_src_ddy:
4282 ddy = get_src(ctx, instr->src[i].src);
4283 break;
4284 case nir_tex_src_texture_offset:
4285 case nir_tex_src_sampler_offset:
4286 case nir_tex_src_plane:
4287 default:
4288 break;
4289 }
4290 }
4291
4292 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4293 result = get_buffer_size(ctx, res_ptr, true);
4294 goto write_result;
4295 }
4296
4297 if (instr->op == nir_texop_texture_samples) {
4298 LLVMValueRef res, samples, is_msaa;
4299 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4300 samples = LLVMBuildExtractElement(ctx->builder, res,
4301 LLVMConstInt(ctx->i32, 3, false), "");
4302 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4303 LLVMConstInt(ctx->i32, 28, false), "");
4304 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4305 LLVMConstInt(ctx->i32, 0xe, false), "");
4306 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4307 LLVMConstInt(ctx->i32, 0xe, false), "");
4308
4309 samples = LLVMBuildLShr(ctx->builder, samples,
4310 LLVMConstInt(ctx->i32, 16, false), "");
4311 samples = LLVMBuildAnd(ctx->builder, samples,
4312 LLVMConstInt(ctx->i32, 0xf, false), "");
4313 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4314 samples, "");
4315 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4316 ctx->i32one, "");
4317 result = samples;
4318 goto write_result;
4319 }
4320
4321 if (coord)
4322 for (chan = 0; chan < instr->coord_components; chan++)
4323 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4324
4325 if (offsets && instr->op != nir_texop_txf) {
4326 LLVMValueRef offset[3], pack;
4327 for (chan = 0; chan < 3; ++chan)
4328 offset[chan] = ctx->i32zero;
4329
4330 args.offset = true;
4331 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4332 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4333 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4334 LLVMConstInt(ctx->i32, 0x3f, false), "");
4335 if (chan)
4336 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4337 LLVMConstInt(ctx->i32, chan * 8, false), "");
4338 }
4339 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4340 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4341 address[count++] = pack;
4342
4343 }
4344 /* pack LOD bias value */
4345 if (instr->op == nir_texop_txb && bias) {
4346 address[count++] = bias;
4347 }
4348
4349 /* Pack depth comparison value */
4350 if (instr->is_shadow && comparator) {
4351 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4352 }
4353
4354 /* pack derivatives */
4355 if (ddx || ddy) {
4356 switch (instr->sampler_dim) {
4357 case GLSL_SAMPLER_DIM_3D:
4358 case GLSL_SAMPLER_DIM_CUBE:
4359 num_deriv_comp = 3;
4360 break;
4361 case GLSL_SAMPLER_DIM_2D:
4362 default:
4363 num_deriv_comp = 2;
4364 break;
4365 case GLSL_SAMPLER_DIM_1D:
4366 num_deriv_comp = 1;
4367 break;
4368 }
4369
4370 for (unsigned i = 0; i < num_deriv_comp; i++) {
4371 derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
4372 derivs[num_deriv_comp + i] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
4373 }
4374 }
4375
4376 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4377 if (instr->is_array && instr->op != nir_texop_lod)
4378 coords[3] = apply_round_slice(ctx, coords[3]);
4379 for (chan = 0; chan < instr->coord_components; chan++)
4380 coords[chan] = to_float(ctx, coords[chan]);
4381 if (instr->coord_components == 3)
4382 coords[3] = LLVMGetUndef(ctx->f32);
4383 ac_prepare_cube_coords(&ctx->ac,
4384 instr->op == nir_texop_txd, instr->is_array,
4385 coords, derivs);
4386 if (num_deriv_comp)
4387 num_deriv_comp--;
4388 }
4389
4390 if (ddx || ddy) {
4391 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4392 address[count++] = derivs[i];
4393 }
4394
4395 /* Pack texture coordinates */
4396 if (coord) {
4397 address[count++] = coords[0];
4398 if (instr->coord_components > 1) {
4399 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4400 coords[1] = apply_round_slice(ctx, coords[1]);
4401 }
4402 address[count++] = coords[1];
4403 }
4404 if (instr->coord_components > 2) {
4405 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4406 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4407 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4408 instr->op != nir_texop_txf) {
4409 coords[2] = apply_round_slice(ctx, coords[2]);
4410 }
4411 address[count++] = coords[2];
4412 }
4413 }
4414
4415 /* Pack LOD */
4416 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4417 instr->op == nir_texop_txf)) {
4418 address[count++] = lod;
4419 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4420 address[count++] = sample_index;
4421 } else if(instr->op == nir_texop_txs) {
4422 count = 0;
4423 if (lod)
4424 address[count++] = lod;
4425 else
4426 address[count++] = ctx->i32zero;
4427 }
4428
4429 for (chan = 0; chan < count; chan++) {
4430 address[chan] = LLVMBuildBitCast(ctx->builder,
4431 address[chan], ctx->i32, "");
4432 }
4433
4434 if (instr->op == nir_texop_samples_identical) {
4435 LLVMValueRef txf_address[4];
4436 struct ac_image_args txf_args = { 0 };
4437 unsigned txf_count = count;
4438 memcpy(txf_address, address, sizeof(txf_address));
4439
4440 if (!instr->is_array)
4441 txf_address[2] = ctx->i32zero;
4442 txf_address[3] = ctx->i32zero;
4443
4444 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4445 fmask_ptr, NULL,
4446 txf_address, txf_count, 0xf);
4447
4448 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4449
4450 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4451 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
4452 goto write_result;
4453 }
4454
4455 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4456 instr->op != nir_texop_txs) {
4457 unsigned sample_chan = instr->is_array ? 3 : 2;
4458 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4459 address[0],
4460 address[1],
4461 instr->is_array ? address[2] : NULL,
4462 address[sample_chan],
4463 fmask_ptr);
4464 }
4465
4466 if (offsets && instr->op == nir_texop_txf) {
4467 nir_const_value *const_offset =
4468 nir_src_as_const_value(instr->src[const_src].src);
4469 int num_offsets = instr->src[const_src].src.ssa->num_components;
4470 assert(const_offset);
4471 num_offsets = MIN2(num_offsets, instr->coord_components);
4472 if (num_offsets > 2)
4473 address[2] = LLVMBuildAdd(ctx->builder,
4474 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4475 if (num_offsets > 1)
4476 address[1] = LLVMBuildAdd(ctx->builder,
4477 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4478 address[0] = LLVMBuildAdd(ctx->builder,
4479 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4480
4481 }
4482
4483 /* TODO TG4 support */
4484 if (instr->op == nir_texop_tg4) {
4485 if (instr->is_shadow)
4486 dmask = 1;
4487 else
4488 dmask = 1 << instr->component;
4489 }
4490 set_tex_fetch_args(ctx, &args, instr, instr->op,
4491 res_ptr, samp_ptr, address, count, dmask);
4492
4493 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4494
4495 if (instr->op == nir_texop_query_levels)
4496 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4497 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4498 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4499 else if (instr->op == nir_texop_txs &&
4500 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4501 instr->is_array) {
4502 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4503 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4504 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4505 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4506 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4507 } else if (instr->dest.ssa.num_components != 4)
4508 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4509
4510 write_result:
4511 if (result) {
4512 assert(instr->dest.is_ssa);
4513 result = to_integer(ctx, result);
4514 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4515 }
4516 }
4517
4518
4519 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4520 {
4521 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4522 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4523
4524 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4525 _mesa_hash_table_insert(ctx->phis, instr, result);
4526 }
4527
4528 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4529 nir_phi_instr *instr,
4530 LLVMValueRef llvm_phi)
4531 {
4532 nir_foreach_phi_src(src, instr) {
4533 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4534 LLVMValueRef llvm_src = get_src(ctx, src->src);
4535
4536 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4537 }
4538 }
4539
4540 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4541 {
4542 struct hash_entry *entry;
4543 hash_table_foreach(ctx->phis, entry) {
4544 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4545 (LLVMValueRef)entry->data);
4546 }
4547 }
4548
4549
4550 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4551 nir_ssa_undef_instr *instr)
4552 {
4553 unsigned num_components = instr->def.num_components;
4554 LLVMValueRef undef;
4555
4556 if (num_components == 1)
4557 undef = LLVMGetUndef(ctx->i32);
4558 else {
4559 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4560 }
4561 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4562 }
4563
4564 static void visit_jump(struct nir_to_llvm_context *ctx,
4565 nir_jump_instr *instr)
4566 {
4567 switch (instr->type) {
4568 case nir_jump_break:
4569 LLVMBuildBr(ctx->builder, ctx->break_block);
4570 LLVMClearInsertionPosition(ctx->builder);
4571 break;
4572 case nir_jump_continue:
4573 LLVMBuildBr(ctx->builder, ctx->continue_block);
4574 LLVMClearInsertionPosition(ctx->builder);
4575 break;
4576 default:
4577 fprintf(stderr, "Unknown NIR jump instr: ");
4578 nir_print_instr(&instr->instr, stderr);
4579 fprintf(stderr, "\n");
4580 abort();
4581 }
4582 }
4583
4584 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4585 struct exec_list *list);
4586
4587 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4588 {
4589 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4590 nir_foreach_instr(instr, block)
4591 {
4592 switch (instr->type) {
4593 case nir_instr_type_alu:
4594 visit_alu(ctx, nir_instr_as_alu(instr));
4595 break;
4596 case nir_instr_type_load_const:
4597 visit_load_const(ctx, nir_instr_as_load_const(instr));
4598 break;
4599 case nir_instr_type_intrinsic:
4600 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4601 break;
4602 case nir_instr_type_tex:
4603 visit_tex(ctx, nir_instr_as_tex(instr));
4604 break;
4605 case nir_instr_type_phi:
4606 visit_phi(ctx, nir_instr_as_phi(instr));
4607 break;
4608 case nir_instr_type_ssa_undef:
4609 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4610 break;
4611 case nir_instr_type_jump:
4612 visit_jump(ctx, nir_instr_as_jump(instr));
4613 break;
4614 default:
4615 fprintf(stderr, "Unknown NIR instr type: ");
4616 nir_print_instr(instr, stderr);
4617 fprintf(stderr, "\n");
4618 abort();
4619 }
4620 }
4621
4622 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4623 }
4624
4625 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4626 {
4627 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4628
4629 LLVMBasicBlockRef merge_block =
4630 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4631 LLVMBasicBlockRef if_block =
4632 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4633 LLVMBasicBlockRef else_block = merge_block;
4634 if (!exec_list_is_empty(&if_stmt->else_list))
4635 else_block = LLVMAppendBasicBlockInContext(
4636 ctx->context, ctx->main_function, "");
4637
4638 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4639 LLVMConstInt(ctx->i32, 0, false), "");
4640 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4641
4642 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4643 visit_cf_list(ctx, &if_stmt->then_list);
4644 if (LLVMGetInsertBlock(ctx->builder))
4645 LLVMBuildBr(ctx->builder, merge_block);
4646
4647 if (!exec_list_is_empty(&if_stmt->else_list)) {
4648 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4649 visit_cf_list(ctx, &if_stmt->else_list);
4650 if (LLVMGetInsertBlock(ctx->builder))
4651 LLVMBuildBr(ctx->builder, merge_block);
4652 }
4653
4654 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4655 }
4656
4657 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4658 {
4659 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4660 LLVMBasicBlockRef break_parent = ctx->break_block;
4661
4662 ctx->continue_block =
4663 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4664 ctx->break_block =
4665 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4666
4667 LLVMBuildBr(ctx->builder, ctx->continue_block);
4668 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4669 visit_cf_list(ctx, &loop->body);
4670
4671 if (LLVMGetInsertBlock(ctx->builder))
4672 LLVMBuildBr(ctx->builder, ctx->continue_block);
4673 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4674
4675 ctx->continue_block = continue_parent;
4676 ctx->break_block = break_parent;
4677 }
4678
4679 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4680 struct exec_list *list)
4681 {
4682 foreach_list_typed(nir_cf_node, node, node, list)
4683 {
4684 switch (node->type) {
4685 case nir_cf_node_block:
4686 visit_block(ctx, nir_cf_node_as_block(node));
4687 break;
4688
4689 case nir_cf_node_if:
4690 visit_if(ctx, nir_cf_node_as_if(node));
4691 break;
4692
4693 case nir_cf_node_loop:
4694 visit_loop(ctx, nir_cf_node_as_loop(node));
4695 break;
4696
4697 default:
4698 assert(0);
4699 }
4700 }
4701 }
4702
4703 static void
4704 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4705 struct nir_variable *variable)
4706 {
4707 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4708 LLVMValueRef t_offset;
4709 LLVMValueRef t_list;
4710 LLVMValueRef input;
4711 LLVMValueRef buffer_index;
4712 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4713 int idx = variable->data.location;
4714 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4715
4716 variable->data.driver_location = idx * 4;
4717
4718 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4719 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4720 ctx->start_instance, "");
4721 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4722 ctx->shader_info->vs.vgpr_comp_cnt);
4723 } else
4724 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4725 ctx->base_vertex, "");
4726
4727 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4728 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4729
4730 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4731
4732 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4733 buffer_index,
4734 LLVMConstInt(ctx->i32, 0, false),
4735 true);
4736
4737 for (unsigned chan = 0; chan < 4; chan++) {
4738 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4739 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4740 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4741 input, llvm_chan, ""));
4742 }
4743 }
4744 }
4745
4746 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4747 unsigned attr,
4748 LLVMValueRef interp_param,
4749 LLVMValueRef prim_mask,
4750 LLVMValueRef result[4])
4751 {
4752 LLVMValueRef attr_number;
4753 unsigned chan;
4754 LLVMValueRef i, j;
4755 bool interp = interp_param != NULL;
4756
4757 attr_number = LLVMConstInt(ctx->i32, attr, false);
4758
4759 /* fs.constant returns the param from the middle vertex, so it's not
4760 * really useful for flat shading. It's meant to be used for custom
4761 * interpolation (but the intrinsic can't fetch from the other two
4762 * vertices).
4763 *
4764 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4765 * to do the right thing. The only reason we use fs.constant is that
4766 * fs.interp cannot be used on integers, because they can be equal
4767 * to NaN.
4768 */
4769 if (interp) {
4770 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4771 LLVMVectorType(ctx->f32, 2), "");
4772
4773 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4774 ctx->i32zero, "");
4775 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4776 ctx->i32one, "");
4777 }
4778
4779 for (chan = 0; chan < 4; chan++) {
4780 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4781
4782 if (interp) {
4783 result[chan] = ac_build_fs_interp(&ctx->ac,
4784 llvm_chan,
4785 attr_number,
4786 prim_mask, i, j);
4787 } else {
4788 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4789 LLVMConstInt(ctx->i32, 2, false),
4790 llvm_chan,
4791 attr_number,
4792 prim_mask);
4793 }
4794 }
4795 }
4796
4797 static void
4798 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4799 struct nir_variable *variable)
4800 {
4801 int idx = variable->data.location;
4802 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4803 LLVMValueRef interp;
4804
4805 variable->data.driver_location = idx * 4;
4806 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4807
4808 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4809 unsigned interp_type;
4810 if (variable->data.sample) {
4811 interp_type = INTERP_SAMPLE;
4812 ctx->shader_info->fs.force_persample = true;
4813 } else if (variable->data.centroid)
4814 interp_type = INTERP_CENTROID;
4815 else
4816 interp_type = INTERP_CENTER;
4817
4818 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4819 } else
4820 interp = NULL;
4821
4822 for (unsigned i = 0; i < attrib_count; ++i)
4823 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4824
4825 }
4826
4827 static void
4828 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4829 struct nir_variable *variable)
4830 {
4831 switch (ctx->stage) {
4832 case MESA_SHADER_VERTEX:
4833 handle_vs_input_decl(ctx, variable);
4834 break;
4835 case MESA_SHADER_FRAGMENT:
4836 handle_fs_input_decl(ctx, variable);
4837 break;
4838 default:
4839 break;
4840 }
4841
4842 }
4843
4844 static void
4845 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4846 struct nir_shader *nir)
4847 {
4848 unsigned index = 0;
4849 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4850 LLVMValueRef interp_param;
4851 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4852
4853 if (!(ctx->input_mask & (1ull << i)))
4854 continue;
4855
4856 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4857 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4858 interp_param = *inputs;
4859 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4860 inputs);
4861
4862 if (!interp_param)
4863 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4864 ++index;
4865 } else if (i == VARYING_SLOT_POS) {
4866 for(int i = 0; i < 3; ++i)
4867 inputs[i] = ctx->frag_pos[i];
4868
4869 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4870 }
4871 }
4872 ctx->shader_info->fs.num_interp = index;
4873 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4874 ctx->shader_info->fs.has_pcoord = true;
4875 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4876 ctx->shader_info->fs.prim_id_input = true;
4877 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4878 ctx->shader_info->fs.layer_input = true;
4879 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4880 }
4881
4882 static LLVMValueRef
4883 ac_build_alloca(struct nir_to_llvm_context *ctx,
4884 LLVMTypeRef type,
4885 const char *name)
4886 {
4887 LLVMBuilderRef builder = ctx->builder;
4888 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4889 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4890 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4891 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4892 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4893 LLVMValueRef res;
4894
4895 if (first_instr) {
4896 LLVMPositionBuilderBefore(first_builder, first_instr);
4897 } else {
4898 LLVMPositionBuilderAtEnd(first_builder, first_block);
4899 }
4900
4901 res = LLVMBuildAlloca(first_builder, type, name);
4902 LLVMBuildStore(builder, LLVMConstNull(type), res);
4903
4904 LLVMDisposeBuilder(first_builder);
4905
4906 return res;
4907 }
4908
4909 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4910 LLVMTypeRef type,
4911 const char *name)
4912 {
4913 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4914 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4915 return ptr;
4916 }
4917
4918 static void
4919 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4920 struct nir_variable *variable)
4921 {
4922 int idx = variable->data.location + variable->data.index;
4923 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4924 uint64_t mask_attribs;
4925 variable->data.driver_location = idx * 4;
4926
4927 /* tess ctrl has it's own load/store paths for outputs */
4928 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4929 return;
4930
4931 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4932 if (ctx->stage == MESA_SHADER_VERTEX ||
4933 ctx->stage == MESA_SHADER_TESS_EVAL ||
4934 ctx->stage == MESA_SHADER_GEOMETRY) {
4935 if (idx == VARYING_SLOT_CLIP_DIST0) {
4936 int length = ctx->num_output_clips + ctx->num_output_culls;
4937 if (ctx->stage == MESA_SHADER_VERTEX) {
4938 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4939 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4940 }
4941 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4942 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4943 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4944 }
4945
4946 if (length > 4)
4947 attrib_count = 2;
4948 else
4949 attrib_count = 1;
4950 mask_attribs = 1ull << idx;
4951 }
4952 }
4953
4954 for (unsigned i = 0; i < attrib_count; ++i) {
4955 for (unsigned chan = 0; chan < 4; chan++) {
4956 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4957 si_build_alloca_undef(ctx, ctx->f32, "");
4958 }
4959 }
4960 ctx->output_mask |= mask_attribs;
4961 }
4962
4963 static void
4964 setup_locals(struct nir_to_llvm_context *ctx,
4965 struct nir_function *func)
4966 {
4967 int i, j;
4968 ctx->num_locals = 0;
4969 nir_foreach_variable(variable, &func->impl->locals) {
4970 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4971 variable->data.driver_location = ctx->num_locals * 4;
4972 ctx->num_locals += attrib_count;
4973 }
4974 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4975 if (!ctx->locals)
4976 return;
4977
4978 for (i = 0; i < ctx->num_locals; i++) {
4979 for (j = 0; j < 4; j++) {
4980 ctx->locals[i * 4 + j] =
4981 si_build_alloca_undef(ctx, ctx->f32, "temp");
4982 }
4983 }
4984 }
4985
4986 static LLVMValueRef
4987 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4988 {
4989 v = to_float(ctx, v);
4990 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4991 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4992 }
4993
4994
4995 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4996 LLVMValueRef src0, LLVMValueRef src1)
4997 {
4998 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4999 LLVMValueRef comp[2];
5000
5001 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5002 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5003 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5004 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5005 }
5006
5007 /* Initialize arguments for the shader export intrinsic */
5008 static void
5009 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5010 LLVMValueRef *values,
5011 unsigned target,
5012 struct ac_export_args *args)
5013 {
5014 /* Default is 0xf. Adjusted below depending on the format. */
5015 args->enabled_channels = 0xf;
5016
5017 /* Specify whether the EXEC mask represents the valid mask */
5018 args->valid_mask = 0;
5019
5020 /* Specify whether this is the last export */
5021 args->done = 0;
5022
5023 /* Specify the target we are exporting */
5024 args->target = target;
5025
5026 args->compr = false;
5027 args->out[0] = LLVMGetUndef(ctx->f32);
5028 args->out[1] = LLVMGetUndef(ctx->f32);
5029 args->out[2] = LLVMGetUndef(ctx->f32);
5030 args->out[3] = LLVMGetUndef(ctx->f32);
5031
5032 if (!values)
5033 return;
5034
5035 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5036 LLVMValueRef val[4];
5037 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5038 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5039 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5040
5041 switch(col_format) {
5042 case V_028714_SPI_SHADER_ZERO:
5043 args->enabled_channels = 0; /* writemask */
5044 args->target = V_008DFC_SQ_EXP_NULL;
5045 break;
5046
5047 case V_028714_SPI_SHADER_32_R:
5048 args->enabled_channels = 1;
5049 args->out[0] = values[0];
5050 break;
5051
5052 case V_028714_SPI_SHADER_32_GR:
5053 args->enabled_channels = 0x3;
5054 args->out[0] = values[0];
5055 args->out[1] = values[1];
5056 break;
5057
5058 case V_028714_SPI_SHADER_32_AR:
5059 args->enabled_channels = 0x9;
5060 args->out[0] = values[0];
5061 args->out[3] = values[3];
5062 break;
5063
5064 case V_028714_SPI_SHADER_FP16_ABGR:
5065 args->compr = 1;
5066
5067 for (unsigned chan = 0; chan < 2; chan++) {
5068 LLVMValueRef pack_args[2] = {
5069 values[2 * chan],
5070 values[2 * chan + 1]
5071 };
5072 LLVMValueRef packed;
5073
5074 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5075 args->out[chan] = packed;
5076 }
5077 break;
5078
5079 case V_028714_SPI_SHADER_UNORM16_ABGR:
5080 for (unsigned chan = 0; chan < 4; chan++) {
5081 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5082 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5083 LLVMConstReal(ctx->f32, 65535), "");
5084 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5085 LLVMConstReal(ctx->f32, 0.5), "");
5086 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5087 ctx->i32, "");
5088 }
5089
5090 args->compr = 1;
5091 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5092 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5093 break;
5094
5095 case V_028714_SPI_SHADER_SNORM16_ABGR:
5096 for (unsigned chan = 0; chan < 4; chan++) {
5097 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
5098 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5099 LLVMConstReal(ctx->f32, 32767), "");
5100
5101 /* If positive, add 0.5, else add -0.5. */
5102 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5103 LLVMBuildSelect(ctx->builder,
5104 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5105 val[chan], ctx->f32zero, ""),
5106 LLVMConstReal(ctx->f32, 0.5),
5107 LLVMConstReal(ctx->f32, -0.5), ""), "");
5108 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5109 }
5110
5111 args->compr = 1;
5112 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5113 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5114 break;
5115
5116 case V_028714_SPI_SHADER_UINT16_ABGR: {
5117 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5118
5119 for (unsigned chan = 0; chan < 4; chan++) {
5120 val[chan] = to_integer(ctx, values[chan]);
5121 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
5122 }
5123
5124 args->compr = 1;
5125 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5126 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5127 break;
5128 }
5129
5130 case V_028714_SPI_SHADER_SINT16_ABGR: {
5131 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5132 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5133
5134 /* Clamp. */
5135 for (unsigned chan = 0; chan < 4; chan++) {
5136 val[chan] = to_integer(ctx, values[chan]);
5137 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
5138 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
5139 }
5140
5141 args->compr = 1;
5142 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5143 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5144 break;
5145 }
5146
5147 default:
5148 case V_028714_SPI_SHADER_32_ABGR:
5149 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5150 break;
5151 }
5152 } else
5153 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5154
5155 for (unsigned i = 0; i < 4; ++i)
5156 args->out[i] = to_float(ctx, args->out[i]);
5157 }
5158
5159 static void
5160 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5161 struct ac_vs_output_info *outinfo)
5162 {
5163 uint32_t param_count = 0;
5164 unsigned target;
5165 unsigned pos_idx, num_pos_exports = 0;
5166 struct ac_export_args args, pos_args[4] = {};
5167 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5168 int i;
5169
5170 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5171 sizeof(outinfo->vs_output_param_offset));
5172
5173 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5174 LLVMValueRef slots[8];
5175 unsigned j;
5176
5177 if (outinfo->cull_dist_mask)
5178 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5179
5180 i = VARYING_SLOT_CLIP_DIST0;
5181 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5182 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5183 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5184
5185 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5186 slots[i] = LLVMGetUndef(ctx->f32);
5187
5188 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5189 target = V_008DFC_SQ_EXP_POS + 3;
5190 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5191 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5192 &args, sizeof(args));
5193 }
5194
5195 target = V_008DFC_SQ_EXP_POS + 2;
5196 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5197 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5198 &args, sizeof(args));
5199
5200 }
5201
5202 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5203 LLVMValueRef values[4];
5204 if (!(ctx->output_mask & (1ull << i)))
5205 continue;
5206
5207 for (unsigned j = 0; j < 4; j++)
5208 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5209 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5210
5211 if (i == VARYING_SLOT_POS) {
5212 target = V_008DFC_SQ_EXP_POS;
5213 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5214 continue;
5215 } else if (i == VARYING_SLOT_PSIZ) {
5216 outinfo->writes_pointsize = true;
5217 psize_value = values[0];
5218 continue;
5219 } else if (i == VARYING_SLOT_LAYER) {
5220 outinfo->writes_layer = true;
5221 layer_value = values[0];
5222 target = V_008DFC_SQ_EXP_PARAM + param_count;
5223 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5224 param_count++;
5225 } else if (i == VARYING_SLOT_VIEWPORT) {
5226 outinfo->writes_viewport_index = true;
5227 viewport_index_value = values[0];
5228 continue;
5229 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5230 target = V_008DFC_SQ_EXP_PARAM + param_count;
5231 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5232 param_count++;
5233 } else if (i >= VARYING_SLOT_VAR0) {
5234 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5235 target = V_008DFC_SQ_EXP_PARAM + param_count;
5236 outinfo->vs_output_param_offset[i] = param_count;
5237 param_count++;
5238 }
5239
5240 si_llvm_init_export_args(ctx, values, target, &args);
5241
5242 if (target >= V_008DFC_SQ_EXP_POS &&
5243 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5244 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5245 &args, sizeof(args));
5246 } else {
5247 ac_build_export(&ctx->ac, &args);
5248 }
5249 }
5250
5251 /* We need to add the position output manually if it's missing. */
5252 if (!pos_args[0].out[0]) {
5253 pos_args[0].enabled_channels = 0xf;
5254 pos_args[0].valid_mask = 0;
5255 pos_args[0].done = 0;
5256 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5257 pos_args[0].compr = 0;
5258 pos_args[0].out[0] = ctx->f32zero; /* X */
5259 pos_args[0].out[1] = ctx->f32zero; /* Y */
5260 pos_args[0].out[2] = ctx->f32zero; /* Z */
5261 pos_args[0].out[3] = ctx->f32one; /* W */
5262 }
5263
5264 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5265 (outinfo->writes_layer == true ? 4 : 0) |
5266 (outinfo->writes_viewport_index == true ? 8 : 0));
5267 if (mask) {
5268 pos_args[1].enabled_channels = mask;
5269 pos_args[1].valid_mask = 0;
5270 pos_args[1].done = 0;
5271 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5272 pos_args[1].compr = 0;
5273 pos_args[1].out[0] = ctx->f32zero; /* X */
5274 pos_args[1].out[1] = ctx->f32zero; /* Y */
5275 pos_args[1].out[2] = ctx->f32zero; /* Z */
5276 pos_args[1].out[3] = ctx->f32zero; /* W */
5277
5278 if (outinfo->writes_pointsize == true)
5279 pos_args[1].out[0] = psize_value;
5280 if (outinfo->writes_layer == true)
5281 pos_args[1].out[2] = layer_value;
5282 if (outinfo->writes_viewport_index == true)
5283 pos_args[1].out[3] = viewport_index_value;
5284 }
5285 for (i = 0; i < 4; i++) {
5286 if (pos_args[i].out[0])
5287 num_pos_exports++;
5288 }
5289
5290 pos_idx = 0;
5291 for (i = 0; i < 4; i++) {
5292 if (!pos_args[i].out[0])
5293 continue;
5294
5295 /* Specify the target we are exporting */
5296 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5297 if (pos_idx == num_pos_exports)
5298 pos_args[i].done = 1;
5299 ac_build_export(&ctx->ac, &pos_args[i]);
5300 }
5301
5302 outinfo->pos_exports = num_pos_exports;
5303 outinfo->param_exports = param_count;
5304 }
5305
5306 static void
5307 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5308 struct ac_es_output_info *outinfo)
5309 {
5310 int j;
5311 uint64_t max_output_written = 0;
5312 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5313 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5314 int param_index;
5315 int length = 4;
5316
5317 if (!(ctx->output_mask & (1ull << i)))
5318 continue;
5319
5320 if (i == VARYING_SLOT_CLIP_DIST0)
5321 length = ctx->num_output_clips + ctx->num_output_culls;
5322
5323 param_index = shader_io_get_unique_index(i);
5324
5325 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5326
5327 for (j = 0; j < length; j++) {
5328 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5329 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5330
5331 ac_build_buffer_store_dword(&ctx->ac,
5332 ctx->esgs_ring,
5333 out_val, 1,
5334 NULL, ctx->es2gs_offset,
5335 (4 * param_index + j) * 4,
5336 1, 1, true, true);
5337 }
5338 }
5339 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5340 }
5341
5342 static void
5343 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5344 {
5345 LLVMValueRef vertex_id = ctx->rel_auto_id;
5346 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5347 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5348 vertex_dw_stride, "");
5349
5350 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5351 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5352 int length = 4;
5353
5354 if (!(ctx->output_mask & (1ull << i)))
5355 continue;
5356
5357 if (i == VARYING_SLOT_CLIP_DIST0)
5358 length = ctx->num_output_clips + ctx->num_output_culls;
5359 int param = shader_io_get_unique_index(i);
5360 mark_tess_output(ctx, false, param);
5361 if (length > 4)
5362 mark_tess_output(ctx, false, param + 1);
5363 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5364 LLVMConstInt(ctx->i32, param * 4, false),
5365 "");
5366 for (unsigned j = 0; j < length; j++) {
5367 lds_store(ctx, dw_addr,
5368 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5369 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5370 }
5371 }
5372 }
5373
5374 struct ac_build_if_state
5375 {
5376 struct nir_to_llvm_context *ctx;
5377 LLVMValueRef condition;
5378 LLVMBasicBlockRef entry_block;
5379 LLVMBasicBlockRef true_block;
5380 LLVMBasicBlockRef false_block;
5381 LLVMBasicBlockRef merge_block;
5382 };
5383
5384 static LLVMBasicBlockRef
5385 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5386 {
5387 LLVMBasicBlockRef current_block;
5388 LLVMBasicBlockRef next_block;
5389 LLVMBasicBlockRef new_block;
5390
5391 /* get current basic block */
5392 current_block = LLVMGetInsertBlock(ctx->builder);
5393
5394 /* chqeck if there's another block after this one */
5395 next_block = LLVMGetNextBasicBlock(current_block);
5396 if (next_block) {
5397 /* insert the new block before the next block */
5398 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5399 }
5400 else {
5401 /* append new block after current block */
5402 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5403 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5404 }
5405 return new_block;
5406 }
5407
5408 static void
5409 ac_nir_build_if(struct ac_build_if_state *ifthen,
5410 struct nir_to_llvm_context *ctx,
5411 LLVMValueRef condition)
5412 {
5413 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5414
5415 memset(ifthen, 0, sizeof *ifthen);
5416 ifthen->ctx = ctx;
5417 ifthen->condition = condition;
5418 ifthen->entry_block = block;
5419
5420 /* create endif/merge basic block for the phi functions */
5421 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5422
5423 /* create/insert true_block before merge_block */
5424 ifthen->true_block =
5425 LLVMInsertBasicBlockInContext(ctx->context,
5426 ifthen->merge_block,
5427 "if-true-block");
5428
5429 /* successive code goes into the true block */
5430 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5431 }
5432
5433 /**
5434 * End a conditional.
5435 */
5436 static void
5437 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5438 {
5439 LLVMBuilderRef builder = ifthen->ctx->builder;
5440
5441 /* Insert branch to the merge block from current block */
5442 LLVMBuildBr(builder, ifthen->merge_block);
5443
5444 /*
5445 * Now patch in the various branch instructions.
5446 */
5447
5448 /* Insert the conditional branch instruction at the end of entry_block */
5449 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5450 if (ifthen->false_block) {
5451 /* we have an else clause */
5452 LLVMBuildCondBr(builder, ifthen->condition,
5453 ifthen->true_block, ifthen->false_block);
5454 }
5455 else {
5456 /* no else clause */
5457 LLVMBuildCondBr(builder, ifthen->condition,
5458 ifthen->true_block, ifthen->merge_block);
5459 }
5460
5461 /* Resume building code at end of the ifthen->merge_block */
5462 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5463 }
5464
5465 static void
5466 write_tess_factors(struct nir_to_llvm_context *ctx)
5467 {
5468 unsigned stride, outer_comps, inner_comps;
5469 struct ac_build_if_state if_ctx, inner_if_ctx;
5470 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5471 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5472 unsigned tess_inner_index, tess_outer_index;
5473 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5474 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5475 int i;
5476 emit_barrier(ctx);
5477
5478 switch (ctx->options->key.tcs.primitive_mode) {
5479 case GL_ISOLINES:
5480 stride = 2;
5481 outer_comps = 2;
5482 inner_comps = 0;
5483 break;
5484 case GL_TRIANGLES:
5485 stride = 4;
5486 outer_comps = 3;
5487 inner_comps = 1;
5488 break;
5489 case GL_QUADS:
5490 stride = 6;
5491 outer_comps = 4;
5492 inner_comps = 2;
5493 break;
5494 default:
5495 return;
5496 }
5497
5498 ac_nir_build_if(&if_ctx, ctx,
5499 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5500 invocation_id, ctx->i32zero, ""));
5501
5502 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5503 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5504
5505 mark_tess_output(ctx, true, tess_inner_index);
5506 mark_tess_output(ctx, true, tess_outer_index);
5507 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5508 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5509 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5510 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5511 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5512
5513 for (i = 0; i < 4; i++) {
5514 inner[i] = LLVMGetUndef(ctx->i32);
5515 outer[i] = LLVMGetUndef(ctx->i32);
5516 }
5517
5518 // LINES reverseal
5519 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5520 outer[0] = out[1] = lds_load(ctx, lds_outer);
5521 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5522 LLVMConstInt(ctx->i32, 1, false), "");
5523 outer[1] = out[0] = lds_load(ctx, lds_outer);
5524 } else {
5525 for (i = 0; i < outer_comps; i++) {
5526 outer[i] = out[i] =
5527 lds_load(ctx, lds_outer);
5528 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5529 LLVMConstInt(ctx->i32, 1, false), "");
5530 }
5531 for (i = 0; i < inner_comps; i++) {
5532 inner[i] = out[outer_comps+i] =
5533 lds_load(ctx, lds_inner);
5534 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5535 LLVMConstInt(ctx->i32, 1, false), "");
5536 }
5537 }
5538
5539 /* Convert the outputs to vectors for stores. */
5540 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5541 vec1 = NULL;
5542
5543 if (stride > 4)
5544 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5545
5546
5547 buffer = ctx->hs_ring_tess_factor;
5548 tf_base = ctx->tess_factor_offset;
5549 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5550 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5551
5552 ac_nir_build_if(&inner_if_ctx, ctx,
5553 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5554 rel_patch_id, ctx->i32zero, ""));
5555
5556 /* Store the dynamic HS control word. */
5557 ac_build_buffer_store_dword(&ctx->ac, buffer,
5558 LLVMConstInt(ctx->i32, 0x80000000, false),
5559 1, ctx->i32zero, tf_base,
5560 0, 1, 0, true, false);
5561 ac_nir_build_endif(&inner_if_ctx);
5562
5563 /* Store the tessellation factors. */
5564 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5565 MIN2(stride, 4), byteoffset, tf_base,
5566 4, 1, 0, true, false);
5567 if (vec1)
5568 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5569 stride - 4, byteoffset, tf_base,
5570 20, 1, 0, true, false);
5571
5572 //TODO store to offchip for TES to read - only if TES reads them
5573 if (1) {
5574 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5575 LLVMValueRef tf_inner_offset;
5576 unsigned param_outer, param_inner;
5577
5578 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5579 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5580 LLVMConstInt(ctx->i32, param_outer, 0));
5581
5582 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5583 util_next_power_of_two(outer_comps));
5584
5585 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5586 outer_comps, tf_outer_offset,
5587 ctx->oc_lds, 0, 1, 0, true, false);
5588 if (inner_comps) {
5589 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5590 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5591 LLVMConstInt(ctx->i32, param_inner, 0));
5592
5593 inner_vec = inner_comps == 1 ? inner[0] :
5594 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5595 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5596 inner_comps, tf_inner_offset,
5597 ctx->oc_lds, 0, 1, 0, true, false);
5598 }
5599 }
5600 ac_nir_build_endif(&if_ctx);
5601 }
5602
5603 static void
5604 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5605 {
5606 write_tess_factors(ctx);
5607 }
5608
5609 static bool
5610 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5611 LLVMValueRef *color, unsigned param, bool is_last,
5612 struct ac_export_args *args)
5613 {
5614 /* Export */
5615 si_llvm_init_export_args(ctx, color, param,
5616 args);
5617
5618 if (is_last) {
5619 args->valid_mask = 1; /* whether the EXEC mask is valid */
5620 args->done = 1; /* DONE bit */
5621 } else if (!args->enabled_channels)
5622 return false; /* unnecessary NULL export */
5623
5624 return true;
5625 }
5626
5627 static void
5628 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5629 LLVMValueRef depth, LLVMValueRef stencil,
5630 LLVMValueRef samplemask)
5631 {
5632 struct ac_export_args args;
5633
5634 args.enabled_channels = 0;
5635 args.valid_mask = 1;
5636 args.done = 1;
5637 args.target = V_008DFC_SQ_EXP_MRTZ;
5638 args.compr = false;
5639
5640 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5641 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5642 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5643 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5644
5645 if (depth) {
5646 args.out[0] = depth;
5647 args.enabled_channels |= 0x1;
5648 }
5649
5650 if (stencil) {
5651 args.out[1] = stencil;
5652 args.enabled_channels |= 0x2;
5653 }
5654
5655 if (samplemask) {
5656 args.out[2] = samplemask;
5657 args.enabled_channels |= 0x4;
5658 }
5659
5660 /* SI (except OLAND) has a bug that it only looks
5661 * at the X writemask component. */
5662 if (ctx->options->chip_class == SI &&
5663 ctx->options->family != CHIP_OLAND)
5664 args.enabled_channels |= 0x1;
5665
5666 ac_build_export(&ctx->ac, &args);
5667 }
5668
5669 static void
5670 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5671 {
5672 unsigned index = 0;
5673 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5674 struct ac_export_args color_args[8];
5675
5676 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5677 LLVMValueRef values[4];
5678
5679 if (!(ctx->output_mask & (1ull << i)))
5680 continue;
5681
5682 if (i == FRAG_RESULT_DEPTH) {
5683 ctx->shader_info->fs.writes_z = true;
5684 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
5685 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5686 } else if (i == FRAG_RESULT_STENCIL) {
5687 ctx->shader_info->fs.writes_stencil = true;
5688 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
5689 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5690 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5691 ctx->shader_info->fs.writes_sample_mask = true;
5692 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
5693 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5694 } else {
5695 bool last = false;
5696 for (unsigned j = 0; j < 4; j++)
5697 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5698 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5699
5700 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5701 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5702
5703 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5704 if (ret)
5705 index++;
5706 }
5707 }
5708
5709 for (unsigned i = 0; i < index; i++)
5710 ac_build_export(&ctx->ac, &color_args[i]);
5711 if (depth || stencil || samplemask)
5712 si_export_mrt_z(ctx, depth, stencil, samplemask);
5713 else if (!index) {
5714 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5715 ac_build_export(&ctx->ac, &color_args[0]);
5716 }
5717
5718 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5719 }
5720
5721 static void
5722 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5723 {
5724 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5725 }
5726
5727 static void
5728 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5729 {
5730 switch (ctx->stage) {
5731 case MESA_SHADER_VERTEX:
5732 if (ctx->options->key.vs.as_ls)
5733 handle_ls_outputs_post(ctx);
5734 else if (ctx->options->key.vs.as_es)
5735 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5736 else
5737 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5738 break;
5739 case MESA_SHADER_FRAGMENT:
5740 handle_fs_outputs_post(ctx);
5741 break;
5742 case MESA_SHADER_GEOMETRY:
5743 emit_gs_epilogue(ctx);
5744 break;
5745 case MESA_SHADER_TESS_CTRL:
5746 handle_tcs_outputs_post(ctx);
5747 break;
5748 case MESA_SHADER_TESS_EVAL:
5749 if (ctx->options->key.tes.as_es)
5750 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5751 else
5752 handle_vs_outputs_post(ctx, &ctx->shader_info->tes.outinfo);
5753 break;
5754 default:
5755 break;
5756 }
5757 }
5758
5759 static void
5760 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5761 struct nir_variable *variable, uint32_t *offset, int idx)
5762 {
5763 unsigned size = glsl_count_attribute_slots(variable->type, false);
5764 variable->data.driver_location = *offset;
5765 *offset += size;
5766 }
5767
5768 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5769 {
5770 LLVMPassManagerRef passmgr;
5771 /* Create the pass manager */
5772 passmgr = LLVMCreateFunctionPassManagerForModule(
5773 ctx->module);
5774
5775 /* This pass should eliminate all the load and store instructions */
5776 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5777
5778 /* Add some optimization passes */
5779 LLVMAddScalarReplAggregatesPass(passmgr);
5780 LLVMAddLICMPass(passmgr);
5781 LLVMAddAggressiveDCEPass(passmgr);
5782 LLVMAddCFGSimplificationPass(passmgr);
5783 LLVMAddInstructionCombiningPass(passmgr);
5784
5785 /* Run the pass */
5786 LLVMInitializeFunctionPassManager(passmgr);
5787 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5788 LLVMFinalizeFunctionPassManager(passmgr);
5789
5790 LLVMDisposeBuilder(ctx->builder);
5791 LLVMDisposePassManager(passmgr);
5792 }
5793
5794 static void
5795 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
5796 {
5797 struct ac_vs_output_info *outinfo;
5798
5799 if (ctx->stage == MESA_SHADER_FRAGMENT ||
5800 ctx->stage == MESA_SHADER_COMPUTE ||
5801 ctx->stage == MESA_SHADER_TESS_CTRL ||
5802 ctx->stage == MESA_SHADER_GEOMETRY)
5803 return;
5804
5805 if (ctx->stage == MESA_SHADER_VERTEX) {
5806 if (ctx->options->key.vs.as_ls ||
5807 ctx->options->key.vs.as_es)
5808 return;
5809 outinfo = &ctx->shader_info->vs.outinfo;
5810 }
5811
5812 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5813 if (ctx->options->key.vs.as_es)
5814 return;
5815 outinfo = &ctx->shader_info->tes.outinfo;
5816 }
5817
5818 ac_optimize_vs_outputs(&ctx->ac,
5819 ctx->main_function,
5820 outinfo->vs_output_param_offset,
5821 VARYING_SLOT_MAX,
5822 &outinfo->param_exports);
5823 }
5824
5825 static void
5826 ac_setup_rings(struct nir_to_llvm_context *ctx)
5827 {
5828 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5829 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5830 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5831 }
5832
5833 if (ctx->is_gs_copy_shader) {
5834 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5835 }
5836 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5837 LLVMValueRef tmp;
5838 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5839 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5840
5841 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5842
5843 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5844 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5845 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5846 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5847
5848 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5849 }
5850
5851 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5852 ctx->stage == MESA_SHADER_TESS_EVAL) {
5853 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5854 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5855 }
5856 }
5857
5858 static
5859 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5860 struct nir_shader *nir,
5861 struct ac_shader_variant_info *shader_info,
5862 const struct ac_nir_compiler_options *options)
5863 {
5864 struct nir_to_llvm_context ctx = {0};
5865 struct nir_function *func;
5866 unsigned i;
5867 ctx.options = options;
5868 ctx.shader_info = shader_info;
5869 ctx.context = LLVMContextCreate();
5870 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5871
5872 ac_llvm_context_init(&ctx.ac, ctx.context);
5873 ctx.ac.module = ctx.module;
5874
5875 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5876
5877 memset(shader_info, 0, sizeof(*shader_info));
5878
5879 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5880
5881 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5882
5883 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5884 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5885 LLVMSetDataLayout(ctx.module, data_layout_str);
5886 LLVMDisposeTargetData(data_layout);
5887 LLVMDisposeMessage(data_layout_str);
5888
5889 setup_types(&ctx);
5890
5891 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5892 ctx.ac.builder = ctx.builder;
5893 ctx.stage = nir->stage;
5894
5895 for (i = 0; i < AC_UD_MAX_SETS; i++)
5896 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5897 for (i = 0; i < AC_UD_MAX_UD; i++)
5898 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5899
5900 create_function(&ctx);
5901
5902 if (nir->stage == MESA_SHADER_COMPUTE) {
5903 int num_shared = 0;
5904 nir_foreach_variable(variable, &nir->shared)
5905 num_shared++;
5906 if (num_shared) {
5907 int idx = 0;
5908 uint32_t shared_size = 0;
5909 LLVMValueRef var;
5910 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5911 nir_foreach_variable(variable, &nir->shared) {
5912 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5913 idx++;
5914 }
5915
5916 shared_size *= 16;
5917 var = LLVMAddGlobalInAddressSpace(ctx.module,
5918 LLVMArrayType(ctx.i8, shared_size),
5919 "compute_lds",
5920 LOCAL_ADDR_SPACE);
5921 LLVMSetAlignment(var, 4);
5922 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5923 }
5924 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5925 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5926
5927 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
5928 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5929 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
5930 }
5931
5932 ac_setup_rings(&ctx);
5933
5934 nir_foreach_variable(variable, &nir->inputs)
5935 handle_shader_input_decl(&ctx, variable);
5936
5937 if (nir->stage == MESA_SHADER_FRAGMENT)
5938 handle_fs_inputs_pre(&ctx, nir);
5939
5940 ctx.num_output_clips = nir->info.clip_distance_array_size;
5941 ctx.num_output_culls = nir->info.cull_distance_array_size;
5942
5943 nir_foreach_variable(variable, &nir->outputs)
5944 handle_shader_output_decl(&ctx, variable);
5945
5946 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5947 _mesa_key_pointer_equal);
5948 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5949 _mesa_key_pointer_equal);
5950
5951 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5952
5953 setup_locals(&ctx, func);
5954
5955 visit_cf_list(&ctx, &func->impl->body);
5956 phi_post_pass(&ctx);
5957
5958 handle_shader_outputs_post(&ctx);
5959 LLVMBuildRetVoid(ctx.builder);
5960
5961 ac_llvm_finalize_module(&ctx);
5962
5963 ac_nir_eliminate_const_vs_outputs(&ctx);
5964 free(ctx.locals);
5965 ralloc_free(ctx.defs);
5966 ralloc_free(ctx.phis);
5967
5968 if (nir->stage == MESA_SHADER_GEOMETRY) {
5969 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
5970 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
5971 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5972 nir->info.gs.vertices_out;
5973 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
5974 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
5975 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
5976 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
5977 shader_info->vs.outputs_written = ctx.tess_outputs_written;
5978 }
5979
5980 return ctx.module;
5981 }
5982
5983 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
5984 {
5985 unsigned *retval = (unsigned *)context;
5986 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5987 char *description = LLVMGetDiagInfoDescription(di);
5988
5989 if (severity == LLVMDSError) {
5990 *retval = 1;
5991 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5992 description);
5993 }
5994
5995 LLVMDisposeMessage(description);
5996 }
5997
5998 static unsigned ac_llvm_compile(LLVMModuleRef M,
5999 struct ac_shader_binary *binary,
6000 LLVMTargetMachineRef tm)
6001 {
6002 unsigned retval = 0;
6003 char *err;
6004 LLVMContextRef llvm_ctx;
6005 LLVMMemoryBufferRef out_buffer;
6006 unsigned buffer_size;
6007 const char *buffer_data;
6008 LLVMBool mem_err;
6009
6010 /* Setup Diagnostic Handler*/
6011 llvm_ctx = LLVMGetModuleContext(M);
6012
6013 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6014 &retval);
6015
6016 /* Compile IR*/
6017 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6018 &err, &out_buffer);
6019
6020 /* Process Errors/Warnings */
6021 if (mem_err) {
6022 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6023 free(err);
6024 retval = 1;
6025 goto out;
6026 }
6027
6028 /* Extract Shader Code*/
6029 buffer_size = LLVMGetBufferSize(out_buffer);
6030 buffer_data = LLVMGetBufferStart(out_buffer);
6031
6032 ac_elf_read(buffer_data, buffer_size, binary);
6033
6034 /* Clean up */
6035 LLVMDisposeMemoryBuffer(out_buffer);
6036
6037 out:
6038 return retval;
6039 }
6040
6041 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6042 LLVMModuleRef llvm_module,
6043 struct ac_shader_binary *binary,
6044 struct ac_shader_config *config,
6045 struct ac_shader_variant_info *shader_info,
6046 gl_shader_stage stage,
6047 bool dump_shader, bool supports_spill)
6048 {
6049 if (dump_shader)
6050 ac_dump_module(llvm_module);
6051
6052 memset(binary, 0, sizeof(*binary));
6053 int v = ac_llvm_compile(llvm_module, binary, tm);
6054 if (v) {
6055 fprintf(stderr, "compile failed\n");
6056 }
6057
6058 if (dump_shader)
6059 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6060
6061 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6062
6063 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6064 LLVMDisposeModule(llvm_module);
6065 LLVMContextDispose(ctx);
6066
6067 if (stage == MESA_SHADER_FRAGMENT) {
6068 shader_info->num_input_vgprs = 0;
6069 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6070 shader_info->num_input_vgprs += 2;
6071 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6072 shader_info->num_input_vgprs += 2;
6073 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6074 shader_info->num_input_vgprs += 2;
6075 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6076 shader_info->num_input_vgprs += 3;
6077 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6078 shader_info->num_input_vgprs += 2;
6079 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6080 shader_info->num_input_vgprs += 2;
6081 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6082 shader_info->num_input_vgprs += 2;
6083 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6084 shader_info->num_input_vgprs += 1;
6085 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6086 shader_info->num_input_vgprs += 1;
6087 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6088 shader_info->num_input_vgprs += 1;
6089 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6090 shader_info->num_input_vgprs += 1;
6091 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6092 shader_info->num_input_vgprs += 1;
6093 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6094 shader_info->num_input_vgprs += 1;
6095 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6096 shader_info->num_input_vgprs += 1;
6097 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6098 shader_info->num_input_vgprs += 1;
6099 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6100 shader_info->num_input_vgprs += 1;
6101 }
6102 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6103
6104 /* +3 for scratch wave offset and VCC */
6105 config->num_sgprs = MAX2(config->num_sgprs,
6106 shader_info->num_input_sgprs + 3);
6107 }
6108
6109 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6110 struct ac_shader_binary *binary,
6111 struct ac_shader_config *config,
6112 struct ac_shader_variant_info *shader_info,
6113 struct nir_shader *nir,
6114 const struct ac_nir_compiler_options *options,
6115 bool dump_shader)
6116 {
6117
6118 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6119 options);
6120
6121 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6122 switch (nir->stage) {
6123 case MESA_SHADER_COMPUTE:
6124 for (int i = 0; i < 3; ++i)
6125 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6126 break;
6127 case MESA_SHADER_FRAGMENT:
6128 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6129 break;
6130 case MESA_SHADER_GEOMETRY:
6131 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6132 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6133 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6134 shader_info->gs.invocations = nir->info.gs.invocations;
6135 break;
6136 case MESA_SHADER_TESS_EVAL:
6137 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6138 shader_info->tes.spacing = nir->info.tess.spacing;
6139 shader_info->tes.ccw = nir->info.tess.ccw;
6140 shader_info->tes.point_mode = nir->info.tess.point_mode;
6141 shader_info->tes.as_es = options->key.tes.as_es;
6142 break;
6143 case MESA_SHADER_TESS_CTRL:
6144 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6145 break;
6146 case MESA_SHADER_VERTEX:
6147 shader_info->vs.as_es = options->key.vs.as_es;
6148 shader_info->vs.as_ls = options->key.vs.as_ls;
6149 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6150 if (options->key.vs.as_ls)
6151 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6152 break;
6153 default:
6154 break;
6155 }
6156 }
6157
6158 static void
6159 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6160 {
6161 LLVMValueRef args[9];
6162 args[0] = ctx->gsvs_ring;
6163 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6164 args[3] = ctx->i32zero;
6165 args[4] = ctx->i32one; /* OFFEN */
6166 args[5] = ctx->i32zero; /* IDXEN */
6167 args[6] = ctx->i32one; /* GLC */
6168 args[7] = ctx->i32one; /* SLC */
6169 args[8] = ctx->i32zero; /* TFE */
6170
6171 int idx = 0;
6172
6173 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6174 int length = 4;
6175 int slot = idx;
6176 int slot_inc = 1;
6177 if (!(ctx->output_mask & (1ull << i)))
6178 continue;
6179
6180 if (i == VARYING_SLOT_CLIP_DIST0) {
6181 /* unpack clip and cull from a single set of slots */
6182 length = ctx->num_output_clips + ctx->num_output_culls;
6183 if (length > 4)
6184 slot_inc = 2;
6185 }
6186
6187 for (unsigned j = 0; j < length; j++) {
6188 LLVMValueRef value;
6189 args[2] = LLVMConstInt(ctx->i32,
6190 (slot * 4 + j) *
6191 ctx->gs_max_out_vertices * 16 * 4, false);
6192
6193 value = ac_build_intrinsic(&ctx->ac,
6194 "llvm.SI.buffer.load.dword.i32.i32",
6195 ctx->i32, args, 9,
6196 AC_FUNC_ATTR_READONLY |
6197 AC_FUNC_ATTR_LEGACY);
6198
6199 LLVMBuildStore(ctx->builder,
6200 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6201 }
6202 idx += slot_inc;
6203 }
6204 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
6205 }
6206
6207 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6208 struct nir_shader *geom_shader,
6209 struct ac_shader_binary *binary,
6210 struct ac_shader_config *config,
6211 struct ac_shader_variant_info *shader_info,
6212 const struct ac_nir_compiler_options *options,
6213 bool dump_shader)
6214 {
6215 struct nir_to_llvm_context ctx = {0};
6216 ctx.context = LLVMContextCreate();
6217 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6218 ctx.options = options;
6219 ctx.shader_info = shader_info;
6220
6221 ac_llvm_context_init(&ctx.ac, ctx.context);
6222 ctx.ac.module = ctx.module;
6223
6224 ctx.is_gs_copy_shader = true;
6225 LLVMSetTarget(ctx.module, "amdgcn--");
6226 setup_types(&ctx);
6227
6228 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6229 ctx.ac.builder = ctx.builder;
6230 ctx.stage = MESA_SHADER_VERTEX;
6231
6232 create_function(&ctx);
6233
6234 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6235 ac_setup_rings(&ctx);
6236
6237 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6238 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6239
6240 nir_foreach_variable(variable, &geom_shader->outputs)
6241 handle_shader_output_decl(&ctx, variable);
6242
6243 ac_gs_copy_shader_emit(&ctx);
6244
6245 LLVMBuildRetVoid(ctx.builder);
6246
6247 ac_llvm_finalize_module(&ctx);
6248
6249 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6250 MESA_SHADER_VERTEX,
6251 dump_shader, options->supports_spill);
6252 }